1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 28 #include "bcmgenet.h" 29 30 /* read a value from the MII */ 31 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location) 32 { 33 int ret; 34 struct net_device *dev = bus->priv; 35 struct bcmgenet_priv *priv = netdev_priv(dev); 36 u32 reg; 37 38 bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | 39 (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD); 40 /* Start MDIO transaction*/ 41 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 42 reg |= MDIO_START_BUSY; 43 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 44 wait_event_timeout(priv->wq, 45 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 46 & MDIO_START_BUSY), 47 HZ / 100); 48 ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 49 50 /* Some broken devices are known not to release the line during 51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for 52 * that condition here and ignore the MDIO controller read failure 53 * indication. 54 */ 55 if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (ret & MDIO_READ_FAIL)) 56 return -EIO; 57 58 return ret & 0xffff; 59 } 60 61 /* write a value to the MII */ 62 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id, 63 int location, u16 val) 64 { 65 struct net_device *dev = bus->priv; 66 struct bcmgenet_priv *priv = netdev_priv(dev); 67 u32 reg; 68 69 bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) | 70 (location << MDIO_REG_SHIFT) | (0xffff & val)), 71 UMAC_MDIO_CMD); 72 reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD); 73 reg |= MDIO_START_BUSY; 74 bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD); 75 wait_event_timeout(priv->wq, 76 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) & 77 MDIO_START_BUSY), 78 HZ / 100); 79 80 return 0; 81 } 82 83 /* setup netdev link state when PHY link status change and 84 * update UMAC and RGMII block when link up 85 */ 86 void bcmgenet_mii_setup(struct net_device *dev) 87 { 88 struct bcmgenet_priv *priv = netdev_priv(dev); 89 struct phy_device *phydev = priv->phydev; 90 u32 reg, cmd_bits = 0; 91 bool status_changed = false; 92 93 if (priv->old_link != phydev->link) { 94 status_changed = true; 95 priv->old_link = phydev->link; 96 } 97 98 if (phydev->link) { 99 /* check speed/duplex/pause changes */ 100 if (priv->old_speed != phydev->speed) { 101 status_changed = true; 102 priv->old_speed = phydev->speed; 103 } 104 105 if (priv->old_duplex != phydev->duplex) { 106 status_changed = true; 107 priv->old_duplex = phydev->duplex; 108 } 109 110 if (priv->old_pause != phydev->pause) { 111 status_changed = true; 112 priv->old_pause = phydev->pause; 113 } 114 115 /* done if nothing has changed */ 116 if (!status_changed) 117 return; 118 119 /* speed */ 120 if (phydev->speed == SPEED_1000) 121 cmd_bits = UMAC_SPEED_1000; 122 else if (phydev->speed == SPEED_100) 123 cmd_bits = UMAC_SPEED_100; 124 else 125 cmd_bits = UMAC_SPEED_10; 126 cmd_bits <<= CMD_SPEED_SHIFT; 127 128 /* duplex */ 129 if (phydev->duplex != DUPLEX_FULL) 130 cmd_bits |= CMD_HD_EN; 131 132 /* pause capability */ 133 if (!phydev->pause) 134 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 135 136 /* 137 * Program UMAC and RGMII block based on established 138 * link speed, duplex, and pause. The speed set in 139 * umac->cmd tell RGMII block which clock to use for 140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 141 * Receive clock is provided by the PHY. 142 */ 143 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 144 reg &= ~OOB_DISABLE; 145 reg |= RGMII_LINK; 146 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 147 148 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 149 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 150 CMD_HD_EN | 151 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 152 reg |= cmd_bits; 153 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 154 } else { 155 /* done if nothing has changed */ 156 if (!status_changed) 157 return; 158 159 /* needed for MoCA fixed PHY to reflect correct link status */ 160 netif_carrier_off(dev); 161 } 162 163 phy_print_status(phydev); 164 } 165 166 167 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 168 struct fixed_phy_status *status) 169 { 170 if (dev && dev->phydev && status) 171 status->link = dev->phydev->link; 172 173 return 0; 174 } 175 176 /* Perform a voluntary PHY software reset, since the EPHY is very finicky about 177 * not doing it and will start corrupting packets 178 */ 179 void bcmgenet_mii_reset(struct net_device *dev) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 183 if (GENET_IS_V4(priv)) 184 return; 185 186 if (priv->phydev) { 187 phy_init_hw(priv->phydev); 188 phy_start_aneg(priv->phydev); 189 } 190 } 191 192 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 193 { 194 struct bcmgenet_priv *priv = netdev_priv(dev); 195 u32 reg = 0; 196 197 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 198 if (GENET_IS_V4(priv)) { 199 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 200 if (enable) { 201 reg &= ~EXT_CK25_DIS; 202 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 203 mdelay(1); 204 205 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 206 reg |= EXT_GPHY_RESET; 207 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 208 mdelay(1); 209 210 reg &= ~EXT_GPHY_RESET; 211 } else { 212 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 213 EXT_GPHY_RESET; 214 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 215 mdelay(1); 216 reg |= EXT_CK25_DIS; 217 } 218 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 219 udelay(60); 220 } else { 221 mdelay(1); 222 } 223 } 224 225 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 226 { 227 u32 reg; 228 229 if (!GENET_IS_V5(priv)) { 230 /* Speed settings are set in bcmgenet_mii_setup() */ 231 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 232 reg |= LED_ACT_SOURCE_MAC; 233 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 234 } 235 236 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 237 fixed_phy_set_link_update(priv->phydev, 238 bcmgenet_fixed_phy_link_update); 239 } 240 241 int bcmgenet_mii_config(struct net_device *dev) 242 { 243 struct bcmgenet_priv *priv = netdev_priv(dev); 244 struct phy_device *phydev = priv->phydev; 245 struct device *kdev = &priv->pdev->dev; 246 const char *phy_name = NULL; 247 u32 id_mode_dis = 0; 248 u32 port_ctrl; 249 u32 reg; 250 251 priv->ext_phy = !priv->internal_phy && 252 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 253 254 switch (priv->phy_interface) { 255 case PHY_INTERFACE_MODE_INTERNAL: 256 case PHY_INTERFACE_MODE_MOCA: 257 /* Irrespective of the actually configured PHY speed (100 or 258 * 1000) GENETv4 only has an internal GPHY so we will just end 259 * up masking the Gigabit features from what we support, not 260 * switching to the EPHY 261 */ 262 if (GENET_IS_V4(priv)) 263 port_ctrl = PORT_MODE_INT_GPHY; 264 else 265 port_ctrl = PORT_MODE_INT_EPHY; 266 267 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 268 269 if (priv->internal_phy) { 270 phy_name = "internal PHY"; 271 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 272 phy_name = "MoCA"; 273 bcmgenet_moca_phy_setup(priv); 274 } 275 break; 276 277 case PHY_INTERFACE_MODE_MII: 278 phy_name = "external MII"; 279 phydev->supported &= PHY_BASIC_FEATURES; 280 bcmgenet_sys_writel(priv, 281 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 282 break; 283 284 case PHY_INTERFACE_MODE_REVMII: 285 phy_name = "external RvMII"; 286 /* of_mdiobus_register took care of reading the 'max-speed' 287 * PHY property for us, effectively limiting the PHY supported 288 * capabilities, use that knowledge to also configure the 289 * Reverse MII interface correctly. 290 */ 291 if ((priv->phydev->supported & PHY_BASIC_FEATURES) == 292 PHY_BASIC_FEATURES) 293 port_ctrl = PORT_MODE_EXT_RVMII_25; 294 else 295 port_ctrl = PORT_MODE_EXT_RVMII_50; 296 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 297 break; 298 299 case PHY_INTERFACE_MODE_RGMII: 300 /* RGMII_NO_ID: TXC transitions at the same time as TXD 301 * (requires PCB or receiver-side delay) 302 * RGMII: Add 2ns delay on TXC (90 degree shift) 303 * 304 * ID is implicitly disabled for 100Mbps (RG)MII operation. 305 */ 306 id_mode_dis = BIT(16); 307 /* fall through */ 308 case PHY_INTERFACE_MODE_RGMII_TXID: 309 if (id_mode_dis) 310 phy_name = "external RGMII (no delay)"; 311 else 312 phy_name = "external RGMII (TX delay)"; 313 bcmgenet_sys_writel(priv, 314 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 315 break; 316 default: 317 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 318 return -EINVAL; 319 } 320 321 /* This is an external PHY (xMII), so we need to enable the RGMII 322 * block for the interface to work 323 */ 324 if (priv->ext_phy) { 325 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 326 reg |= RGMII_MODE_EN | id_mode_dis; 327 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 328 } 329 330 dev_info_once(kdev, "configuring instance for %s\n", phy_name); 331 332 return 0; 333 } 334 335 int bcmgenet_mii_probe(struct net_device *dev) 336 { 337 struct bcmgenet_priv *priv = netdev_priv(dev); 338 struct device_node *dn = priv->pdev->dev.of_node; 339 struct phy_device *phydev; 340 u32 phy_flags; 341 int ret; 342 343 /* Communicate the integrated PHY revision */ 344 phy_flags = priv->gphy_rev; 345 346 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 347 priv->old_link = -1; 348 priv->old_speed = -1; 349 priv->old_duplex = -1; 350 priv->old_pause = -1; 351 352 if (dn) { 353 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 354 phy_flags, priv->phy_interface); 355 if (!phydev) { 356 pr_err("could not attach to PHY\n"); 357 return -ENODEV; 358 } 359 } else { 360 phydev = priv->phydev; 361 phydev->dev_flags = phy_flags; 362 363 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 364 priv->phy_interface); 365 if (ret) { 366 pr_err("could not attach to PHY\n"); 367 return -ENODEV; 368 } 369 } 370 371 priv->phydev = phydev; 372 373 /* Configure port multiplexer based on what the probed PHY device since 374 * reading the 'max-speed' property determines the maximum supported 375 * PHY speed which is needed for bcmgenet_mii_config() to configure 376 * things appropriately. 377 */ 378 ret = bcmgenet_mii_config(dev); 379 if (ret) { 380 phy_disconnect(priv->phydev); 381 return ret; 382 } 383 384 phydev->advertising = phydev->supported; 385 386 /* The internal PHY has its link interrupts routed to the 387 * Ethernet MAC ISRs 388 */ 389 if (priv->internal_phy) 390 priv->phydev->irq = PHY_IGNORE_INTERRUPT; 391 392 return 0; 393 } 394 395 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with 396 * their internal MDIO management controller making them fail to successfully 397 * be read from or written to for the first transaction. We insert a dummy 398 * BMSR read here to make sure that phy_get_device() and get_phy_id() can 399 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a 400 * PHY device for this peripheral. 401 * 402 * Once the PHY driver is registered, we can workaround subsequent reads from 403 * there (e.g: during system-wide power management). 404 * 405 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is 406 * therefore the right location to stick that workaround. Since we do not want 407 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual 408 * Device Tree scan to limit the search area. 409 */ 410 static int bcmgenet_mii_bus_reset(struct mii_bus *bus) 411 { 412 struct net_device *dev = bus->priv; 413 struct bcmgenet_priv *priv = netdev_priv(dev); 414 struct device_node *np = priv->mdio_dn; 415 struct device_node *child = NULL; 416 u32 read_mask = 0; 417 int addr = 0; 418 419 if (!np) { 420 read_mask = 1 << priv->phy_addr; 421 } else { 422 for_each_available_child_of_node(np, child) { 423 addr = of_mdio_parse_addr(&dev->dev, child); 424 if (addr < 0) 425 continue; 426 427 read_mask |= 1 << addr; 428 } 429 } 430 431 for (addr = 0; addr < PHY_MAX_ADDR; addr++) { 432 if (read_mask & 1 << addr) { 433 dev_dbg(&dev->dev, "Workaround for PHY @ %d\n", addr); 434 mdiobus_read(bus, addr, MII_BMSR); 435 } 436 } 437 438 return 0; 439 } 440 441 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv) 442 { 443 struct mii_bus *bus; 444 445 if (priv->mii_bus) 446 return 0; 447 448 priv->mii_bus = mdiobus_alloc(); 449 if (!priv->mii_bus) { 450 pr_err("failed to allocate\n"); 451 return -ENOMEM; 452 } 453 454 bus = priv->mii_bus; 455 bus->priv = priv->dev; 456 bus->name = "bcmgenet MII bus"; 457 bus->parent = &priv->pdev->dev; 458 bus->read = bcmgenet_mii_read; 459 bus->write = bcmgenet_mii_write; 460 bus->reset = bcmgenet_mii_bus_reset; 461 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", 462 priv->pdev->name, priv->pdev->id); 463 464 return 0; 465 } 466 467 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 468 { 469 struct device_node *dn = priv->pdev->dev.of_node; 470 struct device *kdev = &priv->pdev->dev; 471 struct phy_device *phydev = NULL; 472 char *compat; 473 int phy_mode; 474 int ret; 475 476 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 477 if (!compat) 478 return -ENOMEM; 479 480 priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); 481 kfree(compat); 482 if (!priv->mdio_dn) { 483 dev_err(kdev, "unable to find MDIO bus node\n"); 484 return -ENODEV; 485 } 486 487 ret = of_mdiobus_register(priv->mii_bus, priv->mdio_dn); 488 if (ret) { 489 dev_err(kdev, "failed to register MDIO bus\n"); 490 return ret; 491 } 492 493 /* Fetch the PHY phandle */ 494 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 495 496 /* In the case of a fixed PHY, the DT node associated 497 * to the PHY is the Ethernet MAC DT node. 498 */ 499 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 500 ret = of_phy_register_fixed_link(dn); 501 if (ret) 502 return ret; 503 504 priv->phy_dn = of_node_get(dn); 505 } 506 507 /* Get the link mode */ 508 phy_mode = of_get_phy_mode(dn); 509 if (phy_mode < 0) { 510 dev_err(kdev, "invalid PHY mode property\n"); 511 return phy_mode; 512 } 513 514 priv->phy_interface = phy_mode; 515 516 /* We need to specifically look up whether this PHY interface is internal 517 * or not *before* we even try to probe the PHY driver over MDIO as we 518 * may have shut down the internal PHY for power saving purposes. 519 */ 520 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 521 priv->internal_phy = true; 522 523 /* Make sure we initialize MoCA PHYs with a link down */ 524 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 525 phydev = of_phy_find_device(dn); 526 if (phydev) { 527 phydev->link = 0; 528 put_device(&phydev->mdio.dev); 529 } 530 } 531 532 return 0; 533 } 534 535 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 536 { 537 struct device *kdev = &priv->pdev->dev; 538 struct bcmgenet_platform_data *pd = kdev->platform_data; 539 struct mii_bus *mdio = priv->mii_bus; 540 struct phy_device *phydev; 541 int ret; 542 543 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 544 /* 545 * Internal or external PHY with MDIO access 546 */ 547 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 548 mdio->phy_mask = ~(1 << pd->phy_address); 549 else 550 mdio->phy_mask = 0; 551 552 ret = mdiobus_register(mdio); 553 if (ret) { 554 dev_err(kdev, "failed to register MDIO bus\n"); 555 return ret; 556 } 557 558 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 559 phydev = mdiobus_get_phy(mdio, pd->phy_address); 560 else 561 phydev = phy_find_first(mdio); 562 563 if (!phydev) { 564 dev_err(kdev, "failed to register PHY device\n"); 565 mdiobus_unregister(mdio); 566 return -ENODEV; 567 } 568 } else { 569 /* 570 * MoCA port or no MDIO access. 571 * Use fixed PHY to represent the link layer. 572 */ 573 struct fixed_phy_status fphy_status = { 574 .link = 1, 575 .speed = pd->phy_speed, 576 .duplex = pd->phy_duplex, 577 .pause = 0, 578 .asym_pause = 0, 579 }; 580 581 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 582 if (!phydev || IS_ERR(phydev)) { 583 dev_err(kdev, "failed to register fixed PHY device\n"); 584 return -ENODEV; 585 } 586 587 /* Make sure we initialize MoCA PHYs with a link down */ 588 phydev->link = 0; 589 590 } 591 592 priv->phydev = phydev; 593 priv->phy_interface = pd->phy_interface; 594 595 return 0; 596 } 597 598 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 599 { 600 struct device_node *dn = priv->pdev->dev.of_node; 601 602 if (dn) 603 return bcmgenet_mii_of_init(priv); 604 else 605 return bcmgenet_mii_pd_init(priv); 606 } 607 608 int bcmgenet_mii_init(struct net_device *dev) 609 { 610 struct bcmgenet_priv *priv = netdev_priv(dev); 611 struct device_node *dn = priv->pdev->dev.of_node; 612 int ret; 613 614 ret = bcmgenet_mii_alloc(priv); 615 if (ret) 616 return ret; 617 618 ret = bcmgenet_mii_bus_init(priv); 619 if (ret) 620 goto out; 621 622 return 0; 623 624 out: 625 if (of_phy_is_fixed_link(dn)) 626 of_phy_deregister_fixed_link(dn); 627 of_node_put(priv->phy_dn); 628 mdiobus_unregister(priv->mii_bus); 629 mdiobus_free(priv->mii_bus); 630 return ret; 631 } 632 633 void bcmgenet_mii_exit(struct net_device *dev) 634 { 635 struct bcmgenet_priv *priv = netdev_priv(dev); 636 struct device_node *dn = priv->pdev->dev.of_node; 637 638 if (of_phy_is_fixed_link(dn)) 639 of_phy_deregister_fixed_link(dn); 640 of_node_put(priv->phy_dn); 641 mdiobus_unregister(priv->mii_bus); 642 mdiobus_free(priv->mii_bus); 643 } 644