1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 #include <linux/platform_data/mdio-bcm-unimac.h> 28 29 #include "bcmgenet.h" 30 31 /* setup netdev link state when PHY link status change and 32 * update UMAC and RGMII block when link up 33 */ 34 void bcmgenet_mii_setup(struct net_device *dev) 35 { 36 struct bcmgenet_priv *priv = netdev_priv(dev); 37 struct phy_device *phydev = dev->phydev; 38 u32 reg, cmd_bits = 0; 39 bool status_changed = false; 40 41 if (priv->old_link != phydev->link) { 42 status_changed = true; 43 priv->old_link = phydev->link; 44 } 45 46 if (phydev->link) { 47 /* check speed/duplex/pause changes */ 48 if (priv->old_speed != phydev->speed) { 49 status_changed = true; 50 priv->old_speed = phydev->speed; 51 } 52 53 if (priv->old_duplex != phydev->duplex) { 54 status_changed = true; 55 priv->old_duplex = phydev->duplex; 56 } 57 58 if (priv->old_pause != phydev->pause) { 59 status_changed = true; 60 priv->old_pause = phydev->pause; 61 } 62 63 /* done if nothing has changed */ 64 if (!status_changed) 65 return; 66 67 /* speed */ 68 if (phydev->speed == SPEED_1000) 69 cmd_bits = UMAC_SPEED_1000; 70 else if (phydev->speed == SPEED_100) 71 cmd_bits = UMAC_SPEED_100; 72 else 73 cmd_bits = UMAC_SPEED_10; 74 cmd_bits <<= CMD_SPEED_SHIFT; 75 76 /* duplex */ 77 if (phydev->duplex != DUPLEX_FULL) 78 cmd_bits |= CMD_HD_EN; 79 80 /* pause capability */ 81 if (!phydev->pause) 82 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 83 84 /* 85 * Program UMAC and RGMII block based on established 86 * link speed, duplex, and pause. The speed set in 87 * umac->cmd tell RGMII block which clock to use for 88 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 89 * Receive clock is provided by the PHY. 90 */ 91 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 92 reg &= ~OOB_DISABLE; 93 reg |= RGMII_LINK; 94 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 95 96 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 97 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 98 CMD_HD_EN | 99 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 100 reg |= cmd_bits; 101 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 102 } else { 103 /* done if nothing has changed */ 104 if (!status_changed) 105 return; 106 107 /* needed for MoCA fixed PHY to reflect correct link status */ 108 netif_carrier_off(dev); 109 } 110 111 phy_print_status(phydev); 112 } 113 114 115 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 116 struct fixed_phy_status *status) 117 { 118 struct bcmgenet_priv *priv; 119 u32 reg; 120 121 if (dev && dev->phydev && status) { 122 priv = netdev_priv(dev); 123 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 124 status->link = !!(reg & MODE_LINK_STATUS); 125 } 126 127 return 0; 128 } 129 130 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 131 { 132 struct bcmgenet_priv *priv = netdev_priv(dev); 133 u32 reg = 0; 134 135 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 136 if (GENET_IS_V4(priv)) { 137 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 138 if (enable) { 139 reg &= ~EXT_CK25_DIS; 140 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 141 mdelay(1); 142 143 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 144 reg |= EXT_GPHY_RESET; 145 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 146 mdelay(1); 147 148 reg &= ~EXT_GPHY_RESET; 149 } else { 150 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 151 EXT_GPHY_RESET; 152 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 153 mdelay(1); 154 reg |= EXT_CK25_DIS; 155 } 156 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 157 udelay(60); 158 } else { 159 mdelay(1); 160 } 161 } 162 163 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 164 { 165 u32 reg; 166 167 if (!GENET_IS_V5(priv)) { 168 /* Speed settings are set in bcmgenet_mii_setup() */ 169 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 170 reg |= LED_ACT_SOURCE_MAC; 171 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 172 } 173 174 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 175 fixed_phy_set_link_update(priv->dev->phydev, 176 bcmgenet_fixed_phy_link_update); 177 } 178 179 int bcmgenet_mii_config(struct net_device *dev, bool init) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 struct phy_device *phydev = dev->phydev; 183 struct device *kdev = &priv->pdev->dev; 184 const char *phy_name = NULL; 185 u32 id_mode_dis = 0; 186 u32 port_ctrl; 187 u32 reg; 188 189 priv->ext_phy = !priv->internal_phy && 190 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 191 192 switch (priv->phy_interface) { 193 case PHY_INTERFACE_MODE_INTERNAL: 194 case PHY_INTERFACE_MODE_MOCA: 195 /* Irrespective of the actually configured PHY speed (100 or 196 * 1000) GENETv4 only has an internal GPHY so we will just end 197 * up masking the Gigabit features from what we support, not 198 * switching to the EPHY 199 */ 200 if (GENET_IS_V4(priv)) 201 port_ctrl = PORT_MODE_INT_GPHY; 202 else 203 port_ctrl = PORT_MODE_INT_EPHY; 204 205 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 206 207 if (priv->internal_phy) { 208 phy_name = "internal PHY"; 209 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 210 phy_name = "MoCA"; 211 bcmgenet_moca_phy_setup(priv); 212 } 213 break; 214 215 case PHY_INTERFACE_MODE_MII: 216 phy_name = "external MII"; 217 phydev->supported &= PHY_BASIC_FEATURES; 218 bcmgenet_sys_writel(priv, 219 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 220 break; 221 222 case PHY_INTERFACE_MODE_REVMII: 223 phy_name = "external RvMII"; 224 /* of_mdiobus_register took care of reading the 'max-speed' 225 * PHY property for us, effectively limiting the PHY supported 226 * capabilities, use that knowledge to also configure the 227 * Reverse MII interface correctly. 228 */ 229 if ((dev->phydev->supported & PHY_BASIC_FEATURES) == 230 PHY_BASIC_FEATURES) 231 port_ctrl = PORT_MODE_EXT_RVMII_25; 232 else 233 port_ctrl = PORT_MODE_EXT_RVMII_50; 234 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 235 break; 236 237 case PHY_INTERFACE_MODE_RGMII: 238 /* RGMII_NO_ID: TXC transitions at the same time as TXD 239 * (requires PCB or receiver-side delay) 240 * RGMII: Add 2ns delay on TXC (90 degree shift) 241 * 242 * ID is implicitly disabled for 100Mbps (RG)MII operation. 243 */ 244 id_mode_dis = BIT(16); 245 /* fall through */ 246 case PHY_INTERFACE_MODE_RGMII_TXID: 247 if (id_mode_dis) 248 phy_name = "external RGMII (no delay)"; 249 else 250 phy_name = "external RGMII (TX delay)"; 251 bcmgenet_sys_writel(priv, 252 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 253 break; 254 default: 255 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 256 return -EINVAL; 257 } 258 259 /* This is an external PHY (xMII), so we need to enable the RGMII 260 * block for the interface to work 261 */ 262 if (priv->ext_phy) { 263 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 264 reg |= RGMII_MODE_EN | id_mode_dis; 265 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 266 } 267 268 if (init) 269 dev_info(kdev, "configuring instance for %s\n", phy_name); 270 271 return 0; 272 } 273 274 int bcmgenet_mii_probe(struct net_device *dev) 275 { 276 struct bcmgenet_priv *priv = netdev_priv(dev); 277 struct device_node *dn = priv->pdev->dev.of_node; 278 struct phy_device *phydev; 279 u32 phy_flags; 280 int ret; 281 282 /* Communicate the integrated PHY revision */ 283 phy_flags = priv->gphy_rev; 284 285 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 286 priv->old_link = -1; 287 priv->old_speed = -1; 288 priv->old_duplex = -1; 289 priv->old_pause = -1; 290 291 if (dn) { 292 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 293 phy_flags, priv->phy_interface); 294 if (!phydev) { 295 pr_err("could not attach to PHY\n"); 296 return -ENODEV; 297 } 298 } else { 299 phydev = dev->phydev; 300 phydev->dev_flags = phy_flags; 301 302 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 303 priv->phy_interface); 304 if (ret) { 305 pr_err("could not attach to PHY\n"); 306 return -ENODEV; 307 } 308 } 309 310 /* Configure port multiplexer based on what the probed PHY device since 311 * reading the 'max-speed' property determines the maximum supported 312 * PHY speed which is needed for bcmgenet_mii_config() to configure 313 * things appropriately. 314 */ 315 ret = bcmgenet_mii_config(dev, true); 316 if (ret) { 317 phy_disconnect(dev->phydev); 318 return ret; 319 } 320 321 phydev->advertising = phydev->supported; 322 323 /* The internal PHY has its link interrupts routed to the 324 * Ethernet MAC ISRs 325 */ 326 if (priv->internal_phy) 327 dev->phydev->irq = PHY_IGNORE_INTERRUPT; 328 329 return 0; 330 } 331 332 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 333 { 334 struct device_node *dn = priv->pdev->dev.of_node; 335 struct device *kdev = &priv->pdev->dev; 336 char *compat; 337 338 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 339 if (!compat) 340 return NULL; 341 342 priv->mdio_dn = of_find_compatible_node(dn, NULL, compat); 343 kfree(compat); 344 if (!priv->mdio_dn) { 345 dev_err(kdev, "unable to find MDIO bus node\n"); 346 return NULL; 347 } 348 349 return priv->mdio_dn; 350 } 351 352 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 353 struct unimac_mdio_pdata *ppd) 354 { 355 struct device *kdev = &priv->pdev->dev; 356 struct bcmgenet_platform_data *pd = kdev->platform_data; 357 358 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 359 /* 360 * Internal or external PHY with MDIO access 361 */ 362 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 363 ppd->phy_mask = 1 << pd->phy_address; 364 else 365 ppd->phy_mask = 0; 366 } 367 } 368 369 static int bcmgenet_mii_wait(void *wait_func_data) 370 { 371 struct bcmgenet_priv *priv = wait_func_data; 372 373 wait_event_timeout(priv->wq, 374 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 375 & MDIO_START_BUSY), 376 HZ / 100); 377 return 0; 378 } 379 380 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 381 { 382 struct platform_device *pdev = priv->pdev; 383 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 384 struct device_node *dn = pdev->dev.of_node; 385 struct unimac_mdio_pdata ppd; 386 struct platform_device *ppdev; 387 struct resource *pres, res; 388 int id, ret; 389 390 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 391 memset(&res, 0, sizeof(res)); 392 memset(&ppd, 0, sizeof(ppd)); 393 394 ppd.wait_func = bcmgenet_mii_wait; 395 ppd.wait_func_data = priv; 396 ppd.bus_name = "bcmgenet MII bus"; 397 398 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 399 * and is 2 * 32-bits word long, 8 bytes total. 400 */ 401 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 402 res.end = res.start + 8; 403 res.flags = IORESOURCE_MEM; 404 405 if (dn) 406 id = of_alias_get_id(dn, "eth"); 407 else 408 id = pdev->id; 409 410 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 411 if (!ppdev) 412 return -ENOMEM; 413 414 /* Retain this platform_device pointer for later cleanup */ 415 priv->mii_pdev = ppdev; 416 ppdev->dev.parent = &pdev->dev; 417 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 418 if (pdata) 419 bcmgenet_mii_pdata_init(priv, &ppd); 420 421 ret = platform_device_add_resources(ppdev, &res, 1); 422 if (ret) 423 goto out; 424 425 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 426 if (ret) 427 goto out; 428 429 ret = platform_device_add(ppdev); 430 if (ret) 431 goto out; 432 433 return 0; 434 out: 435 platform_device_put(ppdev); 436 return ret; 437 } 438 439 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 440 { 441 struct device_node *dn = priv->pdev->dev.of_node; 442 struct device *kdev = &priv->pdev->dev; 443 struct phy_device *phydev; 444 int phy_mode; 445 int ret; 446 447 /* Fetch the PHY phandle */ 448 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 449 450 /* In the case of a fixed PHY, the DT node associated 451 * to the PHY is the Ethernet MAC DT node. 452 */ 453 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 454 ret = of_phy_register_fixed_link(dn); 455 if (ret) 456 return ret; 457 458 priv->phy_dn = of_node_get(dn); 459 } 460 461 /* Get the link mode */ 462 phy_mode = of_get_phy_mode(dn); 463 if (phy_mode < 0) { 464 dev_err(kdev, "invalid PHY mode property\n"); 465 return phy_mode; 466 } 467 468 priv->phy_interface = phy_mode; 469 470 /* We need to specifically look up whether this PHY interface is internal 471 * or not *before* we even try to probe the PHY driver over MDIO as we 472 * may have shut down the internal PHY for power saving purposes. 473 */ 474 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 475 priv->internal_phy = true; 476 477 /* Make sure we initialize MoCA PHYs with a link down */ 478 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 479 phydev = of_phy_find_device(dn); 480 if (phydev) { 481 phydev->link = 0; 482 put_device(&phydev->mdio.dev); 483 } 484 } 485 486 return 0; 487 } 488 489 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 490 { 491 struct device *kdev = &priv->pdev->dev; 492 struct bcmgenet_platform_data *pd = kdev->platform_data; 493 char phy_name[MII_BUS_ID_SIZE + 3]; 494 char mdio_bus_id[MII_BUS_ID_SIZE]; 495 struct phy_device *phydev; 496 497 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 498 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 499 500 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 501 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 502 mdio_bus_id, pd->phy_address); 503 504 /* 505 * Internal or external PHY with MDIO access 506 */ 507 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 508 if (!phydev) { 509 dev_err(kdev, "failed to register PHY device\n"); 510 return -ENODEV; 511 } 512 } else { 513 /* 514 * MoCA port or no MDIO access. 515 * Use fixed PHY to represent the link layer. 516 */ 517 struct fixed_phy_status fphy_status = { 518 .link = 1, 519 .speed = pd->phy_speed, 520 .duplex = pd->phy_duplex, 521 .pause = 0, 522 .asym_pause = 0, 523 }; 524 525 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 526 if (!phydev || IS_ERR(phydev)) { 527 dev_err(kdev, "failed to register fixed PHY device\n"); 528 return -ENODEV; 529 } 530 531 /* Make sure we initialize MoCA PHYs with a link down */ 532 phydev->link = 0; 533 534 } 535 536 priv->phy_interface = pd->phy_interface; 537 538 return 0; 539 } 540 541 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 542 { 543 struct device_node *dn = priv->pdev->dev.of_node; 544 545 if (dn) 546 return bcmgenet_mii_of_init(priv); 547 else 548 return bcmgenet_mii_pd_init(priv); 549 } 550 551 int bcmgenet_mii_init(struct net_device *dev) 552 { 553 struct bcmgenet_priv *priv = netdev_priv(dev); 554 int ret; 555 556 ret = bcmgenet_mii_register(priv); 557 if (ret) 558 return ret; 559 560 ret = bcmgenet_mii_bus_init(priv); 561 if (ret) 562 goto out; 563 564 return 0; 565 566 out: 567 bcmgenet_mii_exit(dev); 568 return ret; 569 } 570 571 void bcmgenet_mii_exit(struct net_device *dev) 572 { 573 struct bcmgenet_priv *priv = netdev_priv(dev); 574 struct device_node *dn = priv->pdev->dev.of_node; 575 576 if (of_phy_is_fixed_link(dn)) 577 of_phy_deregister_fixed_link(dn); 578 of_node_put(priv->phy_dn); 579 platform_device_unregister(priv->mii_pdev); 580 } 581