1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 #include <linux/platform_data/mdio-bcm-unimac.h> 28 29 #include "bcmgenet.h" 30 31 /* setup netdev link state when PHY link status change and 32 * update UMAC and RGMII block when link up 33 */ 34 void bcmgenet_mii_setup(struct net_device *dev) 35 { 36 struct bcmgenet_priv *priv = netdev_priv(dev); 37 struct phy_device *phydev = dev->phydev; 38 u32 reg, cmd_bits = 0; 39 bool status_changed = false; 40 41 if (priv->old_link != phydev->link) { 42 status_changed = true; 43 priv->old_link = phydev->link; 44 } 45 46 if (phydev->link) { 47 /* check speed/duplex/pause changes */ 48 if (priv->old_speed != phydev->speed) { 49 status_changed = true; 50 priv->old_speed = phydev->speed; 51 } 52 53 if (priv->old_duplex != phydev->duplex) { 54 status_changed = true; 55 priv->old_duplex = phydev->duplex; 56 } 57 58 if (priv->old_pause != phydev->pause) { 59 status_changed = true; 60 priv->old_pause = phydev->pause; 61 } 62 63 /* done if nothing has changed */ 64 if (!status_changed) 65 return; 66 67 /* speed */ 68 if (phydev->speed == SPEED_1000) 69 cmd_bits = UMAC_SPEED_1000; 70 else if (phydev->speed == SPEED_100) 71 cmd_bits = UMAC_SPEED_100; 72 else 73 cmd_bits = UMAC_SPEED_10; 74 cmd_bits <<= CMD_SPEED_SHIFT; 75 76 /* duplex */ 77 if (phydev->duplex != DUPLEX_FULL) 78 cmd_bits |= CMD_HD_EN; 79 80 /* pause capability */ 81 if (!phydev->pause) 82 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 83 84 /* 85 * Program UMAC and RGMII block based on established 86 * link speed, duplex, and pause. The speed set in 87 * umac->cmd tell RGMII block which clock to use for 88 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 89 * Receive clock is provided by the PHY. 90 */ 91 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 92 reg &= ~OOB_DISABLE; 93 reg |= RGMII_LINK; 94 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 95 96 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 97 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 98 CMD_HD_EN | 99 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 100 reg |= cmd_bits; 101 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 102 } else { 103 /* done if nothing has changed */ 104 if (!status_changed) 105 return; 106 107 /* needed for MoCA fixed PHY to reflect correct link status */ 108 netif_carrier_off(dev); 109 } 110 111 phy_print_status(phydev); 112 } 113 114 115 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 116 struct fixed_phy_status *status) 117 { 118 struct bcmgenet_priv *priv; 119 u32 reg; 120 121 if (dev && dev->phydev && status) { 122 priv = netdev_priv(dev); 123 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 124 status->link = !!(reg & MODE_LINK_STATUS); 125 } 126 127 return 0; 128 } 129 130 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 131 { 132 struct bcmgenet_priv *priv = netdev_priv(dev); 133 u32 reg = 0; 134 135 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 136 if (GENET_IS_V4(priv)) { 137 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 138 if (enable) { 139 reg &= ~EXT_CK25_DIS; 140 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 141 mdelay(1); 142 143 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 144 reg |= EXT_GPHY_RESET; 145 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 146 mdelay(1); 147 148 reg &= ~EXT_GPHY_RESET; 149 } else { 150 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 151 EXT_GPHY_RESET; 152 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 153 mdelay(1); 154 reg |= EXT_CK25_DIS; 155 } 156 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 157 udelay(60); 158 } else { 159 mdelay(1); 160 } 161 } 162 163 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 164 { 165 u32 reg; 166 167 if (!GENET_IS_V5(priv)) { 168 /* Speed settings are set in bcmgenet_mii_setup() */ 169 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 170 reg |= LED_ACT_SOURCE_MAC; 171 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 172 } 173 174 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 175 fixed_phy_set_link_update(priv->dev->phydev, 176 bcmgenet_fixed_phy_link_update); 177 } 178 179 int bcmgenet_mii_config(struct net_device *dev, bool init) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 struct phy_device *phydev = dev->phydev; 183 struct device *kdev = &priv->pdev->dev; 184 const char *phy_name = NULL; 185 u32 id_mode_dis = 0; 186 u32 port_ctrl; 187 u32 reg; 188 189 priv->ext_phy = !priv->internal_phy && 190 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 191 192 switch (priv->phy_interface) { 193 case PHY_INTERFACE_MODE_INTERNAL: 194 case PHY_INTERFACE_MODE_MOCA: 195 /* Irrespective of the actually configured PHY speed (100 or 196 * 1000) GENETv4 only has an internal GPHY so we will just end 197 * up masking the Gigabit features from what we support, not 198 * switching to the EPHY 199 */ 200 if (GENET_IS_V4(priv)) 201 port_ctrl = PORT_MODE_INT_GPHY; 202 else 203 port_ctrl = PORT_MODE_INT_EPHY; 204 205 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 206 207 if (priv->internal_phy) { 208 phy_name = "internal PHY"; 209 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 210 phy_name = "MoCA"; 211 bcmgenet_moca_phy_setup(priv); 212 } 213 break; 214 215 case PHY_INTERFACE_MODE_MII: 216 phy_name = "external MII"; 217 phy_set_max_speed(phydev, SPEED_100); 218 bcmgenet_sys_writel(priv, 219 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 220 break; 221 222 case PHY_INTERFACE_MODE_REVMII: 223 phy_name = "external RvMII"; 224 /* of_mdiobus_register took care of reading the 'max-speed' 225 * PHY property for us, effectively limiting the PHY supported 226 * capabilities, use that knowledge to also configure the 227 * Reverse MII interface correctly. 228 */ 229 if (dev->phydev->supported & PHY_1000BT_FEATURES) 230 port_ctrl = PORT_MODE_EXT_RVMII_50; 231 else 232 port_ctrl = PORT_MODE_EXT_RVMII_25; 233 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 234 break; 235 236 case PHY_INTERFACE_MODE_RGMII: 237 /* RGMII_NO_ID: TXC transitions at the same time as TXD 238 * (requires PCB or receiver-side delay) 239 * RGMII: Add 2ns delay on TXC (90 degree shift) 240 * 241 * ID is implicitly disabled for 100Mbps (RG)MII operation. 242 */ 243 id_mode_dis = BIT(16); 244 /* fall through */ 245 case PHY_INTERFACE_MODE_RGMII_TXID: 246 if (id_mode_dis) 247 phy_name = "external RGMII (no delay)"; 248 else 249 phy_name = "external RGMII (TX delay)"; 250 bcmgenet_sys_writel(priv, 251 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 252 break; 253 default: 254 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 255 return -EINVAL; 256 } 257 258 /* This is an external PHY (xMII), so we need to enable the RGMII 259 * block for the interface to work 260 */ 261 if (priv->ext_phy) { 262 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 263 reg |= RGMII_MODE_EN | id_mode_dis; 264 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 265 } 266 267 if (init) 268 dev_info(kdev, "configuring instance for %s\n", phy_name); 269 270 return 0; 271 } 272 273 int bcmgenet_mii_probe(struct net_device *dev) 274 { 275 struct bcmgenet_priv *priv = netdev_priv(dev); 276 struct device_node *dn = priv->pdev->dev.of_node; 277 struct phy_device *phydev; 278 u32 phy_flags; 279 int ret; 280 281 /* Communicate the integrated PHY revision */ 282 phy_flags = priv->gphy_rev; 283 284 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 285 priv->old_link = -1; 286 priv->old_speed = -1; 287 priv->old_duplex = -1; 288 priv->old_pause = -1; 289 290 if (dn) { 291 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 292 phy_flags, priv->phy_interface); 293 if (!phydev) { 294 pr_err("could not attach to PHY\n"); 295 return -ENODEV; 296 } 297 } else { 298 phydev = dev->phydev; 299 phydev->dev_flags = phy_flags; 300 301 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 302 priv->phy_interface); 303 if (ret) { 304 pr_err("could not attach to PHY\n"); 305 return -ENODEV; 306 } 307 } 308 309 /* Configure port multiplexer based on what the probed PHY device since 310 * reading the 'max-speed' property determines the maximum supported 311 * PHY speed which is needed for bcmgenet_mii_config() to configure 312 * things appropriately. 313 */ 314 ret = bcmgenet_mii_config(dev, true); 315 if (ret) { 316 phy_disconnect(dev->phydev); 317 return ret; 318 } 319 320 phydev->advertising = phydev->supported; 321 322 /* The internal PHY has its link interrupts routed to the 323 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 324 * that prevents the signaling of link UP interrupts when 325 * the link operates at 10Mbps, so fallback to polling for 326 * those versions of GENET. 327 */ 328 if (priv->internal_phy && !GENET_IS_V5(priv)) 329 dev->phydev->irq = PHY_IGNORE_INTERRUPT; 330 331 return 0; 332 } 333 334 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 335 { 336 struct device_node *dn = priv->pdev->dev.of_node; 337 struct device *kdev = &priv->pdev->dev; 338 char *compat; 339 340 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 341 if (!compat) 342 return NULL; 343 344 priv->mdio_dn = of_get_compatible_child(dn, compat); 345 kfree(compat); 346 if (!priv->mdio_dn) { 347 dev_err(kdev, "unable to find MDIO bus node\n"); 348 return NULL; 349 } 350 351 return priv->mdio_dn; 352 } 353 354 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 355 struct unimac_mdio_pdata *ppd) 356 { 357 struct device *kdev = &priv->pdev->dev; 358 struct bcmgenet_platform_data *pd = kdev->platform_data; 359 360 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 361 /* 362 * Internal or external PHY with MDIO access 363 */ 364 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 365 ppd->phy_mask = 1 << pd->phy_address; 366 else 367 ppd->phy_mask = 0; 368 } 369 } 370 371 static int bcmgenet_mii_wait(void *wait_func_data) 372 { 373 struct bcmgenet_priv *priv = wait_func_data; 374 375 wait_event_timeout(priv->wq, 376 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 377 & MDIO_START_BUSY), 378 HZ / 100); 379 return 0; 380 } 381 382 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 383 { 384 struct platform_device *pdev = priv->pdev; 385 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 386 struct device_node *dn = pdev->dev.of_node; 387 struct unimac_mdio_pdata ppd; 388 struct platform_device *ppdev; 389 struct resource *pres, res; 390 int id, ret; 391 392 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 393 memset(&res, 0, sizeof(res)); 394 memset(&ppd, 0, sizeof(ppd)); 395 396 ppd.wait_func = bcmgenet_mii_wait; 397 ppd.wait_func_data = priv; 398 ppd.bus_name = "bcmgenet MII bus"; 399 400 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 401 * and is 2 * 32-bits word long, 8 bytes total. 402 */ 403 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 404 res.end = res.start + 8; 405 res.flags = IORESOURCE_MEM; 406 407 if (dn) 408 id = of_alias_get_id(dn, "eth"); 409 else 410 id = pdev->id; 411 412 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 413 if (!ppdev) 414 return -ENOMEM; 415 416 /* Retain this platform_device pointer for later cleanup */ 417 priv->mii_pdev = ppdev; 418 ppdev->dev.parent = &pdev->dev; 419 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 420 if (pdata) 421 bcmgenet_mii_pdata_init(priv, &ppd); 422 423 ret = platform_device_add_resources(ppdev, &res, 1); 424 if (ret) 425 goto out; 426 427 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 428 if (ret) 429 goto out; 430 431 ret = platform_device_add(ppdev); 432 if (ret) 433 goto out; 434 435 return 0; 436 out: 437 platform_device_put(ppdev); 438 return ret; 439 } 440 441 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 442 { 443 struct device_node *dn = priv->pdev->dev.of_node; 444 struct device *kdev = &priv->pdev->dev; 445 struct phy_device *phydev; 446 int phy_mode; 447 int ret; 448 449 /* Fetch the PHY phandle */ 450 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 451 452 /* In the case of a fixed PHY, the DT node associated 453 * to the PHY is the Ethernet MAC DT node. 454 */ 455 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 456 ret = of_phy_register_fixed_link(dn); 457 if (ret) 458 return ret; 459 460 priv->phy_dn = of_node_get(dn); 461 } 462 463 /* Get the link mode */ 464 phy_mode = of_get_phy_mode(dn); 465 if (phy_mode < 0) { 466 dev_err(kdev, "invalid PHY mode property\n"); 467 return phy_mode; 468 } 469 470 priv->phy_interface = phy_mode; 471 472 /* We need to specifically look up whether this PHY interface is internal 473 * or not *before* we even try to probe the PHY driver over MDIO as we 474 * may have shut down the internal PHY for power saving purposes. 475 */ 476 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 477 priv->internal_phy = true; 478 479 /* Make sure we initialize MoCA PHYs with a link down */ 480 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 481 phydev = of_phy_find_device(dn); 482 if (phydev) { 483 phydev->link = 0; 484 put_device(&phydev->mdio.dev); 485 } 486 } 487 488 return 0; 489 } 490 491 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 492 { 493 struct device *kdev = &priv->pdev->dev; 494 struct bcmgenet_platform_data *pd = kdev->platform_data; 495 char phy_name[MII_BUS_ID_SIZE + 3]; 496 char mdio_bus_id[MII_BUS_ID_SIZE]; 497 struct phy_device *phydev; 498 499 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 500 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 501 502 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 503 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 504 mdio_bus_id, pd->phy_address); 505 506 /* 507 * Internal or external PHY with MDIO access 508 */ 509 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 510 if (!phydev) { 511 dev_err(kdev, "failed to register PHY device\n"); 512 return -ENODEV; 513 } 514 } else { 515 /* 516 * MoCA port or no MDIO access. 517 * Use fixed PHY to represent the link layer. 518 */ 519 struct fixed_phy_status fphy_status = { 520 .link = 1, 521 .speed = pd->phy_speed, 522 .duplex = pd->phy_duplex, 523 .pause = 0, 524 .asym_pause = 0, 525 }; 526 527 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); 528 if (!phydev || IS_ERR(phydev)) { 529 dev_err(kdev, "failed to register fixed PHY device\n"); 530 return -ENODEV; 531 } 532 533 /* Make sure we initialize MoCA PHYs with a link down */ 534 phydev->link = 0; 535 536 } 537 538 priv->phy_interface = pd->phy_interface; 539 540 return 0; 541 } 542 543 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 544 { 545 struct device_node *dn = priv->pdev->dev.of_node; 546 547 if (dn) 548 return bcmgenet_mii_of_init(priv); 549 else 550 return bcmgenet_mii_pd_init(priv); 551 } 552 553 int bcmgenet_mii_init(struct net_device *dev) 554 { 555 struct bcmgenet_priv *priv = netdev_priv(dev); 556 int ret; 557 558 ret = bcmgenet_mii_register(priv); 559 if (ret) 560 return ret; 561 562 ret = bcmgenet_mii_bus_init(priv); 563 if (ret) 564 goto out; 565 566 return 0; 567 568 out: 569 bcmgenet_mii_exit(dev); 570 return ret; 571 } 572 573 void bcmgenet_mii_exit(struct net_device *dev) 574 { 575 struct bcmgenet_priv *priv = netdev_priv(dev); 576 struct device_node *dn = priv->pdev->dev.of_node; 577 578 if (of_phy_is_fixed_link(dn)) 579 of_phy_deregister_fixed_link(dn); 580 of_node_put(priv->phy_dn); 581 platform_device_unregister(priv->mii_pdev); 582 } 583