1 /* 2 * Broadcom GENET MDIO routines 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 12 #include <linux/types.h> 13 #include <linux/delay.h> 14 #include <linux/wait.h> 15 #include <linux/mii.h> 16 #include <linux/ethtool.h> 17 #include <linux/bitops.h> 18 #include <linux/netdevice.h> 19 #include <linux/platform_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy_fixed.h> 22 #include <linux/brcmphy.h> 23 #include <linux/of.h> 24 #include <linux/of_net.h> 25 #include <linux/of_mdio.h> 26 #include <linux/platform_data/bcmgenet.h> 27 #include <linux/platform_data/mdio-bcm-unimac.h> 28 29 #include "bcmgenet.h" 30 31 /* setup netdev link state when PHY link status change and 32 * update UMAC and RGMII block when link up 33 */ 34 void bcmgenet_mii_setup(struct net_device *dev) 35 { 36 struct bcmgenet_priv *priv = netdev_priv(dev); 37 struct phy_device *phydev = dev->phydev; 38 u32 reg, cmd_bits = 0; 39 bool status_changed = false; 40 41 if (priv->old_link != phydev->link) { 42 status_changed = true; 43 priv->old_link = phydev->link; 44 } 45 46 if (phydev->link) { 47 /* check speed/duplex/pause changes */ 48 if (priv->old_speed != phydev->speed) { 49 status_changed = true; 50 priv->old_speed = phydev->speed; 51 } 52 53 if (priv->old_duplex != phydev->duplex) { 54 status_changed = true; 55 priv->old_duplex = phydev->duplex; 56 } 57 58 if (priv->old_pause != phydev->pause) { 59 status_changed = true; 60 priv->old_pause = phydev->pause; 61 } 62 63 /* done if nothing has changed */ 64 if (!status_changed) 65 return; 66 67 /* speed */ 68 if (phydev->speed == SPEED_1000) 69 cmd_bits = UMAC_SPEED_1000; 70 else if (phydev->speed == SPEED_100) 71 cmd_bits = UMAC_SPEED_100; 72 else 73 cmd_bits = UMAC_SPEED_10; 74 cmd_bits <<= CMD_SPEED_SHIFT; 75 76 /* duplex */ 77 if (phydev->duplex != DUPLEX_FULL) 78 cmd_bits |= CMD_HD_EN; 79 80 /* pause capability */ 81 if (!phydev->pause) 82 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; 83 84 /* 85 * Program UMAC and RGMII block based on established 86 * link speed, duplex, and pause. The speed set in 87 * umac->cmd tell RGMII block which clock to use for 88 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps). 89 * Receive clock is provided by the PHY. 90 */ 91 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 92 reg &= ~OOB_DISABLE; 93 reg |= RGMII_LINK; 94 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 95 96 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 97 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | 98 CMD_HD_EN | 99 CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE); 100 reg |= cmd_bits; 101 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 102 } else { 103 /* done if nothing has changed */ 104 if (!status_changed) 105 return; 106 107 /* needed for MoCA fixed PHY to reflect correct link status */ 108 netif_carrier_off(dev); 109 } 110 111 phy_print_status(phydev); 112 } 113 114 115 static int bcmgenet_fixed_phy_link_update(struct net_device *dev, 116 struct fixed_phy_status *status) 117 { 118 struct bcmgenet_priv *priv; 119 u32 reg; 120 121 if (dev && dev->phydev && status) { 122 priv = netdev_priv(dev); 123 reg = bcmgenet_umac_readl(priv, UMAC_MODE); 124 status->link = !!(reg & MODE_LINK_STATUS); 125 } 126 127 return 0; 128 } 129 130 void bcmgenet_phy_power_set(struct net_device *dev, bool enable) 131 { 132 struct bcmgenet_priv *priv = netdev_priv(dev); 133 u32 reg = 0; 134 135 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */ 136 if (GENET_IS_V4(priv)) { 137 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL); 138 if (enable) { 139 reg &= ~EXT_CK25_DIS; 140 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 141 mdelay(1); 142 143 reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN); 144 reg |= EXT_GPHY_RESET; 145 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 146 mdelay(1); 147 148 reg &= ~EXT_GPHY_RESET; 149 } else { 150 reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN | 151 EXT_GPHY_RESET; 152 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 153 mdelay(1); 154 reg |= EXT_CK25_DIS; 155 } 156 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL); 157 udelay(60); 158 } else { 159 mdelay(1); 160 } 161 } 162 163 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv) 164 { 165 u32 reg; 166 167 if (!GENET_IS_V5(priv)) { 168 /* Speed settings are set in bcmgenet_mii_setup() */ 169 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL); 170 reg |= LED_ACT_SOURCE_MAC; 171 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL); 172 } 173 174 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 175 fixed_phy_set_link_update(priv->dev->phydev, 176 bcmgenet_fixed_phy_link_update); 177 } 178 179 int bcmgenet_mii_config(struct net_device *dev, bool init) 180 { 181 struct bcmgenet_priv *priv = netdev_priv(dev); 182 struct phy_device *phydev = dev->phydev; 183 struct device *kdev = &priv->pdev->dev; 184 const char *phy_name = NULL; 185 u32 id_mode_dis = 0; 186 u32 port_ctrl; 187 u32 reg; 188 189 priv->ext_phy = !priv->internal_phy && 190 (priv->phy_interface != PHY_INTERFACE_MODE_MOCA); 191 192 switch (priv->phy_interface) { 193 case PHY_INTERFACE_MODE_INTERNAL: 194 case PHY_INTERFACE_MODE_MOCA: 195 /* Irrespective of the actually configured PHY speed (100 or 196 * 1000) GENETv4 only has an internal GPHY so we will just end 197 * up masking the Gigabit features from what we support, not 198 * switching to the EPHY 199 */ 200 if (GENET_IS_V4(priv)) 201 port_ctrl = PORT_MODE_INT_GPHY; 202 else 203 port_ctrl = PORT_MODE_INT_EPHY; 204 205 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 206 207 if (priv->internal_phy) { 208 phy_name = "internal PHY"; 209 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 210 phy_name = "MoCA"; 211 bcmgenet_moca_phy_setup(priv); 212 } 213 break; 214 215 case PHY_INTERFACE_MODE_MII: 216 phy_name = "external MII"; 217 phy_set_max_speed(phydev, SPEED_100); 218 bcmgenet_sys_writel(priv, 219 PORT_MODE_EXT_EPHY, SYS_PORT_CTRL); 220 break; 221 222 case PHY_INTERFACE_MODE_REVMII: 223 phy_name = "external RvMII"; 224 /* of_mdiobus_register took care of reading the 'max-speed' 225 * PHY property for us, effectively limiting the PHY supported 226 * capabilities, use that knowledge to also configure the 227 * Reverse MII interface correctly. 228 */ 229 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 230 dev->phydev->supported)) 231 port_ctrl = PORT_MODE_EXT_RVMII_50; 232 else 233 port_ctrl = PORT_MODE_EXT_RVMII_25; 234 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL); 235 break; 236 237 case PHY_INTERFACE_MODE_RGMII: 238 /* RGMII_NO_ID: TXC transitions at the same time as TXD 239 * (requires PCB or receiver-side delay) 240 * RGMII: Add 2ns delay on TXC (90 degree shift) 241 * 242 * ID is implicitly disabled for 100Mbps (RG)MII operation. 243 */ 244 id_mode_dis = BIT(16); 245 /* fall through */ 246 case PHY_INTERFACE_MODE_RGMII_TXID: 247 if (id_mode_dis) 248 phy_name = "external RGMII (no delay)"; 249 else 250 phy_name = "external RGMII (TX delay)"; 251 bcmgenet_sys_writel(priv, 252 PORT_MODE_EXT_GPHY, SYS_PORT_CTRL); 253 break; 254 default: 255 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface); 256 return -EINVAL; 257 } 258 259 /* This is an external PHY (xMII), so we need to enable the RGMII 260 * block for the interface to work 261 */ 262 if (priv->ext_phy) { 263 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL); 264 reg |= RGMII_MODE_EN | id_mode_dis; 265 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL); 266 } 267 268 if (init) 269 dev_info(kdev, "configuring instance for %s\n", phy_name); 270 271 return 0; 272 } 273 274 int bcmgenet_mii_probe(struct net_device *dev) 275 { 276 struct bcmgenet_priv *priv = netdev_priv(dev); 277 struct device_node *dn = priv->pdev->dev.of_node; 278 struct phy_device *phydev; 279 u32 phy_flags; 280 int ret; 281 282 /* Communicate the integrated PHY revision */ 283 phy_flags = priv->gphy_rev; 284 285 /* Initialize link state variables that bcmgenet_mii_setup() uses */ 286 priv->old_link = -1; 287 priv->old_speed = -1; 288 priv->old_duplex = -1; 289 priv->old_pause = -1; 290 291 if (dn) { 292 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 293 phy_flags, priv->phy_interface); 294 if (!phydev) { 295 pr_err("could not attach to PHY\n"); 296 return -ENODEV; 297 } 298 } else { 299 phydev = dev->phydev; 300 phydev->dev_flags = phy_flags; 301 302 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup, 303 priv->phy_interface); 304 if (ret) { 305 pr_err("could not attach to PHY\n"); 306 return -ENODEV; 307 } 308 } 309 310 /* Configure port multiplexer based on what the probed PHY device since 311 * reading the 'max-speed' property determines the maximum supported 312 * PHY speed which is needed for bcmgenet_mii_config() to configure 313 * things appropriately. 314 */ 315 ret = bcmgenet_mii_config(dev, true); 316 if (ret) { 317 phy_disconnect(dev->phydev); 318 return ret; 319 } 320 321 linkmode_copy(phydev->advertising, phydev->supported); 322 323 /* The internal PHY has its link interrupts routed to the 324 * Ethernet MAC ISRs. On GENETv5 there is a hardware issue 325 * that prevents the signaling of link UP interrupts when 326 * the link operates at 10Mbps, so fallback to polling for 327 * those versions of GENET. 328 */ 329 if (priv->internal_phy && !GENET_IS_V5(priv)) 330 dev->phydev->irq = PHY_IGNORE_INTERRUPT; 331 332 return 0; 333 } 334 335 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv) 336 { 337 struct device_node *dn = priv->pdev->dev.of_node; 338 struct device *kdev = &priv->pdev->dev; 339 char *compat; 340 341 compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version); 342 if (!compat) 343 return NULL; 344 345 priv->mdio_dn = of_get_compatible_child(dn, compat); 346 kfree(compat); 347 if (!priv->mdio_dn) { 348 dev_err(kdev, "unable to find MDIO bus node\n"); 349 return NULL; 350 } 351 352 return priv->mdio_dn; 353 } 354 355 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv, 356 struct unimac_mdio_pdata *ppd) 357 { 358 struct device *kdev = &priv->pdev->dev; 359 struct bcmgenet_platform_data *pd = kdev->platform_data; 360 361 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 362 /* 363 * Internal or external PHY with MDIO access 364 */ 365 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR) 366 ppd->phy_mask = 1 << pd->phy_address; 367 else 368 ppd->phy_mask = 0; 369 } 370 } 371 372 static int bcmgenet_mii_wait(void *wait_func_data) 373 { 374 struct bcmgenet_priv *priv = wait_func_data; 375 376 wait_event_timeout(priv->wq, 377 !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) 378 & MDIO_START_BUSY), 379 HZ / 100); 380 return 0; 381 } 382 383 static int bcmgenet_mii_register(struct bcmgenet_priv *priv) 384 { 385 struct platform_device *pdev = priv->pdev; 386 struct bcmgenet_platform_data *pdata = pdev->dev.platform_data; 387 struct device_node *dn = pdev->dev.of_node; 388 struct unimac_mdio_pdata ppd; 389 struct platform_device *ppdev; 390 struct resource *pres, res; 391 int id, ret; 392 393 pres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 394 memset(&res, 0, sizeof(res)); 395 memset(&ppd, 0, sizeof(ppd)); 396 397 ppd.wait_func = bcmgenet_mii_wait; 398 ppd.wait_func_data = priv; 399 ppd.bus_name = "bcmgenet MII bus"; 400 401 /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD 402 * and is 2 * 32-bits word long, 8 bytes total. 403 */ 404 res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD; 405 res.end = res.start + 8; 406 res.flags = IORESOURCE_MEM; 407 408 if (dn) 409 id = of_alias_get_id(dn, "eth"); 410 else 411 id = pdev->id; 412 413 ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id); 414 if (!ppdev) 415 return -ENOMEM; 416 417 /* Retain this platform_device pointer for later cleanup */ 418 priv->mii_pdev = ppdev; 419 ppdev->dev.parent = &pdev->dev; 420 ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv); 421 if (pdata) 422 bcmgenet_mii_pdata_init(priv, &ppd); 423 424 ret = platform_device_add_resources(ppdev, &res, 1); 425 if (ret) 426 goto out; 427 428 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd)); 429 if (ret) 430 goto out; 431 432 ret = platform_device_add(ppdev); 433 if (ret) 434 goto out; 435 436 return 0; 437 out: 438 platform_device_put(ppdev); 439 return ret; 440 } 441 442 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv) 443 { 444 struct device_node *dn = priv->pdev->dev.of_node; 445 struct device *kdev = &priv->pdev->dev; 446 struct phy_device *phydev; 447 int phy_mode; 448 int ret; 449 450 /* Fetch the PHY phandle */ 451 priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0); 452 453 /* In the case of a fixed PHY, the DT node associated 454 * to the PHY is the Ethernet MAC DT node. 455 */ 456 if (!priv->phy_dn && of_phy_is_fixed_link(dn)) { 457 ret = of_phy_register_fixed_link(dn); 458 if (ret) 459 return ret; 460 461 priv->phy_dn = of_node_get(dn); 462 } 463 464 /* Get the link mode */ 465 phy_mode = of_get_phy_mode(dn); 466 if (phy_mode < 0) { 467 dev_err(kdev, "invalid PHY mode property\n"); 468 return phy_mode; 469 } 470 471 priv->phy_interface = phy_mode; 472 473 /* We need to specifically look up whether this PHY interface is internal 474 * or not *before* we even try to probe the PHY driver over MDIO as we 475 * may have shut down the internal PHY for power saving purposes. 476 */ 477 if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL) 478 priv->internal_phy = true; 479 480 /* Make sure we initialize MoCA PHYs with a link down */ 481 if (phy_mode == PHY_INTERFACE_MODE_MOCA) { 482 phydev = of_phy_find_device(dn); 483 if (phydev) { 484 phydev->link = 0; 485 put_device(&phydev->mdio.dev); 486 } 487 } 488 489 return 0; 490 } 491 492 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv) 493 { 494 struct device *kdev = &priv->pdev->dev; 495 struct bcmgenet_platform_data *pd = kdev->platform_data; 496 char phy_name[MII_BUS_ID_SIZE + 3]; 497 char mdio_bus_id[MII_BUS_ID_SIZE]; 498 struct phy_device *phydev; 499 500 snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d", 501 UNIMAC_MDIO_DRV_NAME, priv->pdev->id); 502 503 if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) { 504 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, 505 mdio_bus_id, pd->phy_address); 506 507 /* 508 * Internal or external PHY with MDIO access 509 */ 510 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface); 511 if (!phydev) { 512 dev_err(kdev, "failed to register PHY device\n"); 513 return -ENODEV; 514 } 515 } else { 516 /* 517 * MoCA port or no MDIO access. 518 * Use fixed PHY to represent the link layer. 519 */ 520 struct fixed_phy_status fphy_status = { 521 .link = 1, 522 .speed = pd->phy_speed, 523 .duplex = pd->phy_duplex, 524 .pause = 0, 525 .asym_pause = 0, 526 }; 527 528 phydev = fixed_phy_register(PHY_POLL, &fphy_status, NULL); 529 if (!phydev || IS_ERR(phydev)) { 530 dev_err(kdev, "failed to register fixed PHY device\n"); 531 return -ENODEV; 532 } 533 534 /* Make sure we initialize MoCA PHYs with a link down */ 535 phydev->link = 0; 536 537 } 538 539 priv->phy_interface = pd->phy_interface; 540 541 return 0; 542 } 543 544 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv) 545 { 546 struct device_node *dn = priv->pdev->dev.of_node; 547 548 if (dn) 549 return bcmgenet_mii_of_init(priv); 550 else 551 return bcmgenet_mii_pd_init(priv); 552 } 553 554 int bcmgenet_mii_init(struct net_device *dev) 555 { 556 struct bcmgenet_priv *priv = netdev_priv(dev); 557 int ret; 558 559 ret = bcmgenet_mii_register(priv); 560 if (ret) 561 return ret; 562 563 ret = bcmgenet_mii_bus_init(priv); 564 if (ret) 565 goto out; 566 567 return 0; 568 569 out: 570 bcmgenet_mii_exit(dev); 571 return ret; 572 } 573 574 void bcmgenet_mii_exit(struct net_device *dev) 575 { 576 struct bcmgenet_priv *priv = netdev_priv(dev); 577 struct device_node *dn = priv->pdev->dev.of_node; 578 579 if (of_phy_is_fixed_link(dn)) 580 of_phy_deregister_fixed_link(dn); 581 of_node_put(priv->phy_dn); 582 platform_device_unregister(priv->mii_pdev); 583 } 584