1 /*
2  * Copyright (c) 2014-2017 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 
9 #ifndef __BCMGENET_H__
10 #define __BCMGENET_H__
11 
12 #include <linux/skbuff.h>
13 #include <linux/netdevice.h>
14 #include <linux/spinlock.h>
15 #include <linux/clk.h>
16 #include <linux/mii.h>
17 #include <linux/if_vlan.h>
18 #include <linux/phy.h>
19 
20 /* total number of Buffer Descriptors, same for Rx/Tx */
21 #define TOTAL_DESC				256
22 
23 /* which ring is descriptor based */
24 #define DESC_INDEX				16
25 
26 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
27  * 1536 is multiple of 256 bytes
28  */
29 #define ENET_BRCM_TAG_LEN	6
30 #define ENET_PAD		8
31 #define ENET_MAX_MTU_SIZE	(ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
32 				 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
33 #define DMA_MAX_BURST_LENGTH    0x10
34 
35 /* misc. configuration */
36 #define CLEAR_ALL_HFB			0xFF
37 #define DMA_FC_THRESH_HI		(TOTAL_DESC >> 4)
38 #define DMA_FC_THRESH_LO		5
39 
40 /* 64B receive/transmit status block */
41 struct status_64 {
42 	u32	length_status;		/* length and peripheral status */
43 	u32	ext_status;		/* Extended status*/
44 	u32	rx_csum;		/* partial rx checksum */
45 	u32	unused1[9];		/* unused */
46 	u32	tx_csum_info;		/* Tx checksum info. */
47 	u32	unused2[3];		/* unused */
48 };
49 
50 /* Rx status bits */
51 #define STATUS_RX_EXT_MASK		0x1FFFFF
52 #define STATUS_RX_CSUM_MASK		0xFFFF
53 #define STATUS_RX_CSUM_OK		0x10000
54 #define STATUS_RX_CSUM_FR		0x20000
55 #define STATUS_RX_PROTO_TCP		0
56 #define STATUS_RX_PROTO_UDP		1
57 #define STATUS_RX_PROTO_ICMP		2
58 #define STATUS_RX_PROTO_OTHER		3
59 #define STATUS_RX_PROTO_MASK		3
60 #define STATUS_RX_PROTO_SHIFT		18
61 #define STATUS_FILTER_INDEX_MASK	0xFFFF
62 /* Tx status bits */
63 #define STATUS_TX_CSUM_START_MASK	0X7FFF
64 #define STATUS_TX_CSUM_START_SHIFT	16
65 #define STATUS_TX_CSUM_PROTO_UDP	0x8000
66 #define STATUS_TX_CSUM_OFFSET_MASK	0x7FFF
67 #define STATUS_TX_CSUM_LV		0x80000000
68 
69 /* DMA Descriptor */
70 #define DMA_DESC_LENGTH_STATUS	0x00	/* in bytes of data in buffer */
71 #define DMA_DESC_ADDRESS_LO	0x04	/* lower bits of PA */
72 #define DMA_DESC_ADDRESS_HI	0x08	/* upper 32 bits of PA, GENETv4+ */
73 
74 /* Rx/Tx common counter group */
75 struct bcmgenet_pkt_counters {
76 	u32	cnt_64;		/* RO Received/Transmited 64 bytes packet */
77 	u32	cnt_127;	/* RO Rx/Tx 127 bytes packet */
78 	u32	cnt_255;	/* RO Rx/Tx 65-255 bytes packet */
79 	u32	cnt_511;	/* RO Rx/Tx 256-511 bytes packet */
80 	u32	cnt_1023;	/* RO Rx/Tx 512-1023 bytes packet */
81 	u32	cnt_1518;	/* RO Rx/Tx 1024-1518 bytes packet */
82 	u32	cnt_mgv;	/* RO Rx/Tx 1519-1522 good VLAN packet */
83 	u32	cnt_2047;	/* RO Rx/Tx 1522-2047 bytes packet*/
84 	u32	cnt_4095;	/* RO Rx/Tx 2048-4095 bytes packet*/
85 	u32	cnt_9216;	/* RO Rx/Tx 4096-9216 bytes packet*/
86 };
87 
88 /* RSV, Receive Status Vector */
89 struct bcmgenet_rx_counters {
90 	struct  bcmgenet_pkt_counters pkt_cnt;
91 	u32	pkt;		/* RO (0x428) Received pkt count*/
92 	u32	bytes;		/* RO Received byte count */
93 	u32	mca;		/* RO # of Received multicast pkt */
94 	u32	bca;		/* RO # of Receive broadcast pkt */
95 	u32	fcs;		/* RO # of Received FCS error  */
96 	u32	cf;		/* RO # of Received control frame pkt*/
97 	u32	pf;		/* RO # of Received pause frame pkt */
98 	u32	uo;		/* RO # of unknown op code pkt */
99 	u32	aln;		/* RO # of alignment error count */
100 	u32	flr;		/* RO # of frame length out of range count */
101 	u32	cde;		/* RO # of code error pkt */
102 	u32	fcr;		/* RO # of carrier sense error pkt */
103 	u32	ovr;		/* RO # of oversize pkt*/
104 	u32	jbr;		/* RO # of jabber count */
105 	u32	mtue;		/* RO # of MTU error pkt*/
106 	u32	pok;		/* RO # of Received good pkt */
107 	u32	uc;		/* RO # of unicast pkt */
108 	u32	ppp;		/* RO # of PPP pkt */
109 	u32	rcrc;		/* RO (0x470),# of CRC match pkt */
110 };
111 
112 /* TSV, Transmit Status Vector */
113 struct bcmgenet_tx_counters {
114 	struct bcmgenet_pkt_counters pkt_cnt;
115 	u32	pkts;		/* RO (0x4a8) Transmited pkt */
116 	u32	mca;		/* RO # of xmited multicast pkt */
117 	u32	bca;		/* RO # of xmited broadcast pkt */
118 	u32	pf;		/* RO # of xmited pause frame count */
119 	u32	cf;		/* RO # of xmited control frame count */
120 	u32	fcs;		/* RO # of xmited FCS error count */
121 	u32	ovr;		/* RO # of xmited oversize pkt */
122 	u32	drf;		/* RO # of xmited deferral pkt */
123 	u32	edf;		/* RO # of xmited Excessive deferral pkt*/
124 	u32	scl;		/* RO # of xmited single collision pkt */
125 	u32	mcl;		/* RO # of xmited multiple collision pkt*/
126 	u32	lcl;		/* RO # of xmited late collision pkt */
127 	u32	ecl;		/* RO # of xmited excessive collision pkt*/
128 	u32	frg;		/* RO # of xmited fragments pkt*/
129 	u32	ncl;		/* RO # of xmited total collision count */
130 	u32	jbr;		/* RO # of xmited jabber count*/
131 	u32	bytes;		/* RO # of xmited byte count */
132 	u32	pok;		/* RO # of xmited good pkt */
133 	u32	uc;		/* RO (0x0x4f0)# of xmited unitcast pkt */
134 };
135 
136 struct bcmgenet_mib_counters {
137 	struct bcmgenet_rx_counters rx;
138 	struct bcmgenet_tx_counters tx;
139 	u32	rx_runt_cnt;
140 	u32	rx_runt_fcs;
141 	u32	rx_runt_fcs_align;
142 	u32	rx_runt_bytes;
143 	u32	rbuf_ovflow_cnt;
144 	u32	rbuf_err_cnt;
145 	u32	mdf_err_cnt;
146 	u32	alloc_rx_buff_failed;
147 	u32	rx_dma_failed;
148 	u32	tx_dma_failed;
149 };
150 
151 #define UMAC_HD_BKP_CTRL		0x004
152 #define	 HD_FC_EN			(1 << 0)
153 #define  HD_FC_BKOFF_OK			(1 << 1)
154 #define  IPG_CONFIG_RX_SHIFT		2
155 #define  IPG_CONFIG_RX_MASK		0x1F
156 
157 #define UMAC_CMD			0x008
158 #define  CMD_TX_EN			(1 << 0)
159 #define  CMD_RX_EN			(1 << 1)
160 #define  UMAC_SPEED_10			0
161 #define  UMAC_SPEED_100			1
162 #define  UMAC_SPEED_1000		2
163 #define  UMAC_SPEED_2500		3
164 #define  CMD_SPEED_SHIFT		2
165 #define  CMD_SPEED_MASK			3
166 #define  CMD_PROMISC			(1 << 4)
167 #define  CMD_PAD_EN			(1 << 5)
168 #define  CMD_CRC_FWD			(1 << 6)
169 #define  CMD_PAUSE_FWD			(1 << 7)
170 #define  CMD_RX_PAUSE_IGNORE		(1 << 8)
171 #define  CMD_TX_ADDR_INS		(1 << 9)
172 #define  CMD_HD_EN			(1 << 10)
173 #define  CMD_SW_RESET			(1 << 13)
174 #define  CMD_LCL_LOOP_EN		(1 << 15)
175 #define  CMD_AUTO_CONFIG		(1 << 22)
176 #define  CMD_CNTL_FRM_EN		(1 << 23)
177 #define  CMD_NO_LEN_CHK			(1 << 24)
178 #define  CMD_RMT_LOOP_EN		(1 << 25)
179 #define  CMD_PRBL_EN			(1 << 27)
180 #define  CMD_TX_PAUSE_IGNORE		(1 << 28)
181 #define  CMD_TX_RX_EN			(1 << 29)
182 #define  CMD_RUNT_FILTER_DIS		(1 << 30)
183 
184 #define UMAC_MAC0			0x00C
185 #define UMAC_MAC1			0x010
186 #define UMAC_MAX_FRAME_LEN		0x014
187 
188 #define UMAC_EEE_CTRL			0x064
189 #define  EN_LPI_RX_PAUSE		(1 << 0)
190 #define  EN_LPI_TX_PFC			(1 << 1)
191 #define  EN_LPI_TX_PAUSE		(1 << 2)
192 #define  EEE_EN				(1 << 3)
193 #define  RX_FIFO_CHECK			(1 << 4)
194 #define  EEE_TX_CLK_DIS			(1 << 5)
195 #define  DIS_EEE_10M			(1 << 6)
196 #define  LP_IDLE_PREDICTION_MODE	(1 << 7)
197 
198 #define UMAC_EEE_LPI_TIMER		0x068
199 #define UMAC_EEE_WAKE_TIMER		0x06C
200 #define UMAC_EEE_REF_COUNT		0x070
201 #define  EEE_REFERENCE_COUNT_MASK	0xffff
202 
203 #define UMAC_TX_FLUSH			0x334
204 
205 #define UMAC_MIB_START			0x400
206 
207 #define UMAC_MDIO_CMD			0x614
208 #define  MDIO_START_BUSY		(1 << 29)
209 #define  MDIO_READ_FAIL			(1 << 28)
210 #define  MDIO_RD			(2 << 26)
211 #define  MDIO_WR			(1 << 26)
212 #define  MDIO_PMD_SHIFT			21
213 #define  MDIO_PMD_MASK			0x1F
214 #define  MDIO_REG_SHIFT			16
215 #define  MDIO_REG_MASK			0x1F
216 
217 #define UMAC_RBUF_OVFL_CNT_V1		0x61C
218 #define RBUF_OVFL_CNT_V2		0x80
219 #define RBUF_OVFL_CNT_V3PLUS		0x94
220 
221 #define UMAC_MPD_CTRL			0x620
222 #define  MPD_EN				(1 << 0)
223 #define  MPD_PW_EN			(1 << 27)
224 #define  MPD_MSEQ_LEN_SHIFT		16
225 #define  MPD_MSEQ_LEN_MASK		0xFF
226 
227 #define UMAC_MPD_PW_MS			0x624
228 #define UMAC_MPD_PW_LS			0x628
229 #define UMAC_RBUF_ERR_CNT_V1		0x634
230 #define RBUF_ERR_CNT_V2			0x84
231 #define RBUF_ERR_CNT_V3PLUS		0x98
232 #define UMAC_MDF_ERR_CNT		0x638
233 #define UMAC_MDF_CTRL			0x650
234 #define UMAC_MDF_ADDR			0x654
235 #define UMAC_MIB_CTRL			0x580
236 #define  MIB_RESET_RX			(1 << 0)
237 #define  MIB_RESET_RUNT			(1 << 1)
238 #define  MIB_RESET_TX			(1 << 2)
239 
240 #define RBUF_CTRL			0x00
241 #define  RBUF_64B_EN			(1 << 0)
242 #define  RBUF_ALIGN_2B			(1 << 1)
243 #define  RBUF_BAD_DIS			(1 << 2)
244 
245 #define RBUF_STATUS			0x0C
246 #define  RBUF_STATUS_WOL		(1 << 0)
247 #define  RBUF_STATUS_MPD_INTR_ACTIVE	(1 << 1)
248 #define  RBUF_STATUS_ACPI_INTR_ACTIVE	(1 << 2)
249 
250 #define RBUF_CHK_CTRL			0x14
251 #define  RBUF_RXCHK_EN			(1 << 0)
252 #define  RBUF_SKIP_FCS			(1 << 4)
253 
254 #define RBUF_ENERGY_CTRL		0x9c
255 #define  RBUF_EEE_EN			(1 << 0)
256 #define  RBUF_PM_EN			(1 << 1)
257 
258 #define RBUF_TBUF_SIZE_CTRL		0xb4
259 
260 #define RBUF_HFB_CTRL_V1		0x38
261 #define  RBUF_HFB_FILTER_EN_SHIFT	16
262 #define  RBUF_HFB_FILTER_EN_MASK	0xffff0000
263 #define  RBUF_HFB_EN			(1 << 0)
264 #define  RBUF_HFB_256B			(1 << 1)
265 #define  RBUF_ACPI_EN			(1 << 2)
266 
267 #define RBUF_HFB_LEN_V1			0x3C
268 #define  RBUF_FLTR_LEN_MASK		0xFF
269 #define  RBUF_FLTR_LEN_SHIFT		8
270 
271 #define TBUF_CTRL			0x00
272 #define TBUF_BP_MC			0x0C
273 #define TBUF_ENERGY_CTRL		0x14
274 #define  TBUF_EEE_EN			(1 << 0)
275 #define  TBUF_PM_EN			(1 << 1)
276 
277 #define TBUF_CTRL_V1			0x80
278 #define TBUF_BP_MC_V1			0xA0
279 
280 #define HFB_CTRL			0x00
281 #define HFB_FLT_ENABLE_V3PLUS		0x04
282 #define HFB_FLT_LEN_V2			0x04
283 #define HFB_FLT_LEN_V3PLUS		0x1C
284 
285 /* uniMac intrl2 registers */
286 #define INTRL2_CPU_STAT			0x00
287 #define INTRL2_CPU_SET			0x04
288 #define INTRL2_CPU_CLEAR		0x08
289 #define INTRL2_CPU_MASK_STATUS		0x0C
290 #define INTRL2_CPU_MASK_SET		0x10
291 #define INTRL2_CPU_MASK_CLEAR		0x14
292 
293 /* INTRL2 instance 0 definitions */
294 #define UMAC_IRQ_SCB			(1 << 0)
295 #define UMAC_IRQ_EPHY			(1 << 1)
296 #define UMAC_IRQ_PHY_DET_R		(1 << 2)
297 #define UMAC_IRQ_PHY_DET_F		(1 << 3)
298 #define UMAC_IRQ_LINK_UP		(1 << 4)
299 #define UMAC_IRQ_LINK_DOWN		(1 << 5)
300 #define UMAC_IRQ_LINK_EVENT		(UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
301 #define UMAC_IRQ_UMAC			(1 << 6)
302 #define UMAC_IRQ_UMAC_TSV		(1 << 7)
303 #define UMAC_IRQ_TBUF_UNDERRUN		(1 << 8)
304 #define UMAC_IRQ_RBUF_OVERFLOW		(1 << 9)
305 #define UMAC_IRQ_HFB_SM			(1 << 10)
306 #define UMAC_IRQ_HFB_MM			(1 << 11)
307 #define UMAC_IRQ_MPD_R			(1 << 12)
308 #define UMAC_IRQ_RXDMA_MBDONE		(1 << 13)
309 #define UMAC_IRQ_RXDMA_PDONE		(1 << 14)
310 #define UMAC_IRQ_RXDMA_BDONE		(1 << 15)
311 #define UMAC_IRQ_RXDMA_DONE		UMAC_IRQ_RXDMA_MBDONE
312 #define UMAC_IRQ_TXDMA_MBDONE		(1 << 16)
313 #define UMAC_IRQ_TXDMA_PDONE		(1 << 17)
314 #define UMAC_IRQ_TXDMA_BDONE		(1 << 18)
315 #define UMAC_IRQ_TXDMA_DONE		UMAC_IRQ_TXDMA_MBDONE
316 
317 /* Only valid for GENETv3+ */
318 #define UMAC_IRQ_MDIO_DONE		(1 << 23)
319 #define UMAC_IRQ_MDIO_ERROR		(1 << 24)
320 
321 /* INTRL2 instance 1 definitions */
322 #define UMAC_IRQ1_TX_INTR_MASK		0xFFFF
323 #define UMAC_IRQ1_RX_INTR_MASK		0xFFFF
324 #define UMAC_IRQ1_RX_INTR_SHIFT		16
325 
326 /* Register block offsets */
327 #define GENET_SYS_OFF			0x0000
328 #define GENET_GR_BRIDGE_OFF		0x0040
329 #define GENET_EXT_OFF			0x0080
330 #define GENET_INTRL2_0_OFF		0x0200
331 #define GENET_INTRL2_1_OFF		0x0240
332 #define GENET_RBUF_OFF			0x0300
333 #define GENET_UMAC_OFF			0x0800
334 
335 /* SYS block offsets and register definitions */
336 #define SYS_REV_CTRL			0x00
337 #define SYS_PORT_CTRL			0x04
338 #define  PORT_MODE_INT_EPHY		0
339 #define  PORT_MODE_INT_GPHY		1
340 #define  PORT_MODE_EXT_EPHY		2
341 #define  PORT_MODE_EXT_GPHY		3
342 #define  PORT_MODE_EXT_RVMII_25		(4 | BIT(4))
343 #define  PORT_MODE_EXT_RVMII_50		4
344 #define  LED_ACT_SOURCE_MAC		(1 << 9)
345 
346 #define SYS_RBUF_FLUSH_CTRL		0x08
347 #define SYS_TBUF_FLUSH_CTRL		0x0C
348 #define RBUF_FLUSH_CTRL_V1		0x04
349 
350 /* Ext block register offsets and definitions */
351 #define EXT_EXT_PWR_MGMT		0x00
352 #define  EXT_PWR_DOWN_BIAS		(1 << 0)
353 #define  EXT_PWR_DOWN_DLL		(1 << 1)
354 #define  EXT_PWR_DOWN_PHY		(1 << 2)
355 #define  EXT_PWR_DN_EN_LD		(1 << 3)
356 #define  EXT_ENERGY_DET			(1 << 4)
357 #define  EXT_IDDQ_FROM_PHY		(1 << 5)
358 #define  EXT_IDDQ_GLBL_PWR		(1 << 7)
359 #define  EXT_PHY_RESET			(1 << 8)
360 #define  EXT_ENERGY_DET_MASK		(1 << 12)
361 #define  EXT_PWR_DOWN_PHY_TX		(1 << 16)
362 #define  EXT_PWR_DOWN_PHY_RX		(1 << 17)
363 #define  EXT_PWR_DOWN_PHY_SD		(1 << 18)
364 #define  EXT_PWR_DOWN_PHY_RD		(1 << 19)
365 #define  EXT_PWR_DOWN_PHY_EN		(1 << 20)
366 
367 #define EXT_RGMII_OOB_CTRL		0x0C
368 #define  RGMII_LINK			(1 << 4)
369 #define  OOB_DISABLE			(1 << 5)
370 #define  RGMII_MODE_EN			(1 << 6)
371 #define  ID_MODE_DIS			(1 << 16)
372 
373 #define EXT_GPHY_CTRL			0x1C
374 #define  EXT_CFG_IDDQ_BIAS		(1 << 0)
375 #define  EXT_CFG_PWR_DOWN		(1 << 1)
376 #define  EXT_CK25_DIS			(1 << 4)
377 #define  EXT_GPHY_RESET			(1 << 5)
378 
379 /* DMA rings size */
380 #define DMA_RING_SIZE			(0x40)
381 #define DMA_RINGS_SIZE			(DMA_RING_SIZE * (DESC_INDEX + 1))
382 
383 /* DMA registers common definitions */
384 #define DMA_RW_POINTER_MASK		0x1FF
385 #define DMA_P_INDEX_DISCARD_CNT_MASK	0xFFFF
386 #define DMA_P_INDEX_DISCARD_CNT_SHIFT	16
387 #define DMA_BUFFER_DONE_CNT_MASK	0xFFFF
388 #define DMA_BUFFER_DONE_CNT_SHIFT	16
389 #define DMA_P_INDEX_MASK		0xFFFF
390 #define DMA_C_INDEX_MASK		0xFFFF
391 
392 /* DMA ring size register */
393 #define DMA_RING_SIZE_MASK		0xFFFF
394 #define DMA_RING_SIZE_SHIFT		16
395 #define DMA_RING_BUFFER_SIZE_MASK	0xFFFF
396 
397 /* DMA interrupt threshold register */
398 #define DMA_INTR_THRESHOLD_MASK		0x01FF
399 
400 /* DMA XON/XOFF register */
401 #define DMA_XON_THREHOLD_MASK		0xFFFF
402 #define DMA_XOFF_THRESHOLD_MASK		0xFFFF
403 #define DMA_XOFF_THRESHOLD_SHIFT	16
404 
405 /* DMA flow period register */
406 #define DMA_FLOW_PERIOD_MASK		0xFFFF
407 #define DMA_MAX_PKT_SIZE_MASK		0xFFFF
408 #define DMA_MAX_PKT_SIZE_SHIFT		16
409 
410 
411 /* DMA control register */
412 #define DMA_EN				(1 << 0)
413 #define DMA_RING_BUF_EN_SHIFT		0x01
414 #define DMA_RING_BUF_EN_MASK		0xFFFF
415 #define DMA_TSB_SWAP_EN			(1 << 20)
416 
417 /* DMA status register */
418 #define DMA_DISABLED			(1 << 0)
419 #define DMA_DESC_RAM_INIT_BUSY		(1 << 1)
420 
421 /* DMA SCB burst size register */
422 #define DMA_SCB_BURST_SIZE_MASK		0x1F
423 
424 /* DMA activity vector register */
425 #define DMA_ACTIVITY_VECTOR_MASK	0x1FFFF
426 
427 /* DMA backpressure mask register */
428 #define DMA_BACKPRESSURE_MASK		0x1FFFF
429 #define DMA_PFC_ENABLE			(1 << 31)
430 
431 /* DMA backpressure status register */
432 #define DMA_BACKPRESSURE_STATUS_MASK	0x1FFFF
433 
434 /* DMA override register */
435 #define DMA_LITTLE_ENDIAN_MODE		(1 << 0)
436 #define DMA_REGISTER_MODE		(1 << 1)
437 
438 /* DMA timeout register */
439 #define DMA_TIMEOUT_MASK		0xFFFF
440 #define DMA_TIMEOUT_VAL			5000	/* micro seconds */
441 
442 /* TDMA rate limiting control register */
443 #define DMA_RATE_LIMIT_EN_MASK		0xFFFF
444 
445 /* TDMA arbitration control register */
446 #define DMA_ARBITER_MODE_MASK		0x03
447 #define DMA_RING_BUF_PRIORITY_MASK	0x1F
448 #define DMA_RING_BUF_PRIORITY_SHIFT	5
449 #define DMA_PRIO_REG_INDEX(q)		((q) / 6)
450 #define DMA_PRIO_REG_SHIFT(q)		(((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
451 #define DMA_RATE_ADJ_MASK		0xFF
452 
453 /* Tx/Rx Dma Descriptor common bits*/
454 #define DMA_BUFLENGTH_MASK		0x0fff
455 #define DMA_BUFLENGTH_SHIFT		16
456 #define DMA_OWN				0x8000
457 #define DMA_EOP				0x4000
458 #define DMA_SOP				0x2000
459 #define DMA_WRAP			0x1000
460 /* Tx specific Dma descriptor bits */
461 #define DMA_TX_UNDERRUN			0x0200
462 #define DMA_TX_APPEND_CRC		0x0040
463 #define DMA_TX_OW_CRC			0x0020
464 #define DMA_TX_DO_CSUM			0x0010
465 #define DMA_TX_QTAG_SHIFT		7
466 
467 /* Rx Specific Dma descriptor bits */
468 #define DMA_RX_CHK_V3PLUS		0x8000
469 #define DMA_RX_CHK_V12			0x1000
470 #define DMA_RX_BRDCAST			0x0040
471 #define DMA_RX_MULT			0x0020
472 #define DMA_RX_LG			0x0010
473 #define DMA_RX_NO			0x0008
474 #define DMA_RX_RXER			0x0004
475 #define DMA_RX_CRC_ERROR		0x0002
476 #define DMA_RX_OV			0x0001
477 #define DMA_RX_FI_MASK			0x001F
478 #define DMA_RX_FI_SHIFT			0x0007
479 #define DMA_DESC_ALLOC_MASK		0x00FF
480 
481 #define DMA_ARBITER_RR			0x00
482 #define DMA_ARBITER_WRR			0x01
483 #define DMA_ARBITER_SP			0x02
484 
485 struct enet_cb {
486 	struct sk_buff      *skb;
487 	void __iomem *bd_addr;
488 	DEFINE_DMA_UNMAP_ADDR(dma_addr);
489 	DEFINE_DMA_UNMAP_LEN(dma_len);
490 };
491 
492 /* power management mode */
493 enum bcmgenet_power_mode {
494 	GENET_POWER_CABLE_SENSE = 0,
495 	GENET_POWER_PASSIVE,
496 	GENET_POWER_WOL_MAGIC,
497 };
498 
499 struct bcmgenet_priv;
500 
501 /* We support both runtime GENET detection and compile-time
502  * to optimize code-paths for a given hardware
503  */
504 enum bcmgenet_version {
505 	GENET_V1 = 1,
506 	GENET_V2,
507 	GENET_V3,
508 	GENET_V4,
509 	GENET_V5
510 };
511 
512 #define GENET_IS_V1(p)	((p)->version == GENET_V1)
513 #define GENET_IS_V2(p)	((p)->version == GENET_V2)
514 #define GENET_IS_V3(p)	((p)->version == GENET_V3)
515 #define GENET_IS_V4(p)	((p)->version == GENET_V4)
516 #define GENET_IS_V5(p)	((p)->version == GENET_V5)
517 
518 /* Hardware flags */
519 #define GENET_HAS_40BITS	(1 << 0)
520 #define GENET_HAS_EXT		(1 << 1)
521 #define GENET_HAS_MDIO_INTR	(1 << 2)
522 #define GENET_HAS_MOCA_LINK_DET	(1 << 3)
523 
524 /* BCMGENET hardware parameters, keep this structure nicely aligned
525  * since it is going to be used in hot paths
526  */
527 struct bcmgenet_hw_params {
528 	u8		tx_queues;
529 	u8		tx_bds_per_q;
530 	u8		rx_queues;
531 	u8		rx_bds_per_q;
532 	u8		bp_in_en_shift;
533 	u32		bp_in_mask;
534 	u8		hfb_filter_cnt;
535 	u8		hfb_filter_size;
536 	u8		qtag_mask;
537 	u16		tbuf_offset;
538 	u32		hfb_offset;
539 	u32		hfb_reg_offset;
540 	u32		rdma_offset;
541 	u32		tdma_offset;
542 	u32		words_per_bd;
543 	u32		flags;
544 };
545 
546 struct bcmgenet_skb_cb {
547 	struct enet_cb *first_cb;	/* First control block of SKB */
548 	struct enet_cb *last_cb;	/* Last control block of SKB */
549 	unsigned int bytes_sent;	/* bytes on the wire (no TSB) */
550 };
551 
552 #define GENET_CB(skb)	((struct bcmgenet_skb_cb *)((skb)->cb))
553 
554 struct bcmgenet_tx_ring {
555 	spinlock_t	lock;		/* ring lock */
556 	struct napi_struct napi;	/* NAPI per tx queue */
557 	unsigned long	packets;
558 	unsigned long	bytes;
559 	unsigned int	index;		/* ring index */
560 	unsigned int	queue;		/* queue index */
561 	struct enet_cb	*cbs;		/* tx ring buffer control block*/
562 	unsigned int	size;		/* size of each tx ring */
563 	unsigned int    clean_ptr;      /* Tx ring clean pointer */
564 	unsigned int	c_index;	/* last consumer index of each ring*/
565 	unsigned int	free_bds;	/* # of free bds for each ring */
566 	unsigned int	write_ptr;	/* Tx ring write pointer SW copy */
567 	unsigned int	prod_index;	/* Tx ring producer index SW copy */
568 	unsigned int	cb_ptr;		/* Tx ring initial CB ptr */
569 	unsigned int	end_ptr;	/* Tx ring end CB ptr */
570 	void (*int_enable)(struct bcmgenet_tx_ring *);
571 	void (*int_disable)(struct bcmgenet_tx_ring *);
572 	struct bcmgenet_priv *priv;
573 };
574 
575 struct bcmgenet_rx_ring {
576 	struct napi_struct napi;	/* Rx NAPI struct */
577 	unsigned long	bytes;
578 	unsigned long	packets;
579 	unsigned long	errors;
580 	unsigned long	dropped;
581 	unsigned int	index;		/* Rx ring index */
582 	struct enet_cb	*cbs;		/* Rx ring buffer control block */
583 	unsigned int	size;		/* Rx ring size */
584 	unsigned int	c_index;	/* Rx last consumer index */
585 	unsigned int	read_ptr;	/* Rx ring read pointer */
586 	unsigned int	cb_ptr;		/* Rx ring initial CB ptr */
587 	unsigned int	end_ptr;	/* Rx ring end CB ptr */
588 	unsigned int	old_discards;
589 	void (*int_enable)(struct bcmgenet_rx_ring *);
590 	void (*int_disable)(struct bcmgenet_rx_ring *);
591 	struct bcmgenet_priv *priv;
592 };
593 
594 /* device context */
595 struct bcmgenet_priv {
596 	void __iomem *base;
597 	enum bcmgenet_version version;
598 	struct net_device *dev;
599 
600 	/* transmit variables */
601 	void __iomem *tx_bds;
602 	struct enet_cb *tx_cbs;
603 	unsigned int num_tx_bds;
604 
605 	struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1];
606 
607 	/* receive variables */
608 	void __iomem *rx_bds;
609 	struct enet_cb *rx_cbs;
610 	unsigned int num_rx_bds;
611 	unsigned int rx_buf_len;
612 
613 	struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1];
614 
615 	/* other misc variables */
616 	struct bcmgenet_hw_params *hw_params;
617 
618 	/* MDIO bus variables */
619 	wait_queue_head_t wq;
620 	struct phy_device *phydev;
621 	bool internal_phy;
622 	struct device_node *phy_dn;
623 	struct device_node *mdio_dn;
624 	struct mii_bus *mii_bus;
625 	u16 gphy_rev;
626 	struct clk *clk_eee;
627 	bool clk_eee_enabled;
628 
629 	/* PHY device variables */
630 	int old_link;
631 	int old_speed;
632 	int old_duplex;
633 	int old_pause;
634 	phy_interface_t phy_interface;
635 	int phy_addr;
636 	int ext_phy;
637 
638 	/* Interrupt variables */
639 	struct work_struct bcmgenet_irq_work;
640 	int irq0;
641 	int irq1;
642 	int wol_irq;
643 	bool wol_irq_disabled;
644 
645 	/* shared status */
646 	spinlock_t lock;
647 	unsigned int irq0_stat;
648 
649 	/* HW descriptors/checksum variables */
650 	bool desc_64b_en;
651 	bool desc_rxchk_en;
652 	bool crc_fwd_en;
653 
654 	unsigned int dma_rx_chk_bit;
655 
656 	u32 msg_enable;
657 
658 	struct clk *clk;
659 	struct platform_device *pdev;
660 
661 	/* WOL */
662 	struct clk *clk_wol;
663 	u32 wolopts;
664 
665 	struct bcmgenet_mib_counters mib;
666 
667 	struct ethtool_eee eee;
668 };
669 
670 #define GENET_IO_MACRO(name, offset)					\
671 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv,	\
672 					u32 off)			\
673 {									\
674 	return __raw_readl(priv->base + offset + off);			\
675 }									\
676 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv,	\
677 					u32 val, u32 off)		\
678 {									\
679 	__raw_writel(val, priv->base + offset + off);			\
680 }
681 
682 GENET_IO_MACRO(ext, GENET_EXT_OFF);
683 GENET_IO_MACRO(umac, GENET_UMAC_OFF);
684 GENET_IO_MACRO(sys, GENET_SYS_OFF);
685 
686 /* interrupt l2 registers accessors */
687 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
688 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
689 
690 /* HFB register accessors  */
691 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
692 
693 /* GENET v2+ HFB control and filter len helpers */
694 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
695 
696 /* RBUF register accessors */
697 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
698 
699 /* MDIO routines */
700 int bcmgenet_mii_init(struct net_device *dev);
701 int bcmgenet_mii_config(struct net_device *dev);
702 int bcmgenet_mii_probe(struct net_device *dev);
703 void bcmgenet_mii_exit(struct net_device *dev);
704 void bcmgenet_mii_reset(struct net_device *dev);
705 void bcmgenet_phy_power_set(struct net_device *dev, bool enable);
706 void bcmgenet_mii_setup(struct net_device *dev);
707 
708 /* Wake-on-LAN routines */
709 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
710 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
711 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
712 				enum bcmgenet_power_mode mode);
713 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
714 			       enum bcmgenet_power_mode mode);
715 
716 #endif /* __BCMGENET_H__ */
717