1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b4af9a55SFlorian Fainelli /* 342138085SDoug Berger * Copyright (c) 2014-2017 Broadcom 4b4af9a55SFlorian Fainelli */ 55e811b39SFlorian Fainelli 6b4af9a55SFlorian Fainelli #ifndef __BCMGENET_H__ 7b4af9a55SFlorian Fainelli #define __BCMGENET_H__ 8b4af9a55SFlorian Fainelli 9b4af9a55SFlorian Fainelli #include <linux/skbuff.h> 10b4af9a55SFlorian Fainelli #include <linux/netdevice.h> 11b4af9a55SFlorian Fainelli #include <linux/spinlock.h> 12b4af9a55SFlorian Fainelli #include <linux/clk.h> 13b4af9a55SFlorian Fainelli #include <linux/mii.h> 14b4af9a55SFlorian Fainelli #include <linux/if_vlan.h> 15b4af9a55SFlorian Fainelli #include <linux/phy.h> 164f75da36STal Gilboa #include <linux/dim.h> 17b4af9a55SFlorian Fainelli 18b4af9a55SFlorian Fainelli /* total number of Buffer Descriptors, same for Rx/Tx */ 19b4af9a55SFlorian Fainelli #define TOTAL_DESC 256 20b4af9a55SFlorian Fainelli 21b4af9a55SFlorian Fainelli /* which ring is descriptor based */ 22b4af9a55SFlorian Fainelli #define DESC_INDEX 16 23b4af9a55SFlorian Fainelli 24b4af9a55SFlorian Fainelli /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 25b4af9a55SFlorian Fainelli * 1536 is multiple of 256 bytes 26b4af9a55SFlorian Fainelli */ 27b4af9a55SFlorian Fainelli #define ENET_BRCM_TAG_LEN 6 28b4af9a55SFlorian Fainelli #define ENET_PAD 8 29b4af9a55SFlorian Fainelli #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 30b4af9a55SFlorian Fainelli ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 31b4af9a55SFlorian Fainelli #define DMA_MAX_BURST_LENGTH 0x10 32b4af9a55SFlorian Fainelli 33b4af9a55SFlorian Fainelli /* misc. configuration */ 34b4af9a55SFlorian Fainelli #define CLEAR_ALL_HFB 0xFF 35b4af9a55SFlorian Fainelli #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 36b4af9a55SFlorian Fainelli #define DMA_FC_THRESH_LO 5 37b4af9a55SFlorian Fainelli 38b4af9a55SFlorian Fainelli /* 64B receive/transmit status block */ 39b4af9a55SFlorian Fainelli struct status_64 { 40b4af9a55SFlorian Fainelli u32 length_status; /* length and peripheral status */ 41b4af9a55SFlorian Fainelli u32 ext_status; /* Extended status*/ 42b4af9a55SFlorian Fainelli u32 rx_csum; /* partial rx checksum */ 43b4af9a55SFlorian Fainelli u32 unused1[9]; /* unused */ 44b4af9a55SFlorian Fainelli u32 tx_csum_info; /* Tx checksum info. */ 45b4af9a55SFlorian Fainelli u32 unused2[3]; /* unused */ 46b4af9a55SFlorian Fainelli }; 47b4af9a55SFlorian Fainelli 48b4af9a55SFlorian Fainelli /* Rx status bits */ 49b4af9a55SFlorian Fainelli #define STATUS_RX_EXT_MASK 0x1FFFFF 50b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_MASK 0xFFFF 51b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_OK 0x10000 52b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_FR 0x20000 53b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_TCP 0 54b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_UDP 1 55b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_ICMP 2 56b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_OTHER 3 57b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_MASK 3 58b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_SHIFT 18 59b4af9a55SFlorian Fainelli #define STATUS_FILTER_INDEX_MASK 0xFFFF 60b4af9a55SFlorian Fainelli /* Tx status bits */ 61b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_START_MASK 0X7FFF 62b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_START_SHIFT 16 63b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_PROTO_UDP 0x8000 64b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 65b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_LV 0x80000000 66b4af9a55SFlorian Fainelli 67b4af9a55SFlorian Fainelli /* DMA Descriptor */ 68b4af9a55SFlorian Fainelli #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 69b4af9a55SFlorian Fainelli #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 70b4af9a55SFlorian Fainelli #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 71b4af9a55SFlorian Fainelli 72b4af9a55SFlorian Fainelli /* Rx/Tx common counter group */ 73b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters { 74b4af9a55SFlorian Fainelli u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 75b4af9a55SFlorian Fainelli u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 76b4af9a55SFlorian Fainelli u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 77b4af9a55SFlorian Fainelli u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 78b4af9a55SFlorian Fainelli u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 79b4af9a55SFlorian Fainelli u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 80b4af9a55SFlorian Fainelli u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 81b4af9a55SFlorian Fainelli u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 82b4af9a55SFlorian Fainelli u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 83b4af9a55SFlorian Fainelli u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 84b4af9a55SFlorian Fainelli }; 85b4af9a55SFlorian Fainelli 86b4af9a55SFlorian Fainelli /* RSV, Receive Status Vector */ 87b4af9a55SFlorian Fainelli struct bcmgenet_rx_counters { 88b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters pkt_cnt; 89b4af9a55SFlorian Fainelli u32 pkt; /* RO (0x428) Received pkt count*/ 90b4af9a55SFlorian Fainelli u32 bytes; /* RO Received byte count */ 91b4af9a55SFlorian Fainelli u32 mca; /* RO # of Received multicast pkt */ 92b4af9a55SFlorian Fainelli u32 bca; /* RO # of Receive broadcast pkt */ 93b4af9a55SFlorian Fainelli u32 fcs; /* RO # of Received FCS error */ 94b4af9a55SFlorian Fainelli u32 cf; /* RO # of Received control frame pkt*/ 95b4af9a55SFlorian Fainelli u32 pf; /* RO # of Received pause frame pkt */ 96b4af9a55SFlorian Fainelli u32 uo; /* RO # of unknown op code pkt */ 97b4af9a55SFlorian Fainelli u32 aln; /* RO # of alignment error count */ 98b4af9a55SFlorian Fainelli u32 flr; /* RO # of frame length out of range count */ 99b4af9a55SFlorian Fainelli u32 cde; /* RO # of code error pkt */ 100b4af9a55SFlorian Fainelli u32 fcr; /* RO # of carrier sense error pkt */ 101b4af9a55SFlorian Fainelli u32 ovr; /* RO # of oversize pkt*/ 102b4af9a55SFlorian Fainelli u32 jbr; /* RO # of jabber count */ 103b4af9a55SFlorian Fainelli u32 mtue; /* RO # of MTU error pkt*/ 104b4af9a55SFlorian Fainelli u32 pok; /* RO # of Received good pkt */ 105b4af9a55SFlorian Fainelli u32 uc; /* RO # of unicast pkt */ 106b4af9a55SFlorian Fainelli u32 ppp; /* RO # of PPP pkt */ 107b4af9a55SFlorian Fainelli u32 rcrc; /* RO (0x470),# of CRC match pkt */ 108b4af9a55SFlorian Fainelli }; 109b4af9a55SFlorian Fainelli 110b4af9a55SFlorian Fainelli /* TSV, Transmit Status Vector */ 111b4af9a55SFlorian Fainelli struct bcmgenet_tx_counters { 112b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters pkt_cnt; 113b4af9a55SFlorian Fainelli u32 pkts; /* RO (0x4a8) Transmited pkt */ 114b4af9a55SFlorian Fainelli u32 mca; /* RO # of xmited multicast pkt */ 115b4af9a55SFlorian Fainelli u32 bca; /* RO # of xmited broadcast pkt */ 116b4af9a55SFlorian Fainelli u32 pf; /* RO # of xmited pause frame count */ 117b4af9a55SFlorian Fainelli u32 cf; /* RO # of xmited control frame count */ 118b4af9a55SFlorian Fainelli u32 fcs; /* RO # of xmited FCS error count */ 119b4af9a55SFlorian Fainelli u32 ovr; /* RO # of xmited oversize pkt */ 120b4af9a55SFlorian Fainelli u32 drf; /* RO # of xmited deferral pkt */ 121b4af9a55SFlorian Fainelli u32 edf; /* RO # of xmited Excessive deferral pkt*/ 122b4af9a55SFlorian Fainelli u32 scl; /* RO # of xmited single collision pkt */ 123b4af9a55SFlorian Fainelli u32 mcl; /* RO # of xmited multiple collision pkt*/ 124b4af9a55SFlorian Fainelli u32 lcl; /* RO # of xmited late collision pkt */ 125b4af9a55SFlorian Fainelli u32 ecl; /* RO # of xmited excessive collision pkt*/ 126b4af9a55SFlorian Fainelli u32 frg; /* RO # of xmited fragments pkt*/ 127b4af9a55SFlorian Fainelli u32 ncl; /* RO # of xmited total collision count */ 128b4af9a55SFlorian Fainelli u32 jbr; /* RO # of xmited jabber count*/ 129b4af9a55SFlorian Fainelli u32 bytes; /* RO # of xmited byte count */ 130b4af9a55SFlorian Fainelli u32 pok; /* RO # of xmited good pkt */ 131b4af9a55SFlorian Fainelli u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 132b4af9a55SFlorian Fainelli }; 133b4af9a55SFlorian Fainelli 134b4af9a55SFlorian Fainelli struct bcmgenet_mib_counters { 135b4af9a55SFlorian Fainelli struct bcmgenet_rx_counters rx; 136b4af9a55SFlorian Fainelli struct bcmgenet_tx_counters tx; 137b4af9a55SFlorian Fainelli u32 rx_runt_cnt; 138b4af9a55SFlorian Fainelli u32 rx_runt_fcs; 139b4af9a55SFlorian Fainelli u32 rx_runt_fcs_align; 140b4af9a55SFlorian Fainelli u32 rx_runt_bytes; 141b4af9a55SFlorian Fainelli u32 rbuf_ovflow_cnt; 142b4af9a55SFlorian Fainelli u32 rbuf_err_cnt; 143b4af9a55SFlorian Fainelli u32 mdf_err_cnt; 14444c8bc3cSFlorian Fainelli u32 alloc_rx_buff_failed; 14544c8bc3cSFlorian Fainelli u32 rx_dma_failed; 14644c8bc3cSFlorian Fainelli u32 tx_dma_failed; 147f1af17c0SDoug Berger u32 tx_realloc_tsb; 148f1af17c0SDoug Berger u32 tx_realloc_tsb_failed; 149b4af9a55SFlorian Fainelli }; 150b4af9a55SFlorian Fainelli 151b4af9a55SFlorian Fainelli #define UMAC_HD_BKP_CTRL 0x004 152b4af9a55SFlorian Fainelli #define HD_FC_EN (1 << 0) 153b4af9a55SFlorian Fainelli #define HD_FC_BKOFF_OK (1 << 1) 154b4af9a55SFlorian Fainelli #define IPG_CONFIG_RX_SHIFT 2 155b4af9a55SFlorian Fainelli #define IPG_CONFIG_RX_MASK 0x1F 156b4af9a55SFlorian Fainelli 157b4af9a55SFlorian Fainelli #define UMAC_CMD 0x008 158b4af9a55SFlorian Fainelli #define CMD_TX_EN (1 << 0) 159b4af9a55SFlorian Fainelli #define CMD_RX_EN (1 << 1) 160b4af9a55SFlorian Fainelli #define UMAC_SPEED_10 0 161b4af9a55SFlorian Fainelli #define UMAC_SPEED_100 1 162b4af9a55SFlorian Fainelli #define UMAC_SPEED_1000 2 163b4af9a55SFlorian Fainelli #define UMAC_SPEED_2500 3 164b4af9a55SFlorian Fainelli #define CMD_SPEED_SHIFT 2 165b4af9a55SFlorian Fainelli #define CMD_SPEED_MASK 3 166b4af9a55SFlorian Fainelli #define CMD_PROMISC (1 << 4) 167b4af9a55SFlorian Fainelli #define CMD_PAD_EN (1 << 5) 168b4af9a55SFlorian Fainelli #define CMD_CRC_FWD (1 << 6) 169b4af9a55SFlorian Fainelli #define CMD_PAUSE_FWD (1 << 7) 170b4af9a55SFlorian Fainelli #define CMD_RX_PAUSE_IGNORE (1 << 8) 171b4af9a55SFlorian Fainelli #define CMD_TX_ADDR_INS (1 << 9) 172b4af9a55SFlorian Fainelli #define CMD_HD_EN (1 << 10) 173b4af9a55SFlorian Fainelli #define CMD_SW_RESET (1 << 13) 174b4af9a55SFlorian Fainelli #define CMD_LCL_LOOP_EN (1 << 15) 175b4af9a55SFlorian Fainelli #define CMD_AUTO_CONFIG (1 << 22) 176b4af9a55SFlorian Fainelli #define CMD_CNTL_FRM_EN (1 << 23) 177b4af9a55SFlorian Fainelli #define CMD_NO_LEN_CHK (1 << 24) 178b4af9a55SFlorian Fainelli #define CMD_RMT_LOOP_EN (1 << 25) 179b4af9a55SFlorian Fainelli #define CMD_PRBL_EN (1 << 27) 180b4af9a55SFlorian Fainelli #define CMD_TX_PAUSE_IGNORE (1 << 28) 181b4af9a55SFlorian Fainelli #define CMD_TX_RX_EN (1 << 29) 182b4af9a55SFlorian Fainelli #define CMD_RUNT_FILTER_DIS (1 << 30) 183b4af9a55SFlorian Fainelli 184b4af9a55SFlorian Fainelli #define UMAC_MAC0 0x00C 185b4af9a55SFlorian Fainelli #define UMAC_MAC1 0x010 186b4af9a55SFlorian Fainelli #define UMAC_MAX_FRAME_LEN 0x014 187b4af9a55SFlorian Fainelli 188c3c397c1SDoug Berger #define UMAC_MODE 0x44 189c3c397c1SDoug Berger #define MODE_LINK_STATUS (1 << 5) 190c3c397c1SDoug Berger 191d0a6db8dSFlorian Fainelli #define UMAC_EEE_CTRL 0x064 192d0a6db8dSFlorian Fainelli #define EN_LPI_RX_PAUSE (1 << 0) 193d0a6db8dSFlorian Fainelli #define EN_LPI_TX_PFC (1 << 1) 194d0a6db8dSFlorian Fainelli #define EN_LPI_TX_PAUSE (1 << 2) 195d0a6db8dSFlorian Fainelli #define EEE_EN (1 << 3) 196d0a6db8dSFlorian Fainelli #define RX_FIFO_CHECK (1 << 4) 197d0a6db8dSFlorian Fainelli #define EEE_TX_CLK_DIS (1 << 5) 198d0a6db8dSFlorian Fainelli #define DIS_EEE_10M (1 << 6) 199d0a6db8dSFlorian Fainelli #define LP_IDLE_PREDICTION_MODE (1 << 7) 200d0a6db8dSFlorian Fainelli 201d0a6db8dSFlorian Fainelli #define UMAC_EEE_LPI_TIMER 0x068 202d0a6db8dSFlorian Fainelli #define UMAC_EEE_WAKE_TIMER 0x06C 203d0a6db8dSFlorian Fainelli #define UMAC_EEE_REF_COUNT 0x070 204d0a6db8dSFlorian Fainelli #define EEE_REFERENCE_COUNT_MASK 0xffff 205d0a6db8dSFlorian Fainelli 206b4af9a55SFlorian Fainelli #define UMAC_TX_FLUSH 0x334 207b4af9a55SFlorian Fainelli 208b4af9a55SFlorian Fainelli #define UMAC_MIB_START 0x400 209b4af9a55SFlorian Fainelli 210b4af9a55SFlorian Fainelli #define UMAC_MDIO_CMD 0x614 211b4af9a55SFlorian Fainelli #define MDIO_START_BUSY (1 << 29) 212b4af9a55SFlorian Fainelli #define MDIO_READ_FAIL (1 << 28) 213b4af9a55SFlorian Fainelli #define MDIO_RD (2 << 26) 214b4af9a55SFlorian Fainelli #define MDIO_WR (1 << 26) 215b4af9a55SFlorian Fainelli #define MDIO_PMD_SHIFT 21 216b4af9a55SFlorian Fainelli #define MDIO_PMD_MASK 0x1F 217b4af9a55SFlorian Fainelli #define MDIO_REG_SHIFT 16 218b4af9a55SFlorian Fainelli #define MDIO_REG_MASK 0x1F 219b4af9a55SFlorian Fainelli 220ffff7132SDoug Berger #define UMAC_RBUF_OVFL_CNT_V1 0x61C 221ffff7132SDoug Berger #define RBUF_OVFL_CNT_V2 0x80 222ffff7132SDoug Berger #define RBUF_OVFL_CNT_V3PLUS 0x94 223b4af9a55SFlorian Fainelli 224b4af9a55SFlorian Fainelli #define UMAC_MPD_CTRL 0x620 225b4af9a55SFlorian Fainelli #define MPD_EN (1 << 0) 226b4af9a55SFlorian Fainelli #define MPD_PW_EN (1 << 27) 227b4af9a55SFlorian Fainelli #define MPD_MSEQ_LEN_SHIFT 16 228b4af9a55SFlorian Fainelli #define MPD_MSEQ_LEN_MASK 0xFF 229b4af9a55SFlorian Fainelli 230b4af9a55SFlorian Fainelli #define UMAC_MPD_PW_MS 0x624 231b4af9a55SFlorian Fainelli #define UMAC_MPD_PW_LS 0x628 232ffff7132SDoug Berger #define UMAC_RBUF_ERR_CNT_V1 0x634 233ffff7132SDoug Berger #define RBUF_ERR_CNT_V2 0x84 234ffff7132SDoug Berger #define RBUF_ERR_CNT_V3PLUS 0x98 235b4af9a55SFlorian Fainelli #define UMAC_MDF_ERR_CNT 0x638 236b4af9a55SFlorian Fainelli #define UMAC_MDF_CTRL 0x650 237b4af9a55SFlorian Fainelli #define UMAC_MDF_ADDR 0x654 238b4af9a55SFlorian Fainelli #define UMAC_MIB_CTRL 0x580 239b4af9a55SFlorian Fainelli #define MIB_RESET_RX (1 << 0) 240b4af9a55SFlorian Fainelli #define MIB_RESET_RUNT (1 << 1) 241b4af9a55SFlorian Fainelli #define MIB_RESET_TX (1 << 2) 242b4af9a55SFlorian Fainelli 243b4af9a55SFlorian Fainelli #define RBUF_CTRL 0x00 244b4af9a55SFlorian Fainelli #define RBUF_64B_EN (1 << 0) 245b4af9a55SFlorian Fainelli #define RBUF_ALIGN_2B (1 << 1) 246b4af9a55SFlorian Fainelli #define RBUF_BAD_DIS (1 << 2) 247b4af9a55SFlorian Fainelli 248b4af9a55SFlorian Fainelli #define RBUF_STATUS 0x0C 249b4af9a55SFlorian Fainelli #define RBUF_STATUS_WOL (1 << 0) 250b4af9a55SFlorian Fainelli #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 251b4af9a55SFlorian Fainelli #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 252b4af9a55SFlorian Fainelli 253b4af9a55SFlorian Fainelli #define RBUF_CHK_CTRL 0x14 254b4af9a55SFlorian Fainelli #define RBUF_RXCHK_EN (1 << 0) 255b4af9a55SFlorian Fainelli #define RBUF_SKIP_FCS (1 << 4) 25681015539SDoug Berger #define RBUF_L3_PARSE_DIS (1 << 5) 257b4af9a55SFlorian Fainelli 258d0a6db8dSFlorian Fainelli #define RBUF_ENERGY_CTRL 0x9c 259d0a6db8dSFlorian Fainelli #define RBUF_EEE_EN (1 << 0) 260d0a6db8dSFlorian Fainelli #define RBUF_PM_EN (1 << 1) 261d0a6db8dSFlorian Fainelli 262b4af9a55SFlorian Fainelli #define RBUF_TBUF_SIZE_CTRL 0xb4 263b4af9a55SFlorian Fainelli 264b4af9a55SFlorian Fainelli #define RBUF_HFB_CTRL_V1 0x38 265b4af9a55SFlorian Fainelli #define RBUF_HFB_FILTER_EN_SHIFT 16 266b4af9a55SFlorian Fainelli #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 267b4af9a55SFlorian Fainelli #define RBUF_HFB_EN (1 << 0) 268b4af9a55SFlorian Fainelli #define RBUF_HFB_256B (1 << 1) 269b4af9a55SFlorian Fainelli #define RBUF_ACPI_EN (1 << 2) 270b4af9a55SFlorian Fainelli 271b4af9a55SFlorian Fainelli #define RBUF_HFB_LEN_V1 0x3C 272b4af9a55SFlorian Fainelli #define RBUF_FLTR_LEN_MASK 0xFF 273b4af9a55SFlorian Fainelli #define RBUF_FLTR_LEN_SHIFT 8 274b4af9a55SFlorian Fainelli 275b4af9a55SFlorian Fainelli #define TBUF_CTRL 0x00 276b4af9a55SFlorian Fainelli #define TBUF_BP_MC 0x0C 277d0a6db8dSFlorian Fainelli #define TBUF_ENERGY_CTRL 0x14 278d0a6db8dSFlorian Fainelli #define TBUF_EEE_EN (1 << 0) 279d0a6db8dSFlorian Fainelli #define TBUF_PM_EN (1 << 1) 280b4af9a55SFlorian Fainelli 281b4af9a55SFlorian Fainelli #define TBUF_CTRL_V1 0x80 282b4af9a55SFlorian Fainelli #define TBUF_BP_MC_V1 0xA0 283b4af9a55SFlorian Fainelli 284b4af9a55SFlorian Fainelli #define HFB_CTRL 0x00 285b4af9a55SFlorian Fainelli #define HFB_FLT_ENABLE_V3PLUS 0x04 286b4af9a55SFlorian Fainelli #define HFB_FLT_LEN_V2 0x04 287b4af9a55SFlorian Fainelli #define HFB_FLT_LEN_V3PLUS 0x1C 288b4af9a55SFlorian Fainelli 289b4af9a55SFlorian Fainelli /* uniMac intrl2 registers */ 290b4af9a55SFlorian Fainelli #define INTRL2_CPU_STAT 0x00 291b4af9a55SFlorian Fainelli #define INTRL2_CPU_SET 0x04 292b4af9a55SFlorian Fainelli #define INTRL2_CPU_CLEAR 0x08 293b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_STATUS 0x0C 294b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_SET 0x10 295b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_CLEAR 0x14 296b4af9a55SFlorian Fainelli 297b4af9a55SFlorian Fainelli /* INTRL2 instance 0 definitions */ 298b4af9a55SFlorian Fainelli #define UMAC_IRQ_SCB (1 << 0) 299b4af9a55SFlorian Fainelli #define UMAC_IRQ_EPHY (1 << 1) 300b4af9a55SFlorian Fainelli #define UMAC_IRQ_PHY_DET_R (1 << 2) 301b4af9a55SFlorian Fainelli #define UMAC_IRQ_PHY_DET_F (1 << 3) 302b4af9a55SFlorian Fainelli #define UMAC_IRQ_LINK_UP (1 << 4) 303b4af9a55SFlorian Fainelli #define UMAC_IRQ_LINK_DOWN (1 << 5) 304e122966dSPetri Gynther #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN) 305b4af9a55SFlorian Fainelli #define UMAC_IRQ_UMAC (1 << 6) 306b4af9a55SFlorian Fainelli #define UMAC_IRQ_UMAC_TSV (1 << 7) 307b4af9a55SFlorian Fainelli #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 308b4af9a55SFlorian Fainelli #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 309b4af9a55SFlorian Fainelli #define UMAC_IRQ_HFB_SM (1 << 10) 310b4af9a55SFlorian Fainelli #define UMAC_IRQ_HFB_MM (1 << 11) 311b4af9a55SFlorian Fainelli #define UMAC_IRQ_MPD_R (1 << 12) 312b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 313b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 314b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 3154a29645bSFlorian Fainelli #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE 316b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 317b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 318b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 3192f913070SFlorian Fainelli #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE 3202f913070SFlorian Fainelli 321b4af9a55SFlorian Fainelli /* Only valid for GENETv3+ */ 322b4af9a55SFlorian Fainelli #define UMAC_IRQ_MDIO_DONE (1 << 23) 323b4af9a55SFlorian Fainelli #define UMAC_IRQ_MDIO_ERROR (1 << 24) 324b4af9a55SFlorian Fainelli 3254055eaefSPetri Gynther /* INTRL2 instance 1 definitions */ 3264055eaefSPetri Gynther #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF 3274055eaefSPetri Gynther #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF 3284055eaefSPetri Gynther #define UMAC_IRQ1_RX_INTR_SHIFT 16 3294055eaefSPetri Gynther 330b4af9a55SFlorian Fainelli /* Register block offsets */ 331b4af9a55SFlorian Fainelli #define GENET_SYS_OFF 0x0000 332b4af9a55SFlorian Fainelli #define GENET_GR_BRIDGE_OFF 0x0040 333b4af9a55SFlorian Fainelli #define GENET_EXT_OFF 0x0080 334b4af9a55SFlorian Fainelli #define GENET_INTRL2_0_OFF 0x0200 335b4af9a55SFlorian Fainelli #define GENET_INTRL2_1_OFF 0x0240 336b4af9a55SFlorian Fainelli #define GENET_RBUF_OFF 0x0300 337b4af9a55SFlorian Fainelli #define GENET_UMAC_OFF 0x0800 338b4af9a55SFlorian Fainelli 339b4af9a55SFlorian Fainelli /* SYS block offsets and register definitions */ 340b4af9a55SFlorian Fainelli #define SYS_REV_CTRL 0x00 341b4af9a55SFlorian Fainelli #define SYS_PORT_CTRL 0x04 342b4af9a55SFlorian Fainelli #define PORT_MODE_INT_EPHY 0 343b4af9a55SFlorian Fainelli #define PORT_MODE_INT_GPHY 1 344b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_EPHY 2 345b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_GPHY 3 346b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 347b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_RVMII_50 4 348b4af9a55SFlorian Fainelli #define LED_ACT_SOURCE_MAC (1 << 9) 349b4af9a55SFlorian Fainelli 350b4af9a55SFlorian Fainelli #define SYS_RBUF_FLUSH_CTRL 0x08 351b4af9a55SFlorian Fainelli #define SYS_TBUF_FLUSH_CTRL 0x0C 352b4af9a55SFlorian Fainelli #define RBUF_FLUSH_CTRL_V1 0x04 353b4af9a55SFlorian Fainelli 354b4af9a55SFlorian Fainelli /* Ext block register offsets and definitions */ 355b4af9a55SFlorian Fainelli #define EXT_EXT_PWR_MGMT 0x00 356b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_BIAS (1 << 0) 357b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_DLL (1 << 1) 358b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_PHY (1 << 2) 359b4af9a55SFlorian Fainelli #define EXT_PWR_DN_EN_LD (1 << 3) 360b4af9a55SFlorian Fainelli #define EXT_ENERGY_DET (1 << 4) 361b4af9a55SFlorian Fainelli #define EXT_IDDQ_FROM_PHY (1 << 5) 36242138085SDoug Berger #define EXT_IDDQ_GLBL_PWR (1 << 7) 363b4af9a55SFlorian Fainelli #define EXT_PHY_RESET (1 << 8) 364b4af9a55SFlorian Fainelli #define EXT_ENERGY_DET_MASK (1 << 12) 36542138085SDoug Berger #define EXT_PWR_DOWN_PHY_TX (1 << 16) 36642138085SDoug Berger #define EXT_PWR_DOWN_PHY_RX (1 << 17) 36742138085SDoug Berger #define EXT_PWR_DOWN_PHY_SD (1 << 18) 36842138085SDoug Berger #define EXT_PWR_DOWN_PHY_RD (1 << 19) 36942138085SDoug Berger #define EXT_PWR_DOWN_PHY_EN (1 << 20) 370b4af9a55SFlorian Fainelli 371b4af9a55SFlorian Fainelli #define EXT_RGMII_OOB_CTRL 0x0C 372efb86fedSFlorian Fainelli #define RGMII_MODE_EN_V123 (1 << 0) 373b4af9a55SFlorian Fainelli #define RGMII_LINK (1 << 4) 374b4af9a55SFlorian Fainelli #define OOB_DISABLE (1 << 5) 3755a680fadSFlorian Fainelli #define RGMII_MODE_EN (1 << 6) 376b4af9a55SFlorian Fainelli #define ID_MODE_DIS (1 << 16) 377b4af9a55SFlorian Fainelli 378b4af9a55SFlorian Fainelli #define EXT_GPHY_CTRL 0x1C 379b4af9a55SFlorian Fainelli #define EXT_CFG_IDDQ_BIAS (1 << 0) 380b4af9a55SFlorian Fainelli #define EXT_CFG_PWR_DOWN (1 << 1) 3810d017e21SFlorian Fainelli #define EXT_CK25_DIS (1 << 4) 382b4af9a55SFlorian Fainelli #define EXT_GPHY_RESET (1 << 5) 383b4af9a55SFlorian Fainelli 384b4af9a55SFlorian Fainelli /* DMA rings size */ 385b4af9a55SFlorian Fainelli #define DMA_RING_SIZE (0x40) 386b4af9a55SFlorian Fainelli #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 387b4af9a55SFlorian Fainelli 388b4af9a55SFlorian Fainelli /* DMA registers common definitions */ 389b4af9a55SFlorian Fainelli #define DMA_RW_POINTER_MASK 0x1FF 390b4af9a55SFlorian Fainelli #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 391b4af9a55SFlorian Fainelli #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 392b4af9a55SFlorian Fainelli #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 393b4af9a55SFlorian Fainelli #define DMA_BUFFER_DONE_CNT_SHIFT 16 394b4af9a55SFlorian Fainelli #define DMA_P_INDEX_MASK 0xFFFF 395b4af9a55SFlorian Fainelli #define DMA_C_INDEX_MASK 0xFFFF 396b4af9a55SFlorian Fainelli 397b4af9a55SFlorian Fainelli /* DMA ring size register */ 398b4af9a55SFlorian Fainelli #define DMA_RING_SIZE_MASK 0xFFFF 399b4af9a55SFlorian Fainelli #define DMA_RING_SIZE_SHIFT 16 400b4af9a55SFlorian Fainelli #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 401b4af9a55SFlorian Fainelli 402b4af9a55SFlorian Fainelli /* DMA interrupt threshold register */ 4032f913070SFlorian Fainelli #define DMA_INTR_THRESHOLD_MASK 0x01FF 404b4af9a55SFlorian Fainelli 405b4af9a55SFlorian Fainelli /* DMA XON/XOFF register */ 406b4af9a55SFlorian Fainelli #define DMA_XON_THREHOLD_MASK 0xFFFF 407b4af9a55SFlorian Fainelli #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 408b4af9a55SFlorian Fainelli #define DMA_XOFF_THRESHOLD_SHIFT 16 409b4af9a55SFlorian Fainelli 410b4af9a55SFlorian Fainelli /* DMA flow period register */ 411b4af9a55SFlorian Fainelli #define DMA_FLOW_PERIOD_MASK 0xFFFF 412b4af9a55SFlorian Fainelli #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 413b4af9a55SFlorian Fainelli #define DMA_MAX_PKT_SIZE_SHIFT 16 414b4af9a55SFlorian Fainelli 415b4af9a55SFlorian Fainelli 416b4af9a55SFlorian Fainelli /* DMA control register */ 417b4af9a55SFlorian Fainelli #define DMA_EN (1 << 0) 418b4af9a55SFlorian Fainelli #define DMA_RING_BUF_EN_SHIFT 0x01 419b4af9a55SFlorian Fainelli #define DMA_RING_BUF_EN_MASK 0xFFFF 420b4af9a55SFlorian Fainelli #define DMA_TSB_SWAP_EN (1 << 20) 421b4af9a55SFlorian Fainelli 422b4af9a55SFlorian Fainelli /* DMA status register */ 423b4af9a55SFlorian Fainelli #define DMA_DISABLED (1 << 0) 424b4af9a55SFlorian Fainelli #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 425b4af9a55SFlorian Fainelli 426b4af9a55SFlorian Fainelli /* DMA SCB burst size register */ 427b4af9a55SFlorian Fainelli #define DMA_SCB_BURST_SIZE_MASK 0x1F 428b4af9a55SFlorian Fainelli 429b4af9a55SFlorian Fainelli /* DMA activity vector register */ 430b4af9a55SFlorian Fainelli #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 431b4af9a55SFlorian Fainelli 432b4af9a55SFlorian Fainelli /* DMA backpressure mask register */ 433b4af9a55SFlorian Fainelli #define DMA_BACKPRESSURE_MASK 0x1FFFF 434b4af9a55SFlorian Fainelli #define DMA_PFC_ENABLE (1 << 31) 435b4af9a55SFlorian Fainelli 436b4af9a55SFlorian Fainelli /* DMA backpressure status register */ 437b4af9a55SFlorian Fainelli #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 438b4af9a55SFlorian Fainelli 439b4af9a55SFlorian Fainelli /* DMA override register */ 440b4af9a55SFlorian Fainelli #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 441b4af9a55SFlorian Fainelli #define DMA_REGISTER_MODE (1 << 1) 442b4af9a55SFlorian Fainelli 443b4af9a55SFlorian Fainelli /* DMA timeout register */ 444b4af9a55SFlorian Fainelli #define DMA_TIMEOUT_MASK 0xFFFF 445b4af9a55SFlorian Fainelli #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 446b4af9a55SFlorian Fainelli 447b4af9a55SFlorian Fainelli /* TDMA rate limiting control register */ 448b4af9a55SFlorian Fainelli #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 449b4af9a55SFlorian Fainelli 450b4af9a55SFlorian Fainelli /* TDMA arbitration control register */ 451b4af9a55SFlorian Fainelli #define DMA_ARBITER_MODE_MASK 0x03 452b4af9a55SFlorian Fainelli #define DMA_RING_BUF_PRIORITY_MASK 0x1F 453b4af9a55SFlorian Fainelli #define DMA_RING_BUF_PRIORITY_SHIFT 5 45437742166SPetri Gynther #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 45537742166SPetri Gynther #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 456b4af9a55SFlorian Fainelli #define DMA_RATE_ADJ_MASK 0xFF 457b4af9a55SFlorian Fainelli 458b4af9a55SFlorian Fainelli /* Tx/Rx Dma Descriptor common bits*/ 459b4af9a55SFlorian Fainelli #define DMA_BUFLENGTH_MASK 0x0fff 460b4af9a55SFlorian Fainelli #define DMA_BUFLENGTH_SHIFT 16 461b4af9a55SFlorian Fainelli #define DMA_OWN 0x8000 462b4af9a55SFlorian Fainelli #define DMA_EOP 0x4000 463b4af9a55SFlorian Fainelli #define DMA_SOP 0x2000 464b4af9a55SFlorian Fainelli #define DMA_WRAP 0x1000 465b4af9a55SFlorian Fainelli /* Tx specific Dma descriptor bits */ 466b4af9a55SFlorian Fainelli #define DMA_TX_UNDERRUN 0x0200 467b4af9a55SFlorian Fainelli #define DMA_TX_APPEND_CRC 0x0040 468b4af9a55SFlorian Fainelli #define DMA_TX_OW_CRC 0x0020 469b4af9a55SFlorian Fainelli #define DMA_TX_DO_CSUM 0x0010 470b4af9a55SFlorian Fainelli #define DMA_TX_QTAG_SHIFT 7 471b4af9a55SFlorian Fainelli 472b4af9a55SFlorian Fainelli /* Rx Specific Dma descriptor bits */ 473b4af9a55SFlorian Fainelli #define DMA_RX_CHK_V3PLUS 0x8000 474b4af9a55SFlorian Fainelli #define DMA_RX_CHK_V12 0x1000 475b4af9a55SFlorian Fainelli #define DMA_RX_BRDCAST 0x0040 476b4af9a55SFlorian Fainelli #define DMA_RX_MULT 0x0020 477b4af9a55SFlorian Fainelli #define DMA_RX_LG 0x0010 478b4af9a55SFlorian Fainelli #define DMA_RX_NO 0x0008 479b4af9a55SFlorian Fainelli #define DMA_RX_RXER 0x0004 480b4af9a55SFlorian Fainelli #define DMA_RX_CRC_ERROR 0x0002 481b4af9a55SFlorian Fainelli #define DMA_RX_OV 0x0001 482b4af9a55SFlorian Fainelli #define DMA_RX_FI_MASK 0x001F 483b4af9a55SFlorian Fainelli #define DMA_RX_FI_SHIFT 0x0007 484b4af9a55SFlorian Fainelli #define DMA_DESC_ALLOC_MASK 0x00FF 485b4af9a55SFlorian Fainelli 486b4af9a55SFlorian Fainelli #define DMA_ARBITER_RR 0x00 487b4af9a55SFlorian Fainelli #define DMA_ARBITER_WRR 0x01 488b4af9a55SFlorian Fainelli #define DMA_ARBITER_SP 0x02 489b4af9a55SFlorian Fainelli 490b4af9a55SFlorian Fainelli struct enet_cb { 491b4af9a55SFlorian Fainelli struct sk_buff *skb; 492b4af9a55SFlorian Fainelli void __iomem *bd_addr; 493b4af9a55SFlorian Fainelli DEFINE_DMA_UNMAP_ADDR(dma_addr); 494b4af9a55SFlorian Fainelli DEFINE_DMA_UNMAP_LEN(dma_len); 495b4af9a55SFlorian Fainelli }; 496b4af9a55SFlorian Fainelli 497b4af9a55SFlorian Fainelli /* power management mode */ 498b4af9a55SFlorian Fainelli enum bcmgenet_power_mode { 499b4af9a55SFlorian Fainelli GENET_POWER_CABLE_SENSE = 0, 500b4af9a55SFlorian Fainelli GENET_POWER_PASSIVE, 501c51de7f3SFlorian Fainelli GENET_POWER_WOL_MAGIC, 502b4af9a55SFlorian Fainelli }; 503b4af9a55SFlorian Fainelli 504b4af9a55SFlorian Fainelli struct bcmgenet_priv; 505b4af9a55SFlorian Fainelli 506b4af9a55SFlorian Fainelli /* We support both runtime GENET detection and compile-time 507b4af9a55SFlorian Fainelli * to optimize code-paths for a given hardware 508b4af9a55SFlorian Fainelli */ 509b4af9a55SFlorian Fainelli enum bcmgenet_version { 510b4af9a55SFlorian Fainelli GENET_V1 = 1, 511b4af9a55SFlorian Fainelli GENET_V2, 512b4af9a55SFlorian Fainelli GENET_V3, 51342138085SDoug Berger GENET_V4, 51442138085SDoug Berger GENET_V5 515b4af9a55SFlorian Fainelli }; 516b4af9a55SFlorian Fainelli 517b4af9a55SFlorian Fainelli #define GENET_IS_V1(p) ((p)->version == GENET_V1) 518b4af9a55SFlorian Fainelli #define GENET_IS_V2(p) ((p)->version == GENET_V2) 519b4af9a55SFlorian Fainelli #define GENET_IS_V3(p) ((p)->version == GENET_V3) 520b4af9a55SFlorian Fainelli #define GENET_IS_V4(p) ((p)->version == GENET_V4) 52142138085SDoug Berger #define GENET_IS_V5(p) ((p)->version == GENET_V5) 522b4af9a55SFlorian Fainelli 523b4af9a55SFlorian Fainelli /* Hardware flags */ 524b4af9a55SFlorian Fainelli #define GENET_HAS_40BITS (1 << 0) 525b4af9a55SFlorian Fainelli #define GENET_HAS_EXT (1 << 1) 526b4af9a55SFlorian Fainelli #define GENET_HAS_MDIO_INTR (1 << 2) 5278d88c6ebSPetri Gynther #define GENET_HAS_MOCA_LINK_DET (1 << 3) 528b4af9a55SFlorian Fainelli 529b4af9a55SFlorian Fainelli /* BCMGENET hardware parameters, keep this structure nicely aligned 530b4af9a55SFlorian Fainelli * since it is going to be used in hot paths 531b4af9a55SFlorian Fainelli */ 532b4af9a55SFlorian Fainelli struct bcmgenet_hw_params { 533b4af9a55SFlorian Fainelli u8 tx_queues; 53451a966a7SPetri Gynther u8 tx_bds_per_q; 535b4af9a55SFlorian Fainelli u8 rx_queues; 5363feafa02SPetri Gynther u8 rx_bds_per_q; 537b4af9a55SFlorian Fainelli u8 bp_in_en_shift; 538b4af9a55SFlorian Fainelli u32 bp_in_mask; 539b4af9a55SFlorian Fainelli u8 hfb_filter_cnt; 5400034de41SPetri Gynther u8 hfb_filter_size; 541b4af9a55SFlorian Fainelli u8 qtag_mask; 542b4af9a55SFlorian Fainelli u16 tbuf_offset; 543b4af9a55SFlorian Fainelli u32 hfb_offset; 544b4af9a55SFlorian Fainelli u32 hfb_reg_offset; 545b4af9a55SFlorian Fainelli u32 rdma_offset; 546b4af9a55SFlorian Fainelli u32 tdma_offset; 547b4af9a55SFlorian Fainelli u32 words_per_bd; 548b4af9a55SFlorian Fainelli u32 flags; 549b4af9a55SFlorian Fainelli }; 550b4af9a55SFlorian Fainelli 55155868120SPetri Gynther struct bcmgenet_skb_cb { 552f48bed16SDoug Berger struct enet_cb *first_cb; /* First control block of SKB */ 553f48bed16SDoug Berger struct enet_cb *last_cb; /* Last control block of SKB */ 55455868120SPetri Gynther unsigned int bytes_sent; /* bytes on the wire (no TSB) */ 55555868120SPetri Gynther }; 55655868120SPetri Gynther 55755868120SPetri Gynther #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb)) 55855868120SPetri Gynther 559b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring { 560b4af9a55SFlorian Fainelli spinlock_t lock; /* ring lock */ 5614092e6acSJaedon Shin struct napi_struct napi; /* NAPI per tx queue */ 56237a30b43SFlorian Fainelli unsigned long packets; 56337a30b43SFlorian Fainelli unsigned long bytes; 564b4af9a55SFlorian Fainelli unsigned int index; /* ring index */ 565b4af9a55SFlorian Fainelli unsigned int queue; /* queue index */ 566b4af9a55SFlorian Fainelli struct enet_cb *cbs; /* tx ring buffer control block*/ 567b4af9a55SFlorian Fainelli unsigned int size; /* size of each tx ring */ 56866d06757SPetri Gynther unsigned int clean_ptr; /* Tx ring clean pointer */ 569b4af9a55SFlorian Fainelli unsigned int c_index; /* last consumer index of each ring*/ 570b4af9a55SFlorian Fainelli unsigned int free_bds; /* # of free bds for each ring */ 571b4af9a55SFlorian Fainelli unsigned int write_ptr; /* Tx ring write pointer SW copy */ 572b4af9a55SFlorian Fainelli unsigned int prod_index; /* Tx ring producer index SW copy */ 573b4af9a55SFlorian Fainelli unsigned int cb_ptr; /* Tx ring initial CB ptr */ 574b4af9a55SFlorian Fainelli unsigned int end_ptr; /* Tx ring end CB ptr */ 5759dbac28fSPetri Gynther void (*int_enable)(struct bcmgenet_tx_ring *); 5769dbac28fSPetri Gynther void (*int_disable)(struct bcmgenet_tx_ring *); 5774092e6acSJaedon Shin struct bcmgenet_priv *priv; 578b4af9a55SFlorian Fainelli }; 579b4af9a55SFlorian Fainelli 5809f4ca058SFlorian Fainelli struct bcmgenet_net_dim { 5819f4ca058SFlorian Fainelli u16 use_dim; 5829f4ca058SFlorian Fainelli u16 event_ctr; 5839f4ca058SFlorian Fainelli unsigned long packets; 5849f4ca058SFlorian Fainelli unsigned long bytes; 5858960b389STal Gilboa struct dim dim; 5869f4ca058SFlorian Fainelli }; 5879f4ca058SFlorian Fainelli 5888ac467e8SPetri Gynther struct bcmgenet_rx_ring { 5894055eaefSPetri Gynther struct napi_struct napi; /* Rx NAPI struct */ 59037a30b43SFlorian Fainelli unsigned long bytes; 59137a30b43SFlorian Fainelli unsigned long packets; 59237a30b43SFlorian Fainelli unsigned long errors; 59337a30b43SFlorian Fainelli unsigned long dropped; 5948ac467e8SPetri Gynther unsigned int index; /* Rx ring index */ 5958ac467e8SPetri Gynther struct enet_cb *cbs; /* Rx ring buffer control block */ 5968ac467e8SPetri Gynther unsigned int size; /* Rx ring size */ 5978ac467e8SPetri Gynther unsigned int c_index; /* Rx last consumer index */ 5988ac467e8SPetri Gynther unsigned int read_ptr; /* Rx ring read pointer */ 5998ac467e8SPetri Gynther unsigned int cb_ptr; /* Rx ring initial CB ptr */ 6008ac467e8SPetri Gynther unsigned int end_ptr; /* Rx ring end CB ptr */ 601d26ea6ccSPetri Gynther unsigned int old_discards; 6029f4ca058SFlorian Fainelli struct bcmgenet_net_dim dim; 6035e6ce1f1SFlorian Fainelli u32 rx_max_coalesced_frames; 6045e6ce1f1SFlorian Fainelli u32 rx_coalesce_usecs; 6054055eaefSPetri Gynther void (*int_enable)(struct bcmgenet_rx_ring *); 6064055eaefSPetri Gynther void (*int_disable)(struct bcmgenet_rx_ring *); 6074055eaefSPetri Gynther struct bcmgenet_priv *priv; 6088ac467e8SPetri Gynther }; 6098ac467e8SPetri Gynther 610b4af9a55SFlorian Fainelli /* device context */ 611b4af9a55SFlorian Fainelli struct bcmgenet_priv { 612b4af9a55SFlorian Fainelli void __iomem *base; 613b4af9a55SFlorian Fainelli enum bcmgenet_version version; 614b4af9a55SFlorian Fainelli struct net_device *dev; 615b4af9a55SFlorian Fainelli 616b4af9a55SFlorian Fainelli /* transmit variables */ 617b4af9a55SFlorian Fainelli void __iomem *tx_bds; 618b4af9a55SFlorian Fainelli struct enet_cb *tx_cbs; 619b4af9a55SFlorian Fainelli unsigned int num_tx_bds; 620b4af9a55SFlorian Fainelli 621b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; 622b4af9a55SFlorian Fainelli 623b4af9a55SFlorian Fainelli /* receive variables */ 624b4af9a55SFlorian Fainelli void __iomem *rx_bds; 625b4af9a55SFlorian Fainelli struct enet_cb *rx_cbs; 626b4af9a55SFlorian Fainelli unsigned int num_rx_bds; 627b4af9a55SFlorian Fainelli unsigned int rx_buf_len; 6288ac467e8SPetri Gynther 6298ac467e8SPetri Gynther struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1]; 630b4af9a55SFlorian Fainelli 631b4af9a55SFlorian Fainelli /* other misc variables */ 632b4af9a55SFlorian Fainelli struct bcmgenet_hw_params *hw_params; 633b4af9a55SFlorian Fainelli 634b4af9a55SFlorian Fainelli /* MDIO bus variables */ 635b4af9a55SFlorian Fainelli wait_queue_head_t wq; 636c624f891SFlorian Fainelli bool internal_phy; 637b4af9a55SFlorian Fainelli struct device_node *phy_dn; 6387b635da8SFlorian Fainelli struct device_node *mdio_dn; 639b4af9a55SFlorian Fainelli struct mii_bus *mii_bus; 640487320c5SFlorian Fainelli u16 gphy_rev; 6416ef398eaSFlorian Fainelli struct clk *clk_eee; 6426ef398eaSFlorian Fainelli bool clk_eee_enabled; 643b4af9a55SFlorian Fainelli 644b4af9a55SFlorian Fainelli /* PHY device variables */ 645b4af9a55SFlorian Fainelli int old_link; 6465ad6e6c5SPetri Gynther int old_speed; 6475ad6e6c5SPetri Gynther int old_duplex; 648b4af9a55SFlorian Fainelli int old_pause; 649b4af9a55SFlorian Fainelli phy_interface_t phy_interface; 650b4af9a55SFlorian Fainelli int phy_addr; 651b4af9a55SFlorian Fainelli int ext_phy; 652b4af9a55SFlorian Fainelli 653b4af9a55SFlorian Fainelli /* Interrupt variables */ 654b4af9a55SFlorian Fainelli struct work_struct bcmgenet_irq_work; 655b4af9a55SFlorian Fainelli int irq0; 656b4af9a55SFlorian Fainelli int irq1; 6578562056fSFlorian Fainelli int wol_irq; 6588562056fSFlorian Fainelli bool wol_irq_disabled; 659b4af9a55SFlorian Fainelli 66007c52d6aSDoug Berger /* shared status */ 66107c52d6aSDoug Berger spinlock_t lock; 66207c52d6aSDoug Berger unsigned int irq0_stat; 66307c52d6aSDoug Berger 664b4af9a55SFlorian Fainelli /* HW descriptors/checksum variables */ 665b4af9a55SFlorian Fainelli bool desc_64b_en; 666b4af9a55SFlorian Fainelli bool desc_rxchk_en; 667b4af9a55SFlorian Fainelli bool crc_fwd_en; 668b4af9a55SFlorian Fainelli 669a50e3a99SStefan Wahren u32 dma_max_burst_length; 670b4af9a55SFlorian Fainelli 671b4af9a55SFlorian Fainelli u32 msg_enable; 672b4af9a55SFlorian Fainelli 673b4af9a55SFlorian Fainelli struct clk *clk; 674b4af9a55SFlorian Fainelli struct platform_device *pdev; 6759a4e7969SFlorian Fainelli struct platform_device *mii_pdev; 676b4af9a55SFlorian Fainelli 677b4af9a55SFlorian Fainelli /* WOL */ 678b4af9a55SFlorian Fainelli struct clk *clk_wol; 679b4af9a55SFlorian Fainelli u32 wolopts; 680b4af9a55SFlorian Fainelli 681b4af9a55SFlorian Fainelli struct bcmgenet_mib_counters mib; 6826ef398eaSFlorian Fainelli 6836ef398eaSFlorian Fainelli struct ethtool_eee eee; 684b4af9a55SFlorian Fainelli }; 685b4af9a55SFlorian Fainelli 686b4af9a55SFlorian Fainelli #define GENET_IO_MACRO(name, offset) \ 687b4af9a55SFlorian Fainelli static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 688b4af9a55SFlorian Fainelli u32 off) \ 689b4af9a55SFlorian Fainelli { \ 69069d2ea9cSFlorian Fainelli /* MIPS chips strapped for BE will automagically configure the \ 69169d2ea9cSFlorian Fainelli * peripheral registers for CPU-native byte order. \ 69269d2ea9cSFlorian Fainelli */ \ 69369d2ea9cSFlorian Fainelli if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 694b4af9a55SFlorian Fainelli return __raw_readl(priv->base + offset + off); \ 69569d2ea9cSFlorian Fainelli else \ 69669d2ea9cSFlorian Fainelli return readl_relaxed(priv->base + offset + off); \ 697b4af9a55SFlorian Fainelli } \ 698b4af9a55SFlorian Fainelli static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 699b4af9a55SFlorian Fainelli u32 val, u32 off) \ 700b4af9a55SFlorian Fainelli { \ 70169d2ea9cSFlorian Fainelli if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 702d081a16dSFlorian Fainelli __raw_writel(val, priv->base + offset + off); \ 70369d2ea9cSFlorian Fainelli else \ 70469d2ea9cSFlorian Fainelli writel_relaxed(val, priv->base + offset + off); \ 705b4af9a55SFlorian Fainelli } 706b4af9a55SFlorian Fainelli 707b4af9a55SFlorian Fainelli GENET_IO_MACRO(ext, GENET_EXT_OFF); 708b4af9a55SFlorian Fainelli GENET_IO_MACRO(umac, GENET_UMAC_OFF); 709b4af9a55SFlorian Fainelli GENET_IO_MACRO(sys, GENET_SYS_OFF); 710b4af9a55SFlorian Fainelli 711b4af9a55SFlorian Fainelli /* interrupt l2 registers accessors */ 712b4af9a55SFlorian Fainelli GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 713b4af9a55SFlorian Fainelli GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 714b4af9a55SFlorian Fainelli 715b4af9a55SFlorian Fainelli /* HFB register accessors */ 716b4af9a55SFlorian Fainelli GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 717b4af9a55SFlorian Fainelli 718b4af9a55SFlorian Fainelli /* GENET v2+ HFB control and filter len helpers */ 719b4af9a55SFlorian Fainelli GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 720b4af9a55SFlorian Fainelli 721b4af9a55SFlorian Fainelli /* RBUF register accessors */ 722b4af9a55SFlorian Fainelli GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 723b4af9a55SFlorian Fainelli 724b4af9a55SFlorian Fainelli /* MDIO routines */ 725b4af9a55SFlorian Fainelli int bcmgenet_mii_init(struct net_device *dev); 72600d51094SFlorian Fainelli int bcmgenet_mii_config(struct net_device *dev, bool init); 7276b6d017fSDoug Berger int bcmgenet_mii_probe(struct net_device *dev); 728b4af9a55SFlorian Fainelli void bcmgenet_mii_exit(struct net_device *dev); 729a642c4f7SFlorian Fainelli void bcmgenet_phy_power_set(struct net_device *dev, bool enable); 730c96e731cSFlorian Fainelli void bcmgenet_mii_setup(struct net_device *dev); 731b4af9a55SFlorian Fainelli 732c51de7f3SFlorian Fainelli /* Wake-on-LAN routines */ 733c51de7f3SFlorian Fainelli void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 734c51de7f3SFlorian Fainelli int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 735c51de7f3SFlorian Fainelli int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 736c51de7f3SFlorian Fainelli enum bcmgenet_power_mode mode); 737c51de7f3SFlorian Fainelli void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 738c51de7f3SFlorian Fainelli enum bcmgenet_power_mode mode); 739c51de7f3SFlorian Fainelli 740b4af9a55SFlorian Fainelli #endif /* __BCMGENET_H__ */ 741