1b4af9a55SFlorian Fainelli /* 2b4af9a55SFlorian Fainelli * Copyright (c) 2014 Broadcom Corporation 3b4af9a55SFlorian Fainelli * 4b4af9a55SFlorian Fainelli * This program is free software; you can redistribute it and/or modify 5b4af9a55SFlorian Fainelli * it under the terms of the GNU General Public License version 2 as 6b4af9a55SFlorian Fainelli * published by the Free Software Foundation. 7b4af9a55SFlorian Fainelli */ 85e811b39SFlorian Fainelli 9b4af9a55SFlorian Fainelli #ifndef __BCMGENET_H__ 10b4af9a55SFlorian Fainelli #define __BCMGENET_H__ 11b4af9a55SFlorian Fainelli 12b4af9a55SFlorian Fainelli #include <linux/skbuff.h> 13b4af9a55SFlorian Fainelli #include <linux/netdevice.h> 14b4af9a55SFlorian Fainelli #include <linux/spinlock.h> 15b4af9a55SFlorian Fainelli #include <linux/clk.h> 16b4af9a55SFlorian Fainelli #include <linux/mii.h> 17b4af9a55SFlorian Fainelli #include <linux/if_vlan.h> 18b4af9a55SFlorian Fainelli #include <linux/phy.h> 19b4af9a55SFlorian Fainelli 20b4af9a55SFlorian Fainelli /* total number of Buffer Descriptors, same for Rx/Tx */ 21b4af9a55SFlorian Fainelli #define TOTAL_DESC 256 22b4af9a55SFlorian Fainelli 23b4af9a55SFlorian Fainelli /* which ring is descriptor based */ 24b4af9a55SFlorian Fainelli #define DESC_INDEX 16 25b4af9a55SFlorian Fainelli 26b4af9a55SFlorian Fainelli /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 27b4af9a55SFlorian Fainelli * 1536 is multiple of 256 bytes 28b4af9a55SFlorian Fainelli */ 29b4af9a55SFlorian Fainelli #define ENET_BRCM_TAG_LEN 6 30b4af9a55SFlorian Fainelli #define ENET_PAD 8 31b4af9a55SFlorian Fainelli #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 32b4af9a55SFlorian Fainelli ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 33b4af9a55SFlorian Fainelli #define DMA_MAX_BURST_LENGTH 0x10 34b4af9a55SFlorian Fainelli 35b4af9a55SFlorian Fainelli /* misc. configuration */ 36b4af9a55SFlorian Fainelli #define CLEAR_ALL_HFB 0xFF 37b4af9a55SFlorian Fainelli #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 38b4af9a55SFlorian Fainelli #define DMA_FC_THRESH_LO 5 39b4af9a55SFlorian Fainelli 40b4af9a55SFlorian Fainelli /* 64B receive/transmit status block */ 41b4af9a55SFlorian Fainelli struct status_64 { 42b4af9a55SFlorian Fainelli u32 length_status; /* length and peripheral status */ 43b4af9a55SFlorian Fainelli u32 ext_status; /* Extended status*/ 44b4af9a55SFlorian Fainelli u32 rx_csum; /* partial rx checksum */ 45b4af9a55SFlorian Fainelli u32 unused1[9]; /* unused */ 46b4af9a55SFlorian Fainelli u32 tx_csum_info; /* Tx checksum info. */ 47b4af9a55SFlorian Fainelli u32 unused2[3]; /* unused */ 48b4af9a55SFlorian Fainelli }; 49b4af9a55SFlorian Fainelli 50b4af9a55SFlorian Fainelli /* Rx status bits */ 51b4af9a55SFlorian Fainelli #define STATUS_RX_EXT_MASK 0x1FFFFF 52b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_MASK 0xFFFF 53b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_OK 0x10000 54b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_FR 0x20000 55b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_TCP 0 56b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_UDP 1 57b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_ICMP 2 58b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_OTHER 3 59b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_MASK 3 60b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_SHIFT 18 61b4af9a55SFlorian Fainelli #define STATUS_FILTER_INDEX_MASK 0xFFFF 62b4af9a55SFlorian Fainelli /* Tx status bits */ 63b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_START_MASK 0X7FFF 64b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_START_SHIFT 16 65b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_PROTO_UDP 0x8000 66b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 67b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_LV 0x80000000 68b4af9a55SFlorian Fainelli 69b4af9a55SFlorian Fainelli /* DMA Descriptor */ 70b4af9a55SFlorian Fainelli #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 71b4af9a55SFlorian Fainelli #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 72b4af9a55SFlorian Fainelli #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 73b4af9a55SFlorian Fainelli 74b4af9a55SFlorian Fainelli /* Rx/Tx common counter group */ 75b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters { 76b4af9a55SFlorian Fainelli u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 77b4af9a55SFlorian Fainelli u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 78b4af9a55SFlorian Fainelli u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 79b4af9a55SFlorian Fainelli u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 80b4af9a55SFlorian Fainelli u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 81b4af9a55SFlorian Fainelli u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 82b4af9a55SFlorian Fainelli u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 83b4af9a55SFlorian Fainelli u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 84b4af9a55SFlorian Fainelli u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 85b4af9a55SFlorian Fainelli u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 86b4af9a55SFlorian Fainelli }; 87b4af9a55SFlorian Fainelli 88b4af9a55SFlorian Fainelli /* RSV, Receive Status Vector */ 89b4af9a55SFlorian Fainelli struct bcmgenet_rx_counters { 90b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters pkt_cnt; 91b4af9a55SFlorian Fainelli u32 pkt; /* RO (0x428) Received pkt count*/ 92b4af9a55SFlorian Fainelli u32 bytes; /* RO Received byte count */ 93b4af9a55SFlorian Fainelli u32 mca; /* RO # of Received multicast pkt */ 94b4af9a55SFlorian Fainelli u32 bca; /* RO # of Receive broadcast pkt */ 95b4af9a55SFlorian Fainelli u32 fcs; /* RO # of Received FCS error */ 96b4af9a55SFlorian Fainelli u32 cf; /* RO # of Received control frame pkt*/ 97b4af9a55SFlorian Fainelli u32 pf; /* RO # of Received pause frame pkt */ 98b4af9a55SFlorian Fainelli u32 uo; /* RO # of unknown op code pkt */ 99b4af9a55SFlorian Fainelli u32 aln; /* RO # of alignment error count */ 100b4af9a55SFlorian Fainelli u32 flr; /* RO # of frame length out of range count */ 101b4af9a55SFlorian Fainelli u32 cde; /* RO # of code error pkt */ 102b4af9a55SFlorian Fainelli u32 fcr; /* RO # of carrier sense error pkt */ 103b4af9a55SFlorian Fainelli u32 ovr; /* RO # of oversize pkt*/ 104b4af9a55SFlorian Fainelli u32 jbr; /* RO # of jabber count */ 105b4af9a55SFlorian Fainelli u32 mtue; /* RO # of MTU error pkt*/ 106b4af9a55SFlorian Fainelli u32 pok; /* RO # of Received good pkt */ 107b4af9a55SFlorian Fainelli u32 uc; /* RO # of unicast pkt */ 108b4af9a55SFlorian Fainelli u32 ppp; /* RO # of PPP pkt */ 109b4af9a55SFlorian Fainelli u32 rcrc; /* RO (0x470),# of CRC match pkt */ 110b4af9a55SFlorian Fainelli }; 111b4af9a55SFlorian Fainelli 112b4af9a55SFlorian Fainelli /* TSV, Transmit Status Vector */ 113b4af9a55SFlorian Fainelli struct bcmgenet_tx_counters { 114b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters pkt_cnt; 115b4af9a55SFlorian Fainelli u32 pkts; /* RO (0x4a8) Transmited pkt */ 116b4af9a55SFlorian Fainelli u32 mca; /* RO # of xmited multicast pkt */ 117b4af9a55SFlorian Fainelli u32 bca; /* RO # of xmited broadcast pkt */ 118b4af9a55SFlorian Fainelli u32 pf; /* RO # of xmited pause frame count */ 119b4af9a55SFlorian Fainelli u32 cf; /* RO # of xmited control frame count */ 120b4af9a55SFlorian Fainelli u32 fcs; /* RO # of xmited FCS error count */ 121b4af9a55SFlorian Fainelli u32 ovr; /* RO # of xmited oversize pkt */ 122b4af9a55SFlorian Fainelli u32 drf; /* RO # of xmited deferral pkt */ 123b4af9a55SFlorian Fainelli u32 edf; /* RO # of xmited Excessive deferral pkt*/ 124b4af9a55SFlorian Fainelli u32 scl; /* RO # of xmited single collision pkt */ 125b4af9a55SFlorian Fainelli u32 mcl; /* RO # of xmited multiple collision pkt*/ 126b4af9a55SFlorian Fainelli u32 lcl; /* RO # of xmited late collision pkt */ 127b4af9a55SFlorian Fainelli u32 ecl; /* RO # of xmited excessive collision pkt*/ 128b4af9a55SFlorian Fainelli u32 frg; /* RO # of xmited fragments pkt*/ 129b4af9a55SFlorian Fainelli u32 ncl; /* RO # of xmited total collision count */ 130b4af9a55SFlorian Fainelli u32 jbr; /* RO # of xmited jabber count*/ 131b4af9a55SFlorian Fainelli u32 bytes; /* RO # of xmited byte count */ 132b4af9a55SFlorian Fainelli u32 pok; /* RO # of xmited good pkt */ 133b4af9a55SFlorian Fainelli u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 134b4af9a55SFlorian Fainelli }; 135b4af9a55SFlorian Fainelli 136b4af9a55SFlorian Fainelli struct bcmgenet_mib_counters { 137b4af9a55SFlorian Fainelli struct bcmgenet_rx_counters rx; 138b4af9a55SFlorian Fainelli struct bcmgenet_tx_counters tx; 139b4af9a55SFlorian Fainelli u32 rx_runt_cnt; 140b4af9a55SFlorian Fainelli u32 rx_runt_fcs; 141b4af9a55SFlorian Fainelli u32 rx_runt_fcs_align; 142b4af9a55SFlorian Fainelli u32 rx_runt_bytes; 143b4af9a55SFlorian Fainelli u32 rbuf_ovflow_cnt; 144b4af9a55SFlorian Fainelli u32 rbuf_err_cnt; 145b4af9a55SFlorian Fainelli u32 mdf_err_cnt; 146b4af9a55SFlorian Fainelli }; 147b4af9a55SFlorian Fainelli 148b4af9a55SFlorian Fainelli #define UMAC_HD_BKP_CTRL 0x004 149b4af9a55SFlorian Fainelli #define HD_FC_EN (1 << 0) 150b4af9a55SFlorian Fainelli #define HD_FC_BKOFF_OK (1 << 1) 151b4af9a55SFlorian Fainelli #define IPG_CONFIG_RX_SHIFT 2 152b4af9a55SFlorian Fainelli #define IPG_CONFIG_RX_MASK 0x1F 153b4af9a55SFlorian Fainelli 154b4af9a55SFlorian Fainelli #define UMAC_CMD 0x008 155b4af9a55SFlorian Fainelli #define CMD_TX_EN (1 << 0) 156b4af9a55SFlorian Fainelli #define CMD_RX_EN (1 << 1) 157b4af9a55SFlorian Fainelli #define UMAC_SPEED_10 0 158b4af9a55SFlorian Fainelli #define UMAC_SPEED_100 1 159b4af9a55SFlorian Fainelli #define UMAC_SPEED_1000 2 160b4af9a55SFlorian Fainelli #define UMAC_SPEED_2500 3 161b4af9a55SFlorian Fainelli #define CMD_SPEED_SHIFT 2 162b4af9a55SFlorian Fainelli #define CMD_SPEED_MASK 3 163b4af9a55SFlorian Fainelli #define CMD_PROMISC (1 << 4) 164b4af9a55SFlorian Fainelli #define CMD_PAD_EN (1 << 5) 165b4af9a55SFlorian Fainelli #define CMD_CRC_FWD (1 << 6) 166b4af9a55SFlorian Fainelli #define CMD_PAUSE_FWD (1 << 7) 167b4af9a55SFlorian Fainelli #define CMD_RX_PAUSE_IGNORE (1 << 8) 168b4af9a55SFlorian Fainelli #define CMD_TX_ADDR_INS (1 << 9) 169b4af9a55SFlorian Fainelli #define CMD_HD_EN (1 << 10) 170b4af9a55SFlorian Fainelli #define CMD_SW_RESET (1 << 13) 171b4af9a55SFlorian Fainelli #define CMD_LCL_LOOP_EN (1 << 15) 172b4af9a55SFlorian Fainelli #define CMD_AUTO_CONFIG (1 << 22) 173b4af9a55SFlorian Fainelli #define CMD_CNTL_FRM_EN (1 << 23) 174b4af9a55SFlorian Fainelli #define CMD_NO_LEN_CHK (1 << 24) 175b4af9a55SFlorian Fainelli #define CMD_RMT_LOOP_EN (1 << 25) 176b4af9a55SFlorian Fainelli #define CMD_PRBL_EN (1 << 27) 177b4af9a55SFlorian Fainelli #define CMD_TX_PAUSE_IGNORE (1 << 28) 178b4af9a55SFlorian Fainelli #define CMD_TX_RX_EN (1 << 29) 179b4af9a55SFlorian Fainelli #define CMD_RUNT_FILTER_DIS (1 << 30) 180b4af9a55SFlorian Fainelli 181b4af9a55SFlorian Fainelli #define UMAC_MAC0 0x00C 182b4af9a55SFlorian Fainelli #define UMAC_MAC1 0x010 183b4af9a55SFlorian Fainelli #define UMAC_MAX_FRAME_LEN 0x014 184b4af9a55SFlorian Fainelli 185b4af9a55SFlorian Fainelli #define UMAC_TX_FLUSH 0x334 186b4af9a55SFlorian Fainelli 187b4af9a55SFlorian Fainelli #define UMAC_MIB_START 0x400 188b4af9a55SFlorian Fainelli 189b4af9a55SFlorian Fainelli #define UMAC_MDIO_CMD 0x614 190b4af9a55SFlorian Fainelli #define MDIO_START_BUSY (1 << 29) 191b4af9a55SFlorian Fainelli #define MDIO_READ_FAIL (1 << 28) 192b4af9a55SFlorian Fainelli #define MDIO_RD (2 << 26) 193b4af9a55SFlorian Fainelli #define MDIO_WR (1 << 26) 194b4af9a55SFlorian Fainelli #define MDIO_PMD_SHIFT 21 195b4af9a55SFlorian Fainelli #define MDIO_PMD_MASK 0x1F 196b4af9a55SFlorian Fainelli #define MDIO_REG_SHIFT 16 197b4af9a55SFlorian Fainelli #define MDIO_REG_MASK 0x1F 198b4af9a55SFlorian Fainelli 199b4af9a55SFlorian Fainelli #define UMAC_RBUF_OVFL_CNT 0x61C 200b4af9a55SFlorian Fainelli 201b4af9a55SFlorian Fainelli #define UMAC_MPD_CTRL 0x620 202b4af9a55SFlorian Fainelli #define MPD_EN (1 << 0) 203b4af9a55SFlorian Fainelli #define MPD_PW_EN (1 << 27) 204b4af9a55SFlorian Fainelli #define MPD_MSEQ_LEN_SHIFT 16 205b4af9a55SFlorian Fainelli #define MPD_MSEQ_LEN_MASK 0xFF 206b4af9a55SFlorian Fainelli 207b4af9a55SFlorian Fainelli #define UMAC_MPD_PW_MS 0x624 208b4af9a55SFlorian Fainelli #define UMAC_MPD_PW_LS 0x628 209b4af9a55SFlorian Fainelli #define UMAC_RBUF_ERR_CNT 0x634 210b4af9a55SFlorian Fainelli #define UMAC_MDF_ERR_CNT 0x638 211b4af9a55SFlorian Fainelli #define UMAC_MDF_CTRL 0x650 212b4af9a55SFlorian Fainelli #define UMAC_MDF_ADDR 0x654 213b4af9a55SFlorian Fainelli #define UMAC_MIB_CTRL 0x580 214b4af9a55SFlorian Fainelli #define MIB_RESET_RX (1 << 0) 215b4af9a55SFlorian Fainelli #define MIB_RESET_RUNT (1 << 1) 216b4af9a55SFlorian Fainelli #define MIB_RESET_TX (1 << 2) 217b4af9a55SFlorian Fainelli 218b4af9a55SFlorian Fainelli #define RBUF_CTRL 0x00 219b4af9a55SFlorian Fainelli #define RBUF_64B_EN (1 << 0) 220b4af9a55SFlorian Fainelli #define RBUF_ALIGN_2B (1 << 1) 221b4af9a55SFlorian Fainelli #define RBUF_BAD_DIS (1 << 2) 222b4af9a55SFlorian Fainelli 223b4af9a55SFlorian Fainelli #define RBUF_STATUS 0x0C 224b4af9a55SFlorian Fainelli #define RBUF_STATUS_WOL (1 << 0) 225b4af9a55SFlorian Fainelli #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 226b4af9a55SFlorian Fainelli #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 227b4af9a55SFlorian Fainelli 228b4af9a55SFlorian Fainelli #define RBUF_CHK_CTRL 0x14 229b4af9a55SFlorian Fainelli #define RBUF_RXCHK_EN (1 << 0) 230b4af9a55SFlorian Fainelli #define RBUF_SKIP_FCS (1 << 4) 231b4af9a55SFlorian Fainelli 232b4af9a55SFlorian Fainelli #define RBUF_TBUF_SIZE_CTRL 0xb4 233b4af9a55SFlorian Fainelli 234b4af9a55SFlorian Fainelli #define RBUF_HFB_CTRL_V1 0x38 235b4af9a55SFlorian Fainelli #define RBUF_HFB_FILTER_EN_SHIFT 16 236b4af9a55SFlorian Fainelli #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 237b4af9a55SFlorian Fainelli #define RBUF_HFB_EN (1 << 0) 238b4af9a55SFlorian Fainelli #define RBUF_HFB_256B (1 << 1) 239b4af9a55SFlorian Fainelli #define RBUF_ACPI_EN (1 << 2) 240b4af9a55SFlorian Fainelli 241b4af9a55SFlorian Fainelli #define RBUF_HFB_LEN_V1 0x3C 242b4af9a55SFlorian Fainelli #define RBUF_FLTR_LEN_MASK 0xFF 243b4af9a55SFlorian Fainelli #define RBUF_FLTR_LEN_SHIFT 8 244b4af9a55SFlorian Fainelli 245b4af9a55SFlorian Fainelli #define TBUF_CTRL 0x00 246b4af9a55SFlorian Fainelli #define TBUF_BP_MC 0x0C 247b4af9a55SFlorian Fainelli 248b4af9a55SFlorian Fainelli #define TBUF_CTRL_V1 0x80 249b4af9a55SFlorian Fainelli #define TBUF_BP_MC_V1 0xA0 250b4af9a55SFlorian Fainelli 251b4af9a55SFlorian Fainelli #define HFB_CTRL 0x00 252b4af9a55SFlorian Fainelli #define HFB_FLT_ENABLE_V3PLUS 0x04 253b4af9a55SFlorian Fainelli #define HFB_FLT_LEN_V2 0x04 254b4af9a55SFlorian Fainelli #define HFB_FLT_LEN_V3PLUS 0x1C 255b4af9a55SFlorian Fainelli 256b4af9a55SFlorian Fainelli /* uniMac intrl2 registers */ 257b4af9a55SFlorian Fainelli #define INTRL2_CPU_STAT 0x00 258b4af9a55SFlorian Fainelli #define INTRL2_CPU_SET 0x04 259b4af9a55SFlorian Fainelli #define INTRL2_CPU_CLEAR 0x08 260b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_STATUS 0x0C 261b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_SET 0x10 262b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_CLEAR 0x14 263b4af9a55SFlorian Fainelli 264b4af9a55SFlorian Fainelli /* INTRL2 instance 0 definitions */ 265b4af9a55SFlorian Fainelli #define UMAC_IRQ_SCB (1 << 0) 266b4af9a55SFlorian Fainelli #define UMAC_IRQ_EPHY (1 << 1) 267b4af9a55SFlorian Fainelli #define UMAC_IRQ_PHY_DET_R (1 << 2) 268b4af9a55SFlorian Fainelli #define UMAC_IRQ_PHY_DET_F (1 << 3) 269b4af9a55SFlorian Fainelli #define UMAC_IRQ_LINK_UP (1 << 4) 270b4af9a55SFlorian Fainelli #define UMAC_IRQ_LINK_DOWN (1 << 5) 271b4af9a55SFlorian Fainelli #define UMAC_IRQ_UMAC (1 << 6) 272b4af9a55SFlorian Fainelli #define UMAC_IRQ_UMAC_TSV (1 << 7) 273b4af9a55SFlorian Fainelli #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 274b4af9a55SFlorian Fainelli #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 275b4af9a55SFlorian Fainelli #define UMAC_IRQ_HFB_SM (1 << 10) 276b4af9a55SFlorian Fainelli #define UMAC_IRQ_HFB_MM (1 << 11) 277b4af9a55SFlorian Fainelli #define UMAC_IRQ_MPD_R (1 << 12) 278b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 279b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 280b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 281b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 282b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 283b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 284b4af9a55SFlorian Fainelli /* Only valid for GENETv3+ */ 285b4af9a55SFlorian Fainelli #define UMAC_IRQ_MDIO_DONE (1 << 23) 286b4af9a55SFlorian Fainelli #define UMAC_IRQ_MDIO_ERROR (1 << 24) 287b4af9a55SFlorian Fainelli 288b4af9a55SFlorian Fainelli /* Register block offsets */ 289b4af9a55SFlorian Fainelli #define GENET_SYS_OFF 0x0000 290b4af9a55SFlorian Fainelli #define GENET_GR_BRIDGE_OFF 0x0040 291b4af9a55SFlorian Fainelli #define GENET_EXT_OFF 0x0080 292b4af9a55SFlorian Fainelli #define GENET_INTRL2_0_OFF 0x0200 293b4af9a55SFlorian Fainelli #define GENET_INTRL2_1_OFF 0x0240 294b4af9a55SFlorian Fainelli #define GENET_RBUF_OFF 0x0300 295b4af9a55SFlorian Fainelli #define GENET_UMAC_OFF 0x0800 296b4af9a55SFlorian Fainelli 297b4af9a55SFlorian Fainelli /* SYS block offsets and register definitions */ 298b4af9a55SFlorian Fainelli #define SYS_REV_CTRL 0x00 299b4af9a55SFlorian Fainelli #define SYS_PORT_CTRL 0x04 300b4af9a55SFlorian Fainelli #define PORT_MODE_INT_EPHY 0 301b4af9a55SFlorian Fainelli #define PORT_MODE_INT_GPHY 1 302b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_EPHY 2 303b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_GPHY 3 304b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 305b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_RVMII_50 4 306b4af9a55SFlorian Fainelli #define LED_ACT_SOURCE_MAC (1 << 9) 307b4af9a55SFlorian Fainelli 308b4af9a55SFlorian Fainelli #define SYS_RBUF_FLUSH_CTRL 0x08 309b4af9a55SFlorian Fainelli #define SYS_TBUF_FLUSH_CTRL 0x0C 310b4af9a55SFlorian Fainelli #define RBUF_FLUSH_CTRL_V1 0x04 311b4af9a55SFlorian Fainelli 312b4af9a55SFlorian Fainelli /* Ext block register offsets and definitions */ 313b4af9a55SFlorian Fainelli #define EXT_EXT_PWR_MGMT 0x00 314b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_BIAS (1 << 0) 315b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_DLL (1 << 1) 316b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_PHY (1 << 2) 317b4af9a55SFlorian Fainelli #define EXT_PWR_DN_EN_LD (1 << 3) 318b4af9a55SFlorian Fainelli #define EXT_ENERGY_DET (1 << 4) 319b4af9a55SFlorian Fainelli #define EXT_IDDQ_FROM_PHY (1 << 5) 320b4af9a55SFlorian Fainelli #define EXT_PHY_RESET (1 << 8) 321b4af9a55SFlorian Fainelli #define EXT_ENERGY_DET_MASK (1 << 12) 322b4af9a55SFlorian Fainelli 323b4af9a55SFlorian Fainelli #define EXT_RGMII_OOB_CTRL 0x0C 324b4af9a55SFlorian Fainelli #define RGMII_LINK (1 << 4) 325b4af9a55SFlorian Fainelli #define OOB_DISABLE (1 << 5) 3265a680fadSFlorian Fainelli #define RGMII_MODE_EN (1 << 6) 327b4af9a55SFlorian Fainelli #define ID_MODE_DIS (1 << 16) 328b4af9a55SFlorian Fainelli 329b4af9a55SFlorian Fainelli #define EXT_GPHY_CTRL 0x1C 330b4af9a55SFlorian Fainelli #define EXT_CFG_IDDQ_BIAS (1 << 0) 331b4af9a55SFlorian Fainelli #define EXT_CFG_PWR_DOWN (1 << 1) 332b4af9a55SFlorian Fainelli #define EXT_GPHY_RESET (1 << 5) 333b4af9a55SFlorian Fainelli 334b4af9a55SFlorian Fainelli /* DMA rings size */ 335b4af9a55SFlorian Fainelli #define DMA_RING_SIZE (0x40) 336b4af9a55SFlorian Fainelli #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 337b4af9a55SFlorian Fainelli 338b4af9a55SFlorian Fainelli /* DMA registers common definitions */ 339b4af9a55SFlorian Fainelli #define DMA_RW_POINTER_MASK 0x1FF 340b4af9a55SFlorian Fainelli #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 341b4af9a55SFlorian Fainelli #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 342b4af9a55SFlorian Fainelli #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 343b4af9a55SFlorian Fainelli #define DMA_BUFFER_DONE_CNT_SHIFT 16 344b4af9a55SFlorian Fainelli #define DMA_P_INDEX_MASK 0xFFFF 345b4af9a55SFlorian Fainelli #define DMA_C_INDEX_MASK 0xFFFF 346b4af9a55SFlorian Fainelli 347b4af9a55SFlorian Fainelli /* DMA ring size register */ 348b4af9a55SFlorian Fainelli #define DMA_RING_SIZE_MASK 0xFFFF 349b4af9a55SFlorian Fainelli #define DMA_RING_SIZE_SHIFT 16 350b4af9a55SFlorian Fainelli #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 351b4af9a55SFlorian Fainelli 352b4af9a55SFlorian Fainelli /* DMA interrupt threshold register */ 353b4af9a55SFlorian Fainelli #define DMA_INTR_THRESHOLD_MASK 0x00FF 354b4af9a55SFlorian Fainelli 355b4af9a55SFlorian Fainelli /* DMA XON/XOFF register */ 356b4af9a55SFlorian Fainelli #define DMA_XON_THREHOLD_MASK 0xFFFF 357b4af9a55SFlorian Fainelli #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 358b4af9a55SFlorian Fainelli #define DMA_XOFF_THRESHOLD_SHIFT 16 359b4af9a55SFlorian Fainelli 360b4af9a55SFlorian Fainelli /* DMA flow period register */ 361b4af9a55SFlorian Fainelli #define DMA_FLOW_PERIOD_MASK 0xFFFF 362b4af9a55SFlorian Fainelli #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 363b4af9a55SFlorian Fainelli #define DMA_MAX_PKT_SIZE_SHIFT 16 364b4af9a55SFlorian Fainelli 365b4af9a55SFlorian Fainelli 366b4af9a55SFlorian Fainelli /* DMA control register */ 367b4af9a55SFlorian Fainelli #define DMA_EN (1 << 0) 368b4af9a55SFlorian Fainelli #define DMA_RING_BUF_EN_SHIFT 0x01 369b4af9a55SFlorian Fainelli #define DMA_RING_BUF_EN_MASK 0xFFFF 370b4af9a55SFlorian Fainelli #define DMA_TSB_SWAP_EN (1 << 20) 371b4af9a55SFlorian Fainelli 372b4af9a55SFlorian Fainelli /* DMA status register */ 373b4af9a55SFlorian Fainelli #define DMA_DISABLED (1 << 0) 374b4af9a55SFlorian Fainelli #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 375b4af9a55SFlorian Fainelli 376b4af9a55SFlorian Fainelli /* DMA SCB burst size register */ 377b4af9a55SFlorian Fainelli #define DMA_SCB_BURST_SIZE_MASK 0x1F 378b4af9a55SFlorian Fainelli 379b4af9a55SFlorian Fainelli /* DMA activity vector register */ 380b4af9a55SFlorian Fainelli #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 381b4af9a55SFlorian Fainelli 382b4af9a55SFlorian Fainelli /* DMA backpressure mask register */ 383b4af9a55SFlorian Fainelli #define DMA_BACKPRESSURE_MASK 0x1FFFF 384b4af9a55SFlorian Fainelli #define DMA_PFC_ENABLE (1 << 31) 385b4af9a55SFlorian Fainelli 386b4af9a55SFlorian Fainelli /* DMA backpressure status register */ 387b4af9a55SFlorian Fainelli #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 388b4af9a55SFlorian Fainelli 389b4af9a55SFlorian Fainelli /* DMA override register */ 390b4af9a55SFlorian Fainelli #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 391b4af9a55SFlorian Fainelli #define DMA_REGISTER_MODE (1 << 1) 392b4af9a55SFlorian Fainelli 393b4af9a55SFlorian Fainelli /* DMA timeout register */ 394b4af9a55SFlorian Fainelli #define DMA_TIMEOUT_MASK 0xFFFF 395b4af9a55SFlorian Fainelli #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 396b4af9a55SFlorian Fainelli 397b4af9a55SFlorian Fainelli /* TDMA rate limiting control register */ 398b4af9a55SFlorian Fainelli #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 399b4af9a55SFlorian Fainelli 400b4af9a55SFlorian Fainelli /* TDMA arbitration control register */ 401b4af9a55SFlorian Fainelli #define DMA_ARBITER_MODE_MASK 0x03 402b4af9a55SFlorian Fainelli #define DMA_RING_BUF_PRIORITY_MASK 0x1F 403b4af9a55SFlorian Fainelli #define DMA_RING_BUF_PRIORITY_SHIFT 5 40437742166SPetri Gynther #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 40537742166SPetri Gynther #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 406b4af9a55SFlorian Fainelli #define DMA_RATE_ADJ_MASK 0xFF 407b4af9a55SFlorian Fainelli 408b4af9a55SFlorian Fainelli /* Tx/Rx Dma Descriptor common bits*/ 409b4af9a55SFlorian Fainelli #define DMA_BUFLENGTH_MASK 0x0fff 410b4af9a55SFlorian Fainelli #define DMA_BUFLENGTH_SHIFT 16 411b4af9a55SFlorian Fainelli #define DMA_OWN 0x8000 412b4af9a55SFlorian Fainelli #define DMA_EOP 0x4000 413b4af9a55SFlorian Fainelli #define DMA_SOP 0x2000 414b4af9a55SFlorian Fainelli #define DMA_WRAP 0x1000 415b4af9a55SFlorian Fainelli /* Tx specific Dma descriptor bits */ 416b4af9a55SFlorian Fainelli #define DMA_TX_UNDERRUN 0x0200 417b4af9a55SFlorian Fainelli #define DMA_TX_APPEND_CRC 0x0040 418b4af9a55SFlorian Fainelli #define DMA_TX_OW_CRC 0x0020 419b4af9a55SFlorian Fainelli #define DMA_TX_DO_CSUM 0x0010 420b4af9a55SFlorian Fainelli #define DMA_TX_QTAG_SHIFT 7 421b4af9a55SFlorian Fainelli 422b4af9a55SFlorian Fainelli /* Rx Specific Dma descriptor bits */ 423b4af9a55SFlorian Fainelli #define DMA_RX_CHK_V3PLUS 0x8000 424b4af9a55SFlorian Fainelli #define DMA_RX_CHK_V12 0x1000 425b4af9a55SFlorian Fainelli #define DMA_RX_BRDCAST 0x0040 426b4af9a55SFlorian Fainelli #define DMA_RX_MULT 0x0020 427b4af9a55SFlorian Fainelli #define DMA_RX_LG 0x0010 428b4af9a55SFlorian Fainelli #define DMA_RX_NO 0x0008 429b4af9a55SFlorian Fainelli #define DMA_RX_RXER 0x0004 430b4af9a55SFlorian Fainelli #define DMA_RX_CRC_ERROR 0x0002 431b4af9a55SFlorian Fainelli #define DMA_RX_OV 0x0001 432b4af9a55SFlorian Fainelli #define DMA_RX_FI_MASK 0x001F 433b4af9a55SFlorian Fainelli #define DMA_RX_FI_SHIFT 0x0007 434b4af9a55SFlorian Fainelli #define DMA_DESC_ALLOC_MASK 0x00FF 435b4af9a55SFlorian Fainelli 436b4af9a55SFlorian Fainelli #define DMA_ARBITER_RR 0x00 437b4af9a55SFlorian Fainelli #define DMA_ARBITER_WRR 0x01 438b4af9a55SFlorian Fainelli #define DMA_ARBITER_SP 0x02 439b4af9a55SFlorian Fainelli 440b4af9a55SFlorian Fainelli struct enet_cb { 441b4af9a55SFlorian Fainelli struct sk_buff *skb; 442b4af9a55SFlorian Fainelli void __iomem *bd_addr; 443b4af9a55SFlorian Fainelli DEFINE_DMA_UNMAP_ADDR(dma_addr); 444b4af9a55SFlorian Fainelli DEFINE_DMA_UNMAP_LEN(dma_len); 445b4af9a55SFlorian Fainelli }; 446b4af9a55SFlorian Fainelli 447b4af9a55SFlorian Fainelli /* power management mode */ 448b4af9a55SFlorian Fainelli enum bcmgenet_power_mode { 449b4af9a55SFlorian Fainelli GENET_POWER_CABLE_SENSE = 0, 450b4af9a55SFlorian Fainelli GENET_POWER_PASSIVE, 451c51de7f3SFlorian Fainelli GENET_POWER_WOL_MAGIC, 452b4af9a55SFlorian Fainelli }; 453b4af9a55SFlorian Fainelli 454b4af9a55SFlorian Fainelli struct bcmgenet_priv; 455b4af9a55SFlorian Fainelli 456b4af9a55SFlorian Fainelli /* We support both runtime GENET detection and compile-time 457b4af9a55SFlorian Fainelli * to optimize code-paths for a given hardware 458b4af9a55SFlorian Fainelli */ 459b4af9a55SFlorian Fainelli enum bcmgenet_version { 460b4af9a55SFlorian Fainelli GENET_V1 = 1, 461b4af9a55SFlorian Fainelli GENET_V2, 462b4af9a55SFlorian Fainelli GENET_V3, 463b4af9a55SFlorian Fainelli GENET_V4 464b4af9a55SFlorian Fainelli }; 465b4af9a55SFlorian Fainelli 466b4af9a55SFlorian Fainelli #define GENET_IS_V1(p) ((p)->version == GENET_V1) 467b4af9a55SFlorian Fainelli #define GENET_IS_V2(p) ((p)->version == GENET_V2) 468b4af9a55SFlorian Fainelli #define GENET_IS_V3(p) ((p)->version == GENET_V3) 469b4af9a55SFlorian Fainelli #define GENET_IS_V4(p) ((p)->version == GENET_V4) 470b4af9a55SFlorian Fainelli 471b4af9a55SFlorian Fainelli /* Hardware flags */ 472b4af9a55SFlorian Fainelli #define GENET_HAS_40BITS (1 << 0) 473b4af9a55SFlorian Fainelli #define GENET_HAS_EXT (1 << 1) 474b4af9a55SFlorian Fainelli #define GENET_HAS_MDIO_INTR (1 << 2) 475b4af9a55SFlorian Fainelli 476b4af9a55SFlorian Fainelli /* BCMGENET hardware parameters, keep this structure nicely aligned 477b4af9a55SFlorian Fainelli * since it is going to be used in hot paths 478b4af9a55SFlorian Fainelli */ 479b4af9a55SFlorian Fainelli struct bcmgenet_hw_params { 480b4af9a55SFlorian Fainelli u8 tx_queues; 481b4af9a55SFlorian Fainelli u8 rx_queues; 482b4af9a55SFlorian Fainelli u8 bds_cnt; 483b4af9a55SFlorian Fainelli u8 bp_in_en_shift; 484b4af9a55SFlorian Fainelli u32 bp_in_mask; 485b4af9a55SFlorian Fainelli u8 hfb_filter_cnt; 486b4af9a55SFlorian Fainelli u8 qtag_mask; 487b4af9a55SFlorian Fainelli u16 tbuf_offset; 488b4af9a55SFlorian Fainelli u32 hfb_offset; 489b4af9a55SFlorian Fainelli u32 hfb_reg_offset; 490b4af9a55SFlorian Fainelli u32 rdma_offset; 491b4af9a55SFlorian Fainelli u32 tdma_offset; 492b4af9a55SFlorian Fainelli u32 words_per_bd; 493b4af9a55SFlorian Fainelli u32 flags; 494b4af9a55SFlorian Fainelli }; 495b4af9a55SFlorian Fainelli 496b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring { 497b4af9a55SFlorian Fainelli spinlock_t lock; /* ring lock */ 498b4af9a55SFlorian Fainelli unsigned int index; /* ring index */ 499b4af9a55SFlorian Fainelli unsigned int queue; /* queue index */ 500b4af9a55SFlorian Fainelli struct enet_cb *cbs; /* tx ring buffer control block*/ 501b4af9a55SFlorian Fainelli unsigned int size; /* size of each tx ring */ 502b4af9a55SFlorian Fainelli unsigned int c_index; /* last consumer index of each ring*/ 503b4af9a55SFlorian Fainelli unsigned int free_bds; /* # of free bds for each ring */ 504b4af9a55SFlorian Fainelli unsigned int write_ptr; /* Tx ring write pointer SW copy */ 505b4af9a55SFlorian Fainelli unsigned int prod_index; /* Tx ring producer index SW copy */ 506b4af9a55SFlorian Fainelli unsigned int cb_ptr; /* Tx ring initial CB ptr */ 507b4af9a55SFlorian Fainelli unsigned int end_ptr; /* Tx ring end CB ptr */ 508b4af9a55SFlorian Fainelli void (*int_enable)(struct bcmgenet_priv *priv, 509b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring *); 510b4af9a55SFlorian Fainelli void (*int_disable)(struct bcmgenet_priv *priv, 511b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring *); 512b4af9a55SFlorian Fainelli }; 513b4af9a55SFlorian Fainelli 514b4af9a55SFlorian Fainelli /* device context */ 515b4af9a55SFlorian Fainelli struct bcmgenet_priv { 516b4af9a55SFlorian Fainelli void __iomem *base; 517b4af9a55SFlorian Fainelli enum bcmgenet_version version; 518b4af9a55SFlorian Fainelli struct net_device *dev; 519b4af9a55SFlorian Fainelli u32 int0_mask; 520b4af9a55SFlorian Fainelli u32 int1_mask; 521b4af9a55SFlorian Fainelli 522b4af9a55SFlorian Fainelli /* NAPI for descriptor based rx */ 523b4af9a55SFlorian Fainelli struct napi_struct napi ____cacheline_aligned; 524b4af9a55SFlorian Fainelli 525b4af9a55SFlorian Fainelli /* transmit variables */ 526b4af9a55SFlorian Fainelli void __iomem *tx_bds; 527b4af9a55SFlorian Fainelli struct enet_cb *tx_cbs; 528b4af9a55SFlorian Fainelli unsigned int num_tx_bds; 529b4af9a55SFlorian Fainelli 530b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; 531b4af9a55SFlorian Fainelli 532b4af9a55SFlorian Fainelli /* receive variables */ 533b4af9a55SFlorian Fainelli void __iomem *rx_bds; 534b4af9a55SFlorian Fainelli void __iomem *rx_bd_assign_ptr; 535b4af9a55SFlorian Fainelli int rx_bd_assign_index; 536b4af9a55SFlorian Fainelli struct enet_cb *rx_cbs; 537b4af9a55SFlorian Fainelli unsigned int num_rx_bds; 538b4af9a55SFlorian Fainelli unsigned int rx_buf_len; 539b4af9a55SFlorian Fainelli unsigned int rx_read_ptr; 540b4af9a55SFlorian Fainelli unsigned int rx_c_index; 541b4af9a55SFlorian Fainelli 542b4af9a55SFlorian Fainelli /* other misc variables */ 543b4af9a55SFlorian Fainelli struct bcmgenet_hw_params *hw_params; 544b4af9a55SFlorian Fainelli 545b4af9a55SFlorian Fainelli /* MDIO bus variables */ 546b4af9a55SFlorian Fainelli wait_queue_head_t wq; 547b4af9a55SFlorian Fainelli struct phy_device *phydev; 548b4af9a55SFlorian Fainelli struct device_node *phy_dn; 549b4af9a55SFlorian Fainelli struct mii_bus *mii_bus; 550487320c5SFlorian Fainelli u16 gphy_rev; 551b4af9a55SFlorian Fainelli 552b4af9a55SFlorian Fainelli /* PHY device variables */ 553b4af9a55SFlorian Fainelli int old_link; 5545ad6e6c5SPetri Gynther int old_speed; 5555ad6e6c5SPetri Gynther int old_duplex; 556b4af9a55SFlorian Fainelli int old_pause; 557b4af9a55SFlorian Fainelli phy_interface_t phy_interface; 558b4af9a55SFlorian Fainelli int phy_addr; 559b4af9a55SFlorian Fainelli int ext_phy; 560b4af9a55SFlorian Fainelli 561b4af9a55SFlorian Fainelli /* Interrupt variables */ 562b4af9a55SFlorian Fainelli struct work_struct bcmgenet_irq_work; 563b4af9a55SFlorian Fainelli int irq0; 564b4af9a55SFlorian Fainelli int irq1; 565b4af9a55SFlorian Fainelli unsigned int irq0_stat; 566b4af9a55SFlorian Fainelli unsigned int irq1_stat; 5678562056fSFlorian Fainelli int wol_irq; 5688562056fSFlorian Fainelli bool wol_irq_disabled; 569b4af9a55SFlorian Fainelli 570b4af9a55SFlorian Fainelli /* HW descriptors/checksum variables */ 571b4af9a55SFlorian Fainelli bool desc_64b_en; 572b4af9a55SFlorian Fainelli bool desc_rxchk_en; 573b4af9a55SFlorian Fainelli bool crc_fwd_en; 574b4af9a55SFlorian Fainelli 575b4af9a55SFlorian Fainelli unsigned int dma_rx_chk_bit; 576b4af9a55SFlorian Fainelli 577b4af9a55SFlorian Fainelli u32 msg_enable; 578b4af9a55SFlorian Fainelli 579b4af9a55SFlorian Fainelli struct clk *clk; 580b4af9a55SFlorian Fainelli struct platform_device *pdev; 581b4af9a55SFlorian Fainelli 582b4af9a55SFlorian Fainelli /* WOL */ 583b4af9a55SFlorian Fainelli struct clk *clk_wol; 584b4af9a55SFlorian Fainelli u32 wolopts; 585b4af9a55SFlorian Fainelli 586b4af9a55SFlorian Fainelli struct bcmgenet_mib_counters mib; 587b4af9a55SFlorian Fainelli }; 588b4af9a55SFlorian Fainelli 589b4af9a55SFlorian Fainelli #define GENET_IO_MACRO(name, offset) \ 590b4af9a55SFlorian Fainelli static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 591b4af9a55SFlorian Fainelli u32 off) \ 592b4af9a55SFlorian Fainelli { \ 593b4af9a55SFlorian Fainelli return __raw_readl(priv->base + offset + off); \ 594b4af9a55SFlorian Fainelli } \ 595b4af9a55SFlorian Fainelli static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 596b4af9a55SFlorian Fainelli u32 val, u32 off) \ 597b4af9a55SFlorian Fainelli { \ 598b4af9a55SFlorian Fainelli __raw_writel(val, priv->base + offset + off); \ 599b4af9a55SFlorian Fainelli } 600b4af9a55SFlorian Fainelli 601b4af9a55SFlorian Fainelli GENET_IO_MACRO(ext, GENET_EXT_OFF); 602b4af9a55SFlorian Fainelli GENET_IO_MACRO(umac, GENET_UMAC_OFF); 603b4af9a55SFlorian Fainelli GENET_IO_MACRO(sys, GENET_SYS_OFF); 604b4af9a55SFlorian Fainelli 605b4af9a55SFlorian Fainelli /* interrupt l2 registers accessors */ 606b4af9a55SFlorian Fainelli GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 607b4af9a55SFlorian Fainelli GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 608b4af9a55SFlorian Fainelli 609b4af9a55SFlorian Fainelli /* HFB register accessors */ 610b4af9a55SFlorian Fainelli GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 611b4af9a55SFlorian Fainelli 612b4af9a55SFlorian Fainelli /* GENET v2+ HFB control and filter len helpers */ 613b4af9a55SFlorian Fainelli GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 614b4af9a55SFlorian Fainelli 615b4af9a55SFlorian Fainelli /* RBUF register accessors */ 616b4af9a55SFlorian Fainelli GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 617b4af9a55SFlorian Fainelli 618b4af9a55SFlorian Fainelli /* MDIO routines */ 619b4af9a55SFlorian Fainelli int bcmgenet_mii_init(struct net_device *dev); 620b4af9a55SFlorian Fainelli int bcmgenet_mii_config(struct net_device *dev); 621b4af9a55SFlorian Fainelli void bcmgenet_mii_exit(struct net_device *dev); 622b4af9a55SFlorian Fainelli void bcmgenet_mii_reset(struct net_device *dev); 623b4af9a55SFlorian Fainelli 624c51de7f3SFlorian Fainelli /* Wake-on-LAN routines */ 625c51de7f3SFlorian Fainelli void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 626c51de7f3SFlorian Fainelli int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 627c51de7f3SFlorian Fainelli int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 628c51de7f3SFlorian Fainelli enum bcmgenet_power_mode mode); 629c51de7f3SFlorian Fainelli void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 630c51de7f3SFlorian Fainelli enum bcmgenet_power_mode mode); 631c51de7f3SFlorian Fainelli 632b4af9a55SFlorian Fainelli #endif /* __BCMGENET_H__ */ 633