1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2b4af9a55SFlorian Fainelli /* 300d1a1bcSDoug Berger * Copyright (c) 2014-2024 Broadcom 4b4af9a55SFlorian Fainelli */ 55e811b39SFlorian Fainelli 6b4af9a55SFlorian Fainelli #ifndef __BCMGENET_H__ 7b4af9a55SFlorian Fainelli #define __BCMGENET_H__ 8b4af9a55SFlorian Fainelli 9b4af9a55SFlorian Fainelli #include <linux/skbuff.h> 10b4af9a55SFlorian Fainelli #include <linux/netdevice.h> 11b4af9a55SFlorian Fainelli #include <linux/spinlock.h> 12b4af9a55SFlorian Fainelli #include <linux/clk.h> 13b4af9a55SFlorian Fainelli #include <linux/mii.h> 14b4af9a55SFlorian Fainelli #include <linux/if_vlan.h> 15b4af9a55SFlorian Fainelli #include <linux/phy.h> 164f75da36STal Gilboa #include <linux/dim.h> 176f768905SDoug Berger #include <linux/ethtool.h> 18b4af9a55SFlorian Fainelli 1928e303daSRafał Miłecki #include "../unimac.h" 2028e303daSRafał Miłecki 21b4af9a55SFlorian Fainelli /* total number of Buffer Descriptors, same for Rx/Tx */ 22b4af9a55SFlorian Fainelli #define TOTAL_DESC 256 23b4af9a55SFlorian Fainelli 24b4af9a55SFlorian Fainelli /* which ring is descriptor based */ 25b4af9a55SFlorian Fainelli #define DESC_INDEX 16 26b4af9a55SFlorian Fainelli 27b4af9a55SFlorian Fainelli /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 28b4af9a55SFlorian Fainelli * 1536 is multiple of 256 bytes 29b4af9a55SFlorian Fainelli */ 30b4af9a55SFlorian Fainelli #define ENET_BRCM_TAG_LEN 6 31b4af9a55SFlorian Fainelli #define ENET_PAD 8 32b4af9a55SFlorian Fainelli #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 33b4af9a55SFlorian Fainelli ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 34b4af9a55SFlorian Fainelli #define DMA_MAX_BURST_LENGTH 0x10 35b4af9a55SFlorian Fainelli 36b4af9a55SFlorian Fainelli /* misc. configuration */ 373e370952SDoug Berger #define MAX_NUM_OF_FS_RULES 16 38b4af9a55SFlorian Fainelli #define CLEAR_ALL_HFB 0xFF 39b4af9a55SFlorian Fainelli #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 40b4af9a55SFlorian Fainelli #define DMA_FC_THRESH_LO 5 41b4af9a55SFlorian Fainelli 42b4af9a55SFlorian Fainelli /* 64B receive/transmit status block */ 43b4af9a55SFlorian Fainelli struct status_64 { 44b4af9a55SFlorian Fainelli u32 length_status; /* length and peripheral status */ 45b4af9a55SFlorian Fainelli u32 ext_status; /* Extended status*/ 46b4af9a55SFlorian Fainelli u32 rx_csum; /* partial rx checksum */ 47b4af9a55SFlorian Fainelli u32 unused1[9]; /* unused */ 48b4af9a55SFlorian Fainelli u32 tx_csum_info; /* Tx checksum info. */ 49b4af9a55SFlorian Fainelli u32 unused2[3]; /* unused */ 50b4af9a55SFlorian Fainelli }; 51b4af9a55SFlorian Fainelli 52b4af9a55SFlorian Fainelli /* Rx status bits */ 53b4af9a55SFlorian Fainelli #define STATUS_RX_EXT_MASK 0x1FFFFF 54b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_MASK 0xFFFF 55b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_OK 0x10000 56b4af9a55SFlorian Fainelli #define STATUS_RX_CSUM_FR 0x20000 57b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_TCP 0 58b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_UDP 1 59b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_ICMP 2 60b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_OTHER 3 61b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_MASK 3 62b4af9a55SFlorian Fainelli #define STATUS_RX_PROTO_SHIFT 18 63b4af9a55SFlorian Fainelli #define STATUS_FILTER_INDEX_MASK 0xFFFF 64b4af9a55SFlorian Fainelli /* Tx status bits */ 65b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_START_MASK 0X7FFF 66b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_START_SHIFT 16 67b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_PROTO_UDP 0x8000 68b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 69b4af9a55SFlorian Fainelli #define STATUS_TX_CSUM_LV 0x80000000 70b4af9a55SFlorian Fainelli 71b4af9a55SFlorian Fainelli /* DMA Descriptor */ 72b4af9a55SFlorian Fainelli #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 73b4af9a55SFlorian Fainelli #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 74b4af9a55SFlorian Fainelli #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 75b4af9a55SFlorian Fainelli 76b4af9a55SFlorian Fainelli /* Rx/Tx common counter group */ 77b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters { 78b4af9a55SFlorian Fainelli u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 79b4af9a55SFlorian Fainelli u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 80b4af9a55SFlorian Fainelli u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 81b4af9a55SFlorian Fainelli u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 82b4af9a55SFlorian Fainelli u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 83b4af9a55SFlorian Fainelli u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 84b4af9a55SFlorian Fainelli u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 85b4af9a55SFlorian Fainelli u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 86b4af9a55SFlorian Fainelli u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 87b4af9a55SFlorian Fainelli u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 88b4af9a55SFlorian Fainelli }; 89b4af9a55SFlorian Fainelli 90b4af9a55SFlorian Fainelli /* RSV, Receive Status Vector */ 91b4af9a55SFlorian Fainelli struct bcmgenet_rx_counters { 92b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters pkt_cnt; 93b4af9a55SFlorian Fainelli u32 pkt; /* RO (0x428) Received pkt count*/ 94b4af9a55SFlorian Fainelli u32 bytes; /* RO Received byte count */ 95b4af9a55SFlorian Fainelli u32 mca; /* RO # of Received multicast pkt */ 96b4af9a55SFlorian Fainelli u32 bca; /* RO # of Receive broadcast pkt */ 97b4af9a55SFlorian Fainelli u32 fcs; /* RO # of Received FCS error */ 98b4af9a55SFlorian Fainelli u32 cf; /* RO # of Received control frame pkt*/ 99b4af9a55SFlorian Fainelli u32 pf; /* RO # of Received pause frame pkt */ 100b4af9a55SFlorian Fainelli u32 uo; /* RO # of unknown op code pkt */ 101b4af9a55SFlorian Fainelli u32 aln; /* RO # of alignment error count */ 102b4af9a55SFlorian Fainelli u32 flr; /* RO # of frame length out of range count */ 103b4af9a55SFlorian Fainelli u32 cde; /* RO # of code error pkt */ 104b4af9a55SFlorian Fainelli u32 fcr; /* RO # of carrier sense error pkt */ 105b4af9a55SFlorian Fainelli u32 ovr; /* RO # of oversize pkt*/ 106b4af9a55SFlorian Fainelli u32 jbr; /* RO # of jabber count */ 107b4af9a55SFlorian Fainelli u32 mtue; /* RO # of MTU error pkt*/ 108b4af9a55SFlorian Fainelli u32 pok; /* RO # of Received good pkt */ 109b4af9a55SFlorian Fainelli u32 uc; /* RO # of unicast pkt */ 110b4af9a55SFlorian Fainelli u32 ppp; /* RO # of PPP pkt */ 111b4af9a55SFlorian Fainelli u32 rcrc; /* RO (0x470),# of CRC match pkt */ 112b4af9a55SFlorian Fainelli }; 113b4af9a55SFlorian Fainelli 114b4af9a55SFlorian Fainelli /* TSV, Transmit Status Vector */ 115b4af9a55SFlorian Fainelli struct bcmgenet_tx_counters { 116b4af9a55SFlorian Fainelli struct bcmgenet_pkt_counters pkt_cnt; 117b4af9a55SFlorian Fainelli u32 pkts; /* RO (0x4a8) Transmited pkt */ 118b4af9a55SFlorian Fainelli u32 mca; /* RO # of xmited multicast pkt */ 119b4af9a55SFlorian Fainelli u32 bca; /* RO # of xmited broadcast pkt */ 120b4af9a55SFlorian Fainelli u32 pf; /* RO # of xmited pause frame count */ 121b4af9a55SFlorian Fainelli u32 cf; /* RO # of xmited control frame count */ 122b4af9a55SFlorian Fainelli u32 fcs; /* RO # of xmited FCS error count */ 123b4af9a55SFlorian Fainelli u32 ovr; /* RO # of xmited oversize pkt */ 124b4af9a55SFlorian Fainelli u32 drf; /* RO # of xmited deferral pkt */ 125b4af9a55SFlorian Fainelli u32 edf; /* RO # of xmited Excessive deferral pkt*/ 126b4af9a55SFlorian Fainelli u32 scl; /* RO # of xmited single collision pkt */ 127b4af9a55SFlorian Fainelli u32 mcl; /* RO # of xmited multiple collision pkt*/ 128b4af9a55SFlorian Fainelli u32 lcl; /* RO # of xmited late collision pkt */ 129b4af9a55SFlorian Fainelli u32 ecl; /* RO # of xmited excessive collision pkt*/ 130b4af9a55SFlorian Fainelli u32 frg; /* RO # of xmited fragments pkt*/ 131b4af9a55SFlorian Fainelli u32 ncl; /* RO # of xmited total collision count */ 132b4af9a55SFlorian Fainelli u32 jbr; /* RO # of xmited jabber count*/ 133b4af9a55SFlorian Fainelli u32 bytes; /* RO # of xmited byte count */ 134b4af9a55SFlorian Fainelli u32 pok; /* RO # of xmited good pkt */ 135b4af9a55SFlorian Fainelli u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 136b4af9a55SFlorian Fainelli }; 137b4af9a55SFlorian Fainelli 138b4af9a55SFlorian Fainelli struct bcmgenet_mib_counters { 139b4af9a55SFlorian Fainelli struct bcmgenet_rx_counters rx; 140b4af9a55SFlorian Fainelli struct bcmgenet_tx_counters tx; 141b4af9a55SFlorian Fainelli u32 rx_runt_cnt; 142b4af9a55SFlorian Fainelli u32 rx_runt_fcs; 143b4af9a55SFlorian Fainelli u32 rx_runt_fcs_align; 144b4af9a55SFlorian Fainelli u32 rx_runt_bytes; 145b4af9a55SFlorian Fainelli u32 rbuf_ovflow_cnt; 146b4af9a55SFlorian Fainelli u32 rbuf_err_cnt; 147b4af9a55SFlorian Fainelli u32 mdf_err_cnt; 14844c8bc3cSFlorian Fainelli u32 alloc_rx_buff_failed; 14944c8bc3cSFlorian Fainelli u32 rx_dma_failed; 15044c8bc3cSFlorian Fainelli u32 tx_dma_failed; 151f1af17c0SDoug Berger u32 tx_realloc_tsb; 152f1af17c0SDoug Berger u32 tx_realloc_tsb_failed; 153b4af9a55SFlorian Fainelli }; 154b4af9a55SFlorian Fainelli 155b4af9a55SFlorian Fainelli #define UMAC_MIB_START 0x400 156b4af9a55SFlorian Fainelli 157b4af9a55SFlorian Fainelli #define UMAC_MDIO_CMD 0x614 158b4af9a55SFlorian Fainelli #define MDIO_START_BUSY (1 << 29) 159b4af9a55SFlorian Fainelli #define MDIO_READ_FAIL (1 << 28) 160b4af9a55SFlorian Fainelli #define MDIO_RD (2 << 26) 161b4af9a55SFlorian Fainelli #define MDIO_WR (1 << 26) 162b4af9a55SFlorian Fainelli #define MDIO_PMD_SHIFT 21 163b4af9a55SFlorian Fainelli #define MDIO_PMD_MASK 0x1F 164b4af9a55SFlorian Fainelli #define MDIO_REG_SHIFT 16 165b4af9a55SFlorian Fainelli #define MDIO_REG_MASK 0x1F 166b4af9a55SFlorian Fainelli 167ffff7132SDoug Berger #define UMAC_RBUF_OVFL_CNT_V1 0x61C 168ffff7132SDoug Berger #define RBUF_OVFL_CNT_V2 0x80 169ffff7132SDoug Berger #define RBUF_OVFL_CNT_V3PLUS 0x94 170b4af9a55SFlorian Fainelli 171b4af9a55SFlorian Fainelli #define UMAC_MPD_CTRL 0x620 172b4af9a55SFlorian Fainelli #define MPD_EN (1 << 0) 173b4af9a55SFlorian Fainelli #define MPD_PW_EN (1 << 27) 174b4af9a55SFlorian Fainelli #define MPD_MSEQ_LEN_SHIFT 16 175b4af9a55SFlorian Fainelli #define MPD_MSEQ_LEN_MASK 0xFF 176b4af9a55SFlorian Fainelli 177b4af9a55SFlorian Fainelli #define UMAC_MPD_PW_MS 0x624 178b4af9a55SFlorian Fainelli #define UMAC_MPD_PW_LS 0x628 179ffff7132SDoug Berger #define UMAC_RBUF_ERR_CNT_V1 0x634 180ffff7132SDoug Berger #define RBUF_ERR_CNT_V2 0x84 181ffff7132SDoug Berger #define RBUF_ERR_CNT_V3PLUS 0x98 182b4af9a55SFlorian Fainelli #define UMAC_MDF_ERR_CNT 0x638 183b4af9a55SFlorian Fainelli #define UMAC_MDF_CTRL 0x650 184b4af9a55SFlorian Fainelli #define UMAC_MDF_ADDR 0x654 185b4af9a55SFlorian Fainelli #define UMAC_MIB_CTRL 0x580 186b4af9a55SFlorian Fainelli #define MIB_RESET_RX (1 << 0) 187b4af9a55SFlorian Fainelli #define MIB_RESET_RUNT (1 << 1) 188b4af9a55SFlorian Fainelli #define MIB_RESET_TX (1 << 2) 189b4af9a55SFlorian Fainelli 190b4af9a55SFlorian Fainelli #define RBUF_CTRL 0x00 191b4af9a55SFlorian Fainelli #define RBUF_64B_EN (1 << 0) 192b4af9a55SFlorian Fainelli #define RBUF_ALIGN_2B (1 << 1) 193b4af9a55SFlorian Fainelli #define RBUF_BAD_DIS (1 << 2) 194b4af9a55SFlorian Fainelli 195b4af9a55SFlorian Fainelli #define RBUF_STATUS 0x0C 196b4af9a55SFlorian Fainelli #define RBUF_STATUS_WOL (1 << 0) 197b4af9a55SFlorian Fainelli #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 198b4af9a55SFlorian Fainelli #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 199b4af9a55SFlorian Fainelli 200b4af9a55SFlorian Fainelli #define RBUF_CHK_CTRL 0x14 201b4af9a55SFlorian Fainelli #define RBUF_RXCHK_EN (1 << 0) 202b4af9a55SFlorian Fainelli #define RBUF_SKIP_FCS (1 << 4) 20381015539SDoug Berger #define RBUF_L3_PARSE_DIS (1 << 5) 204b4af9a55SFlorian Fainelli 205d0a6db8dSFlorian Fainelli #define RBUF_ENERGY_CTRL 0x9c 206d0a6db8dSFlorian Fainelli #define RBUF_EEE_EN (1 << 0) 207d0a6db8dSFlorian Fainelli #define RBUF_PM_EN (1 << 1) 208d0a6db8dSFlorian Fainelli 209b4af9a55SFlorian Fainelli #define RBUF_TBUF_SIZE_CTRL 0xb4 210b4af9a55SFlorian Fainelli 211b4af9a55SFlorian Fainelli #define RBUF_HFB_CTRL_V1 0x38 212b4af9a55SFlorian Fainelli #define RBUF_HFB_FILTER_EN_SHIFT 16 213b4af9a55SFlorian Fainelli #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 214b4af9a55SFlorian Fainelli #define RBUF_HFB_EN (1 << 0) 215b4af9a55SFlorian Fainelli #define RBUF_HFB_256B (1 << 1) 216b4af9a55SFlorian Fainelli #define RBUF_ACPI_EN (1 << 2) 217b4af9a55SFlorian Fainelli 218b4af9a55SFlorian Fainelli #define RBUF_HFB_LEN_V1 0x3C 219b4af9a55SFlorian Fainelli #define RBUF_FLTR_LEN_MASK 0xFF 220b4af9a55SFlorian Fainelli #define RBUF_FLTR_LEN_SHIFT 8 221b4af9a55SFlorian Fainelli 222b4af9a55SFlorian Fainelli #define TBUF_CTRL 0x00 2239a9ba2a4SDoug Berger #define TBUF_64B_EN (1 << 0) 224b4af9a55SFlorian Fainelli #define TBUF_BP_MC 0x0C 225d0a6db8dSFlorian Fainelli #define TBUF_ENERGY_CTRL 0x14 226d0a6db8dSFlorian Fainelli #define TBUF_EEE_EN (1 << 0) 227d0a6db8dSFlorian Fainelli #define TBUF_PM_EN (1 << 1) 228b4af9a55SFlorian Fainelli 229b4af9a55SFlorian Fainelli #define TBUF_CTRL_V1 0x80 230b4af9a55SFlorian Fainelli #define TBUF_BP_MC_V1 0xA0 231b4af9a55SFlorian Fainelli 232b4af9a55SFlorian Fainelli #define HFB_CTRL 0x00 233b4af9a55SFlorian Fainelli #define HFB_FLT_ENABLE_V3PLUS 0x04 234b4af9a55SFlorian Fainelli #define HFB_FLT_LEN_V2 0x04 235b4af9a55SFlorian Fainelli #define HFB_FLT_LEN_V3PLUS 0x1C 236b4af9a55SFlorian Fainelli 237b4af9a55SFlorian Fainelli /* uniMac intrl2 registers */ 238b4af9a55SFlorian Fainelli #define INTRL2_CPU_STAT 0x00 239b4af9a55SFlorian Fainelli #define INTRL2_CPU_SET 0x04 240b4af9a55SFlorian Fainelli #define INTRL2_CPU_CLEAR 0x08 241b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_STATUS 0x0C 242b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_SET 0x10 243b4af9a55SFlorian Fainelli #define INTRL2_CPU_MASK_CLEAR 0x14 244b4af9a55SFlorian Fainelli 245b4af9a55SFlorian Fainelli /* INTRL2 instance 0 definitions */ 246b4af9a55SFlorian Fainelli #define UMAC_IRQ_SCB (1 << 0) 247b4af9a55SFlorian Fainelli #define UMAC_IRQ_EPHY (1 << 1) 248b4af9a55SFlorian Fainelli #define UMAC_IRQ_PHY_DET_R (1 << 2) 249b4af9a55SFlorian Fainelli #define UMAC_IRQ_PHY_DET_F (1 << 3) 250b4af9a55SFlorian Fainelli #define UMAC_IRQ_LINK_UP (1 << 4) 251b4af9a55SFlorian Fainelli #define UMAC_IRQ_LINK_DOWN (1 << 5) 252e122966dSPetri Gynther #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN) 253b4af9a55SFlorian Fainelli #define UMAC_IRQ_UMAC (1 << 6) 254b4af9a55SFlorian Fainelli #define UMAC_IRQ_UMAC_TSV (1 << 7) 255b4af9a55SFlorian Fainelli #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 256b4af9a55SFlorian Fainelli #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 257b4af9a55SFlorian Fainelli #define UMAC_IRQ_HFB_SM (1 << 10) 258b4af9a55SFlorian Fainelli #define UMAC_IRQ_HFB_MM (1 << 11) 259b4af9a55SFlorian Fainelli #define UMAC_IRQ_MPD_R (1 << 12) 260eb236c29SDoug Berger #define UMAC_IRQ_WAKE_EVENT (UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_MM | \ 261eb236c29SDoug Berger UMAC_IRQ_MPD_R) 262b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 263b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 264b4af9a55SFlorian Fainelli #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 2654a29645bSFlorian Fainelli #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE 266b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 267b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 268b4af9a55SFlorian Fainelli #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 2692f913070SFlorian Fainelli #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE 2702f913070SFlorian Fainelli 271b4af9a55SFlorian Fainelli /* Only valid for GENETv3+ */ 272b4af9a55SFlorian Fainelli #define UMAC_IRQ_MDIO_DONE (1 << 23) 273b4af9a55SFlorian Fainelli #define UMAC_IRQ_MDIO_ERROR (1 << 24) 274b4af9a55SFlorian Fainelli 2754055eaefSPetri Gynther /* INTRL2 instance 1 definitions */ 2764055eaefSPetri Gynther #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF 2774055eaefSPetri Gynther #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF 2784055eaefSPetri Gynther #define UMAC_IRQ1_RX_INTR_SHIFT 16 2794055eaefSPetri Gynther 280b4af9a55SFlorian Fainelli /* Register block offsets */ 281b4af9a55SFlorian Fainelli #define GENET_SYS_OFF 0x0000 282b4af9a55SFlorian Fainelli #define GENET_GR_BRIDGE_OFF 0x0040 283b4af9a55SFlorian Fainelli #define GENET_EXT_OFF 0x0080 284b4af9a55SFlorian Fainelli #define GENET_INTRL2_0_OFF 0x0200 285b4af9a55SFlorian Fainelli #define GENET_INTRL2_1_OFF 0x0240 286b4af9a55SFlorian Fainelli #define GENET_RBUF_OFF 0x0300 287b4af9a55SFlorian Fainelli #define GENET_UMAC_OFF 0x0800 288b4af9a55SFlorian Fainelli 289b4af9a55SFlorian Fainelli /* SYS block offsets and register definitions */ 290b4af9a55SFlorian Fainelli #define SYS_REV_CTRL 0x00 291b4af9a55SFlorian Fainelli #define SYS_PORT_CTRL 0x04 292b4af9a55SFlorian Fainelli #define PORT_MODE_INT_EPHY 0 293b4af9a55SFlorian Fainelli #define PORT_MODE_INT_GPHY 1 294b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_EPHY 2 295b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_GPHY 3 296b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 297b4af9a55SFlorian Fainelli #define PORT_MODE_EXT_RVMII_50 4 298b4af9a55SFlorian Fainelli #define LED_ACT_SOURCE_MAC (1 << 9) 299b4af9a55SFlorian Fainelli 300b4af9a55SFlorian Fainelli #define SYS_RBUF_FLUSH_CTRL 0x08 301b4af9a55SFlorian Fainelli #define SYS_TBUF_FLUSH_CTRL 0x0C 302b4af9a55SFlorian Fainelli #define RBUF_FLUSH_CTRL_V1 0x04 303b4af9a55SFlorian Fainelli 304b4af9a55SFlorian Fainelli /* Ext block register offsets and definitions */ 305b4af9a55SFlorian Fainelli #define EXT_EXT_PWR_MGMT 0x00 306b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_BIAS (1 << 0) 307b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_DLL (1 << 1) 308b4af9a55SFlorian Fainelli #define EXT_PWR_DOWN_PHY (1 << 2) 309b4af9a55SFlorian Fainelli #define EXT_PWR_DN_EN_LD (1 << 3) 310b4af9a55SFlorian Fainelli #define EXT_ENERGY_DET (1 << 4) 311b4af9a55SFlorian Fainelli #define EXT_IDDQ_FROM_PHY (1 << 5) 31242138085SDoug Berger #define EXT_IDDQ_GLBL_PWR (1 << 7) 313b4af9a55SFlorian Fainelli #define EXT_PHY_RESET (1 << 8) 314b4af9a55SFlorian Fainelli #define EXT_ENERGY_DET_MASK (1 << 12) 31542138085SDoug Berger #define EXT_PWR_DOWN_PHY_TX (1 << 16) 31642138085SDoug Berger #define EXT_PWR_DOWN_PHY_RX (1 << 17) 31742138085SDoug Berger #define EXT_PWR_DOWN_PHY_SD (1 << 18) 31842138085SDoug Berger #define EXT_PWR_DOWN_PHY_RD (1 << 19) 31942138085SDoug Berger #define EXT_PWR_DOWN_PHY_EN (1 << 20) 320b4af9a55SFlorian Fainelli 321b4af9a55SFlorian Fainelli #define EXT_RGMII_OOB_CTRL 0x0C 322efb86fedSFlorian Fainelli #define RGMII_MODE_EN_V123 (1 << 0) 323b4af9a55SFlorian Fainelli #define RGMII_LINK (1 << 4) 324b4af9a55SFlorian Fainelli #define OOB_DISABLE (1 << 5) 3255a680fadSFlorian Fainelli #define RGMII_MODE_EN (1 << 6) 326b4af9a55SFlorian Fainelli #define ID_MODE_DIS (1 << 16) 327b4af9a55SFlorian Fainelli 328b4af9a55SFlorian Fainelli #define EXT_GPHY_CTRL 0x1C 329b4af9a55SFlorian Fainelli #define EXT_CFG_IDDQ_BIAS (1 << 0) 330b4af9a55SFlorian Fainelli #define EXT_CFG_PWR_DOWN (1 << 1) 3310d017e21SFlorian Fainelli #define EXT_CK25_DIS (1 << 4) 3323cd92eaeSFlorian Fainelli #define EXT_CFG_IDDQ_GLOBAL_PWR (1 << 3) 333b4af9a55SFlorian Fainelli #define EXT_GPHY_RESET (1 << 5) 334b4af9a55SFlorian Fainelli 335b4af9a55SFlorian Fainelli /* DMA rings size */ 336b4af9a55SFlorian Fainelli #define DMA_RING_SIZE (0x40) 337b4af9a55SFlorian Fainelli #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 338b4af9a55SFlorian Fainelli 339b4af9a55SFlorian Fainelli /* DMA registers common definitions */ 340b4af9a55SFlorian Fainelli #define DMA_RW_POINTER_MASK 0x1FF 341b4af9a55SFlorian Fainelli #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 342b4af9a55SFlorian Fainelli #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 343b4af9a55SFlorian Fainelli #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 344b4af9a55SFlorian Fainelli #define DMA_BUFFER_DONE_CNT_SHIFT 16 345b4af9a55SFlorian Fainelli #define DMA_P_INDEX_MASK 0xFFFF 346b4af9a55SFlorian Fainelli #define DMA_C_INDEX_MASK 0xFFFF 347b4af9a55SFlorian Fainelli 348b4af9a55SFlorian Fainelli /* DMA ring size register */ 349b4af9a55SFlorian Fainelli #define DMA_RING_SIZE_MASK 0xFFFF 350b4af9a55SFlorian Fainelli #define DMA_RING_SIZE_SHIFT 16 351b4af9a55SFlorian Fainelli #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 352b4af9a55SFlorian Fainelli 353b4af9a55SFlorian Fainelli /* DMA interrupt threshold register */ 3542f913070SFlorian Fainelli #define DMA_INTR_THRESHOLD_MASK 0x01FF 355b4af9a55SFlorian Fainelli 356b4af9a55SFlorian Fainelli /* DMA XON/XOFF register */ 357b4af9a55SFlorian Fainelli #define DMA_XON_THREHOLD_MASK 0xFFFF 358b4af9a55SFlorian Fainelli #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 359b4af9a55SFlorian Fainelli #define DMA_XOFF_THRESHOLD_SHIFT 16 360b4af9a55SFlorian Fainelli 361b4af9a55SFlorian Fainelli /* DMA flow period register */ 362b4af9a55SFlorian Fainelli #define DMA_FLOW_PERIOD_MASK 0xFFFF 363b4af9a55SFlorian Fainelli #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 364b4af9a55SFlorian Fainelli #define DMA_MAX_PKT_SIZE_SHIFT 16 365b4af9a55SFlorian Fainelli 366b4af9a55SFlorian Fainelli 367b4af9a55SFlorian Fainelli /* DMA control register */ 368b4af9a55SFlorian Fainelli #define DMA_EN (1 << 0) 369b4af9a55SFlorian Fainelli #define DMA_RING_BUF_EN_SHIFT 0x01 370b4af9a55SFlorian Fainelli #define DMA_RING_BUF_EN_MASK 0xFFFF 371b4af9a55SFlorian Fainelli #define DMA_TSB_SWAP_EN (1 << 20) 372b4af9a55SFlorian Fainelli 373b4af9a55SFlorian Fainelli /* DMA status register */ 374b4af9a55SFlorian Fainelli #define DMA_DISABLED (1 << 0) 375b4af9a55SFlorian Fainelli #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 376b4af9a55SFlorian Fainelli 377b4af9a55SFlorian Fainelli /* DMA SCB burst size register */ 378b4af9a55SFlorian Fainelli #define DMA_SCB_BURST_SIZE_MASK 0x1F 379b4af9a55SFlorian Fainelli 380b4af9a55SFlorian Fainelli /* DMA activity vector register */ 381b4af9a55SFlorian Fainelli #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 382b4af9a55SFlorian Fainelli 383b4af9a55SFlorian Fainelli /* DMA backpressure mask register */ 384b4af9a55SFlorian Fainelli #define DMA_BACKPRESSURE_MASK 0x1FFFF 385b4af9a55SFlorian Fainelli #define DMA_PFC_ENABLE (1 << 31) 386b4af9a55SFlorian Fainelli 387b4af9a55SFlorian Fainelli /* DMA backpressure status register */ 388b4af9a55SFlorian Fainelli #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 389b4af9a55SFlorian Fainelli 390b4af9a55SFlorian Fainelli /* DMA override register */ 391b4af9a55SFlorian Fainelli #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 392b4af9a55SFlorian Fainelli #define DMA_REGISTER_MODE (1 << 1) 393b4af9a55SFlorian Fainelli 394b4af9a55SFlorian Fainelli /* DMA timeout register */ 395b4af9a55SFlorian Fainelli #define DMA_TIMEOUT_MASK 0xFFFF 396b4af9a55SFlorian Fainelli #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 397b4af9a55SFlorian Fainelli 398b4af9a55SFlorian Fainelli /* TDMA rate limiting control register */ 399b4af9a55SFlorian Fainelli #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 400b4af9a55SFlorian Fainelli 401b4af9a55SFlorian Fainelli /* TDMA arbitration control register */ 402b4af9a55SFlorian Fainelli #define DMA_ARBITER_MODE_MASK 0x03 403b4af9a55SFlorian Fainelli #define DMA_RING_BUF_PRIORITY_MASK 0x1F 404b4af9a55SFlorian Fainelli #define DMA_RING_BUF_PRIORITY_SHIFT 5 40537742166SPetri Gynther #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 40637742166SPetri Gynther #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 407b4af9a55SFlorian Fainelli #define DMA_RATE_ADJ_MASK 0xFF 408b4af9a55SFlorian Fainelli 409b4af9a55SFlorian Fainelli /* Tx/Rx Dma Descriptor common bits*/ 410b4af9a55SFlorian Fainelli #define DMA_BUFLENGTH_MASK 0x0fff 411b4af9a55SFlorian Fainelli #define DMA_BUFLENGTH_SHIFT 16 412b4af9a55SFlorian Fainelli #define DMA_OWN 0x8000 413b4af9a55SFlorian Fainelli #define DMA_EOP 0x4000 414b4af9a55SFlorian Fainelli #define DMA_SOP 0x2000 415b4af9a55SFlorian Fainelli #define DMA_WRAP 0x1000 416b4af9a55SFlorian Fainelli /* Tx specific Dma descriptor bits */ 417b4af9a55SFlorian Fainelli #define DMA_TX_UNDERRUN 0x0200 418b4af9a55SFlorian Fainelli #define DMA_TX_APPEND_CRC 0x0040 419b4af9a55SFlorian Fainelli #define DMA_TX_OW_CRC 0x0020 420b4af9a55SFlorian Fainelli #define DMA_TX_DO_CSUM 0x0010 421b4af9a55SFlorian Fainelli #define DMA_TX_QTAG_SHIFT 7 422b4af9a55SFlorian Fainelli 423b4af9a55SFlorian Fainelli /* Rx Specific Dma descriptor bits */ 424b4af9a55SFlorian Fainelli #define DMA_RX_CHK_V3PLUS 0x8000 425b4af9a55SFlorian Fainelli #define DMA_RX_CHK_V12 0x1000 426b4af9a55SFlorian Fainelli #define DMA_RX_BRDCAST 0x0040 427b4af9a55SFlorian Fainelli #define DMA_RX_MULT 0x0020 428b4af9a55SFlorian Fainelli #define DMA_RX_LG 0x0010 429b4af9a55SFlorian Fainelli #define DMA_RX_NO 0x0008 430b4af9a55SFlorian Fainelli #define DMA_RX_RXER 0x0004 431b4af9a55SFlorian Fainelli #define DMA_RX_CRC_ERROR 0x0002 432b4af9a55SFlorian Fainelli #define DMA_RX_OV 0x0001 433b4af9a55SFlorian Fainelli #define DMA_RX_FI_MASK 0x001F 434b4af9a55SFlorian Fainelli #define DMA_RX_FI_SHIFT 0x0007 435b4af9a55SFlorian Fainelli #define DMA_DESC_ALLOC_MASK 0x00FF 436b4af9a55SFlorian Fainelli 437b4af9a55SFlorian Fainelli #define DMA_ARBITER_RR 0x00 438b4af9a55SFlorian Fainelli #define DMA_ARBITER_WRR 0x01 439b4af9a55SFlorian Fainelli #define DMA_ARBITER_SP 0x02 440b4af9a55SFlorian Fainelli 441b4af9a55SFlorian Fainelli struct enet_cb { 442b4af9a55SFlorian Fainelli struct sk_buff *skb; 443b4af9a55SFlorian Fainelli void __iomem *bd_addr; 444b4af9a55SFlorian Fainelli DEFINE_DMA_UNMAP_ADDR(dma_addr); 445b4af9a55SFlorian Fainelli DEFINE_DMA_UNMAP_LEN(dma_len); 446b4af9a55SFlorian Fainelli }; 447b4af9a55SFlorian Fainelli 448b4af9a55SFlorian Fainelli /* power management mode */ 449b4af9a55SFlorian Fainelli enum bcmgenet_power_mode { 450b4af9a55SFlorian Fainelli GENET_POWER_CABLE_SENSE = 0, 451b4af9a55SFlorian Fainelli GENET_POWER_PASSIVE, 452c51de7f3SFlorian Fainelli GENET_POWER_WOL_MAGIC, 453b4af9a55SFlorian Fainelli }; 454b4af9a55SFlorian Fainelli 455b4af9a55SFlorian Fainelli struct bcmgenet_priv; 456b4af9a55SFlorian Fainelli 457b4af9a55SFlorian Fainelli /* We support both runtime GENET detection and compile-time 458b4af9a55SFlorian Fainelli * to optimize code-paths for a given hardware 459b4af9a55SFlorian Fainelli */ 460b4af9a55SFlorian Fainelli enum bcmgenet_version { 461b4af9a55SFlorian Fainelli GENET_V1 = 1, 462b4af9a55SFlorian Fainelli GENET_V2, 463b4af9a55SFlorian Fainelli GENET_V3, 46442138085SDoug Berger GENET_V4, 46542138085SDoug Berger GENET_V5 466b4af9a55SFlorian Fainelli }; 467b4af9a55SFlorian Fainelli 468b4af9a55SFlorian Fainelli #define GENET_IS_V1(p) ((p)->version == GENET_V1) 469b4af9a55SFlorian Fainelli #define GENET_IS_V2(p) ((p)->version == GENET_V2) 470b4af9a55SFlorian Fainelli #define GENET_IS_V3(p) ((p)->version == GENET_V3) 471b4af9a55SFlorian Fainelli #define GENET_IS_V4(p) ((p)->version == GENET_V4) 47242138085SDoug Berger #define GENET_IS_V5(p) ((p)->version == GENET_V5) 473b4af9a55SFlorian Fainelli 474b4af9a55SFlorian Fainelli /* Hardware flags */ 475b4af9a55SFlorian Fainelli #define GENET_HAS_40BITS (1 << 0) 476b4af9a55SFlorian Fainelli #define GENET_HAS_EXT (1 << 1) 477b4af9a55SFlorian Fainelli #define GENET_HAS_MDIO_INTR (1 << 2) 4788d88c6ebSPetri Gynther #define GENET_HAS_MOCA_LINK_DET (1 << 3) 479b4af9a55SFlorian Fainelli 480b4af9a55SFlorian Fainelli /* BCMGENET hardware parameters, keep this structure nicely aligned 481b4af9a55SFlorian Fainelli * since it is going to be used in hot paths 482b4af9a55SFlorian Fainelli */ 483b4af9a55SFlorian Fainelli struct bcmgenet_hw_params { 484b4af9a55SFlorian Fainelli u8 tx_queues; 48551a966a7SPetri Gynther u8 tx_bds_per_q; 486b4af9a55SFlorian Fainelli u8 rx_queues; 4873feafa02SPetri Gynther u8 rx_bds_per_q; 488b4af9a55SFlorian Fainelli u8 bp_in_en_shift; 489b4af9a55SFlorian Fainelli u32 bp_in_mask; 490b4af9a55SFlorian Fainelli u8 hfb_filter_cnt; 4910034de41SPetri Gynther u8 hfb_filter_size; 492b4af9a55SFlorian Fainelli u8 qtag_mask; 493b4af9a55SFlorian Fainelli u16 tbuf_offset; 494b4af9a55SFlorian Fainelli u32 hfb_offset; 495b4af9a55SFlorian Fainelli u32 hfb_reg_offset; 496b4af9a55SFlorian Fainelli u32 rdma_offset; 497b4af9a55SFlorian Fainelli u32 tdma_offset; 498b4af9a55SFlorian Fainelli u32 words_per_bd; 499b4af9a55SFlorian Fainelli u32 flags; 500b4af9a55SFlorian Fainelli }; 501b4af9a55SFlorian Fainelli 50255868120SPetri Gynther struct bcmgenet_skb_cb { 503f48bed16SDoug Berger struct enet_cb *first_cb; /* First control block of SKB */ 504f48bed16SDoug Berger struct enet_cb *last_cb; /* Last control block of SKB */ 50555868120SPetri Gynther unsigned int bytes_sent; /* bytes on the wire (no TSB) */ 50655868120SPetri Gynther }; 50755868120SPetri Gynther 50855868120SPetri Gynther #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb)) 50955868120SPetri Gynther 510b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring { 511b4af9a55SFlorian Fainelli spinlock_t lock; /* ring lock */ 5124092e6acSJaedon Shin struct napi_struct napi; /* NAPI per tx queue */ 51337a30b43SFlorian Fainelli unsigned long packets; 51437a30b43SFlorian Fainelli unsigned long bytes; 515b4af9a55SFlorian Fainelli unsigned int index; /* ring index */ 516b4af9a55SFlorian Fainelli unsigned int queue; /* queue index */ 517b4af9a55SFlorian Fainelli struct enet_cb *cbs; /* tx ring buffer control block*/ 518b4af9a55SFlorian Fainelli unsigned int size; /* size of each tx ring */ 51966d06757SPetri Gynther unsigned int clean_ptr; /* Tx ring clean pointer */ 520b4af9a55SFlorian Fainelli unsigned int c_index; /* last consumer index of each ring*/ 521b4af9a55SFlorian Fainelli unsigned int free_bds; /* # of free bds for each ring */ 522b4af9a55SFlorian Fainelli unsigned int write_ptr; /* Tx ring write pointer SW copy */ 523b4af9a55SFlorian Fainelli unsigned int prod_index; /* Tx ring producer index SW copy */ 524b4af9a55SFlorian Fainelli unsigned int cb_ptr; /* Tx ring initial CB ptr */ 525b4af9a55SFlorian Fainelli unsigned int end_ptr; /* Tx ring end CB ptr */ 5269dbac28fSPetri Gynther void (*int_enable)(struct bcmgenet_tx_ring *); 5279dbac28fSPetri Gynther void (*int_disable)(struct bcmgenet_tx_ring *); 5284092e6acSJaedon Shin struct bcmgenet_priv *priv; 529b4af9a55SFlorian Fainelli }; 530b4af9a55SFlorian Fainelli 5319f4ca058SFlorian Fainelli struct bcmgenet_net_dim { 5329f4ca058SFlorian Fainelli u16 use_dim; 5339f4ca058SFlorian Fainelli u16 event_ctr; 5349f4ca058SFlorian Fainelli unsigned long packets; 5359f4ca058SFlorian Fainelli unsigned long bytes; 5368960b389STal Gilboa struct dim dim; 5379f4ca058SFlorian Fainelli }; 5389f4ca058SFlorian Fainelli 5398ac467e8SPetri Gynther struct bcmgenet_rx_ring { 5404055eaefSPetri Gynther struct napi_struct napi; /* Rx NAPI struct */ 54137a30b43SFlorian Fainelli unsigned long bytes; 54237a30b43SFlorian Fainelli unsigned long packets; 54337a30b43SFlorian Fainelli unsigned long errors; 54437a30b43SFlorian Fainelli unsigned long dropped; 5458ac467e8SPetri Gynther unsigned int index; /* Rx ring index */ 5468ac467e8SPetri Gynther struct enet_cb *cbs; /* Rx ring buffer control block */ 5478ac467e8SPetri Gynther unsigned int size; /* Rx ring size */ 5488ac467e8SPetri Gynther unsigned int c_index; /* Rx last consumer index */ 5498ac467e8SPetri Gynther unsigned int read_ptr; /* Rx ring read pointer */ 5508ac467e8SPetri Gynther unsigned int cb_ptr; /* Rx ring initial CB ptr */ 5518ac467e8SPetri Gynther unsigned int end_ptr; /* Rx ring end CB ptr */ 552d26ea6ccSPetri Gynther unsigned int old_discards; 5539f4ca058SFlorian Fainelli struct bcmgenet_net_dim dim; 5545e6ce1f1SFlorian Fainelli u32 rx_max_coalesced_frames; 5555e6ce1f1SFlorian Fainelli u32 rx_coalesce_usecs; 5564055eaefSPetri Gynther void (*int_enable)(struct bcmgenet_rx_ring *); 5574055eaefSPetri Gynther void (*int_disable)(struct bcmgenet_rx_ring *); 5584055eaefSPetri Gynther struct bcmgenet_priv *priv; 5598ac467e8SPetri Gynther }; 5608ac467e8SPetri Gynther 5613e370952SDoug Berger enum bcmgenet_rxnfc_state { 5623e370952SDoug Berger BCMGENET_RXNFC_STATE_UNUSED = 0, 5633e370952SDoug Berger BCMGENET_RXNFC_STATE_DISABLED, 5643e370952SDoug Berger BCMGENET_RXNFC_STATE_ENABLED 5653e370952SDoug Berger }; 5663e370952SDoug Berger 5673e370952SDoug Berger struct bcmgenet_rxnfc_rule { 5683e370952SDoug Berger struct list_head list; 5693e370952SDoug Berger struct ethtool_rx_flow_spec fs; 5703e370952SDoug Berger enum bcmgenet_rxnfc_state state; 5713e370952SDoug Berger }; 5723e370952SDoug Berger 573b4af9a55SFlorian Fainelli /* device context */ 574b4af9a55SFlorian Fainelli struct bcmgenet_priv { 575b4af9a55SFlorian Fainelli void __iomem *base; 57600d1a1bcSDoug Berger /* reg_lock: lock to serialize access to shared registers */ 57700d1a1bcSDoug Berger spinlock_t reg_lock; 578b4af9a55SFlorian Fainelli enum bcmgenet_version version; 579b4af9a55SFlorian Fainelli struct net_device *dev; 580b4af9a55SFlorian Fainelli 581b4af9a55SFlorian Fainelli /* transmit variables */ 582b4af9a55SFlorian Fainelli void __iomem *tx_bds; 583b4af9a55SFlorian Fainelli struct enet_cb *tx_cbs; 584b4af9a55SFlorian Fainelli unsigned int num_tx_bds; 585b4af9a55SFlorian Fainelli 586b4af9a55SFlorian Fainelli struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; 587b4af9a55SFlorian Fainelli 588b4af9a55SFlorian Fainelli /* receive variables */ 589b4af9a55SFlorian Fainelli void __iomem *rx_bds; 590b4af9a55SFlorian Fainelli struct enet_cb *rx_cbs; 591b4af9a55SFlorian Fainelli unsigned int num_rx_bds; 592b4af9a55SFlorian Fainelli unsigned int rx_buf_len; 5933e370952SDoug Berger struct bcmgenet_rxnfc_rule rxnfc_rules[MAX_NUM_OF_FS_RULES]; 5943e370952SDoug Berger struct list_head rxnfc_list; 5958ac467e8SPetri Gynther 5968ac467e8SPetri Gynther struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1]; 597b4af9a55SFlorian Fainelli 598b4af9a55SFlorian Fainelli /* other misc variables */ 599b4af9a55SFlorian Fainelli struct bcmgenet_hw_params *hw_params; 6002d8bdf52SDoug Berger unsigned autoneg_pause:1; 6012d8bdf52SDoug Berger unsigned tx_pause:1; 6022d8bdf52SDoug Berger unsigned rx_pause:1; 603b4af9a55SFlorian Fainelli 604b4af9a55SFlorian Fainelli /* MDIO bus variables */ 605b4af9a55SFlorian Fainelli wait_queue_head_t wq; 606c624f891SFlorian Fainelli bool internal_phy; 607b4af9a55SFlorian Fainelli struct device_node *phy_dn; 6087b635da8SFlorian Fainelli struct device_node *mdio_dn; 609b4af9a55SFlorian Fainelli struct mii_bus *mii_bus; 610487320c5SFlorian Fainelli u16 gphy_rev; 6116ef398eaSFlorian Fainelli struct clk *clk_eee; 6126ef398eaSFlorian Fainelli bool clk_eee_enabled; 613b4af9a55SFlorian Fainelli 614b4af9a55SFlorian Fainelli /* PHY device variables */ 615b4af9a55SFlorian Fainelli phy_interface_t phy_interface; 616b4af9a55SFlorian Fainelli int phy_addr; 617b4af9a55SFlorian Fainelli int ext_phy; 6183cd92eaeSFlorian Fainelli bool ephy_16nm; 619b4af9a55SFlorian Fainelli 620b4af9a55SFlorian Fainelli /* Interrupt variables */ 621b4af9a55SFlorian Fainelli struct work_struct bcmgenet_irq_work; 622b4af9a55SFlorian Fainelli int irq0; 623b4af9a55SFlorian Fainelli int irq1; 6248562056fSFlorian Fainelli int wol_irq; 6258562056fSFlorian Fainelli bool wol_irq_disabled; 626b4af9a55SFlorian Fainelli 62707c52d6aSDoug Berger /* shared status */ 62807c52d6aSDoug Berger spinlock_t lock; 62907c52d6aSDoug Berger unsigned int irq0_stat; 63007c52d6aSDoug Berger 631b4af9a55SFlorian Fainelli /* HW descriptors/checksum variables */ 632b4af9a55SFlorian Fainelli bool crc_fwd_en; 633b4af9a55SFlorian Fainelli 634a50e3a99SStefan Wahren u32 dma_max_burst_length; 635b4af9a55SFlorian Fainelli 636b4af9a55SFlorian Fainelli u32 msg_enable; 637b4af9a55SFlorian Fainelli 638b4af9a55SFlorian Fainelli struct clk *clk; 639b4af9a55SFlorian Fainelli struct platform_device *pdev; 6409a4e7969SFlorian Fainelli struct platform_device *mii_pdev; 641b4af9a55SFlorian Fainelli 642b4af9a55SFlorian Fainelli /* WOL */ 643b4af9a55SFlorian Fainelli struct clk *clk_wol; 644b4af9a55SFlorian Fainelli u32 wolopts; 6456f768905SDoug Berger u8 sopass[SOPASS_MAX]; 6461a1d5106SDoug Berger bool wol_active; 647b4af9a55SFlorian Fainelli 648b4af9a55SFlorian Fainelli struct bcmgenet_mib_counters mib; 6496ef398eaSFlorian Fainelli 6506ef398eaSFlorian Fainelli struct ethtool_eee eee; 651b4af9a55SFlorian Fainelli }; 652b4af9a55SFlorian Fainelli 653b4af9a55SFlorian Fainelli #define GENET_IO_MACRO(name, offset) \ 654b4af9a55SFlorian Fainelli static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 655b4af9a55SFlorian Fainelli u32 off) \ 656b4af9a55SFlorian Fainelli { \ 65769d2ea9cSFlorian Fainelli /* MIPS chips strapped for BE will automagically configure the \ 65869d2ea9cSFlorian Fainelli * peripheral registers for CPU-native byte order. \ 65969d2ea9cSFlorian Fainelli */ \ 66069d2ea9cSFlorian Fainelli if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 661b4af9a55SFlorian Fainelli return __raw_readl(priv->base + offset + off); \ 66269d2ea9cSFlorian Fainelli else \ 66369d2ea9cSFlorian Fainelli return readl_relaxed(priv->base + offset + off); \ 664b4af9a55SFlorian Fainelli } \ 665b4af9a55SFlorian Fainelli static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 666b4af9a55SFlorian Fainelli u32 val, u32 off) \ 667b4af9a55SFlorian Fainelli { \ 66869d2ea9cSFlorian Fainelli if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 669d081a16dSFlorian Fainelli __raw_writel(val, priv->base + offset + off); \ 67069d2ea9cSFlorian Fainelli else \ 67169d2ea9cSFlorian Fainelli writel_relaxed(val, priv->base + offset + off); \ 672b4af9a55SFlorian Fainelli } 673b4af9a55SFlorian Fainelli 674b4af9a55SFlorian Fainelli GENET_IO_MACRO(ext, GENET_EXT_OFF); 675b4af9a55SFlorian Fainelli GENET_IO_MACRO(umac, GENET_UMAC_OFF); 676b4af9a55SFlorian Fainelli GENET_IO_MACRO(sys, GENET_SYS_OFF); 677b4af9a55SFlorian Fainelli 678b4af9a55SFlorian Fainelli /* interrupt l2 registers accessors */ 679b4af9a55SFlorian Fainelli GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 680b4af9a55SFlorian Fainelli GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 681b4af9a55SFlorian Fainelli 682b4af9a55SFlorian Fainelli /* HFB register accessors */ 683b4af9a55SFlorian Fainelli GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 684b4af9a55SFlorian Fainelli 685b4af9a55SFlorian Fainelli /* GENET v2+ HFB control and filter len helpers */ 686b4af9a55SFlorian Fainelli GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 687b4af9a55SFlorian Fainelli 688b4af9a55SFlorian Fainelli /* RBUF register accessors */ 689b4af9a55SFlorian Fainelli GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 690b4af9a55SFlorian Fainelli 691b4af9a55SFlorian Fainelli /* MDIO routines */ 692b4af9a55SFlorian Fainelli int bcmgenet_mii_init(struct net_device *dev); 69300d51094SFlorian Fainelli int bcmgenet_mii_config(struct net_device *dev, bool init); 6946b6d017fSDoug Berger int bcmgenet_mii_probe(struct net_device *dev); 695b4af9a55SFlorian Fainelli void bcmgenet_mii_exit(struct net_device *dev); 6962d8bdf52SDoug Berger void bcmgenet_phy_pause_set(struct net_device *dev, bool rx, bool tx); 697a642c4f7SFlorian Fainelli void bcmgenet_phy_power_set(struct net_device *dev, bool enable); 698c96e731cSFlorian Fainelli void bcmgenet_mii_setup(struct net_device *dev); 699b4af9a55SFlorian Fainelli 700c51de7f3SFlorian Fainelli /* Wake-on-LAN routines */ 701c51de7f3SFlorian Fainelli void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 702c51de7f3SFlorian Fainelli int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 703c51de7f3SFlorian Fainelli int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 704c51de7f3SFlorian Fainelli enum bcmgenet_power_mode mode); 705c51de7f3SFlorian Fainelli void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 706c51de7f3SFlorian Fainelli enum bcmgenet_power_mode mode); 707c51de7f3SFlorian Fainelli 708a9f31047SFlorian Fainelli void bcmgenet_eee_enable_set(struct net_device *dev, bool enable, 709a9f31047SFlorian Fainelli bool tx_lpi_enabled); 710a9f31047SFlorian Fainelli 711b4af9a55SFlorian Fainelli #endif /* __BCMGENET_H__ */ 712