1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2020 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 #include <linux/platform_data/bcmgenet.h> 39 40 #include <asm/unaligned.h> 41 42 #include "bcmgenet.h" 43 44 /* Maximum number of hardware queues, downsized if needed */ 45 #define GENET_MAX_MQ_CNT 4 46 47 /* Default highest priority queue for multi queue support */ 48 #define GENET_Q0_PRIORITY 0 49 50 #define GENET_Q16_RX_BD_CNT \ 51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 52 #define GENET_Q16_TX_BD_CNT \ 53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 54 55 #define RX_BUF_LENGTH 2048 56 #define SKB_ALIGNMENT 32 57 58 /* Tx/Rx DMA register offset, skip 256 descriptors */ 59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 61 62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 66 TOTAL_DESC * DMA_DESC_SIZE) 67 68 /* Forward declarations */ 69 static void bcmgenet_set_rx_mode(struct net_device *dev); 70 71 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 72 { 73 /* MIPS chips strapped for BE will automagically configure the 74 * peripheral registers for CPU-native byte order. 75 */ 76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 77 __raw_writel(value, offset); 78 else 79 writel_relaxed(value, offset); 80 } 81 82 static inline u32 bcmgenet_readl(void __iomem *offset) 83 { 84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 85 return __raw_readl(offset); 86 else 87 return readl_relaxed(offset); 88 } 89 90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 91 void __iomem *d, u32 value) 92 { 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 94 } 95 96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 97 void __iomem *d, 98 dma_addr_t addr) 99 { 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 101 102 /* Register writes to GISB bus can take couple hundred nanoseconds 103 * and are done for each packet, save these expensive writes unless 104 * the platform is explicitly configured for 64-bits/LPAE. 105 */ 106 #ifdef CONFIG_PHYS_ADDR_T_64BIT 107 if (priv->hw_params->flags & GENET_HAS_40BITS) 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 109 #endif 110 } 111 112 /* Combined address + length/status setter */ 113 static inline void dmadesc_set(struct bcmgenet_priv *priv, 114 void __iomem *d, dma_addr_t addr, u32 val) 115 { 116 dmadesc_set_addr(priv, d, addr); 117 dmadesc_set_length_status(priv, d, val); 118 } 119 120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 121 void __iomem *d) 122 { 123 dma_addr_t addr; 124 125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 126 127 /* Register writes to GISB bus can take couple hundred nanoseconds 128 * and are done for each packet, save these expensive writes unless 129 * the platform is explicitly configured for 64-bits/LPAE. 130 */ 131 #ifdef CONFIG_PHYS_ADDR_T_64BIT 132 if (priv->hw_params->flags & GENET_HAS_40BITS) 133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 134 #endif 135 return addr; 136 } 137 138 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 139 140 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 141 NETIF_MSG_LINK) 142 143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 144 { 145 if (GENET_IS_V1(priv)) 146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 147 else 148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 149 } 150 151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152 { 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 155 else 156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 157 } 158 159 /* These macros are defined to deal with register map change 160 * between GENET1.1 and GENET2. Only those currently being used 161 * by driver are defined. 162 */ 163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 164 { 165 if (GENET_IS_V1(priv)) 166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 167 else 168 return bcmgenet_readl(priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 173 { 174 if (GENET_IS_V1(priv)) 175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 176 else 177 bcmgenet_writel(val, priv->base + 178 priv->hw_params->tbuf_offset + TBUF_CTRL); 179 } 180 181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 182 { 183 if (GENET_IS_V1(priv)) 184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 185 else 186 return bcmgenet_readl(priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 191 { 192 if (GENET_IS_V1(priv)) 193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 194 else 195 bcmgenet_writel(val, priv->base + 196 priv->hw_params->tbuf_offset + TBUF_BP_MC); 197 } 198 199 /* RX/TX DMA register accessors */ 200 enum dma_reg { 201 DMA_RING_CFG = 0, 202 DMA_CTRL, 203 DMA_STATUS, 204 DMA_SCB_BURST_SIZE, 205 DMA_ARB_CTRL, 206 DMA_PRIORITY_0, 207 DMA_PRIORITY_1, 208 DMA_PRIORITY_2, 209 DMA_INDEX2RING_0, 210 DMA_INDEX2RING_1, 211 DMA_INDEX2RING_2, 212 DMA_INDEX2RING_3, 213 DMA_INDEX2RING_4, 214 DMA_INDEX2RING_5, 215 DMA_INDEX2RING_6, 216 DMA_INDEX2RING_7, 217 DMA_RING0_TIMEOUT, 218 DMA_RING1_TIMEOUT, 219 DMA_RING2_TIMEOUT, 220 DMA_RING3_TIMEOUT, 221 DMA_RING4_TIMEOUT, 222 DMA_RING5_TIMEOUT, 223 DMA_RING6_TIMEOUT, 224 DMA_RING7_TIMEOUT, 225 DMA_RING8_TIMEOUT, 226 DMA_RING9_TIMEOUT, 227 DMA_RING10_TIMEOUT, 228 DMA_RING11_TIMEOUT, 229 DMA_RING12_TIMEOUT, 230 DMA_RING13_TIMEOUT, 231 DMA_RING14_TIMEOUT, 232 DMA_RING15_TIMEOUT, 233 DMA_RING16_TIMEOUT, 234 }; 235 236 static const u8 bcmgenet_dma_regs_v3plus[] = { 237 [DMA_RING_CFG] = 0x00, 238 [DMA_CTRL] = 0x04, 239 [DMA_STATUS] = 0x08, 240 [DMA_SCB_BURST_SIZE] = 0x0C, 241 [DMA_ARB_CTRL] = 0x2C, 242 [DMA_PRIORITY_0] = 0x30, 243 [DMA_PRIORITY_1] = 0x34, 244 [DMA_PRIORITY_2] = 0x38, 245 [DMA_RING0_TIMEOUT] = 0x2C, 246 [DMA_RING1_TIMEOUT] = 0x30, 247 [DMA_RING2_TIMEOUT] = 0x34, 248 [DMA_RING3_TIMEOUT] = 0x38, 249 [DMA_RING4_TIMEOUT] = 0x3c, 250 [DMA_RING5_TIMEOUT] = 0x40, 251 [DMA_RING6_TIMEOUT] = 0x44, 252 [DMA_RING7_TIMEOUT] = 0x48, 253 [DMA_RING8_TIMEOUT] = 0x4c, 254 [DMA_RING9_TIMEOUT] = 0x50, 255 [DMA_RING10_TIMEOUT] = 0x54, 256 [DMA_RING11_TIMEOUT] = 0x58, 257 [DMA_RING12_TIMEOUT] = 0x5c, 258 [DMA_RING13_TIMEOUT] = 0x60, 259 [DMA_RING14_TIMEOUT] = 0x64, 260 [DMA_RING15_TIMEOUT] = 0x68, 261 [DMA_RING16_TIMEOUT] = 0x6C, 262 [DMA_INDEX2RING_0] = 0x70, 263 [DMA_INDEX2RING_1] = 0x74, 264 [DMA_INDEX2RING_2] = 0x78, 265 [DMA_INDEX2RING_3] = 0x7C, 266 [DMA_INDEX2RING_4] = 0x80, 267 [DMA_INDEX2RING_5] = 0x84, 268 [DMA_INDEX2RING_6] = 0x88, 269 [DMA_INDEX2RING_7] = 0x8C, 270 }; 271 272 static const u8 bcmgenet_dma_regs_v2[] = { 273 [DMA_RING_CFG] = 0x00, 274 [DMA_CTRL] = 0x04, 275 [DMA_STATUS] = 0x08, 276 [DMA_SCB_BURST_SIZE] = 0x0C, 277 [DMA_ARB_CTRL] = 0x30, 278 [DMA_PRIORITY_0] = 0x34, 279 [DMA_PRIORITY_1] = 0x38, 280 [DMA_PRIORITY_2] = 0x3C, 281 [DMA_RING0_TIMEOUT] = 0x2C, 282 [DMA_RING1_TIMEOUT] = 0x30, 283 [DMA_RING2_TIMEOUT] = 0x34, 284 [DMA_RING3_TIMEOUT] = 0x38, 285 [DMA_RING4_TIMEOUT] = 0x3c, 286 [DMA_RING5_TIMEOUT] = 0x40, 287 [DMA_RING6_TIMEOUT] = 0x44, 288 [DMA_RING7_TIMEOUT] = 0x48, 289 [DMA_RING8_TIMEOUT] = 0x4c, 290 [DMA_RING9_TIMEOUT] = 0x50, 291 [DMA_RING10_TIMEOUT] = 0x54, 292 [DMA_RING11_TIMEOUT] = 0x58, 293 [DMA_RING12_TIMEOUT] = 0x5c, 294 [DMA_RING13_TIMEOUT] = 0x60, 295 [DMA_RING14_TIMEOUT] = 0x64, 296 [DMA_RING15_TIMEOUT] = 0x68, 297 [DMA_RING16_TIMEOUT] = 0x6C, 298 }; 299 300 static const u8 bcmgenet_dma_regs_v1[] = { 301 [DMA_CTRL] = 0x00, 302 [DMA_STATUS] = 0x04, 303 [DMA_SCB_BURST_SIZE] = 0x0C, 304 [DMA_ARB_CTRL] = 0x30, 305 [DMA_PRIORITY_0] = 0x34, 306 [DMA_PRIORITY_1] = 0x38, 307 [DMA_PRIORITY_2] = 0x3C, 308 [DMA_RING0_TIMEOUT] = 0x2C, 309 [DMA_RING1_TIMEOUT] = 0x30, 310 [DMA_RING2_TIMEOUT] = 0x34, 311 [DMA_RING3_TIMEOUT] = 0x38, 312 [DMA_RING4_TIMEOUT] = 0x3c, 313 [DMA_RING5_TIMEOUT] = 0x40, 314 [DMA_RING6_TIMEOUT] = 0x44, 315 [DMA_RING7_TIMEOUT] = 0x48, 316 [DMA_RING8_TIMEOUT] = 0x4c, 317 [DMA_RING9_TIMEOUT] = 0x50, 318 [DMA_RING10_TIMEOUT] = 0x54, 319 [DMA_RING11_TIMEOUT] = 0x58, 320 [DMA_RING12_TIMEOUT] = 0x5c, 321 [DMA_RING13_TIMEOUT] = 0x60, 322 [DMA_RING14_TIMEOUT] = 0x64, 323 [DMA_RING15_TIMEOUT] = 0x68, 324 [DMA_RING16_TIMEOUT] = 0x6C, 325 }; 326 327 /* Set at runtime once bcmgenet version is known */ 328 static const u8 *bcmgenet_dma_regs; 329 330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 331 { 332 return netdev_priv(dev_get_drvdata(dev)); 333 } 334 335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 336 enum dma_reg r) 337 { 338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340 } 341 342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 343 u32 val, enum dma_reg r) 344 { 345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 347 } 348 349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 350 enum dma_reg r) 351 { 352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 354 } 355 356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 357 u32 val, enum dma_reg r) 358 { 359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 361 } 362 363 /* RDMA/TDMA ring registers and accessors 364 * we merge the common fields and just prefix with T/D the registers 365 * having different meaning depending on the direction 366 */ 367 enum dma_ring_reg { 368 TDMA_READ_PTR = 0, 369 RDMA_WRITE_PTR = TDMA_READ_PTR, 370 TDMA_READ_PTR_HI, 371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 372 TDMA_CONS_INDEX, 373 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 374 TDMA_PROD_INDEX, 375 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 376 DMA_RING_BUF_SIZE, 377 DMA_START_ADDR, 378 DMA_START_ADDR_HI, 379 DMA_END_ADDR, 380 DMA_END_ADDR_HI, 381 DMA_MBUF_DONE_THRESH, 382 TDMA_FLOW_PERIOD, 383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 384 TDMA_WRITE_PTR, 385 RDMA_READ_PTR = TDMA_WRITE_PTR, 386 TDMA_WRITE_PTR_HI, 387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 388 }; 389 390 /* GENET v4 supports 40-bits pointer addressing 391 * for obvious reasons the LO and HI word parts 392 * are contiguous, but this offsets the other 393 * registers. 394 */ 395 static const u8 genet_dma_ring_regs_v4[] = { 396 [TDMA_READ_PTR] = 0x00, 397 [TDMA_READ_PTR_HI] = 0x04, 398 [TDMA_CONS_INDEX] = 0x08, 399 [TDMA_PROD_INDEX] = 0x0C, 400 [DMA_RING_BUF_SIZE] = 0x10, 401 [DMA_START_ADDR] = 0x14, 402 [DMA_START_ADDR_HI] = 0x18, 403 [DMA_END_ADDR] = 0x1C, 404 [DMA_END_ADDR_HI] = 0x20, 405 [DMA_MBUF_DONE_THRESH] = 0x24, 406 [TDMA_FLOW_PERIOD] = 0x28, 407 [TDMA_WRITE_PTR] = 0x2C, 408 [TDMA_WRITE_PTR_HI] = 0x30, 409 }; 410 411 static const u8 genet_dma_ring_regs_v123[] = { 412 [TDMA_READ_PTR] = 0x00, 413 [TDMA_CONS_INDEX] = 0x04, 414 [TDMA_PROD_INDEX] = 0x08, 415 [DMA_RING_BUF_SIZE] = 0x0C, 416 [DMA_START_ADDR] = 0x10, 417 [DMA_END_ADDR] = 0x14, 418 [DMA_MBUF_DONE_THRESH] = 0x18, 419 [TDMA_FLOW_PERIOD] = 0x1C, 420 [TDMA_WRITE_PTR] = 0x20, 421 }; 422 423 /* Set at runtime once GENET version is known */ 424 static const u8 *genet_dma_ring_regs; 425 426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 427 unsigned int ring, 428 enum dma_ring_reg r) 429 { 430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433 } 434 435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 436 unsigned int ring, u32 val, 437 enum dma_ring_reg r) 438 { 439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442 } 443 444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 445 unsigned int ring, 446 enum dma_ring_reg r) 447 { 448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451 } 452 453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 454 unsigned int ring, u32 val, 455 enum dma_ring_reg r) 456 { 457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 458 (DMA_RING_SIZE * ring) + 459 genet_dma_ring_regs[r]); 460 } 461 462 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv, 463 u32 f_index) 464 { 465 u32 offset; 466 u32 reg; 467 468 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 469 reg = bcmgenet_hfb_reg_readl(priv, offset); 470 return !!(reg & (1 << (f_index % 32))); 471 } 472 473 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 474 { 475 u32 offset; 476 u32 reg; 477 478 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 479 reg = bcmgenet_hfb_reg_readl(priv, offset); 480 reg |= (1 << (f_index % 32)); 481 bcmgenet_hfb_reg_writel(priv, reg, offset); 482 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 483 reg |= RBUF_HFB_EN; 484 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 485 } 486 487 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 488 { 489 u32 offset, reg, reg1; 490 491 offset = HFB_FLT_ENABLE_V3PLUS; 492 reg = bcmgenet_hfb_reg_readl(priv, offset); 493 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 494 if (f_index < 32) { 495 reg1 &= ~(1 << (f_index % 32)); 496 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 497 } else { 498 reg &= ~(1 << (f_index % 32)); 499 bcmgenet_hfb_reg_writel(priv, reg, offset); 500 } 501 if (!reg && !reg1) { 502 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 503 reg &= ~RBUF_HFB_EN; 504 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 505 } 506 } 507 508 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 509 u32 f_index, u32 rx_queue) 510 { 511 u32 offset; 512 u32 reg; 513 514 offset = f_index / 8; 515 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 516 reg &= ~(0xF << (4 * (f_index % 8))); 517 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 518 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 519 } 520 521 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 522 u32 f_index, u32 f_length) 523 { 524 u32 offset; 525 u32 reg; 526 527 offset = HFB_FLT_LEN_V3PLUS + 528 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) * 529 sizeof(u32); 530 reg = bcmgenet_hfb_reg_readl(priv, offset); 531 reg &= ~(0xFF << (8 * (f_index % 4))); 532 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 533 bcmgenet_hfb_reg_writel(priv, reg, offset); 534 } 535 536 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv) 537 { 538 u32 f_index; 539 540 /* First MAX_NUM_OF_FS_RULES are reserved for Rx NFC filters */ 541 for (f_index = MAX_NUM_OF_FS_RULES; 542 f_index < priv->hw_params->hfb_filter_cnt; f_index++) 543 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index)) 544 return f_index; 545 546 return -ENOMEM; 547 } 548 549 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 550 { 551 while (size) { 552 switch (*(unsigned char *)mask++) { 553 case 0x00: 554 case 0x0f: 555 case 0xf0: 556 case 0xff: 557 size--; 558 continue; 559 default: 560 return -EINVAL; 561 } 562 } 563 564 return 0; 565 } 566 567 #define VALIDATE_MASK(x) \ 568 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 569 570 static int bcmgenet_hfb_insert_data(u32 *f, int offset, 571 void *val, void *mask, size_t size) 572 { 573 int index; 574 u32 tmp; 575 576 index = offset / 2; 577 tmp = f[index]; 578 579 while (size--) { 580 if (offset++ & 1) { 581 tmp &= ~0x300FF; 582 tmp |= (*(unsigned char *)val++); 583 switch ((*(unsigned char *)mask++)) { 584 case 0xFF: 585 tmp |= 0x30000; 586 break; 587 case 0xF0: 588 tmp |= 0x20000; 589 break; 590 case 0x0F: 591 tmp |= 0x10000; 592 break; 593 } 594 f[index++] = tmp; 595 if (size) 596 tmp = f[index]; 597 } else { 598 tmp &= ~0xCFF00; 599 tmp |= (*(unsigned char *)val++) << 8; 600 switch ((*(unsigned char *)mask++)) { 601 case 0xFF: 602 tmp |= 0xC0000; 603 break; 604 case 0xF0: 605 tmp |= 0x80000; 606 break; 607 case 0x0F: 608 tmp |= 0x40000; 609 break; 610 } 611 if (!size) 612 f[index] = tmp; 613 } 614 } 615 616 return 0; 617 } 618 619 static void bcmgenet_hfb_set_filter(struct bcmgenet_priv *priv, u32 *f_data, 620 u32 f_length, u32 rx_queue, int f_index) 621 { 622 u32 base = f_index * priv->hw_params->hfb_filter_size; 623 int i; 624 625 for (i = 0; i < f_length; i++) 626 bcmgenet_hfb_writel(priv, f_data[i], (base + i) * sizeof(u32)); 627 628 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length); 629 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue); 630 } 631 632 static int bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 633 struct bcmgenet_rxnfc_rule *rule) 634 { 635 struct ethtool_rx_flow_spec *fs = &rule->fs; 636 int err = 0, offset = 0, f_length = 0; 637 u16 val_16, mask_16; 638 u8 val_8, mask_8; 639 size_t size; 640 u32 *f_data; 641 642 f_data = kcalloc(priv->hw_params->hfb_filter_size, sizeof(u32), 643 GFP_KERNEL); 644 if (!f_data) 645 return -ENOMEM; 646 647 if (fs->flow_type & FLOW_MAC_EXT) { 648 bcmgenet_hfb_insert_data(f_data, 0, 649 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 650 sizeof(fs->h_ext.h_dest)); 651 } 652 653 if (fs->flow_type & FLOW_EXT) { 654 if (fs->m_ext.vlan_etype || 655 fs->m_ext.vlan_tci) { 656 bcmgenet_hfb_insert_data(f_data, 12, 657 &fs->h_ext.vlan_etype, 658 &fs->m_ext.vlan_etype, 659 sizeof(fs->h_ext.vlan_etype)); 660 bcmgenet_hfb_insert_data(f_data, 14, 661 &fs->h_ext.vlan_tci, 662 &fs->m_ext.vlan_tci, 663 sizeof(fs->h_ext.vlan_tci)); 664 offset += VLAN_HLEN; 665 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 666 } 667 } 668 669 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 670 case ETHER_FLOW: 671 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 672 bcmgenet_hfb_insert_data(f_data, 0, 673 &fs->h_u.ether_spec.h_dest, 674 &fs->m_u.ether_spec.h_dest, 675 sizeof(fs->h_u.ether_spec.h_dest)); 676 bcmgenet_hfb_insert_data(f_data, ETH_ALEN, 677 &fs->h_u.ether_spec.h_source, 678 &fs->m_u.ether_spec.h_source, 679 sizeof(fs->h_u.ether_spec.h_source)); 680 bcmgenet_hfb_insert_data(f_data, (2 * ETH_ALEN) + offset, 681 &fs->h_u.ether_spec.h_proto, 682 &fs->m_u.ether_spec.h_proto, 683 sizeof(fs->h_u.ether_spec.h_proto)); 684 break; 685 case IP_USER_FLOW: 686 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 687 /* Specify IP Ether Type */ 688 val_16 = htons(ETH_P_IP); 689 mask_16 = 0xFFFF; 690 bcmgenet_hfb_insert_data(f_data, (2 * ETH_ALEN) + offset, 691 &val_16, &mask_16, sizeof(val_16)); 692 bcmgenet_hfb_insert_data(f_data, 15 + offset, 693 &fs->h_u.usr_ip4_spec.tos, 694 &fs->m_u.usr_ip4_spec.tos, 695 sizeof(fs->h_u.usr_ip4_spec.tos)); 696 bcmgenet_hfb_insert_data(f_data, 23 + offset, 697 &fs->h_u.usr_ip4_spec.proto, 698 &fs->m_u.usr_ip4_spec.proto, 699 sizeof(fs->h_u.usr_ip4_spec.proto)); 700 bcmgenet_hfb_insert_data(f_data, 26 + offset, 701 &fs->h_u.usr_ip4_spec.ip4src, 702 &fs->m_u.usr_ip4_spec.ip4src, 703 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 704 bcmgenet_hfb_insert_data(f_data, 30 + offset, 705 &fs->h_u.usr_ip4_spec.ip4dst, 706 &fs->m_u.usr_ip4_spec.ip4dst, 707 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 708 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 709 break; 710 711 /* Only supports 20 byte IPv4 header */ 712 val_8 = 0x45; 713 mask_8 = 0xFF; 714 bcmgenet_hfb_insert_data(f_data, ETH_HLEN + offset, 715 &val_8, &mask_8, 716 sizeof(val_8)); 717 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 718 bcmgenet_hfb_insert_data(f_data, 719 ETH_HLEN + 20 + offset, 720 &fs->h_u.usr_ip4_spec.l4_4_bytes, 721 &fs->m_u.usr_ip4_spec.l4_4_bytes, 722 size); 723 f_length += DIV_ROUND_UP(size, 2); 724 break; 725 } 726 727 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) { 728 /* Ring 0 flows can be handled by the default Descriptor Ring 729 * We'll map them to ring 0, but don't enable the filter 730 */ 731 bcmgenet_hfb_set_filter(priv, f_data, f_length, 0, 732 fs->location); 733 rule->state = BCMGENET_RXNFC_STATE_DISABLED; 734 } else { 735 /* Other Rx rings are direct mapped here */ 736 bcmgenet_hfb_set_filter(priv, f_data, f_length, 737 fs->ring_cookie, fs->location); 738 bcmgenet_hfb_enable_filter(priv, fs->location); 739 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 740 } 741 742 kfree(f_data); 743 744 return err; 745 } 746 747 /* bcmgenet_hfb_add_filter 748 * 749 * Add new filter to Hardware Filter Block to match and direct Rx traffic to 750 * desired Rx queue. 751 * 752 * f_data is an array of unsigned 32-bit integers where each 32-bit integer 753 * provides filter data for 2 bytes (4 nibbles) of Rx frame: 754 * 755 * bits 31:20 - unused 756 * bit 19 - nibble 0 match enable 757 * bit 18 - nibble 1 match enable 758 * bit 17 - nibble 2 match enable 759 * bit 16 - nibble 3 match enable 760 * bits 15:12 - nibble 0 data 761 * bits 11:8 - nibble 1 data 762 * bits 7:4 - nibble 2 data 763 * bits 3:0 - nibble 3 data 764 * 765 * Example: 766 * In order to match: 767 * - Ethernet frame type = 0x0800 (IP) 768 * - IP version field = 4 769 * - IP protocol field = 0x11 (UDP) 770 * 771 * The following filter is needed: 772 * u32 hfb_filter_ipv4_udp[] = { 773 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 774 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000, 775 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011, 776 * }; 777 * 778 * To add the filter to HFB and direct the traffic to Rx queue 0, call: 779 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp, 780 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0); 781 */ 782 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data, 783 u32 f_length, u32 rx_queue) 784 { 785 int f_index; 786 787 f_index = bcmgenet_hfb_find_unused_filter(priv); 788 if (f_index < 0) 789 return -ENOMEM; 790 791 if (f_length > priv->hw_params->hfb_filter_size) 792 return -EINVAL; 793 794 bcmgenet_hfb_set_filter(priv, f_data, f_length, rx_queue, f_index); 795 bcmgenet_hfb_enable_filter(priv, f_index); 796 797 return 0; 798 } 799 800 /* bcmgenet_hfb_clear 801 * 802 * Clear Hardware Filter Block and disable all filtering. 803 */ 804 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 805 { 806 u32 i; 807 808 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 809 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 810 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 811 812 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 813 bcmgenet_rdma_writel(priv, 0x0, i); 814 815 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 816 bcmgenet_hfb_reg_writel(priv, 0x0, 817 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 818 819 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 820 priv->hw_params->hfb_filter_size; i++) 821 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 822 } 823 824 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 825 { 826 int i; 827 828 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 829 return; 830 831 INIT_LIST_HEAD(&priv->rxnfc_list); 832 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 833 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 834 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 835 } 836 837 bcmgenet_hfb_clear(priv); 838 } 839 840 static int bcmgenet_begin(struct net_device *dev) 841 { 842 struct bcmgenet_priv *priv = netdev_priv(dev); 843 844 /* Turn on the clock */ 845 return clk_prepare_enable(priv->clk); 846 } 847 848 static void bcmgenet_complete(struct net_device *dev) 849 { 850 struct bcmgenet_priv *priv = netdev_priv(dev); 851 852 /* Turn off the clock */ 853 clk_disable_unprepare(priv->clk); 854 } 855 856 static int bcmgenet_get_link_ksettings(struct net_device *dev, 857 struct ethtool_link_ksettings *cmd) 858 { 859 if (!netif_running(dev)) 860 return -EINVAL; 861 862 if (!dev->phydev) 863 return -ENODEV; 864 865 phy_ethtool_ksettings_get(dev->phydev, cmd); 866 867 return 0; 868 } 869 870 static int bcmgenet_set_link_ksettings(struct net_device *dev, 871 const struct ethtool_link_ksettings *cmd) 872 { 873 if (!netif_running(dev)) 874 return -EINVAL; 875 876 if (!dev->phydev) 877 return -ENODEV; 878 879 return phy_ethtool_ksettings_set(dev->phydev, cmd); 880 } 881 882 static int bcmgenet_set_features(struct net_device *dev, 883 netdev_features_t features) 884 { 885 struct bcmgenet_priv *priv = netdev_priv(dev); 886 u32 reg; 887 int ret; 888 889 ret = clk_prepare_enable(priv->clk); 890 if (ret) 891 return ret; 892 893 /* Make sure we reflect the value of CRC_CMD_FWD */ 894 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 895 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 896 897 clk_disable_unprepare(priv->clk); 898 899 return ret; 900 } 901 902 static u32 bcmgenet_get_msglevel(struct net_device *dev) 903 { 904 struct bcmgenet_priv *priv = netdev_priv(dev); 905 906 return priv->msg_enable; 907 } 908 909 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 910 { 911 struct bcmgenet_priv *priv = netdev_priv(dev); 912 913 priv->msg_enable = level; 914 } 915 916 static int bcmgenet_get_coalesce(struct net_device *dev, 917 struct ethtool_coalesce *ec) 918 { 919 struct bcmgenet_priv *priv = netdev_priv(dev); 920 struct bcmgenet_rx_ring *ring; 921 unsigned int i; 922 923 ec->tx_max_coalesced_frames = 924 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 925 DMA_MBUF_DONE_THRESH); 926 ec->rx_max_coalesced_frames = 927 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 928 DMA_MBUF_DONE_THRESH); 929 ec->rx_coalesce_usecs = 930 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 931 932 for (i = 0; i < priv->hw_params->rx_queues; i++) { 933 ring = &priv->rx_rings[i]; 934 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 935 } 936 ring = &priv->rx_rings[DESC_INDEX]; 937 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 938 939 return 0; 940 } 941 942 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 943 u32 usecs, u32 pkts) 944 { 945 struct bcmgenet_priv *priv = ring->priv; 946 unsigned int i = ring->index; 947 u32 reg; 948 949 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 950 951 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 952 reg &= ~DMA_TIMEOUT_MASK; 953 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 954 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 955 } 956 957 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 958 struct ethtool_coalesce *ec) 959 { 960 struct dim_cq_moder moder; 961 u32 usecs, pkts; 962 963 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 964 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 965 usecs = ring->rx_coalesce_usecs; 966 pkts = ring->rx_max_coalesced_frames; 967 968 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 969 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 970 usecs = moder.usec; 971 pkts = moder.pkts; 972 } 973 974 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 975 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 976 } 977 978 static int bcmgenet_set_coalesce(struct net_device *dev, 979 struct ethtool_coalesce *ec) 980 { 981 struct bcmgenet_priv *priv = netdev_priv(dev); 982 unsigned int i; 983 984 /* Base system clock is 125Mhz, DMA timeout is this reference clock 985 * divided by 1024, which yields roughly 8.192us, our maximum value 986 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 987 */ 988 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 989 ec->tx_max_coalesced_frames == 0 || 990 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 991 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 992 return -EINVAL; 993 994 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 995 return -EINVAL; 996 997 /* GENET TDMA hardware does not support a configurable timeout, but will 998 * always generate an interrupt either after MBDONE packets have been 999 * transmitted, or when the ring is empty. 1000 */ 1001 1002 /* Program all TX queues with the same values, as there is no 1003 * ethtool knob to do coalescing on a per-queue basis 1004 */ 1005 for (i = 0; i < priv->hw_params->tx_queues; i++) 1006 bcmgenet_tdma_ring_writel(priv, i, 1007 ec->tx_max_coalesced_frames, 1008 DMA_MBUF_DONE_THRESH); 1009 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 1010 ec->tx_max_coalesced_frames, 1011 DMA_MBUF_DONE_THRESH); 1012 1013 for (i = 0; i < priv->hw_params->rx_queues; i++) 1014 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 1015 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 1016 1017 return 0; 1018 } 1019 1020 /* standard ethtool support functions. */ 1021 enum bcmgenet_stat_type { 1022 BCMGENET_STAT_NETDEV = -1, 1023 BCMGENET_STAT_MIB_RX, 1024 BCMGENET_STAT_MIB_TX, 1025 BCMGENET_STAT_RUNT, 1026 BCMGENET_STAT_MISC, 1027 BCMGENET_STAT_SOFT, 1028 }; 1029 1030 struct bcmgenet_stats { 1031 char stat_string[ETH_GSTRING_LEN]; 1032 int stat_sizeof; 1033 int stat_offset; 1034 enum bcmgenet_stat_type type; 1035 /* reg offset from UMAC base for misc counters */ 1036 u16 reg_offset; 1037 }; 1038 1039 #define STAT_NETDEV(m) { \ 1040 .stat_string = __stringify(m), \ 1041 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 1042 .stat_offset = offsetof(struct net_device_stats, m), \ 1043 .type = BCMGENET_STAT_NETDEV, \ 1044 } 1045 1046 #define STAT_GENET_MIB(str, m, _type) { \ 1047 .stat_string = str, \ 1048 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1049 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1050 .type = _type, \ 1051 } 1052 1053 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 1054 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 1055 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 1056 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 1057 1058 #define STAT_GENET_MISC(str, m, offset) { \ 1059 .stat_string = str, \ 1060 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 1061 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 1062 .type = BCMGENET_STAT_MISC, \ 1063 .reg_offset = offset, \ 1064 } 1065 1066 #define STAT_GENET_Q(num) \ 1067 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 1068 tx_rings[num].packets), \ 1069 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 1070 tx_rings[num].bytes), \ 1071 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 1072 rx_rings[num].bytes), \ 1073 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 1074 rx_rings[num].packets), \ 1075 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 1076 rx_rings[num].errors), \ 1077 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 1078 rx_rings[num].dropped) 1079 1080 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 1081 * between the end of TX stats and the beginning of the RX RUNT 1082 */ 1083 #define BCMGENET_STAT_OFFSET 0xc 1084 1085 /* Hardware counters must be kept in sync because the order/offset 1086 * is important here (order in structure declaration = order in hardware) 1087 */ 1088 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1089 /* general stats */ 1090 STAT_NETDEV(rx_packets), 1091 STAT_NETDEV(tx_packets), 1092 STAT_NETDEV(rx_bytes), 1093 STAT_NETDEV(tx_bytes), 1094 STAT_NETDEV(rx_errors), 1095 STAT_NETDEV(tx_errors), 1096 STAT_NETDEV(rx_dropped), 1097 STAT_NETDEV(tx_dropped), 1098 STAT_NETDEV(multicast), 1099 /* UniMAC RSV counters */ 1100 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1101 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1102 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1103 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1104 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1105 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1106 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1107 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1108 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1109 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1110 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1111 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1112 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1113 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1114 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1115 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1116 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1117 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1118 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1119 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1120 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1121 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1122 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1123 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1124 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1125 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1126 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1127 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1128 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1129 /* UniMAC TSV counters */ 1130 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1131 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1132 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1133 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1134 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1135 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1136 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1137 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1138 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1139 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1140 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1141 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1142 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1143 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1144 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1145 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1146 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1147 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1148 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1149 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1150 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1151 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1152 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1153 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1154 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1155 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1156 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1157 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1158 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1159 /* UniMAC RUNT counters */ 1160 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1161 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1162 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1163 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1164 /* Misc UniMAC counters */ 1165 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1166 UMAC_RBUF_OVFL_CNT_V1), 1167 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1168 UMAC_RBUF_ERR_CNT_V1), 1169 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1170 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1171 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1172 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1173 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1174 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1175 mib.tx_realloc_tsb_failed), 1176 /* Per TX queues */ 1177 STAT_GENET_Q(0), 1178 STAT_GENET_Q(1), 1179 STAT_GENET_Q(2), 1180 STAT_GENET_Q(3), 1181 STAT_GENET_Q(16), 1182 }; 1183 1184 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1185 1186 static void bcmgenet_get_drvinfo(struct net_device *dev, 1187 struct ethtool_drvinfo *info) 1188 { 1189 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 1190 } 1191 1192 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1193 { 1194 switch (string_set) { 1195 case ETH_SS_STATS: 1196 return BCMGENET_STATS_LEN; 1197 default: 1198 return -EOPNOTSUPP; 1199 } 1200 } 1201 1202 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1203 u8 *data) 1204 { 1205 int i; 1206 1207 switch (stringset) { 1208 case ETH_SS_STATS: 1209 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1210 memcpy(data + i * ETH_GSTRING_LEN, 1211 bcmgenet_gstrings_stats[i].stat_string, 1212 ETH_GSTRING_LEN); 1213 } 1214 break; 1215 } 1216 } 1217 1218 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1219 { 1220 u16 new_offset; 1221 u32 val; 1222 1223 switch (offset) { 1224 case UMAC_RBUF_OVFL_CNT_V1: 1225 if (GENET_IS_V2(priv)) 1226 new_offset = RBUF_OVFL_CNT_V2; 1227 else 1228 new_offset = RBUF_OVFL_CNT_V3PLUS; 1229 1230 val = bcmgenet_rbuf_readl(priv, new_offset); 1231 /* clear if overflowed */ 1232 if (val == ~0) 1233 bcmgenet_rbuf_writel(priv, 0, new_offset); 1234 break; 1235 case UMAC_RBUF_ERR_CNT_V1: 1236 if (GENET_IS_V2(priv)) 1237 new_offset = RBUF_ERR_CNT_V2; 1238 else 1239 new_offset = RBUF_ERR_CNT_V3PLUS; 1240 1241 val = bcmgenet_rbuf_readl(priv, new_offset); 1242 /* clear if overflowed */ 1243 if (val == ~0) 1244 bcmgenet_rbuf_writel(priv, 0, new_offset); 1245 break; 1246 default: 1247 val = bcmgenet_umac_readl(priv, offset); 1248 /* clear if overflowed */ 1249 if (val == ~0) 1250 bcmgenet_umac_writel(priv, 0, offset); 1251 break; 1252 } 1253 1254 return val; 1255 } 1256 1257 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1258 { 1259 int i, j = 0; 1260 1261 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1262 const struct bcmgenet_stats *s; 1263 u8 offset = 0; 1264 u32 val = 0; 1265 char *p; 1266 1267 s = &bcmgenet_gstrings_stats[i]; 1268 switch (s->type) { 1269 case BCMGENET_STAT_NETDEV: 1270 case BCMGENET_STAT_SOFT: 1271 continue; 1272 case BCMGENET_STAT_RUNT: 1273 offset += BCMGENET_STAT_OFFSET; 1274 /* fall through */ 1275 case BCMGENET_STAT_MIB_TX: 1276 offset += BCMGENET_STAT_OFFSET; 1277 /* fall through */ 1278 case BCMGENET_STAT_MIB_RX: 1279 val = bcmgenet_umac_readl(priv, 1280 UMAC_MIB_START + j + offset); 1281 offset = 0; /* Reset Offset */ 1282 break; 1283 case BCMGENET_STAT_MISC: 1284 if (GENET_IS_V1(priv)) { 1285 val = bcmgenet_umac_readl(priv, s->reg_offset); 1286 /* clear if overflowed */ 1287 if (val == ~0) 1288 bcmgenet_umac_writel(priv, 0, 1289 s->reg_offset); 1290 } else { 1291 val = bcmgenet_update_stat_misc(priv, 1292 s->reg_offset); 1293 } 1294 break; 1295 } 1296 1297 j += s->stat_sizeof; 1298 p = (char *)priv + s->stat_offset; 1299 *(u32 *)p = val; 1300 } 1301 } 1302 1303 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1304 struct ethtool_stats *stats, 1305 u64 *data) 1306 { 1307 struct bcmgenet_priv *priv = netdev_priv(dev); 1308 int i; 1309 1310 if (netif_running(dev)) 1311 bcmgenet_update_mib_counters(priv); 1312 1313 dev->netdev_ops->ndo_get_stats(dev); 1314 1315 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1316 const struct bcmgenet_stats *s; 1317 char *p; 1318 1319 s = &bcmgenet_gstrings_stats[i]; 1320 if (s->type == BCMGENET_STAT_NETDEV) 1321 p = (char *)&dev->stats; 1322 else 1323 p = (char *)priv; 1324 p += s->stat_offset; 1325 if (sizeof(unsigned long) != sizeof(u32) && 1326 s->stat_sizeof == sizeof(unsigned long)) 1327 data[i] = *(unsigned long *)p; 1328 else 1329 data[i] = *(u32 *)p; 1330 } 1331 } 1332 1333 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1334 { 1335 struct bcmgenet_priv *priv = netdev_priv(dev); 1336 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1337 u32 reg; 1338 1339 if (enable && !priv->clk_eee_enabled) { 1340 clk_prepare_enable(priv->clk_eee); 1341 priv->clk_eee_enabled = true; 1342 } 1343 1344 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1345 if (enable) 1346 reg |= EEE_EN; 1347 else 1348 reg &= ~EEE_EN; 1349 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1350 1351 /* Enable EEE and switch to a 27Mhz clock automatically */ 1352 reg = bcmgenet_readl(priv->base + off); 1353 if (enable) 1354 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1355 else 1356 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1357 bcmgenet_writel(reg, priv->base + off); 1358 1359 /* Do the same for thing for RBUF */ 1360 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1361 if (enable) 1362 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1363 else 1364 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1365 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1366 1367 if (!enable && priv->clk_eee_enabled) { 1368 clk_disable_unprepare(priv->clk_eee); 1369 priv->clk_eee_enabled = false; 1370 } 1371 1372 priv->eee.eee_enabled = enable; 1373 priv->eee.eee_active = enable; 1374 } 1375 1376 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1377 { 1378 struct bcmgenet_priv *priv = netdev_priv(dev); 1379 struct ethtool_eee *p = &priv->eee; 1380 1381 if (GENET_IS_V1(priv)) 1382 return -EOPNOTSUPP; 1383 1384 if (!dev->phydev) 1385 return -ENODEV; 1386 1387 e->eee_enabled = p->eee_enabled; 1388 e->eee_active = p->eee_active; 1389 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1390 1391 return phy_ethtool_get_eee(dev->phydev, e); 1392 } 1393 1394 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1395 { 1396 struct bcmgenet_priv *priv = netdev_priv(dev); 1397 struct ethtool_eee *p = &priv->eee; 1398 int ret = 0; 1399 1400 if (GENET_IS_V1(priv)) 1401 return -EOPNOTSUPP; 1402 1403 if (!dev->phydev) 1404 return -ENODEV; 1405 1406 p->eee_enabled = e->eee_enabled; 1407 1408 if (!p->eee_enabled) { 1409 bcmgenet_eee_enable_set(dev, false); 1410 } else { 1411 ret = phy_init_eee(dev->phydev, 0); 1412 if (ret) { 1413 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1414 return ret; 1415 } 1416 1417 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1418 bcmgenet_eee_enable_set(dev, true); 1419 } 1420 1421 return phy_ethtool_set_eee(dev->phydev, e); 1422 } 1423 1424 static int bcmgenet_validate_flow(struct net_device *dev, 1425 struct ethtool_rxnfc *cmd) 1426 { 1427 struct ethtool_usrip4_spec *l4_mask; 1428 struct ethhdr *eth_mask; 1429 1430 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) { 1431 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1432 cmd->fs.location); 1433 return -EINVAL; 1434 } 1435 1436 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1437 case IP_USER_FLOW: 1438 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1439 /* don't allow mask which isn't valid */ 1440 if (VALIDATE_MASK(l4_mask->ip4src) || 1441 VALIDATE_MASK(l4_mask->ip4dst) || 1442 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1443 VALIDATE_MASK(l4_mask->proto) || 1444 VALIDATE_MASK(l4_mask->ip_ver) || 1445 VALIDATE_MASK(l4_mask->tos)) { 1446 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1447 return -EINVAL; 1448 } 1449 break; 1450 case ETHER_FLOW: 1451 eth_mask = &cmd->fs.m_u.ether_spec; 1452 /* don't allow mask which isn't valid */ 1453 if (VALIDATE_MASK(eth_mask->h_source) || 1454 VALIDATE_MASK(eth_mask->h_source) || 1455 VALIDATE_MASK(eth_mask->h_proto)) { 1456 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1457 return -EINVAL; 1458 } 1459 break; 1460 default: 1461 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1462 cmd->fs.flow_type); 1463 return -EINVAL; 1464 } 1465 1466 if ((cmd->fs.flow_type & FLOW_EXT)) { 1467 /* don't allow mask which isn't valid */ 1468 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1469 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1470 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1471 return -EINVAL; 1472 } 1473 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1474 netdev_err(dev, "rxnfc: user-def not supported\n"); 1475 return -EINVAL; 1476 } 1477 } 1478 1479 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1480 /* don't allow mask which isn't valid */ 1481 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1482 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1483 return -EINVAL; 1484 } 1485 } 1486 1487 return 0; 1488 } 1489 1490 static int bcmgenet_insert_flow(struct net_device *dev, 1491 struct ethtool_rxnfc *cmd) 1492 { 1493 struct bcmgenet_priv *priv = netdev_priv(dev); 1494 struct bcmgenet_rxnfc_rule *loc_rule; 1495 int err; 1496 1497 if (priv->hw_params->hfb_filter_size < 128) { 1498 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1499 return -EINVAL; 1500 } 1501 1502 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1503 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) { 1504 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1505 cmd->fs.ring_cookie); 1506 return -EINVAL; 1507 } 1508 1509 err = bcmgenet_validate_flow(dev, cmd); 1510 if (err) 1511 return err; 1512 1513 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1514 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1515 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1516 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) 1517 list_del(&loc_rule->list); 1518 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1519 memcpy(&loc_rule->fs, &cmd->fs, 1520 sizeof(struct ethtool_rx_flow_spec)); 1521 1522 err = bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1523 if (err) { 1524 netdev_err(dev, "rxnfc: Could not install rule (%d)\n", 1525 err); 1526 return err; 1527 } 1528 1529 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1530 1531 return 0; 1532 } 1533 1534 static int bcmgenet_delete_flow(struct net_device *dev, 1535 struct ethtool_rxnfc *cmd) 1536 { 1537 struct bcmgenet_priv *priv = netdev_priv(dev); 1538 struct bcmgenet_rxnfc_rule *rule; 1539 int err = 0; 1540 1541 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1542 return -EINVAL; 1543 1544 rule = &priv->rxnfc_rules[cmd->fs.location]; 1545 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1546 err = -ENOENT; 1547 goto out; 1548 } 1549 1550 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1551 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1552 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 1553 list_del(&rule->list); 1554 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1555 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1556 1557 out: 1558 return err; 1559 } 1560 1561 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1562 { 1563 struct bcmgenet_priv *priv = netdev_priv(dev); 1564 int err = 0; 1565 1566 switch (cmd->cmd) { 1567 case ETHTOOL_SRXCLSRLINS: 1568 err = bcmgenet_insert_flow(dev, cmd); 1569 break; 1570 case ETHTOOL_SRXCLSRLDEL: 1571 err = bcmgenet_delete_flow(dev, cmd); 1572 break; 1573 default: 1574 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1575 cmd->cmd); 1576 return -EINVAL; 1577 } 1578 1579 return err; 1580 } 1581 1582 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1583 int loc) 1584 { 1585 struct bcmgenet_priv *priv = netdev_priv(dev); 1586 struct bcmgenet_rxnfc_rule *rule; 1587 int err = 0; 1588 1589 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1590 return -EINVAL; 1591 1592 rule = &priv->rxnfc_rules[loc]; 1593 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1594 err = -ENOENT; 1595 else 1596 memcpy(&cmd->fs, &rule->fs, 1597 sizeof(struct ethtool_rx_flow_spec)); 1598 1599 return err; 1600 } 1601 1602 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1603 { 1604 struct list_head *pos; 1605 int res = 0; 1606 1607 list_for_each(pos, &priv->rxnfc_list) 1608 res++; 1609 1610 return res; 1611 } 1612 1613 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1614 u32 *rule_locs) 1615 { 1616 struct bcmgenet_priv *priv = netdev_priv(dev); 1617 struct bcmgenet_rxnfc_rule *rule; 1618 int err = 0; 1619 int i = 0; 1620 1621 switch (cmd->cmd) { 1622 case ETHTOOL_GRXRINGS: 1623 cmd->data = priv->hw_params->rx_queues ?: 1; 1624 break; 1625 case ETHTOOL_GRXCLSRLCNT: 1626 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1627 cmd->data = MAX_NUM_OF_FS_RULES; 1628 break; 1629 case ETHTOOL_GRXCLSRULE: 1630 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1631 break; 1632 case ETHTOOL_GRXCLSRLALL: 1633 list_for_each_entry(rule, &priv->rxnfc_list, list) 1634 if (i < cmd->rule_cnt) 1635 rule_locs[i++] = rule->fs.location; 1636 cmd->rule_cnt = i; 1637 cmd->data = MAX_NUM_OF_FS_RULES; 1638 break; 1639 default: 1640 err = -EOPNOTSUPP; 1641 break; 1642 } 1643 1644 return err; 1645 } 1646 1647 /* standard ethtool support functions. */ 1648 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1649 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1650 ETHTOOL_COALESCE_MAX_FRAMES | 1651 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1652 .begin = bcmgenet_begin, 1653 .complete = bcmgenet_complete, 1654 .get_strings = bcmgenet_get_strings, 1655 .get_sset_count = bcmgenet_get_sset_count, 1656 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1657 .get_drvinfo = bcmgenet_get_drvinfo, 1658 .get_link = ethtool_op_get_link, 1659 .get_msglevel = bcmgenet_get_msglevel, 1660 .set_msglevel = bcmgenet_set_msglevel, 1661 .get_wol = bcmgenet_get_wol, 1662 .set_wol = bcmgenet_set_wol, 1663 .get_eee = bcmgenet_get_eee, 1664 .set_eee = bcmgenet_set_eee, 1665 .nway_reset = phy_ethtool_nway_reset, 1666 .get_coalesce = bcmgenet_get_coalesce, 1667 .set_coalesce = bcmgenet_set_coalesce, 1668 .get_link_ksettings = bcmgenet_get_link_ksettings, 1669 .set_link_ksettings = bcmgenet_set_link_ksettings, 1670 .get_ts_info = ethtool_op_get_ts_info, 1671 .get_rxnfc = bcmgenet_get_rxnfc, 1672 .set_rxnfc = bcmgenet_set_rxnfc, 1673 }; 1674 1675 /* Power down the unimac, based on mode. */ 1676 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1677 enum bcmgenet_power_mode mode) 1678 { 1679 int ret = 0; 1680 u32 reg; 1681 1682 switch (mode) { 1683 case GENET_POWER_CABLE_SENSE: 1684 phy_detach(priv->dev->phydev); 1685 break; 1686 1687 case GENET_POWER_WOL_MAGIC: 1688 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1689 break; 1690 1691 case GENET_POWER_PASSIVE: 1692 /* Power down LED */ 1693 if (priv->hw_params->flags & GENET_HAS_EXT) { 1694 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1695 if (GENET_IS_V5(priv)) 1696 reg |= EXT_PWR_DOWN_PHY_EN | 1697 EXT_PWR_DOWN_PHY_RD | 1698 EXT_PWR_DOWN_PHY_SD | 1699 EXT_PWR_DOWN_PHY_RX | 1700 EXT_PWR_DOWN_PHY_TX | 1701 EXT_IDDQ_GLBL_PWR; 1702 else 1703 reg |= EXT_PWR_DOWN_PHY; 1704 1705 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1706 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1707 1708 bcmgenet_phy_power_set(priv->dev, false); 1709 } 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 return ret; 1716 } 1717 1718 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1719 enum bcmgenet_power_mode mode) 1720 { 1721 u32 reg; 1722 1723 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1724 return; 1725 1726 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1727 1728 switch (mode) { 1729 case GENET_POWER_PASSIVE: 1730 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1731 if (GENET_IS_V5(priv)) { 1732 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1733 EXT_PWR_DOWN_PHY_RD | 1734 EXT_PWR_DOWN_PHY_SD | 1735 EXT_PWR_DOWN_PHY_RX | 1736 EXT_PWR_DOWN_PHY_TX | 1737 EXT_IDDQ_GLBL_PWR); 1738 reg |= EXT_PHY_RESET; 1739 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1740 mdelay(1); 1741 1742 reg &= ~EXT_PHY_RESET; 1743 } else { 1744 reg &= ~EXT_PWR_DOWN_PHY; 1745 reg |= EXT_PWR_DN_EN_LD; 1746 } 1747 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1748 bcmgenet_phy_power_set(priv->dev, true); 1749 break; 1750 1751 case GENET_POWER_CABLE_SENSE: 1752 /* enable APD */ 1753 if (!GENET_IS_V5(priv)) { 1754 reg |= EXT_PWR_DN_EN_LD; 1755 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1756 } 1757 break; 1758 case GENET_POWER_WOL_MAGIC: 1759 bcmgenet_wol_power_up_cfg(priv, mode); 1760 return; 1761 default: 1762 break; 1763 } 1764 } 1765 1766 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1767 struct bcmgenet_tx_ring *ring) 1768 { 1769 struct enet_cb *tx_cb_ptr; 1770 1771 tx_cb_ptr = ring->cbs; 1772 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1773 1774 /* Advancing local write pointer */ 1775 if (ring->write_ptr == ring->end_ptr) 1776 ring->write_ptr = ring->cb_ptr; 1777 else 1778 ring->write_ptr++; 1779 1780 return tx_cb_ptr; 1781 } 1782 1783 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1784 struct bcmgenet_tx_ring *ring) 1785 { 1786 struct enet_cb *tx_cb_ptr; 1787 1788 tx_cb_ptr = ring->cbs; 1789 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1790 1791 /* Rewinding local write pointer */ 1792 if (ring->write_ptr == ring->cb_ptr) 1793 ring->write_ptr = ring->end_ptr; 1794 else 1795 ring->write_ptr--; 1796 1797 return tx_cb_ptr; 1798 } 1799 1800 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1801 { 1802 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1803 INTRL2_CPU_MASK_SET); 1804 } 1805 1806 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1807 { 1808 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1809 INTRL2_CPU_MASK_CLEAR); 1810 } 1811 1812 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1813 { 1814 bcmgenet_intrl2_1_writel(ring->priv, 1815 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1816 INTRL2_CPU_MASK_SET); 1817 } 1818 1819 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1820 { 1821 bcmgenet_intrl2_1_writel(ring->priv, 1822 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1823 INTRL2_CPU_MASK_CLEAR); 1824 } 1825 1826 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1827 { 1828 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1829 INTRL2_CPU_MASK_SET); 1830 } 1831 1832 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1833 { 1834 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1835 INTRL2_CPU_MASK_CLEAR); 1836 } 1837 1838 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1839 { 1840 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1841 INTRL2_CPU_MASK_CLEAR); 1842 } 1843 1844 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1845 { 1846 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1847 INTRL2_CPU_MASK_SET); 1848 } 1849 1850 /* Simple helper to free a transmit control block's resources 1851 * Returns an skb when the last transmit control block associated with the 1852 * skb is freed. The skb should be freed by the caller if necessary. 1853 */ 1854 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1855 struct enet_cb *cb) 1856 { 1857 struct sk_buff *skb; 1858 1859 skb = cb->skb; 1860 1861 if (skb) { 1862 cb->skb = NULL; 1863 if (cb == GENET_CB(skb)->first_cb) 1864 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1865 dma_unmap_len(cb, dma_len), 1866 DMA_TO_DEVICE); 1867 else 1868 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1869 dma_unmap_len(cb, dma_len), 1870 DMA_TO_DEVICE); 1871 dma_unmap_addr_set(cb, dma_addr, 0); 1872 1873 if (cb == GENET_CB(skb)->last_cb) 1874 return skb; 1875 1876 } else if (dma_unmap_addr(cb, dma_addr)) { 1877 dma_unmap_page(dev, 1878 dma_unmap_addr(cb, dma_addr), 1879 dma_unmap_len(cb, dma_len), 1880 DMA_TO_DEVICE); 1881 dma_unmap_addr_set(cb, dma_addr, 0); 1882 } 1883 1884 return NULL; 1885 } 1886 1887 /* Simple helper to free a receive control block's resources */ 1888 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1889 struct enet_cb *cb) 1890 { 1891 struct sk_buff *skb; 1892 1893 skb = cb->skb; 1894 cb->skb = NULL; 1895 1896 if (dma_unmap_addr(cb, dma_addr)) { 1897 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1898 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1899 dma_unmap_addr_set(cb, dma_addr, 0); 1900 } 1901 1902 return skb; 1903 } 1904 1905 /* Unlocked version of the reclaim routine */ 1906 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1907 struct bcmgenet_tx_ring *ring) 1908 { 1909 struct bcmgenet_priv *priv = netdev_priv(dev); 1910 unsigned int txbds_processed = 0; 1911 unsigned int bytes_compl = 0; 1912 unsigned int pkts_compl = 0; 1913 unsigned int txbds_ready; 1914 unsigned int c_index; 1915 struct sk_buff *skb; 1916 1917 /* Clear status before servicing to reduce spurious interrupts */ 1918 if (ring->index == DESC_INDEX) 1919 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1920 INTRL2_CPU_CLEAR); 1921 else 1922 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1923 INTRL2_CPU_CLEAR); 1924 1925 /* Compute how many buffers are transmitted since last xmit call */ 1926 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1927 & DMA_C_INDEX_MASK; 1928 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1929 1930 netif_dbg(priv, tx_done, dev, 1931 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1932 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1933 1934 /* Reclaim transmitted buffers */ 1935 while (txbds_processed < txbds_ready) { 1936 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1937 &priv->tx_cbs[ring->clean_ptr]); 1938 if (skb) { 1939 pkts_compl++; 1940 bytes_compl += GENET_CB(skb)->bytes_sent; 1941 dev_consume_skb_any(skb); 1942 } 1943 1944 txbds_processed++; 1945 if (likely(ring->clean_ptr < ring->end_ptr)) 1946 ring->clean_ptr++; 1947 else 1948 ring->clean_ptr = ring->cb_ptr; 1949 } 1950 1951 ring->free_bds += txbds_processed; 1952 ring->c_index = c_index; 1953 1954 ring->packets += pkts_compl; 1955 ring->bytes += bytes_compl; 1956 1957 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1958 pkts_compl, bytes_compl); 1959 1960 return txbds_processed; 1961 } 1962 1963 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1964 struct bcmgenet_tx_ring *ring) 1965 { 1966 unsigned int released; 1967 1968 spin_lock_bh(&ring->lock); 1969 released = __bcmgenet_tx_reclaim(dev, ring); 1970 spin_unlock_bh(&ring->lock); 1971 1972 return released; 1973 } 1974 1975 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1976 { 1977 struct bcmgenet_tx_ring *ring = 1978 container_of(napi, struct bcmgenet_tx_ring, napi); 1979 unsigned int work_done = 0; 1980 struct netdev_queue *txq; 1981 1982 spin_lock(&ring->lock); 1983 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1984 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1985 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1986 netif_tx_wake_queue(txq); 1987 } 1988 spin_unlock(&ring->lock); 1989 1990 if (work_done == 0) { 1991 napi_complete(napi); 1992 ring->int_enable(ring); 1993 1994 return 0; 1995 } 1996 1997 return budget; 1998 } 1999 2000 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 2001 { 2002 struct bcmgenet_priv *priv = netdev_priv(dev); 2003 int i; 2004 2005 if (netif_is_multiqueue(dev)) { 2006 for (i = 0; i < priv->hw_params->tx_queues; i++) 2007 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 2008 } 2009 2010 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 2011 } 2012 2013 /* Reallocate the SKB to put enough headroom in front of it and insert 2014 * the transmit checksum offsets in the descriptors 2015 */ 2016 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 2017 struct sk_buff *skb) 2018 { 2019 struct bcmgenet_priv *priv = netdev_priv(dev); 2020 struct status_64 *status = NULL; 2021 struct sk_buff *new_skb; 2022 u16 offset; 2023 u8 ip_proto; 2024 __be16 ip_ver; 2025 u32 tx_csum_info; 2026 2027 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 2028 /* If 64 byte status block enabled, must make sure skb has 2029 * enough headroom for us to insert 64B status block. 2030 */ 2031 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 2032 if (!new_skb) { 2033 dev_kfree_skb_any(skb); 2034 priv->mib.tx_realloc_tsb_failed++; 2035 dev->stats.tx_dropped++; 2036 return NULL; 2037 } 2038 dev_consume_skb_any(skb); 2039 skb = new_skb; 2040 priv->mib.tx_realloc_tsb++; 2041 } 2042 2043 skb_push(skb, sizeof(*status)); 2044 status = (struct status_64 *)skb->data; 2045 2046 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2047 ip_ver = skb->protocol; 2048 switch (ip_ver) { 2049 case htons(ETH_P_IP): 2050 ip_proto = ip_hdr(skb)->protocol; 2051 break; 2052 case htons(ETH_P_IPV6): 2053 ip_proto = ipv6_hdr(skb)->nexthdr; 2054 break; 2055 default: 2056 /* don't use UDP flag */ 2057 ip_proto = 0; 2058 break; 2059 } 2060 2061 offset = skb_checksum_start_offset(skb) - sizeof(*status); 2062 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 2063 (offset + skb->csum_offset) | 2064 STATUS_TX_CSUM_LV; 2065 2066 /* Set the special UDP flag for UDP */ 2067 if (ip_proto == IPPROTO_UDP) 2068 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 2069 2070 status->tx_csum_info = tx_csum_info; 2071 } 2072 2073 return skb; 2074 } 2075 2076 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2077 { 2078 struct bcmgenet_priv *priv = netdev_priv(dev); 2079 struct device *kdev = &priv->pdev->dev; 2080 struct bcmgenet_tx_ring *ring = NULL; 2081 struct enet_cb *tx_cb_ptr; 2082 struct netdev_queue *txq; 2083 int nr_frags, index; 2084 dma_addr_t mapping; 2085 unsigned int size; 2086 skb_frag_t *frag; 2087 u32 len_stat; 2088 int ret; 2089 int i; 2090 2091 index = skb_get_queue_mapping(skb); 2092 /* Mapping strategy: 2093 * queue_mapping = 0, unclassified, packet xmited through ring16 2094 * queue_mapping = 1, goes to ring 0. (highest priority queue 2095 * queue_mapping = 2, goes to ring 1. 2096 * queue_mapping = 3, goes to ring 2. 2097 * queue_mapping = 4, goes to ring 3. 2098 */ 2099 if (index == 0) 2100 index = DESC_INDEX; 2101 else 2102 index -= 1; 2103 2104 ring = &priv->tx_rings[index]; 2105 txq = netdev_get_tx_queue(dev, ring->queue); 2106 2107 nr_frags = skb_shinfo(skb)->nr_frags; 2108 2109 spin_lock(&ring->lock); 2110 if (ring->free_bds <= (nr_frags + 1)) { 2111 if (!netif_tx_queue_stopped(txq)) { 2112 netif_tx_stop_queue(txq); 2113 netdev_err(dev, 2114 "%s: tx ring %d full when queue %d awake\n", 2115 __func__, index, ring->queue); 2116 } 2117 ret = NETDEV_TX_BUSY; 2118 goto out; 2119 } 2120 2121 if (skb_padto(skb, ETH_ZLEN)) { 2122 ret = NETDEV_TX_OK; 2123 goto out; 2124 } 2125 2126 /* Retain how many bytes will be sent on the wire, without TSB inserted 2127 * by transmit checksum offload 2128 */ 2129 GENET_CB(skb)->bytes_sent = skb->len; 2130 2131 /* add the Transmit Status Block */ 2132 skb = bcmgenet_add_tsb(dev, skb); 2133 if (!skb) { 2134 ret = NETDEV_TX_OK; 2135 goto out; 2136 } 2137 2138 for (i = 0; i <= nr_frags; i++) { 2139 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2140 2141 BUG_ON(!tx_cb_ptr); 2142 2143 if (!i) { 2144 /* Transmit single SKB or head of fragment list */ 2145 GENET_CB(skb)->first_cb = tx_cb_ptr; 2146 size = skb_headlen(skb); 2147 mapping = dma_map_single(kdev, skb->data, size, 2148 DMA_TO_DEVICE); 2149 } else { 2150 /* xmit fragment */ 2151 frag = &skb_shinfo(skb)->frags[i - 1]; 2152 size = skb_frag_size(frag); 2153 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2154 DMA_TO_DEVICE); 2155 } 2156 2157 ret = dma_mapping_error(kdev, mapping); 2158 if (ret) { 2159 priv->mib.tx_dma_failed++; 2160 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2161 ret = NETDEV_TX_OK; 2162 goto out_unmap_frags; 2163 } 2164 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2165 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2166 2167 tx_cb_ptr->skb = skb; 2168 2169 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2170 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2171 2172 if (!i) { 2173 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 2174 if (skb->ip_summed == CHECKSUM_PARTIAL) 2175 len_stat |= DMA_TX_DO_CSUM; 2176 } 2177 if (i == nr_frags) 2178 len_stat |= DMA_EOP; 2179 2180 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2181 } 2182 2183 GENET_CB(skb)->last_cb = tx_cb_ptr; 2184 skb_tx_timestamp(skb); 2185 2186 /* Decrement total BD count and advance our write pointer */ 2187 ring->free_bds -= nr_frags + 1; 2188 ring->prod_index += nr_frags + 1; 2189 ring->prod_index &= DMA_P_INDEX_MASK; 2190 2191 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2192 2193 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2194 netif_tx_stop_queue(txq); 2195 2196 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2197 /* Packets are ready, update producer index */ 2198 bcmgenet_tdma_ring_writel(priv, ring->index, 2199 ring->prod_index, TDMA_PROD_INDEX); 2200 out: 2201 spin_unlock(&ring->lock); 2202 2203 return ret; 2204 2205 out_unmap_frags: 2206 /* Back up for failed control block mapping */ 2207 bcmgenet_put_txcb(priv, ring); 2208 2209 /* Unmap successfully mapped control blocks */ 2210 while (i-- > 0) { 2211 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2212 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2213 } 2214 2215 dev_kfree_skb(skb); 2216 goto out; 2217 } 2218 2219 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2220 struct enet_cb *cb) 2221 { 2222 struct device *kdev = &priv->pdev->dev; 2223 struct sk_buff *skb; 2224 struct sk_buff *rx_skb; 2225 dma_addr_t mapping; 2226 2227 /* Allocate a new Rx skb */ 2228 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2229 GFP_ATOMIC | __GFP_NOWARN); 2230 if (!skb) { 2231 priv->mib.alloc_rx_buff_failed++; 2232 netif_err(priv, rx_err, priv->dev, 2233 "%s: Rx skb allocation failed\n", __func__); 2234 return NULL; 2235 } 2236 2237 /* DMA-map the new Rx skb */ 2238 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2239 DMA_FROM_DEVICE); 2240 if (dma_mapping_error(kdev, mapping)) { 2241 priv->mib.rx_dma_failed++; 2242 dev_kfree_skb_any(skb); 2243 netif_err(priv, rx_err, priv->dev, 2244 "%s: Rx skb DMA mapping failed\n", __func__); 2245 return NULL; 2246 } 2247 2248 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2249 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2250 2251 /* Put the new Rx skb on the ring */ 2252 cb->skb = skb; 2253 dma_unmap_addr_set(cb, dma_addr, mapping); 2254 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2255 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2256 2257 /* Return the current Rx skb to caller */ 2258 return rx_skb; 2259 } 2260 2261 /* bcmgenet_desc_rx - descriptor based rx process. 2262 * this could be called from bottom half, or from NAPI polling method. 2263 */ 2264 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2265 unsigned int budget) 2266 { 2267 struct bcmgenet_priv *priv = ring->priv; 2268 struct net_device *dev = priv->dev; 2269 struct enet_cb *cb; 2270 struct sk_buff *skb; 2271 u32 dma_length_status; 2272 unsigned long dma_flag; 2273 int len; 2274 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2275 unsigned int bytes_processed = 0; 2276 unsigned int p_index, mask; 2277 unsigned int discards; 2278 2279 /* Clear status before servicing to reduce spurious interrupts */ 2280 if (ring->index == DESC_INDEX) { 2281 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 2282 INTRL2_CPU_CLEAR); 2283 } else { 2284 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2285 bcmgenet_intrl2_1_writel(priv, 2286 mask, 2287 INTRL2_CPU_CLEAR); 2288 } 2289 2290 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2291 2292 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2293 DMA_P_INDEX_DISCARD_CNT_MASK; 2294 if (discards > ring->old_discards) { 2295 discards = discards - ring->old_discards; 2296 ring->errors += discards; 2297 ring->old_discards += discards; 2298 2299 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2300 if (ring->old_discards >= 0xC000) { 2301 ring->old_discards = 0; 2302 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2303 RDMA_PROD_INDEX); 2304 } 2305 } 2306 2307 p_index &= DMA_P_INDEX_MASK; 2308 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2309 2310 netif_dbg(priv, rx_status, dev, 2311 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2312 2313 while ((rxpktprocessed < rxpkttoprocess) && 2314 (rxpktprocessed < budget)) { 2315 struct status_64 *status; 2316 __be16 rx_csum; 2317 2318 cb = &priv->rx_cbs[ring->read_ptr]; 2319 skb = bcmgenet_rx_refill(priv, cb); 2320 2321 if (unlikely(!skb)) { 2322 ring->dropped++; 2323 goto next; 2324 } 2325 2326 status = (struct status_64 *)skb->data; 2327 dma_length_status = status->length_status; 2328 if (dev->features & NETIF_F_RXCSUM) { 2329 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2330 skb->csum = (__force __wsum)ntohs(rx_csum); 2331 skb->ip_summed = CHECKSUM_COMPLETE; 2332 } 2333 2334 /* DMA flags and length are still valid no matter how 2335 * we got the Receive Status Vector (64B RSB or register) 2336 */ 2337 dma_flag = dma_length_status & 0xffff; 2338 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2339 2340 netif_dbg(priv, rx_status, dev, 2341 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2342 __func__, p_index, ring->c_index, 2343 ring->read_ptr, dma_length_status); 2344 2345 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2346 netif_err(priv, rx_status, dev, 2347 "dropping fragmented packet!\n"); 2348 ring->errors++; 2349 dev_kfree_skb_any(skb); 2350 goto next; 2351 } 2352 2353 /* report errors */ 2354 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2355 DMA_RX_OV | 2356 DMA_RX_NO | 2357 DMA_RX_LG | 2358 DMA_RX_RXER))) { 2359 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2360 (unsigned int)dma_flag); 2361 if (dma_flag & DMA_RX_CRC_ERROR) 2362 dev->stats.rx_crc_errors++; 2363 if (dma_flag & DMA_RX_OV) 2364 dev->stats.rx_over_errors++; 2365 if (dma_flag & DMA_RX_NO) 2366 dev->stats.rx_frame_errors++; 2367 if (dma_flag & DMA_RX_LG) 2368 dev->stats.rx_length_errors++; 2369 dev->stats.rx_errors++; 2370 dev_kfree_skb_any(skb); 2371 goto next; 2372 } /* error packet */ 2373 2374 skb_put(skb, len); 2375 2376 /* remove RSB and hardware 2bytes added for IP alignment */ 2377 skb_pull(skb, 66); 2378 len -= 66; 2379 2380 if (priv->crc_fwd_en) { 2381 skb_trim(skb, len - ETH_FCS_LEN); 2382 len -= ETH_FCS_LEN; 2383 } 2384 2385 bytes_processed += len; 2386 2387 /*Finish setting up the received SKB and send it to the kernel*/ 2388 skb->protocol = eth_type_trans(skb, priv->dev); 2389 ring->packets++; 2390 ring->bytes += len; 2391 if (dma_flag & DMA_RX_MULT) 2392 dev->stats.multicast++; 2393 2394 /* Notify kernel */ 2395 napi_gro_receive(&ring->napi, skb); 2396 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2397 2398 next: 2399 rxpktprocessed++; 2400 if (likely(ring->read_ptr < ring->end_ptr)) 2401 ring->read_ptr++; 2402 else 2403 ring->read_ptr = ring->cb_ptr; 2404 2405 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2406 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2407 } 2408 2409 ring->dim.bytes = bytes_processed; 2410 ring->dim.packets = rxpktprocessed; 2411 2412 return rxpktprocessed; 2413 } 2414 2415 /* Rx NAPI polling method */ 2416 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2417 { 2418 struct bcmgenet_rx_ring *ring = container_of(napi, 2419 struct bcmgenet_rx_ring, napi); 2420 struct dim_sample dim_sample = {}; 2421 unsigned int work_done; 2422 2423 work_done = bcmgenet_desc_rx(ring, budget); 2424 2425 if (work_done < budget) { 2426 napi_complete_done(napi, work_done); 2427 ring->int_enable(ring); 2428 } 2429 2430 if (ring->dim.use_dim) { 2431 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2432 ring->dim.bytes, &dim_sample); 2433 net_dim(&ring->dim.dim, dim_sample); 2434 } 2435 2436 return work_done; 2437 } 2438 2439 static void bcmgenet_dim_work(struct work_struct *work) 2440 { 2441 struct dim *dim = container_of(work, struct dim, work); 2442 struct bcmgenet_net_dim *ndim = 2443 container_of(dim, struct bcmgenet_net_dim, dim); 2444 struct bcmgenet_rx_ring *ring = 2445 container_of(ndim, struct bcmgenet_rx_ring, dim); 2446 struct dim_cq_moder cur_profile = 2447 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2448 2449 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2450 dim->state = DIM_START_MEASURE; 2451 } 2452 2453 /* Assign skb to RX DMA descriptor. */ 2454 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2455 struct bcmgenet_rx_ring *ring) 2456 { 2457 struct enet_cb *cb; 2458 struct sk_buff *skb; 2459 int i; 2460 2461 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2462 2463 /* loop here for each buffer needing assign */ 2464 for (i = 0; i < ring->size; i++) { 2465 cb = ring->cbs + i; 2466 skb = bcmgenet_rx_refill(priv, cb); 2467 if (skb) 2468 dev_consume_skb_any(skb); 2469 if (!cb->skb) 2470 return -ENOMEM; 2471 } 2472 2473 return 0; 2474 } 2475 2476 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2477 { 2478 struct sk_buff *skb; 2479 struct enet_cb *cb; 2480 int i; 2481 2482 for (i = 0; i < priv->num_rx_bds; i++) { 2483 cb = &priv->rx_cbs[i]; 2484 2485 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2486 if (skb) 2487 dev_consume_skb_any(skb); 2488 } 2489 } 2490 2491 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2492 { 2493 u32 reg; 2494 2495 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2496 if (reg & CMD_SW_RESET) 2497 return; 2498 if (enable) 2499 reg |= mask; 2500 else 2501 reg &= ~mask; 2502 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2503 2504 /* UniMAC stops on a packet boundary, wait for a full-size packet 2505 * to be processed 2506 */ 2507 if (enable == 0) 2508 usleep_range(1000, 2000); 2509 } 2510 2511 static void reset_umac(struct bcmgenet_priv *priv) 2512 { 2513 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2514 bcmgenet_rbuf_ctrl_set(priv, 0); 2515 udelay(10); 2516 2517 /* issue soft reset and disable MAC while updating its registers */ 2518 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2519 udelay(2); 2520 } 2521 2522 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2523 { 2524 /* Mask all interrupts.*/ 2525 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2526 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2527 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2528 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2529 } 2530 2531 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2532 { 2533 u32 int0_enable = 0; 2534 2535 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2536 * and MoCA PHY 2537 */ 2538 if (priv->internal_phy) { 2539 int0_enable |= UMAC_IRQ_LINK_EVENT; 2540 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2541 int0_enable |= UMAC_IRQ_PHY_DET_R; 2542 } else if (priv->ext_phy) { 2543 int0_enable |= UMAC_IRQ_LINK_EVENT; 2544 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2545 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2546 int0_enable |= UMAC_IRQ_LINK_EVENT; 2547 } 2548 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2549 } 2550 2551 static void init_umac(struct bcmgenet_priv *priv) 2552 { 2553 struct device *kdev = &priv->pdev->dev; 2554 u32 reg; 2555 u32 int0_enable = 0; 2556 2557 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2558 2559 reset_umac(priv); 2560 2561 /* clear tx/rx counter */ 2562 bcmgenet_umac_writel(priv, 2563 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2564 UMAC_MIB_CTRL); 2565 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2566 2567 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2568 2569 /* init tx registers, enable TSB */ 2570 reg = bcmgenet_tbuf_ctrl_get(priv); 2571 reg |= TBUF_64B_EN; 2572 bcmgenet_tbuf_ctrl_set(priv, reg); 2573 2574 /* init rx registers, enable ip header optimization and RSB */ 2575 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2576 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2577 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2578 2579 /* enable rx checksumming */ 2580 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2581 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2582 /* If UniMAC forwards CRC, we need to skip over it to get 2583 * a valid CHK bit to be set in the per-packet status word 2584 */ 2585 if (priv->crc_fwd_en) 2586 reg |= RBUF_SKIP_FCS; 2587 else 2588 reg &= ~RBUF_SKIP_FCS; 2589 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2590 2591 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2592 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2593 2594 bcmgenet_intr_disable(priv); 2595 2596 /* Configure backpressure vectors for MoCA */ 2597 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2598 reg = bcmgenet_bp_mc_get(priv); 2599 reg |= BIT(priv->hw_params->bp_in_en_shift); 2600 2601 /* bp_mask: back pressure mask */ 2602 if (netif_is_multiqueue(priv->dev)) 2603 reg |= priv->hw_params->bp_in_mask; 2604 else 2605 reg &= ~priv->hw_params->bp_in_mask; 2606 bcmgenet_bp_mc_set(priv, reg); 2607 } 2608 2609 /* Enable MDIO interrupts on GENET v3+ */ 2610 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2611 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2612 2613 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2614 2615 dev_dbg(kdev, "done init umac\n"); 2616 } 2617 2618 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2619 void (*cb)(struct work_struct *work)) 2620 { 2621 struct bcmgenet_net_dim *dim = &ring->dim; 2622 2623 INIT_WORK(&dim->dim.work, cb); 2624 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2625 dim->event_ctr = 0; 2626 dim->packets = 0; 2627 dim->bytes = 0; 2628 } 2629 2630 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2631 { 2632 struct bcmgenet_net_dim *dim = &ring->dim; 2633 struct dim_cq_moder moder; 2634 u32 usecs, pkts; 2635 2636 usecs = ring->rx_coalesce_usecs; 2637 pkts = ring->rx_max_coalesced_frames; 2638 2639 /* If DIM was enabled, re-apply default parameters */ 2640 if (dim->use_dim) { 2641 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2642 usecs = moder.usec; 2643 pkts = moder.pkts; 2644 } 2645 2646 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2647 } 2648 2649 /* Initialize a Tx ring along with corresponding hardware registers */ 2650 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2651 unsigned int index, unsigned int size, 2652 unsigned int start_ptr, unsigned int end_ptr) 2653 { 2654 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2655 u32 words_per_bd = WORDS_PER_BD(priv); 2656 u32 flow_period_val = 0; 2657 2658 spin_lock_init(&ring->lock); 2659 ring->priv = priv; 2660 ring->index = index; 2661 if (index == DESC_INDEX) { 2662 ring->queue = 0; 2663 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2664 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2665 } else { 2666 ring->queue = index + 1; 2667 ring->int_enable = bcmgenet_tx_ring_int_enable; 2668 ring->int_disable = bcmgenet_tx_ring_int_disable; 2669 } 2670 ring->cbs = priv->tx_cbs + start_ptr; 2671 ring->size = size; 2672 ring->clean_ptr = start_ptr; 2673 ring->c_index = 0; 2674 ring->free_bds = size; 2675 ring->write_ptr = start_ptr; 2676 ring->cb_ptr = start_ptr; 2677 ring->end_ptr = end_ptr - 1; 2678 ring->prod_index = 0; 2679 2680 /* Set flow period for ring != 16 */ 2681 if (index != DESC_INDEX) 2682 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2683 2684 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2685 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2686 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2687 /* Disable rate control for now */ 2688 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2689 TDMA_FLOW_PERIOD); 2690 bcmgenet_tdma_ring_writel(priv, index, 2691 ((size << DMA_RING_SIZE_SHIFT) | 2692 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2693 2694 /* Set start and end address, read and write pointers */ 2695 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2696 DMA_START_ADDR); 2697 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2698 TDMA_READ_PTR); 2699 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2700 TDMA_WRITE_PTR); 2701 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2702 DMA_END_ADDR); 2703 2704 /* Initialize Tx NAPI */ 2705 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2706 NAPI_POLL_WEIGHT); 2707 } 2708 2709 /* Initialize a RDMA ring */ 2710 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2711 unsigned int index, unsigned int size, 2712 unsigned int start_ptr, unsigned int end_ptr) 2713 { 2714 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2715 u32 words_per_bd = WORDS_PER_BD(priv); 2716 int ret; 2717 2718 ring->priv = priv; 2719 ring->index = index; 2720 if (index == DESC_INDEX) { 2721 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2722 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2723 } else { 2724 ring->int_enable = bcmgenet_rx_ring_int_enable; 2725 ring->int_disable = bcmgenet_rx_ring_int_disable; 2726 } 2727 ring->cbs = priv->rx_cbs + start_ptr; 2728 ring->size = size; 2729 ring->c_index = 0; 2730 ring->read_ptr = start_ptr; 2731 ring->cb_ptr = start_ptr; 2732 ring->end_ptr = end_ptr - 1; 2733 2734 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2735 if (ret) 2736 return ret; 2737 2738 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2739 bcmgenet_init_rx_coalesce(ring); 2740 2741 /* Initialize Rx NAPI */ 2742 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2743 NAPI_POLL_WEIGHT); 2744 2745 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2746 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2747 bcmgenet_rdma_ring_writel(priv, index, 2748 ((size << DMA_RING_SIZE_SHIFT) | 2749 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2750 bcmgenet_rdma_ring_writel(priv, index, 2751 (DMA_FC_THRESH_LO << 2752 DMA_XOFF_THRESHOLD_SHIFT) | 2753 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2754 2755 /* Set start and end address, read and write pointers */ 2756 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2757 DMA_START_ADDR); 2758 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2759 RDMA_READ_PTR); 2760 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2761 RDMA_WRITE_PTR); 2762 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2763 DMA_END_ADDR); 2764 2765 return ret; 2766 } 2767 2768 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2769 { 2770 unsigned int i; 2771 struct bcmgenet_tx_ring *ring; 2772 2773 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2774 ring = &priv->tx_rings[i]; 2775 napi_enable(&ring->napi); 2776 ring->int_enable(ring); 2777 } 2778 2779 ring = &priv->tx_rings[DESC_INDEX]; 2780 napi_enable(&ring->napi); 2781 ring->int_enable(ring); 2782 } 2783 2784 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2785 { 2786 unsigned int i; 2787 struct bcmgenet_tx_ring *ring; 2788 2789 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2790 ring = &priv->tx_rings[i]; 2791 napi_disable(&ring->napi); 2792 } 2793 2794 ring = &priv->tx_rings[DESC_INDEX]; 2795 napi_disable(&ring->napi); 2796 } 2797 2798 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2799 { 2800 unsigned int i; 2801 struct bcmgenet_tx_ring *ring; 2802 2803 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2804 ring = &priv->tx_rings[i]; 2805 netif_napi_del(&ring->napi); 2806 } 2807 2808 ring = &priv->tx_rings[DESC_INDEX]; 2809 netif_napi_del(&ring->napi); 2810 } 2811 2812 /* Initialize Tx queues 2813 * 2814 * Queues 0-3 are priority-based, each one has 32 descriptors, 2815 * with queue 0 being the highest priority queue. 2816 * 2817 * Queue 16 is the default Tx queue with 2818 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2819 * 2820 * The transmit control block pool is then partitioned as follows: 2821 * - Tx queue 0 uses tx_cbs[0..31] 2822 * - Tx queue 1 uses tx_cbs[32..63] 2823 * - Tx queue 2 uses tx_cbs[64..95] 2824 * - Tx queue 3 uses tx_cbs[96..127] 2825 * - Tx queue 16 uses tx_cbs[128..255] 2826 */ 2827 static void bcmgenet_init_tx_queues(struct net_device *dev) 2828 { 2829 struct bcmgenet_priv *priv = netdev_priv(dev); 2830 u32 i, dma_enable; 2831 u32 dma_ctrl, ring_cfg; 2832 u32 dma_priority[3] = {0, 0, 0}; 2833 2834 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2835 dma_enable = dma_ctrl & DMA_EN; 2836 dma_ctrl &= ~DMA_EN; 2837 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2838 2839 dma_ctrl = 0; 2840 ring_cfg = 0; 2841 2842 /* Enable strict priority arbiter mode */ 2843 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2844 2845 /* Initialize Tx priority queues */ 2846 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2847 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2848 i * priv->hw_params->tx_bds_per_q, 2849 (i + 1) * priv->hw_params->tx_bds_per_q); 2850 ring_cfg |= (1 << i); 2851 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2852 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2853 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2854 } 2855 2856 /* Initialize Tx default queue 16 */ 2857 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2858 priv->hw_params->tx_queues * 2859 priv->hw_params->tx_bds_per_q, 2860 TOTAL_DESC); 2861 ring_cfg |= (1 << DESC_INDEX); 2862 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2863 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2864 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2865 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2866 2867 /* Set Tx queue priorities */ 2868 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2869 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2870 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2871 2872 /* Enable Tx queues */ 2873 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2874 2875 /* Enable Tx DMA */ 2876 if (dma_enable) 2877 dma_ctrl |= DMA_EN; 2878 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2879 } 2880 2881 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2882 { 2883 unsigned int i; 2884 struct bcmgenet_rx_ring *ring; 2885 2886 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2887 ring = &priv->rx_rings[i]; 2888 napi_enable(&ring->napi); 2889 ring->int_enable(ring); 2890 } 2891 2892 ring = &priv->rx_rings[DESC_INDEX]; 2893 napi_enable(&ring->napi); 2894 ring->int_enable(ring); 2895 } 2896 2897 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2898 { 2899 unsigned int i; 2900 struct bcmgenet_rx_ring *ring; 2901 2902 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2903 ring = &priv->rx_rings[i]; 2904 napi_disable(&ring->napi); 2905 cancel_work_sync(&ring->dim.dim.work); 2906 } 2907 2908 ring = &priv->rx_rings[DESC_INDEX]; 2909 napi_disable(&ring->napi); 2910 cancel_work_sync(&ring->dim.dim.work); 2911 } 2912 2913 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2914 { 2915 unsigned int i; 2916 struct bcmgenet_rx_ring *ring; 2917 2918 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2919 ring = &priv->rx_rings[i]; 2920 netif_napi_del(&ring->napi); 2921 } 2922 2923 ring = &priv->rx_rings[DESC_INDEX]; 2924 netif_napi_del(&ring->napi); 2925 } 2926 2927 /* Initialize Rx queues 2928 * 2929 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2930 * used to direct traffic to these queues. 2931 * 2932 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2933 */ 2934 static int bcmgenet_init_rx_queues(struct net_device *dev) 2935 { 2936 struct bcmgenet_priv *priv = netdev_priv(dev); 2937 u32 i; 2938 u32 dma_enable; 2939 u32 dma_ctrl; 2940 u32 ring_cfg; 2941 int ret; 2942 2943 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2944 dma_enable = dma_ctrl & DMA_EN; 2945 dma_ctrl &= ~DMA_EN; 2946 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2947 2948 dma_ctrl = 0; 2949 ring_cfg = 0; 2950 2951 /* Initialize Rx priority queues */ 2952 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2953 ret = bcmgenet_init_rx_ring(priv, i, 2954 priv->hw_params->rx_bds_per_q, 2955 i * priv->hw_params->rx_bds_per_q, 2956 (i + 1) * 2957 priv->hw_params->rx_bds_per_q); 2958 if (ret) 2959 return ret; 2960 2961 ring_cfg |= (1 << i); 2962 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2963 } 2964 2965 /* Initialize Rx default queue 16 */ 2966 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2967 priv->hw_params->rx_queues * 2968 priv->hw_params->rx_bds_per_q, 2969 TOTAL_DESC); 2970 if (ret) 2971 return ret; 2972 2973 ring_cfg |= (1 << DESC_INDEX); 2974 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2975 2976 /* Enable rings */ 2977 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2978 2979 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2980 if (dma_enable) 2981 dma_ctrl |= DMA_EN; 2982 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2983 2984 return 0; 2985 } 2986 2987 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2988 { 2989 int ret = 0; 2990 int timeout = 0; 2991 u32 reg; 2992 u32 dma_ctrl; 2993 int i; 2994 2995 /* Disable TDMA to stop add more frames in TX DMA */ 2996 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2997 reg &= ~DMA_EN; 2998 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2999 3000 /* Check TDMA status register to confirm TDMA is disabled */ 3001 while (timeout++ < DMA_TIMEOUT_VAL) { 3002 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 3003 if (reg & DMA_DISABLED) 3004 break; 3005 3006 udelay(1); 3007 } 3008 3009 if (timeout == DMA_TIMEOUT_VAL) { 3010 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 3011 ret = -ETIMEDOUT; 3012 } 3013 3014 /* Wait 10ms for packet drain in both tx and rx dma */ 3015 usleep_range(10000, 20000); 3016 3017 /* Disable RDMA */ 3018 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3019 reg &= ~DMA_EN; 3020 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3021 3022 timeout = 0; 3023 /* Check RDMA status register to confirm RDMA is disabled */ 3024 while (timeout++ < DMA_TIMEOUT_VAL) { 3025 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 3026 if (reg & DMA_DISABLED) 3027 break; 3028 3029 udelay(1); 3030 } 3031 3032 if (timeout == DMA_TIMEOUT_VAL) { 3033 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 3034 ret = -ETIMEDOUT; 3035 } 3036 3037 dma_ctrl = 0; 3038 for (i = 0; i < priv->hw_params->rx_queues; i++) 3039 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3040 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3041 reg &= ~dma_ctrl; 3042 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3043 3044 dma_ctrl = 0; 3045 for (i = 0; i < priv->hw_params->tx_queues; i++) 3046 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3047 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3048 reg &= ~dma_ctrl; 3049 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3050 3051 return ret; 3052 } 3053 3054 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 3055 { 3056 struct netdev_queue *txq; 3057 int i; 3058 3059 bcmgenet_fini_rx_napi(priv); 3060 bcmgenet_fini_tx_napi(priv); 3061 3062 for (i = 0; i < priv->num_tx_bds; i++) 3063 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 3064 priv->tx_cbs + i)); 3065 3066 for (i = 0; i < priv->hw_params->tx_queues; i++) { 3067 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 3068 netdev_tx_reset_queue(txq); 3069 } 3070 3071 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 3072 netdev_tx_reset_queue(txq); 3073 3074 bcmgenet_free_rx_buffers(priv); 3075 kfree(priv->rx_cbs); 3076 kfree(priv->tx_cbs); 3077 } 3078 3079 /* init_edma: Initialize DMA control register */ 3080 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 3081 { 3082 int ret; 3083 unsigned int i; 3084 struct enet_cb *cb; 3085 3086 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3087 3088 /* Initialize common Rx ring structures */ 3089 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3090 priv->num_rx_bds = TOTAL_DESC; 3091 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3092 GFP_KERNEL); 3093 if (!priv->rx_cbs) 3094 return -ENOMEM; 3095 3096 for (i = 0; i < priv->num_rx_bds; i++) { 3097 cb = priv->rx_cbs + i; 3098 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3099 } 3100 3101 /* Initialize common TX ring structures */ 3102 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3103 priv->num_tx_bds = TOTAL_DESC; 3104 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3105 GFP_KERNEL); 3106 if (!priv->tx_cbs) { 3107 kfree(priv->rx_cbs); 3108 return -ENOMEM; 3109 } 3110 3111 for (i = 0; i < priv->num_tx_bds; i++) { 3112 cb = priv->tx_cbs + i; 3113 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3114 } 3115 3116 /* Init rDma */ 3117 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3118 DMA_SCB_BURST_SIZE); 3119 3120 /* Initialize Rx queues */ 3121 ret = bcmgenet_init_rx_queues(priv->dev); 3122 if (ret) { 3123 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3124 bcmgenet_free_rx_buffers(priv); 3125 kfree(priv->rx_cbs); 3126 kfree(priv->tx_cbs); 3127 return ret; 3128 } 3129 3130 /* Init tDma */ 3131 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3132 DMA_SCB_BURST_SIZE); 3133 3134 /* Initialize Tx queues */ 3135 bcmgenet_init_tx_queues(priv->dev); 3136 3137 return 0; 3138 } 3139 3140 /* Interrupt bottom half */ 3141 static void bcmgenet_irq_task(struct work_struct *work) 3142 { 3143 unsigned int status; 3144 struct bcmgenet_priv *priv = container_of( 3145 work, struct bcmgenet_priv, bcmgenet_irq_work); 3146 3147 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3148 3149 spin_lock_irq(&priv->lock); 3150 status = priv->irq0_stat; 3151 priv->irq0_stat = 0; 3152 spin_unlock_irq(&priv->lock); 3153 3154 if (status & UMAC_IRQ_PHY_DET_R && 3155 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3156 phy_init_hw(priv->dev->phydev); 3157 genphy_config_aneg(priv->dev->phydev); 3158 } 3159 3160 /* Link UP/DOWN event */ 3161 if (status & UMAC_IRQ_LINK_EVENT) 3162 phy_mac_interrupt(priv->dev->phydev); 3163 3164 } 3165 3166 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 3167 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3168 { 3169 struct bcmgenet_priv *priv = dev_id; 3170 struct bcmgenet_rx_ring *rx_ring; 3171 struct bcmgenet_tx_ring *tx_ring; 3172 unsigned int index, status; 3173 3174 /* Read irq status */ 3175 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3176 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3177 3178 /* clear interrupts */ 3179 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3180 3181 netif_dbg(priv, intr, priv->dev, 3182 "%s: IRQ=0x%x\n", __func__, status); 3183 3184 /* Check Rx priority queue interrupts */ 3185 for (index = 0; index < priv->hw_params->rx_queues; index++) { 3186 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3187 continue; 3188 3189 rx_ring = &priv->rx_rings[index]; 3190 rx_ring->dim.event_ctr++; 3191 3192 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3193 rx_ring->int_disable(rx_ring); 3194 __napi_schedule_irqoff(&rx_ring->napi); 3195 } 3196 } 3197 3198 /* Check Tx priority queue interrupts */ 3199 for (index = 0; index < priv->hw_params->tx_queues; index++) { 3200 if (!(status & BIT(index))) 3201 continue; 3202 3203 tx_ring = &priv->tx_rings[index]; 3204 3205 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3206 tx_ring->int_disable(tx_ring); 3207 __napi_schedule_irqoff(&tx_ring->napi); 3208 } 3209 } 3210 3211 return IRQ_HANDLED; 3212 } 3213 3214 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 3215 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3216 { 3217 struct bcmgenet_priv *priv = dev_id; 3218 struct bcmgenet_rx_ring *rx_ring; 3219 struct bcmgenet_tx_ring *tx_ring; 3220 unsigned int status; 3221 unsigned long flags; 3222 3223 /* Read irq status */ 3224 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3225 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3226 3227 /* clear interrupts */ 3228 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3229 3230 netif_dbg(priv, intr, priv->dev, 3231 "IRQ=0x%x\n", status); 3232 3233 if (status & UMAC_IRQ_RXDMA_DONE) { 3234 rx_ring = &priv->rx_rings[DESC_INDEX]; 3235 rx_ring->dim.event_ctr++; 3236 3237 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3238 rx_ring->int_disable(rx_ring); 3239 __napi_schedule_irqoff(&rx_ring->napi); 3240 } 3241 } 3242 3243 if (status & UMAC_IRQ_TXDMA_DONE) { 3244 tx_ring = &priv->tx_rings[DESC_INDEX]; 3245 3246 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3247 tx_ring->int_disable(tx_ring); 3248 __napi_schedule_irqoff(&tx_ring->napi); 3249 } 3250 } 3251 3252 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 3253 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 3254 wake_up(&priv->wq); 3255 } 3256 3257 /* all other interested interrupts handled in bottom half */ 3258 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3259 if (status) { 3260 /* Save irq status for bottom-half processing. */ 3261 spin_lock_irqsave(&priv->lock, flags); 3262 priv->irq0_stat |= status; 3263 spin_unlock_irqrestore(&priv->lock, flags); 3264 3265 schedule_work(&priv->bcmgenet_irq_work); 3266 } 3267 3268 return IRQ_HANDLED; 3269 } 3270 3271 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3272 { 3273 /* Acknowledge the interrupt */ 3274 return IRQ_HANDLED; 3275 } 3276 3277 #ifdef CONFIG_NET_POLL_CONTROLLER 3278 static void bcmgenet_poll_controller(struct net_device *dev) 3279 { 3280 struct bcmgenet_priv *priv = netdev_priv(dev); 3281 3282 /* Invoke the main RX/TX interrupt handler */ 3283 disable_irq(priv->irq0); 3284 bcmgenet_isr0(priv->irq0, priv); 3285 enable_irq(priv->irq0); 3286 3287 /* And the interrupt handler for RX/TX priority queues */ 3288 disable_irq(priv->irq1); 3289 bcmgenet_isr1(priv->irq1, priv); 3290 enable_irq(priv->irq1); 3291 } 3292 #endif 3293 3294 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3295 { 3296 u32 reg; 3297 3298 reg = bcmgenet_rbuf_ctrl_get(priv); 3299 reg |= BIT(1); 3300 bcmgenet_rbuf_ctrl_set(priv, reg); 3301 udelay(10); 3302 3303 reg &= ~BIT(1); 3304 bcmgenet_rbuf_ctrl_set(priv, reg); 3305 udelay(10); 3306 } 3307 3308 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3309 unsigned char *addr) 3310 { 3311 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3312 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3313 } 3314 3315 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3316 unsigned char *addr) 3317 { 3318 u32 addr_tmp; 3319 3320 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3321 put_unaligned_be32(addr_tmp, &addr[0]); 3322 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3323 put_unaligned_be16(addr_tmp, &addr[4]); 3324 } 3325 3326 /* Returns a reusable dma control register value */ 3327 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 3328 { 3329 u32 reg; 3330 u32 dma_ctrl; 3331 3332 /* disable DMA */ 3333 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3334 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3335 reg &= ~dma_ctrl; 3336 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3337 3338 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3339 reg &= ~dma_ctrl; 3340 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3341 3342 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3343 udelay(10); 3344 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3345 3346 return dma_ctrl; 3347 } 3348 3349 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 3350 { 3351 u32 reg; 3352 3353 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3354 reg |= dma_ctrl; 3355 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3356 3357 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3358 reg |= dma_ctrl; 3359 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3360 } 3361 3362 static void bcmgenet_netif_start(struct net_device *dev) 3363 { 3364 struct bcmgenet_priv *priv = netdev_priv(dev); 3365 3366 /* Start the network engine */ 3367 bcmgenet_set_rx_mode(dev); 3368 bcmgenet_enable_rx_napi(priv); 3369 3370 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3371 3372 bcmgenet_enable_tx_napi(priv); 3373 3374 /* Monitor link interrupts now */ 3375 bcmgenet_link_intr_enable(priv); 3376 3377 phy_start(dev->phydev); 3378 } 3379 3380 static int bcmgenet_open(struct net_device *dev) 3381 { 3382 struct bcmgenet_priv *priv = netdev_priv(dev); 3383 unsigned long dma_ctrl; 3384 u32 reg; 3385 int ret; 3386 3387 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3388 3389 /* Turn on the clock */ 3390 clk_prepare_enable(priv->clk); 3391 3392 /* If this is an internal GPHY, power it back on now, before UniMAC is 3393 * brought out of reset as absolutely no UniMAC activity is allowed 3394 */ 3395 if (priv->internal_phy) 3396 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3397 3398 /* take MAC out of reset */ 3399 bcmgenet_umac_reset(priv); 3400 3401 init_umac(priv); 3402 3403 /* Apply features again in case we changed them while interface was 3404 * down 3405 */ 3406 bcmgenet_set_features(dev, dev->features); 3407 3408 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3409 3410 if (priv->internal_phy) { 3411 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3412 reg |= EXT_ENERGY_DET_MASK; 3413 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3414 } 3415 3416 /* Disable RX/TX DMA and flush TX queues */ 3417 dma_ctrl = bcmgenet_dma_disable(priv); 3418 3419 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3420 ret = bcmgenet_init_dma(priv); 3421 if (ret) { 3422 netdev_err(dev, "failed to initialize DMA\n"); 3423 goto err_clk_disable; 3424 } 3425 3426 /* Always enable ring 16 - descriptor ring */ 3427 bcmgenet_enable_dma(priv, dma_ctrl); 3428 3429 /* HFB init */ 3430 bcmgenet_hfb_init(priv); 3431 3432 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3433 dev->name, priv); 3434 if (ret < 0) { 3435 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3436 goto err_fini_dma; 3437 } 3438 3439 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3440 dev->name, priv); 3441 if (ret < 0) { 3442 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3443 goto err_irq0; 3444 } 3445 3446 ret = bcmgenet_mii_probe(dev); 3447 if (ret) { 3448 netdev_err(dev, "failed to connect to PHY\n"); 3449 goto err_irq1; 3450 } 3451 3452 bcmgenet_netif_start(dev); 3453 3454 netif_tx_start_all_queues(dev); 3455 3456 return 0; 3457 3458 err_irq1: 3459 free_irq(priv->irq1, priv); 3460 err_irq0: 3461 free_irq(priv->irq0, priv); 3462 err_fini_dma: 3463 bcmgenet_dma_teardown(priv); 3464 bcmgenet_fini_dma(priv); 3465 err_clk_disable: 3466 if (priv->internal_phy) 3467 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3468 clk_disable_unprepare(priv->clk); 3469 return ret; 3470 } 3471 3472 static void bcmgenet_netif_stop(struct net_device *dev) 3473 { 3474 struct bcmgenet_priv *priv = netdev_priv(dev); 3475 3476 bcmgenet_disable_tx_napi(priv); 3477 netif_tx_disable(dev); 3478 3479 /* Disable MAC receive */ 3480 umac_enable_set(priv, CMD_RX_EN, false); 3481 3482 bcmgenet_dma_teardown(priv); 3483 3484 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3485 umac_enable_set(priv, CMD_TX_EN, false); 3486 3487 phy_stop(dev->phydev); 3488 bcmgenet_disable_rx_napi(priv); 3489 bcmgenet_intr_disable(priv); 3490 3491 /* Wait for pending work items to complete. Since interrupts are 3492 * disabled no new work will be scheduled. 3493 */ 3494 cancel_work_sync(&priv->bcmgenet_irq_work); 3495 3496 priv->old_link = -1; 3497 priv->old_speed = -1; 3498 priv->old_duplex = -1; 3499 priv->old_pause = -1; 3500 3501 /* tx reclaim */ 3502 bcmgenet_tx_reclaim_all(dev); 3503 bcmgenet_fini_dma(priv); 3504 } 3505 3506 static int bcmgenet_close(struct net_device *dev) 3507 { 3508 struct bcmgenet_priv *priv = netdev_priv(dev); 3509 int ret = 0; 3510 3511 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3512 3513 bcmgenet_netif_stop(dev); 3514 3515 /* Really kill the PHY state machine and disconnect from it */ 3516 phy_disconnect(dev->phydev); 3517 3518 free_irq(priv->irq0, priv); 3519 free_irq(priv->irq1, priv); 3520 3521 if (priv->internal_phy) 3522 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3523 3524 clk_disable_unprepare(priv->clk); 3525 3526 return ret; 3527 } 3528 3529 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3530 { 3531 struct bcmgenet_priv *priv = ring->priv; 3532 u32 p_index, c_index, intsts, intmsk; 3533 struct netdev_queue *txq; 3534 unsigned int free_bds; 3535 bool txq_stopped; 3536 3537 if (!netif_msg_tx_err(priv)) 3538 return; 3539 3540 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3541 3542 spin_lock(&ring->lock); 3543 if (ring->index == DESC_INDEX) { 3544 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3545 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3546 } else { 3547 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3548 intmsk = 1 << ring->index; 3549 } 3550 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3551 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3552 txq_stopped = netif_tx_queue_stopped(txq); 3553 free_bds = ring->free_bds; 3554 spin_unlock(&ring->lock); 3555 3556 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3557 "TX queue status: %s, interrupts: %s\n" 3558 "(sw)free_bds: %d (sw)size: %d\n" 3559 "(sw)p_index: %d (hw)p_index: %d\n" 3560 "(sw)c_index: %d (hw)c_index: %d\n" 3561 "(sw)clean_p: %d (sw)write_p: %d\n" 3562 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3563 ring->index, ring->queue, 3564 txq_stopped ? "stopped" : "active", 3565 intsts & intmsk ? "enabled" : "disabled", 3566 free_bds, ring->size, 3567 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3568 ring->c_index, c_index & DMA_C_INDEX_MASK, 3569 ring->clean_ptr, ring->write_ptr, 3570 ring->cb_ptr, ring->end_ptr); 3571 } 3572 3573 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3574 { 3575 struct bcmgenet_priv *priv = netdev_priv(dev); 3576 u32 int0_enable = 0; 3577 u32 int1_enable = 0; 3578 unsigned int q; 3579 3580 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3581 3582 for (q = 0; q < priv->hw_params->tx_queues; q++) 3583 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3584 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3585 3586 bcmgenet_tx_reclaim_all(dev); 3587 3588 for (q = 0; q < priv->hw_params->tx_queues; q++) 3589 int1_enable |= (1 << q); 3590 3591 int0_enable = UMAC_IRQ_TXDMA_DONE; 3592 3593 /* Re-enable TX interrupts if disabled */ 3594 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3595 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3596 3597 netif_trans_update(dev); 3598 3599 dev->stats.tx_errors++; 3600 3601 netif_tx_wake_all_queues(dev); 3602 } 3603 3604 #define MAX_MDF_FILTER 17 3605 3606 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3607 unsigned char *addr, 3608 int *i) 3609 { 3610 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3611 UMAC_MDF_ADDR + (*i * 4)); 3612 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3613 addr[4] << 8 | addr[5], 3614 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3615 *i += 2; 3616 } 3617 3618 static void bcmgenet_set_rx_mode(struct net_device *dev) 3619 { 3620 struct bcmgenet_priv *priv = netdev_priv(dev); 3621 struct netdev_hw_addr *ha; 3622 int i, nfilter; 3623 u32 reg; 3624 3625 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3626 3627 /* Number of filters needed */ 3628 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3629 3630 /* 3631 * Turn on promicuous mode for three scenarios 3632 * 1. IFF_PROMISC flag is set 3633 * 2. IFF_ALLMULTI flag is set 3634 * 3. The number of filters needed exceeds the number filters 3635 * supported by the hardware. 3636 */ 3637 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3638 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3639 (nfilter > MAX_MDF_FILTER)) { 3640 reg |= CMD_PROMISC; 3641 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3642 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3643 return; 3644 } else { 3645 reg &= ~CMD_PROMISC; 3646 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3647 } 3648 3649 /* update MDF filter */ 3650 i = 0; 3651 /* Broadcast */ 3652 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3653 /* my own address.*/ 3654 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3655 3656 /* Unicast */ 3657 netdev_for_each_uc_addr(ha, dev) 3658 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3659 3660 /* Multicast */ 3661 netdev_for_each_mc_addr(ha, dev) 3662 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3663 3664 /* Enable filters */ 3665 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3666 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3667 } 3668 3669 /* Set the hardware MAC address. */ 3670 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3671 { 3672 struct sockaddr *addr = p; 3673 3674 /* Setting the MAC address at the hardware level is not possible 3675 * without disabling the UniMAC RX/TX enable bits. 3676 */ 3677 if (netif_running(dev)) 3678 return -EBUSY; 3679 3680 ether_addr_copy(dev->dev_addr, addr->sa_data); 3681 3682 return 0; 3683 } 3684 3685 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3686 { 3687 struct bcmgenet_priv *priv = netdev_priv(dev); 3688 unsigned long tx_bytes = 0, tx_packets = 0; 3689 unsigned long rx_bytes = 0, rx_packets = 0; 3690 unsigned long rx_errors = 0, rx_dropped = 0; 3691 struct bcmgenet_tx_ring *tx_ring; 3692 struct bcmgenet_rx_ring *rx_ring; 3693 unsigned int q; 3694 3695 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3696 tx_ring = &priv->tx_rings[q]; 3697 tx_bytes += tx_ring->bytes; 3698 tx_packets += tx_ring->packets; 3699 } 3700 tx_ring = &priv->tx_rings[DESC_INDEX]; 3701 tx_bytes += tx_ring->bytes; 3702 tx_packets += tx_ring->packets; 3703 3704 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3705 rx_ring = &priv->rx_rings[q]; 3706 3707 rx_bytes += rx_ring->bytes; 3708 rx_packets += rx_ring->packets; 3709 rx_errors += rx_ring->errors; 3710 rx_dropped += rx_ring->dropped; 3711 } 3712 rx_ring = &priv->rx_rings[DESC_INDEX]; 3713 rx_bytes += rx_ring->bytes; 3714 rx_packets += rx_ring->packets; 3715 rx_errors += rx_ring->errors; 3716 rx_dropped += rx_ring->dropped; 3717 3718 dev->stats.tx_bytes = tx_bytes; 3719 dev->stats.tx_packets = tx_packets; 3720 dev->stats.rx_bytes = rx_bytes; 3721 dev->stats.rx_packets = rx_packets; 3722 dev->stats.rx_errors = rx_errors; 3723 dev->stats.rx_missed_errors = rx_errors; 3724 dev->stats.rx_dropped = rx_dropped; 3725 return &dev->stats; 3726 } 3727 3728 static const struct net_device_ops bcmgenet_netdev_ops = { 3729 .ndo_open = bcmgenet_open, 3730 .ndo_stop = bcmgenet_close, 3731 .ndo_start_xmit = bcmgenet_xmit, 3732 .ndo_tx_timeout = bcmgenet_timeout, 3733 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3734 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3735 .ndo_do_ioctl = phy_do_ioctl_running, 3736 .ndo_set_features = bcmgenet_set_features, 3737 #ifdef CONFIG_NET_POLL_CONTROLLER 3738 .ndo_poll_controller = bcmgenet_poll_controller, 3739 #endif 3740 .ndo_get_stats = bcmgenet_get_stats, 3741 }; 3742 3743 /* Array of GENET hardware parameters/characteristics */ 3744 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3745 [GENET_V1] = { 3746 .tx_queues = 0, 3747 .tx_bds_per_q = 0, 3748 .rx_queues = 0, 3749 .rx_bds_per_q = 0, 3750 .bp_in_en_shift = 16, 3751 .bp_in_mask = 0xffff, 3752 .hfb_filter_cnt = 16, 3753 .qtag_mask = 0x1F, 3754 .hfb_offset = 0x1000, 3755 .rdma_offset = 0x2000, 3756 .tdma_offset = 0x3000, 3757 .words_per_bd = 2, 3758 }, 3759 [GENET_V2] = { 3760 .tx_queues = 4, 3761 .tx_bds_per_q = 32, 3762 .rx_queues = 0, 3763 .rx_bds_per_q = 0, 3764 .bp_in_en_shift = 16, 3765 .bp_in_mask = 0xffff, 3766 .hfb_filter_cnt = 16, 3767 .qtag_mask = 0x1F, 3768 .tbuf_offset = 0x0600, 3769 .hfb_offset = 0x1000, 3770 .hfb_reg_offset = 0x2000, 3771 .rdma_offset = 0x3000, 3772 .tdma_offset = 0x4000, 3773 .words_per_bd = 2, 3774 .flags = GENET_HAS_EXT, 3775 }, 3776 [GENET_V3] = { 3777 .tx_queues = 4, 3778 .tx_bds_per_q = 32, 3779 .rx_queues = 0, 3780 .rx_bds_per_q = 0, 3781 .bp_in_en_shift = 17, 3782 .bp_in_mask = 0x1ffff, 3783 .hfb_filter_cnt = 48, 3784 .hfb_filter_size = 128, 3785 .qtag_mask = 0x3F, 3786 .tbuf_offset = 0x0600, 3787 .hfb_offset = 0x8000, 3788 .hfb_reg_offset = 0xfc00, 3789 .rdma_offset = 0x10000, 3790 .tdma_offset = 0x11000, 3791 .words_per_bd = 2, 3792 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3793 GENET_HAS_MOCA_LINK_DET, 3794 }, 3795 [GENET_V4] = { 3796 .tx_queues = 4, 3797 .tx_bds_per_q = 32, 3798 .rx_queues = 0, 3799 .rx_bds_per_q = 0, 3800 .bp_in_en_shift = 17, 3801 .bp_in_mask = 0x1ffff, 3802 .hfb_filter_cnt = 48, 3803 .hfb_filter_size = 128, 3804 .qtag_mask = 0x3F, 3805 .tbuf_offset = 0x0600, 3806 .hfb_offset = 0x8000, 3807 .hfb_reg_offset = 0xfc00, 3808 .rdma_offset = 0x2000, 3809 .tdma_offset = 0x4000, 3810 .words_per_bd = 3, 3811 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3812 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3813 }, 3814 [GENET_V5] = { 3815 .tx_queues = 4, 3816 .tx_bds_per_q = 32, 3817 .rx_queues = 0, 3818 .rx_bds_per_q = 0, 3819 .bp_in_en_shift = 17, 3820 .bp_in_mask = 0x1ffff, 3821 .hfb_filter_cnt = 48, 3822 .hfb_filter_size = 128, 3823 .qtag_mask = 0x3F, 3824 .tbuf_offset = 0x0600, 3825 .hfb_offset = 0x8000, 3826 .hfb_reg_offset = 0xfc00, 3827 .rdma_offset = 0x2000, 3828 .tdma_offset = 0x4000, 3829 .words_per_bd = 3, 3830 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3831 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3832 }, 3833 }; 3834 3835 /* Infer hardware parameters from the detected GENET version */ 3836 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3837 { 3838 struct bcmgenet_hw_params *params; 3839 u32 reg; 3840 u8 major; 3841 u16 gphy_rev; 3842 3843 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3844 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3845 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3846 } else if (GENET_IS_V3(priv)) { 3847 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3848 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3849 } else if (GENET_IS_V2(priv)) { 3850 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3851 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3852 } else if (GENET_IS_V1(priv)) { 3853 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3854 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3855 } 3856 3857 /* enum genet_version starts at 1 */ 3858 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3859 params = priv->hw_params; 3860 3861 /* Read GENET HW version */ 3862 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3863 major = (reg >> 24 & 0x0f); 3864 if (major == 6) 3865 major = 5; 3866 else if (major == 5) 3867 major = 4; 3868 else if (major == 0) 3869 major = 1; 3870 if (major != priv->version) { 3871 dev_err(&priv->pdev->dev, 3872 "GENET version mismatch, got: %d, configured for: %d\n", 3873 major, priv->version); 3874 } 3875 3876 /* Print the GENET core version */ 3877 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3878 major, (reg >> 16) & 0x0f, reg & 0xffff); 3879 3880 /* Store the integrated PHY revision for the MDIO probing function 3881 * to pass this information to the PHY driver. The PHY driver expects 3882 * to find the PHY major revision in bits 15:8 while the GENET register 3883 * stores that information in bits 7:0, account for that. 3884 * 3885 * On newer chips, starting with PHY revision G0, a new scheme is 3886 * deployed similar to the Starfighter 2 switch with GPHY major 3887 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3888 * is reserved as well as special value 0x01ff, we have a small 3889 * heuristic to check for the new GPHY revision and re-arrange things 3890 * so the GPHY driver is happy. 3891 */ 3892 gphy_rev = reg & 0xffff; 3893 3894 if (GENET_IS_V5(priv)) { 3895 /* The EPHY revision should come from the MDIO registers of 3896 * the PHY not from GENET. 3897 */ 3898 if (gphy_rev != 0) { 3899 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3900 gphy_rev); 3901 } 3902 /* This is reserved so should require special treatment */ 3903 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3904 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3905 return; 3906 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3907 } else if ((gphy_rev & 0xf0) != 0) { 3908 priv->gphy_rev = gphy_rev << 8; 3909 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3910 } else if ((gphy_rev & 0xff00) != 0) { 3911 priv->gphy_rev = gphy_rev; 3912 } 3913 3914 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3915 if (!(params->flags & GENET_HAS_40BITS)) 3916 pr_warn("GENET does not support 40-bits PA\n"); 3917 #endif 3918 3919 pr_debug("Configuration for version: %d\n" 3920 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3921 "BP << en: %2d, BP msk: 0x%05x\n" 3922 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3923 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3924 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3925 "Words/BD: %d\n", 3926 priv->version, 3927 params->tx_queues, params->tx_bds_per_q, 3928 params->rx_queues, params->rx_bds_per_q, 3929 params->bp_in_en_shift, params->bp_in_mask, 3930 params->hfb_filter_cnt, params->qtag_mask, 3931 params->tbuf_offset, params->hfb_offset, 3932 params->hfb_reg_offset, 3933 params->rdma_offset, params->tdma_offset, 3934 params->words_per_bd); 3935 } 3936 3937 struct bcmgenet_plat_data { 3938 enum bcmgenet_version version; 3939 u32 dma_max_burst_length; 3940 }; 3941 3942 static const struct bcmgenet_plat_data v1_plat_data = { 3943 .version = GENET_V1, 3944 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3945 }; 3946 3947 static const struct bcmgenet_plat_data v2_plat_data = { 3948 .version = GENET_V2, 3949 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3950 }; 3951 3952 static const struct bcmgenet_plat_data v3_plat_data = { 3953 .version = GENET_V3, 3954 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3955 }; 3956 3957 static const struct bcmgenet_plat_data v4_plat_data = { 3958 .version = GENET_V4, 3959 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3960 }; 3961 3962 static const struct bcmgenet_plat_data v5_plat_data = { 3963 .version = GENET_V5, 3964 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3965 }; 3966 3967 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3968 .version = GENET_V5, 3969 .dma_max_burst_length = 0x08, 3970 }; 3971 3972 static const struct of_device_id bcmgenet_match[] = { 3973 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3974 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3975 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3976 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3977 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3978 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3979 { }, 3980 }; 3981 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3982 3983 static int bcmgenet_probe(struct platform_device *pdev) 3984 { 3985 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3986 const struct bcmgenet_plat_data *pdata; 3987 struct bcmgenet_priv *priv; 3988 struct net_device *dev; 3989 unsigned int i; 3990 int err = -EIO; 3991 3992 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3993 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3994 GENET_MAX_MQ_CNT + 1); 3995 if (!dev) { 3996 dev_err(&pdev->dev, "can't allocate net device\n"); 3997 return -ENOMEM; 3998 } 3999 4000 priv = netdev_priv(dev); 4001 priv->irq0 = platform_get_irq(pdev, 0); 4002 if (priv->irq0 < 0) { 4003 err = priv->irq0; 4004 goto err; 4005 } 4006 priv->irq1 = platform_get_irq(pdev, 1); 4007 if (priv->irq1 < 0) { 4008 err = priv->irq1; 4009 goto err; 4010 } 4011 priv->wol_irq = platform_get_irq_optional(pdev, 2); 4012 4013 priv->base = devm_platform_ioremap_resource(pdev, 0); 4014 if (IS_ERR(priv->base)) { 4015 err = PTR_ERR(priv->base); 4016 goto err; 4017 } 4018 4019 spin_lock_init(&priv->lock); 4020 4021 SET_NETDEV_DEV(dev, &pdev->dev); 4022 dev_set_drvdata(&pdev->dev, dev); 4023 dev->watchdog_timeo = 2 * HZ; 4024 dev->ethtool_ops = &bcmgenet_ethtool_ops; 4025 dev->netdev_ops = &bcmgenet_netdev_ops; 4026 4027 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 4028 4029 /* Set default features */ 4030 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 4031 NETIF_F_RXCSUM; 4032 dev->hw_features |= dev->features; 4033 dev->vlan_features |= dev->features; 4034 4035 /* Request the WOL interrupt and advertise suspend if available */ 4036 priv->wol_irq_disabled = true; 4037 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 4038 dev->name, priv); 4039 if (!err) 4040 device_set_wakeup_capable(&pdev->dev, 1); 4041 4042 /* Set the needed headroom to account for any possible 4043 * features enabling/disabling at runtime 4044 */ 4045 dev->needed_headroom += 64; 4046 4047 netdev_boot_setup_check(dev); 4048 4049 priv->dev = dev; 4050 priv->pdev = pdev; 4051 4052 pdata = device_get_match_data(&pdev->dev); 4053 if (pdata) { 4054 priv->version = pdata->version; 4055 priv->dma_max_burst_length = pdata->dma_max_burst_length; 4056 } else { 4057 priv->version = pd->genet_version; 4058 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 4059 } 4060 4061 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 4062 if (IS_ERR(priv->clk)) { 4063 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 4064 err = PTR_ERR(priv->clk); 4065 goto err; 4066 } 4067 4068 err = clk_prepare_enable(priv->clk); 4069 if (err) 4070 goto err; 4071 4072 bcmgenet_set_hw_params(priv); 4073 4074 err = -EIO; 4075 if (priv->hw_params->flags & GENET_HAS_40BITS) 4076 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4077 if (err) 4078 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4079 if (err) 4080 goto err; 4081 4082 /* Mii wait queue */ 4083 init_waitqueue_head(&priv->wq); 4084 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4085 priv->rx_buf_len = RX_BUF_LENGTH; 4086 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4087 4088 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4089 if (IS_ERR(priv->clk_wol)) { 4090 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4091 err = PTR_ERR(priv->clk_wol); 4092 goto err; 4093 } 4094 4095 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4096 if (IS_ERR(priv->clk_eee)) { 4097 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4098 err = PTR_ERR(priv->clk_eee); 4099 goto err; 4100 } 4101 4102 /* If this is an internal GPHY, power it on now, before UniMAC is 4103 * brought out of reset as absolutely no UniMAC activity is allowed 4104 */ 4105 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4106 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4107 4108 if (pd && !IS_ERR_OR_NULL(pd->mac_address)) 4109 ether_addr_copy(dev->dev_addr, pd->mac_address); 4110 else 4111 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 4112 if (has_acpi_companion(&pdev->dev)) 4113 bcmgenet_get_hw_addr(priv, dev->dev_addr); 4114 4115 if (!is_valid_ether_addr(dev->dev_addr)) { 4116 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4117 eth_hw_addr_random(dev); 4118 } 4119 4120 reset_umac(priv); 4121 4122 err = bcmgenet_mii_init(dev); 4123 if (err) 4124 goto err_clk_disable; 4125 4126 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 4127 * just the ring 16 descriptor based TX 4128 */ 4129 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4130 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4131 4132 /* Set default coalescing parameters */ 4133 for (i = 0; i < priv->hw_params->rx_queues; i++) 4134 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4135 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 4136 4137 /* libphy will determine the link state */ 4138 netif_carrier_off(dev); 4139 4140 /* Turn off the main clock, WOL clock is handled separately */ 4141 clk_disable_unprepare(priv->clk); 4142 4143 err = register_netdev(dev); 4144 if (err) 4145 goto err; 4146 4147 return err; 4148 4149 err_clk_disable: 4150 clk_disable_unprepare(priv->clk); 4151 err: 4152 free_netdev(dev); 4153 return err; 4154 } 4155 4156 static int bcmgenet_remove(struct platform_device *pdev) 4157 { 4158 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4159 4160 dev_set_drvdata(&pdev->dev, NULL); 4161 unregister_netdev(priv->dev); 4162 bcmgenet_mii_exit(priv->dev); 4163 free_netdev(priv->dev); 4164 4165 return 0; 4166 } 4167 4168 static void bcmgenet_shutdown(struct platform_device *pdev) 4169 { 4170 bcmgenet_remove(pdev); 4171 } 4172 4173 #ifdef CONFIG_PM_SLEEP 4174 static int bcmgenet_resume_noirq(struct device *d) 4175 { 4176 struct net_device *dev = dev_get_drvdata(d); 4177 struct bcmgenet_priv *priv = netdev_priv(dev); 4178 int ret; 4179 u32 reg; 4180 4181 if (!netif_running(dev)) 4182 return 0; 4183 4184 /* Turn on the clock */ 4185 ret = clk_prepare_enable(priv->clk); 4186 if (ret) 4187 return ret; 4188 4189 if (device_may_wakeup(d) && priv->wolopts) { 4190 /* Account for Wake-on-LAN events and clear those events 4191 * (Some devices need more time between enabling the clocks 4192 * and the interrupt register reflecting the wake event so 4193 * read the register twice) 4194 */ 4195 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4196 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4197 if (reg & UMAC_IRQ_WAKE_EVENT) 4198 pm_wakeup_event(&priv->pdev->dev, 0); 4199 } 4200 4201 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR); 4202 4203 return 0; 4204 } 4205 4206 static int bcmgenet_resume(struct device *d) 4207 { 4208 struct net_device *dev = dev_get_drvdata(d); 4209 struct bcmgenet_priv *priv = netdev_priv(dev); 4210 unsigned long dma_ctrl; 4211 u32 offset, reg; 4212 int ret; 4213 4214 if (!netif_running(dev)) 4215 return 0; 4216 4217 /* From WOL-enabled suspend, switch to regular clock */ 4218 if (device_may_wakeup(d) && priv->wolopts) 4219 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 4220 4221 /* If this is an internal GPHY, power it back on now, before UniMAC is 4222 * brought out of reset as absolutely no UniMAC activity is allowed 4223 */ 4224 if (priv->internal_phy) 4225 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4226 4227 bcmgenet_umac_reset(priv); 4228 4229 init_umac(priv); 4230 4231 phy_init_hw(dev->phydev); 4232 4233 /* Speed settings must be restored */ 4234 genphy_config_aneg(dev->phydev); 4235 bcmgenet_mii_config(priv->dev, false); 4236 4237 /* Restore enabled features */ 4238 bcmgenet_set_features(dev, dev->features); 4239 4240 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4241 4242 offset = HFB_FLT_ENABLE_V3PLUS; 4243 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[1], offset); 4244 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[2], offset + sizeof(u32)); 4245 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[0], HFB_CTRL); 4246 4247 if (priv->internal_phy) { 4248 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 4249 reg |= EXT_ENERGY_DET_MASK; 4250 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 4251 } 4252 4253 /* Disable RX/TX DMA and flush TX queues */ 4254 dma_ctrl = bcmgenet_dma_disable(priv); 4255 4256 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4257 ret = bcmgenet_init_dma(priv); 4258 if (ret) { 4259 netdev_err(dev, "failed to initialize DMA\n"); 4260 goto out_clk_disable; 4261 } 4262 4263 /* Always enable ring 16 - descriptor ring */ 4264 bcmgenet_enable_dma(priv, dma_ctrl); 4265 4266 if (!device_may_wakeup(d)) 4267 phy_resume(dev->phydev); 4268 4269 if (priv->eee.eee_enabled) 4270 bcmgenet_eee_enable_set(dev, true); 4271 4272 bcmgenet_netif_start(dev); 4273 4274 netif_device_attach(dev); 4275 4276 return 0; 4277 4278 out_clk_disable: 4279 if (priv->internal_phy) 4280 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4281 clk_disable_unprepare(priv->clk); 4282 return ret; 4283 } 4284 4285 static int bcmgenet_suspend(struct device *d) 4286 { 4287 struct net_device *dev = dev_get_drvdata(d); 4288 struct bcmgenet_priv *priv = netdev_priv(dev); 4289 u32 offset; 4290 4291 if (!netif_running(dev)) 4292 return 0; 4293 4294 netif_device_detach(dev); 4295 4296 bcmgenet_netif_stop(dev); 4297 4298 if (!device_may_wakeup(d)) 4299 phy_suspend(dev->phydev); 4300 4301 /* Preserve filter state and disable filtering */ 4302 priv->hfb_en[0] = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 4303 offset = HFB_FLT_ENABLE_V3PLUS; 4304 priv->hfb_en[1] = bcmgenet_hfb_reg_readl(priv, offset); 4305 priv->hfb_en[2] = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 4306 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 4307 4308 return 0; 4309 } 4310 4311 static int bcmgenet_suspend_noirq(struct device *d) 4312 { 4313 struct net_device *dev = dev_get_drvdata(d); 4314 struct bcmgenet_priv *priv = netdev_priv(dev); 4315 int ret = 0; 4316 4317 if (!netif_running(dev)) 4318 return 0; 4319 4320 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4321 if (device_may_wakeup(d) && priv->wolopts) 4322 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4323 else if (priv->internal_phy) 4324 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4325 4326 /* Let the framework handle resumption and leave the clocks on */ 4327 if (ret) 4328 return ret; 4329 4330 /* Turn off the clocks */ 4331 clk_disable_unprepare(priv->clk); 4332 4333 return 0; 4334 } 4335 #else 4336 #define bcmgenet_suspend NULL 4337 #define bcmgenet_suspend_noirq NULL 4338 #define bcmgenet_resume NULL 4339 #define bcmgenet_resume_noirq NULL 4340 #endif /* CONFIG_PM_SLEEP */ 4341 4342 static const struct dev_pm_ops bcmgenet_pm_ops = { 4343 .suspend = bcmgenet_suspend, 4344 .suspend_noirq = bcmgenet_suspend_noirq, 4345 .resume = bcmgenet_resume, 4346 .resume_noirq = bcmgenet_resume_noirq, 4347 }; 4348 4349 static const struct acpi_device_id genet_acpi_match[] = { 4350 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4351 { }, 4352 }; 4353 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4354 4355 static struct platform_driver bcmgenet_driver = { 4356 .probe = bcmgenet_probe, 4357 .remove = bcmgenet_remove, 4358 .shutdown = bcmgenet_shutdown, 4359 .driver = { 4360 .name = "bcmgenet", 4361 .of_match_table = bcmgenet_match, 4362 .pm = &bcmgenet_pm_ops, 4363 .acpi_match_table = genet_acpi_match, 4364 }, 4365 }; 4366 module_platform_driver(bcmgenet_driver); 4367 4368 MODULE_AUTHOR("Broadcom Corporation"); 4369 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4370 MODULE_ALIAS("platform:bcmgenet"); 4371 MODULE_LICENSE("GPL"); 4372