1 /* 2 * Broadcom GENET (Gigabit Ethernet) controller driver 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) "bcmgenet: " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/types.h> 17 #include <linux/fcntl.h> 18 #include <linux/interrupt.h> 19 #include <linux/string.h> 20 #include <linux/if_ether.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/delay.h> 24 #include <linux/platform_device.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/pm.h> 27 #include <linux/clk.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_net.h> 32 #include <linux/of_platform.h> 33 #include <net/arp.h> 34 35 #include <linux/mii.h> 36 #include <linux/ethtool.h> 37 #include <linux/netdevice.h> 38 #include <linux/inetdevice.h> 39 #include <linux/etherdevice.h> 40 #include <linux/skbuff.h> 41 #include <linux/in.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/phy.h> 45 #include <linux/platform_data/bcmgenet.h> 46 47 #include <asm/unaligned.h> 48 49 #include "bcmgenet.h" 50 51 /* Maximum number of hardware queues, downsized if needed */ 52 #define GENET_MAX_MQ_CNT 4 53 54 /* Default highest priority queue for multi queue support */ 55 #define GENET_Q0_PRIORITY 0 56 57 #define GENET_Q16_RX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 59 #define GENET_Q16_TX_BD_CNT \ 60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 61 62 #define RX_BUF_LENGTH 2048 63 #define SKB_ALIGNMENT 32 64 65 /* Tx/Rx DMA register offset, skip 256 descriptors */ 66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 68 69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 70 TOTAL_DESC * DMA_DESC_SIZE) 71 72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 73 TOTAL_DESC * DMA_DESC_SIZE) 74 75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 76 void __iomem *d, u32 value) 77 { 78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS); 79 } 80 81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 82 void __iomem *d) 83 { 84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS); 85 } 86 87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 88 void __iomem *d, 89 dma_addr_t addr) 90 { 91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 92 93 /* Register writes to GISB bus can take couple hundred nanoseconds 94 * and are done for each packet, save these expensive writes unless 95 * the platform is explicitly configured for 64-bits/LPAE. 96 */ 97 #ifdef CONFIG_PHYS_ADDR_T_64BIT 98 if (priv->hw_params->flags & GENET_HAS_40BITS) 99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 100 #endif 101 } 102 103 /* Combined address + length/status setter */ 104 static inline void dmadesc_set(struct bcmgenet_priv *priv, 105 void __iomem *d, dma_addr_t addr, u32 val) 106 { 107 dmadesc_set_addr(priv, d, addr); 108 dmadesc_set_length_status(priv, d, val); 109 } 110 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 112 void __iomem *d) 113 { 114 dma_addr_t addr; 115 116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO); 117 118 /* Register writes to GISB bus can take couple hundred nanoseconds 119 * and are done for each packet, save these expensive writes unless 120 * the platform is explicitly configured for 64-bits/LPAE. 121 */ 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT 123 if (priv->hw_params->flags & GENET_HAS_40BITS) 124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32; 125 #endif 126 return addr; 127 } 128 129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 130 131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 132 NETIF_MSG_LINK) 133 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 135 { 136 if (GENET_IS_V1(priv)) 137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 138 else 139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 140 } 141 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 143 { 144 if (GENET_IS_V1(priv)) 145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 146 else 147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 148 } 149 150 /* These macros are defined to deal with register map change 151 * between GENET1.1 and GENET2. Only those currently being used 152 * by driver are defined. 153 */ 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 155 { 156 if (GENET_IS_V1(priv)) 157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 158 else 159 return __raw_readl(priv->base + 160 priv->hw_params->tbuf_offset + TBUF_CTRL); 161 } 162 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 164 { 165 if (GENET_IS_V1(priv)) 166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 167 else 168 __raw_writel(val, priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 173 { 174 if (GENET_IS_V1(priv)) 175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 176 else 177 return __raw_readl(priv->base + 178 priv->hw_params->tbuf_offset + TBUF_BP_MC); 179 } 180 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 182 { 183 if (GENET_IS_V1(priv)) 184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 185 else 186 __raw_writel(val, priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 /* RX/TX DMA register accessors */ 191 enum dma_reg { 192 DMA_RING_CFG = 0, 193 DMA_CTRL, 194 DMA_STATUS, 195 DMA_SCB_BURST_SIZE, 196 DMA_ARB_CTRL, 197 DMA_PRIORITY_0, 198 DMA_PRIORITY_1, 199 DMA_PRIORITY_2, 200 DMA_INDEX2RING_0, 201 DMA_INDEX2RING_1, 202 DMA_INDEX2RING_2, 203 DMA_INDEX2RING_3, 204 DMA_INDEX2RING_4, 205 DMA_INDEX2RING_5, 206 DMA_INDEX2RING_6, 207 DMA_INDEX2RING_7, 208 DMA_RING0_TIMEOUT, 209 DMA_RING1_TIMEOUT, 210 DMA_RING2_TIMEOUT, 211 DMA_RING3_TIMEOUT, 212 DMA_RING4_TIMEOUT, 213 DMA_RING5_TIMEOUT, 214 DMA_RING6_TIMEOUT, 215 DMA_RING7_TIMEOUT, 216 DMA_RING8_TIMEOUT, 217 DMA_RING9_TIMEOUT, 218 DMA_RING10_TIMEOUT, 219 DMA_RING11_TIMEOUT, 220 DMA_RING12_TIMEOUT, 221 DMA_RING13_TIMEOUT, 222 DMA_RING14_TIMEOUT, 223 DMA_RING15_TIMEOUT, 224 DMA_RING16_TIMEOUT, 225 }; 226 227 static const u8 bcmgenet_dma_regs_v3plus[] = { 228 [DMA_RING_CFG] = 0x00, 229 [DMA_CTRL] = 0x04, 230 [DMA_STATUS] = 0x08, 231 [DMA_SCB_BURST_SIZE] = 0x0C, 232 [DMA_ARB_CTRL] = 0x2C, 233 [DMA_PRIORITY_0] = 0x30, 234 [DMA_PRIORITY_1] = 0x34, 235 [DMA_PRIORITY_2] = 0x38, 236 [DMA_RING0_TIMEOUT] = 0x2C, 237 [DMA_RING1_TIMEOUT] = 0x30, 238 [DMA_RING2_TIMEOUT] = 0x34, 239 [DMA_RING3_TIMEOUT] = 0x38, 240 [DMA_RING4_TIMEOUT] = 0x3c, 241 [DMA_RING5_TIMEOUT] = 0x40, 242 [DMA_RING6_TIMEOUT] = 0x44, 243 [DMA_RING7_TIMEOUT] = 0x48, 244 [DMA_RING8_TIMEOUT] = 0x4c, 245 [DMA_RING9_TIMEOUT] = 0x50, 246 [DMA_RING10_TIMEOUT] = 0x54, 247 [DMA_RING11_TIMEOUT] = 0x58, 248 [DMA_RING12_TIMEOUT] = 0x5c, 249 [DMA_RING13_TIMEOUT] = 0x60, 250 [DMA_RING14_TIMEOUT] = 0x64, 251 [DMA_RING15_TIMEOUT] = 0x68, 252 [DMA_RING16_TIMEOUT] = 0x6C, 253 [DMA_INDEX2RING_0] = 0x70, 254 [DMA_INDEX2RING_1] = 0x74, 255 [DMA_INDEX2RING_2] = 0x78, 256 [DMA_INDEX2RING_3] = 0x7C, 257 [DMA_INDEX2RING_4] = 0x80, 258 [DMA_INDEX2RING_5] = 0x84, 259 [DMA_INDEX2RING_6] = 0x88, 260 [DMA_INDEX2RING_7] = 0x8C, 261 }; 262 263 static const u8 bcmgenet_dma_regs_v2[] = { 264 [DMA_RING_CFG] = 0x00, 265 [DMA_CTRL] = 0x04, 266 [DMA_STATUS] = 0x08, 267 [DMA_SCB_BURST_SIZE] = 0x0C, 268 [DMA_ARB_CTRL] = 0x30, 269 [DMA_PRIORITY_0] = 0x34, 270 [DMA_PRIORITY_1] = 0x38, 271 [DMA_PRIORITY_2] = 0x3C, 272 [DMA_RING0_TIMEOUT] = 0x2C, 273 [DMA_RING1_TIMEOUT] = 0x30, 274 [DMA_RING2_TIMEOUT] = 0x34, 275 [DMA_RING3_TIMEOUT] = 0x38, 276 [DMA_RING4_TIMEOUT] = 0x3c, 277 [DMA_RING5_TIMEOUT] = 0x40, 278 [DMA_RING6_TIMEOUT] = 0x44, 279 [DMA_RING7_TIMEOUT] = 0x48, 280 [DMA_RING8_TIMEOUT] = 0x4c, 281 [DMA_RING9_TIMEOUT] = 0x50, 282 [DMA_RING10_TIMEOUT] = 0x54, 283 [DMA_RING11_TIMEOUT] = 0x58, 284 [DMA_RING12_TIMEOUT] = 0x5c, 285 [DMA_RING13_TIMEOUT] = 0x60, 286 [DMA_RING14_TIMEOUT] = 0x64, 287 [DMA_RING15_TIMEOUT] = 0x68, 288 [DMA_RING16_TIMEOUT] = 0x6C, 289 }; 290 291 static const u8 bcmgenet_dma_regs_v1[] = { 292 [DMA_CTRL] = 0x00, 293 [DMA_STATUS] = 0x04, 294 [DMA_SCB_BURST_SIZE] = 0x0C, 295 [DMA_ARB_CTRL] = 0x30, 296 [DMA_PRIORITY_0] = 0x34, 297 [DMA_PRIORITY_1] = 0x38, 298 [DMA_PRIORITY_2] = 0x3C, 299 [DMA_RING0_TIMEOUT] = 0x2C, 300 [DMA_RING1_TIMEOUT] = 0x30, 301 [DMA_RING2_TIMEOUT] = 0x34, 302 [DMA_RING3_TIMEOUT] = 0x38, 303 [DMA_RING4_TIMEOUT] = 0x3c, 304 [DMA_RING5_TIMEOUT] = 0x40, 305 [DMA_RING6_TIMEOUT] = 0x44, 306 [DMA_RING7_TIMEOUT] = 0x48, 307 [DMA_RING8_TIMEOUT] = 0x4c, 308 [DMA_RING9_TIMEOUT] = 0x50, 309 [DMA_RING10_TIMEOUT] = 0x54, 310 [DMA_RING11_TIMEOUT] = 0x58, 311 [DMA_RING12_TIMEOUT] = 0x5c, 312 [DMA_RING13_TIMEOUT] = 0x60, 313 [DMA_RING14_TIMEOUT] = 0x64, 314 [DMA_RING15_TIMEOUT] = 0x68, 315 [DMA_RING16_TIMEOUT] = 0x6C, 316 }; 317 318 /* Set at runtime once bcmgenet version is known */ 319 static const u8 *bcmgenet_dma_regs; 320 321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 322 { 323 return netdev_priv(dev_get_drvdata(dev)); 324 } 325 326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 327 enum dma_reg r) 328 { 329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 331 } 332 333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 334 u32 val, enum dma_reg r) 335 { 336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 338 } 339 340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 341 enum dma_reg r) 342 { 343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 345 } 346 347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 348 u32 val, enum dma_reg r) 349 { 350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 352 } 353 354 /* RDMA/TDMA ring registers and accessors 355 * we merge the common fields and just prefix with T/D the registers 356 * having different meaning depending on the direction 357 */ 358 enum dma_ring_reg { 359 TDMA_READ_PTR = 0, 360 RDMA_WRITE_PTR = TDMA_READ_PTR, 361 TDMA_READ_PTR_HI, 362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 363 TDMA_CONS_INDEX, 364 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 365 TDMA_PROD_INDEX, 366 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 367 DMA_RING_BUF_SIZE, 368 DMA_START_ADDR, 369 DMA_START_ADDR_HI, 370 DMA_END_ADDR, 371 DMA_END_ADDR_HI, 372 DMA_MBUF_DONE_THRESH, 373 TDMA_FLOW_PERIOD, 374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 375 TDMA_WRITE_PTR, 376 RDMA_READ_PTR = TDMA_WRITE_PTR, 377 TDMA_WRITE_PTR_HI, 378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 379 }; 380 381 /* GENET v4 supports 40-bits pointer addressing 382 * for obvious reasons the LO and HI word parts 383 * are contiguous, but this offsets the other 384 * registers. 385 */ 386 static const u8 genet_dma_ring_regs_v4[] = { 387 [TDMA_READ_PTR] = 0x00, 388 [TDMA_READ_PTR_HI] = 0x04, 389 [TDMA_CONS_INDEX] = 0x08, 390 [TDMA_PROD_INDEX] = 0x0C, 391 [DMA_RING_BUF_SIZE] = 0x10, 392 [DMA_START_ADDR] = 0x14, 393 [DMA_START_ADDR_HI] = 0x18, 394 [DMA_END_ADDR] = 0x1C, 395 [DMA_END_ADDR_HI] = 0x20, 396 [DMA_MBUF_DONE_THRESH] = 0x24, 397 [TDMA_FLOW_PERIOD] = 0x28, 398 [TDMA_WRITE_PTR] = 0x2C, 399 [TDMA_WRITE_PTR_HI] = 0x30, 400 }; 401 402 static const u8 genet_dma_ring_regs_v123[] = { 403 [TDMA_READ_PTR] = 0x00, 404 [TDMA_CONS_INDEX] = 0x04, 405 [TDMA_PROD_INDEX] = 0x08, 406 [DMA_RING_BUF_SIZE] = 0x0C, 407 [DMA_START_ADDR] = 0x10, 408 [DMA_END_ADDR] = 0x14, 409 [DMA_MBUF_DONE_THRESH] = 0x18, 410 [TDMA_FLOW_PERIOD] = 0x1C, 411 [TDMA_WRITE_PTR] = 0x20, 412 }; 413 414 /* Set at runtime once GENET version is known */ 415 static const u8 *genet_dma_ring_regs; 416 417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 418 unsigned int ring, 419 enum dma_ring_reg r) 420 { 421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 422 (DMA_RING_SIZE * ring) + 423 genet_dma_ring_regs[r]); 424 } 425 426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 427 unsigned int ring, u32 val, 428 enum dma_ring_reg r) 429 { 430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433 } 434 435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 436 unsigned int ring, 437 enum dma_ring_reg r) 438 { 439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442 } 443 444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 445 unsigned int ring, u32 val, 446 enum dma_ring_reg r) 447 { 448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451 } 452 453 static int bcmgenet_begin(struct net_device *dev) 454 { 455 struct bcmgenet_priv *priv = netdev_priv(dev); 456 457 /* Turn on the clock */ 458 return clk_prepare_enable(priv->clk); 459 } 460 461 static void bcmgenet_complete(struct net_device *dev) 462 { 463 struct bcmgenet_priv *priv = netdev_priv(dev); 464 465 /* Turn off the clock */ 466 clk_disable_unprepare(priv->clk); 467 } 468 469 static int bcmgenet_get_link_ksettings(struct net_device *dev, 470 struct ethtool_link_ksettings *cmd) 471 { 472 struct bcmgenet_priv *priv = netdev_priv(dev); 473 474 if (!netif_running(dev)) 475 return -EINVAL; 476 477 if (!priv->phydev) 478 return -ENODEV; 479 480 phy_ethtool_ksettings_get(priv->phydev, cmd); 481 482 return 0; 483 } 484 485 static int bcmgenet_set_link_ksettings(struct net_device *dev, 486 const struct ethtool_link_ksettings *cmd) 487 { 488 struct bcmgenet_priv *priv = netdev_priv(dev); 489 490 if (!netif_running(dev)) 491 return -EINVAL; 492 493 if (!priv->phydev) 494 return -ENODEV; 495 496 return phy_ethtool_ksettings_set(priv->phydev, cmd); 497 } 498 499 static int bcmgenet_set_rx_csum(struct net_device *dev, 500 netdev_features_t wanted) 501 { 502 struct bcmgenet_priv *priv = netdev_priv(dev); 503 u32 rbuf_chk_ctrl; 504 bool rx_csum_en; 505 506 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 507 508 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 509 510 /* enable rx checksumming */ 511 if (rx_csum_en) 512 rbuf_chk_ctrl |= RBUF_RXCHK_EN; 513 else 514 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 515 priv->desc_rxchk_en = rx_csum_en; 516 517 /* If UniMAC forwards CRC, we need to skip over it to get 518 * a valid CHK bit to be set in the per-packet status word 519 */ 520 if (rx_csum_en && priv->crc_fwd_en) 521 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 522 else 523 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 524 525 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 526 527 return 0; 528 } 529 530 static int bcmgenet_set_tx_csum(struct net_device *dev, 531 netdev_features_t wanted) 532 { 533 struct bcmgenet_priv *priv = netdev_priv(dev); 534 bool desc_64b_en; 535 u32 tbuf_ctrl, rbuf_ctrl; 536 537 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 538 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 539 540 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 541 542 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 543 if (desc_64b_en) { 544 tbuf_ctrl |= RBUF_64B_EN; 545 rbuf_ctrl |= RBUF_64B_EN; 546 } else { 547 tbuf_ctrl &= ~RBUF_64B_EN; 548 rbuf_ctrl &= ~RBUF_64B_EN; 549 } 550 priv->desc_64b_en = desc_64b_en; 551 552 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 553 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 554 555 return 0; 556 } 557 558 static int bcmgenet_set_features(struct net_device *dev, 559 netdev_features_t features) 560 { 561 netdev_features_t changed = features ^ dev->features; 562 netdev_features_t wanted = dev->wanted_features; 563 int ret = 0; 564 565 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 566 ret = bcmgenet_set_tx_csum(dev, wanted); 567 if (changed & (NETIF_F_RXCSUM)) 568 ret = bcmgenet_set_rx_csum(dev, wanted); 569 570 return ret; 571 } 572 573 static u32 bcmgenet_get_msglevel(struct net_device *dev) 574 { 575 struct bcmgenet_priv *priv = netdev_priv(dev); 576 577 return priv->msg_enable; 578 } 579 580 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 581 { 582 struct bcmgenet_priv *priv = netdev_priv(dev); 583 584 priv->msg_enable = level; 585 } 586 587 static int bcmgenet_get_coalesce(struct net_device *dev, 588 struct ethtool_coalesce *ec) 589 { 590 struct bcmgenet_priv *priv = netdev_priv(dev); 591 592 ec->tx_max_coalesced_frames = 593 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 594 DMA_MBUF_DONE_THRESH); 595 ec->rx_max_coalesced_frames = 596 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 597 DMA_MBUF_DONE_THRESH); 598 ec->rx_coalesce_usecs = 599 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 600 601 return 0; 602 } 603 604 static int bcmgenet_set_coalesce(struct net_device *dev, 605 struct ethtool_coalesce *ec) 606 { 607 struct bcmgenet_priv *priv = netdev_priv(dev); 608 unsigned int i; 609 u32 reg; 610 611 /* Base system clock is 125Mhz, DMA timeout is this reference clock 612 * divided by 1024, which yields roughly 8.192us, our maximum value 613 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 614 */ 615 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 616 ec->tx_max_coalesced_frames == 0 || 617 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 618 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 619 return -EINVAL; 620 621 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 622 return -EINVAL; 623 624 /* GENET TDMA hardware does not support a configurable timeout, but will 625 * always generate an interrupt either after MBDONE packets have been 626 * transmitted, or when the ring is empty. 627 */ 628 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high || 629 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low) 630 return -EOPNOTSUPP; 631 632 /* Program all TX queues with the same values, as there is no 633 * ethtool knob to do coalescing on a per-queue basis 634 */ 635 for (i = 0; i < priv->hw_params->tx_queues; i++) 636 bcmgenet_tdma_ring_writel(priv, i, 637 ec->tx_max_coalesced_frames, 638 DMA_MBUF_DONE_THRESH); 639 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 640 ec->tx_max_coalesced_frames, 641 DMA_MBUF_DONE_THRESH); 642 643 for (i = 0; i < priv->hw_params->rx_queues; i++) { 644 bcmgenet_rdma_ring_writel(priv, i, 645 ec->rx_max_coalesced_frames, 646 DMA_MBUF_DONE_THRESH); 647 648 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 649 reg &= ~DMA_TIMEOUT_MASK; 650 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); 651 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 652 } 653 654 bcmgenet_rdma_ring_writel(priv, DESC_INDEX, 655 ec->rx_max_coalesced_frames, 656 DMA_MBUF_DONE_THRESH); 657 658 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT); 659 reg &= ~DMA_TIMEOUT_MASK; 660 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); 661 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT); 662 663 return 0; 664 } 665 666 /* standard ethtool support functions. */ 667 enum bcmgenet_stat_type { 668 BCMGENET_STAT_NETDEV = -1, 669 BCMGENET_STAT_MIB_RX, 670 BCMGENET_STAT_MIB_TX, 671 BCMGENET_STAT_RUNT, 672 BCMGENET_STAT_MISC, 673 BCMGENET_STAT_SOFT, 674 }; 675 676 struct bcmgenet_stats { 677 char stat_string[ETH_GSTRING_LEN]; 678 int stat_sizeof; 679 int stat_offset; 680 enum bcmgenet_stat_type type; 681 /* reg offset from UMAC base for misc counters */ 682 u16 reg_offset; 683 }; 684 685 #define STAT_NETDEV(m) { \ 686 .stat_string = __stringify(m), \ 687 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 688 .stat_offset = offsetof(struct net_device_stats, m), \ 689 .type = BCMGENET_STAT_NETDEV, \ 690 } 691 692 #define STAT_GENET_MIB(str, m, _type) { \ 693 .stat_string = str, \ 694 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 695 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 696 .type = _type, \ 697 } 698 699 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 700 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 701 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 702 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 703 704 #define STAT_GENET_MISC(str, m, offset) { \ 705 .stat_string = str, \ 706 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 707 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 708 .type = BCMGENET_STAT_MISC, \ 709 .reg_offset = offset, \ 710 } 711 712 #define STAT_GENET_Q(num) \ 713 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 714 tx_rings[num].packets), \ 715 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 716 tx_rings[num].bytes), \ 717 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 718 rx_rings[num].bytes), \ 719 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 720 rx_rings[num].packets), \ 721 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 722 rx_rings[num].errors), \ 723 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 724 rx_rings[num].dropped) 725 726 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 727 * between the end of TX stats and the beginning of the RX RUNT 728 */ 729 #define BCMGENET_STAT_OFFSET 0xc 730 731 /* Hardware counters must be kept in sync because the order/offset 732 * is important here (order in structure declaration = order in hardware) 733 */ 734 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 735 /* general stats */ 736 STAT_NETDEV(rx_packets), 737 STAT_NETDEV(tx_packets), 738 STAT_NETDEV(rx_bytes), 739 STAT_NETDEV(tx_bytes), 740 STAT_NETDEV(rx_errors), 741 STAT_NETDEV(tx_errors), 742 STAT_NETDEV(rx_dropped), 743 STAT_NETDEV(tx_dropped), 744 STAT_NETDEV(multicast), 745 /* UniMAC RSV counters */ 746 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 747 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 748 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 749 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 750 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 751 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 752 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 753 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 754 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 755 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 756 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 757 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 758 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 759 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 760 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 761 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 762 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 763 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 764 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 765 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 766 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 767 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 768 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 769 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 770 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 771 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 772 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 773 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 774 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 775 /* UniMAC TSV counters */ 776 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 777 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 778 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 779 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 780 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 781 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 782 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 783 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 784 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 785 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 786 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 787 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 788 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 789 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 790 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 791 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 792 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 793 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 794 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 795 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 796 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 797 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 798 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 799 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 800 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 801 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 802 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 803 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 804 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 805 /* UniMAC RUNT counters */ 806 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 807 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 808 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 809 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 810 /* Misc UniMAC counters */ 811 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 812 UMAC_RBUF_OVFL_CNT_V1), 813 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 814 UMAC_RBUF_ERR_CNT_V1), 815 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 816 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 817 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 818 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 819 /* Per TX queues */ 820 STAT_GENET_Q(0), 821 STAT_GENET_Q(1), 822 STAT_GENET_Q(2), 823 STAT_GENET_Q(3), 824 STAT_GENET_Q(16), 825 }; 826 827 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 828 829 static void bcmgenet_get_drvinfo(struct net_device *dev, 830 struct ethtool_drvinfo *info) 831 { 832 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 833 strlcpy(info->version, "v2.0", sizeof(info->version)); 834 } 835 836 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 837 { 838 switch (string_set) { 839 case ETH_SS_STATS: 840 return BCMGENET_STATS_LEN; 841 default: 842 return -EOPNOTSUPP; 843 } 844 } 845 846 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 847 u8 *data) 848 { 849 int i; 850 851 switch (stringset) { 852 case ETH_SS_STATS: 853 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 854 memcpy(data + i * ETH_GSTRING_LEN, 855 bcmgenet_gstrings_stats[i].stat_string, 856 ETH_GSTRING_LEN); 857 } 858 break; 859 } 860 } 861 862 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 863 { 864 u16 new_offset; 865 u32 val; 866 867 switch (offset) { 868 case UMAC_RBUF_OVFL_CNT_V1: 869 if (GENET_IS_V2(priv)) 870 new_offset = RBUF_OVFL_CNT_V2; 871 else 872 new_offset = RBUF_OVFL_CNT_V3PLUS; 873 874 val = bcmgenet_rbuf_readl(priv, new_offset); 875 /* clear if overflowed */ 876 if (val == ~0) 877 bcmgenet_rbuf_writel(priv, 0, new_offset); 878 break; 879 case UMAC_RBUF_ERR_CNT_V1: 880 if (GENET_IS_V2(priv)) 881 new_offset = RBUF_ERR_CNT_V2; 882 else 883 new_offset = RBUF_ERR_CNT_V3PLUS; 884 885 val = bcmgenet_rbuf_readl(priv, new_offset); 886 /* clear if overflowed */ 887 if (val == ~0) 888 bcmgenet_rbuf_writel(priv, 0, new_offset); 889 break; 890 default: 891 val = bcmgenet_umac_readl(priv, offset); 892 /* clear if overflowed */ 893 if (val == ~0) 894 bcmgenet_umac_writel(priv, 0, offset); 895 break; 896 } 897 898 return val; 899 } 900 901 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 902 { 903 int i, j = 0; 904 905 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 906 const struct bcmgenet_stats *s; 907 u8 offset = 0; 908 u32 val = 0; 909 char *p; 910 911 s = &bcmgenet_gstrings_stats[i]; 912 switch (s->type) { 913 case BCMGENET_STAT_NETDEV: 914 case BCMGENET_STAT_SOFT: 915 continue; 916 case BCMGENET_STAT_RUNT: 917 offset += BCMGENET_STAT_OFFSET; 918 /* fall through */ 919 case BCMGENET_STAT_MIB_TX: 920 offset += BCMGENET_STAT_OFFSET; 921 /* fall through */ 922 case BCMGENET_STAT_MIB_RX: 923 val = bcmgenet_umac_readl(priv, 924 UMAC_MIB_START + j + offset); 925 offset = 0; /* Reset Offset */ 926 break; 927 case BCMGENET_STAT_MISC: 928 if (GENET_IS_V1(priv)) { 929 val = bcmgenet_umac_readl(priv, s->reg_offset); 930 /* clear if overflowed */ 931 if (val == ~0) 932 bcmgenet_umac_writel(priv, 0, 933 s->reg_offset); 934 } else { 935 val = bcmgenet_update_stat_misc(priv, 936 s->reg_offset); 937 } 938 break; 939 } 940 941 j += s->stat_sizeof; 942 p = (char *)priv + s->stat_offset; 943 *(u32 *)p = val; 944 } 945 } 946 947 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 948 struct ethtool_stats *stats, 949 u64 *data) 950 { 951 struct bcmgenet_priv *priv = netdev_priv(dev); 952 int i; 953 954 if (netif_running(dev)) 955 bcmgenet_update_mib_counters(priv); 956 957 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 958 const struct bcmgenet_stats *s; 959 char *p; 960 961 s = &bcmgenet_gstrings_stats[i]; 962 if (s->type == BCMGENET_STAT_NETDEV) 963 p = (char *)&dev->stats; 964 else 965 p = (char *)priv; 966 p += s->stat_offset; 967 if (sizeof(unsigned long) != sizeof(u32) && 968 s->stat_sizeof == sizeof(unsigned long)) 969 data[i] = *(unsigned long *)p; 970 else 971 data[i] = *(u32 *)p; 972 } 973 } 974 975 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 976 { 977 struct bcmgenet_priv *priv = netdev_priv(dev); 978 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 979 u32 reg; 980 981 if (enable && !priv->clk_eee_enabled) { 982 clk_prepare_enable(priv->clk_eee); 983 priv->clk_eee_enabled = true; 984 } 985 986 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 987 if (enable) 988 reg |= EEE_EN; 989 else 990 reg &= ~EEE_EN; 991 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 992 993 /* Enable EEE and switch to a 27Mhz clock automatically */ 994 reg = __raw_readl(priv->base + off); 995 if (enable) 996 reg |= TBUF_EEE_EN | TBUF_PM_EN; 997 else 998 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 999 __raw_writel(reg, priv->base + off); 1000 1001 /* Do the same for thing for RBUF */ 1002 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1003 if (enable) 1004 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1005 else 1006 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1007 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1008 1009 if (!enable && priv->clk_eee_enabled) { 1010 clk_disable_unprepare(priv->clk_eee); 1011 priv->clk_eee_enabled = false; 1012 } 1013 1014 priv->eee.eee_enabled = enable; 1015 priv->eee.eee_active = enable; 1016 } 1017 1018 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1019 { 1020 struct bcmgenet_priv *priv = netdev_priv(dev); 1021 struct ethtool_eee *p = &priv->eee; 1022 1023 if (GENET_IS_V1(priv)) 1024 return -EOPNOTSUPP; 1025 1026 e->eee_enabled = p->eee_enabled; 1027 e->eee_active = p->eee_active; 1028 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1029 1030 return phy_ethtool_get_eee(priv->phydev, e); 1031 } 1032 1033 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1034 { 1035 struct bcmgenet_priv *priv = netdev_priv(dev); 1036 struct ethtool_eee *p = &priv->eee; 1037 int ret = 0; 1038 1039 if (GENET_IS_V1(priv)) 1040 return -EOPNOTSUPP; 1041 1042 p->eee_enabled = e->eee_enabled; 1043 1044 if (!p->eee_enabled) { 1045 bcmgenet_eee_enable_set(dev, false); 1046 } else { 1047 ret = phy_init_eee(priv->phydev, 0); 1048 if (ret) { 1049 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1050 return ret; 1051 } 1052 1053 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1054 bcmgenet_eee_enable_set(dev, true); 1055 } 1056 1057 return phy_ethtool_set_eee(priv->phydev, e); 1058 } 1059 1060 /* standard ethtool support functions. */ 1061 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1062 .begin = bcmgenet_begin, 1063 .complete = bcmgenet_complete, 1064 .get_strings = bcmgenet_get_strings, 1065 .get_sset_count = bcmgenet_get_sset_count, 1066 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1067 .get_drvinfo = bcmgenet_get_drvinfo, 1068 .get_link = ethtool_op_get_link, 1069 .get_msglevel = bcmgenet_get_msglevel, 1070 .set_msglevel = bcmgenet_set_msglevel, 1071 .get_wol = bcmgenet_get_wol, 1072 .set_wol = bcmgenet_set_wol, 1073 .get_eee = bcmgenet_get_eee, 1074 .set_eee = bcmgenet_set_eee, 1075 .nway_reset = phy_ethtool_nway_reset, 1076 .get_coalesce = bcmgenet_get_coalesce, 1077 .set_coalesce = bcmgenet_set_coalesce, 1078 .get_link_ksettings = bcmgenet_get_link_ksettings, 1079 .set_link_ksettings = bcmgenet_set_link_ksettings, 1080 }; 1081 1082 /* Power down the unimac, based on mode. */ 1083 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1084 enum bcmgenet_power_mode mode) 1085 { 1086 int ret = 0; 1087 u32 reg; 1088 1089 switch (mode) { 1090 case GENET_POWER_CABLE_SENSE: 1091 phy_detach(priv->phydev); 1092 break; 1093 1094 case GENET_POWER_WOL_MAGIC: 1095 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1096 break; 1097 1098 case GENET_POWER_PASSIVE: 1099 /* Power down LED */ 1100 if (priv->hw_params->flags & GENET_HAS_EXT) { 1101 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1102 if (GENET_IS_V5(priv)) 1103 reg |= EXT_PWR_DOWN_PHY_EN | 1104 EXT_PWR_DOWN_PHY_RD | 1105 EXT_PWR_DOWN_PHY_SD | 1106 EXT_PWR_DOWN_PHY_RX | 1107 EXT_PWR_DOWN_PHY_TX | 1108 EXT_IDDQ_GLBL_PWR; 1109 else 1110 reg |= EXT_PWR_DOWN_PHY; 1111 1112 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1113 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1114 1115 bcmgenet_phy_power_set(priv->dev, false); 1116 } 1117 break; 1118 default: 1119 break; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1126 enum bcmgenet_power_mode mode) 1127 { 1128 u32 reg; 1129 1130 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1131 return; 1132 1133 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1134 1135 switch (mode) { 1136 case GENET_POWER_PASSIVE: 1137 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1138 if (GENET_IS_V5(priv)) { 1139 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1140 EXT_PWR_DOWN_PHY_RD | 1141 EXT_PWR_DOWN_PHY_SD | 1142 EXT_PWR_DOWN_PHY_RX | 1143 EXT_PWR_DOWN_PHY_TX | 1144 EXT_IDDQ_GLBL_PWR); 1145 reg |= EXT_PHY_RESET; 1146 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1147 mdelay(1); 1148 1149 reg &= ~EXT_PHY_RESET; 1150 } else { 1151 reg &= ~EXT_PWR_DOWN_PHY; 1152 reg |= EXT_PWR_DN_EN_LD; 1153 } 1154 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1155 bcmgenet_phy_power_set(priv->dev, true); 1156 bcmgenet_mii_reset(priv->dev); 1157 break; 1158 1159 case GENET_POWER_CABLE_SENSE: 1160 /* enable APD */ 1161 if (!GENET_IS_V5(priv)) { 1162 reg |= EXT_PWR_DN_EN_LD; 1163 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1164 } 1165 break; 1166 case GENET_POWER_WOL_MAGIC: 1167 bcmgenet_wol_power_up_cfg(priv, mode); 1168 return; 1169 default: 1170 break; 1171 } 1172 } 1173 1174 /* ioctl handle special commands that are not present in ethtool. */ 1175 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1176 { 1177 struct bcmgenet_priv *priv = netdev_priv(dev); 1178 1179 if (!netif_running(dev)) 1180 return -EINVAL; 1181 1182 if (!priv->phydev) 1183 return -ENODEV; 1184 1185 return phy_mii_ioctl(priv->phydev, rq, cmd); 1186 } 1187 1188 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1189 struct bcmgenet_tx_ring *ring) 1190 { 1191 struct enet_cb *tx_cb_ptr; 1192 1193 tx_cb_ptr = ring->cbs; 1194 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1195 1196 /* Advancing local write pointer */ 1197 if (ring->write_ptr == ring->end_ptr) 1198 ring->write_ptr = ring->cb_ptr; 1199 else 1200 ring->write_ptr++; 1201 1202 return tx_cb_ptr; 1203 } 1204 1205 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1206 struct bcmgenet_tx_ring *ring) 1207 { 1208 struct enet_cb *tx_cb_ptr; 1209 1210 tx_cb_ptr = ring->cbs; 1211 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1212 1213 /* Rewinding local write pointer */ 1214 if (ring->write_ptr == ring->cb_ptr) 1215 ring->write_ptr = ring->end_ptr; 1216 else 1217 ring->write_ptr--; 1218 1219 return tx_cb_ptr; 1220 } 1221 1222 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1223 { 1224 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1225 INTRL2_CPU_MASK_SET); 1226 } 1227 1228 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1229 { 1230 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1231 INTRL2_CPU_MASK_CLEAR); 1232 } 1233 1234 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1235 { 1236 bcmgenet_intrl2_1_writel(ring->priv, 1237 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1238 INTRL2_CPU_MASK_SET); 1239 } 1240 1241 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1242 { 1243 bcmgenet_intrl2_1_writel(ring->priv, 1244 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1245 INTRL2_CPU_MASK_CLEAR); 1246 } 1247 1248 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1249 { 1250 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1251 INTRL2_CPU_MASK_SET); 1252 } 1253 1254 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1255 { 1256 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1257 INTRL2_CPU_MASK_CLEAR); 1258 } 1259 1260 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1261 { 1262 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1263 INTRL2_CPU_MASK_CLEAR); 1264 } 1265 1266 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1267 { 1268 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1269 INTRL2_CPU_MASK_SET); 1270 } 1271 1272 /* Simple helper to free a transmit control block's resources 1273 * Returns an skb when the last transmit control block associated with the 1274 * skb is freed. The skb should be freed by the caller if necessary. 1275 */ 1276 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1277 struct enet_cb *cb) 1278 { 1279 struct sk_buff *skb; 1280 1281 skb = cb->skb; 1282 1283 if (skb) { 1284 cb->skb = NULL; 1285 if (cb == GENET_CB(skb)->first_cb) 1286 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1287 dma_unmap_len(cb, dma_len), 1288 DMA_TO_DEVICE); 1289 else 1290 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1291 dma_unmap_len(cb, dma_len), 1292 DMA_TO_DEVICE); 1293 dma_unmap_addr_set(cb, dma_addr, 0); 1294 1295 if (cb == GENET_CB(skb)->last_cb) 1296 return skb; 1297 1298 } else if (dma_unmap_addr(cb, dma_addr)) { 1299 dma_unmap_page(dev, 1300 dma_unmap_addr(cb, dma_addr), 1301 dma_unmap_len(cb, dma_len), 1302 DMA_TO_DEVICE); 1303 dma_unmap_addr_set(cb, dma_addr, 0); 1304 } 1305 1306 return 0; 1307 } 1308 1309 /* Simple helper to free a receive control block's resources */ 1310 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1311 struct enet_cb *cb) 1312 { 1313 struct sk_buff *skb; 1314 1315 skb = cb->skb; 1316 cb->skb = NULL; 1317 1318 if (dma_unmap_addr(cb, dma_addr)) { 1319 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1320 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1321 dma_unmap_addr_set(cb, dma_addr, 0); 1322 } 1323 1324 return skb; 1325 } 1326 1327 /* Unlocked version of the reclaim routine */ 1328 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1329 struct bcmgenet_tx_ring *ring) 1330 { 1331 struct bcmgenet_priv *priv = netdev_priv(dev); 1332 unsigned int txbds_processed = 0; 1333 unsigned int bytes_compl = 0; 1334 unsigned int pkts_compl = 0; 1335 unsigned int txbds_ready; 1336 unsigned int c_index; 1337 struct sk_buff *skb; 1338 1339 /* Clear status before servicing to reduce spurious interrupts */ 1340 if (ring->index == DESC_INDEX) 1341 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1342 INTRL2_CPU_CLEAR); 1343 else 1344 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1345 INTRL2_CPU_CLEAR); 1346 1347 /* Compute how many buffers are transmitted since last xmit call */ 1348 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1349 & DMA_C_INDEX_MASK; 1350 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1351 1352 netif_dbg(priv, tx_done, dev, 1353 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1354 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1355 1356 /* Reclaim transmitted buffers */ 1357 while (txbds_processed < txbds_ready) { 1358 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1359 &priv->tx_cbs[ring->clean_ptr]); 1360 if (skb) { 1361 pkts_compl++; 1362 bytes_compl += GENET_CB(skb)->bytes_sent; 1363 dev_kfree_skb_any(skb); 1364 } 1365 1366 txbds_processed++; 1367 if (likely(ring->clean_ptr < ring->end_ptr)) 1368 ring->clean_ptr++; 1369 else 1370 ring->clean_ptr = ring->cb_ptr; 1371 } 1372 1373 ring->free_bds += txbds_processed; 1374 ring->c_index = c_index; 1375 1376 ring->packets += pkts_compl; 1377 ring->bytes += bytes_compl; 1378 1379 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1380 pkts_compl, bytes_compl); 1381 1382 return txbds_processed; 1383 } 1384 1385 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1386 struct bcmgenet_tx_ring *ring) 1387 { 1388 unsigned int released; 1389 unsigned long flags; 1390 1391 spin_lock_irqsave(&ring->lock, flags); 1392 released = __bcmgenet_tx_reclaim(dev, ring); 1393 spin_unlock_irqrestore(&ring->lock, flags); 1394 1395 return released; 1396 } 1397 1398 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1399 { 1400 struct bcmgenet_tx_ring *ring = 1401 container_of(napi, struct bcmgenet_tx_ring, napi); 1402 unsigned int work_done = 0; 1403 struct netdev_queue *txq; 1404 unsigned long flags; 1405 1406 spin_lock_irqsave(&ring->lock, flags); 1407 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1408 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1409 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1410 netif_tx_wake_queue(txq); 1411 } 1412 spin_unlock_irqrestore(&ring->lock, flags); 1413 1414 if (work_done == 0) { 1415 napi_complete(napi); 1416 ring->int_enable(ring); 1417 1418 return 0; 1419 } 1420 1421 return budget; 1422 } 1423 1424 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1425 { 1426 struct bcmgenet_priv *priv = netdev_priv(dev); 1427 int i; 1428 1429 if (netif_is_multiqueue(dev)) { 1430 for (i = 0; i < priv->hw_params->tx_queues; i++) 1431 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1432 } 1433 1434 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1435 } 1436 1437 /* Reallocate the SKB to put enough headroom in front of it and insert 1438 * the transmit checksum offsets in the descriptors 1439 */ 1440 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1441 struct sk_buff *skb) 1442 { 1443 struct status_64 *status = NULL; 1444 struct sk_buff *new_skb; 1445 u16 offset; 1446 u8 ip_proto; 1447 u16 ip_ver; 1448 u32 tx_csum_info; 1449 1450 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1451 /* If 64 byte status block enabled, must make sure skb has 1452 * enough headroom for us to insert 64B status block. 1453 */ 1454 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1455 dev_kfree_skb(skb); 1456 if (!new_skb) { 1457 dev->stats.tx_dropped++; 1458 return NULL; 1459 } 1460 skb = new_skb; 1461 } 1462 1463 skb_push(skb, sizeof(*status)); 1464 status = (struct status_64 *)skb->data; 1465 1466 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1467 ip_ver = htons(skb->protocol); 1468 switch (ip_ver) { 1469 case ETH_P_IP: 1470 ip_proto = ip_hdr(skb)->protocol; 1471 break; 1472 case ETH_P_IPV6: 1473 ip_proto = ipv6_hdr(skb)->nexthdr; 1474 break; 1475 default: 1476 return skb; 1477 } 1478 1479 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1480 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1481 (offset + skb->csum_offset); 1482 1483 /* Set the length valid bit for TCP and UDP and just set 1484 * the special UDP flag for IPv4, else just set to 0. 1485 */ 1486 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1487 tx_csum_info |= STATUS_TX_CSUM_LV; 1488 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1489 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1490 } else { 1491 tx_csum_info = 0; 1492 } 1493 1494 status->tx_csum_info = tx_csum_info; 1495 } 1496 1497 return skb; 1498 } 1499 1500 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1501 { 1502 struct bcmgenet_priv *priv = netdev_priv(dev); 1503 struct device *kdev = &priv->pdev->dev; 1504 struct bcmgenet_tx_ring *ring = NULL; 1505 struct enet_cb *tx_cb_ptr; 1506 struct netdev_queue *txq; 1507 unsigned long flags = 0; 1508 int nr_frags, index; 1509 dma_addr_t mapping; 1510 unsigned int size; 1511 skb_frag_t *frag; 1512 u32 len_stat; 1513 int ret; 1514 int i; 1515 1516 index = skb_get_queue_mapping(skb); 1517 /* Mapping strategy: 1518 * queue_mapping = 0, unclassified, packet xmited through ring16 1519 * queue_mapping = 1, goes to ring 0. (highest priority queue 1520 * queue_mapping = 2, goes to ring 1. 1521 * queue_mapping = 3, goes to ring 2. 1522 * queue_mapping = 4, goes to ring 3. 1523 */ 1524 if (index == 0) 1525 index = DESC_INDEX; 1526 else 1527 index -= 1; 1528 1529 ring = &priv->tx_rings[index]; 1530 txq = netdev_get_tx_queue(dev, ring->queue); 1531 1532 nr_frags = skb_shinfo(skb)->nr_frags; 1533 1534 spin_lock_irqsave(&ring->lock, flags); 1535 if (ring->free_bds <= (nr_frags + 1)) { 1536 if (!netif_tx_queue_stopped(txq)) { 1537 netif_tx_stop_queue(txq); 1538 netdev_err(dev, 1539 "%s: tx ring %d full when queue %d awake\n", 1540 __func__, index, ring->queue); 1541 } 1542 ret = NETDEV_TX_BUSY; 1543 goto out; 1544 } 1545 1546 if (skb_padto(skb, ETH_ZLEN)) { 1547 ret = NETDEV_TX_OK; 1548 goto out; 1549 } 1550 1551 /* Retain how many bytes will be sent on the wire, without TSB inserted 1552 * by transmit checksum offload 1553 */ 1554 GENET_CB(skb)->bytes_sent = skb->len; 1555 1556 /* set the SKB transmit checksum */ 1557 if (priv->desc_64b_en) { 1558 skb = bcmgenet_put_tx_csum(dev, skb); 1559 if (!skb) { 1560 ret = NETDEV_TX_OK; 1561 goto out; 1562 } 1563 } 1564 1565 for (i = 0; i <= nr_frags; i++) { 1566 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1567 1568 if (unlikely(!tx_cb_ptr)) 1569 BUG(); 1570 1571 if (!i) { 1572 /* Transmit single SKB or head of fragment list */ 1573 GENET_CB(skb)->first_cb = tx_cb_ptr; 1574 size = skb_headlen(skb); 1575 mapping = dma_map_single(kdev, skb->data, size, 1576 DMA_TO_DEVICE); 1577 } else { 1578 /* xmit fragment */ 1579 frag = &skb_shinfo(skb)->frags[i - 1]; 1580 size = skb_frag_size(frag); 1581 mapping = skb_frag_dma_map(kdev, frag, 0, size, 1582 DMA_TO_DEVICE); 1583 } 1584 1585 ret = dma_mapping_error(kdev, mapping); 1586 if (ret) { 1587 priv->mib.tx_dma_failed++; 1588 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1589 ret = NETDEV_TX_OK; 1590 goto out_unmap_frags; 1591 } 1592 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1593 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 1594 1595 tx_cb_ptr->skb = skb; 1596 1597 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 1598 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 1599 1600 if (!i) { 1601 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 1602 if (skb->ip_summed == CHECKSUM_PARTIAL) 1603 len_stat |= DMA_TX_DO_CSUM; 1604 } 1605 if (i == nr_frags) 1606 len_stat |= DMA_EOP; 1607 1608 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 1609 } 1610 1611 GENET_CB(skb)->last_cb = tx_cb_ptr; 1612 skb_tx_timestamp(skb); 1613 1614 /* Decrement total BD count and advance our write pointer */ 1615 ring->free_bds -= nr_frags + 1; 1616 ring->prod_index += nr_frags + 1; 1617 ring->prod_index &= DMA_P_INDEX_MASK; 1618 1619 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1620 1621 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1622 netif_tx_stop_queue(txq); 1623 1624 if (!skb->xmit_more || netif_xmit_stopped(txq)) 1625 /* Packets are ready, update producer index */ 1626 bcmgenet_tdma_ring_writel(priv, ring->index, 1627 ring->prod_index, TDMA_PROD_INDEX); 1628 out: 1629 spin_unlock_irqrestore(&ring->lock, flags); 1630 1631 return ret; 1632 1633 out_unmap_frags: 1634 /* Back up for failed control block mapping */ 1635 bcmgenet_put_txcb(priv, ring); 1636 1637 /* Unmap successfully mapped control blocks */ 1638 while (i-- > 0) { 1639 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 1640 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 1641 } 1642 1643 dev_kfree_skb(skb); 1644 goto out; 1645 } 1646 1647 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1648 struct enet_cb *cb) 1649 { 1650 struct device *kdev = &priv->pdev->dev; 1651 struct sk_buff *skb; 1652 struct sk_buff *rx_skb; 1653 dma_addr_t mapping; 1654 1655 /* Allocate a new Rx skb */ 1656 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1657 if (!skb) { 1658 priv->mib.alloc_rx_buff_failed++; 1659 netif_err(priv, rx_err, priv->dev, 1660 "%s: Rx skb allocation failed\n", __func__); 1661 return NULL; 1662 } 1663 1664 /* DMA-map the new Rx skb */ 1665 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1666 DMA_FROM_DEVICE); 1667 if (dma_mapping_error(kdev, mapping)) { 1668 priv->mib.rx_dma_failed++; 1669 dev_kfree_skb_any(skb); 1670 netif_err(priv, rx_err, priv->dev, 1671 "%s: Rx skb DMA mapping failed\n", __func__); 1672 return NULL; 1673 } 1674 1675 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1676 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 1677 1678 /* Put the new Rx skb on the ring */ 1679 cb->skb = skb; 1680 dma_unmap_addr_set(cb, dma_addr, mapping); 1681 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 1682 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1683 1684 /* Return the current Rx skb to caller */ 1685 return rx_skb; 1686 } 1687 1688 /* bcmgenet_desc_rx - descriptor based rx process. 1689 * this could be called from bottom half, or from NAPI polling method. 1690 */ 1691 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1692 unsigned int budget) 1693 { 1694 struct bcmgenet_priv *priv = ring->priv; 1695 struct net_device *dev = priv->dev; 1696 struct enet_cb *cb; 1697 struct sk_buff *skb; 1698 u32 dma_length_status; 1699 unsigned long dma_flag; 1700 int len; 1701 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1702 unsigned int p_index, mask; 1703 unsigned int discards; 1704 unsigned int chksum_ok = 0; 1705 1706 /* Clear status before servicing to reduce spurious interrupts */ 1707 if (ring->index == DESC_INDEX) { 1708 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1709 INTRL2_CPU_CLEAR); 1710 } else { 1711 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1712 bcmgenet_intrl2_1_writel(priv, 1713 mask, 1714 INTRL2_CPU_CLEAR); 1715 } 1716 1717 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1718 1719 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1720 DMA_P_INDEX_DISCARD_CNT_MASK; 1721 if (discards > ring->old_discards) { 1722 discards = discards - ring->old_discards; 1723 ring->errors += discards; 1724 ring->old_discards += discards; 1725 1726 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1727 if (ring->old_discards >= 0xC000) { 1728 ring->old_discards = 0; 1729 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1730 RDMA_PROD_INDEX); 1731 } 1732 } 1733 1734 p_index &= DMA_P_INDEX_MASK; 1735 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1736 1737 netif_dbg(priv, rx_status, dev, 1738 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1739 1740 while ((rxpktprocessed < rxpkttoprocess) && 1741 (rxpktprocessed < budget)) { 1742 cb = &priv->rx_cbs[ring->read_ptr]; 1743 skb = bcmgenet_rx_refill(priv, cb); 1744 1745 if (unlikely(!skb)) { 1746 ring->dropped++; 1747 goto next; 1748 } 1749 1750 if (!priv->desc_64b_en) { 1751 dma_length_status = 1752 dmadesc_get_length_status(priv, cb->bd_addr); 1753 } else { 1754 struct status_64 *status; 1755 1756 status = (struct status_64 *)skb->data; 1757 dma_length_status = status->length_status; 1758 } 1759 1760 /* DMA flags and length are still valid no matter how 1761 * we got the Receive Status Vector (64B RSB or register) 1762 */ 1763 dma_flag = dma_length_status & 0xffff; 1764 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1765 1766 netif_dbg(priv, rx_status, dev, 1767 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1768 __func__, p_index, ring->c_index, 1769 ring->read_ptr, dma_length_status); 1770 1771 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1772 netif_err(priv, rx_status, dev, 1773 "dropping fragmented packet!\n"); 1774 ring->errors++; 1775 dev_kfree_skb_any(skb); 1776 goto next; 1777 } 1778 1779 /* report errors */ 1780 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1781 DMA_RX_OV | 1782 DMA_RX_NO | 1783 DMA_RX_LG | 1784 DMA_RX_RXER))) { 1785 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1786 (unsigned int)dma_flag); 1787 if (dma_flag & DMA_RX_CRC_ERROR) 1788 dev->stats.rx_crc_errors++; 1789 if (dma_flag & DMA_RX_OV) 1790 dev->stats.rx_over_errors++; 1791 if (dma_flag & DMA_RX_NO) 1792 dev->stats.rx_frame_errors++; 1793 if (dma_flag & DMA_RX_LG) 1794 dev->stats.rx_length_errors++; 1795 dev->stats.rx_errors++; 1796 dev_kfree_skb_any(skb); 1797 goto next; 1798 } /* error packet */ 1799 1800 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && 1801 priv->desc_rxchk_en; 1802 1803 skb_put(skb, len); 1804 if (priv->desc_64b_en) { 1805 skb_pull(skb, 64); 1806 len -= 64; 1807 } 1808 1809 if (likely(chksum_ok)) 1810 skb->ip_summed = CHECKSUM_UNNECESSARY; 1811 1812 /* remove hardware 2bytes added for IP alignment */ 1813 skb_pull(skb, 2); 1814 len -= 2; 1815 1816 if (priv->crc_fwd_en) { 1817 skb_trim(skb, len - ETH_FCS_LEN); 1818 len -= ETH_FCS_LEN; 1819 } 1820 1821 /*Finish setting up the received SKB and send it to the kernel*/ 1822 skb->protocol = eth_type_trans(skb, priv->dev); 1823 ring->packets++; 1824 ring->bytes += len; 1825 if (dma_flag & DMA_RX_MULT) 1826 dev->stats.multicast++; 1827 1828 /* Notify kernel */ 1829 napi_gro_receive(&ring->napi, skb); 1830 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1831 1832 next: 1833 rxpktprocessed++; 1834 if (likely(ring->read_ptr < ring->end_ptr)) 1835 ring->read_ptr++; 1836 else 1837 ring->read_ptr = ring->cb_ptr; 1838 1839 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1840 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1841 } 1842 1843 return rxpktprocessed; 1844 } 1845 1846 /* Rx NAPI polling method */ 1847 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1848 { 1849 struct bcmgenet_rx_ring *ring = container_of(napi, 1850 struct bcmgenet_rx_ring, napi); 1851 unsigned int work_done; 1852 1853 work_done = bcmgenet_desc_rx(ring, budget); 1854 1855 if (work_done < budget) { 1856 napi_complete_done(napi, work_done); 1857 ring->int_enable(ring); 1858 } 1859 1860 return work_done; 1861 } 1862 1863 /* Assign skb to RX DMA descriptor. */ 1864 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1865 struct bcmgenet_rx_ring *ring) 1866 { 1867 struct enet_cb *cb; 1868 struct sk_buff *skb; 1869 int i; 1870 1871 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1872 1873 /* loop here for each buffer needing assign */ 1874 for (i = 0; i < ring->size; i++) { 1875 cb = ring->cbs + i; 1876 skb = bcmgenet_rx_refill(priv, cb); 1877 if (skb) 1878 dev_kfree_skb_any(skb); 1879 if (!cb->skb) 1880 return -ENOMEM; 1881 } 1882 1883 return 0; 1884 } 1885 1886 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1887 { 1888 struct sk_buff *skb; 1889 struct enet_cb *cb; 1890 int i; 1891 1892 for (i = 0; i < priv->num_rx_bds; i++) { 1893 cb = &priv->rx_cbs[i]; 1894 1895 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 1896 if (skb) 1897 dev_kfree_skb_any(skb); 1898 } 1899 } 1900 1901 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1902 { 1903 u32 reg; 1904 1905 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1906 if (enable) 1907 reg |= mask; 1908 else 1909 reg &= ~mask; 1910 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1911 1912 /* UniMAC stops on a packet boundary, wait for a full-size packet 1913 * to be processed 1914 */ 1915 if (enable == 0) 1916 usleep_range(1000, 2000); 1917 } 1918 1919 static int reset_umac(struct bcmgenet_priv *priv) 1920 { 1921 struct device *kdev = &priv->pdev->dev; 1922 unsigned int timeout = 0; 1923 u32 reg; 1924 1925 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1926 bcmgenet_rbuf_ctrl_set(priv, 0); 1927 udelay(10); 1928 1929 /* disable MAC while updating its registers */ 1930 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1931 1932 /* issue soft reset, wait for it to complete */ 1933 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 1934 while (timeout++ < 1000) { 1935 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1936 if (!(reg & CMD_SW_RESET)) 1937 return 0; 1938 1939 udelay(1); 1940 } 1941 1942 if (timeout == 1000) { 1943 dev_err(kdev, 1944 "timeout waiting for MAC to come out of reset\n"); 1945 return -ETIMEDOUT; 1946 } 1947 1948 return 0; 1949 } 1950 1951 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1952 { 1953 /* Mask all interrupts.*/ 1954 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1955 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1956 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1957 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1958 } 1959 1960 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 1961 { 1962 u32 int0_enable = 0; 1963 1964 /* Monitor cable plug/unplugged event for internal PHY, external PHY 1965 * and MoCA PHY 1966 */ 1967 if (priv->internal_phy) { 1968 int0_enable |= UMAC_IRQ_LINK_EVENT; 1969 } else if (priv->ext_phy) { 1970 int0_enable |= UMAC_IRQ_LINK_EVENT; 1971 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1972 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 1973 int0_enable |= UMAC_IRQ_LINK_EVENT; 1974 } 1975 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 1976 } 1977 1978 static int init_umac(struct bcmgenet_priv *priv) 1979 { 1980 struct device *kdev = &priv->pdev->dev; 1981 int ret; 1982 u32 reg; 1983 u32 int0_enable = 0; 1984 1985 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 1986 1987 ret = reset_umac(priv); 1988 if (ret) 1989 return ret; 1990 1991 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1992 /* clear tx/rx counter */ 1993 bcmgenet_umac_writel(priv, 1994 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 1995 UMAC_MIB_CTRL); 1996 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 1997 1998 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1999 2000 /* init rx registers, enable ip header optimization */ 2001 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2002 reg |= RBUF_ALIGN_2B; 2003 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2004 2005 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2006 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2007 2008 bcmgenet_intr_disable(priv); 2009 2010 /* Configure backpressure vectors for MoCA */ 2011 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2012 reg = bcmgenet_bp_mc_get(priv); 2013 reg |= BIT(priv->hw_params->bp_in_en_shift); 2014 2015 /* bp_mask: back pressure mask */ 2016 if (netif_is_multiqueue(priv->dev)) 2017 reg |= priv->hw_params->bp_in_mask; 2018 else 2019 reg &= ~priv->hw_params->bp_in_mask; 2020 bcmgenet_bp_mc_set(priv, reg); 2021 } 2022 2023 /* Enable MDIO interrupts on GENET v3+ */ 2024 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2025 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2026 2027 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2028 2029 dev_dbg(kdev, "done init umac\n"); 2030 2031 return 0; 2032 } 2033 2034 /* Initialize a Tx ring along with corresponding hardware registers */ 2035 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2036 unsigned int index, unsigned int size, 2037 unsigned int start_ptr, unsigned int end_ptr) 2038 { 2039 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2040 u32 words_per_bd = WORDS_PER_BD(priv); 2041 u32 flow_period_val = 0; 2042 2043 spin_lock_init(&ring->lock); 2044 ring->priv = priv; 2045 ring->index = index; 2046 if (index == DESC_INDEX) { 2047 ring->queue = 0; 2048 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2049 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2050 } else { 2051 ring->queue = index + 1; 2052 ring->int_enable = bcmgenet_tx_ring_int_enable; 2053 ring->int_disable = bcmgenet_tx_ring_int_disable; 2054 } 2055 ring->cbs = priv->tx_cbs + start_ptr; 2056 ring->size = size; 2057 ring->clean_ptr = start_ptr; 2058 ring->c_index = 0; 2059 ring->free_bds = size; 2060 ring->write_ptr = start_ptr; 2061 ring->cb_ptr = start_ptr; 2062 ring->end_ptr = end_ptr - 1; 2063 ring->prod_index = 0; 2064 2065 /* Set flow period for ring != 16 */ 2066 if (index != DESC_INDEX) 2067 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2068 2069 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2070 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2071 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2072 /* Disable rate control for now */ 2073 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2074 TDMA_FLOW_PERIOD); 2075 bcmgenet_tdma_ring_writel(priv, index, 2076 ((size << DMA_RING_SIZE_SHIFT) | 2077 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2078 2079 /* Set start and end address, read and write pointers */ 2080 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2081 DMA_START_ADDR); 2082 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2083 TDMA_READ_PTR); 2084 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2085 TDMA_WRITE_PTR); 2086 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2087 DMA_END_ADDR); 2088 } 2089 2090 /* Initialize a RDMA ring */ 2091 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2092 unsigned int index, unsigned int size, 2093 unsigned int start_ptr, unsigned int end_ptr) 2094 { 2095 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2096 u32 words_per_bd = WORDS_PER_BD(priv); 2097 int ret; 2098 2099 ring->priv = priv; 2100 ring->index = index; 2101 if (index == DESC_INDEX) { 2102 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2103 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2104 } else { 2105 ring->int_enable = bcmgenet_rx_ring_int_enable; 2106 ring->int_disable = bcmgenet_rx_ring_int_disable; 2107 } 2108 ring->cbs = priv->rx_cbs + start_ptr; 2109 ring->size = size; 2110 ring->c_index = 0; 2111 ring->read_ptr = start_ptr; 2112 ring->cb_ptr = start_ptr; 2113 ring->end_ptr = end_ptr - 1; 2114 2115 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2116 if (ret) 2117 return ret; 2118 2119 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2120 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2121 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2122 bcmgenet_rdma_ring_writel(priv, index, 2123 ((size << DMA_RING_SIZE_SHIFT) | 2124 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2125 bcmgenet_rdma_ring_writel(priv, index, 2126 (DMA_FC_THRESH_LO << 2127 DMA_XOFF_THRESHOLD_SHIFT) | 2128 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2129 2130 /* Set start and end address, read and write pointers */ 2131 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2132 DMA_START_ADDR); 2133 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2134 RDMA_READ_PTR); 2135 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2136 RDMA_WRITE_PTR); 2137 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2138 DMA_END_ADDR); 2139 2140 return ret; 2141 } 2142 2143 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) 2144 { 2145 unsigned int i; 2146 struct bcmgenet_tx_ring *ring; 2147 2148 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2149 ring = &priv->tx_rings[i]; 2150 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 2151 } 2152 2153 ring = &priv->tx_rings[DESC_INDEX]; 2154 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 2155 } 2156 2157 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2158 { 2159 unsigned int i; 2160 u32 int0_enable = UMAC_IRQ_TXDMA_DONE; 2161 u32 int1_enable = 0; 2162 struct bcmgenet_tx_ring *ring; 2163 2164 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2165 ring = &priv->tx_rings[i]; 2166 napi_enable(&ring->napi); 2167 int1_enable |= (1 << i); 2168 } 2169 2170 ring = &priv->tx_rings[DESC_INDEX]; 2171 napi_enable(&ring->napi); 2172 2173 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2174 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2175 } 2176 2177 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2178 { 2179 unsigned int i; 2180 u32 int0_disable = UMAC_IRQ_TXDMA_DONE; 2181 u32 int1_disable = 0xffff; 2182 struct bcmgenet_tx_ring *ring; 2183 2184 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); 2185 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); 2186 2187 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2188 ring = &priv->tx_rings[i]; 2189 napi_disable(&ring->napi); 2190 } 2191 2192 ring = &priv->tx_rings[DESC_INDEX]; 2193 napi_disable(&ring->napi); 2194 } 2195 2196 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2197 { 2198 unsigned int i; 2199 struct bcmgenet_tx_ring *ring; 2200 2201 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2202 ring = &priv->tx_rings[i]; 2203 netif_napi_del(&ring->napi); 2204 } 2205 2206 ring = &priv->tx_rings[DESC_INDEX]; 2207 netif_napi_del(&ring->napi); 2208 } 2209 2210 /* Initialize Tx queues 2211 * 2212 * Queues 0-3 are priority-based, each one has 32 descriptors, 2213 * with queue 0 being the highest priority queue. 2214 * 2215 * Queue 16 is the default Tx queue with 2216 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2217 * 2218 * The transmit control block pool is then partitioned as follows: 2219 * - Tx queue 0 uses tx_cbs[0..31] 2220 * - Tx queue 1 uses tx_cbs[32..63] 2221 * - Tx queue 2 uses tx_cbs[64..95] 2222 * - Tx queue 3 uses tx_cbs[96..127] 2223 * - Tx queue 16 uses tx_cbs[128..255] 2224 */ 2225 static void bcmgenet_init_tx_queues(struct net_device *dev) 2226 { 2227 struct bcmgenet_priv *priv = netdev_priv(dev); 2228 u32 i, dma_enable; 2229 u32 dma_ctrl, ring_cfg; 2230 u32 dma_priority[3] = {0, 0, 0}; 2231 2232 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2233 dma_enable = dma_ctrl & DMA_EN; 2234 dma_ctrl &= ~DMA_EN; 2235 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2236 2237 dma_ctrl = 0; 2238 ring_cfg = 0; 2239 2240 /* Enable strict priority arbiter mode */ 2241 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2242 2243 /* Initialize Tx priority queues */ 2244 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2245 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2246 i * priv->hw_params->tx_bds_per_q, 2247 (i + 1) * priv->hw_params->tx_bds_per_q); 2248 ring_cfg |= (1 << i); 2249 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2250 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2251 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2252 } 2253 2254 /* Initialize Tx default queue 16 */ 2255 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2256 priv->hw_params->tx_queues * 2257 priv->hw_params->tx_bds_per_q, 2258 TOTAL_DESC); 2259 ring_cfg |= (1 << DESC_INDEX); 2260 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2261 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2262 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2263 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2264 2265 /* Set Tx queue priorities */ 2266 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2267 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2268 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2269 2270 /* Initialize Tx NAPI */ 2271 bcmgenet_init_tx_napi(priv); 2272 2273 /* Enable Tx queues */ 2274 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2275 2276 /* Enable Tx DMA */ 2277 if (dma_enable) 2278 dma_ctrl |= DMA_EN; 2279 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2280 } 2281 2282 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv) 2283 { 2284 unsigned int i; 2285 struct bcmgenet_rx_ring *ring; 2286 2287 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2288 ring = &priv->rx_rings[i]; 2289 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2290 } 2291 2292 ring = &priv->rx_rings[DESC_INDEX]; 2293 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2294 } 2295 2296 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2297 { 2298 unsigned int i; 2299 u32 int0_enable = UMAC_IRQ_RXDMA_DONE; 2300 u32 int1_enable = 0; 2301 struct bcmgenet_rx_ring *ring; 2302 2303 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2304 ring = &priv->rx_rings[i]; 2305 napi_enable(&ring->napi); 2306 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); 2307 } 2308 2309 ring = &priv->rx_rings[DESC_INDEX]; 2310 napi_enable(&ring->napi); 2311 2312 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2313 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2314 } 2315 2316 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2317 { 2318 unsigned int i; 2319 u32 int0_disable = UMAC_IRQ_RXDMA_DONE; 2320 u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT; 2321 struct bcmgenet_rx_ring *ring; 2322 2323 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); 2324 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); 2325 2326 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2327 ring = &priv->rx_rings[i]; 2328 napi_disable(&ring->napi); 2329 } 2330 2331 ring = &priv->rx_rings[DESC_INDEX]; 2332 napi_disable(&ring->napi); 2333 } 2334 2335 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2336 { 2337 unsigned int i; 2338 struct bcmgenet_rx_ring *ring; 2339 2340 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2341 ring = &priv->rx_rings[i]; 2342 netif_napi_del(&ring->napi); 2343 } 2344 2345 ring = &priv->rx_rings[DESC_INDEX]; 2346 netif_napi_del(&ring->napi); 2347 } 2348 2349 /* Initialize Rx queues 2350 * 2351 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2352 * used to direct traffic to these queues. 2353 * 2354 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2355 */ 2356 static int bcmgenet_init_rx_queues(struct net_device *dev) 2357 { 2358 struct bcmgenet_priv *priv = netdev_priv(dev); 2359 u32 i; 2360 u32 dma_enable; 2361 u32 dma_ctrl; 2362 u32 ring_cfg; 2363 int ret; 2364 2365 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2366 dma_enable = dma_ctrl & DMA_EN; 2367 dma_ctrl &= ~DMA_EN; 2368 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2369 2370 dma_ctrl = 0; 2371 ring_cfg = 0; 2372 2373 /* Initialize Rx priority queues */ 2374 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2375 ret = bcmgenet_init_rx_ring(priv, i, 2376 priv->hw_params->rx_bds_per_q, 2377 i * priv->hw_params->rx_bds_per_q, 2378 (i + 1) * 2379 priv->hw_params->rx_bds_per_q); 2380 if (ret) 2381 return ret; 2382 2383 ring_cfg |= (1 << i); 2384 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2385 } 2386 2387 /* Initialize Rx default queue 16 */ 2388 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2389 priv->hw_params->rx_queues * 2390 priv->hw_params->rx_bds_per_q, 2391 TOTAL_DESC); 2392 if (ret) 2393 return ret; 2394 2395 ring_cfg |= (1 << DESC_INDEX); 2396 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2397 2398 /* Initialize Rx NAPI */ 2399 bcmgenet_init_rx_napi(priv); 2400 2401 /* Enable rings */ 2402 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2403 2404 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2405 if (dma_enable) 2406 dma_ctrl |= DMA_EN; 2407 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2408 2409 return 0; 2410 } 2411 2412 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2413 { 2414 int ret = 0; 2415 int timeout = 0; 2416 u32 reg; 2417 u32 dma_ctrl; 2418 int i; 2419 2420 /* Disable TDMA to stop add more frames in TX DMA */ 2421 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2422 reg &= ~DMA_EN; 2423 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2424 2425 /* Check TDMA status register to confirm TDMA is disabled */ 2426 while (timeout++ < DMA_TIMEOUT_VAL) { 2427 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2428 if (reg & DMA_DISABLED) 2429 break; 2430 2431 udelay(1); 2432 } 2433 2434 if (timeout == DMA_TIMEOUT_VAL) { 2435 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2436 ret = -ETIMEDOUT; 2437 } 2438 2439 /* Wait 10ms for packet drain in both tx and rx dma */ 2440 usleep_range(10000, 20000); 2441 2442 /* Disable RDMA */ 2443 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2444 reg &= ~DMA_EN; 2445 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2446 2447 timeout = 0; 2448 /* Check RDMA status register to confirm RDMA is disabled */ 2449 while (timeout++ < DMA_TIMEOUT_VAL) { 2450 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2451 if (reg & DMA_DISABLED) 2452 break; 2453 2454 udelay(1); 2455 } 2456 2457 if (timeout == DMA_TIMEOUT_VAL) { 2458 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2459 ret = -ETIMEDOUT; 2460 } 2461 2462 dma_ctrl = 0; 2463 for (i = 0; i < priv->hw_params->rx_queues; i++) 2464 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2465 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2466 reg &= ~dma_ctrl; 2467 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2468 2469 dma_ctrl = 0; 2470 for (i = 0; i < priv->hw_params->tx_queues; i++) 2471 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2472 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2473 reg &= ~dma_ctrl; 2474 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2475 2476 return ret; 2477 } 2478 2479 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2480 { 2481 struct netdev_queue *txq; 2482 struct sk_buff *skb; 2483 struct enet_cb *cb; 2484 int i; 2485 2486 bcmgenet_fini_rx_napi(priv); 2487 bcmgenet_fini_tx_napi(priv); 2488 2489 /* disable DMA */ 2490 bcmgenet_dma_teardown(priv); 2491 2492 for (i = 0; i < priv->num_tx_bds; i++) { 2493 cb = priv->tx_cbs + i; 2494 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb); 2495 if (skb) 2496 dev_kfree_skb(skb); 2497 } 2498 2499 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2500 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2501 netdev_tx_reset_queue(txq); 2502 } 2503 2504 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2505 netdev_tx_reset_queue(txq); 2506 2507 bcmgenet_free_rx_buffers(priv); 2508 kfree(priv->rx_cbs); 2509 kfree(priv->tx_cbs); 2510 } 2511 2512 /* init_edma: Initialize DMA control register */ 2513 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2514 { 2515 int ret; 2516 unsigned int i; 2517 struct enet_cb *cb; 2518 2519 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2520 2521 /* Initialize common Rx ring structures */ 2522 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2523 priv->num_rx_bds = TOTAL_DESC; 2524 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2525 GFP_KERNEL); 2526 if (!priv->rx_cbs) 2527 return -ENOMEM; 2528 2529 for (i = 0; i < priv->num_rx_bds; i++) { 2530 cb = priv->rx_cbs + i; 2531 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2532 } 2533 2534 /* Initialize common TX ring structures */ 2535 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2536 priv->num_tx_bds = TOTAL_DESC; 2537 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2538 GFP_KERNEL); 2539 if (!priv->tx_cbs) { 2540 kfree(priv->rx_cbs); 2541 return -ENOMEM; 2542 } 2543 2544 for (i = 0; i < priv->num_tx_bds; i++) { 2545 cb = priv->tx_cbs + i; 2546 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2547 } 2548 2549 /* Init rDma */ 2550 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2551 2552 /* Initialize Rx queues */ 2553 ret = bcmgenet_init_rx_queues(priv->dev); 2554 if (ret) { 2555 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2556 bcmgenet_free_rx_buffers(priv); 2557 kfree(priv->rx_cbs); 2558 kfree(priv->tx_cbs); 2559 return ret; 2560 } 2561 2562 /* Init tDma */ 2563 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2564 2565 /* Initialize Tx queues */ 2566 bcmgenet_init_tx_queues(priv->dev); 2567 2568 return 0; 2569 } 2570 2571 /* Interrupt bottom half */ 2572 static void bcmgenet_irq_task(struct work_struct *work) 2573 { 2574 unsigned long flags; 2575 unsigned int status; 2576 struct bcmgenet_priv *priv = container_of( 2577 work, struct bcmgenet_priv, bcmgenet_irq_work); 2578 2579 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2580 2581 spin_lock_irqsave(&priv->lock, flags); 2582 status = priv->irq0_stat; 2583 priv->irq0_stat = 0; 2584 spin_unlock_irqrestore(&priv->lock, flags); 2585 2586 if (status & UMAC_IRQ_MPD_R) { 2587 netif_dbg(priv, wol, priv->dev, 2588 "magic packet detected, waking up\n"); 2589 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 2590 } 2591 2592 /* Link UP/DOWN event */ 2593 if (status & UMAC_IRQ_LINK_EVENT) 2594 phy_mac_interrupt(priv->phydev, 2595 !!(status & UMAC_IRQ_LINK_UP)); 2596 } 2597 2598 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2599 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2600 { 2601 struct bcmgenet_priv *priv = dev_id; 2602 struct bcmgenet_rx_ring *rx_ring; 2603 struct bcmgenet_tx_ring *tx_ring; 2604 unsigned int index, status; 2605 2606 /* Read irq status */ 2607 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2608 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2609 2610 /* clear interrupts */ 2611 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2612 2613 netif_dbg(priv, intr, priv->dev, 2614 "%s: IRQ=0x%x\n", __func__, status); 2615 2616 /* Check Rx priority queue interrupts */ 2617 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2618 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2619 continue; 2620 2621 rx_ring = &priv->rx_rings[index]; 2622 2623 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2624 rx_ring->int_disable(rx_ring); 2625 __napi_schedule_irqoff(&rx_ring->napi); 2626 } 2627 } 2628 2629 /* Check Tx priority queue interrupts */ 2630 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2631 if (!(status & BIT(index))) 2632 continue; 2633 2634 tx_ring = &priv->tx_rings[index]; 2635 2636 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2637 tx_ring->int_disable(tx_ring); 2638 __napi_schedule_irqoff(&tx_ring->napi); 2639 } 2640 } 2641 2642 return IRQ_HANDLED; 2643 } 2644 2645 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2646 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2647 { 2648 struct bcmgenet_priv *priv = dev_id; 2649 struct bcmgenet_rx_ring *rx_ring; 2650 struct bcmgenet_tx_ring *tx_ring; 2651 unsigned int status; 2652 unsigned long flags; 2653 2654 /* Read irq status */ 2655 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2656 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2657 2658 /* clear interrupts */ 2659 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2660 2661 netif_dbg(priv, intr, priv->dev, 2662 "IRQ=0x%x\n", status); 2663 2664 if (status & UMAC_IRQ_RXDMA_DONE) { 2665 rx_ring = &priv->rx_rings[DESC_INDEX]; 2666 2667 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2668 rx_ring->int_disable(rx_ring); 2669 __napi_schedule_irqoff(&rx_ring->napi); 2670 } 2671 } 2672 2673 if (status & UMAC_IRQ_TXDMA_DONE) { 2674 tx_ring = &priv->tx_rings[DESC_INDEX]; 2675 2676 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2677 tx_ring->int_disable(tx_ring); 2678 __napi_schedule_irqoff(&tx_ring->napi); 2679 } 2680 } 2681 2682 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | 2683 UMAC_IRQ_PHY_DET_F | 2684 UMAC_IRQ_LINK_EVENT | 2685 UMAC_IRQ_HFB_SM | 2686 UMAC_IRQ_HFB_MM)) { 2687 /* all other interested interrupts handled in bottom half */ 2688 schedule_work(&priv->bcmgenet_irq_work); 2689 } 2690 2691 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2692 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2693 wake_up(&priv->wq); 2694 } 2695 2696 /* all other interested interrupts handled in bottom half */ 2697 status &= (UMAC_IRQ_LINK_EVENT | 2698 UMAC_IRQ_MPD_R); 2699 if (status) { 2700 /* Save irq status for bottom-half processing. */ 2701 spin_lock_irqsave(&priv->lock, flags); 2702 priv->irq0_stat |= status; 2703 spin_unlock_irqrestore(&priv->lock, flags); 2704 2705 schedule_work(&priv->bcmgenet_irq_work); 2706 } 2707 2708 return IRQ_HANDLED; 2709 } 2710 2711 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2712 { 2713 struct bcmgenet_priv *priv = dev_id; 2714 2715 pm_wakeup_event(&priv->pdev->dev, 0); 2716 2717 return IRQ_HANDLED; 2718 } 2719 2720 #ifdef CONFIG_NET_POLL_CONTROLLER 2721 static void bcmgenet_poll_controller(struct net_device *dev) 2722 { 2723 struct bcmgenet_priv *priv = netdev_priv(dev); 2724 2725 /* Invoke the main RX/TX interrupt handler */ 2726 disable_irq(priv->irq0); 2727 bcmgenet_isr0(priv->irq0, priv); 2728 enable_irq(priv->irq0); 2729 2730 /* And the interrupt handler for RX/TX priority queues */ 2731 disable_irq(priv->irq1); 2732 bcmgenet_isr1(priv->irq1, priv); 2733 enable_irq(priv->irq1); 2734 } 2735 #endif 2736 2737 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2738 { 2739 u32 reg; 2740 2741 reg = bcmgenet_rbuf_ctrl_get(priv); 2742 reg |= BIT(1); 2743 bcmgenet_rbuf_ctrl_set(priv, reg); 2744 udelay(10); 2745 2746 reg &= ~BIT(1); 2747 bcmgenet_rbuf_ctrl_set(priv, reg); 2748 udelay(10); 2749 } 2750 2751 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2752 unsigned char *addr) 2753 { 2754 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2755 (addr[2] << 8) | addr[3], UMAC_MAC0); 2756 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2757 } 2758 2759 /* Returns a reusable dma control register value */ 2760 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2761 { 2762 u32 reg; 2763 u32 dma_ctrl; 2764 2765 /* disable DMA */ 2766 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2767 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2768 reg &= ~dma_ctrl; 2769 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2770 2771 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2772 reg &= ~dma_ctrl; 2773 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2774 2775 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2776 udelay(10); 2777 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2778 2779 return dma_ctrl; 2780 } 2781 2782 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2783 { 2784 u32 reg; 2785 2786 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2787 reg |= dma_ctrl; 2788 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2789 2790 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2791 reg |= dma_ctrl; 2792 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2793 } 2794 2795 /* bcmgenet_hfb_clear 2796 * 2797 * Clear Hardware Filter Block and disable all filtering. 2798 */ 2799 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2800 { 2801 u32 i; 2802 2803 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2804 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2805 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2806 2807 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2808 bcmgenet_rdma_writel(priv, 0x0, i); 2809 2810 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2811 bcmgenet_hfb_reg_writel(priv, 0x0, 2812 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2813 2814 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2815 priv->hw_params->hfb_filter_size; i++) 2816 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2817 } 2818 2819 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2820 { 2821 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2822 return; 2823 2824 bcmgenet_hfb_clear(priv); 2825 } 2826 2827 static void bcmgenet_netif_start(struct net_device *dev) 2828 { 2829 struct bcmgenet_priv *priv = netdev_priv(dev); 2830 2831 /* Start the network engine */ 2832 bcmgenet_enable_rx_napi(priv); 2833 bcmgenet_enable_tx_napi(priv); 2834 2835 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2836 2837 netif_tx_start_all_queues(dev); 2838 2839 /* Monitor link interrupts now */ 2840 bcmgenet_link_intr_enable(priv); 2841 2842 phy_start(priv->phydev); 2843 } 2844 2845 static int bcmgenet_open(struct net_device *dev) 2846 { 2847 struct bcmgenet_priv *priv = netdev_priv(dev); 2848 unsigned long dma_ctrl; 2849 u32 reg; 2850 int ret; 2851 2852 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2853 2854 /* Turn on the clock */ 2855 clk_prepare_enable(priv->clk); 2856 2857 /* If this is an internal GPHY, power it back on now, before UniMAC is 2858 * brought out of reset as absolutely no UniMAC activity is allowed 2859 */ 2860 if (priv->internal_phy) 2861 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2862 2863 /* take MAC out of reset */ 2864 bcmgenet_umac_reset(priv); 2865 2866 ret = init_umac(priv); 2867 if (ret) 2868 goto err_clk_disable; 2869 2870 /* disable ethernet MAC while updating its registers */ 2871 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 2872 2873 /* Make sure we reflect the value of CRC_CMD_FWD */ 2874 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2875 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 2876 2877 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2878 2879 if (priv->internal_phy) { 2880 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2881 reg |= EXT_ENERGY_DET_MASK; 2882 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2883 } 2884 2885 /* Disable RX/TX DMA and flush TX queues */ 2886 dma_ctrl = bcmgenet_dma_disable(priv); 2887 2888 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2889 ret = bcmgenet_init_dma(priv); 2890 if (ret) { 2891 netdev_err(dev, "failed to initialize DMA\n"); 2892 goto err_clk_disable; 2893 } 2894 2895 /* Always enable ring 16 - descriptor ring */ 2896 bcmgenet_enable_dma(priv, dma_ctrl); 2897 2898 /* HFB init */ 2899 bcmgenet_hfb_init(priv); 2900 2901 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2902 dev->name, priv); 2903 if (ret < 0) { 2904 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2905 goto err_fini_dma; 2906 } 2907 2908 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2909 dev->name, priv); 2910 if (ret < 0) { 2911 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2912 goto err_irq0; 2913 } 2914 2915 ret = bcmgenet_mii_probe(dev); 2916 if (ret) { 2917 netdev_err(dev, "failed to connect to PHY\n"); 2918 goto err_irq1; 2919 } 2920 2921 bcmgenet_netif_start(dev); 2922 2923 return 0; 2924 2925 err_irq1: 2926 free_irq(priv->irq1, priv); 2927 err_irq0: 2928 free_irq(priv->irq0, priv); 2929 err_fini_dma: 2930 bcmgenet_fini_dma(priv); 2931 err_clk_disable: 2932 if (priv->internal_phy) 2933 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2934 clk_disable_unprepare(priv->clk); 2935 return ret; 2936 } 2937 2938 static void bcmgenet_netif_stop(struct net_device *dev) 2939 { 2940 struct bcmgenet_priv *priv = netdev_priv(dev); 2941 2942 netif_tx_stop_all_queues(dev); 2943 phy_stop(priv->phydev); 2944 bcmgenet_intr_disable(priv); 2945 bcmgenet_disable_rx_napi(priv); 2946 bcmgenet_disable_tx_napi(priv); 2947 2948 /* Wait for pending work items to complete. Since interrupts are 2949 * disabled no new work will be scheduled. 2950 */ 2951 cancel_work_sync(&priv->bcmgenet_irq_work); 2952 2953 priv->old_link = -1; 2954 priv->old_speed = -1; 2955 priv->old_duplex = -1; 2956 priv->old_pause = -1; 2957 } 2958 2959 static int bcmgenet_close(struct net_device *dev) 2960 { 2961 struct bcmgenet_priv *priv = netdev_priv(dev); 2962 int ret; 2963 2964 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2965 2966 bcmgenet_netif_stop(dev); 2967 2968 /* Really kill the PHY state machine and disconnect from it */ 2969 phy_disconnect(priv->phydev); 2970 2971 /* Disable MAC receive */ 2972 umac_enable_set(priv, CMD_RX_EN, false); 2973 2974 ret = bcmgenet_dma_teardown(priv); 2975 if (ret) 2976 return ret; 2977 2978 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2979 umac_enable_set(priv, CMD_TX_EN, false); 2980 2981 /* tx reclaim */ 2982 bcmgenet_tx_reclaim_all(dev); 2983 bcmgenet_fini_dma(priv); 2984 2985 free_irq(priv->irq0, priv); 2986 free_irq(priv->irq1, priv); 2987 2988 if (priv->internal_phy) 2989 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2990 2991 clk_disable_unprepare(priv->clk); 2992 2993 return ret; 2994 } 2995 2996 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 2997 { 2998 struct bcmgenet_priv *priv = ring->priv; 2999 u32 p_index, c_index, intsts, intmsk; 3000 struct netdev_queue *txq; 3001 unsigned int free_bds; 3002 unsigned long flags; 3003 bool txq_stopped; 3004 3005 if (!netif_msg_tx_err(priv)) 3006 return; 3007 3008 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3009 3010 spin_lock_irqsave(&ring->lock, flags); 3011 if (ring->index == DESC_INDEX) { 3012 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3013 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3014 } else { 3015 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3016 intmsk = 1 << ring->index; 3017 } 3018 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3019 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3020 txq_stopped = netif_tx_queue_stopped(txq); 3021 free_bds = ring->free_bds; 3022 spin_unlock_irqrestore(&ring->lock, flags); 3023 3024 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3025 "TX queue status: %s, interrupts: %s\n" 3026 "(sw)free_bds: %d (sw)size: %d\n" 3027 "(sw)p_index: %d (hw)p_index: %d\n" 3028 "(sw)c_index: %d (hw)c_index: %d\n" 3029 "(sw)clean_p: %d (sw)write_p: %d\n" 3030 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3031 ring->index, ring->queue, 3032 txq_stopped ? "stopped" : "active", 3033 intsts & intmsk ? "enabled" : "disabled", 3034 free_bds, ring->size, 3035 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3036 ring->c_index, c_index & DMA_C_INDEX_MASK, 3037 ring->clean_ptr, ring->write_ptr, 3038 ring->cb_ptr, ring->end_ptr); 3039 } 3040 3041 static void bcmgenet_timeout(struct net_device *dev) 3042 { 3043 struct bcmgenet_priv *priv = netdev_priv(dev); 3044 u32 int0_enable = 0; 3045 u32 int1_enable = 0; 3046 unsigned int q; 3047 3048 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3049 3050 for (q = 0; q < priv->hw_params->tx_queues; q++) 3051 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3052 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3053 3054 bcmgenet_tx_reclaim_all(dev); 3055 3056 for (q = 0; q < priv->hw_params->tx_queues; q++) 3057 int1_enable |= (1 << q); 3058 3059 int0_enable = UMAC_IRQ_TXDMA_DONE; 3060 3061 /* Re-enable TX interrupts if disabled */ 3062 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3063 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3064 3065 netif_trans_update(dev); 3066 3067 dev->stats.tx_errors++; 3068 3069 netif_tx_wake_all_queues(dev); 3070 } 3071 3072 #define MAX_MC_COUNT 16 3073 3074 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3075 unsigned char *addr, 3076 int *i, 3077 int *mc) 3078 { 3079 u32 reg; 3080 3081 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3082 UMAC_MDF_ADDR + (*i * 4)); 3083 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3084 addr[4] << 8 | addr[5], 3085 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3086 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); 3087 reg |= (1 << (MAX_MC_COUNT - *mc)); 3088 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3089 *i += 2; 3090 (*mc)++; 3091 } 3092 3093 static void bcmgenet_set_rx_mode(struct net_device *dev) 3094 { 3095 struct bcmgenet_priv *priv = netdev_priv(dev); 3096 struct netdev_hw_addr *ha; 3097 int i, mc; 3098 u32 reg; 3099 3100 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3101 3102 /* Promiscuous mode */ 3103 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3104 if (dev->flags & IFF_PROMISC) { 3105 reg |= CMD_PROMISC; 3106 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3107 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3108 return; 3109 } else { 3110 reg &= ~CMD_PROMISC; 3111 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3112 } 3113 3114 /* UniMac doesn't support ALLMULTI */ 3115 if (dev->flags & IFF_ALLMULTI) { 3116 netdev_warn(dev, "ALLMULTI is not supported\n"); 3117 return; 3118 } 3119 3120 /* update MDF filter */ 3121 i = 0; 3122 mc = 0; 3123 /* Broadcast */ 3124 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); 3125 /* my own address.*/ 3126 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); 3127 /* Unicast list*/ 3128 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) 3129 return; 3130 3131 if (!netdev_uc_empty(dev)) 3132 netdev_for_each_uc_addr(ha, dev) 3133 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 3134 /* Multicast */ 3135 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) 3136 return; 3137 3138 netdev_for_each_mc_addr(ha, dev) 3139 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 3140 } 3141 3142 /* Set the hardware MAC address. */ 3143 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3144 { 3145 struct sockaddr *addr = p; 3146 3147 /* Setting the MAC address at the hardware level is not possible 3148 * without disabling the UniMAC RX/TX enable bits. 3149 */ 3150 if (netif_running(dev)) 3151 return -EBUSY; 3152 3153 ether_addr_copy(dev->dev_addr, addr->sa_data); 3154 3155 return 0; 3156 } 3157 3158 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3159 { 3160 struct bcmgenet_priv *priv = netdev_priv(dev); 3161 unsigned long tx_bytes = 0, tx_packets = 0; 3162 unsigned long rx_bytes = 0, rx_packets = 0; 3163 unsigned long rx_errors = 0, rx_dropped = 0; 3164 struct bcmgenet_tx_ring *tx_ring; 3165 struct bcmgenet_rx_ring *rx_ring; 3166 unsigned int q; 3167 3168 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3169 tx_ring = &priv->tx_rings[q]; 3170 tx_bytes += tx_ring->bytes; 3171 tx_packets += tx_ring->packets; 3172 } 3173 tx_ring = &priv->tx_rings[DESC_INDEX]; 3174 tx_bytes += tx_ring->bytes; 3175 tx_packets += tx_ring->packets; 3176 3177 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3178 rx_ring = &priv->rx_rings[q]; 3179 3180 rx_bytes += rx_ring->bytes; 3181 rx_packets += rx_ring->packets; 3182 rx_errors += rx_ring->errors; 3183 rx_dropped += rx_ring->dropped; 3184 } 3185 rx_ring = &priv->rx_rings[DESC_INDEX]; 3186 rx_bytes += rx_ring->bytes; 3187 rx_packets += rx_ring->packets; 3188 rx_errors += rx_ring->errors; 3189 rx_dropped += rx_ring->dropped; 3190 3191 dev->stats.tx_bytes = tx_bytes; 3192 dev->stats.tx_packets = tx_packets; 3193 dev->stats.rx_bytes = rx_bytes; 3194 dev->stats.rx_packets = rx_packets; 3195 dev->stats.rx_errors = rx_errors; 3196 dev->stats.rx_missed_errors = rx_errors; 3197 return &dev->stats; 3198 } 3199 3200 static const struct net_device_ops bcmgenet_netdev_ops = { 3201 .ndo_open = bcmgenet_open, 3202 .ndo_stop = bcmgenet_close, 3203 .ndo_start_xmit = bcmgenet_xmit, 3204 .ndo_tx_timeout = bcmgenet_timeout, 3205 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3206 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3207 .ndo_do_ioctl = bcmgenet_ioctl, 3208 .ndo_set_features = bcmgenet_set_features, 3209 #ifdef CONFIG_NET_POLL_CONTROLLER 3210 .ndo_poll_controller = bcmgenet_poll_controller, 3211 #endif 3212 .ndo_get_stats = bcmgenet_get_stats, 3213 }; 3214 3215 /* Array of GENET hardware parameters/characteristics */ 3216 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3217 [GENET_V1] = { 3218 .tx_queues = 0, 3219 .tx_bds_per_q = 0, 3220 .rx_queues = 0, 3221 .rx_bds_per_q = 0, 3222 .bp_in_en_shift = 16, 3223 .bp_in_mask = 0xffff, 3224 .hfb_filter_cnt = 16, 3225 .qtag_mask = 0x1F, 3226 .hfb_offset = 0x1000, 3227 .rdma_offset = 0x2000, 3228 .tdma_offset = 0x3000, 3229 .words_per_bd = 2, 3230 }, 3231 [GENET_V2] = { 3232 .tx_queues = 4, 3233 .tx_bds_per_q = 32, 3234 .rx_queues = 0, 3235 .rx_bds_per_q = 0, 3236 .bp_in_en_shift = 16, 3237 .bp_in_mask = 0xffff, 3238 .hfb_filter_cnt = 16, 3239 .qtag_mask = 0x1F, 3240 .tbuf_offset = 0x0600, 3241 .hfb_offset = 0x1000, 3242 .hfb_reg_offset = 0x2000, 3243 .rdma_offset = 0x3000, 3244 .tdma_offset = 0x4000, 3245 .words_per_bd = 2, 3246 .flags = GENET_HAS_EXT, 3247 }, 3248 [GENET_V3] = { 3249 .tx_queues = 4, 3250 .tx_bds_per_q = 32, 3251 .rx_queues = 0, 3252 .rx_bds_per_q = 0, 3253 .bp_in_en_shift = 17, 3254 .bp_in_mask = 0x1ffff, 3255 .hfb_filter_cnt = 48, 3256 .hfb_filter_size = 128, 3257 .qtag_mask = 0x3F, 3258 .tbuf_offset = 0x0600, 3259 .hfb_offset = 0x8000, 3260 .hfb_reg_offset = 0xfc00, 3261 .rdma_offset = 0x10000, 3262 .tdma_offset = 0x11000, 3263 .words_per_bd = 2, 3264 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3265 GENET_HAS_MOCA_LINK_DET, 3266 }, 3267 [GENET_V4] = { 3268 .tx_queues = 4, 3269 .tx_bds_per_q = 32, 3270 .rx_queues = 0, 3271 .rx_bds_per_q = 0, 3272 .bp_in_en_shift = 17, 3273 .bp_in_mask = 0x1ffff, 3274 .hfb_filter_cnt = 48, 3275 .hfb_filter_size = 128, 3276 .qtag_mask = 0x3F, 3277 .tbuf_offset = 0x0600, 3278 .hfb_offset = 0x8000, 3279 .hfb_reg_offset = 0xfc00, 3280 .rdma_offset = 0x2000, 3281 .tdma_offset = 0x4000, 3282 .words_per_bd = 3, 3283 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3284 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3285 }, 3286 [GENET_V5] = { 3287 .tx_queues = 4, 3288 .tx_bds_per_q = 32, 3289 .rx_queues = 0, 3290 .rx_bds_per_q = 0, 3291 .bp_in_en_shift = 17, 3292 .bp_in_mask = 0x1ffff, 3293 .hfb_filter_cnt = 48, 3294 .hfb_filter_size = 128, 3295 .qtag_mask = 0x3F, 3296 .tbuf_offset = 0x0600, 3297 .hfb_offset = 0x8000, 3298 .hfb_reg_offset = 0xfc00, 3299 .rdma_offset = 0x2000, 3300 .tdma_offset = 0x4000, 3301 .words_per_bd = 3, 3302 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3303 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3304 }, 3305 }; 3306 3307 /* Infer hardware parameters from the detected GENET version */ 3308 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3309 { 3310 struct bcmgenet_hw_params *params; 3311 u32 reg; 3312 u8 major; 3313 u16 gphy_rev; 3314 3315 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3316 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3317 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3318 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3319 } else if (GENET_IS_V3(priv)) { 3320 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3321 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3322 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3323 } else if (GENET_IS_V2(priv)) { 3324 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3325 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3326 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3327 } else if (GENET_IS_V1(priv)) { 3328 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3329 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3330 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3331 } 3332 3333 /* enum genet_version starts at 1 */ 3334 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3335 params = priv->hw_params; 3336 3337 /* Read GENET HW version */ 3338 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3339 major = (reg >> 24 & 0x0f); 3340 if (major == 6) 3341 major = 5; 3342 else if (major == 5) 3343 major = 4; 3344 else if (major == 0) 3345 major = 1; 3346 if (major != priv->version) { 3347 dev_err(&priv->pdev->dev, 3348 "GENET version mismatch, got: %d, configured for: %d\n", 3349 major, priv->version); 3350 } 3351 3352 /* Print the GENET core version */ 3353 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3354 major, (reg >> 16) & 0x0f, reg & 0xffff); 3355 3356 /* Store the integrated PHY revision for the MDIO probing function 3357 * to pass this information to the PHY driver. The PHY driver expects 3358 * to find the PHY major revision in bits 15:8 while the GENET register 3359 * stores that information in bits 7:0, account for that. 3360 * 3361 * On newer chips, starting with PHY revision G0, a new scheme is 3362 * deployed similar to the Starfighter 2 switch with GPHY major 3363 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3364 * is reserved as well as special value 0x01ff, we have a small 3365 * heuristic to check for the new GPHY revision and re-arrange things 3366 * so the GPHY driver is happy. 3367 */ 3368 gphy_rev = reg & 0xffff; 3369 3370 if (GENET_IS_V5(priv)) { 3371 /* The EPHY revision should come from the MDIO registers of 3372 * the PHY not from GENET. 3373 */ 3374 if (gphy_rev != 0) { 3375 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3376 gphy_rev); 3377 } 3378 /* This is reserved so should require special treatment */ 3379 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3380 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3381 return; 3382 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3383 } else if ((gphy_rev & 0xf0) != 0) { 3384 priv->gphy_rev = gphy_rev << 8; 3385 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3386 } else if ((gphy_rev & 0xff00) != 0) { 3387 priv->gphy_rev = gphy_rev; 3388 } 3389 3390 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3391 if (!(params->flags & GENET_HAS_40BITS)) 3392 pr_warn("GENET does not support 40-bits PA\n"); 3393 #endif 3394 3395 pr_debug("Configuration for version: %d\n" 3396 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3397 "BP << en: %2d, BP msk: 0x%05x\n" 3398 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3399 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3400 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3401 "Words/BD: %d\n", 3402 priv->version, 3403 params->tx_queues, params->tx_bds_per_q, 3404 params->rx_queues, params->rx_bds_per_q, 3405 params->bp_in_en_shift, params->bp_in_mask, 3406 params->hfb_filter_cnt, params->qtag_mask, 3407 params->tbuf_offset, params->hfb_offset, 3408 params->hfb_reg_offset, 3409 params->rdma_offset, params->tdma_offset, 3410 params->words_per_bd); 3411 } 3412 3413 static const struct of_device_id bcmgenet_match[] = { 3414 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, 3415 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, 3416 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, 3417 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, 3418 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 }, 3419 { }, 3420 }; 3421 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3422 3423 static int bcmgenet_probe(struct platform_device *pdev) 3424 { 3425 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3426 struct device_node *dn = pdev->dev.of_node; 3427 const struct of_device_id *of_id = NULL; 3428 struct bcmgenet_priv *priv; 3429 struct net_device *dev; 3430 const void *macaddr; 3431 struct resource *r; 3432 int err = -EIO; 3433 const char *phy_mode_str; 3434 3435 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3436 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3437 GENET_MAX_MQ_CNT + 1); 3438 if (!dev) { 3439 dev_err(&pdev->dev, "can't allocate net device\n"); 3440 return -ENOMEM; 3441 } 3442 3443 if (dn) { 3444 of_id = of_match_node(bcmgenet_match, dn); 3445 if (!of_id) 3446 return -EINVAL; 3447 } 3448 3449 priv = netdev_priv(dev); 3450 priv->irq0 = platform_get_irq(pdev, 0); 3451 priv->irq1 = platform_get_irq(pdev, 1); 3452 priv->wol_irq = platform_get_irq(pdev, 2); 3453 if (!priv->irq0 || !priv->irq1) { 3454 dev_err(&pdev->dev, "can't find IRQs\n"); 3455 err = -EINVAL; 3456 goto err; 3457 } 3458 3459 if (dn) { 3460 macaddr = of_get_mac_address(dn); 3461 if (!macaddr) { 3462 dev_err(&pdev->dev, "can't find MAC address\n"); 3463 err = -EINVAL; 3464 goto err; 3465 } 3466 } else { 3467 macaddr = pd->mac_address; 3468 } 3469 3470 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3471 priv->base = devm_ioremap_resource(&pdev->dev, r); 3472 if (IS_ERR(priv->base)) { 3473 err = PTR_ERR(priv->base); 3474 goto err; 3475 } 3476 3477 spin_lock_init(&priv->lock); 3478 3479 SET_NETDEV_DEV(dev, &pdev->dev); 3480 dev_set_drvdata(&pdev->dev, dev); 3481 ether_addr_copy(dev->dev_addr, macaddr); 3482 dev->watchdog_timeo = 2 * HZ; 3483 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3484 dev->netdev_ops = &bcmgenet_netdev_ops; 3485 3486 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3487 3488 /* Set hardware features */ 3489 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 3490 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; 3491 3492 /* Request the WOL interrupt and advertise suspend if available */ 3493 priv->wol_irq_disabled = true; 3494 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3495 dev->name, priv); 3496 if (!err) 3497 device_set_wakeup_capable(&pdev->dev, 1); 3498 3499 /* Set the needed headroom to account for any possible 3500 * features enabling/disabling at runtime 3501 */ 3502 dev->needed_headroom += 64; 3503 3504 netdev_boot_setup_check(dev); 3505 3506 priv->dev = dev; 3507 priv->pdev = pdev; 3508 if (of_id) 3509 priv->version = (enum bcmgenet_version)of_id->data; 3510 else 3511 priv->version = pd->genet_version; 3512 3513 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3514 if (IS_ERR(priv->clk)) { 3515 dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); 3516 priv->clk = NULL; 3517 } 3518 3519 clk_prepare_enable(priv->clk); 3520 3521 bcmgenet_set_hw_params(priv); 3522 3523 /* Mii wait queue */ 3524 init_waitqueue_head(&priv->wq); 3525 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3526 priv->rx_buf_len = RX_BUF_LENGTH; 3527 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3528 3529 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3530 if (IS_ERR(priv->clk_wol)) { 3531 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3532 priv->clk_wol = NULL; 3533 } 3534 3535 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3536 if (IS_ERR(priv->clk_eee)) { 3537 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3538 priv->clk_eee = NULL; 3539 } 3540 3541 /* If this is an internal GPHY, power it on now, before UniMAC is 3542 * brought out of reset as absolutely no UniMAC activity is allowed 3543 */ 3544 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) && 3545 !strcasecmp(phy_mode_str, "internal")) 3546 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3547 3548 err = reset_umac(priv); 3549 if (err) 3550 goto err_clk_disable; 3551 3552 err = bcmgenet_mii_init(dev); 3553 if (err) 3554 goto err_clk_disable; 3555 3556 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3557 * just the ring 16 descriptor based TX 3558 */ 3559 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3560 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3561 3562 /* libphy will determine the link state */ 3563 netif_carrier_off(dev); 3564 3565 /* Turn off the main clock, WOL clock is handled separately */ 3566 clk_disable_unprepare(priv->clk); 3567 3568 err = register_netdev(dev); 3569 if (err) 3570 goto err; 3571 3572 return err; 3573 3574 err_clk_disable: 3575 clk_disable_unprepare(priv->clk); 3576 err: 3577 free_netdev(dev); 3578 return err; 3579 } 3580 3581 static int bcmgenet_remove(struct platform_device *pdev) 3582 { 3583 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3584 3585 dev_set_drvdata(&pdev->dev, NULL); 3586 unregister_netdev(priv->dev); 3587 bcmgenet_mii_exit(priv->dev); 3588 free_netdev(priv->dev); 3589 3590 return 0; 3591 } 3592 3593 #ifdef CONFIG_PM_SLEEP 3594 static int bcmgenet_suspend(struct device *d) 3595 { 3596 struct net_device *dev = dev_get_drvdata(d); 3597 struct bcmgenet_priv *priv = netdev_priv(dev); 3598 int ret; 3599 3600 if (!netif_running(dev)) 3601 return 0; 3602 3603 bcmgenet_netif_stop(dev); 3604 3605 if (!device_may_wakeup(d)) 3606 phy_suspend(priv->phydev); 3607 3608 netif_device_detach(dev); 3609 3610 /* Disable MAC receive */ 3611 umac_enable_set(priv, CMD_RX_EN, false); 3612 3613 ret = bcmgenet_dma_teardown(priv); 3614 if (ret) 3615 return ret; 3616 3617 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3618 umac_enable_set(priv, CMD_TX_EN, false); 3619 3620 /* tx reclaim */ 3621 bcmgenet_tx_reclaim_all(dev); 3622 bcmgenet_fini_dma(priv); 3623 3624 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3625 if (device_may_wakeup(d) && priv->wolopts) { 3626 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3627 clk_prepare_enable(priv->clk_wol); 3628 } else if (priv->internal_phy) { 3629 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3630 } 3631 3632 /* Turn off the clocks */ 3633 clk_disable_unprepare(priv->clk); 3634 3635 return ret; 3636 } 3637 3638 static int bcmgenet_resume(struct device *d) 3639 { 3640 struct net_device *dev = dev_get_drvdata(d); 3641 struct bcmgenet_priv *priv = netdev_priv(dev); 3642 unsigned long dma_ctrl; 3643 int ret; 3644 u32 reg; 3645 3646 if (!netif_running(dev)) 3647 return 0; 3648 3649 /* Turn on the clock */ 3650 ret = clk_prepare_enable(priv->clk); 3651 if (ret) 3652 return ret; 3653 3654 /* If this is an internal GPHY, power it back on now, before UniMAC is 3655 * brought out of reset as absolutely no UniMAC activity is allowed 3656 */ 3657 if (priv->internal_phy) 3658 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3659 3660 bcmgenet_umac_reset(priv); 3661 3662 ret = init_umac(priv); 3663 if (ret) 3664 goto out_clk_disable; 3665 3666 /* From WOL-enabled suspend, switch to regular clock */ 3667 if (priv->wolopts) 3668 clk_disable_unprepare(priv->clk_wol); 3669 3670 phy_init_hw(priv->phydev); 3671 /* Speed settings must be restored */ 3672 bcmgenet_mii_config(priv->dev, false); 3673 3674 /* disable ethernet MAC while updating its registers */ 3675 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 3676 3677 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3678 3679 if (priv->internal_phy) { 3680 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3681 reg |= EXT_ENERGY_DET_MASK; 3682 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3683 } 3684 3685 if (priv->wolopts) 3686 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3687 3688 /* Disable RX/TX DMA and flush TX queues */ 3689 dma_ctrl = bcmgenet_dma_disable(priv); 3690 3691 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3692 ret = bcmgenet_init_dma(priv); 3693 if (ret) { 3694 netdev_err(dev, "failed to initialize DMA\n"); 3695 goto out_clk_disable; 3696 } 3697 3698 /* Always enable ring 16 - descriptor ring */ 3699 bcmgenet_enable_dma(priv, dma_ctrl); 3700 3701 netif_device_attach(dev); 3702 3703 if (!device_may_wakeup(d)) 3704 phy_resume(priv->phydev); 3705 3706 if (priv->eee.eee_enabled) 3707 bcmgenet_eee_enable_set(dev, true); 3708 3709 bcmgenet_netif_start(dev); 3710 3711 return 0; 3712 3713 out_clk_disable: 3714 if (priv->internal_phy) 3715 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3716 clk_disable_unprepare(priv->clk); 3717 return ret; 3718 } 3719 #endif /* CONFIG_PM_SLEEP */ 3720 3721 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3722 3723 static struct platform_driver bcmgenet_driver = { 3724 .probe = bcmgenet_probe, 3725 .remove = bcmgenet_remove, 3726 .driver = { 3727 .name = "bcmgenet", 3728 .of_match_table = bcmgenet_match, 3729 .pm = &bcmgenet_pm_ops, 3730 }, 3731 }; 3732 module_platform_driver(bcmgenet_driver); 3733 3734 MODULE_AUTHOR("Broadcom Corporation"); 3735 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3736 MODULE_ALIAS("platform:bcmgenet"); 3737 MODULE_LICENSE("GPL"); 3738