1 /* 2 * Broadcom GENET (Gigabit Ethernet) controller driver 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) "bcmgenet: " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/types.h> 17 #include <linux/fcntl.h> 18 #include <linux/interrupt.h> 19 #include <linux/string.h> 20 #include <linux/if_ether.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/delay.h> 24 #include <linux/platform_device.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/pm.h> 27 #include <linux/clk.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_net.h> 32 #include <linux/of_platform.h> 33 #include <net/arp.h> 34 35 #include <linux/mii.h> 36 #include <linux/ethtool.h> 37 #include <linux/netdevice.h> 38 #include <linux/inetdevice.h> 39 #include <linux/etherdevice.h> 40 #include <linux/skbuff.h> 41 #include <linux/in.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/phy.h> 45 #include <linux/platform_data/bcmgenet.h> 46 47 #include <asm/unaligned.h> 48 49 #include "bcmgenet.h" 50 51 /* Maximum number of hardware queues, downsized if needed */ 52 #define GENET_MAX_MQ_CNT 4 53 54 /* Default highest priority queue for multi queue support */ 55 #define GENET_Q0_PRIORITY 0 56 57 #define GENET_Q16_RX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 59 #define GENET_Q16_TX_BD_CNT \ 60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 61 62 #define RX_BUF_LENGTH 2048 63 #define SKB_ALIGNMENT 32 64 65 /* Tx/Rx DMA register offset, skip 256 descriptors */ 66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 68 69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 70 TOTAL_DESC * DMA_DESC_SIZE) 71 72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 73 TOTAL_DESC * DMA_DESC_SIZE) 74 75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 76 void __iomem *d, u32 value) 77 { 78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS); 79 } 80 81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 82 void __iomem *d) 83 { 84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS); 85 } 86 87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 88 void __iomem *d, 89 dma_addr_t addr) 90 { 91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 92 93 /* Register writes to GISB bus can take couple hundred nanoseconds 94 * and are done for each packet, save these expensive writes unless 95 * the platform is explicitly configured for 64-bits/LPAE. 96 */ 97 #ifdef CONFIG_PHYS_ADDR_T_64BIT 98 if (priv->hw_params->flags & GENET_HAS_40BITS) 99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 100 #endif 101 } 102 103 /* Combined address + length/status setter */ 104 static inline void dmadesc_set(struct bcmgenet_priv *priv, 105 void __iomem *d, dma_addr_t addr, u32 val) 106 { 107 dmadesc_set_length_status(priv, d, val); 108 dmadesc_set_addr(priv, d, addr); 109 } 110 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 112 void __iomem *d) 113 { 114 dma_addr_t addr; 115 116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO); 117 118 /* Register writes to GISB bus can take couple hundred nanoseconds 119 * and are done for each packet, save these expensive writes unless 120 * the platform is explicitly configured for 64-bits/LPAE. 121 */ 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT 123 if (priv->hw_params->flags & GENET_HAS_40BITS) 124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32; 125 #endif 126 return addr; 127 } 128 129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 130 131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 132 NETIF_MSG_LINK) 133 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 135 { 136 if (GENET_IS_V1(priv)) 137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 138 else 139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 140 } 141 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 143 { 144 if (GENET_IS_V1(priv)) 145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 146 else 147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 148 } 149 150 /* These macros are defined to deal with register map change 151 * between GENET1.1 and GENET2. Only those currently being used 152 * by driver are defined. 153 */ 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 155 { 156 if (GENET_IS_V1(priv)) 157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 158 else 159 return __raw_readl(priv->base + 160 priv->hw_params->tbuf_offset + TBUF_CTRL); 161 } 162 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 164 { 165 if (GENET_IS_V1(priv)) 166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 167 else 168 __raw_writel(val, priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 173 { 174 if (GENET_IS_V1(priv)) 175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 176 else 177 return __raw_readl(priv->base + 178 priv->hw_params->tbuf_offset + TBUF_BP_MC); 179 } 180 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 182 { 183 if (GENET_IS_V1(priv)) 184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 185 else 186 __raw_writel(val, priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 /* RX/TX DMA register accessors */ 191 enum dma_reg { 192 DMA_RING_CFG = 0, 193 DMA_CTRL, 194 DMA_STATUS, 195 DMA_SCB_BURST_SIZE, 196 DMA_ARB_CTRL, 197 DMA_PRIORITY_0, 198 DMA_PRIORITY_1, 199 DMA_PRIORITY_2, 200 DMA_INDEX2RING_0, 201 DMA_INDEX2RING_1, 202 DMA_INDEX2RING_2, 203 DMA_INDEX2RING_3, 204 DMA_INDEX2RING_4, 205 DMA_INDEX2RING_5, 206 DMA_INDEX2RING_6, 207 DMA_INDEX2RING_7, 208 }; 209 210 static const u8 bcmgenet_dma_regs_v3plus[] = { 211 [DMA_RING_CFG] = 0x00, 212 [DMA_CTRL] = 0x04, 213 [DMA_STATUS] = 0x08, 214 [DMA_SCB_BURST_SIZE] = 0x0C, 215 [DMA_ARB_CTRL] = 0x2C, 216 [DMA_PRIORITY_0] = 0x30, 217 [DMA_PRIORITY_1] = 0x34, 218 [DMA_PRIORITY_2] = 0x38, 219 [DMA_INDEX2RING_0] = 0x70, 220 [DMA_INDEX2RING_1] = 0x74, 221 [DMA_INDEX2RING_2] = 0x78, 222 [DMA_INDEX2RING_3] = 0x7C, 223 [DMA_INDEX2RING_4] = 0x80, 224 [DMA_INDEX2RING_5] = 0x84, 225 [DMA_INDEX2RING_6] = 0x88, 226 [DMA_INDEX2RING_7] = 0x8C, 227 }; 228 229 static const u8 bcmgenet_dma_regs_v2[] = { 230 [DMA_RING_CFG] = 0x00, 231 [DMA_CTRL] = 0x04, 232 [DMA_STATUS] = 0x08, 233 [DMA_SCB_BURST_SIZE] = 0x0C, 234 [DMA_ARB_CTRL] = 0x30, 235 [DMA_PRIORITY_0] = 0x34, 236 [DMA_PRIORITY_1] = 0x38, 237 [DMA_PRIORITY_2] = 0x3C, 238 }; 239 240 static const u8 bcmgenet_dma_regs_v1[] = { 241 [DMA_CTRL] = 0x00, 242 [DMA_STATUS] = 0x04, 243 [DMA_SCB_BURST_SIZE] = 0x0C, 244 [DMA_ARB_CTRL] = 0x30, 245 [DMA_PRIORITY_0] = 0x34, 246 [DMA_PRIORITY_1] = 0x38, 247 [DMA_PRIORITY_2] = 0x3C, 248 }; 249 250 /* Set at runtime once bcmgenet version is known */ 251 static const u8 *bcmgenet_dma_regs; 252 253 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 254 { 255 return netdev_priv(dev_get_drvdata(dev)); 256 } 257 258 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 259 enum dma_reg r) 260 { 261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 263 } 264 265 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 266 u32 val, enum dma_reg r) 267 { 268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 270 } 271 272 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 273 enum dma_reg r) 274 { 275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 277 } 278 279 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 280 u32 val, enum dma_reg r) 281 { 282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 284 } 285 286 /* RDMA/TDMA ring registers and accessors 287 * we merge the common fields and just prefix with T/D the registers 288 * having different meaning depending on the direction 289 */ 290 enum dma_ring_reg { 291 TDMA_READ_PTR = 0, 292 RDMA_WRITE_PTR = TDMA_READ_PTR, 293 TDMA_READ_PTR_HI, 294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 295 TDMA_CONS_INDEX, 296 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 297 TDMA_PROD_INDEX, 298 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 299 DMA_RING_BUF_SIZE, 300 DMA_START_ADDR, 301 DMA_START_ADDR_HI, 302 DMA_END_ADDR, 303 DMA_END_ADDR_HI, 304 DMA_MBUF_DONE_THRESH, 305 TDMA_FLOW_PERIOD, 306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 307 TDMA_WRITE_PTR, 308 RDMA_READ_PTR = TDMA_WRITE_PTR, 309 TDMA_WRITE_PTR_HI, 310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 311 }; 312 313 /* GENET v4 supports 40-bits pointer addressing 314 * for obvious reasons the LO and HI word parts 315 * are contiguous, but this offsets the other 316 * registers. 317 */ 318 static const u8 genet_dma_ring_regs_v4[] = { 319 [TDMA_READ_PTR] = 0x00, 320 [TDMA_READ_PTR_HI] = 0x04, 321 [TDMA_CONS_INDEX] = 0x08, 322 [TDMA_PROD_INDEX] = 0x0C, 323 [DMA_RING_BUF_SIZE] = 0x10, 324 [DMA_START_ADDR] = 0x14, 325 [DMA_START_ADDR_HI] = 0x18, 326 [DMA_END_ADDR] = 0x1C, 327 [DMA_END_ADDR_HI] = 0x20, 328 [DMA_MBUF_DONE_THRESH] = 0x24, 329 [TDMA_FLOW_PERIOD] = 0x28, 330 [TDMA_WRITE_PTR] = 0x2C, 331 [TDMA_WRITE_PTR_HI] = 0x30, 332 }; 333 334 static const u8 genet_dma_ring_regs_v123[] = { 335 [TDMA_READ_PTR] = 0x00, 336 [TDMA_CONS_INDEX] = 0x04, 337 [TDMA_PROD_INDEX] = 0x08, 338 [DMA_RING_BUF_SIZE] = 0x0C, 339 [DMA_START_ADDR] = 0x10, 340 [DMA_END_ADDR] = 0x14, 341 [DMA_MBUF_DONE_THRESH] = 0x18, 342 [TDMA_FLOW_PERIOD] = 0x1C, 343 [TDMA_WRITE_PTR] = 0x20, 344 }; 345 346 /* Set at runtime once GENET version is known */ 347 static const u8 *genet_dma_ring_regs; 348 349 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 350 unsigned int ring, 351 enum dma_ring_reg r) 352 { 353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 354 (DMA_RING_SIZE * ring) + 355 genet_dma_ring_regs[r]); 356 } 357 358 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 359 unsigned int ring, u32 val, 360 enum dma_ring_reg r) 361 { 362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 363 (DMA_RING_SIZE * ring) + 364 genet_dma_ring_regs[r]); 365 } 366 367 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 368 unsigned int ring, 369 enum dma_ring_reg r) 370 { 371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 372 (DMA_RING_SIZE * ring) + 373 genet_dma_ring_regs[r]); 374 } 375 376 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 377 unsigned int ring, u32 val, 378 enum dma_ring_reg r) 379 { 380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 381 (DMA_RING_SIZE * ring) + 382 genet_dma_ring_regs[r]); 383 } 384 385 static int bcmgenet_get_settings(struct net_device *dev, 386 struct ethtool_cmd *cmd) 387 { 388 struct bcmgenet_priv *priv = netdev_priv(dev); 389 390 if (!netif_running(dev)) 391 return -EINVAL; 392 393 if (!priv->phydev) 394 return -ENODEV; 395 396 return phy_ethtool_gset(priv->phydev, cmd); 397 } 398 399 static int bcmgenet_set_settings(struct net_device *dev, 400 struct ethtool_cmd *cmd) 401 { 402 struct bcmgenet_priv *priv = netdev_priv(dev); 403 404 if (!netif_running(dev)) 405 return -EINVAL; 406 407 if (!priv->phydev) 408 return -ENODEV; 409 410 return phy_ethtool_sset(priv->phydev, cmd); 411 } 412 413 static int bcmgenet_set_rx_csum(struct net_device *dev, 414 netdev_features_t wanted) 415 { 416 struct bcmgenet_priv *priv = netdev_priv(dev); 417 u32 rbuf_chk_ctrl; 418 bool rx_csum_en; 419 420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 421 422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 423 424 /* enable rx checksumming */ 425 if (rx_csum_en) 426 rbuf_chk_ctrl |= RBUF_RXCHK_EN; 427 else 428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 429 priv->desc_rxchk_en = rx_csum_en; 430 431 /* If UniMAC forwards CRC, we need to skip over it to get 432 * a valid CHK bit to be set in the per-packet status word 433 */ 434 if (rx_csum_en && priv->crc_fwd_en) 435 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 436 else 437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 438 439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 440 441 return 0; 442 } 443 444 static int bcmgenet_set_tx_csum(struct net_device *dev, 445 netdev_features_t wanted) 446 { 447 struct bcmgenet_priv *priv = netdev_priv(dev); 448 bool desc_64b_en; 449 u32 tbuf_ctrl, rbuf_ctrl; 450 451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 453 454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 455 456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 457 if (desc_64b_en) { 458 tbuf_ctrl |= RBUF_64B_EN; 459 rbuf_ctrl |= RBUF_64B_EN; 460 } else { 461 tbuf_ctrl &= ~RBUF_64B_EN; 462 rbuf_ctrl &= ~RBUF_64B_EN; 463 } 464 priv->desc_64b_en = desc_64b_en; 465 466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 468 469 return 0; 470 } 471 472 static int bcmgenet_set_features(struct net_device *dev, 473 netdev_features_t features) 474 { 475 netdev_features_t changed = features ^ dev->features; 476 netdev_features_t wanted = dev->wanted_features; 477 int ret = 0; 478 479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 480 ret = bcmgenet_set_tx_csum(dev, wanted); 481 if (changed & (NETIF_F_RXCSUM)) 482 ret = bcmgenet_set_rx_csum(dev, wanted); 483 484 return ret; 485 } 486 487 static u32 bcmgenet_get_msglevel(struct net_device *dev) 488 { 489 struct bcmgenet_priv *priv = netdev_priv(dev); 490 491 return priv->msg_enable; 492 } 493 494 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 495 { 496 struct bcmgenet_priv *priv = netdev_priv(dev); 497 498 priv->msg_enable = level; 499 } 500 501 /* standard ethtool support functions. */ 502 enum bcmgenet_stat_type { 503 BCMGENET_STAT_NETDEV = -1, 504 BCMGENET_STAT_MIB_RX, 505 BCMGENET_STAT_MIB_TX, 506 BCMGENET_STAT_RUNT, 507 BCMGENET_STAT_MISC, 508 BCMGENET_STAT_SOFT, 509 }; 510 511 struct bcmgenet_stats { 512 char stat_string[ETH_GSTRING_LEN]; 513 int stat_sizeof; 514 int stat_offset; 515 enum bcmgenet_stat_type type; 516 /* reg offset from UMAC base for misc counters */ 517 u16 reg_offset; 518 }; 519 520 #define STAT_NETDEV(m) { \ 521 .stat_string = __stringify(m), \ 522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 523 .stat_offset = offsetof(struct net_device_stats, m), \ 524 .type = BCMGENET_STAT_NETDEV, \ 525 } 526 527 #define STAT_GENET_MIB(str, m, _type) { \ 528 .stat_string = str, \ 529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 530 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 531 .type = _type, \ 532 } 533 534 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 535 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 536 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 537 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 538 539 #define STAT_GENET_MISC(str, m, offset) { \ 540 .stat_string = str, \ 541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 542 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 543 .type = BCMGENET_STAT_MISC, \ 544 .reg_offset = offset, \ 545 } 546 547 548 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 549 * between the end of TX stats and the beginning of the RX RUNT 550 */ 551 #define BCMGENET_STAT_OFFSET 0xc 552 553 /* Hardware counters must be kept in sync because the order/offset 554 * is important here (order in structure declaration = order in hardware) 555 */ 556 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 557 /* general stats */ 558 STAT_NETDEV(rx_packets), 559 STAT_NETDEV(tx_packets), 560 STAT_NETDEV(rx_bytes), 561 STAT_NETDEV(tx_bytes), 562 STAT_NETDEV(rx_errors), 563 STAT_NETDEV(tx_errors), 564 STAT_NETDEV(rx_dropped), 565 STAT_NETDEV(tx_dropped), 566 STAT_NETDEV(multicast), 567 /* UniMAC RSV counters */ 568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 597 /* UniMAC TSV counters */ 598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 627 /* UniMAC RUNT counters */ 628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 632 /* Misc UniMAC counters */ 633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 634 UMAC_RBUF_OVFL_CNT), 635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT), 636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 640 }; 641 642 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 643 644 static void bcmgenet_get_drvinfo(struct net_device *dev, 645 struct ethtool_drvinfo *info) 646 { 647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 648 strlcpy(info->version, "v2.0", sizeof(info->version)); 649 info->n_stats = BCMGENET_STATS_LEN; 650 } 651 652 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 653 { 654 switch (string_set) { 655 case ETH_SS_STATS: 656 return BCMGENET_STATS_LEN; 657 default: 658 return -EOPNOTSUPP; 659 } 660 } 661 662 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 663 u8 *data) 664 { 665 int i; 666 667 switch (stringset) { 668 case ETH_SS_STATS: 669 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 670 memcpy(data + i * ETH_GSTRING_LEN, 671 bcmgenet_gstrings_stats[i].stat_string, 672 ETH_GSTRING_LEN); 673 } 674 break; 675 } 676 } 677 678 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 679 { 680 int i, j = 0; 681 682 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 683 const struct bcmgenet_stats *s; 684 u8 offset = 0; 685 u32 val = 0; 686 char *p; 687 688 s = &bcmgenet_gstrings_stats[i]; 689 switch (s->type) { 690 case BCMGENET_STAT_NETDEV: 691 case BCMGENET_STAT_SOFT: 692 continue; 693 case BCMGENET_STAT_MIB_RX: 694 case BCMGENET_STAT_MIB_TX: 695 case BCMGENET_STAT_RUNT: 696 if (s->type != BCMGENET_STAT_MIB_RX) 697 offset = BCMGENET_STAT_OFFSET; 698 val = bcmgenet_umac_readl(priv, 699 UMAC_MIB_START + j + offset); 700 break; 701 case BCMGENET_STAT_MISC: 702 val = bcmgenet_umac_readl(priv, s->reg_offset); 703 /* clear if overflowed */ 704 if (val == ~0) 705 bcmgenet_umac_writel(priv, 0, s->reg_offset); 706 break; 707 } 708 709 j += s->stat_sizeof; 710 p = (char *)priv + s->stat_offset; 711 *(u32 *)p = val; 712 } 713 } 714 715 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 716 struct ethtool_stats *stats, 717 u64 *data) 718 { 719 struct bcmgenet_priv *priv = netdev_priv(dev); 720 int i; 721 722 if (netif_running(dev)) 723 bcmgenet_update_mib_counters(priv); 724 725 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 726 const struct bcmgenet_stats *s; 727 char *p; 728 729 s = &bcmgenet_gstrings_stats[i]; 730 if (s->type == BCMGENET_STAT_NETDEV) 731 p = (char *)&dev->stats; 732 else 733 p = (char *)priv; 734 p += s->stat_offset; 735 data[i] = *(u32 *)p; 736 } 737 } 738 739 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 740 { 741 struct bcmgenet_priv *priv = netdev_priv(dev); 742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 743 u32 reg; 744 745 if (enable && !priv->clk_eee_enabled) { 746 clk_prepare_enable(priv->clk_eee); 747 priv->clk_eee_enabled = true; 748 } 749 750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 751 if (enable) 752 reg |= EEE_EN; 753 else 754 reg &= ~EEE_EN; 755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 756 757 /* Enable EEE and switch to a 27Mhz clock automatically */ 758 reg = __raw_readl(priv->base + off); 759 if (enable) 760 reg |= TBUF_EEE_EN | TBUF_PM_EN; 761 else 762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 763 __raw_writel(reg, priv->base + off); 764 765 /* Do the same for thing for RBUF */ 766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 767 if (enable) 768 reg |= RBUF_EEE_EN | RBUF_PM_EN; 769 else 770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 772 773 if (!enable && priv->clk_eee_enabled) { 774 clk_disable_unprepare(priv->clk_eee); 775 priv->clk_eee_enabled = false; 776 } 777 778 priv->eee.eee_enabled = enable; 779 priv->eee.eee_active = enable; 780 } 781 782 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 783 { 784 struct bcmgenet_priv *priv = netdev_priv(dev); 785 struct ethtool_eee *p = &priv->eee; 786 787 if (GENET_IS_V1(priv)) 788 return -EOPNOTSUPP; 789 790 e->eee_enabled = p->eee_enabled; 791 e->eee_active = p->eee_active; 792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 793 794 return phy_ethtool_get_eee(priv->phydev, e); 795 } 796 797 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 798 { 799 struct bcmgenet_priv *priv = netdev_priv(dev); 800 struct ethtool_eee *p = &priv->eee; 801 int ret = 0; 802 803 if (GENET_IS_V1(priv)) 804 return -EOPNOTSUPP; 805 806 p->eee_enabled = e->eee_enabled; 807 808 if (!p->eee_enabled) { 809 bcmgenet_eee_enable_set(dev, false); 810 } else { 811 ret = phy_init_eee(priv->phydev, 0); 812 if (ret) { 813 netif_err(priv, hw, dev, "EEE initialization failed\n"); 814 return ret; 815 } 816 817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 818 bcmgenet_eee_enable_set(dev, true); 819 } 820 821 return phy_ethtool_set_eee(priv->phydev, e); 822 } 823 824 static int bcmgenet_nway_reset(struct net_device *dev) 825 { 826 struct bcmgenet_priv *priv = netdev_priv(dev); 827 828 return genphy_restart_aneg(priv->phydev); 829 } 830 831 /* standard ethtool support functions. */ 832 static struct ethtool_ops bcmgenet_ethtool_ops = { 833 .get_strings = bcmgenet_get_strings, 834 .get_sset_count = bcmgenet_get_sset_count, 835 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 836 .get_settings = bcmgenet_get_settings, 837 .set_settings = bcmgenet_set_settings, 838 .get_drvinfo = bcmgenet_get_drvinfo, 839 .get_link = ethtool_op_get_link, 840 .get_msglevel = bcmgenet_get_msglevel, 841 .set_msglevel = bcmgenet_set_msglevel, 842 .get_wol = bcmgenet_get_wol, 843 .set_wol = bcmgenet_set_wol, 844 .get_eee = bcmgenet_get_eee, 845 .set_eee = bcmgenet_set_eee, 846 .nway_reset = bcmgenet_nway_reset, 847 }; 848 849 /* Power down the unimac, based on mode. */ 850 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 851 enum bcmgenet_power_mode mode) 852 { 853 int ret = 0; 854 u32 reg; 855 856 switch (mode) { 857 case GENET_POWER_CABLE_SENSE: 858 phy_detach(priv->phydev); 859 break; 860 861 case GENET_POWER_WOL_MAGIC: 862 ret = bcmgenet_wol_power_down_cfg(priv, mode); 863 break; 864 865 case GENET_POWER_PASSIVE: 866 /* Power down LED */ 867 if (priv->hw_params->flags & GENET_HAS_EXT) { 868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 869 reg |= (EXT_PWR_DOWN_PHY | 870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 872 873 bcmgenet_phy_power_set(priv->dev, false); 874 } 875 break; 876 default: 877 break; 878 } 879 880 return 0; 881 } 882 883 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 884 enum bcmgenet_power_mode mode) 885 { 886 u32 reg; 887 888 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 889 return; 890 891 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 892 893 switch (mode) { 894 case GENET_POWER_PASSIVE: 895 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY | 896 EXT_PWR_DOWN_BIAS); 897 /* fallthrough */ 898 case GENET_POWER_CABLE_SENSE: 899 /* enable APD */ 900 reg |= EXT_PWR_DN_EN_LD; 901 break; 902 case GENET_POWER_WOL_MAGIC: 903 bcmgenet_wol_power_up_cfg(priv, mode); 904 return; 905 default: 906 break; 907 } 908 909 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 910 if (mode == GENET_POWER_PASSIVE) 911 bcmgenet_phy_power_set(priv->dev, true); 912 } 913 914 /* ioctl handle special commands that are not present in ethtool. */ 915 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 916 { 917 struct bcmgenet_priv *priv = netdev_priv(dev); 918 int val = 0; 919 920 if (!netif_running(dev)) 921 return -EINVAL; 922 923 switch (cmd) { 924 case SIOCGMIIPHY: 925 case SIOCGMIIREG: 926 case SIOCSMIIREG: 927 if (!priv->phydev) 928 val = -ENODEV; 929 else 930 val = phy_mii_ioctl(priv->phydev, rq, cmd); 931 break; 932 933 default: 934 val = -EINVAL; 935 break; 936 } 937 938 return val; 939 } 940 941 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 942 struct bcmgenet_tx_ring *ring) 943 { 944 struct enet_cb *tx_cb_ptr; 945 946 tx_cb_ptr = ring->cbs; 947 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 948 949 /* Advancing local write pointer */ 950 if (ring->write_ptr == ring->end_ptr) 951 ring->write_ptr = ring->cb_ptr; 952 else 953 ring->write_ptr++; 954 955 return tx_cb_ptr; 956 } 957 958 /* Simple helper to free a control block's resources */ 959 static void bcmgenet_free_cb(struct enet_cb *cb) 960 { 961 dev_kfree_skb_any(cb->skb); 962 cb->skb = NULL; 963 dma_unmap_addr_set(cb, dma_addr, 0); 964 } 965 966 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 967 { 968 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 969 INTRL2_CPU_MASK_SET); 970 } 971 972 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 973 { 974 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 975 INTRL2_CPU_MASK_CLEAR); 976 } 977 978 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 979 { 980 bcmgenet_intrl2_1_writel(ring->priv, 981 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 982 INTRL2_CPU_MASK_SET); 983 } 984 985 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 986 { 987 bcmgenet_intrl2_1_writel(ring->priv, 988 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 989 INTRL2_CPU_MASK_CLEAR); 990 } 991 992 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 993 { 994 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 995 INTRL2_CPU_MASK_SET); 996 } 997 998 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 999 { 1000 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1001 INTRL2_CPU_MASK_CLEAR); 1002 } 1003 1004 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1005 { 1006 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1007 INTRL2_CPU_MASK_CLEAR); 1008 } 1009 1010 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1011 { 1012 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1013 INTRL2_CPU_MASK_SET); 1014 } 1015 1016 /* Unlocked version of the reclaim routine */ 1017 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1018 struct bcmgenet_tx_ring *ring) 1019 { 1020 struct bcmgenet_priv *priv = netdev_priv(dev); 1021 struct enet_cb *tx_cb_ptr; 1022 struct netdev_queue *txq; 1023 unsigned int pkts_compl = 0; 1024 unsigned int c_index; 1025 unsigned int txbds_ready; 1026 unsigned int txbds_processed = 0; 1027 1028 /* Compute how many buffers are transmitted since last xmit call */ 1029 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 1030 c_index &= DMA_C_INDEX_MASK; 1031 1032 if (likely(c_index >= ring->c_index)) 1033 txbds_ready = c_index - ring->c_index; 1034 else 1035 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index; 1036 1037 netif_dbg(priv, tx_done, dev, 1038 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1039 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1040 1041 /* Reclaim transmitted buffers */ 1042 while (txbds_processed < txbds_ready) { 1043 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr]; 1044 if (tx_cb_ptr->skb) { 1045 pkts_compl++; 1046 dev->stats.tx_packets++; 1047 dev->stats.tx_bytes += tx_cb_ptr->skb->len; 1048 dma_unmap_single(&dev->dev, 1049 dma_unmap_addr(tx_cb_ptr, dma_addr), 1050 tx_cb_ptr->skb->len, 1051 DMA_TO_DEVICE); 1052 bcmgenet_free_cb(tx_cb_ptr); 1053 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) { 1054 dev->stats.tx_bytes += 1055 dma_unmap_len(tx_cb_ptr, dma_len); 1056 dma_unmap_page(&dev->dev, 1057 dma_unmap_addr(tx_cb_ptr, dma_addr), 1058 dma_unmap_len(tx_cb_ptr, dma_len), 1059 DMA_TO_DEVICE); 1060 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0); 1061 } 1062 1063 txbds_processed++; 1064 if (likely(ring->clean_ptr < ring->end_ptr)) 1065 ring->clean_ptr++; 1066 else 1067 ring->clean_ptr = ring->cb_ptr; 1068 } 1069 1070 ring->free_bds += txbds_processed; 1071 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK; 1072 1073 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1074 txq = netdev_get_tx_queue(dev, ring->queue); 1075 if (netif_tx_queue_stopped(txq)) 1076 netif_tx_wake_queue(txq); 1077 } 1078 1079 return pkts_compl; 1080 } 1081 1082 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1083 struct bcmgenet_tx_ring *ring) 1084 { 1085 unsigned int released; 1086 unsigned long flags; 1087 1088 spin_lock_irqsave(&ring->lock, flags); 1089 released = __bcmgenet_tx_reclaim(dev, ring); 1090 spin_unlock_irqrestore(&ring->lock, flags); 1091 1092 return released; 1093 } 1094 1095 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1096 { 1097 struct bcmgenet_tx_ring *ring = 1098 container_of(napi, struct bcmgenet_tx_ring, napi); 1099 unsigned int work_done = 0; 1100 1101 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring); 1102 1103 if (work_done == 0) { 1104 napi_complete(napi); 1105 ring->int_enable(ring); 1106 1107 return 0; 1108 } 1109 1110 return budget; 1111 } 1112 1113 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1114 { 1115 struct bcmgenet_priv *priv = netdev_priv(dev); 1116 int i; 1117 1118 if (netif_is_multiqueue(dev)) { 1119 for (i = 0; i < priv->hw_params->tx_queues; i++) 1120 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1121 } 1122 1123 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1124 } 1125 1126 /* Transmits a single SKB (either head of a fragment or a single SKB) 1127 * caller must hold priv->lock 1128 */ 1129 static int bcmgenet_xmit_single(struct net_device *dev, 1130 struct sk_buff *skb, 1131 u16 dma_desc_flags, 1132 struct bcmgenet_tx_ring *ring) 1133 { 1134 struct bcmgenet_priv *priv = netdev_priv(dev); 1135 struct device *kdev = &priv->pdev->dev; 1136 struct enet_cb *tx_cb_ptr; 1137 unsigned int skb_len; 1138 dma_addr_t mapping; 1139 u32 length_status; 1140 int ret; 1141 1142 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1143 1144 if (unlikely(!tx_cb_ptr)) 1145 BUG(); 1146 1147 tx_cb_ptr->skb = skb; 1148 1149 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb); 1150 1151 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1152 ret = dma_mapping_error(kdev, mapping); 1153 if (ret) { 1154 priv->mib.tx_dma_failed++; 1155 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1156 dev_kfree_skb(skb); 1157 return ret; 1158 } 1159 1160 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1161 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len); 1162 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | 1163 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) | 1164 DMA_TX_APPEND_CRC; 1165 1166 if (skb->ip_summed == CHECKSUM_PARTIAL) 1167 length_status |= DMA_TX_DO_CSUM; 1168 1169 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status); 1170 1171 return 0; 1172 } 1173 1174 /* Transmit a SKB fragment */ 1175 static int bcmgenet_xmit_frag(struct net_device *dev, 1176 skb_frag_t *frag, 1177 u16 dma_desc_flags, 1178 struct bcmgenet_tx_ring *ring) 1179 { 1180 struct bcmgenet_priv *priv = netdev_priv(dev); 1181 struct device *kdev = &priv->pdev->dev; 1182 struct enet_cb *tx_cb_ptr; 1183 dma_addr_t mapping; 1184 int ret; 1185 1186 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1187 1188 if (unlikely(!tx_cb_ptr)) 1189 BUG(); 1190 tx_cb_ptr->skb = NULL; 1191 1192 mapping = skb_frag_dma_map(kdev, frag, 0, 1193 skb_frag_size(frag), DMA_TO_DEVICE); 1194 ret = dma_mapping_error(kdev, mapping); 1195 if (ret) { 1196 priv->mib.tx_dma_failed++; 1197 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n", 1198 __func__); 1199 return ret; 1200 } 1201 1202 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1203 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size); 1204 1205 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, 1206 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | 1207 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT)); 1208 1209 return 0; 1210 } 1211 1212 /* Reallocate the SKB to put enough headroom in front of it and insert 1213 * the transmit checksum offsets in the descriptors 1214 */ 1215 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1216 struct sk_buff *skb) 1217 { 1218 struct status_64 *status = NULL; 1219 struct sk_buff *new_skb; 1220 u16 offset; 1221 u8 ip_proto; 1222 u16 ip_ver; 1223 u32 tx_csum_info; 1224 1225 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1226 /* If 64 byte status block enabled, must make sure skb has 1227 * enough headroom for us to insert 64B status block. 1228 */ 1229 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1230 dev_kfree_skb(skb); 1231 if (!new_skb) { 1232 dev->stats.tx_dropped++; 1233 return NULL; 1234 } 1235 skb = new_skb; 1236 } 1237 1238 skb_push(skb, sizeof(*status)); 1239 status = (struct status_64 *)skb->data; 1240 1241 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1242 ip_ver = htons(skb->protocol); 1243 switch (ip_ver) { 1244 case ETH_P_IP: 1245 ip_proto = ip_hdr(skb)->protocol; 1246 break; 1247 case ETH_P_IPV6: 1248 ip_proto = ipv6_hdr(skb)->nexthdr; 1249 break; 1250 default: 1251 return skb; 1252 } 1253 1254 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1255 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1256 (offset + skb->csum_offset); 1257 1258 /* Set the length valid bit for TCP and UDP and just set 1259 * the special UDP flag for IPv4, else just set to 0. 1260 */ 1261 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1262 tx_csum_info |= STATUS_TX_CSUM_LV; 1263 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1264 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1265 } else { 1266 tx_csum_info = 0; 1267 } 1268 1269 status->tx_csum_info = tx_csum_info; 1270 } 1271 1272 return skb; 1273 } 1274 1275 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1276 { 1277 struct bcmgenet_priv *priv = netdev_priv(dev); 1278 struct bcmgenet_tx_ring *ring = NULL; 1279 struct netdev_queue *txq; 1280 unsigned long flags = 0; 1281 int nr_frags, index; 1282 u16 dma_desc_flags; 1283 int ret; 1284 int i; 1285 1286 index = skb_get_queue_mapping(skb); 1287 /* Mapping strategy: 1288 * queue_mapping = 0, unclassified, packet xmited through ring16 1289 * queue_mapping = 1, goes to ring 0. (highest priority queue 1290 * queue_mapping = 2, goes to ring 1. 1291 * queue_mapping = 3, goes to ring 2. 1292 * queue_mapping = 4, goes to ring 3. 1293 */ 1294 if (index == 0) 1295 index = DESC_INDEX; 1296 else 1297 index -= 1; 1298 1299 nr_frags = skb_shinfo(skb)->nr_frags; 1300 ring = &priv->tx_rings[index]; 1301 txq = netdev_get_tx_queue(dev, ring->queue); 1302 1303 spin_lock_irqsave(&ring->lock, flags); 1304 if (ring->free_bds <= nr_frags + 1) { 1305 netif_tx_stop_queue(txq); 1306 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n", 1307 __func__, index, ring->queue); 1308 ret = NETDEV_TX_BUSY; 1309 goto out; 1310 } 1311 1312 if (skb_padto(skb, ETH_ZLEN)) { 1313 ret = NETDEV_TX_OK; 1314 goto out; 1315 } 1316 1317 /* set the SKB transmit checksum */ 1318 if (priv->desc_64b_en) { 1319 skb = bcmgenet_put_tx_csum(dev, skb); 1320 if (!skb) { 1321 ret = NETDEV_TX_OK; 1322 goto out; 1323 } 1324 } 1325 1326 dma_desc_flags = DMA_SOP; 1327 if (nr_frags == 0) 1328 dma_desc_flags |= DMA_EOP; 1329 1330 /* Transmit single SKB or head of fragment list */ 1331 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring); 1332 if (ret) { 1333 ret = NETDEV_TX_OK; 1334 goto out; 1335 } 1336 1337 /* xmit fragment */ 1338 for (i = 0; i < nr_frags; i++) { 1339 ret = bcmgenet_xmit_frag(dev, 1340 &skb_shinfo(skb)->frags[i], 1341 (i == nr_frags - 1) ? DMA_EOP : 0, 1342 ring); 1343 if (ret) { 1344 ret = NETDEV_TX_OK; 1345 goto out; 1346 } 1347 } 1348 1349 skb_tx_timestamp(skb); 1350 1351 /* Decrement total BD count and advance our write pointer */ 1352 ring->free_bds -= nr_frags + 1; 1353 ring->prod_index += nr_frags + 1; 1354 ring->prod_index &= DMA_P_INDEX_MASK; 1355 1356 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1357 netif_tx_stop_queue(txq); 1358 1359 if (!skb->xmit_more || netif_xmit_stopped(txq)) 1360 /* Packets are ready, update producer index */ 1361 bcmgenet_tdma_ring_writel(priv, ring->index, 1362 ring->prod_index, TDMA_PROD_INDEX); 1363 out: 1364 spin_unlock_irqrestore(&ring->lock, flags); 1365 1366 return ret; 1367 } 1368 1369 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1370 struct enet_cb *cb) 1371 { 1372 struct device *kdev = &priv->pdev->dev; 1373 struct sk_buff *skb; 1374 struct sk_buff *rx_skb; 1375 dma_addr_t mapping; 1376 1377 /* Allocate a new Rx skb */ 1378 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1379 if (!skb) { 1380 priv->mib.alloc_rx_buff_failed++; 1381 netif_err(priv, rx_err, priv->dev, 1382 "%s: Rx skb allocation failed\n", __func__); 1383 return NULL; 1384 } 1385 1386 /* DMA-map the new Rx skb */ 1387 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1388 DMA_FROM_DEVICE); 1389 if (dma_mapping_error(kdev, mapping)) { 1390 priv->mib.rx_dma_failed++; 1391 dev_kfree_skb_any(skb); 1392 netif_err(priv, rx_err, priv->dev, 1393 "%s: Rx skb DMA mapping failed\n", __func__); 1394 return NULL; 1395 } 1396 1397 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1398 rx_skb = cb->skb; 1399 if (likely(rx_skb)) 1400 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 1401 priv->rx_buf_len, DMA_FROM_DEVICE); 1402 1403 /* Put the new Rx skb on the ring */ 1404 cb->skb = skb; 1405 dma_unmap_addr_set(cb, dma_addr, mapping); 1406 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1407 1408 /* Return the current Rx skb to caller */ 1409 return rx_skb; 1410 } 1411 1412 /* bcmgenet_desc_rx - descriptor based rx process. 1413 * this could be called from bottom half, or from NAPI polling method. 1414 */ 1415 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1416 unsigned int budget) 1417 { 1418 struct bcmgenet_priv *priv = ring->priv; 1419 struct net_device *dev = priv->dev; 1420 struct enet_cb *cb; 1421 struct sk_buff *skb; 1422 u32 dma_length_status; 1423 unsigned long dma_flag; 1424 int len; 1425 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1426 unsigned int p_index; 1427 unsigned int discards; 1428 unsigned int chksum_ok = 0; 1429 1430 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1431 1432 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1433 DMA_P_INDEX_DISCARD_CNT_MASK; 1434 if (discards > ring->old_discards) { 1435 discards = discards - ring->old_discards; 1436 dev->stats.rx_missed_errors += discards; 1437 dev->stats.rx_errors += discards; 1438 ring->old_discards += discards; 1439 1440 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1441 if (ring->old_discards >= 0xC000) { 1442 ring->old_discards = 0; 1443 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1444 RDMA_PROD_INDEX); 1445 } 1446 } 1447 1448 p_index &= DMA_P_INDEX_MASK; 1449 1450 if (likely(p_index >= ring->c_index)) 1451 rxpkttoprocess = p_index - ring->c_index; 1452 else 1453 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index + 1454 p_index; 1455 1456 netif_dbg(priv, rx_status, dev, 1457 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1458 1459 while ((rxpktprocessed < rxpkttoprocess) && 1460 (rxpktprocessed < budget)) { 1461 cb = &priv->rx_cbs[ring->read_ptr]; 1462 skb = bcmgenet_rx_refill(priv, cb); 1463 1464 if (unlikely(!skb)) { 1465 dev->stats.rx_dropped++; 1466 goto next; 1467 } 1468 1469 if (!priv->desc_64b_en) { 1470 dma_length_status = 1471 dmadesc_get_length_status(priv, cb->bd_addr); 1472 } else { 1473 struct status_64 *status; 1474 1475 status = (struct status_64 *)skb->data; 1476 dma_length_status = status->length_status; 1477 } 1478 1479 /* DMA flags and length are still valid no matter how 1480 * we got the Receive Status Vector (64B RSB or register) 1481 */ 1482 dma_flag = dma_length_status & 0xffff; 1483 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1484 1485 netif_dbg(priv, rx_status, dev, 1486 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1487 __func__, p_index, ring->c_index, 1488 ring->read_ptr, dma_length_status); 1489 1490 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1491 netif_err(priv, rx_status, dev, 1492 "dropping fragmented packet!\n"); 1493 dev->stats.rx_errors++; 1494 dev_kfree_skb_any(skb); 1495 goto next; 1496 } 1497 1498 /* report errors */ 1499 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1500 DMA_RX_OV | 1501 DMA_RX_NO | 1502 DMA_RX_LG | 1503 DMA_RX_RXER))) { 1504 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1505 (unsigned int)dma_flag); 1506 if (dma_flag & DMA_RX_CRC_ERROR) 1507 dev->stats.rx_crc_errors++; 1508 if (dma_flag & DMA_RX_OV) 1509 dev->stats.rx_over_errors++; 1510 if (dma_flag & DMA_RX_NO) 1511 dev->stats.rx_frame_errors++; 1512 if (dma_flag & DMA_RX_LG) 1513 dev->stats.rx_length_errors++; 1514 dev->stats.rx_errors++; 1515 dev_kfree_skb_any(skb); 1516 goto next; 1517 } /* error packet */ 1518 1519 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && 1520 priv->desc_rxchk_en; 1521 1522 skb_put(skb, len); 1523 if (priv->desc_64b_en) { 1524 skb_pull(skb, 64); 1525 len -= 64; 1526 } 1527 1528 if (likely(chksum_ok)) 1529 skb->ip_summed = CHECKSUM_UNNECESSARY; 1530 1531 /* remove hardware 2bytes added for IP alignment */ 1532 skb_pull(skb, 2); 1533 len -= 2; 1534 1535 if (priv->crc_fwd_en) { 1536 skb_trim(skb, len - ETH_FCS_LEN); 1537 len -= ETH_FCS_LEN; 1538 } 1539 1540 /*Finish setting up the received SKB and send it to the kernel*/ 1541 skb->protocol = eth_type_trans(skb, priv->dev); 1542 dev->stats.rx_packets++; 1543 dev->stats.rx_bytes += len; 1544 if (dma_flag & DMA_RX_MULT) 1545 dev->stats.multicast++; 1546 1547 /* Notify kernel */ 1548 napi_gro_receive(&ring->napi, skb); 1549 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1550 1551 next: 1552 rxpktprocessed++; 1553 if (likely(ring->read_ptr < ring->end_ptr)) 1554 ring->read_ptr++; 1555 else 1556 ring->read_ptr = ring->cb_ptr; 1557 1558 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1559 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1560 } 1561 1562 return rxpktprocessed; 1563 } 1564 1565 /* Rx NAPI polling method */ 1566 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1567 { 1568 struct bcmgenet_rx_ring *ring = container_of(napi, 1569 struct bcmgenet_rx_ring, napi); 1570 unsigned int work_done; 1571 1572 work_done = bcmgenet_desc_rx(ring, budget); 1573 1574 if (work_done < budget) { 1575 napi_complete(napi); 1576 ring->int_enable(ring); 1577 } 1578 1579 return work_done; 1580 } 1581 1582 /* Assign skb to RX DMA descriptor. */ 1583 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1584 struct bcmgenet_rx_ring *ring) 1585 { 1586 struct enet_cb *cb; 1587 struct sk_buff *skb; 1588 int i; 1589 1590 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1591 1592 /* loop here for each buffer needing assign */ 1593 for (i = 0; i < ring->size; i++) { 1594 cb = ring->cbs + i; 1595 skb = bcmgenet_rx_refill(priv, cb); 1596 if (skb) 1597 dev_kfree_skb_any(skb); 1598 if (!cb->skb) 1599 return -ENOMEM; 1600 } 1601 1602 return 0; 1603 } 1604 1605 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1606 { 1607 struct enet_cb *cb; 1608 int i; 1609 1610 for (i = 0; i < priv->num_rx_bds; i++) { 1611 cb = &priv->rx_cbs[i]; 1612 1613 if (dma_unmap_addr(cb, dma_addr)) { 1614 dma_unmap_single(&priv->dev->dev, 1615 dma_unmap_addr(cb, dma_addr), 1616 priv->rx_buf_len, DMA_FROM_DEVICE); 1617 dma_unmap_addr_set(cb, dma_addr, 0); 1618 } 1619 1620 if (cb->skb) 1621 bcmgenet_free_cb(cb); 1622 } 1623 } 1624 1625 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1626 { 1627 u32 reg; 1628 1629 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1630 if (enable) 1631 reg |= mask; 1632 else 1633 reg &= ~mask; 1634 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1635 1636 /* UniMAC stops on a packet boundary, wait for a full-size packet 1637 * to be processed 1638 */ 1639 if (enable == 0) 1640 usleep_range(1000, 2000); 1641 } 1642 1643 static int reset_umac(struct bcmgenet_priv *priv) 1644 { 1645 struct device *kdev = &priv->pdev->dev; 1646 unsigned int timeout = 0; 1647 u32 reg; 1648 1649 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1650 bcmgenet_rbuf_ctrl_set(priv, 0); 1651 udelay(10); 1652 1653 /* disable MAC while updating its registers */ 1654 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1655 1656 /* issue soft reset, wait for it to complete */ 1657 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 1658 while (timeout++ < 1000) { 1659 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1660 if (!(reg & CMD_SW_RESET)) 1661 return 0; 1662 1663 udelay(1); 1664 } 1665 1666 if (timeout == 1000) { 1667 dev_err(kdev, 1668 "timeout waiting for MAC to come out of reset\n"); 1669 return -ETIMEDOUT; 1670 } 1671 1672 return 0; 1673 } 1674 1675 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1676 { 1677 /* Mask all interrupts.*/ 1678 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1679 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1680 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1681 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1682 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1683 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1684 } 1685 1686 static int init_umac(struct bcmgenet_priv *priv) 1687 { 1688 struct device *kdev = &priv->pdev->dev; 1689 int ret; 1690 u32 reg; 1691 u32 int0_enable = 0; 1692 u32 int1_enable = 0; 1693 int i; 1694 1695 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 1696 1697 ret = reset_umac(priv); 1698 if (ret) 1699 return ret; 1700 1701 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1702 /* clear tx/rx counter */ 1703 bcmgenet_umac_writel(priv, 1704 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 1705 UMAC_MIB_CTRL); 1706 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 1707 1708 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1709 1710 /* init rx registers, enable ip header optimization */ 1711 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 1712 reg |= RBUF_ALIGN_2B; 1713 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 1714 1715 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 1716 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 1717 1718 bcmgenet_intr_disable(priv); 1719 1720 /* Enable Rx default queue 16 interrupts */ 1721 int0_enable |= UMAC_IRQ_RXDMA_DONE; 1722 1723 /* Enable Tx default queue 16 interrupts */ 1724 int0_enable |= UMAC_IRQ_TXDMA_DONE; 1725 1726 /* Monitor cable plug/unplugged event for internal PHY */ 1727 if (priv->internal_phy) { 1728 int0_enable |= UMAC_IRQ_LINK_EVENT; 1729 } else if (priv->ext_phy) { 1730 int0_enable |= UMAC_IRQ_LINK_EVENT; 1731 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1732 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 1733 int0_enable |= UMAC_IRQ_LINK_EVENT; 1734 1735 reg = bcmgenet_bp_mc_get(priv); 1736 reg |= BIT(priv->hw_params->bp_in_en_shift); 1737 1738 /* bp_mask: back pressure mask */ 1739 if (netif_is_multiqueue(priv->dev)) 1740 reg |= priv->hw_params->bp_in_mask; 1741 else 1742 reg &= ~priv->hw_params->bp_in_mask; 1743 bcmgenet_bp_mc_set(priv, reg); 1744 } 1745 1746 /* Enable MDIO interrupts on GENET v3+ */ 1747 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 1748 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 1749 1750 /* Enable Rx priority queue interrupts */ 1751 for (i = 0; i < priv->hw_params->rx_queues; ++i) 1752 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); 1753 1754 /* Enable Tx priority queue interrupts */ 1755 for (i = 0; i < priv->hw_params->tx_queues; ++i) 1756 int1_enable |= (1 << i); 1757 1758 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 1759 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 1760 1761 /* Enable rx/tx engine.*/ 1762 dev_dbg(kdev, "done init umac\n"); 1763 1764 return 0; 1765 } 1766 1767 /* Initialize a Tx ring along with corresponding hardware registers */ 1768 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 1769 unsigned int index, unsigned int size, 1770 unsigned int start_ptr, unsigned int end_ptr) 1771 { 1772 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 1773 u32 words_per_bd = WORDS_PER_BD(priv); 1774 u32 flow_period_val = 0; 1775 1776 spin_lock_init(&ring->lock); 1777 ring->priv = priv; 1778 ring->index = index; 1779 if (index == DESC_INDEX) { 1780 ring->queue = 0; 1781 ring->int_enable = bcmgenet_tx_ring16_int_enable; 1782 ring->int_disable = bcmgenet_tx_ring16_int_disable; 1783 } else { 1784 ring->queue = index + 1; 1785 ring->int_enable = bcmgenet_tx_ring_int_enable; 1786 ring->int_disable = bcmgenet_tx_ring_int_disable; 1787 } 1788 ring->cbs = priv->tx_cbs + start_ptr; 1789 ring->size = size; 1790 ring->clean_ptr = start_ptr; 1791 ring->c_index = 0; 1792 ring->free_bds = size; 1793 ring->write_ptr = start_ptr; 1794 ring->cb_ptr = start_ptr; 1795 ring->end_ptr = end_ptr - 1; 1796 ring->prod_index = 0; 1797 1798 /* Set flow period for ring != 16 */ 1799 if (index != DESC_INDEX) 1800 flow_period_val = ENET_MAX_MTU_SIZE << 16; 1801 1802 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 1803 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 1804 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 1805 /* Disable rate control for now */ 1806 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 1807 TDMA_FLOW_PERIOD); 1808 bcmgenet_tdma_ring_writel(priv, index, 1809 ((size << DMA_RING_SIZE_SHIFT) | 1810 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 1811 1812 /* Set start and end address, read and write pointers */ 1813 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 1814 DMA_START_ADDR); 1815 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 1816 TDMA_READ_PTR); 1817 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 1818 TDMA_WRITE_PTR); 1819 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 1820 DMA_END_ADDR); 1821 } 1822 1823 /* Initialize a RDMA ring */ 1824 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 1825 unsigned int index, unsigned int size, 1826 unsigned int start_ptr, unsigned int end_ptr) 1827 { 1828 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 1829 u32 words_per_bd = WORDS_PER_BD(priv); 1830 int ret; 1831 1832 ring->priv = priv; 1833 ring->index = index; 1834 if (index == DESC_INDEX) { 1835 ring->int_enable = bcmgenet_rx_ring16_int_enable; 1836 ring->int_disable = bcmgenet_rx_ring16_int_disable; 1837 } else { 1838 ring->int_enable = bcmgenet_rx_ring_int_enable; 1839 ring->int_disable = bcmgenet_rx_ring_int_disable; 1840 } 1841 ring->cbs = priv->rx_cbs + start_ptr; 1842 ring->size = size; 1843 ring->c_index = 0; 1844 ring->read_ptr = start_ptr; 1845 ring->cb_ptr = start_ptr; 1846 ring->end_ptr = end_ptr - 1; 1847 1848 ret = bcmgenet_alloc_rx_buffers(priv, ring); 1849 if (ret) 1850 return ret; 1851 1852 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 1853 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 1854 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 1855 bcmgenet_rdma_ring_writel(priv, index, 1856 ((size << DMA_RING_SIZE_SHIFT) | 1857 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 1858 bcmgenet_rdma_ring_writel(priv, index, 1859 (DMA_FC_THRESH_LO << 1860 DMA_XOFF_THRESHOLD_SHIFT) | 1861 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 1862 1863 /* Set start and end address, read and write pointers */ 1864 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 1865 DMA_START_ADDR); 1866 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 1867 RDMA_READ_PTR); 1868 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 1869 RDMA_WRITE_PTR); 1870 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 1871 DMA_END_ADDR); 1872 1873 return ret; 1874 } 1875 1876 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) 1877 { 1878 unsigned int i; 1879 struct bcmgenet_tx_ring *ring; 1880 1881 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 1882 ring = &priv->tx_rings[i]; 1883 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 1884 } 1885 1886 ring = &priv->tx_rings[DESC_INDEX]; 1887 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 1888 } 1889 1890 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 1891 { 1892 unsigned int i; 1893 struct bcmgenet_tx_ring *ring; 1894 1895 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 1896 ring = &priv->tx_rings[i]; 1897 napi_enable(&ring->napi); 1898 } 1899 1900 ring = &priv->tx_rings[DESC_INDEX]; 1901 napi_enable(&ring->napi); 1902 } 1903 1904 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 1905 { 1906 unsigned int i; 1907 struct bcmgenet_tx_ring *ring; 1908 1909 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 1910 ring = &priv->tx_rings[i]; 1911 napi_disable(&ring->napi); 1912 } 1913 1914 ring = &priv->tx_rings[DESC_INDEX]; 1915 napi_disable(&ring->napi); 1916 } 1917 1918 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 1919 { 1920 unsigned int i; 1921 struct bcmgenet_tx_ring *ring; 1922 1923 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 1924 ring = &priv->tx_rings[i]; 1925 netif_napi_del(&ring->napi); 1926 } 1927 1928 ring = &priv->tx_rings[DESC_INDEX]; 1929 netif_napi_del(&ring->napi); 1930 } 1931 1932 /* Initialize Tx queues 1933 * 1934 * Queues 0-3 are priority-based, each one has 32 descriptors, 1935 * with queue 0 being the highest priority queue. 1936 * 1937 * Queue 16 is the default Tx queue with 1938 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 1939 * 1940 * The transmit control block pool is then partitioned as follows: 1941 * - Tx queue 0 uses tx_cbs[0..31] 1942 * - Tx queue 1 uses tx_cbs[32..63] 1943 * - Tx queue 2 uses tx_cbs[64..95] 1944 * - Tx queue 3 uses tx_cbs[96..127] 1945 * - Tx queue 16 uses tx_cbs[128..255] 1946 */ 1947 static void bcmgenet_init_tx_queues(struct net_device *dev) 1948 { 1949 struct bcmgenet_priv *priv = netdev_priv(dev); 1950 u32 i, dma_enable; 1951 u32 dma_ctrl, ring_cfg; 1952 u32 dma_priority[3] = {0, 0, 0}; 1953 1954 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 1955 dma_enable = dma_ctrl & DMA_EN; 1956 dma_ctrl &= ~DMA_EN; 1957 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 1958 1959 dma_ctrl = 0; 1960 ring_cfg = 0; 1961 1962 /* Enable strict priority arbiter mode */ 1963 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 1964 1965 /* Initialize Tx priority queues */ 1966 for (i = 0; i < priv->hw_params->tx_queues; i++) { 1967 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 1968 i * priv->hw_params->tx_bds_per_q, 1969 (i + 1) * priv->hw_params->tx_bds_per_q); 1970 ring_cfg |= (1 << i); 1971 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 1972 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 1973 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 1974 } 1975 1976 /* Initialize Tx default queue 16 */ 1977 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 1978 priv->hw_params->tx_queues * 1979 priv->hw_params->tx_bds_per_q, 1980 TOTAL_DESC); 1981 ring_cfg |= (1 << DESC_INDEX); 1982 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 1983 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 1984 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 1985 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 1986 1987 /* Set Tx queue priorities */ 1988 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 1989 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 1990 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 1991 1992 /* Initialize Tx NAPI */ 1993 bcmgenet_init_tx_napi(priv); 1994 1995 /* Enable Tx queues */ 1996 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 1997 1998 /* Enable Tx DMA */ 1999 if (dma_enable) 2000 dma_ctrl |= DMA_EN; 2001 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2002 } 2003 2004 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv) 2005 { 2006 unsigned int i; 2007 struct bcmgenet_rx_ring *ring; 2008 2009 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2010 ring = &priv->rx_rings[i]; 2011 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2012 } 2013 2014 ring = &priv->rx_rings[DESC_INDEX]; 2015 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2016 } 2017 2018 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2019 { 2020 unsigned int i; 2021 struct bcmgenet_rx_ring *ring; 2022 2023 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2024 ring = &priv->rx_rings[i]; 2025 napi_enable(&ring->napi); 2026 } 2027 2028 ring = &priv->rx_rings[DESC_INDEX]; 2029 napi_enable(&ring->napi); 2030 } 2031 2032 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2033 { 2034 unsigned int i; 2035 struct bcmgenet_rx_ring *ring; 2036 2037 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2038 ring = &priv->rx_rings[i]; 2039 napi_disable(&ring->napi); 2040 } 2041 2042 ring = &priv->rx_rings[DESC_INDEX]; 2043 napi_disable(&ring->napi); 2044 } 2045 2046 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2047 { 2048 unsigned int i; 2049 struct bcmgenet_rx_ring *ring; 2050 2051 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2052 ring = &priv->rx_rings[i]; 2053 netif_napi_del(&ring->napi); 2054 } 2055 2056 ring = &priv->rx_rings[DESC_INDEX]; 2057 netif_napi_del(&ring->napi); 2058 } 2059 2060 /* Initialize Rx queues 2061 * 2062 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2063 * used to direct traffic to these queues. 2064 * 2065 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2066 */ 2067 static int bcmgenet_init_rx_queues(struct net_device *dev) 2068 { 2069 struct bcmgenet_priv *priv = netdev_priv(dev); 2070 u32 i; 2071 u32 dma_enable; 2072 u32 dma_ctrl; 2073 u32 ring_cfg; 2074 int ret; 2075 2076 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2077 dma_enable = dma_ctrl & DMA_EN; 2078 dma_ctrl &= ~DMA_EN; 2079 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2080 2081 dma_ctrl = 0; 2082 ring_cfg = 0; 2083 2084 /* Initialize Rx priority queues */ 2085 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2086 ret = bcmgenet_init_rx_ring(priv, i, 2087 priv->hw_params->rx_bds_per_q, 2088 i * priv->hw_params->rx_bds_per_q, 2089 (i + 1) * 2090 priv->hw_params->rx_bds_per_q); 2091 if (ret) 2092 return ret; 2093 2094 ring_cfg |= (1 << i); 2095 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2096 } 2097 2098 /* Initialize Rx default queue 16 */ 2099 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2100 priv->hw_params->rx_queues * 2101 priv->hw_params->rx_bds_per_q, 2102 TOTAL_DESC); 2103 if (ret) 2104 return ret; 2105 2106 ring_cfg |= (1 << DESC_INDEX); 2107 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2108 2109 /* Initialize Rx NAPI */ 2110 bcmgenet_init_rx_napi(priv); 2111 2112 /* Enable rings */ 2113 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2114 2115 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2116 if (dma_enable) 2117 dma_ctrl |= DMA_EN; 2118 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2119 2120 return 0; 2121 } 2122 2123 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2124 { 2125 int ret = 0; 2126 int timeout = 0; 2127 u32 reg; 2128 2129 /* Disable TDMA to stop add more frames in TX DMA */ 2130 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2131 reg &= ~DMA_EN; 2132 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2133 2134 /* Check TDMA status register to confirm TDMA is disabled */ 2135 while (timeout++ < DMA_TIMEOUT_VAL) { 2136 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2137 if (reg & DMA_DISABLED) 2138 break; 2139 2140 udelay(1); 2141 } 2142 2143 if (timeout == DMA_TIMEOUT_VAL) { 2144 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2145 ret = -ETIMEDOUT; 2146 } 2147 2148 /* Wait 10ms for packet drain in both tx and rx dma */ 2149 usleep_range(10000, 20000); 2150 2151 /* Disable RDMA */ 2152 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2153 reg &= ~DMA_EN; 2154 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2155 2156 timeout = 0; 2157 /* Check RDMA status register to confirm RDMA is disabled */ 2158 while (timeout++ < DMA_TIMEOUT_VAL) { 2159 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2160 if (reg & DMA_DISABLED) 2161 break; 2162 2163 udelay(1); 2164 } 2165 2166 if (timeout == DMA_TIMEOUT_VAL) { 2167 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2168 ret = -ETIMEDOUT; 2169 } 2170 2171 return ret; 2172 } 2173 2174 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2175 { 2176 int i; 2177 2178 bcmgenet_fini_rx_napi(priv); 2179 bcmgenet_fini_tx_napi(priv); 2180 2181 /* disable DMA */ 2182 bcmgenet_dma_teardown(priv); 2183 2184 for (i = 0; i < priv->num_tx_bds; i++) { 2185 if (priv->tx_cbs[i].skb != NULL) { 2186 dev_kfree_skb(priv->tx_cbs[i].skb); 2187 priv->tx_cbs[i].skb = NULL; 2188 } 2189 } 2190 2191 bcmgenet_free_rx_buffers(priv); 2192 kfree(priv->rx_cbs); 2193 kfree(priv->tx_cbs); 2194 } 2195 2196 /* init_edma: Initialize DMA control register */ 2197 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2198 { 2199 int ret; 2200 unsigned int i; 2201 struct enet_cb *cb; 2202 2203 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2204 2205 /* Initialize common Rx ring structures */ 2206 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2207 priv->num_rx_bds = TOTAL_DESC; 2208 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2209 GFP_KERNEL); 2210 if (!priv->rx_cbs) 2211 return -ENOMEM; 2212 2213 for (i = 0; i < priv->num_rx_bds; i++) { 2214 cb = priv->rx_cbs + i; 2215 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2216 } 2217 2218 /* Initialize common TX ring structures */ 2219 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2220 priv->num_tx_bds = TOTAL_DESC; 2221 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2222 GFP_KERNEL); 2223 if (!priv->tx_cbs) { 2224 kfree(priv->rx_cbs); 2225 return -ENOMEM; 2226 } 2227 2228 for (i = 0; i < priv->num_tx_bds; i++) { 2229 cb = priv->tx_cbs + i; 2230 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2231 } 2232 2233 /* Init rDma */ 2234 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2235 2236 /* Initialize Rx queues */ 2237 ret = bcmgenet_init_rx_queues(priv->dev); 2238 if (ret) { 2239 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2240 bcmgenet_free_rx_buffers(priv); 2241 kfree(priv->rx_cbs); 2242 kfree(priv->tx_cbs); 2243 return ret; 2244 } 2245 2246 /* Init tDma */ 2247 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2248 2249 /* Initialize Tx queues */ 2250 bcmgenet_init_tx_queues(priv->dev); 2251 2252 return 0; 2253 } 2254 2255 /* Interrupt bottom half */ 2256 static void bcmgenet_irq_task(struct work_struct *work) 2257 { 2258 struct bcmgenet_priv *priv = container_of( 2259 work, struct bcmgenet_priv, bcmgenet_irq_work); 2260 2261 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2262 2263 if (priv->irq0_stat & UMAC_IRQ_MPD_R) { 2264 priv->irq0_stat &= ~UMAC_IRQ_MPD_R; 2265 netif_dbg(priv, wol, priv->dev, 2266 "magic packet detected, waking up\n"); 2267 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 2268 } 2269 2270 /* Link UP/DOWN event */ 2271 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2272 (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) { 2273 phy_mac_interrupt(priv->phydev, 2274 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP)); 2275 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT; 2276 } 2277 } 2278 2279 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2280 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2281 { 2282 struct bcmgenet_priv *priv = dev_id; 2283 struct bcmgenet_rx_ring *rx_ring; 2284 struct bcmgenet_tx_ring *tx_ring; 2285 unsigned int index; 2286 2287 /* Save irq status for bottom-half processing. */ 2288 priv->irq1_stat = 2289 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2290 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2291 2292 /* clear interrupts */ 2293 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 2294 2295 netif_dbg(priv, intr, priv->dev, 2296 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat); 2297 2298 /* Check Rx priority queue interrupts */ 2299 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2300 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2301 continue; 2302 2303 rx_ring = &priv->rx_rings[index]; 2304 2305 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2306 rx_ring->int_disable(rx_ring); 2307 __napi_schedule(&rx_ring->napi); 2308 } 2309 } 2310 2311 /* Check Tx priority queue interrupts */ 2312 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2313 if (!(priv->irq1_stat & BIT(index))) 2314 continue; 2315 2316 tx_ring = &priv->tx_rings[index]; 2317 2318 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2319 tx_ring->int_disable(tx_ring); 2320 __napi_schedule(&tx_ring->napi); 2321 } 2322 } 2323 2324 return IRQ_HANDLED; 2325 } 2326 2327 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2328 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2329 { 2330 struct bcmgenet_priv *priv = dev_id; 2331 struct bcmgenet_rx_ring *rx_ring; 2332 struct bcmgenet_tx_ring *tx_ring; 2333 2334 /* Save irq status for bottom-half processing. */ 2335 priv->irq0_stat = 2336 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2337 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2338 2339 /* clear interrupts */ 2340 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 2341 2342 netif_dbg(priv, intr, priv->dev, 2343 "IRQ=0x%x\n", priv->irq0_stat); 2344 2345 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) { 2346 rx_ring = &priv->rx_rings[DESC_INDEX]; 2347 2348 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2349 rx_ring->int_disable(rx_ring); 2350 __napi_schedule(&rx_ring->napi); 2351 } 2352 } 2353 2354 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) { 2355 tx_ring = &priv->tx_rings[DESC_INDEX]; 2356 2357 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2358 tx_ring->int_disable(tx_ring); 2359 __napi_schedule(&tx_ring->napi); 2360 } 2361 } 2362 2363 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | 2364 UMAC_IRQ_PHY_DET_F | 2365 UMAC_IRQ_LINK_EVENT | 2366 UMAC_IRQ_HFB_SM | 2367 UMAC_IRQ_HFB_MM | 2368 UMAC_IRQ_MPD_R)) { 2369 /* all other interested interrupts handled in bottom half */ 2370 schedule_work(&priv->bcmgenet_irq_work); 2371 } 2372 2373 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2374 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2375 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2376 wake_up(&priv->wq); 2377 } 2378 2379 return IRQ_HANDLED; 2380 } 2381 2382 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2383 { 2384 struct bcmgenet_priv *priv = dev_id; 2385 2386 pm_wakeup_event(&priv->pdev->dev, 0); 2387 2388 return IRQ_HANDLED; 2389 } 2390 2391 #ifdef CONFIG_NET_POLL_CONTROLLER 2392 static void bcmgenet_poll_controller(struct net_device *dev) 2393 { 2394 struct bcmgenet_priv *priv = netdev_priv(dev); 2395 2396 /* Invoke the main RX/TX interrupt handler */ 2397 disable_irq(priv->irq0); 2398 bcmgenet_isr0(priv->irq0, priv); 2399 enable_irq(priv->irq0); 2400 2401 /* And the interrupt handler for RX/TX priority queues */ 2402 disable_irq(priv->irq1); 2403 bcmgenet_isr1(priv->irq1, priv); 2404 enable_irq(priv->irq1); 2405 } 2406 #endif 2407 2408 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2409 { 2410 u32 reg; 2411 2412 reg = bcmgenet_rbuf_ctrl_get(priv); 2413 reg |= BIT(1); 2414 bcmgenet_rbuf_ctrl_set(priv, reg); 2415 udelay(10); 2416 2417 reg &= ~BIT(1); 2418 bcmgenet_rbuf_ctrl_set(priv, reg); 2419 udelay(10); 2420 } 2421 2422 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2423 unsigned char *addr) 2424 { 2425 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2426 (addr[2] << 8) | addr[3], UMAC_MAC0); 2427 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2428 } 2429 2430 /* Returns a reusable dma control register value */ 2431 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2432 { 2433 u32 reg; 2434 u32 dma_ctrl; 2435 2436 /* disable DMA */ 2437 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2438 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2439 reg &= ~dma_ctrl; 2440 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2441 2442 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2443 reg &= ~dma_ctrl; 2444 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2445 2446 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2447 udelay(10); 2448 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2449 2450 return dma_ctrl; 2451 } 2452 2453 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2454 { 2455 u32 reg; 2456 2457 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2458 reg |= dma_ctrl; 2459 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2460 2461 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2462 reg |= dma_ctrl; 2463 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2464 } 2465 2466 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv, 2467 u32 f_index) 2468 { 2469 u32 offset; 2470 u32 reg; 2471 2472 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 2473 reg = bcmgenet_hfb_reg_readl(priv, offset); 2474 return !!(reg & (1 << (f_index % 32))); 2475 } 2476 2477 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 2478 { 2479 u32 offset; 2480 u32 reg; 2481 2482 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 2483 reg = bcmgenet_hfb_reg_readl(priv, offset); 2484 reg |= (1 << (f_index % 32)); 2485 bcmgenet_hfb_reg_writel(priv, reg, offset); 2486 } 2487 2488 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 2489 u32 f_index, u32 rx_queue) 2490 { 2491 u32 offset; 2492 u32 reg; 2493 2494 offset = f_index / 8; 2495 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 2496 reg &= ~(0xF << (4 * (f_index % 8))); 2497 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 2498 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 2499 } 2500 2501 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 2502 u32 f_index, u32 f_length) 2503 { 2504 u32 offset; 2505 u32 reg; 2506 2507 offset = HFB_FLT_LEN_V3PLUS + 2508 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) * 2509 sizeof(u32); 2510 reg = bcmgenet_hfb_reg_readl(priv, offset); 2511 reg &= ~(0xFF << (8 * (f_index % 4))); 2512 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 2513 bcmgenet_hfb_reg_writel(priv, reg, offset); 2514 } 2515 2516 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv) 2517 { 2518 u32 f_index; 2519 2520 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++) 2521 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index)) 2522 return f_index; 2523 2524 return -ENOMEM; 2525 } 2526 2527 /* bcmgenet_hfb_add_filter 2528 * 2529 * Add new filter to Hardware Filter Block to match and direct Rx traffic to 2530 * desired Rx queue. 2531 * 2532 * f_data is an array of unsigned 32-bit integers where each 32-bit integer 2533 * provides filter data for 2 bytes (4 nibbles) of Rx frame: 2534 * 2535 * bits 31:20 - unused 2536 * bit 19 - nibble 0 match enable 2537 * bit 18 - nibble 1 match enable 2538 * bit 17 - nibble 2 match enable 2539 * bit 16 - nibble 3 match enable 2540 * bits 15:12 - nibble 0 data 2541 * bits 11:8 - nibble 1 data 2542 * bits 7:4 - nibble 2 data 2543 * bits 3:0 - nibble 3 data 2544 * 2545 * Example: 2546 * In order to match: 2547 * - Ethernet frame type = 0x0800 (IP) 2548 * - IP version field = 4 2549 * - IP protocol field = 0x11 (UDP) 2550 * 2551 * The following filter is needed: 2552 * u32 hfb_filter_ipv4_udp[] = { 2553 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000, 2554 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000, 2555 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011, 2556 * }; 2557 * 2558 * To add the filter to HFB and direct the traffic to Rx queue 0, call: 2559 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp, 2560 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0); 2561 */ 2562 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data, 2563 u32 f_length, u32 rx_queue) 2564 { 2565 int f_index; 2566 u32 i; 2567 2568 f_index = bcmgenet_hfb_find_unused_filter(priv); 2569 if (f_index < 0) 2570 return -ENOMEM; 2571 2572 if (f_length > priv->hw_params->hfb_filter_size) 2573 return -EINVAL; 2574 2575 for (i = 0; i < f_length; i++) 2576 bcmgenet_hfb_writel(priv, f_data[i], 2577 (f_index * priv->hw_params->hfb_filter_size + i) * 2578 sizeof(u32)); 2579 2580 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length); 2581 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue); 2582 bcmgenet_hfb_enable_filter(priv, f_index); 2583 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL); 2584 2585 return 0; 2586 } 2587 2588 /* bcmgenet_hfb_clear 2589 * 2590 * Clear Hardware Filter Block and disable all filtering. 2591 */ 2592 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2593 { 2594 u32 i; 2595 2596 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2597 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2598 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2599 2600 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2601 bcmgenet_rdma_writel(priv, 0x0, i); 2602 2603 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2604 bcmgenet_hfb_reg_writel(priv, 0x0, 2605 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2606 2607 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2608 priv->hw_params->hfb_filter_size; i++) 2609 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2610 } 2611 2612 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2613 { 2614 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2615 return; 2616 2617 bcmgenet_hfb_clear(priv); 2618 } 2619 2620 static void bcmgenet_netif_start(struct net_device *dev) 2621 { 2622 struct bcmgenet_priv *priv = netdev_priv(dev); 2623 2624 /* Start the network engine */ 2625 bcmgenet_enable_rx_napi(priv); 2626 bcmgenet_enable_tx_napi(priv); 2627 2628 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2629 2630 netif_tx_start_all_queues(dev); 2631 2632 phy_start(priv->phydev); 2633 } 2634 2635 static int bcmgenet_open(struct net_device *dev) 2636 { 2637 struct bcmgenet_priv *priv = netdev_priv(dev); 2638 unsigned long dma_ctrl; 2639 u32 reg; 2640 int ret; 2641 2642 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2643 2644 /* Turn on the clock */ 2645 clk_prepare_enable(priv->clk); 2646 2647 /* If this is an internal GPHY, power it back on now, before UniMAC is 2648 * brought out of reset as absolutely no UniMAC activity is allowed 2649 */ 2650 if (priv->internal_phy) 2651 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2652 2653 /* take MAC out of reset */ 2654 bcmgenet_umac_reset(priv); 2655 2656 ret = init_umac(priv); 2657 if (ret) 2658 goto err_clk_disable; 2659 2660 /* disable ethernet MAC while updating its registers */ 2661 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 2662 2663 /* Make sure we reflect the value of CRC_CMD_FWD */ 2664 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2665 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 2666 2667 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2668 2669 if (priv->internal_phy) { 2670 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2671 reg |= EXT_ENERGY_DET_MASK; 2672 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2673 } 2674 2675 /* Disable RX/TX DMA and flush TX queues */ 2676 dma_ctrl = bcmgenet_dma_disable(priv); 2677 2678 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2679 ret = bcmgenet_init_dma(priv); 2680 if (ret) { 2681 netdev_err(dev, "failed to initialize DMA\n"); 2682 goto err_clk_disable; 2683 } 2684 2685 /* Always enable ring 16 - descriptor ring */ 2686 bcmgenet_enable_dma(priv, dma_ctrl); 2687 2688 /* HFB init */ 2689 bcmgenet_hfb_init(priv); 2690 2691 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2692 dev->name, priv); 2693 if (ret < 0) { 2694 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2695 goto err_fini_dma; 2696 } 2697 2698 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2699 dev->name, priv); 2700 if (ret < 0) { 2701 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2702 goto err_irq0; 2703 } 2704 2705 ret = bcmgenet_mii_probe(dev); 2706 if (ret) { 2707 netdev_err(dev, "failed to connect to PHY\n"); 2708 goto err_irq1; 2709 } 2710 2711 bcmgenet_netif_start(dev); 2712 2713 return 0; 2714 2715 err_irq1: 2716 free_irq(priv->irq1, priv); 2717 err_irq0: 2718 free_irq(priv->irq0, priv); 2719 err_fini_dma: 2720 bcmgenet_fini_dma(priv); 2721 err_clk_disable: 2722 clk_disable_unprepare(priv->clk); 2723 return ret; 2724 } 2725 2726 static void bcmgenet_netif_stop(struct net_device *dev) 2727 { 2728 struct bcmgenet_priv *priv = netdev_priv(dev); 2729 2730 netif_tx_stop_all_queues(dev); 2731 phy_stop(priv->phydev); 2732 bcmgenet_intr_disable(priv); 2733 bcmgenet_disable_rx_napi(priv); 2734 bcmgenet_disable_tx_napi(priv); 2735 2736 /* Wait for pending work items to complete. Since interrupts are 2737 * disabled no new work will be scheduled. 2738 */ 2739 cancel_work_sync(&priv->bcmgenet_irq_work); 2740 2741 priv->old_link = -1; 2742 priv->old_speed = -1; 2743 priv->old_duplex = -1; 2744 priv->old_pause = -1; 2745 } 2746 2747 static int bcmgenet_close(struct net_device *dev) 2748 { 2749 struct bcmgenet_priv *priv = netdev_priv(dev); 2750 int ret; 2751 2752 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2753 2754 bcmgenet_netif_stop(dev); 2755 2756 /* Really kill the PHY state machine and disconnect from it */ 2757 phy_disconnect(priv->phydev); 2758 2759 /* Disable MAC receive */ 2760 umac_enable_set(priv, CMD_RX_EN, false); 2761 2762 ret = bcmgenet_dma_teardown(priv); 2763 if (ret) 2764 return ret; 2765 2766 /* Disable MAC transmit. TX DMA disabled have to done before this */ 2767 umac_enable_set(priv, CMD_TX_EN, false); 2768 2769 /* tx reclaim */ 2770 bcmgenet_tx_reclaim_all(dev); 2771 bcmgenet_fini_dma(priv); 2772 2773 free_irq(priv->irq0, priv); 2774 free_irq(priv->irq1, priv); 2775 2776 if (priv->internal_phy) 2777 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2778 2779 clk_disable_unprepare(priv->clk); 2780 2781 return ret; 2782 } 2783 2784 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 2785 { 2786 struct bcmgenet_priv *priv = ring->priv; 2787 u32 p_index, c_index, intsts, intmsk; 2788 struct netdev_queue *txq; 2789 unsigned int free_bds; 2790 unsigned long flags; 2791 bool txq_stopped; 2792 2793 if (!netif_msg_tx_err(priv)) 2794 return; 2795 2796 txq = netdev_get_tx_queue(priv->dev, ring->queue); 2797 2798 spin_lock_irqsave(&ring->lock, flags); 2799 if (ring->index == DESC_INDEX) { 2800 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2801 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 2802 } else { 2803 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2804 intmsk = 1 << ring->index; 2805 } 2806 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 2807 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 2808 txq_stopped = netif_tx_queue_stopped(txq); 2809 free_bds = ring->free_bds; 2810 spin_unlock_irqrestore(&ring->lock, flags); 2811 2812 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 2813 "TX queue status: %s, interrupts: %s\n" 2814 "(sw)free_bds: %d (sw)size: %d\n" 2815 "(sw)p_index: %d (hw)p_index: %d\n" 2816 "(sw)c_index: %d (hw)c_index: %d\n" 2817 "(sw)clean_p: %d (sw)write_p: %d\n" 2818 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 2819 ring->index, ring->queue, 2820 txq_stopped ? "stopped" : "active", 2821 intsts & intmsk ? "enabled" : "disabled", 2822 free_bds, ring->size, 2823 ring->prod_index, p_index & DMA_P_INDEX_MASK, 2824 ring->c_index, c_index & DMA_C_INDEX_MASK, 2825 ring->clean_ptr, ring->write_ptr, 2826 ring->cb_ptr, ring->end_ptr); 2827 } 2828 2829 static void bcmgenet_timeout(struct net_device *dev) 2830 { 2831 struct bcmgenet_priv *priv = netdev_priv(dev); 2832 u32 int0_enable = 0; 2833 u32 int1_enable = 0; 2834 unsigned int q; 2835 2836 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 2837 2838 bcmgenet_disable_tx_napi(priv); 2839 2840 for (q = 0; q < priv->hw_params->tx_queues; q++) 2841 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 2842 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 2843 2844 bcmgenet_tx_reclaim_all(dev); 2845 2846 for (q = 0; q < priv->hw_params->tx_queues; q++) 2847 int1_enable |= (1 << q); 2848 2849 int0_enable = UMAC_IRQ_TXDMA_DONE; 2850 2851 /* Re-enable TX interrupts if disabled */ 2852 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2853 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2854 2855 bcmgenet_enable_tx_napi(priv); 2856 2857 dev->trans_start = jiffies; 2858 2859 dev->stats.tx_errors++; 2860 2861 netif_tx_wake_all_queues(dev); 2862 } 2863 2864 #define MAX_MC_COUNT 16 2865 2866 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 2867 unsigned char *addr, 2868 int *i, 2869 int *mc) 2870 { 2871 u32 reg; 2872 2873 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 2874 UMAC_MDF_ADDR + (*i * 4)); 2875 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 2876 addr[4] << 8 | addr[5], 2877 UMAC_MDF_ADDR + ((*i + 1) * 4)); 2878 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); 2879 reg |= (1 << (MAX_MC_COUNT - *mc)); 2880 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 2881 *i += 2; 2882 (*mc)++; 2883 } 2884 2885 static void bcmgenet_set_rx_mode(struct net_device *dev) 2886 { 2887 struct bcmgenet_priv *priv = netdev_priv(dev); 2888 struct netdev_hw_addr *ha; 2889 int i, mc; 2890 u32 reg; 2891 2892 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 2893 2894 /* Promiscuous mode */ 2895 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2896 if (dev->flags & IFF_PROMISC) { 2897 reg |= CMD_PROMISC; 2898 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2899 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 2900 return; 2901 } else { 2902 reg &= ~CMD_PROMISC; 2903 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2904 } 2905 2906 /* UniMac doesn't support ALLMULTI */ 2907 if (dev->flags & IFF_ALLMULTI) { 2908 netdev_warn(dev, "ALLMULTI is not supported\n"); 2909 return; 2910 } 2911 2912 /* update MDF filter */ 2913 i = 0; 2914 mc = 0; 2915 /* Broadcast */ 2916 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); 2917 /* my own address.*/ 2918 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); 2919 /* Unicast list*/ 2920 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) 2921 return; 2922 2923 if (!netdev_uc_empty(dev)) 2924 netdev_for_each_uc_addr(ha, dev) 2925 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 2926 /* Multicast */ 2927 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) 2928 return; 2929 2930 netdev_for_each_mc_addr(ha, dev) 2931 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 2932 } 2933 2934 /* Set the hardware MAC address. */ 2935 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 2936 { 2937 struct sockaddr *addr = p; 2938 2939 /* Setting the MAC address at the hardware level is not possible 2940 * without disabling the UniMAC RX/TX enable bits. 2941 */ 2942 if (netif_running(dev)) 2943 return -EBUSY; 2944 2945 ether_addr_copy(dev->dev_addr, addr->sa_data); 2946 2947 return 0; 2948 } 2949 2950 static const struct net_device_ops bcmgenet_netdev_ops = { 2951 .ndo_open = bcmgenet_open, 2952 .ndo_stop = bcmgenet_close, 2953 .ndo_start_xmit = bcmgenet_xmit, 2954 .ndo_tx_timeout = bcmgenet_timeout, 2955 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 2956 .ndo_set_mac_address = bcmgenet_set_mac_addr, 2957 .ndo_do_ioctl = bcmgenet_ioctl, 2958 .ndo_set_features = bcmgenet_set_features, 2959 #ifdef CONFIG_NET_POLL_CONTROLLER 2960 .ndo_poll_controller = bcmgenet_poll_controller, 2961 #endif 2962 }; 2963 2964 /* Array of GENET hardware parameters/characteristics */ 2965 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 2966 [GENET_V1] = { 2967 .tx_queues = 0, 2968 .tx_bds_per_q = 0, 2969 .rx_queues = 0, 2970 .rx_bds_per_q = 0, 2971 .bp_in_en_shift = 16, 2972 .bp_in_mask = 0xffff, 2973 .hfb_filter_cnt = 16, 2974 .qtag_mask = 0x1F, 2975 .hfb_offset = 0x1000, 2976 .rdma_offset = 0x2000, 2977 .tdma_offset = 0x3000, 2978 .words_per_bd = 2, 2979 }, 2980 [GENET_V2] = { 2981 .tx_queues = 4, 2982 .tx_bds_per_q = 32, 2983 .rx_queues = 0, 2984 .rx_bds_per_q = 0, 2985 .bp_in_en_shift = 16, 2986 .bp_in_mask = 0xffff, 2987 .hfb_filter_cnt = 16, 2988 .qtag_mask = 0x1F, 2989 .tbuf_offset = 0x0600, 2990 .hfb_offset = 0x1000, 2991 .hfb_reg_offset = 0x2000, 2992 .rdma_offset = 0x3000, 2993 .tdma_offset = 0x4000, 2994 .words_per_bd = 2, 2995 .flags = GENET_HAS_EXT, 2996 }, 2997 [GENET_V3] = { 2998 .tx_queues = 4, 2999 .tx_bds_per_q = 32, 3000 .rx_queues = 0, 3001 .rx_bds_per_q = 0, 3002 .bp_in_en_shift = 17, 3003 .bp_in_mask = 0x1ffff, 3004 .hfb_filter_cnt = 48, 3005 .hfb_filter_size = 128, 3006 .qtag_mask = 0x3F, 3007 .tbuf_offset = 0x0600, 3008 .hfb_offset = 0x8000, 3009 .hfb_reg_offset = 0xfc00, 3010 .rdma_offset = 0x10000, 3011 .tdma_offset = 0x11000, 3012 .words_per_bd = 2, 3013 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3014 GENET_HAS_MOCA_LINK_DET, 3015 }, 3016 [GENET_V4] = { 3017 .tx_queues = 4, 3018 .tx_bds_per_q = 32, 3019 .rx_queues = 0, 3020 .rx_bds_per_q = 0, 3021 .bp_in_en_shift = 17, 3022 .bp_in_mask = 0x1ffff, 3023 .hfb_filter_cnt = 48, 3024 .hfb_filter_size = 128, 3025 .qtag_mask = 0x3F, 3026 .tbuf_offset = 0x0600, 3027 .hfb_offset = 0x8000, 3028 .hfb_reg_offset = 0xfc00, 3029 .rdma_offset = 0x2000, 3030 .tdma_offset = 0x4000, 3031 .words_per_bd = 3, 3032 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3033 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3034 }, 3035 }; 3036 3037 /* Infer hardware parameters from the detected GENET version */ 3038 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3039 { 3040 struct bcmgenet_hw_params *params; 3041 u32 reg; 3042 u8 major; 3043 u16 gphy_rev; 3044 3045 if (GENET_IS_V4(priv)) { 3046 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3047 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3048 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3049 priv->version = GENET_V4; 3050 } else if (GENET_IS_V3(priv)) { 3051 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3052 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3053 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3054 priv->version = GENET_V3; 3055 } else if (GENET_IS_V2(priv)) { 3056 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3057 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3058 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3059 priv->version = GENET_V2; 3060 } else if (GENET_IS_V1(priv)) { 3061 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3062 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3063 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3064 priv->version = GENET_V1; 3065 } 3066 3067 /* enum genet_version starts at 1 */ 3068 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3069 params = priv->hw_params; 3070 3071 /* Read GENET HW version */ 3072 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3073 major = (reg >> 24 & 0x0f); 3074 if (major == 5) 3075 major = 4; 3076 else if (major == 0) 3077 major = 1; 3078 if (major != priv->version) { 3079 dev_err(&priv->pdev->dev, 3080 "GENET version mismatch, got: %d, configured for: %d\n", 3081 major, priv->version); 3082 } 3083 3084 /* Print the GENET core version */ 3085 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3086 major, (reg >> 16) & 0x0f, reg & 0xffff); 3087 3088 /* Store the integrated PHY revision for the MDIO probing function 3089 * to pass this information to the PHY driver. The PHY driver expects 3090 * to find the PHY major revision in bits 15:8 while the GENET register 3091 * stores that information in bits 7:0, account for that. 3092 * 3093 * On newer chips, starting with PHY revision G0, a new scheme is 3094 * deployed similar to the Starfighter 2 switch with GPHY major 3095 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3096 * is reserved as well as special value 0x01ff, we have a small 3097 * heuristic to check for the new GPHY revision and re-arrange things 3098 * so the GPHY driver is happy. 3099 */ 3100 gphy_rev = reg & 0xffff; 3101 3102 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3103 if ((gphy_rev & 0xf0) != 0) 3104 priv->gphy_rev = gphy_rev << 8; 3105 3106 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3107 else if ((gphy_rev & 0xff00) != 0) 3108 priv->gphy_rev = gphy_rev; 3109 3110 /* This is reserved so should require special treatment */ 3111 else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3112 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3113 return; 3114 } 3115 3116 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3117 if (!(params->flags & GENET_HAS_40BITS)) 3118 pr_warn("GENET does not support 40-bits PA\n"); 3119 #endif 3120 3121 pr_debug("Configuration for version: %d\n" 3122 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3123 "BP << en: %2d, BP msk: 0x%05x\n" 3124 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3125 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3126 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3127 "Words/BD: %d\n", 3128 priv->version, 3129 params->tx_queues, params->tx_bds_per_q, 3130 params->rx_queues, params->rx_bds_per_q, 3131 params->bp_in_en_shift, params->bp_in_mask, 3132 params->hfb_filter_cnt, params->qtag_mask, 3133 params->tbuf_offset, params->hfb_offset, 3134 params->hfb_reg_offset, 3135 params->rdma_offset, params->tdma_offset, 3136 params->words_per_bd); 3137 } 3138 3139 static const struct of_device_id bcmgenet_match[] = { 3140 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, 3141 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, 3142 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, 3143 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, 3144 { }, 3145 }; 3146 3147 static int bcmgenet_probe(struct platform_device *pdev) 3148 { 3149 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3150 struct device_node *dn = pdev->dev.of_node; 3151 const struct of_device_id *of_id = NULL; 3152 struct bcmgenet_priv *priv; 3153 struct net_device *dev; 3154 const void *macaddr; 3155 struct resource *r; 3156 int err = -EIO; 3157 3158 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3159 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3160 GENET_MAX_MQ_CNT + 1); 3161 if (!dev) { 3162 dev_err(&pdev->dev, "can't allocate net device\n"); 3163 return -ENOMEM; 3164 } 3165 3166 if (dn) { 3167 of_id = of_match_node(bcmgenet_match, dn); 3168 if (!of_id) 3169 return -EINVAL; 3170 } 3171 3172 priv = netdev_priv(dev); 3173 priv->irq0 = platform_get_irq(pdev, 0); 3174 priv->irq1 = platform_get_irq(pdev, 1); 3175 priv->wol_irq = platform_get_irq(pdev, 2); 3176 if (!priv->irq0 || !priv->irq1) { 3177 dev_err(&pdev->dev, "can't find IRQs\n"); 3178 err = -EINVAL; 3179 goto err; 3180 } 3181 3182 if (dn) { 3183 macaddr = of_get_mac_address(dn); 3184 if (!macaddr) { 3185 dev_err(&pdev->dev, "can't find MAC address\n"); 3186 err = -EINVAL; 3187 goto err; 3188 } 3189 } else { 3190 macaddr = pd->mac_address; 3191 } 3192 3193 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3194 priv->base = devm_ioremap_resource(&pdev->dev, r); 3195 if (IS_ERR(priv->base)) { 3196 err = PTR_ERR(priv->base); 3197 goto err; 3198 } 3199 3200 SET_NETDEV_DEV(dev, &pdev->dev); 3201 dev_set_drvdata(&pdev->dev, dev); 3202 ether_addr_copy(dev->dev_addr, macaddr); 3203 dev->watchdog_timeo = 2 * HZ; 3204 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3205 dev->netdev_ops = &bcmgenet_netdev_ops; 3206 3207 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3208 3209 /* Set hardware features */ 3210 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 3211 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; 3212 3213 /* Request the WOL interrupt and advertise suspend if available */ 3214 priv->wol_irq_disabled = true; 3215 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3216 dev->name, priv); 3217 if (!err) 3218 device_set_wakeup_capable(&pdev->dev, 1); 3219 3220 /* Set the needed headroom to account for any possible 3221 * features enabling/disabling at runtime 3222 */ 3223 dev->needed_headroom += 64; 3224 3225 netdev_boot_setup_check(dev); 3226 3227 priv->dev = dev; 3228 priv->pdev = pdev; 3229 if (of_id) 3230 priv->version = (enum bcmgenet_version)of_id->data; 3231 else 3232 priv->version = pd->genet_version; 3233 3234 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3235 if (IS_ERR(priv->clk)) { 3236 dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); 3237 priv->clk = NULL; 3238 } 3239 3240 clk_prepare_enable(priv->clk); 3241 3242 bcmgenet_set_hw_params(priv); 3243 3244 /* Mii wait queue */ 3245 init_waitqueue_head(&priv->wq); 3246 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3247 priv->rx_buf_len = RX_BUF_LENGTH; 3248 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3249 3250 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3251 if (IS_ERR(priv->clk_wol)) { 3252 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3253 priv->clk_wol = NULL; 3254 } 3255 3256 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3257 if (IS_ERR(priv->clk_eee)) { 3258 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3259 priv->clk_eee = NULL; 3260 } 3261 3262 err = reset_umac(priv); 3263 if (err) 3264 goto err_clk_disable; 3265 3266 err = bcmgenet_mii_init(dev); 3267 if (err) 3268 goto err_clk_disable; 3269 3270 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3271 * just the ring 16 descriptor based TX 3272 */ 3273 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3274 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3275 3276 /* libphy will determine the link state */ 3277 netif_carrier_off(dev); 3278 3279 /* Turn off the main clock, WOL clock is handled separately */ 3280 clk_disable_unprepare(priv->clk); 3281 3282 err = register_netdev(dev); 3283 if (err) 3284 goto err; 3285 3286 return err; 3287 3288 err_clk_disable: 3289 clk_disable_unprepare(priv->clk); 3290 err: 3291 free_netdev(dev); 3292 return err; 3293 } 3294 3295 static int bcmgenet_remove(struct platform_device *pdev) 3296 { 3297 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3298 3299 dev_set_drvdata(&pdev->dev, NULL); 3300 unregister_netdev(priv->dev); 3301 bcmgenet_mii_exit(priv->dev); 3302 free_netdev(priv->dev); 3303 3304 return 0; 3305 } 3306 3307 #ifdef CONFIG_PM_SLEEP 3308 static int bcmgenet_suspend(struct device *d) 3309 { 3310 struct net_device *dev = dev_get_drvdata(d); 3311 struct bcmgenet_priv *priv = netdev_priv(dev); 3312 int ret; 3313 3314 if (!netif_running(dev)) 3315 return 0; 3316 3317 bcmgenet_netif_stop(dev); 3318 3319 phy_suspend(priv->phydev); 3320 3321 netif_device_detach(dev); 3322 3323 /* Disable MAC receive */ 3324 umac_enable_set(priv, CMD_RX_EN, false); 3325 3326 ret = bcmgenet_dma_teardown(priv); 3327 if (ret) 3328 return ret; 3329 3330 /* Disable MAC transmit. TX DMA disabled have to done before this */ 3331 umac_enable_set(priv, CMD_TX_EN, false); 3332 3333 /* tx reclaim */ 3334 bcmgenet_tx_reclaim_all(dev); 3335 bcmgenet_fini_dma(priv); 3336 3337 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3338 if (device_may_wakeup(d) && priv->wolopts) { 3339 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3340 clk_prepare_enable(priv->clk_wol); 3341 } else if (priv->internal_phy) { 3342 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3343 } 3344 3345 /* Turn off the clocks */ 3346 clk_disable_unprepare(priv->clk); 3347 3348 return ret; 3349 } 3350 3351 static int bcmgenet_resume(struct device *d) 3352 { 3353 struct net_device *dev = dev_get_drvdata(d); 3354 struct bcmgenet_priv *priv = netdev_priv(dev); 3355 unsigned long dma_ctrl; 3356 int ret; 3357 u32 reg; 3358 3359 if (!netif_running(dev)) 3360 return 0; 3361 3362 /* Turn on the clock */ 3363 ret = clk_prepare_enable(priv->clk); 3364 if (ret) 3365 return ret; 3366 3367 /* If this is an internal GPHY, power it back on now, before UniMAC is 3368 * brought out of reset as absolutely no UniMAC activity is allowed 3369 */ 3370 if (priv->internal_phy) 3371 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3372 3373 bcmgenet_umac_reset(priv); 3374 3375 ret = init_umac(priv); 3376 if (ret) 3377 goto out_clk_disable; 3378 3379 /* From WOL-enabled suspend, switch to regular clock */ 3380 if (priv->wolopts) 3381 clk_disable_unprepare(priv->clk_wol); 3382 3383 phy_init_hw(priv->phydev); 3384 /* Speed settings must be restored */ 3385 bcmgenet_mii_config(priv->dev); 3386 3387 /* disable ethernet MAC while updating its registers */ 3388 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 3389 3390 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3391 3392 if (priv->internal_phy) { 3393 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3394 reg |= EXT_ENERGY_DET_MASK; 3395 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3396 } 3397 3398 if (priv->wolopts) 3399 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3400 3401 /* Disable RX/TX DMA and flush TX queues */ 3402 dma_ctrl = bcmgenet_dma_disable(priv); 3403 3404 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3405 ret = bcmgenet_init_dma(priv); 3406 if (ret) { 3407 netdev_err(dev, "failed to initialize DMA\n"); 3408 goto out_clk_disable; 3409 } 3410 3411 /* Always enable ring 16 - descriptor ring */ 3412 bcmgenet_enable_dma(priv, dma_ctrl); 3413 3414 netif_device_attach(dev); 3415 3416 phy_resume(priv->phydev); 3417 3418 if (priv->eee.eee_enabled) 3419 bcmgenet_eee_enable_set(dev, true); 3420 3421 bcmgenet_netif_start(dev); 3422 3423 return 0; 3424 3425 out_clk_disable: 3426 clk_disable_unprepare(priv->clk); 3427 return ret; 3428 } 3429 #endif /* CONFIG_PM_SLEEP */ 3430 3431 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3432 3433 static struct platform_driver bcmgenet_driver = { 3434 .probe = bcmgenet_probe, 3435 .remove = bcmgenet_remove, 3436 .driver = { 3437 .name = "bcmgenet", 3438 .of_match_table = bcmgenet_match, 3439 .pm = &bcmgenet_pm_ops, 3440 }, 3441 }; 3442 module_platform_driver(bcmgenet_driver); 3443 3444 MODULE_AUTHOR("Broadcom Corporation"); 3445 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3446 MODULE_ALIAS("platform:bcmgenet"); 3447 MODULE_LICENSE("GPL"); 3448