1 /* 2 * Broadcom GENET (Gigabit Ethernet) controller driver 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) "bcmgenet: " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/types.h> 17 #include <linux/fcntl.h> 18 #include <linux/interrupt.h> 19 #include <linux/string.h> 20 #include <linux/if_ether.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/delay.h> 24 #include <linux/platform_device.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/pm.h> 27 #include <linux/clk.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_net.h> 32 #include <linux/of_platform.h> 33 #include <net/arp.h> 34 35 #include <linux/mii.h> 36 #include <linux/ethtool.h> 37 #include <linux/netdevice.h> 38 #include <linux/inetdevice.h> 39 #include <linux/etherdevice.h> 40 #include <linux/skbuff.h> 41 #include <linux/in.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/phy.h> 45 #include <linux/platform_data/bcmgenet.h> 46 47 #include <asm/unaligned.h> 48 49 #include "bcmgenet.h" 50 51 /* Maximum number of hardware queues, downsized if needed */ 52 #define GENET_MAX_MQ_CNT 4 53 54 /* Default highest priority queue for multi queue support */ 55 #define GENET_Q0_PRIORITY 0 56 57 #define GENET_Q16_RX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 59 #define GENET_Q16_TX_BD_CNT \ 60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 61 62 #define RX_BUF_LENGTH 2048 63 #define SKB_ALIGNMENT 32 64 65 /* Tx/Rx DMA register offset, skip 256 descriptors */ 66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 68 69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 70 TOTAL_DESC * DMA_DESC_SIZE) 71 72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 73 TOTAL_DESC * DMA_DESC_SIZE) 74 75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 76 void __iomem *d, u32 value) 77 { 78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS); 79 } 80 81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 82 void __iomem *d) 83 { 84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS); 85 } 86 87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 88 void __iomem *d, 89 dma_addr_t addr) 90 { 91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 92 93 /* Register writes to GISB bus can take couple hundred nanoseconds 94 * and are done for each packet, save these expensive writes unless 95 * the platform is explicitly configured for 64-bits/LPAE. 96 */ 97 #ifdef CONFIG_PHYS_ADDR_T_64BIT 98 if (priv->hw_params->flags & GENET_HAS_40BITS) 99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 100 #endif 101 } 102 103 /* Combined address + length/status setter */ 104 static inline void dmadesc_set(struct bcmgenet_priv *priv, 105 void __iomem *d, dma_addr_t addr, u32 val) 106 { 107 dmadesc_set_addr(priv, d, addr); 108 dmadesc_set_length_status(priv, d, val); 109 } 110 111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 112 void __iomem *d) 113 { 114 dma_addr_t addr; 115 116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO); 117 118 /* Register writes to GISB bus can take couple hundred nanoseconds 119 * and are done for each packet, save these expensive writes unless 120 * the platform is explicitly configured for 64-bits/LPAE. 121 */ 122 #ifdef CONFIG_PHYS_ADDR_T_64BIT 123 if (priv->hw_params->flags & GENET_HAS_40BITS) 124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32; 125 #endif 126 return addr; 127 } 128 129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 130 131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 132 NETIF_MSG_LINK) 133 134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 135 { 136 if (GENET_IS_V1(priv)) 137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 138 else 139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 140 } 141 142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 143 { 144 if (GENET_IS_V1(priv)) 145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 146 else 147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 148 } 149 150 /* These macros are defined to deal with register map change 151 * between GENET1.1 and GENET2. Only those currently being used 152 * by driver are defined. 153 */ 154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 155 { 156 if (GENET_IS_V1(priv)) 157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 158 else 159 return __raw_readl(priv->base + 160 priv->hw_params->tbuf_offset + TBUF_CTRL); 161 } 162 163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 164 { 165 if (GENET_IS_V1(priv)) 166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 167 else 168 __raw_writel(val, priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 173 { 174 if (GENET_IS_V1(priv)) 175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 176 else 177 return __raw_readl(priv->base + 178 priv->hw_params->tbuf_offset + TBUF_BP_MC); 179 } 180 181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 182 { 183 if (GENET_IS_V1(priv)) 184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 185 else 186 __raw_writel(val, priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 /* RX/TX DMA register accessors */ 191 enum dma_reg { 192 DMA_RING_CFG = 0, 193 DMA_CTRL, 194 DMA_STATUS, 195 DMA_SCB_BURST_SIZE, 196 DMA_ARB_CTRL, 197 DMA_PRIORITY_0, 198 DMA_PRIORITY_1, 199 DMA_PRIORITY_2, 200 DMA_INDEX2RING_0, 201 DMA_INDEX2RING_1, 202 DMA_INDEX2RING_2, 203 DMA_INDEX2RING_3, 204 DMA_INDEX2RING_4, 205 DMA_INDEX2RING_5, 206 DMA_INDEX2RING_6, 207 DMA_INDEX2RING_7, 208 DMA_RING0_TIMEOUT, 209 DMA_RING1_TIMEOUT, 210 DMA_RING2_TIMEOUT, 211 DMA_RING3_TIMEOUT, 212 DMA_RING4_TIMEOUT, 213 DMA_RING5_TIMEOUT, 214 DMA_RING6_TIMEOUT, 215 DMA_RING7_TIMEOUT, 216 DMA_RING8_TIMEOUT, 217 DMA_RING9_TIMEOUT, 218 DMA_RING10_TIMEOUT, 219 DMA_RING11_TIMEOUT, 220 DMA_RING12_TIMEOUT, 221 DMA_RING13_TIMEOUT, 222 DMA_RING14_TIMEOUT, 223 DMA_RING15_TIMEOUT, 224 DMA_RING16_TIMEOUT, 225 }; 226 227 static const u8 bcmgenet_dma_regs_v3plus[] = { 228 [DMA_RING_CFG] = 0x00, 229 [DMA_CTRL] = 0x04, 230 [DMA_STATUS] = 0x08, 231 [DMA_SCB_BURST_SIZE] = 0x0C, 232 [DMA_ARB_CTRL] = 0x2C, 233 [DMA_PRIORITY_0] = 0x30, 234 [DMA_PRIORITY_1] = 0x34, 235 [DMA_PRIORITY_2] = 0x38, 236 [DMA_RING0_TIMEOUT] = 0x2C, 237 [DMA_RING1_TIMEOUT] = 0x30, 238 [DMA_RING2_TIMEOUT] = 0x34, 239 [DMA_RING3_TIMEOUT] = 0x38, 240 [DMA_RING4_TIMEOUT] = 0x3c, 241 [DMA_RING5_TIMEOUT] = 0x40, 242 [DMA_RING6_TIMEOUT] = 0x44, 243 [DMA_RING7_TIMEOUT] = 0x48, 244 [DMA_RING8_TIMEOUT] = 0x4c, 245 [DMA_RING9_TIMEOUT] = 0x50, 246 [DMA_RING10_TIMEOUT] = 0x54, 247 [DMA_RING11_TIMEOUT] = 0x58, 248 [DMA_RING12_TIMEOUT] = 0x5c, 249 [DMA_RING13_TIMEOUT] = 0x60, 250 [DMA_RING14_TIMEOUT] = 0x64, 251 [DMA_RING15_TIMEOUT] = 0x68, 252 [DMA_RING16_TIMEOUT] = 0x6C, 253 [DMA_INDEX2RING_0] = 0x70, 254 [DMA_INDEX2RING_1] = 0x74, 255 [DMA_INDEX2RING_2] = 0x78, 256 [DMA_INDEX2RING_3] = 0x7C, 257 [DMA_INDEX2RING_4] = 0x80, 258 [DMA_INDEX2RING_5] = 0x84, 259 [DMA_INDEX2RING_6] = 0x88, 260 [DMA_INDEX2RING_7] = 0x8C, 261 }; 262 263 static const u8 bcmgenet_dma_regs_v2[] = { 264 [DMA_RING_CFG] = 0x00, 265 [DMA_CTRL] = 0x04, 266 [DMA_STATUS] = 0x08, 267 [DMA_SCB_BURST_SIZE] = 0x0C, 268 [DMA_ARB_CTRL] = 0x30, 269 [DMA_PRIORITY_0] = 0x34, 270 [DMA_PRIORITY_1] = 0x38, 271 [DMA_PRIORITY_2] = 0x3C, 272 [DMA_RING0_TIMEOUT] = 0x2C, 273 [DMA_RING1_TIMEOUT] = 0x30, 274 [DMA_RING2_TIMEOUT] = 0x34, 275 [DMA_RING3_TIMEOUT] = 0x38, 276 [DMA_RING4_TIMEOUT] = 0x3c, 277 [DMA_RING5_TIMEOUT] = 0x40, 278 [DMA_RING6_TIMEOUT] = 0x44, 279 [DMA_RING7_TIMEOUT] = 0x48, 280 [DMA_RING8_TIMEOUT] = 0x4c, 281 [DMA_RING9_TIMEOUT] = 0x50, 282 [DMA_RING10_TIMEOUT] = 0x54, 283 [DMA_RING11_TIMEOUT] = 0x58, 284 [DMA_RING12_TIMEOUT] = 0x5c, 285 [DMA_RING13_TIMEOUT] = 0x60, 286 [DMA_RING14_TIMEOUT] = 0x64, 287 [DMA_RING15_TIMEOUT] = 0x68, 288 [DMA_RING16_TIMEOUT] = 0x6C, 289 }; 290 291 static const u8 bcmgenet_dma_regs_v1[] = { 292 [DMA_CTRL] = 0x00, 293 [DMA_STATUS] = 0x04, 294 [DMA_SCB_BURST_SIZE] = 0x0C, 295 [DMA_ARB_CTRL] = 0x30, 296 [DMA_PRIORITY_0] = 0x34, 297 [DMA_PRIORITY_1] = 0x38, 298 [DMA_PRIORITY_2] = 0x3C, 299 [DMA_RING0_TIMEOUT] = 0x2C, 300 [DMA_RING1_TIMEOUT] = 0x30, 301 [DMA_RING2_TIMEOUT] = 0x34, 302 [DMA_RING3_TIMEOUT] = 0x38, 303 [DMA_RING4_TIMEOUT] = 0x3c, 304 [DMA_RING5_TIMEOUT] = 0x40, 305 [DMA_RING6_TIMEOUT] = 0x44, 306 [DMA_RING7_TIMEOUT] = 0x48, 307 [DMA_RING8_TIMEOUT] = 0x4c, 308 [DMA_RING9_TIMEOUT] = 0x50, 309 [DMA_RING10_TIMEOUT] = 0x54, 310 [DMA_RING11_TIMEOUT] = 0x58, 311 [DMA_RING12_TIMEOUT] = 0x5c, 312 [DMA_RING13_TIMEOUT] = 0x60, 313 [DMA_RING14_TIMEOUT] = 0x64, 314 [DMA_RING15_TIMEOUT] = 0x68, 315 [DMA_RING16_TIMEOUT] = 0x6C, 316 }; 317 318 /* Set at runtime once bcmgenet version is known */ 319 static const u8 *bcmgenet_dma_regs; 320 321 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 322 { 323 return netdev_priv(dev_get_drvdata(dev)); 324 } 325 326 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 327 enum dma_reg r) 328 { 329 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 330 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 331 } 332 333 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 334 u32 val, enum dma_reg r) 335 { 336 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 337 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 338 } 339 340 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 341 enum dma_reg r) 342 { 343 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 344 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 345 } 346 347 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 348 u32 val, enum dma_reg r) 349 { 350 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 351 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 352 } 353 354 /* RDMA/TDMA ring registers and accessors 355 * we merge the common fields and just prefix with T/D the registers 356 * having different meaning depending on the direction 357 */ 358 enum dma_ring_reg { 359 TDMA_READ_PTR = 0, 360 RDMA_WRITE_PTR = TDMA_READ_PTR, 361 TDMA_READ_PTR_HI, 362 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 363 TDMA_CONS_INDEX, 364 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 365 TDMA_PROD_INDEX, 366 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 367 DMA_RING_BUF_SIZE, 368 DMA_START_ADDR, 369 DMA_START_ADDR_HI, 370 DMA_END_ADDR, 371 DMA_END_ADDR_HI, 372 DMA_MBUF_DONE_THRESH, 373 TDMA_FLOW_PERIOD, 374 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 375 TDMA_WRITE_PTR, 376 RDMA_READ_PTR = TDMA_WRITE_PTR, 377 TDMA_WRITE_PTR_HI, 378 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 379 }; 380 381 /* GENET v4 supports 40-bits pointer addressing 382 * for obvious reasons the LO and HI word parts 383 * are contiguous, but this offsets the other 384 * registers. 385 */ 386 static const u8 genet_dma_ring_regs_v4[] = { 387 [TDMA_READ_PTR] = 0x00, 388 [TDMA_READ_PTR_HI] = 0x04, 389 [TDMA_CONS_INDEX] = 0x08, 390 [TDMA_PROD_INDEX] = 0x0C, 391 [DMA_RING_BUF_SIZE] = 0x10, 392 [DMA_START_ADDR] = 0x14, 393 [DMA_START_ADDR_HI] = 0x18, 394 [DMA_END_ADDR] = 0x1C, 395 [DMA_END_ADDR_HI] = 0x20, 396 [DMA_MBUF_DONE_THRESH] = 0x24, 397 [TDMA_FLOW_PERIOD] = 0x28, 398 [TDMA_WRITE_PTR] = 0x2C, 399 [TDMA_WRITE_PTR_HI] = 0x30, 400 }; 401 402 static const u8 genet_dma_ring_regs_v123[] = { 403 [TDMA_READ_PTR] = 0x00, 404 [TDMA_CONS_INDEX] = 0x04, 405 [TDMA_PROD_INDEX] = 0x08, 406 [DMA_RING_BUF_SIZE] = 0x0C, 407 [DMA_START_ADDR] = 0x10, 408 [DMA_END_ADDR] = 0x14, 409 [DMA_MBUF_DONE_THRESH] = 0x18, 410 [TDMA_FLOW_PERIOD] = 0x1C, 411 [TDMA_WRITE_PTR] = 0x20, 412 }; 413 414 /* Set at runtime once GENET version is known */ 415 static const u8 *genet_dma_ring_regs; 416 417 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 418 unsigned int ring, 419 enum dma_ring_reg r) 420 { 421 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 422 (DMA_RING_SIZE * ring) + 423 genet_dma_ring_regs[r]); 424 } 425 426 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 427 unsigned int ring, u32 val, 428 enum dma_ring_reg r) 429 { 430 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433 } 434 435 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 436 unsigned int ring, 437 enum dma_ring_reg r) 438 { 439 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442 } 443 444 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 445 unsigned int ring, u32 val, 446 enum dma_ring_reg r) 447 { 448 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451 } 452 453 static int bcmgenet_begin(struct net_device *dev) 454 { 455 struct bcmgenet_priv *priv = netdev_priv(dev); 456 457 /* Turn on the clock */ 458 return clk_prepare_enable(priv->clk); 459 } 460 461 static void bcmgenet_complete(struct net_device *dev) 462 { 463 struct bcmgenet_priv *priv = netdev_priv(dev); 464 465 /* Turn off the clock */ 466 clk_disable_unprepare(priv->clk); 467 } 468 469 static int bcmgenet_get_link_ksettings(struct net_device *dev, 470 struct ethtool_link_ksettings *cmd) 471 { 472 struct bcmgenet_priv *priv = netdev_priv(dev); 473 474 if (!netif_running(dev)) 475 return -EINVAL; 476 477 if (!priv->phydev) 478 return -ENODEV; 479 480 return phy_ethtool_ksettings_get(priv->phydev, cmd); 481 } 482 483 static int bcmgenet_set_link_ksettings(struct net_device *dev, 484 const struct ethtool_link_ksettings *cmd) 485 { 486 struct bcmgenet_priv *priv = netdev_priv(dev); 487 488 if (!netif_running(dev)) 489 return -EINVAL; 490 491 if (!priv->phydev) 492 return -ENODEV; 493 494 return phy_ethtool_ksettings_set(priv->phydev, cmd); 495 } 496 497 static int bcmgenet_set_rx_csum(struct net_device *dev, 498 netdev_features_t wanted) 499 { 500 struct bcmgenet_priv *priv = netdev_priv(dev); 501 u32 rbuf_chk_ctrl; 502 bool rx_csum_en; 503 504 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 505 506 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 507 508 /* enable rx checksumming */ 509 if (rx_csum_en) 510 rbuf_chk_ctrl |= RBUF_RXCHK_EN; 511 else 512 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 513 priv->desc_rxchk_en = rx_csum_en; 514 515 /* If UniMAC forwards CRC, we need to skip over it to get 516 * a valid CHK bit to be set in the per-packet status word 517 */ 518 if (rx_csum_en && priv->crc_fwd_en) 519 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 520 else 521 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 522 523 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 524 525 return 0; 526 } 527 528 static int bcmgenet_set_tx_csum(struct net_device *dev, 529 netdev_features_t wanted) 530 { 531 struct bcmgenet_priv *priv = netdev_priv(dev); 532 bool desc_64b_en; 533 u32 tbuf_ctrl, rbuf_ctrl; 534 535 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 536 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 537 538 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 539 540 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 541 if (desc_64b_en) { 542 tbuf_ctrl |= RBUF_64B_EN; 543 rbuf_ctrl |= RBUF_64B_EN; 544 } else { 545 tbuf_ctrl &= ~RBUF_64B_EN; 546 rbuf_ctrl &= ~RBUF_64B_EN; 547 } 548 priv->desc_64b_en = desc_64b_en; 549 550 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 551 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 552 553 return 0; 554 } 555 556 static int bcmgenet_set_features(struct net_device *dev, 557 netdev_features_t features) 558 { 559 netdev_features_t changed = features ^ dev->features; 560 netdev_features_t wanted = dev->wanted_features; 561 int ret = 0; 562 563 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 564 ret = bcmgenet_set_tx_csum(dev, wanted); 565 if (changed & (NETIF_F_RXCSUM)) 566 ret = bcmgenet_set_rx_csum(dev, wanted); 567 568 return ret; 569 } 570 571 static u32 bcmgenet_get_msglevel(struct net_device *dev) 572 { 573 struct bcmgenet_priv *priv = netdev_priv(dev); 574 575 return priv->msg_enable; 576 } 577 578 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 579 { 580 struct bcmgenet_priv *priv = netdev_priv(dev); 581 582 priv->msg_enable = level; 583 } 584 585 static int bcmgenet_get_coalesce(struct net_device *dev, 586 struct ethtool_coalesce *ec) 587 { 588 struct bcmgenet_priv *priv = netdev_priv(dev); 589 590 ec->tx_max_coalesced_frames = 591 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 592 DMA_MBUF_DONE_THRESH); 593 ec->rx_max_coalesced_frames = 594 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 595 DMA_MBUF_DONE_THRESH); 596 ec->rx_coalesce_usecs = 597 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 598 599 return 0; 600 } 601 602 static int bcmgenet_set_coalesce(struct net_device *dev, 603 struct ethtool_coalesce *ec) 604 { 605 struct bcmgenet_priv *priv = netdev_priv(dev); 606 unsigned int i; 607 u32 reg; 608 609 /* Base system clock is 125Mhz, DMA timeout is this reference clock 610 * divided by 1024, which yields roughly 8.192us, our maximum value 611 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 612 */ 613 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 614 ec->tx_max_coalesced_frames == 0 || 615 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 616 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 617 return -EINVAL; 618 619 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 620 return -EINVAL; 621 622 /* GENET TDMA hardware does not support a configurable timeout, but will 623 * always generate an interrupt either after MBDONE packets have been 624 * transmitted, or when the ring is empty. 625 */ 626 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high || 627 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low) 628 return -EOPNOTSUPP; 629 630 /* Program all TX queues with the same values, as there is no 631 * ethtool knob to do coalescing on a per-queue basis 632 */ 633 for (i = 0; i < priv->hw_params->tx_queues; i++) 634 bcmgenet_tdma_ring_writel(priv, i, 635 ec->tx_max_coalesced_frames, 636 DMA_MBUF_DONE_THRESH); 637 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 638 ec->tx_max_coalesced_frames, 639 DMA_MBUF_DONE_THRESH); 640 641 for (i = 0; i < priv->hw_params->rx_queues; i++) { 642 bcmgenet_rdma_ring_writel(priv, i, 643 ec->rx_max_coalesced_frames, 644 DMA_MBUF_DONE_THRESH); 645 646 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 647 reg &= ~DMA_TIMEOUT_MASK; 648 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); 649 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 650 } 651 652 bcmgenet_rdma_ring_writel(priv, DESC_INDEX, 653 ec->rx_max_coalesced_frames, 654 DMA_MBUF_DONE_THRESH); 655 656 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT); 657 reg &= ~DMA_TIMEOUT_MASK; 658 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); 659 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT); 660 661 return 0; 662 } 663 664 /* standard ethtool support functions. */ 665 enum bcmgenet_stat_type { 666 BCMGENET_STAT_NETDEV = -1, 667 BCMGENET_STAT_MIB_RX, 668 BCMGENET_STAT_MIB_TX, 669 BCMGENET_STAT_RUNT, 670 BCMGENET_STAT_MISC, 671 BCMGENET_STAT_SOFT, 672 }; 673 674 struct bcmgenet_stats { 675 char stat_string[ETH_GSTRING_LEN]; 676 int stat_sizeof; 677 int stat_offset; 678 enum bcmgenet_stat_type type; 679 /* reg offset from UMAC base for misc counters */ 680 u16 reg_offset; 681 }; 682 683 #define STAT_NETDEV(m) { \ 684 .stat_string = __stringify(m), \ 685 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 686 .stat_offset = offsetof(struct net_device_stats, m), \ 687 .type = BCMGENET_STAT_NETDEV, \ 688 } 689 690 #define STAT_GENET_MIB(str, m, _type) { \ 691 .stat_string = str, \ 692 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 693 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 694 .type = _type, \ 695 } 696 697 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 698 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 699 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 700 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 701 702 #define STAT_GENET_MISC(str, m, offset) { \ 703 .stat_string = str, \ 704 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 705 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 706 .type = BCMGENET_STAT_MISC, \ 707 .reg_offset = offset, \ 708 } 709 710 #define STAT_GENET_Q(num) \ 711 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 712 tx_rings[num].packets), \ 713 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 714 tx_rings[num].bytes), \ 715 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 716 rx_rings[num].bytes), \ 717 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 718 rx_rings[num].packets), \ 719 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 720 rx_rings[num].errors), \ 721 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 722 rx_rings[num].dropped) 723 724 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 725 * between the end of TX stats and the beginning of the RX RUNT 726 */ 727 #define BCMGENET_STAT_OFFSET 0xc 728 729 /* Hardware counters must be kept in sync because the order/offset 730 * is important here (order in structure declaration = order in hardware) 731 */ 732 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 733 /* general stats */ 734 STAT_NETDEV(rx_packets), 735 STAT_NETDEV(tx_packets), 736 STAT_NETDEV(rx_bytes), 737 STAT_NETDEV(tx_bytes), 738 STAT_NETDEV(rx_errors), 739 STAT_NETDEV(tx_errors), 740 STAT_NETDEV(rx_dropped), 741 STAT_NETDEV(tx_dropped), 742 STAT_NETDEV(multicast), 743 /* UniMAC RSV counters */ 744 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 745 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 746 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 747 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 748 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 749 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 750 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 751 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 752 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 753 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 754 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 755 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 756 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 757 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 758 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 759 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 760 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 761 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 762 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 763 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 764 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 765 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 766 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 767 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 768 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 769 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 770 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 771 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 772 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 773 /* UniMAC TSV counters */ 774 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 775 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 776 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 777 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 778 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 779 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 780 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 781 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 782 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 783 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 784 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 785 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 786 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 787 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 788 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 789 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 790 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 791 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 792 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 793 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 794 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 795 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 796 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 797 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 798 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 799 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 800 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 801 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 802 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 803 /* UniMAC RUNT counters */ 804 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 805 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 806 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 807 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 808 /* Misc UniMAC counters */ 809 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 810 UMAC_RBUF_OVFL_CNT_V1), 811 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 812 UMAC_RBUF_ERR_CNT_V1), 813 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 814 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 815 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 816 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 817 /* Per TX queues */ 818 STAT_GENET_Q(0), 819 STAT_GENET_Q(1), 820 STAT_GENET_Q(2), 821 STAT_GENET_Q(3), 822 STAT_GENET_Q(16), 823 }; 824 825 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 826 827 static void bcmgenet_get_drvinfo(struct net_device *dev, 828 struct ethtool_drvinfo *info) 829 { 830 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 831 strlcpy(info->version, "v2.0", sizeof(info->version)); 832 } 833 834 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 835 { 836 switch (string_set) { 837 case ETH_SS_STATS: 838 return BCMGENET_STATS_LEN; 839 default: 840 return -EOPNOTSUPP; 841 } 842 } 843 844 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 845 u8 *data) 846 { 847 int i; 848 849 switch (stringset) { 850 case ETH_SS_STATS: 851 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 852 memcpy(data + i * ETH_GSTRING_LEN, 853 bcmgenet_gstrings_stats[i].stat_string, 854 ETH_GSTRING_LEN); 855 } 856 break; 857 } 858 } 859 860 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 861 { 862 u16 new_offset; 863 u32 val; 864 865 switch (offset) { 866 case UMAC_RBUF_OVFL_CNT_V1: 867 if (GENET_IS_V2(priv)) 868 new_offset = RBUF_OVFL_CNT_V2; 869 else 870 new_offset = RBUF_OVFL_CNT_V3PLUS; 871 872 val = bcmgenet_rbuf_readl(priv, new_offset); 873 /* clear if overflowed */ 874 if (val == ~0) 875 bcmgenet_rbuf_writel(priv, 0, new_offset); 876 break; 877 case UMAC_RBUF_ERR_CNT_V1: 878 if (GENET_IS_V2(priv)) 879 new_offset = RBUF_ERR_CNT_V2; 880 else 881 new_offset = RBUF_ERR_CNT_V3PLUS; 882 883 val = bcmgenet_rbuf_readl(priv, new_offset); 884 /* clear if overflowed */ 885 if (val == ~0) 886 bcmgenet_rbuf_writel(priv, 0, new_offset); 887 break; 888 default: 889 val = bcmgenet_umac_readl(priv, offset); 890 /* clear if overflowed */ 891 if (val == ~0) 892 bcmgenet_umac_writel(priv, 0, offset); 893 break; 894 } 895 896 return val; 897 } 898 899 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 900 { 901 int i, j = 0; 902 903 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 904 const struct bcmgenet_stats *s; 905 u8 offset = 0; 906 u32 val = 0; 907 char *p; 908 909 s = &bcmgenet_gstrings_stats[i]; 910 switch (s->type) { 911 case BCMGENET_STAT_NETDEV: 912 case BCMGENET_STAT_SOFT: 913 continue; 914 case BCMGENET_STAT_RUNT: 915 offset += BCMGENET_STAT_OFFSET; 916 /* fall through */ 917 case BCMGENET_STAT_MIB_TX: 918 offset += BCMGENET_STAT_OFFSET; 919 /* fall through */ 920 case BCMGENET_STAT_MIB_RX: 921 val = bcmgenet_umac_readl(priv, 922 UMAC_MIB_START + j + offset); 923 offset = 0; /* Reset Offset */ 924 break; 925 case BCMGENET_STAT_MISC: 926 if (GENET_IS_V1(priv)) { 927 val = bcmgenet_umac_readl(priv, s->reg_offset); 928 /* clear if overflowed */ 929 if (val == ~0) 930 bcmgenet_umac_writel(priv, 0, 931 s->reg_offset); 932 } else { 933 val = bcmgenet_update_stat_misc(priv, 934 s->reg_offset); 935 } 936 break; 937 } 938 939 j += s->stat_sizeof; 940 p = (char *)priv + s->stat_offset; 941 *(u32 *)p = val; 942 } 943 } 944 945 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 946 struct ethtool_stats *stats, 947 u64 *data) 948 { 949 struct bcmgenet_priv *priv = netdev_priv(dev); 950 int i; 951 952 if (netif_running(dev)) 953 bcmgenet_update_mib_counters(priv); 954 955 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 956 const struct bcmgenet_stats *s; 957 char *p; 958 959 s = &bcmgenet_gstrings_stats[i]; 960 if (s->type == BCMGENET_STAT_NETDEV) 961 p = (char *)&dev->stats; 962 else 963 p = (char *)priv; 964 p += s->stat_offset; 965 if (sizeof(unsigned long) != sizeof(u32) && 966 s->stat_sizeof == sizeof(unsigned long)) 967 data[i] = *(unsigned long *)p; 968 else 969 data[i] = *(u32 *)p; 970 } 971 } 972 973 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 974 { 975 struct bcmgenet_priv *priv = netdev_priv(dev); 976 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 977 u32 reg; 978 979 if (enable && !priv->clk_eee_enabled) { 980 clk_prepare_enable(priv->clk_eee); 981 priv->clk_eee_enabled = true; 982 } 983 984 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 985 if (enable) 986 reg |= EEE_EN; 987 else 988 reg &= ~EEE_EN; 989 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 990 991 /* Enable EEE and switch to a 27Mhz clock automatically */ 992 reg = __raw_readl(priv->base + off); 993 if (enable) 994 reg |= TBUF_EEE_EN | TBUF_PM_EN; 995 else 996 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 997 __raw_writel(reg, priv->base + off); 998 999 /* Do the same for thing for RBUF */ 1000 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1001 if (enable) 1002 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1003 else 1004 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1005 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1006 1007 if (!enable && priv->clk_eee_enabled) { 1008 clk_disable_unprepare(priv->clk_eee); 1009 priv->clk_eee_enabled = false; 1010 } 1011 1012 priv->eee.eee_enabled = enable; 1013 priv->eee.eee_active = enable; 1014 } 1015 1016 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1017 { 1018 struct bcmgenet_priv *priv = netdev_priv(dev); 1019 struct ethtool_eee *p = &priv->eee; 1020 1021 if (GENET_IS_V1(priv)) 1022 return -EOPNOTSUPP; 1023 1024 e->eee_enabled = p->eee_enabled; 1025 e->eee_active = p->eee_active; 1026 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1027 1028 return phy_ethtool_get_eee(priv->phydev, e); 1029 } 1030 1031 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1032 { 1033 struct bcmgenet_priv *priv = netdev_priv(dev); 1034 struct ethtool_eee *p = &priv->eee; 1035 int ret = 0; 1036 1037 if (GENET_IS_V1(priv)) 1038 return -EOPNOTSUPP; 1039 1040 p->eee_enabled = e->eee_enabled; 1041 1042 if (!p->eee_enabled) { 1043 bcmgenet_eee_enable_set(dev, false); 1044 } else { 1045 ret = phy_init_eee(priv->phydev, 0); 1046 if (ret) { 1047 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1048 return ret; 1049 } 1050 1051 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1052 bcmgenet_eee_enable_set(dev, true); 1053 } 1054 1055 return phy_ethtool_set_eee(priv->phydev, e); 1056 } 1057 1058 /* standard ethtool support functions. */ 1059 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1060 .begin = bcmgenet_begin, 1061 .complete = bcmgenet_complete, 1062 .get_strings = bcmgenet_get_strings, 1063 .get_sset_count = bcmgenet_get_sset_count, 1064 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1065 .get_drvinfo = bcmgenet_get_drvinfo, 1066 .get_link = ethtool_op_get_link, 1067 .get_msglevel = bcmgenet_get_msglevel, 1068 .set_msglevel = bcmgenet_set_msglevel, 1069 .get_wol = bcmgenet_get_wol, 1070 .set_wol = bcmgenet_set_wol, 1071 .get_eee = bcmgenet_get_eee, 1072 .set_eee = bcmgenet_set_eee, 1073 .nway_reset = phy_ethtool_nway_reset, 1074 .get_coalesce = bcmgenet_get_coalesce, 1075 .set_coalesce = bcmgenet_set_coalesce, 1076 .get_link_ksettings = bcmgenet_get_link_ksettings, 1077 .set_link_ksettings = bcmgenet_set_link_ksettings, 1078 }; 1079 1080 /* Power down the unimac, based on mode. */ 1081 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1082 enum bcmgenet_power_mode mode) 1083 { 1084 int ret = 0; 1085 u32 reg; 1086 1087 switch (mode) { 1088 case GENET_POWER_CABLE_SENSE: 1089 phy_detach(priv->phydev); 1090 break; 1091 1092 case GENET_POWER_WOL_MAGIC: 1093 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1094 break; 1095 1096 case GENET_POWER_PASSIVE: 1097 /* Power down LED */ 1098 if (priv->hw_params->flags & GENET_HAS_EXT) { 1099 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1100 if (GENET_IS_V5(priv)) 1101 reg |= EXT_PWR_DOWN_PHY_EN | 1102 EXT_PWR_DOWN_PHY_RD | 1103 EXT_PWR_DOWN_PHY_SD | 1104 EXT_PWR_DOWN_PHY_RX | 1105 EXT_PWR_DOWN_PHY_TX | 1106 EXT_IDDQ_GLBL_PWR; 1107 else 1108 reg |= EXT_PWR_DOWN_PHY; 1109 1110 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1111 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1112 1113 bcmgenet_phy_power_set(priv->dev, false); 1114 } 1115 break; 1116 default: 1117 break; 1118 } 1119 1120 return 0; 1121 } 1122 1123 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1124 enum bcmgenet_power_mode mode) 1125 { 1126 u32 reg; 1127 1128 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1129 return; 1130 1131 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1132 1133 switch (mode) { 1134 case GENET_POWER_PASSIVE: 1135 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1136 if (GENET_IS_V5(priv)) { 1137 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1138 EXT_PWR_DOWN_PHY_RD | 1139 EXT_PWR_DOWN_PHY_SD | 1140 EXT_PWR_DOWN_PHY_RX | 1141 EXT_PWR_DOWN_PHY_TX | 1142 EXT_IDDQ_GLBL_PWR); 1143 reg |= EXT_PHY_RESET; 1144 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1145 mdelay(1); 1146 1147 reg &= ~EXT_PHY_RESET; 1148 } else { 1149 reg &= ~EXT_PWR_DOWN_PHY; 1150 reg |= EXT_PWR_DN_EN_LD; 1151 } 1152 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1153 bcmgenet_phy_power_set(priv->dev, true); 1154 bcmgenet_mii_reset(priv->dev); 1155 break; 1156 1157 case GENET_POWER_CABLE_SENSE: 1158 /* enable APD */ 1159 if (!GENET_IS_V5(priv)) { 1160 reg |= EXT_PWR_DN_EN_LD; 1161 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1162 } 1163 break; 1164 case GENET_POWER_WOL_MAGIC: 1165 bcmgenet_wol_power_up_cfg(priv, mode); 1166 return; 1167 default: 1168 break; 1169 } 1170 } 1171 1172 /* ioctl handle special commands that are not present in ethtool. */ 1173 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1174 { 1175 struct bcmgenet_priv *priv = netdev_priv(dev); 1176 1177 if (!netif_running(dev)) 1178 return -EINVAL; 1179 1180 if (!priv->phydev) 1181 return -ENODEV; 1182 1183 return phy_mii_ioctl(priv->phydev, rq, cmd); 1184 } 1185 1186 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1187 struct bcmgenet_tx_ring *ring) 1188 { 1189 struct enet_cb *tx_cb_ptr; 1190 1191 tx_cb_ptr = ring->cbs; 1192 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1193 1194 /* Advancing local write pointer */ 1195 if (ring->write_ptr == ring->end_ptr) 1196 ring->write_ptr = ring->cb_ptr; 1197 else 1198 ring->write_ptr++; 1199 1200 return tx_cb_ptr; 1201 } 1202 1203 /* Simple helper to free a control block's resources */ 1204 static void bcmgenet_free_cb(struct enet_cb *cb) 1205 { 1206 dev_kfree_skb_any(cb->skb); 1207 cb->skb = NULL; 1208 dma_unmap_addr_set(cb, dma_addr, 0); 1209 } 1210 1211 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1212 { 1213 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1214 INTRL2_CPU_MASK_SET); 1215 } 1216 1217 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1218 { 1219 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1220 INTRL2_CPU_MASK_CLEAR); 1221 } 1222 1223 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1224 { 1225 bcmgenet_intrl2_1_writel(ring->priv, 1226 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1227 INTRL2_CPU_MASK_SET); 1228 } 1229 1230 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1231 { 1232 bcmgenet_intrl2_1_writel(ring->priv, 1233 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1234 INTRL2_CPU_MASK_CLEAR); 1235 } 1236 1237 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1238 { 1239 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1240 INTRL2_CPU_MASK_SET); 1241 } 1242 1243 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1244 { 1245 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1246 INTRL2_CPU_MASK_CLEAR); 1247 } 1248 1249 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1250 { 1251 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1252 INTRL2_CPU_MASK_CLEAR); 1253 } 1254 1255 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1256 { 1257 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1258 INTRL2_CPU_MASK_SET); 1259 } 1260 1261 /* Unlocked version of the reclaim routine */ 1262 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1263 struct bcmgenet_tx_ring *ring) 1264 { 1265 struct bcmgenet_priv *priv = netdev_priv(dev); 1266 struct device *kdev = &priv->pdev->dev; 1267 struct enet_cb *tx_cb_ptr; 1268 unsigned int pkts_compl = 0; 1269 unsigned int bytes_compl = 0; 1270 unsigned int c_index; 1271 unsigned int txbds_ready; 1272 unsigned int txbds_processed = 0; 1273 1274 /* Clear status before servicing to reduce spurious interrupts */ 1275 if (ring->index == DESC_INDEX) 1276 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1277 INTRL2_CPU_CLEAR); 1278 else 1279 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1280 INTRL2_CPU_CLEAR); 1281 1282 /* Compute how many buffers are transmitted since last xmit call */ 1283 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1284 & DMA_C_INDEX_MASK; 1285 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1286 1287 netif_dbg(priv, tx_done, dev, 1288 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1289 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1290 1291 /* Reclaim transmitted buffers */ 1292 while (txbds_processed < txbds_ready) { 1293 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr]; 1294 if (tx_cb_ptr->skb) { 1295 pkts_compl++; 1296 bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent; 1297 dma_unmap_single(kdev, 1298 dma_unmap_addr(tx_cb_ptr, dma_addr), 1299 dma_unmap_len(tx_cb_ptr, dma_len), 1300 DMA_TO_DEVICE); 1301 bcmgenet_free_cb(tx_cb_ptr); 1302 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) { 1303 dma_unmap_page(kdev, 1304 dma_unmap_addr(tx_cb_ptr, dma_addr), 1305 dma_unmap_len(tx_cb_ptr, dma_len), 1306 DMA_TO_DEVICE); 1307 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0); 1308 } 1309 1310 txbds_processed++; 1311 if (likely(ring->clean_ptr < ring->end_ptr)) 1312 ring->clean_ptr++; 1313 else 1314 ring->clean_ptr = ring->cb_ptr; 1315 } 1316 1317 ring->free_bds += txbds_processed; 1318 ring->c_index = c_index; 1319 1320 ring->packets += pkts_compl; 1321 ring->bytes += bytes_compl; 1322 1323 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1324 pkts_compl, bytes_compl); 1325 1326 return txbds_processed; 1327 } 1328 1329 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1330 struct bcmgenet_tx_ring *ring) 1331 { 1332 unsigned int released; 1333 unsigned long flags; 1334 1335 spin_lock_irqsave(&ring->lock, flags); 1336 released = __bcmgenet_tx_reclaim(dev, ring); 1337 spin_unlock_irqrestore(&ring->lock, flags); 1338 1339 return released; 1340 } 1341 1342 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1343 { 1344 struct bcmgenet_tx_ring *ring = 1345 container_of(napi, struct bcmgenet_tx_ring, napi); 1346 unsigned int work_done = 0; 1347 struct netdev_queue *txq; 1348 unsigned long flags; 1349 1350 spin_lock_irqsave(&ring->lock, flags); 1351 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1352 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1353 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1354 netif_tx_wake_queue(txq); 1355 } 1356 spin_unlock_irqrestore(&ring->lock, flags); 1357 1358 if (work_done == 0) { 1359 napi_complete(napi); 1360 ring->int_enable(ring); 1361 1362 return 0; 1363 } 1364 1365 return budget; 1366 } 1367 1368 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1369 { 1370 struct bcmgenet_priv *priv = netdev_priv(dev); 1371 int i; 1372 1373 if (netif_is_multiqueue(dev)) { 1374 for (i = 0; i < priv->hw_params->tx_queues; i++) 1375 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1376 } 1377 1378 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1379 } 1380 1381 /* Transmits a single SKB (either head of a fragment or a single SKB) 1382 * caller must hold priv->lock 1383 */ 1384 static int bcmgenet_xmit_single(struct net_device *dev, 1385 struct sk_buff *skb, 1386 u16 dma_desc_flags, 1387 struct bcmgenet_tx_ring *ring) 1388 { 1389 struct bcmgenet_priv *priv = netdev_priv(dev); 1390 struct device *kdev = &priv->pdev->dev; 1391 struct enet_cb *tx_cb_ptr; 1392 unsigned int skb_len; 1393 dma_addr_t mapping; 1394 u32 length_status; 1395 int ret; 1396 1397 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1398 1399 if (unlikely(!tx_cb_ptr)) 1400 BUG(); 1401 1402 tx_cb_ptr->skb = skb; 1403 1404 skb_len = skb_headlen(skb); 1405 1406 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 1407 ret = dma_mapping_error(kdev, mapping); 1408 if (ret) { 1409 priv->mib.tx_dma_failed++; 1410 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1411 dev_kfree_skb(skb); 1412 return ret; 1413 } 1414 1415 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1416 dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len); 1417 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | 1418 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) | 1419 DMA_TX_APPEND_CRC; 1420 1421 if (skb->ip_summed == CHECKSUM_PARTIAL) 1422 length_status |= DMA_TX_DO_CSUM; 1423 1424 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status); 1425 1426 return 0; 1427 } 1428 1429 /* Transmit a SKB fragment */ 1430 static int bcmgenet_xmit_frag(struct net_device *dev, 1431 skb_frag_t *frag, 1432 u16 dma_desc_flags, 1433 struct bcmgenet_tx_ring *ring) 1434 { 1435 struct bcmgenet_priv *priv = netdev_priv(dev); 1436 struct device *kdev = &priv->pdev->dev; 1437 struct enet_cb *tx_cb_ptr; 1438 unsigned int frag_size; 1439 dma_addr_t mapping; 1440 int ret; 1441 1442 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1443 1444 if (unlikely(!tx_cb_ptr)) 1445 BUG(); 1446 1447 tx_cb_ptr->skb = NULL; 1448 1449 frag_size = skb_frag_size(frag); 1450 1451 mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE); 1452 ret = dma_mapping_error(kdev, mapping); 1453 if (ret) { 1454 priv->mib.tx_dma_failed++; 1455 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n", 1456 __func__); 1457 return ret; 1458 } 1459 1460 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1461 dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size); 1462 1463 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, 1464 (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | 1465 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT)); 1466 1467 return 0; 1468 } 1469 1470 /* Reallocate the SKB to put enough headroom in front of it and insert 1471 * the transmit checksum offsets in the descriptors 1472 */ 1473 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1474 struct sk_buff *skb) 1475 { 1476 struct status_64 *status = NULL; 1477 struct sk_buff *new_skb; 1478 u16 offset; 1479 u8 ip_proto; 1480 u16 ip_ver; 1481 u32 tx_csum_info; 1482 1483 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1484 /* If 64 byte status block enabled, must make sure skb has 1485 * enough headroom for us to insert 64B status block. 1486 */ 1487 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1488 dev_kfree_skb(skb); 1489 if (!new_skb) { 1490 dev->stats.tx_dropped++; 1491 return NULL; 1492 } 1493 skb = new_skb; 1494 } 1495 1496 skb_push(skb, sizeof(*status)); 1497 status = (struct status_64 *)skb->data; 1498 1499 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1500 ip_ver = htons(skb->protocol); 1501 switch (ip_ver) { 1502 case ETH_P_IP: 1503 ip_proto = ip_hdr(skb)->protocol; 1504 break; 1505 case ETH_P_IPV6: 1506 ip_proto = ipv6_hdr(skb)->nexthdr; 1507 break; 1508 default: 1509 return skb; 1510 } 1511 1512 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1513 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1514 (offset + skb->csum_offset); 1515 1516 /* Set the length valid bit for TCP and UDP and just set 1517 * the special UDP flag for IPv4, else just set to 0. 1518 */ 1519 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1520 tx_csum_info |= STATUS_TX_CSUM_LV; 1521 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1522 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1523 } else { 1524 tx_csum_info = 0; 1525 } 1526 1527 status->tx_csum_info = tx_csum_info; 1528 } 1529 1530 return skb; 1531 } 1532 1533 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1534 { 1535 struct bcmgenet_priv *priv = netdev_priv(dev); 1536 struct bcmgenet_tx_ring *ring = NULL; 1537 struct netdev_queue *txq; 1538 unsigned long flags = 0; 1539 int nr_frags, index; 1540 u16 dma_desc_flags; 1541 int ret; 1542 int i; 1543 1544 index = skb_get_queue_mapping(skb); 1545 /* Mapping strategy: 1546 * queue_mapping = 0, unclassified, packet xmited through ring16 1547 * queue_mapping = 1, goes to ring 0. (highest priority queue 1548 * queue_mapping = 2, goes to ring 1. 1549 * queue_mapping = 3, goes to ring 2. 1550 * queue_mapping = 4, goes to ring 3. 1551 */ 1552 if (index == 0) 1553 index = DESC_INDEX; 1554 else 1555 index -= 1; 1556 1557 ring = &priv->tx_rings[index]; 1558 txq = netdev_get_tx_queue(dev, ring->queue); 1559 1560 nr_frags = skb_shinfo(skb)->nr_frags; 1561 1562 spin_lock_irqsave(&ring->lock, flags); 1563 if (ring->free_bds <= (nr_frags + 1)) { 1564 if (!netif_tx_queue_stopped(txq)) { 1565 netif_tx_stop_queue(txq); 1566 netdev_err(dev, 1567 "%s: tx ring %d full when queue %d awake\n", 1568 __func__, index, ring->queue); 1569 } 1570 ret = NETDEV_TX_BUSY; 1571 goto out; 1572 } 1573 1574 if (skb_padto(skb, ETH_ZLEN)) { 1575 ret = NETDEV_TX_OK; 1576 goto out; 1577 } 1578 1579 /* Retain how many bytes will be sent on the wire, without TSB inserted 1580 * by transmit checksum offload 1581 */ 1582 GENET_CB(skb)->bytes_sent = skb->len; 1583 1584 /* set the SKB transmit checksum */ 1585 if (priv->desc_64b_en) { 1586 skb = bcmgenet_put_tx_csum(dev, skb); 1587 if (!skb) { 1588 ret = NETDEV_TX_OK; 1589 goto out; 1590 } 1591 } 1592 1593 dma_desc_flags = DMA_SOP; 1594 if (nr_frags == 0) 1595 dma_desc_flags |= DMA_EOP; 1596 1597 /* Transmit single SKB or head of fragment list */ 1598 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring); 1599 if (ret) { 1600 ret = NETDEV_TX_OK; 1601 goto out; 1602 } 1603 1604 /* xmit fragment */ 1605 for (i = 0; i < nr_frags; i++) { 1606 ret = bcmgenet_xmit_frag(dev, 1607 &skb_shinfo(skb)->frags[i], 1608 (i == nr_frags - 1) ? DMA_EOP : 0, 1609 ring); 1610 if (ret) { 1611 ret = NETDEV_TX_OK; 1612 goto out; 1613 } 1614 } 1615 1616 skb_tx_timestamp(skb); 1617 1618 /* Decrement total BD count and advance our write pointer */ 1619 ring->free_bds -= nr_frags + 1; 1620 ring->prod_index += nr_frags + 1; 1621 ring->prod_index &= DMA_P_INDEX_MASK; 1622 1623 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1624 1625 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1626 netif_tx_stop_queue(txq); 1627 1628 if (!skb->xmit_more || netif_xmit_stopped(txq)) 1629 /* Packets are ready, update producer index */ 1630 bcmgenet_tdma_ring_writel(priv, ring->index, 1631 ring->prod_index, TDMA_PROD_INDEX); 1632 out: 1633 spin_unlock_irqrestore(&ring->lock, flags); 1634 1635 return ret; 1636 } 1637 1638 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1639 struct enet_cb *cb) 1640 { 1641 struct device *kdev = &priv->pdev->dev; 1642 struct sk_buff *skb; 1643 struct sk_buff *rx_skb; 1644 dma_addr_t mapping; 1645 1646 /* Allocate a new Rx skb */ 1647 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1648 if (!skb) { 1649 priv->mib.alloc_rx_buff_failed++; 1650 netif_err(priv, rx_err, priv->dev, 1651 "%s: Rx skb allocation failed\n", __func__); 1652 return NULL; 1653 } 1654 1655 /* DMA-map the new Rx skb */ 1656 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1657 DMA_FROM_DEVICE); 1658 if (dma_mapping_error(kdev, mapping)) { 1659 priv->mib.rx_dma_failed++; 1660 dev_kfree_skb_any(skb); 1661 netif_err(priv, rx_err, priv->dev, 1662 "%s: Rx skb DMA mapping failed\n", __func__); 1663 return NULL; 1664 } 1665 1666 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1667 rx_skb = cb->skb; 1668 if (likely(rx_skb)) 1669 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), 1670 priv->rx_buf_len, DMA_FROM_DEVICE); 1671 1672 /* Put the new Rx skb on the ring */ 1673 cb->skb = skb; 1674 dma_unmap_addr_set(cb, dma_addr, mapping); 1675 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1676 1677 /* Return the current Rx skb to caller */ 1678 return rx_skb; 1679 } 1680 1681 /* bcmgenet_desc_rx - descriptor based rx process. 1682 * this could be called from bottom half, or from NAPI polling method. 1683 */ 1684 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1685 unsigned int budget) 1686 { 1687 struct bcmgenet_priv *priv = ring->priv; 1688 struct net_device *dev = priv->dev; 1689 struct enet_cb *cb; 1690 struct sk_buff *skb; 1691 u32 dma_length_status; 1692 unsigned long dma_flag; 1693 int len; 1694 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1695 unsigned int p_index, mask; 1696 unsigned int discards; 1697 unsigned int chksum_ok = 0; 1698 1699 /* Clear status before servicing to reduce spurious interrupts */ 1700 if (ring->index == DESC_INDEX) { 1701 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1702 INTRL2_CPU_CLEAR); 1703 } else { 1704 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1705 bcmgenet_intrl2_1_writel(priv, 1706 mask, 1707 INTRL2_CPU_CLEAR); 1708 } 1709 1710 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1711 1712 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1713 DMA_P_INDEX_DISCARD_CNT_MASK; 1714 if (discards > ring->old_discards) { 1715 discards = discards - ring->old_discards; 1716 ring->errors += discards; 1717 ring->old_discards += discards; 1718 1719 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1720 if (ring->old_discards >= 0xC000) { 1721 ring->old_discards = 0; 1722 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1723 RDMA_PROD_INDEX); 1724 } 1725 } 1726 1727 p_index &= DMA_P_INDEX_MASK; 1728 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1729 1730 netif_dbg(priv, rx_status, dev, 1731 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1732 1733 while ((rxpktprocessed < rxpkttoprocess) && 1734 (rxpktprocessed < budget)) { 1735 cb = &priv->rx_cbs[ring->read_ptr]; 1736 skb = bcmgenet_rx_refill(priv, cb); 1737 1738 if (unlikely(!skb)) { 1739 ring->dropped++; 1740 goto next; 1741 } 1742 1743 if (!priv->desc_64b_en) { 1744 dma_length_status = 1745 dmadesc_get_length_status(priv, cb->bd_addr); 1746 } else { 1747 struct status_64 *status; 1748 1749 status = (struct status_64 *)skb->data; 1750 dma_length_status = status->length_status; 1751 } 1752 1753 /* DMA flags and length are still valid no matter how 1754 * we got the Receive Status Vector (64B RSB or register) 1755 */ 1756 dma_flag = dma_length_status & 0xffff; 1757 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1758 1759 netif_dbg(priv, rx_status, dev, 1760 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1761 __func__, p_index, ring->c_index, 1762 ring->read_ptr, dma_length_status); 1763 1764 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1765 netif_err(priv, rx_status, dev, 1766 "dropping fragmented packet!\n"); 1767 ring->errors++; 1768 dev_kfree_skb_any(skb); 1769 goto next; 1770 } 1771 1772 /* report errors */ 1773 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1774 DMA_RX_OV | 1775 DMA_RX_NO | 1776 DMA_RX_LG | 1777 DMA_RX_RXER))) { 1778 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1779 (unsigned int)dma_flag); 1780 if (dma_flag & DMA_RX_CRC_ERROR) 1781 dev->stats.rx_crc_errors++; 1782 if (dma_flag & DMA_RX_OV) 1783 dev->stats.rx_over_errors++; 1784 if (dma_flag & DMA_RX_NO) 1785 dev->stats.rx_frame_errors++; 1786 if (dma_flag & DMA_RX_LG) 1787 dev->stats.rx_length_errors++; 1788 dev->stats.rx_errors++; 1789 dev_kfree_skb_any(skb); 1790 goto next; 1791 } /* error packet */ 1792 1793 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && 1794 priv->desc_rxchk_en; 1795 1796 skb_put(skb, len); 1797 if (priv->desc_64b_en) { 1798 skb_pull(skb, 64); 1799 len -= 64; 1800 } 1801 1802 if (likely(chksum_ok)) 1803 skb->ip_summed = CHECKSUM_UNNECESSARY; 1804 1805 /* remove hardware 2bytes added for IP alignment */ 1806 skb_pull(skb, 2); 1807 len -= 2; 1808 1809 if (priv->crc_fwd_en) { 1810 skb_trim(skb, len - ETH_FCS_LEN); 1811 len -= ETH_FCS_LEN; 1812 } 1813 1814 /*Finish setting up the received SKB and send it to the kernel*/ 1815 skb->protocol = eth_type_trans(skb, priv->dev); 1816 ring->packets++; 1817 ring->bytes += len; 1818 if (dma_flag & DMA_RX_MULT) 1819 dev->stats.multicast++; 1820 1821 /* Notify kernel */ 1822 napi_gro_receive(&ring->napi, skb); 1823 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1824 1825 next: 1826 rxpktprocessed++; 1827 if (likely(ring->read_ptr < ring->end_ptr)) 1828 ring->read_ptr++; 1829 else 1830 ring->read_ptr = ring->cb_ptr; 1831 1832 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1833 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1834 } 1835 1836 return rxpktprocessed; 1837 } 1838 1839 /* Rx NAPI polling method */ 1840 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1841 { 1842 struct bcmgenet_rx_ring *ring = container_of(napi, 1843 struct bcmgenet_rx_ring, napi); 1844 unsigned int work_done; 1845 1846 work_done = bcmgenet_desc_rx(ring, budget); 1847 1848 if (work_done < budget) { 1849 napi_complete_done(napi, work_done); 1850 ring->int_enable(ring); 1851 } 1852 1853 return work_done; 1854 } 1855 1856 /* Assign skb to RX DMA descriptor. */ 1857 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1858 struct bcmgenet_rx_ring *ring) 1859 { 1860 struct enet_cb *cb; 1861 struct sk_buff *skb; 1862 int i; 1863 1864 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1865 1866 /* loop here for each buffer needing assign */ 1867 for (i = 0; i < ring->size; i++) { 1868 cb = ring->cbs + i; 1869 skb = bcmgenet_rx_refill(priv, cb); 1870 if (skb) 1871 dev_kfree_skb_any(skb); 1872 if (!cb->skb) 1873 return -ENOMEM; 1874 } 1875 1876 return 0; 1877 } 1878 1879 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1880 { 1881 struct device *kdev = &priv->pdev->dev; 1882 struct enet_cb *cb; 1883 int i; 1884 1885 for (i = 0; i < priv->num_rx_bds; i++) { 1886 cb = &priv->rx_cbs[i]; 1887 1888 if (dma_unmap_addr(cb, dma_addr)) { 1889 dma_unmap_single(kdev, 1890 dma_unmap_addr(cb, dma_addr), 1891 priv->rx_buf_len, DMA_FROM_DEVICE); 1892 dma_unmap_addr_set(cb, dma_addr, 0); 1893 } 1894 1895 if (cb->skb) 1896 bcmgenet_free_cb(cb); 1897 } 1898 } 1899 1900 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1901 { 1902 u32 reg; 1903 1904 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1905 if (enable) 1906 reg |= mask; 1907 else 1908 reg &= ~mask; 1909 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1910 1911 /* UniMAC stops on a packet boundary, wait for a full-size packet 1912 * to be processed 1913 */ 1914 if (enable == 0) 1915 usleep_range(1000, 2000); 1916 } 1917 1918 static int reset_umac(struct bcmgenet_priv *priv) 1919 { 1920 struct device *kdev = &priv->pdev->dev; 1921 unsigned int timeout = 0; 1922 u32 reg; 1923 1924 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1925 bcmgenet_rbuf_ctrl_set(priv, 0); 1926 udelay(10); 1927 1928 /* disable MAC while updating its registers */ 1929 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1930 1931 /* issue soft reset, wait for it to complete */ 1932 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 1933 while (timeout++ < 1000) { 1934 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1935 if (!(reg & CMD_SW_RESET)) 1936 return 0; 1937 1938 udelay(1); 1939 } 1940 1941 if (timeout == 1000) { 1942 dev_err(kdev, 1943 "timeout waiting for MAC to come out of reset\n"); 1944 return -ETIMEDOUT; 1945 } 1946 1947 return 0; 1948 } 1949 1950 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1951 { 1952 /* Mask all interrupts.*/ 1953 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1954 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1955 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1956 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1957 } 1958 1959 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 1960 { 1961 u32 int0_enable = 0; 1962 1963 /* Monitor cable plug/unplugged event for internal PHY, external PHY 1964 * and MoCA PHY 1965 */ 1966 if (priv->internal_phy) { 1967 int0_enable |= UMAC_IRQ_LINK_EVENT; 1968 } else if (priv->ext_phy) { 1969 int0_enable |= UMAC_IRQ_LINK_EVENT; 1970 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1971 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 1972 int0_enable |= UMAC_IRQ_LINK_EVENT; 1973 } 1974 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 1975 } 1976 1977 static int init_umac(struct bcmgenet_priv *priv) 1978 { 1979 struct device *kdev = &priv->pdev->dev; 1980 int ret; 1981 u32 reg; 1982 u32 int0_enable = 0; 1983 1984 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 1985 1986 ret = reset_umac(priv); 1987 if (ret) 1988 return ret; 1989 1990 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1991 /* clear tx/rx counter */ 1992 bcmgenet_umac_writel(priv, 1993 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 1994 UMAC_MIB_CTRL); 1995 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 1996 1997 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1998 1999 /* init rx registers, enable ip header optimization */ 2000 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2001 reg |= RBUF_ALIGN_2B; 2002 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2003 2004 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2005 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2006 2007 bcmgenet_intr_disable(priv); 2008 2009 /* Configure backpressure vectors for MoCA */ 2010 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2011 reg = bcmgenet_bp_mc_get(priv); 2012 reg |= BIT(priv->hw_params->bp_in_en_shift); 2013 2014 /* bp_mask: back pressure mask */ 2015 if (netif_is_multiqueue(priv->dev)) 2016 reg |= priv->hw_params->bp_in_mask; 2017 else 2018 reg &= ~priv->hw_params->bp_in_mask; 2019 bcmgenet_bp_mc_set(priv, reg); 2020 } 2021 2022 /* Enable MDIO interrupts on GENET v3+ */ 2023 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2024 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2025 2026 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2027 2028 dev_dbg(kdev, "done init umac\n"); 2029 2030 return 0; 2031 } 2032 2033 /* Initialize a Tx ring along with corresponding hardware registers */ 2034 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2035 unsigned int index, unsigned int size, 2036 unsigned int start_ptr, unsigned int end_ptr) 2037 { 2038 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2039 u32 words_per_bd = WORDS_PER_BD(priv); 2040 u32 flow_period_val = 0; 2041 2042 spin_lock_init(&ring->lock); 2043 ring->priv = priv; 2044 ring->index = index; 2045 if (index == DESC_INDEX) { 2046 ring->queue = 0; 2047 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2048 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2049 } else { 2050 ring->queue = index + 1; 2051 ring->int_enable = bcmgenet_tx_ring_int_enable; 2052 ring->int_disable = bcmgenet_tx_ring_int_disable; 2053 } 2054 ring->cbs = priv->tx_cbs + start_ptr; 2055 ring->size = size; 2056 ring->clean_ptr = start_ptr; 2057 ring->c_index = 0; 2058 ring->free_bds = size; 2059 ring->write_ptr = start_ptr; 2060 ring->cb_ptr = start_ptr; 2061 ring->end_ptr = end_ptr - 1; 2062 ring->prod_index = 0; 2063 2064 /* Set flow period for ring != 16 */ 2065 if (index != DESC_INDEX) 2066 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2067 2068 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2069 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2070 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2071 /* Disable rate control for now */ 2072 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2073 TDMA_FLOW_PERIOD); 2074 bcmgenet_tdma_ring_writel(priv, index, 2075 ((size << DMA_RING_SIZE_SHIFT) | 2076 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2077 2078 /* Set start and end address, read and write pointers */ 2079 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2080 DMA_START_ADDR); 2081 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2082 TDMA_READ_PTR); 2083 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2084 TDMA_WRITE_PTR); 2085 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2086 DMA_END_ADDR); 2087 } 2088 2089 /* Initialize a RDMA ring */ 2090 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2091 unsigned int index, unsigned int size, 2092 unsigned int start_ptr, unsigned int end_ptr) 2093 { 2094 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2095 u32 words_per_bd = WORDS_PER_BD(priv); 2096 int ret; 2097 2098 ring->priv = priv; 2099 ring->index = index; 2100 if (index == DESC_INDEX) { 2101 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2102 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2103 } else { 2104 ring->int_enable = bcmgenet_rx_ring_int_enable; 2105 ring->int_disable = bcmgenet_rx_ring_int_disable; 2106 } 2107 ring->cbs = priv->rx_cbs + start_ptr; 2108 ring->size = size; 2109 ring->c_index = 0; 2110 ring->read_ptr = start_ptr; 2111 ring->cb_ptr = start_ptr; 2112 ring->end_ptr = end_ptr - 1; 2113 2114 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2115 if (ret) 2116 return ret; 2117 2118 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2119 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2120 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2121 bcmgenet_rdma_ring_writel(priv, index, 2122 ((size << DMA_RING_SIZE_SHIFT) | 2123 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2124 bcmgenet_rdma_ring_writel(priv, index, 2125 (DMA_FC_THRESH_LO << 2126 DMA_XOFF_THRESHOLD_SHIFT) | 2127 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2128 2129 /* Set start and end address, read and write pointers */ 2130 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2131 DMA_START_ADDR); 2132 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2133 RDMA_READ_PTR); 2134 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2135 RDMA_WRITE_PTR); 2136 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2137 DMA_END_ADDR); 2138 2139 return ret; 2140 } 2141 2142 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) 2143 { 2144 unsigned int i; 2145 struct bcmgenet_tx_ring *ring; 2146 2147 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2148 ring = &priv->tx_rings[i]; 2149 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 2150 } 2151 2152 ring = &priv->tx_rings[DESC_INDEX]; 2153 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 2154 } 2155 2156 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2157 { 2158 unsigned int i; 2159 u32 int0_enable = UMAC_IRQ_TXDMA_DONE; 2160 u32 int1_enable = 0; 2161 struct bcmgenet_tx_ring *ring; 2162 2163 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2164 ring = &priv->tx_rings[i]; 2165 napi_enable(&ring->napi); 2166 int1_enable |= (1 << i); 2167 } 2168 2169 ring = &priv->tx_rings[DESC_INDEX]; 2170 napi_enable(&ring->napi); 2171 2172 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2173 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2174 } 2175 2176 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2177 { 2178 unsigned int i; 2179 u32 int0_disable = UMAC_IRQ_TXDMA_DONE; 2180 u32 int1_disable = 0xffff; 2181 struct bcmgenet_tx_ring *ring; 2182 2183 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); 2184 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); 2185 2186 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2187 ring = &priv->tx_rings[i]; 2188 napi_disable(&ring->napi); 2189 } 2190 2191 ring = &priv->tx_rings[DESC_INDEX]; 2192 napi_disable(&ring->napi); 2193 } 2194 2195 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2196 { 2197 unsigned int i; 2198 struct bcmgenet_tx_ring *ring; 2199 2200 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2201 ring = &priv->tx_rings[i]; 2202 netif_napi_del(&ring->napi); 2203 } 2204 2205 ring = &priv->tx_rings[DESC_INDEX]; 2206 netif_napi_del(&ring->napi); 2207 } 2208 2209 /* Initialize Tx queues 2210 * 2211 * Queues 0-3 are priority-based, each one has 32 descriptors, 2212 * with queue 0 being the highest priority queue. 2213 * 2214 * Queue 16 is the default Tx queue with 2215 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2216 * 2217 * The transmit control block pool is then partitioned as follows: 2218 * - Tx queue 0 uses tx_cbs[0..31] 2219 * - Tx queue 1 uses tx_cbs[32..63] 2220 * - Tx queue 2 uses tx_cbs[64..95] 2221 * - Tx queue 3 uses tx_cbs[96..127] 2222 * - Tx queue 16 uses tx_cbs[128..255] 2223 */ 2224 static void bcmgenet_init_tx_queues(struct net_device *dev) 2225 { 2226 struct bcmgenet_priv *priv = netdev_priv(dev); 2227 u32 i, dma_enable; 2228 u32 dma_ctrl, ring_cfg; 2229 u32 dma_priority[3] = {0, 0, 0}; 2230 2231 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2232 dma_enable = dma_ctrl & DMA_EN; 2233 dma_ctrl &= ~DMA_EN; 2234 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2235 2236 dma_ctrl = 0; 2237 ring_cfg = 0; 2238 2239 /* Enable strict priority arbiter mode */ 2240 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2241 2242 /* Initialize Tx priority queues */ 2243 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2244 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2245 i * priv->hw_params->tx_bds_per_q, 2246 (i + 1) * priv->hw_params->tx_bds_per_q); 2247 ring_cfg |= (1 << i); 2248 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2249 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2250 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2251 } 2252 2253 /* Initialize Tx default queue 16 */ 2254 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2255 priv->hw_params->tx_queues * 2256 priv->hw_params->tx_bds_per_q, 2257 TOTAL_DESC); 2258 ring_cfg |= (1 << DESC_INDEX); 2259 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2260 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2261 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2262 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2263 2264 /* Set Tx queue priorities */ 2265 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2266 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2267 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2268 2269 /* Initialize Tx NAPI */ 2270 bcmgenet_init_tx_napi(priv); 2271 2272 /* Enable Tx queues */ 2273 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2274 2275 /* Enable Tx DMA */ 2276 if (dma_enable) 2277 dma_ctrl |= DMA_EN; 2278 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2279 } 2280 2281 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv) 2282 { 2283 unsigned int i; 2284 struct bcmgenet_rx_ring *ring; 2285 2286 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2287 ring = &priv->rx_rings[i]; 2288 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2289 } 2290 2291 ring = &priv->rx_rings[DESC_INDEX]; 2292 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2293 } 2294 2295 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2296 { 2297 unsigned int i; 2298 u32 int0_enable = UMAC_IRQ_RXDMA_DONE; 2299 u32 int1_enable = 0; 2300 struct bcmgenet_rx_ring *ring; 2301 2302 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2303 ring = &priv->rx_rings[i]; 2304 napi_enable(&ring->napi); 2305 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); 2306 } 2307 2308 ring = &priv->rx_rings[DESC_INDEX]; 2309 napi_enable(&ring->napi); 2310 2311 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2312 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2313 } 2314 2315 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2316 { 2317 unsigned int i; 2318 u32 int0_disable = UMAC_IRQ_RXDMA_DONE; 2319 u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT; 2320 struct bcmgenet_rx_ring *ring; 2321 2322 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); 2323 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); 2324 2325 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2326 ring = &priv->rx_rings[i]; 2327 napi_disable(&ring->napi); 2328 } 2329 2330 ring = &priv->rx_rings[DESC_INDEX]; 2331 napi_disable(&ring->napi); 2332 } 2333 2334 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2335 { 2336 unsigned int i; 2337 struct bcmgenet_rx_ring *ring; 2338 2339 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2340 ring = &priv->rx_rings[i]; 2341 netif_napi_del(&ring->napi); 2342 } 2343 2344 ring = &priv->rx_rings[DESC_INDEX]; 2345 netif_napi_del(&ring->napi); 2346 } 2347 2348 /* Initialize Rx queues 2349 * 2350 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2351 * used to direct traffic to these queues. 2352 * 2353 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2354 */ 2355 static int bcmgenet_init_rx_queues(struct net_device *dev) 2356 { 2357 struct bcmgenet_priv *priv = netdev_priv(dev); 2358 u32 i; 2359 u32 dma_enable; 2360 u32 dma_ctrl; 2361 u32 ring_cfg; 2362 int ret; 2363 2364 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2365 dma_enable = dma_ctrl & DMA_EN; 2366 dma_ctrl &= ~DMA_EN; 2367 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2368 2369 dma_ctrl = 0; 2370 ring_cfg = 0; 2371 2372 /* Initialize Rx priority queues */ 2373 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2374 ret = bcmgenet_init_rx_ring(priv, i, 2375 priv->hw_params->rx_bds_per_q, 2376 i * priv->hw_params->rx_bds_per_q, 2377 (i + 1) * 2378 priv->hw_params->rx_bds_per_q); 2379 if (ret) 2380 return ret; 2381 2382 ring_cfg |= (1 << i); 2383 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2384 } 2385 2386 /* Initialize Rx default queue 16 */ 2387 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2388 priv->hw_params->rx_queues * 2389 priv->hw_params->rx_bds_per_q, 2390 TOTAL_DESC); 2391 if (ret) 2392 return ret; 2393 2394 ring_cfg |= (1 << DESC_INDEX); 2395 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2396 2397 /* Initialize Rx NAPI */ 2398 bcmgenet_init_rx_napi(priv); 2399 2400 /* Enable rings */ 2401 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2402 2403 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2404 if (dma_enable) 2405 dma_ctrl |= DMA_EN; 2406 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2407 2408 return 0; 2409 } 2410 2411 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2412 { 2413 int ret = 0; 2414 int timeout = 0; 2415 u32 reg; 2416 u32 dma_ctrl; 2417 int i; 2418 2419 /* Disable TDMA to stop add more frames in TX DMA */ 2420 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2421 reg &= ~DMA_EN; 2422 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2423 2424 /* Check TDMA status register to confirm TDMA is disabled */ 2425 while (timeout++ < DMA_TIMEOUT_VAL) { 2426 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2427 if (reg & DMA_DISABLED) 2428 break; 2429 2430 udelay(1); 2431 } 2432 2433 if (timeout == DMA_TIMEOUT_VAL) { 2434 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2435 ret = -ETIMEDOUT; 2436 } 2437 2438 /* Wait 10ms for packet drain in both tx and rx dma */ 2439 usleep_range(10000, 20000); 2440 2441 /* Disable RDMA */ 2442 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2443 reg &= ~DMA_EN; 2444 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2445 2446 timeout = 0; 2447 /* Check RDMA status register to confirm RDMA is disabled */ 2448 while (timeout++ < DMA_TIMEOUT_VAL) { 2449 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2450 if (reg & DMA_DISABLED) 2451 break; 2452 2453 udelay(1); 2454 } 2455 2456 if (timeout == DMA_TIMEOUT_VAL) { 2457 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2458 ret = -ETIMEDOUT; 2459 } 2460 2461 dma_ctrl = 0; 2462 for (i = 0; i < priv->hw_params->rx_queues; i++) 2463 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2464 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2465 reg &= ~dma_ctrl; 2466 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2467 2468 dma_ctrl = 0; 2469 for (i = 0; i < priv->hw_params->tx_queues; i++) 2470 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2471 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2472 reg &= ~dma_ctrl; 2473 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2474 2475 return ret; 2476 } 2477 2478 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2479 { 2480 int i; 2481 struct netdev_queue *txq; 2482 2483 bcmgenet_fini_rx_napi(priv); 2484 bcmgenet_fini_tx_napi(priv); 2485 2486 /* disable DMA */ 2487 bcmgenet_dma_teardown(priv); 2488 2489 for (i = 0; i < priv->num_tx_bds; i++) { 2490 if (priv->tx_cbs[i].skb != NULL) { 2491 dev_kfree_skb(priv->tx_cbs[i].skb); 2492 priv->tx_cbs[i].skb = NULL; 2493 } 2494 } 2495 2496 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2497 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2498 netdev_tx_reset_queue(txq); 2499 } 2500 2501 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2502 netdev_tx_reset_queue(txq); 2503 2504 bcmgenet_free_rx_buffers(priv); 2505 kfree(priv->rx_cbs); 2506 kfree(priv->tx_cbs); 2507 } 2508 2509 /* init_edma: Initialize DMA control register */ 2510 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2511 { 2512 int ret; 2513 unsigned int i; 2514 struct enet_cb *cb; 2515 2516 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2517 2518 /* Initialize common Rx ring structures */ 2519 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2520 priv->num_rx_bds = TOTAL_DESC; 2521 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2522 GFP_KERNEL); 2523 if (!priv->rx_cbs) 2524 return -ENOMEM; 2525 2526 for (i = 0; i < priv->num_rx_bds; i++) { 2527 cb = priv->rx_cbs + i; 2528 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2529 } 2530 2531 /* Initialize common TX ring structures */ 2532 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2533 priv->num_tx_bds = TOTAL_DESC; 2534 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2535 GFP_KERNEL); 2536 if (!priv->tx_cbs) { 2537 kfree(priv->rx_cbs); 2538 return -ENOMEM; 2539 } 2540 2541 for (i = 0; i < priv->num_tx_bds; i++) { 2542 cb = priv->tx_cbs + i; 2543 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2544 } 2545 2546 /* Init rDma */ 2547 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2548 2549 /* Initialize Rx queues */ 2550 ret = bcmgenet_init_rx_queues(priv->dev); 2551 if (ret) { 2552 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2553 bcmgenet_free_rx_buffers(priv); 2554 kfree(priv->rx_cbs); 2555 kfree(priv->tx_cbs); 2556 return ret; 2557 } 2558 2559 /* Init tDma */ 2560 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2561 2562 /* Initialize Tx queues */ 2563 bcmgenet_init_tx_queues(priv->dev); 2564 2565 return 0; 2566 } 2567 2568 /* Interrupt bottom half */ 2569 static void bcmgenet_irq_task(struct work_struct *work) 2570 { 2571 unsigned long flags; 2572 unsigned int status; 2573 struct bcmgenet_priv *priv = container_of( 2574 work, struct bcmgenet_priv, bcmgenet_irq_work); 2575 2576 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2577 2578 spin_lock_irqsave(&priv->lock, flags); 2579 status = priv->irq0_stat; 2580 priv->irq0_stat = 0; 2581 spin_unlock_irqrestore(&priv->lock, flags); 2582 2583 if (status & UMAC_IRQ_MPD_R) { 2584 netif_dbg(priv, wol, priv->dev, 2585 "magic packet detected, waking up\n"); 2586 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 2587 } 2588 2589 /* Link UP/DOWN event */ 2590 if (status & UMAC_IRQ_LINK_EVENT) 2591 phy_mac_interrupt(priv->phydev, 2592 !!(status & UMAC_IRQ_LINK_UP)); 2593 } 2594 2595 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2596 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2597 { 2598 struct bcmgenet_priv *priv = dev_id; 2599 struct bcmgenet_rx_ring *rx_ring; 2600 struct bcmgenet_tx_ring *tx_ring; 2601 unsigned int index, status; 2602 2603 /* Read irq status */ 2604 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2605 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2606 2607 /* clear interrupts */ 2608 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2609 2610 netif_dbg(priv, intr, priv->dev, 2611 "%s: IRQ=0x%x\n", __func__, status); 2612 2613 /* Check Rx priority queue interrupts */ 2614 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2615 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2616 continue; 2617 2618 rx_ring = &priv->rx_rings[index]; 2619 2620 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2621 rx_ring->int_disable(rx_ring); 2622 __napi_schedule_irqoff(&rx_ring->napi); 2623 } 2624 } 2625 2626 /* Check Tx priority queue interrupts */ 2627 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2628 if (!(status & BIT(index))) 2629 continue; 2630 2631 tx_ring = &priv->tx_rings[index]; 2632 2633 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2634 tx_ring->int_disable(tx_ring); 2635 __napi_schedule_irqoff(&tx_ring->napi); 2636 } 2637 } 2638 2639 return IRQ_HANDLED; 2640 } 2641 2642 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2643 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2644 { 2645 struct bcmgenet_priv *priv = dev_id; 2646 struct bcmgenet_rx_ring *rx_ring; 2647 struct bcmgenet_tx_ring *tx_ring; 2648 unsigned int status; 2649 unsigned long flags; 2650 2651 /* Read irq status */ 2652 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2653 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2654 2655 /* clear interrupts */ 2656 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2657 2658 netif_dbg(priv, intr, priv->dev, 2659 "IRQ=0x%x\n", status); 2660 2661 if (status & UMAC_IRQ_RXDMA_DONE) { 2662 rx_ring = &priv->rx_rings[DESC_INDEX]; 2663 2664 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2665 rx_ring->int_disable(rx_ring); 2666 __napi_schedule_irqoff(&rx_ring->napi); 2667 } 2668 } 2669 2670 if (status & UMAC_IRQ_TXDMA_DONE) { 2671 tx_ring = &priv->tx_rings[DESC_INDEX]; 2672 2673 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2674 tx_ring->int_disable(tx_ring); 2675 __napi_schedule_irqoff(&tx_ring->napi); 2676 } 2677 } 2678 2679 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | 2680 UMAC_IRQ_PHY_DET_F | 2681 UMAC_IRQ_LINK_EVENT | 2682 UMAC_IRQ_HFB_SM | 2683 UMAC_IRQ_HFB_MM)) { 2684 /* all other interested interrupts handled in bottom half */ 2685 schedule_work(&priv->bcmgenet_irq_work); 2686 } 2687 2688 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2689 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2690 wake_up(&priv->wq); 2691 } 2692 2693 /* all other interested interrupts handled in bottom half */ 2694 status &= (UMAC_IRQ_LINK_EVENT | 2695 UMAC_IRQ_MPD_R); 2696 if (status) { 2697 /* Save irq status for bottom-half processing. */ 2698 spin_lock_irqsave(&priv->lock, flags); 2699 priv->irq0_stat |= status; 2700 spin_unlock_irqrestore(&priv->lock, flags); 2701 2702 schedule_work(&priv->bcmgenet_irq_work); 2703 } 2704 2705 return IRQ_HANDLED; 2706 } 2707 2708 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2709 { 2710 struct bcmgenet_priv *priv = dev_id; 2711 2712 pm_wakeup_event(&priv->pdev->dev, 0); 2713 2714 return IRQ_HANDLED; 2715 } 2716 2717 #ifdef CONFIG_NET_POLL_CONTROLLER 2718 static void bcmgenet_poll_controller(struct net_device *dev) 2719 { 2720 struct bcmgenet_priv *priv = netdev_priv(dev); 2721 2722 /* Invoke the main RX/TX interrupt handler */ 2723 disable_irq(priv->irq0); 2724 bcmgenet_isr0(priv->irq0, priv); 2725 enable_irq(priv->irq0); 2726 2727 /* And the interrupt handler for RX/TX priority queues */ 2728 disable_irq(priv->irq1); 2729 bcmgenet_isr1(priv->irq1, priv); 2730 enable_irq(priv->irq1); 2731 } 2732 #endif 2733 2734 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2735 { 2736 u32 reg; 2737 2738 reg = bcmgenet_rbuf_ctrl_get(priv); 2739 reg |= BIT(1); 2740 bcmgenet_rbuf_ctrl_set(priv, reg); 2741 udelay(10); 2742 2743 reg &= ~BIT(1); 2744 bcmgenet_rbuf_ctrl_set(priv, reg); 2745 udelay(10); 2746 } 2747 2748 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2749 unsigned char *addr) 2750 { 2751 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2752 (addr[2] << 8) | addr[3], UMAC_MAC0); 2753 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2754 } 2755 2756 /* Returns a reusable dma control register value */ 2757 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2758 { 2759 u32 reg; 2760 u32 dma_ctrl; 2761 2762 /* disable DMA */ 2763 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2764 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2765 reg &= ~dma_ctrl; 2766 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2767 2768 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2769 reg &= ~dma_ctrl; 2770 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2771 2772 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2773 udelay(10); 2774 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2775 2776 return dma_ctrl; 2777 } 2778 2779 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2780 { 2781 u32 reg; 2782 2783 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2784 reg |= dma_ctrl; 2785 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2786 2787 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2788 reg |= dma_ctrl; 2789 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2790 } 2791 2792 /* bcmgenet_hfb_clear 2793 * 2794 * Clear Hardware Filter Block and disable all filtering. 2795 */ 2796 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2797 { 2798 u32 i; 2799 2800 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2801 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2802 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2803 2804 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2805 bcmgenet_rdma_writel(priv, 0x0, i); 2806 2807 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2808 bcmgenet_hfb_reg_writel(priv, 0x0, 2809 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2810 2811 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2812 priv->hw_params->hfb_filter_size; i++) 2813 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2814 } 2815 2816 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2817 { 2818 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2819 return; 2820 2821 bcmgenet_hfb_clear(priv); 2822 } 2823 2824 static void bcmgenet_netif_start(struct net_device *dev) 2825 { 2826 struct bcmgenet_priv *priv = netdev_priv(dev); 2827 2828 /* Start the network engine */ 2829 bcmgenet_enable_rx_napi(priv); 2830 bcmgenet_enable_tx_napi(priv); 2831 2832 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2833 2834 netif_tx_start_all_queues(dev); 2835 2836 /* Monitor link interrupts now */ 2837 bcmgenet_link_intr_enable(priv); 2838 2839 phy_start(priv->phydev); 2840 } 2841 2842 static int bcmgenet_open(struct net_device *dev) 2843 { 2844 struct bcmgenet_priv *priv = netdev_priv(dev); 2845 unsigned long dma_ctrl; 2846 u32 reg; 2847 int ret; 2848 2849 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2850 2851 /* Turn on the clock */ 2852 clk_prepare_enable(priv->clk); 2853 2854 /* If this is an internal GPHY, power it back on now, before UniMAC is 2855 * brought out of reset as absolutely no UniMAC activity is allowed 2856 */ 2857 if (priv->internal_phy) 2858 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2859 2860 /* take MAC out of reset */ 2861 bcmgenet_umac_reset(priv); 2862 2863 ret = init_umac(priv); 2864 if (ret) 2865 goto err_clk_disable; 2866 2867 /* disable ethernet MAC while updating its registers */ 2868 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 2869 2870 /* Make sure we reflect the value of CRC_CMD_FWD */ 2871 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2872 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 2873 2874 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2875 2876 if (priv->internal_phy) { 2877 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2878 reg |= EXT_ENERGY_DET_MASK; 2879 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2880 } 2881 2882 /* Disable RX/TX DMA and flush TX queues */ 2883 dma_ctrl = bcmgenet_dma_disable(priv); 2884 2885 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2886 ret = bcmgenet_init_dma(priv); 2887 if (ret) { 2888 netdev_err(dev, "failed to initialize DMA\n"); 2889 goto err_clk_disable; 2890 } 2891 2892 /* Always enable ring 16 - descriptor ring */ 2893 bcmgenet_enable_dma(priv, dma_ctrl); 2894 2895 /* HFB init */ 2896 bcmgenet_hfb_init(priv); 2897 2898 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2899 dev->name, priv); 2900 if (ret < 0) { 2901 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2902 goto err_fini_dma; 2903 } 2904 2905 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2906 dev->name, priv); 2907 if (ret < 0) { 2908 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2909 goto err_irq0; 2910 } 2911 2912 ret = bcmgenet_mii_probe(dev); 2913 if (ret) { 2914 netdev_err(dev, "failed to connect to PHY\n"); 2915 goto err_irq1; 2916 } 2917 2918 bcmgenet_netif_start(dev); 2919 2920 return 0; 2921 2922 err_irq1: 2923 free_irq(priv->irq1, priv); 2924 err_irq0: 2925 free_irq(priv->irq0, priv); 2926 err_fini_dma: 2927 bcmgenet_fini_dma(priv); 2928 err_clk_disable: 2929 if (priv->internal_phy) 2930 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2931 clk_disable_unprepare(priv->clk); 2932 return ret; 2933 } 2934 2935 static void bcmgenet_netif_stop(struct net_device *dev) 2936 { 2937 struct bcmgenet_priv *priv = netdev_priv(dev); 2938 2939 netif_tx_stop_all_queues(dev); 2940 phy_stop(priv->phydev); 2941 bcmgenet_intr_disable(priv); 2942 bcmgenet_disable_rx_napi(priv); 2943 bcmgenet_disable_tx_napi(priv); 2944 2945 /* Wait for pending work items to complete. Since interrupts are 2946 * disabled no new work will be scheduled. 2947 */ 2948 cancel_work_sync(&priv->bcmgenet_irq_work); 2949 2950 priv->old_link = -1; 2951 priv->old_speed = -1; 2952 priv->old_duplex = -1; 2953 priv->old_pause = -1; 2954 } 2955 2956 static int bcmgenet_close(struct net_device *dev) 2957 { 2958 struct bcmgenet_priv *priv = netdev_priv(dev); 2959 int ret; 2960 2961 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2962 2963 bcmgenet_netif_stop(dev); 2964 2965 /* Really kill the PHY state machine and disconnect from it */ 2966 phy_disconnect(priv->phydev); 2967 2968 /* Disable MAC receive */ 2969 umac_enable_set(priv, CMD_RX_EN, false); 2970 2971 ret = bcmgenet_dma_teardown(priv); 2972 if (ret) 2973 return ret; 2974 2975 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2976 umac_enable_set(priv, CMD_TX_EN, false); 2977 2978 /* tx reclaim */ 2979 bcmgenet_tx_reclaim_all(dev); 2980 bcmgenet_fini_dma(priv); 2981 2982 free_irq(priv->irq0, priv); 2983 free_irq(priv->irq1, priv); 2984 2985 if (priv->internal_phy) 2986 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2987 2988 clk_disable_unprepare(priv->clk); 2989 2990 return ret; 2991 } 2992 2993 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 2994 { 2995 struct bcmgenet_priv *priv = ring->priv; 2996 u32 p_index, c_index, intsts, intmsk; 2997 struct netdev_queue *txq; 2998 unsigned int free_bds; 2999 unsigned long flags; 3000 bool txq_stopped; 3001 3002 if (!netif_msg_tx_err(priv)) 3003 return; 3004 3005 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3006 3007 spin_lock_irqsave(&ring->lock, flags); 3008 if (ring->index == DESC_INDEX) { 3009 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3010 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3011 } else { 3012 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3013 intmsk = 1 << ring->index; 3014 } 3015 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3016 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3017 txq_stopped = netif_tx_queue_stopped(txq); 3018 free_bds = ring->free_bds; 3019 spin_unlock_irqrestore(&ring->lock, flags); 3020 3021 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3022 "TX queue status: %s, interrupts: %s\n" 3023 "(sw)free_bds: %d (sw)size: %d\n" 3024 "(sw)p_index: %d (hw)p_index: %d\n" 3025 "(sw)c_index: %d (hw)c_index: %d\n" 3026 "(sw)clean_p: %d (sw)write_p: %d\n" 3027 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3028 ring->index, ring->queue, 3029 txq_stopped ? "stopped" : "active", 3030 intsts & intmsk ? "enabled" : "disabled", 3031 free_bds, ring->size, 3032 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3033 ring->c_index, c_index & DMA_C_INDEX_MASK, 3034 ring->clean_ptr, ring->write_ptr, 3035 ring->cb_ptr, ring->end_ptr); 3036 } 3037 3038 static void bcmgenet_timeout(struct net_device *dev) 3039 { 3040 struct bcmgenet_priv *priv = netdev_priv(dev); 3041 u32 int0_enable = 0; 3042 u32 int1_enable = 0; 3043 unsigned int q; 3044 3045 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3046 3047 for (q = 0; q < priv->hw_params->tx_queues; q++) 3048 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3049 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3050 3051 bcmgenet_tx_reclaim_all(dev); 3052 3053 for (q = 0; q < priv->hw_params->tx_queues; q++) 3054 int1_enable |= (1 << q); 3055 3056 int0_enable = UMAC_IRQ_TXDMA_DONE; 3057 3058 /* Re-enable TX interrupts if disabled */ 3059 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3060 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3061 3062 netif_trans_update(dev); 3063 3064 dev->stats.tx_errors++; 3065 3066 netif_tx_wake_all_queues(dev); 3067 } 3068 3069 #define MAX_MC_COUNT 16 3070 3071 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3072 unsigned char *addr, 3073 int *i, 3074 int *mc) 3075 { 3076 u32 reg; 3077 3078 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3079 UMAC_MDF_ADDR + (*i * 4)); 3080 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3081 addr[4] << 8 | addr[5], 3082 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3083 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); 3084 reg |= (1 << (MAX_MC_COUNT - *mc)); 3085 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3086 *i += 2; 3087 (*mc)++; 3088 } 3089 3090 static void bcmgenet_set_rx_mode(struct net_device *dev) 3091 { 3092 struct bcmgenet_priv *priv = netdev_priv(dev); 3093 struct netdev_hw_addr *ha; 3094 int i, mc; 3095 u32 reg; 3096 3097 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3098 3099 /* Promiscuous mode */ 3100 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3101 if (dev->flags & IFF_PROMISC) { 3102 reg |= CMD_PROMISC; 3103 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3104 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3105 return; 3106 } else { 3107 reg &= ~CMD_PROMISC; 3108 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3109 } 3110 3111 /* UniMac doesn't support ALLMULTI */ 3112 if (dev->flags & IFF_ALLMULTI) { 3113 netdev_warn(dev, "ALLMULTI is not supported\n"); 3114 return; 3115 } 3116 3117 /* update MDF filter */ 3118 i = 0; 3119 mc = 0; 3120 /* Broadcast */ 3121 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); 3122 /* my own address.*/ 3123 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); 3124 /* Unicast list*/ 3125 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) 3126 return; 3127 3128 if (!netdev_uc_empty(dev)) 3129 netdev_for_each_uc_addr(ha, dev) 3130 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 3131 /* Multicast */ 3132 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) 3133 return; 3134 3135 netdev_for_each_mc_addr(ha, dev) 3136 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 3137 } 3138 3139 /* Set the hardware MAC address. */ 3140 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3141 { 3142 struct sockaddr *addr = p; 3143 3144 /* Setting the MAC address at the hardware level is not possible 3145 * without disabling the UniMAC RX/TX enable bits. 3146 */ 3147 if (netif_running(dev)) 3148 return -EBUSY; 3149 3150 ether_addr_copy(dev->dev_addr, addr->sa_data); 3151 3152 return 0; 3153 } 3154 3155 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3156 { 3157 struct bcmgenet_priv *priv = netdev_priv(dev); 3158 unsigned long tx_bytes = 0, tx_packets = 0; 3159 unsigned long rx_bytes = 0, rx_packets = 0; 3160 unsigned long rx_errors = 0, rx_dropped = 0; 3161 struct bcmgenet_tx_ring *tx_ring; 3162 struct bcmgenet_rx_ring *rx_ring; 3163 unsigned int q; 3164 3165 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3166 tx_ring = &priv->tx_rings[q]; 3167 tx_bytes += tx_ring->bytes; 3168 tx_packets += tx_ring->packets; 3169 } 3170 tx_ring = &priv->tx_rings[DESC_INDEX]; 3171 tx_bytes += tx_ring->bytes; 3172 tx_packets += tx_ring->packets; 3173 3174 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3175 rx_ring = &priv->rx_rings[q]; 3176 3177 rx_bytes += rx_ring->bytes; 3178 rx_packets += rx_ring->packets; 3179 rx_errors += rx_ring->errors; 3180 rx_dropped += rx_ring->dropped; 3181 } 3182 rx_ring = &priv->rx_rings[DESC_INDEX]; 3183 rx_bytes += rx_ring->bytes; 3184 rx_packets += rx_ring->packets; 3185 rx_errors += rx_ring->errors; 3186 rx_dropped += rx_ring->dropped; 3187 3188 dev->stats.tx_bytes = tx_bytes; 3189 dev->stats.tx_packets = tx_packets; 3190 dev->stats.rx_bytes = rx_bytes; 3191 dev->stats.rx_packets = rx_packets; 3192 dev->stats.rx_errors = rx_errors; 3193 dev->stats.rx_missed_errors = rx_errors; 3194 return &dev->stats; 3195 } 3196 3197 static const struct net_device_ops bcmgenet_netdev_ops = { 3198 .ndo_open = bcmgenet_open, 3199 .ndo_stop = bcmgenet_close, 3200 .ndo_start_xmit = bcmgenet_xmit, 3201 .ndo_tx_timeout = bcmgenet_timeout, 3202 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3203 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3204 .ndo_do_ioctl = bcmgenet_ioctl, 3205 .ndo_set_features = bcmgenet_set_features, 3206 #ifdef CONFIG_NET_POLL_CONTROLLER 3207 .ndo_poll_controller = bcmgenet_poll_controller, 3208 #endif 3209 .ndo_get_stats = bcmgenet_get_stats, 3210 }; 3211 3212 /* Array of GENET hardware parameters/characteristics */ 3213 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3214 [GENET_V1] = { 3215 .tx_queues = 0, 3216 .tx_bds_per_q = 0, 3217 .rx_queues = 0, 3218 .rx_bds_per_q = 0, 3219 .bp_in_en_shift = 16, 3220 .bp_in_mask = 0xffff, 3221 .hfb_filter_cnt = 16, 3222 .qtag_mask = 0x1F, 3223 .hfb_offset = 0x1000, 3224 .rdma_offset = 0x2000, 3225 .tdma_offset = 0x3000, 3226 .words_per_bd = 2, 3227 }, 3228 [GENET_V2] = { 3229 .tx_queues = 4, 3230 .tx_bds_per_q = 32, 3231 .rx_queues = 0, 3232 .rx_bds_per_q = 0, 3233 .bp_in_en_shift = 16, 3234 .bp_in_mask = 0xffff, 3235 .hfb_filter_cnt = 16, 3236 .qtag_mask = 0x1F, 3237 .tbuf_offset = 0x0600, 3238 .hfb_offset = 0x1000, 3239 .hfb_reg_offset = 0x2000, 3240 .rdma_offset = 0x3000, 3241 .tdma_offset = 0x4000, 3242 .words_per_bd = 2, 3243 .flags = GENET_HAS_EXT, 3244 }, 3245 [GENET_V3] = { 3246 .tx_queues = 4, 3247 .tx_bds_per_q = 32, 3248 .rx_queues = 0, 3249 .rx_bds_per_q = 0, 3250 .bp_in_en_shift = 17, 3251 .bp_in_mask = 0x1ffff, 3252 .hfb_filter_cnt = 48, 3253 .hfb_filter_size = 128, 3254 .qtag_mask = 0x3F, 3255 .tbuf_offset = 0x0600, 3256 .hfb_offset = 0x8000, 3257 .hfb_reg_offset = 0xfc00, 3258 .rdma_offset = 0x10000, 3259 .tdma_offset = 0x11000, 3260 .words_per_bd = 2, 3261 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3262 GENET_HAS_MOCA_LINK_DET, 3263 }, 3264 [GENET_V4] = { 3265 .tx_queues = 4, 3266 .tx_bds_per_q = 32, 3267 .rx_queues = 0, 3268 .rx_bds_per_q = 0, 3269 .bp_in_en_shift = 17, 3270 .bp_in_mask = 0x1ffff, 3271 .hfb_filter_cnt = 48, 3272 .hfb_filter_size = 128, 3273 .qtag_mask = 0x3F, 3274 .tbuf_offset = 0x0600, 3275 .hfb_offset = 0x8000, 3276 .hfb_reg_offset = 0xfc00, 3277 .rdma_offset = 0x2000, 3278 .tdma_offset = 0x4000, 3279 .words_per_bd = 3, 3280 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3281 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3282 }, 3283 [GENET_V5] = { 3284 .tx_queues = 4, 3285 .tx_bds_per_q = 32, 3286 .rx_queues = 0, 3287 .rx_bds_per_q = 0, 3288 .bp_in_en_shift = 17, 3289 .bp_in_mask = 0x1ffff, 3290 .hfb_filter_cnt = 48, 3291 .hfb_filter_size = 128, 3292 .qtag_mask = 0x3F, 3293 .tbuf_offset = 0x0600, 3294 .hfb_offset = 0x8000, 3295 .hfb_reg_offset = 0xfc00, 3296 .rdma_offset = 0x2000, 3297 .tdma_offset = 0x4000, 3298 .words_per_bd = 3, 3299 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3300 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3301 }, 3302 }; 3303 3304 /* Infer hardware parameters from the detected GENET version */ 3305 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3306 { 3307 struct bcmgenet_hw_params *params; 3308 u32 reg; 3309 u8 major; 3310 u16 gphy_rev; 3311 3312 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3313 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3314 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3315 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3316 } else if (GENET_IS_V3(priv)) { 3317 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3318 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3319 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3320 } else if (GENET_IS_V2(priv)) { 3321 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3322 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3323 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3324 } else if (GENET_IS_V1(priv)) { 3325 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3326 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3327 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3328 } 3329 3330 /* enum genet_version starts at 1 */ 3331 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3332 params = priv->hw_params; 3333 3334 /* Read GENET HW version */ 3335 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3336 major = (reg >> 24 & 0x0f); 3337 if (major == 6) 3338 major = 5; 3339 else if (major == 5) 3340 major = 4; 3341 else if (major == 0) 3342 major = 1; 3343 if (major != priv->version) { 3344 dev_err(&priv->pdev->dev, 3345 "GENET version mismatch, got: %d, configured for: %d\n", 3346 major, priv->version); 3347 } 3348 3349 /* Print the GENET core version */ 3350 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3351 major, (reg >> 16) & 0x0f, reg & 0xffff); 3352 3353 /* Store the integrated PHY revision for the MDIO probing function 3354 * to pass this information to the PHY driver. The PHY driver expects 3355 * to find the PHY major revision in bits 15:8 while the GENET register 3356 * stores that information in bits 7:0, account for that. 3357 * 3358 * On newer chips, starting with PHY revision G0, a new scheme is 3359 * deployed similar to the Starfighter 2 switch with GPHY major 3360 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3361 * is reserved as well as special value 0x01ff, we have a small 3362 * heuristic to check for the new GPHY revision and re-arrange things 3363 * so the GPHY driver is happy. 3364 */ 3365 gphy_rev = reg & 0xffff; 3366 3367 if (GENET_IS_V5(priv)) { 3368 /* The EPHY revision should come from the MDIO registers of 3369 * the PHY not from GENET. 3370 */ 3371 if (gphy_rev != 0) { 3372 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3373 gphy_rev); 3374 } 3375 /* This is reserved so should require special treatment */ 3376 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3377 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3378 return; 3379 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3380 } else if ((gphy_rev & 0xf0) != 0) { 3381 priv->gphy_rev = gphy_rev << 8; 3382 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3383 } else if ((gphy_rev & 0xff00) != 0) { 3384 priv->gphy_rev = gphy_rev; 3385 } 3386 3387 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3388 if (!(params->flags & GENET_HAS_40BITS)) 3389 pr_warn("GENET does not support 40-bits PA\n"); 3390 #endif 3391 3392 pr_debug("Configuration for version: %d\n" 3393 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3394 "BP << en: %2d, BP msk: 0x%05x\n" 3395 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3396 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3397 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3398 "Words/BD: %d\n", 3399 priv->version, 3400 params->tx_queues, params->tx_bds_per_q, 3401 params->rx_queues, params->rx_bds_per_q, 3402 params->bp_in_en_shift, params->bp_in_mask, 3403 params->hfb_filter_cnt, params->qtag_mask, 3404 params->tbuf_offset, params->hfb_offset, 3405 params->hfb_reg_offset, 3406 params->rdma_offset, params->tdma_offset, 3407 params->words_per_bd); 3408 } 3409 3410 static const struct of_device_id bcmgenet_match[] = { 3411 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, 3412 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, 3413 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, 3414 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, 3415 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 }, 3416 { }, 3417 }; 3418 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3419 3420 static int bcmgenet_probe(struct platform_device *pdev) 3421 { 3422 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3423 struct device_node *dn = pdev->dev.of_node; 3424 const struct of_device_id *of_id = NULL; 3425 struct bcmgenet_priv *priv; 3426 struct net_device *dev; 3427 const void *macaddr; 3428 struct resource *r; 3429 int err = -EIO; 3430 const char *phy_mode_str; 3431 3432 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3433 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3434 GENET_MAX_MQ_CNT + 1); 3435 if (!dev) { 3436 dev_err(&pdev->dev, "can't allocate net device\n"); 3437 return -ENOMEM; 3438 } 3439 3440 if (dn) { 3441 of_id = of_match_node(bcmgenet_match, dn); 3442 if (!of_id) 3443 return -EINVAL; 3444 } 3445 3446 priv = netdev_priv(dev); 3447 priv->irq0 = platform_get_irq(pdev, 0); 3448 priv->irq1 = platform_get_irq(pdev, 1); 3449 priv->wol_irq = platform_get_irq(pdev, 2); 3450 if (!priv->irq0 || !priv->irq1) { 3451 dev_err(&pdev->dev, "can't find IRQs\n"); 3452 err = -EINVAL; 3453 goto err; 3454 } 3455 3456 if (dn) { 3457 macaddr = of_get_mac_address(dn); 3458 if (!macaddr) { 3459 dev_err(&pdev->dev, "can't find MAC address\n"); 3460 err = -EINVAL; 3461 goto err; 3462 } 3463 } else { 3464 macaddr = pd->mac_address; 3465 } 3466 3467 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3468 priv->base = devm_ioremap_resource(&pdev->dev, r); 3469 if (IS_ERR(priv->base)) { 3470 err = PTR_ERR(priv->base); 3471 goto err; 3472 } 3473 3474 spin_lock_init(&priv->lock); 3475 3476 SET_NETDEV_DEV(dev, &pdev->dev); 3477 dev_set_drvdata(&pdev->dev, dev); 3478 ether_addr_copy(dev->dev_addr, macaddr); 3479 dev->watchdog_timeo = 2 * HZ; 3480 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3481 dev->netdev_ops = &bcmgenet_netdev_ops; 3482 3483 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3484 3485 /* Set hardware features */ 3486 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 3487 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; 3488 3489 /* Request the WOL interrupt and advertise suspend if available */ 3490 priv->wol_irq_disabled = true; 3491 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3492 dev->name, priv); 3493 if (!err) 3494 device_set_wakeup_capable(&pdev->dev, 1); 3495 3496 /* Set the needed headroom to account for any possible 3497 * features enabling/disabling at runtime 3498 */ 3499 dev->needed_headroom += 64; 3500 3501 netdev_boot_setup_check(dev); 3502 3503 priv->dev = dev; 3504 priv->pdev = pdev; 3505 if (of_id) 3506 priv->version = (enum bcmgenet_version)of_id->data; 3507 else 3508 priv->version = pd->genet_version; 3509 3510 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3511 if (IS_ERR(priv->clk)) { 3512 dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); 3513 priv->clk = NULL; 3514 } 3515 3516 clk_prepare_enable(priv->clk); 3517 3518 bcmgenet_set_hw_params(priv); 3519 3520 /* Mii wait queue */ 3521 init_waitqueue_head(&priv->wq); 3522 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3523 priv->rx_buf_len = RX_BUF_LENGTH; 3524 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3525 3526 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3527 if (IS_ERR(priv->clk_wol)) { 3528 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3529 priv->clk_wol = NULL; 3530 } 3531 3532 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3533 if (IS_ERR(priv->clk_eee)) { 3534 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3535 priv->clk_eee = NULL; 3536 } 3537 3538 /* If this is an internal GPHY, power it on now, before UniMAC is 3539 * brought out of reset as absolutely no UniMAC activity is allowed 3540 */ 3541 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) && 3542 !strcasecmp(phy_mode_str, "internal")) 3543 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3544 3545 err = reset_umac(priv); 3546 if (err) 3547 goto err_clk_disable; 3548 3549 err = bcmgenet_mii_init(dev); 3550 if (err) 3551 goto err_clk_disable; 3552 3553 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3554 * just the ring 16 descriptor based TX 3555 */ 3556 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3557 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3558 3559 /* libphy will determine the link state */ 3560 netif_carrier_off(dev); 3561 3562 /* Turn off the main clock, WOL clock is handled separately */ 3563 clk_disable_unprepare(priv->clk); 3564 3565 err = register_netdev(dev); 3566 if (err) 3567 goto err; 3568 3569 return err; 3570 3571 err_clk_disable: 3572 clk_disable_unprepare(priv->clk); 3573 err: 3574 free_netdev(dev); 3575 return err; 3576 } 3577 3578 static int bcmgenet_remove(struct platform_device *pdev) 3579 { 3580 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3581 3582 dev_set_drvdata(&pdev->dev, NULL); 3583 unregister_netdev(priv->dev); 3584 bcmgenet_mii_exit(priv->dev); 3585 free_netdev(priv->dev); 3586 3587 return 0; 3588 } 3589 3590 #ifdef CONFIG_PM_SLEEP 3591 static int bcmgenet_suspend(struct device *d) 3592 { 3593 struct net_device *dev = dev_get_drvdata(d); 3594 struct bcmgenet_priv *priv = netdev_priv(dev); 3595 int ret; 3596 3597 if (!netif_running(dev)) 3598 return 0; 3599 3600 bcmgenet_netif_stop(dev); 3601 3602 if (!device_may_wakeup(d)) 3603 phy_suspend(priv->phydev); 3604 3605 netif_device_detach(dev); 3606 3607 /* Disable MAC receive */ 3608 umac_enable_set(priv, CMD_RX_EN, false); 3609 3610 ret = bcmgenet_dma_teardown(priv); 3611 if (ret) 3612 return ret; 3613 3614 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3615 umac_enable_set(priv, CMD_TX_EN, false); 3616 3617 /* tx reclaim */ 3618 bcmgenet_tx_reclaim_all(dev); 3619 bcmgenet_fini_dma(priv); 3620 3621 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3622 if (device_may_wakeup(d) && priv->wolopts) { 3623 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3624 clk_prepare_enable(priv->clk_wol); 3625 } else if (priv->internal_phy) { 3626 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3627 } 3628 3629 /* Turn off the clocks */ 3630 clk_disable_unprepare(priv->clk); 3631 3632 return ret; 3633 } 3634 3635 static int bcmgenet_resume(struct device *d) 3636 { 3637 struct net_device *dev = dev_get_drvdata(d); 3638 struct bcmgenet_priv *priv = netdev_priv(dev); 3639 unsigned long dma_ctrl; 3640 int ret; 3641 u32 reg; 3642 3643 if (!netif_running(dev)) 3644 return 0; 3645 3646 /* Turn on the clock */ 3647 ret = clk_prepare_enable(priv->clk); 3648 if (ret) 3649 return ret; 3650 3651 /* If this is an internal GPHY, power it back on now, before UniMAC is 3652 * brought out of reset as absolutely no UniMAC activity is allowed 3653 */ 3654 if (priv->internal_phy) 3655 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3656 3657 bcmgenet_umac_reset(priv); 3658 3659 ret = init_umac(priv); 3660 if (ret) 3661 goto out_clk_disable; 3662 3663 /* From WOL-enabled suspend, switch to regular clock */ 3664 if (priv->wolopts) 3665 clk_disable_unprepare(priv->clk_wol); 3666 3667 phy_init_hw(priv->phydev); 3668 /* Speed settings must be restored */ 3669 bcmgenet_mii_config(priv->dev); 3670 3671 /* disable ethernet MAC while updating its registers */ 3672 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 3673 3674 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3675 3676 if (priv->internal_phy) { 3677 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3678 reg |= EXT_ENERGY_DET_MASK; 3679 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3680 } 3681 3682 if (priv->wolopts) 3683 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3684 3685 /* Disable RX/TX DMA and flush TX queues */ 3686 dma_ctrl = bcmgenet_dma_disable(priv); 3687 3688 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3689 ret = bcmgenet_init_dma(priv); 3690 if (ret) { 3691 netdev_err(dev, "failed to initialize DMA\n"); 3692 goto out_clk_disable; 3693 } 3694 3695 /* Always enable ring 16 - descriptor ring */ 3696 bcmgenet_enable_dma(priv, dma_ctrl); 3697 3698 netif_device_attach(dev); 3699 3700 if (!device_may_wakeup(d)) 3701 phy_resume(priv->phydev); 3702 3703 if (priv->eee.eee_enabled) 3704 bcmgenet_eee_enable_set(dev, true); 3705 3706 bcmgenet_netif_start(dev); 3707 3708 return 0; 3709 3710 out_clk_disable: 3711 if (priv->internal_phy) 3712 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3713 clk_disable_unprepare(priv->clk); 3714 return ret; 3715 } 3716 #endif /* CONFIG_PM_SLEEP */ 3717 3718 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3719 3720 static struct platform_driver bcmgenet_driver = { 3721 .probe = bcmgenet_probe, 3722 .remove = bcmgenet_remove, 3723 .driver = { 3724 .name = "bcmgenet", 3725 .of_match_table = bcmgenet_match, 3726 .pm = &bcmgenet_pm_ops, 3727 }, 3728 }; 3729 module_platform_driver(bcmgenet_driver); 3730 3731 MODULE_AUTHOR("Broadcom Corporation"); 3732 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3733 MODULE_ALIAS("platform:bcmgenet"); 3734 MODULE_LICENSE("GPL"); 3735