1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2020 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 #include <linux/platform_data/bcmgenet.h> 39 40 #include <asm/unaligned.h> 41 42 #include "bcmgenet.h" 43 44 /* Maximum number of hardware queues, downsized if needed */ 45 #define GENET_MAX_MQ_CNT 4 46 47 /* Default highest priority queue for multi queue support */ 48 #define GENET_Q0_PRIORITY 0 49 50 #define GENET_Q16_RX_BD_CNT \ 51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 52 #define GENET_Q16_TX_BD_CNT \ 53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 54 55 #define RX_BUF_LENGTH 2048 56 #define SKB_ALIGNMENT 32 57 58 /* Tx/Rx DMA register offset, skip 256 descriptors */ 59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 61 62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 66 TOTAL_DESC * DMA_DESC_SIZE) 67 68 /* Forward declarations */ 69 static void bcmgenet_set_rx_mode(struct net_device *dev); 70 71 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 72 { 73 /* MIPS chips strapped for BE will automagically configure the 74 * peripheral registers for CPU-native byte order. 75 */ 76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 77 __raw_writel(value, offset); 78 else 79 writel_relaxed(value, offset); 80 } 81 82 static inline u32 bcmgenet_readl(void __iomem *offset) 83 { 84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 85 return __raw_readl(offset); 86 else 87 return readl_relaxed(offset); 88 } 89 90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 91 void __iomem *d, u32 value) 92 { 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 94 } 95 96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 97 void __iomem *d, 98 dma_addr_t addr) 99 { 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 101 102 /* Register writes to GISB bus can take couple hundred nanoseconds 103 * and are done for each packet, save these expensive writes unless 104 * the platform is explicitly configured for 64-bits/LPAE. 105 */ 106 #ifdef CONFIG_PHYS_ADDR_T_64BIT 107 if (priv->hw_params->flags & GENET_HAS_40BITS) 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 109 #endif 110 } 111 112 /* Combined address + length/status setter */ 113 static inline void dmadesc_set(struct bcmgenet_priv *priv, 114 void __iomem *d, dma_addr_t addr, u32 val) 115 { 116 dmadesc_set_addr(priv, d, addr); 117 dmadesc_set_length_status(priv, d, val); 118 } 119 120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 121 void __iomem *d) 122 { 123 dma_addr_t addr; 124 125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 126 127 /* Register writes to GISB bus can take couple hundred nanoseconds 128 * and are done for each packet, save these expensive writes unless 129 * the platform is explicitly configured for 64-bits/LPAE. 130 */ 131 #ifdef CONFIG_PHYS_ADDR_T_64BIT 132 if (priv->hw_params->flags & GENET_HAS_40BITS) 133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 134 #endif 135 return addr; 136 } 137 138 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 139 140 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 141 NETIF_MSG_LINK) 142 143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 144 { 145 if (GENET_IS_V1(priv)) 146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 147 else 148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 149 } 150 151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152 { 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 155 else 156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 157 } 158 159 /* These macros are defined to deal with register map change 160 * between GENET1.1 and GENET2. Only those currently being used 161 * by driver are defined. 162 */ 163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 164 { 165 if (GENET_IS_V1(priv)) 166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 167 else 168 return bcmgenet_readl(priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 173 { 174 if (GENET_IS_V1(priv)) 175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 176 else 177 bcmgenet_writel(val, priv->base + 178 priv->hw_params->tbuf_offset + TBUF_CTRL); 179 } 180 181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 182 { 183 if (GENET_IS_V1(priv)) 184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 185 else 186 return bcmgenet_readl(priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 191 { 192 if (GENET_IS_V1(priv)) 193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 194 else 195 bcmgenet_writel(val, priv->base + 196 priv->hw_params->tbuf_offset + TBUF_BP_MC); 197 } 198 199 /* RX/TX DMA register accessors */ 200 enum dma_reg { 201 DMA_RING_CFG = 0, 202 DMA_CTRL, 203 DMA_STATUS, 204 DMA_SCB_BURST_SIZE, 205 DMA_ARB_CTRL, 206 DMA_PRIORITY_0, 207 DMA_PRIORITY_1, 208 DMA_PRIORITY_2, 209 DMA_INDEX2RING_0, 210 DMA_INDEX2RING_1, 211 DMA_INDEX2RING_2, 212 DMA_INDEX2RING_3, 213 DMA_INDEX2RING_4, 214 DMA_INDEX2RING_5, 215 DMA_INDEX2RING_6, 216 DMA_INDEX2RING_7, 217 DMA_RING0_TIMEOUT, 218 DMA_RING1_TIMEOUT, 219 DMA_RING2_TIMEOUT, 220 DMA_RING3_TIMEOUT, 221 DMA_RING4_TIMEOUT, 222 DMA_RING5_TIMEOUT, 223 DMA_RING6_TIMEOUT, 224 DMA_RING7_TIMEOUT, 225 DMA_RING8_TIMEOUT, 226 DMA_RING9_TIMEOUT, 227 DMA_RING10_TIMEOUT, 228 DMA_RING11_TIMEOUT, 229 DMA_RING12_TIMEOUT, 230 DMA_RING13_TIMEOUT, 231 DMA_RING14_TIMEOUT, 232 DMA_RING15_TIMEOUT, 233 DMA_RING16_TIMEOUT, 234 }; 235 236 static const u8 bcmgenet_dma_regs_v3plus[] = { 237 [DMA_RING_CFG] = 0x00, 238 [DMA_CTRL] = 0x04, 239 [DMA_STATUS] = 0x08, 240 [DMA_SCB_BURST_SIZE] = 0x0C, 241 [DMA_ARB_CTRL] = 0x2C, 242 [DMA_PRIORITY_0] = 0x30, 243 [DMA_PRIORITY_1] = 0x34, 244 [DMA_PRIORITY_2] = 0x38, 245 [DMA_RING0_TIMEOUT] = 0x2C, 246 [DMA_RING1_TIMEOUT] = 0x30, 247 [DMA_RING2_TIMEOUT] = 0x34, 248 [DMA_RING3_TIMEOUT] = 0x38, 249 [DMA_RING4_TIMEOUT] = 0x3c, 250 [DMA_RING5_TIMEOUT] = 0x40, 251 [DMA_RING6_TIMEOUT] = 0x44, 252 [DMA_RING7_TIMEOUT] = 0x48, 253 [DMA_RING8_TIMEOUT] = 0x4c, 254 [DMA_RING9_TIMEOUT] = 0x50, 255 [DMA_RING10_TIMEOUT] = 0x54, 256 [DMA_RING11_TIMEOUT] = 0x58, 257 [DMA_RING12_TIMEOUT] = 0x5c, 258 [DMA_RING13_TIMEOUT] = 0x60, 259 [DMA_RING14_TIMEOUT] = 0x64, 260 [DMA_RING15_TIMEOUT] = 0x68, 261 [DMA_RING16_TIMEOUT] = 0x6C, 262 [DMA_INDEX2RING_0] = 0x70, 263 [DMA_INDEX2RING_1] = 0x74, 264 [DMA_INDEX2RING_2] = 0x78, 265 [DMA_INDEX2RING_3] = 0x7C, 266 [DMA_INDEX2RING_4] = 0x80, 267 [DMA_INDEX2RING_5] = 0x84, 268 [DMA_INDEX2RING_6] = 0x88, 269 [DMA_INDEX2RING_7] = 0x8C, 270 }; 271 272 static const u8 bcmgenet_dma_regs_v2[] = { 273 [DMA_RING_CFG] = 0x00, 274 [DMA_CTRL] = 0x04, 275 [DMA_STATUS] = 0x08, 276 [DMA_SCB_BURST_SIZE] = 0x0C, 277 [DMA_ARB_CTRL] = 0x30, 278 [DMA_PRIORITY_0] = 0x34, 279 [DMA_PRIORITY_1] = 0x38, 280 [DMA_PRIORITY_2] = 0x3C, 281 [DMA_RING0_TIMEOUT] = 0x2C, 282 [DMA_RING1_TIMEOUT] = 0x30, 283 [DMA_RING2_TIMEOUT] = 0x34, 284 [DMA_RING3_TIMEOUT] = 0x38, 285 [DMA_RING4_TIMEOUT] = 0x3c, 286 [DMA_RING5_TIMEOUT] = 0x40, 287 [DMA_RING6_TIMEOUT] = 0x44, 288 [DMA_RING7_TIMEOUT] = 0x48, 289 [DMA_RING8_TIMEOUT] = 0x4c, 290 [DMA_RING9_TIMEOUT] = 0x50, 291 [DMA_RING10_TIMEOUT] = 0x54, 292 [DMA_RING11_TIMEOUT] = 0x58, 293 [DMA_RING12_TIMEOUT] = 0x5c, 294 [DMA_RING13_TIMEOUT] = 0x60, 295 [DMA_RING14_TIMEOUT] = 0x64, 296 [DMA_RING15_TIMEOUT] = 0x68, 297 [DMA_RING16_TIMEOUT] = 0x6C, 298 }; 299 300 static const u8 bcmgenet_dma_regs_v1[] = { 301 [DMA_CTRL] = 0x00, 302 [DMA_STATUS] = 0x04, 303 [DMA_SCB_BURST_SIZE] = 0x0C, 304 [DMA_ARB_CTRL] = 0x30, 305 [DMA_PRIORITY_0] = 0x34, 306 [DMA_PRIORITY_1] = 0x38, 307 [DMA_PRIORITY_2] = 0x3C, 308 [DMA_RING0_TIMEOUT] = 0x2C, 309 [DMA_RING1_TIMEOUT] = 0x30, 310 [DMA_RING2_TIMEOUT] = 0x34, 311 [DMA_RING3_TIMEOUT] = 0x38, 312 [DMA_RING4_TIMEOUT] = 0x3c, 313 [DMA_RING5_TIMEOUT] = 0x40, 314 [DMA_RING6_TIMEOUT] = 0x44, 315 [DMA_RING7_TIMEOUT] = 0x48, 316 [DMA_RING8_TIMEOUT] = 0x4c, 317 [DMA_RING9_TIMEOUT] = 0x50, 318 [DMA_RING10_TIMEOUT] = 0x54, 319 [DMA_RING11_TIMEOUT] = 0x58, 320 [DMA_RING12_TIMEOUT] = 0x5c, 321 [DMA_RING13_TIMEOUT] = 0x60, 322 [DMA_RING14_TIMEOUT] = 0x64, 323 [DMA_RING15_TIMEOUT] = 0x68, 324 [DMA_RING16_TIMEOUT] = 0x6C, 325 }; 326 327 /* Set at runtime once bcmgenet version is known */ 328 static const u8 *bcmgenet_dma_regs; 329 330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 331 { 332 return netdev_priv(dev_get_drvdata(dev)); 333 } 334 335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 336 enum dma_reg r) 337 { 338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340 } 341 342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 343 u32 val, enum dma_reg r) 344 { 345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 347 } 348 349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 350 enum dma_reg r) 351 { 352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 354 } 355 356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 357 u32 val, enum dma_reg r) 358 { 359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 361 } 362 363 /* RDMA/TDMA ring registers and accessors 364 * we merge the common fields and just prefix with T/D the registers 365 * having different meaning depending on the direction 366 */ 367 enum dma_ring_reg { 368 TDMA_READ_PTR = 0, 369 RDMA_WRITE_PTR = TDMA_READ_PTR, 370 TDMA_READ_PTR_HI, 371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 372 TDMA_CONS_INDEX, 373 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 374 TDMA_PROD_INDEX, 375 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 376 DMA_RING_BUF_SIZE, 377 DMA_START_ADDR, 378 DMA_START_ADDR_HI, 379 DMA_END_ADDR, 380 DMA_END_ADDR_HI, 381 DMA_MBUF_DONE_THRESH, 382 TDMA_FLOW_PERIOD, 383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 384 TDMA_WRITE_PTR, 385 RDMA_READ_PTR = TDMA_WRITE_PTR, 386 TDMA_WRITE_PTR_HI, 387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 388 }; 389 390 /* GENET v4 supports 40-bits pointer addressing 391 * for obvious reasons the LO and HI word parts 392 * are contiguous, but this offsets the other 393 * registers. 394 */ 395 static const u8 genet_dma_ring_regs_v4[] = { 396 [TDMA_READ_PTR] = 0x00, 397 [TDMA_READ_PTR_HI] = 0x04, 398 [TDMA_CONS_INDEX] = 0x08, 399 [TDMA_PROD_INDEX] = 0x0C, 400 [DMA_RING_BUF_SIZE] = 0x10, 401 [DMA_START_ADDR] = 0x14, 402 [DMA_START_ADDR_HI] = 0x18, 403 [DMA_END_ADDR] = 0x1C, 404 [DMA_END_ADDR_HI] = 0x20, 405 [DMA_MBUF_DONE_THRESH] = 0x24, 406 [TDMA_FLOW_PERIOD] = 0x28, 407 [TDMA_WRITE_PTR] = 0x2C, 408 [TDMA_WRITE_PTR_HI] = 0x30, 409 }; 410 411 static const u8 genet_dma_ring_regs_v123[] = { 412 [TDMA_READ_PTR] = 0x00, 413 [TDMA_CONS_INDEX] = 0x04, 414 [TDMA_PROD_INDEX] = 0x08, 415 [DMA_RING_BUF_SIZE] = 0x0C, 416 [DMA_START_ADDR] = 0x10, 417 [DMA_END_ADDR] = 0x14, 418 [DMA_MBUF_DONE_THRESH] = 0x18, 419 [TDMA_FLOW_PERIOD] = 0x1C, 420 [TDMA_WRITE_PTR] = 0x20, 421 }; 422 423 /* Set at runtime once GENET version is known */ 424 static const u8 *genet_dma_ring_regs; 425 426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 427 unsigned int ring, 428 enum dma_ring_reg r) 429 { 430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433 } 434 435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 436 unsigned int ring, u32 val, 437 enum dma_ring_reg r) 438 { 439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442 } 443 444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 445 unsigned int ring, 446 enum dma_ring_reg r) 447 { 448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451 } 452 453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 454 unsigned int ring, u32 val, 455 enum dma_ring_reg r) 456 { 457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 458 (DMA_RING_SIZE * ring) + 459 genet_dma_ring_regs[r]); 460 } 461 462 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 463 { 464 u32 offset; 465 u32 reg; 466 467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 468 reg = bcmgenet_hfb_reg_readl(priv, offset); 469 reg |= (1 << (f_index % 32)); 470 bcmgenet_hfb_reg_writel(priv, reg, offset); 471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 472 reg |= RBUF_HFB_EN; 473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 474 } 475 476 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 477 { 478 u32 offset, reg, reg1; 479 480 offset = HFB_FLT_ENABLE_V3PLUS; 481 reg = bcmgenet_hfb_reg_readl(priv, offset); 482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 483 if (f_index < 32) { 484 reg1 &= ~(1 << (f_index % 32)); 485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 486 } else { 487 reg &= ~(1 << (f_index % 32)); 488 bcmgenet_hfb_reg_writel(priv, reg, offset); 489 } 490 if (!reg && !reg1) { 491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 492 reg &= ~RBUF_HFB_EN; 493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 494 } 495 } 496 497 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 498 u32 f_index, u32 rx_queue) 499 { 500 u32 offset; 501 u32 reg; 502 503 offset = f_index / 8; 504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 505 reg &= ~(0xF << (4 * (f_index % 8))); 506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 508 } 509 510 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 511 u32 f_index, u32 f_length) 512 { 513 u32 offset; 514 u32 reg; 515 516 offset = HFB_FLT_LEN_V3PLUS + 517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) * 518 sizeof(u32); 519 reg = bcmgenet_hfb_reg_readl(priv, offset); 520 reg &= ~(0xFF << (8 * (f_index % 4))); 521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 522 bcmgenet_hfb_reg_writel(priv, reg, offset); 523 } 524 525 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 526 { 527 while (size) { 528 switch (*(unsigned char *)mask++) { 529 case 0x00: 530 case 0x0f: 531 case 0xf0: 532 case 0xff: 533 size--; 534 continue; 535 default: 536 return -EINVAL; 537 } 538 } 539 540 return 0; 541 } 542 543 #define VALIDATE_MASK(x) \ 544 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 545 546 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index, 547 u32 offset, void *val, void *mask, 548 size_t size) 549 { 550 u32 index, tmp; 551 552 index = f_index * priv->hw_params->hfb_filter_size + offset / 2; 553 tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32)); 554 555 while (size--) { 556 if (offset++ & 1) { 557 tmp &= ~0x300FF; 558 tmp |= (*(unsigned char *)val++); 559 switch ((*(unsigned char *)mask++)) { 560 case 0xFF: 561 tmp |= 0x30000; 562 break; 563 case 0xF0: 564 tmp |= 0x20000; 565 break; 566 case 0x0F: 567 tmp |= 0x10000; 568 break; 569 } 570 bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32)); 571 if (size) 572 tmp = bcmgenet_hfb_readl(priv, 573 index * sizeof(u32)); 574 } else { 575 tmp &= ~0xCFF00; 576 tmp |= (*(unsigned char *)val++) << 8; 577 switch ((*(unsigned char *)mask++)) { 578 case 0xFF: 579 tmp |= 0xC0000; 580 break; 581 case 0xF0: 582 tmp |= 0x80000; 583 break; 584 case 0x0F: 585 tmp |= 0x40000; 586 break; 587 } 588 if (!size) 589 bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32)); 590 } 591 } 592 593 return 0; 594 } 595 596 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 597 struct bcmgenet_rxnfc_rule *rule) 598 { 599 struct ethtool_rx_flow_spec *fs = &rule->fs; 600 u32 offset = 0, f_length = 0, f; 601 u8 val_8, mask_8; 602 __be16 val_16; 603 u16 mask_16; 604 size_t size; 605 606 f = fs->location; 607 if (fs->flow_type & FLOW_MAC_EXT) { 608 bcmgenet_hfb_insert_data(priv, f, 0, 609 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 610 sizeof(fs->h_ext.h_dest)); 611 } 612 613 if (fs->flow_type & FLOW_EXT) { 614 if (fs->m_ext.vlan_etype || 615 fs->m_ext.vlan_tci) { 616 bcmgenet_hfb_insert_data(priv, f, 12, 617 &fs->h_ext.vlan_etype, 618 &fs->m_ext.vlan_etype, 619 sizeof(fs->h_ext.vlan_etype)); 620 bcmgenet_hfb_insert_data(priv, f, 14, 621 &fs->h_ext.vlan_tci, 622 &fs->m_ext.vlan_tci, 623 sizeof(fs->h_ext.vlan_tci)); 624 offset += VLAN_HLEN; 625 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 626 } 627 } 628 629 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 630 case ETHER_FLOW: 631 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 632 bcmgenet_hfb_insert_data(priv, f, 0, 633 &fs->h_u.ether_spec.h_dest, 634 &fs->m_u.ether_spec.h_dest, 635 sizeof(fs->h_u.ether_spec.h_dest)); 636 bcmgenet_hfb_insert_data(priv, f, ETH_ALEN, 637 &fs->h_u.ether_spec.h_source, 638 &fs->m_u.ether_spec.h_source, 639 sizeof(fs->h_u.ether_spec.h_source)); 640 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 641 &fs->h_u.ether_spec.h_proto, 642 &fs->m_u.ether_spec.h_proto, 643 sizeof(fs->h_u.ether_spec.h_proto)); 644 break; 645 case IP_USER_FLOW: 646 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 647 /* Specify IP Ether Type */ 648 val_16 = htons(ETH_P_IP); 649 mask_16 = 0xFFFF; 650 bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset, 651 &val_16, &mask_16, sizeof(val_16)); 652 bcmgenet_hfb_insert_data(priv, f, 15 + offset, 653 &fs->h_u.usr_ip4_spec.tos, 654 &fs->m_u.usr_ip4_spec.tos, 655 sizeof(fs->h_u.usr_ip4_spec.tos)); 656 bcmgenet_hfb_insert_data(priv, f, 23 + offset, 657 &fs->h_u.usr_ip4_spec.proto, 658 &fs->m_u.usr_ip4_spec.proto, 659 sizeof(fs->h_u.usr_ip4_spec.proto)); 660 bcmgenet_hfb_insert_data(priv, f, 26 + offset, 661 &fs->h_u.usr_ip4_spec.ip4src, 662 &fs->m_u.usr_ip4_spec.ip4src, 663 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 664 bcmgenet_hfb_insert_data(priv, f, 30 + offset, 665 &fs->h_u.usr_ip4_spec.ip4dst, 666 &fs->m_u.usr_ip4_spec.ip4dst, 667 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 668 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 669 break; 670 671 /* Only supports 20 byte IPv4 header */ 672 val_8 = 0x45; 673 mask_8 = 0xFF; 674 bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset, 675 &val_8, &mask_8, 676 sizeof(val_8)); 677 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 678 bcmgenet_hfb_insert_data(priv, f, 679 ETH_HLEN + 20 + offset, 680 &fs->h_u.usr_ip4_spec.l4_4_bytes, 681 &fs->m_u.usr_ip4_spec.l4_4_bytes, 682 size); 683 f_length += DIV_ROUND_UP(size, 2); 684 break; 685 } 686 687 bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length); 688 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) { 689 /* Ring 0 flows can be handled by the default Descriptor Ring 690 * We'll map them to ring 0, but don't enable the filter 691 */ 692 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0); 693 rule->state = BCMGENET_RXNFC_STATE_DISABLED; 694 } else { 695 /* Other Rx rings are direct mapped here */ 696 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 697 fs->ring_cookie); 698 bcmgenet_hfb_enable_filter(priv, f); 699 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 700 } 701 } 702 703 /* bcmgenet_hfb_clear 704 * 705 * Clear Hardware Filter Block and disable all filtering. 706 */ 707 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index) 708 { 709 u32 base, i; 710 711 base = f_index * priv->hw_params->hfb_filter_size; 712 for (i = 0; i < priv->hw_params->hfb_filter_size; i++) 713 bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32)); 714 } 715 716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 717 { 718 u32 i; 719 720 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 721 return; 722 723 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 724 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 725 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 726 727 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 728 bcmgenet_rdma_writel(priv, 0x0, i); 729 730 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 731 bcmgenet_hfb_reg_writel(priv, 0x0, 732 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 733 734 for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++) 735 bcmgenet_hfb_clear_filter(priv, i); 736 } 737 738 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 739 { 740 int i; 741 742 INIT_LIST_HEAD(&priv->rxnfc_list); 743 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 744 return; 745 746 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 747 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 748 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 749 } 750 751 bcmgenet_hfb_clear(priv); 752 } 753 754 static int bcmgenet_begin(struct net_device *dev) 755 { 756 struct bcmgenet_priv *priv = netdev_priv(dev); 757 758 /* Turn on the clock */ 759 return clk_prepare_enable(priv->clk); 760 } 761 762 static void bcmgenet_complete(struct net_device *dev) 763 { 764 struct bcmgenet_priv *priv = netdev_priv(dev); 765 766 /* Turn off the clock */ 767 clk_disable_unprepare(priv->clk); 768 } 769 770 static int bcmgenet_get_link_ksettings(struct net_device *dev, 771 struct ethtool_link_ksettings *cmd) 772 { 773 if (!netif_running(dev)) 774 return -EINVAL; 775 776 if (!dev->phydev) 777 return -ENODEV; 778 779 phy_ethtool_ksettings_get(dev->phydev, cmd); 780 781 return 0; 782 } 783 784 static int bcmgenet_set_link_ksettings(struct net_device *dev, 785 const struct ethtool_link_ksettings *cmd) 786 { 787 if (!netif_running(dev)) 788 return -EINVAL; 789 790 if (!dev->phydev) 791 return -ENODEV; 792 793 return phy_ethtool_ksettings_set(dev->phydev, cmd); 794 } 795 796 static int bcmgenet_set_features(struct net_device *dev, 797 netdev_features_t features) 798 { 799 struct bcmgenet_priv *priv = netdev_priv(dev); 800 u32 reg; 801 int ret; 802 803 ret = clk_prepare_enable(priv->clk); 804 if (ret) 805 return ret; 806 807 /* Make sure we reflect the value of CRC_CMD_FWD */ 808 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 809 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 810 811 clk_disable_unprepare(priv->clk); 812 813 return ret; 814 } 815 816 static u32 bcmgenet_get_msglevel(struct net_device *dev) 817 { 818 struct bcmgenet_priv *priv = netdev_priv(dev); 819 820 return priv->msg_enable; 821 } 822 823 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 824 { 825 struct bcmgenet_priv *priv = netdev_priv(dev); 826 827 priv->msg_enable = level; 828 } 829 830 static int bcmgenet_get_coalesce(struct net_device *dev, 831 struct ethtool_coalesce *ec, 832 struct kernel_ethtool_coalesce *kernel_coal, 833 struct netlink_ext_ack *extack) 834 { 835 struct bcmgenet_priv *priv = netdev_priv(dev); 836 struct bcmgenet_rx_ring *ring; 837 unsigned int i; 838 839 ec->tx_max_coalesced_frames = 840 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 841 DMA_MBUF_DONE_THRESH); 842 ec->rx_max_coalesced_frames = 843 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 844 DMA_MBUF_DONE_THRESH); 845 ec->rx_coalesce_usecs = 846 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 847 848 for (i = 0; i < priv->hw_params->rx_queues; i++) { 849 ring = &priv->rx_rings[i]; 850 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 851 } 852 ring = &priv->rx_rings[DESC_INDEX]; 853 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 854 855 return 0; 856 } 857 858 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 859 u32 usecs, u32 pkts) 860 { 861 struct bcmgenet_priv *priv = ring->priv; 862 unsigned int i = ring->index; 863 u32 reg; 864 865 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 866 867 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 868 reg &= ~DMA_TIMEOUT_MASK; 869 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 870 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 871 } 872 873 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 874 struct ethtool_coalesce *ec) 875 { 876 struct dim_cq_moder moder; 877 u32 usecs, pkts; 878 879 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 880 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 881 usecs = ring->rx_coalesce_usecs; 882 pkts = ring->rx_max_coalesced_frames; 883 884 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 885 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 886 usecs = moder.usec; 887 pkts = moder.pkts; 888 } 889 890 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 891 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 892 } 893 894 static int bcmgenet_set_coalesce(struct net_device *dev, 895 struct ethtool_coalesce *ec, 896 struct kernel_ethtool_coalesce *kernel_coal, 897 struct netlink_ext_ack *extack) 898 { 899 struct bcmgenet_priv *priv = netdev_priv(dev); 900 unsigned int i; 901 902 /* Base system clock is 125Mhz, DMA timeout is this reference clock 903 * divided by 1024, which yields roughly 8.192us, our maximum value 904 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 905 */ 906 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 907 ec->tx_max_coalesced_frames == 0 || 908 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 909 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 910 return -EINVAL; 911 912 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 913 return -EINVAL; 914 915 /* GENET TDMA hardware does not support a configurable timeout, but will 916 * always generate an interrupt either after MBDONE packets have been 917 * transmitted, or when the ring is empty. 918 */ 919 920 /* Program all TX queues with the same values, as there is no 921 * ethtool knob to do coalescing on a per-queue basis 922 */ 923 for (i = 0; i < priv->hw_params->tx_queues; i++) 924 bcmgenet_tdma_ring_writel(priv, i, 925 ec->tx_max_coalesced_frames, 926 DMA_MBUF_DONE_THRESH); 927 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 928 ec->tx_max_coalesced_frames, 929 DMA_MBUF_DONE_THRESH); 930 931 for (i = 0; i < priv->hw_params->rx_queues; i++) 932 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 933 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 934 935 return 0; 936 } 937 938 /* standard ethtool support functions. */ 939 enum bcmgenet_stat_type { 940 BCMGENET_STAT_NETDEV = -1, 941 BCMGENET_STAT_MIB_RX, 942 BCMGENET_STAT_MIB_TX, 943 BCMGENET_STAT_RUNT, 944 BCMGENET_STAT_MISC, 945 BCMGENET_STAT_SOFT, 946 }; 947 948 struct bcmgenet_stats { 949 char stat_string[ETH_GSTRING_LEN]; 950 int stat_sizeof; 951 int stat_offset; 952 enum bcmgenet_stat_type type; 953 /* reg offset from UMAC base for misc counters */ 954 u16 reg_offset; 955 }; 956 957 #define STAT_NETDEV(m) { \ 958 .stat_string = __stringify(m), \ 959 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 960 .stat_offset = offsetof(struct net_device_stats, m), \ 961 .type = BCMGENET_STAT_NETDEV, \ 962 } 963 964 #define STAT_GENET_MIB(str, m, _type) { \ 965 .stat_string = str, \ 966 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 967 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 968 .type = _type, \ 969 } 970 971 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 972 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 973 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 974 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 975 976 #define STAT_GENET_MISC(str, m, offset) { \ 977 .stat_string = str, \ 978 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 979 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 980 .type = BCMGENET_STAT_MISC, \ 981 .reg_offset = offset, \ 982 } 983 984 #define STAT_GENET_Q(num) \ 985 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 986 tx_rings[num].packets), \ 987 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 988 tx_rings[num].bytes), \ 989 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 990 rx_rings[num].bytes), \ 991 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 992 rx_rings[num].packets), \ 993 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 994 rx_rings[num].errors), \ 995 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 996 rx_rings[num].dropped) 997 998 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 999 * between the end of TX stats and the beginning of the RX RUNT 1000 */ 1001 #define BCMGENET_STAT_OFFSET 0xc 1002 1003 /* Hardware counters must be kept in sync because the order/offset 1004 * is important here (order in structure declaration = order in hardware) 1005 */ 1006 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1007 /* general stats */ 1008 STAT_NETDEV(rx_packets), 1009 STAT_NETDEV(tx_packets), 1010 STAT_NETDEV(rx_bytes), 1011 STAT_NETDEV(tx_bytes), 1012 STAT_NETDEV(rx_errors), 1013 STAT_NETDEV(tx_errors), 1014 STAT_NETDEV(rx_dropped), 1015 STAT_NETDEV(tx_dropped), 1016 STAT_NETDEV(multicast), 1017 /* UniMAC RSV counters */ 1018 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1019 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1020 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1021 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1022 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1023 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1024 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1025 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1026 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1027 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1028 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1029 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1030 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1031 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1032 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1033 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1034 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1035 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1036 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1037 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1038 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1039 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1040 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1041 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1042 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1043 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1044 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1045 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1046 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1047 /* UniMAC TSV counters */ 1048 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1049 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1050 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1051 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1052 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1053 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1054 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1055 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1056 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1057 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1058 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1059 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1060 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1061 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1062 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1063 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1064 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1065 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1066 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1067 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1068 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1069 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1070 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1071 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1072 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1073 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1074 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1075 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1076 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1077 /* UniMAC RUNT counters */ 1078 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1079 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1080 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1081 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1082 /* Misc UniMAC counters */ 1083 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1084 UMAC_RBUF_OVFL_CNT_V1), 1085 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1086 UMAC_RBUF_ERR_CNT_V1), 1087 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1088 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1089 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1090 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1091 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1092 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1093 mib.tx_realloc_tsb_failed), 1094 /* Per TX queues */ 1095 STAT_GENET_Q(0), 1096 STAT_GENET_Q(1), 1097 STAT_GENET_Q(2), 1098 STAT_GENET_Q(3), 1099 STAT_GENET_Q(16), 1100 }; 1101 1102 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1103 1104 static void bcmgenet_get_drvinfo(struct net_device *dev, 1105 struct ethtool_drvinfo *info) 1106 { 1107 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 1108 } 1109 1110 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1111 { 1112 switch (string_set) { 1113 case ETH_SS_STATS: 1114 return BCMGENET_STATS_LEN; 1115 default: 1116 return -EOPNOTSUPP; 1117 } 1118 } 1119 1120 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1121 u8 *data) 1122 { 1123 int i; 1124 1125 switch (stringset) { 1126 case ETH_SS_STATS: 1127 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1128 memcpy(data + i * ETH_GSTRING_LEN, 1129 bcmgenet_gstrings_stats[i].stat_string, 1130 ETH_GSTRING_LEN); 1131 } 1132 break; 1133 } 1134 } 1135 1136 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1137 { 1138 u16 new_offset; 1139 u32 val; 1140 1141 switch (offset) { 1142 case UMAC_RBUF_OVFL_CNT_V1: 1143 if (GENET_IS_V2(priv)) 1144 new_offset = RBUF_OVFL_CNT_V2; 1145 else 1146 new_offset = RBUF_OVFL_CNT_V3PLUS; 1147 1148 val = bcmgenet_rbuf_readl(priv, new_offset); 1149 /* clear if overflowed */ 1150 if (val == ~0) 1151 bcmgenet_rbuf_writel(priv, 0, new_offset); 1152 break; 1153 case UMAC_RBUF_ERR_CNT_V1: 1154 if (GENET_IS_V2(priv)) 1155 new_offset = RBUF_ERR_CNT_V2; 1156 else 1157 new_offset = RBUF_ERR_CNT_V3PLUS; 1158 1159 val = bcmgenet_rbuf_readl(priv, new_offset); 1160 /* clear if overflowed */ 1161 if (val == ~0) 1162 bcmgenet_rbuf_writel(priv, 0, new_offset); 1163 break; 1164 default: 1165 val = bcmgenet_umac_readl(priv, offset); 1166 /* clear if overflowed */ 1167 if (val == ~0) 1168 bcmgenet_umac_writel(priv, 0, offset); 1169 break; 1170 } 1171 1172 return val; 1173 } 1174 1175 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1176 { 1177 int i, j = 0; 1178 1179 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1180 const struct bcmgenet_stats *s; 1181 u8 offset = 0; 1182 u32 val = 0; 1183 char *p; 1184 1185 s = &bcmgenet_gstrings_stats[i]; 1186 switch (s->type) { 1187 case BCMGENET_STAT_NETDEV: 1188 case BCMGENET_STAT_SOFT: 1189 continue; 1190 case BCMGENET_STAT_RUNT: 1191 offset += BCMGENET_STAT_OFFSET; 1192 fallthrough; 1193 case BCMGENET_STAT_MIB_TX: 1194 offset += BCMGENET_STAT_OFFSET; 1195 fallthrough; 1196 case BCMGENET_STAT_MIB_RX: 1197 val = bcmgenet_umac_readl(priv, 1198 UMAC_MIB_START + j + offset); 1199 offset = 0; /* Reset Offset */ 1200 break; 1201 case BCMGENET_STAT_MISC: 1202 if (GENET_IS_V1(priv)) { 1203 val = bcmgenet_umac_readl(priv, s->reg_offset); 1204 /* clear if overflowed */ 1205 if (val == ~0) 1206 bcmgenet_umac_writel(priv, 0, 1207 s->reg_offset); 1208 } else { 1209 val = bcmgenet_update_stat_misc(priv, 1210 s->reg_offset); 1211 } 1212 break; 1213 } 1214 1215 j += s->stat_sizeof; 1216 p = (char *)priv + s->stat_offset; 1217 *(u32 *)p = val; 1218 } 1219 } 1220 1221 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1222 struct ethtool_stats *stats, 1223 u64 *data) 1224 { 1225 struct bcmgenet_priv *priv = netdev_priv(dev); 1226 int i; 1227 1228 if (netif_running(dev)) 1229 bcmgenet_update_mib_counters(priv); 1230 1231 dev->netdev_ops->ndo_get_stats(dev); 1232 1233 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1234 const struct bcmgenet_stats *s; 1235 char *p; 1236 1237 s = &bcmgenet_gstrings_stats[i]; 1238 if (s->type == BCMGENET_STAT_NETDEV) 1239 p = (char *)&dev->stats; 1240 else 1241 p = (char *)priv; 1242 p += s->stat_offset; 1243 if (sizeof(unsigned long) != sizeof(u32) && 1244 s->stat_sizeof == sizeof(unsigned long)) 1245 data[i] = *(unsigned long *)p; 1246 else 1247 data[i] = *(u32 *)p; 1248 } 1249 } 1250 1251 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1252 { 1253 struct bcmgenet_priv *priv = netdev_priv(dev); 1254 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1255 u32 reg; 1256 1257 if (enable && !priv->clk_eee_enabled) { 1258 clk_prepare_enable(priv->clk_eee); 1259 priv->clk_eee_enabled = true; 1260 } 1261 1262 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1263 if (enable) 1264 reg |= EEE_EN; 1265 else 1266 reg &= ~EEE_EN; 1267 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1268 1269 /* Enable EEE and switch to a 27Mhz clock automatically */ 1270 reg = bcmgenet_readl(priv->base + off); 1271 if (enable) 1272 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1273 else 1274 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1275 bcmgenet_writel(reg, priv->base + off); 1276 1277 /* Do the same for thing for RBUF */ 1278 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1279 if (enable) 1280 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1281 else 1282 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1283 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1284 1285 if (!enable && priv->clk_eee_enabled) { 1286 clk_disable_unprepare(priv->clk_eee); 1287 priv->clk_eee_enabled = false; 1288 } 1289 1290 priv->eee.eee_enabled = enable; 1291 priv->eee.eee_active = enable; 1292 } 1293 1294 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1295 { 1296 struct bcmgenet_priv *priv = netdev_priv(dev); 1297 struct ethtool_eee *p = &priv->eee; 1298 1299 if (GENET_IS_V1(priv)) 1300 return -EOPNOTSUPP; 1301 1302 if (!dev->phydev) 1303 return -ENODEV; 1304 1305 e->eee_enabled = p->eee_enabled; 1306 e->eee_active = p->eee_active; 1307 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1308 1309 return phy_ethtool_get_eee(dev->phydev, e); 1310 } 1311 1312 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1313 { 1314 struct bcmgenet_priv *priv = netdev_priv(dev); 1315 struct ethtool_eee *p = &priv->eee; 1316 int ret = 0; 1317 1318 if (GENET_IS_V1(priv)) 1319 return -EOPNOTSUPP; 1320 1321 if (!dev->phydev) 1322 return -ENODEV; 1323 1324 p->eee_enabled = e->eee_enabled; 1325 1326 if (!p->eee_enabled) { 1327 bcmgenet_eee_enable_set(dev, false); 1328 } else { 1329 ret = phy_init_eee(dev->phydev, 0); 1330 if (ret) { 1331 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1332 return ret; 1333 } 1334 1335 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1336 bcmgenet_eee_enable_set(dev, true); 1337 } 1338 1339 return phy_ethtool_set_eee(dev->phydev, e); 1340 } 1341 1342 static int bcmgenet_validate_flow(struct net_device *dev, 1343 struct ethtool_rxnfc *cmd) 1344 { 1345 struct ethtool_usrip4_spec *l4_mask; 1346 struct ethhdr *eth_mask; 1347 1348 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) { 1349 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1350 cmd->fs.location); 1351 return -EINVAL; 1352 } 1353 1354 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1355 case IP_USER_FLOW: 1356 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1357 /* don't allow mask which isn't valid */ 1358 if (VALIDATE_MASK(l4_mask->ip4src) || 1359 VALIDATE_MASK(l4_mask->ip4dst) || 1360 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1361 VALIDATE_MASK(l4_mask->proto) || 1362 VALIDATE_MASK(l4_mask->ip_ver) || 1363 VALIDATE_MASK(l4_mask->tos)) { 1364 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1365 return -EINVAL; 1366 } 1367 break; 1368 case ETHER_FLOW: 1369 eth_mask = &cmd->fs.m_u.ether_spec; 1370 /* don't allow mask which isn't valid */ 1371 if (VALIDATE_MASK(eth_mask->h_dest) || 1372 VALIDATE_MASK(eth_mask->h_source) || 1373 VALIDATE_MASK(eth_mask->h_proto)) { 1374 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1375 return -EINVAL; 1376 } 1377 break; 1378 default: 1379 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1380 cmd->fs.flow_type); 1381 return -EINVAL; 1382 } 1383 1384 if ((cmd->fs.flow_type & FLOW_EXT)) { 1385 /* don't allow mask which isn't valid */ 1386 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1387 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1388 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1389 return -EINVAL; 1390 } 1391 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1392 netdev_err(dev, "rxnfc: user-def not supported\n"); 1393 return -EINVAL; 1394 } 1395 } 1396 1397 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1398 /* don't allow mask which isn't valid */ 1399 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1400 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1401 return -EINVAL; 1402 } 1403 } 1404 1405 return 0; 1406 } 1407 1408 static int bcmgenet_insert_flow(struct net_device *dev, 1409 struct ethtool_rxnfc *cmd) 1410 { 1411 struct bcmgenet_priv *priv = netdev_priv(dev); 1412 struct bcmgenet_rxnfc_rule *loc_rule; 1413 int err; 1414 1415 if (priv->hw_params->hfb_filter_size < 128) { 1416 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1417 return -EINVAL; 1418 } 1419 1420 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1421 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) { 1422 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1423 cmd->fs.ring_cookie); 1424 return -EINVAL; 1425 } 1426 1427 err = bcmgenet_validate_flow(dev, cmd); 1428 if (err) 1429 return err; 1430 1431 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1432 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1433 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1434 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1435 list_del(&loc_rule->list); 1436 bcmgenet_hfb_clear_filter(priv, cmd->fs.location); 1437 } 1438 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1439 memcpy(&loc_rule->fs, &cmd->fs, 1440 sizeof(struct ethtool_rx_flow_spec)); 1441 1442 bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1443 1444 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1445 1446 return 0; 1447 } 1448 1449 static int bcmgenet_delete_flow(struct net_device *dev, 1450 struct ethtool_rxnfc *cmd) 1451 { 1452 struct bcmgenet_priv *priv = netdev_priv(dev); 1453 struct bcmgenet_rxnfc_rule *rule; 1454 int err = 0; 1455 1456 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1457 return -EINVAL; 1458 1459 rule = &priv->rxnfc_rules[cmd->fs.location]; 1460 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1461 err = -ENOENT; 1462 goto out; 1463 } 1464 1465 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1466 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1467 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) { 1468 list_del(&rule->list); 1469 bcmgenet_hfb_clear_filter(priv, cmd->fs.location); 1470 } 1471 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1472 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1473 1474 out: 1475 return err; 1476 } 1477 1478 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1479 { 1480 struct bcmgenet_priv *priv = netdev_priv(dev); 1481 int err = 0; 1482 1483 switch (cmd->cmd) { 1484 case ETHTOOL_SRXCLSRLINS: 1485 err = bcmgenet_insert_flow(dev, cmd); 1486 break; 1487 case ETHTOOL_SRXCLSRLDEL: 1488 err = bcmgenet_delete_flow(dev, cmd); 1489 break; 1490 default: 1491 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1492 cmd->cmd); 1493 return -EINVAL; 1494 } 1495 1496 return err; 1497 } 1498 1499 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1500 int loc) 1501 { 1502 struct bcmgenet_priv *priv = netdev_priv(dev); 1503 struct bcmgenet_rxnfc_rule *rule; 1504 int err = 0; 1505 1506 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1507 return -EINVAL; 1508 1509 rule = &priv->rxnfc_rules[loc]; 1510 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1511 err = -ENOENT; 1512 else 1513 memcpy(&cmd->fs, &rule->fs, 1514 sizeof(struct ethtool_rx_flow_spec)); 1515 1516 return err; 1517 } 1518 1519 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1520 { 1521 struct list_head *pos; 1522 int res = 0; 1523 1524 list_for_each(pos, &priv->rxnfc_list) 1525 res++; 1526 1527 return res; 1528 } 1529 1530 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1531 u32 *rule_locs) 1532 { 1533 struct bcmgenet_priv *priv = netdev_priv(dev); 1534 struct bcmgenet_rxnfc_rule *rule; 1535 int err = 0; 1536 int i = 0; 1537 1538 switch (cmd->cmd) { 1539 case ETHTOOL_GRXRINGS: 1540 cmd->data = priv->hw_params->rx_queues ?: 1; 1541 break; 1542 case ETHTOOL_GRXCLSRLCNT: 1543 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1544 cmd->data = MAX_NUM_OF_FS_RULES; 1545 break; 1546 case ETHTOOL_GRXCLSRULE: 1547 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1548 break; 1549 case ETHTOOL_GRXCLSRLALL: 1550 list_for_each_entry(rule, &priv->rxnfc_list, list) 1551 if (i < cmd->rule_cnt) 1552 rule_locs[i++] = rule->fs.location; 1553 cmd->rule_cnt = i; 1554 cmd->data = MAX_NUM_OF_FS_RULES; 1555 break; 1556 default: 1557 err = -EOPNOTSUPP; 1558 break; 1559 } 1560 1561 return err; 1562 } 1563 1564 /* standard ethtool support functions. */ 1565 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1566 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1567 ETHTOOL_COALESCE_MAX_FRAMES | 1568 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1569 .begin = bcmgenet_begin, 1570 .complete = bcmgenet_complete, 1571 .get_strings = bcmgenet_get_strings, 1572 .get_sset_count = bcmgenet_get_sset_count, 1573 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1574 .get_drvinfo = bcmgenet_get_drvinfo, 1575 .get_link = ethtool_op_get_link, 1576 .get_msglevel = bcmgenet_get_msglevel, 1577 .set_msglevel = bcmgenet_set_msglevel, 1578 .get_wol = bcmgenet_get_wol, 1579 .set_wol = bcmgenet_set_wol, 1580 .get_eee = bcmgenet_get_eee, 1581 .set_eee = bcmgenet_set_eee, 1582 .nway_reset = phy_ethtool_nway_reset, 1583 .get_coalesce = bcmgenet_get_coalesce, 1584 .set_coalesce = bcmgenet_set_coalesce, 1585 .get_link_ksettings = bcmgenet_get_link_ksettings, 1586 .set_link_ksettings = bcmgenet_set_link_ksettings, 1587 .get_ts_info = ethtool_op_get_ts_info, 1588 .get_rxnfc = bcmgenet_get_rxnfc, 1589 .set_rxnfc = bcmgenet_set_rxnfc, 1590 }; 1591 1592 /* Power down the unimac, based on mode. */ 1593 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1594 enum bcmgenet_power_mode mode) 1595 { 1596 int ret = 0; 1597 u32 reg; 1598 1599 switch (mode) { 1600 case GENET_POWER_CABLE_SENSE: 1601 phy_detach(priv->dev->phydev); 1602 break; 1603 1604 case GENET_POWER_WOL_MAGIC: 1605 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1606 break; 1607 1608 case GENET_POWER_PASSIVE: 1609 /* Power down LED */ 1610 if (priv->hw_params->flags & GENET_HAS_EXT) { 1611 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1612 if (GENET_IS_V5(priv)) 1613 reg |= EXT_PWR_DOWN_PHY_EN | 1614 EXT_PWR_DOWN_PHY_RD | 1615 EXT_PWR_DOWN_PHY_SD | 1616 EXT_PWR_DOWN_PHY_RX | 1617 EXT_PWR_DOWN_PHY_TX | 1618 EXT_IDDQ_GLBL_PWR; 1619 else 1620 reg |= EXT_PWR_DOWN_PHY; 1621 1622 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1623 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1624 1625 bcmgenet_phy_power_set(priv->dev, false); 1626 } 1627 break; 1628 default: 1629 break; 1630 } 1631 1632 return ret; 1633 } 1634 1635 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1636 enum bcmgenet_power_mode mode) 1637 { 1638 u32 reg; 1639 1640 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1641 return; 1642 1643 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1644 1645 switch (mode) { 1646 case GENET_POWER_PASSIVE: 1647 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS | 1648 EXT_ENERGY_DET_MASK); 1649 if (GENET_IS_V5(priv)) { 1650 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1651 EXT_PWR_DOWN_PHY_RD | 1652 EXT_PWR_DOWN_PHY_SD | 1653 EXT_PWR_DOWN_PHY_RX | 1654 EXT_PWR_DOWN_PHY_TX | 1655 EXT_IDDQ_GLBL_PWR); 1656 reg |= EXT_PHY_RESET; 1657 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1658 mdelay(1); 1659 1660 reg &= ~EXT_PHY_RESET; 1661 } else { 1662 reg &= ~EXT_PWR_DOWN_PHY; 1663 reg |= EXT_PWR_DN_EN_LD; 1664 } 1665 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1666 bcmgenet_phy_power_set(priv->dev, true); 1667 break; 1668 1669 case GENET_POWER_CABLE_SENSE: 1670 /* enable APD */ 1671 if (!GENET_IS_V5(priv)) { 1672 reg |= EXT_PWR_DN_EN_LD; 1673 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1674 } 1675 break; 1676 case GENET_POWER_WOL_MAGIC: 1677 bcmgenet_wol_power_up_cfg(priv, mode); 1678 return; 1679 default: 1680 break; 1681 } 1682 } 1683 1684 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1685 struct bcmgenet_tx_ring *ring) 1686 { 1687 struct enet_cb *tx_cb_ptr; 1688 1689 tx_cb_ptr = ring->cbs; 1690 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1691 1692 /* Advancing local write pointer */ 1693 if (ring->write_ptr == ring->end_ptr) 1694 ring->write_ptr = ring->cb_ptr; 1695 else 1696 ring->write_ptr++; 1697 1698 return tx_cb_ptr; 1699 } 1700 1701 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1702 struct bcmgenet_tx_ring *ring) 1703 { 1704 struct enet_cb *tx_cb_ptr; 1705 1706 tx_cb_ptr = ring->cbs; 1707 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1708 1709 /* Rewinding local write pointer */ 1710 if (ring->write_ptr == ring->cb_ptr) 1711 ring->write_ptr = ring->end_ptr; 1712 else 1713 ring->write_ptr--; 1714 1715 return tx_cb_ptr; 1716 } 1717 1718 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1719 { 1720 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1721 INTRL2_CPU_MASK_SET); 1722 } 1723 1724 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1725 { 1726 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1727 INTRL2_CPU_MASK_CLEAR); 1728 } 1729 1730 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1731 { 1732 bcmgenet_intrl2_1_writel(ring->priv, 1733 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1734 INTRL2_CPU_MASK_SET); 1735 } 1736 1737 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1738 { 1739 bcmgenet_intrl2_1_writel(ring->priv, 1740 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1741 INTRL2_CPU_MASK_CLEAR); 1742 } 1743 1744 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1745 { 1746 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1747 INTRL2_CPU_MASK_SET); 1748 } 1749 1750 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1751 { 1752 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1753 INTRL2_CPU_MASK_CLEAR); 1754 } 1755 1756 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1757 { 1758 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1759 INTRL2_CPU_MASK_CLEAR); 1760 } 1761 1762 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1763 { 1764 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1765 INTRL2_CPU_MASK_SET); 1766 } 1767 1768 /* Simple helper to free a transmit control block's resources 1769 * Returns an skb when the last transmit control block associated with the 1770 * skb is freed. The skb should be freed by the caller if necessary. 1771 */ 1772 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1773 struct enet_cb *cb) 1774 { 1775 struct sk_buff *skb; 1776 1777 skb = cb->skb; 1778 1779 if (skb) { 1780 cb->skb = NULL; 1781 if (cb == GENET_CB(skb)->first_cb) 1782 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1783 dma_unmap_len(cb, dma_len), 1784 DMA_TO_DEVICE); 1785 else 1786 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1787 dma_unmap_len(cb, dma_len), 1788 DMA_TO_DEVICE); 1789 dma_unmap_addr_set(cb, dma_addr, 0); 1790 1791 if (cb == GENET_CB(skb)->last_cb) 1792 return skb; 1793 1794 } else if (dma_unmap_addr(cb, dma_addr)) { 1795 dma_unmap_page(dev, 1796 dma_unmap_addr(cb, dma_addr), 1797 dma_unmap_len(cb, dma_len), 1798 DMA_TO_DEVICE); 1799 dma_unmap_addr_set(cb, dma_addr, 0); 1800 } 1801 1802 return NULL; 1803 } 1804 1805 /* Simple helper to free a receive control block's resources */ 1806 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1807 struct enet_cb *cb) 1808 { 1809 struct sk_buff *skb; 1810 1811 skb = cb->skb; 1812 cb->skb = NULL; 1813 1814 if (dma_unmap_addr(cb, dma_addr)) { 1815 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1816 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1817 dma_unmap_addr_set(cb, dma_addr, 0); 1818 } 1819 1820 return skb; 1821 } 1822 1823 /* Unlocked version of the reclaim routine */ 1824 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1825 struct bcmgenet_tx_ring *ring) 1826 { 1827 struct bcmgenet_priv *priv = netdev_priv(dev); 1828 unsigned int txbds_processed = 0; 1829 unsigned int bytes_compl = 0; 1830 unsigned int pkts_compl = 0; 1831 unsigned int txbds_ready; 1832 unsigned int c_index; 1833 struct sk_buff *skb; 1834 1835 /* Clear status before servicing to reduce spurious interrupts */ 1836 if (ring->index == DESC_INDEX) 1837 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1838 INTRL2_CPU_CLEAR); 1839 else 1840 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1841 INTRL2_CPU_CLEAR); 1842 1843 /* Compute how many buffers are transmitted since last xmit call */ 1844 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1845 & DMA_C_INDEX_MASK; 1846 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1847 1848 netif_dbg(priv, tx_done, dev, 1849 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1850 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1851 1852 /* Reclaim transmitted buffers */ 1853 while (txbds_processed < txbds_ready) { 1854 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1855 &priv->tx_cbs[ring->clean_ptr]); 1856 if (skb) { 1857 pkts_compl++; 1858 bytes_compl += GENET_CB(skb)->bytes_sent; 1859 dev_consume_skb_any(skb); 1860 } 1861 1862 txbds_processed++; 1863 if (likely(ring->clean_ptr < ring->end_ptr)) 1864 ring->clean_ptr++; 1865 else 1866 ring->clean_ptr = ring->cb_ptr; 1867 } 1868 1869 ring->free_bds += txbds_processed; 1870 ring->c_index = c_index; 1871 1872 ring->packets += pkts_compl; 1873 ring->bytes += bytes_compl; 1874 1875 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1876 pkts_compl, bytes_compl); 1877 1878 return txbds_processed; 1879 } 1880 1881 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1882 struct bcmgenet_tx_ring *ring) 1883 { 1884 unsigned int released; 1885 1886 spin_lock_bh(&ring->lock); 1887 released = __bcmgenet_tx_reclaim(dev, ring); 1888 spin_unlock_bh(&ring->lock); 1889 1890 return released; 1891 } 1892 1893 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1894 { 1895 struct bcmgenet_tx_ring *ring = 1896 container_of(napi, struct bcmgenet_tx_ring, napi); 1897 unsigned int work_done = 0; 1898 struct netdev_queue *txq; 1899 1900 spin_lock(&ring->lock); 1901 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1902 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1903 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1904 netif_tx_wake_queue(txq); 1905 } 1906 spin_unlock(&ring->lock); 1907 1908 if (work_done == 0) { 1909 napi_complete(napi); 1910 ring->int_enable(ring); 1911 1912 return 0; 1913 } 1914 1915 return budget; 1916 } 1917 1918 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1919 { 1920 struct bcmgenet_priv *priv = netdev_priv(dev); 1921 int i; 1922 1923 if (netif_is_multiqueue(dev)) { 1924 for (i = 0; i < priv->hw_params->tx_queues; i++) 1925 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1926 } 1927 1928 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1929 } 1930 1931 /* Reallocate the SKB to put enough headroom in front of it and insert 1932 * the transmit checksum offsets in the descriptors 1933 */ 1934 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 1935 struct sk_buff *skb) 1936 { 1937 struct bcmgenet_priv *priv = netdev_priv(dev); 1938 struct status_64 *status = NULL; 1939 struct sk_buff *new_skb; 1940 u16 offset; 1941 u8 ip_proto; 1942 __be16 ip_ver; 1943 u32 tx_csum_info; 1944 1945 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1946 /* If 64 byte status block enabled, must make sure skb has 1947 * enough headroom for us to insert 64B status block. 1948 */ 1949 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1950 if (!new_skb) { 1951 dev_kfree_skb_any(skb); 1952 priv->mib.tx_realloc_tsb_failed++; 1953 dev->stats.tx_dropped++; 1954 return NULL; 1955 } 1956 dev_consume_skb_any(skb); 1957 skb = new_skb; 1958 priv->mib.tx_realloc_tsb++; 1959 } 1960 1961 skb_push(skb, sizeof(*status)); 1962 status = (struct status_64 *)skb->data; 1963 1964 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1965 ip_ver = skb->protocol; 1966 switch (ip_ver) { 1967 case htons(ETH_P_IP): 1968 ip_proto = ip_hdr(skb)->protocol; 1969 break; 1970 case htons(ETH_P_IPV6): 1971 ip_proto = ipv6_hdr(skb)->nexthdr; 1972 break; 1973 default: 1974 /* don't use UDP flag */ 1975 ip_proto = 0; 1976 break; 1977 } 1978 1979 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1980 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1981 (offset + skb->csum_offset) | 1982 STATUS_TX_CSUM_LV; 1983 1984 /* Set the special UDP flag for UDP */ 1985 if (ip_proto == IPPROTO_UDP) 1986 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1987 1988 status->tx_csum_info = tx_csum_info; 1989 } 1990 1991 return skb; 1992 } 1993 1994 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1995 { 1996 struct bcmgenet_priv *priv = netdev_priv(dev); 1997 struct device *kdev = &priv->pdev->dev; 1998 struct bcmgenet_tx_ring *ring = NULL; 1999 struct enet_cb *tx_cb_ptr; 2000 struct netdev_queue *txq; 2001 int nr_frags, index; 2002 dma_addr_t mapping; 2003 unsigned int size; 2004 skb_frag_t *frag; 2005 u32 len_stat; 2006 int ret; 2007 int i; 2008 2009 index = skb_get_queue_mapping(skb); 2010 /* Mapping strategy: 2011 * queue_mapping = 0, unclassified, packet xmited through ring16 2012 * queue_mapping = 1, goes to ring 0. (highest priority queue 2013 * queue_mapping = 2, goes to ring 1. 2014 * queue_mapping = 3, goes to ring 2. 2015 * queue_mapping = 4, goes to ring 3. 2016 */ 2017 if (index == 0) 2018 index = DESC_INDEX; 2019 else 2020 index -= 1; 2021 2022 ring = &priv->tx_rings[index]; 2023 txq = netdev_get_tx_queue(dev, ring->queue); 2024 2025 nr_frags = skb_shinfo(skb)->nr_frags; 2026 2027 spin_lock(&ring->lock); 2028 if (ring->free_bds <= (nr_frags + 1)) { 2029 if (!netif_tx_queue_stopped(txq)) { 2030 netif_tx_stop_queue(txq); 2031 netdev_err(dev, 2032 "%s: tx ring %d full when queue %d awake\n", 2033 __func__, index, ring->queue); 2034 } 2035 ret = NETDEV_TX_BUSY; 2036 goto out; 2037 } 2038 2039 /* Retain how many bytes will be sent on the wire, without TSB inserted 2040 * by transmit checksum offload 2041 */ 2042 GENET_CB(skb)->bytes_sent = skb->len; 2043 2044 /* add the Transmit Status Block */ 2045 skb = bcmgenet_add_tsb(dev, skb); 2046 if (!skb) { 2047 ret = NETDEV_TX_OK; 2048 goto out; 2049 } 2050 2051 for (i = 0; i <= nr_frags; i++) { 2052 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2053 2054 BUG_ON(!tx_cb_ptr); 2055 2056 if (!i) { 2057 /* Transmit single SKB or head of fragment list */ 2058 GENET_CB(skb)->first_cb = tx_cb_ptr; 2059 size = skb_headlen(skb); 2060 mapping = dma_map_single(kdev, skb->data, size, 2061 DMA_TO_DEVICE); 2062 } else { 2063 /* xmit fragment */ 2064 frag = &skb_shinfo(skb)->frags[i - 1]; 2065 size = skb_frag_size(frag); 2066 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2067 DMA_TO_DEVICE); 2068 } 2069 2070 ret = dma_mapping_error(kdev, mapping); 2071 if (ret) { 2072 priv->mib.tx_dma_failed++; 2073 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2074 ret = NETDEV_TX_OK; 2075 goto out_unmap_frags; 2076 } 2077 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2078 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2079 2080 tx_cb_ptr->skb = skb; 2081 2082 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2083 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2084 2085 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2086 * will need to restore software padding of "runt" packets 2087 */ 2088 if (!i) { 2089 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 2090 if (skb->ip_summed == CHECKSUM_PARTIAL) 2091 len_stat |= DMA_TX_DO_CSUM; 2092 } 2093 if (i == nr_frags) 2094 len_stat |= DMA_EOP; 2095 2096 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2097 } 2098 2099 GENET_CB(skb)->last_cb = tx_cb_ptr; 2100 skb_tx_timestamp(skb); 2101 2102 /* Decrement total BD count and advance our write pointer */ 2103 ring->free_bds -= nr_frags + 1; 2104 ring->prod_index += nr_frags + 1; 2105 ring->prod_index &= DMA_P_INDEX_MASK; 2106 2107 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2108 2109 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2110 netif_tx_stop_queue(txq); 2111 2112 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2113 /* Packets are ready, update producer index */ 2114 bcmgenet_tdma_ring_writel(priv, ring->index, 2115 ring->prod_index, TDMA_PROD_INDEX); 2116 out: 2117 spin_unlock(&ring->lock); 2118 2119 return ret; 2120 2121 out_unmap_frags: 2122 /* Back up for failed control block mapping */ 2123 bcmgenet_put_txcb(priv, ring); 2124 2125 /* Unmap successfully mapped control blocks */ 2126 while (i-- > 0) { 2127 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2128 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2129 } 2130 2131 dev_kfree_skb(skb); 2132 goto out; 2133 } 2134 2135 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2136 struct enet_cb *cb) 2137 { 2138 struct device *kdev = &priv->pdev->dev; 2139 struct sk_buff *skb; 2140 struct sk_buff *rx_skb; 2141 dma_addr_t mapping; 2142 2143 /* Allocate a new Rx skb */ 2144 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2145 GFP_ATOMIC | __GFP_NOWARN); 2146 if (!skb) { 2147 priv->mib.alloc_rx_buff_failed++; 2148 netif_err(priv, rx_err, priv->dev, 2149 "%s: Rx skb allocation failed\n", __func__); 2150 return NULL; 2151 } 2152 2153 /* DMA-map the new Rx skb */ 2154 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2155 DMA_FROM_DEVICE); 2156 if (dma_mapping_error(kdev, mapping)) { 2157 priv->mib.rx_dma_failed++; 2158 dev_kfree_skb_any(skb); 2159 netif_err(priv, rx_err, priv->dev, 2160 "%s: Rx skb DMA mapping failed\n", __func__); 2161 return NULL; 2162 } 2163 2164 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2165 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2166 2167 /* Put the new Rx skb on the ring */ 2168 cb->skb = skb; 2169 dma_unmap_addr_set(cb, dma_addr, mapping); 2170 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2171 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2172 2173 /* Return the current Rx skb to caller */ 2174 return rx_skb; 2175 } 2176 2177 /* bcmgenet_desc_rx - descriptor based rx process. 2178 * this could be called from bottom half, or from NAPI polling method. 2179 */ 2180 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2181 unsigned int budget) 2182 { 2183 struct bcmgenet_priv *priv = ring->priv; 2184 struct net_device *dev = priv->dev; 2185 struct enet_cb *cb; 2186 struct sk_buff *skb; 2187 u32 dma_length_status; 2188 unsigned long dma_flag; 2189 int len; 2190 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2191 unsigned int bytes_processed = 0; 2192 unsigned int p_index, mask; 2193 unsigned int discards; 2194 2195 /* Clear status before servicing to reduce spurious interrupts */ 2196 if (ring->index == DESC_INDEX) { 2197 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 2198 INTRL2_CPU_CLEAR); 2199 } else { 2200 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2201 bcmgenet_intrl2_1_writel(priv, 2202 mask, 2203 INTRL2_CPU_CLEAR); 2204 } 2205 2206 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2207 2208 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2209 DMA_P_INDEX_DISCARD_CNT_MASK; 2210 if (discards > ring->old_discards) { 2211 discards = discards - ring->old_discards; 2212 ring->errors += discards; 2213 ring->old_discards += discards; 2214 2215 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2216 if (ring->old_discards >= 0xC000) { 2217 ring->old_discards = 0; 2218 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2219 RDMA_PROD_INDEX); 2220 } 2221 } 2222 2223 p_index &= DMA_P_INDEX_MASK; 2224 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2225 2226 netif_dbg(priv, rx_status, dev, 2227 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2228 2229 while ((rxpktprocessed < rxpkttoprocess) && 2230 (rxpktprocessed < budget)) { 2231 struct status_64 *status; 2232 __be16 rx_csum; 2233 2234 cb = &priv->rx_cbs[ring->read_ptr]; 2235 skb = bcmgenet_rx_refill(priv, cb); 2236 2237 if (unlikely(!skb)) { 2238 ring->dropped++; 2239 goto next; 2240 } 2241 2242 status = (struct status_64 *)skb->data; 2243 dma_length_status = status->length_status; 2244 if (dev->features & NETIF_F_RXCSUM) { 2245 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2246 skb->csum = (__force __wsum)ntohs(rx_csum); 2247 skb->ip_summed = CHECKSUM_COMPLETE; 2248 } 2249 2250 /* DMA flags and length are still valid no matter how 2251 * we got the Receive Status Vector (64B RSB or register) 2252 */ 2253 dma_flag = dma_length_status & 0xffff; 2254 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2255 2256 netif_dbg(priv, rx_status, dev, 2257 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2258 __func__, p_index, ring->c_index, 2259 ring->read_ptr, dma_length_status); 2260 2261 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2262 netif_err(priv, rx_status, dev, 2263 "dropping fragmented packet!\n"); 2264 ring->errors++; 2265 dev_kfree_skb_any(skb); 2266 goto next; 2267 } 2268 2269 /* report errors */ 2270 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2271 DMA_RX_OV | 2272 DMA_RX_NO | 2273 DMA_RX_LG | 2274 DMA_RX_RXER))) { 2275 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2276 (unsigned int)dma_flag); 2277 if (dma_flag & DMA_RX_CRC_ERROR) 2278 dev->stats.rx_crc_errors++; 2279 if (dma_flag & DMA_RX_OV) 2280 dev->stats.rx_over_errors++; 2281 if (dma_flag & DMA_RX_NO) 2282 dev->stats.rx_frame_errors++; 2283 if (dma_flag & DMA_RX_LG) 2284 dev->stats.rx_length_errors++; 2285 dev->stats.rx_errors++; 2286 dev_kfree_skb_any(skb); 2287 goto next; 2288 } /* error packet */ 2289 2290 skb_put(skb, len); 2291 2292 /* remove RSB and hardware 2bytes added for IP alignment */ 2293 skb_pull(skb, 66); 2294 len -= 66; 2295 2296 if (priv->crc_fwd_en) { 2297 skb_trim(skb, len - ETH_FCS_LEN); 2298 len -= ETH_FCS_LEN; 2299 } 2300 2301 bytes_processed += len; 2302 2303 /*Finish setting up the received SKB and send it to the kernel*/ 2304 skb->protocol = eth_type_trans(skb, priv->dev); 2305 ring->packets++; 2306 ring->bytes += len; 2307 if (dma_flag & DMA_RX_MULT) 2308 dev->stats.multicast++; 2309 2310 /* Notify kernel */ 2311 napi_gro_receive(&ring->napi, skb); 2312 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2313 2314 next: 2315 rxpktprocessed++; 2316 if (likely(ring->read_ptr < ring->end_ptr)) 2317 ring->read_ptr++; 2318 else 2319 ring->read_ptr = ring->cb_ptr; 2320 2321 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2322 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2323 } 2324 2325 ring->dim.bytes = bytes_processed; 2326 ring->dim.packets = rxpktprocessed; 2327 2328 return rxpktprocessed; 2329 } 2330 2331 /* Rx NAPI polling method */ 2332 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2333 { 2334 struct bcmgenet_rx_ring *ring = container_of(napi, 2335 struct bcmgenet_rx_ring, napi); 2336 struct dim_sample dim_sample = {}; 2337 unsigned int work_done; 2338 2339 work_done = bcmgenet_desc_rx(ring, budget); 2340 2341 if (work_done < budget) { 2342 napi_complete_done(napi, work_done); 2343 ring->int_enable(ring); 2344 } 2345 2346 if (ring->dim.use_dim) { 2347 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2348 ring->dim.bytes, &dim_sample); 2349 net_dim(&ring->dim.dim, dim_sample); 2350 } 2351 2352 return work_done; 2353 } 2354 2355 static void bcmgenet_dim_work(struct work_struct *work) 2356 { 2357 struct dim *dim = container_of(work, struct dim, work); 2358 struct bcmgenet_net_dim *ndim = 2359 container_of(dim, struct bcmgenet_net_dim, dim); 2360 struct bcmgenet_rx_ring *ring = 2361 container_of(ndim, struct bcmgenet_rx_ring, dim); 2362 struct dim_cq_moder cur_profile = 2363 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2364 2365 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2366 dim->state = DIM_START_MEASURE; 2367 } 2368 2369 /* Assign skb to RX DMA descriptor. */ 2370 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2371 struct bcmgenet_rx_ring *ring) 2372 { 2373 struct enet_cb *cb; 2374 struct sk_buff *skb; 2375 int i; 2376 2377 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2378 2379 /* loop here for each buffer needing assign */ 2380 for (i = 0; i < ring->size; i++) { 2381 cb = ring->cbs + i; 2382 skb = bcmgenet_rx_refill(priv, cb); 2383 if (skb) 2384 dev_consume_skb_any(skb); 2385 if (!cb->skb) 2386 return -ENOMEM; 2387 } 2388 2389 return 0; 2390 } 2391 2392 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2393 { 2394 struct sk_buff *skb; 2395 struct enet_cb *cb; 2396 int i; 2397 2398 for (i = 0; i < priv->num_rx_bds; i++) { 2399 cb = &priv->rx_cbs[i]; 2400 2401 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2402 if (skb) 2403 dev_consume_skb_any(skb); 2404 } 2405 } 2406 2407 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2408 { 2409 u32 reg; 2410 2411 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2412 if (reg & CMD_SW_RESET) 2413 return; 2414 if (enable) 2415 reg |= mask; 2416 else 2417 reg &= ~mask; 2418 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2419 2420 /* UniMAC stops on a packet boundary, wait for a full-size packet 2421 * to be processed 2422 */ 2423 if (enable == 0) 2424 usleep_range(1000, 2000); 2425 } 2426 2427 static void reset_umac(struct bcmgenet_priv *priv) 2428 { 2429 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2430 bcmgenet_rbuf_ctrl_set(priv, 0); 2431 udelay(10); 2432 2433 /* issue soft reset and disable MAC while updating its registers */ 2434 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2435 udelay(2); 2436 } 2437 2438 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2439 { 2440 /* Mask all interrupts.*/ 2441 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2442 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2443 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2444 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2445 } 2446 2447 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2448 { 2449 u32 int0_enable = 0; 2450 2451 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2452 * and MoCA PHY 2453 */ 2454 if (priv->internal_phy) { 2455 int0_enable |= UMAC_IRQ_LINK_EVENT; 2456 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2457 int0_enable |= UMAC_IRQ_PHY_DET_R; 2458 } else if (priv->ext_phy) { 2459 int0_enable |= UMAC_IRQ_LINK_EVENT; 2460 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2461 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2462 int0_enable |= UMAC_IRQ_LINK_EVENT; 2463 } 2464 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2465 } 2466 2467 static void init_umac(struct bcmgenet_priv *priv) 2468 { 2469 struct device *kdev = &priv->pdev->dev; 2470 u32 reg; 2471 u32 int0_enable = 0; 2472 2473 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2474 2475 reset_umac(priv); 2476 2477 /* clear tx/rx counter */ 2478 bcmgenet_umac_writel(priv, 2479 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2480 UMAC_MIB_CTRL); 2481 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2482 2483 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2484 2485 /* init tx registers, enable TSB */ 2486 reg = bcmgenet_tbuf_ctrl_get(priv); 2487 reg |= TBUF_64B_EN; 2488 bcmgenet_tbuf_ctrl_set(priv, reg); 2489 2490 /* init rx registers, enable ip header optimization and RSB */ 2491 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2492 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2493 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2494 2495 /* enable rx checksumming */ 2496 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2497 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2498 /* If UniMAC forwards CRC, we need to skip over it to get 2499 * a valid CHK bit to be set in the per-packet status word 2500 */ 2501 if (priv->crc_fwd_en) 2502 reg |= RBUF_SKIP_FCS; 2503 else 2504 reg &= ~RBUF_SKIP_FCS; 2505 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2506 2507 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2508 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2509 2510 bcmgenet_intr_disable(priv); 2511 2512 /* Configure backpressure vectors for MoCA */ 2513 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2514 reg = bcmgenet_bp_mc_get(priv); 2515 reg |= BIT(priv->hw_params->bp_in_en_shift); 2516 2517 /* bp_mask: back pressure mask */ 2518 if (netif_is_multiqueue(priv->dev)) 2519 reg |= priv->hw_params->bp_in_mask; 2520 else 2521 reg &= ~priv->hw_params->bp_in_mask; 2522 bcmgenet_bp_mc_set(priv, reg); 2523 } 2524 2525 /* Enable MDIO interrupts on GENET v3+ */ 2526 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2527 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2528 2529 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2530 2531 dev_dbg(kdev, "done init umac\n"); 2532 } 2533 2534 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2535 void (*cb)(struct work_struct *work)) 2536 { 2537 struct bcmgenet_net_dim *dim = &ring->dim; 2538 2539 INIT_WORK(&dim->dim.work, cb); 2540 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2541 dim->event_ctr = 0; 2542 dim->packets = 0; 2543 dim->bytes = 0; 2544 } 2545 2546 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2547 { 2548 struct bcmgenet_net_dim *dim = &ring->dim; 2549 struct dim_cq_moder moder; 2550 u32 usecs, pkts; 2551 2552 usecs = ring->rx_coalesce_usecs; 2553 pkts = ring->rx_max_coalesced_frames; 2554 2555 /* If DIM was enabled, re-apply default parameters */ 2556 if (dim->use_dim) { 2557 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2558 usecs = moder.usec; 2559 pkts = moder.pkts; 2560 } 2561 2562 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2563 } 2564 2565 /* Initialize a Tx ring along with corresponding hardware registers */ 2566 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2567 unsigned int index, unsigned int size, 2568 unsigned int start_ptr, unsigned int end_ptr) 2569 { 2570 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2571 u32 words_per_bd = WORDS_PER_BD(priv); 2572 u32 flow_period_val = 0; 2573 2574 spin_lock_init(&ring->lock); 2575 ring->priv = priv; 2576 ring->index = index; 2577 if (index == DESC_INDEX) { 2578 ring->queue = 0; 2579 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2580 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2581 } else { 2582 ring->queue = index + 1; 2583 ring->int_enable = bcmgenet_tx_ring_int_enable; 2584 ring->int_disable = bcmgenet_tx_ring_int_disable; 2585 } 2586 ring->cbs = priv->tx_cbs + start_ptr; 2587 ring->size = size; 2588 ring->clean_ptr = start_ptr; 2589 ring->c_index = 0; 2590 ring->free_bds = size; 2591 ring->write_ptr = start_ptr; 2592 ring->cb_ptr = start_ptr; 2593 ring->end_ptr = end_ptr - 1; 2594 ring->prod_index = 0; 2595 2596 /* Set flow period for ring != 16 */ 2597 if (index != DESC_INDEX) 2598 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2599 2600 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2601 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2602 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2603 /* Disable rate control for now */ 2604 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2605 TDMA_FLOW_PERIOD); 2606 bcmgenet_tdma_ring_writel(priv, index, 2607 ((size << DMA_RING_SIZE_SHIFT) | 2608 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2609 2610 /* Set start and end address, read and write pointers */ 2611 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2612 DMA_START_ADDR); 2613 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2614 TDMA_READ_PTR); 2615 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2616 TDMA_WRITE_PTR); 2617 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2618 DMA_END_ADDR); 2619 2620 /* Initialize Tx NAPI */ 2621 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2622 NAPI_POLL_WEIGHT); 2623 } 2624 2625 /* Initialize a RDMA ring */ 2626 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2627 unsigned int index, unsigned int size, 2628 unsigned int start_ptr, unsigned int end_ptr) 2629 { 2630 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2631 u32 words_per_bd = WORDS_PER_BD(priv); 2632 int ret; 2633 2634 ring->priv = priv; 2635 ring->index = index; 2636 if (index == DESC_INDEX) { 2637 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2638 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2639 } else { 2640 ring->int_enable = bcmgenet_rx_ring_int_enable; 2641 ring->int_disable = bcmgenet_rx_ring_int_disable; 2642 } 2643 ring->cbs = priv->rx_cbs + start_ptr; 2644 ring->size = size; 2645 ring->c_index = 0; 2646 ring->read_ptr = start_ptr; 2647 ring->cb_ptr = start_ptr; 2648 ring->end_ptr = end_ptr - 1; 2649 2650 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2651 if (ret) 2652 return ret; 2653 2654 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2655 bcmgenet_init_rx_coalesce(ring); 2656 2657 /* Initialize Rx NAPI */ 2658 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2659 NAPI_POLL_WEIGHT); 2660 2661 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2662 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2663 bcmgenet_rdma_ring_writel(priv, index, 2664 ((size << DMA_RING_SIZE_SHIFT) | 2665 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2666 bcmgenet_rdma_ring_writel(priv, index, 2667 (DMA_FC_THRESH_LO << 2668 DMA_XOFF_THRESHOLD_SHIFT) | 2669 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2670 2671 /* Set start and end address, read and write pointers */ 2672 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2673 DMA_START_ADDR); 2674 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2675 RDMA_READ_PTR); 2676 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2677 RDMA_WRITE_PTR); 2678 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2679 DMA_END_ADDR); 2680 2681 return ret; 2682 } 2683 2684 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2685 { 2686 unsigned int i; 2687 struct bcmgenet_tx_ring *ring; 2688 2689 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2690 ring = &priv->tx_rings[i]; 2691 napi_enable(&ring->napi); 2692 ring->int_enable(ring); 2693 } 2694 2695 ring = &priv->tx_rings[DESC_INDEX]; 2696 napi_enable(&ring->napi); 2697 ring->int_enable(ring); 2698 } 2699 2700 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2701 { 2702 unsigned int i; 2703 struct bcmgenet_tx_ring *ring; 2704 2705 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2706 ring = &priv->tx_rings[i]; 2707 napi_disable(&ring->napi); 2708 } 2709 2710 ring = &priv->tx_rings[DESC_INDEX]; 2711 napi_disable(&ring->napi); 2712 } 2713 2714 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2715 { 2716 unsigned int i; 2717 struct bcmgenet_tx_ring *ring; 2718 2719 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2720 ring = &priv->tx_rings[i]; 2721 netif_napi_del(&ring->napi); 2722 } 2723 2724 ring = &priv->tx_rings[DESC_INDEX]; 2725 netif_napi_del(&ring->napi); 2726 } 2727 2728 /* Initialize Tx queues 2729 * 2730 * Queues 0-3 are priority-based, each one has 32 descriptors, 2731 * with queue 0 being the highest priority queue. 2732 * 2733 * Queue 16 is the default Tx queue with 2734 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2735 * 2736 * The transmit control block pool is then partitioned as follows: 2737 * - Tx queue 0 uses tx_cbs[0..31] 2738 * - Tx queue 1 uses tx_cbs[32..63] 2739 * - Tx queue 2 uses tx_cbs[64..95] 2740 * - Tx queue 3 uses tx_cbs[96..127] 2741 * - Tx queue 16 uses tx_cbs[128..255] 2742 */ 2743 static void bcmgenet_init_tx_queues(struct net_device *dev) 2744 { 2745 struct bcmgenet_priv *priv = netdev_priv(dev); 2746 u32 i, dma_enable; 2747 u32 dma_ctrl, ring_cfg; 2748 u32 dma_priority[3] = {0, 0, 0}; 2749 2750 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2751 dma_enable = dma_ctrl & DMA_EN; 2752 dma_ctrl &= ~DMA_EN; 2753 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2754 2755 dma_ctrl = 0; 2756 ring_cfg = 0; 2757 2758 /* Enable strict priority arbiter mode */ 2759 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2760 2761 /* Initialize Tx priority queues */ 2762 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2763 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2764 i * priv->hw_params->tx_bds_per_q, 2765 (i + 1) * priv->hw_params->tx_bds_per_q); 2766 ring_cfg |= (1 << i); 2767 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2768 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2769 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2770 } 2771 2772 /* Initialize Tx default queue 16 */ 2773 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2774 priv->hw_params->tx_queues * 2775 priv->hw_params->tx_bds_per_q, 2776 TOTAL_DESC); 2777 ring_cfg |= (1 << DESC_INDEX); 2778 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2779 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2780 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2781 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2782 2783 /* Set Tx queue priorities */ 2784 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2785 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2786 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2787 2788 /* Enable Tx queues */ 2789 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2790 2791 /* Enable Tx DMA */ 2792 if (dma_enable) 2793 dma_ctrl |= DMA_EN; 2794 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2795 } 2796 2797 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2798 { 2799 unsigned int i; 2800 struct bcmgenet_rx_ring *ring; 2801 2802 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2803 ring = &priv->rx_rings[i]; 2804 napi_enable(&ring->napi); 2805 ring->int_enable(ring); 2806 } 2807 2808 ring = &priv->rx_rings[DESC_INDEX]; 2809 napi_enable(&ring->napi); 2810 ring->int_enable(ring); 2811 } 2812 2813 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2814 { 2815 unsigned int i; 2816 struct bcmgenet_rx_ring *ring; 2817 2818 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2819 ring = &priv->rx_rings[i]; 2820 napi_disable(&ring->napi); 2821 cancel_work_sync(&ring->dim.dim.work); 2822 } 2823 2824 ring = &priv->rx_rings[DESC_INDEX]; 2825 napi_disable(&ring->napi); 2826 cancel_work_sync(&ring->dim.dim.work); 2827 } 2828 2829 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2830 { 2831 unsigned int i; 2832 struct bcmgenet_rx_ring *ring; 2833 2834 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2835 ring = &priv->rx_rings[i]; 2836 netif_napi_del(&ring->napi); 2837 } 2838 2839 ring = &priv->rx_rings[DESC_INDEX]; 2840 netif_napi_del(&ring->napi); 2841 } 2842 2843 /* Initialize Rx queues 2844 * 2845 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2846 * used to direct traffic to these queues. 2847 * 2848 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2849 */ 2850 static int bcmgenet_init_rx_queues(struct net_device *dev) 2851 { 2852 struct bcmgenet_priv *priv = netdev_priv(dev); 2853 u32 i; 2854 u32 dma_enable; 2855 u32 dma_ctrl; 2856 u32 ring_cfg; 2857 int ret; 2858 2859 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2860 dma_enable = dma_ctrl & DMA_EN; 2861 dma_ctrl &= ~DMA_EN; 2862 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2863 2864 dma_ctrl = 0; 2865 ring_cfg = 0; 2866 2867 /* Initialize Rx priority queues */ 2868 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2869 ret = bcmgenet_init_rx_ring(priv, i, 2870 priv->hw_params->rx_bds_per_q, 2871 i * priv->hw_params->rx_bds_per_q, 2872 (i + 1) * 2873 priv->hw_params->rx_bds_per_q); 2874 if (ret) 2875 return ret; 2876 2877 ring_cfg |= (1 << i); 2878 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2879 } 2880 2881 /* Initialize Rx default queue 16 */ 2882 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2883 priv->hw_params->rx_queues * 2884 priv->hw_params->rx_bds_per_q, 2885 TOTAL_DESC); 2886 if (ret) 2887 return ret; 2888 2889 ring_cfg |= (1 << DESC_INDEX); 2890 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2891 2892 /* Enable rings */ 2893 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2894 2895 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2896 if (dma_enable) 2897 dma_ctrl |= DMA_EN; 2898 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2899 2900 return 0; 2901 } 2902 2903 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2904 { 2905 int ret = 0; 2906 int timeout = 0; 2907 u32 reg; 2908 u32 dma_ctrl; 2909 int i; 2910 2911 /* Disable TDMA to stop add more frames in TX DMA */ 2912 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2913 reg &= ~DMA_EN; 2914 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2915 2916 /* Check TDMA status register to confirm TDMA is disabled */ 2917 while (timeout++ < DMA_TIMEOUT_VAL) { 2918 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2919 if (reg & DMA_DISABLED) 2920 break; 2921 2922 udelay(1); 2923 } 2924 2925 if (timeout == DMA_TIMEOUT_VAL) { 2926 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2927 ret = -ETIMEDOUT; 2928 } 2929 2930 /* Wait 10ms for packet drain in both tx and rx dma */ 2931 usleep_range(10000, 20000); 2932 2933 /* Disable RDMA */ 2934 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2935 reg &= ~DMA_EN; 2936 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2937 2938 timeout = 0; 2939 /* Check RDMA status register to confirm RDMA is disabled */ 2940 while (timeout++ < DMA_TIMEOUT_VAL) { 2941 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2942 if (reg & DMA_DISABLED) 2943 break; 2944 2945 udelay(1); 2946 } 2947 2948 if (timeout == DMA_TIMEOUT_VAL) { 2949 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2950 ret = -ETIMEDOUT; 2951 } 2952 2953 dma_ctrl = 0; 2954 for (i = 0; i < priv->hw_params->rx_queues; i++) 2955 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2956 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2957 reg &= ~dma_ctrl; 2958 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2959 2960 dma_ctrl = 0; 2961 for (i = 0; i < priv->hw_params->tx_queues; i++) 2962 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2963 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2964 reg &= ~dma_ctrl; 2965 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2966 2967 return ret; 2968 } 2969 2970 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2971 { 2972 struct netdev_queue *txq; 2973 int i; 2974 2975 bcmgenet_fini_rx_napi(priv); 2976 bcmgenet_fini_tx_napi(priv); 2977 2978 for (i = 0; i < priv->num_tx_bds; i++) 2979 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2980 priv->tx_cbs + i)); 2981 2982 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2983 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2984 netdev_tx_reset_queue(txq); 2985 } 2986 2987 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2988 netdev_tx_reset_queue(txq); 2989 2990 bcmgenet_free_rx_buffers(priv); 2991 kfree(priv->rx_cbs); 2992 kfree(priv->tx_cbs); 2993 } 2994 2995 /* init_edma: Initialize DMA control register */ 2996 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2997 { 2998 int ret; 2999 unsigned int i; 3000 struct enet_cb *cb; 3001 3002 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3003 3004 /* Initialize common Rx ring structures */ 3005 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3006 priv->num_rx_bds = TOTAL_DESC; 3007 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3008 GFP_KERNEL); 3009 if (!priv->rx_cbs) 3010 return -ENOMEM; 3011 3012 for (i = 0; i < priv->num_rx_bds; i++) { 3013 cb = priv->rx_cbs + i; 3014 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3015 } 3016 3017 /* Initialize common TX ring structures */ 3018 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3019 priv->num_tx_bds = TOTAL_DESC; 3020 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3021 GFP_KERNEL); 3022 if (!priv->tx_cbs) { 3023 kfree(priv->rx_cbs); 3024 return -ENOMEM; 3025 } 3026 3027 for (i = 0; i < priv->num_tx_bds; i++) { 3028 cb = priv->tx_cbs + i; 3029 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3030 } 3031 3032 /* Init rDma */ 3033 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3034 DMA_SCB_BURST_SIZE); 3035 3036 /* Initialize Rx queues */ 3037 ret = bcmgenet_init_rx_queues(priv->dev); 3038 if (ret) { 3039 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3040 bcmgenet_free_rx_buffers(priv); 3041 kfree(priv->rx_cbs); 3042 kfree(priv->tx_cbs); 3043 return ret; 3044 } 3045 3046 /* Init tDma */ 3047 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3048 DMA_SCB_BURST_SIZE); 3049 3050 /* Initialize Tx queues */ 3051 bcmgenet_init_tx_queues(priv->dev); 3052 3053 return 0; 3054 } 3055 3056 /* Interrupt bottom half */ 3057 static void bcmgenet_irq_task(struct work_struct *work) 3058 { 3059 unsigned int status; 3060 struct bcmgenet_priv *priv = container_of( 3061 work, struct bcmgenet_priv, bcmgenet_irq_work); 3062 3063 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3064 3065 spin_lock_irq(&priv->lock); 3066 status = priv->irq0_stat; 3067 priv->irq0_stat = 0; 3068 spin_unlock_irq(&priv->lock); 3069 3070 if (status & UMAC_IRQ_PHY_DET_R && 3071 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3072 phy_init_hw(priv->dev->phydev); 3073 genphy_config_aneg(priv->dev->phydev); 3074 } 3075 3076 /* Link UP/DOWN event */ 3077 if (status & UMAC_IRQ_LINK_EVENT) 3078 phy_mac_interrupt(priv->dev->phydev); 3079 3080 } 3081 3082 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 3083 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3084 { 3085 struct bcmgenet_priv *priv = dev_id; 3086 struct bcmgenet_rx_ring *rx_ring; 3087 struct bcmgenet_tx_ring *tx_ring; 3088 unsigned int index, status; 3089 3090 /* Read irq status */ 3091 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3092 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3093 3094 /* clear interrupts */ 3095 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3096 3097 netif_dbg(priv, intr, priv->dev, 3098 "%s: IRQ=0x%x\n", __func__, status); 3099 3100 /* Check Rx priority queue interrupts */ 3101 for (index = 0; index < priv->hw_params->rx_queues; index++) { 3102 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3103 continue; 3104 3105 rx_ring = &priv->rx_rings[index]; 3106 rx_ring->dim.event_ctr++; 3107 3108 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3109 rx_ring->int_disable(rx_ring); 3110 __napi_schedule_irqoff(&rx_ring->napi); 3111 } 3112 } 3113 3114 /* Check Tx priority queue interrupts */ 3115 for (index = 0; index < priv->hw_params->tx_queues; index++) { 3116 if (!(status & BIT(index))) 3117 continue; 3118 3119 tx_ring = &priv->tx_rings[index]; 3120 3121 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3122 tx_ring->int_disable(tx_ring); 3123 __napi_schedule_irqoff(&tx_ring->napi); 3124 } 3125 } 3126 3127 return IRQ_HANDLED; 3128 } 3129 3130 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 3131 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3132 { 3133 struct bcmgenet_priv *priv = dev_id; 3134 struct bcmgenet_rx_ring *rx_ring; 3135 struct bcmgenet_tx_ring *tx_ring; 3136 unsigned int status; 3137 unsigned long flags; 3138 3139 /* Read irq status */ 3140 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3141 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3142 3143 /* clear interrupts */ 3144 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3145 3146 netif_dbg(priv, intr, priv->dev, 3147 "IRQ=0x%x\n", status); 3148 3149 if (status & UMAC_IRQ_RXDMA_DONE) { 3150 rx_ring = &priv->rx_rings[DESC_INDEX]; 3151 rx_ring->dim.event_ctr++; 3152 3153 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3154 rx_ring->int_disable(rx_ring); 3155 __napi_schedule_irqoff(&rx_ring->napi); 3156 } 3157 } 3158 3159 if (status & UMAC_IRQ_TXDMA_DONE) { 3160 tx_ring = &priv->tx_rings[DESC_INDEX]; 3161 3162 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3163 tx_ring->int_disable(tx_ring); 3164 __napi_schedule_irqoff(&tx_ring->napi); 3165 } 3166 } 3167 3168 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 3169 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 3170 wake_up(&priv->wq); 3171 } 3172 3173 /* all other interested interrupts handled in bottom half */ 3174 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3175 if (status) { 3176 /* Save irq status for bottom-half processing. */ 3177 spin_lock_irqsave(&priv->lock, flags); 3178 priv->irq0_stat |= status; 3179 spin_unlock_irqrestore(&priv->lock, flags); 3180 3181 schedule_work(&priv->bcmgenet_irq_work); 3182 } 3183 3184 return IRQ_HANDLED; 3185 } 3186 3187 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3188 { 3189 /* Acknowledge the interrupt */ 3190 return IRQ_HANDLED; 3191 } 3192 3193 #ifdef CONFIG_NET_POLL_CONTROLLER 3194 static void bcmgenet_poll_controller(struct net_device *dev) 3195 { 3196 struct bcmgenet_priv *priv = netdev_priv(dev); 3197 3198 /* Invoke the main RX/TX interrupt handler */ 3199 disable_irq(priv->irq0); 3200 bcmgenet_isr0(priv->irq0, priv); 3201 enable_irq(priv->irq0); 3202 3203 /* And the interrupt handler for RX/TX priority queues */ 3204 disable_irq(priv->irq1); 3205 bcmgenet_isr1(priv->irq1, priv); 3206 enable_irq(priv->irq1); 3207 } 3208 #endif 3209 3210 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3211 { 3212 u32 reg; 3213 3214 reg = bcmgenet_rbuf_ctrl_get(priv); 3215 reg |= BIT(1); 3216 bcmgenet_rbuf_ctrl_set(priv, reg); 3217 udelay(10); 3218 3219 reg &= ~BIT(1); 3220 bcmgenet_rbuf_ctrl_set(priv, reg); 3221 udelay(10); 3222 } 3223 3224 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3225 unsigned char *addr) 3226 { 3227 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3228 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3229 } 3230 3231 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3232 unsigned char *addr) 3233 { 3234 u32 addr_tmp; 3235 3236 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3237 put_unaligned_be32(addr_tmp, &addr[0]); 3238 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3239 put_unaligned_be16(addr_tmp, &addr[4]); 3240 } 3241 3242 /* Returns a reusable dma control register value */ 3243 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 3244 { 3245 unsigned int i; 3246 u32 reg; 3247 u32 dma_ctrl; 3248 3249 /* disable DMA */ 3250 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3251 for (i = 0; i < priv->hw_params->tx_queues; i++) 3252 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3253 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3254 reg &= ~dma_ctrl; 3255 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3256 3257 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3258 for (i = 0; i < priv->hw_params->rx_queues; i++) 3259 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 3260 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3261 reg &= ~dma_ctrl; 3262 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3263 3264 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3265 udelay(10); 3266 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3267 3268 return dma_ctrl; 3269 } 3270 3271 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 3272 { 3273 u32 reg; 3274 3275 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3276 reg |= dma_ctrl; 3277 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3278 3279 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3280 reg |= dma_ctrl; 3281 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3282 } 3283 3284 static void bcmgenet_netif_start(struct net_device *dev) 3285 { 3286 struct bcmgenet_priv *priv = netdev_priv(dev); 3287 3288 /* Start the network engine */ 3289 bcmgenet_set_rx_mode(dev); 3290 bcmgenet_enable_rx_napi(priv); 3291 3292 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3293 3294 bcmgenet_enable_tx_napi(priv); 3295 3296 /* Monitor link interrupts now */ 3297 bcmgenet_link_intr_enable(priv); 3298 3299 phy_start(dev->phydev); 3300 } 3301 3302 static int bcmgenet_open(struct net_device *dev) 3303 { 3304 struct bcmgenet_priv *priv = netdev_priv(dev); 3305 unsigned long dma_ctrl; 3306 int ret; 3307 3308 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3309 3310 /* Turn on the clock */ 3311 clk_prepare_enable(priv->clk); 3312 3313 /* If this is an internal GPHY, power it back on now, before UniMAC is 3314 * brought out of reset as absolutely no UniMAC activity is allowed 3315 */ 3316 if (priv->internal_phy) 3317 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3318 3319 /* take MAC out of reset */ 3320 bcmgenet_umac_reset(priv); 3321 3322 init_umac(priv); 3323 3324 /* Apply features again in case we changed them while interface was 3325 * down 3326 */ 3327 bcmgenet_set_features(dev, dev->features); 3328 3329 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3330 3331 /* Disable RX/TX DMA and flush TX queues */ 3332 dma_ctrl = bcmgenet_dma_disable(priv); 3333 3334 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3335 ret = bcmgenet_init_dma(priv); 3336 if (ret) { 3337 netdev_err(dev, "failed to initialize DMA\n"); 3338 goto err_clk_disable; 3339 } 3340 3341 /* Always enable ring 16 - descriptor ring */ 3342 bcmgenet_enable_dma(priv, dma_ctrl); 3343 3344 /* HFB init */ 3345 bcmgenet_hfb_init(priv); 3346 3347 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3348 dev->name, priv); 3349 if (ret < 0) { 3350 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3351 goto err_fini_dma; 3352 } 3353 3354 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3355 dev->name, priv); 3356 if (ret < 0) { 3357 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3358 goto err_irq0; 3359 } 3360 3361 ret = bcmgenet_mii_probe(dev); 3362 if (ret) { 3363 netdev_err(dev, "failed to connect to PHY\n"); 3364 goto err_irq1; 3365 } 3366 3367 bcmgenet_netif_start(dev); 3368 3369 netif_tx_start_all_queues(dev); 3370 3371 return 0; 3372 3373 err_irq1: 3374 free_irq(priv->irq1, priv); 3375 err_irq0: 3376 free_irq(priv->irq0, priv); 3377 err_fini_dma: 3378 bcmgenet_dma_teardown(priv); 3379 bcmgenet_fini_dma(priv); 3380 err_clk_disable: 3381 if (priv->internal_phy) 3382 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3383 clk_disable_unprepare(priv->clk); 3384 return ret; 3385 } 3386 3387 static void bcmgenet_netif_stop(struct net_device *dev) 3388 { 3389 struct bcmgenet_priv *priv = netdev_priv(dev); 3390 3391 bcmgenet_disable_tx_napi(priv); 3392 netif_tx_disable(dev); 3393 3394 /* Disable MAC receive */ 3395 umac_enable_set(priv, CMD_RX_EN, false); 3396 3397 bcmgenet_dma_teardown(priv); 3398 3399 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3400 umac_enable_set(priv, CMD_TX_EN, false); 3401 3402 phy_stop(dev->phydev); 3403 bcmgenet_disable_rx_napi(priv); 3404 bcmgenet_intr_disable(priv); 3405 3406 /* Wait for pending work items to complete. Since interrupts are 3407 * disabled no new work will be scheduled. 3408 */ 3409 cancel_work_sync(&priv->bcmgenet_irq_work); 3410 3411 priv->old_link = -1; 3412 priv->old_speed = -1; 3413 priv->old_duplex = -1; 3414 priv->old_pause = -1; 3415 3416 /* tx reclaim */ 3417 bcmgenet_tx_reclaim_all(dev); 3418 bcmgenet_fini_dma(priv); 3419 } 3420 3421 static int bcmgenet_close(struct net_device *dev) 3422 { 3423 struct bcmgenet_priv *priv = netdev_priv(dev); 3424 int ret = 0; 3425 3426 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3427 3428 bcmgenet_netif_stop(dev); 3429 3430 /* Really kill the PHY state machine and disconnect from it */ 3431 phy_disconnect(dev->phydev); 3432 3433 free_irq(priv->irq0, priv); 3434 free_irq(priv->irq1, priv); 3435 3436 if (priv->internal_phy) 3437 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3438 3439 clk_disable_unprepare(priv->clk); 3440 3441 return ret; 3442 } 3443 3444 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3445 { 3446 struct bcmgenet_priv *priv = ring->priv; 3447 u32 p_index, c_index, intsts, intmsk; 3448 struct netdev_queue *txq; 3449 unsigned int free_bds; 3450 bool txq_stopped; 3451 3452 if (!netif_msg_tx_err(priv)) 3453 return; 3454 3455 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3456 3457 spin_lock(&ring->lock); 3458 if (ring->index == DESC_INDEX) { 3459 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3460 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3461 } else { 3462 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3463 intmsk = 1 << ring->index; 3464 } 3465 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3466 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3467 txq_stopped = netif_tx_queue_stopped(txq); 3468 free_bds = ring->free_bds; 3469 spin_unlock(&ring->lock); 3470 3471 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3472 "TX queue status: %s, interrupts: %s\n" 3473 "(sw)free_bds: %d (sw)size: %d\n" 3474 "(sw)p_index: %d (hw)p_index: %d\n" 3475 "(sw)c_index: %d (hw)c_index: %d\n" 3476 "(sw)clean_p: %d (sw)write_p: %d\n" 3477 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3478 ring->index, ring->queue, 3479 txq_stopped ? "stopped" : "active", 3480 intsts & intmsk ? "enabled" : "disabled", 3481 free_bds, ring->size, 3482 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3483 ring->c_index, c_index & DMA_C_INDEX_MASK, 3484 ring->clean_ptr, ring->write_ptr, 3485 ring->cb_ptr, ring->end_ptr); 3486 } 3487 3488 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3489 { 3490 struct bcmgenet_priv *priv = netdev_priv(dev); 3491 u32 int0_enable = 0; 3492 u32 int1_enable = 0; 3493 unsigned int q; 3494 3495 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3496 3497 for (q = 0; q < priv->hw_params->tx_queues; q++) 3498 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3499 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3500 3501 bcmgenet_tx_reclaim_all(dev); 3502 3503 for (q = 0; q < priv->hw_params->tx_queues; q++) 3504 int1_enable |= (1 << q); 3505 3506 int0_enable = UMAC_IRQ_TXDMA_DONE; 3507 3508 /* Re-enable TX interrupts if disabled */ 3509 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3510 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3511 3512 netif_trans_update(dev); 3513 3514 dev->stats.tx_errors++; 3515 3516 netif_tx_wake_all_queues(dev); 3517 } 3518 3519 #define MAX_MDF_FILTER 17 3520 3521 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3522 unsigned char *addr, 3523 int *i) 3524 { 3525 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3526 UMAC_MDF_ADDR + (*i * 4)); 3527 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3528 addr[4] << 8 | addr[5], 3529 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3530 *i += 2; 3531 } 3532 3533 static void bcmgenet_set_rx_mode(struct net_device *dev) 3534 { 3535 struct bcmgenet_priv *priv = netdev_priv(dev); 3536 struct netdev_hw_addr *ha; 3537 int i, nfilter; 3538 u32 reg; 3539 3540 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3541 3542 /* Number of filters needed */ 3543 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3544 3545 /* 3546 * Turn on promicuous mode for three scenarios 3547 * 1. IFF_PROMISC flag is set 3548 * 2. IFF_ALLMULTI flag is set 3549 * 3. The number of filters needed exceeds the number filters 3550 * supported by the hardware. 3551 */ 3552 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3553 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3554 (nfilter > MAX_MDF_FILTER)) { 3555 reg |= CMD_PROMISC; 3556 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3557 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3558 return; 3559 } else { 3560 reg &= ~CMD_PROMISC; 3561 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3562 } 3563 3564 /* update MDF filter */ 3565 i = 0; 3566 /* Broadcast */ 3567 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3568 /* my own address.*/ 3569 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3570 3571 /* Unicast */ 3572 netdev_for_each_uc_addr(ha, dev) 3573 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3574 3575 /* Multicast */ 3576 netdev_for_each_mc_addr(ha, dev) 3577 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3578 3579 /* Enable filters */ 3580 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3581 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3582 } 3583 3584 /* Set the hardware MAC address. */ 3585 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3586 { 3587 struct sockaddr *addr = p; 3588 3589 /* Setting the MAC address at the hardware level is not possible 3590 * without disabling the UniMAC RX/TX enable bits. 3591 */ 3592 if (netif_running(dev)) 3593 return -EBUSY; 3594 3595 ether_addr_copy(dev->dev_addr, addr->sa_data); 3596 3597 return 0; 3598 } 3599 3600 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3601 { 3602 struct bcmgenet_priv *priv = netdev_priv(dev); 3603 unsigned long tx_bytes = 0, tx_packets = 0; 3604 unsigned long rx_bytes = 0, rx_packets = 0; 3605 unsigned long rx_errors = 0, rx_dropped = 0; 3606 struct bcmgenet_tx_ring *tx_ring; 3607 struct bcmgenet_rx_ring *rx_ring; 3608 unsigned int q; 3609 3610 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3611 tx_ring = &priv->tx_rings[q]; 3612 tx_bytes += tx_ring->bytes; 3613 tx_packets += tx_ring->packets; 3614 } 3615 tx_ring = &priv->tx_rings[DESC_INDEX]; 3616 tx_bytes += tx_ring->bytes; 3617 tx_packets += tx_ring->packets; 3618 3619 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3620 rx_ring = &priv->rx_rings[q]; 3621 3622 rx_bytes += rx_ring->bytes; 3623 rx_packets += rx_ring->packets; 3624 rx_errors += rx_ring->errors; 3625 rx_dropped += rx_ring->dropped; 3626 } 3627 rx_ring = &priv->rx_rings[DESC_INDEX]; 3628 rx_bytes += rx_ring->bytes; 3629 rx_packets += rx_ring->packets; 3630 rx_errors += rx_ring->errors; 3631 rx_dropped += rx_ring->dropped; 3632 3633 dev->stats.tx_bytes = tx_bytes; 3634 dev->stats.tx_packets = tx_packets; 3635 dev->stats.rx_bytes = rx_bytes; 3636 dev->stats.rx_packets = rx_packets; 3637 dev->stats.rx_errors = rx_errors; 3638 dev->stats.rx_missed_errors = rx_errors; 3639 dev->stats.rx_dropped = rx_dropped; 3640 return &dev->stats; 3641 } 3642 3643 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier) 3644 { 3645 struct bcmgenet_priv *priv = netdev_priv(dev); 3646 3647 if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) || 3648 priv->phy_interface != PHY_INTERFACE_MODE_MOCA) 3649 return -EOPNOTSUPP; 3650 3651 if (new_carrier) 3652 netif_carrier_on(dev); 3653 else 3654 netif_carrier_off(dev); 3655 3656 return 0; 3657 } 3658 3659 static const struct net_device_ops bcmgenet_netdev_ops = { 3660 .ndo_open = bcmgenet_open, 3661 .ndo_stop = bcmgenet_close, 3662 .ndo_start_xmit = bcmgenet_xmit, 3663 .ndo_tx_timeout = bcmgenet_timeout, 3664 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3665 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3666 .ndo_eth_ioctl = phy_do_ioctl_running, 3667 .ndo_set_features = bcmgenet_set_features, 3668 #ifdef CONFIG_NET_POLL_CONTROLLER 3669 .ndo_poll_controller = bcmgenet_poll_controller, 3670 #endif 3671 .ndo_get_stats = bcmgenet_get_stats, 3672 .ndo_change_carrier = bcmgenet_change_carrier, 3673 }; 3674 3675 /* Array of GENET hardware parameters/characteristics */ 3676 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3677 [GENET_V1] = { 3678 .tx_queues = 0, 3679 .tx_bds_per_q = 0, 3680 .rx_queues = 0, 3681 .rx_bds_per_q = 0, 3682 .bp_in_en_shift = 16, 3683 .bp_in_mask = 0xffff, 3684 .hfb_filter_cnt = 16, 3685 .qtag_mask = 0x1F, 3686 .hfb_offset = 0x1000, 3687 .rdma_offset = 0x2000, 3688 .tdma_offset = 0x3000, 3689 .words_per_bd = 2, 3690 }, 3691 [GENET_V2] = { 3692 .tx_queues = 4, 3693 .tx_bds_per_q = 32, 3694 .rx_queues = 0, 3695 .rx_bds_per_q = 0, 3696 .bp_in_en_shift = 16, 3697 .bp_in_mask = 0xffff, 3698 .hfb_filter_cnt = 16, 3699 .qtag_mask = 0x1F, 3700 .tbuf_offset = 0x0600, 3701 .hfb_offset = 0x1000, 3702 .hfb_reg_offset = 0x2000, 3703 .rdma_offset = 0x3000, 3704 .tdma_offset = 0x4000, 3705 .words_per_bd = 2, 3706 .flags = GENET_HAS_EXT, 3707 }, 3708 [GENET_V3] = { 3709 .tx_queues = 4, 3710 .tx_bds_per_q = 32, 3711 .rx_queues = 0, 3712 .rx_bds_per_q = 0, 3713 .bp_in_en_shift = 17, 3714 .bp_in_mask = 0x1ffff, 3715 .hfb_filter_cnt = 48, 3716 .hfb_filter_size = 128, 3717 .qtag_mask = 0x3F, 3718 .tbuf_offset = 0x0600, 3719 .hfb_offset = 0x8000, 3720 .hfb_reg_offset = 0xfc00, 3721 .rdma_offset = 0x10000, 3722 .tdma_offset = 0x11000, 3723 .words_per_bd = 2, 3724 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3725 GENET_HAS_MOCA_LINK_DET, 3726 }, 3727 [GENET_V4] = { 3728 .tx_queues = 4, 3729 .tx_bds_per_q = 32, 3730 .rx_queues = 0, 3731 .rx_bds_per_q = 0, 3732 .bp_in_en_shift = 17, 3733 .bp_in_mask = 0x1ffff, 3734 .hfb_filter_cnt = 48, 3735 .hfb_filter_size = 128, 3736 .qtag_mask = 0x3F, 3737 .tbuf_offset = 0x0600, 3738 .hfb_offset = 0x8000, 3739 .hfb_reg_offset = 0xfc00, 3740 .rdma_offset = 0x2000, 3741 .tdma_offset = 0x4000, 3742 .words_per_bd = 3, 3743 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3744 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3745 }, 3746 [GENET_V5] = { 3747 .tx_queues = 4, 3748 .tx_bds_per_q = 32, 3749 .rx_queues = 0, 3750 .rx_bds_per_q = 0, 3751 .bp_in_en_shift = 17, 3752 .bp_in_mask = 0x1ffff, 3753 .hfb_filter_cnt = 48, 3754 .hfb_filter_size = 128, 3755 .qtag_mask = 0x3F, 3756 .tbuf_offset = 0x0600, 3757 .hfb_offset = 0x8000, 3758 .hfb_reg_offset = 0xfc00, 3759 .rdma_offset = 0x2000, 3760 .tdma_offset = 0x4000, 3761 .words_per_bd = 3, 3762 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3763 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3764 }, 3765 }; 3766 3767 /* Infer hardware parameters from the detected GENET version */ 3768 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3769 { 3770 struct bcmgenet_hw_params *params; 3771 u32 reg; 3772 u8 major; 3773 u16 gphy_rev; 3774 3775 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3776 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3777 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3778 } else if (GENET_IS_V3(priv)) { 3779 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3780 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3781 } else if (GENET_IS_V2(priv)) { 3782 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3783 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3784 } else if (GENET_IS_V1(priv)) { 3785 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3786 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3787 } 3788 3789 /* enum genet_version starts at 1 */ 3790 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3791 params = priv->hw_params; 3792 3793 /* Read GENET HW version */ 3794 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3795 major = (reg >> 24 & 0x0f); 3796 if (major == 6) 3797 major = 5; 3798 else if (major == 5) 3799 major = 4; 3800 else if (major == 0) 3801 major = 1; 3802 if (major != priv->version) { 3803 dev_err(&priv->pdev->dev, 3804 "GENET version mismatch, got: %d, configured for: %d\n", 3805 major, priv->version); 3806 } 3807 3808 /* Print the GENET core version */ 3809 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3810 major, (reg >> 16) & 0x0f, reg & 0xffff); 3811 3812 /* Store the integrated PHY revision for the MDIO probing function 3813 * to pass this information to the PHY driver. The PHY driver expects 3814 * to find the PHY major revision in bits 15:8 while the GENET register 3815 * stores that information in bits 7:0, account for that. 3816 * 3817 * On newer chips, starting with PHY revision G0, a new scheme is 3818 * deployed similar to the Starfighter 2 switch with GPHY major 3819 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3820 * is reserved as well as special value 0x01ff, we have a small 3821 * heuristic to check for the new GPHY revision and re-arrange things 3822 * so the GPHY driver is happy. 3823 */ 3824 gphy_rev = reg & 0xffff; 3825 3826 if (GENET_IS_V5(priv)) { 3827 /* The EPHY revision should come from the MDIO registers of 3828 * the PHY not from GENET. 3829 */ 3830 if (gphy_rev != 0) { 3831 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3832 gphy_rev); 3833 } 3834 /* This is reserved so should require special treatment */ 3835 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3836 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3837 return; 3838 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3839 } else if ((gphy_rev & 0xf0) != 0) { 3840 priv->gphy_rev = gphy_rev << 8; 3841 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3842 } else if ((gphy_rev & 0xff00) != 0) { 3843 priv->gphy_rev = gphy_rev; 3844 } 3845 3846 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3847 if (!(params->flags & GENET_HAS_40BITS)) 3848 pr_warn("GENET does not support 40-bits PA\n"); 3849 #endif 3850 3851 pr_debug("Configuration for version: %d\n" 3852 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3853 "BP << en: %2d, BP msk: 0x%05x\n" 3854 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3855 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3856 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3857 "Words/BD: %d\n", 3858 priv->version, 3859 params->tx_queues, params->tx_bds_per_q, 3860 params->rx_queues, params->rx_bds_per_q, 3861 params->bp_in_en_shift, params->bp_in_mask, 3862 params->hfb_filter_cnt, params->qtag_mask, 3863 params->tbuf_offset, params->hfb_offset, 3864 params->hfb_reg_offset, 3865 params->rdma_offset, params->tdma_offset, 3866 params->words_per_bd); 3867 } 3868 3869 struct bcmgenet_plat_data { 3870 enum bcmgenet_version version; 3871 u32 dma_max_burst_length; 3872 }; 3873 3874 static const struct bcmgenet_plat_data v1_plat_data = { 3875 .version = GENET_V1, 3876 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3877 }; 3878 3879 static const struct bcmgenet_plat_data v2_plat_data = { 3880 .version = GENET_V2, 3881 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3882 }; 3883 3884 static const struct bcmgenet_plat_data v3_plat_data = { 3885 .version = GENET_V3, 3886 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3887 }; 3888 3889 static const struct bcmgenet_plat_data v4_plat_data = { 3890 .version = GENET_V4, 3891 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3892 }; 3893 3894 static const struct bcmgenet_plat_data v5_plat_data = { 3895 .version = GENET_V5, 3896 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3897 }; 3898 3899 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3900 .version = GENET_V5, 3901 .dma_max_burst_length = 0x08, 3902 }; 3903 3904 static const struct of_device_id bcmgenet_match[] = { 3905 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3906 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3907 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3908 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3909 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3910 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3911 { }, 3912 }; 3913 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3914 3915 static int bcmgenet_probe(struct platform_device *pdev) 3916 { 3917 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3918 const struct bcmgenet_plat_data *pdata; 3919 struct bcmgenet_priv *priv; 3920 struct net_device *dev; 3921 unsigned int i; 3922 int err = -EIO; 3923 3924 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3925 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3926 GENET_MAX_MQ_CNT + 1); 3927 if (!dev) { 3928 dev_err(&pdev->dev, "can't allocate net device\n"); 3929 return -ENOMEM; 3930 } 3931 3932 priv = netdev_priv(dev); 3933 priv->irq0 = platform_get_irq(pdev, 0); 3934 if (priv->irq0 < 0) { 3935 err = priv->irq0; 3936 goto err; 3937 } 3938 priv->irq1 = platform_get_irq(pdev, 1); 3939 if (priv->irq1 < 0) { 3940 err = priv->irq1; 3941 goto err; 3942 } 3943 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3944 3945 priv->base = devm_platform_ioremap_resource(pdev, 0); 3946 if (IS_ERR(priv->base)) { 3947 err = PTR_ERR(priv->base); 3948 goto err; 3949 } 3950 3951 spin_lock_init(&priv->lock); 3952 3953 SET_NETDEV_DEV(dev, &pdev->dev); 3954 dev_set_drvdata(&pdev->dev, dev); 3955 dev->watchdog_timeo = 2 * HZ; 3956 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3957 dev->netdev_ops = &bcmgenet_netdev_ops; 3958 3959 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3960 3961 /* Set default features */ 3962 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3963 NETIF_F_RXCSUM; 3964 dev->hw_features |= dev->features; 3965 dev->vlan_features |= dev->features; 3966 3967 /* Request the WOL interrupt and advertise suspend if available */ 3968 priv->wol_irq_disabled = true; 3969 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3970 dev->name, priv); 3971 if (!err) 3972 device_set_wakeup_capable(&pdev->dev, 1); 3973 3974 /* Set the needed headroom to account for any possible 3975 * features enabling/disabling at runtime 3976 */ 3977 dev->needed_headroom += 64; 3978 3979 priv->dev = dev; 3980 priv->pdev = pdev; 3981 3982 pdata = device_get_match_data(&pdev->dev); 3983 if (pdata) { 3984 priv->version = pdata->version; 3985 priv->dma_max_burst_length = pdata->dma_max_burst_length; 3986 } else { 3987 priv->version = pd->genet_version; 3988 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 3989 } 3990 3991 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 3992 if (IS_ERR(priv->clk)) { 3993 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 3994 err = PTR_ERR(priv->clk); 3995 goto err; 3996 } 3997 3998 err = clk_prepare_enable(priv->clk); 3999 if (err) 4000 goto err; 4001 4002 bcmgenet_set_hw_params(priv); 4003 4004 err = -EIO; 4005 if (priv->hw_params->flags & GENET_HAS_40BITS) 4006 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 4007 if (err) 4008 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4009 if (err) 4010 goto err_clk_disable; 4011 4012 /* Mii wait queue */ 4013 init_waitqueue_head(&priv->wq); 4014 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4015 priv->rx_buf_len = RX_BUF_LENGTH; 4016 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4017 4018 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4019 if (IS_ERR(priv->clk_wol)) { 4020 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4021 err = PTR_ERR(priv->clk_wol); 4022 goto err_clk_disable; 4023 } 4024 4025 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4026 if (IS_ERR(priv->clk_eee)) { 4027 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4028 err = PTR_ERR(priv->clk_eee); 4029 goto err_clk_disable; 4030 } 4031 4032 /* If this is an internal GPHY, power it on now, before UniMAC is 4033 * brought out of reset as absolutely no UniMAC activity is allowed 4034 */ 4035 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4036 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4037 4038 if (pd && !IS_ERR_OR_NULL(pd->mac_address)) 4039 ether_addr_copy(dev->dev_addr, pd->mac_address); 4040 else 4041 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 4042 if (has_acpi_companion(&pdev->dev)) 4043 bcmgenet_get_hw_addr(priv, dev->dev_addr); 4044 4045 if (!is_valid_ether_addr(dev->dev_addr)) { 4046 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4047 eth_hw_addr_random(dev); 4048 } 4049 4050 reset_umac(priv); 4051 4052 err = bcmgenet_mii_init(dev); 4053 if (err) 4054 goto err_clk_disable; 4055 4056 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 4057 * just the ring 16 descriptor based TX 4058 */ 4059 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4060 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4061 4062 /* Set default coalescing parameters */ 4063 for (i = 0; i < priv->hw_params->rx_queues; i++) 4064 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4065 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 4066 4067 /* libphy will determine the link state */ 4068 netif_carrier_off(dev); 4069 4070 /* Turn off the main clock, WOL clock is handled separately */ 4071 clk_disable_unprepare(priv->clk); 4072 4073 err = register_netdev(dev); 4074 if (err) { 4075 bcmgenet_mii_exit(dev); 4076 goto err; 4077 } 4078 4079 return err; 4080 4081 err_clk_disable: 4082 clk_disable_unprepare(priv->clk); 4083 err: 4084 free_netdev(dev); 4085 return err; 4086 } 4087 4088 static int bcmgenet_remove(struct platform_device *pdev) 4089 { 4090 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4091 4092 dev_set_drvdata(&pdev->dev, NULL); 4093 unregister_netdev(priv->dev); 4094 bcmgenet_mii_exit(priv->dev); 4095 free_netdev(priv->dev); 4096 4097 return 0; 4098 } 4099 4100 static void bcmgenet_shutdown(struct platform_device *pdev) 4101 { 4102 bcmgenet_remove(pdev); 4103 } 4104 4105 #ifdef CONFIG_PM_SLEEP 4106 static int bcmgenet_resume_noirq(struct device *d) 4107 { 4108 struct net_device *dev = dev_get_drvdata(d); 4109 struct bcmgenet_priv *priv = netdev_priv(dev); 4110 int ret; 4111 u32 reg; 4112 4113 if (!netif_running(dev)) 4114 return 0; 4115 4116 /* Turn on the clock */ 4117 ret = clk_prepare_enable(priv->clk); 4118 if (ret) 4119 return ret; 4120 4121 if (device_may_wakeup(d) && priv->wolopts) { 4122 /* Account for Wake-on-LAN events and clear those events 4123 * (Some devices need more time between enabling the clocks 4124 * and the interrupt register reflecting the wake event so 4125 * read the register twice) 4126 */ 4127 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4128 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4129 if (reg & UMAC_IRQ_WAKE_EVENT) 4130 pm_wakeup_event(&priv->pdev->dev, 0); 4131 } 4132 4133 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR); 4134 4135 return 0; 4136 } 4137 4138 static int bcmgenet_resume(struct device *d) 4139 { 4140 struct net_device *dev = dev_get_drvdata(d); 4141 struct bcmgenet_priv *priv = netdev_priv(dev); 4142 struct bcmgenet_rxnfc_rule *rule; 4143 unsigned long dma_ctrl; 4144 int ret; 4145 4146 if (!netif_running(dev)) 4147 return 0; 4148 4149 /* From WOL-enabled suspend, switch to regular clock */ 4150 if (device_may_wakeup(d) && priv->wolopts) 4151 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 4152 4153 /* If this is an internal GPHY, power it back on now, before UniMAC is 4154 * brought out of reset as absolutely no UniMAC activity is allowed 4155 */ 4156 if (priv->internal_phy) 4157 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4158 4159 bcmgenet_umac_reset(priv); 4160 4161 init_umac(priv); 4162 4163 phy_init_hw(dev->phydev); 4164 4165 /* Speed settings must be restored */ 4166 genphy_config_aneg(dev->phydev); 4167 bcmgenet_mii_config(priv->dev, false); 4168 4169 /* Restore enabled features */ 4170 bcmgenet_set_features(dev, dev->features); 4171 4172 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4173 4174 /* Restore hardware filters */ 4175 bcmgenet_hfb_clear(priv); 4176 list_for_each_entry(rule, &priv->rxnfc_list, list) 4177 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 4178 bcmgenet_hfb_create_rxnfc_filter(priv, rule); 4179 4180 /* Disable RX/TX DMA and flush TX queues */ 4181 dma_ctrl = bcmgenet_dma_disable(priv); 4182 4183 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4184 ret = bcmgenet_init_dma(priv); 4185 if (ret) { 4186 netdev_err(dev, "failed to initialize DMA\n"); 4187 goto out_clk_disable; 4188 } 4189 4190 /* Always enable ring 16 - descriptor ring */ 4191 bcmgenet_enable_dma(priv, dma_ctrl); 4192 4193 if (!device_may_wakeup(d)) 4194 phy_resume(dev->phydev); 4195 4196 if (priv->eee.eee_enabled) 4197 bcmgenet_eee_enable_set(dev, true); 4198 4199 bcmgenet_netif_start(dev); 4200 4201 netif_device_attach(dev); 4202 4203 return 0; 4204 4205 out_clk_disable: 4206 if (priv->internal_phy) 4207 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4208 clk_disable_unprepare(priv->clk); 4209 return ret; 4210 } 4211 4212 static int bcmgenet_suspend(struct device *d) 4213 { 4214 struct net_device *dev = dev_get_drvdata(d); 4215 struct bcmgenet_priv *priv = netdev_priv(dev); 4216 4217 if (!netif_running(dev)) 4218 return 0; 4219 4220 netif_device_detach(dev); 4221 4222 bcmgenet_netif_stop(dev); 4223 4224 if (!device_may_wakeup(d)) 4225 phy_suspend(dev->phydev); 4226 4227 /* Disable filtering */ 4228 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 4229 4230 return 0; 4231 } 4232 4233 static int bcmgenet_suspend_noirq(struct device *d) 4234 { 4235 struct net_device *dev = dev_get_drvdata(d); 4236 struct bcmgenet_priv *priv = netdev_priv(dev); 4237 int ret = 0; 4238 4239 if (!netif_running(dev)) 4240 return 0; 4241 4242 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4243 if (device_may_wakeup(d) && priv->wolopts) 4244 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4245 else if (priv->internal_phy) 4246 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4247 4248 /* Let the framework handle resumption and leave the clocks on */ 4249 if (ret) 4250 return ret; 4251 4252 /* Turn off the clocks */ 4253 clk_disable_unprepare(priv->clk); 4254 4255 return 0; 4256 } 4257 #else 4258 #define bcmgenet_suspend NULL 4259 #define bcmgenet_suspend_noirq NULL 4260 #define bcmgenet_resume NULL 4261 #define bcmgenet_resume_noirq NULL 4262 #endif /* CONFIG_PM_SLEEP */ 4263 4264 static const struct dev_pm_ops bcmgenet_pm_ops = { 4265 .suspend = bcmgenet_suspend, 4266 .suspend_noirq = bcmgenet_suspend_noirq, 4267 .resume = bcmgenet_resume, 4268 .resume_noirq = bcmgenet_resume_noirq, 4269 }; 4270 4271 static const struct acpi_device_id genet_acpi_match[] = { 4272 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4273 { }, 4274 }; 4275 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4276 4277 static struct platform_driver bcmgenet_driver = { 4278 .probe = bcmgenet_probe, 4279 .remove = bcmgenet_remove, 4280 .shutdown = bcmgenet_shutdown, 4281 .driver = { 4282 .name = "bcmgenet", 4283 .of_match_table = bcmgenet_match, 4284 .pm = &bcmgenet_pm_ops, 4285 .acpi_match_table = genet_acpi_match, 4286 }, 4287 }; 4288 module_platform_driver(bcmgenet_driver); 4289 4290 MODULE_AUTHOR("Broadcom Corporation"); 4291 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4292 MODULE_ALIAS("platform:bcmgenet"); 4293 MODULE_LICENSE("GPL"); 4294 MODULE_SOFTDEP("pre: mdio-bcm-unimac"); 4295