1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2019 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_net.h> 30 #include <linux/of_platform.h> 31 #include <net/arp.h> 32 33 #include <linux/mii.h> 34 #include <linux/ethtool.h> 35 #include <linux/netdevice.h> 36 #include <linux/inetdevice.h> 37 #include <linux/etherdevice.h> 38 #include <linux/skbuff.h> 39 #include <linux/in.h> 40 #include <linux/ip.h> 41 #include <linux/ipv6.h> 42 #include <linux/phy.h> 43 #include <linux/platform_data/bcmgenet.h> 44 45 #include <asm/unaligned.h> 46 47 #include "bcmgenet.h" 48 49 /* Maximum number of hardware queues, downsized if needed */ 50 #define GENET_MAX_MQ_CNT 4 51 52 /* Default highest priority queue for multi queue support */ 53 #define GENET_Q0_PRIORITY 0 54 55 #define GENET_Q16_RX_BD_CNT \ 56 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 57 #define GENET_Q16_TX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 59 60 #define RX_BUF_LENGTH 2048 61 #define SKB_ALIGNMENT 32 62 63 /* Tx/Rx DMA register offset, skip 256 descriptors */ 64 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 65 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 66 67 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 68 TOTAL_DESC * DMA_DESC_SIZE) 69 70 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 71 TOTAL_DESC * DMA_DESC_SIZE) 72 73 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 74 { 75 /* MIPS chips strapped for BE will automagically configure the 76 * peripheral registers for CPU-native byte order. 77 */ 78 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 79 __raw_writel(value, offset); 80 else 81 writel_relaxed(value, offset); 82 } 83 84 static inline u32 bcmgenet_readl(void __iomem *offset) 85 { 86 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 87 return __raw_readl(offset); 88 else 89 return readl_relaxed(offset); 90 } 91 92 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 93 void __iomem *d, u32 value) 94 { 95 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 96 } 97 98 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 99 void __iomem *d) 100 { 101 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS); 102 } 103 104 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 105 void __iomem *d, 106 dma_addr_t addr) 107 { 108 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 109 110 /* Register writes to GISB bus can take couple hundred nanoseconds 111 * and are done for each packet, save these expensive writes unless 112 * the platform is explicitly configured for 64-bits/LPAE. 113 */ 114 #ifdef CONFIG_PHYS_ADDR_T_64BIT 115 if (priv->hw_params->flags & GENET_HAS_40BITS) 116 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 117 #endif 118 } 119 120 /* Combined address + length/status setter */ 121 static inline void dmadesc_set(struct bcmgenet_priv *priv, 122 void __iomem *d, dma_addr_t addr, u32 val) 123 { 124 dmadesc_set_addr(priv, d, addr); 125 dmadesc_set_length_status(priv, d, val); 126 } 127 128 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 129 void __iomem *d) 130 { 131 dma_addr_t addr; 132 133 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 134 135 /* Register writes to GISB bus can take couple hundred nanoseconds 136 * and are done for each packet, save these expensive writes unless 137 * the platform is explicitly configured for 64-bits/LPAE. 138 */ 139 #ifdef CONFIG_PHYS_ADDR_T_64BIT 140 if (priv->hw_params->flags & GENET_HAS_40BITS) 141 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 142 #endif 143 return addr; 144 } 145 146 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 147 148 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 149 NETIF_MSG_LINK) 150 151 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 152 { 153 if (GENET_IS_V1(priv)) 154 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 155 else 156 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 157 } 158 159 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 160 { 161 if (GENET_IS_V1(priv)) 162 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 163 else 164 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 165 } 166 167 /* These macros are defined to deal with register map change 168 * between GENET1.1 and GENET2. Only those currently being used 169 * by driver are defined. 170 */ 171 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 172 { 173 if (GENET_IS_V1(priv)) 174 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 175 else 176 return bcmgenet_readl(priv->base + 177 priv->hw_params->tbuf_offset + TBUF_CTRL); 178 } 179 180 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 181 { 182 if (GENET_IS_V1(priv)) 183 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 184 else 185 bcmgenet_writel(val, priv->base + 186 priv->hw_params->tbuf_offset + TBUF_CTRL); 187 } 188 189 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 190 { 191 if (GENET_IS_V1(priv)) 192 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 193 else 194 return bcmgenet_readl(priv->base + 195 priv->hw_params->tbuf_offset + TBUF_BP_MC); 196 } 197 198 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 199 { 200 if (GENET_IS_V1(priv)) 201 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 202 else 203 bcmgenet_writel(val, priv->base + 204 priv->hw_params->tbuf_offset + TBUF_BP_MC); 205 } 206 207 /* RX/TX DMA register accessors */ 208 enum dma_reg { 209 DMA_RING_CFG = 0, 210 DMA_CTRL, 211 DMA_STATUS, 212 DMA_SCB_BURST_SIZE, 213 DMA_ARB_CTRL, 214 DMA_PRIORITY_0, 215 DMA_PRIORITY_1, 216 DMA_PRIORITY_2, 217 DMA_INDEX2RING_0, 218 DMA_INDEX2RING_1, 219 DMA_INDEX2RING_2, 220 DMA_INDEX2RING_3, 221 DMA_INDEX2RING_4, 222 DMA_INDEX2RING_5, 223 DMA_INDEX2RING_6, 224 DMA_INDEX2RING_7, 225 DMA_RING0_TIMEOUT, 226 DMA_RING1_TIMEOUT, 227 DMA_RING2_TIMEOUT, 228 DMA_RING3_TIMEOUT, 229 DMA_RING4_TIMEOUT, 230 DMA_RING5_TIMEOUT, 231 DMA_RING6_TIMEOUT, 232 DMA_RING7_TIMEOUT, 233 DMA_RING8_TIMEOUT, 234 DMA_RING9_TIMEOUT, 235 DMA_RING10_TIMEOUT, 236 DMA_RING11_TIMEOUT, 237 DMA_RING12_TIMEOUT, 238 DMA_RING13_TIMEOUT, 239 DMA_RING14_TIMEOUT, 240 DMA_RING15_TIMEOUT, 241 DMA_RING16_TIMEOUT, 242 }; 243 244 static const u8 bcmgenet_dma_regs_v3plus[] = { 245 [DMA_RING_CFG] = 0x00, 246 [DMA_CTRL] = 0x04, 247 [DMA_STATUS] = 0x08, 248 [DMA_SCB_BURST_SIZE] = 0x0C, 249 [DMA_ARB_CTRL] = 0x2C, 250 [DMA_PRIORITY_0] = 0x30, 251 [DMA_PRIORITY_1] = 0x34, 252 [DMA_PRIORITY_2] = 0x38, 253 [DMA_RING0_TIMEOUT] = 0x2C, 254 [DMA_RING1_TIMEOUT] = 0x30, 255 [DMA_RING2_TIMEOUT] = 0x34, 256 [DMA_RING3_TIMEOUT] = 0x38, 257 [DMA_RING4_TIMEOUT] = 0x3c, 258 [DMA_RING5_TIMEOUT] = 0x40, 259 [DMA_RING6_TIMEOUT] = 0x44, 260 [DMA_RING7_TIMEOUT] = 0x48, 261 [DMA_RING8_TIMEOUT] = 0x4c, 262 [DMA_RING9_TIMEOUT] = 0x50, 263 [DMA_RING10_TIMEOUT] = 0x54, 264 [DMA_RING11_TIMEOUT] = 0x58, 265 [DMA_RING12_TIMEOUT] = 0x5c, 266 [DMA_RING13_TIMEOUT] = 0x60, 267 [DMA_RING14_TIMEOUT] = 0x64, 268 [DMA_RING15_TIMEOUT] = 0x68, 269 [DMA_RING16_TIMEOUT] = 0x6C, 270 [DMA_INDEX2RING_0] = 0x70, 271 [DMA_INDEX2RING_1] = 0x74, 272 [DMA_INDEX2RING_2] = 0x78, 273 [DMA_INDEX2RING_3] = 0x7C, 274 [DMA_INDEX2RING_4] = 0x80, 275 [DMA_INDEX2RING_5] = 0x84, 276 [DMA_INDEX2RING_6] = 0x88, 277 [DMA_INDEX2RING_7] = 0x8C, 278 }; 279 280 static const u8 bcmgenet_dma_regs_v2[] = { 281 [DMA_RING_CFG] = 0x00, 282 [DMA_CTRL] = 0x04, 283 [DMA_STATUS] = 0x08, 284 [DMA_SCB_BURST_SIZE] = 0x0C, 285 [DMA_ARB_CTRL] = 0x30, 286 [DMA_PRIORITY_0] = 0x34, 287 [DMA_PRIORITY_1] = 0x38, 288 [DMA_PRIORITY_2] = 0x3C, 289 [DMA_RING0_TIMEOUT] = 0x2C, 290 [DMA_RING1_TIMEOUT] = 0x30, 291 [DMA_RING2_TIMEOUT] = 0x34, 292 [DMA_RING3_TIMEOUT] = 0x38, 293 [DMA_RING4_TIMEOUT] = 0x3c, 294 [DMA_RING5_TIMEOUT] = 0x40, 295 [DMA_RING6_TIMEOUT] = 0x44, 296 [DMA_RING7_TIMEOUT] = 0x48, 297 [DMA_RING8_TIMEOUT] = 0x4c, 298 [DMA_RING9_TIMEOUT] = 0x50, 299 [DMA_RING10_TIMEOUT] = 0x54, 300 [DMA_RING11_TIMEOUT] = 0x58, 301 [DMA_RING12_TIMEOUT] = 0x5c, 302 [DMA_RING13_TIMEOUT] = 0x60, 303 [DMA_RING14_TIMEOUT] = 0x64, 304 [DMA_RING15_TIMEOUT] = 0x68, 305 [DMA_RING16_TIMEOUT] = 0x6C, 306 }; 307 308 static const u8 bcmgenet_dma_regs_v1[] = { 309 [DMA_CTRL] = 0x00, 310 [DMA_STATUS] = 0x04, 311 [DMA_SCB_BURST_SIZE] = 0x0C, 312 [DMA_ARB_CTRL] = 0x30, 313 [DMA_PRIORITY_0] = 0x34, 314 [DMA_PRIORITY_1] = 0x38, 315 [DMA_PRIORITY_2] = 0x3C, 316 [DMA_RING0_TIMEOUT] = 0x2C, 317 [DMA_RING1_TIMEOUT] = 0x30, 318 [DMA_RING2_TIMEOUT] = 0x34, 319 [DMA_RING3_TIMEOUT] = 0x38, 320 [DMA_RING4_TIMEOUT] = 0x3c, 321 [DMA_RING5_TIMEOUT] = 0x40, 322 [DMA_RING6_TIMEOUT] = 0x44, 323 [DMA_RING7_TIMEOUT] = 0x48, 324 [DMA_RING8_TIMEOUT] = 0x4c, 325 [DMA_RING9_TIMEOUT] = 0x50, 326 [DMA_RING10_TIMEOUT] = 0x54, 327 [DMA_RING11_TIMEOUT] = 0x58, 328 [DMA_RING12_TIMEOUT] = 0x5c, 329 [DMA_RING13_TIMEOUT] = 0x60, 330 [DMA_RING14_TIMEOUT] = 0x64, 331 [DMA_RING15_TIMEOUT] = 0x68, 332 [DMA_RING16_TIMEOUT] = 0x6C, 333 }; 334 335 /* Set at runtime once bcmgenet version is known */ 336 static const u8 *bcmgenet_dma_regs; 337 338 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 339 { 340 return netdev_priv(dev_get_drvdata(dev)); 341 } 342 343 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 344 enum dma_reg r) 345 { 346 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 347 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 348 } 349 350 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 351 u32 val, enum dma_reg r) 352 { 353 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 354 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 355 } 356 357 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 358 enum dma_reg r) 359 { 360 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 361 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 362 } 363 364 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 365 u32 val, enum dma_reg r) 366 { 367 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 368 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 369 } 370 371 /* RDMA/TDMA ring registers and accessors 372 * we merge the common fields and just prefix with T/D the registers 373 * having different meaning depending on the direction 374 */ 375 enum dma_ring_reg { 376 TDMA_READ_PTR = 0, 377 RDMA_WRITE_PTR = TDMA_READ_PTR, 378 TDMA_READ_PTR_HI, 379 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 380 TDMA_CONS_INDEX, 381 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 382 TDMA_PROD_INDEX, 383 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 384 DMA_RING_BUF_SIZE, 385 DMA_START_ADDR, 386 DMA_START_ADDR_HI, 387 DMA_END_ADDR, 388 DMA_END_ADDR_HI, 389 DMA_MBUF_DONE_THRESH, 390 TDMA_FLOW_PERIOD, 391 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 392 TDMA_WRITE_PTR, 393 RDMA_READ_PTR = TDMA_WRITE_PTR, 394 TDMA_WRITE_PTR_HI, 395 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 396 }; 397 398 /* GENET v4 supports 40-bits pointer addressing 399 * for obvious reasons the LO and HI word parts 400 * are contiguous, but this offsets the other 401 * registers. 402 */ 403 static const u8 genet_dma_ring_regs_v4[] = { 404 [TDMA_READ_PTR] = 0x00, 405 [TDMA_READ_PTR_HI] = 0x04, 406 [TDMA_CONS_INDEX] = 0x08, 407 [TDMA_PROD_INDEX] = 0x0C, 408 [DMA_RING_BUF_SIZE] = 0x10, 409 [DMA_START_ADDR] = 0x14, 410 [DMA_START_ADDR_HI] = 0x18, 411 [DMA_END_ADDR] = 0x1C, 412 [DMA_END_ADDR_HI] = 0x20, 413 [DMA_MBUF_DONE_THRESH] = 0x24, 414 [TDMA_FLOW_PERIOD] = 0x28, 415 [TDMA_WRITE_PTR] = 0x2C, 416 [TDMA_WRITE_PTR_HI] = 0x30, 417 }; 418 419 static const u8 genet_dma_ring_regs_v123[] = { 420 [TDMA_READ_PTR] = 0x00, 421 [TDMA_CONS_INDEX] = 0x04, 422 [TDMA_PROD_INDEX] = 0x08, 423 [DMA_RING_BUF_SIZE] = 0x0C, 424 [DMA_START_ADDR] = 0x10, 425 [DMA_END_ADDR] = 0x14, 426 [DMA_MBUF_DONE_THRESH] = 0x18, 427 [TDMA_FLOW_PERIOD] = 0x1C, 428 [TDMA_WRITE_PTR] = 0x20, 429 }; 430 431 /* Set at runtime once GENET version is known */ 432 static const u8 *genet_dma_ring_regs; 433 434 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 435 unsigned int ring, 436 enum dma_ring_reg r) 437 { 438 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 439 (DMA_RING_SIZE * ring) + 440 genet_dma_ring_regs[r]); 441 } 442 443 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 444 unsigned int ring, u32 val, 445 enum dma_ring_reg r) 446 { 447 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 448 (DMA_RING_SIZE * ring) + 449 genet_dma_ring_regs[r]); 450 } 451 452 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 453 unsigned int ring, 454 enum dma_ring_reg r) 455 { 456 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 457 (DMA_RING_SIZE * ring) + 458 genet_dma_ring_regs[r]); 459 } 460 461 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 462 unsigned int ring, u32 val, 463 enum dma_ring_reg r) 464 { 465 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 466 (DMA_RING_SIZE * ring) + 467 genet_dma_ring_regs[r]); 468 } 469 470 static int bcmgenet_begin(struct net_device *dev) 471 { 472 struct bcmgenet_priv *priv = netdev_priv(dev); 473 474 /* Turn on the clock */ 475 return clk_prepare_enable(priv->clk); 476 } 477 478 static void bcmgenet_complete(struct net_device *dev) 479 { 480 struct bcmgenet_priv *priv = netdev_priv(dev); 481 482 /* Turn off the clock */ 483 clk_disable_unprepare(priv->clk); 484 } 485 486 static int bcmgenet_get_link_ksettings(struct net_device *dev, 487 struct ethtool_link_ksettings *cmd) 488 { 489 if (!netif_running(dev)) 490 return -EINVAL; 491 492 if (!dev->phydev) 493 return -ENODEV; 494 495 phy_ethtool_ksettings_get(dev->phydev, cmd); 496 497 return 0; 498 } 499 500 static int bcmgenet_set_link_ksettings(struct net_device *dev, 501 const struct ethtool_link_ksettings *cmd) 502 { 503 if (!netif_running(dev)) 504 return -EINVAL; 505 506 if (!dev->phydev) 507 return -ENODEV; 508 509 return phy_ethtool_ksettings_set(dev->phydev, cmd); 510 } 511 512 static void bcmgenet_set_rx_csum(struct net_device *dev, 513 netdev_features_t wanted) 514 { 515 struct bcmgenet_priv *priv = netdev_priv(dev); 516 u32 rbuf_chk_ctrl; 517 bool rx_csum_en; 518 519 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 520 521 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 522 523 /* enable rx checksumming */ 524 if (rx_csum_en) 525 rbuf_chk_ctrl |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 526 else 527 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 528 priv->desc_rxchk_en = rx_csum_en; 529 530 /* If UniMAC forwards CRC, we need to skip over it to get 531 * a valid CHK bit to be set in the per-packet status word 532 */ 533 if (rx_csum_en && priv->crc_fwd_en) 534 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 535 else 536 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 537 538 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 539 } 540 541 static void bcmgenet_set_tx_csum(struct net_device *dev, 542 netdev_features_t wanted) 543 { 544 struct bcmgenet_priv *priv = netdev_priv(dev); 545 bool desc_64b_en; 546 u32 tbuf_ctrl, rbuf_ctrl; 547 548 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 549 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 550 551 desc_64b_en = !!(wanted & NETIF_F_HW_CSUM); 552 553 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 554 if (desc_64b_en) { 555 tbuf_ctrl |= RBUF_64B_EN; 556 rbuf_ctrl |= RBUF_64B_EN; 557 } else { 558 tbuf_ctrl &= ~RBUF_64B_EN; 559 rbuf_ctrl &= ~RBUF_64B_EN; 560 } 561 priv->desc_64b_en = desc_64b_en; 562 563 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 564 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 565 } 566 567 static int bcmgenet_set_features(struct net_device *dev, 568 netdev_features_t features) 569 { 570 struct bcmgenet_priv *priv = netdev_priv(dev); 571 u32 reg; 572 int ret; 573 574 ret = clk_prepare_enable(priv->clk); 575 if (ret) 576 return ret; 577 578 /* Make sure we reflect the value of CRC_CMD_FWD */ 579 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 580 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 581 582 bcmgenet_set_tx_csum(dev, features); 583 bcmgenet_set_rx_csum(dev, features); 584 585 clk_disable_unprepare(priv->clk); 586 587 return ret; 588 } 589 590 static u32 bcmgenet_get_msglevel(struct net_device *dev) 591 { 592 struct bcmgenet_priv *priv = netdev_priv(dev); 593 594 return priv->msg_enable; 595 } 596 597 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 598 { 599 struct bcmgenet_priv *priv = netdev_priv(dev); 600 601 priv->msg_enable = level; 602 } 603 604 static int bcmgenet_get_coalesce(struct net_device *dev, 605 struct ethtool_coalesce *ec) 606 { 607 struct bcmgenet_priv *priv = netdev_priv(dev); 608 struct bcmgenet_rx_ring *ring; 609 unsigned int i; 610 611 ec->tx_max_coalesced_frames = 612 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 613 DMA_MBUF_DONE_THRESH); 614 ec->rx_max_coalesced_frames = 615 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 616 DMA_MBUF_DONE_THRESH); 617 ec->rx_coalesce_usecs = 618 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 619 620 for (i = 0; i < priv->hw_params->rx_queues; i++) { 621 ring = &priv->rx_rings[i]; 622 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 623 } 624 ring = &priv->rx_rings[DESC_INDEX]; 625 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 626 627 return 0; 628 } 629 630 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 631 u32 usecs, u32 pkts) 632 { 633 struct bcmgenet_priv *priv = ring->priv; 634 unsigned int i = ring->index; 635 u32 reg; 636 637 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 638 639 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 640 reg &= ~DMA_TIMEOUT_MASK; 641 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 642 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 643 } 644 645 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 646 struct ethtool_coalesce *ec) 647 { 648 struct dim_cq_moder moder; 649 u32 usecs, pkts; 650 651 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 652 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 653 usecs = ring->rx_coalesce_usecs; 654 pkts = ring->rx_max_coalesced_frames; 655 656 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 657 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 658 usecs = moder.usec; 659 pkts = moder.pkts; 660 } 661 662 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 663 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 664 } 665 666 static int bcmgenet_set_coalesce(struct net_device *dev, 667 struct ethtool_coalesce *ec) 668 { 669 struct bcmgenet_priv *priv = netdev_priv(dev); 670 unsigned int i; 671 672 /* Base system clock is 125Mhz, DMA timeout is this reference clock 673 * divided by 1024, which yields roughly 8.192us, our maximum value 674 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 675 */ 676 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 677 ec->tx_max_coalesced_frames == 0 || 678 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 679 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 680 return -EINVAL; 681 682 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 683 return -EINVAL; 684 685 /* GENET TDMA hardware does not support a configurable timeout, but will 686 * always generate an interrupt either after MBDONE packets have been 687 * transmitted, or when the ring is empty. 688 */ 689 690 /* Program all TX queues with the same values, as there is no 691 * ethtool knob to do coalescing on a per-queue basis 692 */ 693 for (i = 0; i < priv->hw_params->tx_queues; i++) 694 bcmgenet_tdma_ring_writel(priv, i, 695 ec->tx_max_coalesced_frames, 696 DMA_MBUF_DONE_THRESH); 697 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 698 ec->tx_max_coalesced_frames, 699 DMA_MBUF_DONE_THRESH); 700 701 for (i = 0; i < priv->hw_params->rx_queues; i++) 702 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 703 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 704 705 return 0; 706 } 707 708 /* standard ethtool support functions. */ 709 enum bcmgenet_stat_type { 710 BCMGENET_STAT_NETDEV = -1, 711 BCMGENET_STAT_MIB_RX, 712 BCMGENET_STAT_MIB_TX, 713 BCMGENET_STAT_RUNT, 714 BCMGENET_STAT_MISC, 715 BCMGENET_STAT_SOFT, 716 }; 717 718 struct bcmgenet_stats { 719 char stat_string[ETH_GSTRING_LEN]; 720 int stat_sizeof; 721 int stat_offset; 722 enum bcmgenet_stat_type type; 723 /* reg offset from UMAC base for misc counters */ 724 u16 reg_offset; 725 }; 726 727 #define STAT_NETDEV(m) { \ 728 .stat_string = __stringify(m), \ 729 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 730 .stat_offset = offsetof(struct net_device_stats, m), \ 731 .type = BCMGENET_STAT_NETDEV, \ 732 } 733 734 #define STAT_GENET_MIB(str, m, _type) { \ 735 .stat_string = str, \ 736 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 737 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 738 .type = _type, \ 739 } 740 741 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 742 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 743 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 744 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 745 746 #define STAT_GENET_MISC(str, m, offset) { \ 747 .stat_string = str, \ 748 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 749 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 750 .type = BCMGENET_STAT_MISC, \ 751 .reg_offset = offset, \ 752 } 753 754 #define STAT_GENET_Q(num) \ 755 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 756 tx_rings[num].packets), \ 757 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 758 tx_rings[num].bytes), \ 759 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 760 rx_rings[num].bytes), \ 761 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 762 rx_rings[num].packets), \ 763 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 764 rx_rings[num].errors), \ 765 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 766 rx_rings[num].dropped) 767 768 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 769 * between the end of TX stats and the beginning of the RX RUNT 770 */ 771 #define BCMGENET_STAT_OFFSET 0xc 772 773 /* Hardware counters must be kept in sync because the order/offset 774 * is important here (order in structure declaration = order in hardware) 775 */ 776 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 777 /* general stats */ 778 STAT_NETDEV(rx_packets), 779 STAT_NETDEV(tx_packets), 780 STAT_NETDEV(rx_bytes), 781 STAT_NETDEV(tx_bytes), 782 STAT_NETDEV(rx_errors), 783 STAT_NETDEV(tx_errors), 784 STAT_NETDEV(rx_dropped), 785 STAT_NETDEV(tx_dropped), 786 STAT_NETDEV(multicast), 787 /* UniMAC RSV counters */ 788 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 789 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 790 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 791 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 792 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 793 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 794 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 795 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 796 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 797 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 798 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 799 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 800 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 801 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 802 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 803 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 804 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 805 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 806 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 807 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 808 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 809 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 810 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 811 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 812 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 813 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 814 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 815 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 816 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 817 /* UniMAC TSV counters */ 818 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 819 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 820 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 821 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 822 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 823 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 824 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 825 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 826 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 827 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 828 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 829 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 830 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 831 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 832 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 833 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 834 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 835 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 836 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 837 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 838 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 839 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 840 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 841 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 842 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 843 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 844 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 845 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 846 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 847 /* UniMAC RUNT counters */ 848 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 849 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 850 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 851 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 852 /* Misc UniMAC counters */ 853 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 854 UMAC_RBUF_OVFL_CNT_V1), 855 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 856 UMAC_RBUF_ERR_CNT_V1), 857 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 858 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 859 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 860 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 861 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 862 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 863 mib.tx_realloc_tsb_failed), 864 /* Per TX queues */ 865 STAT_GENET_Q(0), 866 STAT_GENET_Q(1), 867 STAT_GENET_Q(2), 868 STAT_GENET_Q(3), 869 STAT_GENET_Q(16), 870 }; 871 872 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 873 874 static void bcmgenet_get_drvinfo(struct net_device *dev, 875 struct ethtool_drvinfo *info) 876 { 877 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 878 } 879 880 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 881 { 882 switch (string_set) { 883 case ETH_SS_STATS: 884 return BCMGENET_STATS_LEN; 885 default: 886 return -EOPNOTSUPP; 887 } 888 } 889 890 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 891 u8 *data) 892 { 893 int i; 894 895 switch (stringset) { 896 case ETH_SS_STATS: 897 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 898 memcpy(data + i * ETH_GSTRING_LEN, 899 bcmgenet_gstrings_stats[i].stat_string, 900 ETH_GSTRING_LEN); 901 } 902 break; 903 } 904 } 905 906 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 907 { 908 u16 new_offset; 909 u32 val; 910 911 switch (offset) { 912 case UMAC_RBUF_OVFL_CNT_V1: 913 if (GENET_IS_V2(priv)) 914 new_offset = RBUF_OVFL_CNT_V2; 915 else 916 new_offset = RBUF_OVFL_CNT_V3PLUS; 917 918 val = bcmgenet_rbuf_readl(priv, new_offset); 919 /* clear if overflowed */ 920 if (val == ~0) 921 bcmgenet_rbuf_writel(priv, 0, new_offset); 922 break; 923 case UMAC_RBUF_ERR_CNT_V1: 924 if (GENET_IS_V2(priv)) 925 new_offset = RBUF_ERR_CNT_V2; 926 else 927 new_offset = RBUF_ERR_CNT_V3PLUS; 928 929 val = bcmgenet_rbuf_readl(priv, new_offset); 930 /* clear if overflowed */ 931 if (val == ~0) 932 bcmgenet_rbuf_writel(priv, 0, new_offset); 933 break; 934 default: 935 val = bcmgenet_umac_readl(priv, offset); 936 /* clear if overflowed */ 937 if (val == ~0) 938 bcmgenet_umac_writel(priv, 0, offset); 939 break; 940 } 941 942 return val; 943 } 944 945 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 946 { 947 int i, j = 0; 948 949 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 950 const struct bcmgenet_stats *s; 951 u8 offset = 0; 952 u32 val = 0; 953 char *p; 954 955 s = &bcmgenet_gstrings_stats[i]; 956 switch (s->type) { 957 case BCMGENET_STAT_NETDEV: 958 case BCMGENET_STAT_SOFT: 959 continue; 960 case BCMGENET_STAT_RUNT: 961 offset += BCMGENET_STAT_OFFSET; 962 /* fall through */ 963 case BCMGENET_STAT_MIB_TX: 964 offset += BCMGENET_STAT_OFFSET; 965 /* fall through */ 966 case BCMGENET_STAT_MIB_RX: 967 val = bcmgenet_umac_readl(priv, 968 UMAC_MIB_START + j + offset); 969 offset = 0; /* Reset Offset */ 970 break; 971 case BCMGENET_STAT_MISC: 972 if (GENET_IS_V1(priv)) { 973 val = bcmgenet_umac_readl(priv, s->reg_offset); 974 /* clear if overflowed */ 975 if (val == ~0) 976 bcmgenet_umac_writel(priv, 0, 977 s->reg_offset); 978 } else { 979 val = bcmgenet_update_stat_misc(priv, 980 s->reg_offset); 981 } 982 break; 983 } 984 985 j += s->stat_sizeof; 986 p = (char *)priv + s->stat_offset; 987 *(u32 *)p = val; 988 } 989 } 990 991 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 992 struct ethtool_stats *stats, 993 u64 *data) 994 { 995 struct bcmgenet_priv *priv = netdev_priv(dev); 996 int i; 997 998 if (netif_running(dev)) 999 bcmgenet_update_mib_counters(priv); 1000 1001 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1002 const struct bcmgenet_stats *s; 1003 char *p; 1004 1005 s = &bcmgenet_gstrings_stats[i]; 1006 if (s->type == BCMGENET_STAT_NETDEV) 1007 p = (char *)&dev->stats; 1008 else 1009 p = (char *)priv; 1010 p += s->stat_offset; 1011 if (sizeof(unsigned long) != sizeof(u32) && 1012 s->stat_sizeof == sizeof(unsigned long)) 1013 data[i] = *(unsigned long *)p; 1014 else 1015 data[i] = *(u32 *)p; 1016 } 1017 } 1018 1019 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1020 { 1021 struct bcmgenet_priv *priv = netdev_priv(dev); 1022 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1023 u32 reg; 1024 1025 if (enable && !priv->clk_eee_enabled) { 1026 clk_prepare_enable(priv->clk_eee); 1027 priv->clk_eee_enabled = true; 1028 } 1029 1030 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1031 if (enable) 1032 reg |= EEE_EN; 1033 else 1034 reg &= ~EEE_EN; 1035 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1036 1037 /* Enable EEE and switch to a 27Mhz clock automatically */ 1038 reg = bcmgenet_readl(priv->base + off); 1039 if (enable) 1040 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1041 else 1042 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1043 bcmgenet_writel(reg, priv->base + off); 1044 1045 /* Do the same for thing for RBUF */ 1046 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1047 if (enable) 1048 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1049 else 1050 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1051 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1052 1053 if (!enable && priv->clk_eee_enabled) { 1054 clk_disable_unprepare(priv->clk_eee); 1055 priv->clk_eee_enabled = false; 1056 } 1057 1058 priv->eee.eee_enabled = enable; 1059 priv->eee.eee_active = enable; 1060 } 1061 1062 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1063 { 1064 struct bcmgenet_priv *priv = netdev_priv(dev); 1065 struct ethtool_eee *p = &priv->eee; 1066 1067 if (GENET_IS_V1(priv)) 1068 return -EOPNOTSUPP; 1069 1070 if (!dev->phydev) 1071 return -ENODEV; 1072 1073 e->eee_enabled = p->eee_enabled; 1074 e->eee_active = p->eee_active; 1075 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1076 1077 return phy_ethtool_get_eee(dev->phydev, e); 1078 } 1079 1080 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1081 { 1082 struct bcmgenet_priv *priv = netdev_priv(dev); 1083 struct ethtool_eee *p = &priv->eee; 1084 int ret = 0; 1085 1086 if (GENET_IS_V1(priv)) 1087 return -EOPNOTSUPP; 1088 1089 if (!dev->phydev) 1090 return -ENODEV; 1091 1092 p->eee_enabled = e->eee_enabled; 1093 1094 if (!p->eee_enabled) { 1095 bcmgenet_eee_enable_set(dev, false); 1096 } else { 1097 ret = phy_init_eee(dev->phydev, 0); 1098 if (ret) { 1099 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1100 return ret; 1101 } 1102 1103 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1104 bcmgenet_eee_enable_set(dev, true); 1105 } 1106 1107 return phy_ethtool_set_eee(dev->phydev, e); 1108 } 1109 1110 /* standard ethtool support functions. */ 1111 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1112 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1113 ETHTOOL_COALESCE_MAX_FRAMES | 1114 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1115 .begin = bcmgenet_begin, 1116 .complete = bcmgenet_complete, 1117 .get_strings = bcmgenet_get_strings, 1118 .get_sset_count = bcmgenet_get_sset_count, 1119 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1120 .get_drvinfo = bcmgenet_get_drvinfo, 1121 .get_link = ethtool_op_get_link, 1122 .get_msglevel = bcmgenet_get_msglevel, 1123 .set_msglevel = bcmgenet_set_msglevel, 1124 .get_wol = bcmgenet_get_wol, 1125 .set_wol = bcmgenet_set_wol, 1126 .get_eee = bcmgenet_get_eee, 1127 .set_eee = bcmgenet_set_eee, 1128 .nway_reset = phy_ethtool_nway_reset, 1129 .get_coalesce = bcmgenet_get_coalesce, 1130 .set_coalesce = bcmgenet_set_coalesce, 1131 .get_link_ksettings = bcmgenet_get_link_ksettings, 1132 .set_link_ksettings = bcmgenet_set_link_ksettings, 1133 .get_ts_info = ethtool_op_get_ts_info, 1134 }; 1135 1136 /* Power down the unimac, based on mode. */ 1137 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1138 enum bcmgenet_power_mode mode) 1139 { 1140 int ret = 0; 1141 u32 reg; 1142 1143 switch (mode) { 1144 case GENET_POWER_CABLE_SENSE: 1145 phy_detach(priv->dev->phydev); 1146 break; 1147 1148 case GENET_POWER_WOL_MAGIC: 1149 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1150 break; 1151 1152 case GENET_POWER_PASSIVE: 1153 /* Power down LED */ 1154 if (priv->hw_params->flags & GENET_HAS_EXT) { 1155 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1156 if (GENET_IS_V5(priv)) 1157 reg |= EXT_PWR_DOWN_PHY_EN | 1158 EXT_PWR_DOWN_PHY_RD | 1159 EXT_PWR_DOWN_PHY_SD | 1160 EXT_PWR_DOWN_PHY_RX | 1161 EXT_PWR_DOWN_PHY_TX | 1162 EXT_IDDQ_GLBL_PWR; 1163 else 1164 reg |= EXT_PWR_DOWN_PHY; 1165 1166 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1167 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1168 1169 bcmgenet_phy_power_set(priv->dev, false); 1170 } 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 return ret; 1177 } 1178 1179 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1180 enum bcmgenet_power_mode mode) 1181 { 1182 u32 reg; 1183 1184 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1185 return; 1186 1187 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1188 1189 switch (mode) { 1190 case GENET_POWER_PASSIVE: 1191 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1192 if (GENET_IS_V5(priv)) { 1193 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1194 EXT_PWR_DOWN_PHY_RD | 1195 EXT_PWR_DOWN_PHY_SD | 1196 EXT_PWR_DOWN_PHY_RX | 1197 EXT_PWR_DOWN_PHY_TX | 1198 EXT_IDDQ_GLBL_PWR); 1199 reg |= EXT_PHY_RESET; 1200 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1201 mdelay(1); 1202 1203 reg &= ~EXT_PHY_RESET; 1204 } else { 1205 reg &= ~EXT_PWR_DOWN_PHY; 1206 reg |= EXT_PWR_DN_EN_LD; 1207 } 1208 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1209 bcmgenet_phy_power_set(priv->dev, true); 1210 break; 1211 1212 case GENET_POWER_CABLE_SENSE: 1213 /* enable APD */ 1214 if (!GENET_IS_V5(priv)) { 1215 reg |= EXT_PWR_DN_EN_LD; 1216 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1217 } 1218 break; 1219 case GENET_POWER_WOL_MAGIC: 1220 bcmgenet_wol_power_up_cfg(priv, mode); 1221 return; 1222 default: 1223 break; 1224 } 1225 } 1226 1227 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1228 struct bcmgenet_tx_ring *ring) 1229 { 1230 struct enet_cb *tx_cb_ptr; 1231 1232 tx_cb_ptr = ring->cbs; 1233 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1234 1235 /* Advancing local write pointer */ 1236 if (ring->write_ptr == ring->end_ptr) 1237 ring->write_ptr = ring->cb_ptr; 1238 else 1239 ring->write_ptr++; 1240 1241 return tx_cb_ptr; 1242 } 1243 1244 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1245 struct bcmgenet_tx_ring *ring) 1246 { 1247 struct enet_cb *tx_cb_ptr; 1248 1249 tx_cb_ptr = ring->cbs; 1250 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1251 1252 /* Rewinding local write pointer */ 1253 if (ring->write_ptr == ring->cb_ptr) 1254 ring->write_ptr = ring->end_ptr; 1255 else 1256 ring->write_ptr--; 1257 1258 return tx_cb_ptr; 1259 } 1260 1261 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1262 { 1263 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1264 INTRL2_CPU_MASK_SET); 1265 } 1266 1267 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1268 { 1269 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1270 INTRL2_CPU_MASK_CLEAR); 1271 } 1272 1273 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1274 { 1275 bcmgenet_intrl2_1_writel(ring->priv, 1276 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1277 INTRL2_CPU_MASK_SET); 1278 } 1279 1280 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1281 { 1282 bcmgenet_intrl2_1_writel(ring->priv, 1283 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1284 INTRL2_CPU_MASK_CLEAR); 1285 } 1286 1287 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1288 { 1289 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1290 INTRL2_CPU_MASK_SET); 1291 } 1292 1293 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1294 { 1295 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1296 INTRL2_CPU_MASK_CLEAR); 1297 } 1298 1299 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1300 { 1301 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1302 INTRL2_CPU_MASK_CLEAR); 1303 } 1304 1305 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1306 { 1307 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1308 INTRL2_CPU_MASK_SET); 1309 } 1310 1311 /* Simple helper to free a transmit control block's resources 1312 * Returns an skb when the last transmit control block associated with the 1313 * skb is freed. The skb should be freed by the caller if necessary. 1314 */ 1315 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1316 struct enet_cb *cb) 1317 { 1318 struct sk_buff *skb; 1319 1320 skb = cb->skb; 1321 1322 if (skb) { 1323 cb->skb = NULL; 1324 if (cb == GENET_CB(skb)->first_cb) 1325 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1326 dma_unmap_len(cb, dma_len), 1327 DMA_TO_DEVICE); 1328 else 1329 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1330 dma_unmap_len(cb, dma_len), 1331 DMA_TO_DEVICE); 1332 dma_unmap_addr_set(cb, dma_addr, 0); 1333 1334 if (cb == GENET_CB(skb)->last_cb) 1335 return skb; 1336 1337 } else if (dma_unmap_addr(cb, dma_addr)) { 1338 dma_unmap_page(dev, 1339 dma_unmap_addr(cb, dma_addr), 1340 dma_unmap_len(cb, dma_len), 1341 DMA_TO_DEVICE); 1342 dma_unmap_addr_set(cb, dma_addr, 0); 1343 } 1344 1345 return NULL; 1346 } 1347 1348 /* Simple helper to free a receive control block's resources */ 1349 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1350 struct enet_cb *cb) 1351 { 1352 struct sk_buff *skb; 1353 1354 skb = cb->skb; 1355 cb->skb = NULL; 1356 1357 if (dma_unmap_addr(cb, dma_addr)) { 1358 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1359 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1360 dma_unmap_addr_set(cb, dma_addr, 0); 1361 } 1362 1363 return skb; 1364 } 1365 1366 /* Unlocked version of the reclaim routine */ 1367 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1368 struct bcmgenet_tx_ring *ring) 1369 { 1370 struct bcmgenet_priv *priv = netdev_priv(dev); 1371 unsigned int txbds_processed = 0; 1372 unsigned int bytes_compl = 0; 1373 unsigned int pkts_compl = 0; 1374 unsigned int txbds_ready; 1375 unsigned int c_index; 1376 struct sk_buff *skb; 1377 1378 /* Clear status before servicing to reduce spurious interrupts */ 1379 if (ring->index == DESC_INDEX) 1380 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1381 INTRL2_CPU_CLEAR); 1382 else 1383 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1384 INTRL2_CPU_CLEAR); 1385 1386 /* Compute how many buffers are transmitted since last xmit call */ 1387 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1388 & DMA_C_INDEX_MASK; 1389 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1390 1391 netif_dbg(priv, tx_done, dev, 1392 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1393 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1394 1395 /* Reclaim transmitted buffers */ 1396 while (txbds_processed < txbds_ready) { 1397 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1398 &priv->tx_cbs[ring->clean_ptr]); 1399 if (skb) { 1400 pkts_compl++; 1401 bytes_compl += GENET_CB(skb)->bytes_sent; 1402 dev_consume_skb_any(skb); 1403 } 1404 1405 txbds_processed++; 1406 if (likely(ring->clean_ptr < ring->end_ptr)) 1407 ring->clean_ptr++; 1408 else 1409 ring->clean_ptr = ring->cb_ptr; 1410 } 1411 1412 ring->free_bds += txbds_processed; 1413 ring->c_index = c_index; 1414 1415 ring->packets += pkts_compl; 1416 ring->bytes += bytes_compl; 1417 1418 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1419 pkts_compl, bytes_compl); 1420 1421 return txbds_processed; 1422 } 1423 1424 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1425 struct bcmgenet_tx_ring *ring) 1426 { 1427 unsigned int released; 1428 1429 spin_lock_bh(&ring->lock); 1430 released = __bcmgenet_tx_reclaim(dev, ring); 1431 spin_unlock_bh(&ring->lock); 1432 1433 return released; 1434 } 1435 1436 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1437 { 1438 struct bcmgenet_tx_ring *ring = 1439 container_of(napi, struct bcmgenet_tx_ring, napi); 1440 unsigned int work_done = 0; 1441 struct netdev_queue *txq; 1442 1443 spin_lock(&ring->lock); 1444 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1445 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1446 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1447 netif_tx_wake_queue(txq); 1448 } 1449 spin_unlock(&ring->lock); 1450 1451 if (work_done == 0) { 1452 napi_complete(napi); 1453 ring->int_enable(ring); 1454 1455 return 0; 1456 } 1457 1458 return budget; 1459 } 1460 1461 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1462 { 1463 struct bcmgenet_priv *priv = netdev_priv(dev); 1464 int i; 1465 1466 if (netif_is_multiqueue(dev)) { 1467 for (i = 0; i < priv->hw_params->tx_queues; i++) 1468 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1469 } 1470 1471 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1472 } 1473 1474 /* Reallocate the SKB to put enough headroom in front of it and insert 1475 * the transmit checksum offsets in the descriptors 1476 */ 1477 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1478 struct sk_buff *skb) 1479 { 1480 struct bcmgenet_priv *priv = netdev_priv(dev); 1481 struct status_64 *status = NULL; 1482 struct sk_buff *new_skb; 1483 u16 offset; 1484 u8 ip_proto; 1485 __be16 ip_ver; 1486 u32 tx_csum_info; 1487 1488 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1489 /* If 64 byte status block enabled, must make sure skb has 1490 * enough headroom for us to insert 64B status block. 1491 */ 1492 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1493 if (!new_skb) { 1494 dev_kfree_skb_any(skb); 1495 priv->mib.tx_realloc_tsb_failed++; 1496 dev->stats.tx_dropped++; 1497 return NULL; 1498 } 1499 dev_consume_skb_any(skb); 1500 skb = new_skb; 1501 priv->mib.tx_realloc_tsb++; 1502 } 1503 1504 skb_push(skb, sizeof(*status)); 1505 status = (struct status_64 *)skb->data; 1506 1507 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1508 ip_ver = skb->protocol; 1509 switch (ip_ver) { 1510 case htons(ETH_P_IP): 1511 ip_proto = ip_hdr(skb)->protocol; 1512 break; 1513 case htons(ETH_P_IPV6): 1514 ip_proto = ipv6_hdr(skb)->nexthdr; 1515 break; 1516 default: 1517 /* don't use UDP flag */ 1518 ip_proto = 0; 1519 break; 1520 } 1521 1522 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1523 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1524 (offset + skb->csum_offset) | 1525 STATUS_TX_CSUM_LV; 1526 1527 /* Set the special UDP flag for UDP */ 1528 if (ip_proto == IPPROTO_UDP) 1529 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1530 1531 status->tx_csum_info = tx_csum_info; 1532 } 1533 1534 return skb; 1535 } 1536 1537 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1538 { 1539 struct bcmgenet_priv *priv = netdev_priv(dev); 1540 struct device *kdev = &priv->pdev->dev; 1541 struct bcmgenet_tx_ring *ring = NULL; 1542 struct enet_cb *tx_cb_ptr; 1543 struct netdev_queue *txq; 1544 int nr_frags, index; 1545 dma_addr_t mapping; 1546 unsigned int size; 1547 skb_frag_t *frag; 1548 u32 len_stat; 1549 int ret; 1550 int i; 1551 1552 index = skb_get_queue_mapping(skb); 1553 /* Mapping strategy: 1554 * queue_mapping = 0, unclassified, packet xmited through ring16 1555 * queue_mapping = 1, goes to ring 0. (highest priority queue 1556 * queue_mapping = 2, goes to ring 1. 1557 * queue_mapping = 3, goes to ring 2. 1558 * queue_mapping = 4, goes to ring 3. 1559 */ 1560 if (index == 0) 1561 index = DESC_INDEX; 1562 else 1563 index -= 1; 1564 1565 ring = &priv->tx_rings[index]; 1566 txq = netdev_get_tx_queue(dev, ring->queue); 1567 1568 nr_frags = skb_shinfo(skb)->nr_frags; 1569 1570 spin_lock(&ring->lock); 1571 if (ring->free_bds <= (nr_frags + 1)) { 1572 if (!netif_tx_queue_stopped(txq)) { 1573 netif_tx_stop_queue(txq); 1574 netdev_err(dev, 1575 "%s: tx ring %d full when queue %d awake\n", 1576 __func__, index, ring->queue); 1577 } 1578 ret = NETDEV_TX_BUSY; 1579 goto out; 1580 } 1581 1582 if (skb_padto(skb, ETH_ZLEN)) { 1583 ret = NETDEV_TX_OK; 1584 goto out; 1585 } 1586 1587 /* Retain how many bytes will be sent on the wire, without TSB inserted 1588 * by transmit checksum offload 1589 */ 1590 GENET_CB(skb)->bytes_sent = skb->len; 1591 1592 /* set the SKB transmit checksum */ 1593 if (priv->desc_64b_en) { 1594 skb = bcmgenet_put_tx_csum(dev, skb); 1595 if (!skb) { 1596 ret = NETDEV_TX_OK; 1597 goto out; 1598 } 1599 } 1600 1601 for (i = 0; i <= nr_frags; i++) { 1602 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1603 1604 BUG_ON(!tx_cb_ptr); 1605 1606 if (!i) { 1607 /* Transmit single SKB or head of fragment list */ 1608 GENET_CB(skb)->first_cb = tx_cb_ptr; 1609 size = skb_headlen(skb); 1610 mapping = dma_map_single(kdev, skb->data, size, 1611 DMA_TO_DEVICE); 1612 } else { 1613 /* xmit fragment */ 1614 frag = &skb_shinfo(skb)->frags[i - 1]; 1615 size = skb_frag_size(frag); 1616 mapping = skb_frag_dma_map(kdev, frag, 0, size, 1617 DMA_TO_DEVICE); 1618 } 1619 1620 ret = dma_mapping_error(kdev, mapping); 1621 if (ret) { 1622 priv->mib.tx_dma_failed++; 1623 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1624 ret = NETDEV_TX_OK; 1625 goto out_unmap_frags; 1626 } 1627 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1628 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 1629 1630 tx_cb_ptr->skb = skb; 1631 1632 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 1633 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 1634 1635 if (!i) { 1636 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 1637 if (skb->ip_summed == CHECKSUM_PARTIAL) 1638 len_stat |= DMA_TX_DO_CSUM; 1639 } 1640 if (i == nr_frags) 1641 len_stat |= DMA_EOP; 1642 1643 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 1644 } 1645 1646 GENET_CB(skb)->last_cb = tx_cb_ptr; 1647 skb_tx_timestamp(skb); 1648 1649 /* Decrement total BD count and advance our write pointer */ 1650 ring->free_bds -= nr_frags + 1; 1651 ring->prod_index += nr_frags + 1; 1652 ring->prod_index &= DMA_P_INDEX_MASK; 1653 1654 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1655 1656 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1657 netif_tx_stop_queue(txq); 1658 1659 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 1660 /* Packets are ready, update producer index */ 1661 bcmgenet_tdma_ring_writel(priv, ring->index, 1662 ring->prod_index, TDMA_PROD_INDEX); 1663 out: 1664 spin_unlock(&ring->lock); 1665 1666 return ret; 1667 1668 out_unmap_frags: 1669 /* Back up for failed control block mapping */ 1670 bcmgenet_put_txcb(priv, ring); 1671 1672 /* Unmap successfully mapped control blocks */ 1673 while (i-- > 0) { 1674 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 1675 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 1676 } 1677 1678 dev_kfree_skb(skb); 1679 goto out; 1680 } 1681 1682 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1683 struct enet_cb *cb) 1684 { 1685 struct device *kdev = &priv->pdev->dev; 1686 struct sk_buff *skb; 1687 struct sk_buff *rx_skb; 1688 dma_addr_t mapping; 1689 1690 /* Allocate a new Rx skb */ 1691 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1692 if (!skb) { 1693 priv->mib.alloc_rx_buff_failed++; 1694 netif_err(priv, rx_err, priv->dev, 1695 "%s: Rx skb allocation failed\n", __func__); 1696 return NULL; 1697 } 1698 1699 /* DMA-map the new Rx skb */ 1700 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1701 DMA_FROM_DEVICE); 1702 if (dma_mapping_error(kdev, mapping)) { 1703 priv->mib.rx_dma_failed++; 1704 dev_kfree_skb_any(skb); 1705 netif_err(priv, rx_err, priv->dev, 1706 "%s: Rx skb DMA mapping failed\n", __func__); 1707 return NULL; 1708 } 1709 1710 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1711 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 1712 1713 /* Put the new Rx skb on the ring */ 1714 cb->skb = skb; 1715 dma_unmap_addr_set(cb, dma_addr, mapping); 1716 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 1717 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1718 1719 /* Return the current Rx skb to caller */ 1720 return rx_skb; 1721 } 1722 1723 /* bcmgenet_desc_rx - descriptor based rx process. 1724 * this could be called from bottom half, or from NAPI polling method. 1725 */ 1726 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1727 unsigned int budget) 1728 { 1729 struct bcmgenet_priv *priv = ring->priv; 1730 struct net_device *dev = priv->dev; 1731 struct enet_cb *cb; 1732 struct sk_buff *skb; 1733 u32 dma_length_status; 1734 unsigned long dma_flag; 1735 int len; 1736 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1737 unsigned int bytes_processed = 0; 1738 unsigned int p_index, mask; 1739 unsigned int discards; 1740 1741 /* Clear status before servicing to reduce spurious interrupts */ 1742 if (ring->index == DESC_INDEX) { 1743 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1744 INTRL2_CPU_CLEAR); 1745 } else { 1746 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1747 bcmgenet_intrl2_1_writel(priv, 1748 mask, 1749 INTRL2_CPU_CLEAR); 1750 } 1751 1752 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1753 1754 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1755 DMA_P_INDEX_DISCARD_CNT_MASK; 1756 if (discards > ring->old_discards) { 1757 discards = discards - ring->old_discards; 1758 ring->errors += discards; 1759 ring->old_discards += discards; 1760 1761 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1762 if (ring->old_discards >= 0xC000) { 1763 ring->old_discards = 0; 1764 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1765 RDMA_PROD_INDEX); 1766 } 1767 } 1768 1769 p_index &= DMA_P_INDEX_MASK; 1770 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1771 1772 netif_dbg(priv, rx_status, dev, 1773 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1774 1775 while ((rxpktprocessed < rxpkttoprocess) && 1776 (rxpktprocessed < budget)) { 1777 cb = &priv->rx_cbs[ring->read_ptr]; 1778 skb = bcmgenet_rx_refill(priv, cb); 1779 1780 if (unlikely(!skb)) { 1781 ring->dropped++; 1782 goto next; 1783 } 1784 1785 if (!priv->desc_64b_en) { 1786 dma_length_status = 1787 dmadesc_get_length_status(priv, cb->bd_addr); 1788 } else { 1789 struct status_64 *status; 1790 __be16 rx_csum; 1791 1792 status = (struct status_64 *)skb->data; 1793 dma_length_status = status->length_status; 1794 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 1795 if (priv->desc_rxchk_en) { 1796 skb->csum = (__force __wsum)ntohs(rx_csum); 1797 skb->ip_summed = CHECKSUM_COMPLETE; 1798 } 1799 } 1800 1801 /* DMA flags and length are still valid no matter how 1802 * we got the Receive Status Vector (64B RSB or register) 1803 */ 1804 dma_flag = dma_length_status & 0xffff; 1805 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1806 1807 netif_dbg(priv, rx_status, dev, 1808 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1809 __func__, p_index, ring->c_index, 1810 ring->read_ptr, dma_length_status); 1811 1812 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1813 netif_err(priv, rx_status, dev, 1814 "dropping fragmented packet!\n"); 1815 ring->errors++; 1816 dev_kfree_skb_any(skb); 1817 goto next; 1818 } 1819 1820 /* report errors */ 1821 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1822 DMA_RX_OV | 1823 DMA_RX_NO | 1824 DMA_RX_LG | 1825 DMA_RX_RXER))) { 1826 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1827 (unsigned int)dma_flag); 1828 if (dma_flag & DMA_RX_CRC_ERROR) 1829 dev->stats.rx_crc_errors++; 1830 if (dma_flag & DMA_RX_OV) 1831 dev->stats.rx_over_errors++; 1832 if (dma_flag & DMA_RX_NO) 1833 dev->stats.rx_frame_errors++; 1834 if (dma_flag & DMA_RX_LG) 1835 dev->stats.rx_length_errors++; 1836 dev->stats.rx_errors++; 1837 dev_kfree_skb_any(skb); 1838 goto next; 1839 } /* error packet */ 1840 1841 skb_put(skb, len); 1842 if (priv->desc_64b_en) { 1843 skb_pull(skb, 64); 1844 len -= 64; 1845 } 1846 1847 /* remove hardware 2bytes added for IP alignment */ 1848 skb_pull(skb, 2); 1849 len -= 2; 1850 1851 if (priv->crc_fwd_en) { 1852 skb_trim(skb, len - ETH_FCS_LEN); 1853 len -= ETH_FCS_LEN; 1854 } 1855 1856 bytes_processed += len; 1857 1858 /*Finish setting up the received SKB and send it to the kernel*/ 1859 skb->protocol = eth_type_trans(skb, priv->dev); 1860 ring->packets++; 1861 ring->bytes += len; 1862 if (dma_flag & DMA_RX_MULT) 1863 dev->stats.multicast++; 1864 1865 /* Notify kernel */ 1866 napi_gro_receive(&ring->napi, skb); 1867 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1868 1869 next: 1870 rxpktprocessed++; 1871 if (likely(ring->read_ptr < ring->end_ptr)) 1872 ring->read_ptr++; 1873 else 1874 ring->read_ptr = ring->cb_ptr; 1875 1876 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1877 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1878 } 1879 1880 ring->dim.bytes = bytes_processed; 1881 ring->dim.packets = rxpktprocessed; 1882 1883 return rxpktprocessed; 1884 } 1885 1886 /* Rx NAPI polling method */ 1887 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1888 { 1889 struct bcmgenet_rx_ring *ring = container_of(napi, 1890 struct bcmgenet_rx_ring, napi); 1891 struct dim_sample dim_sample = {}; 1892 unsigned int work_done; 1893 1894 work_done = bcmgenet_desc_rx(ring, budget); 1895 1896 if (work_done < budget) { 1897 napi_complete_done(napi, work_done); 1898 ring->int_enable(ring); 1899 } 1900 1901 if (ring->dim.use_dim) { 1902 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 1903 ring->dim.bytes, &dim_sample); 1904 net_dim(&ring->dim.dim, dim_sample); 1905 } 1906 1907 return work_done; 1908 } 1909 1910 static void bcmgenet_dim_work(struct work_struct *work) 1911 { 1912 struct dim *dim = container_of(work, struct dim, work); 1913 struct bcmgenet_net_dim *ndim = 1914 container_of(dim, struct bcmgenet_net_dim, dim); 1915 struct bcmgenet_rx_ring *ring = 1916 container_of(ndim, struct bcmgenet_rx_ring, dim); 1917 struct dim_cq_moder cur_profile = 1918 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1919 1920 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 1921 dim->state = DIM_START_MEASURE; 1922 } 1923 1924 /* Assign skb to RX DMA descriptor. */ 1925 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1926 struct bcmgenet_rx_ring *ring) 1927 { 1928 struct enet_cb *cb; 1929 struct sk_buff *skb; 1930 int i; 1931 1932 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1933 1934 /* loop here for each buffer needing assign */ 1935 for (i = 0; i < ring->size; i++) { 1936 cb = ring->cbs + i; 1937 skb = bcmgenet_rx_refill(priv, cb); 1938 if (skb) 1939 dev_consume_skb_any(skb); 1940 if (!cb->skb) 1941 return -ENOMEM; 1942 } 1943 1944 return 0; 1945 } 1946 1947 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1948 { 1949 struct sk_buff *skb; 1950 struct enet_cb *cb; 1951 int i; 1952 1953 for (i = 0; i < priv->num_rx_bds; i++) { 1954 cb = &priv->rx_cbs[i]; 1955 1956 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 1957 if (skb) 1958 dev_consume_skb_any(skb); 1959 } 1960 } 1961 1962 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1963 { 1964 u32 reg; 1965 1966 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1967 if (enable) 1968 reg |= mask; 1969 else 1970 reg &= ~mask; 1971 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1972 1973 /* UniMAC stops on a packet boundary, wait for a full-size packet 1974 * to be processed 1975 */ 1976 if (enable == 0) 1977 usleep_range(1000, 2000); 1978 } 1979 1980 static void reset_umac(struct bcmgenet_priv *priv) 1981 { 1982 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1983 bcmgenet_rbuf_ctrl_set(priv, 0); 1984 udelay(10); 1985 1986 /* disable MAC while updating its registers */ 1987 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1988 1989 /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */ 1990 bcmgenet_umac_writel(priv, CMD_SW_RESET | CMD_LCL_LOOP_EN, UMAC_CMD); 1991 } 1992 1993 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1994 { 1995 /* Mask all interrupts.*/ 1996 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1997 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1998 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1999 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2000 } 2001 2002 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2003 { 2004 u32 int0_enable = 0; 2005 2006 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2007 * and MoCA PHY 2008 */ 2009 if (priv->internal_phy) { 2010 int0_enable |= UMAC_IRQ_LINK_EVENT; 2011 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2012 int0_enable |= UMAC_IRQ_PHY_DET_R; 2013 } else if (priv->ext_phy) { 2014 int0_enable |= UMAC_IRQ_LINK_EVENT; 2015 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2016 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2017 int0_enable |= UMAC_IRQ_LINK_EVENT; 2018 } 2019 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2020 } 2021 2022 static void init_umac(struct bcmgenet_priv *priv) 2023 { 2024 struct device *kdev = &priv->pdev->dev; 2025 u32 reg; 2026 u32 int0_enable = 0; 2027 2028 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2029 2030 reset_umac(priv); 2031 2032 /* clear tx/rx counter */ 2033 bcmgenet_umac_writel(priv, 2034 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2035 UMAC_MIB_CTRL); 2036 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2037 2038 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2039 2040 /* init rx registers, enable ip header optimization */ 2041 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2042 reg |= RBUF_ALIGN_2B; 2043 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2044 2045 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2046 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2047 2048 bcmgenet_intr_disable(priv); 2049 2050 /* Configure backpressure vectors for MoCA */ 2051 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2052 reg = bcmgenet_bp_mc_get(priv); 2053 reg |= BIT(priv->hw_params->bp_in_en_shift); 2054 2055 /* bp_mask: back pressure mask */ 2056 if (netif_is_multiqueue(priv->dev)) 2057 reg |= priv->hw_params->bp_in_mask; 2058 else 2059 reg &= ~priv->hw_params->bp_in_mask; 2060 bcmgenet_bp_mc_set(priv, reg); 2061 } 2062 2063 /* Enable MDIO interrupts on GENET v3+ */ 2064 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2065 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2066 2067 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2068 2069 dev_dbg(kdev, "done init umac\n"); 2070 } 2071 2072 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2073 void (*cb)(struct work_struct *work)) 2074 { 2075 struct bcmgenet_net_dim *dim = &ring->dim; 2076 2077 INIT_WORK(&dim->dim.work, cb); 2078 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2079 dim->event_ctr = 0; 2080 dim->packets = 0; 2081 dim->bytes = 0; 2082 } 2083 2084 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2085 { 2086 struct bcmgenet_net_dim *dim = &ring->dim; 2087 struct dim_cq_moder moder; 2088 u32 usecs, pkts; 2089 2090 usecs = ring->rx_coalesce_usecs; 2091 pkts = ring->rx_max_coalesced_frames; 2092 2093 /* If DIM was enabled, re-apply default parameters */ 2094 if (dim->use_dim) { 2095 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2096 usecs = moder.usec; 2097 pkts = moder.pkts; 2098 } 2099 2100 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2101 } 2102 2103 /* Initialize a Tx ring along with corresponding hardware registers */ 2104 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2105 unsigned int index, unsigned int size, 2106 unsigned int start_ptr, unsigned int end_ptr) 2107 { 2108 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2109 u32 words_per_bd = WORDS_PER_BD(priv); 2110 u32 flow_period_val = 0; 2111 2112 spin_lock_init(&ring->lock); 2113 ring->priv = priv; 2114 ring->index = index; 2115 if (index == DESC_INDEX) { 2116 ring->queue = 0; 2117 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2118 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2119 } else { 2120 ring->queue = index + 1; 2121 ring->int_enable = bcmgenet_tx_ring_int_enable; 2122 ring->int_disable = bcmgenet_tx_ring_int_disable; 2123 } 2124 ring->cbs = priv->tx_cbs + start_ptr; 2125 ring->size = size; 2126 ring->clean_ptr = start_ptr; 2127 ring->c_index = 0; 2128 ring->free_bds = size; 2129 ring->write_ptr = start_ptr; 2130 ring->cb_ptr = start_ptr; 2131 ring->end_ptr = end_ptr - 1; 2132 ring->prod_index = 0; 2133 2134 /* Set flow period for ring != 16 */ 2135 if (index != DESC_INDEX) 2136 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2137 2138 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2139 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2140 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2141 /* Disable rate control for now */ 2142 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2143 TDMA_FLOW_PERIOD); 2144 bcmgenet_tdma_ring_writel(priv, index, 2145 ((size << DMA_RING_SIZE_SHIFT) | 2146 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2147 2148 /* Set start and end address, read and write pointers */ 2149 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2150 DMA_START_ADDR); 2151 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2152 TDMA_READ_PTR); 2153 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2154 TDMA_WRITE_PTR); 2155 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2156 DMA_END_ADDR); 2157 2158 /* Initialize Tx NAPI */ 2159 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2160 NAPI_POLL_WEIGHT); 2161 } 2162 2163 /* Initialize a RDMA ring */ 2164 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2165 unsigned int index, unsigned int size, 2166 unsigned int start_ptr, unsigned int end_ptr) 2167 { 2168 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2169 u32 words_per_bd = WORDS_PER_BD(priv); 2170 int ret; 2171 2172 ring->priv = priv; 2173 ring->index = index; 2174 if (index == DESC_INDEX) { 2175 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2176 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2177 } else { 2178 ring->int_enable = bcmgenet_rx_ring_int_enable; 2179 ring->int_disable = bcmgenet_rx_ring_int_disable; 2180 } 2181 ring->cbs = priv->rx_cbs + start_ptr; 2182 ring->size = size; 2183 ring->c_index = 0; 2184 ring->read_ptr = start_ptr; 2185 ring->cb_ptr = start_ptr; 2186 ring->end_ptr = end_ptr - 1; 2187 2188 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2189 if (ret) 2190 return ret; 2191 2192 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2193 bcmgenet_init_rx_coalesce(ring); 2194 2195 /* Initialize Rx NAPI */ 2196 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2197 NAPI_POLL_WEIGHT); 2198 2199 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2200 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2201 bcmgenet_rdma_ring_writel(priv, index, 2202 ((size << DMA_RING_SIZE_SHIFT) | 2203 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2204 bcmgenet_rdma_ring_writel(priv, index, 2205 (DMA_FC_THRESH_LO << 2206 DMA_XOFF_THRESHOLD_SHIFT) | 2207 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2208 2209 /* Set start and end address, read and write pointers */ 2210 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2211 DMA_START_ADDR); 2212 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2213 RDMA_READ_PTR); 2214 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2215 RDMA_WRITE_PTR); 2216 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2217 DMA_END_ADDR); 2218 2219 return ret; 2220 } 2221 2222 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2223 { 2224 unsigned int i; 2225 struct bcmgenet_tx_ring *ring; 2226 2227 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2228 ring = &priv->tx_rings[i]; 2229 napi_enable(&ring->napi); 2230 ring->int_enable(ring); 2231 } 2232 2233 ring = &priv->tx_rings[DESC_INDEX]; 2234 napi_enable(&ring->napi); 2235 ring->int_enable(ring); 2236 } 2237 2238 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2239 { 2240 unsigned int i; 2241 struct bcmgenet_tx_ring *ring; 2242 2243 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2244 ring = &priv->tx_rings[i]; 2245 napi_disable(&ring->napi); 2246 } 2247 2248 ring = &priv->tx_rings[DESC_INDEX]; 2249 napi_disable(&ring->napi); 2250 } 2251 2252 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2253 { 2254 unsigned int i; 2255 struct bcmgenet_tx_ring *ring; 2256 2257 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2258 ring = &priv->tx_rings[i]; 2259 netif_napi_del(&ring->napi); 2260 } 2261 2262 ring = &priv->tx_rings[DESC_INDEX]; 2263 netif_napi_del(&ring->napi); 2264 } 2265 2266 /* Initialize Tx queues 2267 * 2268 * Queues 0-3 are priority-based, each one has 32 descriptors, 2269 * with queue 0 being the highest priority queue. 2270 * 2271 * Queue 16 is the default Tx queue with 2272 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2273 * 2274 * The transmit control block pool is then partitioned as follows: 2275 * - Tx queue 0 uses tx_cbs[0..31] 2276 * - Tx queue 1 uses tx_cbs[32..63] 2277 * - Tx queue 2 uses tx_cbs[64..95] 2278 * - Tx queue 3 uses tx_cbs[96..127] 2279 * - Tx queue 16 uses tx_cbs[128..255] 2280 */ 2281 static void bcmgenet_init_tx_queues(struct net_device *dev) 2282 { 2283 struct bcmgenet_priv *priv = netdev_priv(dev); 2284 u32 i, dma_enable; 2285 u32 dma_ctrl, ring_cfg; 2286 u32 dma_priority[3] = {0, 0, 0}; 2287 2288 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2289 dma_enable = dma_ctrl & DMA_EN; 2290 dma_ctrl &= ~DMA_EN; 2291 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2292 2293 dma_ctrl = 0; 2294 ring_cfg = 0; 2295 2296 /* Enable strict priority arbiter mode */ 2297 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2298 2299 /* Initialize Tx priority queues */ 2300 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2301 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2302 i * priv->hw_params->tx_bds_per_q, 2303 (i + 1) * priv->hw_params->tx_bds_per_q); 2304 ring_cfg |= (1 << i); 2305 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2306 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2307 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2308 } 2309 2310 /* Initialize Tx default queue 16 */ 2311 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2312 priv->hw_params->tx_queues * 2313 priv->hw_params->tx_bds_per_q, 2314 TOTAL_DESC); 2315 ring_cfg |= (1 << DESC_INDEX); 2316 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2317 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2318 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2319 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2320 2321 /* Set Tx queue priorities */ 2322 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2323 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2324 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2325 2326 /* Enable Tx queues */ 2327 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2328 2329 /* Enable Tx DMA */ 2330 if (dma_enable) 2331 dma_ctrl |= DMA_EN; 2332 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2333 } 2334 2335 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2336 { 2337 unsigned int i; 2338 struct bcmgenet_rx_ring *ring; 2339 2340 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2341 ring = &priv->rx_rings[i]; 2342 napi_enable(&ring->napi); 2343 ring->int_enable(ring); 2344 } 2345 2346 ring = &priv->rx_rings[DESC_INDEX]; 2347 napi_enable(&ring->napi); 2348 ring->int_enable(ring); 2349 } 2350 2351 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2352 { 2353 unsigned int i; 2354 struct bcmgenet_rx_ring *ring; 2355 2356 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2357 ring = &priv->rx_rings[i]; 2358 napi_disable(&ring->napi); 2359 cancel_work_sync(&ring->dim.dim.work); 2360 } 2361 2362 ring = &priv->rx_rings[DESC_INDEX]; 2363 napi_disable(&ring->napi); 2364 cancel_work_sync(&ring->dim.dim.work); 2365 } 2366 2367 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2368 { 2369 unsigned int i; 2370 struct bcmgenet_rx_ring *ring; 2371 2372 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2373 ring = &priv->rx_rings[i]; 2374 netif_napi_del(&ring->napi); 2375 } 2376 2377 ring = &priv->rx_rings[DESC_INDEX]; 2378 netif_napi_del(&ring->napi); 2379 } 2380 2381 /* Initialize Rx queues 2382 * 2383 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2384 * used to direct traffic to these queues. 2385 * 2386 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2387 */ 2388 static int bcmgenet_init_rx_queues(struct net_device *dev) 2389 { 2390 struct bcmgenet_priv *priv = netdev_priv(dev); 2391 u32 i; 2392 u32 dma_enable; 2393 u32 dma_ctrl; 2394 u32 ring_cfg; 2395 int ret; 2396 2397 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2398 dma_enable = dma_ctrl & DMA_EN; 2399 dma_ctrl &= ~DMA_EN; 2400 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2401 2402 dma_ctrl = 0; 2403 ring_cfg = 0; 2404 2405 /* Initialize Rx priority queues */ 2406 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2407 ret = bcmgenet_init_rx_ring(priv, i, 2408 priv->hw_params->rx_bds_per_q, 2409 i * priv->hw_params->rx_bds_per_q, 2410 (i + 1) * 2411 priv->hw_params->rx_bds_per_q); 2412 if (ret) 2413 return ret; 2414 2415 ring_cfg |= (1 << i); 2416 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2417 } 2418 2419 /* Initialize Rx default queue 16 */ 2420 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2421 priv->hw_params->rx_queues * 2422 priv->hw_params->rx_bds_per_q, 2423 TOTAL_DESC); 2424 if (ret) 2425 return ret; 2426 2427 ring_cfg |= (1 << DESC_INDEX); 2428 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2429 2430 /* Enable rings */ 2431 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2432 2433 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2434 if (dma_enable) 2435 dma_ctrl |= DMA_EN; 2436 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2437 2438 return 0; 2439 } 2440 2441 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2442 { 2443 int ret = 0; 2444 int timeout = 0; 2445 u32 reg; 2446 u32 dma_ctrl; 2447 int i; 2448 2449 /* Disable TDMA to stop add more frames in TX DMA */ 2450 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2451 reg &= ~DMA_EN; 2452 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2453 2454 /* Check TDMA status register to confirm TDMA is disabled */ 2455 while (timeout++ < DMA_TIMEOUT_VAL) { 2456 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2457 if (reg & DMA_DISABLED) 2458 break; 2459 2460 udelay(1); 2461 } 2462 2463 if (timeout == DMA_TIMEOUT_VAL) { 2464 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2465 ret = -ETIMEDOUT; 2466 } 2467 2468 /* Wait 10ms for packet drain in both tx and rx dma */ 2469 usleep_range(10000, 20000); 2470 2471 /* Disable RDMA */ 2472 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2473 reg &= ~DMA_EN; 2474 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2475 2476 timeout = 0; 2477 /* Check RDMA status register to confirm RDMA is disabled */ 2478 while (timeout++ < DMA_TIMEOUT_VAL) { 2479 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2480 if (reg & DMA_DISABLED) 2481 break; 2482 2483 udelay(1); 2484 } 2485 2486 if (timeout == DMA_TIMEOUT_VAL) { 2487 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2488 ret = -ETIMEDOUT; 2489 } 2490 2491 dma_ctrl = 0; 2492 for (i = 0; i < priv->hw_params->rx_queues; i++) 2493 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2494 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2495 reg &= ~dma_ctrl; 2496 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2497 2498 dma_ctrl = 0; 2499 for (i = 0; i < priv->hw_params->tx_queues; i++) 2500 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2501 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2502 reg &= ~dma_ctrl; 2503 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2504 2505 return ret; 2506 } 2507 2508 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2509 { 2510 struct netdev_queue *txq; 2511 int i; 2512 2513 bcmgenet_fini_rx_napi(priv); 2514 bcmgenet_fini_tx_napi(priv); 2515 2516 for (i = 0; i < priv->num_tx_bds; i++) 2517 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2518 priv->tx_cbs + i)); 2519 2520 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2521 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2522 netdev_tx_reset_queue(txq); 2523 } 2524 2525 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2526 netdev_tx_reset_queue(txq); 2527 2528 bcmgenet_free_rx_buffers(priv); 2529 kfree(priv->rx_cbs); 2530 kfree(priv->tx_cbs); 2531 } 2532 2533 /* init_edma: Initialize DMA control register */ 2534 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2535 { 2536 int ret; 2537 unsigned int i; 2538 struct enet_cb *cb; 2539 2540 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2541 2542 /* Initialize common Rx ring structures */ 2543 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2544 priv->num_rx_bds = TOTAL_DESC; 2545 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2546 GFP_KERNEL); 2547 if (!priv->rx_cbs) 2548 return -ENOMEM; 2549 2550 for (i = 0; i < priv->num_rx_bds; i++) { 2551 cb = priv->rx_cbs + i; 2552 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2553 } 2554 2555 /* Initialize common TX ring structures */ 2556 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2557 priv->num_tx_bds = TOTAL_DESC; 2558 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2559 GFP_KERNEL); 2560 if (!priv->tx_cbs) { 2561 kfree(priv->rx_cbs); 2562 return -ENOMEM; 2563 } 2564 2565 for (i = 0; i < priv->num_tx_bds; i++) { 2566 cb = priv->tx_cbs + i; 2567 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2568 } 2569 2570 /* Init rDma */ 2571 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 2572 DMA_SCB_BURST_SIZE); 2573 2574 /* Initialize Rx queues */ 2575 ret = bcmgenet_init_rx_queues(priv->dev); 2576 if (ret) { 2577 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2578 bcmgenet_free_rx_buffers(priv); 2579 kfree(priv->rx_cbs); 2580 kfree(priv->tx_cbs); 2581 return ret; 2582 } 2583 2584 /* Init tDma */ 2585 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 2586 DMA_SCB_BURST_SIZE); 2587 2588 /* Initialize Tx queues */ 2589 bcmgenet_init_tx_queues(priv->dev); 2590 2591 return 0; 2592 } 2593 2594 /* Interrupt bottom half */ 2595 static void bcmgenet_irq_task(struct work_struct *work) 2596 { 2597 unsigned int status; 2598 struct bcmgenet_priv *priv = container_of( 2599 work, struct bcmgenet_priv, bcmgenet_irq_work); 2600 2601 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2602 2603 spin_lock_irq(&priv->lock); 2604 status = priv->irq0_stat; 2605 priv->irq0_stat = 0; 2606 spin_unlock_irq(&priv->lock); 2607 2608 if (status & UMAC_IRQ_PHY_DET_R && 2609 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 2610 phy_init_hw(priv->dev->phydev); 2611 genphy_config_aneg(priv->dev->phydev); 2612 } 2613 2614 /* Link UP/DOWN event */ 2615 if (status & UMAC_IRQ_LINK_EVENT) 2616 phy_mac_interrupt(priv->dev->phydev); 2617 2618 } 2619 2620 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2621 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2622 { 2623 struct bcmgenet_priv *priv = dev_id; 2624 struct bcmgenet_rx_ring *rx_ring; 2625 struct bcmgenet_tx_ring *tx_ring; 2626 unsigned int index, status; 2627 2628 /* Read irq status */ 2629 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2630 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2631 2632 /* clear interrupts */ 2633 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2634 2635 netif_dbg(priv, intr, priv->dev, 2636 "%s: IRQ=0x%x\n", __func__, status); 2637 2638 /* Check Rx priority queue interrupts */ 2639 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2640 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2641 continue; 2642 2643 rx_ring = &priv->rx_rings[index]; 2644 rx_ring->dim.event_ctr++; 2645 2646 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2647 rx_ring->int_disable(rx_ring); 2648 __napi_schedule_irqoff(&rx_ring->napi); 2649 } 2650 } 2651 2652 /* Check Tx priority queue interrupts */ 2653 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2654 if (!(status & BIT(index))) 2655 continue; 2656 2657 tx_ring = &priv->tx_rings[index]; 2658 2659 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2660 tx_ring->int_disable(tx_ring); 2661 __napi_schedule_irqoff(&tx_ring->napi); 2662 } 2663 } 2664 2665 return IRQ_HANDLED; 2666 } 2667 2668 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2669 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2670 { 2671 struct bcmgenet_priv *priv = dev_id; 2672 struct bcmgenet_rx_ring *rx_ring; 2673 struct bcmgenet_tx_ring *tx_ring; 2674 unsigned int status; 2675 unsigned long flags; 2676 2677 /* Read irq status */ 2678 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2679 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2680 2681 /* clear interrupts */ 2682 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2683 2684 netif_dbg(priv, intr, priv->dev, 2685 "IRQ=0x%x\n", status); 2686 2687 if (status & UMAC_IRQ_RXDMA_DONE) { 2688 rx_ring = &priv->rx_rings[DESC_INDEX]; 2689 rx_ring->dim.event_ctr++; 2690 2691 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2692 rx_ring->int_disable(rx_ring); 2693 __napi_schedule_irqoff(&rx_ring->napi); 2694 } 2695 } 2696 2697 if (status & UMAC_IRQ_TXDMA_DONE) { 2698 tx_ring = &priv->tx_rings[DESC_INDEX]; 2699 2700 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2701 tx_ring->int_disable(tx_ring); 2702 __napi_schedule_irqoff(&tx_ring->napi); 2703 } 2704 } 2705 2706 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2707 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2708 wake_up(&priv->wq); 2709 } 2710 2711 /* all other interested interrupts handled in bottom half */ 2712 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 2713 if (status) { 2714 /* Save irq status for bottom-half processing. */ 2715 spin_lock_irqsave(&priv->lock, flags); 2716 priv->irq0_stat |= status; 2717 spin_unlock_irqrestore(&priv->lock, flags); 2718 2719 schedule_work(&priv->bcmgenet_irq_work); 2720 } 2721 2722 return IRQ_HANDLED; 2723 } 2724 2725 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2726 { 2727 struct bcmgenet_priv *priv = dev_id; 2728 2729 pm_wakeup_event(&priv->pdev->dev, 0); 2730 2731 return IRQ_HANDLED; 2732 } 2733 2734 #ifdef CONFIG_NET_POLL_CONTROLLER 2735 static void bcmgenet_poll_controller(struct net_device *dev) 2736 { 2737 struct bcmgenet_priv *priv = netdev_priv(dev); 2738 2739 /* Invoke the main RX/TX interrupt handler */ 2740 disable_irq(priv->irq0); 2741 bcmgenet_isr0(priv->irq0, priv); 2742 enable_irq(priv->irq0); 2743 2744 /* And the interrupt handler for RX/TX priority queues */ 2745 disable_irq(priv->irq1); 2746 bcmgenet_isr1(priv->irq1, priv); 2747 enable_irq(priv->irq1); 2748 } 2749 #endif 2750 2751 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2752 { 2753 u32 reg; 2754 2755 reg = bcmgenet_rbuf_ctrl_get(priv); 2756 reg |= BIT(1); 2757 bcmgenet_rbuf_ctrl_set(priv, reg); 2758 udelay(10); 2759 2760 reg &= ~BIT(1); 2761 bcmgenet_rbuf_ctrl_set(priv, reg); 2762 udelay(10); 2763 } 2764 2765 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2766 unsigned char *addr) 2767 { 2768 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2769 (addr[2] << 8) | addr[3], UMAC_MAC0); 2770 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2771 } 2772 2773 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 2774 unsigned char *addr) 2775 { 2776 u32 addr_tmp; 2777 2778 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 2779 addr[0] = addr_tmp >> 24; 2780 addr[1] = (addr_tmp >> 16) & 0xff; 2781 addr[2] = (addr_tmp >> 8) & 0xff; 2782 addr[3] = addr_tmp & 0xff; 2783 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 2784 addr[4] = (addr_tmp >> 8) & 0xff; 2785 addr[5] = addr_tmp & 0xff; 2786 } 2787 2788 /* Returns a reusable dma control register value */ 2789 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2790 { 2791 u32 reg; 2792 u32 dma_ctrl; 2793 2794 /* disable DMA */ 2795 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2796 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2797 reg &= ~dma_ctrl; 2798 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2799 2800 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2801 reg &= ~dma_ctrl; 2802 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2803 2804 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2805 udelay(10); 2806 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2807 2808 return dma_ctrl; 2809 } 2810 2811 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2812 { 2813 u32 reg; 2814 2815 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2816 reg |= dma_ctrl; 2817 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2818 2819 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2820 reg |= dma_ctrl; 2821 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2822 } 2823 2824 /* bcmgenet_hfb_clear 2825 * 2826 * Clear Hardware Filter Block and disable all filtering. 2827 */ 2828 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2829 { 2830 u32 i; 2831 2832 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2833 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2834 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2835 2836 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2837 bcmgenet_rdma_writel(priv, 0x0, i); 2838 2839 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2840 bcmgenet_hfb_reg_writel(priv, 0x0, 2841 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2842 2843 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2844 priv->hw_params->hfb_filter_size; i++) 2845 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2846 } 2847 2848 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2849 { 2850 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2851 return; 2852 2853 bcmgenet_hfb_clear(priv); 2854 } 2855 2856 static void bcmgenet_netif_start(struct net_device *dev) 2857 { 2858 struct bcmgenet_priv *priv = netdev_priv(dev); 2859 2860 /* Start the network engine */ 2861 bcmgenet_enable_rx_napi(priv); 2862 2863 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2864 2865 bcmgenet_enable_tx_napi(priv); 2866 2867 /* Monitor link interrupts now */ 2868 bcmgenet_link_intr_enable(priv); 2869 2870 phy_start(dev->phydev); 2871 } 2872 2873 static int bcmgenet_open(struct net_device *dev) 2874 { 2875 struct bcmgenet_priv *priv = netdev_priv(dev); 2876 unsigned long dma_ctrl; 2877 u32 reg; 2878 int ret; 2879 2880 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2881 2882 /* Turn on the clock */ 2883 clk_prepare_enable(priv->clk); 2884 2885 /* If this is an internal GPHY, power it back on now, before UniMAC is 2886 * brought out of reset as absolutely no UniMAC activity is allowed 2887 */ 2888 if (priv->internal_phy) 2889 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2890 2891 /* take MAC out of reset */ 2892 bcmgenet_umac_reset(priv); 2893 2894 init_umac(priv); 2895 2896 /* Apply features again in case we changed them while interface was 2897 * down 2898 */ 2899 bcmgenet_set_features(dev, dev->features); 2900 2901 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2902 2903 if (priv->internal_phy) { 2904 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2905 reg |= EXT_ENERGY_DET_MASK; 2906 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2907 } 2908 2909 /* Disable RX/TX DMA and flush TX queues */ 2910 dma_ctrl = bcmgenet_dma_disable(priv); 2911 2912 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2913 ret = bcmgenet_init_dma(priv); 2914 if (ret) { 2915 netdev_err(dev, "failed to initialize DMA\n"); 2916 goto err_clk_disable; 2917 } 2918 2919 /* Always enable ring 16 - descriptor ring */ 2920 bcmgenet_enable_dma(priv, dma_ctrl); 2921 2922 /* HFB init */ 2923 bcmgenet_hfb_init(priv); 2924 2925 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2926 dev->name, priv); 2927 if (ret < 0) { 2928 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2929 goto err_fini_dma; 2930 } 2931 2932 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2933 dev->name, priv); 2934 if (ret < 0) { 2935 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2936 goto err_irq0; 2937 } 2938 2939 ret = bcmgenet_mii_probe(dev); 2940 if (ret) { 2941 netdev_err(dev, "failed to connect to PHY\n"); 2942 goto err_irq1; 2943 } 2944 2945 bcmgenet_netif_start(dev); 2946 2947 netif_tx_start_all_queues(dev); 2948 2949 return 0; 2950 2951 err_irq1: 2952 free_irq(priv->irq1, priv); 2953 err_irq0: 2954 free_irq(priv->irq0, priv); 2955 err_fini_dma: 2956 bcmgenet_dma_teardown(priv); 2957 bcmgenet_fini_dma(priv); 2958 err_clk_disable: 2959 if (priv->internal_phy) 2960 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2961 clk_disable_unprepare(priv->clk); 2962 return ret; 2963 } 2964 2965 static void bcmgenet_netif_stop(struct net_device *dev) 2966 { 2967 struct bcmgenet_priv *priv = netdev_priv(dev); 2968 2969 bcmgenet_disable_tx_napi(priv); 2970 netif_tx_disable(dev); 2971 2972 /* Disable MAC receive */ 2973 umac_enable_set(priv, CMD_RX_EN, false); 2974 2975 bcmgenet_dma_teardown(priv); 2976 2977 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2978 umac_enable_set(priv, CMD_TX_EN, false); 2979 2980 phy_stop(dev->phydev); 2981 bcmgenet_disable_rx_napi(priv); 2982 bcmgenet_intr_disable(priv); 2983 2984 /* Wait for pending work items to complete. Since interrupts are 2985 * disabled no new work will be scheduled. 2986 */ 2987 cancel_work_sync(&priv->bcmgenet_irq_work); 2988 2989 priv->old_link = -1; 2990 priv->old_speed = -1; 2991 priv->old_duplex = -1; 2992 priv->old_pause = -1; 2993 2994 /* tx reclaim */ 2995 bcmgenet_tx_reclaim_all(dev); 2996 bcmgenet_fini_dma(priv); 2997 } 2998 2999 static int bcmgenet_close(struct net_device *dev) 3000 { 3001 struct bcmgenet_priv *priv = netdev_priv(dev); 3002 int ret = 0; 3003 3004 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3005 3006 bcmgenet_netif_stop(dev); 3007 3008 /* Really kill the PHY state machine and disconnect from it */ 3009 phy_disconnect(dev->phydev); 3010 3011 free_irq(priv->irq0, priv); 3012 free_irq(priv->irq1, priv); 3013 3014 if (priv->internal_phy) 3015 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3016 3017 clk_disable_unprepare(priv->clk); 3018 3019 return ret; 3020 } 3021 3022 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3023 { 3024 struct bcmgenet_priv *priv = ring->priv; 3025 u32 p_index, c_index, intsts, intmsk; 3026 struct netdev_queue *txq; 3027 unsigned int free_bds; 3028 bool txq_stopped; 3029 3030 if (!netif_msg_tx_err(priv)) 3031 return; 3032 3033 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3034 3035 spin_lock(&ring->lock); 3036 if (ring->index == DESC_INDEX) { 3037 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3038 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3039 } else { 3040 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3041 intmsk = 1 << ring->index; 3042 } 3043 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3044 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3045 txq_stopped = netif_tx_queue_stopped(txq); 3046 free_bds = ring->free_bds; 3047 spin_unlock(&ring->lock); 3048 3049 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3050 "TX queue status: %s, interrupts: %s\n" 3051 "(sw)free_bds: %d (sw)size: %d\n" 3052 "(sw)p_index: %d (hw)p_index: %d\n" 3053 "(sw)c_index: %d (hw)c_index: %d\n" 3054 "(sw)clean_p: %d (sw)write_p: %d\n" 3055 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3056 ring->index, ring->queue, 3057 txq_stopped ? "stopped" : "active", 3058 intsts & intmsk ? "enabled" : "disabled", 3059 free_bds, ring->size, 3060 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3061 ring->c_index, c_index & DMA_C_INDEX_MASK, 3062 ring->clean_ptr, ring->write_ptr, 3063 ring->cb_ptr, ring->end_ptr); 3064 } 3065 3066 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3067 { 3068 struct bcmgenet_priv *priv = netdev_priv(dev); 3069 u32 int0_enable = 0; 3070 u32 int1_enable = 0; 3071 unsigned int q; 3072 3073 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3074 3075 for (q = 0; q < priv->hw_params->tx_queues; q++) 3076 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3077 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3078 3079 bcmgenet_tx_reclaim_all(dev); 3080 3081 for (q = 0; q < priv->hw_params->tx_queues; q++) 3082 int1_enable |= (1 << q); 3083 3084 int0_enable = UMAC_IRQ_TXDMA_DONE; 3085 3086 /* Re-enable TX interrupts if disabled */ 3087 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3088 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3089 3090 netif_trans_update(dev); 3091 3092 dev->stats.tx_errors++; 3093 3094 netif_tx_wake_all_queues(dev); 3095 } 3096 3097 #define MAX_MDF_FILTER 17 3098 3099 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3100 unsigned char *addr, 3101 int *i) 3102 { 3103 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3104 UMAC_MDF_ADDR + (*i * 4)); 3105 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3106 addr[4] << 8 | addr[5], 3107 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3108 *i += 2; 3109 } 3110 3111 static void bcmgenet_set_rx_mode(struct net_device *dev) 3112 { 3113 struct bcmgenet_priv *priv = netdev_priv(dev); 3114 struct netdev_hw_addr *ha; 3115 int i, nfilter; 3116 u32 reg; 3117 3118 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3119 3120 /* Number of filters needed */ 3121 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3122 3123 /* 3124 * Turn on promicuous mode for three scenarios 3125 * 1. IFF_PROMISC flag is set 3126 * 2. IFF_ALLMULTI flag is set 3127 * 3. The number of filters needed exceeds the number filters 3128 * supported by the hardware. 3129 */ 3130 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3131 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3132 (nfilter > MAX_MDF_FILTER)) { 3133 reg |= CMD_PROMISC; 3134 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3135 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3136 return; 3137 } else { 3138 reg &= ~CMD_PROMISC; 3139 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3140 } 3141 3142 /* update MDF filter */ 3143 i = 0; 3144 /* Broadcast */ 3145 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3146 /* my own address.*/ 3147 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3148 3149 /* Unicast */ 3150 netdev_for_each_uc_addr(ha, dev) 3151 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3152 3153 /* Multicast */ 3154 netdev_for_each_mc_addr(ha, dev) 3155 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3156 3157 /* Enable filters */ 3158 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3159 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3160 } 3161 3162 /* Set the hardware MAC address. */ 3163 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3164 { 3165 struct sockaddr *addr = p; 3166 3167 /* Setting the MAC address at the hardware level is not possible 3168 * without disabling the UniMAC RX/TX enable bits. 3169 */ 3170 if (netif_running(dev)) 3171 return -EBUSY; 3172 3173 ether_addr_copy(dev->dev_addr, addr->sa_data); 3174 3175 return 0; 3176 } 3177 3178 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3179 { 3180 struct bcmgenet_priv *priv = netdev_priv(dev); 3181 unsigned long tx_bytes = 0, tx_packets = 0; 3182 unsigned long rx_bytes = 0, rx_packets = 0; 3183 unsigned long rx_errors = 0, rx_dropped = 0; 3184 struct bcmgenet_tx_ring *tx_ring; 3185 struct bcmgenet_rx_ring *rx_ring; 3186 unsigned int q; 3187 3188 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3189 tx_ring = &priv->tx_rings[q]; 3190 tx_bytes += tx_ring->bytes; 3191 tx_packets += tx_ring->packets; 3192 } 3193 tx_ring = &priv->tx_rings[DESC_INDEX]; 3194 tx_bytes += tx_ring->bytes; 3195 tx_packets += tx_ring->packets; 3196 3197 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3198 rx_ring = &priv->rx_rings[q]; 3199 3200 rx_bytes += rx_ring->bytes; 3201 rx_packets += rx_ring->packets; 3202 rx_errors += rx_ring->errors; 3203 rx_dropped += rx_ring->dropped; 3204 } 3205 rx_ring = &priv->rx_rings[DESC_INDEX]; 3206 rx_bytes += rx_ring->bytes; 3207 rx_packets += rx_ring->packets; 3208 rx_errors += rx_ring->errors; 3209 rx_dropped += rx_ring->dropped; 3210 3211 dev->stats.tx_bytes = tx_bytes; 3212 dev->stats.tx_packets = tx_packets; 3213 dev->stats.rx_bytes = rx_bytes; 3214 dev->stats.rx_packets = rx_packets; 3215 dev->stats.rx_errors = rx_errors; 3216 dev->stats.rx_missed_errors = rx_errors; 3217 return &dev->stats; 3218 } 3219 3220 static const struct net_device_ops bcmgenet_netdev_ops = { 3221 .ndo_open = bcmgenet_open, 3222 .ndo_stop = bcmgenet_close, 3223 .ndo_start_xmit = bcmgenet_xmit, 3224 .ndo_tx_timeout = bcmgenet_timeout, 3225 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3226 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3227 .ndo_do_ioctl = phy_do_ioctl_running, 3228 .ndo_set_features = bcmgenet_set_features, 3229 #ifdef CONFIG_NET_POLL_CONTROLLER 3230 .ndo_poll_controller = bcmgenet_poll_controller, 3231 #endif 3232 .ndo_get_stats = bcmgenet_get_stats, 3233 }; 3234 3235 /* Array of GENET hardware parameters/characteristics */ 3236 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3237 [GENET_V1] = { 3238 .tx_queues = 0, 3239 .tx_bds_per_q = 0, 3240 .rx_queues = 0, 3241 .rx_bds_per_q = 0, 3242 .bp_in_en_shift = 16, 3243 .bp_in_mask = 0xffff, 3244 .hfb_filter_cnt = 16, 3245 .qtag_mask = 0x1F, 3246 .hfb_offset = 0x1000, 3247 .rdma_offset = 0x2000, 3248 .tdma_offset = 0x3000, 3249 .words_per_bd = 2, 3250 }, 3251 [GENET_V2] = { 3252 .tx_queues = 4, 3253 .tx_bds_per_q = 32, 3254 .rx_queues = 0, 3255 .rx_bds_per_q = 0, 3256 .bp_in_en_shift = 16, 3257 .bp_in_mask = 0xffff, 3258 .hfb_filter_cnt = 16, 3259 .qtag_mask = 0x1F, 3260 .tbuf_offset = 0x0600, 3261 .hfb_offset = 0x1000, 3262 .hfb_reg_offset = 0x2000, 3263 .rdma_offset = 0x3000, 3264 .tdma_offset = 0x4000, 3265 .words_per_bd = 2, 3266 .flags = GENET_HAS_EXT, 3267 }, 3268 [GENET_V3] = { 3269 .tx_queues = 4, 3270 .tx_bds_per_q = 32, 3271 .rx_queues = 0, 3272 .rx_bds_per_q = 0, 3273 .bp_in_en_shift = 17, 3274 .bp_in_mask = 0x1ffff, 3275 .hfb_filter_cnt = 48, 3276 .hfb_filter_size = 128, 3277 .qtag_mask = 0x3F, 3278 .tbuf_offset = 0x0600, 3279 .hfb_offset = 0x8000, 3280 .hfb_reg_offset = 0xfc00, 3281 .rdma_offset = 0x10000, 3282 .tdma_offset = 0x11000, 3283 .words_per_bd = 2, 3284 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3285 GENET_HAS_MOCA_LINK_DET, 3286 }, 3287 [GENET_V4] = { 3288 .tx_queues = 4, 3289 .tx_bds_per_q = 32, 3290 .rx_queues = 0, 3291 .rx_bds_per_q = 0, 3292 .bp_in_en_shift = 17, 3293 .bp_in_mask = 0x1ffff, 3294 .hfb_filter_cnt = 48, 3295 .hfb_filter_size = 128, 3296 .qtag_mask = 0x3F, 3297 .tbuf_offset = 0x0600, 3298 .hfb_offset = 0x8000, 3299 .hfb_reg_offset = 0xfc00, 3300 .rdma_offset = 0x2000, 3301 .tdma_offset = 0x4000, 3302 .words_per_bd = 3, 3303 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3304 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3305 }, 3306 [GENET_V5] = { 3307 .tx_queues = 4, 3308 .tx_bds_per_q = 32, 3309 .rx_queues = 0, 3310 .rx_bds_per_q = 0, 3311 .bp_in_en_shift = 17, 3312 .bp_in_mask = 0x1ffff, 3313 .hfb_filter_cnt = 48, 3314 .hfb_filter_size = 128, 3315 .qtag_mask = 0x3F, 3316 .tbuf_offset = 0x0600, 3317 .hfb_offset = 0x8000, 3318 .hfb_reg_offset = 0xfc00, 3319 .rdma_offset = 0x2000, 3320 .tdma_offset = 0x4000, 3321 .words_per_bd = 3, 3322 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3323 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3324 }, 3325 }; 3326 3327 /* Infer hardware parameters from the detected GENET version */ 3328 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3329 { 3330 struct bcmgenet_hw_params *params; 3331 u32 reg; 3332 u8 major; 3333 u16 gphy_rev; 3334 3335 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3336 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3337 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3338 } else if (GENET_IS_V3(priv)) { 3339 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3340 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3341 } else if (GENET_IS_V2(priv)) { 3342 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3343 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3344 } else if (GENET_IS_V1(priv)) { 3345 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3346 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3347 } 3348 3349 /* enum genet_version starts at 1 */ 3350 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3351 params = priv->hw_params; 3352 3353 /* Read GENET HW version */ 3354 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3355 major = (reg >> 24 & 0x0f); 3356 if (major == 6) 3357 major = 5; 3358 else if (major == 5) 3359 major = 4; 3360 else if (major == 0) 3361 major = 1; 3362 if (major != priv->version) { 3363 dev_err(&priv->pdev->dev, 3364 "GENET version mismatch, got: %d, configured for: %d\n", 3365 major, priv->version); 3366 } 3367 3368 /* Print the GENET core version */ 3369 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3370 major, (reg >> 16) & 0x0f, reg & 0xffff); 3371 3372 /* Store the integrated PHY revision for the MDIO probing function 3373 * to pass this information to the PHY driver. The PHY driver expects 3374 * to find the PHY major revision in bits 15:8 while the GENET register 3375 * stores that information in bits 7:0, account for that. 3376 * 3377 * On newer chips, starting with PHY revision G0, a new scheme is 3378 * deployed similar to the Starfighter 2 switch with GPHY major 3379 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3380 * is reserved as well as special value 0x01ff, we have a small 3381 * heuristic to check for the new GPHY revision and re-arrange things 3382 * so the GPHY driver is happy. 3383 */ 3384 gphy_rev = reg & 0xffff; 3385 3386 if (GENET_IS_V5(priv)) { 3387 /* The EPHY revision should come from the MDIO registers of 3388 * the PHY not from GENET. 3389 */ 3390 if (gphy_rev != 0) { 3391 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3392 gphy_rev); 3393 } 3394 /* This is reserved so should require special treatment */ 3395 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3396 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3397 return; 3398 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3399 } else if ((gphy_rev & 0xf0) != 0) { 3400 priv->gphy_rev = gphy_rev << 8; 3401 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3402 } else if ((gphy_rev & 0xff00) != 0) { 3403 priv->gphy_rev = gphy_rev; 3404 } 3405 3406 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3407 if (!(params->flags & GENET_HAS_40BITS)) 3408 pr_warn("GENET does not support 40-bits PA\n"); 3409 #endif 3410 3411 pr_debug("Configuration for version: %d\n" 3412 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3413 "BP << en: %2d, BP msk: 0x%05x\n" 3414 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3415 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3416 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3417 "Words/BD: %d\n", 3418 priv->version, 3419 params->tx_queues, params->tx_bds_per_q, 3420 params->rx_queues, params->rx_bds_per_q, 3421 params->bp_in_en_shift, params->bp_in_mask, 3422 params->hfb_filter_cnt, params->qtag_mask, 3423 params->tbuf_offset, params->hfb_offset, 3424 params->hfb_reg_offset, 3425 params->rdma_offset, params->tdma_offset, 3426 params->words_per_bd); 3427 } 3428 3429 struct bcmgenet_plat_data { 3430 enum bcmgenet_version version; 3431 u32 dma_max_burst_length; 3432 }; 3433 3434 static const struct bcmgenet_plat_data v1_plat_data = { 3435 .version = GENET_V1, 3436 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3437 }; 3438 3439 static const struct bcmgenet_plat_data v2_plat_data = { 3440 .version = GENET_V2, 3441 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3442 }; 3443 3444 static const struct bcmgenet_plat_data v3_plat_data = { 3445 .version = GENET_V3, 3446 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3447 }; 3448 3449 static const struct bcmgenet_plat_data v4_plat_data = { 3450 .version = GENET_V4, 3451 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3452 }; 3453 3454 static const struct bcmgenet_plat_data v5_plat_data = { 3455 .version = GENET_V5, 3456 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3457 }; 3458 3459 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3460 .version = GENET_V5, 3461 .dma_max_burst_length = 0x08, 3462 }; 3463 3464 static const struct of_device_id bcmgenet_match[] = { 3465 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3466 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3467 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3468 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3469 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3470 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3471 { }, 3472 }; 3473 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3474 3475 static int bcmgenet_probe(struct platform_device *pdev) 3476 { 3477 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3478 struct device_node *dn = pdev->dev.of_node; 3479 const struct of_device_id *of_id = NULL; 3480 const struct bcmgenet_plat_data *pdata; 3481 struct bcmgenet_priv *priv; 3482 struct net_device *dev; 3483 unsigned int i; 3484 int err = -EIO; 3485 3486 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3487 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3488 GENET_MAX_MQ_CNT + 1); 3489 if (!dev) { 3490 dev_err(&pdev->dev, "can't allocate net device\n"); 3491 return -ENOMEM; 3492 } 3493 3494 if (dn) { 3495 of_id = of_match_node(bcmgenet_match, dn); 3496 if (!of_id) 3497 return -EINVAL; 3498 } 3499 3500 priv = netdev_priv(dev); 3501 priv->irq0 = platform_get_irq(pdev, 0); 3502 if (priv->irq0 < 0) { 3503 err = priv->irq0; 3504 goto err; 3505 } 3506 priv->irq1 = platform_get_irq(pdev, 1); 3507 if (priv->irq1 < 0) { 3508 err = priv->irq1; 3509 goto err; 3510 } 3511 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3512 3513 priv->base = devm_platform_ioremap_resource(pdev, 0); 3514 if (IS_ERR(priv->base)) { 3515 err = PTR_ERR(priv->base); 3516 goto err; 3517 } 3518 3519 spin_lock_init(&priv->lock); 3520 3521 SET_NETDEV_DEV(dev, &pdev->dev); 3522 dev_set_drvdata(&pdev->dev, dev); 3523 dev->watchdog_timeo = 2 * HZ; 3524 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3525 dev->netdev_ops = &bcmgenet_netdev_ops; 3526 3527 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3528 3529 /* Set default features */ 3530 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3531 NETIF_F_RXCSUM; 3532 dev->hw_features |= dev->features; 3533 dev->vlan_features |= dev->features; 3534 3535 /* Request the WOL interrupt and advertise suspend if available */ 3536 priv->wol_irq_disabled = true; 3537 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3538 dev->name, priv); 3539 if (!err) 3540 device_set_wakeup_capable(&pdev->dev, 1); 3541 3542 /* Set the needed headroom to account for any possible 3543 * features enabling/disabling at runtime 3544 */ 3545 dev->needed_headroom += 64; 3546 3547 netdev_boot_setup_check(dev); 3548 3549 priv->dev = dev; 3550 priv->pdev = pdev; 3551 3552 pdata = device_get_match_data(&pdev->dev); 3553 if (pdata) { 3554 priv->version = pdata->version; 3555 priv->dma_max_burst_length = pdata->dma_max_burst_length; 3556 } else { 3557 priv->version = pd->genet_version; 3558 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 3559 } 3560 3561 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3562 if (IS_ERR(priv->clk)) { 3563 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 3564 priv->clk = NULL; 3565 } 3566 3567 clk_prepare_enable(priv->clk); 3568 3569 bcmgenet_set_hw_params(priv); 3570 3571 err = -EIO; 3572 if (priv->hw_params->flags & GENET_HAS_40BITS) 3573 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 3574 if (err) 3575 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3576 if (err) 3577 goto err; 3578 3579 /* Mii wait queue */ 3580 init_waitqueue_head(&priv->wq); 3581 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3582 priv->rx_buf_len = RX_BUF_LENGTH; 3583 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3584 3585 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3586 if (IS_ERR(priv->clk_wol)) { 3587 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3588 priv->clk_wol = NULL; 3589 } 3590 3591 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3592 if (IS_ERR(priv->clk_eee)) { 3593 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3594 priv->clk_eee = NULL; 3595 } 3596 3597 /* If this is an internal GPHY, power it on now, before UniMAC is 3598 * brought out of reset as absolutely no UniMAC activity is allowed 3599 */ 3600 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 3601 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3602 3603 if ((pd) && (!IS_ERR_OR_NULL(pd->mac_address))) 3604 ether_addr_copy(dev->dev_addr, pd->mac_address); 3605 else 3606 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 3607 if (has_acpi_companion(&pdev->dev)) 3608 bcmgenet_get_hw_addr(priv, dev->dev_addr); 3609 3610 if (!is_valid_ether_addr(dev->dev_addr)) { 3611 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 3612 eth_hw_addr_random(dev); 3613 } 3614 3615 reset_umac(priv); 3616 3617 err = bcmgenet_mii_init(dev); 3618 if (err) 3619 goto err_clk_disable; 3620 3621 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3622 * just the ring 16 descriptor based TX 3623 */ 3624 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3625 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3626 3627 /* Set default coalescing parameters */ 3628 for (i = 0; i < priv->hw_params->rx_queues; i++) 3629 priv->rx_rings[i].rx_max_coalesced_frames = 1; 3630 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 3631 3632 /* libphy will determine the link state */ 3633 netif_carrier_off(dev); 3634 3635 /* Turn off the main clock, WOL clock is handled separately */ 3636 clk_disable_unprepare(priv->clk); 3637 3638 err = register_netdev(dev); 3639 if (err) 3640 goto err; 3641 3642 return err; 3643 3644 err_clk_disable: 3645 clk_disable_unprepare(priv->clk); 3646 err: 3647 free_netdev(dev); 3648 return err; 3649 } 3650 3651 static int bcmgenet_remove(struct platform_device *pdev) 3652 { 3653 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3654 3655 dev_set_drvdata(&pdev->dev, NULL); 3656 unregister_netdev(priv->dev); 3657 bcmgenet_mii_exit(priv->dev); 3658 free_netdev(priv->dev); 3659 3660 return 0; 3661 } 3662 3663 static void bcmgenet_shutdown(struct platform_device *pdev) 3664 { 3665 bcmgenet_remove(pdev); 3666 } 3667 3668 #ifdef CONFIG_PM_SLEEP 3669 static int bcmgenet_resume(struct device *d) 3670 { 3671 struct net_device *dev = dev_get_drvdata(d); 3672 struct bcmgenet_priv *priv = netdev_priv(dev); 3673 unsigned long dma_ctrl; 3674 int ret; 3675 u32 reg; 3676 3677 if (!netif_running(dev)) 3678 return 0; 3679 3680 /* Turn on the clock */ 3681 ret = clk_prepare_enable(priv->clk); 3682 if (ret) 3683 return ret; 3684 3685 /* If this is an internal GPHY, power it back on now, before UniMAC is 3686 * brought out of reset as absolutely no UniMAC activity is allowed 3687 */ 3688 if (priv->internal_phy) 3689 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3690 3691 bcmgenet_umac_reset(priv); 3692 3693 init_umac(priv); 3694 3695 /* From WOL-enabled suspend, switch to regular clock */ 3696 if (priv->wolopts) 3697 clk_disable_unprepare(priv->clk_wol); 3698 3699 phy_init_hw(dev->phydev); 3700 3701 /* Speed settings must be restored */ 3702 genphy_config_aneg(dev->phydev); 3703 bcmgenet_mii_config(priv->dev, false); 3704 3705 /* Restore enabled features */ 3706 bcmgenet_set_features(dev, dev->features); 3707 3708 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3709 3710 if (priv->internal_phy) { 3711 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3712 reg |= EXT_ENERGY_DET_MASK; 3713 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3714 } 3715 3716 if (priv->wolopts) 3717 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3718 3719 /* Disable RX/TX DMA and flush TX queues */ 3720 dma_ctrl = bcmgenet_dma_disable(priv); 3721 3722 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3723 ret = bcmgenet_init_dma(priv); 3724 if (ret) { 3725 netdev_err(dev, "failed to initialize DMA\n"); 3726 goto out_clk_disable; 3727 } 3728 3729 /* Always enable ring 16 - descriptor ring */ 3730 bcmgenet_enable_dma(priv, dma_ctrl); 3731 3732 if (!device_may_wakeup(d)) 3733 phy_resume(dev->phydev); 3734 3735 if (priv->eee.eee_enabled) 3736 bcmgenet_eee_enable_set(dev, true); 3737 3738 bcmgenet_netif_start(dev); 3739 3740 netif_device_attach(dev); 3741 3742 return 0; 3743 3744 out_clk_disable: 3745 if (priv->internal_phy) 3746 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3747 clk_disable_unprepare(priv->clk); 3748 return ret; 3749 } 3750 3751 static int bcmgenet_suspend(struct device *d) 3752 { 3753 struct net_device *dev = dev_get_drvdata(d); 3754 struct bcmgenet_priv *priv = netdev_priv(dev); 3755 int ret = 0; 3756 3757 if (!netif_running(dev)) 3758 return 0; 3759 3760 netif_device_detach(dev); 3761 3762 bcmgenet_netif_stop(dev); 3763 3764 if (!device_may_wakeup(d)) 3765 phy_suspend(dev->phydev); 3766 3767 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3768 if (device_may_wakeup(d) && priv->wolopts) { 3769 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3770 clk_prepare_enable(priv->clk_wol); 3771 } else if (priv->internal_phy) { 3772 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3773 } 3774 3775 /* Turn off the clocks */ 3776 clk_disable_unprepare(priv->clk); 3777 3778 if (ret) 3779 bcmgenet_resume(d); 3780 3781 return ret; 3782 } 3783 #endif /* CONFIG_PM_SLEEP */ 3784 3785 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3786 3787 static const struct acpi_device_id genet_acpi_match[] = { 3788 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 3789 { }, 3790 }; 3791 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 3792 3793 static struct platform_driver bcmgenet_driver = { 3794 .probe = bcmgenet_probe, 3795 .remove = bcmgenet_remove, 3796 .shutdown = bcmgenet_shutdown, 3797 .driver = { 3798 .name = "bcmgenet", 3799 .of_match_table = bcmgenet_match, 3800 .pm = &bcmgenet_pm_ops, 3801 .acpi_match_table = ACPI_PTR(genet_acpi_match), 3802 }, 3803 }; 3804 module_platform_driver(bcmgenet_driver); 3805 3806 MODULE_AUTHOR("Broadcom Corporation"); 3807 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3808 MODULE_ALIAS("platform:bcmgenet"); 3809 MODULE_LICENSE("GPL"); 3810