1 /* 2 * Broadcom GENET (Gigabit Ethernet) controller driver 3 * 4 * Copyright (c) 2014-2017 Broadcom 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #define pr_fmt(fmt) "bcmgenet: " fmt 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/types.h> 17 #include <linux/fcntl.h> 18 #include <linux/interrupt.h> 19 #include <linux/string.h> 20 #include <linux/if_ether.h> 21 #include <linux/init.h> 22 #include <linux/errno.h> 23 #include <linux/delay.h> 24 #include <linux/platform_device.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/pm.h> 27 #include <linux/clk.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_net.h> 32 #include <linux/of_platform.h> 33 #include <net/arp.h> 34 35 #include <linux/mii.h> 36 #include <linux/ethtool.h> 37 #include <linux/netdevice.h> 38 #include <linux/inetdevice.h> 39 #include <linux/etherdevice.h> 40 #include <linux/skbuff.h> 41 #include <linux/in.h> 42 #include <linux/ip.h> 43 #include <linux/ipv6.h> 44 #include <linux/phy.h> 45 #include <linux/platform_data/bcmgenet.h> 46 47 #include <asm/unaligned.h> 48 49 #include "bcmgenet.h" 50 51 /* Maximum number of hardware queues, downsized if needed */ 52 #define GENET_MAX_MQ_CNT 4 53 54 /* Default highest priority queue for multi queue support */ 55 #define GENET_Q0_PRIORITY 0 56 57 #define GENET_Q16_RX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 59 #define GENET_Q16_TX_BD_CNT \ 60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 61 62 #define RX_BUF_LENGTH 2048 63 #define SKB_ALIGNMENT 32 64 65 /* Tx/Rx DMA register offset, skip 256 descriptors */ 66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 68 69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 70 TOTAL_DESC * DMA_DESC_SIZE) 71 72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 73 TOTAL_DESC * DMA_DESC_SIZE) 74 75 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 76 { 77 /* MIPS chips strapped for BE will automagically configure the 78 * peripheral registers for CPU-native byte order. 79 */ 80 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 81 __raw_writel(value, offset); 82 else 83 writel_relaxed(value, offset); 84 } 85 86 static inline u32 bcmgenet_readl(void __iomem *offset) 87 { 88 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 89 return __raw_readl(offset); 90 else 91 return readl_relaxed(offset); 92 } 93 94 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 95 void __iomem *d, u32 value) 96 { 97 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 98 } 99 100 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 101 void __iomem *d) 102 { 103 return bcmgenet_readl(d + DMA_DESC_LENGTH_STATUS); 104 } 105 106 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 107 void __iomem *d, 108 dma_addr_t addr) 109 { 110 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 111 112 /* Register writes to GISB bus can take couple hundred nanoseconds 113 * and are done for each packet, save these expensive writes unless 114 * the platform is explicitly configured for 64-bits/LPAE. 115 */ 116 #ifdef CONFIG_PHYS_ADDR_T_64BIT 117 if (priv->hw_params->flags & GENET_HAS_40BITS) 118 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 119 #endif 120 } 121 122 /* Combined address + length/status setter */ 123 static inline void dmadesc_set(struct bcmgenet_priv *priv, 124 void __iomem *d, dma_addr_t addr, u32 val) 125 { 126 dmadesc_set_addr(priv, d, addr); 127 dmadesc_set_length_status(priv, d, val); 128 } 129 130 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 131 void __iomem *d) 132 { 133 dma_addr_t addr; 134 135 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 136 137 /* Register writes to GISB bus can take couple hundred nanoseconds 138 * and are done for each packet, save these expensive writes unless 139 * the platform is explicitly configured for 64-bits/LPAE. 140 */ 141 #ifdef CONFIG_PHYS_ADDR_T_64BIT 142 if (priv->hw_params->flags & GENET_HAS_40BITS) 143 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 144 #endif 145 return addr; 146 } 147 148 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 149 150 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 151 NETIF_MSG_LINK) 152 153 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 154 { 155 if (GENET_IS_V1(priv)) 156 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 157 else 158 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 159 } 160 161 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 162 { 163 if (GENET_IS_V1(priv)) 164 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 165 else 166 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 167 } 168 169 /* These macros are defined to deal with register map change 170 * between GENET1.1 and GENET2. Only those currently being used 171 * by driver are defined. 172 */ 173 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 174 { 175 if (GENET_IS_V1(priv)) 176 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 177 else 178 return bcmgenet_readl(priv->base + 179 priv->hw_params->tbuf_offset + TBUF_CTRL); 180 } 181 182 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 183 { 184 if (GENET_IS_V1(priv)) 185 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 186 else 187 bcmgenet_writel(val, priv->base + 188 priv->hw_params->tbuf_offset + TBUF_CTRL); 189 } 190 191 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 192 { 193 if (GENET_IS_V1(priv)) 194 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 195 else 196 return bcmgenet_readl(priv->base + 197 priv->hw_params->tbuf_offset + TBUF_BP_MC); 198 } 199 200 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 201 { 202 if (GENET_IS_V1(priv)) 203 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 204 else 205 bcmgenet_writel(val, priv->base + 206 priv->hw_params->tbuf_offset + TBUF_BP_MC); 207 } 208 209 /* RX/TX DMA register accessors */ 210 enum dma_reg { 211 DMA_RING_CFG = 0, 212 DMA_CTRL, 213 DMA_STATUS, 214 DMA_SCB_BURST_SIZE, 215 DMA_ARB_CTRL, 216 DMA_PRIORITY_0, 217 DMA_PRIORITY_1, 218 DMA_PRIORITY_2, 219 DMA_INDEX2RING_0, 220 DMA_INDEX2RING_1, 221 DMA_INDEX2RING_2, 222 DMA_INDEX2RING_3, 223 DMA_INDEX2RING_4, 224 DMA_INDEX2RING_5, 225 DMA_INDEX2RING_6, 226 DMA_INDEX2RING_7, 227 DMA_RING0_TIMEOUT, 228 DMA_RING1_TIMEOUT, 229 DMA_RING2_TIMEOUT, 230 DMA_RING3_TIMEOUT, 231 DMA_RING4_TIMEOUT, 232 DMA_RING5_TIMEOUT, 233 DMA_RING6_TIMEOUT, 234 DMA_RING7_TIMEOUT, 235 DMA_RING8_TIMEOUT, 236 DMA_RING9_TIMEOUT, 237 DMA_RING10_TIMEOUT, 238 DMA_RING11_TIMEOUT, 239 DMA_RING12_TIMEOUT, 240 DMA_RING13_TIMEOUT, 241 DMA_RING14_TIMEOUT, 242 DMA_RING15_TIMEOUT, 243 DMA_RING16_TIMEOUT, 244 }; 245 246 static const u8 bcmgenet_dma_regs_v3plus[] = { 247 [DMA_RING_CFG] = 0x00, 248 [DMA_CTRL] = 0x04, 249 [DMA_STATUS] = 0x08, 250 [DMA_SCB_BURST_SIZE] = 0x0C, 251 [DMA_ARB_CTRL] = 0x2C, 252 [DMA_PRIORITY_0] = 0x30, 253 [DMA_PRIORITY_1] = 0x34, 254 [DMA_PRIORITY_2] = 0x38, 255 [DMA_RING0_TIMEOUT] = 0x2C, 256 [DMA_RING1_TIMEOUT] = 0x30, 257 [DMA_RING2_TIMEOUT] = 0x34, 258 [DMA_RING3_TIMEOUT] = 0x38, 259 [DMA_RING4_TIMEOUT] = 0x3c, 260 [DMA_RING5_TIMEOUT] = 0x40, 261 [DMA_RING6_TIMEOUT] = 0x44, 262 [DMA_RING7_TIMEOUT] = 0x48, 263 [DMA_RING8_TIMEOUT] = 0x4c, 264 [DMA_RING9_TIMEOUT] = 0x50, 265 [DMA_RING10_TIMEOUT] = 0x54, 266 [DMA_RING11_TIMEOUT] = 0x58, 267 [DMA_RING12_TIMEOUT] = 0x5c, 268 [DMA_RING13_TIMEOUT] = 0x60, 269 [DMA_RING14_TIMEOUT] = 0x64, 270 [DMA_RING15_TIMEOUT] = 0x68, 271 [DMA_RING16_TIMEOUT] = 0x6C, 272 [DMA_INDEX2RING_0] = 0x70, 273 [DMA_INDEX2RING_1] = 0x74, 274 [DMA_INDEX2RING_2] = 0x78, 275 [DMA_INDEX2RING_3] = 0x7C, 276 [DMA_INDEX2RING_4] = 0x80, 277 [DMA_INDEX2RING_5] = 0x84, 278 [DMA_INDEX2RING_6] = 0x88, 279 [DMA_INDEX2RING_7] = 0x8C, 280 }; 281 282 static const u8 bcmgenet_dma_regs_v2[] = { 283 [DMA_RING_CFG] = 0x00, 284 [DMA_CTRL] = 0x04, 285 [DMA_STATUS] = 0x08, 286 [DMA_SCB_BURST_SIZE] = 0x0C, 287 [DMA_ARB_CTRL] = 0x30, 288 [DMA_PRIORITY_0] = 0x34, 289 [DMA_PRIORITY_1] = 0x38, 290 [DMA_PRIORITY_2] = 0x3C, 291 [DMA_RING0_TIMEOUT] = 0x2C, 292 [DMA_RING1_TIMEOUT] = 0x30, 293 [DMA_RING2_TIMEOUT] = 0x34, 294 [DMA_RING3_TIMEOUT] = 0x38, 295 [DMA_RING4_TIMEOUT] = 0x3c, 296 [DMA_RING5_TIMEOUT] = 0x40, 297 [DMA_RING6_TIMEOUT] = 0x44, 298 [DMA_RING7_TIMEOUT] = 0x48, 299 [DMA_RING8_TIMEOUT] = 0x4c, 300 [DMA_RING9_TIMEOUT] = 0x50, 301 [DMA_RING10_TIMEOUT] = 0x54, 302 [DMA_RING11_TIMEOUT] = 0x58, 303 [DMA_RING12_TIMEOUT] = 0x5c, 304 [DMA_RING13_TIMEOUT] = 0x60, 305 [DMA_RING14_TIMEOUT] = 0x64, 306 [DMA_RING15_TIMEOUT] = 0x68, 307 [DMA_RING16_TIMEOUT] = 0x6C, 308 }; 309 310 static const u8 bcmgenet_dma_regs_v1[] = { 311 [DMA_CTRL] = 0x00, 312 [DMA_STATUS] = 0x04, 313 [DMA_SCB_BURST_SIZE] = 0x0C, 314 [DMA_ARB_CTRL] = 0x30, 315 [DMA_PRIORITY_0] = 0x34, 316 [DMA_PRIORITY_1] = 0x38, 317 [DMA_PRIORITY_2] = 0x3C, 318 [DMA_RING0_TIMEOUT] = 0x2C, 319 [DMA_RING1_TIMEOUT] = 0x30, 320 [DMA_RING2_TIMEOUT] = 0x34, 321 [DMA_RING3_TIMEOUT] = 0x38, 322 [DMA_RING4_TIMEOUT] = 0x3c, 323 [DMA_RING5_TIMEOUT] = 0x40, 324 [DMA_RING6_TIMEOUT] = 0x44, 325 [DMA_RING7_TIMEOUT] = 0x48, 326 [DMA_RING8_TIMEOUT] = 0x4c, 327 [DMA_RING9_TIMEOUT] = 0x50, 328 [DMA_RING10_TIMEOUT] = 0x54, 329 [DMA_RING11_TIMEOUT] = 0x58, 330 [DMA_RING12_TIMEOUT] = 0x5c, 331 [DMA_RING13_TIMEOUT] = 0x60, 332 [DMA_RING14_TIMEOUT] = 0x64, 333 [DMA_RING15_TIMEOUT] = 0x68, 334 [DMA_RING16_TIMEOUT] = 0x6C, 335 }; 336 337 /* Set at runtime once bcmgenet version is known */ 338 static const u8 *bcmgenet_dma_regs; 339 340 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 341 { 342 return netdev_priv(dev_get_drvdata(dev)); 343 } 344 345 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 346 enum dma_reg r) 347 { 348 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 349 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 350 } 351 352 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 353 u32 val, enum dma_reg r) 354 { 355 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 356 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 357 } 358 359 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 360 enum dma_reg r) 361 { 362 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 363 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 364 } 365 366 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 367 u32 val, enum dma_reg r) 368 { 369 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 370 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 371 } 372 373 /* RDMA/TDMA ring registers and accessors 374 * we merge the common fields and just prefix with T/D the registers 375 * having different meaning depending on the direction 376 */ 377 enum dma_ring_reg { 378 TDMA_READ_PTR = 0, 379 RDMA_WRITE_PTR = TDMA_READ_PTR, 380 TDMA_READ_PTR_HI, 381 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 382 TDMA_CONS_INDEX, 383 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 384 TDMA_PROD_INDEX, 385 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 386 DMA_RING_BUF_SIZE, 387 DMA_START_ADDR, 388 DMA_START_ADDR_HI, 389 DMA_END_ADDR, 390 DMA_END_ADDR_HI, 391 DMA_MBUF_DONE_THRESH, 392 TDMA_FLOW_PERIOD, 393 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 394 TDMA_WRITE_PTR, 395 RDMA_READ_PTR = TDMA_WRITE_PTR, 396 TDMA_WRITE_PTR_HI, 397 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 398 }; 399 400 /* GENET v4 supports 40-bits pointer addressing 401 * for obvious reasons the LO and HI word parts 402 * are contiguous, but this offsets the other 403 * registers. 404 */ 405 static const u8 genet_dma_ring_regs_v4[] = { 406 [TDMA_READ_PTR] = 0x00, 407 [TDMA_READ_PTR_HI] = 0x04, 408 [TDMA_CONS_INDEX] = 0x08, 409 [TDMA_PROD_INDEX] = 0x0C, 410 [DMA_RING_BUF_SIZE] = 0x10, 411 [DMA_START_ADDR] = 0x14, 412 [DMA_START_ADDR_HI] = 0x18, 413 [DMA_END_ADDR] = 0x1C, 414 [DMA_END_ADDR_HI] = 0x20, 415 [DMA_MBUF_DONE_THRESH] = 0x24, 416 [TDMA_FLOW_PERIOD] = 0x28, 417 [TDMA_WRITE_PTR] = 0x2C, 418 [TDMA_WRITE_PTR_HI] = 0x30, 419 }; 420 421 static const u8 genet_dma_ring_regs_v123[] = { 422 [TDMA_READ_PTR] = 0x00, 423 [TDMA_CONS_INDEX] = 0x04, 424 [TDMA_PROD_INDEX] = 0x08, 425 [DMA_RING_BUF_SIZE] = 0x0C, 426 [DMA_START_ADDR] = 0x10, 427 [DMA_END_ADDR] = 0x14, 428 [DMA_MBUF_DONE_THRESH] = 0x18, 429 [TDMA_FLOW_PERIOD] = 0x1C, 430 [TDMA_WRITE_PTR] = 0x20, 431 }; 432 433 /* Set at runtime once GENET version is known */ 434 static const u8 *genet_dma_ring_regs; 435 436 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 437 unsigned int ring, 438 enum dma_ring_reg r) 439 { 440 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 441 (DMA_RING_SIZE * ring) + 442 genet_dma_ring_regs[r]); 443 } 444 445 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 446 unsigned int ring, u32 val, 447 enum dma_ring_reg r) 448 { 449 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 450 (DMA_RING_SIZE * ring) + 451 genet_dma_ring_regs[r]); 452 } 453 454 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 455 unsigned int ring, 456 enum dma_ring_reg r) 457 { 458 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 459 (DMA_RING_SIZE * ring) + 460 genet_dma_ring_regs[r]); 461 } 462 463 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 464 unsigned int ring, u32 val, 465 enum dma_ring_reg r) 466 { 467 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 468 (DMA_RING_SIZE * ring) + 469 genet_dma_ring_regs[r]); 470 } 471 472 static int bcmgenet_begin(struct net_device *dev) 473 { 474 struct bcmgenet_priv *priv = netdev_priv(dev); 475 476 /* Turn on the clock */ 477 return clk_prepare_enable(priv->clk); 478 } 479 480 static void bcmgenet_complete(struct net_device *dev) 481 { 482 struct bcmgenet_priv *priv = netdev_priv(dev); 483 484 /* Turn off the clock */ 485 clk_disable_unprepare(priv->clk); 486 } 487 488 static int bcmgenet_get_link_ksettings(struct net_device *dev, 489 struct ethtool_link_ksettings *cmd) 490 { 491 struct bcmgenet_priv *priv = netdev_priv(dev); 492 493 if (!netif_running(dev)) 494 return -EINVAL; 495 496 if (!priv->phydev) 497 return -ENODEV; 498 499 phy_ethtool_ksettings_get(priv->phydev, cmd); 500 501 return 0; 502 } 503 504 static int bcmgenet_set_link_ksettings(struct net_device *dev, 505 const struct ethtool_link_ksettings *cmd) 506 { 507 struct bcmgenet_priv *priv = netdev_priv(dev); 508 509 if (!netif_running(dev)) 510 return -EINVAL; 511 512 if (!priv->phydev) 513 return -ENODEV; 514 515 return phy_ethtool_ksettings_set(priv->phydev, cmd); 516 } 517 518 static int bcmgenet_set_rx_csum(struct net_device *dev, 519 netdev_features_t wanted) 520 { 521 struct bcmgenet_priv *priv = netdev_priv(dev); 522 u32 rbuf_chk_ctrl; 523 bool rx_csum_en; 524 525 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 526 527 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 528 529 /* enable rx checksumming */ 530 if (rx_csum_en) 531 rbuf_chk_ctrl |= RBUF_RXCHK_EN; 532 else 533 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 534 priv->desc_rxchk_en = rx_csum_en; 535 536 /* If UniMAC forwards CRC, we need to skip over it to get 537 * a valid CHK bit to be set in the per-packet status word 538 */ 539 if (rx_csum_en && priv->crc_fwd_en) 540 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 541 else 542 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 543 544 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 545 546 return 0; 547 } 548 549 static int bcmgenet_set_tx_csum(struct net_device *dev, 550 netdev_features_t wanted) 551 { 552 struct bcmgenet_priv *priv = netdev_priv(dev); 553 bool desc_64b_en; 554 u32 tbuf_ctrl, rbuf_ctrl; 555 556 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 557 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 558 559 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 560 561 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 562 if (desc_64b_en) { 563 tbuf_ctrl |= RBUF_64B_EN; 564 rbuf_ctrl |= RBUF_64B_EN; 565 } else { 566 tbuf_ctrl &= ~RBUF_64B_EN; 567 rbuf_ctrl &= ~RBUF_64B_EN; 568 } 569 priv->desc_64b_en = desc_64b_en; 570 571 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 572 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 573 574 return 0; 575 } 576 577 static int bcmgenet_set_features(struct net_device *dev, 578 netdev_features_t features) 579 { 580 netdev_features_t changed = features ^ dev->features; 581 netdev_features_t wanted = dev->wanted_features; 582 int ret = 0; 583 584 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 585 ret = bcmgenet_set_tx_csum(dev, wanted); 586 if (changed & (NETIF_F_RXCSUM)) 587 ret = bcmgenet_set_rx_csum(dev, wanted); 588 589 return ret; 590 } 591 592 static u32 bcmgenet_get_msglevel(struct net_device *dev) 593 { 594 struct bcmgenet_priv *priv = netdev_priv(dev); 595 596 return priv->msg_enable; 597 } 598 599 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 600 { 601 struct bcmgenet_priv *priv = netdev_priv(dev); 602 603 priv->msg_enable = level; 604 } 605 606 static int bcmgenet_get_coalesce(struct net_device *dev, 607 struct ethtool_coalesce *ec) 608 { 609 struct bcmgenet_priv *priv = netdev_priv(dev); 610 611 ec->tx_max_coalesced_frames = 612 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 613 DMA_MBUF_DONE_THRESH); 614 ec->rx_max_coalesced_frames = 615 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 616 DMA_MBUF_DONE_THRESH); 617 ec->rx_coalesce_usecs = 618 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 619 620 return 0; 621 } 622 623 static int bcmgenet_set_coalesce(struct net_device *dev, 624 struct ethtool_coalesce *ec) 625 { 626 struct bcmgenet_priv *priv = netdev_priv(dev); 627 unsigned int i; 628 u32 reg; 629 630 /* Base system clock is 125Mhz, DMA timeout is this reference clock 631 * divided by 1024, which yields roughly 8.192us, our maximum value 632 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 633 */ 634 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 635 ec->tx_max_coalesced_frames == 0 || 636 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 637 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 638 return -EINVAL; 639 640 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 641 return -EINVAL; 642 643 /* GENET TDMA hardware does not support a configurable timeout, but will 644 * always generate an interrupt either after MBDONE packets have been 645 * transmitted, or when the ring is empty. 646 */ 647 if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high || 648 ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low) 649 return -EOPNOTSUPP; 650 651 /* Program all TX queues with the same values, as there is no 652 * ethtool knob to do coalescing on a per-queue basis 653 */ 654 for (i = 0; i < priv->hw_params->tx_queues; i++) 655 bcmgenet_tdma_ring_writel(priv, i, 656 ec->tx_max_coalesced_frames, 657 DMA_MBUF_DONE_THRESH); 658 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 659 ec->tx_max_coalesced_frames, 660 DMA_MBUF_DONE_THRESH); 661 662 for (i = 0; i < priv->hw_params->rx_queues; i++) { 663 bcmgenet_rdma_ring_writel(priv, i, 664 ec->rx_max_coalesced_frames, 665 DMA_MBUF_DONE_THRESH); 666 667 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 668 reg &= ~DMA_TIMEOUT_MASK; 669 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); 670 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 671 } 672 673 bcmgenet_rdma_ring_writel(priv, DESC_INDEX, 674 ec->rx_max_coalesced_frames, 675 DMA_MBUF_DONE_THRESH); 676 677 reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT); 678 reg &= ~DMA_TIMEOUT_MASK; 679 reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192); 680 bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT); 681 682 return 0; 683 } 684 685 /* standard ethtool support functions. */ 686 enum bcmgenet_stat_type { 687 BCMGENET_STAT_NETDEV = -1, 688 BCMGENET_STAT_MIB_RX, 689 BCMGENET_STAT_MIB_TX, 690 BCMGENET_STAT_RUNT, 691 BCMGENET_STAT_MISC, 692 BCMGENET_STAT_SOFT, 693 }; 694 695 struct bcmgenet_stats { 696 char stat_string[ETH_GSTRING_LEN]; 697 int stat_sizeof; 698 int stat_offset; 699 enum bcmgenet_stat_type type; 700 /* reg offset from UMAC base for misc counters */ 701 u16 reg_offset; 702 }; 703 704 #define STAT_NETDEV(m) { \ 705 .stat_string = __stringify(m), \ 706 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 707 .stat_offset = offsetof(struct net_device_stats, m), \ 708 .type = BCMGENET_STAT_NETDEV, \ 709 } 710 711 #define STAT_GENET_MIB(str, m, _type) { \ 712 .stat_string = str, \ 713 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 714 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 715 .type = _type, \ 716 } 717 718 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 719 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 720 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 721 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 722 723 #define STAT_GENET_MISC(str, m, offset) { \ 724 .stat_string = str, \ 725 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 726 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 727 .type = BCMGENET_STAT_MISC, \ 728 .reg_offset = offset, \ 729 } 730 731 #define STAT_GENET_Q(num) \ 732 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 733 tx_rings[num].packets), \ 734 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 735 tx_rings[num].bytes), \ 736 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 737 rx_rings[num].bytes), \ 738 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 739 rx_rings[num].packets), \ 740 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 741 rx_rings[num].errors), \ 742 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 743 rx_rings[num].dropped) 744 745 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 746 * between the end of TX stats and the beginning of the RX RUNT 747 */ 748 #define BCMGENET_STAT_OFFSET 0xc 749 750 /* Hardware counters must be kept in sync because the order/offset 751 * is important here (order in structure declaration = order in hardware) 752 */ 753 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 754 /* general stats */ 755 STAT_NETDEV(rx_packets), 756 STAT_NETDEV(tx_packets), 757 STAT_NETDEV(rx_bytes), 758 STAT_NETDEV(tx_bytes), 759 STAT_NETDEV(rx_errors), 760 STAT_NETDEV(tx_errors), 761 STAT_NETDEV(rx_dropped), 762 STAT_NETDEV(tx_dropped), 763 STAT_NETDEV(multicast), 764 /* UniMAC RSV counters */ 765 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 766 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 767 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 768 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 769 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 770 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 771 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 772 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 773 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 774 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 775 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 776 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 777 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 778 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 779 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 780 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 781 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 782 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 783 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 784 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 785 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 786 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 787 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 788 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 789 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 790 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 791 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 792 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 793 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 794 /* UniMAC TSV counters */ 795 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 796 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 797 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 798 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 799 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 800 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 801 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 802 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 803 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 804 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 805 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 806 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 807 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 808 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 809 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 810 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 811 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 812 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 813 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 814 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 815 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 816 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 817 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 818 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 819 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 820 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 821 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 822 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 823 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 824 /* UniMAC RUNT counters */ 825 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 826 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 827 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 828 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 829 /* Misc UniMAC counters */ 830 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 831 UMAC_RBUF_OVFL_CNT_V1), 832 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 833 UMAC_RBUF_ERR_CNT_V1), 834 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 835 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 836 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 837 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 838 /* Per TX queues */ 839 STAT_GENET_Q(0), 840 STAT_GENET_Q(1), 841 STAT_GENET_Q(2), 842 STAT_GENET_Q(3), 843 STAT_GENET_Q(16), 844 }; 845 846 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 847 848 static void bcmgenet_get_drvinfo(struct net_device *dev, 849 struct ethtool_drvinfo *info) 850 { 851 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 852 strlcpy(info->version, "v2.0", sizeof(info->version)); 853 } 854 855 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 856 { 857 switch (string_set) { 858 case ETH_SS_STATS: 859 return BCMGENET_STATS_LEN; 860 default: 861 return -EOPNOTSUPP; 862 } 863 } 864 865 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 866 u8 *data) 867 { 868 int i; 869 870 switch (stringset) { 871 case ETH_SS_STATS: 872 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 873 memcpy(data + i * ETH_GSTRING_LEN, 874 bcmgenet_gstrings_stats[i].stat_string, 875 ETH_GSTRING_LEN); 876 } 877 break; 878 } 879 } 880 881 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 882 { 883 u16 new_offset; 884 u32 val; 885 886 switch (offset) { 887 case UMAC_RBUF_OVFL_CNT_V1: 888 if (GENET_IS_V2(priv)) 889 new_offset = RBUF_OVFL_CNT_V2; 890 else 891 new_offset = RBUF_OVFL_CNT_V3PLUS; 892 893 val = bcmgenet_rbuf_readl(priv, new_offset); 894 /* clear if overflowed */ 895 if (val == ~0) 896 bcmgenet_rbuf_writel(priv, 0, new_offset); 897 break; 898 case UMAC_RBUF_ERR_CNT_V1: 899 if (GENET_IS_V2(priv)) 900 new_offset = RBUF_ERR_CNT_V2; 901 else 902 new_offset = RBUF_ERR_CNT_V3PLUS; 903 904 val = bcmgenet_rbuf_readl(priv, new_offset); 905 /* clear if overflowed */ 906 if (val == ~0) 907 bcmgenet_rbuf_writel(priv, 0, new_offset); 908 break; 909 default: 910 val = bcmgenet_umac_readl(priv, offset); 911 /* clear if overflowed */ 912 if (val == ~0) 913 bcmgenet_umac_writel(priv, 0, offset); 914 break; 915 } 916 917 return val; 918 } 919 920 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 921 { 922 int i, j = 0; 923 924 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 925 const struct bcmgenet_stats *s; 926 u8 offset = 0; 927 u32 val = 0; 928 char *p; 929 930 s = &bcmgenet_gstrings_stats[i]; 931 switch (s->type) { 932 case BCMGENET_STAT_NETDEV: 933 case BCMGENET_STAT_SOFT: 934 continue; 935 case BCMGENET_STAT_RUNT: 936 offset += BCMGENET_STAT_OFFSET; 937 /* fall through */ 938 case BCMGENET_STAT_MIB_TX: 939 offset += BCMGENET_STAT_OFFSET; 940 /* fall through */ 941 case BCMGENET_STAT_MIB_RX: 942 val = bcmgenet_umac_readl(priv, 943 UMAC_MIB_START + j + offset); 944 offset = 0; /* Reset Offset */ 945 break; 946 case BCMGENET_STAT_MISC: 947 if (GENET_IS_V1(priv)) { 948 val = bcmgenet_umac_readl(priv, s->reg_offset); 949 /* clear if overflowed */ 950 if (val == ~0) 951 bcmgenet_umac_writel(priv, 0, 952 s->reg_offset); 953 } else { 954 val = bcmgenet_update_stat_misc(priv, 955 s->reg_offset); 956 } 957 break; 958 } 959 960 j += s->stat_sizeof; 961 p = (char *)priv + s->stat_offset; 962 *(u32 *)p = val; 963 } 964 } 965 966 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 967 struct ethtool_stats *stats, 968 u64 *data) 969 { 970 struct bcmgenet_priv *priv = netdev_priv(dev); 971 int i; 972 973 if (netif_running(dev)) 974 bcmgenet_update_mib_counters(priv); 975 976 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 977 const struct bcmgenet_stats *s; 978 char *p; 979 980 s = &bcmgenet_gstrings_stats[i]; 981 if (s->type == BCMGENET_STAT_NETDEV) 982 p = (char *)&dev->stats; 983 else 984 p = (char *)priv; 985 p += s->stat_offset; 986 if (sizeof(unsigned long) != sizeof(u32) && 987 s->stat_sizeof == sizeof(unsigned long)) 988 data[i] = *(unsigned long *)p; 989 else 990 data[i] = *(u32 *)p; 991 } 992 } 993 994 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 995 { 996 struct bcmgenet_priv *priv = netdev_priv(dev); 997 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 998 u32 reg; 999 1000 if (enable && !priv->clk_eee_enabled) { 1001 clk_prepare_enable(priv->clk_eee); 1002 priv->clk_eee_enabled = true; 1003 } 1004 1005 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1006 if (enable) 1007 reg |= EEE_EN; 1008 else 1009 reg &= ~EEE_EN; 1010 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1011 1012 /* Enable EEE and switch to a 27Mhz clock automatically */ 1013 reg = bcmgenet_readl(priv->base + off); 1014 if (enable) 1015 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1016 else 1017 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1018 bcmgenet_writel(reg, priv->base + off); 1019 1020 /* Do the same for thing for RBUF */ 1021 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1022 if (enable) 1023 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1024 else 1025 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1026 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1027 1028 if (!enable && priv->clk_eee_enabled) { 1029 clk_disable_unprepare(priv->clk_eee); 1030 priv->clk_eee_enabled = false; 1031 } 1032 1033 priv->eee.eee_enabled = enable; 1034 priv->eee.eee_active = enable; 1035 } 1036 1037 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1038 { 1039 struct bcmgenet_priv *priv = netdev_priv(dev); 1040 struct ethtool_eee *p = &priv->eee; 1041 1042 if (GENET_IS_V1(priv)) 1043 return -EOPNOTSUPP; 1044 1045 e->eee_enabled = p->eee_enabled; 1046 e->eee_active = p->eee_active; 1047 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1048 1049 return phy_ethtool_get_eee(priv->phydev, e); 1050 } 1051 1052 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1053 { 1054 struct bcmgenet_priv *priv = netdev_priv(dev); 1055 struct ethtool_eee *p = &priv->eee; 1056 int ret = 0; 1057 1058 if (GENET_IS_V1(priv)) 1059 return -EOPNOTSUPP; 1060 1061 p->eee_enabled = e->eee_enabled; 1062 1063 if (!p->eee_enabled) { 1064 bcmgenet_eee_enable_set(dev, false); 1065 } else { 1066 ret = phy_init_eee(priv->phydev, 0); 1067 if (ret) { 1068 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1069 return ret; 1070 } 1071 1072 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1073 bcmgenet_eee_enable_set(dev, true); 1074 } 1075 1076 return phy_ethtool_set_eee(priv->phydev, e); 1077 } 1078 1079 /* standard ethtool support functions. */ 1080 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1081 .begin = bcmgenet_begin, 1082 .complete = bcmgenet_complete, 1083 .get_strings = bcmgenet_get_strings, 1084 .get_sset_count = bcmgenet_get_sset_count, 1085 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1086 .get_drvinfo = bcmgenet_get_drvinfo, 1087 .get_link = ethtool_op_get_link, 1088 .get_msglevel = bcmgenet_get_msglevel, 1089 .set_msglevel = bcmgenet_set_msglevel, 1090 .get_wol = bcmgenet_get_wol, 1091 .set_wol = bcmgenet_set_wol, 1092 .get_eee = bcmgenet_get_eee, 1093 .set_eee = bcmgenet_set_eee, 1094 .nway_reset = phy_ethtool_nway_reset, 1095 .get_coalesce = bcmgenet_get_coalesce, 1096 .set_coalesce = bcmgenet_set_coalesce, 1097 .get_link_ksettings = bcmgenet_get_link_ksettings, 1098 .set_link_ksettings = bcmgenet_set_link_ksettings, 1099 }; 1100 1101 /* Power down the unimac, based on mode. */ 1102 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1103 enum bcmgenet_power_mode mode) 1104 { 1105 int ret = 0; 1106 u32 reg; 1107 1108 switch (mode) { 1109 case GENET_POWER_CABLE_SENSE: 1110 phy_detach(priv->phydev); 1111 break; 1112 1113 case GENET_POWER_WOL_MAGIC: 1114 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1115 break; 1116 1117 case GENET_POWER_PASSIVE: 1118 /* Power down LED */ 1119 if (priv->hw_params->flags & GENET_HAS_EXT) { 1120 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1121 if (GENET_IS_V5(priv)) 1122 reg |= EXT_PWR_DOWN_PHY_EN | 1123 EXT_PWR_DOWN_PHY_RD | 1124 EXT_PWR_DOWN_PHY_SD | 1125 EXT_PWR_DOWN_PHY_RX | 1126 EXT_PWR_DOWN_PHY_TX | 1127 EXT_IDDQ_GLBL_PWR; 1128 else 1129 reg |= EXT_PWR_DOWN_PHY; 1130 1131 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1132 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1133 1134 bcmgenet_phy_power_set(priv->dev, false); 1135 } 1136 break; 1137 default: 1138 break; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1145 enum bcmgenet_power_mode mode) 1146 { 1147 u32 reg; 1148 1149 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1150 return; 1151 1152 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1153 1154 switch (mode) { 1155 case GENET_POWER_PASSIVE: 1156 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1157 if (GENET_IS_V5(priv)) { 1158 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1159 EXT_PWR_DOWN_PHY_RD | 1160 EXT_PWR_DOWN_PHY_SD | 1161 EXT_PWR_DOWN_PHY_RX | 1162 EXT_PWR_DOWN_PHY_TX | 1163 EXT_IDDQ_GLBL_PWR); 1164 reg |= EXT_PHY_RESET; 1165 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1166 mdelay(1); 1167 1168 reg &= ~EXT_PHY_RESET; 1169 } else { 1170 reg &= ~EXT_PWR_DOWN_PHY; 1171 reg |= EXT_PWR_DN_EN_LD; 1172 } 1173 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1174 bcmgenet_phy_power_set(priv->dev, true); 1175 bcmgenet_mii_reset(priv->dev); 1176 break; 1177 1178 case GENET_POWER_CABLE_SENSE: 1179 /* enable APD */ 1180 if (!GENET_IS_V5(priv)) { 1181 reg |= EXT_PWR_DN_EN_LD; 1182 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1183 } 1184 break; 1185 case GENET_POWER_WOL_MAGIC: 1186 bcmgenet_wol_power_up_cfg(priv, mode); 1187 return; 1188 default: 1189 break; 1190 } 1191 } 1192 1193 /* ioctl handle special commands that are not present in ethtool. */ 1194 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1195 { 1196 struct bcmgenet_priv *priv = netdev_priv(dev); 1197 1198 if (!netif_running(dev)) 1199 return -EINVAL; 1200 1201 if (!priv->phydev) 1202 return -ENODEV; 1203 1204 return phy_mii_ioctl(priv->phydev, rq, cmd); 1205 } 1206 1207 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1208 struct bcmgenet_tx_ring *ring) 1209 { 1210 struct enet_cb *tx_cb_ptr; 1211 1212 tx_cb_ptr = ring->cbs; 1213 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1214 1215 /* Advancing local write pointer */ 1216 if (ring->write_ptr == ring->end_ptr) 1217 ring->write_ptr = ring->cb_ptr; 1218 else 1219 ring->write_ptr++; 1220 1221 return tx_cb_ptr; 1222 } 1223 1224 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1225 struct bcmgenet_tx_ring *ring) 1226 { 1227 struct enet_cb *tx_cb_ptr; 1228 1229 tx_cb_ptr = ring->cbs; 1230 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1231 1232 /* Rewinding local write pointer */ 1233 if (ring->write_ptr == ring->cb_ptr) 1234 ring->write_ptr = ring->end_ptr; 1235 else 1236 ring->write_ptr--; 1237 1238 return tx_cb_ptr; 1239 } 1240 1241 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1242 { 1243 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1244 INTRL2_CPU_MASK_SET); 1245 } 1246 1247 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1248 { 1249 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1250 INTRL2_CPU_MASK_CLEAR); 1251 } 1252 1253 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1254 { 1255 bcmgenet_intrl2_1_writel(ring->priv, 1256 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1257 INTRL2_CPU_MASK_SET); 1258 } 1259 1260 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1261 { 1262 bcmgenet_intrl2_1_writel(ring->priv, 1263 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1264 INTRL2_CPU_MASK_CLEAR); 1265 } 1266 1267 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1268 { 1269 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1270 INTRL2_CPU_MASK_SET); 1271 } 1272 1273 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1274 { 1275 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1276 INTRL2_CPU_MASK_CLEAR); 1277 } 1278 1279 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1280 { 1281 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1282 INTRL2_CPU_MASK_CLEAR); 1283 } 1284 1285 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1286 { 1287 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1288 INTRL2_CPU_MASK_SET); 1289 } 1290 1291 /* Simple helper to free a transmit control block's resources 1292 * Returns an skb when the last transmit control block associated with the 1293 * skb is freed. The skb should be freed by the caller if necessary. 1294 */ 1295 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1296 struct enet_cb *cb) 1297 { 1298 struct sk_buff *skb; 1299 1300 skb = cb->skb; 1301 1302 if (skb) { 1303 cb->skb = NULL; 1304 if (cb == GENET_CB(skb)->first_cb) 1305 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1306 dma_unmap_len(cb, dma_len), 1307 DMA_TO_DEVICE); 1308 else 1309 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1310 dma_unmap_len(cb, dma_len), 1311 DMA_TO_DEVICE); 1312 dma_unmap_addr_set(cb, dma_addr, 0); 1313 1314 if (cb == GENET_CB(skb)->last_cb) 1315 return skb; 1316 1317 } else if (dma_unmap_addr(cb, dma_addr)) { 1318 dma_unmap_page(dev, 1319 dma_unmap_addr(cb, dma_addr), 1320 dma_unmap_len(cb, dma_len), 1321 DMA_TO_DEVICE); 1322 dma_unmap_addr_set(cb, dma_addr, 0); 1323 } 1324 1325 return 0; 1326 } 1327 1328 /* Simple helper to free a receive control block's resources */ 1329 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1330 struct enet_cb *cb) 1331 { 1332 struct sk_buff *skb; 1333 1334 skb = cb->skb; 1335 cb->skb = NULL; 1336 1337 if (dma_unmap_addr(cb, dma_addr)) { 1338 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1339 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1340 dma_unmap_addr_set(cb, dma_addr, 0); 1341 } 1342 1343 return skb; 1344 } 1345 1346 /* Unlocked version of the reclaim routine */ 1347 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1348 struct bcmgenet_tx_ring *ring) 1349 { 1350 struct bcmgenet_priv *priv = netdev_priv(dev); 1351 unsigned int txbds_processed = 0; 1352 unsigned int bytes_compl = 0; 1353 unsigned int pkts_compl = 0; 1354 unsigned int txbds_ready; 1355 unsigned int c_index; 1356 struct sk_buff *skb; 1357 1358 /* Clear status before servicing to reduce spurious interrupts */ 1359 if (ring->index == DESC_INDEX) 1360 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1361 INTRL2_CPU_CLEAR); 1362 else 1363 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1364 INTRL2_CPU_CLEAR); 1365 1366 /* Compute how many buffers are transmitted since last xmit call */ 1367 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1368 & DMA_C_INDEX_MASK; 1369 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1370 1371 netif_dbg(priv, tx_done, dev, 1372 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1373 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1374 1375 /* Reclaim transmitted buffers */ 1376 while (txbds_processed < txbds_ready) { 1377 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1378 &priv->tx_cbs[ring->clean_ptr]); 1379 if (skb) { 1380 pkts_compl++; 1381 bytes_compl += GENET_CB(skb)->bytes_sent; 1382 dev_consume_skb_any(skb); 1383 } 1384 1385 txbds_processed++; 1386 if (likely(ring->clean_ptr < ring->end_ptr)) 1387 ring->clean_ptr++; 1388 else 1389 ring->clean_ptr = ring->cb_ptr; 1390 } 1391 1392 ring->free_bds += txbds_processed; 1393 ring->c_index = c_index; 1394 1395 ring->packets += pkts_compl; 1396 ring->bytes += bytes_compl; 1397 1398 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1399 pkts_compl, bytes_compl); 1400 1401 return txbds_processed; 1402 } 1403 1404 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1405 struct bcmgenet_tx_ring *ring) 1406 { 1407 unsigned int released; 1408 unsigned long flags; 1409 1410 spin_lock_irqsave(&ring->lock, flags); 1411 released = __bcmgenet_tx_reclaim(dev, ring); 1412 spin_unlock_irqrestore(&ring->lock, flags); 1413 1414 return released; 1415 } 1416 1417 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1418 { 1419 struct bcmgenet_tx_ring *ring = 1420 container_of(napi, struct bcmgenet_tx_ring, napi); 1421 unsigned int work_done = 0; 1422 struct netdev_queue *txq; 1423 unsigned long flags; 1424 1425 spin_lock_irqsave(&ring->lock, flags); 1426 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1427 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1428 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1429 netif_tx_wake_queue(txq); 1430 } 1431 spin_unlock_irqrestore(&ring->lock, flags); 1432 1433 if (work_done == 0) { 1434 napi_complete(napi); 1435 ring->int_enable(ring); 1436 1437 return 0; 1438 } 1439 1440 return budget; 1441 } 1442 1443 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1444 { 1445 struct bcmgenet_priv *priv = netdev_priv(dev); 1446 int i; 1447 1448 if (netif_is_multiqueue(dev)) { 1449 for (i = 0; i < priv->hw_params->tx_queues; i++) 1450 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1451 } 1452 1453 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1454 } 1455 1456 /* Reallocate the SKB to put enough headroom in front of it and insert 1457 * the transmit checksum offsets in the descriptors 1458 */ 1459 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev, 1460 struct sk_buff *skb) 1461 { 1462 struct status_64 *status = NULL; 1463 struct sk_buff *new_skb; 1464 u16 offset; 1465 u8 ip_proto; 1466 u16 ip_ver; 1467 u32 tx_csum_info; 1468 1469 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1470 /* If 64 byte status block enabled, must make sure skb has 1471 * enough headroom for us to insert 64B status block. 1472 */ 1473 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1474 dev_kfree_skb(skb); 1475 if (!new_skb) { 1476 dev->stats.tx_dropped++; 1477 return NULL; 1478 } 1479 skb = new_skb; 1480 } 1481 1482 skb_push(skb, sizeof(*status)); 1483 status = (struct status_64 *)skb->data; 1484 1485 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1486 ip_ver = htons(skb->protocol); 1487 switch (ip_ver) { 1488 case ETH_P_IP: 1489 ip_proto = ip_hdr(skb)->protocol; 1490 break; 1491 case ETH_P_IPV6: 1492 ip_proto = ipv6_hdr(skb)->nexthdr; 1493 break; 1494 default: 1495 return skb; 1496 } 1497 1498 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1499 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1500 (offset + skb->csum_offset); 1501 1502 /* Set the length valid bit for TCP and UDP and just set 1503 * the special UDP flag for IPv4, else just set to 0. 1504 */ 1505 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1506 tx_csum_info |= STATUS_TX_CSUM_LV; 1507 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1508 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1509 } else { 1510 tx_csum_info = 0; 1511 } 1512 1513 status->tx_csum_info = tx_csum_info; 1514 } 1515 1516 return skb; 1517 } 1518 1519 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1520 { 1521 struct bcmgenet_priv *priv = netdev_priv(dev); 1522 struct device *kdev = &priv->pdev->dev; 1523 struct bcmgenet_tx_ring *ring = NULL; 1524 struct enet_cb *tx_cb_ptr; 1525 struct netdev_queue *txq; 1526 unsigned long flags = 0; 1527 int nr_frags, index; 1528 dma_addr_t mapping; 1529 unsigned int size; 1530 skb_frag_t *frag; 1531 u32 len_stat; 1532 int ret; 1533 int i; 1534 1535 index = skb_get_queue_mapping(skb); 1536 /* Mapping strategy: 1537 * queue_mapping = 0, unclassified, packet xmited through ring16 1538 * queue_mapping = 1, goes to ring 0. (highest priority queue 1539 * queue_mapping = 2, goes to ring 1. 1540 * queue_mapping = 3, goes to ring 2. 1541 * queue_mapping = 4, goes to ring 3. 1542 */ 1543 if (index == 0) 1544 index = DESC_INDEX; 1545 else 1546 index -= 1; 1547 1548 ring = &priv->tx_rings[index]; 1549 txq = netdev_get_tx_queue(dev, ring->queue); 1550 1551 nr_frags = skb_shinfo(skb)->nr_frags; 1552 1553 spin_lock_irqsave(&ring->lock, flags); 1554 if (ring->free_bds <= (nr_frags + 1)) { 1555 if (!netif_tx_queue_stopped(txq)) { 1556 netif_tx_stop_queue(txq); 1557 netdev_err(dev, 1558 "%s: tx ring %d full when queue %d awake\n", 1559 __func__, index, ring->queue); 1560 } 1561 ret = NETDEV_TX_BUSY; 1562 goto out; 1563 } 1564 1565 if (skb_padto(skb, ETH_ZLEN)) { 1566 ret = NETDEV_TX_OK; 1567 goto out; 1568 } 1569 1570 /* Retain how many bytes will be sent on the wire, without TSB inserted 1571 * by transmit checksum offload 1572 */ 1573 GENET_CB(skb)->bytes_sent = skb->len; 1574 1575 /* set the SKB transmit checksum */ 1576 if (priv->desc_64b_en) { 1577 skb = bcmgenet_put_tx_csum(dev, skb); 1578 if (!skb) { 1579 ret = NETDEV_TX_OK; 1580 goto out; 1581 } 1582 } 1583 1584 for (i = 0; i <= nr_frags; i++) { 1585 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1586 1587 if (unlikely(!tx_cb_ptr)) 1588 BUG(); 1589 1590 if (!i) { 1591 /* Transmit single SKB or head of fragment list */ 1592 GENET_CB(skb)->first_cb = tx_cb_ptr; 1593 size = skb_headlen(skb); 1594 mapping = dma_map_single(kdev, skb->data, size, 1595 DMA_TO_DEVICE); 1596 } else { 1597 /* xmit fragment */ 1598 frag = &skb_shinfo(skb)->frags[i - 1]; 1599 size = skb_frag_size(frag); 1600 mapping = skb_frag_dma_map(kdev, frag, 0, size, 1601 DMA_TO_DEVICE); 1602 } 1603 1604 ret = dma_mapping_error(kdev, mapping); 1605 if (ret) { 1606 priv->mib.tx_dma_failed++; 1607 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1608 ret = NETDEV_TX_OK; 1609 goto out_unmap_frags; 1610 } 1611 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1612 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 1613 1614 tx_cb_ptr->skb = skb; 1615 1616 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 1617 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 1618 1619 if (!i) { 1620 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 1621 if (skb->ip_summed == CHECKSUM_PARTIAL) 1622 len_stat |= DMA_TX_DO_CSUM; 1623 } 1624 if (i == nr_frags) 1625 len_stat |= DMA_EOP; 1626 1627 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 1628 } 1629 1630 GENET_CB(skb)->last_cb = tx_cb_ptr; 1631 skb_tx_timestamp(skb); 1632 1633 /* Decrement total BD count and advance our write pointer */ 1634 ring->free_bds -= nr_frags + 1; 1635 ring->prod_index += nr_frags + 1; 1636 ring->prod_index &= DMA_P_INDEX_MASK; 1637 1638 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1639 1640 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1641 netif_tx_stop_queue(txq); 1642 1643 if (!skb->xmit_more || netif_xmit_stopped(txq)) 1644 /* Packets are ready, update producer index */ 1645 bcmgenet_tdma_ring_writel(priv, ring->index, 1646 ring->prod_index, TDMA_PROD_INDEX); 1647 out: 1648 spin_unlock_irqrestore(&ring->lock, flags); 1649 1650 return ret; 1651 1652 out_unmap_frags: 1653 /* Back up for failed control block mapping */ 1654 bcmgenet_put_txcb(priv, ring); 1655 1656 /* Unmap successfully mapped control blocks */ 1657 while (i-- > 0) { 1658 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 1659 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 1660 } 1661 1662 dev_kfree_skb(skb); 1663 goto out; 1664 } 1665 1666 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1667 struct enet_cb *cb) 1668 { 1669 struct device *kdev = &priv->pdev->dev; 1670 struct sk_buff *skb; 1671 struct sk_buff *rx_skb; 1672 dma_addr_t mapping; 1673 1674 /* Allocate a new Rx skb */ 1675 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1676 if (!skb) { 1677 priv->mib.alloc_rx_buff_failed++; 1678 netif_err(priv, rx_err, priv->dev, 1679 "%s: Rx skb allocation failed\n", __func__); 1680 return NULL; 1681 } 1682 1683 /* DMA-map the new Rx skb */ 1684 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1685 DMA_FROM_DEVICE); 1686 if (dma_mapping_error(kdev, mapping)) { 1687 priv->mib.rx_dma_failed++; 1688 dev_kfree_skb_any(skb); 1689 netif_err(priv, rx_err, priv->dev, 1690 "%s: Rx skb DMA mapping failed\n", __func__); 1691 return NULL; 1692 } 1693 1694 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1695 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 1696 1697 /* Put the new Rx skb on the ring */ 1698 cb->skb = skb; 1699 dma_unmap_addr_set(cb, dma_addr, mapping); 1700 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 1701 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1702 1703 /* Return the current Rx skb to caller */ 1704 return rx_skb; 1705 } 1706 1707 /* bcmgenet_desc_rx - descriptor based rx process. 1708 * this could be called from bottom half, or from NAPI polling method. 1709 */ 1710 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1711 unsigned int budget) 1712 { 1713 struct bcmgenet_priv *priv = ring->priv; 1714 struct net_device *dev = priv->dev; 1715 struct enet_cb *cb; 1716 struct sk_buff *skb; 1717 u32 dma_length_status; 1718 unsigned long dma_flag; 1719 int len; 1720 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1721 unsigned int p_index, mask; 1722 unsigned int discards; 1723 unsigned int chksum_ok = 0; 1724 1725 /* Clear status before servicing to reduce spurious interrupts */ 1726 if (ring->index == DESC_INDEX) { 1727 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1728 INTRL2_CPU_CLEAR); 1729 } else { 1730 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1731 bcmgenet_intrl2_1_writel(priv, 1732 mask, 1733 INTRL2_CPU_CLEAR); 1734 } 1735 1736 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1737 1738 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1739 DMA_P_INDEX_DISCARD_CNT_MASK; 1740 if (discards > ring->old_discards) { 1741 discards = discards - ring->old_discards; 1742 ring->errors += discards; 1743 ring->old_discards += discards; 1744 1745 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1746 if (ring->old_discards >= 0xC000) { 1747 ring->old_discards = 0; 1748 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1749 RDMA_PROD_INDEX); 1750 } 1751 } 1752 1753 p_index &= DMA_P_INDEX_MASK; 1754 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1755 1756 netif_dbg(priv, rx_status, dev, 1757 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1758 1759 while ((rxpktprocessed < rxpkttoprocess) && 1760 (rxpktprocessed < budget)) { 1761 cb = &priv->rx_cbs[ring->read_ptr]; 1762 skb = bcmgenet_rx_refill(priv, cb); 1763 1764 if (unlikely(!skb)) { 1765 ring->dropped++; 1766 goto next; 1767 } 1768 1769 if (!priv->desc_64b_en) { 1770 dma_length_status = 1771 dmadesc_get_length_status(priv, cb->bd_addr); 1772 } else { 1773 struct status_64 *status; 1774 1775 status = (struct status_64 *)skb->data; 1776 dma_length_status = status->length_status; 1777 } 1778 1779 /* DMA flags and length are still valid no matter how 1780 * we got the Receive Status Vector (64B RSB or register) 1781 */ 1782 dma_flag = dma_length_status & 0xffff; 1783 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1784 1785 netif_dbg(priv, rx_status, dev, 1786 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1787 __func__, p_index, ring->c_index, 1788 ring->read_ptr, dma_length_status); 1789 1790 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1791 netif_err(priv, rx_status, dev, 1792 "dropping fragmented packet!\n"); 1793 ring->errors++; 1794 dev_kfree_skb_any(skb); 1795 goto next; 1796 } 1797 1798 /* report errors */ 1799 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1800 DMA_RX_OV | 1801 DMA_RX_NO | 1802 DMA_RX_LG | 1803 DMA_RX_RXER))) { 1804 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1805 (unsigned int)dma_flag); 1806 if (dma_flag & DMA_RX_CRC_ERROR) 1807 dev->stats.rx_crc_errors++; 1808 if (dma_flag & DMA_RX_OV) 1809 dev->stats.rx_over_errors++; 1810 if (dma_flag & DMA_RX_NO) 1811 dev->stats.rx_frame_errors++; 1812 if (dma_flag & DMA_RX_LG) 1813 dev->stats.rx_length_errors++; 1814 dev->stats.rx_errors++; 1815 dev_kfree_skb_any(skb); 1816 goto next; 1817 } /* error packet */ 1818 1819 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && 1820 priv->desc_rxchk_en; 1821 1822 skb_put(skb, len); 1823 if (priv->desc_64b_en) { 1824 skb_pull(skb, 64); 1825 len -= 64; 1826 } 1827 1828 if (likely(chksum_ok)) 1829 skb->ip_summed = CHECKSUM_UNNECESSARY; 1830 1831 /* remove hardware 2bytes added for IP alignment */ 1832 skb_pull(skb, 2); 1833 len -= 2; 1834 1835 if (priv->crc_fwd_en) { 1836 skb_trim(skb, len - ETH_FCS_LEN); 1837 len -= ETH_FCS_LEN; 1838 } 1839 1840 /*Finish setting up the received SKB and send it to the kernel*/ 1841 skb->protocol = eth_type_trans(skb, priv->dev); 1842 ring->packets++; 1843 ring->bytes += len; 1844 if (dma_flag & DMA_RX_MULT) 1845 dev->stats.multicast++; 1846 1847 /* Notify kernel */ 1848 napi_gro_receive(&ring->napi, skb); 1849 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1850 1851 next: 1852 rxpktprocessed++; 1853 if (likely(ring->read_ptr < ring->end_ptr)) 1854 ring->read_ptr++; 1855 else 1856 ring->read_ptr = ring->cb_ptr; 1857 1858 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1859 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1860 } 1861 1862 return rxpktprocessed; 1863 } 1864 1865 /* Rx NAPI polling method */ 1866 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1867 { 1868 struct bcmgenet_rx_ring *ring = container_of(napi, 1869 struct bcmgenet_rx_ring, napi); 1870 unsigned int work_done; 1871 1872 work_done = bcmgenet_desc_rx(ring, budget); 1873 1874 if (work_done < budget) { 1875 napi_complete_done(napi, work_done); 1876 ring->int_enable(ring); 1877 } 1878 1879 return work_done; 1880 } 1881 1882 /* Assign skb to RX DMA descriptor. */ 1883 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1884 struct bcmgenet_rx_ring *ring) 1885 { 1886 struct enet_cb *cb; 1887 struct sk_buff *skb; 1888 int i; 1889 1890 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1891 1892 /* loop here for each buffer needing assign */ 1893 for (i = 0; i < ring->size; i++) { 1894 cb = ring->cbs + i; 1895 skb = bcmgenet_rx_refill(priv, cb); 1896 if (skb) 1897 dev_consume_skb_any(skb); 1898 if (!cb->skb) 1899 return -ENOMEM; 1900 } 1901 1902 return 0; 1903 } 1904 1905 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1906 { 1907 struct sk_buff *skb; 1908 struct enet_cb *cb; 1909 int i; 1910 1911 for (i = 0; i < priv->num_rx_bds; i++) { 1912 cb = &priv->rx_cbs[i]; 1913 1914 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 1915 if (skb) 1916 dev_consume_skb_any(skb); 1917 } 1918 } 1919 1920 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1921 { 1922 u32 reg; 1923 1924 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1925 if (enable) 1926 reg |= mask; 1927 else 1928 reg &= ~mask; 1929 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1930 1931 /* UniMAC stops on a packet boundary, wait for a full-size packet 1932 * to be processed 1933 */ 1934 if (enable == 0) 1935 usleep_range(1000, 2000); 1936 } 1937 1938 static int reset_umac(struct bcmgenet_priv *priv) 1939 { 1940 struct device *kdev = &priv->pdev->dev; 1941 unsigned int timeout = 0; 1942 u32 reg; 1943 1944 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1945 bcmgenet_rbuf_ctrl_set(priv, 0); 1946 udelay(10); 1947 1948 /* disable MAC while updating its registers */ 1949 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1950 1951 /* issue soft reset, wait for it to complete */ 1952 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 1953 while (timeout++ < 1000) { 1954 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1955 if (!(reg & CMD_SW_RESET)) 1956 return 0; 1957 1958 udelay(1); 1959 } 1960 1961 if (timeout == 1000) { 1962 dev_err(kdev, 1963 "timeout waiting for MAC to come out of reset\n"); 1964 return -ETIMEDOUT; 1965 } 1966 1967 return 0; 1968 } 1969 1970 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1971 { 1972 /* Mask all interrupts.*/ 1973 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1974 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1975 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1976 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1977 } 1978 1979 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 1980 { 1981 u32 int0_enable = 0; 1982 1983 /* Monitor cable plug/unplugged event for internal PHY, external PHY 1984 * and MoCA PHY 1985 */ 1986 if (priv->internal_phy) { 1987 int0_enable |= UMAC_IRQ_LINK_EVENT; 1988 } else if (priv->ext_phy) { 1989 int0_enable |= UMAC_IRQ_LINK_EVENT; 1990 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1991 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 1992 int0_enable |= UMAC_IRQ_LINK_EVENT; 1993 } 1994 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 1995 } 1996 1997 static int init_umac(struct bcmgenet_priv *priv) 1998 { 1999 struct device *kdev = &priv->pdev->dev; 2000 int ret; 2001 u32 reg; 2002 u32 int0_enable = 0; 2003 2004 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2005 2006 ret = reset_umac(priv); 2007 if (ret) 2008 return ret; 2009 2010 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 2011 /* clear tx/rx counter */ 2012 bcmgenet_umac_writel(priv, 2013 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2014 UMAC_MIB_CTRL); 2015 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2016 2017 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2018 2019 /* init rx registers, enable ip header optimization */ 2020 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2021 reg |= RBUF_ALIGN_2B; 2022 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2023 2024 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2025 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2026 2027 bcmgenet_intr_disable(priv); 2028 2029 /* Configure backpressure vectors for MoCA */ 2030 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2031 reg = bcmgenet_bp_mc_get(priv); 2032 reg |= BIT(priv->hw_params->bp_in_en_shift); 2033 2034 /* bp_mask: back pressure mask */ 2035 if (netif_is_multiqueue(priv->dev)) 2036 reg |= priv->hw_params->bp_in_mask; 2037 else 2038 reg &= ~priv->hw_params->bp_in_mask; 2039 bcmgenet_bp_mc_set(priv, reg); 2040 } 2041 2042 /* Enable MDIO interrupts on GENET v3+ */ 2043 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2044 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2045 2046 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2047 2048 dev_dbg(kdev, "done init umac\n"); 2049 2050 return 0; 2051 } 2052 2053 /* Initialize a Tx ring along with corresponding hardware registers */ 2054 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2055 unsigned int index, unsigned int size, 2056 unsigned int start_ptr, unsigned int end_ptr) 2057 { 2058 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2059 u32 words_per_bd = WORDS_PER_BD(priv); 2060 u32 flow_period_val = 0; 2061 2062 spin_lock_init(&ring->lock); 2063 ring->priv = priv; 2064 ring->index = index; 2065 if (index == DESC_INDEX) { 2066 ring->queue = 0; 2067 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2068 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2069 } else { 2070 ring->queue = index + 1; 2071 ring->int_enable = bcmgenet_tx_ring_int_enable; 2072 ring->int_disable = bcmgenet_tx_ring_int_disable; 2073 } 2074 ring->cbs = priv->tx_cbs + start_ptr; 2075 ring->size = size; 2076 ring->clean_ptr = start_ptr; 2077 ring->c_index = 0; 2078 ring->free_bds = size; 2079 ring->write_ptr = start_ptr; 2080 ring->cb_ptr = start_ptr; 2081 ring->end_ptr = end_ptr - 1; 2082 ring->prod_index = 0; 2083 2084 /* Set flow period for ring != 16 */ 2085 if (index != DESC_INDEX) 2086 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2087 2088 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2089 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2090 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2091 /* Disable rate control for now */ 2092 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2093 TDMA_FLOW_PERIOD); 2094 bcmgenet_tdma_ring_writel(priv, index, 2095 ((size << DMA_RING_SIZE_SHIFT) | 2096 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2097 2098 /* Set start and end address, read and write pointers */ 2099 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2100 DMA_START_ADDR); 2101 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2102 TDMA_READ_PTR); 2103 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2104 TDMA_WRITE_PTR); 2105 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2106 DMA_END_ADDR); 2107 } 2108 2109 /* Initialize a RDMA ring */ 2110 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2111 unsigned int index, unsigned int size, 2112 unsigned int start_ptr, unsigned int end_ptr) 2113 { 2114 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2115 u32 words_per_bd = WORDS_PER_BD(priv); 2116 int ret; 2117 2118 ring->priv = priv; 2119 ring->index = index; 2120 if (index == DESC_INDEX) { 2121 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2122 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2123 } else { 2124 ring->int_enable = bcmgenet_rx_ring_int_enable; 2125 ring->int_disable = bcmgenet_rx_ring_int_disable; 2126 } 2127 ring->cbs = priv->rx_cbs + start_ptr; 2128 ring->size = size; 2129 ring->c_index = 0; 2130 ring->read_ptr = start_ptr; 2131 ring->cb_ptr = start_ptr; 2132 ring->end_ptr = end_ptr - 1; 2133 2134 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2135 if (ret) 2136 return ret; 2137 2138 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2139 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2140 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2141 bcmgenet_rdma_ring_writel(priv, index, 2142 ((size << DMA_RING_SIZE_SHIFT) | 2143 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2144 bcmgenet_rdma_ring_writel(priv, index, 2145 (DMA_FC_THRESH_LO << 2146 DMA_XOFF_THRESHOLD_SHIFT) | 2147 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2148 2149 /* Set start and end address, read and write pointers */ 2150 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2151 DMA_START_ADDR); 2152 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2153 RDMA_READ_PTR); 2154 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2155 RDMA_WRITE_PTR); 2156 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2157 DMA_END_ADDR); 2158 2159 return ret; 2160 } 2161 2162 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv) 2163 { 2164 unsigned int i; 2165 struct bcmgenet_tx_ring *ring; 2166 2167 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2168 ring = &priv->tx_rings[i]; 2169 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 2170 } 2171 2172 ring = &priv->tx_rings[DESC_INDEX]; 2173 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64); 2174 } 2175 2176 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2177 { 2178 unsigned int i; 2179 u32 int0_enable = UMAC_IRQ_TXDMA_DONE; 2180 u32 int1_enable = 0; 2181 struct bcmgenet_tx_ring *ring; 2182 2183 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2184 ring = &priv->tx_rings[i]; 2185 napi_enable(&ring->napi); 2186 int1_enable |= (1 << i); 2187 } 2188 2189 ring = &priv->tx_rings[DESC_INDEX]; 2190 napi_enable(&ring->napi); 2191 2192 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2193 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2194 } 2195 2196 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2197 { 2198 unsigned int i; 2199 u32 int0_disable = UMAC_IRQ_TXDMA_DONE; 2200 u32 int1_disable = 0xffff; 2201 struct bcmgenet_tx_ring *ring; 2202 2203 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); 2204 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); 2205 2206 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2207 ring = &priv->tx_rings[i]; 2208 napi_disable(&ring->napi); 2209 } 2210 2211 ring = &priv->tx_rings[DESC_INDEX]; 2212 napi_disable(&ring->napi); 2213 } 2214 2215 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2216 { 2217 unsigned int i; 2218 struct bcmgenet_tx_ring *ring; 2219 2220 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2221 ring = &priv->tx_rings[i]; 2222 netif_napi_del(&ring->napi); 2223 } 2224 2225 ring = &priv->tx_rings[DESC_INDEX]; 2226 netif_napi_del(&ring->napi); 2227 } 2228 2229 /* Initialize Tx queues 2230 * 2231 * Queues 0-3 are priority-based, each one has 32 descriptors, 2232 * with queue 0 being the highest priority queue. 2233 * 2234 * Queue 16 is the default Tx queue with 2235 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2236 * 2237 * The transmit control block pool is then partitioned as follows: 2238 * - Tx queue 0 uses tx_cbs[0..31] 2239 * - Tx queue 1 uses tx_cbs[32..63] 2240 * - Tx queue 2 uses tx_cbs[64..95] 2241 * - Tx queue 3 uses tx_cbs[96..127] 2242 * - Tx queue 16 uses tx_cbs[128..255] 2243 */ 2244 static void bcmgenet_init_tx_queues(struct net_device *dev) 2245 { 2246 struct bcmgenet_priv *priv = netdev_priv(dev); 2247 u32 i, dma_enable; 2248 u32 dma_ctrl, ring_cfg; 2249 u32 dma_priority[3] = {0, 0, 0}; 2250 2251 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2252 dma_enable = dma_ctrl & DMA_EN; 2253 dma_ctrl &= ~DMA_EN; 2254 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2255 2256 dma_ctrl = 0; 2257 ring_cfg = 0; 2258 2259 /* Enable strict priority arbiter mode */ 2260 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2261 2262 /* Initialize Tx priority queues */ 2263 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2264 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2265 i * priv->hw_params->tx_bds_per_q, 2266 (i + 1) * priv->hw_params->tx_bds_per_q); 2267 ring_cfg |= (1 << i); 2268 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2269 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2270 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2271 } 2272 2273 /* Initialize Tx default queue 16 */ 2274 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2275 priv->hw_params->tx_queues * 2276 priv->hw_params->tx_bds_per_q, 2277 TOTAL_DESC); 2278 ring_cfg |= (1 << DESC_INDEX); 2279 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2280 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2281 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2282 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2283 2284 /* Set Tx queue priorities */ 2285 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2286 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2287 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2288 2289 /* Initialize Tx NAPI */ 2290 bcmgenet_init_tx_napi(priv); 2291 2292 /* Enable Tx queues */ 2293 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2294 2295 /* Enable Tx DMA */ 2296 if (dma_enable) 2297 dma_ctrl |= DMA_EN; 2298 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2299 } 2300 2301 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv) 2302 { 2303 unsigned int i; 2304 struct bcmgenet_rx_ring *ring; 2305 2306 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2307 ring = &priv->rx_rings[i]; 2308 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2309 } 2310 2311 ring = &priv->rx_rings[DESC_INDEX]; 2312 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64); 2313 } 2314 2315 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2316 { 2317 unsigned int i; 2318 u32 int0_enable = UMAC_IRQ_RXDMA_DONE; 2319 u32 int1_enable = 0; 2320 struct bcmgenet_rx_ring *ring; 2321 2322 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2323 ring = &priv->rx_rings[i]; 2324 napi_enable(&ring->napi); 2325 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i)); 2326 } 2327 2328 ring = &priv->rx_rings[DESC_INDEX]; 2329 napi_enable(&ring->napi); 2330 2331 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2332 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 2333 } 2334 2335 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2336 { 2337 unsigned int i; 2338 u32 int0_disable = UMAC_IRQ_RXDMA_DONE; 2339 u32 int1_disable = 0xffff << UMAC_IRQ1_RX_INTR_SHIFT; 2340 struct bcmgenet_rx_ring *ring; 2341 2342 bcmgenet_intrl2_0_writel(priv, int0_disable, INTRL2_CPU_MASK_SET); 2343 bcmgenet_intrl2_1_writel(priv, int1_disable, INTRL2_CPU_MASK_SET); 2344 2345 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2346 ring = &priv->rx_rings[i]; 2347 napi_disable(&ring->napi); 2348 } 2349 2350 ring = &priv->rx_rings[DESC_INDEX]; 2351 napi_disable(&ring->napi); 2352 } 2353 2354 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2355 { 2356 unsigned int i; 2357 struct bcmgenet_rx_ring *ring; 2358 2359 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2360 ring = &priv->rx_rings[i]; 2361 netif_napi_del(&ring->napi); 2362 } 2363 2364 ring = &priv->rx_rings[DESC_INDEX]; 2365 netif_napi_del(&ring->napi); 2366 } 2367 2368 /* Initialize Rx queues 2369 * 2370 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2371 * used to direct traffic to these queues. 2372 * 2373 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2374 */ 2375 static int bcmgenet_init_rx_queues(struct net_device *dev) 2376 { 2377 struct bcmgenet_priv *priv = netdev_priv(dev); 2378 u32 i; 2379 u32 dma_enable; 2380 u32 dma_ctrl; 2381 u32 ring_cfg; 2382 int ret; 2383 2384 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2385 dma_enable = dma_ctrl & DMA_EN; 2386 dma_ctrl &= ~DMA_EN; 2387 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2388 2389 dma_ctrl = 0; 2390 ring_cfg = 0; 2391 2392 /* Initialize Rx priority queues */ 2393 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2394 ret = bcmgenet_init_rx_ring(priv, i, 2395 priv->hw_params->rx_bds_per_q, 2396 i * priv->hw_params->rx_bds_per_q, 2397 (i + 1) * 2398 priv->hw_params->rx_bds_per_q); 2399 if (ret) 2400 return ret; 2401 2402 ring_cfg |= (1 << i); 2403 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2404 } 2405 2406 /* Initialize Rx default queue 16 */ 2407 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2408 priv->hw_params->rx_queues * 2409 priv->hw_params->rx_bds_per_q, 2410 TOTAL_DESC); 2411 if (ret) 2412 return ret; 2413 2414 ring_cfg |= (1 << DESC_INDEX); 2415 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2416 2417 /* Initialize Rx NAPI */ 2418 bcmgenet_init_rx_napi(priv); 2419 2420 /* Enable rings */ 2421 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2422 2423 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2424 if (dma_enable) 2425 dma_ctrl |= DMA_EN; 2426 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2427 2428 return 0; 2429 } 2430 2431 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2432 { 2433 int ret = 0; 2434 int timeout = 0; 2435 u32 reg; 2436 u32 dma_ctrl; 2437 int i; 2438 2439 /* Disable TDMA to stop add more frames in TX DMA */ 2440 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2441 reg &= ~DMA_EN; 2442 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2443 2444 /* Check TDMA status register to confirm TDMA is disabled */ 2445 while (timeout++ < DMA_TIMEOUT_VAL) { 2446 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2447 if (reg & DMA_DISABLED) 2448 break; 2449 2450 udelay(1); 2451 } 2452 2453 if (timeout == DMA_TIMEOUT_VAL) { 2454 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2455 ret = -ETIMEDOUT; 2456 } 2457 2458 /* Wait 10ms for packet drain in both tx and rx dma */ 2459 usleep_range(10000, 20000); 2460 2461 /* Disable RDMA */ 2462 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2463 reg &= ~DMA_EN; 2464 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2465 2466 timeout = 0; 2467 /* Check RDMA status register to confirm RDMA is disabled */ 2468 while (timeout++ < DMA_TIMEOUT_VAL) { 2469 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2470 if (reg & DMA_DISABLED) 2471 break; 2472 2473 udelay(1); 2474 } 2475 2476 if (timeout == DMA_TIMEOUT_VAL) { 2477 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2478 ret = -ETIMEDOUT; 2479 } 2480 2481 dma_ctrl = 0; 2482 for (i = 0; i < priv->hw_params->rx_queues; i++) 2483 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2484 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2485 reg &= ~dma_ctrl; 2486 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2487 2488 dma_ctrl = 0; 2489 for (i = 0; i < priv->hw_params->tx_queues; i++) 2490 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2491 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2492 reg &= ~dma_ctrl; 2493 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2494 2495 return ret; 2496 } 2497 2498 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2499 { 2500 struct netdev_queue *txq; 2501 struct sk_buff *skb; 2502 struct enet_cb *cb; 2503 int i; 2504 2505 bcmgenet_fini_rx_napi(priv); 2506 bcmgenet_fini_tx_napi(priv); 2507 2508 /* disable DMA */ 2509 bcmgenet_dma_teardown(priv); 2510 2511 for (i = 0; i < priv->num_tx_bds; i++) { 2512 cb = priv->tx_cbs + i; 2513 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, cb); 2514 if (skb) 2515 dev_kfree_skb(skb); 2516 } 2517 2518 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2519 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2520 netdev_tx_reset_queue(txq); 2521 } 2522 2523 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2524 netdev_tx_reset_queue(txq); 2525 2526 bcmgenet_free_rx_buffers(priv); 2527 kfree(priv->rx_cbs); 2528 kfree(priv->tx_cbs); 2529 } 2530 2531 /* init_edma: Initialize DMA control register */ 2532 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2533 { 2534 int ret; 2535 unsigned int i; 2536 struct enet_cb *cb; 2537 2538 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2539 2540 /* Initialize common Rx ring structures */ 2541 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2542 priv->num_rx_bds = TOTAL_DESC; 2543 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2544 GFP_KERNEL); 2545 if (!priv->rx_cbs) 2546 return -ENOMEM; 2547 2548 for (i = 0; i < priv->num_rx_bds; i++) { 2549 cb = priv->rx_cbs + i; 2550 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2551 } 2552 2553 /* Initialize common TX ring structures */ 2554 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2555 priv->num_tx_bds = TOTAL_DESC; 2556 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2557 GFP_KERNEL); 2558 if (!priv->tx_cbs) { 2559 kfree(priv->rx_cbs); 2560 return -ENOMEM; 2561 } 2562 2563 for (i = 0; i < priv->num_tx_bds; i++) { 2564 cb = priv->tx_cbs + i; 2565 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2566 } 2567 2568 /* Init rDma */ 2569 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2570 2571 /* Initialize Rx queues */ 2572 ret = bcmgenet_init_rx_queues(priv->dev); 2573 if (ret) { 2574 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2575 bcmgenet_free_rx_buffers(priv); 2576 kfree(priv->rx_cbs); 2577 kfree(priv->tx_cbs); 2578 return ret; 2579 } 2580 2581 /* Init tDma */ 2582 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 2583 2584 /* Initialize Tx queues */ 2585 bcmgenet_init_tx_queues(priv->dev); 2586 2587 return 0; 2588 } 2589 2590 /* Interrupt bottom half */ 2591 static void bcmgenet_irq_task(struct work_struct *work) 2592 { 2593 unsigned long flags; 2594 unsigned int status; 2595 struct bcmgenet_priv *priv = container_of( 2596 work, struct bcmgenet_priv, bcmgenet_irq_work); 2597 2598 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2599 2600 spin_lock_irqsave(&priv->lock, flags); 2601 status = priv->irq0_stat; 2602 priv->irq0_stat = 0; 2603 spin_unlock_irqrestore(&priv->lock, flags); 2604 2605 if (status & UMAC_IRQ_MPD_R) { 2606 netif_dbg(priv, wol, priv->dev, 2607 "magic packet detected, waking up\n"); 2608 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 2609 } 2610 2611 /* Link UP/DOWN event */ 2612 if (status & UMAC_IRQ_LINK_EVENT) 2613 phy_mac_interrupt(priv->phydev, 2614 !!(status & UMAC_IRQ_LINK_UP)); 2615 } 2616 2617 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2618 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2619 { 2620 struct bcmgenet_priv *priv = dev_id; 2621 struct bcmgenet_rx_ring *rx_ring; 2622 struct bcmgenet_tx_ring *tx_ring; 2623 unsigned int index, status; 2624 2625 /* Read irq status */ 2626 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2627 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2628 2629 /* clear interrupts */ 2630 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2631 2632 netif_dbg(priv, intr, priv->dev, 2633 "%s: IRQ=0x%x\n", __func__, status); 2634 2635 /* Check Rx priority queue interrupts */ 2636 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2637 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2638 continue; 2639 2640 rx_ring = &priv->rx_rings[index]; 2641 2642 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2643 rx_ring->int_disable(rx_ring); 2644 __napi_schedule_irqoff(&rx_ring->napi); 2645 } 2646 } 2647 2648 /* Check Tx priority queue interrupts */ 2649 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2650 if (!(status & BIT(index))) 2651 continue; 2652 2653 tx_ring = &priv->tx_rings[index]; 2654 2655 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2656 tx_ring->int_disable(tx_ring); 2657 __napi_schedule_irqoff(&tx_ring->napi); 2658 } 2659 } 2660 2661 return IRQ_HANDLED; 2662 } 2663 2664 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2665 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2666 { 2667 struct bcmgenet_priv *priv = dev_id; 2668 struct bcmgenet_rx_ring *rx_ring; 2669 struct bcmgenet_tx_ring *tx_ring; 2670 unsigned int status; 2671 unsigned long flags; 2672 2673 /* Read irq status */ 2674 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2675 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2676 2677 /* clear interrupts */ 2678 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2679 2680 netif_dbg(priv, intr, priv->dev, 2681 "IRQ=0x%x\n", status); 2682 2683 if (status & UMAC_IRQ_RXDMA_DONE) { 2684 rx_ring = &priv->rx_rings[DESC_INDEX]; 2685 2686 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2687 rx_ring->int_disable(rx_ring); 2688 __napi_schedule_irqoff(&rx_ring->napi); 2689 } 2690 } 2691 2692 if (status & UMAC_IRQ_TXDMA_DONE) { 2693 tx_ring = &priv->tx_rings[DESC_INDEX]; 2694 2695 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2696 tx_ring->int_disable(tx_ring); 2697 __napi_schedule_irqoff(&tx_ring->napi); 2698 } 2699 } 2700 2701 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | 2702 UMAC_IRQ_PHY_DET_F | 2703 UMAC_IRQ_LINK_EVENT | 2704 UMAC_IRQ_HFB_SM | 2705 UMAC_IRQ_HFB_MM)) { 2706 /* all other interested interrupts handled in bottom half */ 2707 schedule_work(&priv->bcmgenet_irq_work); 2708 } 2709 2710 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2711 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2712 wake_up(&priv->wq); 2713 } 2714 2715 /* all other interested interrupts handled in bottom half */ 2716 status &= (UMAC_IRQ_LINK_EVENT | 2717 UMAC_IRQ_MPD_R); 2718 if (status) { 2719 /* Save irq status for bottom-half processing. */ 2720 spin_lock_irqsave(&priv->lock, flags); 2721 priv->irq0_stat |= status; 2722 spin_unlock_irqrestore(&priv->lock, flags); 2723 2724 schedule_work(&priv->bcmgenet_irq_work); 2725 } 2726 2727 return IRQ_HANDLED; 2728 } 2729 2730 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2731 { 2732 struct bcmgenet_priv *priv = dev_id; 2733 2734 pm_wakeup_event(&priv->pdev->dev, 0); 2735 2736 return IRQ_HANDLED; 2737 } 2738 2739 #ifdef CONFIG_NET_POLL_CONTROLLER 2740 static void bcmgenet_poll_controller(struct net_device *dev) 2741 { 2742 struct bcmgenet_priv *priv = netdev_priv(dev); 2743 2744 /* Invoke the main RX/TX interrupt handler */ 2745 disable_irq(priv->irq0); 2746 bcmgenet_isr0(priv->irq0, priv); 2747 enable_irq(priv->irq0); 2748 2749 /* And the interrupt handler for RX/TX priority queues */ 2750 disable_irq(priv->irq1); 2751 bcmgenet_isr1(priv->irq1, priv); 2752 enable_irq(priv->irq1); 2753 } 2754 #endif 2755 2756 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2757 { 2758 u32 reg; 2759 2760 reg = bcmgenet_rbuf_ctrl_get(priv); 2761 reg |= BIT(1); 2762 bcmgenet_rbuf_ctrl_set(priv, reg); 2763 udelay(10); 2764 2765 reg &= ~BIT(1); 2766 bcmgenet_rbuf_ctrl_set(priv, reg); 2767 udelay(10); 2768 } 2769 2770 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2771 unsigned char *addr) 2772 { 2773 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2774 (addr[2] << 8) | addr[3], UMAC_MAC0); 2775 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2776 } 2777 2778 /* Returns a reusable dma control register value */ 2779 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2780 { 2781 u32 reg; 2782 u32 dma_ctrl; 2783 2784 /* disable DMA */ 2785 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2786 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2787 reg &= ~dma_ctrl; 2788 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2789 2790 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2791 reg &= ~dma_ctrl; 2792 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2793 2794 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2795 udelay(10); 2796 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2797 2798 return dma_ctrl; 2799 } 2800 2801 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2802 { 2803 u32 reg; 2804 2805 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2806 reg |= dma_ctrl; 2807 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2808 2809 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2810 reg |= dma_ctrl; 2811 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2812 } 2813 2814 /* bcmgenet_hfb_clear 2815 * 2816 * Clear Hardware Filter Block and disable all filtering. 2817 */ 2818 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2819 { 2820 u32 i; 2821 2822 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2823 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2824 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2825 2826 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2827 bcmgenet_rdma_writel(priv, 0x0, i); 2828 2829 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2830 bcmgenet_hfb_reg_writel(priv, 0x0, 2831 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2832 2833 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2834 priv->hw_params->hfb_filter_size; i++) 2835 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2836 } 2837 2838 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2839 { 2840 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2841 return; 2842 2843 bcmgenet_hfb_clear(priv); 2844 } 2845 2846 static void bcmgenet_netif_start(struct net_device *dev) 2847 { 2848 struct bcmgenet_priv *priv = netdev_priv(dev); 2849 2850 /* Start the network engine */ 2851 bcmgenet_enable_rx_napi(priv); 2852 bcmgenet_enable_tx_napi(priv); 2853 2854 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2855 2856 netif_tx_start_all_queues(dev); 2857 2858 /* Monitor link interrupts now */ 2859 bcmgenet_link_intr_enable(priv); 2860 2861 phy_start(priv->phydev); 2862 } 2863 2864 static int bcmgenet_open(struct net_device *dev) 2865 { 2866 struct bcmgenet_priv *priv = netdev_priv(dev); 2867 unsigned long dma_ctrl; 2868 u32 reg; 2869 int ret; 2870 2871 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2872 2873 /* Turn on the clock */ 2874 clk_prepare_enable(priv->clk); 2875 2876 /* If this is an internal GPHY, power it back on now, before UniMAC is 2877 * brought out of reset as absolutely no UniMAC activity is allowed 2878 */ 2879 if (priv->internal_phy) 2880 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2881 2882 /* take MAC out of reset */ 2883 bcmgenet_umac_reset(priv); 2884 2885 ret = init_umac(priv); 2886 if (ret) 2887 goto err_clk_disable; 2888 2889 /* disable ethernet MAC while updating its registers */ 2890 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 2891 2892 /* Make sure we reflect the value of CRC_CMD_FWD */ 2893 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2894 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 2895 2896 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2897 2898 if (priv->internal_phy) { 2899 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2900 reg |= EXT_ENERGY_DET_MASK; 2901 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2902 } 2903 2904 /* Disable RX/TX DMA and flush TX queues */ 2905 dma_ctrl = bcmgenet_dma_disable(priv); 2906 2907 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2908 ret = bcmgenet_init_dma(priv); 2909 if (ret) { 2910 netdev_err(dev, "failed to initialize DMA\n"); 2911 goto err_clk_disable; 2912 } 2913 2914 /* Always enable ring 16 - descriptor ring */ 2915 bcmgenet_enable_dma(priv, dma_ctrl); 2916 2917 /* HFB init */ 2918 bcmgenet_hfb_init(priv); 2919 2920 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2921 dev->name, priv); 2922 if (ret < 0) { 2923 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2924 goto err_fini_dma; 2925 } 2926 2927 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2928 dev->name, priv); 2929 if (ret < 0) { 2930 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2931 goto err_irq0; 2932 } 2933 2934 ret = bcmgenet_mii_probe(dev); 2935 if (ret) { 2936 netdev_err(dev, "failed to connect to PHY\n"); 2937 goto err_irq1; 2938 } 2939 2940 bcmgenet_netif_start(dev); 2941 2942 return 0; 2943 2944 err_irq1: 2945 free_irq(priv->irq1, priv); 2946 err_irq0: 2947 free_irq(priv->irq0, priv); 2948 err_fini_dma: 2949 bcmgenet_fini_dma(priv); 2950 err_clk_disable: 2951 if (priv->internal_phy) 2952 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2953 clk_disable_unprepare(priv->clk); 2954 return ret; 2955 } 2956 2957 static void bcmgenet_netif_stop(struct net_device *dev) 2958 { 2959 struct bcmgenet_priv *priv = netdev_priv(dev); 2960 2961 netif_tx_stop_all_queues(dev); 2962 phy_stop(priv->phydev); 2963 bcmgenet_intr_disable(priv); 2964 bcmgenet_disable_rx_napi(priv); 2965 bcmgenet_disable_tx_napi(priv); 2966 2967 /* Wait for pending work items to complete. Since interrupts are 2968 * disabled no new work will be scheduled. 2969 */ 2970 cancel_work_sync(&priv->bcmgenet_irq_work); 2971 2972 priv->old_link = -1; 2973 priv->old_speed = -1; 2974 priv->old_duplex = -1; 2975 priv->old_pause = -1; 2976 } 2977 2978 static int bcmgenet_close(struct net_device *dev) 2979 { 2980 struct bcmgenet_priv *priv = netdev_priv(dev); 2981 int ret; 2982 2983 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2984 2985 bcmgenet_netif_stop(dev); 2986 2987 /* Really kill the PHY state machine and disconnect from it */ 2988 phy_disconnect(priv->phydev); 2989 2990 /* Disable MAC receive */ 2991 umac_enable_set(priv, CMD_RX_EN, false); 2992 2993 ret = bcmgenet_dma_teardown(priv); 2994 if (ret) 2995 return ret; 2996 2997 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2998 umac_enable_set(priv, CMD_TX_EN, false); 2999 3000 /* tx reclaim */ 3001 bcmgenet_tx_reclaim_all(dev); 3002 bcmgenet_fini_dma(priv); 3003 3004 free_irq(priv->irq0, priv); 3005 free_irq(priv->irq1, priv); 3006 3007 if (priv->internal_phy) 3008 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3009 3010 clk_disable_unprepare(priv->clk); 3011 3012 return ret; 3013 } 3014 3015 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3016 { 3017 struct bcmgenet_priv *priv = ring->priv; 3018 u32 p_index, c_index, intsts, intmsk; 3019 struct netdev_queue *txq; 3020 unsigned int free_bds; 3021 unsigned long flags; 3022 bool txq_stopped; 3023 3024 if (!netif_msg_tx_err(priv)) 3025 return; 3026 3027 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3028 3029 spin_lock_irqsave(&ring->lock, flags); 3030 if (ring->index == DESC_INDEX) { 3031 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3032 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3033 } else { 3034 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3035 intmsk = 1 << ring->index; 3036 } 3037 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3038 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3039 txq_stopped = netif_tx_queue_stopped(txq); 3040 free_bds = ring->free_bds; 3041 spin_unlock_irqrestore(&ring->lock, flags); 3042 3043 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3044 "TX queue status: %s, interrupts: %s\n" 3045 "(sw)free_bds: %d (sw)size: %d\n" 3046 "(sw)p_index: %d (hw)p_index: %d\n" 3047 "(sw)c_index: %d (hw)c_index: %d\n" 3048 "(sw)clean_p: %d (sw)write_p: %d\n" 3049 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3050 ring->index, ring->queue, 3051 txq_stopped ? "stopped" : "active", 3052 intsts & intmsk ? "enabled" : "disabled", 3053 free_bds, ring->size, 3054 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3055 ring->c_index, c_index & DMA_C_INDEX_MASK, 3056 ring->clean_ptr, ring->write_ptr, 3057 ring->cb_ptr, ring->end_ptr); 3058 } 3059 3060 static void bcmgenet_timeout(struct net_device *dev) 3061 { 3062 struct bcmgenet_priv *priv = netdev_priv(dev); 3063 u32 int0_enable = 0; 3064 u32 int1_enable = 0; 3065 unsigned int q; 3066 3067 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3068 3069 for (q = 0; q < priv->hw_params->tx_queues; q++) 3070 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3071 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3072 3073 bcmgenet_tx_reclaim_all(dev); 3074 3075 for (q = 0; q < priv->hw_params->tx_queues; q++) 3076 int1_enable |= (1 << q); 3077 3078 int0_enable = UMAC_IRQ_TXDMA_DONE; 3079 3080 /* Re-enable TX interrupts if disabled */ 3081 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3082 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3083 3084 netif_trans_update(dev); 3085 3086 dev->stats.tx_errors++; 3087 3088 netif_tx_wake_all_queues(dev); 3089 } 3090 3091 #define MAX_MC_COUNT 16 3092 3093 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3094 unsigned char *addr, 3095 int *i, 3096 int *mc) 3097 { 3098 u32 reg; 3099 3100 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3101 UMAC_MDF_ADDR + (*i * 4)); 3102 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3103 addr[4] << 8 | addr[5], 3104 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3105 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); 3106 reg |= (1 << (MAX_MC_COUNT - *mc)); 3107 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3108 *i += 2; 3109 (*mc)++; 3110 } 3111 3112 static void bcmgenet_set_rx_mode(struct net_device *dev) 3113 { 3114 struct bcmgenet_priv *priv = netdev_priv(dev); 3115 struct netdev_hw_addr *ha; 3116 int i, mc; 3117 u32 reg; 3118 3119 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3120 3121 /* Promiscuous mode */ 3122 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3123 if (dev->flags & IFF_PROMISC) { 3124 reg |= CMD_PROMISC; 3125 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3126 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3127 return; 3128 } else { 3129 reg &= ~CMD_PROMISC; 3130 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3131 } 3132 3133 /* UniMac doesn't support ALLMULTI */ 3134 if (dev->flags & IFF_ALLMULTI) { 3135 netdev_warn(dev, "ALLMULTI is not supported\n"); 3136 return; 3137 } 3138 3139 /* update MDF filter */ 3140 i = 0; 3141 mc = 0; 3142 /* Broadcast */ 3143 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); 3144 /* my own address.*/ 3145 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); 3146 /* Unicast list*/ 3147 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) 3148 return; 3149 3150 if (!netdev_uc_empty(dev)) 3151 netdev_for_each_uc_addr(ha, dev) 3152 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 3153 /* Multicast */ 3154 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) 3155 return; 3156 3157 netdev_for_each_mc_addr(ha, dev) 3158 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 3159 } 3160 3161 /* Set the hardware MAC address. */ 3162 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3163 { 3164 struct sockaddr *addr = p; 3165 3166 /* Setting the MAC address at the hardware level is not possible 3167 * without disabling the UniMAC RX/TX enable bits. 3168 */ 3169 if (netif_running(dev)) 3170 return -EBUSY; 3171 3172 ether_addr_copy(dev->dev_addr, addr->sa_data); 3173 3174 return 0; 3175 } 3176 3177 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3178 { 3179 struct bcmgenet_priv *priv = netdev_priv(dev); 3180 unsigned long tx_bytes = 0, tx_packets = 0; 3181 unsigned long rx_bytes = 0, rx_packets = 0; 3182 unsigned long rx_errors = 0, rx_dropped = 0; 3183 struct bcmgenet_tx_ring *tx_ring; 3184 struct bcmgenet_rx_ring *rx_ring; 3185 unsigned int q; 3186 3187 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3188 tx_ring = &priv->tx_rings[q]; 3189 tx_bytes += tx_ring->bytes; 3190 tx_packets += tx_ring->packets; 3191 } 3192 tx_ring = &priv->tx_rings[DESC_INDEX]; 3193 tx_bytes += tx_ring->bytes; 3194 tx_packets += tx_ring->packets; 3195 3196 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3197 rx_ring = &priv->rx_rings[q]; 3198 3199 rx_bytes += rx_ring->bytes; 3200 rx_packets += rx_ring->packets; 3201 rx_errors += rx_ring->errors; 3202 rx_dropped += rx_ring->dropped; 3203 } 3204 rx_ring = &priv->rx_rings[DESC_INDEX]; 3205 rx_bytes += rx_ring->bytes; 3206 rx_packets += rx_ring->packets; 3207 rx_errors += rx_ring->errors; 3208 rx_dropped += rx_ring->dropped; 3209 3210 dev->stats.tx_bytes = tx_bytes; 3211 dev->stats.tx_packets = tx_packets; 3212 dev->stats.rx_bytes = rx_bytes; 3213 dev->stats.rx_packets = rx_packets; 3214 dev->stats.rx_errors = rx_errors; 3215 dev->stats.rx_missed_errors = rx_errors; 3216 return &dev->stats; 3217 } 3218 3219 static const struct net_device_ops bcmgenet_netdev_ops = { 3220 .ndo_open = bcmgenet_open, 3221 .ndo_stop = bcmgenet_close, 3222 .ndo_start_xmit = bcmgenet_xmit, 3223 .ndo_tx_timeout = bcmgenet_timeout, 3224 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3225 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3226 .ndo_do_ioctl = bcmgenet_ioctl, 3227 .ndo_set_features = bcmgenet_set_features, 3228 #ifdef CONFIG_NET_POLL_CONTROLLER 3229 .ndo_poll_controller = bcmgenet_poll_controller, 3230 #endif 3231 .ndo_get_stats = bcmgenet_get_stats, 3232 }; 3233 3234 /* Array of GENET hardware parameters/characteristics */ 3235 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3236 [GENET_V1] = { 3237 .tx_queues = 0, 3238 .tx_bds_per_q = 0, 3239 .rx_queues = 0, 3240 .rx_bds_per_q = 0, 3241 .bp_in_en_shift = 16, 3242 .bp_in_mask = 0xffff, 3243 .hfb_filter_cnt = 16, 3244 .qtag_mask = 0x1F, 3245 .hfb_offset = 0x1000, 3246 .rdma_offset = 0x2000, 3247 .tdma_offset = 0x3000, 3248 .words_per_bd = 2, 3249 }, 3250 [GENET_V2] = { 3251 .tx_queues = 4, 3252 .tx_bds_per_q = 32, 3253 .rx_queues = 0, 3254 .rx_bds_per_q = 0, 3255 .bp_in_en_shift = 16, 3256 .bp_in_mask = 0xffff, 3257 .hfb_filter_cnt = 16, 3258 .qtag_mask = 0x1F, 3259 .tbuf_offset = 0x0600, 3260 .hfb_offset = 0x1000, 3261 .hfb_reg_offset = 0x2000, 3262 .rdma_offset = 0x3000, 3263 .tdma_offset = 0x4000, 3264 .words_per_bd = 2, 3265 .flags = GENET_HAS_EXT, 3266 }, 3267 [GENET_V3] = { 3268 .tx_queues = 4, 3269 .tx_bds_per_q = 32, 3270 .rx_queues = 0, 3271 .rx_bds_per_q = 0, 3272 .bp_in_en_shift = 17, 3273 .bp_in_mask = 0x1ffff, 3274 .hfb_filter_cnt = 48, 3275 .hfb_filter_size = 128, 3276 .qtag_mask = 0x3F, 3277 .tbuf_offset = 0x0600, 3278 .hfb_offset = 0x8000, 3279 .hfb_reg_offset = 0xfc00, 3280 .rdma_offset = 0x10000, 3281 .tdma_offset = 0x11000, 3282 .words_per_bd = 2, 3283 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3284 GENET_HAS_MOCA_LINK_DET, 3285 }, 3286 [GENET_V4] = { 3287 .tx_queues = 4, 3288 .tx_bds_per_q = 32, 3289 .rx_queues = 0, 3290 .rx_bds_per_q = 0, 3291 .bp_in_en_shift = 17, 3292 .bp_in_mask = 0x1ffff, 3293 .hfb_filter_cnt = 48, 3294 .hfb_filter_size = 128, 3295 .qtag_mask = 0x3F, 3296 .tbuf_offset = 0x0600, 3297 .hfb_offset = 0x8000, 3298 .hfb_reg_offset = 0xfc00, 3299 .rdma_offset = 0x2000, 3300 .tdma_offset = 0x4000, 3301 .words_per_bd = 3, 3302 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3303 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3304 }, 3305 [GENET_V5] = { 3306 .tx_queues = 4, 3307 .tx_bds_per_q = 32, 3308 .rx_queues = 0, 3309 .rx_bds_per_q = 0, 3310 .bp_in_en_shift = 17, 3311 .bp_in_mask = 0x1ffff, 3312 .hfb_filter_cnt = 48, 3313 .hfb_filter_size = 128, 3314 .qtag_mask = 0x3F, 3315 .tbuf_offset = 0x0600, 3316 .hfb_offset = 0x8000, 3317 .hfb_reg_offset = 0xfc00, 3318 .rdma_offset = 0x2000, 3319 .tdma_offset = 0x4000, 3320 .words_per_bd = 3, 3321 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3322 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3323 }, 3324 }; 3325 3326 /* Infer hardware parameters from the detected GENET version */ 3327 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3328 { 3329 struct bcmgenet_hw_params *params; 3330 u32 reg; 3331 u8 major; 3332 u16 gphy_rev; 3333 3334 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3335 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3336 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3337 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3338 } else if (GENET_IS_V3(priv)) { 3339 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3340 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3341 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 3342 } else if (GENET_IS_V2(priv)) { 3343 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3344 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3345 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3346 } else if (GENET_IS_V1(priv)) { 3347 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3348 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3349 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 3350 } 3351 3352 /* enum genet_version starts at 1 */ 3353 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3354 params = priv->hw_params; 3355 3356 /* Read GENET HW version */ 3357 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3358 major = (reg >> 24 & 0x0f); 3359 if (major == 6) 3360 major = 5; 3361 else if (major == 5) 3362 major = 4; 3363 else if (major == 0) 3364 major = 1; 3365 if (major != priv->version) { 3366 dev_err(&priv->pdev->dev, 3367 "GENET version mismatch, got: %d, configured for: %d\n", 3368 major, priv->version); 3369 } 3370 3371 /* Print the GENET core version */ 3372 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3373 major, (reg >> 16) & 0x0f, reg & 0xffff); 3374 3375 /* Store the integrated PHY revision for the MDIO probing function 3376 * to pass this information to the PHY driver. The PHY driver expects 3377 * to find the PHY major revision in bits 15:8 while the GENET register 3378 * stores that information in bits 7:0, account for that. 3379 * 3380 * On newer chips, starting with PHY revision G0, a new scheme is 3381 * deployed similar to the Starfighter 2 switch with GPHY major 3382 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3383 * is reserved as well as special value 0x01ff, we have a small 3384 * heuristic to check for the new GPHY revision and re-arrange things 3385 * so the GPHY driver is happy. 3386 */ 3387 gphy_rev = reg & 0xffff; 3388 3389 if (GENET_IS_V5(priv)) { 3390 /* The EPHY revision should come from the MDIO registers of 3391 * the PHY not from GENET. 3392 */ 3393 if (gphy_rev != 0) { 3394 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3395 gphy_rev); 3396 } 3397 /* This is reserved so should require special treatment */ 3398 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3399 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3400 return; 3401 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3402 } else if ((gphy_rev & 0xf0) != 0) { 3403 priv->gphy_rev = gphy_rev << 8; 3404 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3405 } else if ((gphy_rev & 0xff00) != 0) { 3406 priv->gphy_rev = gphy_rev; 3407 } 3408 3409 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3410 if (!(params->flags & GENET_HAS_40BITS)) 3411 pr_warn("GENET does not support 40-bits PA\n"); 3412 #endif 3413 3414 pr_debug("Configuration for version: %d\n" 3415 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3416 "BP << en: %2d, BP msk: 0x%05x\n" 3417 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3418 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3419 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3420 "Words/BD: %d\n", 3421 priv->version, 3422 params->tx_queues, params->tx_bds_per_q, 3423 params->rx_queues, params->rx_bds_per_q, 3424 params->bp_in_en_shift, params->bp_in_mask, 3425 params->hfb_filter_cnt, params->qtag_mask, 3426 params->tbuf_offset, params->hfb_offset, 3427 params->hfb_reg_offset, 3428 params->rdma_offset, params->tdma_offset, 3429 params->words_per_bd); 3430 } 3431 3432 static const struct of_device_id bcmgenet_match[] = { 3433 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, 3434 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, 3435 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, 3436 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, 3437 { .compatible = "brcm,genet-v5", .data = (void *)GENET_V5 }, 3438 { }, 3439 }; 3440 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3441 3442 static int bcmgenet_probe(struct platform_device *pdev) 3443 { 3444 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3445 struct device_node *dn = pdev->dev.of_node; 3446 const struct of_device_id *of_id = NULL; 3447 struct bcmgenet_priv *priv; 3448 struct net_device *dev; 3449 const void *macaddr; 3450 struct resource *r; 3451 int err = -EIO; 3452 const char *phy_mode_str; 3453 3454 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3455 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3456 GENET_MAX_MQ_CNT + 1); 3457 if (!dev) { 3458 dev_err(&pdev->dev, "can't allocate net device\n"); 3459 return -ENOMEM; 3460 } 3461 3462 if (dn) { 3463 of_id = of_match_node(bcmgenet_match, dn); 3464 if (!of_id) 3465 return -EINVAL; 3466 } 3467 3468 priv = netdev_priv(dev); 3469 priv->irq0 = platform_get_irq(pdev, 0); 3470 priv->irq1 = platform_get_irq(pdev, 1); 3471 priv->wol_irq = platform_get_irq(pdev, 2); 3472 if (!priv->irq0 || !priv->irq1) { 3473 dev_err(&pdev->dev, "can't find IRQs\n"); 3474 err = -EINVAL; 3475 goto err; 3476 } 3477 3478 if (dn) { 3479 macaddr = of_get_mac_address(dn); 3480 if (!macaddr) { 3481 dev_err(&pdev->dev, "can't find MAC address\n"); 3482 err = -EINVAL; 3483 goto err; 3484 } 3485 } else { 3486 macaddr = pd->mac_address; 3487 } 3488 3489 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3490 priv->base = devm_ioremap_resource(&pdev->dev, r); 3491 if (IS_ERR(priv->base)) { 3492 err = PTR_ERR(priv->base); 3493 goto err; 3494 } 3495 3496 spin_lock_init(&priv->lock); 3497 3498 SET_NETDEV_DEV(dev, &pdev->dev); 3499 dev_set_drvdata(&pdev->dev, dev); 3500 ether_addr_copy(dev->dev_addr, macaddr); 3501 dev->watchdog_timeo = 2 * HZ; 3502 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3503 dev->netdev_ops = &bcmgenet_netdev_ops; 3504 3505 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3506 3507 /* Set hardware features */ 3508 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 3509 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; 3510 3511 /* Request the WOL interrupt and advertise suspend if available */ 3512 priv->wol_irq_disabled = true; 3513 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3514 dev->name, priv); 3515 if (!err) 3516 device_set_wakeup_capable(&pdev->dev, 1); 3517 3518 /* Set the needed headroom to account for any possible 3519 * features enabling/disabling at runtime 3520 */ 3521 dev->needed_headroom += 64; 3522 3523 netdev_boot_setup_check(dev); 3524 3525 priv->dev = dev; 3526 priv->pdev = pdev; 3527 if (of_id) 3528 priv->version = (enum bcmgenet_version)of_id->data; 3529 else 3530 priv->version = pd->genet_version; 3531 3532 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3533 if (IS_ERR(priv->clk)) { 3534 dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); 3535 priv->clk = NULL; 3536 } 3537 3538 clk_prepare_enable(priv->clk); 3539 3540 bcmgenet_set_hw_params(priv); 3541 3542 /* Mii wait queue */ 3543 init_waitqueue_head(&priv->wq); 3544 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3545 priv->rx_buf_len = RX_BUF_LENGTH; 3546 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3547 3548 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3549 if (IS_ERR(priv->clk_wol)) { 3550 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3551 priv->clk_wol = NULL; 3552 } 3553 3554 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3555 if (IS_ERR(priv->clk_eee)) { 3556 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3557 priv->clk_eee = NULL; 3558 } 3559 3560 /* If this is an internal GPHY, power it on now, before UniMAC is 3561 * brought out of reset as absolutely no UniMAC activity is allowed 3562 */ 3563 if (dn && !of_property_read_string(dn, "phy-mode", &phy_mode_str) && 3564 !strcasecmp(phy_mode_str, "internal")) 3565 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3566 3567 err = reset_umac(priv); 3568 if (err) 3569 goto err_clk_disable; 3570 3571 err = bcmgenet_mii_init(dev); 3572 if (err) 3573 goto err_clk_disable; 3574 3575 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3576 * just the ring 16 descriptor based TX 3577 */ 3578 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3579 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3580 3581 /* libphy will determine the link state */ 3582 netif_carrier_off(dev); 3583 3584 /* Turn off the main clock, WOL clock is handled separately */ 3585 clk_disable_unprepare(priv->clk); 3586 3587 err = register_netdev(dev); 3588 if (err) 3589 goto err; 3590 3591 return err; 3592 3593 err_clk_disable: 3594 clk_disable_unprepare(priv->clk); 3595 err: 3596 free_netdev(dev); 3597 return err; 3598 } 3599 3600 static int bcmgenet_remove(struct platform_device *pdev) 3601 { 3602 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3603 3604 dev_set_drvdata(&pdev->dev, NULL); 3605 unregister_netdev(priv->dev); 3606 bcmgenet_mii_exit(priv->dev); 3607 free_netdev(priv->dev); 3608 3609 return 0; 3610 } 3611 3612 #ifdef CONFIG_PM_SLEEP 3613 static int bcmgenet_suspend(struct device *d) 3614 { 3615 struct net_device *dev = dev_get_drvdata(d); 3616 struct bcmgenet_priv *priv = netdev_priv(dev); 3617 int ret; 3618 3619 if (!netif_running(dev)) 3620 return 0; 3621 3622 bcmgenet_netif_stop(dev); 3623 3624 if (!device_may_wakeup(d)) 3625 phy_suspend(priv->phydev); 3626 3627 netif_device_detach(dev); 3628 3629 /* Disable MAC receive */ 3630 umac_enable_set(priv, CMD_RX_EN, false); 3631 3632 ret = bcmgenet_dma_teardown(priv); 3633 if (ret) 3634 return ret; 3635 3636 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3637 umac_enable_set(priv, CMD_TX_EN, false); 3638 3639 /* tx reclaim */ 3640 bcmgenet_tx_reclaim_all(dev); 3641 bcmgenet_fini_dma(priv); 3642 3643 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3644 if (device_may_wakeup(d) && priv->wolopts) { 3645 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3646 clk_prepare_enable(priv->clk_wol); 3647 } else if (priv->internal_phy) { 3648 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3649 } 3650 3651 /* Turn off the clocks */ 3652 clk_disable_unprepare(priv->clk); 3653 3654 return ret; 3655 } 3656 3657 static int bcmgenet_resume(struct device *d) 3658 { 3659 struct net_device *dev = dev_get_drvdata(d); 3660 struct bcmgenet_priv *priv = netdev_priv(dev); 3661 unsigned long dma_ctrl; 3662 int ret; 3663 u32 reg; 3664 3665 if (!netif_running(dev)) 3666 return 0; 3667 3668 /* Turn on the clock */ 3669 ret = clk_prepare_enable(priv->clk); 3670 if (ret) 3671 return ret; 3672 3673 /* If this is an internal GPHY, power it back on now, before UniMAC is 3674 * brought out of reset as absolutely no UniMAC activity is allowed 3675 */ 3676 if (priv->internal_phy) 3677 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3678 3679 bcmgenet_umac_reset(priv); 3680 3681 ret = init_umac(priv); 3682 if (ret) 3683 goto out_clk_disable; 3684 3685 /* From WOL-enabled suspend, switch to regular clock */ 3686 if (priv->wolopts) 3687 clk_disable_unprepare(priv->clk_wol); 3688 3689 phy_init_hw(priv->phydev); 3690 /* Speed settings must be restored */ 3691 bcmgenet_mii_config(priv->dev, false); 3692 3693 /* disable ethernet MAC while updating its registers */ 3694 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 3695 3696 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3697 3698 if (priv->internal_phy) { 3699 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3700 reg |= EXT_ENERGY_DET_MASK; 3701 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3702 } 3703 3704 if (priv->wolopts) 3705 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3706 3707 /* Disable RX/TX DMA and flush TX queues */ 3708 dma_ctrl = bcmgenet_dma_disable(priv); 3709 3710 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3711 ret = bcmgenet_init_dma(priv); 3712 if (ret) { 3713 netdev_err(dev, "failed to initialize DMA\n"); 3714 goto out_clk_disable; 3715 } 3716 3717 /* Always enable ring 16 - descriptor ring */ 3718 bcmgenet_enable_dma(priv, dma_ctrl); 3719 3720 netif_device_attach(dev); 3721 3722 if (!device_may_wakeup(d)) 3723 phy_resume(priv->phydev); 3724 3725 if (priv->eee.eee_enabled) 3726 bcmgenet_eee_enable_set(dev, true); 3727 3728 bcmgenet_netif_start(dev); 3729 3730 return 0; 3731 3732 out_clk_disable: 3733 if (priv->internal_phy) 3734 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3735 clk_disable_unprepare(priv->clk); 3736 return ret; 3737 } 3738 #endif /* CONFIG_PM_SLEEP */ 3739 3740 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3741 3742 static struct platform_driver bcmgenet_driver = { 3743 .probe = bcmgenet_probe, 3744 .remove = bcmgenet_remove, 3745 .driver = { 3746 .name = "bcmgenet", 3747 .of_match_table = bcmgenet_match, 3748 .pm = &bcmgenet_pm_ops, 3749 }, 3750 }; 3751 module_platform_driver(bcmgenet_driver); 3752 3753 MODULE_AUTHOR("Broadcom Corporation"); 3754 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3755 MODULE_ALIAS("platform:bcmgenet"); 3756 MODULE_LICENSE("GPL"); 3757