1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Broadcom GENET (Gigabit Ethernet) controller driver
4  *
5  * Copyright (c) 2014-2020 Broadcom
6  */
7 
8 #define pr_fmt(fmt)				"bcmgenet: " fmt
9 
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/types.h>
15 #include <linux/fcntl.h>
16 #include <linux/interrupt.h>
17 #include <linux/string.h>
18 #include <linux/if_ether.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/pm.h>
25 #include <linux/clk.h>
26 #include <net/arp.h>
27 
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/netdevice.h>
31 #include <linux/inetdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/phy.h>
38 #include <linux/platform_data/bcmgenet.h>
39 
40 #include <asm/unaligned.h>
41 
42 #include "bcmgenet.h"
43 
44 /* Maximum number of hardware queues, downsized if needed */
45 #define GENET_MAX_MQ_CNT	4
46 
47 /* Default highest priority queue for multi queue support */
48 #define GENET_Q0_PRIORITY	0
49 
50 #define GENET_Q16_RX_BD_CNT	\
51 	(TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
52 #define GENET_Q16_TX_BD_CNT	\
53 	(TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
54 
55 #define RX_BUF_LENGTH		2048
56 #define SKB_ALIGNMENT		32
57 
58 /* Tx/Rx DMA register offset, skip 256 descriptors */
59 #define WORDS_PER_BD(p)		(p->hw_params->words_per_bd)
60 #define DMA_DESC_SIZE		(WORDS_PER_BD(priv) * sizeof(u32))
61 
62 #define GENET_TDMA_REG_OFF	(priv->hw_params->tdma_offset + \
63 				TOTAL_DESC * DMA_DESC_SIZE)
64 
65 #define GENET_RDMA_REG_OFF	(priv->hw_params->rdma_offset + \
66 				TOTAL_DESC * DMA_DESC_SIZE)
67 
68 /* Forward declarations */
69 static void bcmgenet_set_rx_mode(struct net_device *dev);
70 
71 static inline void bcmgenet_writel(u32 value, void __iomem *offset)
72 {
73 	/* MIPS chips strapped for BE will automagically configure the
74 	 * peripheral registers for CPU-native byte order.
75 	 */
76 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
77 		__raw_writel(value, offset);
78 	else
79 		writel_relaxed(value, offset);
80 }
81 
82 static inline u32 bcmgenet_readl(void __iomem *offset)
83 {
84 	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
85 		return __raw_readl(offset);
86 	else
87 		return readl_relaxed(offset);
88 }
89 
90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
91 					     void __iomem *d, u32 value)
92 {
93 	bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS);
94 }
95 
96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
97 				    void __iomem *d,
98 				    dma_addr_t addr)
99 {
100 	bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
101 
102 	/* Register writes to GISB bus can take couple hundred nanoseconds
103 	 * and are done for each packet, save these expensive writes unless
104 	 * the platform is explicitly configured for 64-bits/LPAE.
105 	 */
106 #ifdef CONFIG_PHYS_ADDR_T_64BIT
107 	if (priv->hw_params->flags & GENET_HAS_40BITS)
108 		bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
109 #endif
110 }
111 
112 /* Combined address + length/status setter */
113 static inline void dmadesc_set(struct bcmgenet_priv *priv,
114 			       void __iomem *d, dma_addr_t addr, u32 val)
115 {
116 	dmadesc_set_addr(priv, d, addr);
117 	dmadesc_set_length_status(priv, d, val);
118 }
119 
120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
121 					  void __iomem *d)
122 {
123 	dma_addr_t addr;
124 
125 	addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO);
126 
127 	/* Register writes to GISB bus can take couple hundred nanoseconds
128 	 * and are done for each packet, save these expensive writes unless
129 	 * the platform is explicitly configured for 64-bits/LPAE.
130 	 */
131 #ifdef CONFIG_PHYS_ADDR_T_64BIT
132 	if (priv->hw_params->flags & GENET_HAS_40BITS)
133 		addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32;
134 #endif
135 	return addr;
136 }
137 
138 #define GENET_VER_FMT	"%1d.%1d EPHY: 0x%04x"
139 
140 #define GENET_MSG_DEFAULT	(NETIF_MSG_DRV | NETIF_MSG_PROBE | \
141 				NETIF_MSG_LINK)
142 
143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
144 {
145 	if (GENET_IS_V1(priv))
146 		return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
147 	else
148 		return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
149 }
150 
151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
152 {
153 	if (GENET_IS_V1(priv))
154 		bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
155 	else
156 		bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
157 }
158 
159 /* These macros are defined to deal with register map change
160  * between GENET1.1 and GENET2. Only those currently being used
161  * by driver are defined.
162  */
163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
164 {
165 	if (GENET_IS_V1(priv))
166 		return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
167 	else
168 		return bcmgenet_readl(priv->base +
169 				      priv->hw_params->tbuf_offset + TBUF_CTRL);
170 }
171 
172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
173 {
174 	if (GENET_IS_V1(priv))
175 		bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
176 	else
177 		bcmgenet_writel(val, priv->base +
178 				priv->hw_params->tbuf_offset + TBUF_CTRL);
179 }
180 
181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
182 {
183 	if (GENET_IS_V1(priv))
184 		return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
185 	else
186 		return bcmgenet_readl(priv->base +
187 				      priv->hw_params->tbuf_offset + TBUF_BP_MC);
188 }
189 
190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
191 {
192 	if (GENET_IS_V1(priv))
193 		bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
194 	else
195 		bcmgenet_writel(val, priv->base +
196 				priv->hw_params->tbuf_offset + TBUF_BP_MC);
197 }
198 
199 /* RX/TX DMA register accessors */
200 enum dma_reg {
201 	DMA_RING_CFG = 0,
202 	DMA_CTRL,
203 	DMA_STATUS,
204 	DMA_SCB_BURST_SIZE,
205 	DMA_ARB_CTRL,
206 	DMA_PRIORITY_0,
207 	DMA_PRIORITY_1,
208 	DMA_PRIORITY_2,
209 	DMA_INDEX2RING_0,
210 	DMA_INDEX2RING_1,
211 	DMA_INDEX2RING_2,
212 	DMA_INDEX2RING_3,
213 	DMA_INDEX2RING_4,
214 	DMA_INDEX2RING_5,
215 	DMA_INDEX2RING_6,
216 	DMA_INDEX2RING_7,
217 	DMA_RING0_TIMEOUT,
218 	DMA_RING1_TIMEOUT,
219 	DMA_RING2_TIMEOUT,
220 	DMA_RING3_TIMEOUT,
221 	DMA_RING4_TIMEOUT,
222 	DMA_RING5_TIMEOUT,
223 	DMA_RING6_TIMEOUT,
224 	DMA_RING7_TIMEOUT,
225 	DMA_RING8_TIMEOUT,
226 	DMA_RING9_TIMEOUT,
227 	DMA_RING10_TIMEOUT,
228 	DMA_RING11_TIMEOUT,
229 	DMA_RING12_TIMEOUT,
230 	DMA_RING13_TIMEOUT,
231 	DMA_RING14_TIMEOUT,
232 	DMA_RING15_TIMEOUT,
233 	DMA_RING16_TIMEOUT,
234 };
235 
236 static const u8 bcmgenet_dma_regs_v3plus[] = {
237 	[DMA_RING_CFG]		= 0x00,
238 	[DMA_CTRL]		= 0x04,
239 	[DMA_STATUS]		= 0x08,
240 	[DMA_SCB_BURST_SIZE]	= 0x0C,
241 	[DMA_ARB_CTRL]		= 0x2C,
242 	[DMA_PRIORITY_0]	= 0x30,
243 	[DMA_PRIORITY_1]	= 0x34,
244 	[DMA_PRIORITY_2]	= 0x38,
245 	[DMA_RING0_TIMEOUT]	= 0x2C,
246 	[DMA_RING1_TIMEOUT]	= 0x30,
247 	[DMA_RING2_TIMEOUT]	= 0x34,
248 	[DMA_RING3_TIMEOUT]	= 0x38,
249 	[DMA_RING4_TIMEOUT]	= 0x3c,
250 	[DMA_RING5_TIMEOUT]	= 0x40,
251 	[DMA_RING6_TIMEOUT]	= 0x44,
252 	[DMA_RING7_TIMEOUT]	= 0x48,
253 	[DMA_RING8_TIMEOUT]	= 0x4c,
254 	[DMA_RING9_TIMEOUT]	= 0x50,
255 	[DMA_RING10_TIMEOUT]	= 0x54,
256 	[DMA_RING11_TIMEOUT]	= 0x58,
257 	[DMA_RING12_TIMEOUT]	= 0x5c,
258 	[DMA_RING13_TIMEOUT]	= 0x60,
259 	[DMA_RING14_TIMEOUT]	= 0x64,
260 	[DMA_RING15_TIMEOUT]	= 0x68,
261 	[DMA_RING16_TIMEOUT]	= 0x6C,
262 	[DMA_INDEX2RING_0]	= 0x70,
263 	[DMA_INDEX2RING_1]	= 0x74,
264 	[DMA_INDEX2RING_2]	= 0x78,
265 	[DMA_INDEX2RING_3]	= 0x7C,
266 	[DMA_INDEX2RING_4]	= 0x80,
267 	[DMA_INDEX2RING_5]	= 0x84,
268 	[DMA_INDEX2RING_6]	= 0x88,
269 	[DMA_INDEX2RING_7]	= 0x8C,
270 };
271 
272 static const u8 bcmgenet_dma_regs_v2[] = {
273 	[DMA_RING_CFG]		= 0x00,
274 	[DMA_CTRL]		= 0x04,
275 	[DMA_STATUS]		= 0x08,
276 	[DMA_SCB_BURST_SIZE]	= 0x0C,
277 	[DMA_ARB_CTRL]		= 0x30,
278 	[DMA_PRIORITY_0]	= 0x34,
279 	[DMA_PRIORITY_1]	= 0x38,
280 	[DMA_PRIORITY_2]	= 0x3C,
281 	[DMA_RING0_TIMEOUT]	= 0x2C,
282 	[DMA_RING1_TIMEOUT]	= 0x30,
283 	[DMA_RING2_TIMEOUT]	= 0x34,
284 	[DMA_RING3_TIMEOUT]	= 0x38,
285 	[DMA_RING4_TIMEOUT]	= 0x3c,
286 	[DMA_RING5_TIMEOUT]	= 0x40,
287 	[DMA_RING6_TIMEOUT]	= 0x44,
288 	[DMA_RING7_TIMEOUT]	= 0x48,
289 	[DMA_RING8_TIMEOUT]	= 0x4c,
290 	[DMA_RING9_TIMEOUT]	= 0x50,
291 	[DMA_RING10_TIMEOUT]	= 0x54,
292 	[DMA_RING11_TIMEOUT]	= 0x58,
293 	[DMA_RING12_TIMEOUT]	= 0x5c,
294 	[DMA_RING13_TIMEOUT]	= 0x60,
295 	[DMA_RING14_TIMEOUT]	= 0x64,
296 	[DMA_RING15_TIMEOUT]	= 0x68,
297 	[DMA_RING16_TIMEOUT]	= 0x6C,
298 };
299 
300 static const u8 bcmgenet_dma_regs_v1[] = {
301 	[DMA_CTRL]		= 0x00,
302 	[DMA_STATUS]		= 0x04,
303 	[DMA_SCB_BURST_SIZE]	= 0x0C,
304 	[DMA_ARB_CTRL]		= 0x30,
305 	[DMA_PRIORITY_0]	= 0x34,
306 	[DMA_PRIORITY_1]	= 0x38,
307 	[DMA_PRIORITY_2]	= 0x3C,
308 	[DMA_RING0_TIMEOUT]	= 0x2C,
309 	[DMA_RING1_TIMEOUT]	= 0x30,
310 	[DMA_RING2_TIMEOUT]	= 0x34,
311 	[DMA_RING3_TIMEOUT]	= 0x38,
312 	[DMA_RING4_TIMEOUT]	= 0x3c,
313 	[DMA_RING5_TIMEOUT]	= 0x40,
314 	[DMA_RING6_TIMEOUT]	= 0x44,
315 	[DMA_RING7_TIMEOUT]	= 0x48,
316 	[DMA_RING8_TIMEOUT]	= 0x4c,
317 	[DMA_RING9_TIMEOUT]	= 0x50,
318 	[DMA_RING10_TIMEOUT]	= 0x54,
319 	[DMA_RING11_TIMEOUT]	= 0x58,
320 	[DMA_RING12_TIMEOUT]	= 0x5c,
321 	[DMA_RING13_TIMEOUT]	= 0x60,
322 	[DMA_RING14_TIMEOUT]	= 0x64,
323 	[DMA_RING15_TIMEOUT]	= 0x68,
324 	[DMA_RING16_TIMEOUT]	= 0x6C,
325 };
326 
327 /* Set at runtime once bcmgenet version is known */
328 static const u8 *bcmgenet_dma_regs;
329 
330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
331 {
332 	return netdev_priv(dev_get_drvdata(dev));
333 }
334 
335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
336 				      enum dma_reg r)
337 {
338 	return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
339 			      DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
340 }
341 
342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
343 					u32 val, enum dma_reg r)
344 {
345 	bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
346 			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
347 }
348 
349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
350 				      enum dma_reg r)
351 {
352 	return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
353 			      DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
354 }
355 
356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
357 					u32 val, enum dma_reg r)
358 {
359 	bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
360 			DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
361 }
362 
363 /* RDMA/TDMA ring registers and accessors
364  * we merge the common fields and just prefix with T/D the registers
365  * having different meaning depending on the direction
366  */
367 enum dma_ring_reg {
368 	TDMA_READ_PTR = 0,
369 	RDMA_WRITE_PTR = TDMA_READ_PTR,
370 	TDMA_READ_PTR_HI,
371 	RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
372 	TDMA_CONS_INDEX,
373 	RDMA_PROD_INDEX = TDMA_CONS_INDEX,
374 	TDMA_PROD_INDEX,
375 	RDMA_CONS_INDEX = TDMA_PROD_INDEX,
376 	DMA_RING_BUF_SIZE,
377 	DMA_START_ADDR,
378 	DMA_START_ADDR_HI,
379 	DMA_END_ADDR,
380 	DMA_END_ADDR_HI,
381 	DMA_MBUF_DONE_THRESH,
382 	TDMA_FLOW_PERIOD,
383 	RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
384 	TDMA_WRITE_PTR,
385 	RDMA_READ_PTR = TDMA_WRITE_PTR,
386 	TDMA_WRITE_PTR_HI,
387 	RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
388 };
389 
390 /* GENET v4 supports 40-bits pointer addressing
391  * for obvious reasons the LO and HI word parts
392  * are contiguous, but this offsets the other
393  * registers.
394  */
395 static const u8 genet_dma_ring_regs_v4[] = {
396 	[TDMA_READ_PTR]			= 0x00,
397 	[TDMA_READ_PTR_HI]		= 0x04,
398 	[TDMA_CONS_INDEX]		= 0x08,
399 	[TDMA_PROD_INDEX]		= 0x0C,
400 	[DMA_RING_BUF_SIZE]		= 0x10,
401 	[DMA_START_ADDR]		= 0x14,
402 	[DMA_START_ADDR_HI]		= 0x18,
403 	[DMA_END_ADDR]			= 0x1C,
404 	[DMA_END_ADDR_HI]		= 0x20,
405 	[DMA_MBUF_DONE_THRESH]		= 0x24,
406 	[TDMA_FLOW_PERIOD]		= 0x28,
407 	[TDMA_WRITE_PTR]		= 0x2C,
408 	[TDMA_WRITE_PTR_HI]		= 0x30,
409 };
410 
411 static const u8 genet_dma_ring_regs_v123[] = {
412 	[TDMA_READ_PTR]			= 0x00,
413 	[TDMA_CONS_INDEX]		= 0x04,
414 	[TDMA_PROD_INDEX]		= 0x08,
415 	[DMA_RING_BUF_SIZE]		= 0x0C,
416 	[DMA_START_ADDR]		= 0x10,
417 	[DMA_END_ADDR]			= 0x14,
418 	[DMA_MBUF_DONE_THRESH]		= 0x18,
419 	[TDMA_FLOW_PERIOD]		= 0x1C,
420 	[TDMA_WRITE_PTR]		= 0x20,
421 };
422 
423 /* Set at runtime once GENET version is known */
424 static const u8 *genet_dma_ring_regs;
425 
426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
427 					   unsigned int ring,
428 					   enum dma_ring_reg r)
429 {
430 	return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF +
431 			      (DMA_RING_SIZE * ring) +
432 			      genet_dma_ring_regs[r]);
433 }
434 
435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
436 					     unsigned int ring, u32 val,
437 					     enum dma_ring_reg r)
438 {
439 	bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF +
440 			(DMA_RING_SIZE * ring) +
441 			genet_dma_ring_regs[r]);
442 }
443 
444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
445 					   unsigned int ring,
446 					   enum dma_ring_reg r)
447 {
448 	return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF +
449 			      (DMA_RING_SIZE * ring) +
450 			      genet_dma_ring_regs[r]);
451 }
452 
453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
454 					     unsigned int ring, u32 val,
455 					     enum dma_ring_reg r)
456 {
457 	bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF +
458 			(DMA_RING_SIZE * ring) +
459 			genet_dma_ring_regs[r]);
460 }
461 
462 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
463 {
464 	u32 offset;
465 	u32 reg;
466 
467 	offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
468 	reg = bcmgenet_hfb_reg_readl(priv, offset);
469 	reg |= (1 << (f_index % 32));
470 	bcmgenet_hfb_reg_writel(priv, reg, offset);
471 	reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
472 	reg |= RBUF_HFB_EN;
473 	bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
474 }
475 
476 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index)
477 {
478 	u32 offset, reg, reg1;
479 
480 	offset = HFB_FLT_ENABLE_V3PLUS;
481 	reg = bcmgenet_hfb_reg_readl(priv, offset);
482 	reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32));
483 	if  (f_index < 32) {
484 		reg1 &= ~(1 << (f_index % 32));
485 		bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32));
486 	} else {
487 		reg &= ~(1 << (f_index % 32));
488 		bcmgenet_hfb_reg_writel(priv, reg, offset);
489 	}
490 	if (!reg && !reg1) {
491 		reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL);
492 		reg &= ~RBUF_HFB_EN;
493 		bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL);
494 	}
495 }
496 
497 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
498 						     u32 f_index, u32 rx_queue)
499 {
500 	u32 offset;
501 	u32 reg;
502 
503 	offset = f_index / 8;
504 	reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
505 	reg &= ~(0xF << (4 * (f_index % 8)));
506 	reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
507 	bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
508 }
509 
510 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
511 					   u32 f_index, u32 f_length)
512 {
513 	u32 offset;
514 	u32 reg;
515 
516 	offset = HFB_FLT_LEN_V3PLUS +
517 		 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
518 		 sizeof(u32);
519 	reg = bcmgenet_hfb_reg_readl(priv, offset);
520 	reg &= ~(0xFF << (8 * (f_index % 4)));
521 	reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
522 	bcmgenet_hfb_reg_writel(priv, reg, offset);
523 }
524 
525 static int bcmgenet_hfb_validate_mask(void *mask, size_t size)
526 {
527 	while (size) {
528 		switch (*(unsigned char *)mask++) {
529 		case 0x00:
530 		case 0x0f:
531 		case 0xf0:
532 		case 0xff:
533 			size--;
534 			continue;
535 		default:
536 			return -EINVAL;
537 		}
538 	}
539 
540 	return 0;
541 }
542 
543 #define VALIDATE_MASK(x) \
544 	bcmgenet_hfb_validate_mask(&(x), sizeof(x))
545 
546 static int bcmgenet_hfb_insert_data(struct bcmgenet_priv *priv, u32 f_index,
547 				    u32 offset, void *val, void *mask,
548 				    size_t size)
549 {
550 	u32 index, tmp;
551 
552 	index = f_index * priv->hw_params->hfb_filter_size + offset / 2;
553 	tmp = bcmgenet_hfb_readl(priv, index * sizeof(u32));
554 
555 	while (size--) {
556 		if (offset++ & 1) {
557 			tmp &= ~0x300FF;
558 			tmp |= (*(unsigned char *)val++);
559 			switch ((*(unsigned char *)mask++)) {
560 			case 0xFF:
561 				tmp |= 0x30000;
562 				break;
563 			case 0xF0:
564 				tmp |= 0x20000;
565 				break;
566 			case 0x0F:
567 				tmp |= 0x10000;
568 				break;
569 			}
570 			bcmgenet_hfb_writel(priv, tmp, index++ * sizeof(u32));
571 			if (size)
572 				tmp = bcmgenet_hfb_readl(priv,
573 							 index * sizeof(u32));
574 		} else {
575 			tmp &= ~0xCFF00;
576 			tmp |= (*(unsigned char *)val++) << 8;
577 			switch ((*(unsigned char *)mask++)) {
578 			case 0xFF:
579 				tmp |= 0xC0000;
580 				break;
581 			case 0xF0:
582 				tmp |= 0x80000;
583 				break;
584 			case 0x0F:
585 				tmp |= 0x40000;
586 				break;
587 			}
588 			if (!size)
589 				bcmgenet_hfb_writel(priv, tmp, index * sizeof(u32));
590 		}
591 	}
592 
593 	return 0;
594 }
595 
596 static void bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv,
597 					     struct bcmgenet_rxnfc_rule *rule)
598 {
599 	struct ethtool_rx_flow_spec *fs = &rule->fs;
600 	u32 offset = 0, f_length = 0, f;
601 	u8 val_8, mask_8;
602 	__be16 val_16;
603 	u16 mask_16;
604 	size_t size;
605 
606 	f = fs->location;
607 	if (fs->flow_type & FLOW_MAC_EXT) {
608 		bcmgenet_hfb_insert_data(priv, f, 0,
609 					 &fs->h_ext.h_dest, &fs->m_ext.h_dest,
610 					 sizeof(fs->h_ext.h_dest));
611 	}
612 
613 	if (fs->flow_type & FLOW_EXT) {
614 		if (fs->m_ext.vlan_etype ||
615 		    fs->m_ext.vlan_tci) {
616 			bcmgenet_hfb_insert_data(priv, f, 12,
617 						 &fs->h_ext.vlan_etype,
618 						 &fs->m_ext.vlan_etype,
619 						 sizeof(fs->h_ext.vlan_etype));
620 			bcmgenet_hfb_insert_data(priv, f, 14,
621 						 &fs->h_ext.vlan_tci,
622 						 &fs->m_ext.vlan_tci,
623 						 sizeof(fs->h_ext.vlan_tci));
624 			offset += VLAN_HLEN;
625 			f_length += DIV_ROUND_UP(VLAN_HLEN, 2);
626 		}
627 	}
628 
629 	switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
630 	case ETHER_FLOW:
631 		f_length += DIV_ROUND_UP(ETH_HLEN, 2);
632 		bcmgenet_hfb_insert_data(priv, f, 0,
633 					 &fs->h_u.ether_spec.h_dest,
634 					 &fs->m_u.ether_spec.h_dest,
635 					 sizeof(fs->h_u.ether_spec.h_dest));
636 		bcmgenet_hfb_insert_data(priv, f, ETH_ALEN,
637 					 &fs->h_u.ether_spec.h_source,
638 					 &fs->m_u.ether_spec.h_source,
639 					 sizeof(fs->h_u.ether_spec.h_source));
640 		bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
641 					 &fs->h_u.ether_spec.h_proto,
642 					 &fs->m_u.ether_spec.h_proto,
643 					 sizeof(fs->h_u.ether_spec.h_proto));
644 		break;
645 	case IP_USER_FLOW:
646 		f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2);
647 		/* Specify IP Ether Type */
648 		val_16 = htons(ETH_P_IP);
649 		mask_16 = 0xFFFF;
650 		bcmgenet_hfb_insert_data(priv, f, (2 * ETH_ALEN) + offset,
651 					 &val_16, &mask_16, sizeof(val_16));
652 		bcmgenet_hfb_insert_data(priv, f, 15 + offset,
653 					 &fs->h_u.usr_ip4_spec.tos,
654 					 &fs->m_u.usr_ip4_spec.tos,
655 					 sizeof(fs->h_u.usr_ip4_spec.tos));
656 		bcmgenet_hfb_insert_data(priv, f, 23 + offset,
657 					 &fs->h_u.usr_ip4_spec.proto,
658 					 &fs->m_u.usr_ip4_spec.proto,
659 					 sizeof(fs->h_u.usr_ip4_spec.proto));
660 		bcmgenet_hfb_insert_data(priv, f, 26 + offset,
661 					 &fs->h_u.usr_ip4_spec.ip4src,
662 					 &fs->m_u.usr_ip4_spec.ip4src,
663 					 sizeof(fs->h_u.usr_ip4_spec.ip4src));
664 		bcmgenet_hfb_insert_data(priv, f, 30 + offset,
665 					 &fs->h_u.usr_ip4_spec.ip4dst,
666 					 &fs->m_u.usr_ip4_spec.ip4dst,
667 					 sizeof(fs->h_u.usr_ip4_spec.ip4dst));
668 		if (!fs->m_u.usr_ip4_spec.l4_4_bytes)
669 			break;
670 
671 		/* Only supports 20 byte IPv4 header */
672 		val_8 = 0x45;
673 		mask_8 = 0xFF;
674 		bcmgenet_hfb_insert_data(priv, f, ETH_HLEN + offset,
675 					 &val_8, &mask_8,
676 					 sizeof(val_8));
677 		size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes);
678 		bcmgenet_hfb_insert_data(priv, f,
679 					 ETH_HLEN + 20 + offset,
680 					 &fs->h_u.usr_ip4_spec.l4_4_bytes,
681 					 &fs->m_u.usr_ip4_spec.l4_4_bytes,
682 					 size);
683 		f_length += DIV_ROUND_UP(size, 2);
684 		break;
685 	}
686 
687 	bcmgenet_hfb_set_filter_length(priv, f, 2 * f_length);
688 	if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) {
689 		/* Ring 0 flows can be handled by the default Descriptor Ring
690 		 * We'll map them to ring 0, but don't enable the filter
691 		 */
692 		bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f, 0);
693 		rule->state = BCMGENET_RXNFC_STATE_DISABLED;
694 	} else {
695 		/* Other Rx rings are direct mapped here */
696 		bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f,
697 							 fs->ring_cookie);
698 		bcmgenet_hfb_enable_filter(priv, f);
699 		rule->state = BCMGENET_RXNFC_STATE_ENABLED;
700 	}
701 }
702 
703 /* bcmgenet_hfb_clear
704  *
705  * Clear Hardware Filter Block and disable all filtering.
706  */
707 static void bcmgenet_hfb_clear_filter(struct bcmgenet_priv *priv, u32 f_index)
708 {
709 	u32 base, i;
710 
711 	base = f_index * priv->hw_params->hfb_filter_size;
712 	for (i = 0; i < priv->hw_params->hfb_filter_size; i++)
713 		bcmgenet_hfb_writel(priv, 0x0, (base + i) * sizeof(u32));
714 }
715 
716 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
717 {
718 	u32 i;
719 
720 	if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
721 		return;
722 
723 	bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
724 	bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
725 	bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
726 
727 	for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
728 		bcmgenet_rdma_writel(priv, 0x0, i);
729 
730 	for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
731 		bcmgenet_hfb_reg_writel(priv, 0x0,
732 					HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
733 
734 	for (i = 0; i < priv->hw_params->hfb_filter_cnt; i++)
735 		bcmgenet_hfb_clear_filter(priv, i);
736 }
737 
738 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
739 {
740 	int i;
741 
742 	INIT_LIST_HEAD(&priv->rxnfc_list);
743 	if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
744 		return;
745 
746 	for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
747 		INIT_LIST_HEAD(&priv->rxnfc_rules[i].list);
748 		priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED;
749 	}
750 
751 	bcmgenet_hfb_clear(priv);
752 }
753 
754 static int bcmgenet_begin(struct net_device *dev)
755 {
756 	struct bcmgenet_priv *priv = netdev_priv(dev);
757 
758 	/* Turn on the clock */
759 	return clk_prepare_enable(priv->clk);
760 }
761 
762 static void bcmgenet_complete(struct net_device *dev)
763 {
764 	struct bcmgenet_priv *priv = netdev_priv(dev);
765 
766 	/* Turn off the clock */
767 	clk_disable_unprepare(priv->clk);
768 }
769 
770 static int bcmgenet_get_link_ksettings(struct net_device *dev,
771 				       struct ethtool_link_ksettings *cmd)
772 {
773 	if (!netif_running(dev))
774 		return -EINVAL;
775 
776 	if (!dev->phydev)
777 		return -ENODEV;
778 
779 	phy_ethtool_ksettings_get(dev->phydev, cmd);
780 
781 	return 0;
782 }
783 
784 static int bcmgenet_set_link_ksettings(struct net_device *dev,
785 				       const struct ethtool_link_ksettings *cmd)
786 {
787 	if (!netif_running(dev))
788 		return -EINVAL;
789 
790 	if (!dev->phydev)
791 		return -ENODEV;
792 
793 	return phy_ethtool_ksettings_set(dev->phydev, cmd);
794 }
795 
796 static int bcmgenet_set_features(struct net_device *dev,
797 				 netdev_features_t features)
798 {
799 	struct bcmgenet_priv *priv = netdev_priv(dev);
800 	u32 reg;
801 	int ret;
802 
803 	ret = clk_prepare_enable(priv->clk);
804 	if (ret)
805 		return ret;
806 
807 	/* Make sure we reflect the value of CRC_CMD_FWD */
808 	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
809 	priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
810 
811 	clk_disable_unprepare(priv->clk);
812 
813 	return ret;
814 }
815 
816 static u32 bcmgenet_get_msglevel(struct net_device *dev)
817 {
818 	struct bcmgenet_priv *priv = netdev_priv(dev);
819 
820 	return priv->msg_enable;
821 }
822 
823 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
824 {
825 	struct bcmgenet_priv *priv = netdev_priv(dev);
826 
827 	priv->msg_enable = level;
828 }
829 
830 static int bcmgenet_get_coalesce(struct net_device *dev,
831 				 struct ethtool_coalesce *ec,
832 				 struct kernel_ethtool_coalesce *kernel_coal,
833 				 struct netlink_ext_ack *extack)
834 {
835 	struct bcmgenet_priv *priv = netdev_priv(dev);
836 	struct bcmgenet_rx_ring *ring;
837 	unsigned int i;
838 
839 	ec->tx_max_coalesced_frames =
840 		bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
841 					 DMA_MBUF_DONE_THRESH);
842 	ec->rx_max_coalesced_frames =
843 		bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
844 					 DMA_MBUF_DONE_THRESH);
845 	ec->rx_coalesce_usecs =
846 		bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
847 
848 	for (i = 0; i < priv->hw_params->rx_queues; i++) {
849 		ring = &priv->rx_rings[i];
850 		ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
851 	}
852 	ring = &priv->rx_rings[DESC_INDEX];
853 	ec->use_adaptive_rx_coalesce |= ring->dim.use_dim;
854 
855 	return 0;
856 }
857 
858 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring,
859 				     u32 usecs, u32 pkts)
860 {
861 	struct bcmgenet_priv *priv = ring->priv;
862 	unsigned int i = ring->index;
863 	u32 reg;
864 
865 	bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH);
866 
867 	reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
868 	reg &= ~DMA_TIMEOUT_MASK;
869 	reg |= DIV_ROUND_UP(usecs * 1000, 8192);
870 	bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
871 }
872 
873 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring,
874 					  struct ethtool_coalesce *ec)
875 {
876 	struct dim_cq_moder moder;
877 	u32 usecs, pkts;
878 
879 	ring->rx_coalesce_usecs = ec->rx_coalesce_usecs;
880 	ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
881 	usecs = ring->rx_coalesce_usecs;
882 	pkts = ring->rx_max_coalesced_frames;
883 
884 	if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) {
885 		moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode);
886 		usecs = moder.usec;
887 		pkts = moder.pkts;
888 	}
889 
890 	ring->dim.use_dim = ec->use_adaptive_rx_coalesce;
891 	bcmgenet_set_rx_coalesce(ring, usecs, pkts);
892 }
893 
894 static int bcmgenet_set_coalesce(struct net_device *dev,
895 				 struct ethtool_coalesce *ec,
896 				 struct kernel_ethtool_coalesce *kernel_coal,
897 				 struct netlink_ext_ack *extack)
898 {
899 	struct bcmgenet_priv *priv = netdev_priv(dev);
900 	unsigned int i;
901 
902 	/* Base system clock is 125Mhz, DMA timeout is this reference clock
903 	 * divided by 1024, which yields roughly 8.192us, our maximum value
904 	 * has to fit in the DMA_TIMEOUT_MASK (16 bits)
905 	 */
906 	if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
907 	    ec->tx_max_coalesced_frames == 0 ||
908 	    ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
909 	    ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
910 		return -EINVAL;
911 
912 	if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
913 		return -EINVAL;
914 
915 	/* GENET TDMA hardware does not support a configurable timeout, but will
916 	 * always generate an interrupt either after MBDONE packets have been
917 	 * transmitted, or when the ring is empty.
918 	 */
919 
920 	/* Program all TX queues with the same values, as there is no
921 	 * ethtool knob to do coalescing on a per-queue basis
922 	 */
923 	for (i = 0; i < priv->hw_params->tx_queues; i++)
924 		bcmgenet_tdma_ring_writel(priv, i,
925 					  ec->tx_max_coalesced_frames,
926 					  DMA_MBUF_DONE_THRESH);
927 	bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
928 				  ec->tx_max_coalesced_frames,
929 				  DMA_MBUF_DONE_THRESH);
930 
931 	for (i = 0; i < priv->hw_params->rx_queues; i++)
932 		bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec);
933 	bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec);
934 
935 	return 0;
936 }
937 
938 static void bcmgenet_get_pauseparam(struct net_device *dev,
939 				    struct ethtool_pauseparam *epause)
940 {
941 	struct bcmgenet_priv *priv;
942 	u32 umac_cmd;
943 
944 	priv = netdev_priv(dev);
945 
946 	epause->autoneg = priv->autoneg_pause;
947 
948 	if (netif_carrier_ok(dev)) {
949 		/* report active state when link is up */
950 		umac_cmd = bcmgenet_umac_readl(priv, UMAC_CMD);
951 		epause->tx_pause = !(umac_cmd & CMD_TX_PAUSE_IGNORE);
952 		epause->rx_pause = !(umac_cmd & CMD_RX_PAUSE_IGNORE);
953 	} else {
954 		/* otherwise report stored settings */
955 		epause->tx_pause = priv->tx_pause;
956 		epause->rx_pause = priv->rx_pause;
957 	}
958 }
959 
960 static int bcmgenet_set_pauseparam(struct net_device *dev,
961 				   struct ethtool_pauseparam *epause)
962 {
963 	struct bcmgenet_priv *priv = netdev_priv(dev);
964 
965 	if (!dev->phydev)
966 		return -ENODEV;
967 
968 	if (!phy_validate_pause(dev->phydev, epause))
969 		return -EINVAL;
970 
971 	priv->autoneg_pause = !!epause->autoneg;
972 	priv->tx_pause = !!epause->tx_pause;
973 	priv->rx_pause = !!epause->rx_pause;
974 
975 	bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
976 
977 	return 0;
978 }
979 
980 /* standard ethtool support functions. */
981 enum bcmgenet_stat_type {
982 	BCMGENET_STAT_NETDEV = -1,
983 	BCMGENET_STAT_MIB_RX,
984 	BCMGENET_STAT_MIB_TX,
985 	BCMGENET_STAT_RUNT,
986 	BCMGENET_STAT_MISC,
987 	BCMGENET_STAT_SOFT,
988 };
989 
990 struct bcmgenet_stats {
991 	char stat_string[ETH_GSTRING_LEN];
992 	int stat_sizeof;
993 	int stat_offset;
994 	enum bcmgenet_stat_type type;
995 	/* reg offset from UMAC base for misc counters */
996 	u16 reg_offset;
997 };
998 
999 #define STAT_NETDEV(m) { \
1000 	.stat_string = __stringify(m), \
1001 	.stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
1002 	.stat_offset = offsetof(struct net_device_stats, m), \
1003 	.type = BCMGENET_STAT_NETDEV, \
1004 }
1005 
1006 #define STAT_GENET_MIB(str, m, _type) { \
1007 	.stat_string = str, \
1008 	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1009 	.stat_offset = offsetof(struct bcmgenet_priv, m), \
1010 	.type = _type, \
1011 }
1012 
1013 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
1014 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
1015 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
1016 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
1017 
1018 #define STAT_GENET_MISC(str, m, offset) { \
1019 	.stat_string = str, \
1020 	.stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
1021 	.stat_offset = offsetof(struct bcmgenet_priv, m), \
1022 	.type = BCMGENET_STAT_MISC, \
1023 	.reg_offset = offset, \
1024 }
1025 
1026 #define STAT_GENET_Q(num) \
1027 	STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \
1028 			tx_rings[num].packets), \
1029 	STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \
1030 			tx_rings[num].bytes), \
1031 	STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \
1032 			rx_rings[num].bytes),	 \
1033 	STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \
1034 			rx_rings[num].packets), \
1035 	STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \
1036 			rx_rings[num].errors), \
1037 	STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \
1038 			rx_rings[num].dropped)
1039 
1040 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
1041  * between the end of TX stats and the beginning of the RX RUNT
1042  */
1043 #define BCMGENET_STAT_OFFSET	0xc
1044 
1045 /* Hardware counters must be kept in sync because the order/offset
1046  * is important here (order in structure declaration = order in hardware)
1047  */
1048 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
1049 	/* general stats */
1050 	STAT_NETDEV(rx_packets),
1051 	STAT_NETDEV(tx_packets),
1052 	STAT_NETDEV(rx_bytes),
1053 	STAT_NETDEV(tx_bytes),
1054 	STAT_NETDEV(rx_errors),
1055 	STAT_NETDEV(tx_errors),
1056 	STAT_NETDEV(rx_dropped),
1057 	STAT_NETDEV(tx_dropped),
1058 	STAT_NETDEV(multicast),
1059 	/* UniMAC RSV counters */
1060 	STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
1061 	STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
1062 	STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
1063 	STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
1064 	STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
1065 	STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
1066 	STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
1067 	STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
1068 	STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
1069 	STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
1070 	STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
1071 	STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
1072 	STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
1073 	STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
1074 	STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
1075 	STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
1076 	STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
1077 	STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
1078 	STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
1079 	STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
1080 	STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
1081 	STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
1082 	STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
1083 	STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
1084 	STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
1085 	STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
1086 	STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
1087 	STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
1088 	STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
1089 	/* UniMAC TSV counters */
1090 	STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
1091 	STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
1092 	STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
1093 	STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
1094 	STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
1095 	STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
1096 	STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
1097 	STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
1098 	STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
1099 	STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
1100 	STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
1101 	STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
1102 	STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
1103 	STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
1104 	STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
1105 	STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
1106 	STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
1107 	STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
1108 	STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
1109 	STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
1110 	STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
1111 	STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
1112 	STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
1113 	STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
1114 	STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
1115 	STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
1116 	STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
1117 	STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
1118 	STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
1119 	/* UniMAC RUNT counters */
1120 	STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
1121 	STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
1122 	STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
1123 	STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
1124 	/* Misc UniMAC counters */
1125 	STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
1126 			UMAC_RBUF_OVFL_CNT_V1),
1127 	STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt,
1128 			UMAC_RBUF_ERR_CNT_V1),
1129 	STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
1130 	STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
1131 	STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
1132 	STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
1133 	STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb),
1134 	STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed",
1135 			    mib.tx_realloc_tsb_failed),
1136 	/* Per TX queues */
1137 	STAT_GENET_Q(0),
1138 	STAT_GENET_Q(1),
1139 	STAT_GENET_Q(2),
1140 	STAT_GENET_Q(3),
1141 	STAT_GENET_Q(16),
1142 };
1143 
1144 #define BCMGENET_STATS_LEN	ARRAY_SIZE(bcmgenet_gstrings_stats)
1145 
1146 static void bcmgenet_get_drvinfo(struct net_device *dev,
1147 				 struct ethtool_drvinfo *info)
1148 {
1149 	strscpy(info->driver, "bcmgenet", sizeof(info->driver));
1150 }
1151 
1152 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
1153 {
1154 	switch (string_set) {
1155 	case ETH_SS_STATS:
1156 		return BCMGENET_STATS_LEN;
1157 	default:
1158 		return -EOPNOTSUPP;
1159 	}
1160 }
1161 
1162 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
1163 				 u8 *data)
1164 {
1165 	int i;
1166 
1167 	switch (stringset) {
1168 	case ETH_SS_STATS:
1169 		for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1170 			memcpy(data + i * ETH_GSTRING_LEN,
1171 			       bcmgenet_gstrings_stats[i].stat_string,
1172 			       ETH_GSTRING_LEN);
1173 		}
1174 		break;
1175 	}
1176 }
1177 
1178 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset)
1179 {
1180 	u16 new_offset;
1181 	u32 val;
1182 
1183 	switch (offset) {
1184 	case UMAC_RBUF_OVFL_CNT_V1:
1185 		if (GENET_IS_V2(priv))
1186 			new_offset = RBUF_OVFL_CNT_V2;
1187 		else
1188 			new_offset = RBUF_OVFL_CNT_V3PLUS;
1189 
1190 		val = bcmgenet_rbuf_readl(priv,	new_offset);
1191 		/* clear if overflowed */
1192 		if (val == ~0)
1193 			bcmgenet_rbuf_writel(priv, 0, new_offset);
1194 		break;
1195 	case UMAC_RBUF_ERR_CNT_V1:
1196 		if (GENET_IS_V2(priv))
1197 			new_offset = RBUF_ERR_CNT_V2;
1198 		else
1199 			new_offset = RBUF_ERR_CNT_V3PLUS;
1200 
1201 		val = bcmgenet_rbuf_readl(priv,	new_offset);
1202 		/* clear if overflowed */
1203 		if (val == ~0)
1204 			bcmgenet_rbuf_writel(priv, 0, new_offset);
1205 		break;
1206 	default:
1207 		val = bcmgenet_umac_readl(priv, offset);
1208 		/* clear if overflowed */
1209 		if (val == ~0)
1210 			bcmgenet_umac_writel(priv, 0, offset);
1211 		break;
1212 	}
1213 
1214 	return val;
1215 }
1216 
1217 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
1218 {
1219 	int i, j = 0;
1220 
1221 	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1222 		const struct bcmgenet_stats *s;
1223 		u8 offset = 0;
1224 		u32 val = 0;
1225 		char *p;
1226 
1227 		s = &bcmgenet_gstrings_stats[i];
1228 		switch (s->type) {
1229 		case BCMGENET_STAT_NETDEV:
1230 		case BCMGENET_STAT_SOFT:
1231 			continue;
1232 		case BCMGENET_STAT_RUNT:
1233 			offset += BCMGENET_STAT_OFFSET;
1234 			fallthrough;
1235 		case BCMGENET_STAT_MIB_TX:
1236 			offset += BCMGENET_STAT_OFFSET;
1237 			fallthrough;
1238 		case BCMGENET_STAT_MIB_RX:
1239 			val = bcmgenet_umac_readl(priv,
1240 						  UMAC_MIB_START + j + offset);
1241 			offset = 0;	/* Reset Offset */
1242 			break;
1243 		case BCMGENET_STAT_MISC:
1244 			if (GENET_IS_V1(priv)) {
1245 				val = bcmgenet_umac_readl(priv, s->reg_offset);
1246 				/* clear if overflowed */
1247 				if (val == ~0)
1248 					bcmgenet_umac_writel(priv, 0,
1249 							     s->reg_offset);
1250 			} else {
1251 				val = bcmgenet_update_stat_misc(priv,
1252 								s->reg_offset);
1253 			}
1254 			break;
1255 		}
1256 
1257 		j += s->stat_sizeof;
1258 		p = (char *)priv + s->stat_offset;
1259 		*(u32 *)p = val;
1260 	}
1261 }
1262 
1263 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
1264 				       struct ethtool_stats *stats,
1265 				       u64 *data)
1266 {
1267 	struct bcmgenet_priv *priv = netdev_priv(dev);
1268 	int i;
1269 
1270 	if (netif_running(dev))
1271 		bcmgenet_update_mib_counters(priv);
1272 
1273 	dev->netdev_ops->ndo_get_stats(dev);
1274 
1275 	for (i = 0; i < BCMGENET_STATS_LEN; i++) {
1276 		const struct bcmgenet_stats *s;
1277 		char *p;
1278 
1279 		s = &bcmgenet_gstrings_stats[i];
1280 		if (s->type == BCMGENET_STAT_NETDEV)
1281 			p = (char *)&dev->stats;
1282 		else
1283 			p = (char *)priv;
1284 		p += s->stat_offset;
1285 		if (sizeof(unsigned long) != sizeof(u32) &&
1286 		    s->stat_sizeof == sizeof(unsigned long))
1287 			data[i] = *(unsigned long *)p;
1288 		else
1289 			data[i] = *(u32 *)p;
1290 	}
1291 }
1292 
1293 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
1294 {
1295 	struct bcmgenet_priv *priv = netdev_priv(dev);
1296 	u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
1297 	u32 reg;
1298 
1299 	if (enable && !priv->clk_eee_enabled) {
1300 		clk_prepare_enable(priv->clk_eee);
1301 		priv->clk_eee_enabled = true;
1302 	}
1303 
1304 	reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
1305 	if (enable)
1306 		reg |= EEE_EN;
1307 	else
1308 		reg &= ~EEE_EN;
1309 	bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
1310 
1311 	/* Enable EEE and switch to a 27Mhz clock automatically */
1312 	reg = bcmgenet_readl(priv->base + off);
1313 	if (enable)
1314 		reg |= TBUF_EEE_EN | TBUF_PM_EN;
1315 	else
1316 		reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
1317 	bcmgenet_writel(reg, priv->base + off);
1318 
1319 	/* Do the same for thing for RBUF */
1320 	reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
1321 	if (enable)
1322 		reg |= RBUF_EEE_EN | RBUF_PM_EN;
1323 	else
1324 		reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
1325 	bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
1326 
1327 	if (!enable && priv->clk_eee_enabled) {
1328 		clk_disable_unprepare(priv->clk_eee);
1329 		priv->clk_eee_enabled = false;
1330 	}
1331 
1332 	priv->eee.eee_enabled = enable;
1333 	priv->eee.eee_active = enable;
1334 }
1335 
1336 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
1337 {
1338 	struct bcmgenet_priv *priv = netdev_priv(dev);
1339 	struct ethtool_eee *p = &priv->eee;
1340 
1341 	if (GENET_IS_V1(priv))
1342 		return -EOPNOTSUPP;
1343 
1344 	if (!dev->phydev)
1345 		return -ENODEV;
1346 
1347 	e->eee_enabled = p->eee_enabled;
1348 	e->eee_active = p->eee_active;
1349 	e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
1350 
1351 	return phy_ethtool_get_eee(dev->phydev, e);
1352 }
1353 
1354 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
1355 {
1356 	struct bcmgenet_priv *priv = netdev_priv(dev);
1357 	struct ethtool_eee *p = &priv->eee;
1358 	int ret = 0;
1359 
1360 	if (GENET_IS_V1(priv))
1361 		return -EOPNOTSUPP;
1362 
1363 	if (!dev->phydev)
1364 		return -ENODEV;
1365 
1366 	p->eee_enabled = e->eee_enabled;
1367 
1368 	if (!p->eee_enabled) {
1369 		bcmgenet_eee_enable_set(dev, false);
1370 	} else {
1371 		ret = phy_init_eee(dev->phydev, false);
1372 		if (ret) {
1373 			netif_err(priv, hw, dev, "EEE initialization failed\n");
1374 			return ret;
1375 		}
1376 
1377 		bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
1378 		bcmgenet_eee_enable_set(dev, true);
1379 	}
1380 
1381 	return phy_ethtool_set_eee(dev->phydev, e);
1382 }
1383 
1384 static int bcmgenet_validate_flow(struct net_device *dev,
1385 				  struct ethtool_rxnfc *cmd)
1386 {
1387 	struct ethtool_usrip4_spec *l4_mask;
1388 	struct ethhdr *eth_mask;
1389 
1390 	if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) {
1391 		netdev_err(dev, "rxnfc: Invalid location (%d)\n",
1392 			   cmd->fs.location);
1393 		return -EINVAL;
1394 	}
1395 
1396 	switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1397 	case IP_USER_FLOW:
1398 		l4_mask = &cmd->fs.m_u.usr_ip4_spec;
1399 		/* don't allow mask which isn't valid */
1400 		if (VALIDATE_MASK(l4_mask->ip4src) ||
1401 		    VALIDATE_MASK(l4_mask->ip4dst) ||
1402 		    VALIDATE_MASK(l4_mask->l4_4_bytes) ||
1403 		    VALIDATE_MASK(l4_mask->proto) ||
1404 		    VALIDATE_MASK(l4_mask->ip_ver) ||
1405 		    VALIDATE_MASK(l4_mask->tos)) {
1406 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1407 			return -EINVAL;
1408 		}
1409 		break;
1410 	case ETHER_FLOW:
1411 		eth_mask = &cmd->fs.m_u.ether_spec;
1412 		/* don't allow mask which isn't valid */
1413 		if (VALIDATE_MASK(eth_mask->h_dest) ||
1414 		    VALIDATE_MASK(eth_mask->h_source) ||
1415 		    VALIDATE_MASK(eth_mask->h_proto)) {
1416 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1417 			return -EINVAL;
1418 		}
1419 		break;
1420 	default:
1421 		netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n",
1422 			   cmd->fs.flow_type);
1423 		return -EINVAL;
1424 	}
1425 
1426 	if ((cmd->fs.flow_type & FLOW_EXT)) {
1427 		/* don't allow mask which isn't valid */
1428 		if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) ||
1429 		    VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) {
1430 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1431 			return -EINVAL;
1432 		}
1433 		if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) {
1434 			netdev_err(dev, "rxnfc: user-def not supported\n");
1435 			return -EINVAL;
1436 		}
1437 	}
1438 
1439 	if ((cmd->fs.flow_type & FLOW_MAC_EXT)) {
1440 		/* don't allow mask which isn't valid */
1441 		if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) {
1442 			netdev_err(dev, "rxnfc: Unsupported mask\n");
1443 			return -EINVAL;
1444 		}
1445 	}
1446 
1447 	return 0;
1448 }
1449 
1450 static int bcmgenet_insert_flow(struct net_device *dev,
1451 				struct ethtool_rxnfc *cmd)
1452 {
1453 	struct bcmgenet_priv *priv = netdev_priv(dev);
1454 	struct bcmgenet_rxnfc_rule *loc_rule;
1455 	int err;
1456 
1457 	if (priv->hw_params->hfb_filter_size < 128) {
1458 		netdev_err(dev, "rxnfc: Not supported by this device\n");
1459 		return -EINVAL;
1460 	}
1461 
1462 	if (cmd->fs.ring_cookie > priv->hw_params->rx_queues &&
1463 	    cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) {
1464 		netdev_err(dev, "rxnfc: Unsupported action (%llu)\n",
1465 			   cmd->fs.ring_cookie);
1466 		return -EINVAL;
1467 	}
1468 
1469 	err = bcmgenet_validate_flow(dev, cmd);
1470 	if (err)
1471 		return err;
1472 
1473 	loc_rule = &priv->rxnfc_rules[cmd->fs.location];
1474 	if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1475 		bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1476 	if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1477 		list_del(&loc_rule->list);
1478 		bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1479 	}
1480 	loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1481 	memcpy(&loc_rule->fs, &cmd->fs,
1482 	       sizeof(struct ethtool_rx_flow_spec));
1483 
1484 	bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule);
1485 
1486 	list_add_tail(&loc_rule->list, &priv->rxnfc_list);
1487 
1488 	return 0;
1489 }
1490 
1491 static int bcmgenet_delete_flow(struct net_device *dev,
1492 				struct ethtool_rxnfc *cmd)
1493 {
1494 	struct bcmgenet_priv *priv = netdev_priv(dev);
1495 	struct bcmgenet_rxnfc_rule *rule;
1496 	int err = 0;
1497 
1498 	if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1499 		return -EINVAL;
1500 
1501 	rule = &priv->rxnfc_rules[cmd->fs.location];
1502 	if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) {
1503 		err =  -ENOENT;
1504 		goto out;
1505 	}
1506 
1507 	if (rule->state == BCMGENET_RXNFC_STATE_ENABLED)
1508 		bcmgenet_hfb_disable_filter(priv, cmd->fs.location);
1509 	if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) {
1510 		list_del(&rule->list);
1511 		bcmgenet_hfb_clear_filter(priv, cmd->fs.location);
1512 	}
1513 	rule->state = BCMGENET_RXNFC_STATE_UNUSED;
1514 	memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec));
1515 
1516 out:
1517 	return err;
1518 }
1519 
1520 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1521 {
1522 	struct bcmgenet_priv *priv = netdev_priv(dev);
1523 	int err = 0;
1524 
1525 	switch (cmd->cmd) {
1526 	case ETHTOOL_SRXCLSRLINS:
1527 		err = bcmgenet_insert_flow(dev, cmd);
1528 		break;
1529 	case ETHTOOL_SRXCLSRLDEL:
1530 		err = bcmgenet_delete_flow(dev, cmd);
1531 		break;
1532 	default:
1533 		netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n",
1534 			    cmd->cmd);
1535 		return -EINVAL;
1536 	}
1537 
1538 	return err;
1539 }
1540 
1541 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1542 			     int loc)
1543 {
1544 	struct bcmgenet_priv *priv = netdev_priv(dev);
1545 	struct bcmgenet_rxnfc_rule *rule;
1546 	int err = 0;
1547 
1548 	if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1549 		return -EINVAL;
1550 
1551 	rule = &priv->rxnfc_rules[loc];
1552 	if (rule->state == BCMGENET_RXNFC_STATE_UNUSED)
1553 		err = -ENOENT;
1554 	else
1555 		memcpy(&cmd->fs, &rule->fs,
1556 		       sizeof(struct ethtool_rx_flow_spec));
1557 
1558 	return err;
1559 }
1560 
1561 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv)
1562 {
1563 	struct list_head *pos;
1564 	int res = 0;
1565 
1566 	list_for_each(pos, &priv->rxnfc_list)
1567 		res++;
1568 
1569 	return res;
1570 }
1571 
1572 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1573 			      u32 *rule_locs)
1574 {
1575 	struct bcmgenet_priv *priv = netdev_priv(dev);
1576 	struct bcmgenet_rxnfc_rule *rule;
1577 	int err = 0;
1578 	int i = 0;
1579 
1580 	switch (cmd->cmd) {
1581 	case ETHTOOL_GRXRINGS:
1582 		cmd->data = priv->hw_params->rx_queues ?: 1;
1583 		break;
1584 	case ETHTOOL_GRXCLSRLCNT:
1585 		cmd->rule_cnt = bcmgenet_get_num_flows(priv);
1586 		cmd->data = MAX_NUM_OF_FS_RULES;
1587 		break;
1588 	case ETHTOOL_GRXCLSRULE:
1589 		err = bcmgenet_get_flow(dev, cmd, cmd->fs.location);
1590 		break;
1591 	case ETHTOOL_GRXCLSRLALL:
1592 		list_for_each_entry(rule, &priv->rxnfc_list, list)
1593 			if (i < cmd->rule_cnt)
1594 				rule_locs[i++] = rule->fs.location;
1595 		cmd->rule_cnt = i;
1596 		cmd->data = MAX_NUM_OF_FS_RULES;
1597 		break;
1598 	default:
1599 		err = -EOPNOTSUPP;
1600 		break;
1601 	}
1602 
1603 	return err;
1604 }
1605 
1606 /* standard ethtool support functions. */
1607 static const struct ethtool_ops bcmgenet_ethtool_ops = {
1608 	.supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS |
1609 				     ETHTOOL_COALESCE_MAX_FRAMES |
1610 				     ETHTOOL_COALESCE_USE_ADAPTIVE_RX,
1611 	.begin			= bcmgenet_begin,
1612 	.complete		= bcmgenet_complete,
1613 	.get_strings		= bcmgenet_get_strings,
1614 	.get_sset_count		= bcmgenet_get_sset_count,
1615 	.get_ethtool_stats	= bcmgenet_get_ethtool_stats,
1616 	.get_drvinfo		= bcmgenet_get_drvinfo,
1617 	.get_link		= ethtool_op_get_link,
1618 	.get_msglevel		= bcmgenet_get_msglevel,
1619 	.set_msglevel		= bcmgenet_set_msglevel,
1620 	.get_wol		= bcmgenet_get_wol,
1621 	.set_wol		= bcmgenet_set_wol,
1622 	.get_eee		= bcmgenet_get_eee,
1623 	.set_eee		= bcmgenet_set_eee,
1624 	.nway_reset		= phy_ethtool_nway_reset,
1625 	.get_coalesce		= bcmgenet_get_coalesce,
1626 	.set_coalesce		= bcmgenet_set_coalesce,
1627 	.get_link_ksettings	= bcmgenet_get_link_ksettings,
1628 	.set_link_ksettings	= bcmgenet_set_link_ksettings,
1629 	.get_ts_info		= ethtool_op_get_ts_info,
1630 	.get_rxnfc		= bcmgenet_get_rxnfc,
1631 	.set_rxnfc		= bcmgenet_set_rxnfc,
1632 	.get_pauseparam		= bcmgenet_get_pauseparam,
1633 	.set_pauseparam		= bcmgenet_set_pauseparam,
1634 };
1635 
1636 /* Power down the unimac, based on mode. */
1637 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
1638 				enum bcmgenet_power_mode mode)
1639 {
1640 	int ret = 0;
1641 	u32 reg;
1642 
1643 	switch (mode) {
1644 	case GENET_POWER_CABLE_SENSE:
1645 		phy_detach(priv->dev->phydev);
1646 		break;
1647 
1648 	case GENET_POWER_WOL_MAGIC:
1649 		ret = bcmgenet_wol_power_down_cfg(priv, mode);
1650 		break;
1651 
1652 	case GENET_POWER_PASSIVE:
1653 		/* Power down LED */
1654 		if (priv->hw_params->flags & GENET_HAS_EXT) {
1655 			reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1656 			if (GENET_IS_V5(priv) && !priv->ephy_16nm)
1657 				reg |= EXT_PWR_DOWN_PHY_EN |
1658 				       EXT_PWR_DOWN_PHY_RD |
1659 				       EXT_PWR_DOWN_PHY_SD |
1660 				       EXT_PWR_DOWN_PHY_RX |
1661 				       EXT_PWR_DOWN_PHY_TX |
1662 				       EXT_IDDQ_GLBL_PWR;
1663 			else
1664 				reg |= EXT_PWR_DOWN_PHY;
1665 
1666 			reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1667 			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1668 
1669 			bcmgenet_phy_power_set(priv->dev, false);
1670 		}
1671 		break;
1672 	default:
1673 		break;
1674 	}
1675 
1676 	return ret;
1677 }
1678 
1679 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1680 			      enum bcmgenet_power_mode mode)
1681 {
1682 	u32 reg;
1683 
1684 	if (!(priv->hw_params->flags & GENET_HAS_EXT))
1685 		return;
1686 
1687 	reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1688 
1689 	switch (mode) {
1690 	case GENET_POWER_PASSIVE:
1691 		reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS |
1692 			 EXT_ENERGY_DET_MASK);
1693 		if (GENET_IS_V5(priv) && !priv->ephy_16nm) {
1694 			reg &= ~(EXT_PWR_DOWN_PHY_EN |
1695 				 EXT_PWR_DOWN_PHY_RD |
1696 				 EXT_PWR_DOWN_PHY_SD |
1697 				 EXT_PWR_DOWN_PHY_RX |
1698 				 EXT_PWR_DOWN_PHY_TX |
1699 				 EXT_IDDQ_GLBL_PWR);
1700 			reg |=   EXT_PHY_RESET;
1701 			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1702 			mdelay(1);
1703 
1704 			reg &=  ~EXT_PHY_RESET;
1705 		} else {
1706 			reg &= ~EXT_PWR_DOWN_PHY;
1707 			reg |= EXT_PWR_DN_EN_LD;
1708 		}
1709 		bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1710 		bcmgenet_phy_power_set(priv->dev, true);
1711 		break;
1712 
1713 	case GENET_POWER_CABLE_SENSE:
1714 		/* enable APD */
1715 		if (!GENET_IS_V5(priv)) {
1716 			reg |= EXT_PWR_DN_EN_LD;
1717 			bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1718 		}
1719 		break;
1720 	case GENET_POWER_WOL_MAGIC:
1721 		bcmgenet_wol_power_up_cfg(priv, mode);
1722 		return;
1723 	default:
1724 		break;
1725 	}
1726 }
1727 
1728 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1729 					 struct bcmgenet_tx_ring *ring)
1730 {
1731 	struct enet_cb *tx_cb_ptr;
1732 
1733 	tx_cb_ptr = ring->cbs;
1734 	tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1735 
1736 	/* Advancing local write pointer */
1737 	if (ring->write_ptr == ring->end_ptr)
1738 		ring->write_ptr = ring->cb_ptr;
1739 	else
1740 		ring->write_ptr++;
1741 
1742 	return tx_cb_ptr;
1743 }
1744 
1745 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv,
1746 					 struct bcmgenet_tx_ring *ring)
1747 {
1748 	struct enet_cb *tx_cb_ptr;
1749 
1750 	tx_cb_ptr = ring->cbs;
1751 	tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1752 
1753 	/* Rewinding local write pointer */
1754 	if (ring->write_ptr == ring->cb_ptr)
1755 		ring->write_ptr = ring->end_ptr;
1756 	else
1757 		ring->write_ptr--;
1758 
1759 	return tx_cb_ptr;
1760 }
1761 
1762 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1763 {
1764 	bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1765 				 INTRL2_CPU_MASK_SET);
1766 }
1767 
1768 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1769 {
1770 	bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1771 				 INTRL2_CPU_MASK_CLEAR);
1772 }
1773 
1774 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1775 {
1776 	bcmgenet_intrl2_1_writel(ring->priv,
1777 				 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1778 				 INTRL2_CPU_MASK_SET);
1779 }
1780 
1781 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1782 {
1783 	bcmgenet_intrl2_1_writel(ring->priv,
1784 				 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1785 				 INTRL2_CPU_MASK_CLEAR);
1786 }
1787 
1788 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1789 {
1790 	bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1791 				 INTRL2_CPU_MASK_SET);
1792 }
1793 
1794 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1795 {
1796 	bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1797 				 INTRL2_CPU_MASK_CLEAR);
1798 }
1799 
1800 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1801 {
1802 	bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1803 				 INTRL2_CPU_MASK_CLEAR);
1804 }
1805 
1806 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1807 {
1808 	bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1809 				 INTRL2_CPU_MASK_SET);
1810 }
1811 
1812 /* Simple helper to free a transmit control block's resources
1813  * Returns an skb when the last transmit control block associated with the
1814  * skb is freed.  The skb should be freed by the caller if necessary.
1815  */
1816 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev,
1817 					   struct enet_cb *cb)
1818 {
1819 	struct sk_buff *skb;
1820 
1821 	skb = cb->skb;
1822 
1823 	if (skb) {
1824 		cb->skb = NULL;
1825 		if (cb == GENET_CB(skb)->first_cb)
1826 			dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1827 					 dma_unmap_len(cb, dma_len),
1828 					 DMA_TO_DEVICE);
1829 		else
1830 			dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr),
1831 				       dma_unmap_len(cb, dma_len),
1832 				       DMA_TO_DEVICE);
1833 		dma_unmap_addr_set(cb, dma_addr, 0);
1834 
1835 		if (cb == GENET_CB(skb)->last_cb)
1836 			return skb;
1837 
1838 	} else if (dma_unmap_addr(cb, dma_addr)) {
1839 		dma_unmap_page(dev,
1840 			       dma_unmap_addr(cb, dma_addr),
1841 			       dma_unmap_len(cb, dma_len),
1842 			       DMA_TO_DEVICE);
1843 		dma_unmap_addr_set(cb, dma_addr, 0);
1844 	}
1845 
1846 	return NULL;
1847 }
1848 
1849 /* Simple helper to free a receive control block's resources */
1850 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev,
1851 					   struct enet_cb *cb)
1852 {
1853 	struct sk_buff *skb;
1854 
1855 	skb = cb->skb;
1856 	cb->skb = NULL;
1857 
1858 	if (dma_unmap_addr(cb, dma_addr)) {
1859 		dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr),
1860 				 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE);
1861 		dma_unmap_addr_set(cb, dma_addr, 0);
1862 	}
1863 
1864 	return skb;
1865 }
1866 
1867 /* Unlocked version of the reclaim routine */
1868 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1869 					  struct bcmgenet_tx_ring *ring)
1870 {
1871 	struct bcmgenet_priv *priv = netdev_priv(dev);
1872 	unsigned int txbds_processed = 0;
1873 	unsigned int bytes_compl = 0;
1874 	unsigned int pkts_compl = 0;
1875 	unsigned int txbds_ready;
1876 	unsigned int c_index;
1877 	struct sk_buff *skb;
1878 
1879 	/* Clear status before servicing to reduce spurious interrupts */
1880 	if (ring->index == DESC_INDEX)
1881 		bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE,
1882 					 INTRL2_CPU_CLEAR);
1883 	else
1884 		bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
1885 					 INTRL2_CPU_CLEAR);
1886 
1887 	/* Compute how many buffers are transmitted since last xmit call */
1888 	c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX)
1889 		& DMA_C_INDEX_MASK;
1890 	txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK;
1891 
1892 	netif_dbg(priv, tx_done, dev,
1893 		  "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1894 		  __func__, ring->index, ring->c_index, c_index, txbds_ready);
1895 
1896 	/* Reclaim transmitted buffers */
1897 	while (txbds_processed < txbds_ready) {
1898 		skb = bcmgenet_free_tx_cb(&priv->pdev->dev,
1899 					  &priv->tx_cbs[ring->clean_ptr]);
1900 		if (skb) {
1901 			pkts_compl++;
1902 			bytes_compl += GENET_CB(skb)->bytes_sent;
1903 			dev_consume_skb_any(skb);
1904 		}
1905 
1906 		txbds_processed++;
1907 		if (likely(ring->clean_ptr < ring->end_ptr))
1908 			ring->clean_ptr++;
1909 		else
1910 			ring->clean_ptr = ring->cb_ptr;
1911 	}
1912 
1913 	ring->free_bds += txbds_processed;
1914 	ring->c_index = c_index;
1915 
1916 	ring->packets += pkts_compl;
1917 	ring->bytes += bytes_compl;
1918 
1919 	netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue),
1920 				  pkts_compl, bytes_compl);
1921 
1922 	return txbds_processed;
1923 }
1924 
1925 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1926 				struct bcmgenet_tx_ring *ring)
1927 {
1928 	unsigned int released;
1929 
1930 	spin_lock_bh(&ring->lock);
1931 	released = __bcmgenet_tx_reclaim(dev, ring);
1932 	spin_unlock_bh(&ring->lock);
1933 
1934 	return released;
1935 }
1936 
1937 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1938 {
1939 	struct bcmgenet_tx_ring *ring =
1940 		container_of(napi, struct bcmgenet_tx_ring, napi);
1941 	unsigned int work_done = 0;
1942 	struct netdev_queue *txq;
1943 
1944 	spin_lock(&ring->lock);
1945 	work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring);
1946 	if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1947 		txq = netdev_get_tx_queue(ring->priv->dev, ring->queue);
1948 		netif_tx_wake_queue(txq);
1949 	}
1950 	spin_unlock(&ring->lock);
1951 
1952 	if (work_done == 0) {
1953 		napi_complete(napi);
1954 		ring->int_enable(ring);
1955 
1956 		return 0;
1957 	}
1958 
1959 	return budget;
1960 }
1961 
1962 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1963 {
1964 	struct bcmgenet_priv *priv = netdev_priv(dev);
1965 	int i;
1966 
1967 	if (netif_is_multiqueue(dev)) {
1968 		for (i = 0; i < priv->hw_params->tx_queues; i++)
1969 			bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1970 	}
1971 
1972 	bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1973 }
1974 
1975 /* Reallocate the SKB to put enough headroom in front of it and insert
1976  * the transmit checksum offsets in the descriptors
1977  */
1978 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev,
1979 					struct sk_buff *skb)
1980 {
1981 	struct bcmgenet_priv *priv = netdev_priv(dev);
1982 	struct status_64 *status = NULL;
1983 	struct sk_buff *new_skb;
1984 	u16 offset;
1985 	u8 ip_proto;
1986 	__be16 ip_ver;
1987 	u32 tx_csum_info;
1988 
1989 	if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1990 		/* If 64 byte status block enabled, must make sure skb has
1991 		 * enough headroom for us to insert 64B status block.
1992 		 */
1993 		new_skb = skb_realloc_headroom(skb, sizeof(*status));
1994 		if (!new_skb) {
1995 			dev_kfree_skb_any(skb);
1996 			priv->mib.tx_realloc_tsb_failed++;
1997 			dev->stats.tx_dropped++;
1998 			return NULL;
1999 		}
2000 		dev_consume_skb_any(skb);
2001 		skb = new_skb;
2002 		priv->mib.tx_realloc_tsb++;
2003 	}
2004 
2005 	skb_push(skb, sizeof(*status));
2006 	status = (struct status_64 *)skb->data;
2007 
2008 	if (skb->ip_summed  == CHECKSUM_PARTIAL) {
2009 		ip_ver = skb->protocol;
2010 		switch (ip_ver) {
2011 		case htons(ETH_P_IP):
2012 			ip_proto = ip_hdr(skb)->protocol;
2013 			break;
2014 		case htons(ETH_P_IPV6):
2015 			ip_proto = ipv6_hdr(skb)->nexthdr;
2016 			break;
2017 		default:
2018 			/* don't use UDP flag */
2019 			ip_proto = 0;
2020 			break;
2021 		}
2022 
2023 		offset = skb_checksum_start_offset(skb) - sizeof(*status);
2024 		tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
2025 				(offset + skb->csum_offset) |
2026 				STATUS_TX_CSUM_LV;
2027 
2028 		/* Set the special UDP flag for UDP */
2029 		if (ip_proto == IPPROTO_UDP)
2030 			tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
2031 
2032 		status->tx_csum_info = tx_csum_info;
2033 	}
2034 
2035 	return skb;
2036 }
2037 
2038 static void bcmgenet_hide_tsb(struct sk_buff *skb)
2039 {
2040 	__skb_pull(skb, sizeof(struct status_64));
2041 }
2042 
2043 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
2044 {
2045 	struct bcmgenet_priv *priv = netdev_priv(dev);
2046 	struct device *kdev = &priv->pdev->dev;
2047 	struct bcmgenet_tx_ring *ring = NULL;
2048 	struct enet_cb *tx_cb_ptr;
2049 	struct netdev_queue *txq;
2050 	int nr_frags, index;
2051 	dma_addr_t mapping;
2052 	unsigned int size;
2053 	skb_frag_t *frag;
2054 	u32 len_stat;
2055 	int ret;
2056 	int i;
2057 
2058 	index = skb_get_queue_mapping(skb);
2059 	/* Mapping strategy:
2060 	 * queue_mapping = 0, unclassified, packet xmited through ring16
2061 	 * queue_mapping = 1, goes to ring 0. (highest priority queue
2062 	 * queue_mapping = 2, goes to ring 1.
2063 	 * queue_mapping = 3, goes to ring 2.
2064 	 * queue_mapping = 4, goes to ring 3.
2065 	 */
2066 	if (index == 0)
2067 		index = DESC_INDEX;
2068 	else
2069 		index -= 1;
2070 
2071 	ring = &priv->tx_rings[index];
2072 	txq = netdev_get_tx_queue(dev, ring->queue);
2073 
2074 	nr_frags = skb_shinfo(skb)->nr_frags;
2075 
2076 	spin_lock(&ring->lock);
2077 	if (ring->free_bds <= (nr_frags + 1)) {
2078 		if (!netif_tx_queue_stopped(txq)) {
2079 			netif_tx_stop_queue(txq);
2080 			netdev_err(dev,
2081 				   "%s: tx ring %d full when queue %d awake\n",
2082 				   __func__, index, ring->queue);
2083 		}
2084 		ret = NETDEV_TX_BUSY;
2085 		goto out;
2086 	}
2087 
2088 	/* Retain how many bytes will be sent on the wire, without TSB inserted
2089 	 * by transmit checksum offload
2090 	 */
2091 	GENET_CB(skb)->bytes_sent = skb->len;
2092 
2093 	/* add the Transmit Status Block */
2094 	skb = bcmgenet_add_tsb(dev, skb);
2095 	if (!skb) {
2096 		ret = NETDEV_TX_OK;
2097 		goto out;
2098 	}
2099 
2100 	for (i = 0; i <= nr_frags; i++) {
2101 		tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
2102 
2103 		BUG_ON(!tx_cb_ptr);
2104 
2105 		if (!i) {
2106 			/* Transmit single SKB or head of fragment list */
2107 			GENET_CB(skb)->first_cb = tx_cb_ptr;
2108 			size = skb_headlen(skb);
2109 			mapping = dma_map_single(kdev, skb->data, size,
2110 						 DMA_TO_DEVICE);
2111 		} else {
2112 			/* xmit fragment */
2113 			frag = &skb_shinfo(skb)->frags[i - 1];
2114 			size = skb_frag_size(frag);
2115 			mapping = skb_frag_dma_map(kdev, frag, 0, size,
2116 						   DMA_TO_DEVICE);
2117 		}
2118 
2119 		ret = dma_mapping_error(kdev, mapping);
2120 		if (ret) {
2121 			priv->mib.tx_dma_failed++;
2122 			netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
2123 			ret = NETDEV_TX_OK;
2124 			goto out_unmap_frags;
2125 		}
2126 		dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
2127 		dma_unmap_len_set(tx_cb_ptr, dma_len, size);
2128 
2129 		tx_cb_ptr->skb = skb;
2130 
2131 		len_stat = (size << DMA_BUFLENGTH_SHIFT) |
2132 			   (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT);
2133 
2134 		/* Note: if we ever change from DMA_TX_APPEND_CRC below we
2135 		 * will need to restore software padding of "runt" packets
2136 		 */
2137 		if (!i) {
2138 			len_stat |= DMA_TX_APPEND_CRC | DMA_SOP;
2139 			if (skb->ip_summed == CHECKSUM_PARTIAL)
2140 				len_stat |= DMA_TX_DO_CSUM;
2141 		}
2142 		if (i == nr_frags)
2143 			len_stat |= DMA_EOP;
2144 
2145 		dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat);
2146 	}
2147 
2148 	GENET_CB(skb)->last_cb = tx_cb_ptr;
2149 
2150 	bcmgenet_hide_tsb(skb);
2151 	skb_tx_timestamp(skb);
2152 
2153 	/* Decrement total BD count and advance our write pointer */
2154 	ring->free_bds -= nr_frags + 1;
2155 	ring->prod_index += nr_frags + 1;
2156 	ring->prod_index &= DMA_P_INDEX_MASK;
2157 
2158 	netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
2159 
2160 	if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
2161 		netif_tx_stop_queue(txq);
2162 
2163 	if (!netdev_xmit_more() || netif_xmit_stopped(txq))
2164 		/* Packets are ready, update producer index */
2165 		bcmgenet_tdma_ring_writel(priv, ring->index,
2166 					  ring->prod_index, TDMA_PROD_INDEX);
2167 out:
2168 	spin_unlock(&ring->lock);
2169 
2170 	return ret;
2171 
2172 out_unmap_frags:
2173 	/* Back up for failed control block mapping */
2174 	bcmgenet_put_txcb(priv, ring);
2175 
2176 	/* Unmap successfully mapped control blocks */
2177 	while (i-- > 0) {
2178 		tx_cb_ptr = bcmgenet_put_txcb(priv, ring);
2179 		bcmgenet_free_tx_cb(kdev, tx_cb_ptr);
2180 	}
2181 
2182 	dev_kfree_skb(skb);
2183 	goto out;
2184 }
2185 
2186 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
2187 					  struct enet_cb *cb)
2188 {
2189 	struct device *kdev = &priv->pdev->dev;
2190 	struct sk_buff *skb;
2191 	struct sk_buff *rx_skb;
2192 	dma_addr_t mapping;
2193 
2194 	/* Allocate a new Rx skb */
2195 	skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT,
2196 				 GFP_ATOMIC | __GFP_NOWARN);
2197 	if (!skb) {
2198 		priv->mib.alloc_rx_buff_failed++;
2199 		netif_err(priv, rx_err, priv->dev,
2200 			  "%s: Rx skb allocation failed\n", __func__);
2201 		return NULL;
2202 	}
2203 
2204 	/* DMA-map the new Rx skb */
2205 	mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
2206 				 DMA_FROM_DEVICE);
2207 	if (dma_mapping_error(kdev, mapping)) {
2208 		priv->mib.rx_dma_failed++;
2209 		dev_kfree_skb_any(skb);
2210 		netif_err(priv, rx_err, priv->dev,
2211 			  "%s: Rx skb DMA mapping failed\n", __func__);
2212 		return NULL;
2213 	}
2214 
2215 	/* Grab the current Rx skb from the ring and DMA-unmap it */
2216 	rx_skb = bcmgenet_free_rx_cb(kdev, cb);
2217 
2218 	/* Put the new Rx skb on the ring */
2219 	cb->skb = skb;
2220 	dma_unmap_addr_set(cb, dma_addr, mapping);
2221 	dma_unmap_len_set(cb, dma_len, priv->rx_buf_len);
2222 	dmadesc_set_addr(priv, cb->bd_addr, mapping);
2223 
2224 	/* Return the current Rx skb to caller */
2225 	return rx_skb;
2226 }
2227 
2228 /* bcmgenet_desc_rx - descriptor based rx process.
2229  * this could be called from bottom half, or from NAPI polling method.
2230  */
2231 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
2232 				     unsigned int budget)
2233 {
2234 	struct bcmgenet_priv *priv = ring->priv;
2235 	struct net_device *dev = priv->dev;
2236 	struct enet_cb *cb;
2237 	struct sk_buff *skb;
2238 	u32 dma_length_status;
2239 	unsigned long dma_flag;
2240 	int len;
2241 	unsigned int rxpktprocessed = 0, rxpkttoprocess;
2242 	unsigned int bytes_processed = 0;
2243 	unsigned int p_index, mask;
2244 	unsigned int discards;
2245 
2246 	/* Clear status before servicing to reduce spurious interrupts */
2247 	if (ring->index == DESC_INDEX) {
2248 		bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE,
2249 					 INTRL2_CPU_CLEAR);
2250 	} else {
2251 		mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index);
2252 		bcmgenet_intrl2_1_writel(priv,
2253 					 mask,
2254 					 INTRL2_CPU_CLEAR);
2255 	}
2256 
2257 	p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
2258 
2259 	discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
2260 		   DMA_P_INDEX_DISCARD_CNT_MASK;
2261 	if (discards > ring->old_discards) {
2262 		discards = discards - ring->old_discards;
2263 		ring->errors += discards;
2264 		ring->old_discards += discards;
2265 
2266 		/* Clear HW register when we reach 75% of maximum 0xFFFF */
2267 		if (ring->old_discards >= 0xC000) {
2268 			ring->old_discards = 0;
2269 			bcmgenet_rdma_ring_writel(priv, ring->index, 0,
2270 						  RDMA_PROD_INDEX);
2271 		}
2272 	}
2273 
2274 	p_index &= DMA_P_INDEX_MASK;
2275 	rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK;
2276 
2277 	netif_dbg(priv, rx_status, dev,
2278 		  "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
2279 
2280 	while ((rxpktprocessed < rxpkttoprocess) &&
2281 	       (rxpktprocessed < budget)) {
2282 		struct status_64 *status;
2283 		__be16 rx_csum;
2284 
2285 		cb = &priv->rx_cbs[ring->read_ptr];
2286 		skb = bcmgenet_rx_refill(priv, cb);
2287 
2288 		if (unlikely(!skb)) {
2289 			ring->dropped++;
2290 			goto next;
2291 		}
2292 
2293 		status = (struct status_64 *)skb->data;
2294 		dma_length_status = status->length_status;
2295 		if (dev->features & NETIF_F_RXCSUM) {
2296 			rx_csum = (__force __be16)(status->rx_csum & 0xffff);
2297 			if (rx_csum) {
2298 				skb->csum = (__force __wsum)ntohs(rx_csum);
2299 				skb->ip_summed = CHECKSUM_COMPLETE;
2300 			}
2301 		}
2302 
2303 		/* DMA flags and length are still valid no matter how
2304 		 * we got the Receive Status Vector (64B RSB or register)
2305 		 */
2306 		dma_flag = dma_length_status & 0xffff;
2307 		len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
2308 
2309 		netif_dbg(priv, rx_status, dev,
2310 			  "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
2311 			  __func__, p_index, ring->c_index,
2312 			  ring->read_ptr, dma_length_status);
2313 
2314 		if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
2315 			netif_err(priv, rx_status, dev,
2316 				  "dropping fragmented packet!\n");
2317 			ring->errors++;
2318 			dev_kfree_skb_any(skb);
2319 			goto next;
2320 		}
2321 
2322 		/* report errors */
2323 		if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
2324 						DMA_RX_OV |
2325 						DMA_RX_NO |
2326 						DMA_RX_LG |
2327 						DMA_RX_RXER))) {
2328 			netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
2329 				  (unsigned int)dma_flag);
2330 			if (dma_flag & DMA_RX_CRC_ERROR)
2331 				dev->stats.rx_crc_errors++;
2332 			if (dma_flag & DMA_RX_OV)
2333 				dev->stats.rx_over_errors++;
2334 			if (dma_flag & DMA_RX_NO)
2335 				dev->stats.rx_frame_errors++;
2336 			if (dma_flag & DMA_RX_LG)
2337 				dev->stats.rx_length_errors++;
2338 			dev->stats.rx_errors++;
2339 			dev_kfree_skb_any(skb);
2340 			goto next;
2341 		} /* error packet */
2342 
2343 		skb_put(skb, len);
2344 
2345 		/* remove RSB and hardware 2bytes added for IP alignment */
2346 		skb_pull(skb, 66);
2347 		len -= 66;
2348 
2349 		if (priv->crc_fwd_en) {
2350 			skb_trim(skb, len - ETH_FCS_LEN);
2351 			len -= ETH_FCS_LEN;
2352 		}
2353 
2354 		bytes_processed += len;
2355 
2356 		/*Finish setting up the received SKB and send it to the kernel*/
2357 		skb->protocol = eth_type_trans(skb, priv->dev);
2358 		ring->packets++;
2359 		ring->bytes += len;
2360 		if (dma_flag & DMA_RX_MULT)
2361 			dev->stats.multicast++;
2362 
2363 		/* Notify kernel */
2364 		napi_gro_receive(&ring->napi, skb);
2365 		netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
2366 
2367 next:
2368 		rxpktprocessed++;
2369 		if (likely(ring->read_ptr < ring->end_ptr))
2370 			ring->read_ptr++;
2371 		else
2372 			ring->read_ptr = ring->cb_ptr;
2373 
2374 		ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
2375 		bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
2376 	}
2377 
2378 	ring->dim.bytes = bytes_processed;
2379 	ring->dim.packets = rxpktprocessed;
2380 
2381 	return rxpktprocessed;
2382 }
2383 
2384 /* Rx NAPI polling method */
2385 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
2386 {
2387 	struct bcmgenet_rx_ring *ring = container_of(napi,
2388 			struct bcmgenet_rx_ring, napi);
2389 	struct dim_sample dim_sample = {};
2390 	unsigned int work_done;
2391 
2392 	work_done = bcmgenet_desc_rx(ring, budget);
2393 
2394 	if (work_done < budget) {
2395 		napi_complete_done(napi, work_done);
2396 		ring->int_enable(ring);
2397 	}
2398 
2399 	if (ring->dim.use_dim) {
2400 		dim_update_sample(ring->dim.event_ctr, ring->dim.packets,
2401 				  ring->dim.bytes, &dim_sample);
2402 		net_dim(&ring->dim.dim, dim_sample);
2403 	}
2404 
2405 	return work_done;
2406 }
2407 
2408 static void bcmgenet_dim_work(struct work_struct *work)
2409 {
2410 	struct dim *dim = container_of(work, struct dim, work);
2411 	struct bcmgenet_net_dim *ndim =
2412 			container_of(dim, struct bcmgenet_net_dim, dim);
2413 	struct bcmgenet_rx_ring *ring =
2414 			container_of(ndim, struct bcmgenet_rx_ring, dim);
2415 	struct dim_cq_moder cur_profile =
2416 			net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
2417 
2418 	bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts);
2419 	dim->state = DIM_START_MEASURE;
2420 }
2421 
2422 /* Assign skb to RX DMA descriptor. */
2423 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
2424 				     struct bcmgenet_rx_ring *ring)
2425 {
2426 	struct enet_cb *cb;
2427 	struct sk_buff *skb;
2428 	int i;
2429 
2430 	netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2431 
2432 	/* loop here for each buffer needing assign */
2433 	for (i = 0; i < ring->size; i++) {
2434 		cb = ring->cbs + i;
2435 		skb = bcmgenet_rx_refill(priv, cb);
2436 		if (skb)
2437 			dev_consume_skb_any(skb);
2438 		if (!cb->skb)
2439 			return -ENOMEM;
2440 	}
2441 
2442 	return 0;
2443 }
2444 
2445 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
2446 {
2447 	struct sk_buff *skb;
2448 	struct enet_cb *cb;
2449 	int i;
2450 
2451 	for (i = 0; i < priv->num_rx_bds; i++) {
2452 		cb = &priv->rx_cbs[i];
2453 
2454 		skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb);
2455 		if (skb)
2456 			dev_consume_skb_any(skb);
2457 	}
2458 }
2459 
2460 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
2461 {
2462 	u32 reg;
2463 
2464 	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2465 	if (reg & CMD_SW_RESET)
2466 		return;
2467 	if (enable)
2468 		reg |= mask;
2469 	else
2470 		reg &= ~mask;
2471 	bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2472 
2473 	/* UniMAC stops on a packet boundary, wait for a full-size packet
2474 	 * to be processed
2475 	 */
2476 	if (enable == 0)
2477 		usleep_range(1000, 2000);
2478 }
2479 
2480 static void reset_umac(struct bcmgenet_priv *priv)
2481 {
2482 	/* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
2483 	bcmgenet_rbuf_ctrl_set(priv, 0);
2484 	udelay(10);
2485 
2486 	/* issue soft reset and disable MAC while updating its registers */
2487 	bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
2488 	udelay(2);
2489 }
2490 
2491 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
2492 {
2493 	/* Mask all interrupts.*/
2494 	bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2495 	bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2496 	bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
2497 	bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
2498 }
2499 
2500 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
2501 {
2502 	u32 int0_enable = 0;
2503 
2504 	/* Monitor cable plug/unplugged event for internal PHY, external PHY
2505 	 * and MoCA PHY
2506 	 */
2507 	if (priv->internal_phy) {
2508 		int0_enable |= UMAC_IRQ_LINK_EVENT;
2509 		if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv))
2510 			int0_enable |= UMAC_IRQ_PHY_DET_R;
2511 	} else if (priv->ext_phy) {
2512 		int0_enable |= UMAC_IRQ_LINK_EVENT;
2513 	} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2514 		if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
2515 			int0_enable |= UMAC_IRQ_LINK_EVENT;
2516 	}
2517 	bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2518 }
2519 
2520 static void init_umac(struct bcmgenet_priv *priv)
2521 {
2522 	struct device *kdev = &priv->pdev->dev;
2523 	u32 reg;
2524 	u32 int0_enable = 0;
2525 
2526 	dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
2527 
2528 	reset_umac(priv);
2529 
2530 	/* clear tx/rx counter */
2531 	bcmgenet_umac_writel(priv,
2532 			     MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
2533 			     UMAC_MIB_CTRL);
2534 	bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
2535 
2536 	bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2537 
2538 	/* init tx registers, enable TSB */
2539 	reg = bcmgenet_tbuf_ctrl_get(priv);
2540 	reg |= TBUF_64B_EN;
2541 	bcmgenet_tbuf_ctrl_set(priv, reg);
2542 
2543 	/* init rx registers, enable ip header optimization and RSB */
2544 	reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
2545 	reg |= RBUF_ALIGN_2B | RBUF_64B_EN;
2546 	bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
2547 
2548 	/* enable rx checksumming */
2549 	reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
2550 	reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS;
2551 	/* If UniMAC forwards CRC, we need to skip over it to get
2552 	 * a valid CHK bit to be set in the per-packet status word
2553 	 */
2554 	if (priv->crc_fwd_en)
2555 		reg |= RBUF_SKIP_FCS;
2556 	else
2557 		reg &= ~RBUF_SKIP_FCS;
2558 	bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL);
2559 
2560 	if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
2561 		bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
2562 
2563 	bcmgenet_intr_disable(priv);
2564 
2565 	/* Configure backpressure vectors for MoCA */
2566 	if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
2567 		reg = bcmgenet_bp_mc_get(priv);
2568 		reg |= BIT(priv->hw_params->bp_in_en_shift);
2569 
2570 		/* bp_mask: back pressure mask */
2571 		if (netif_is_multiqueue(priv->dev))
2572 			reg |= priv->hw_params->bp_in_mask;
2573 		else
2574 			reg &= ~priv->hw_params->bp_in_mask;
2575 		bcmgenet_bp_mc_set(priv, reg);
2576 	}
2577 
2578 	/* Enable MDIO interrupts on GENET v3+ */
2579 	if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
2580 		int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2581 
2582 	bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2583 
2584 	dev_dbg(kdev, "done init umac\n");
2585 }
2586 
2587 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring,
2588 			      void (*cb)(struct work_struct *work))
2589 {
2590 	struct bcmgenet_net_dim *dim = &ring->dim;
2591 
2592 	INIT_WORK(&dim->dim.work, cb);
2593 	dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2594 	dim->event_ctr = 0;
2595 	dim->packets = 0;
2596 	dim->bytes = 0;
2597 }
2598 
2599 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring)
2600 {
2601 	struct bcmgenet_net_dim *dim = &ring->dim;
2602 	struct dim_cq_moder moder;
2603 	u32 usecs, pkts;
2604 
2605 	usecs = ring->rx_coalesce_usecs;
2606 	pkts = ring->rx_max_coalesced_frames;
2607 
2608 	/* If DIM was enabled, re-apply default parameters */
2609 	if (dim->use_dim) {
2610 		moder = net_dim_get_def_rx_moderation(dim->dim.mode);
2611 		usecs = moder.usec;
2612 		pkts = moder.pkts;
2613 	}
2614 
2615 	bcmgenet_set_rx_coalesce(ring, usecs, pkts);
2616 }
2617 
2618 /* Initialize a Tx ring along with corresponding hardware registers */
2619 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
2620 				  unsigned int index, unsigned int size,
2621 				  unsigned int start_ptr, unsigned int end_ptr)
2622 {
2623 	struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
2624 	u32 words_per_bd = WORDS_PER_BD(priv);
2625 	u32 flow_period_val = 0;
2626 
2627 	spin_lock_init(&ring->lock);
2628 	ring->priv = priv;
2629 	ring->index = index;
2630 	if (index == DESC_INDEX) {
2631 		ring->queue = 0;
2632 		ring->int_enable = bcmgenet_tx_ring16_int_enable;
2633 		ring->int_disable = bcmgenet_tx_ring16_int_disable;
2634 	} else {
2635 		ring->queue = index + 1;
2636 		ring->int_enable = bcmgenet_tx_ring_int_enable;
2637 		ring->int_disable = bcmgenet_tx_ring_int_disable;
2638 	}
2639 	ring->cbs = priv->tx_cbs + start_ptr;
2640 	ring->size = size;
2641 	ring->clean_ptr = start_ptr;
2642 	ring->c_index = 0;
2643 	ring->free_bds = size;
2644 	ring->write_ptr = start_ptr;
2645 	ring->cb_ptr = start_ptr;
2646 	ring->end_ptr = end_ptr - 1;
2647 	ring->prod_index = 0;
2648 
2649 	/* Set flow period for ring != 16 */
2650 	if (index != DESC_INDEX)
2651 		flow_period_val = ENET_MAX_MTU_SIZE << 16;
2652 
2653 	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
2654 	bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
2655 	bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2656 	/* Disable rate control for now */
2657 	bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
2658 				  TDMA_FLOW_PERIOD);
2659 	bcmgenet_tdma_ring_writel(priv, index,
2660 				  ((size << DMA_RING_SIZE_SHIFT) |
2661 				   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2662 
2663 	/* Set start and end address, read and write pointers */
2664 	bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2665 				  DMA_START_ADDR);
2666 	bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2667 				  TDMA_READ_PTR);
2668 	bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
2669 				  TDMA_WRITE_PTR);
2670 	bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2671 				  DMA_END_ADDR);
2672 
2673 	/* Initialize Tx NAPI */
2674 	netif_napi_add_tx(priv->dev, &ring->napi, bcmgenet_tx_poll);
2675 }
2676 
2677 /* Initialize a RDMA ring */
2678 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2679 				 unsigned int index, unsigned int size,
2680 				 unsigned int start_ptr, unsigned int end_ptr)
2681 {
2682 	struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2683 	u32 words_per_bd = WORDS_PER_BD(priv);
2684 	int ret;
2685 
2686 	ring->priv = priv;
2687 	ring->index = index;
2688 	if (index == DESC_INDEX) {
2689 		ring->int_enable = bcmgenet_rx_ring16_int_enable;
2690 		ring->int_disable = bcmgenet_rx_ring16_int_disable;
2691 	} else {
2692 		ring->int_enable = bcmgenet_rx_ring_int_enable;
2693 		ring->int_disable = bcmgenet_rx_ring_int_disable;
2694 	}
2695 	ring->cbs = priv->rx_cbs + start_ptr;
2696 	ring->size = size;
2697 	ring->c_index = 0;
2698 	ring->read_ptr = start_ptr;
2699 	ring->cb_ptr = start_ptr;
2700 	ring->end_ptr = end_ptr - 1;
2701 
2702 	ret = bcmgenet_alloc_rx_buffers(priv, ring);
2703 	if (ret)
2704 		return ret;
2705 
2706 	bcmgenet_init_dim(ring, bcmgenet_dim_work);
2707 	bcmgenet_init_rx_coalesce(ring);
2708 
2709 	/* Initialize Rx NAPI */
2710 	netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll);
2711 
2712 	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2713 	bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2714 	bcmgenet_rdma_ring_writel(priv, index,
2715 				  ((size << DMA_RING_SIZE_SHIFT) |
2716 				   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2717 	bcmgenet_rdma_ring_writel(priv, index,
2718 				  (DMA_FC_THRESH_LO <<
2719 				   DMA_XOFF_THRESHOLD_SHIFT) |
2720 				   DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2721 
2722 	/* Set start and end address, read and write pointers */
2723 	bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2724 				  DMA_START_ADDR);
2725 	bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2726 				  RDMA_READ_PTR);
2727 	bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2728 				  RDMA_WRITE_PTR);
2729 	bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2730 				  DMA_END_ADDR);
2731 
2732 	return ret;
2733 }
2734 
2735 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2736 {
2737 	unsigned int i;
2738 	struct bcmgenet_tx_ring *ring;
2739 
2740 	for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2741 		ring = &priv->tx_rings[i];
2742 		napi_enable(&ring->napi);
2743 		ring->int_enable(ring);
2744 	}
2745 
2746 	ring = &priv->tx_rings[DESC_INDEX];
2747 	napi_enable(&ring->napi);
2748 	ring->int_enable(ring);
2749 }
2750 
2751 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2752 {
2753 	unsigned int i;
2754 	struct bcmgenet_tx_ring *ring;
2755 
2756 	for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2757 		ring = &priv->tx_rings[i];
2758 		napi_disable(&ring->napi);
2759 	}
2760 
2761 	ring = &priv->tx_rings[DESC_INDEX];
2762 	napi_disable(&ring->napi);
2763 }
2764 
2765 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2766 {
2767 	unsigned int i;
2768 	struct bcmgenet_tx_ring *ring;
2769 
2770 	for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2771 		ring = &priv->tx_rings[i];
2772 		netif_napi_del(&ring->napi);
2773 	}
2774 
2775 	ring = &priv->tx_rings[DESC_INDEX];
2776 	netif_napi_del(&ring->napi);
2777 }
2778 
2779 /* Initialize Tx queues
2780  *
2781  * Queues 0-3 are priority-based, each one has 32 descriptors,
2782  * with queue 0 being the highest priority queue.
2783  *
2784  * Queue 16 is the default Tx queue with
2785  * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2786  *
2787  * The transmit control block pool is then partitioned as follows:
2788  * - Tx queue 0 uses tx_cbs[0..31]
2789  * - Tx queue 1 uses tx_cbs[32..63]
2790  * - Tx queue 2 uses tx_cbs[64..95]
2791  * - Tx queue 3 uses tx_cbs[96..127]
2792  * - Tx queue 16 uses tx_cbs[128..255]
2793  */
2794 static void bcmgenet_init_tx_queues(struct net_device *dev)
2795 {
2796 	struct bcmgenet_priv *priv = netdev_priv(dev);
2797 	u32 i, dma_enable;
2798 	u32 dma_ctrl, ring_cfg;
2799 	u32 dma_priority[3] = {0, 0, 0};
2800 
2801 	dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2802 	dma_enable = dma_ctrl & DMA_EN;
2803 	dma_ctrl &= ~DMA_EN;
2804 	bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2805 
2806 	dma_ctrl = 0;
2807 	ring_cfg = 0;
2808 
2809 	/* Enable strict priority arbiter mode */
2810 	bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2811 
2812 	/* Initialize Tx priority queues */
2813 	for (i = 0; i < priv->hw_params->tx_queues; i++) {
2814 		bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2815 				      i * priv->hw_params->tx_bds_per_q,
2816 				      (i + 1) * priv->hw_params->tx_bds_per_q);
2817 		ring_cfg |= (1 << i);
2818 		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2819 		dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2820 			((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2821 	}
2822 
2823 	/* Initialize Tx default queue 16 */
2824 	bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2825 			      priv->hw_params->tx_queues *
2826 			      priv->hw_params->tx_bds_per_q,
2827 			      TOTAL_DESC);
2828 	ring_cfg |= (1 << DESC_INDEX);
2829 	dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2830 	dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2831 		((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2832 		 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2833 
2834 	/* Set Tx queue priorities */
2835 	bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2836 	bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2837 	bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2838 
2839 	/* Enable Tx queues */
2840 	bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2841 
2842 	/* Enable Tx DMA */
2843 	if (dma_enable)
2844 		dma_ctrl |= DMA_EN;
2845 	bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2846 }
2847 
2848 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2849 {
2850 	unsigned int i;
2851 	struct bcmgenet_rx_ring *ring;
2852 
2853 	for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2854 		ring = &priv->rx_rings[i];
2855 		napi_enable(&ring->napi);
2856 		ring->int_enable(ring);
2857 	}
2858 
2859 	ring = &priv->rx_rings[DESC_INDEX];
2860 	napi_enable(&ring->napi);
2861 	ring->int_enable(ring);
2862 }
2863 
2864 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2865 {
2866 	unsigned int i;
2867 	struct bcmgenet_rx_ring *ring;
2868 
2869 	for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2870 		ring = &priv->rx_rings[i];
2871 		napi_disable(&ring->napi);
2872 		cancel_work_sync(&ring->dim.dim.work);
2873 	}
2874 
2875 	ring = &priv->rx_rings[DESC_INDEX];
2876 	napi_disable(&ring->napi);
2877 	cancel_work_sync(&ring->dim.dim.work);
2878 }
2879 
2880 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2881 {
2882 	unsigned int i;
2883 	struct bcmgenet_rx_ring *ring;
2884 
2885 	for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2886 		ring = &priv->rx_rings[i];
2887 		netif_napi_del(&ring->napi);
2888 	}
2889 
2890 	ring = &priv->rx_rings[DESC_INDEX];
2891 	netif_napi_del(&ring->napi);
2892 }
2893 
2894 /* Initialize Rx queues
2895  *
2896  * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2897  * used to direct traffic to these queues.
2898  *
2899  * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2900  */
2901 static int bcmgenet_init_rx_queues(struct net_device *dev)
2902 {
2903 	struct bcmgenet_priv *priv = netdev_priv(dev);
2904 	u32 i;
2905 	u32 dma_enable;
2906 	u32 dma_ctrl;
2907 	u32 ring_cfg;
2908 	int ret;
2909 
2910 	dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2911 	dma_enable = dma_ctrl & DMA_EN;
2912 	dma_ctrl &= ~DMA_EN;
2913 	bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2914 
2915 	dma_ctrl = 0;
2916 	ring_cfg = 0;
2917 
2918 	/* Initialize Rx priority queues */
2919 	for (i = 0; i < priv->hw_params->rx_queues; i++) {
2920 		ret = bcmgenet_init_rx_ring(priv, i,
2921 					    priv->hw_params->rx_bds_per_q,
2922 					    i * priv->hw_params->rx_bds_per_q,
2923 					    (i + 1) *
2924 					    priv->hw_params->rx_bds_per_q);
2925 		if (ret)
2926 			return ret;
2927 
2928 		ring_cfg |= (1 << i);
2929 		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2930 	}
2931 
2932 	/* Initialize Rx default queue 16 */
2933 	ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2934 				    priv->hw_params->rx_queues *
2935 				    priv->hw_params->rx_bds_per_q,
2936 				    TOTAL_DESC);
2937 	if (ret)
2938 		return ret;
2939 
2940 	ring_cfg |= (1 << DESC_INDEX);
2941 	dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2942 
2943 	/* Enable rings */
2944 	bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2945 
2946 	/* Configure ring as descriptor ring and re-enable DMA if enabled */
2947 	if (dma_enable)
2948 		dma_ctrl |= DMA_EN;
2949 	bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2950 
2951 	return 0;
2952 }
2953 
2954 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2955 {
2956 	int ret = 0;
2957 	int timeout = 0;
2958 	u32 reg;
2959 	u32 dma_ctrl;
2960 	int i;
2961 
2962 	/* Disable TDMA to stop add more frames in TX DMA */
2963 	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2964 	reg &= ~DMA_EN;
2965 	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2966 
2967 	/* Check TDMA status register to confirm TDMA is disabled */
2968 	while (timeout++ < DMA_TIMEOUT_VAL) {
2969 		reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2970 		if (reg & DMA_DISABLED)
2971 			break;
2972 
2973 		udelay(1);
2974 	}
2975 
2976 	if (timeout == DMA_TIMEOUT_VAL) {
2977 		netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2978 		ret = -ETIMEDOUT;
2979 	}
2980 
2981 	/* Wait 10ms for packet drain in both tx and rx dma */
2982 	usleep_range(10000, 20000);
2983 
2984 	/* Disable RDMA */
2985 	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2986 	reg &= ~DMA_EN;
2987 	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2988 
2989 	timeout = 0;
2990 	/* Check RDMA status register to confirm RDMA is disabled */
2991 	while (timeout++ < DMA_TIMEOUT_VAL) {
2992 		reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2993 		if (reg & DMA_DISABLED)
2994 			break;
2995 
2996 		udelay(1);
2997 	}
2998 
2999 	if (timeout == DMA_TIMEOUT_VAL) {
3000 		netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
3001 		ret = -ETIMEDOUT;
3002 	}
3003 
3004 	dma_ctrl = 0;
3005 	for (i = 0; i < priv->hw_params->rx_queues; i++)
3006 		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3007 	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3008 	reg &= ~dma_ctrl;
3009 	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3010 
3011 	dma_ctrl = 0;
3012 	for (i = 0; i < priv->hw_params->tx_queues; i++)
3013 		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3014 	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3015 	reg &= ~dma_ctrl;
3016 	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3017 
3018 	return ret;
3019 }
3020 
3021 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
3022 {
3023 	struct netdev_queue *txq;
3024 	int i;
3025 
3026 	bcmgenet_fini_rx_napi(priv);
3027 	bcmgenet_fini_tx_napi(priv);
3028 
3029 	for (i = 0; i < priv->num_tx_bds; i++)
3030 		dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev,
3031 						  priv->tx_cbs + i));
3032 
3033 	for (i = 0; i < priv->hw_params->tx_queues; i++) {
3034 		txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
3035 		netdev_tx_reset_queue(txq);
3036 	}
3037 
3038 	txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
3039 	netdev_tx_reset_queue(txq);
3040 
3041 	bcmgenet_free_rx_buffers(priv);
3042 	kfree(priv->rx_cbs);
3043 	kfree(priv->tx_cbs);
3044 }
3045 
3046 /* init_edma: Initialize DMA control register */
3047 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
3048 {
3049 	int ret;
3050 	unsigned int i;
3051 	struct enet_cb *cb;
3052 
3053 	netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
3054 
3055 	/* Initialize common Rx ring structures */
3056 	priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
3057 	priv->num_rx_bds = TOTAL_DESC;
3058 	priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
3059 			       GFP_KERNEL);
3060 	if (!priv->rx_cbs)
3061 		return -ENOMEM;
3062 
3063 	for (i = 0; i < priv->num_rx_bds; i++) {
3064 		cb = priv->rx_cbs + i;
3065 		cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
3066 	}
3067 
3068 	/* Initialize common TX ring structures */
3069 	priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
3070 	priv->num_tx_bds = TOTAL_DESC;
3071 	priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
3072 			       GFP_KERNEL);
3073 	if (!priv->tx_cbs) {
3074 		kfree(priv->rx_cbs);
3075 		return -ENOMEM;
3076 	}
3077 
3078 	for (i = 0; i < priv->num_tx_bds; i++) {
3079 		cb = priv->tx_cbs + i;
3080 		cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
3081 	}
3082 
3083 	/* Init rDma */
3084 	bcmgenet_rdma_writel(priv, priv->dma_max_burst_length,
3085 			     DMA_SCB_BURST_SIZE);
3086 
3087 	/* Initialize Rx queues */
3088 	ret = bcmgenet_init_rx_queues(priv->dev);
3089 	if (ret) {
3090 		netdev_err(priv->dev, "failed to initialize Rx queues\n");
3091 		bcmgenet_free_rx_buffers(priv);
3092 		kfree(priv->rx_cbs);
3093 		kfree(priv->tx_cbs);
3094 		return ret;
3095 	}
3096 
3097 	/* Init tDma */
3098 	bcmgenet_tdma_writel(priv, priv->dma_max_burst_length,
3099 			     DMA_SCB_BURST_SIZE);
3100 
3101 	/* Initialize Tx queues */
3102 	bcmgenet_init_tx_queues(priv->dev);
3103 
3104 	return 0;
3105 }
3106 
3107 /* Interrupt bottom half */
3108 static void bcmgenet_irq_task(struct work_struct *work)
3109 {
3110 	unsigned int status;
3111 	struct bcmgenet_priv *priv = container_of(
3112 			work, struct bcmgenet_priv, bcmgenet_irq_work);
3113 
3114 	netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
3115 
3116 	spin_lock_irq(&priv->lock);
3117 	status = priv->irq0_stat;
3118 	priv->irq0_stat = 0;
3119 	spin_unlock_irq(&priv->lock);
3120 
3121 	if (status & UMAC_IRQ_PHY_DET_R &&
3122 	    priv->dev->phydev->autoneg != AUTONEG_ENABLE) {
3123 		phy_init_hw(priv->dev->phydev);
3124 		genphy_config_aneg(priv->dev->phydev);
3125 	}
3126 
3127 	/* Link UP/DOWN event */
3128 	if (status & UMAC_IRQ_LINK_EVENT)
3129 		phy_mac_interrupt(priv->dev->phydev);
3130 
3131 }
3132 
3133 /* bcmgenet_isr1: handle Rx and Tx priority queues */
3134 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
3135 {
3136 	struct bcmgenet_priv *priv = dev_id;
3137 	struct bcmgenet_rx_ring *rx_ring;
3138 	struct bcmgenet_tx_ring *tx_ring;
3139 	unsigned int index, status;
3140 
3141 	/* Read irq status */
3142 	status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
3143 		~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3144 
3145 	/* clear interrupts */
3146 	bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR);
3147 
3148 	netif_dbg(priv, intr, priv->dev,
3149 		  "%s: IRQ=0x%x\n", __func__, status);
3150 
3151 	/* Check Rx priority queue interrupts */
3152 	for (index = 0; index < priv->hw_params->rx_queues; index++) {
3153 		if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
3154 			continue;
3155 
3156 		rx_ring = &priv->rx_rings[index];
3157 		rx_ring->dim.event_ctr++;
3158 
3159 		if (likely(napi_schedule_prep(&rx_ring->napi))) {
3160 			rx_ring->int_disable(rx_ring);
3161 			__napi_schedule_irqoff(&rx_ring->napi);
3162 		}
3163 	}
3164 
3165 	/* Check Tx priority queue interrupts */
3166 	for (index = 0; index < priv->hw_params->tx_queues; index++) {
3167 		if (!(status & BIT(index)))
3168 			continue;
3169 
3170 		tx_ring = &priv->tx_rings[index];
3171 
3172 		if (likely(napi_schedule_prep(&tx_ring->napi))) {
3173 			tx_ring->int_disable(tx_ring);
3174 			__napi_schedule_irqoff(&tx_ring->napi);
3175 		}
3176 	}
3177 
3178 	return IRQ_HANDLED;
3179 }
3180 
3181 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
3182 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
3183 {
3184 	struct bcmgenet_priv *priv = dev_id;
3185 	struct bcmgenet_rx_ring *rx_ring;
3186 	struct bcmgenet_tx_ring *tx_ring;
3187 	unsigned int status;
3188 	unsigned long flags;
3189 
3190 	/* Read irq status */
3191 	status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
3192 		~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3193 
3194 	/* clear interrupts */
3195 	bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR);
3196 
3197 	netif_dbg(priv, intr, priv->dev,
3198 		  "IRQ=0x%x\n", status);
3199 
3200 	if (status & UMAC_IRQ_RXDMA_DONE) {
3201 		rx_ring = &priv->rx_rings[DESC_INDEX];
3202 		rx_ring->dim.event_ctr++;
3203 
3204 		if (likely(napi_schedule_prep(&rx_ring->napi))) {
3205 			rx_ring->int_disable(rx_ring);
3206 			__napi_schedule_irqoff(&rx_ring->napi);
3207 		}
3208 	}
3209 
3210 	if (status & UMAC_IRQ_TXDMA_DONE) {
3211 		tx_ring = &priv->tx_rings[DESC_INDEX];
3212 
3213 		if (likely(napi_schedule_prep(&tx_ring->napi))) {
3214 			tx_ring->int_disable(tx_ring);
3215 			__napi_schedule_irqoff(&tx_ring->napi);
3216 		}
3217 	}
3218 
3219 	if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
3220 		status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
3221 		wake_up(&priv->wq);
3222 	}
3223 
3224 	/* all other interested interrupts handled in bottom half */
3225 	status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R);
3226 	if (status) {
3227 		/* Save irq status for bottom-half processing. */
3228 		spin_lock_irqsave(&priv->lock, flags);
3229 		priv->irq0_stat |= status;
3230 		spin_unlock_irqrestore(&priv->lock, flags);
3231 
3232 		schedule_work(&priv->bcmgenet_irq_work);
3233 	}
3234 
3235 	return IRQ_HANDLED;
3236 }
3237 
3238 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
3239 {
3240 	/* Acknowledge the interrupt */
3241 	return IRQ_HANDLED;
3242 }
3243 
3244 #ifdef CONFIG_NET_POLL_CONTROLLER
3245 static void bcmgenet_poll_controller(struct net_device *dev)
3246 {
3247 	struct bcmgenet_priv *priv = netdev_priv(dev);
3248 
3249 	/* Invoke the main RX/TX interrupt handler */
3250 	disable_irq(priv->irq0);
3251 	bcmgenet_isr0(priv->irq0, priv);
3252 	enable_irq(priv->irq0);
3253 
3254 	/* And the interrupt handler for RX/TX priority queues */
3255 	disable_irq(priv->irq1);
3256 	bcmgenet_isr1(priv->irq1, priv);
3257 	enable_irq(priv->irq1);
3258 }
3259 #endif
3260 
3261 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
3262 {
3263 	u32 reg;
3264 
3265 	reg = bcmgenet_rbuf_ctrl_get(priv);
3266 	reg |= BIT(1);
3267 	bcmgenet_rbuf_ctrl_set(priv, reg);
3268 	udelay(10);
3269 
3270 	reg &= ~BIT(1);
3271 	bcmgenet_rbuf_ctrl_set(priv, reg);
3272 	udelay(10);
3273 }
3274 
3275 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
3276 				 const unsigned char *addr)
3277 {
3278 	bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0);
3279 	bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1);
3280 }
3281 
3282 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv,
3283 				 unsigned char *addr)
3284 {
3285 	u32 addr_tmp;
3286 
3287 	addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0);
3288 	put_unaligned_be32(addr_tmp, &addr[0]);
3289 	addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1);
3290 	put_unaligned_be16(addr_tmp, &addr[4]);
3291 }
3292 
3293 /* Returns a reusable dma control register value */
3294 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
3295 {
3296 	unsigned int i;
3297 	u32 reg;
3298 	u32 dma_ctrl;
3299 
3300 	/* disable DMA */
3301 	dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3302 	for (i = 0; i < priv->hw_params->tx_queues; i++)
3303 		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3304 	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3305 	reg &= ~dma_ctrl;
3306 	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3307 
3308 	dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
3309 	for (i = 0; i < priv->hw_params->rx_queues; i++)
3310 		dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
3311 	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3312 	reg &= ~dma_ctrl;
3313 	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3314 
3315 	bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
3316 	udelay(10);
3317 	bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
3318 
3319 	return dma_ctrl;
3320 }
3321 
3322 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
3323 {
3324 	u32 reg;
3325 
3326 	reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
3327 	reg |= dma_ctrl;
3328 	bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
3329 
3330 	reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
3331 	reg |= dma_ctrl;
3332 	bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
3333 }
3334 
3335 static void bcmgenet_netif_start(struct net_device *dev)
3336 {
3337 	struct bcmgenet_priv *priv = netdev_priv(dev);
3338 
3339 	/* Start the network engine */
3340 	bcmgenet_set_rx_mode(dev);
3341 	bcmgenet_enable_rx_napi(priv);
3342 
3343 	umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
3344 
3345 	bcmgenet_enable_tx_napi(priv);
3346 
3347 	/* Monitor link interrupts now */
3348 	bcmgenet_link_intr_enable(priv);
3349 
3350 	phy_start(dev->phydev);
3351 }
3352 
3353 static int bcmgenet_open(struct net_device *dev)
3354 {
3355 	struct bcmgenet_priv *priv = netdev_priv(dev);
3356 	unsigned long dma_ctrl;
3357 	int ret;
3358 
3359 	netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
3360 
3361 	/* Turn on the clock */
3362 	clk_prepare_enable(priv->clk);
3363 
3364 	/* If this is an internal GPHY, power it back on now, before UniMAC is
3365 	 * brought out of reset as absolutely no UniMAC activity is allowed
3366 	 */
3367 	if (priv->internal_phy)
3368 		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3369 
3370 	/* take MAC out of reset */
3371 	bcmgenet_umac_reset(priv);
3372 
3373 	init_umac(priv);
3374 
3375 	/* Apply features again in case we changed them while interface was
3376 	 * down
3377 	 */
3378 	bcmgenet_set_features(dev, dev->features);
3379 
3380 	bcmgenet_set_hw_addr(priv, dev->dev_addr);
3381 
3382 	/* Disable RX/TX DMA and flush TX queues */
3383 	dma_ctrl = bcmgenet_dma_disable(priv);
3384 
3385 	/* Reinitialize TDMA and RDMA and SW housekeeping */
3386 	ret = bcmgenet_init_dma(priv);
3387 	if (ret) {
3388 		netdev_err(dev, "failed to initialize DMA\n");
3389 		goto err_clk_disable;
3390 	}
3391 
3392 	/* Always enable ring 16 - descriptor ring */
3393 	bcmgenet_enable_dma(priv, dma_ctrl);
3394 
3395 	/* HFB init */
3396 	bcmgenet_hfb_init(priv);
3397 
3398 	ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
3399 			  dev->name, priv);
3400 	if (ret < 0) {
3401 		netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
3402 		goto err_fini_dma;
3403 	}
3404 
3405 	ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
3406 			  dev->name, priv);
3407 	if (ret < 0) {
3408 		netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
3409 		goto err_irq0;
3410 	}
3411 
3412 	ret = bcmgenet_mii_probe(dev);
3413 	if (ret) {
3414 		netdev_err(dev, "failed to connect to PHY\n");
3415 		goto err_irq1;
3416 	}
3417 
3418 	bcmgenet_phy_pause_set(dev, priv->rx_pause, priv->tx_pause);
3419 
3420 	bcmgenet_netif_start(dev);
3421 
3422 	netif_tx_start_all_queues(dev);
3423 
3424 	return 0;
3425 
3426 err_irq1:
3427 	free_irq(priv->irq1, priv);
3428 err_irq0:
3429 	free_irq(priv->irq0, priv);
3430 err_fini_dma:
3431 	bcmgenet_dma_teardown(priv);
3432 	bcmgenet_fini_dma(priv);
3433 err_clk_disable:
3434 	if (priv->internal_phy)
3435 		bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3436 	clk_disable_unprepare(priv->clk);
3437 	return ret;
3438 }
3439 
3440 static void bcmgenet_netif_stop(struct net_device *dev)
3441 {
3442 	struct bcmgenet_priv *priv = netdev_priv(dev);
3443 
3444 	bcmgenet_disable_tx_napi(priv);
3445 	netif_tx_disable(dev);
3446 
3447 	/* Disable MAC receive */
3448 	umac_enable_set(priv, CMD_RX_EN, false);
3449 
3450 	bcmgenet_dma_teardown(priv);
3451 
3452 	/* Disable MAC transmit. TX DMA disabled must be done before this */
3453 	umac_enable_set(priv, CMD_TX_EN, false);
3454 
3455 	phy_stop(dev->phydev);
3456 	bcmgenet_disable_rx_napi(priv);
3457 	bcmgenet_intr_disable(priv);
3458 
3459 	/* Wait for pending work items to complete. Since interrupts are
3460 	 * disabled no new work will be scheduled.
3461 	 */
3462 	cancel_work_sync(&priv->bcmgenet_irq_work);
3463 
3464 	/* tx reclaim */
3465 	bcmgenet_tx_reclaim_all(dev);
3466 	bcmgenet_fini_dma(priv);
3467 }
3468 
3469 static int bcmgenet_close(struct net_device *dev)
3470 {
3471 	struct bcmgenet_priv *priv = netdev_priv(dev);
3472 	int ret = 0;
3473 
3474 	netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
3475 
3476 	bcmgenet_netif_stop(dev);
3477 
3478 	/* Really kill the PHY state machine and disconnect from it */
3479 	phy_disconnect(dev->phydev);
3480 
3481 	free_irq(priv->irq0, priv);
3482 	free_irq(priv->irq1, priv);
3483 
3484 	if (priv->internal_phy)
3485 		ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3486 
3487 	clk_disable_unprepare(priv->clk);
3488 
3489 	return ret;
3490 }
3491 
3492 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
3493 {
3494 	struct bcmgenet_priv *priv = ring->priv;
3495 	u32 p_index, c_index, intsts, intmsk;
3496 	struct netdev_queue *txq;
3497 	unsigned int free_bds;
3498 	bool txq_stopped;
3499 
3500 	if (!netif_msg_tx_err(priv))
3501 		return;
3502 
3503 	txq = netdev_get_tx_queue(priv->dev, ring->queue);
3504 
3505 	spin_lock(&ring->lock);
3506 	if (ring->index == DESC_INDEX) {
3507 		intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
3508 		intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
3509 	} else {
3510 		intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
3511 		intmsk = 1 << ring->index;
3512 	}
3513 	c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
3514 	p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
3515 	txq_stopped = netif_tx_queue_stopped(txq);
3516 	free_bds = ring->free_bds;
3517 	spin_unlock(&ring->lock);
3518 
3519 	netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
3520 		  "TX queue status: %s, interrupts: %s\n"
3521 		  "(sw)free_bds: %d (sw)size: %d\n"
3522 		  "(sw)p_index: %d (hw)p_index: %d\n"
3523 		  "(sw)c_index: %d (hw)c_index: %d\n"
3524 		  "(sw)clean_p: %d (sw)write_p: %d\n"
3525 		  "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
3526 		  ring->index, ring->queue,
3527 		  txq_stopped ? "stopped" : "active",
3528 		  intsts & intmsk ? "enabled" : "disabled",
3529 		  free_bds, ring->size,
3530 		  ring->prod_index, p_index & DMA_P_INDEX_MASK,
3531 		  ring->c_index, c_index & DMA_C_INDEX_MASK,
3532 		  ring->clean_ptr, ring->write_ptr,
3533 		  ring->cb_ptr, ring->end_ptr);
3534 }
3535 
3536 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue)
3537 {
3538 	struct bcmgenet_priv *priv = netdev_priv(dev);
3539 	u32 int0_enable = 0;
3540 	u32 int1_enable = 0;
3541 	unsigned int q;
3542 
3543 	netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
3544 
3545 	for (q = 0; q < priv->hw_params->tx_queues; q++)
3546 		bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
3547 	bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
3548 
3549 	bcmgenet_tx_reclaim_all(dev);
3550 
3551 	for (q = 0; q < priv->hw_params->tx_queues; q++)
3552 		int1_enable |= (1 << q);
3553 
3554 	int0_enable = UMAC_IRQ_TXDMA_DONE;
3555 
3556 	/* Re-enable TX interrupts if disabled */
3557 	bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
3558 	bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
3559 
3560 	netif_trans_update(dev);
3561 
3562 	dev->stats.tx_errors++;
3563 
3564 	netif_tx_wake_all_queues(dev);
3565 }
3566 
3567 #define MAX_MDF_FILTER	17
3568 
3569 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
3570 					 const unsigned char *addr,
3571 					 int *i)
3572 {
3573 	bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
3574 			     UMAC_MDF_ADDR + (*i * 4));
3575 	bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
3576 			     addr[4] << 8 | addr[5],
3577 			     UMAC_MDF_ADDR + ((*i + 1) * 4));
3578 	*i += 2;
3579 }
3580 
3581 static void bcmgenet_set_rx_mode(struct net_device *dev)
3582 {
3583 	struct bcmgenet_priv *priv = netdev_priv(dev);
3584 	struct netdev_hw_addr *ha;
3585 	int i, nfilter;
3586 	u32 reg;
3587 
3588 	netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
3589 
3590 	/* Number of filters needed */
3591 	nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2;
3592 
3593 	/*
3594 	 * Turn on promicuous mode for three scenarios
3595 	 * 1. IFF_PROMISC flag is set
3596 	 * 2. IFF_ALLMULTI flag is set
3597 	 * 3. The number of filters needed exceeds the number filters
3598 	 *    supported by the hardware.
3599 	*/
3600 	reg = bcmgenet_umac_readl(priv, UMAC_CMD);
3601 	if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
3602 	    (nfilter > MAX_MDF_FILTER)) {
3603 		reg |= CMD_PROMISC;
3604 		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3605 		bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
3606 		return;
3607 	} else {
3608 		reg &= ~CMD_PROMISC;
3609 		bcmgenet_umac_writel(priv, reg, UMAC_CMD);
3610 	}
3611 
3612 	/* update MDF filter */
3613 	i = 0;
3614 	/* Broadcast */
3615 	bcmgenet_set_mdf_addr(priv, dev->broadcast, &i);
3616 	/* my own address.*/
3617 	bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i);
3618 
3619 	/* Unicast */
3620 	netdev_for_each_uc_addr(ha, dev)
3621 		bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3622 
3623 	/* Multicast */
3624 	netdev_for_each_mc_addr(ha, dev)
3625 		bcmgenet_set_mdf_addr(priv, ha->addr, &i);
3626 
3627 	/* Enable filters */
3628 	reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter);
3629 	bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
3630 }
3631 
3632 /* Set the hardware MAC address. */
3633 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3634 {
3635 	struct sockaddr *addr = p;
3636 
3637 	/* Setting the MAC address at the hardware level is not possible
3638 	 * without disabling the UniMAC RX/TX enable bits.
3639 	 */
3640 	if (netif_running(dev))
3641 		return -EBUSY;
3642 
3643 	eth_hw_addr_set(dev, addr->sa_data);
3644 
3645 	return 0;
3646 }
3647 
3648 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev)
3649 {
3650 	struct bcmgenet_priv *priv = netdev_priv(dev);
3651 	unsigned long tx_bytes = 0, tx_packets = 0;
3652 	unsigned long rx_bytes = 0, rx_packets = 0;
3653 	unsigned long rx_errors = 0, rx_dropped = 0;
3654 	struct bcmgenet_tx_ring *tx_ring;
3655 	struct bcmgenet_rx_ring *rx_ring;
3656 	unsigned int q;
3657 
3658 	for (q = 0; q < priv->hw_params->tx_queues; q++) {
3659 		tx_ring = &priv->tx_rings[q];
3660 		tx_bytes += tx_ring->bytes;
3661 		tx_packets += tx_ring->packets;
3662 	}
3663 	tx_ring = &priv->tx_rings[DESC_INDEX];
3664 	tx_bytes += tx_ring->bytes;
3665 	tx_packets += tx_ring->packets;
3666 
3667 	for (q = 0; q < priv->hw_params->rx_queues; q++) {
3668 		rx_ring = &priv->rx_rings[q];
3669 
3670 		rx_bytes += rx_ring->bytes;
3671 		rx_packets += rx_ring->packets;
3672 		rx_errors += rx_ring->errors;
3673 		rx_dropped += rx_ring->dropped;
3674 	}
3675 	rx_ring = &priv->rx_rings[DESC_INDEX];
3676 	rx_bytes += rx_ring->bytes;
3677 	rx_packets += rx_ring->packets;
3678 	rx_errors += rx_ring->errors;
3679 	rx_dropped += rx_ring->dropped;
3680 
3681 	dev->stats.tx_bytes = tx_bytes;
3682 	dev->stats.tx_packets = tx_packets;
3683 	dev->stats.rx_bytes = rx_bytes;
3684 	dev->stats.rx_packets = rx_packets;
3685 	dev->stats.rx_errors = rx_errors;
3686 	dev->stats.rx_missed_errors = rx_errors;
3687 	dev->stats.rx_dropped = rx_dropped;
3688 	return &dev->stats;
3689 }
3690 
3691 static int bcmgenet_change_carrier(struct net_device *dev, bool new_carrier)
3692 {
3693 	struct bcmgenet_priv *priv = netdev_priv(dev);
3694 
3695 	if (!dev->phydev || !phy_is_pseudo_fixed_link(dev->phydev) ||
3696 	    priv->phy_interface != PHY_INTERFACE_MODE_MOCA)
3697 		return -EOPNOTSUPP;
3698 
3699 	if (new_carrier)
3700 		netif_carrier_on(dev);
3701 	else
3702 		netif_carrier_off(dev);
3703 
3704 	return 0;
3705 }
3706 
3707 static const struct net_device_ops bcmgenet_netdev_ops = {
3708 	.ndo_open		= bcmgenet_open,
3709 	.ndo_stop		= bcmgenet_close,
3710 	.ndo_start_xmit		= bcmgenet_xmit,
3711 	.ndo_tx_timeout		= bcmgenet_timeout,
3712 	.ndo_set_rx_mode	= bcmgenet_set_rx_mode,
3713 	.ndo_set_mac_address	= bcmgenet_set_mac_addr,
3714 	.ndo_eth_ioctl		= phy_do_ioctl_running,
3715 	.ndo_set_features	= bcmgenet_set_features,
3716 #ifdef CONFIG_NET_POLL_CONTROLLER
3717 	.ndo_poll_controller	= bcmgenet_poll_controller,
3718 #endif
3719 	.ndo_get_stats		= bcmgenet_get_stats,
3720 	.ndo_change_carrier	= bcmgenet_change_carrier,
3721 };
3722 
3723 /* Array of GENET hardware parameters/characteristics */
3724 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3725 	[GENET_V1] = {
3726 		.tx_queues = 0,
3727 		.tx_bds_per_q = 0,
3728 		.rx_queues = 0,
3729 		.rx_bds_per_q = 0,
3730 		.bp_in_en_shift = 16,
3731 		.bp_in_mask = 0xffff,
3732 		.hfb_filter_cnt = 16,
3733 		.qtag_mask = 0x1F,
3734 		.hfb_offset = 0x1000,
3735 		.rdma_offset = 0x2000,
3736 		.tdma_offset = 0x3000,
3737 		.words_per_bd = 2,
3738 	},
3739 	[GENET_V2] = {
3740 		.tx_queues = 4,
3741 		.tx_bds_per_q = 32,
3742 		.rx_queues = 0,
3743 		.rx_bds_per_q = 0,
3744 		.bp_in_en_shift = 16,
3745 		.bp_in_mask = 0xffff,
3746 		.hfb_filter_cnt = 16,
3747 		.qtag_mask = 0x1F,
3748 		.tbuf_offset = 0x0600,
3749 		.hfb_offset = 0x1000,
3750 		.hfb_reg_offset = 0x2000,
3751 		.rdma_offset = 0x3000,
3752 		.tdma_offset = 0x4000,
3753 		.words_per_bd = 2,
3754 		.flags = GENET_HAS_EXT,
3755 	},
3756 	[GENET_V3] = {
3757 		.tx_queues = 4,
3758 		.tx_bds_per_q = 32,
3759 		.rx_queues = 0,
3760 		.rx_bds_per_q = 0,
3761 		.bp_in_en_shift = 17,
3762 		.bp_in_mask = 0x1ffff,
3763 		.hfb_filter_cnt = 48,
3764 		.hfb_filter_size = 128,
3765 		.qtag_mask = 0x3F,
3766 		.tbuf_offset = 0x0600,
3767 		.hfb_offset = 0x8000,
3768 		.hfb_reg_offset = 0xfc00,
3769 		.rdma_offset = 0x10000,
3770 		.tdma_offset = 0x11000,
3771 		.words_per_bd = 2,
3772 		.flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3773 			 GENET_HAS_MOCA_LINK_DET,
3774 	},
3775 	[GENET_V4] = {
3776 		.tx_queues = 4,
3777 		.tx_bds_per_q = 32,
3778 		.rx_queues = 0,
3779 		.rx_bds_per_q = 0,
3780 		.bp_in_en_shift = 17,
3781 		.bp_in_mask = 0x1ffff,
3782 		.hfb_filter_cnt = 48,
3783 		.hfb_filter_size = 128,
3784 		.qtag_mask = 0x3F,
3785 		.tbuf_offset = 0x0600,
3786 		.hfb_offset = 0x8000,
3787 		.hfb_reg_offset = 0xfc00,
3788 		.rdma_offset = 0x2000,
3789 		.tdma_offset = 0x4000,
3790 		.words_per_bd = 3,
3791 		.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3792 			 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3793 	},
3794 	[GENET_V5] = {
3795 		.tx_queues = 4,
3796 		.tx_bds_per_q = 32,
3797 		.rx_queues = 0,
3798 		.rx_bds_per_q = 0,
3799 		.bp_in_en_shift = 17,
3800 		.bp_in_mask = 0x1ffff,
3801 		.hfb_filter_cnt = 48,
3802 		.hfb_filter_size = 128,
3803 		.qtag_mask = 0x3F,
3804 		.tbuf_offset = 0x0600,
3805 		.hfb_offset = 0x8000,
3806 		.hfb_reg_offset = 0xfc00,
3807 		.rdma_offset = 0x2000,
3808 		.tdma_offset = 0x4000,
3809 		.words_per_bd = 3,
3810 		.flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3811 			 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3812 	},
3813 };
3814 
3815 /* Infer hardware parameters from the detected GENET version */
3816 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3817 {
3818 	struct bcmgenet_hw_params *params;
3819 	u32 reg;
3820 	u8 major;
3821 	u16 gphy_rev;
3822 
3823 	if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) {
3824 		bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3825 		genet_dma_ring_regs = genet_dma_ring_regs_v4;
3826 	} else if (GENET_IS_V3(priv)) {
3827 		bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3828 		genet_dma_ring_regs = genet_dma_ring_regs_v123;
3829 	} else if (GENET_IS_V2(priv)) {
3830 		bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3831 		genet_dma_ring_regs = genet_dma_ring_regs_v123;
3832 	} else if (GENET_IS_V1(priv)) {
3833 		bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3834 		genet_dma_ring_regs = genet_dma_ring_regs_v123;
3835 	}
3836 
3837 	/* enum genet_version starts at 1 */
3838 	priv->hw_params = &bcmgenet_hw_params[priv->version];
3839 	params = priv->hw_params;
3840 
3841 	/* Read GENET HW version */
3842 	reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3843 	major = (reg >> 24 & 0x0f);
3844 	if (major == 6)
3845 		major = 5;
3846 	else if (major == 5)
3847 		major = 4;
3848 	else if (major == 0)
3849 		major = 1;
3850 	if (major != priv->version) {
3851 		dev_err(&priv->pdev->dev,
3852 			"GENET version mismatch, got: %d, configured for: %d\n",
3853 			major, priv->version);
3854 	}
3855 
3856 	/* Print the GENET core version */
3857 	dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3858 		 major, (reg >> 16) & 0x0f, reg & 0xffff);
3859 
3860 	/* Store the integrated PHY revision for the MDIO probing function
3861 	 * to pass this information to the PHY driver. The PHY driver expects
3862 	 * to find the PHY major revision in bits 15:8 while the GENET register
3863 	 * stores that information in bits 7:0, account for that.
3864 	 *
3865 	 * On newer chips, starting with PHY revision G0, a new scheme is
3866 	 * deployed similar to the Starfighter 2 switch with GPHY major
3867 	 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3868 	 * is reserved as well as special value 0x01ff, we have a small
3869 	 * heuristic to check for the new GPHY revision and re-arrange things
3870 	 * so the GPHY driver is happy.
3871 	 */
3872 	gphy_rev = reg & 0xffff;
3873 
3874 	if (GENET_IS_V5(priv)) {
3875 		/* The EPHY revision should come from the MDIO registers of
3876 		 * the PHY not from GENET.
3877 		 */
3878 		if (gphy_rev != 0) {
3879 			pr_warn("GENET is reporting EPHY revision: 0x%04x\n",
3880 				gphy_rev);
3881 		}
3882 	/* This is reserved so should require special treatment */
3883 	} else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3884 		pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3885 		return;
3886 	/* This is the good old scheme, just GPHY major, no minor nor patch */
3887 	} else if ((gphy_rev & 0xf0) != 0) {
3888 		priv->gphy_rev = gphy_rev << 8;
3889 	/* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3890 	} else if ((gphy_rev & 0xff00) != 0) {
3891 		priv->gphy_rev = gphy_rev;
3892 	}
3893 
3894 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3895 	if (!(params->flags & GENET_HAS_40BITS))
3896 		pr_warn("GENET does not support 40-bits PA\n");
3897 #endif
3898 
3899 	pr_debug("Configuration for version: %d\n"
3900 		"TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3901 		"BP << en: %2d, BP msk: 0x%05x\n"
3902 		"HFB count: %2d, QTAQ msk: 0x%05x\n"
3903 		"TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3904 		"RDMA: 0x%05x, TDMA: 0x%05x\n"
3905 		"Words/BD: %d\n",
3906 		priv->version,
3907 		params->tx_queues, params->tx_bds_per_q,
3908 		params->rx_queues, params->rx_bds_per_q,
3909 		params->bp_in_en_shift, params->bp_in_mask,
3910 		params->hfb_filter_cnt, params->qtag_mask,
3911 		params->tbuf_offset, params->hfb_offset,
3912 		params->hfb_reg_offset,
3913 		params->rdma_offset, params->tdma_offset,
3914 		params->words_per_bd);
3915 }
3916 
3917 struct bcmgenet_plat_data {
3918 	enum bcmgenet_version version;
3919 	u32 dma_max_burst_length;
3920 	bool ephy_16nm;
3921 };
3922 
3923 static const struct bcmgenet_plat_data v1_plat_data = {
3924 	.version = GENET_V1,
3925 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3926 };
3927 
3928 static const struct bcmgenet_plat_data v2_plat_data = {
3929 	.version = GENET_V2,
3930 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3931 };
3932 
3933 static const struct bcmgenet_plat_data v3_plat_data = {
3934 	.version = GENET_V3,
3935 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3936 };
3937 
3938 static const struct bcmgenet_plat_data v4_plat_data = {
3939 	.version = GENET_V4,
3940 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3941 };
3942 
3943 static const struct bcmgenet_plat_data v5_plat_data = {
3944 	.version = GENET_V5,
3945 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3946 };
3947 
3948 static const struct bcmgenet_plat_data bcm2711_plat_data = {
3949 	.version = GENET_V5,
3950 	.dma_max_burst_length = 0x08,
3951 };
3952 
3953 static const struct bcmgenet_plat_data bcm7712_plat_data = {
3954 	.version = GENET_V5,
3955 	.dma_max_burst_length = DMA_MAX_BURST_LENGTH,
3956 	.ephy_16nm = true,
3957 };
3958 
3959 static const struct of_device_id bcmgenet_match[] = {
3960 	{ .compatible = "brcm,genet-v1", .data = &v1_plat_data },
3961 	{ .compatible = "brcm,genet-v2", .data = &v2_plat_data },
3962 	{ .compatible = "brcm,genet-v3", .data = &v3_plat_data },
3963 	{ .compatible = "brcm,genet-v4", .data = &v4_plat_data },
3964 	{ .compatible = "brcm,genet-v5", .data = &v5_plat_data },
3965 	{ .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data },
3966 	{ .compatible = "brcm,bcm7712-genet-v5", .data = &bcm7712_plat_data },
3967 	{ },
3968 };
3969 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3970 
3971 static int bcmgenet_probe(struct platform_device *pdev)
3972 {
3973 	struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3974 	const struct bcmgenet_plat_data *pdata;
3975 	struct bcmgenet_priv *priv;
3976 	struct net_device *dev;
3977 	unsigned int i;
3978 	int err = -EIO;
3979 
3980 	/* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3981 	dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3982 				 GENET_MAX_MQ_CNT + 1);
3983 	if (!dev) {
3984 		dev_err(&pdev->dev, "can't allocate net device\n");
3985 		return -ENOMEM;
3986 	}
3987 
3988 	priv = netdev_priv(dev);
3989 	priv->irq0 = platform_get_irq(pdev, 0);
3990 	if (priv->irq0 < 0) {
3991 		err = priv->irq0;
3992 		goto err;
3993 	}
3994 	priv->irq1 = platform_get_irq(pdev, 1);
3995 	if (priv->irq1 < 0) {
3996 		err = priv->irq1;
3997 		goto err;
3998 	}
3999 	priv->wol_irq = platform_get_irq_optional(pdev, 2);
4000 	if (priv->wol_irq == -EPROBE_DEFER) {
4001 		err = priv->wol_irq;
4002 		goto err;
4003 	}
4004 
4005 	priv->base = devm_platform_ioremap_resource(pdev, 0);
4006 	if (IS_ERR(priv->base)) {
4007 		err = PTR_ERR(priv->base);
4008 		goto err;
4009 	}
4010 
4011 	spin_lock_init(&priv->lock);
4012 
4013 	/* Set default pause parameters */
4014 	priv->autoneg_pause = 1;
4015 	priv->tx_pause = 1;
4016 	priv->rx_pause = 1;
4017 
4018 	SET_NETDEV_DEV(dev, &pdev->dev);
4019 	dev_set_drvdata(&pdev->dev, dev);
4020 	dev->watchdog_timeo = 2 * HZ;
4021 	dev->ethtool_ops = &bcmgenet_ethtool_ops;
4022 	dev->netdev_ops = &bcmgenet_netdev_ops;
4023 
4024 	priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
4025 
4026 	/* Set default features */
4027 	dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM |
4028 			 NETIF_F_RXCSUM;
4029 	dev->hw_features |= dev->features;
4030 	dev->vlan_features |= dev->features;
4031 
4032 	/* Request the WOL interrupt and advertise suspend if available */
4033 	priv->wol_irq_disabled = true;
4034 	if (priv->wol_irq > 0) {
4035 		err = devm_request_irq(&pdev->dev, priv->wol_irq,
4036 				       bcmgenet_wol_isr, 0, dev->name, priv);
4037 		if (!err)
4038 			device_set_wakeup_capable(&pdev->dev, 1);
4039 	}
4040 
4041 	/* Set the needed headroom to account for any possible
4042 	 * features enabling/disabling at runtime
4043 	 */
4044 	dev->needed_headroom += 64;
4045 
4046 	priv->dev = dev;
4047 	priv->pdev = pdev;
4048 
4049 	pdata = device_get_match_data(&pdev->dev);
4050 	if (pdata) {
4051 		priv->version = pdata->version;
4052 		priv->dma_max_burst_length = pdata->dma_max_burst_length;
4053 		priv->ephy_16nm = pdata->ephy_16nm;
4054 	} else {
4055 		priv->version = pd->genet_version;
4056 		priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH;
4057 	}
4058 
4059 	priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet");
4060 	if (IS_ERR(priv->clk)) {
4061 		dev_dbg(&priv->pdev->dev, "failed to get enet clock\n");
4062 		err = PTR_ERR(priv->clk);
4063 		goto err;
4064 	}
4065 
4066 	err = clk_prepare_enable(priv->clk);
4067 	if (err)
4068 		goto err;
4069 
4070 	bcmgenet_set_hw_params(priv);
4071 
4072 	err = -EIO;
4073 	if (priv->hw_params->flags & GENET_HAS_40BITS)
4074 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
4075 	if (err)
4076 		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4077 	if (err)
4078 		goto err_clk_disable;
4079 
4080 	/* Mii wait queue */
4081 	init_waitqueue_head(&priv->wq);
4082 	/* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
4083 	priv->rx_buf_len = RX_BUF_LENGTH;
4084 	INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
4085 
4086 	priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol");
4087 	if (IS_ERR(priv->clk_wol)) {
4088 		dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n");
4089 		err = PTR_ERR(priv->clk_wol);
4090 		goto err_clk_disable;
4091 	}
4092 
4093 	priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee");
4094 	if (IS_ERR(priv->clk_eee)) {
4095 		dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n");
4096 		err = PTR_ERR(priv->clk_eee);
4097 		goto err_clk_disable;
4098 	}
4099 
4100 	/* If this is an internal GPHY, power it on now, before UniMAC is
4101 	 * brought out of reset as absolutely no UniMAC activity is allowed
4102 	 */
4103 	if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL)
4104 		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4105 
4106 	if (pd && !IS_ERR_OR_NULL(pd->mac_address))
4107 		eth_hw_addr_set(dev, pd->mac_address);
4108 	else
4109 		if (device_get_ethdev_address(&pdev->dev, dev))
4110 			if (has_acpi_companion(&pdev->dev)) {
4111 				u8 addr[ETH_ALEN];
4112 
4113 				bcmgenet_get_hw_addr(priv, addr);
4114 				eth_hw_addr_set(dev, addr);
4115 			}
4116 
4117 	if (!is_valid_ether_addr(dev->dev_addr)) {
4118 		dev_warn(&pdev->dev, "using random Ethernet MAC\n");
4119 		eth_hw_addr_random(dev);
4120 	}
4121 
4122 	reset_umac(priv);
4123 
4124 	err = bcmgenet_mii_init(dev);
4125 	if (err)
4126 		goto err_clk_disable;
4127 
4128 	/* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
4129 	 * just the ring 16 descriptor based TX
4130 	 */
4131 	netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
4132 	netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
4133 
4134 	/* Set default coalescing parameters */
4135 	for (i = 0; i < priv->hw_params->rx_queues; i++)
4136 		priv->rx_rings[i].rx_max_coalesced_frames = 1;
4137 	priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1;
4138 
4139 	/* libphy will determine the link state */
4140 	netif_carrier_off(dev);
4141 
4142 	/* Turn off the main clock, WOL clock is handled separately */
4143 	clk_disable_unprepare(priv->clk);
4144 
4145 	err = register_netdev(dev);
4146 	if (err) {
4147 		bcmgenet_mii_exit(dev);
4148 		goto err;
4149 	}
4150 
4151 	return err;
4152 
4153 err_clk_disable:
4154 	clk_disable_unprepare(priv->clk);
4155 err:
4156 	free_netdev(dev);
4157 	return err;
4158 }
4159 
4160 static int bcmgenet_remove(struct platform_device *pdev)
4161 {
4162 	struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
4163 
4164 	dev_set_drvdata(&pdev->dev, NULL);
4165 	unregister_netdev(priv->dev);
4166 	bcmgenet_mii_exit(priv->dev);
4167 	free_netdev(priv->dev);
4168 
4169 	return 0;
4170 }
4171 
4172 static void bcmgenet_shutdown(struct platform_device *pdev)
4173 {
4174 	bcmgenet_remove(pdev);
4175 }
4176 
4177 #ifdef CONFIG_PM_SLEEP
4178 static int bcmgenet_resume_noirq(struct device *d)
4179 {
4180 	struct net_device *dev = dev_get_drvdata(d);
4181 	struct bcmgenet_priv *priv = netdev_priv(dev);
4182 	int ret;
4183 	u32 reg;
4184 
4185 	if (!netif_running(dev))
4186 		return 0;
4187 
4188 	/* Turn on the clock */
4189 	ret = clk_prepare_enable(priv->clk);
4190 	if (ret)
4191 		return ret;
4192 
4193 	if (device_may_wakeup(d) && priv->wolopts) {
4194 		/* Account for Wake-on-LAN events and clear those events
4195 		 * (Some devices need more time between enabling the clocks
4196 		 *  and the interrupt register reflecting the wake event so
4197 		 *  read the register twice)
4198 		 */
4199 		reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4200 		reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT);
4201 		if (reg & UMAC_IRQ_WAKE_EVENT)
4202 			pm_wakeup_event(&priv->pdev->dev, 0);
4203 	}
4204 
4205 	bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR);
4206 
4207 	return 0;
4208 }
4209 
4210 static int bcmgenet_resume(struct device *d)
4211 {
4212 	struct net_device *dev = dev_get_drvdata(d);
4213 	struct bcmgenet_priv *priv = netdev_priv(dev);
4214 	struct bcmgenet_rxnfc_rule *rule;
4215 	unsigned long dma_ctrl;
4216 	int ret;
4217 
4218 	if (!netif_running(dev))
4219 		return 0;
4220 
4221 	/* From WOL-enabled suspend, switch to regular clock */
4222 	if (device_may_wakeup(d) && priv->wolopts)
4223 		bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
4224 
4225 	/* If this is an internal GPHY, power it back on now, before UniMAC is
4226 	 * brought out of reset as absolutely no UniMAC activity is allowed
4227 	 */
4228 	if (priv->internal_phy)
4229 		bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
4230 
4231 	bcmgenet_umac_reset(priv);
4232 
4233 	init_umac(priv);
4234 
4235 	phy_init_hw(dev->phydev);
4236 
4237 	/* Speed settings must be restored */
4238 	genphy_config_aneg(dev->phydev);
4239 	bcmgenet_mii_config(priv->dev, false);
4240 
4241 	/* Restore enabled features */
4242 	bcmgenet_set_features(dev, dev->features);
4243 
4244 	bcmgenet_set_hw_addr(priv, dev->dev_addr);
4245 
4246 	/* Restore hardware filters */
4247 	bcmgenet_hfb_clear(priv);
4248 	list_for_each_entry(rule, &priv->rxnfc_list, list)
4249 		if (rule->state != BCMGENET_RXNFC_STATE_UNUSED)
4250 			bcmgenet_hfb_create_rxnfc_filter(priv, rule);
4251 
4252 	/* Disable RX/TX DMA and flush TX queues */
4253 	dma_ctrl = bcmgenet_dma_disable(priv);
4254 
4255 	/* Reinitialize TDMA and RDMA and SW housekeeping */
4256 	ret = bcmgenet_init_dma(priv);
4257 	if (ret) {
4258 		netdev_err(dev, "failed to initialize DMA\n");
4259 		goto out_clk_disable;
4260 	}
4261 
4262 	/* Always enable ring 16 - descriptor ring */
4263 	bcmgenet_enable_dma(priv, dma_ctrl);
4264 
4265 	if (!device_may_wakeup(d))
4266 		phy_resume(dev->phydev);
4267 
4268 	if (priv->eee.eee_enabled)
4269 		bcmgenet_eee_enable_set(dev, true);
4270 
4271 	bcmgenet_netif_start(dev);
4272 
4273 	netif_device_attach(dev);
4274 
4275 	return 0;
4276 
4277 out_clk_disable:
4278 	if (priv->internal_phy)
4279 		bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4280 	clk_disable_unprepare(priv->clk);
4281 	return ret;
4282 }
4283 
4284 static int bcmgenet_suspend(struct device *d)
4285 {
4286 	struct net_device *dev = dev_get_drvdata(d);
4287 	struct bcmgenet_priv *priv = netdev_priv(dev);
4288 
4289 	if (!netif_running(dev))
4290 		return 0;
4291 
4292 	netif_device_detach(dev);
4293 
4294 	bcmgenet_netif_stop(dev);
4295 
4296 	if (!device_may_wakeup(d))
4297 		phy_suspend(dev->phydev);
4298 
4299 	/* Disable filtering */
4300 	bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL);
4301 
4302 	return 0;
4303 }
4304 
4305 static int bcmgenet_suspend_noirq(struct device *d)
4306 {
4307 	struct net_device *dev = dev_get_drvdata(d);
4308 	struct bcmgenet_priv *priv = netdev_priv(dev);
4309 	int ret = 0;
4310 
4311 	if (!netif_running(dev))
4312 		return 0;
4313 
4314 	/* Prepare the device for Wake-on-LAN and switch to the slow clock */
4315 	if (device_may_wakeup(d) && priv->wolopts)
4316 		ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
4317 	else if (priv->internal_phy)
4318 		ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
4319 
4320 	/* Let the framework handle resumption and leave the clocks on */
4321 	if (ret)
4322 		return ret;
4323 
4324 	/* Turn off the clocks */
4325 	clk_disable_unprepare(priv->clk);
4326 
4327 	return 0;
4328 }
4329 #else
4330 #define bcmgenet_suspend	NULL
4331 #define bcmgenet_suspend_noirq	NULL
4332 #define bcmgenet_resume		NULL
4333 #define bcmgenet_resume_noirq	NULL
4334 #endif /* CONFIG_PM_SLEEP */
4335 
4336 static const struct dev_pm_ops bcmgenet_pm_ops = {
4337 	.suspend	= bcmgenet_suspend,
4338 	.suspend_noirq	= bcmgenet_suspend_noirq,
4339 	.resume		= bcmgenet_resume,
4340 	.resume_noirq	= bcmgenet_resume_noirq,
4341 };
4342 
4343 static const struct acpi_device_id genet_acpi_match[] = {
4344 	{ "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data },
4345 	{ },
4346 };
4347 MODULE_DEVICE_TABLE(acpi, genet_acpi_match);
4348 
4349 static struct platform_driver bcmgenet_driver = {
4350 	.probe	= bcmgenet_probe,
4351 	.remove	= bcmgenet_remove,
4352 	.shutdown = bcmgenet_shutdown,
4353 	.driver	= {
4354 		.name	= "bcmgenet",
4355 		.of_match_table = bcmgenet_match,
4356 		.pm	= &bcmgenet_pm_ops,
4357 		.acpi_match_table = genet_acpi_match,
4358 	},
4359 };
4360 module_platform_driver(bcmgenet_driver);
4361 
4362 MODULE_AUTHOR("Broadcom Corporation");
4363 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
4364 MODULE_ALIAS("platform:bcmgenet");
4365 MODULE_LICENSE("GPL");
4366 MODULE_SOFTDEP("pre: mdio-bcm-unimac");
4367