1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2020 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <net/arp.h> 27 28 #include <linux/mii.h> 29 #include <linux/ethtool.h> 30 #include <linux/netdevice.h> 31 #include <linux/inetdevice.h> 32 #include <linux/etherdevice.h> 33 #include <linux/skbuff.h> 34 #include <linux/in.h> 35 #include <linux/ip.h> 36 #include <linux/ipv6.h> 37 #include <linux/phy.h> 38 #include <linux/platform_data/bcmgenet.h> 39 40 #include <asm/unaligned.h> 41 42 #include "bcmgenet.h" 43 44 /* Maximum number of hardware queues, downsized if needed */ 45 #define GENET_MAX_MQ_CNT 4 46 47 /* Default highest priority queue for multi queue support */ 48 #define GENET_Q0_PRIORITY 0 49 50 #define GENET_Q16_RX_BD_CNT \ 51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 52 #define GENET_Q16_TX_BD_CNT \ 53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 54 55 #define RX_BUF_LENGTH 2048 56 #define SKB_ALIGNMENT 32 57 58 /* Tx/Rx DMA register offset, skip 256 descriptors */ 59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 60 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 61 62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 63 TOTAL_DESC * DMA_DESC_SIZE) 64 65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 66 TOTAL_DESC * DMA_DESC_SIZE) 67 68 /* Forward declarations */ 69 static void bcmgenet_set_rx_mode(struct net_device *dev); 70 71 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 72 { 73 /* MIPS chips strapped for BE will automagically configure the 74 * peripheral registers for CPU-native byte order. 75 */ 76 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 77 __raw_writel(value, offset); 78 else 79 writel_relaxed(value, offset); 80 } 81 82 static inline u32 bcmgenet_readl(void __iomem *offset) 83 { 84 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 85 return __raw_readl(offset); 86 else 87 return readl_relaxed(offset); 88 } 89 90 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 91 void __iomem *d, u32 value) 92 { 93 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 94 } 95 96 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 97 void __iomem *d, 98 dma_addr_t addr) 99 { 100 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 101 102 /* Register writes to GISB bus can take couple hundred nanoseconds 103 * and are done for each packet, save these expensive writes unless 104 * the platform is explicitly configured for 64-bits/LPAE. 105 */ 106 #ifdef CONFIG_PHYS_ADDR_T_64BIT 107 if (priv->hw_params->flags & GENET_HAS_40BITS) 108 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 109 #endif 110 } 111 112 /* Combined address + length/status setter */ 113 static inline void dmadesc_set(struct bcmgenet_priv *priv, 114 void __iomem *d, dma_addr_t addr, u32 val) 115 { 116 dmadesc_set_addr(priv, d, addr); 117 dmadesc_set_length_status(priv, d, val); 118 } 119 120 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 121 void __iomem *d) 122 { 123 dma_addr_t addr; 124 125 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 126 127 /* Register writes to GISB bus can take couple hundred nanoseconds 128 * and are done for each packet, save these expensive writes unless 129 * the platform is explicitly configured for 64-bits/LPAE. 130 */ 131 #ifdef CONFIG_PHYS_ADDR_T_64BIT 132 if (priv->hw_params->flags & GENET_HAS_40BITS) 133 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 134 #endif 135 return addr; 136 } 137 138 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 139 140 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 141 NETIF_MSG_LINK) 142 143 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 144 { 145 if (GENET_IS_V1(priv)) 146 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 147 else 148 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 149 } 150 151 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 152 { 153 if (GENET_IS_V1(priv)) 154 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 155 else 156 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 157 } 158 159 /* These macros are defined to deal with register map change 160 * between GENET1.1 and GENET2. Only those currently being used 161 * by driver are defined. 162 */ 163 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 164 { 165 if (GENET_IS_V1(priv)) 166 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 167 else 168 return bcmgenet_readl(priv->base + 169 priv->hw_params->tbuf_offset + TBUF_CTRL); 170 } 171 172 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 173 { 174 if (GENET_IS_V1(priv)) 175 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 176 else 177 bcmgenet_writel(val, priv->base + 178 priv->hw_params->tbuf_offset + TBUF_CTRL); 179 } 180 181 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 182 { 183 if (GENET_IS_V1(priv)) 184 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 185 else 186 return bcmgenet_readl(priv->base + 187 priv->hw_params->tbuf_offset + TBUF_BP_MC); 188 } 189 190 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 191 { 192 if (GENET_IS_V1(priv)) 193 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 194 else 195 bcmgenet_writel(val, priv->base + 196 priv->hw_params->tbuf_offset + TBUF_BP_MC); 197 } 198 199 /* RX/TX DMA register accessors */ 200 enum dma_reg { 201 DMA_RING_CFG = 0, 202 DMA_CTRL, 203 DMA_STATUS, 204 DMA_SCB_BURST_SIZE, 205 DMA_ARB_CTRL, 206 DMA_PRIORITY_0, 207 DMA_PRIORITY_1, 208 DMA_PRIORITY_2, 209 DMA_INDEX2RING_0, 210 DMA_INDEX2RING_1, 211 DMA_INDEX2RING_2, 212 DMA_INDEX2RING_3, 213 DMA_INDEX2RING_4, 214 DMA_INDEX2RING_5, 215 DMA_INDEX2RING_6, 216 DMA_INDEX2RING_7, 217 DMA_RING0_TIMEOUT, 218 DMA_RING1_TIMEOUT, 219 DMA_RING2_TIMEOUT, 220 DMA_RING3_TIMEOUT, 221 DMA_RING4_TIMEOUT, 222 DMA_RING5_TIMEOUT, 223 DMA_RING6_TIMEOUT, 224 DMA_RING7_TIMEOUT, 225 DMA_RING8_TIMEOUT, 226 DMA_RING9_TIMEOUT, 227 DMA_RING10_TIMEOUT, 228 DMA_RING11_TIMEOUT, 229 DMA_RING12_TIMEOUT, 230 DMA_RING13_TIMEOUT, 231 DMA_RING14_TIMEOUT, 232 DMA_RING15_TIMEOUT, 233 DMA_RING16_TIMEOUT, 234 }; 235 236 static const u8 bcmgenet_dma_regs_v3plus[] = { 237 [DMA_RING_CFG] = 0x00, 238 [DMA_CTRL] = 0x04, 239 [DMA_STATUS] = 0x08, 240 [DMA_SCB_BURST_SIZE] = 0x0C, 241 [DMA_ARB_CTRL] = 0x2C, 242 [DMA_PRIORITY_0] = 0x30, 243 [DMA_PRIORITY_1] = 0x34, 244 [DMA_PRIORITY_2] = 0x38, 245 [DMA_RING0_TIMEOUT] = 0x2C, 246 [DMA_RING1_TIMEOUT] = 0x30, 247 [DMA_RING2_TIMEOUT] = 0x34, 248 [DMA_RING3_TIMEOUT] = 0x38, 249 [DMA_RING4_TIMEOUT] = 0x3c, 250 [DMA_RING5_TIMEOUT] = 0x40, 251 [DMA_RING6_TIMEOUT] = 0x44, 252 [DMA_RING7_TIMEOUT] = 0x48, 253 [DMA_RING8_TIMEOUT] = 0x4c, 254 [DMA_RING9_TIMEOUT] = 0x50, 255 [DMA_RING10_TIMEOUT] = 0x54, 256 [DMA_RING11_TIMEOUT] = 0x58, 257 [DMA_RING12_TIMEOUT] = 0x5c, 258 [DMA_RING13_TIMEOUT] = 0x60, 259 [DMA_RING14_TIMEOUT] = 0x64, 260 [DMA_RING15_TIMEOUT] = 0x68, 261 [DMA_RING16_TIMEOUT] = 0x6C, 262 [DMA_INDEX2RING_0] = 0x70, 263 [DMA_INDEX2RING_1] = 0x74, 264 [DMA_INDEX2RING_2] = 0x78, 265 [DMA_INDEX2RING_3] = 0x7C, 266 [DMA_INDEX2RING_4] = 0x80, 267 [DMA_INDEX2RING_5] = 0x84, 268 [DMA_INDEX2RING_6] = 0x88, 269 [DMA_INDEX2RING_7] = 0x8C, 270 }; 271 272 static const u8 bcmgenet_dma_regs_v2[] = { 273 [DMA_RING_CFG] = 0x00, 274 [DMA_CTRL] = 0x04, 275 [DMA_STATUS] = 0x08, 276 [DMA_SCB_BURST_SIZE] = 0x0C, 277 [DMA_ARB_CTRL] = 0x30, 278 [DMA_PRIORITY_0] = 0x34, 279 [DMA_PRIORITY_1] = 0x38, 280 [DMA_PRIORITY_2] = 0x3C, 281 [DMA_RING0_TIMEOUT] = 0x2C, 282 [DMA_RING1_TIMEOUT] = 0x30, 283 [DMA_RING2_TIMEOUT] = 0x34, 284 [DMA_RING3_TIMEOUT] = 0x38, 285 [DMA_RING4_TIMEOUT] = 0x3c, 286 [DMA_RING5_TIMEOUT] = 0x40, 287 [DMA_RING6_TIMEOUT] = 0x44, 288 [DMA_RING7_TIMEOUT] = 0x48, 289 [DMA_RING8_TIMEOUT] = 0x4c, 290 [DMA_RING9_TIMEOUT] = 0x50, 291 [DMA_RING10_TIMEOUT] = 0x54, 292 [DMA_RING11_TIMEOUT] = 0x58, 293 [DMA_RING12_TIMEOUT] = 0x5c, 294 [DMA_RING13_TIMEOUT] = 0x60, 295 [DMA_RING14_TIMEOUT] = 0x64, 296 [DMA_RING15_TIMEOUT] = 0x68, 297 [DMA_RING16_TIMEOUT] = 0x6C, 298 }; 299 300 static const u8 bcmgenet_dma_regs_v1[] = { 301 [DMA_CTRL] = 0x00, 302 [DMA_STATUS] = 0x04, 303 [DMA_SCB_BURST_SIZE] = 0x0C, 304 [DMA_ARB_CTRL] = 0x30, 305 [DMA_PRIORITY_0] = 0x34, 306 [DMA_PRIORITY_1] = 0x38, 307 [DMA_PRIORITY_2] = 0x3C, 308 [DMA_RING0_TIMEOUT] = 0x2C, 309 [DMA_RING1_TIMEOUT] = 0x30, 310 [DMA_RING2_TIMEOUT] = 0x34, 311 [DMA_RING3_TIMEOUT] = 0x38, 312 [DMA_RING4_TIMEOUT] = 0x3c, 313 [DMA_RING5_TIMEOUT] = 0x40, 314 [DMA_RING6_TIMEOUT] = 0x44, 315 [DMA_RING7_TIMEOUT] = 0x48, 316 [DMA_RING8_TIMEOUT] = 0x4c, 317 [DMA_RING9_TIMEOUT] = 0x50, 318 [DMA_RING10_TIMEOUT] = 0x54, 319 [DMA_RING11_TIMEOUT] = 0x58, 320 [DMA_RING12_TIMEOUT] = 0x5c, 321 [DMA_RING13_TIMEOUT] = 0x60, 322 [DMA_RING14_TIMEOUT] = 0x64, 323 [DMA_RING15_TIMEOUT] = 0x68, 324 [DMA_RING16_TIMEOUT] = 0x6C, 325 }; 326 327 /* Set at runtime once bcmgenet version is known */ 328 static const u8 *bcmgenet_dma_regs; 329 330 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 331 { 332 return netdev_priv(dev_get_drvdata(dev)); 333 } 334 335 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 336 enum dma_reg r) 337 { 338 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 339 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 340 } 341 342 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 343 u32 val, enum dma_reg r) 344 { 345 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 346 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 347 } 348 349 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 350 enum dma_reg r) 351 { 352 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 353 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 354 } 355 356 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 357 u32 val, enum dma_reg r) 358 { 359 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 360 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 361 } 362 363 /* RDMA/TDMA ring registers and accessors 364 * we merge the common fields and just prefix with T/D the registers 365 * having different meaning depending on the direction 366 */ 367 enum dma_ring_reg { 368 TDMA_READ_PTR = 0, 369 RDMA_WRITE_PTR = TDMA_READ_PTR, 370 TDMA_READ_PTR_HI, 371 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 372 TDMA_CONS_INDEX, 373 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 374 TDMA_PROD_INDEX, 375 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 376 DMA_RING_BUF_SIZE, 377 DMA_START_ADDR, 378 DMA_START_ADDR_HI, 379 DMA_END_ADDR, 380 DMA_END_ADDR_HI, 381 DMA_MBUF_DONE_THRESH, 382 TDMA_FLOW_PERIOD, 383 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 384 TDMA_WRITE_PTR, 385 RDMA_READ_PTR = TDMA_WRITE_PTR, 386 TDMA_WRITE_PTR_HI, 387 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 388 }; 389 390 /* GENET v4 supports 40-bits pointer addressing 391 * for obvious reasons the LO and HI word parts 392 * are contiguous, but this offsets the other 393 * registers. 394 */ 395 static const u8 genet_dma_ring_regs_v4[] = { 396 [TDMA_READ_PTR] = 0x00, 397 [TDMA_READ_PTR_HI] = 0x04, 398 [TDMA_CONS_INDEX] = 0x08, 399 [TDMA_PROD_INDEX] = 0x0C, 400 [DMA_RING_BUF_SIZE] = 0x10, 401 [DMA_START_ADDR] = 0x14, 402 [DMA_START_ADDR_HI] = 0x18, 403 [DMA_END_ADDR] = 0x1C, 404 [DMA_END_ADDR_HI] = 0x20, 405 [DMA_MBUF_DONE_THRESH] = 0x24, 406 [TDMA_FLOW_PERIOD] = 0x28, 407 [TDMA_WRITE_PTR] = 0x2C, 408 [TDMA_WRITE_PTR_HI] = 0x30, 409 }; 410 411 static const u8 genet_dma_ring_regs_v123[] = { 412 [TDMA_READ_PTR] = 0x00, 413 [TDMA_CONS_INDEX] = 0x04, 414 [TDMA_PROD_INDEX] = 0x08, 415 [DMA_RING_BUF_SIZE] = 0x0C, 416 [DMA_START_ADDR] = 0x10, 417 [DMA_END_ADDR] = 0x14, 418 [DMA_MBUF_DONE_THRESH] = 0x18, 419 [TDMA_FLOW_PERIOD] = 0x1C, 420 [TDMA_WRITE_PTR] = 0x20, 421 }; 422 423 /* Set at runtime once GENET version is known */ 424 static const u8 *genet_dma_ring_regs; 425 426 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 427 unsigned int ring, 428 enum dma_ring_reg r) 429 { 430 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 431 (DMA_RING_SIZE * ring) + 432 genet_dma_ring_regs[r]); 433 } 434 435 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 436 unsigned int ring, u32 val, 437 enum dma_ring_reg r) 438 { 439 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 440 (DMA_RING_SIZE * ring) + 441 genet_dma_ring_regs[r]); 442 } 443 444 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 445 unsigned int ring, 446 enum dma_ring_reg r) 447 { 448 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 449 (DMA_RING_SIZE * ring) + 450 genet_dma_ring_regs[r]); 451 } 452 453 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 454 unsigned int ring, u32 val, 455 enum dma_ring_reg r) 456 { 457 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 458 (DMA_RING_SIZE * ring) + 459 genet_dma_ring_regs[r]); 460 } 461 462 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index) 463 { 464 u32 offset; 465 u32 reg; 466 467 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32); 468 reg = bcmgenet_hfb_reg_readl(priv, offset); 469 reg |= (1 << (f_index % 32)); 470 bcmgenet_hfb_reg_writel(priv, reg, offset); 471 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 472 reg |= RBUF_HFB_EN; 473 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 474 } 475 476 static void bcmgenet_hfb_disable_filter(struct bcmgenet_priv *priv, u32 f_index) 477 { 478 u32 offset, reg, reg1; 479 480 offset = HFB_FLT_ENABLE_V3PLUS; 481 reg = bcmgenet_hfb_reg_readl(priv, offset); 482 reg1 = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 483 if (f_index < 32) { 484 reg1 &= ~(1 << (f_index % 32)); 485 bcmgenet_hfb_reg_writel(priv, reg1, offset + sizeof(u32)); 486 } else { 487 reg &= ~(1 << (f_index % 32)); 488 bcmgenet_hfb_reg_writel(priv, reg, offset); 489 } 490 if (!reg && !reg1) { 491 reg = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 492 reg &= ~RBUF_HFB_EN; 493 bcmgenet_hfb_reg_writel(priv, reg, HFB_CTRL); 494 } 495 } 496 497 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv, 498 u32 f_index, u32 rx_queue) 499 { 500 u32 offset; 501 u32 reg; 502 503 offset = f_index / 8; 504 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset); 505 reg &= ~(0xF << (4 * (f_index % 8))); 506 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8))); 507 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset); 508 } 509 510 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv, 511 u32 f_index, u32 f_length) 512 { 513 u32 offset; 514 u32 reg; 515 516 offset = HFB_FLT_LEN_V3PLUS + 517 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) * 518 sizeof(u32); 519 reg = bcmgenet_hfb_reg_readl(priv, offset); 520 reg &= ~(0xFF << (8 * (f_index % 4))); 521 reg |= ((f_length & 0xFF) << (8 * (f_index % 4))); 522 bcmgenet_hfb_reg_writel(priv, reg, offset); 523 } 524 525 static int bcmgenet_hfb_validate_mask(void *mask, size_t size) 526 { 527 while (size) { 528 switch (*(unsigned char *)mask++) { 529 case 0x00: 530 case 0x0f: 531 case 0xf0: 532 case 0xff: 533 size--; 534 continue; 535 default: 536 return -EINVAL; 537 } 538 } 539 540 return 0; 541 } 542 543 #define VALIDATE_MASK(x) \ 544 bcmgenet_hfb_validate_mask(&(x), sizeof(x)) 545 546 static int bcmgenet_hfb_insert_data(u32 *f, int offset, 547 void *val, void *mask, size_t size) 548 { 549 int index; 550 u32 tmp; 551 552 index = offset / 2; 553 tmp = f[index]; 554 555 while (size--) { 556 if (offset++ & 1) { 557 tmp &= ~0x300FF; 558 tmp |= (*(unsigned char *)val++); 559 switch ((*(unsigned char *)mask++)) { 560 case 0xFF: 561 tmp |= 0x30000; 562 break; 563 case 0xF0: 564 tmp |= 0x20000; 565 break; 566 case 0x0F: 567 tmp |= 0x10000; 568 break; 569 } 570 f[index++] = tmp; 571 if (size) 572 tmp = f[index]; 573 } else { 574 tmp &= ~0xCFF00; 575 tmp |= (*(unsigned char *)val++) << 8; 576 switch ((*(unsigned char *)mask++)) { 577 case 0xFF: 578 tmp |= 0xC0000; 579 break; 580 case 0xF0: 581 tmp |= 0x80000; 582 break; 583 case 0x0F: 584 tmp |= 0x40000; 585 break; 586 } 587 if (!size) 588 f[index] = tmp; 589 } 590 } 591 592 return 0; 593 } 594 595 static void bcmgenet_hfb_set_filter(struct bcmgenet_priv *priv, u32 *f_data, 596 u32 f_length, u32 rx_queue, int f_index) 597 { 598 u32 base = f_index * priv->hw_params->hfb_filter_size; 599 int i; 600 601 for (i = 0; i < f_length; i++) 602 bcmgenet_hfb_writel(priv, f_data[i], (base + i) * sizeof(u32)); 603 604 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length); 605 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue); 606 } 607 608 static int bcmgenet_hfb_create_rxnfc_filter(struct bcmgenet_priv *priv, 609 struct bcmgenet_rxnfc_rule *rule) 610 { 611 struct ethtool_rx_flow_spec *fs = &rule->fs; 612 int err = 0, offset = 0, f_length = 0; 613 u8 val_8, mask_8; 614 __be16 val_16; 615 u16 mask_16; 616 size_t size; 617 u32 *f_data; 618 619 f_data = kcalloc(priv->hw_params->hfb_filter_size, sizeof(u32), 620 GFP_KERNEL); 621 if (!f_data) 622 return -ENOMEM; 623 624 if (fs->flow_type & FLOW_MAC_EXT) { 625 bcmgenet_hfb_insert_data(f_data, 0, 626 &fs->h_ext.h_dest, &fs->m_ext.h_dest, 627 sizeof(fs->h_ext.h_dest)); 628 } 629 630 if (fs->flow_type & FLOW_EXT) { 631 if (fs->m_ext.vlan_etype || 632 fs->m_ext.vlan_tci) { 633 bcmgenet_hfb_insert_data(f_data, 12, 634 &fs->h_ext.vlan_etype, 635 &fs->m_ext.vlan_etype, 636 sizeof(fs->h_ext.vlan_etype)); 637 bcmgenet_hfb_insert_data(f_data, 14, 638 &fs->h_ext.vlan_tci, 639 &fs->m_ext.vlan_tci, 640 sizeof(fs->h_ext.vlan_tci)); 641 offset += VLAN_HLEN; 642 f_length += DIV_ROUND_UP(VLAN_HLEN, 2); 643 } 644 } 645 646 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 647 case ETHER_FLOW: 648 f_length += DIV_ROUND_UP(ETH_HLEN, 2); 649 bcmgenet_hfb_insert_data(f_data, 0, 650 &fs->h_u.ether_spec.h_dest, 651 &fs->m_u.ether_spec.h_dest, 652 sizeof(fs->h_u.ether_spec.h_dest)); 653 bcmgenet_hfb_insert_data(f_data, ETH_ALEN, 654 &fs->h_u.ether_spec.h_source, 655 &fs->m_u.ether_spec.h_source, 656 sizeof(fs->h_u.ether_spec.h_source)); 657 bcmgenet_hfb_insert_data(f_data, (2 * ETH_ALEN) + offset, 658 &fs->h_u.ether_spec.h_proto, 659 &fs->m_u.ether_spec.h_proto, 660 sizeof(fs->h_u.ether_spec.h_proto)); 661 break; 662 case IP_USER_FLOW: 663 f_length += DIV_ROUND_UP(ETH_HLEN + 20, 2); 664 /* Specify IP Ether Type */ 665 val_16 = htons(ETH_P_IP); 666 mask_16 = 0xFFFF; 667 bcmgenet_hfb_insert_data(f_data, (2 * ETH_ALEN) + offset, 668 &val_16, &mask_16, sizeof(val_16)); 669 bcmgenet_hfb_insert_data(f_data, 15 + offset, 670 &fs->h_u.usr_ip4_spec.tos, 671 &fs->m_u.usr_ip4_spec.tos, 672 sizeof(fs->h_u.usr_ip4_spec.tos)); 673 bcmgenet_hfb_insert_data(f_data, 23 + offset, 674 &fs->h_u.usr_ip4_spec.proto, 675 &fs->m_u.usr_ip4_spec.proto, 676 sizeof(fs->h_u.usr_ip4_spec.proto)); 677 bcmgenet_hfb_insert_data(f_data, 26 + offset, 678 &fs->h_u.usr_ip4_spec.ip4src, 679 &fs->m_u.usr_ip4_spec.ip4src, 680 sizeof(fs->h_u.usr_ip4_spec.ip4src)); 681 bcmgenet_hfb_insert_data(f_data, 30 + offset, 682 &fs->h_u.usr_ip4_spec.ip4dst, 683 &fs->m_u.usr_ip4_spec.ip4dst, 684 sizeof(fs->h_u.usr_ip4_spec.ip4dst)); 685 if (!fs->m_u.usr_ip4_spec.l4_4_bytes) 686 break; 687 688 /* Only supports 20 byte IPv4 header */ 689 val_8 = 0x45; 690 mask_8 = 0xFF; 691 bcmgenet_hfb_insert_data(f_data, ETH_HLEN + offset, 692 &val_8, &mask_8, 693 sizeof(val_8)); 694 size = sizeof(fs->h_u.usr_ip4_spec.l4_4_bytes); 695 bcmgenet_hfb_insert_data(f_data, 696 ETH_HLEN + 20 + offset, 697 &fs->h_u.usr_ip4_spec.l4_4_bytes, 698 &fs->m_u.usr_ip4_spec.l4_4_bytes, 699 size); 700 f_length += DIV_ROUND_UP(size, 2); 701 break; 702 } 703 704 if (!fs->ring_cookie || fs->ring_cookie == RX_CLS_FLOW_WAKE) { 705 /* Ring 0 flows can be handled by the default Descriptor Ring 706 * We'll map them to ring 0, but don't enable the filter 707 */ 708 bcmgenet_hfb_set_filter(priv, f_data, f_length, 0, 709 fs->location); 710 rule->state = BCMGENET_RXNFC_STATE_DISABLED; 711 } else { 712 /* Other Rx rings are direct mapped here */ 713 bcmgenet_hfb_set_filter(priv, f_data, f_length, 714 fs->ring_cookie, fs->location); 715 bcmgenet_hfb_enable_filter(priv, fs->location); 716 rule->state = BCMGENET_RXNFC_STATE_ENABLED; 717 } 718 719 kfree(f_data); 720 721 return err; 722 } 723 724 /* bcmgenet_hfb_clear 725 * 726 * Clear Hardware Filter Block and disable all filtering. 727 */ 728 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 729 { 730 u32 i; 731 732 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 733 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 734 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 735 736 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 737 bcmgenet_rdma_writel(priv, 0x0, i); 738 739 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 740 bcmgenet_hfb_reg_writel(priv, 0x0, 741 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 742 743 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 744 priv->hw_params->hfb_filter_size; i++) 745 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 746 } 747 748 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 749 { 750 int i; 751 752 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 753 return; 754 755 INIT_LIST_HEAD(&priv->rxnfc_list); 756 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) { 757 INIT_LIST_HEAD(&priv->rxnfc_rules[i].list); 758 priv->rxnfc_rules[i].state = BCMGENET_RXNFC_STATE_UNUSED; 759 } 760 761 bcmgenet_hfb_clear(priv); 762 } 763 764 static int bcmgenet_begin(struct net_device *dev) 765 { 766 struct bcmgenet_priv *priv = netdev_priv(dev); 767 768 /* Turn on the clock */ 769 return clk_prepare_enable(priv->clk); 770 } 771 772 static void bcmgenet_complete(struct net_device *dev) 773 { 774 struct bcmgenet_priv *priv = netdev_priv(dev); 775 776 /* Turn off the clock */ 777 clk_disable_unprepare(priv->clk); 778 } 779 780 static int bcmgenet_get_link_ksettings(struct net_device *dev, 781 struct ethtool_link_ksettings *cmd) 782 { 783 if (!netif_running(dev)) 784 return -EINVAL; 785 786 if (!dev->phydev) 787 return -ENODEV; 788 789 phy_ethtool_ksettings_get(dev->phydev, cmd); 790 791 return 0; 792 } 793 794 static int bcmgenet_set_link_ksettings(struct net_device *dev, 795 const struct ethtool_link_ksettings *cmd) 796 { 797 if (!netif_running(dev)) 798 return -EINVAL; 799 800 if (!dev->phydev) 801 return -ENODEV; 802 803 return phy_ethtool_ksettings_set(dev->phydev, cmd); 804 } 805 806 static int bcmgenet_set_features(struct net_device *dev, 807 netdev_features_t features) 808 { 809 struct bcmgenet_priv *priv = netdev_priv(dev); 810 u32 reg; 811 int ret; 812 813 ret = clk_prepare_enable(priv->clk); 814 if (ret) 815 return ret; 816 817 /* Make sure we reflect the value of CRC_CMD_FWD */ 818 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 819 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 820 821 clk_disable_unprepare(priv->clk); 822 823 return ret; 824 } 825 826 static u32 bcmgenet_get_msglevel(struct net_device *dev) 827 { 828 struct bcmgenet_priv *priv = netdev_priv(dev); 829 830 return priv->msg_enable; 831 } 832 833 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 834 { 835 struct bcmgenet_priv *priv = netdev_priv(dev); 836 837 priv->msg_enable = level; 838 } 839 840 static int bcmgenet_get_coalesce(struct net_device *dev, 841 struct ethtool_coalesce *ec) 842 { 843 struct bcmgenet_priv *priv = netdev_priv(dev); 844 struct bcmgenet_rx_ring *ring; 845 unsigned int i; 846 847 ec->tx_max_coalesced_frames = 848 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 849 DMA_MBUF_DONE_THRESH); 850 ec->rx_max_coalesced_frames = 851 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 852 DMA_MBUF_DONE_THRESH); 853 ec->rx_coalesce_usecs = 854 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 855 856 for (i = 0; i < priv->hw_params->rx_queues; i++) { 857 ring = &priv->rx_rings[i]; 858 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 859 } 860 ring = &priv->rx_rings[DESC_INDEX]; 861 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 862 863 return 0; 864 } 865 866 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 867 u32 usecs, u32 pkts) 868 { 869 struct bcmgenet_priv *priv = ring->priv; 870 unsigned int i = ring->index; 871 u32 reg; 872 873 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 874 875 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 876 reg &= ~DMA_TIMEOUT_MASK; 877 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 878 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 879 } 880 881 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 882 struct ethtool_coalesce *ec) 883 { 884 struct dim_cq_moder moder; 885 u32 usecs, pkts; 886 887 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 888 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 889 usecs = ring->rx_coalesce_usecs; 890 pkts = ring->rx_max_coalesced_frames; 891 892 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 893 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 894 usecs = moder.usec; 895 pkts = moder.pkts; 896 } 897 898 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 899 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 900 } 901 902 static int bcmgenet_set_coalesce(struct net_device *dev, 903 struct ethtool_coalesce *ec) 904 { 905 struct bcmgenet_priv *priv = netdev_priv(dev); 906 unsigned int i; 907 908 /* Base system clock is 125Mhz, DMA timeout is this reference clock 909 * divided by 1024, which yields roughly 8.192us, our maximum value 910 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 911 */ 912 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 913 ec->tx_max_coalesced_frames == 0 || 914 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 915 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 916 return -EINVAL; 917 918 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 919 return -EINVAL; 920 921 /* GENET TDMA hardware does not support a configurable timeout, but will 922 * always generate an interrupt either after MBDONE packets have been 923 * transmitted, or when the ring is empty. 924 */ 925 926 /* Program all TX queues with the same values, as there is no 927 * ethtool knob to do coalescing on a per-queue basis 928 */ 929 for (i = 0; i < priv->hw_params->tx_queues; i++) 930 bcmgenet_tdma_ring_writel(priv, i, 931 ec->tx_max_coalesced_frames, 932 DMA_MBUF_DONE_THRESH); 933 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 934 ec->tx_max_coalesced_frames, 935 DMA_MBUF_DONE_THRESH); 936 937 for (i = 0; i < priv->hw_params->rx_queues; i++) 938 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 939 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 940 941 return 0; 942 } 943 944 /* standard ethtool support functions. */ 945 enum bcmgenet_stat_type { 946 BCMGENET_STAT_NETDEV = -1, 947 BCMGENET_STAT_MIB_RX, 948 BCMGENET_STAT_MIB_TX, 949 BCMGENET_STAT_RUNT, 950 BCMGENET_STAT_MISC, 951 BCMGENET_STAT_SOFT, 952 }; 953 954 struct bcmgenet_stats { 955 char stat_string[ETH_GSTRING_LEN]; 956 int stat_sizeof; 957 int stat_offset; 958 enum bcmgenet_stat_type type; 959 /* reg offset from UMAC base for misc counters */ 960 u16 reg_offset; 961 }; 962 963 #define STAT_NETDEV(m) { \ 964 .stat_string = __stringify(m), \ 965 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 966 .stat_offset = offsetof(struct net_device_stats, m), \ 967 .type = BCMGENET_STAT_NETDEV, \ 968 } 969 970 #define STAT_GENET_MIB(str, m, _type) { \ 971 .stat_string = str, \ 972 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 973 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 974 .type = _type, \ 975 } 976 977 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 978 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 979 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 980 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 981 982 #define STAT_GENET_MISC(str, m, offset) { \ 983 .stat_string = str, \ 984 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 985 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 986 .type = BCMGENET_STAT_MISC, \ 987 .reg_offset = offset, \ 988 } 989 990 #define STAT_GENET_Q(num) \ 991 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 992 tx_rings[num].packets), \ 993 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 994 tx_rings[num].bytes), \ 995 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 996 rx_rings[num].bytes), \ 997 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 998 rx_rings[num].packets), \ 999 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 1000 rx_rings[num].errors), \ 1001 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 1002 rx_rings[num].dropped) 1003 1004 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 1005 * between the end of TX stats and the beginning of the RX RUNT 1006 */ 1007 #define BCMGENET_STAT_OFFSET 0xc 1008 1009 /* Hardware counters must be kept in sync because the order/offset 1010 * is important here (order in structure declaration = order in hardware) 1011 */ 1012 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 1013 /* general stats */ 1014 STAT_NETDEV(rx_packets), 1015 STAT_NETDEV(tx_packets), 1016 STAT_NETDEV(rx_bytes), 1017 STAT_NETDEV(tx_bytes), 1018 STAT_NETDEV(rx_errors), 1019 STAT_NETDEV(tx_errors), 1020 STAT_NETDEV(rx_dropped), 1021 STAT_NETDEV(tx_dropped), 1022 STAT_NETDEV(multicast), 1023 /* UniMAC RSV counters */ 1024 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 1025 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 1026 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 1027 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 1028 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 1029 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 1030 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 1031 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 1032 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 1033 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 1034 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 1035 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 1036 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 1037 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 1038 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 1039 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 1040 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 1041 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 1042 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 1043 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 1044 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 1045 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 1046 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 1047 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 1048 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 1049 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 1050 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 1051 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 1052 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 1053 /* UniMAC TSV counters */ 1054 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 1055 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 1056 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 1057 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 1058 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 1059 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 1060 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 1061 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 1062 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 1063 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 1064 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 1065 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 1066 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 1067 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 1068 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 1069 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 1070 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 1071 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 1072 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 1073 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 1074 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 1075 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 1076 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 1077 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 1078 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 1079 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 1080 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 1081 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 1082 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 1083 /* UniMAC RUNT counters */ 1084 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 1085 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 1086 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 1087 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 1088 /* Misc UniMAC counters */ 1089 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 1090 UMAC_RBUF_OVFL_CNT_V1), 1091 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 1092 UMAC_RBUF_ERR_CNT_V1), 1093 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 1094 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 1095 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 1096 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 1097 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 1098 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 1099 mib.tx_realloc_tsb_failed), 1100 /* Per TX queues */ 1101 STAT_GENET_Q(0), 1102 STAT_GENET_Q(1), 1103 STAT_GENET_Q(2), 1104 STAT_GENET_Q(3), 1105 STAT_GENET_Q(16), 1106 }; 1107 1108 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 1109 1110 static void bcmgenet_get_drvinfo(struct net_device *dev, 1111 struct ethtool_drvinfo *info) 1112 { 1113 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 1114 } 1115 1116 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 1117 { 1118 switch (string_set) { 1119 case ETH_SS_STATS: 1120 return BCMGENET_STATS_LEN; 1121 default: 1122 return -EOPNOTSUPP; 1123 } 1124 } 1125 1126 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 1127 u8 *data) 1128 { 1129 int i; 1130 1131 switch (stringset) { 1132 case ETH_SS_STATS: 1133 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1134 memcpy(data + i * ETH_GSTRING_LEN, 1135 bcmgenet_gstrings_stats[i].stat_string, 1136 ETH_GSTRING_LEN); 1137 } 1138 break; 1139 } 1140 } 1141 1142 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 1143 { 1144 u16 new_offset; 1145 u32 val; 1146 1147 switch (offset) { 1148 case UMAC_RBUF_OVFL_CNT_V1: 1149 if (GENET_IS_V2(priv)) 1150 new_offset = RBUF_OVFL_CNT_V2; 1151 else 1152 new_offset = RBUF_OVFL_CNT_V3PLUS; 1153 1154 val = bcmgenet_rbuf_readl(priv, new_offset); 1155 /* clear if overflowed */ 1156 if (val == ~0) 1157 bcmgenet_rbuf_writel(priv, 0, new_offset); 1158 break; 1159 case UMAC_RBUF_ERR_CNT_V1: 1160 if (GENET_IS_V2(priv)) 1161 new_offset = RBUF_ERR_CNT_V2; 1162 else 1163 new_offset = RBUF_ERR_CNT_V3PLUS; 1164 1165 val = bcmgenet_rbuf_readl(priv, new_offset); 1166 /* clear if overflowed */ 1167 if (val == ~0) 1168 bcmgenet_rbuf_writel(priv, 0, new_offset); 1169 break; 1170 default: 1171 val = bcmgenet_umac_readl(priv, offset); 1172 /* clear if overflowed */ 1173 if (val == ~0) 1174 bcmgenet_umac_writel(priv, 0, offset); 1175 break; 1176 } 1177 1178 return val; 1179 } 1180 1181 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 1182 { 1183 int i, j = 0; 1184 1185 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1186 const struct bcmgenet_stats *s; 1187 u8 offset = 0; 1188 u32 val = 0; 1189 char *p; 1190 1191 s = &bcmgenet_gstrings_stats[i]; 1192 switch (s->type) { 1193 case BCMGENET_STAT_NETDEV: 1194 case BCMGENET_STAT_SOFT: 1195 continue; 1196 case BCMGENET_STAT_RUNT: 1197 offset += BCMGENET_STAT_OFFSET; 1198 /* fall through */ 1199 case BCMGENET_STAT_MIB_TX: 1200 offset += BCMGENET_STAT_OFFSET; 1201 /* fall through */ 1202 case BCMGENET_STAT_MIB_RX: 1203 val = bcmgenet_umac_readl(priv, 1204 UMAC_MIB_START + j + offset); 1205 offset = 0; /* Reset Offset */ 1206 break; 1207 case BCMGENET_STAT_MISC: 1208 if (GENET_IS_V1(priv)) { 1209 val = bcmgenet_umac_readl(priv, s->reg_offset); 1210 /* clear if overflowed */ 1211 if (val == ~0) 1212 bcmgenet_umac_writel(priv, 0, 1213 s->reg_offset); 1214 } else { 1215 val = bcmgenet_update_stat_misc(priv, 1216 s->reg_offset); 1217 } 1218 break; 1219 } 1220 1221 j += s->stat_sizeof; 1222 p = (char *)priv + s->stat_offset; 1223 *(u32 *)p = val; 1224 } 1225 } 1226 1227 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 1228 struct ethtool_stats *stats, 1229 u64 *data) 1230 { 1231 struct bcmgenet_priv *priv = netdev_priv(dev); 1232 int i; 1233 1234 if (netif_running(dev)) 1235 bcmgenet_update_mib_counters(priv); 1236 1237 dev->netdev_ops->ndo_get_stats(dev); 1238 1239 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 1240 const struct bcmgenet_stats *s; 1241 char *p; 1242 1243 s = &bcmgenet_gstrings_stats[i]; 1244 if (s->type == BCMGENET_STAT_NETDEV) 1245 p = (char *)&dev->stats; 1246 else 1247 p = (char *)priv; 1248 p += s->stat_offset; 1249 if (sizeof(unsigned long) != sizeof(u32) && 1250 s->stat_sizeof == sizeof(unsigned long)) 1251 data[i] = *(unsigned long *)p; 1252 else 1253 data[i] = *(u32 *)p; 1254 } 1255 } 1256 1257 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 1258 { 1259 struct bcmgenet_priv *priv = netdev_priv(dev); 1260 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 1261 u32 reg; 1262 1263 if (enable && !priv->clk_eee_enabled) { 1264 clk_prepare_enable(priv->clk_eee); 1265 priv->clk_eee_enabled = true; 1266 } 1267 1268 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 1269 if (enable) 1270 reg |= EEE_EN; 1271 else 1272 reg &= ~EEE_EN; 1273 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 1274 1275 /* Enable EEE and switch to a 27Mhz clock automatically */ 1276 reg = bcmgenet_readl(priv->base + off); 1277 if (enable) 1278 reg |= TBUF_EEE_EN | TBUF_PM_EN; 1279 else 1280 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 1281 bcmgenet_writel(reg, priv->base + off); 1282 1283 /* Do the same for thing for RBUF */ 1284 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 1285 if (enable) 1286 reg |= RBUF_EEE_EN | RBUF_PM_EN; 1287 else 1288 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 1289 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 1290 1291 if (!enable && priv->clk_eee_enabled) { 1292 clk_disable_unprepare(priv->clk_eee); 1293 priv->clk_eee_enabled = false; 1294 } 1295 1296 priv->eee.eee_enabled = enable; 1297 priv->eee.eee_active = enable; 1298 } 1299 1300 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1301 { 1302 struct bcmgenet_priv *priv = netdev_priv(dev); 1303 struct ethtool_eee *p = &priv->eee; 1304 1305 if (GENET_IS_V1(priv)) 1306 return -EOPNOTSUPP; 1307 1308 if (!dev->phydev) 1309 return -ENODEV; 1310 1311 e->eee_enabled = p->eee_enabled; 1312 e->eee_active = p->eee_active; 1313 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1314 1315 return phy_ethtool_get_eee(dev->phydev, e); 1316 } 1317 1318 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1319 { 1320 struct bcmgenet_priv *priv = netdev_priv(dev); 1321 struct ethtool_eee *p = &priv->eee; 1322 int ret = 0; 1323 1324 if (GENET_IS_V1(priv)) 1325 return -EOPNOTSUPP; 1326 1327 if (!dev->phydev) 1328 return -ENODEV; 1329 1330 p->eee_enabled = e->eee_enabled; 1331 1332 if (!p->eee_enabled) { 1333 bcmgenet_eee_enable_set(dev, false); 1334 } else { 1335 ret = phy_init_eee(dev->phydev, 0); 1336 if (ret) { 1337 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1338 return ret; 1339 } 1340 1341 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1342 bcmgenet_eee_enable_set(dev, true); 1343 } 1344 1345 return phy_ethtool_set_eee(dev->phydev, e); 1346 } 1347 1348 static int bcmgenet_validate_flow(struct net_device *dev, 1349 struct ethtool_rxnfc *cmd) 1350 { 1351 struct ethtool_usrip4_spec *l4_mask; 1352 struct ethhdr *eth_mask; 1353 1354 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) { 1355 netdev_err(dev, "rxnfc: Invalid location (%d)\n", 1356 cmd->fs.location); 1357 return -EINVAL; 1358 } 1359 1360 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) { 1361 case IP_USER_FLOW: 1362 l4_mask = &cmd->fs.m_u.usr_ip4_spec; 1363 /* don't allow mask which isn't valid */ 1364 if (VALIDATE_MASK(l4_mask->ip4src) || 1365 VALIDATE_MASK(l4_mask->ip4dst) || 1366 VALIDATE_MASK(l4_mask->l4_4_bytes) || 1367 VALIDATE_MASK(l4_mask->proto) || 1368 VALIDATE_MASK(l4_mask->ip_ver) || 1369 VALIDATE_MASK(l4_mask->tos)) { 1370 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1371 return -EINVAL; 1372 } 1373 break; 1374 case ETHER_FLOW: 1375 eth_mask = &cmd->fs.m_u.ether_spec; 1376 /* don't allow mask which isn't valid */ 1377 if (VALIDATE_MASK(eth_mask->h_source) || 1378 VALIDATE_MASK(eth_mask->h_source) || 1379 VALIDATE_MASK(eth_mask->h_proto)) { 1380 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1381 return -EINVAL; 1382 } 1383 break; 1384 default: 1385 netdev_err(dev, "rxnfc: Unsupported flow type (0x%x)\n", 1386 cmd->fs.flow_type); 1387 return -EINVAL; 1388 } 1389 1390 if ((cmd->fs.flow_type & FLOW_EXT)) { 1391 /* don't allow mask which isn't valid */ 1392 if (VALIDATE_MASK(cmd->fs.m_ext.vlan_etype) || 1393 VALIDATE_MASK(cmd->fs.m_ext.vlan_tci)) { 1394 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1395 return -EINVAL; 1396 } 1397 if (cmd->fs.m_ext.data[0] || cmd->fs.m_ext.data[1]) { 1398 netdev_err(dev, "rxnfc: user-def not supported\n"); 1399 return -EINVAL; 1400 } 1401 } 1402 1403 if ((cmd->fs.flow_type & FLOW_MAC_EXT)) { 1404 /* don't allow mask which isn't valid */ 1405 if (VALIDATE_MASK(cmd->fs.m_ext.h_dest)) { 1406 netdev_err(dev, "rxnfc: Unsupported mask\n"); 1407 return -EINVAL; 1408 } 1409 } 1410 1411 return 0; 1412 } 1413 1414 static int bcmgenet_insert_flow(struct net_device *dev, 1415 struct ethtool_rxnfc *cmd) 1416 { 1417 struct bcmgenet_priv *priv = netdev_priv(dev); 1418 struct bcmgenet_rxnfc_rule *loc_rule; 1419 int err; 1420 1421 if (priv->hw_params->hfb_filter_size < 128) { 1422 netdev_err(dev, "rxnfc: Not supported by this device\n"); 1423 return -EINVAL; 1424 } 1425 1426 if (cmd->fs.ring_cookie > priv->hw_params->rx_queues && 1427 cmd->fs.ring_cookie != RX_CLS_FLOW_WAKE) { 1428 netdev_err(dev, "rxnfc: Unsupported action (%llu)\n", 1429 cmd->fs.ring_cookie); 1430 return -EINVAL; 1431 } 1432 1433 err = bcmgenet_validate_flow(dev, cmd); 1434 if (err) 1435 return err; 1436 1437 loc_rule = &priv->rxnfc_rules[cmd->fs.location]; 1438 if (loc_rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1439 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1440 if (loc_rule->state != BCMGENET_RXNFC_STATE_UNUSED) 1441 list_del(&loc_rule->list); 1442 loc_rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1443 memcpy(&loc_rule->fs, &cmd->fs, 1444 sizeof(struct ethtool_rx_flow_spec)); 1445 1446 err = bcmgenet_hfb_create_rxnfc_filter(priv, loc_rule); 1447 if (err) { 1448 netdev_err(dev, "rxnfc: Could not install rule (%d)\n", 1449 err); 1450 return err; 1451 } 1452 1453 list_add_tail(&loc_rule->list, &priv->rxnfc_list); 1454 1455 return 0; 1456 } 1457 1458 static int bcmgenet_delete_flow(struct net_device *dev, 1459 struct ethtool_rxnfc *cmd) 1460 { 1461 struct bcmgenet_priv *priv = netdev_priv(dev); 1462 struct bcmgenet_rxnfc_rule *rule; 1463 int err = 0; 1464 1465 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES) 1466 return -EINVAL; 1467 1468 rule = &priv->rxnfc_rules[cmd->fs.location]; 1469 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) { 1470 err = -ENOENT; 1471 goto out; 1472 } 1473 1474 if (rule->state == BCMGENET_RXNFC_STATE_ENABLED) 1475 bcmgenet_hfb_disable_filter(priv, cmd->fs.location); 1476 if (rule->state != BCMGENET_RXNFC_STATE_UNUSED) 1477 list_del(&rule->list); 1478 rule->state = BCMGENET_RXNFC_STATE_UNUSED; 1479 memset(&rule->fs, 0, sizeof(struct ethtool_rx_flow_spec)); 1480 1481 out: 1482 return err; 1483 } 1484 1485 static int bcmgenet_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 1486 { 1487 struct bcmgenet_priv *priv = netdev_priv(dev); 1488 int err = 0; 1489 1490 switch (cmd->cmd) { 1491 case ETHTOOL_SRXCLSRLINS: 1492 err = bcmgenet_insert_flow(dev, cmd); 1493 break; 1494 case ETHTOOL_SRXCLSRLDEL: 1495 err = bcmgenet_delete_flow(dev, cmd); 1496 break; 1497 default: 1498 netdev_warn(priv->dev, "Unsupported ethtool command. (%d)\n", 1499 cmd->cmd); 1500 return -EINVAL; 1501 } 1502 1503 return err; 1504 } 1505 1506 static int bcmgenet_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd, 1507 int loc) 1508 { 1509 struct bcmgenet_priv *priv = netdev_priv(dev); 1510 struct bcmgenet_rxnfc_rule *rule; 1511 int err = 0; 1512 1513 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES) 1514 return -EINVAL; 1515 1516 rule = &priv->rxnfc_rules[loc]; 1517 if (rule->state == BCMGENET_RXNFC_STATE_UNUSED) 1518 err = -ENOENT; 1519 else 1520 memcpy(&cmd->fs, &rule->fs, 1521 sizeof(struct ethtool_rx_flow_spec)); 1522 1523 return err; 1524 } 1525 1526 static int bcmgenet_get_num_flows(struct bcmgenet_priv *priv) 1527 { 1528 struct list_head *pos; 1529 int res = 0; 1530 1531 list_for_each(pos, &priv->rxnfc_list) 1532 res++; 1533 1534 return res; 1535 } 1536 1537 static int bcmgenet_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 1538 u32 *rule_locs) 1539 { 1540 struct bcmgenet_priv *priv = netdev_priv(dev); 1541 struct bcmgenet_rxnfc_rule *rule; 1542 int err = 0; 1543 int i = 0; 1544 1545 switch (cmd->cmd) { 1546 case ETHTOOL_GRXRINGS: 1547 cmd->data = priv->hw_params->rx_queues ?: 1; 1548 break; 1549 case ETHTOOL_GRXCLSRLCNT: 1550 cmd->rule_cnt = bcmgenet_get_num_flows(priv); 1551 cmd->data = MAX_NUM_OF_FS_RULES; 1552 break; 1553 case ETHTOOL_GRXCLSRULE: 1554 err = bcmgenet_get_flow(dev, cmd, cmd->fs.location); 1555 break; 1556 case ETHTOOL_GRXCLSRLALL: 1557 list_for_each_entry(rule, &priv->rxnfc_list, list) 1558 if (i < cmd->rule_cnt) 1559 rule_locs[i++] = rule->fs.location; 1560 cmd->rule_cnt = i; 1561 cmd->data = MAX_NUM_OF_FS_RULES; 1562 break; 1563 default: 1564 err = -EOPNOTSUPP; 1565 break; 1566 } 1567 1568 return err; 1569 } 1570 1571 /* standard ethtool support functions. */ 1572 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1573 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1574 ETHTOOL_COALESCE_MAX_FRAMES | 1575 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1576 .begin = bcmgenet_begin, 1577 .complete = bcmgenet_complete, 1578 .get_strings = bcmgenet_get_strings, 1579 .get_sset_count = bcmgenet_get_sset_count, 1580 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1581 .get_drvinfo = bcmgenet_get_drvinfo, 1582 .get_link = ethtool_op_get_link, 1583 .get_msglevel = bcmgenet_get_msglevel, 1584 .set_msglevel = bcmgenet_set_msglevel, 1585 .get_wol = bcmgenet_get_wol, 1586 .set_wol = bcmgenet_set_wol, 1587 .get_eee = bcmgenet_get_eee, 1588 .set_eee = bcmgenet_set_eee, 1589 .nway_reset = phy_ethtool_nway_reset, 1590 .get_coalesce = bcmgenet_get_coalesce, 1591 .set_coalesce = bcmgenet_set_coalesce, 1592 .get_link_ksettings = bcmgenet_get_link_ksettings, 1593 .set_link_ksettings = bcmgenet_set_link_ksettings, 1594 .get_ts_info = ethtool_op_get_ts_info, 1595 .get_rxnfc = bcmgenet_get_rxnfc, 1596 .set_rxnfc = bcmgenet_set_rxnfc, 1597 }; 1598 1599 /* Power down the unimac, based on mode. */ 1600 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1601 enum bcmgenet_power_mode mode) 1602 { 1603 int ret = 0; 1604 u32 reg; 1605 1606 switch (mode) { 1607 case GENET_POWER_CABLE_SENSE: 1608 phy_detach(priv->dev->phydev); 1609 break; 1610 1611 case GENET_POWER_WOL_MAGIC: 1612 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1613 break; 1614 1615 case GENET_POWER_PASSIVE: 1616 /* Power down LED */ 1617 if (priv->hw_params->flags & GENET_HAS_EXT) { 1618 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1619 if (GENET_IS_V5(priv)) 1620 reg |= EXT_PWR_DOWN_PHY_EN | 1621 EXT_PWR_DOWN_PHY_RD | 1622 EXT_PWR_DOWN_PHY_SD | 1623 EXT_PWR_DOWN_PHY_RX | 1624 EXT_PWR_DOWN_PHY_TX | 1625 EXT_IDDQ_GLBL_PWR; 1626 else 1627 reg |= EXT_PWR_DOWN_PHY; 1628 1629 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1630 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1631 1632 bcmgenet_phy_power_set(priv->dev, false); 1633 } 1634 break; 1635 default: 1636 break; 1637 } 1638 1639 return ret; 1640 } 1641 1642 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1643 enum bcmgenet_power_mode mode) 1644 { 1645 u32 reg; 1646 1647 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1648 return; 1649 1650 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1651 1652 switch (mode) { 1653 case GENET_POWER_PASSIVE: 1654 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1655 if (GENET_IS_V5(priv)) { 1656 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1657 EXT_PWR_DOWN_PHY_RD | 1658 EXT_PWR_DOWN_PHY_SD | 1659 EXT_PWR_DOWN_PHY_RX | 1660 EXT_PWR_DOWN_PHY_TX | 1661 EXT_IDDQ_GLBL_PWR); 1662 reg |= EXT_PHY_RESET; 1663 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1664 mdelay(1); 1665 1666 reg &= ~EXT_PHY_RESET; 1667 } else { 1668 reg &= ~EXT_PWR_DOWN_PHY; 1669 reg |= EXT_PWR_DN_EN_LD; 1670 } 1671 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1672 bcmgenet_phy_power_set(priv->dev, true); 1673 break; 1674 1675 case GENET_POWER_CABLE_SENSE: 1676 /* enable APD */ 1677 if (!GENET_IS_V5(priv)) { 1678 reg |= EXT_PWR_DN_EN_LD; 1679 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1680 } 1681 break; 1682 case GENET_POWER_WOL_MAGIC: 1683 bcmgenet_wol_power_up_cfg(priv, mode); 1684 return; 1685 default: 1686 break; 1687 } 1688 } 1689 1690 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1691 struct bcmgenet_tx_ring *ring) 1692 { 1693 struct enet_cb *tx_cb_ptr; 1694 1695 tx_cb_ptr = ring->cbs; 1696 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1697 1698 /* Advancing local write pointer */ 1699 if (ring->write_ptr == ring->end_ptr) 1700 ring->write_ptr = ring->cb_ptr; 1701 else 1702 ring->write_ptr++; 1703 1704 return tx_cb_ptr; 1705 } 1706 1707 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1708 struct bcmgenet_tx_ring *ring) 1709 { 1710 struct enet_cb *tx_cb_ptr; 1711 1712 tx_cb_ptr = ring->cbs; 1713 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1714 1715 /* Rewinding local write pointer */ 1716 if (ring->write_ptr == ring->cb_ptr) 1717 ring->write_ptr = ring->end_ptr; 1718 else 1719 ring->write_ptr--; 1720 1721 return tx_cb_ptr; 1722 } 1723 1724 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1725 { 1726 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1727 INTRL2_CPU_MASK_SET); 1728 } 1729 1730 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1731 { 1732 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1733 INTRL2_CPU_MASK_CLEAR); 1734 } 1735 1736 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1737 { 1738 bcmgenet_intrl2_1_writel(ring->priv, 1739 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1740 INTRL2_CPU_MASK_SET); 1741 } 1742 1743 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1744 { 1745 bcmgenet_intrl2_1_writel(ring->priv, 1746 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1747 INTRL2_CPU_MASK_CLEAR); 1748 } 1749 1750 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1751 { 1752 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1753 INTRL2_CPU_MASK_SET); 1754 } 1755 1756 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1757 { 1758 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1759 INTRL2_CPU_MASK_CLEAR); 1760 } 1761 1762 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1763 { 1764 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1765 INTRL2_CPU_MASK_CLEAR); 1766 } 1767 1768 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1769 { 1770 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1771 INTRL2_CPU_MASK_SET); 1772 } 1773 1774 /* Simple helper to free a transmit control block's resources 1775 * Returns an skb when the last transmit control block associated with the 1776 * skb is freed. The skb should be freed by the caller if necessary. 1777 */ 1778 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1779 struct enet_cb *cb) 1780 { 1781 struct sk_buff *skb; 1782 1783 skb = cb->skb; 1784 1785 if (skb) { 1786 cb->skb = NULL; 1787 if (cb == GENET_CB(skb)->first_cb) 1788 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1789 dma_unmap_len(cb, dma_len), 1790 DMA_TO_DEVICE); 1791 else 1792 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1793 dma_unmap_len(cb, dma_len), 1794 DMA_TO_DEVICE); 1795 dma_unmap_addr_set(cb, dma_addr, 0); 1796 1797 if (cb == GENET_CB(skb)->last_cb) 1798 return skb; 1799 1800 } else if (dma_unmap_addr(cb, dma_addr)) { 1801 dma_unmap_page(dev, 1802 dma_unmap_addr(cb, dma_addr), 1803 dma_unmap_len(cb, dma_len), 1804 DMA_TO_DEVICE); 1805 dma_unmap_addr_set(cb, dma_addr, 0); 1806 } 1807 1808 return NULL; 1809 } 1810 1811 /* Simple helper to free a receive control block's resources */ 1812 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1813 struct enet_cb *cb) 1814 { 1815 struct sk_buff *skb; 1816 1817 skb = cb->skb; 1818 cb->skb = NULL; 1819 1820 if (dma_unmap_addr(cb, dma_addr)) { 1821 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1822 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1823 dma_unmap_addr_set(cb, dma_addr, 0); 1824 } 1825 1826 return skb; 1827 } 1828 1829 /* Unlocked version of the reclaim routine */ 1830 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1831 struct bcmgenet_tx_ring *ring) 1832 { 1833 struct bcmgenet_priv *priv = netdev_priv(dev); 1834 unsigned int txbds_processed = 0; 1835 unsigned int bytes_compl = 0; 1836 unsigned int pkts_compl = 0; 1837 unsigned int txbds_ready; 1838 unsigned int c_index; 1839 struct sk_buff *skb; 1840 1841 /* Clear status before servicing to reduce spurious interrupts */ 1842 if (ring->index == DESC_INDEX) 1843 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1844 INTRL2_CPU_CLEAR); 1845 else 1846 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1847 INTRL2_CPU_CLEAR); 1848 1849 /* Compute how many buffers are transmitted since last xmit call */ 1850 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1851 & DMA_C_INDEX_MASK; 1852 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1853 1854 netif_dbg(priv, tx_done, dev, 1855 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1856 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1857 1858 /* Reclaim transmitted buffers */ 1859 while (txbds_processed < txbds_ready) { 1860 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1861 &priv->tx_cbs[ring->clean_ptr]); 1862 if (skb) { 1863 pkts_compl++; 1864 bytes_compl += GENET_CB(skb)->bytes_sent; 1865 dev_consume_skb_any(skb); 1866 } 1867 1868 txbds_processed++; 1869 if (likely(ring->clean_ptr < ring->end_ptr)) 1870 ring->clean_ptr++; 1871 else 1872 ring->clean_ptr = ring->cb_ptr; 1873 } 1874 1875 ring->free_bds += txbds_processed; 1876 ring->c_index = c_index; 1877 1878 ring->packets += pkts_compl; 1879 ring->bytes += bytes_compl; 1880 1881 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1882 pkts_compl, bytes_compl); 1883 1884 return txbds_processed; 1885 } 1886 1887 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1888 struct bcmgenet_tx_ring *ring) 1889 { 1890 unsigned int released; 1891 1892 spin_lock_bh(&ring->lock); 1893 released = __bcmgenet_tx_reclaim(dev, ring); 1894 spin_unlock_bh(&ring->lock); 1895 1896 return released; 1897 } 1898 1899 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1900 { 1901 struct bcmgenet_tx_ring *ring = 1902 container_of(napi, struct bcmgenet_tx_ring, napi); 1903 unsigned int work_done = 0; 1904 struct netdev_queue *txq; 1905 1906 spin_lock(&ring->lock); 1907 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1908 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1909 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1910 netif_tx_wake_queue(txq); 1911 } 1912 spin_unlock(&ring->lock); 1913 1914 if (work_done == 0) { 1915 napi_complete(napi); 1916 ring->int_enable(ring); 1917 1918 return 0; 1919 } 1920 1921 return budget; 1922 } 1923 1924 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1925 { 1926 struct bcmgenet_priv *priv = netdev_priv(dev); 1927 int i; 1928 1929 if (netif_is_multiqueue(dev)) { 1930 for (i = 0; i < priv->hw_params->tx_queues; i++) 1931 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1932 } 1933 1934 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1935 } 1936 1937 /* Reallocate the SKB to put enough headroom in front of it and insert 1938 * the transmit checksum offsets in the descriptors 1939 */ 1940 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 1941 struct sk_buff *skb) 1942 { 1943 struct bcmgenet_priv *priv = netdev_priv(dev); 1944 struct status_64 *status = NULL; 1945 struct sk_buff *new_skb; 1946 u16 offset; 1947 u8 ip_proto; 1948 __be16 ip_ver; 1949 u32 tx_csum_info; 1950 1951 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1952 /* If 64 byte status block enabled, must make sure skb has 1953 * enough headroom for us to insert 64B status block. 1954 */ 1955 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1956 if (!new_skb) { 1957 dev_kfree_skb_any(skb); 1958 priv->mib.tx_realloc_tsb_failed++; 1959 dev->stats.tx_dropped++; 1960 return NULL; 1961 } 1962 dev_consume_skb_any(skb); 1963 skb = new_skb; 1964 priv->mib.tx_realloc_tsb++; 1965 } 1966 1967 skb_push(skb, sizeof(*status)); 1968 status = (struct status_64 *)skb->data; 1969 1970 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1971 ip_ver = skb->protocol; 1972 switch (ip_ver) { 1973 case htons(ETH_P_IP): 1974 ip_proto = ip_hdr(skb)->protocol; 1975 break; 1976 case htons(ETH_P_IPV6): 1977 ip_proto = ipv6_hdr(skb)->nexthdr; 1978 break; 1979 default: 1980 /* don't use UDP flag */ 1981 ip_proto = 0; 1982 break; 1983 } 1984 1985 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1986 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1987 (offset + skb->csum_offset) | 1988 STATUS_TX_CSUM_LV; 1989 1990 /* Set the special UDP flag for UDP */ 1991 if (ip_proto == IPPROTO_UDP) 1992 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1993 1994 status->tx_csum_info = tx_csum_info; 1995 } 1996 1997 return skb; 1998 } 1999 2000 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 2001 { 2002 struct bcmgenet_priv *priv = netdev_priv(dev); 2003 struct device *kdev = &priv->pdev->dev; 2004 struct bcmgenet_tx_ring *ring = NULL; 2005 struct enet_cb *tx_cb_ptr; 2006 struct netdev_queue *txq; 2007 int nr_frags, index; 2008 dma_addr_t mapping; 2009 unsigned int size; 2010 skb_frag_t *frag; 2011 u32 len_stat; 2012 int ret; 2013 int i; 2014 2015 index = skb_get_queue_mapping(skb); 2016 /* Mapping strategy: 2017 * queue_mapping = 0, unclassified, packet xmited through ring16 2018 * queue_mapping = 1, goes to ring 0. (highest priority queue 2019 * queue_mapping = 2, goes to ring 1. 2020 * queue_mapping = 3, goes to ring 2. 2021 * queue_mapping = 4, goes to ring 3. 2022 */ 2023 if (index == 0) 2024 index = DESC_INDEX; 2025 else 2026 index -= 1; 2027 2028 ring = &priv->tx_rings[index]; 2029 txq = netdev_get_tx_queue(dev, ring->queue); 2030 2031 nr_frags = skb_shinfo(skb)->nr_frags; 2032 2033 spin_lock(&ring->lock); 2034 if (ring->free_bds <= (nr_frags + 1)) { 2035 if (!netif_tx_queue_stopped(txq)) { 2036 netif_tx_stop_queue(txq); 2037 netdev_err(dev, 2038 "%s: tx ring %d full when queue %d awake\n", 2039 __func__, index, ring->queue); 2040 } 2041 ret = NETDEV_TX_BUSY; 2042 goto out; 2043 } 2044 2045 /* Retain how many bytes will be sent on the wire, without TSB inserted 2046 * by transmit checksum offload 2047 */ 2048 GENET_CB(skb)->bytes_sent = skb->len; 2049 2050 /* add the Transmit Status Block */ 2051 skb = bcmgenet_add_tsb(dev, skb); 2052 if (!skb) { 2053 ret = NETDEV_TX_OK; 2054 goto out; 2055 } 2056 2057 for (i = 0; i <= nr_frags; i++) { 2058 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 2059 2060 BUG_ON(!tx_cb_ptr); 2061 2062 if (!i) { 2063 /* Transmit single SKB or head of fragment list */ 2064 GENET_CB(skb)->first_cb = tx_cb_ptr; 2065 size = skb_headlen(skb); 2066 mapping = dma_map_single(kdev, skb->data, size, 2067 DMA_TO_DEVICE); 2068 } else { 2069 /* xmit fragment */ 2070 frag = &skb_shinfo(skb)->frags[i - 1]; 2071 size = skb_frag_size(frag); 2072 mapping = skb_frag_dma_map(kdev, frag, 0, size, 2073 DMA_TO_DEVICE); 2074 } 2075 2076 ret = dma_mapping_error(kdev, mapping); 2077 if (ret) { 2078 priv->mib.tx_dma_failed++; 2079 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 2080 ret = NETDEV_TX_OK; 2081 goto out_unmap_frags; 2082 } 2083 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 2084 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 2085 2086 tx_cb_ptr->skb = skb; 2087 2088 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 2089 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 2090 2091 /* Note: if we ever change from DMA_TX_APPEND_CRC below we 2092 * will need to restore software padding of "runt" packets 2093 */ 2094 if (!i) { 2095 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 2096 if (skb->ip_summed == CHECKSUM_PARTIAL) 2097 len_stat |= DMA_TX_DO_CSUM; 2098 } 2099 if (i == nr_frags) 2100 len_stat |= DMA_EOP; 2101 2102 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 2103 } 2104 2105 GENET_CB(skb)->last_cb = tx_cb_ptr; 2106 skb_tx_timestamp(skb); 2107 2108 /* Decrement total BD count and advance our write pointer */ 2109 ring->free_bds -= nr_frags + 1; 2110 ring->prod_index += nr_frags + 1; 2111 ring->prod_index &= DMA_P_INDEX_MASK; 2112 2113 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 2114 2115 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 2116 netif_tx_stop_queue(txq); 2117 2118 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 2119 /* Packets are ready, update producer index */ 2120 bcmgenet_tdma_ring_writel(priv, ring->index, 2121 ring->prod_index, TDMA_PROD_INDEX); 2122 out: 2123 spin_unlock(&ring->lock); 2124 2125 return ret; 2126 2127 out_unmap_frags: 2128 /* Back up for failed control block mapping */ 2129 bcmgenet_put_txcb(priv, ring); 2130 2131 /* Unmap successfully mapped control blocks */ 2132 while (i-- > 0) { 2133 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 2134 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 2135 } 2136 2137 dev_kfree_skb(skb); 2138 goto out; 2139 } 2140 2141 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 2142 struct enet_cb *cb) 2143 { 2144 struct device *kdev = &priv->pdev->dev; 2145 struct sk_buff *skb; 2146 struct sk_buff *rx_skb; 2147 dma_addr_t mapping; 2148 2149 /* Allocate a new Rx skb */ 2150 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 2151 GFP_ATOMIC | __GFP_NOWARN); 2152 if (!skb) { 2153 priv->mib.alloc_rx_buff_failed++; 2154 netif_err(priv, rx_err, priv->dev, 2155 "%s: Rx skb allocation failed\n", __func__); 2156 return NULL; 2157 } 2158 2159 /* DMA-map the new Rx skb */ 2160 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 2161 DMA_FROM_DEVICE); 2162 if (dma_mapping_error(kdev, mapping)) { 2163 priv->mib.rx_dma_failed++; 2164 dev_kfree_skb_any(skb); 2165 netif_err(priv, rx_err, priv->dev, 2166 "%s: Rx skb DMA mapping failed\n", __func__); 2167 return NULL; 2168 } 2169 2170 /* Grab the current Rx skb from the ring and DMA-unmap it */ 2171 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 2172 2173 /* Put the new Rx skb on the ring */ 2174 cb->skb = skb; 2175 dma_unmap_addr_set(cb, dma_addr, mapping); 2176 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 2177 dmadesc_set_addr(priv, cb->bd_addr, mapping); 2178 2179 /* Return the current Rx skb to caller */ 2180 return rx_skb; 2181 } 2182 2183 /* bcmgenet_desc_rx - descriptor based rx process. 2184 * this could be called from bottom half, or from NAPI polling method. 2185 */ 2186 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 2187 unsigned int budget) 2188 { 2189 struct bcmgenet_priv *priv = ring->priv; 2190 struct net_device *dev = priv->dev; 2191 struct enet_cb *cb; 2192 struct sk_buff *skb; 2193 u32 dma_length_status; 2194 unsigned long dma_flag; 2195 int len; 2196 unsigned int rxpktprocessed = 0, rxpkttoprocess; 2197 unsigned int bytes_processed = 0; 2198 unsigned int p_index, mask; 2199 unsigned int discards; 2200 2201 /* Clear status before servicing to reduce spurious interrupts */ 2202 if (ring->index == DESC_INDEX) { 2203 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 2204 INTRL2_CPU_CLEAR); 2205 } else { 2206 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 2207 bcmgenet_intrl2_1_writel(priv, 2208 mask, 2209 INTRL2_CPU_CLEAR); 2210 } 2211 2212 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 2213 2214 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 2215 DMA_P_INDEX_DISCARD_CNT_MASK; 2216 if (discards > ring->old_discards) { 2217 discards = discards - ring->old_discards; 2218 ring->errors += discards; 2219 ring->old_discards += discards; 2220 2221 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 2222 if (ring->old_discards >= 0xC000) { 2223 ring->old_discards = 0; 2224 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 2225 RDMA_PROD_INDEX); 2226 } 2227 } 2228 2229 p_index &= DMA_P_INDEX_MASK; 2230 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 2231 2232 netif_dbg(priv, rx_status, dev, 2233 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 2234 2235 while ((rxpktprocessed < rxpkttoprocess) && 2236 (rxpktprocessed < budget)) { 2237 struct status_64 *status; 2238 __be16 rx_csum; 2239 2240 cb = &priv->rx_cbs[ring->read_ptr]; 2241 skb = bcmgenet_rx_refill(priv, cb); 2242 2243 if (unlikely(!skb)) { 2244 ring->dropped++; 2245 goto next; 2246 } 2247 2248 status = (struct status_64 *)skb->data; 2249 dma_length_status = status->length_status; 2250 if (dev->features & NETIF_F_RXCSUM) { 2251 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 2252 skb->csum = (__force __wsum)ntohs(rx_csum); 2253 skb->ip_summed = CHECKSUM_COMPLETE; 2254 } 2255 2256 /* DMA flags and length are still valid no matter how 2257 * we got the Receive Status Vector (64B RSB or register) 2258 */ 2259 dma_flag = dma_length_status & 0xffff; 2260 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 2261 2262 netif_dbg(priv, rx_status, dev, 2263 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 2264 __func__, p_index, ring->c_index, 2265 ring->read_ptr, dma_length_status); 2266 2267 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 2268 netif_err(priv, rx_status, dev, 2269 "dropping fragmented packet!\n"); 2270 ring->errors++; 2271 dev_kfree_skb_any(skb); 2272 goto next; 2273 } 2274 2275 /* report errors */ 2276 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 2277 DMA_RX_OV | 2278 DMA_RX_NO | 2279 DMA_RX_LG | 2280 DMA_RX_RXER))) { 2281 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 2282 (unsigned int)dma_flag); 2283 if (dma_flag & DMA_RX_CRC_ERROR) 2284 dev->stats.rx_crc_errors++; 2285 if (dma_flag & DMA_RX_OV) 2286 dev->stats.rx_over_errors++; 2287 if (dma_flag & DMA_RX_NO) 2288 dev->stats.rx_frame_errors++; 2289 if (dma_flag & DMA_RX_LG) 2290 dev->stats.rx_length_errors++; 2291 dev->stats.rx_errors++; 2292 dev_kfree_skb_any(skb); 2293 goto next; 2294 } /* error packet */ 2295 2296 skb_put(skb, len); 2297 2298 /* remove RSB and hardware 2bytes added for IP alignment */ 2299 skb_pull(skb, 66); 2300 len -= 66; 2301 2302 if (priv->crc_fwd_en) { 2303 skb_trim(skb, len - ETH_FCS_LEN); 2304 len -= ETH_FCS_LEN; 2305 } 2306 2307 bytes_processed += len; 2308 2309 /*Finish setting up the received SKB and send it to the kernel*/ 2310 skb->protocol = eth_type_trans(skb, priv->dev); 2311 ring->packets++; 2312 ring->bytes += len; 2313 if (dma_flag & DMA_RX_MULT) 2314 dev->stats.multicast++; 2315 2316 /* Notify kernel */ 2317 napi_gro_receive(&ring->napi, skb); 2318 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 2319 2320 next: 2321 rxpktprocessed++; 2322 if (likely(ring->read_ptr < ring->end_ptr)) 2323 ring->read_ptr++; 2324 else 2325 ring->read_ptr = ring->cb_ptr; 2326 2327 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 2328 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 2329 } 2330 2331 ring->dim.bytes = bytes_processed; 2332 ring->dim.packets = rxpktprocessed; 2333 2334 return rxpktprocessed; 2335 } 2336 2337 /* Rx NAPI polling method */ 2338 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 2339 { 2340 struct bcmgenet_rx_ring *ring = container_of(napi, 2341 struct bcmgenet_rx_ring, napi); 2342 struct dim_sample dim_sample = {}; 2343 unsigned int work_done; 2344 2345 work_done = bcmgenet_desc_rx(ring, budget); 2346 2347 if (work_done < budget) { 2348 napi_complete_done(napi, work_done); 2349 ring->int_enable(ring); 2350 } 2351 2352 if (ring->dim.use_dim) { 2353 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 2354 ring->dim.bytes, &dim_sample); 2355 net_dim(&ring->dim.dim, dim_sample); 2356 } 2357 2358 return work_done; 2359 } 2360 2361 static void bcmgenet_dim_work(struct work_struct *work) 2362 { 2363 struct dim *dim = container_of(work, struct dim, work); 2364 struct bcmgenet_net_dim *ndim = 2365 container_of(dim, struct bcmgenet_net_dim, dim); 2366 struct bcmgenet_rx_ring *ring = 2367 container_of(ndim, struct bcmgenet_rx_ring, dim); 2368 struct dim_cq_moder cur_profile = 2369 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 2370 2371 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 2372 dim->state = DIM_START_MEASURE; 2373 } 2374 2375 /* Assign skb to RX DMA descriptor. */ 2376 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 2377 struct bcmgenet_rx_ring *ring) 2378 { 2379 struct enet_cb *cb; 2380 struct sk_buff *skb; 2381 int i; 2382 2383 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2384 2385 /* loop here for each buffer needing assign */ 2386 for (i = 0; i < ring->size; i++) { 2387 cb = ring->cbs + i; 2388 skb = bcmgenet_rx_refill(priv, cb); 2389 if (skb) 2390 dev_consume_skb_any(skb); 2391 if (!cb->skb) 2392 return -ENOMEM; 2393 } 2394 2395 return 0; 2396 } 2397 2398 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 2399 { 2400 struct sk_buff *skb; 2401 struct enet_cb *cb; 2402 int i; 2403 2404 for (i = 0; i < priv->num_rx_bds; i++) { 2405 cb = &priv->rx_cbs[i]; 2406 2407 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 2408 if (skb) 2409 dev_consume_skb_any(skb); 2410 } 2411 } 2412 2413 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 2414 { 2415 u32 reg; 2416 2417 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2418 if (reg & CMD_SW_RESET) 2419 return; 2420 if (enable) 2421 reg |= mask; 2422 else 2423 reg &= ~mask; 2424 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2425 2426 /* UniMAC stops on a packet boundary, wait for a full-size packet 2427 * to be processed 2428 */ 2429 if (enable == 0) 2430 usleep_range(1000, 2000); 2431 } 2432 2433 static void reset_umac(struct bcmgenet_priv *priv) 2434 { 2435 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 2436 bcmgenet_rbuf_ctrl_set(priv, 0); 2437 udelay(10); 2438 2439 /* issue soft reset and disable MAC while updating its registers */ 2440 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 2441 udelay(2); 2442 } 2443 2444 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 2445 { 2446 /* Mask all interrupts.*/ 2447 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2448 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2449 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 2450 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 2451 } 2452 2453 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 2454 { 2455 u32 int0_enable = 0; 2456 2457 /* Monitor cable plug/unplugged event for internal PHY, external PHY 2458 * and MoCA PHY 2459 */ 2460 if (priv->internal_phy) { 2461 int0_enable |= UMAC_IRQ_LINK_EVENT; 2462 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 2463 int0_enable |= UMAC_IRQ_PHY_DET_R; 2464 } else if (priv->ext_phy) { 2465 int0_enable |= UMAC_IRQ_LINK_EVENT; 2466 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2467 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 2468 int0_enable |= UMAC_IRQ_LINK_EVENT; 2469 } 2470 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2471 } 2472 2473 static void init_umac(struct bcmgenet_priv *priv) 2474 { 2475 struct device *kdev = &priv->pdev->dev; 2476 u32 reg; 2477 u32 int0_enable = 0; 2478 2479 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 2480 2481 reset_umac(priv); 2482 2483 /* clear tx/rx counter */ 2484 bcmgenet_umac_writel(priv, 2485 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 2486 UMAC_MIB_CTRL); 2487 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 2488 2489 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 2490 2491 /* init tx registers, enable TSB */ 2492 reg = bcmgenet_tbuf_ctrl_get(priv); 2493 reg |= TBUF_64B_EN; 2494 bcmgenet_tbuf_ctrl_set(priv, reg); 2495 2496 /* init rx registers, enable ip header optimization and RSB */ 2497 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 2498 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 2499 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 2500 2501 /* enable rx checksumming */ 2502 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 2503 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 2504 /* If UniMAC forwards CRC, we need to skip over it to get 2505 * a valid CHK bit to be set in the per-packet status word 2506 */ 2507 if (priv->crc_fwd_en) 2508 reg |= RBUF_SKIP_FCS; 2509 else 2510 reg &= ~RBUF_SKIP_FCS; 2511 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 2512 2513 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 2514 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 2515 2516 bcmgenet_intr_disable(priv); 2517 2518 /* Configure backpressure vectors for MoCA */ 2519 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 2520 reg = bcmgenet_bp_mc_get(priv); 2521 reg |= BIT(priv->hw_params->bp_in_en_shift); 2522 2523 /* bp_mask: back pressure mask */ 2524 if (netif_is_multiqueue(priv->dev)) 2525 reg |= priv->hw_params->bp_in_mask; 2526 else 2527 reg &= ~priv->hw_params->bp_in_mask; 2528 bcmgenet_bp_mc_set(priv, reg); 2529 } 2530 2531 /* Enable MDIO interrupts on GENET v3+ */ 2532 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2533 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2534 2535 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2536 2537 dev_dbg(kdev, "done init umac\n"); 2538 } 2539 2540 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2541 void (*cb)(struct work_struct *work)) 2542 { 2543 struct bcmgenet_net_dim *dim = &ring->dim; 2544 2545 INIT_WORK(&dim->dim.work, cb); 2546 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2547 dim->event_ctr = 0; 2548 dim->packets = 0; 2549 dim->bytes = 0; 2550 } 2551 2552 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2553 { 2554 struct bcmgenet_net_dim *dim = &ring->dim; 2555 struct dim_cq_moder moder; 2556 u32 usecs, pkts; 2557 2558 usecs = ring->rx_coalesce_usecs; 2559 pkts = ring->rx_max_coalesced_frames; 2560 2561 /* If DIM was enabled, re-apply default parameters */ 2562 if (dim->use_dim) { 2563 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2564 usecs = moder.usec; 2565 pkts = moder.pkts; 2566 } 2567 2568 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2569 } 2570 2571 /* Initialize a Tx ring along with corresponding hardware registers */ 2572 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2573 unsigned int index, unsigned int size, 2574 unsigned int start_ptr, unsigned int end_ptr) 2575 { 2576 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2577 u32 words_per_bd = WORDS_PER_BD(priv); 2578 u32 flow_period_val = 0; 2579 2580 spin_lock_init(&ring->lock); 2581 ring->priv = priv; 2582 ring->index = index; 2583 if (index == DESC_INDEX) { 2584 ring->queue = 0; 2585 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2586 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2587 } else { 2588 ring->queue = index + 1; 2589 ring->int_enable = bcmgenet_tx_ring_int_enable; 2590 ring->int_disable = bcmgenet_tx_ring_int_disable; 2591 } 2592 ring->cbs = priv->tx_cbs + start_ptr; 2593 ring->size = size; 2594 ring->clean_ptr = start_ptr; 2595 ring->c_index = 0; 2596 ring->free_bds = size; 2597 ring->write_ptr = start_ptr; 2598 ring->cb_ptr = start_ptr; 2599 ring->end_ptr = end_ptr - 1; 2600 ring->prod_index = 0; 2601 2602 /* Set flow period for ring != 16 */ 2603 if (index != DESC_INDEX) 2604 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2605 2606 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2607 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2608 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2609 /* Disable rate control for now */ 2610 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2611 TDMA_FLOW_PERIOD); 2612 bcmgenet_tdma_ring_writel(priv, index, 2613 ((size << DMA_RING_SIZE_SHIFT) | 2614 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2615 2616 /* Set start and end address, read and write pointers */ 2617 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2618 DMA_START_ADDR); 2619 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2620 TDMA_READ_PTR); 2621 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2622 TDMA_WRITE_PTR); 2623 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2624 DMA_END_ADDR); 2625 2626 /* Initialize Tx NAPI */ 2627 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2628 NAPI_POLL_WEIGHT); 2629 } 2630 2631 /* Initialize a RDMA ring */ 2632 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2633 unsigned int index, unsigned int size, 2634 unsigned int start_ptr, unsigned int end_ptr) 2635 { 2636 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2637 u32 words_per_bd = WORDS_PER_BD(priv); 2638 int ret; 2639 2640 ring->priv = priv; 2641 ring->index = index; 2642 if (index == DESC_INDEX) { 2643 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2644 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2645 } else { 2646 ring->int_enable = bcmgenet_rx_ring_int_enable; 2647 ring->int_disable = bcmgenet_rx_ring_int_disable; 2648 } 2649 ring->cbs = priv->rx_cbs + start_ptr; 2650 ring->size = size; 2651 ring->c_index = 0; 2652 ring->read_ptr = start_ptr; 2653 ring->cb_ptr = start_ptr; 2654 ring->end_ptr = end_ptr - 1; 2655 2656 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2657 if (ret) 2658 return ret; 2659 2660 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2661 bcmgenet_init_rx_coalesce(ring); 2662 2663 /* Initialize Rx NAPI */ 2664 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2665 NAPI_POLL_WEIGHT); 2666 2667 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2668 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2669 bcmgenet_rdma_ring_writel(priv, index, 2670 ((size << DMA_RING_SIZE_SHIFT) | 2671 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2672 bcmgenet_rdma_ring_writel(priv, index, 2673 (DMA_FC_THRESH_LO << 2674 DMA_XOFF_THRESHOLD_SHIFT) | 2675 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2676 2677 /* Set start and end address, read and write pointers */ 2678 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2679 DMA_START_ADDR); 2680 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2681 RDMA_READ_PTR); 2682 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2683 RDMA_WRITE_PTR); 2684 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2685 DMA_END_ADDR); 2686 2687 return ret; 2688 } 2689 2690 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2691 { 2692 unsigned int i; 2693 struct bcmgenet_tx_ring *ring; 2694 2695 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2696 ring = &priv->tx_rings[i]; 2697 napi_enable(&ring->napi); 2698 ring->int_enable(ring); 2699 } 2700 2701 ring = &priv->tx_rings[DESC_INDEX]; 2702 napi_enable(&ring->napi); 2703 ring->int_enable(ring); 2704 } 2705 2706 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2707 { 2708 unsigned int i; 2709 struct bcmgenet_tx_ring *ring; 2710 2711 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2712 ring = &priv->tx_rings[i]; 2713 napi_disable(&ring->napi); 2714 } 2715 2716 ring = &priv->tx_rings[DESC_INDEX]; 2717 napi_disable(&ring->napi); 2718 } 2719 2720 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2721 { 2722 unsigned int i; 2723 struct bcmgenet_tx_ring *ring; 2724 2725 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2726 ring = &priv->tx_rings[i]; 2727 netif_napi_del(&ring->napi); 2728 } 2729 2730 ring = &priv->tx_rings[DESC_INDEX]; 2731 netif_napi_del(&ring->napi); 2732 } 2733 2734 /* Initialize Tx queues 2735 * 2736 * Queues 0-3 are priority-based, each one has 32 descriptors, 2737 * with queue 0 being the highest priority queue. 2738 * 2739 * Queue 16 is the default Tx queue with 2740 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2741 * 2742 * The transmit control block pool is then partitioned as follows: 2743 * - Tx queue 0 uses tx_cbs[0..31] 2744 * - Tx queue 1 uses tx_cbs[32..63] 2745 * - Tx queue 2 uses tx_cbs[64..95] 2746 * - Tx queue 3 uses tx_cbs[96..127] 2747 * - Tx queue 16 uses tx_cbs[128..255] 2748 */ 2749 static void bcmgenet_init_tx_queues(struct net_device *dev) 2750 { 2751 struct bcmgenet_priv *priv = netdev_priv(dev); 2752 u32 i, dma_enable; 2753 u32 dma_ctrl, ring_cfg; 2754 u32 dma_priority[3] = {0, 0, 0}; 2755 2756 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2757 dma_enable = dma_ctrl & DMA_EN; 2758 dma_ctrl &= ~DMA_EN; 2759 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2760 2761 dma_ctrl = 0; 2762 ring_cfg = 0; 2763 2764 /* Enable strict priority arbiter mode */ 2765 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2766 2767 /* Initialize Tx priority queues */ 2768 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2769 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2770 i * priv->hw_params->tx_bds_per_q, 2771 (i + 1) * priv->hw_params->tx_bds_per_q); 2772 ring_cfg |= (1 << i); 2773 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2774 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2775 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2776 } 2777 2778 /* Initialize Tx default queue 16 */ 2779 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2780 priv->hw_params->tx_queues * 2781 priv->hw_params->tx_bds_per_q, 2782 TOTAL_DESC); 2783 ring_cfg |= (1 << DESC_INDEX); 2784 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2785 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2786 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2787 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2788 2789 /* Set Tx queue priorities */ 2790 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2791 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2792 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2793 2794 /* Enable Tx queues */ 2795 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2796 2797 /* Enable Tx DMA */ 2798 if (dma_enable) 2799 dma_ctrl |= DMA_EN; 2800 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2801 } 2802 2803 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2804 { 2805 unsigned int i; 2806 struct bcmgenet_rx_ring *ring; 2807 2808 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2809 ring = &priv->rx_rings[i]; 2810 napi_enable(&ring->napi); 2811 ring->int_enable(ring); 2812 } 2813 2814 ring = &priv->rx_rings[DESC_INDEX]; 2815 napi_enable(&ring->napi); 2816 ring->int_enable(ring); 2817 } 2818 2819 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2820 { 2821 unsigned int i; 2822 struct bcmgenet_rx_ring *ring; 2823 2824 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2825 ring = &priv->rx_rings[i]; 2826 napi_disable(&ring->napi); 2827 cancel_work_sync(&ring->dim.dim.work); 2828 } 2829 2830 ring = &priv->rx_rings[DESC_INDEX]; 2831 napi_disable(&ring->napi); 2832 cancel_work_sync(&ring->dim.dim.work); 2833 } 2834 2835 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2836 { 2837 unsigned int i; 2838 struct bcmgenet_rx_ring *ring; 2839 2840 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2841 ring = &priv->rx_rings[i]; 2842 netif_napi_del(&ring->napi); 2843 } 2844 2845 ring = &priv->rx_rings[DESC_INDEX]; 2846 netif_napi_del(&ring->napi); 2847 } 2848 2849 /* Initialize Rx queues 2850 * 2851 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2852 * used to direct traffic to these queues. 2853 * 2854 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2855 */ 2856 static int bcmgenet_init_rx_queues(struct net_device *dev) 2857 { 2858 struct bcmgenet_priv *priv = netdev_priv(dev); 2859 u32 i; 2860 u32 dma_enable; 2861 u32 dma_ctrl; 2862 u32 ring_cfg; 2863 int ret; 2864 2865 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2866 dma_enable = dma_ctrl & DMA_EN; 2867 dma_ctrl &= ~DMA_EN; 2868 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2869 2870 dma_ctrl = 0; 2871 ring_cfg = 0; 2872 2873 /* Initialize Rx priority queues */ 2874 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2875 ret = bcmgenet_init_rx_ring(priv, i, 2876 priv->hw_params->rx_bds_per_q, 2877 i * priv->hw_params->rx_bds_per_q, 2878 (i + 1) * 2879 priv->hw_params->rx_bds_per_q); 2880 if (ret) 2881 return ret; 2882 2883 ring_cfg |= (1 << i); 2884 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2885 } 2886 2887 /* Initialize Rx default queue 16 */ 2888 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2889 priv->hw_params->rx_queues * 2890 priv->hw_params->rx_bds_per_q, 2891 TOTAL_DESC); 2892 if (ret) 2893 return ret; 2894 2895 ring_cfg |= (1 << DESC_INDEX); 2896 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2897 2898 /* Enable rings */ 2899 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2900 2901 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2902 if (dma_enable) 2903 dma_ctrl |= DMA_EN; 2904 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2905 2906 return 0; 2907 } 2908 2909 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2910 { 2911 int ret = 0; 2912 int timeout = 0; 2913 u32 reg; 2914 u32 dma_ctrl; 2915 int i; 2916 2917 /* Disable TDMA to stop add more frames in TX DMA */ 2918 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2919 reg &= ~DMA_EN; 2920 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2921 2922 /* Check TDMA status register to confirm TDMA is disabled */ 2923 while (timeout++ < DMA_TIMEOUT_VAL) { 2924 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2925 if (reg & DMA_DISABLED) 2926 break; 2927 2928 udelay(1); 2929 } 2930 2931 if (timeout == DMA_TIMEOUT_VAL) { 2932 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2933 ret = -ETIMEDOUT; 2934 } 2935 2936 /* Wait 10ms for packet drain in both tx and rx dma */ 2937 usleep_range(10000, 20000); 2938 2939 /* Disable RDMA */ 2940 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2941 reg &= ~DMA_EN; 2942 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2943 2944 timeout = 0; 2945 /* Check RDMA status register to confirm RDMA is disabled */ 2946 while (timeout++ < DMA_TIMEOUT_VAL) { 2947 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2948 if (reg & DMA_DISABLED) 2949 break; 2950 2951 udelay(1); 2952 } 2953 2954 if (timeout == DMA_TIMEOUT_VAL) { 2955 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2956 ret = -ETIMEDOUT; 2957 } 2958 2959 dma_ctrl = 0; 2960 for (i = 0; i < priv->hw_params->rx_queues; i++) 2961 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2962 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2963 reg &= ~dma_ctrl; 2964 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2965 2966 dma_ctrl = 0; 2967 for (i = 0; i < priv->hw_params->tx_queues; i++) 2968 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2969 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2970 reg &= ~dma_ctrl; 2971 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2972 2973 return ret; 2974 } 2975 2976 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2977 { 2978 struct netdev_queue *txq; 2979 int i; 2980 2981 bcmgenet_fini_rx_napi(priv); 2982 bcmgenet_fini_tx_napi(priv); 2983 2984 for (i = 0; i < priv->num_tx_bds; i++) 2985 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2986 priv->tx_cbs + i)); 2987 2988 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2989 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2990 netdev_tx_reset_queue(txq); 2991 } 2992 2993 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2994 netdev_tx_reset_queue(txq); 2995 2996 bcmgenet_free_rx_buffers(priv); 2997 kfree(priv->rx_cbs); 2998 kfree(priv->tx_cbs); 2999 } 3000 3001 /* init_edma: Initialize DMA control register */ 3002 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 3003 { 3004 int ret; 3005 unsigned int i; 3006 struct enet_cb *cb; 3007 3008 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 3009 3010 /* Initialize common Rx ring structures */ 3011 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 3012 priv->num_rx_bds = TOTAL_DESC; 3013 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 3014 GFP_KERNEL); 3015 if (!priv->rx_cbs) 3016 return -ENOMEM; 3017 3018 for (i = 0; i < priv->num_rx_bds; i++) { 3019 cb = priv->rx_cbs + i; 3020 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 3021 } 3022 3023 /* Initialize common TX ring structures */ 3024 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 3025 priv->num_tx_bds = TOTAL_DESC; 3026 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 3027 GFP_KERNEL); 3028 if (!priv->tx_cbs) { 3029 kfree(priv->rx_cbs); 3030 return -ENOMEM; 3031 } 3032 3033 for (i = 0; i < priv->num_tx_bds; i++) { 3034 cb = priv->tx_cbs + i; 3035 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 3036 } 3037 3038 /* Init rDma */ 3039 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 3040 DMA_SCB_BURST_SIZE); 3041 3042 /* Initialize Rx queues */ 3043 ret = bcmgenet_init_rx_queues(priv->dev); 3044 if (ret) { 3045 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 3046 bcmgenet_free_rx_buffers(priv); 3047 kfree(priv->rx_cbs); 3048 kfree(priv->tx_cbs); 3049 return ret; 3050 } 3051 3052 /* Init tDma */ 3053 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 3054 DMA_SCB_BURST_SIZE); 3055 3056 /* Initialize Tx queues */ 3057 bcmgenet_init_tx_queues(priv->dev); 3058 3059 return 0; 3060 } 3061 3062 /* Interrupt bottom half */ 3063 static void bcmgenet_irq_task(struct work_struct *work) 3064 { 3065 unsigned int status; 3066 struct bcmgenet_priv *priv = container_of( 3067 work, struct bcmgenet_priv, bcmgenet_irq_work); 3068 3069 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 3070 3071 spin_lock_irq(&priv->lock); 3072 status = priv->irq0_stat; 3073 priv->irq0_stat = 0; 3074 spin_unlock_irq(&priv->lock); 3075 3076 if (status & UMAC_IRQ_PHY_DET_R && 3077 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 3078 phy_init_hw(priv->dev->phydev); 3079 genphy_config_aneg(priv->dev->phydev); 3080 } 3081 3082 /* Link UP/DOWN event */ 3083 if (status & UMAC_IRQ_LINK_EVENT) 3084 phy_mac_interrupt(priv->dev->phydev); 3085 3086 } 3087 3088 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 3089 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 3090 { 3091 struct bcmgenet_priv *priv = dev_id; 3092 struct bcmgenet_rx_ring *rx_ring; 3093 struct bcmgenet_tx_ring *tx_ring; 3094 unsigned int index, status; 3095 3096 /* Read irq status */ 3097 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 3098 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3099 3100 /* clear interrupts */ 3101 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 3102 3103 netif_dbg(priv, intr, priv->dev, 3104 "%s: IRQ=0x%x\n", __func__, status); 3105 3106 /* Check Rx priority queue interrupts */ 3107 for (index = 0; index < priv->hw_params->rx_queues; index++) { 3108 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 3109 continue; 3110 3111 rx_ring = &priv->rx_rings[index]; 3112 rx_ring->dim.event_ctr++; 3113 3114 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3115 rx_ring->int_disable(rx_ring); 3116 __napi_schedule_irqoff(&rx_ring->napi); 3117 } 3118 } 3119 3120 /* Check Tx priority queue interrupts */ 3121 for (index = 0; index < priv->hw_params->tx_queues; index++) { 3122 if (!(status & BIT(index))) 3123 continue; 3124 3125 tx_ring = &priv->tx_rings[index]; 3126 3127 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3128 tx_ring->int_disable(tx_ring); 3129 __napi_schedule_irqoff(&tx_ring->napi); 3130 } 3131 } 3132 3133 return IRQ_HANDLED; 3134 } 3135 3136 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 3137 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 3138 { 3139 struct bcmgenet_priv *priv = dev_id; 3140 struct bcmgenet_rx_ring *rx_ring; 3141 struct bcmgenet_tx_ring *tx_ring; 3142 unsigned int status; 3143 unsigned long flags; 3144 3145 /* Read irq status */ 3146 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 3147 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3148 3149 /* clear interrupts */ 3150 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 3151 3152 netif_dbg(priv, intr, priv->dev, 3153 "IRQ=0x%x\n", status); 3154 3155 if (status & UMAC_IRQ_RXDMA_DONE) { 3156 rx_ring = &priv->rx_rings[DESC_INDEX]; 3157 rx_ring->dim.event_ctr++; 3158 3159 if (likely(napi_schedule_prep(&rx_ring->napi))) { 3160 rx_ring->int_disable(rx_ring); 3161 __napi_schedule_irqoff(&rx_ring->napi); 3162 } 3163 } 3164 3165 if (status & UMAC_IRQ_TXDMA_DONE) { 3166 tx_ring = &priv->tx_rings[DESC_INDEX]; 3167 3168 if (likely(napi_schedule_prep(&tx_ring->napi))) { 3169 tx_ring->int_disable(tx_ring); 3170 __napi_schedule_irqoff(&tx_ring->napi); 3171 } 3172 } 3173 3174 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 3175 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 3176 wake_up(&priv->wq); 3177 } 3178 3179 /* all other interested interrupts handled in bottom half */ 3180 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 3181 if (status) { 3182 /* Save irq status for bottom-half processing. */ 3183 spin_lock_irqsave(&priv->lock, flags); 3184 priv->irq0_stat |= status; 3185 spin_unlock_irqrestore(&priv->lock, flags); 3186 3187 schedule_work(&priv->bcmgenet_irq_work); 3188 } 3189 3190 return IRQ_HANDLED; 3191 } 3192 3193 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 3194 { 3195 /* Acknowledge the interrupt */ 3196 return IRQ_HANDLED; 3197 } 3198 3199 #ifdef CONFIG_NET_POLL_CONTROLLER 3200 static void bcmgenet_poll_controller(struct net_device *dev) 3201 { 3202 struct bcmgenet_priv *priv = netdev_priv(dev); 3203 3204 /* Invoke the main RX/TX interrupt handler */ 3205 disable_irq(priv->irq0); 3206 bcmgenet_isr0(priv->irq0, priv); 3207 enable_irq(priv->irq0); 3208 3209 /* And the interrupt handler for RX/TX priority queues */ 3210 disable_irq(priv->irq1); 3211 bcmgenet_isr1(priv->irq1, priv); 3212 enable_irq(priv->irq1); 3213 } 3214 #endif 3215 3216 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 3217 { 3218 u32 reg; 3219 3220 reg = bcmgenet_rbuf_ctrl_get(priv); 3221 reg |= BIT(1); 3222 bcmgenet_rbuf_ctrl_set(priv, reg); 3223 udelay(10); 3224 3225 reg &= ~BIT(1); 3226 bcmgenet_rbuf_ctrl_set(priv, reg); 3227 udelay(10); 3228 } 3229 3230 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 3231 unsigned char *addr) 3232 { 3233 bcmgenet_umac_writel(priv, get_unaligned_be32(&addr[0]), UMAC_MAC0); 3234 bcmgenet_umac_writel(priv, get_unaligned_be16(&addr[4]), UMAC_MAC1); 3235 } 3236 3237 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 3238 unsigned char *addr) 3239 { 3240 u32 addr_tmp; 3241 3242 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 3243 put_unaligned_be32(addr_tmp, &addr[0]); 3244 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 3245 put_unaligned_be16(addr_tmp, &addr[4]); 3246 } 3247 3248 /* Returns a reusable dma control register value */ 3249 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 3250 { 3251 u32 reg; 3252 u32 dma_ctrl; 3253 3254 /* disable DMA */ 3255 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 3256 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3257 reg &= ~dma_ctrl; 3258 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3259 3260 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3261 reg &= ~dma_ctrl; 3262 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3263 3264 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 3265 udelay(10); 3266 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 3267 3268 return dma_ctrl; 3269 } 3270 3271 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 3272 { 3273 u32 reg; 3274 3275 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 3276 reg |= dma_ctrl; 3277 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 3278 3279 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 3280 reg |= dma_ctrl; 3281 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 3282 } 3283 3284 static void bcmgenet_netif_start(struct net_device *dev) 3285 { 3286 struct bcmgenet_priv *priv = netdev_priv(dev); 3287 3288 /* Start the network engine */ 3289 bcmgenet_set_rx_mode(dev); 3290 bcmgenet_enable_rx_napi(priv); 3291 3292 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 3293 3294 bcmgenet_enable_tx_napi(priv); 3295 3296 /* Monitor link interrupts now */ 3297 bcmgenet_link_intr_enable(priv); 3298 3299 phy_start(dev->phydev); 3300 } 3301 3302 static int bcmgenet_open(struct net_device *dev) 3303 { 3304 struct bcmgenet_priv *priv = netdev_priv(dev); 3305 unsigned long dma_ctrl; 3306 u32 reg; 3307 int ret; 3308 3309 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 3310 3311 /* Turn on the clock */ 3312 clk_prepare_enable(priv->clk); 3313 3314 /* If this is an internal GPHY, power it back on now, before UniMAC is 3315 * brought out of reset as absolutely no UniMAC activity is allowed 3316 */ 3317 if (priv->internal_phy) 3318 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3319 3320 /* take MAC out of reset */ 3321 bcmgenet_umac_reset(priv); 3322 3323 init_umac(priv); 3324 3325 /* Apply features again in case we changed them while interface was 3326 * down 3327 */ 3328 bcmgenet_set_features(dev, dev->features); 3329 3330 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3331 3332 if (priv->internal_phy) { 3333 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3334 reg |= EXT_ENERGY_DET_MASK; 3335 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3336 } 3337 3338 /* Disable RX/TX DMA and flush TX queues */ 3339 dma_ctrl = bcmgenet_dma_disable(priv); 3340 3341 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3342 ret = bcmgenet_init_dma(priv); 3343 if (ret) { 3344 netdev_err(dev, "failed to initialize DMA\n"); 3345 goto err_clk_disable; 3346 } 3347 3348 /* Always enable ring 16 - descriptor ring */ 3349 bcmgenet_enable_dma(priv, dma_ctrl); 3350 3351 /* HFB init */ 3352 bcmgenet_hfb_init(priv); 3353 3354 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 3355 dev->name, priv); 3356 if (ret < 0) { 3357 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 3358 goto err_fini_dma; 3359 } 3360 3361 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 3362 dev->name, priv); 3363 if (ret < 0) { 3364 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 3365 goto err_irq0; 3366 } 3367 3368 ret = bcmgenet_mii_probe(dev); 3369 if (ret) { 3370 netdev_err(dev, "failed to connect to PHY\n"); 3371 goto err_irq1; 3372 } 3373 3374 bcmgenet_netif_start(dev); 3375 3376 netif_tx_start_all_queues(dev); 3377 3378 return 0; 3379 3380 err_irq1: 3381 free_irq(priv->irq1, priv); 3382 err_irq0: 3383 free_irq(priv->irq0, priv); 3384 err_fini_dma: 3385 bcmgenet_dma_teardown(priv); 3386 bcmgenet_fini_dma(priv); 3387 err_clk_disable: 3388 if (priv->internal_phy) 3389 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3390 clk_disable_unprepare(priv->clk); 3391 return ret; 3392 } 3393 3394 static void bcmgenet_netif_stop(struct net_device *dev) 3395 { 3396 struct bcmgenet_priv *priv = netdev_priv(dev); 3397 3398 bcmgenet_disable_tx_napi(priv); 3399 netif_tx_disable(dev); 3400 3401 /* Disable MAC receive */ 3402 umac_enable_set(priv, CMD_RX_EN, false); 3403 3404 bcmgenet_dma_teardown(priv); 3405 3406 /* Disable MAC transmit. TX DMA disabled must be done before this */ 3407 umac_enable_set(priv, CMD_TX_EN, false); 3408 3409 phy_stop(dev->phydev); 3410 bcmgenet_disable_rx_napi(priv); 3411 bcmgenet_intr_disable(priv); 3412 3413 /* Wait for pending work items to complete. Since interrupts are 3414 * disabled no new work will be scheduled. 3415 */ 3416 cancel_work_sync(&priv->bcmgenet_irq_work); 3417 3418 priv->old_link = -1; 3419 priv->old_speed = -1; 3420 priv->old_duplex = -1; 3421 priv->old_pause = -1; 3422 3423 /* tx reclaim */ 3424 bcmgenet_tx_reclaim_all(dev); 3425 bcmgenet_fini_dma(priv); 3426 } 3427 3428 static int bcmgenet_close(struct net_device *dev) 3429 { 3430 struct bcmgenet_priv *priv = netdev_priv(dev); 3431 int ret = 0; 3432 3433 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 3434 3435 bcmgenet_netif_stop(dev); 3436 3437 /* Really kill the PHY state machine and disconnect from it */ 3438 phy_disconnect(dev->phydev); 3439 3440 free_irq(priv->irq0, priv); 3441 free_irq(priv->irq1, priv); 3442 3443 if (priv->internal_phy) 3444 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3445 3446 clk_disable_unprepare(priv->clk); 3447 3448 return ret; 3449 } 3450 3451 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 3452 { 3453 struct bcmgenet_priv *priv = ring->priv; 3454 u32 p_index, c_index, intsts, intmsk; 3455 struct netdev_queue *txq; 3456 unsigned int free_bds; 3457 bool txq_stopped; 3458 3459 if (!netif_msg_tx_err(priv)) 3460 return; 3461 3462 txq = netdev_get_tx_queue(priv->dev, ring->queue); 3463 3464 spin_lock(&ring->lock); 3465 if (ring->index == DESC_INDEX) { 3466 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 3467 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 3468 } else { 3469 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 3470 intmsk = 1 << ring->index; 3471 } 3472 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 3473 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 3474 txq_stopped = netif_tx_queue_stopped(txq); 3475 free_bds = ring->free_bds; 3476 spin_unlock(&ring->lock); 3477 3478 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 3479 "TX queue status: %s, interrupts: %s\n" 3480 "(sw)free_bds: %d (sw)size: %d\n" 3481 "(sw)p_index: %d (hw)p_index: %d\n" 3482 "(sw)c_index: %d (hw)c_index: %d\n" 3483 "(sw)clean_p: %d (sw)write_p: %d\n" 3484 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3485 ring->index, ring->queue, 3486 txq_stopped ? "stopped" : "active", 3487 intsts & intmsk ? "enabled" : "disabled", 3488 free_bds, ring->size, 3489 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3490 ring->c_index, c_index & DMA_C_INDEX_MASK, 3491 ring->clean_ptr, ring->write_ptr, 3492 ring->cb_ptr, ring->end_ptr); 3493 } 3494 3495 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3496 { 3497 struct bcmgenet_priv *priv = netdev_priv(dev); 3498 u32 int0_enable = 0; 3499 u32 int1_enable = 0; 3500 unsigned int q; 3501 3502 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3503 3504 for (q = 0; q < priv->hw_params->tx_queues; q++) 3505 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3506 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3507 3508 bcmgenet_tx_reclaim_all(dev); 3509 3510 for (q = 0; q < priv->hw_params->tx_queues; q++) 3511 int1_enable |= (1 << q); 3512 3513 int0_enable = UMAC_IRQ_TXDMA_DONE; 3514 3515 /* Re-enable TX interrupts if disabled */ 3516 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3517 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3518 3519 netif_trans_update(dev); 3520 3521 dev->stats.tx_errors++; 3522 3523 netif_tx_wake_all_queues(dev); 3524 } 3525 3526 #define MAX_MDF_FILTER 17 3527 3528 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3529 unsigned char *addr, 3530 int *i) 3531 { 3532 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3533 UMAC_MDF_ADDR + (*i * 4)); 3534 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3535 addr[4] << 8 | addr[5], 3536 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3537 *i += 2; 3538 } 3539 3540 static void bcmgenet_set_rx_mode(struct net_device *dev) 3541 { 3542 struct bcmgenet_priv *priv = netdev_priv(dev); 3543 struct netdev_hw_addr *ha; 3544 int i, nfilter; 3545 u32 reg; 3546 3547 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3548 3549 /* Number of filters needed */ 3550 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3551 3552 /* 3553 * Turn on promicuous mode for three scenarios 3554 * 1. IFF_PROMISC flag is set 3555 * 2. IFF_ALLMULTI flag is set 3556 * 3. The number of filters needed exceeds the number filters 3557 * supported by the hardware. 3558 */ 3559 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3560 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3561 (nfilter > MAX_MDF_FILTER)) { 3562 reg |= CMD_PROMISC; 3563 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3564 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3565 return; 3566 } else { 3567 reg &= ~CMD_PROMISC; 3568 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3569 } 3570 3571 /* update MDF filter */ 3572 i = 0; 3573 /* Broadcast */ 3574 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3575 /* my own address.*/ 3576 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3577 3578 /* Unicast */ 3579 netdev_for_each_uc_addr(ha, dev) 3580 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3581 3582 /* Multicast */ 3583 netdev_for_each_mc_addr(ha, dev) 3584 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3585 3586 /* Enable filters */ 3587 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3588 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3589 } 3590 3591 /* Set the hardware MAC address. */ 3592 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3593 { 3594 struct sockaddr *addr = p; 3595 3596 /* Setting the MAC address at the hardware level is not possible 3597 * without disabling the UniMAC RX/TX enable bits. 3598 */ 3599 if (netif_running(dev)) 3600 return -EBUSY; 3601 3602 ether_addr_copy(dev->dev_addr, addr->sa_data); 3603 3604 return 0; 3605 } 3606 3607 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3608 { 3609 struct bcmgenet_priv *priv = netdev_priv(dev); 3610 unsigned long tx_bytes = 0, tx_packets = 0; 3611 unsigned long rx_bytes = 0, rx_packets = 0; 3612 unsigned long rx_errors = 0, rx_dropped = 0; 3613 struct bcmgenet_tx_ring *tx_ring; 3614 struct bcmgenet_rx_ring *rx_ring; 3615 unsigned int q; 3616 3617 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3618 tx_ring = &priv->tx_rings[q]; 3619 tx_bytes += tx_ring->bytes; 3620 tx_packets += tx_ring->packets; 3621 } 3622 tx_ring = &priv->tx_rings[DESC_INDEX]; 3623 tx_bytes += tx_ring->bytes; 3624 tx_packets += tx_ring->packets; 3625 3626 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3627 rx_ring = &priv->rx_rings[q]; 3628 3629 rx_bytes += rx_ring->bytes; 3630 rx_packets += rx_ring->packets; 3631 rx_errors += rx_ring->errors; 3632 rx_dropped += rx_ring->dropped; 3633 } 3634 rx_ring = &priv->rx_rings[DESC_INDEX]; 3635 rx_bytes += rx_ring->bytes; 3636 rx_packets += rx_ring->packets; 3637 rx_errors += rx_ring->errors; 3638 rx_dropped += rx_ring->dropped; 3639 3640 dev->stats.tx_bytes = tx_bytes; 3641 dev->stats.tx_packets = tx_packets; 3642 dev->stats.rx_bytes = rx_bytes; 3643 dev->stats.rx_packets = rx_packets; 3644 dev->stats.rx_errors = rx_errors; 3645 dev->stats.rx_missed_errors = rx_errors; 3646 dev->stats.rx_dropped = rx_dropped; 3647 return &dev->stats; 3648 } 3649 3650 static const struct net_device_ops bcmgenet_netdev_ops = { 3651 .ndo_open = bcmgenet_open, 3652 .ndo_stop = bcmgenet_close, 3653 .ndo_start_xmit = bcmgenet_xmit, 3654 .ndo_tx_timeout = bcmgenet_timeout, 3655 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3656 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3657 .ndo_do_ioctl = phy_do_ioctl_running, 3658 .ndo_set_features = bcmgenet_set_features, 3659 #ifdef CONFIG_NET_POLL_CONTROLLER 3660 .ndo_poll_controller = bcmgenet_poll_controller, 3661 #endif 3662 .ndo_get_stats = bcmgenet_get_stats, 3663 }; 3664 3665 /* Array of GENET hardware parameters/characteristics */ 3666 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3667 [GENET_V1] = { 3668 .tx_queues = 0, 3669 .tx_bds_per_q = 0, 3670 .rx_queues = 0, 3671 .rx_bds_per_q = 0, 3672 .bp_in_en_shift = 16, 3673 .bp_in_mask = 0xffff, 3674 .hfb_filter_cnt = 16, 3675 .qtag_mask = 0x1F, 3676 .hfb_offset = 0x1000, 3677 .rdma_offset = 0x2000, 3678 .tdma_offset = 0x3000, 3679 .words_per_bd = 2, 3680 }, 3681 [GENET_V2] = { 3682 .tx_queues = 4, 3683 .tx_bds_per_q = 32, 3684 .rx_queues = 0, 3685 .rx_bds_per_q = 0, 3686 .bp_in_en_shift = 16, 3687 .bp_in_mask = 0xffff, 3688 .hfb_filter_cnt = 16, 3689 .qtag_mask = 0x1F, 3690 .tbuf_offset = 0x0600, 3691 .hfb_offset = 0x1000, 3692 .hfb_reg_offset = 0x2000, 3693 .rdma_offset = 0x3000, 3694 .tdma_offset = 0x4000, 3695 .words_per_bd = 2, 3696 .flags = GENET_HAS_EXT, 3697 }, 3698 [GENET_V3] = { 3699 .tx_queues = 4, 3700 .tx_bds_per_q = 32, 3701 .rx_queues = 0, 3702 .rx_bds_per_q = 0, 3703 .bp_in_en_shift = 17, 3704 .bp_in_mask = 0x1ffff, 3705 .hfb_filter_cnt = 48, 3706 .hfb_filter_size = 128, 3707 .qtag_mask = 0x3F, 3708 .tbuf_offset = 0x0600, 3709 .hfb_offset = 0x8000, 3710 .hfb_reg_offset = 0xfc00, 3711 .rdma_offset = 0x10000, 3712 .tdma_offset = 0x11000, 3713 .words_per_bd = 2, 3714 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3715 GENET_HAS_MOCA_LINK_DET, 3716 }, 3717 [GENET_V4] = { 3718 .tx_queues = 4, 3719 .tx_bds_per_q = 32, 3720 .rx_queues = 0, 3721 .rx_bds_per_q = 0, 3722 .bp_in_en_shift = 17, 3723 .bp_in_mask = 0x1ffff, 3724 .hfb_filter_cnt = 48, 3725 .hfb_filter_size = 128, 3726 .qtag_mask = 0x3F, 3727 .tbuf_offset = 0x0600, 3728 .hfb_offset = 0x8000, 3729 .hfb_reg_offset = 0xfc00, 3730 .rdma_offset = 0x2000, 3731 .tdma_offset = 0x4000, 3732 .words_per_bd = 3, 3733 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3734 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3735 }, 3736 [GENET_V5] = { 3737 .tx_queues = 4, 3738 .tx_bds_per_q = 32, 3739 .rx_queues = 0, 3740 .rx_bds_per_q = 0, 3741 .bp_in_en_shift = 17, 3742 .bp_in_mask = 0x1ffff, 3743 .hfb_filter_cnt = 48, 3744 .hfb_filter_size = 128, 3745 .qtag_mask = 0x3F, 3746 .tbuf_offset = 0x0600, 3747 .hfb_offset = 0x8000, 3748 .hfb_reg_offset = 0xfc00, 3749 .rdma_offset = 0x2000, 3750 .tdma_offset = 0x4000, 3751 .words_per_bd = 3, 3752 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3753 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3754 }, 3755 }; 3756 3757 /* Infer hardware parameters from the detected GENET version */ 3758 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3759 { 3760 struct bcmgenet_hw_params *params; 3761 u32 reg; 3762 u8 major; 3763 u16 gphy_rev; 3764 3765 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3766 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3767 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3768 } else if (GENET_IS_V3(priv)) { 3769 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3770 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3771 } else if (GENET_IS_V2(priv)) { 3772 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3773 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3774 } else if (GENET_IS_V1(priv)) { 3775 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3776 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3777 } 3778 3779 /* enum genet_version starts at 1 */ 3780 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3781 params = priv->hw_params; 3782 3783 /* Read GENET HW version */ 3784 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3785 major = (reg >> 24 & 0x0f); 3786 if (major == 6) 3787 major = 5; 3788 else if (major == 5) 3789 major = 4; 3790 else if (major == 0) 3791 major = 1; 3792 if (major != priv->version) { 3793 dev_err(&priv->pdev->dev, 3794 "GENET version mismatch, got: %d, configured for: %d\n", 3795 major, priv->version); 3796 } 3797 3798 /* Print the GENET core version */ 3799 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3800 major, (reg >> 16) & 0x0f, reg & 0xffff); 3801 3802 /* Store the integrated PHY revision for the MDIO probing function 3803 * to pass this information to the PHY driver. The PHY driver expects 3804 * to find the PHY major revision in bits 15:8 while the GENET register 3805 * stores that information in bits 7:0, account for that. 3806 * 3807 * On newer chips, starting with PHY revision G0, a new scheme is 3808 * deployed similar to the Starfighter 2 switch with GPHY major 3809 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3810 * is reserved as well as special value 0x01ff, we have a small 3811 * heuristic to check for the new GPHY revision and re-arrange things 3812 * so the GPHY driver is happy. 3813 */ 3814 gphy_rev = reg & 0xffff; 3815 3816 if (GENET_IS_V5(priv)) { 3817 /* The EPHY revision should come from the MDIO registers of 3818 * the PHY not from GENET. 3819 */ 3820 if (gphy_rev != 0) { 3821 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3822 gphy_rev); 3823 } 3824 /* This is reserved so should require special treatment */ 3825 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3826 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3827 return; 3828 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3829 } else if ((gphy_rev & 0xf0) != 0) { 3830 priv->gphy_rev = gphy_rev << 8; 3831 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3832 } else if ((gphy_rev & 0xff00) != 0) { 3833 priv->gphy_rev = gphy_rev; 3834 } 3835 3836 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3837 if (!(params->flags & GENET_HAS_40BITS)) 3838 pr_warn("GENET does not support 40-bits PA\n"); 3839 #endif 3840 3841 pr_debug("Configuration for version: %d\n" 3842 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3843 "BP << en: %2d, BP msk: 0x%05x\n" 3844 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3845 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3846 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3847 "Words/BD: %d\n", 3848 priv->version, 3849 params->tx_queues, params->tx_bds_per_q, 3850 params->rx_queues, params->rx_bds_per_q, 3851 params->bp_in_en_shift, params->bp_in_mask, 3852 params->hfb_filter_cnt, params->qtag_mask, 3853 params->tbuf_offset, params->hfb_offset, 3854 params->hfb_reg_offset, 3855 params->rdma_offset, params->tdma_offset, 3856 params->words_per_bd); 3857 } 3858 3859 struct bcmgenet_plat_data { 3860 enum bcmgenet_version version; 3861 u32 dma_max_burst_length; 3862 }; 3863 3864 static const struct bcmgenet_plat_data v1_plat_data = { 3865 .version = GENET_V1, 3866 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3867 }; 3868 3869 static const struct bcmgenet_plat_data v2_plat_data = { 3870 .version = GENET_V2, 3871 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3872 }; 3873 3874 static const struct bcmgenet_plat_data v3_plat_data = { 3875 .version = GENET_V3, 3876 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3877 }; 3878 3879 static const struct bcmgenet_plat_data v4_plat_data = { 3880 .version = GENET_V4, 3881 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3882 }; 3883 3884 static const struct bcmgenet_plat_data v5_plat_data = { 3885 .version = GENET_V5, 3886 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3887 }; 3888 3889 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3890 .version = GENET_V5, 3891 .dma_max_burst_length = 0x08, 3892 }; 3893 3894 static const struct of_device_id bcmgenet_match[] = { 3895 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3896 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3897 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3898 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3899 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3900 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3901 { }, 3902 }; 3903 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3904 3905 static int bcmgenet_probe(struct platform_device *pdev) 3906 { 3907 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3908 const struct bcmgenet_plat_data *pdata; 3909 struct bcmgenet_priv *priv; 3910 struct net_device *dev; 3911 unsigned int i; 3912 int err = -EIO; 3913 3914 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3915 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3916 GENET_MAX_MQ_CNT + 1); 3917 if (!dev) { 3918 dev_err(&pdev->dev, "can't allocate net device\n"); 3919 return -ENOMEM; 3920 } 3921 3922 priv = netdev_priv(dev); 3923 priv->irq0 = platform_get_irq(pdev, 0); 3924 if (priv->irq0 < 0) { 3925 err = priv->irq0; 3926 goto err; 3927 } 3928 priv->irq1 = platform_get_irq(pdev, 1); 3929 if (priv->irq1 < 0) { 3930 err = priv->irq1; 3931 goto err; 3932 } 3933 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3934 3935 priv->base = devm_platform_ioremap_resource(pdev, 0); 3936 if (IS_ERR(priv->base)) { 3937 err = PTR_ERR(priv->base); 3938 goto err; 3939 } 3940 3941 spin_lock_init(&priv->lock); 3942 3943 SET_NETDEV_DEV(dev, &pdev->dev); 3944 dev_set_drvdata(&pdev->dev, dev); 3945 dev->watchdog_timeo = 2 * HZ; 3946 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3947 dev->netdev_ops = &bcmgenet_netdev_ops; 3948 3949 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3950 3951 /* Set default features */ 3952 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3953 NETIF_F_RXCSUM; 3954 dev->hw_features |= dev->features; 3955 dev->vlan_features |= dev->features; 3956 3957 /* Request the WOL interrupt and advertise suspend if available */ 3958 priv->wol_irq_disabled = true; 3959 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3960 dev->name, priv); 3961 if (!err) 3962 device_set_wakeup_capable(&pdev->dev, 1); 3963 3964 /* Set the needed headroom to account for any possible 3965 * features enabling/disabling at runtime 3966 */ 3967 dev->needed_headroom += 64; 3968 3969 netdev_boot_setup_check(dev); 3970 3971 priv->dev = dev; 3972 priv->pdev = pdev; 3973 3974 pdata = device_get_match_data(&pdev->dev); 3975 if (pdata) { 3976 priv->version = pdata->version; 3977 priv->dma_max_burst_length = pdata->dma_max_burst_length; 3978 } else { 3979 priv->version = pd->genet_version; 3980 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 3981 } 3982 3983 priv->clk = devm_clk_get_optional(&priv->pdev->dev, "enet"); 3984 if (IS_ERR(priv->clk)) { 3985 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 3986 err = PTR_ERR(priv->clk); 3987 goto err; 3988 } 3989 3990 err = clk_prepare_enable(priv->clk); 3991 if (err) 3992 goto err; 3993 3994 bcmgenet_set_hw_params(priv); 3995 3996 err = -EIO; 3997 if (priv->hw_params->flags & GENET_HAS_40BITS) 3998 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 3999 if (err) 4000 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 4001 if (err) 4002 goto err; 4003 4004 /* Mii wait queue */ 4005 init_waitqueue_head(&priv->wq); 4006 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 4007 priv->rx_buf_len = RX_BUF_LENGTH; 4008 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 4009 4010 priv->clk_wol = devm_clk_get_optional(&priv->pdev->dev, "enet-wol"); 4011 if (IS_ERR(priv->clk_wol)) { 4012 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 4013 err = PTR_ERR(priv->clk_wol); 4014 goto err; 4015 } 4016 4017 priv->clk_eee = devm_clk_get_optional(&priv->pdev->dev, "enet-eee"); 4018 if (IS_ERR(priv->clk_eee)) { 4019 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 4020 err = PTR_ERR(priv->clk_eee); 4021 goto err; 4022 } 4023 4024 /* If this is an internal GPHY, power it on now, before UniMAC is 4025 * brought out of reset as absolutely no UniMAC activity is allowed 4026 */ 4027 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 4028 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4029 4030 if (pd && !IS_ERR_OR_NULL(pd->mac_address)) 4031 ether_addr_copy(dev->dev_addr, pd->mac_address); 4032 else 4033 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 4034 if (has_acpi_companion(&pdev->dev)) 4035 bcmgenet_get_hw_addr(priv, dev->dev_addr); 4036 4037 if (!is_valid_ether_addr(dev->dev_addr)) { 4038 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 4039 eth_hw_addr_random(dev); 4040 } 4041 4042 reset_umac(priv); 4043 4044 err = bcmgenet_mii_init(dev); 4045 if (err) 4046 goto err_clk_disable; 4047 4048 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 4049 * just the ring 16 descriptor based TX 4050 */ 4051 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 4052 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 4053 4054 /* Set default coalescing parameters */ 4055 for (i = 0; i < priv->hw_params->rx_queues; i++) 4056 priv->rx_rings[i].rx_max_coalesced_frames = 1; 4057 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 4058 4059 /* libphy will determine the link state */ 4060 netif_carrier_off(dev); 4061 4062 /* Turn off the main clock, WOL clock is handled separately */ 4063 clk_disable_unprepare(priv->clk); 4064 4065 err = register_netdev(dev); 4066 if (err) 4067 goto err; 4068 4069 return err; 4070 4071 err_clk_disable: 4072 clk_disable_unprepare(priv->clk); 4073 err: 4074 free_netdev(dev); 4075 return err; 4076 } 4077 4078 static int bcmgenet_remove(struct platform_device *pdev) 4079 { 4080 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 4081 4082 dev_set_drvdata(&pdev->dev, NULL); 4083 unregister_netdev(priv->dev); 4084 bcmgenet_mii_exit(priv->dev); 4085 free_netdev(priv->dev); 4086 4087 return 0; 4088 } 4089 4090 static void bcmgenet_shutdown(struct platform_device *pdev) 4091 { 4092 bcmgenet_remove(pdev); 4093 } 4094 4095 #ifdef CONFIG_PM_SLEEP 4096 static int bcmgenet_resume_noirq(struct device *d) 4097 { 4098 struct net_device *dev = dev_get_drvdata(d); 4099 struct bcmgenet_priv *priv = netdev_priv(dev); 4100 int ret; 4101 u32 reg; 4102 4103 if (!netif_running(dev)) 4104 return 0; 4105 4106 /* Turn on the clock */ 4107 ret = clk_prepare_enable(priv->clk); 4108 if (ret) 4109 return ret; 4110 4111 if (device_may_wakeup(d) && priv->wolopts) { 4112 /* Account for Wake-on-LAN events and clear those events 4113 * (Some devices need more time between enabling the clocks 4114 * and the interrupt register reflecting the wake event so 4115 * read the register twice) 4116 */ 4117 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4118 reg = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT); 4119 if (reg & UMAC_IRQ_WAKE_EVENT) 4120 pm_wakeup_event(&priv->pdev->dev, 0); 4121 } 4122 4123 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_WAKE_EVENT, INTRL2_CPU_CLEAR); 4124 4125 return 0; 4126 } 4127 4128 static int bcmgenet_resume(struct device *d) 4129 { 4130 struct net_device *dev = dev_get_drvdata(d); 4131 struct bcmgenet_priv *priv = netdev_priv(dev); 4132 unsigned long dma_ctrl; 4133 u32 offset, reg; 4134 int ret; 4135 4136 if (!netif_running(dev)) 4137 return 0; 4138 4139 /* From WOL-enabled suspend, switch to regular clock */ 4140 if (device_may_wakeup(d) && priv->wolopts) 4141 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 4142 4143 /* If this is an internal GPHY, power it back on now, before UniMAC is 4144 * brought out of reset as absolutely no UniMAC activity is allowed 4145 */ 4146 if (priv->internal_phy) 4147 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 4148 4149 bcmgenet_umac_reset(priv); 4150 4151 init_umac(priv); 4152 4153 phy_init_hw(dev->phydev); 4154 4155 /* Speed settings must be restored */ 4156 genphy_config_aneg(dev->phydev); 4157 bcmgenet_mii_config(priv->dev, false); 4158 4159 /* Restore enabled features */ 4160 bcmgenet_set_features(dev, dev->features); 4161 4162 bcmgenet_set_hw_addr(priv, dev->dev_addr); 4163 4164 offset = HFB_FLT_ENABLE_V3PLUS; 4165 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[1], offset); 4166 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[2], offset + sizeof(u32)); 4167 bcmgenet_hfb_reg_writel(priv, priv->hfb_en[0], HFB_CTRL); 4168 4169 if (priv->internal_phy) { 4170 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 4171 reg |= EXT_ENERGY_DET_MASK; 4172 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 4173 } 4174 4175 /* Disable RX/TX DMA and flush TX queues */ 4176 dma_ctrl = bcmgenet_dma_disable(priv); 4177 4178 /* Reinitialize TDMA and RDMA and SW housekeeping */ 4179 ret = bcmgenet_init_dma(priv); 4180 if (ret) { 4181 netdev_err(dev, "failed to initialize DMA\n"); 4182 goto out_clk_disable; 4183 } 4184 4185 /* Always enable ring 16 - descriptor ring */ 4186 bcmgenet_enable_dma(priv, dma_ctrl); 4187 4188 if (!device_may_wakeup(d)) 4189 phy_resume(dev->phydev); 4190 4191 if (priv->eee.eee_enabled) 4192 bcmgenet_eee_enable_set(dev, true); 4193 4194 bcmgenet_netif_start(dev); 4195 4196 netif_device_attach(dev); 4197 4198 return 0; 4199 4200 out_clk_disable: 4201 if (priv->internal_phy) 4202 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4203 clk_disable_unprepare(priv->clk); 4204 return ret; 4205 } 4206 4207 static int bcmgenet_suspend(struct device *d) 4208 { 4209 struct net_device *dev = dev_get_drvdata(d); 4210 struct bcmgenet_priv *priv = netdev_priv(dev); 4211 u32 offset; 4212 4213 if (!netif_running(dev)) 4214 return 0; 4215 4216 netif_device_detach(dev); 4217 4218 bcmgenet_netif_stop(dev); 4219 4220 if (!device_may_wakeup(d)) 4221 phy_suspend(dev->phydev); 4222 4223 /* Preserve filter state and disable filtering */ 4224 priv->hfb_en[0] = bcmgenet_hfb_reg_readl(priv, HFB_CTRL); 4225 offset = HFB_FLT_ENABLE_V3PLUS; 4226 priv->hfb_en[1] = bcmgenet_hfb_reg_readl(priv, offset); 4227 priv->hfb_en[2] = bcmgenet_hfb_reg_readl(priv, offset + sizeof(u32)); 4228 bcmgenet_hfb_reg_writel(priv, 0, HFB_CTRL); 4229 4230 return 0; 4231 } 4232 4233 static int bcmgenet_suspend_noirq(struct device *d) 4234 { 4235 struct net_device *dev = dev_get_drvdata(d); 4236 struct bcmgenet_priv *priv = netdev_priv(dev); 4237 int ret = 0; 4238 4239 if (!netif_running(dev)) 4240 return 0; 4241 4242 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 4243 if (device_may_wakeup(d) && priv->wolopts) 4244 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 4245 else if (priv->internal_phy) 4246 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 4247 4248 /* Let the framework handle resumption and leave the clocks on */ 4249 if (ret) 4250 return ret; 4251 4252 /* Turn off the clocks */ 4253 clk_disable_unprepare(priv->clk); 4254 4255 return 0; 4256 } 4257 #else 4258 #define bcmgenet_suspend NULL 4259 #define bcmgenet_suspend_noirq NULL 4260 #define bcmgenet_resume NULL 4261 #define bcmgenet_resume_noirq NULL 4262 #endif /* CONFIG_PM_SLEEP */ 4263 4264 static const struct dev_pm_ops bcmgenet_pm_ops = { 4265 .suspend = bcmgenet_suspend, 4266 .suspend_noirq = bcmgenet_suspend_noirq, 4267 .resume = bcmgenet_resume, 4268 .resume_noirq = bcmgenet_resume_noirq, 4269 }; 4270 4271 static const struct acpi_device_id genet_acpi_match[] = { 4272 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 4273 { }, 4274 }; 4275 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 4276 4277 static struct platform_driver bcmgenet_driver = { 4278 .probe = bcmgenet_probe, 4279 .remove = bcmgenet_remove, 4280 .shutdown = bcmgenet_shutdown, 4281 .driver = { 4282 .name = "bcmgenet", 4283 .of_match_table = bcmgenet_match, 4284 .pm = &bcmgenet_pm_ops, 4285 .acpi_match_table = genet_acpi_match, 4286 }, 4287 }; 4288 module_platform_driver(bcmgenet_driver); 4289 4290 MODULE_AUTHOR("Broadcom Corporation"); 4291 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 4292 MODULE_ALIAS("platform:bcmgenet"); 4293 MODULE_LICENSE("GPL"); 4294