1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Broadcom GENET (Gigabit Ethernet) controller driver 4 * 5 * Copyright (c) 2014-2019 Broadcom 6 */ 7 8 #define pr_fmt(fmt) "bcmgenet: " fmt 9 10 #include <linux/acpi.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/sched.h> 14 #include <linux/types.h> 15 #include <linux/fcntl.h> 16 #include <linux/interrupt.h> 17 #include <linux/string.h> 18 #include <linux/if_ether.h> 19 #include <linux/init.h> 20 #include <linux/errno.h> 21 #include <linux/delay.h> 22 #include <linux/platform_device.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/pm.h> 25 #include <linux/clk.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_net.h> 30 #include <linux/of_platform.h> 31 #include <net/arp.h> 32 33 #include <linux/mii.h> 34 #include <linux/ethtool.h> 35 #include <linux/netdevice.h> 36 #include <linux/inetdevice.h> 37 #include <linux/etherdevice.h> 38 #include <linux/skbuff.h> 39 #include <linux/in.h> 40 #include <linux/ip.h> 41 #include <linux/ipv6.h> 42 #include <linux/phy.h> 43 #include <linux/platform_data/bcmgenet.h> 44 45 #include <asm/unaligned.h> 46 47 #include "bcmgenet.h" 48 49 /* Maximum number of hardware queues, downsized if needed */ 50 #define GENET_MAX_MQ_CNT 4 51 52 /* Default highest priority queue for multi queue support */ 53 #define GENET_Q0_PRIORITY 0 54 55 #define GENET_Q16_RX_BD_CNT \ 56 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q) 57 #define GENET_Q16_TX_BD_CNT \ 58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q) 59 60 #define RX_BUF_LENGTH 2048 61 #define SKB_ALIGNMENT 32 62 63 /* Tx/Rx DMA register offset, skip 256 descriptors */ 64 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 65 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 66 67 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 68 TOTAL_DESC * DMA_DESC_SIZE) 69 70 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 71 TOTAL_DESC * DMA_DESC_SIZE) 72 73 static inline void bcmgenet_writel(u32 value, void __iomem *offset) 74 { 75 /* MIPS chips strapped for BE will automagically configure the 76 * peripheral registers for CPU-native byte order. 77 */ 78 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 79 __raw_writel(value, offset); 80 else 81 writel_relaxed(value, offset); 82 } 83 84 static inline u32 bcmgenet_readl(void __iomem *offset) 85 { 86 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) 87 return __raw_readl(offset); 88 else 89 return readl_relaxed(offset); 90 } 91 92 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 93 void __iomem *d, u32 value) 94 { 95 bcmgenet_writel(value, d + DMA_DESC_LENGTH_STATUS); 96 } 97 98 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 99 void __iomem *d, 100 dma_addr_t addr) 101 { 102 bcmgenet_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 103 104 /* Register writes to GISB bus can take couple hundred nanoseconds 105 * and are done for each packet, save these expensive writes unless 106 * the platform is explicitly configured for 64-bits/LPAE. 107 */ 108 #ifdef CONFIG_PHYS_ADDR_T_64BIT 109 if (priv->hw_params->flags & GENET_HAS_40BITS) 110 bcmgenet_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 111 #endif 112 } 113 114 /* Combined address + length/status setter */ 115 static inline void dmadesc_set(struct bcmgenet_priv *priv, 116 void __iomem *d, dma_addr_t addr, u32 val) 117 { 118 dmadesc_set_addr(priv, d, addr); 119 dmadesc_set_length_status(priv, d, val); 120 } 121 122 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 123 void __iomem *d) 124 { 125 dma_addr_t addr; 126 127 addr = bcmgenet_readl(d + DMA_DESC_ADDRESS_LO); 128 129 /* Register writes to GISB bus can take couple hundred nanoseconds 130 * and are done for each packet, save these expensive writes unless 131 * the platform is explicitly configured for 64-bits/LPAE. 132 */ 133 #ifdef CONFIG_PHYS_ADDR_T_64BIT 134 if (priv->hw_params->flags & GENET_HAS_40BITS) 135 addr |= (u64)bcmgenet_readl(d + DMA_DESC_ADDRESS_HI) << 32; 136 #endif 137 return addr; 138 } 139 140 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 141 142 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 143 NETIF_MSG_LINK) 144 145 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 146 { 147 if (GENET_IS_V1(priv)) 148 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 149 else 150 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 151 } 152 153 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 154 { 155 if (GENET_IS_V1(priv)) 156 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 157 else 158 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 159 } 160 161 /* These macros are defined to deal with register map change 162 * between GENET1.1 and GENET2. Only those currently being used 163 * by driver are defined. 164 */ 165 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 166 { 167 if (GENET_IS_V1(priv)) 168 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 169 else 170 return bcmgenet_readl(priv->base + 171 priv->hw_params->tbuf_offset + TBUF_CTRL); 172 } 173 174 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 175 { 176 if (GENET_IS_V1(priv)) 177 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 178 else 179 bcmgenet_writel(val, priv->base + 180 priv->hw_params->tbuf_offset + TBUF_CTRL); 181 } 182 183 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 184 { 185 if (GENET_IS_V1(priv)) 186 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 187 else 188 return bcmgenet_readl(priv->base + 189 priv->hw_params->tbuf_offset + TBUF_BP_MC); 190 } 191 192 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 193 { 194 if (GENET_IS_V1(priv)) 195 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 196 else 197 bcmgenet_writel(val, priv->base + 198 priv->hw_params->tbuf_offset + TBUF_BP_MC); 199 } 200 201 /* RX/TX DMA register accessors */ 202 enum dma_reg { 203 DMA_RING_CFG = 0, 204 DMA_CTRL, 205 DMA_STATUS, 206 DMA_SCB_BURST_SIZE, 207 DMA_ARB_CTRL, 208 DMA_PRIORITY_0, 209 DMA_PRIORITY_1, 210 DMA_PRIORITY_2, 211 DMA_INDEX2RING_0, 212 DMA_INDEX2RING_1, 213 DMA_INDEX2RING_2, 214 DMA_INDEX2RING_3, 215 DMA_INDEX2RING_4, 216 DMA_INDEX2RING_5, 217 DMA_INDEX2RING_6, 218 DMA_INDEX2RING_7, 219 DMA_RING0_TIMEOUT, 220 DMA_RING1_TIMEOUT, 221 DMA_RING2_TIMEOUT, 222 DMA_RING3_TIMEOUT, 223 DMA_RING4_TIMEOUT, 224 DMA_RING5_TIMEOUT, 225 DMA_RING6_TIMEOUT, 226 DMA_RING7_TIMEOUT, 227 DMA_RING8_TIMEOUT, 228 DMA_RING9_TIMEOUT, 229 DMA_RING10_TIMEOUT, 230 DMA_RING11_TIMEOUT, 231 DMA_RING12_TIMEOUT, 232 DMA_RING13_TIMEOUT, 233 DMA_RING14_TIMEOUT, 234 DMA_RING15_TIMEOUT, 235 DMA_RING16_TIMEOUT, 236 }; 237 238 static const u8 bcmgenet_dma_regs_v3plus[] = { 239 [DMA_RING_CFG] = 0x00, 240 [DMA_CTRL] = 0x04, 241 [DMA_STATUS] = 0x08, 242 [DMA_SCB_BURST_SIZE] = 0x0C, 243 [DMA_ARB_CTRL] = 0x2C, 244 [DMA_PRIORITY_0] = 0x30, 245 [DMA_PRIORITY_1] = 0x34, 246 [DMA_PRIORITY_2] = 0x38, 247 [DMA_RING0_TIMEOUT] = 0x2C, 248 [DMA_RING1_TIMEOUT] = 0x30, 249 [DMA_RING2_TIMEOUT] = 0x34, 250 [DMA_RING3_TIMEOUT] = 0x38, 251 [DMA_RING4_TIMEOUT] = 0x3c, 252 [DMA_RING5_TIMEOUT] = 0x40, 253 [DMA_RING6_TIMEOUT] = 0x44, 254 [DMA_RING7_TIMEOUT] = 0x48, 255 [DMA_RING8_TIMEOUT] = 0x4c, 256 [DMA_RING9_TIMEOUT] = 0x50, 257 [DMA_RING10_TIMEOUT] = 0x54, 258 [DMA_RING11_TIMEOUT] = 0x58, 259 [DMA_RING12_TIMEOUT] = 0x5c, 260 [DMA_RING13_TIMEOUT] = 0x60, 261 [DMA_RING14_TIMEOUT] = 0x64, 262 [DMA_RING15_TIMEOUT] = 0x68, 263 [DMA_RING16_TIMEOUT] = 0x6C, 264 [DMA_INDEX2RING_0] = 0x70, 265 [DMA_INDEX2RING_1] = 0x74, 266 [DMA_INDEX2RING_2] = 0x78, 267 [DMA_INDEX2RING_3] = 0x7C, 268 [DMA_INDEX2RING_4] = 0x80, 269 [DMA_INDEX2RING_5] = 0x84, 270 [DMA_INDEX2RING_6] = 0x88, 271 [DMA_INDEX2RING_7] = 0x8C, 272 }; 273 274 static const u8 bcmgenet_dma_regs_v2[] = { 275 [DMA_RING_CFG] = 0x00, 276 [DMA_CTRL] = 0x04, 277 [DMA_STATUS] = 0x08, 278 [DMA_SCB_BURST_SIZE] = 0x0C, 279 [DMA_ARB_CTRL] = 0x30, 280 [DMA_PRIORITY_0] = 0x34, 281 [DMA_PRIORITY_1] = 0x38, 282 [DMA_PRIORITY_2] = 0x3C, 283 [DMA_RING0_TIMEOUT] = 0x2C, 284 [DMA_RING1_TIMEOUT] = 0x30, 285 [DMA_RING2_TIMEOUT] = 0x34, 286 [DMA_RING3_TIMEOUT] = 0x38, 287 [DMA_RING4_TIMEOUT] = 0x3c, 288 [DMA_RING5_TIMEOUT] = 0x40, 289 [DMA_RING6_TIMEOUT] = 0x44, 290 [DMA_RING7_TIMEOUT] = 0x48, 291 [DMA_RING8_TIMEOUT] = 0x4c, 292 [DMA_RING9_TIMEOUT] = 0x50, 293 [DMA_RING10_TIMEOUT] = 0x54, 294 [DMA_RING11_TIMEOUT] = 0x58, 295 [DMA_RING12_TIMEOUT] = 0x5c, 296 [DMA_RING13_TIMEOUT] = 0x60, 297 [DMA_RING14_TIMEOUT] = 0x64, 298 [DMA_RING15_TIMEOUT] = 0x68, 299 [DMA_RING16_TIMEOUT] = 0x6C, 300 }; 301 302 static const u8 bcmgenet_dma_regs_v1[] = { 303 [DMA_CTRL] = 0x00, 304 [DMA_STATUS] = 0x04, 305 [DMA_SCB_BURST_SIZE] = 0x0C, 306 [DMA_ARB_CTRL] = 0x30, 307 [DMA_PRIORITY_0] = 0x34, 308 [DMA_PRIORITY_1] = 0x38, 309 [DMA_PRIORITY_2] = 0x3C, 310 [DMA_RING0_TIMEOUT] = 0x2C, 311 [DMA_RING1_TIMEOUT] = 0x30, 312 [DMA_RING2_TIMEOUT] = 0x34, 313 [DMA_RING3_TIMEOUT] = 0x38, 314 [DMA_RING4_TIMEOUT] = 0x3c, 315 [DMA_RING5_TIMEOUT] = 0x40, 316 [DMA_RING6_TIMEOUT] = 0x44, 317 [DMA_RING7_TIMEOUT] = 0x48, 318 [DMA_RING8_TIMEOUT] = 0x4c, 319 [DMA_RING9_TIMEOUT] = 0x50, 320 [DMA_RING10_TIMEOUT] = 0x54, 321 [DMA_RING11_TIMEOUT] = 0x58, 322 [DMA_RING12_TIMEOUT] = 0x5c, 323 [DMA_RING13_TIMEOUT] = 0x60, 324 [DMA_RING14_TIMEOUT] = 0x64, 325 [DMA_RING15_TIMEOUT] = 0x68, 326 [DMA_RING16_TIMEOUT] = 0x6C, 327 }; 328 329 /* Set at runtime once bcmgenet version is known */ 330 static const u8 *bcmgenet_dma_regs; 331 332 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 333 { 334 return netdev_priv(dev_get_drvdata(dev)); 335 } 336 337 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 338 enum dma_reg r) 339 { 340 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 341 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 342 } 343 344 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 345 u32 val, enum dma_reg r) 346 { 347 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 348 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 349 } 350 351 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 352 enum dma_reg r) 353 { 354 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 355 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 356 } 357 358 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 359 u32 val, enum dma_reg r) 360 { 361 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 362 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 363 } 364 365 /* RDMA/TDMA ring registers and accessors 366 * we merge the common fields and just prefix with T/D the registers 367 * having different meaning depending on the direction 368 */ 369 enum dma_ring_reg { 370 TDMA_READ_PTR = 0, 371 RDMA_WRITE_PTR = TDMA_READ_PTR, 372 TDMA_READ_PTR_HI, 373 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 374 TDMA_CONS_INDEX, 375 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 376 TDMA_PROD_INDEX, 377 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 378 DMA_RING_BUF_SIZE, 379 DMA_START_ADDR, 380 DMA_START_ADDR_HI, 381 DMA_END_ADDR, 382 DMA_END_ADDR_HI, 383 DMA_MBUF_DONE_THRESH, 384 TDMA_FLOW_PERIOD, 385 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 386 TDMA_WRITE_PTR, 387 RDMA_READ_PTR = TDMA_WRITE_PTR, 388 TDMA_WRITE_PTR_HI, 389 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 390 }; 391 392 /* GENET v4 supports 40-bits pointer addressing 393 * for obvious reasons the LO and HI word parts 394 * are contiguous, but this offsets the other 395 * registers. 396 */ 397 static const u8 genet_dma_ring_regs_v4[] = { 398 [TDMA_READ_PTR] = 0x00, 399 [TDMA_READ_PTR_HI] = 0x04, 400 [TDMA_CONS_INDEX] = 0x08, 401 [TDMA_PROD_INDEX] = 0x0C, 402 [DMA_RING_BUF_SIZE] = 0x10, 403 [DMA_START_ADDR] = 0x14, 404 [DMA_START_ADDR_HI] = 0x18, 405 [DMA_END_ADDR] = 0x1C, 406 [DMA_END_ADDR_HI] = 0x20, 407 [DMA_MBUF_DONE_THRESH] = 0x24, 408 [TDMA_FLOW_PERIOD] = 0x28, 409 [TDMA_WRITE_PTR] = 0x2C, 410 [TDMA_WRITE_PTR_HI] = 0x30, 411 }; 412 413 static const u8 genet_dma_ring_regs_v123[] = { 414 [TDMA_READ_PTR] = 0x00, 415 [TDMA_CONS_INDEX] = 0x04, 416 [TDMA_PROD_INDEX] = 0x08, 417 [DMA_RING_BUF_SIZE] = 0x0C, 418 [DMA_START_ADDR] = 0x10, 419 [DMA_END_ADDR] = 0x14, 420 [DMA_MBUF_DONE_THRESH] = 0x18, 421 [TDMA_FLOW_PERIOD] = 0x1C, 422 [TDMA_WRITE_PTR] = 0x20, 423 }; 424 425 /* Set at runtime once GENET version is known */ 426 static const u8 *genet_dma_ring_regs; 427 428 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 429 unsigned int ring, 430 enum dma_ring_reg r) 431 { 432 return bcmgenet_readl(priv->base + GENET_TDMA_REG_OFF + 433 (DMA_RING_SIZE * ring) + 434 genet_dma_ring_regs[r]); 435 } 436 437 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 438 unsigned int ring, u32 val, 439 enum dma_ring_reg r) 440 { 441 bcmgenet_writel(val, priv->base + GENET_TDMA_REG_OFF + 442 (DMA_RING_SIZE * ring) + 443 genet_dma_ring_regs[r]); 444 } 445 446 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 447 unsigned int ring, 448 enum dma_ring_reg r) 449 { 450 return bcmgenet_readl(priv->base + GENET_RDMA_REG_OFF + 451 (DMA_RING_SIZE * ring) + 452 genet_dma_ring_regs[r]); 453 } 454 455 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 456 unsigned int ring, u32 val, 457 enum dma_ring_reg r) 458 { 459 bcmgenet_writel(val, priv->base + GENET_RDMA_REG_OFF + 460 (DMA_RING_SIZE * ring) + 461 genet_dma_ring_regs[r]); 462 } 463 464 static int bcmgenet_begin(struct net_device *dev) 465 { 466 struct bcmgenet_priv *priv = netdev_priv(dev); 467 468 /* Turn on the clock */ 469 return clk_prepare_enable(priv->clk); 470 } 471 472 static void bcmgenet_complete(struct net_device *dev) 473 { 474 struct bcmgenet_priv *priv = netdev_priv(dev); 475 476 /* Turn off the clock */ 477 clk_disable_unprepare(priv->clk); 478 } 479 480 static int bcmgenet_get_link_ksettings(struct net_device *dev, 481 struct ethtool_link_ksettings *cmd) 482 { 483 if (!netif_running(dev)) 484 return -EINVAL; 485 486 if (!dev->phydev) 487 return -ENODEV; 488 489 phy_ethtool_ksettings_get(dev->phydev, cmd); 490 491 return 0; 492 } 493 494 static int bcmgenet_set_link_ksettings(struct net_device *dev, 495 const struct ethtool_link_ksettings *cmd) 496 { 497 if (!netif_running(dev)) 498 return -EINVAL; 499 500 if (!dev->phydev) 501 return -ENODEV; 502 503 return phy_ethtool_ksettings_set(dev->phydev, cmd); 504 } 505 506 static int bcmgenet_set_features(struct net_device *dev, 507 netdev_features_t features) 508 { 509 struct bcmgenet_priv *priv = netdev_priv(dev); 510 u32 reg; 511 int ret; 512 513 ret = clk_prepare_enable(priv->clk); 514 if (ret) 515 return ret; 516 517 /* Make sure we reflect the value of CRC_CMD_FWD */ 518 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 519 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 520 521 clk_disable_unprepare(priv->clk); 522 523 return ret; 524 } 525 526 static u32 bcmgenet_get_msglevel(struct net_device *dev) 527 { 528 struct bcmgenet_priv *priv = netdev_priv(dev); 529 530 return priv->msg_enable; 531 } 532 533 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 534 { 535 struct bcmgenet_priv *priv = netdev_priv(dev); 536 537 priv->msg_enable = level; 538 } 539 540 static int bcmgenet_get_coalesce(struct net_device *dev, 541 struct ethtool_coalesce *ec) 542 { 543 struct bcmgenet_priv *priv = netdev_priv(dev); 544 struct bcmgenet_rx_ring *ring; 545 unsigned int i; 546 547 ec->tx_max_coalesced_frames = 548 bcmgenet_tdma_ring_readl(priv, DESC_INDEX, 549 DMA_MBUF_DONE_THRESH); 550 ec->rx_max_coalesced_frames = 551 bcmgenet_rdma_ring_readl(priv, DESC_INDEX, 552 DMA_MBUF_DONE_THRESH); 553 ec->rx_coalesce_usecs = 554 bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000; 555 556 for (i = 0; i < priv->hw_params->rx_queues; i++) { 557 ring = &priv->rx_rings[i]; 558 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 559 } 560 ring = &priv->rx_rings[DESC_INDEX]; 561 ec->use_adaptive_rx_coalesce |= ring->dim.use_dim; 562 563 return 0; 564 } 565 566 static void bcmgenet_set_rx_coalesce(struct bcmgenet_rx_ring *ring, 567 u32 usecs, u32 pkts) 568 { 569 struct bcmgenet_priv *priv = ring->priv; 570 unsigned int i = ring->index; 571 u32 reg; 572 573 bcmgenet_rdma_ring_writel(priv, i, pkts, DMA_MBUF_DONE_THRESH); 574 575 reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i); 576 reg &= ~DMA_TIMEOUT_MASK; 577 reg |= DIV_ROUND_UP(usecs * 1000, 8192); 578 bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i); 579 } 580 581 static void bcmgenet_set_ring_rx_coalesce(struct bcmgenet_rx_ring *ring, 582 struct ethtool_coalesce *ec) 583 { 584 struct dim_cq_moder moder; 585 u32 usecs, pkts; 586 587 ring->rx_coalesce_usecs = ec->rx_coalesce_usecs; 588 ring->rx_max_coalesced_frames = ec->rx_max_coalesced_frames; 589 usecs = ring->rx_coalesce_usecs; 590 pkts = ring->rx_max_coalesced_frames; 591 592 if (ec->use_adaptive_rx_coalesce && !ring->dim.use_dim) { 593 moder = net_dim_get_def_rx_moderation(ring->dim.dim.mode); 594 usecs = moder.usec; 595 pkts = moder.pkts; 596 } 597 598 ring->dim.use_dim = ec->use_adaptive_rx_coalesce; 599 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 600 } 601 602 static int bcmgenet_set_coalesce(struct net_device *dev, 603 struct ethtool_coalesce *ec) 604 { 605 struct bcmgenet_priv *priv = netdev_priv(dev); 606 unsigned int i; 607 608 /* Base system clock is 125Mhz, DMA timeout is this reference clock 609 * divided by 1024, which yields roughly 8.192us, our maximum value 610 * has to fit in the DMA_TIMEOUT_MASK (16 bits) 611 */ 612 if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 613 ec->tx_max_coalesced_frames == 0 || 614 ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK || 615 ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1) 616 return -EINVAL; 617 618 if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0) 619 return -EINVAL; 620 621 /* GENET TDMA hardware does not support a configurable timeout, but will 622 * always generate an interrupt either after MBDONE packets have been 623 * transmitted, or when the ring is empty. 624 */ 625 626 /* Program all TX queues with the same values, as there is no 627 * ethtool knob to do coalescing on a per-queue basis 628 */ 629 for (i = 0; i < priv->hw_params->tx_queues; i++) 630 bcmgenet_tdma_ring_writel(priv, i, 631 ec->tx_max_coalesced_frames, 632 DMA_MBUF_DONE_THRESH); 633 bcmgenet_tdma_ring_writel(priv, DESC_INDEX, 634 ec->tx_max_coalesced_frames, 635 DMA_MBUF_DONE_THRESH); 636 637 for (i = 0; i < priv->hw_params->rx_queues; i++) 638 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[i], ec); 639 bcmgenet_set_ring_rx_coalesce(&priv->rx_rings[DESC_INDEX], ec); 640 641 return 0; 642 } 643 644 /* standard ethtool support functions. */ 645 enum bcmgenet_stat_type { 646 BCMGENET_STAT_NETDEV = -1, 647 BCMGENET_STAT_MIB_RX, 648 BCMGENET_STAT_MIB_TX, 649 BCMGENET_STAT_RUNT, 650 BCMGENET_STAT_MISC, 651 BCMGENET_STAT_SOFT, 652 }; 653 654 struct bcmgenet_stats { 655 char stat_string[ETH_GSTRING_LEN]; 656 int stat_sizeof; 657 int stat_offset; 658 enum bcmgenet_stat_type type; 659 /* reg offset from UMAC base for misc counters */ 660 u16 reg_offset; 661 }; 662 663 #define STAT_NETDEV(m) { \ 664 .stat_string = __stringify(m), \ 665 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 666 .stat_offset = offsetof(struct net_device_stats, m), \ 667 .type = BCMGENET_STAT_NETDEV, \ 668 } 669 670 #define STAT_GENET_MIB(str, m, _type) { \ 671 .stat_string = str, \ 672 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 673 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 674 .type = _type, \ 675 } 676 677 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 678 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 679 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 680 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT) 681 682 #define STAT_GENET_MISC(str, m, offset) { \ 683 .stat_string = str, \ 684 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 685 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 686 .type = BCMGENET_STAT_MISC, \ 687 .reg_offset = offset, \ 688 } 689 690 #define STAT_GENET_Q(num) \ 691 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_packets", \ 692 tx_rings[num].packets), \ 693 STAT_GENET_SOFT_MIB("txq" __stringify(num) "_bytes", \ 694 tx_rings[num].bytes), \ 695 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_bytes", \ 696 rx_rings[num].bytes), \ 697 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_packets", \ 698 rx_rings[num].packets), \ 699 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_errors", \ 700 rx_rings[num].errors), \ 701 STAT_GENET_SOFT_MIB("rxq" __stringify(num) "_dropped", \ 702 rx_rings[num].dropped) 703 704 /* There is a 0xC gap between the end of RX and beginning of TX stats and then 705 * between the end of TX stats and the beginning of the RX RUNT 706 */ 707 #define BCMGENET_STAT_OFFSET 0xc 708 709 /* Hardware counters must be kept in sync because the order/offset 710 * is important here (order in structure declaration = order in hardware) 711 */ 712 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 713 /* general stats */ 714 STAT_NETDEV(rx_packets), 715 STAT_NETDEV(tx_packets), 716 STAT_NETDEV(rx_bytes), 717 STAT_NETDEV(tx_bytes), 718 STAT_NETDEV(rx_errors), 719 STAT_NETDEV(tx_errors), 720 STAT_NETDEV(rx_dropped), 721 STAT_NETDEV(tx_dropped), 722 STAT_NETDEV(multicast), 723 /* UniMAC RSV counters */ 724 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 725 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 726 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 727 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 728 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 729 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 730 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 731 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 732 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 733 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 734 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 735 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 736 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 737 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 738 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 739 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 740 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 741 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 742 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 743 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 744 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 745 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 746 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 747 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 748 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 749 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 750 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 751 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 752 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 753 /* UniMAC TSV counters */ 754 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 755 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 756 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 757 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 758 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 759 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 760 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 761 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 762 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 763 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 764 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 765 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 766 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 767 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 768 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 769 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 770 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 771 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 772 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 773 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 774 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 775 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 776 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 777 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 778 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 779 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 780 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 781 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 782 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 783 /* UniMAC RUNT counters */ 784 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 785 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 786 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 787 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 788 /* Misc UniMAC counters */ 789 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 790 UMAC_RBUF_OVFL_CNT_V1), 791 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, 792 UMAC_RBUF_ERR_CNT_V1), 793 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 794 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), 795 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed), 796 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed), 797 STAT_GENET_SOFT_MIB("tx_realloc_tsb", mib.tx_realloc_tsb), 798 STAT_GENET_SOFT_MIB("tx_realloc_tsb_failed", 799 mib.tx_realloc_tsb_failed), 800 /* Per TX queues */ 801 STAT_GENET_Q(0), 802 STAT_GENET_Q(1), 803 STAT_GENET_Q(2), 804 STAT_GENET_Q(3), 805 STAT_GENET_Q(16), 806 }; 807 808 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 809 810 static void bcmgenet_get_drvinfo(struct net_device *dev, 811 struct ethtool_drvinfo *info) 812 { 813 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 814 } 815 816 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 817 { 818 switch (string_set) { 819 case ETH_SS_STATS: 820 return BCMGENET_STATS_LEN; 821 default: 822 return -EOPNOTSUPP; 823 } 824 } 825 826 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 827 u8 *data) 828 { 829 int i; 830 831 switch (stringset) { 832 case ETH_SS_STATS: 833 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 834 memcpy(data + i * ETH_GSTRING_LEN, 835 bcmgenet_gstrings_stats[i].stat_string, 836 ETH_GSTRING_LEN); 837 } 838 break; 839 } 840 } 841 842 static u32 bcmgenet_update_stat_misc(struct bcmgenet_priv *priv, u16 offset) 843 { 844 u16 new_offset; 845 u32 val; 846 847 switch (offset) { 848 case UMAC_RBUF_OVFL_CNT_V1: 849 if (GENET_IS_V2(priv)) 850 new_offset = RBUF_OVFL_CNT_V2; 851 else 852 new_offset = RBUF_OVFL_CNT_V3PLUS; 853 854 val = bcmgenet_rbuf_readl(priv, new_offset); 855 /* clear if overflowed */ 856 if (val == ~0) 857 bcmgenet_rbuf_writel(priv, 0, new_offset); 858 break; 859 case UMAC_RBUF_ERR_CNT_V1: 860 if (GENET_IS_V2(priv)) 861 new_offset = RBUF_ERR_CNT_V2; 862 else 863 new_offset = RBUF_ERR_CNT_V3PLUS; 864 865 val = bcmgenet_rbuf_readl(priv, new_offset); 866 /* clear if overflowed */ 867 if (val == ~0) 868 bcmgenet_rbuf_writel(priv, 0, new_offset); 869 break; 870 default: 871 val = bcmgenet_umac_readl(priv, offset); 872 /* clear if overflowed */ 873 if (val == ~0) 874 bcmgenet_umac_writel(priv, 0, offset); 875 break; 876 } 877 878 return val; 879 } 880 881 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 882 { 883 int i, j = 0; 884 885 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 886 const struct bcmgenet_stats *s; 887 u8 offset = 0; 888 u32 val = 0; 889 char *p; 890 891 s = &bcmgenet_gstrings_stats[i]; 892 switch (s->type) { 893 case BCMGENET_STAT_NETDEV: 894 case BCMGENET_STAT_SOFT: 895 continue; 896 case BCMGENET_STAT_RUNT: 897 offset += BCMGENET_STAT_OFFSET; 898 /* fall through */ 899 case BCMGENET_STAT_MIB_TX: 900 offset += BCMGENET_STAT_OFFSET; 901 /* fall through */ 902 case BCMGENET_STAT_MIB_RX: 903 val = bcmgenet_umac_readl(priv, 904 UMAC_MIB_START + j + offset); 905 offset = 0; /* Reset Offset */ 906 break; 907 case BCMGENET_STAT_MISC: 908 if (GENET_IS_V1(priv)) { 909 val = bcmgenet_umac_readl(priv, s->reg_offset); 910 /* clear if overflowed */ 911 if (val == ~0) 912 bcmgenet_umac_writel(priv, 0, 913 s->reg_offset); 914 } else { 915 val = bcmgenet_update_stat_misc(priv, 916 s->reg_offset); 917 } 918 break; 919 } 920 921 j += s->stat_sizeof; 922 p = (char *)priv + s->stat_offset; 923 *(u32 *)p = val; 924 } 925 } 926 927 static void bcmgenet_get_ethtool_stats(struct net_device *dev, 928 struct ethtool_stats *stats, 929 u64 *data) 930 { 931 struct bcmgenet_priv *priv = netdev_priv(dev); 932 int i; 933 934 if (netif_running(dev)) 935 bcmgenet_update_mib_counters(priv); 936 937 dev->netdev_ops->ndo_get_stats(dev); 938 939 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 940 const struct bcmgenet_stats *s; 941 char *p; 942 943 s = &bcmgenet_gstrings_stats[i]; 944 if (s->type == BCMGENET_STAT_NETDEV) 945 p = (char *)&dev->stats; 946 else 947 p = (char *)priv; 948 p += s->stat_offset; 949 if (sizeof(unsigned long) != sizeof(u32) && 950 s->stat_sizeof == sizeof(unsigned long)) 951 data[i] = *(unsigned long *)p; 952 else 953 data[i] = *(u32 *)p; 954 } 955 } 956 957 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable) 958 { 959 struct bcmgenet_priv *priv = netdev_priv(dev); 960 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL; 961 u32 reg; 962 963 if (enable && !priv->clk_eee_enabled) { 964 clk_prepare_enable(priv->clk_eee); 965 priv->clk_eee_enabled = true; 966 } 967 968 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL); 969 if (enable) 970 reg |= EEE_EN; 971 else 972 reg &= ~EEE_EN; 973 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL); 974 975 /* Enable EEE and switch to a 27Mhz clock automatically */ 976 reg = bcmgenet_readl(priv->base + off); 977 if (enable) 978 reg |= TBUF_EEE_EN | TBUF_PM_EN; 979 else 980 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN); 981 bcmgenet_writel(reg, priv->base + off); 982 983 /* Do the same for thing for RBUF */ 984 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL); 985 if (enable) 986 reg |= RBUF_EEE_EN | RBUF_PM_EN; 987 else 988 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN); 989 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL); 990 991 if (!enable && priv->clk_eee_enabled) { 992 clk_disable_unprepare(priv->clk_eee); 993 priv->clk_eee_enabled = false; 994 } 995 996 priv->eee.eee_enabled = enable; 997 priv->eee.eee_active = enable; 998 } 999 1000 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e) 1001 { 1002 struct bcmgenet_priv *priv = netdev_priv(dev); 1003 struct ethtool_eee *p = &priv->eee; 1004 1005 if (GENET_IS_V1(priv)) 1006 return -EOPNOTSUPP; 1007 1008 if (!dev->phydev) 1009 return -ENODEV; 1010 1011 e->eee_enabled = p->eee_enabled; 1012 e->eee_active = p->eee_active; 1013 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER); 1014 1015 return phy_ethtool_get_eee(dev->phydev, e); 1016 } 1017 1018 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e) 1019 { 1020 struct bcmgenet_priv *priv = netdev_priv(dev); 1021 struct ethtool_eee *p = &priv->eee; 1022 int ret = 0; 1023 1024 if (GENET_IS_V1(priv)) 1025 return -EOPNOTSUPP; 1026 1027 if (!dev->phydev) 1028 return -ENODEV; 1029 1030 p->eee_enabled = e->eee_enabled; 1031 1032 if (!p->eee_enabled) { 1033 bcmgenet_eee_enable_set(dev, false); 1034 } else { 1035 ret = phy_init_eee(dev->phydev, 0); 1036 if (ret) { 1037 netif_err(priv, hw, dev, "EEE initialization failed\n"); 1038 return ret; 1039 } 1040 1041 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER); 1042 bcmgenet_eee_enable_set(dev, true); 1043 } 1044 1045 return phy_ethtool_set_eee(dev->phydev, e); 1046 } 1047 1048 /* standard ethtool support functions. */ 1049 static const struct ethtool_ops bcmgenet_ethtool_ops = { 1050 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS | 1051 ETHTOOL_COALESCE_MAX_FRAMES | 1052 ETHTOOL_COALESCE_USE_ADAPTIVE_RX, 1053 .begin = bcmgenet_begin, 1054 .complete = bcmgenet_complete, 1055 .get_strings = bcmgenet_get_strings, 1056 .get_sset_count = bcmgenet_get_sset_count, 1057 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 1058 .get_drvinfo = bcmgenet_get_drvinfo, 1059 .get_link = ethtool_op_get_link, 1060 .get_msglevel = bcmgenet_get_msglevel, 1061 .set_msglevel = bcmgenet_set_msglevel, 1062 .get_wol = bcmgenet_get_wol, 1063 .set_wol = bcmgenet_set_wol, 1064 .get_eee = bcmgenet_get_eee, 1065 .set_eee = bcmgenet_set_eee, 1066 .nway_reset = phy_ethtool_nway_reset, 1067 .get_coalesce = bcmgenet_get_coalesce, 1068 .set_coalesce = bcmgenet_set_coalesce, 1069 .get_link_ksettings = bcmgenet_get_link_ksettings, 1070 .set_link_ksettings = bcmgenet_set_link_ksettings, 1071 .get_ts_info = ethtool_op_get_ts_info, 1072 }; 1073 1074 /* Power down the unimac, based on mode. */ 1075 static int bcmgenet_power_down(struct bcmgenet_priv *priv, 1076 enum bcmgenet_power_mode mode) 1077 { 1078 int ret = 0; 1079 u32 reg; 1080 1081 switch (mode) { 1082 case GENET_POWER_CABLE_SENSE: 1083 phy_detach(priv->dev->phydev); 1084 break; 1085 1086 case GENET_POWER_WOL_MAGIC: 1087 ret = bcmgenet_wol_power_down_cfg(priv, mode); 1088 break; 1089 1090 case GENET_POWER_PASSIVE: 1091 /* Power down LED */ 1092 if (priv->hw_params->flags & GENET_HAS_EXT) { 1093 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1094 if (GENET_IS_V5(priv)) 1095 reg |= EXT_PWR_DOWN_PHY_EN | 1096 EXT_PWR_DOWN_PHY_RD | 1097 EXT_PWR_DOWN_PHY_SD | 1098 EXT_PWR_DOWN_PHY_RX | 1099 EXT_PWR_DOWN_PHY_TX | 1100 EXT_IDDQ_GLBL_PWR; 1101 else 1102 reg |= EXT_PWR_DOWN_PHY; 1103 1104 reg |= (EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1105 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1106 1107 bcmgenet_phy_power_set(priv->dev, false); 1108 } 1109 break; 1110 default: 1111 break; 1112 } 1113 1114 return ret; 1115 } 1116 1117 static void bcmgenet_power_up(struct bcmgenet_priv *priv, 1118 enum bcmgenet_power_mode mode) 1119 { 1120 u32 reg; 1121 1122 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 1123 return; 1124 1125 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 1126 1127 switch (mode) { 1128 case GENET_POWER_PASSIVE: 1129 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 1130 if (GENET_IS_V5(priv)) { 1131 reg &= ~(EXT_PWR_DOWN_PHY_EN | 1132 EXT_PWR_DOWN_PHY_RD | 1133 EXT_PWR_DOWN_PHY_SD | 1134 EXT_PWR_DOWN_PHY_RX | 1135 EXT_PWR_DOWN_PHY_TX | 1136 EXT_IDDQ_GLBL_PWR); 1137 reg |= EXT_PHY_RESET; 1138 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1139 mdelay(1); 1140 1141 reg &= ~EXT_PHY_RESET; 1142 } else { 1143 reg &= ~EXT_PWR_DOWN_PHY; 1144 reg |= EXT_PWR_DN_EN_LD; 1145 } 1146 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1147 bcmgenet_phy_power_set(priv->dev, true); 1148 break; 1149 1150 case GENET_POWER_CABLE_SENSE: 1151 /* enable APD */ 1152 if (!GENET_IS_V5(priv)) { 1153 reg |= EXT_PWR_DN_EN_LD; 1154 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 1155 } 1156 break; 1157 case GENET_POWER_WOL_MAGIC: 1158 bcmgenet_wol_power_up_cfg(priv, mode); 1159 return; 1160 default: 1161 break; 1162 } 1163 } 1164 1165 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 1166 struct bcmgenet_tx_ring *ring) 1167 { 1168 struct enet_cb *tx_cb_ptr; 1169 1170 tx_cb_ptr = ring->cbs; 1171 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1172 1173 /* Advancing local write pointer */ 1174 if (ring->write_ptr == ring->end_ptr) 1175 ring->write_ptr = ring->cb_ptr; 1176 else 1177 ring->write_ptr++; 1178 1179 return tx_cb_ptr; 1180 } 1181 1182 static struct enet_cb *bcmgenet_put_txcb(struct bcmgenet_priv *priv, 1183 struct bcmgenet_tx_ring *ring) 1184 { 1185 struct enet_cb *tx_cb_ptr; 1186 1187 tx_cb_ptr = ring->cbs; 1188 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 1189 1190 /* Rewinding local write pointer */ 1191 if (ring->write_ptr == ring->cb_ptr) 1192 ring->write_ptr = ring->end_ptr; 1193 else 1194 ring->write_ptr--; 1195 1196 return tx_cb_ptr; 1197 } 1198 1199 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) 1200 { 1201 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1202 INTRL2_CPU_MASK_SET); 1203 } 1204 1205 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) 1206 { 1207 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE, 1208 INTRL2_CPU_MASK_CLEAR); 1209 } 1210 1211 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring) 1212 { 1213 bcmgenet_intrl2_1_writel(ring->priv, 1214 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1215 INTRL2_CPU_MASK_SET); 1216 } 1217 1218 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) 1219 { 1220 bcmgenet_intrl2_1_writel(ring->priv, 1221 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index), 1222 INTRL2_CPU_MASK_CLEAR); 1223 } 1224 1225 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) 1226 { 1227 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1228 INTRL2_CPU_MASK_SET); 1229 } 1230 1231 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) 1232 { 1233 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE, 1234 INTRL2_CPU_MASK_CLEAR); 1235 } 1236 1237 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring) 1238 { 1239 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1240 INTRL2_CPU_MASK_CLEAR); 1241 } 1242 1243 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring) 1244 { 1245 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index, 1246 INTRL2_CPU_MASK_SET); 1247 } 1248 1249 /* Simple helper to free a transmit control block's resources 1250 * Returns an skb when the last transmit control block associated with the 1251 * skb is freed. The skb should be freed by the caller if necessary. 1252 */ 1253 static struct sk_buff *bcmgenet_free_tx_cb(struct device *dev, 1254 struct enet_cb *cb) 1255 { 1256 struct sk_buff *skb; 1257 1258 skb = cb->skb; 1259 1260 if (skb) { 1261 cb->skb = NULL; 1262 if (cb == GENET_CB(skb)->first_cb) 1263 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1264 dma_unmap_len(cb, dma_len), 1265 DMA_TO_DEVICE); 1266 else 1267 dma_unmap_page(dev, dma_unmap_addr(cb, dma_addr), 1268 dma_unmap_len(cb, dma_len), 1269 DMA_TO_DEVICE); 1270 dma_unmap_addr_set(cb, dma_addr, 0); 1271 1272 if (cb == GENET_CB(skb)->last_cb) 1273 return skb; 1274 1275 } else if (dma_unmap_addr(cb, dma_addr)) { 1276 dma_unmap_page(dev, 1277 dma_unmap_addr(cb, dma_addr), 1278 dma_unmap_len(cb, dma_len), 1279 DMA_TO_DEVICE); 1280 dma_unmap_addr_set(cb, dma_addr, 0); 1281 } 1282 1283 return NULL; 1284 } 1285 1286 /* Simple helper to free a receive control block's resources */ 1287 static struct sk_buff *bcmgenet_free_rx_cb(struct device *dev, 1288 struct enet_cb *cb) 1289 { 1290 struct sk_buff *skb; 1291 1292 skb = cb->skb; 1293 cb->skb = NULL; 1294 1295 if (dma_unmap_addr(cb, dma_addr)) { 1296 dma_unmap_single(dev, dma_unmap_addr(cb, dma_addr), 1297 dma_unmap_len(cb, dma_len), DMA_FROM_DEVICE); 1298 dma_unmap_addr_set(cb, dma_addr, 0); 1299 } 1300 1301 return skb; 1302 } 1303 1304 /* Unlocked version of the reclaim routine */ 1305 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev, 1306 struct bcmgenet_tx_ring *ring) 1307 { 1308 struct bcmgenet_priv *priv = netdev_priv(dev); 1309 unsigned int txbds_processed = 0; 1310 unsigned int bytes_compl = 0; 1311 unsigned int pkts_compl = 0; 1312 unsigned int txbds_ready; 1313 unsigned int c_index; 1314 struct sk_buff *skb; 1315 1316 /* Clear status before servicing to reduce spurious interrupts */ 1317 if (ring->index == DESC_INDEX) 1318 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_TXDMA_DONE, 1319 INTRL2_CPU_CLEAR); 1320 else 1321 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 1322 INTRL2_CPU_CLEAR); 1323 1324 /* Compute how many buffers are transmitted since last xmit call */ 1325 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX) 1326 & DMA_C_INDEX_MASK; 1327 txbds_ready = (c_index - ring->c_index) & DMA_C_INDEX_MASK; 1328 1329 netif_dbg(priv, tx_done, dev, 1330 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", 1331 __func__, ring->index, ring->c_index, c_index, txbds_ready); 1332 1333 /* Reclaim transmitted buffers */ 1334 while (txbds_processed < txbds_ready) { 1335 skb = bcmgenet_free_tx_cb(&priv->pdev->dev, 1336 &priv->tx_cbs[ring->clean_ptr]); 1337 if (skb) { 1338 pkts_compl++; 1339 bytes_compl += GENET_CB(skb)->bytes_sent; 1340 dev_consume_skb_any(skb); 1341 } 1342 1343 txbds_processed++; 1344 if (likely(ring->clean_ptr < ring->end_ptr)) 1345 ring->clean_ptr++; 1346 else 1347 ring->clean_ptr = ring->cb_ptr; 1348 } 1349 1350 ring->free_bds += txbds_processed; 1351 ring->c_index = c_index; 1352 1353 ring->packets += pkts_compl; 1354 ring->bytes += bytes_compl; 1355 1356 netdev_tx_completed_queue(netdev_get_tx_queue(dev, ring->queue), 1357 pkts_compl, bytes_compl); 1358 1359 return txbds_processed; 1360 } 1361 1362 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev, 1363 struct bcmgenet_tx_ring *ring) 1364 { 1365 unsigned int released; 1366 1367 spin_lock_bh(&ring->lock); 1368 released = __bcmgenet_tx_reclaim(dev, ring); 1369 spin_unlock_bh(&ring->lock); 1370 1371 return released; 1372 } 1373 1374 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget) 1375 { 1376 struct bcmgenet_tx_ring *ring = 1377 container_of(napi, struct bcmgenet_tx_ring, napi); 1378 unsigned int work_done = 0; 1379 struct netdev_queue *txq; 1380 1381 spin_lock(&ring->lock); 1382 work_done = __bcmgenet_tx_reclaim(ring->priv->dev, ring); 1383 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) { 1384 txq = netdev_get_tx_queue(ring->priv->dev, ring->queue); 1385 netif_tx_wake_queue(txq); 1386 } 1387 spin_unlock(&ring->lock); 1388 1389 if (work_done == 0) { 1390 napi_complete(napi); 1391 ring->int_enable(ring); 1392 1393 return 0; 1394 } 1395 1396 return budget; 1397 } 1398 1399 static void bcmgenet_tx_reclaim_all(struct net_device *dev) 1400 { 1401 struct bcmgenet_priv *priv = netdev_priv(dev); 1402 int i; 1403 1404 if (netif_is_multiqueue(dev)) { 1405 for (i = 0; i < priv->hw_params->tx_queues; i++) 1406 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 1407 } 1408 1409 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 1410 } 1411 1412 /* Reallocate the SKB to put enough headroom in front of it and insert 1413 * the transmit checksum offsets in the descriptors 1414 */ 1415 static struct sk_buff *bcmgenet_add_tsb(struct net_device *dev, 1416 struct sk_buff *skb) 1417 { 1418 struct bcmgenet_priv *priv = netdev_priv(dev); 1419 struct status_64 *status = NULL; 1420 struct sk_buff *new_skb; 1421 u16 offset; 1422 u8 ip_proto; 1423 __be16 ip_ver; 1424 u32 tx_csum_info; 1425 1426 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1427 /* If 64 byte status block enabled, must make sure skb has 1428 * enough headroom for us to insert 64B status block. 1429 */ 1430 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1431 if (!new_skb) { 1432 dev_kfree_skb_any(skb); 1433 priv->mib.tx_realloc_tsb_failed++; 1434 dev->stats.tx_dropped++; 1435 return NULL; 1436 } 1437 dev_consume_skb_any(skb); 1438 skb = new_skb; 1439 priv->mib.tx_realloc_tsb++; 1440 } 1441 1442 skb_push(skb, sizeof(*status)); 1443 status = (struct status_64 *)skb->data; 1444 1445 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1446 ip_ver = skb->protocol; 1447 switch (ip_ver) { 1448 case htons(ETH_P_IP): 1449 ip_proto = ip_hdr(skb)->protocol; 1450 break; 1451 case htons(ETH_P_IPV6): 1452 ip_proto = ipv6_hdr(skb)->nexthdr; 1453 break; 1454 default: 1455 /* don't use UDP flag */ 1456 ip_proto = 0; 1457 break; 1458 } 1459 1460 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1461 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1462 (offset + skb->csum_offset) | 1463 STATUS_TX_CSUM_LV; 1464 1465 /* Set the special UDP flag for UDP */ 1466 if (ip_proto == IPPROTO_UDP) 1467 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1468 1469 status->tx_csum_info = tx_csum_info; 1470 } 1471 1472 return skb; 1473 } 1474 1475 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1476 { 1477 struct bcmgenet_priv *priv = netdev_priv(dev); 1478 struct device *kdev = &priv->pdev->dev; 1479 struct bcmgenet_tx_ring *ring = NULL; 1480 struct enet_cb *tx_cb_ptr; 1481 struct netdev_queue *txq; 1482 int nr_frags, index; 1483 dma_addr_t mapping; 1484 unsigned int size; 1485 skb_frag_t *frag; 1486 u32 len_stat; 1487 int ret; 1488 int i; 1489 1490 index = skb_get_queue_mapping(skb); 1491 /* Mapping strategy: 1492 * queue_mapping = 0, unclassified, packet xmited through ring16 1493 * queue_mapping = 1, goes to ring 0. (highest priority queue 1494 * queue_mapping = 2, goes to ring 1. 1495 * queue_mapping = 3, goes to ring 2. 1496 * queue_mapping = 4, goes to ring 3. 1497 */ 1498 if (index == 0) 1499 index = DESC_INDEX; 1500 else 1501 index -= 1; 1502 1503 ring = &priv->tx_rings[index]; 1504 txq = netdev_get_tx_queue(dev, ring->queue); 1505 1506 nr_frags = skb_shinfo(skb)->nr_frags; 1507 1508 spin_lock(&ring->lock); 1509 if (ring->free_bds <= (nr_frags + 1)) { 1510 if (!netif_tx_queue_stopped(txq)) { 1511 netif_tx_stop_queue(txq); 1512 netdev_err(dev, 1513 "%s: tx ring %d full when queue %d awake\n", 1514 __func__, index, ring->queue); 1515 } 1516 ret = NETDEV_TX_BUSY; 1517 goto out; 1518 } 1519 1520 if (skb_padto(skb, ETH_ZLEN)) { 1521 ret = NETDEV_TX_OK; 1522 goto out; 1523 } 1524 1525 /* Retain how many bytes will be sent on the wire, without TSB inserted 1526 * by transmit checksum offload 1527 */ 1528 GENET_CB(skb)->bytes_sent = skb->len; 1529 1530 /* add the Transmit Status Block */ 1531 skb = bcmgenet_add_tsb(dev, skb); 1532 if (!skb) { 1533 ret = NETDEV_TX_OK; 1534 goto out; 1535 } 1536 1537 for (i = 0; i <= nr_frags; i++) { 1538 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1539 1540 BUG_ON(!tx_cb_ptr); 1541 1542 if (!i) { 1543 /* Transmit single SKB or head of fragment list */ 1544 GENET_CB(skb)->first_cb = tx_cb_ptr; 1545 size = skb_headlen(skb); 1546 mapping = dma_map_single(kdev, skb->data, size, 1547 DMA_TO_DEVICE); 1548 } else { 1549 /* xmit fragment */ 1550 frag = &skb_shinfo(skb)->frags[i - 1]; 1551 size = skb_frag_size(frag); 1552 mapping = skb_frag_dma_map(kdev, frag, 0, size, 1553 DMA_TO_DEVICE); 1554 } 1555 1556 ret = dma_mapping_error(kdev, mapping); 1557 if (ret) { 1558 priv->mib.tx_dma_failed++; 1559 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 1560 ret = NETDEV_TX_OK; 1561 goto out_unmap_frags; 1562 } 1563 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1564 dma_unmap_len_set(tx_cb_ptr, dma_len, size); 1565 1566 tx_cb_ptr->skb = skb; 1567 1568 len_stat = (size << DMA_BUFLENGTH_SHIFT) | 1569 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT); 1570 1571 if (!i) { 1572 len_stat |= DMA_TX_APPEND_CRC | DMA_SOP; 1573 if (skb->ip_summed == CHECKSUM_PARTIAL) 1574 len_stat |= DMA_TX_DO_CSUM; 1575 } 1576 if (i == nr_frags) 1577 len_stat |= DMA_EOP; 1578 1579 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, len_stat); 1580 } 1581 1582 GENET_CB(skb)->last_cb = tx_cb_ptr; 1583 skb_tx_timestamp(skb); 1584 1585 /* Decrement total BD count and advance our write pointer */ 1586 ring->free_bds -= nr_frags + 1; 1587 ring->prod_index += nr_frags + 1; 1588 ring->prod_index &= DMA_P_INDEX_MASK; 1589 1590 netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent); 1591 1592 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) 1593 netif_tx_stop_queue(txq); 1594 1595 if (!netdev_xmit_more() || netif_xmit_stopped(txq)) 1596 /* Packets are ready, update producer index */ 1597 bcmgenet_tdma_ring_writel(priv, ring->index, 1598 ring->prod_index, TDMA_PROD_INDEX); 1599 out: 1600 spin_unlock(&ring->lock); 1601 1602 return ret; 1603 1604 out_unmap_frags: 1605 /* Back up for failed control block mapping */ 1606 bcmgenet_put_txcb(priv, ring); 1607 1608 /* Unmap successfully mapped control blocks */ 1609 while (i-- > 0) { 1610 tx_cb_ptr = bcmgenet_put_txcb(priv, ring); 1611 bcmgenet_free_tx_cb(kdev, tx_cb_ptr); 1612 } 1613 1614 dev_kfree_skb(skb); 1615 goto out; 1616 } 1617 1618 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv, 1619 struct enet_cb *cb) 1620 { 1621 struct device *kdev = &priv->pdev->dev; 1622 struct sk_buff *skb; 1623 struct sk_buff *rx_skb; 1624 dma_addr_t mapping; 1625 1626 /* Allocate a new Rx skb */ 1627 skb = __netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT, 1628 GFP_ATOMIC | __GFP_NOWARN); 1629 if (!skb) { 1630 priv->mib.alloc_rx_buff_failed++; 1631 netif_err(priv, rx_err, priv->dev, 1632 "%s: Rx skb allocation failed\n", __func__); 1633 return NULL; 1634 } 1635 1636 /* DMA-map the new Rx skb */ 1637 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len, 1638 DMA_FROM_DEVICE); 1639 if (dma_mapping_error(kdev, mapping)) { 1640 priv->mib.rx_dma_failed++; 1641 dev_kfree_skb_any(skb); 1642 netif_err(priv, rx_err, priv->dev, 1643 "%s: Rx skb DMA mapping failed\n", __func__); 1644 return NULL; 1645 } 1646 1647 /* Grab the current Rx skb from the ring and DMA-unmap it */ 1648 rx_skb = bcmgenet_free_rx_cb(kdev, cb); 1649 1650 /* Put the new Rx skb on the ring */ 1651 cb->skb = skb; 1652 dma_unmap_addr_set(cb, dma_addr, mapping); 1653 dma_unmap_len_set(cb, dma_len, priv->rx_buf_len); 1654 dmadesc_set_addr(priv, cb->bd_addr, mapping); 1655 1656 /* Return the current Rx skb to caller */ 1657 return rx_skb; 1658 } 1659 1660 /* bcmgenet_desc_rx - descriptor based rx process. 1661 * this could be called from bottom half, or from NAPI polling method. 1662 */ 1663 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, 1664 unsigned int budget) 1665 { 1666 struct bcmgenet_priv *priv = ring->priv; 1667 struct net_device *dev = priv->dev; 1668 struct enet_cb *cb; 1669 struct sk_buff *skb; 1670 u32 dma_length_status; 1671 unsigned long dma_flag; 1672 int len; 1673 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1674 unsigned int bytes_processed = 0; 1675 unsigned int p_index, mask; 1676 unsigned int discards; 1677 1678 /* Clear status before servicing to reduce spurious interrupts */ 1679 if (ring->index == DESC_INDEX) { 1680 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_DONE, 1681 INTRL2_CPU_CLEAR); 1682 } else { 1683 mask = 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index); 1684 bcmgenet_intrl2_1_writel(priv, 1685 mask, 1686 INTRL2_CPU_CLEAR); 1687 } 1688 1689 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX); 1690 1691 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) & 1692 DMA_P_INDEX_DISCARD_CNT_MASK; 1693 if (discards > ring->old_discards) { 1694 discards = discards - ring->old_discards; 1695 ring->errors += discards; 1696 ring->old_discards += discards; 1697 1698 /* Clear HW register when we reach 75% of maximum 0xFFFF */ 1699 if (ring->old_discards >= 0xC000) { 1700 ring->old_discards = 0; 1701 bcmgenet_rdma_ring_writel(priv, ring->index, 0, 1702 RDMA_PROD_INDEX); 1703 } 1704 } 1705 1706 p_index &= DMA_P_INDEX_MASK; 1707 rxpkttoprocess = (p_index - ring->c_index) & DMA_C_INDEX_MASK; 1708 1709 netif_dbg(priv, rx_status, dev, 1710 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1711 1712 while ((rxpktprocessed < rxpkttoprocess) && 1713 (rxpktprocessed < budget)) { 1714 struct status_64 *status; 1715 __be16 rx_csum; 1716 1717 cb = &priv->rx_cbs[ring->read_ptr]; 1718 skb = bcmgenet_rx_refill(priv, cb); 1719 1720 if (unlikely(!skb)) { 1721 ring->dropped++; 1722 goto next; 1723 } 1724 1725 status = (struct status_64 *)skb->data; 1726 dma_length_status = status->length_status; 1727 if (dev->features & NETIF_F_RXCSUM) { 1728 rx_csum = (__force __be16)(status->rx_csum & 0xffff); 1729 skb->csum = (__force __wsum)ntohs(rx_csum); 1730 skb->ip_summed = CHECKSUM_COMPLETE; 1731 } 1732 1733 /* DMA flags and length are still valid no matter how 1734 * we got the Receive Status Vector (64B RSB or register) 1735 */ 1736 dma_flag = dma_length_status & 0xffff; 1737 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1738 1739 netif_dbg(priv, rx_status, dev, 1740 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1741 __func__, p_index, ring->c_index, 1742 ring->read_ptr, dma_length_status); 1743 1744 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1745 netif_err(priv, rx_status, dev, 1746 "dropping fragmented packet!\n"); 1747 ring->errors++; 1748 dev_kfree_skb_any(skb); 1749 goto next; 1750 } 1751 1752 /* report errors */ 1753 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1754 DMA_RX_OV | 1755 DMA_RX_NO | 1756 DMA_RX_LG | 1757 DMA_RX_RXER))) { 1758 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1759 (unsigned int)dma_flag); 1760 if (dma_flag & DMA_RX_CRC_ERROR) 1761 dev->stats.rx_crc_errors++; 1762 if (dma_flag & DMA_RX_OV) 1763 dev->stats.rx_over_errors++; 1764 if (dma_flag & DMA_RX_NO) 1765 dev->stats.rx_frame_errors++; 1766 if (dma_flag & DMA_RX_LG) 1767 dev->stats.rx_length_errors++; 1768 dev->stats.rx_errors++; 1769 dev_kfree_skb_any(skb); 1770 goto next; 1771 } /* error packet */ 1772 1773 skb_put(skb, len); 1774 1775 /* remove RSB and hardware 2bytes added for IP alignment */ 1776 skb_pull(skb, 66); 1777 len -= 66; 1778 1779 if (priv->crc_fwd_en) { 1780 skb_trim(skb, len - ETH_FCS_LEN); 1781 len -= ETH_FCS_LEN; 1782 } 1783 1784 bytes_processed += len; 1785 1786 /*Finish setting up the received SKB and send it to the kernel*/ 1787 skb->protocol = eth_type_trans(skb, priv->dev); 1788 ring->packets++; 1789 ring->bytes += len; 1790 if (dma_flag & DMA_RX_MULT) 1791 dev->stats.multicast++; 1792 1793 /* Notify kernel */ 1794 napi_gro_receive(&ring->napi, skb); 1795 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1796 1797 next: 1798 rxpktprocessed++; 1799 if (likely(ring->read_ptr < ring->end_ptr)) 1800 ring->read_ptr++; 1801 else 1802 ring->read_ptr = ring->cb_ptr; 1803 1804 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK; 1805 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX); 1806 } 1807 1808 ring->dim.bytes = bytes_processed; 1809 ring->dim.packets = rxpktprocessed; 1810 1811 return rxpktprocessed; 1812 } 1813 1814 /* Rx NAPI polling method */ 1815 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget) 1816 { 1817 struct bcmgenet_rx_ring *ring = container_of(napi, 1818 struct bcmgenet_rx_ring, napi); 1819 struct dim_sample dim_sample = {}; 1820 unsigned int work_done; 1821 1822 work_done = bcmgenet_desc_rx(ring, budget); 1823 1824 if (work_done < budget) { 1825 napi_complete_done(napi, work_done); 1826 ring->int_enable(ring); 1827 } 1828 1829 if (ring->dim.use_dim) { 1830 dim_update_sample(ring->dim.event_ctr, ring->dim.packets, 1831 ring->dim.bytes, &dim_sample); 1832 net_dim(&ring->dim.dim, dim_sample); 1833 } 1834 1835 return work_done; 1836 } 1837 1838 static void bcmgenet_dim_work(struct work_struct *work) 1839 { 1840 struct dim *dim = container_of(work, struct dim, work); 1841 struct bcmgenet_net_dim *ndim = 1842 container_of(dim, struct bcmgenet_net_dim, dim); 1843 struct bcmgenet_rx_ring *ring = 1844 container_of(ndim, struct bcmgenet_rx_ring, dim); 1845 struct dim_cq_moder cur_profile = 1846 net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1847 1848 bcmgenet_set_rx_coalesce(ring, cur_profile.usec, cur_profile.pkts); 1849 dim->state = DIM_START_MEASURE; 1850 } 1851 1852 /* Assign skb to RX DMA descriptor. */ 1853 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv, 1854 struct bcmgenet_rx_ring *ring) 1855 { 1856 struct enet_cb *cb; 1857 struct sk_buff *skb; 1858 int i; 1859 1860 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 1861 1862 /* loop here for each buffer needing assign */ 1863 for (i = 0; i < ring->size; i++) { 1864 cb = ring->cbs + i; 1865 skb = bcmgenet_rx_refill(priv, cb); 1866 if (skb) 1867 dev_consume_skb_any(skb); 1868 if (!cb->skb) 1869 return -ENOMEM; 1870 } 1871 1872 return 0; 1873 } 1874 1875 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1876 { 1877 struct sk_buff *skb; 1878 struct enet_cb *cb; 1879 int i; 1880 1881 for (i = 0; i < priv->num_rx_bds; i++) { 1882 cb = &priv->rx_cbs[i]; 1883 1884 skb = bcmgenet_free_rx_cb(&priv->pdev->dev, cb); 1885 if (skb) 1886 dev_consume_skb_any(skb); 1887 } 1888 } 1889 1890 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1891 { 1892 u32 reg; 1893 1894 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1895 if (reg & CMD_SW_RESET) 1896 return; 1897 if (enable) 1898 reg |= mask; 1899 else 1900 reg &= ~mask; 1901 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1902 1903 /* UniMAC stops on a packet boundary, wait for a full-size packet 1904 * to be processed 1905 */ 1906 if (enable == 0) 1907 usleep_range(1000, 2000); 1908 } 1909 1910 static void reset_umac(struct bcmgenet_priv *priv) 1911 { 1912 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1913 bcmgenet_rbuf_ctrl_set(priv, 0); 1914 udelay(10); 1915 1916 /* issue soft reset and disable MAC while updating its registers */ 1917 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 1918 udelay(2); 1919 } 1920 1921 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1922 { 1923 /* Mask all interrupts.*/ 1924 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1925 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1926 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1927 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1928 } 1929 1930 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv) 1931 { 1932 u32 int0_enable = 0; 1933 1934 /* Monitor cable plug/unplugged event for internal PHY, external PHY 1935 * and MoCA PHY 1936 */ 1937 if (priv->internal_phy) { 1938 int0_enable |= UMAC_IRQ_LINK_EVENT; 1939 if (GENET_IS_V1(priv) || GENET_IS_V2(priv) || GENET_IS_V3(priv)) 1940 int0_enable |= UMAC_IRQ_PHY_DET_R; 1941 } else if (priv->ext_phy) { 1942 int0_enable |= UMAC_IRQ_LINK_EVENT; 1943 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1944 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET) 1945 int0_enable |= UMAC_IRQ_LINK_EVENT; 1946 } 1947 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 1948 } 1949 1950 static void init_umac(struct bcmgenet_priv *priv) 1951 { 1952 struct device *kdev = &priv->pdev->dev; 1953 u32 reg; 1954 u32 int0_enable = 0; 1955 1956 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 1957 1958 reset_umac(priv); 1959 1960 /* clear tx/rx counter */ 1961 bcmgenet_umac_writel(priv, 1962 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 1963 UMAC_MIB_CTRL); 1964 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 1965 1966 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1967 1968 /* init tx registers, enable TSB */ 1969 reg = bcmgenet_tbuf_ctrl_get(priv); 1970 reg |= TBUF_64B_EN; 1971 bcmgenet_tbuf_ctrl_set(priv, reg); 1972 1973 /* init rx registers, enable ip header optimization and RSB */ 1974 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 1975 reg |= RBUF_ALIGN_2B | RBUF_64B_EN; 1976 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 1977 1978 /* enable rx checksumming */ 1979 reg = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 1980 reg |= RBUF_RXCHK_EN | RBUF_L3_PARSE_DIS; 1981 /* If UniMAC forwards CRC, we need to skip over it to get 1982 * a valid CHK bit to be set in the per-packet status word 1983 */ 1984 if (priv->crc_fwd_en) 1985 reg |= RBUF_SKIP_FCS; 1986 else 1987 reg &= ~RBUF_SKIP_FCS; 1988 bcmgenet_rbuf_writel(priv, reg, RBUF_CHK_CTRL); 1989 1990 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 1991 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 1992 1993 bcmgenet_intr_disable(priv); 1994 1995 /* Configure backpressure vectors for MoCA */ 1996 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1997 reg = bcmgenet_bp_mc_get(priv); 1998 reg |= BIT(priv->hw_params->bp_in_en_shift); 1999 2000 /* bp_mask: back pressure mask */ 2001 if (netif_is_multiqueue(priv->dev)) 2002 reg |= priv->hw_params->bp_in_mask; 2003 else 2004 reg &= ~priv->hw_params->bp_in_mask; 2005 bcmgenet_bp_mc_set(priv, reg); 2006 } 2007 2008 /* Enable MDIO interrupts on GENET v3+ */ 2009 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 2010 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 2011 2012 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 2013 2014 dev_dbg(kdev, "done init umac\n"); 2015 } 2016 2017 static void bcmgenet_init_dim(struct bcmgenet_rx_ring *ring, 2018 void (*cb)(struct work_struct *work)) 2019 { 2020 struct bcmgenet_net_dim *dim = &ring->dim; 2021 2022 INIT_WORK(&dim->dim.work, cb); 2023 dim->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 2024 dim->event_ctr = 0; 2025 dim->packets = 0; 2026 dim->bytes = 0; 2027 } 2028 2029 static void bcmgenet_init_rx_coalesce(struct bcmgenet_rx_ring *ring) 2030 { 2031 struct bcmgenet_net_dim *dim = &ring->dim; 2032 struct dim_cq_moder moder; 2033 u32 usecs, pkts; 2034 2035 usecs = ring->rx_coalesce_usecs; 2036 pkts = ring->rx_max_coalesced_frames; 2037 2038 /* If DIM was enabled, re-apply default parameters */ 2039 if (dim->use_dim) { 2040 moder = net_dim_get_def_rx_moderation(dim->dim.mode); 2041 usecs = moder.usec; 2042 pkts = moder.pkts; 2043 } 2044 2045 bcmgenet_set_rx_coalesce(ring, usecs, pkts); 2046 } 2047 2048 /* Initialize a Tx ring along with corresponding hardware registers */ 2049 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 2050 unsigned int index, unsigned int size, 2051 unsigned int start_ptr, unsigned int end_ptr) 2052 { 2053 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 2054 u32 words_per_bd = WORDS_PER_BD(priv); 2055 u32 flow_period_val = 0; 2056 2057 spin_lock_init(&ring->lock); 2058 ring->priv = priv; 2059 ring->index = index; 2060 if (index == DESC_INDEX) { 2061 ring->queue = 0; 2062 ring->int_enable = bcmgenet_tx_ring16_int_enable; 2063 ring->int_disable = bcmgenet_tx_ring16_int_disable; 2064 } else { 2065 ring->queue = index + 1; 2066 ring->int_enable = bcmgenet_tx_ring_int_enable; 2067 ring->int_disable = bcmgenet_tx_ring_int_disable; 2068 } 2069 ring->cbs = priv->tx_cbs + start_ptr; 2070 ring->size = size; 2071 ring->clean_ptr = start_ptr; 2072 ring->c_index = 0; 2073 ring->free_bds = size; 2074 ring->write_ptr = start_ptr; 2075 ring->cb_ptr = start_ptr; 2076 ring->end_ptr = end_ptr - 1; 2077 ring->prod_index = 0; 2078 2079 /* Set flow period for ring != 16 */ 2080 if (index != DESC_INDEX) 2081 flow_period_val = ENET_MAX_MTU_SIZE << 16; 2082 2083 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 2084 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 2085 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 2086 /* Disable rate control for now */ 2087 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 2088 TDMA_FLOW_PERIOD); 2089 bcmgenet_tdma_ring_writel(priv, index, 2090 ((size << DMA_RING_SIZE_SHIFT) | 2091 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2092 2093 /* Set start and end address, read and write pointers */ 2094 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2095 DMA_START_ADDR); 2096 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2097 TDMA_READ_PTR); 2098 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd, 2099 TDMA_WRITE_PTR); 2100 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2101 DMA_END_ADDR); 2102 2103 /* Initialize Tx NAPI */ 2104 netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 2105 NAPI_POLL_WEIGHT); 2106 } 2107 2108 /* Initialize a RDMA ring */ 2109 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 2110 unsigned int index, unsigned int size, 2111 unsigned int start_ptr, unsigned int end_ptr) 2112 { 2113 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index]; 2114 u32 words_per_bd = WORDS_PER_BD(priv); 2115 int ret; 2116 2117 ring->priv = priv; 2118 ring->index = index; 2119 if (index == DESC_INDEX) { 2120 ring->int_enable = bcmgenet_rx_ring16_int_enable; 2121 ring->int_disable = bcmgenet_rx_ring16_int_disable; 2122 } else { 2123 ring->int_enable = bcmgenet_rx_ring_int_enable; 2124 ring->int_disable = bcmgenet_rx_ring_int_disable; 2125 } 2126 ring->cbs = priv->rx_cbs + start_ptr; 2127 ring->size = size; 2128 ring->c_index = 0; 2129 ring->read_ptr = start_ptr; 2130 ring->cb_ptr = start_ptr; 2131 ring->end_ptr = end_ptr - 1; 2132 2133 ret = bcmgenet_alloc_rx_buffers(priv, ring); 2134 if (ret) 2135 return ret; 2136 2137 bcmgenet_init_dim(ring, bcmgenet_dim_work); 2138 bcmgenet_init_rx_coalesce(ring); 2139 2140 /* Initialize Rx NAPI */ 2141 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 2142 NAPI_POLL_WEIGHT); 2143 2144 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 2145 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 2146 bcmgenet_rdma_ring_writel(priv, index, 2147 ((size << DMA_RING_SIZE_SHIFT) | 2148 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 2149 bcmgenet_rdma_ring_writel(priv, index, 2150 (DMA_FC_THRESH_LO << 2151 DMA_XOFF_THRESHOLD_SHIFT) | 2152 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 2153 2154 /* Set start and end address, read and write pointers */ 2155 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2156 DMA_START_ADDR); 2157 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2158 RDMA_READ_PTR); 2159 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd, 2160 RDMA_WRITE_PTR); 2161 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 2162 DMA_END_ADDR); 2163 2164 return ret; 2165 } 2166 2167 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv) 2168 { 2169 unsigned int i; 2170 struct bcmgenet_tx_ring *ring; 2171 2172 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2173 ring = &priv->tx_rings[i]; 2174 napi_enable(&ring->napi); 2175 ring->int_enable(ring); 2176 } 2177 2178 ring = &priv->tx_rings[DESC_INDEX]; 2179 napi_enable(&ring->napi); 2180 ring->int_enable(ring); 2181 } 2182 2183 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv) 2184 { 2185 unsigned int i; 2186 struct bcmgenet_tx_ring *ring; 2187 2188 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2189 ring = &priv->tx_rings[i]; 2190 napi_disable(&ring->napi); 2191 } 2192 2193 ring = &priv->tx_rings[DESC_INDEX]; 2194 napi_disable(&ring->napi); 2195 } 2196 2197 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv) 2198 { 2199 unsigned int i; 2200 struct bcmgenet_tx_ring *ring; 2201 2202 for (i = 0; i < priv->hw_params->tx_queues; ++i) { 2203 ring = &priv->tx_rings[i]; 2204 netif_napi_del(&ring->napi); 2205 } 2206 2207 ring = &priv->tx_rings[DESC_INDEX]; 2208 netif_napi_del(&ring->napi); 2209 } 2210 2211 /* Initialize Tx queues 2212 * 2213 * Queues 0-3 are priority-based, each one has 32 descriptors, 2214 * with queue 0 being the highest priority queue. 2215 * 2216 * Queue 16 is the default Tx queue with 2217 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors. 2218 * 2219 * The transmit control block pool is then partitioned as follows: 2220 * - Tx queue 0 uses tx_cbs[0..31] 2221 * - Tx queue 1 uses tx_cbs[32..63] 2222 * - Tx queue 2 uses tx_cbs[64..95] 2223 * - Tx queue 3 uses tx_cbs[96..127] 2224 * - Tx queue 16 uses tx_cbs[128..255] 2225 */ 2226 static void bcmgenet_init_tx_queues(struct net_device *dev) 2227 { 2228 struct bcmgenet_priv *priv = netdev_priv(dev); 2229 u32 i, dma_enable; 2230 u32 dma_ctrl, ring_cfg; 2231 u32 dma_priority[3] = {0, 0, 0}; 2232 2233 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 2234 dma_enable = dma_ctrl & DMA_EN; 2235 dma_ctrl &= ~DMA_EN; 2236 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2237 2238 dma_ctrl = 0; 2239 ring_cfg = 0; 2240 2241 /* Enable strict priority arbiter mode */ 2242 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 2243 2244 /* Initialize Tx priority queues */ 2245 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2246 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q, 2247 i * priv->hw_params->tx_bds_per_q, 2248 (i + 1) * priv->hw_params->tx_bds_per_q); 2249 ring_cfg |= (1 << i); 2250 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2251 dma_priority[DMA_PRIO_REG_INDEX(i)] |= 2252 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i)); 2253 } 2254 2255 /* Initialize Tx default queue 16 */ 2256 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT, 2257 priv->hw_params->tx_queues * 2258 priv->hw_params->tx_bds_per_q, 2259 TOTAL_DESC); 2260 ring_cfg |= (1 << DESC_INDEX); 2261 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2262 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |= 2263 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 2264 DMA_PRIO_REG_SHIFT(DESC_INDEX)); 2265 2266 /* Set Tx queue priorities */ 2267 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0); 2268 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1); 2269 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2); 2270 2271 /* Enable Tx queues */ 2272 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG); 2273 2274 /* Enable Tx DMA */ 2275 if (dma_enable) 2276 dma_ctrl |= DMA_EN; 2277 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 2278 } 2279 2280 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv) 2281 { 2282 unsigned int i; 2283 struct bcmgenet_rx_ring *ring; 2284 2285 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2286 ring = &priv->rx_rings[i]; 2287 napi_enable(&ring->napi); 2288 ring->int_enable(ring); 2289 } 2290 2291 ring = &priv->rx_rings[DESC_INDEX]; 2292 napi_enable(&ring->napi); 2293 ring->int_enable(ring); 2294 } 2295 2296 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv) 2297 { 2298 unsigned int i; 2299 struct bcmgenet_rx_ring *ring; 2300 2301 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2302 ring = &priv->rx_rings[i]; 2303 napi_disable(&ring->napi); 2304 cancel_work_sync(&ring->dim.dim.work); 2305 } 2306 2307 ring = &priv->rx_rings[DESC_INDEX]; 2308 napi_disable(&ring->napi); 2309 cancel_work_sync(&ring->dim.dim.work); 2310 } 2311 2312 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv) 2313 { 2314 unsigned int i; 2315 struct bcmgenet_rx_ring *ring; 2316 2317 for (i = 0; i < priv->hw_params->rx_queues; ++i) { 2318 ring = &priv->rx_rings[i]; 2319 netif_napi_del(&ring->napi); 2320 } 2321 2322 ring = &priv->rx_rings[DESC_INDEX]; 2323 netif_napi_del(&ring->napi); 2324 } 2325 2326 /* Initialize Rx queues 2327 * 2328 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be 2329 * used to direct traffic to these queues. 2330 * 2331 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors. 2332 */ 2333 static int bcmgenet_init_rx_queues(struct net_device *dev) 2334 { 2335 struct bcmgenet_priv *priv = netdev_priv(dev); 2336 u32 i; 2337 u32 dma_enable; 2338 u32 dma_ctrl; 2339 u32 ring_cfg; 2340 int ret; 2341 2342 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL); 2343 dma_enable = dma_ctrl & DMA_EN; 2344 dma_ctrl &= ~DMA_EN; 2345 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2346 2347 dma_ctrl = 0; 2348 ring_cfg = 0; 2349 2350 /* Initialize Rx priority queues */ 2351 for (i = 0; i < priv->hw_params->rx_queues; i++) { 2352 ret = bcmgenet_init_rx_ring(priv, i, 2353 priv->hw_params->rx_bds_per_q, 2354 i * priv->hw_params->rx_bds_per_q, 2355 (i + 1) * 2356 priv->hw_params->rx_bds_per_q); 2357 if (ret) 2358 return ret; 2359 2360 ring_cfg |= (1 << i); 2361 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2362 } 2363 2364 /* Initialize Rx default queue 16 */ 2365 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT, 2366 priv->hw_params->rx_queues * 2367 priv->hw_params->rx_bds_per_q, 2368 TOTAL_DESC); 2369 if (ret) 2370 return ret; 2371 2372 ring_cfg |= (1 << DESC_INDEX); 2373 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT)); 2374 2375 /* Enable rings */ 2376 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG); 2377 2378 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 2379 if (dma_enable) 2380 dma_ctrl |= DMA_EN; 2381 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL); 2382 2383 return 0; 2384 } 2385 2386 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2387 { 2388 int ret = 0; 2389 int timeout = 0; 2390 u32 reg; 2391 u32 dma_ctrl; 2392 int i; 2393 2394 /* Disable TDMA to stop add more frames in TX DMA */ 2395 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2396 reg &= ~DMA_EN; 2397 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2398 2399 /* Check TDMA status register to confirm TDMA is disabled */ 2400 while (timeout++ < DMA_TIMEOUT_VAL) { 2401 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2402 if (reg & DMA_DISABLED) 2403 break; 2404 2405 udelay(1); 2406 } 2407 2408 if (timeout == DMA_TIMEOUT_VAL) { 2409 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2410 ret = -ETIMEDOUT; 2411 } 2412 2413 /* Wait 10ms for packet drain in both tx and rx dma */ 2414 usleep_range(10000, 20000); 2415 2416 /* Disable RDMA */ 2417 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2418 reg &= ~DMA_EN; 2419 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2420 2421 timeout = 0; 2422 /* Check RDMA status register to confirm RDMA is disabled */ 2423 while (timeout++ < DMA_TIMEOUT_VAL) { 2424 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2425 if (reg & DMA_DISABLED) 2426 break; 2427 2428 udelay(1); 2429 } 2430 2431 if (timeout == DMA_TIMEOUT_VAL) { 2432 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2433 ret = -ETIMEDOUT; 2434 } 2435 2436 dma_ctrl = 0; 2437 for (i = 0; i < priv->hw_params->rx_queues; i++) 2438 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2439 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2440 reg &= ~dma_ctrl; 2441 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2442 2443 dma_ctrl = 0; 2444 for (i = 0; i < priv->hw_params->tx_queues; i++) 2445 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT)); 2446 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2447 reg &= ~dma_ctrl; 2448 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2449 2450 return ret; 2451 } 2452 2453 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 2454 { 2455 struct netdev_queue *txq; 2456 int i; 2457 2458 bcmgenet_fini_rx_napi(priv); 2459 bcmgenet_fini_tx_napi(priv); 2460 2461 for (i = 0; i < priv->num_tx_bds; i++) 2462 dev_kfree_skb(bcmgenet_free_tx_cb(&priv->pdev->dev, 2463 priv->tx_cbs + i)); 2464 2465 for (i = 0; i < priv->hw_params->tx_queues; i++) { 2466 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue); 2467 netdev_tx_reset_queue(txq); 2468 } 2469 2470 txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue); 2471 netdev_tx_reset_queue(txq); 2472 2473 bcmgenet_free_rx_buffers(priv); 2474 kfree(priv->rx_cbs); 2475 kfree(priv->tx_cbs); 2476 } 2477 2478 /* init_edma: Initialize DMA control register */ 2479 static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 2480 { 2481 int ret; 2482 unsigned int i; 2483 struct enet_cb *cb; 2484 2485 netif_dbg(priv, hw, priv->dev, "%s\n", __func__); 2486 2487 /* Initialize common Rx ring structures */ 2488 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 2489 priv->num_rx_bds = TOTAL_DESC; 2490 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 2491 GFP_KERNEL); 2492 if (!priv->rx_cbs) 2493 return -ENOMEM; 2494 2495 for (i = 0; i < priv->num_rx_bds; i++) { 2496 cb = priv->rx_cbs + i; 2497 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE; 2498 } 2499 2500 /* Initialize common TX ring structures */ 2501 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 2502 priv->num_tx_bds = TOTAL_DESC; 2503 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 2504 GFP_KERNEL); 2505 if (!priv->tx_cbs) { 2506 kfree(priv->rx_cbs); 2507 return -ENOMEM; 2508 } 2509 2510 for (i = 0; i < priv->num_tx_bds; i++) { 2511 cb = priv->tx_cbs + i; 2512 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE; 2513 } 2514 2515 /* Init rDma */ 2516 bcmgenet_rdma_writel(priv, priv->dma_max_burst_length, 2517 DMA_SCB_BURST_SIZE); 2518 2519 /* Initialize Rx queues */ 2520 ret = bcmgenet_init_rx_queues(priv->dev); 2521 if (ret) { 2522 netdev_err(priv->dev, "failed to initialize Rx queues\n"); 2523 bcmgenet_free_rx_buffers(priv); 2524 kfree(priv->rx_cbs); 2525 kfree(priv->tx_cbs); 2526 return ret; 2527 } 2528 2529 /* Init tDma */ 2530 bcmgenet_tdma_writel(priv, priv->dma_max_burst_length, 2531 DMA_SCB_BURST_SIZE); 2532 2533 /* Initialize Tx queues */ 2534 bcmgenet_init_tx_queues(priv->dev); 2535 2536 return 0; 2537 } 2538 2539 /* Interrupt bottom half */ 2540 static void bcmgenet_irq_task(struct work_struct *work) 2541 { 2542 unsigned int status; 2543 struct bcmgenet_priv *priv = container_of( 2544 work, struct bcmgenet_priv, bcmgenet_irq_work); 2545 2546 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 2547 2548 spin_lock_irq(&priv->lock); 2549 status = priv->irq0_stat; 2550 priv->irq0_stat = 0; 2551 spin_unlock_irq(&priv->lock); 2552 2553 if (status & UMAC_IRQ_PHY_DET_R && 2554 priv->dev->phydev->autoneg != AUTONEG_ENABLE) { 2555 phy_init_hw(priv->dev->phydev); 2556 genphy_config_aneg(priv->dev->phydev); 2557 } 2558 2559 /* Link UP/DOWN event */ 2560 if (status & UMAC_IRQ_LINK_EVENT) 2561 phy_mac_interrupt(priv->dev->phydev); 2562 2563 } 2564 2565 /* bcmgenet_isr1: handle Rx and Tx priority queues */ 2566 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 2567 { 2568 struct bcmgenet_priv *priv = dev_id; 2569 struct bcmgenet_rx_ring *rx_ring; 2570 struct bcmgenet_tx_ring *tx_ring; 2571 unsigned int index, status; 2572 2573 /* Read irq status */ 2574 status = bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 2575 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2576 2577 /* clear interrupts */ 2578 bcmgenet_intrl2_1_writel(priv, status, INTRL2_CPU_CLEAR); 2579 2580 netif_dbg(priv, intr, priv->dev, 2581 "%s: IRQ=0x%x\n", __func__, status); 2582 2583 /* Check Rx priority queue interrupts */ 2584 for (index = 0; index < priv->hw_params->rx_queues; index++) { 2585 if (!(status & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index))) 2586 continue; 2587 2588 rx_ring = &priv->rx_rings[index]; 2589 rx_ring->dim.event_ctr++; 2590 2591 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2592 rx_ring->int_disable(rx_ring); 2593 __napi_schedule_irqoff(&rx_ring->napi); 2594 } 2595 } 2596 2597 /* Check Tx priority queue interrupts */ 2598 for (index = 0; index < priv->hw_params->tx_queues; index++) { 2599 if (!(status & BIT(index))) 2600 continue; 2601 2602 tx_ring = &priv->tx_rings[index]; 2603 2604 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2605 tx_ring->int_disable(tx_ring); 2606 __napi_schedule_irqoff(&tx_ring->napi); 2607 } 2608 } 2609 2610 return IRQ_HANDLED; 2611 } 2612 2613 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */ 2614 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 2615 { 2616 struct bcmgenet_priv *priv = dev_id; 2617 struct bcmgenet_rx_ring *rx_ring; 2618 struct bcmgenet_tx_ring *tx_ring; 2619 unsigned int status; 2620 unsigned long flags; 2621 2622 /* Read irq status */ 2623 status = bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 2624 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2625 2626 /* clear interrupts */ 2627 bcmgenet_intrl2_0_writel(priv, status, INTRL2_CPU_CLEAR); 2628 2629 netif_dbg(priv, intr, priv->dev, 2630 "IRQ=0x%x\n", status); 2631 2632 if (status & UMAC_IRQ_RXDMA_DONE) { 2633 rx_ring = &priv->rx_rings[DESC_INDEX]; 2634 rx_ring->dim.event_ctr++; 2635 2636 if (likely(napi_schedule_prep(&rx_ring->napi))) { 2637 rx_ring->int_disable(rx_ring); 2638 __napi_schedule_irqoff(&rx_ring->napi); 2639 } 2640 } 2641 2642 if (status & UMAC_IRQ_TXDMA_DONE) { 2643 tx_ring = &priv->tx_rings[DESC_INDEX]; 2644 2645 if (likely(napi_schedule_prep(&tx_ring->napi))) { 2646 tx_ring->int_disable(tx_ring); 2647 __napi_schedule_irqoff(&tx_ring->napi); 2648 } 2649 } 2650 2651 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 2652 status & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 2653 wake_up(&priv->wq); 2654 } 2655 2656 /* all other interested interrupts handled in bottom half */ 2657 status &= (UMAC_IRQ_LINK_EVENT | UMAC_IRQ_PHY_DET_R); 2658 if (status) { 2659 /* Save irq status for bottom-half processing. */ 2660 spin_lock_irqsave(&priv->lock, flags); 2661 priv->irq0_stat |= status; 2662 spin_unlock_irqrestore(&priv->lock, flags); 2663 2664 schedule_work(&priv->bcmgenet_irq_work); 2665 } 2666 2667 return IRQ_HANDLED; 2668 } 2669 2670 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 2671 { 2672 struct bcmgenet_priv *priv = dev_id; 2673 2674 pm_wakeup_event(&priv->pdev->dev, 0); 2675 2676 return IRQ_HANDLED; 2677 } 2678 2679 #ifdef CONFIG_NET_POLL_CONTROLLER 2680 static void bcmgenet_poll_controller(struct net_device *dev) 2681 { 2682 struct bcmgenet_priv *priv = netdev_priv(dev); 2683 2684 /* Invoke the main RX/TX interrupt handler */ 2685 disable_irq(priv->irq0); 2686 bcmgenet_isr0(priv->irq0, priv); 2687 enable_irq(priv->irq0); 2688 2689 /* And the interrupt handler for RX/TX priority queues */ 2690 disable_irq(priv->irq1); 2691 bcmgenet_isr1(priv->irq1, priv); 2692 enable_irq(priv->irq1); 2693 } 2694 #endif 2695 2696 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 2697 { 2698 u32 reg; 2699 2700 reg = bcmgenet_rbuf_ctrl_get(priv); 2701 reg |= BIT(1); 2702 bcmgenet_rbuf_ctrl_set(priv, reg); 2703 udelay(10); 2704 2705 reg &= ~BIT(1); 2706 bcmgenet_rbuf_ctrl_set(priv, reg); 2707 udelay(10); 2708 } 2709 2710 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 2711 unsigned char *addr) 2712 { 2713 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 2714 (addr[2] << 8) | addr[3], UMAC_MAC0); 2715 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 2716 } 2717 2718 static void bcmgenet_get_hw_addr(struct bcmgenet_priv *priv, 2719 unsigned char *addr) 2720 { 2721 u32 addr_tmp; 2722 2723 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC0); 2724 addr[0] = addr_tmp >> 24; 2725 addr[1] = (addr_tmp >> 16) & 0xff; 2726 addr[2] = (addr_tmp >> 8) & 0xff; 2727 addr[3] = addr_tmp & 0xff; 2728 addr_tmp = bcmgenet_umac_readl(priv, UMAC_MAC1); 2729 addr[4] = (addr_tmp >> 8) & 0xff; 2730 addr[5] = addr_tmp & 0xff; 2731 } 2732 2733 /* Returns a reusable dma control register value */ 2734 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 2735 { 2736 u32 reg; 2737 u32 dma_ctrl; 2738 2739 /* disable DMA */ 2740 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 2741 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2742 reg &= ~dma_ctrl; 2743 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2744 2745 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2746 reg &= ~dma_ctrl; 2747 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2748 2749 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 2750 udelay(10); 2751 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 2752 2753 return dma_ctrl; 2754 } 2755 2756 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 2757 { 2758 u32 reg; 2759 2760 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2761 reg |= dma_ctrl; 2762 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2763 2764 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2765 reg |= dma_ctrl; 2766 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2767 } 2768 2769 /* bcmgenet_hfb_clear 2770 * 2771 * Clear Hardware Filter Block and disable all filtering. 2772 */ 2773 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv) 2774 { 2775 u32 i; 2776 2777 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL); 2778 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS); 2779 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4); 2780 2781 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++) 2782 bcmgenet_rdma_writel(priv, 0x0, i); 2783 2784 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++) 2785 bcmgenet_hfb_reg_writel(priv, 0x0, 2786 HFB_FLT_LEN_V3PLUS + i * sizeof(u32)); 2787 2788 for (i = 0; i < priv->hw_params->hfb_filter_cnt * 2789 priv->hw_params->hfb_filter_size; i++) 2790 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32)); 2791 } 2792 2793 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv) 2794 { 2795 if (GENET_IS_V1(priv) || GENET_IS_V2(priv)) 2796 return; 2797 2798 bcmgenet_hfb_clear(priv); 2799 } 2800 2801 static void bcmgenet_netif_start(struct net_device *dev) 2802 { 2803 struct bcmgenet_priv *priv = netdev_priv(dev); 2804 2805 /* Start the network engine */ 2806 bcmgenet_enable_rx_napi(priv); 2807 2808 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2809 2810 bcmgenet_enable_tx_napi(priv); 2811 2812 /* Monitor link interrupts now */ 2813 bcmgenet_link_intr_enable(priv); 2814 2815 phy_start(dev->phydev); 2816 } 2817 2818 static int bcmgenet_open(struct net_device *dev) 2819 { 2820 struct bcmgenet_priv *priv = netdev_priv(dev); 2821 unsigned long dma_ctrl; 2822 u32 reg; 2823 int ret; 2824 2825 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2826 2827 /* Turn on the clock */ 2828 clk_prepare_enable(priv->clk); 2829 2830 /* If this is an internal GPHY, power it back on now, before UniMAC is 2831 * brought out of reset as absolutely no UniMAC activity is allowed 2832 */ 2833 if (priv->internal_phy) 2834 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2835 2836 /* take MAC out of reset */ 2837 bcmgenet_umac_reset(priv); 2838 2839 init_umac(priv); 2840 2841 /* Apply features again in case we changed them while interface was 2842 * down 2843 */ 2844 bcmgenet_set_features(dev, dev->features); 2845 2846 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2847 2848 if (priv->internal_phy) { 2849 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2850 reg |= EXT_ENERGY_DET_MASK; 2851 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2852 } 2853 2854 /* Disable RX/TX DMA and flush TX queues */ 2855 dma_ctrl = bcmgenet_dma_disable(priv); 2856 2857 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2858 ret = bcmgenet_init_dma(priv); 2859 if (ret) { 2860 netdev_err(dev, "failed to initialize DMA\n"); 2861 goto err_clk_disable; 2862 } 2863 2864 /* Always enable ring 16 - descriptor ring */ 2865 bcmgenet_enable_dma(priv, dma_ctrl); 2866 2867 /* HFB init */ 2868 bcmgenet_hfb_init(priv); 2869 2870 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2871 dev->name, priv); 2872 if (ret < 0) { 2873 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2874 goto err_fini_dma; 2875 } 2876 2877 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2878 dev->name, priv); 2879 if (ret < 0) { 2880 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2881 goto err_irq0; 2882 } 2883 2884 ret = bcmgenet_mii_probe(dev); 2885 if (ret) { 2886 netdev_err(dev, "failed to connect to PHY\n"); 2887 goto err_irq1; 2888 } 2889 2890 bcmgenet_netif_start(dev); 2891 2892 netif_tx_start_all_queues(dev); 2893 2894 return 0; 2895 2896 err_irq1: 2897 free_irq(priv->irq1, priv); 2898 err_irq0: 2899 free_irq(priv->irq0, priv); 2900 err_fini_dma: 2901 bcmgenet_dma_teardown(priv); 2902 bcmgenet_fini_dma(priv); 2903 err_clk_disable: 2904 if (priv->internal_phy) 2905 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2906 clk_disable_unprepare(priv->clk); 2907 return ret; 2908 } 2909 2910 static void bcmgenet_netif_stop(struct net_device *dev) 2911 { 2912 struct bcmgenet_priv *priv = netdev_priv(dev); 2913 2914 bcmgenet_disable_tx_napi(priv); 2915 netif_tx_disable(dev); 2916 2917 /* Disable MAC receive */ 2918 umac_enable_set(priv, CMD_RX_EN, false); 2919 2920 bcmgenet_dma_teardown(priv); 2921 2922 /* Disable MAC transmit. TX DMA disabled must be done before this */ 2923 umac_enable_set(priv, CMD_TX_EN, false); 2924 2925 phy_stop(dev->phydev); 2926 bcmgenet_disable_rx_napi(priv); 2927 bcmgenet_intr_disable(priv); 2928 2929 /* Wait for pending work items to complete. Since interrupts are 2930 * disabled no new work will be scheduled. 2931 */ 2932 cancel_work_sync(&priv->bcmgenet_irq_work); 2933 2934 priv->old_link = -1; 2935 priv->old_speed = -1; 2936 priv->old_duplex = -1; 2937 priv->old_pause = -1; 2938 2939 /* tx reclaim */ 2940 bcmgenet_tx_reclaim_all(dev); 2941 bcmgenet_fini_dma(priv); 2942 } 2943 2944 static int bcmgenet_close(struct net_device *dev) 2945 { 2946 struct bcmgenet_priv *priv = netdev_priv(dev); 2947 int ret = 0; 2948 2949 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2950 2951 bcmgenet_netif_stop(dev); 2952 2953 /* Really kill the PHY state machine and disconnect from it */ 2954 phy_disconnect(dev->phydev); 2955 2956 free_irq(priv->irq0, priv); 2957 free_irq(priv->irq1, priv); 2958 2959 if (priv->internal_phy) 2960 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2961 2962 clk_disable_unprepare(priv->clk); 2963 2964 return ret; 2965 } 2966 2967 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring) 2968 { 2969 struct bcmgenet_priv *priv = ring->priv; 2970 u32 p_index, c_index, intsts, intmsk; 2971 struct netdev_queue *txq; 2972 unsigned int free_bds; 2973 bool txq_stopped; 2974 2975 if (!netif_msg_tx_err(priv)) 2976 return; 2977 2978 txq = netdev_get_tx_queue(priv->dev, ring->queue); 2979 2980 spin_lock(&ring->lock); 2981 if (ring->index == DESC_INDEX) { 2982 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 2983 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE; 2984 } else { 2985 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); 2986 intmsk = 1 << ring->index; 2987 } 2988 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 2989 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX); 2990 txq_stopped = netif_tx_queue_stopped(txq); 2991 free_bds = ring->free_bds; 2992 spin_unlock(&ring->lock); 2993 2994 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n" 2995 "TX queue status: %s, interrupts: %s\n" 2996 "(sw)free_bds: %d (sw)size: %d\n" 2997 "(sw)p_index: %d (hw)p_index: %d\n" 2998 "(sw)c_index: %d (hw)c_index: %d\n" 2999 "(sw)clean_p: %d (sw)write_p: %d\n" 3000 "(sw)cb_ptr: %d (sw)end_ptr: %d\n", 3001 ring->index, ring->queue, 3002 txq_stopped ? "stopped" : "active", 3003 intsts & intmsk ? "enabled" : "disabled", 3004 free_bds, ring->size, 3005 ring->prod_index, p_index & DMA_P_INDEX_MASK, 3006 ring->c_index, c_index & DMA_C_INDEX_MASK, 3007 ring->clean_ptr, ring->write_ptr, 3008 ring->cb_ptr, ring->end_ptr); 3009 } 3010 3011 static void bcmgenet_timeout(struct net_device *dev, unsigned int txqueue) 3012 { 3013 struct bcmgenet_priv *priv = netdev_priv(dev); 3014 u32 int0_enable = 0; 3015 u32 int1_enable = 0; 3016 unsigned int q; 3017 3018 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 3019 3020 for (q = 0; q < priv->hw_params->tx_queues; q++) 3021 bcmgenet_dump_tx_queue(&priv->tx_rings[q]); 3022 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]); 3023 3024 bcmgenet_tx_reclaim_all(dev); 3025 3026 for (q = 0; q < priv->hw_params->tx_queues; q++) 3027 int1_enable |= (1 << q); 3028 3029 int0_enable = UMAC_IRQ_TXDMA_DONE; 3030 3031 /* Re-enable TX interrupts if disabled */ 3032 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR); 3033 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR); 3034 3035 netif_trans_update(dev); 3036 3037 dev->stats.tx_errors++; 3038 3039 netif_tx_wake_all_queues(dev); 3040 } 3041 3042 #define MAX_MDF_FILTER 17 3043 3044 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 3045 unsigned char *addr, 3046 int *i) 3047 { 3048 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 3049 UMAC_MDF_ADDR + (*i * 4)); 3050 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 3051 addr[4] << 8 | addr[5], 3052 UMAC_MDF_ADDR + ((*i + 1) * 4)); 3053 *i += 2; 3054 } 3055 3056 static void bcmgenet_set_rx_mode(struct net_device *dev) 3057 { 3058 struct bcmgenet_priv *priv = netdev_priv(dev); 3059 struct netdev_hw_addr *ha; 3060 int i, nfilter; 3061 u32 reg; 3062 3063 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 3064 3065 /* Number of filters needed */ 3066 nfilter = netdev_uc_count(dev) + netdev_mc_count(dev) + 2; 3067 3068 /* 3069 * Turn on promicuous mode for three scenarios 3070 * 1. IFF_PROMISC flag is set 3071 * 2. IFF_ALLMULTI flag is set 3072 * 3. The number of filters needed exceeds the number filters 3073 * supported by the hardware. 3074 */ 3075 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 3076 if ((dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) || 3077 (nfilter > MAX_MDF_FILTER)) { 3078 reg |= CMD_PROMISC; 3079 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3080 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 3081 return; 3082 } else { 3083 reg &= ~CMD_PROMISC; 3084 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 3085 } 3086 3087 /* update MDF filter */ 3088 i = 0; 3089 /* Broadcast */ 3090 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i); 3091 /* my own address.*/ 3092 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i); 3093 3094 /* Unicast */ 3095 netdev_for_each_uc_addr(ha, dev) 3096 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3097 3098 /* Multicast */ 3099 netdev_for_each_mc_addr(ha, dev) 3100 bcmgenet_set_mdf_addr(priv, ha->addr, &i); 3101 3102 /* Enable filters */ 3103 reg = GENMASK(MAX_MDF_FILTER - 1, MAX_MDF_FILTER - nfilter); 3104 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 3105 } 3106 3107 /* Set the hardware MAC address. */ 3108 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 3109 { 3110 struct sockaddr *addr = p; 3111 3112 /* Setting the MAC address at the hardware level is not possible 3113 * without disabling the UniMAC RX/TX enable bits. 3114 */ 3115 if (netif_running(dev)) 3116 return -EBUSY; 3117 3118 ether_addr_copy(dev->dev_addr, addr->sa_data); 3119 3120 return 0; 3121 } 3122 3123 static struct net_device_stats *bcmgenet_get_stats(struct net_device *dev) 3124 { 3125 struct bcmgenet_priv *priv = netdev_priv(dev); 3126 unsigned long tx_bytes = 0, tx_packets = 0; 3127 unsigned long rx_bytes = 0, rx_packets = 0; 3128 unsigned long rx_errors = 0, rx_dropped = 0; 3129 struct bcmgenet_tx_ring *tx_ring; 3130 struct bcmgenet_rx_ring *rx_ring; 3131 unsigned int q; 3132 3133 for (q = 0; q < priv->hw_params->tx_queues; q++) { 3134 tx_ring = &priv->tx_rings[q]; 3135 tx_bytes += tx_ring->bytes; 3136 tx_packets += tx_ring->packets; 3137 } 3138 tx_ring = &priv->tx_rings[DESC_INDEX]; 3139 tx_bytes += tx_ring->bytes; 3140 tx_packets += tx_ring->packets; 3141 3142 for (q = 0; q < priv->hw_params->rx_queues; q++) { 3143 rx_ring = &priv->rx_rings[q]; 3144 3145 rx_bytes += rx_ring->bytes; 3146 rx_packets += rx_ring->packets; 3147 rx_errors += rx_ring->errors; 3148 rx_dropped += rx_ring->dropped; 3149 } 3150 rx_ring = &priv->rx_rings[DESC_INDEX]; 3151 rx_bytes += rx_ring->bytes; 3152 rx_packets += rx_ring->packets; 3153 rx_errors += rx_ring->errors; 3154 rx_dropped += rx_ring->dropped; 3155 3156 dev->stats.tx_bytes = tx_bytes; 3157 dev->stats.tx_packets = tx_packets; 3158 dev->stats.rx_bytes = rx_bytes; 3159 dev->stats.rx_packets = rx_packets; 3160 dev->stats.rx_errors = rx_errors; 3161 dev->stats.rx_missed_errors = rx_errors; 3162 dev->stats.rx_dropped = rx_dropped; 3163 return &dev->stats; 3164 } 3165 3166 static const struct net_device_ops bcmgenet_netdev_ops = { 3167 .ndo_open = bcmgenet_open, 3168 .ndo_stop = bcmgenet_close, 3169 .ndo_start_xmit = bcmgenet_xmit, 3170 .ndo_tx_timeout = bcmgenet_timeout, 3171 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 3172 .ndo_set_mac_address = bcmgenet_set_mac_addr, 3173 .ndo_do_ioctl = phy_do_ioctl_running, 3174 .ndo_set_features = bcmgenet_set_features, 3175 #ifdef CONFIG_NET_POLL_CONTROLLER 3176 .ndo_poll_controller = bcmgenet_poll_controller, 3177 #endif 3178 .ndo_get_stats = bcmgenet_get_stats, 3179 }; 3180 3181 /* Array of GENET hardware parameters/characteristics */ 3182 static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 3183 [GENET_V1] = { 3184 .tx_queues = 0, 3185 .tx_bds_per_q = 0, 3186 .rx_queues = 0, 3187 .rx_bds_per_q = 0, 3188 .bp_in_en_shift = 16, 3189 .bp_in_mask = 0xffff, 3190 .hfb_filter_cnt = 16, 3191 .qtag_mask = 0x1F, 3192 .hfb_offset = 0x1000, 3193 .rdma_offset = 0x2000, 3194 .tdma_offset = 0x3000, 3195 .words_per_bd = 2, 3196 }, 3197 [GENET_V2] = { 3198 .tx_queues = 4, 3199 .tx_bds_per_q = 32, 3200 .rx_queues = 0, 3201 .rx_bds_per_q = 0, 3202 .bp_in_en_shift = 16, 3203 .bp_in_mask = 0xffff, 3204 .hfb_filter_cnt = 16, 3205 .qtag_mask = 0x1F, 3206 .tbuf_offset = 0x0600, 3207 .hfb_offset = 0x1000, 3208 .hfb_reg_offset = 0x2000, 3209 .rdma_offset = 0x3000, 3210 .tdma_offset = 0x4000, 3211 .words_per_bd = 2, 3212 .flags = GENET_HAS_EXT, 3213 }, 3214 [GENET_V3] = { 3215 .tx_queues = 4, 3216 .tx_bds_per_q = 32, 3217 .rx_queues = 0, 3218 .rx_bds_per_q = 0, 3219 .bp_in_en_shift = 17, 3220 .bp_in_mask = 0x1ffff, 3221 .hfb_filter_cnt = 48, 3222 .hfb_filter_size = 128, 3223 .qtag_mask = 0x3F, 3224 .tbuf_offset = 0x0600, 3225 .hfb_offset = 0x8000, 3226 .hfb_reg_offset = 0xfc00, 3227 .rdma_offset = 0x10000, 3228 .tdma_offset = 0x11000, 3229 .words_per_bd = 2, 3230 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR | 3231 GENET_HAS_MOCA_LINK_DET, 3232 }, 3233 [GENET_V4] = { 3234 .tx_queues = 4, 3235 .tx_bds_per_q = 32, 3236 .rx_queues = 0, 3237 .rx_bds_per_q = 0, 3238 .bp_in_en_shift = 17, 3239 .bp_in_mask = 0x1ffff, 3240 .hfb_filter_cnt = 48, 3241 .hfb_filter_size = 128, 3242 .qtag_mask = 0x3F, 3243 .tbuf_offset = 0x0600, 3244 .hfb_offset = 0x8000, 3245 .hfb_reg_offset = 0xfc00, 3246 .rdma_offset = 0x2000, 3247 .tdma_offset = 0x4000, 3248 .words_per_bd = 3, 3249 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3250 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3251 }, 3252 [GENET_V5] = { 3253 .tx_queues = 4, 3254 .tx_bds_per_q = 32, 3255 .rx_queues = 0, 3256 .rx_bds_per_q = 0, 3257 .bp_in_en_shift = 17, 3258 .bp_in_mask = 0x1ffff, 3259 .hfb_filter_cnt = 48, 3260 .hfb_filter_size = 128, 3261 .qtag_mask = 0x3F, 3262 .tbuf_offset = 0x0600, 3263 .hfb_offset = 0x8000, 3264 .hfb_reg_offset = 0xfc00, 3265 .rdma_offset = 0x2000, 3266 .tdma_offset = 0x4000, 3267 .words_per_bd = 3, 3268 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | 3269 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET, 3270 }, 3271 }; 3272 3273 /* Infer hardware parameters from the detected GENET version */ 3274 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 3275 { 3276 struct bcmgenet_hw_params *params; 3277 u32 reg; 3278 u8 major; 3279 u16 gphy_rev; 3280 3281 if (GENET_IS_V5(priv) || GENET_IS_V4(priv)) { 3282 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3283 genet_dma_ring_regs = genet_dma_ring_regs_v4; 3284 } else if (GENET_IS_V3(priv)) { 3285 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 3286 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3287 } else if (GENET_IS_V2(priv)) { 3288 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 3289 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3290 } else if (GENET_IS_V1(priv)) { 3291 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 3292 genet_dma_ring_regs = genet_dma_ring_regs_v123; 3293 } 3294 3295 /* enum genet_version starts at 1 */ 3296 priv->hw_params = &bcmgenet_hw_params[priv->version]; 3297 params = priv->hw_params; 3298 3299 /* Read GENET HW version */ 3300 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 3301 major = (reg >> 24 & 0x0f); 3302 if (major == 6) 3303 major = 5; 3304 else if (major == 5) 3305 major = 4; 3306 else if (major == 0) 3307 major = 1; 3308 if (major != priv->version) { 3309 dev_err(&priv->pdev->dev, 3310 "GENET version mismatch, got: %d, configured for: %d\n", 3311 major, priv->version); 3312 } 3313 3314 /* Print the GENET core version */ 3315 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 3316 major, (reg >> 16) & 0x0f, reg & 0xffff); 3317 3318 /* Store the integrated PHY revision for the MDIO probing function 3319 * to pass this information to the PHY driver. The PHY driver expects 3320 * to find the PHY major revision in bits 15:8 while the GENET register 3321 * stores that information in bits 7:0, account for that. 3322 * 3323 * On newer chips, starting with PHY revision G0, a new scheme is 3324 * deployed similar to the Starfighter 2 switch with GPHY major 3325 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0 3326 * is reserved as well as special value 0x01ff, we have a small 3327 * heuristic to check for the new GPHY revision and re-arrange things 3328 * so the GPHY driver is happy. 3329 */ 3330 gphy_rev = reg & 0xffff; 3331 3332 if (GENET_IS_V5(priv)) { 3333 /* The EPHY revision should come from the MDIO registers of 3334 * the PHY not from GENET. 3335 */ 3336 if (gphy_rev != 0) { 3337 pr_warn("GENET is reporting EPHY revision: 0x%04x\n", 3338 gphy_rev); 3339 } 3340 /* This is reserved so should require special treatment */ 3341 } else if (gphy_rev == 0 || gphy_rev == 0x01ff) { 3342 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev); 3343 return; 3344 /* This is the good old scheme, just GPHY major, no minor nor patch */ 3345 } else if ((gphy_rev & 0xf0) != 0) { 3346 priv->gphy_rev = gphy_rev << 8; 3347 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */ 3348 } else if ((gphy_rev & 0xff00) != 0) { 3349 priv->gphy_rev = gphy_rev; 3350 } 3351 3352 #ifdef CONFIG_PHYS_ADDR_T_64BIT 3353 if (!(params->flags & GENET_HAS_40BITS)) 3354 pr_warn("GENET does not support 40-bits PA\n"); 3355 #endif 3356 3357 pr_debug("Configuration for version: %d\n" 3358 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n" 3359 "BP << en: %2d, BP msk: 0x%05x\n" 3360 "HFB count: %2d, QTAQ msk: 0x%05x\n" 3361 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 3362 "RDMA: 0x%05x, TDMA: 0x%05x\n" 3363 "Words/BD: %d\n", 3364 priv->version, 3365 params->tx_queues, params->tx_bds_per_q, 3366 params->rx_queues, params->rx_bds_per_q, 3367 params->bp_in_en_shift, params->bp_in_mask, 3368 params->hfb_filter_cnt, params->qtag_mask, 3369 params->tbuf_offset, params->hfb_offset, 3370 params->hfb_reg_offset, 3371 params->rdma_offset, params->tdma_offset, 3372 params->words_per_bd); 3373 } 3374 3375 struct bcmgenet_plat_data { 3376 enum bcmgenet_version version; 3377 u32 dma_max_burst_length; 3378 }; 3379 3380 static const struct bcmgenet_plat_data v1_plat_data = { 3381 .version = GENET_V1, 3382 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3383 }; 3384 3385 static const struct bcmgenet_plat_data v2_plat_data = { 3386 .version = GENET_V2, 3387 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3388 }; 3389 3390 static const struct bcmgenet_plat_data v3_plat_data = { 3391 .version = GENET_V3, 3392 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3393 }; 3394 3395 static const struct bcmgenet_plat_data v4_plat_data = { 3396 .version = GENET_V4, 3397 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3398 }; 3399 3400 static const struct bcmgenet_plat_data v5_plat_data = { 3401 .version = GENET_V5, 3402 .dma_max_burst_length = DMA_MAX_BURST_LENGTH, 3403 }; 3404 3405 static const struct bcmgenet_plat_data bcm2711_plat_data = { 3406 .version = GENET_V5, 3407 .dma_max_burst_length = 0x08, 3408 }; 3409 3410 static const struct of_device_id bcmgenet_match[] = { 3411 { .compatible = "brcm,genet-v1", .data = &v1_plat_data }, 3412 { .compatible = "brcm,genet-v2", .data = &v2_plat_data }, 3413 { .compatible = "brcm,genet-v3", .data = &v3_plat_data }, 3414 { .compatible = "brcm,genet-v4", .data = &v4_plat_data }, 3415 { .compatible = "brcm,genet-v5", .data = &v5_plat_data }, 3416 { .compatible = "brcm,bcm2711-genet-v5", .data = &bcm2711_plat_data }, 3417 { }, 3418 }; 3419 MODULE_DEVICE_TABLE(of, bcmgenet_match); 3420 3421 static int bcmgenet_probe(struct platform_device *pdev) 3422 { 3423 struct bcmgenet_platform_data *pd = pdev->dev.platform_data; 3424 struct device_node *dn = pdev->dev.of_node; 3425 const struct of_device_id *of_id = NULL; 3426 const struct bcmgenet_plat_data *pdata; 3427 struct bcmgenet_priv *priv; 3428 struct net_device *dev; 3429 unsigned int i; 3430 int err = -EIO; 3431 3432 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */ 3433 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 3434 GENET_MAX_MQ_CNT + 1); 3435 if (!dev) { 3436 dev_err(&pdev->dev, "can't allocate net device\n"); 3437 return -ENOMEM; 3438 } 3439 3440 if (dn) { 3441 of_id = of_match_node(bcmgenet_match, dn); 3442 if (!of_id) 3443 return -EINVAL; 3444 } 3445 3446 priv = netdev_priv(dev); 3447 priv->irq0 = platform_get_irq(pdev, 0); 3448 if (priv->irq0 < 0) { 3449 err = priv->irq0; 3450 goto err; 3451 } 3452 priv->irq1 = platform_get_irq(pdev, 1); 3453 if (priv->irq1 < 0) { 3454 err = priv->irq1; 3455 goto err; 3456 } 3457 priv->wol_irq = platform_get_irq_optional(pdev, 2); 3458 3459 priv->base = devm_platform_ioremap_resource(pdev, 0); 3460 if (IS_ERR(priv->base)) { 3461 err = PTR_ERR(priv->base); 3462 goto err; 3463 } 3464 3465 spin_lock_init(&priv->lock); 3466 3467 SET_NETDEV_DEV(dev, &pdev->dev); 3468 dev_set_drvdata(&pdev->dev, dev); 3469 dev->watchdog_timeo = 2 * HZ; 3470 dev->ethtool_ops = &bcmgenet_ethtool_ops; 3471 dev->netdev_ops = &bcmgenet_netdev_ops; 3472 3473 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 3474 3475 /* Set default features */ 3476 dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_CSUM | 3477 NETIF_F_RXCSUM; 3478 dev->hw_features |= dev->features; 3479 dev->vlan_features |= dev->features; 3480 3481 /* Request the WOL interrupt and advertise suspend if available */ 3482 priv->wol_irq_disabled = true; 3483 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 3484 dev->name, priv); 3485 if (!err) 3486 device_set_wakeup_capable(&pdev->dev, 1); 3487 3488 /* Set the needed headroom to account for any possible 3489 * features enabling/disabling at runtime 3490 */ 3491 dev->needed_headroom += 64; 3492 3493 netdev_boot_setup_check(dev); 3494 3495 priv->dev = dev; 3496 priv->pdev = pdev; 3497 3498 pdata = device_get_match_data(&pdev->dev); 3499 if (pdata) { 3500 priv->version = pdata->version; 3501 priv->dma_max_burst_length = pdata->dma_max_burst_length; 3502 } else { 3503 priv->version = pd->genet_version; 3504 priv->dma_max_burst_length = DMA_MAX_BURST_LENGTH; 3505 } 3506 3507 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 3508 if (IS_ERR(priv->clk)) { 3509 dev_dbg(&priv->pdev->dev, "failed to get enet clock\n"); 3510 priv->clk = NULL; 3511 } 3512 3513 clk_prepare_enable(priv->clk); 3514 3515 bcmgenet_set_hw_params(priv); 3516 3517 err = -EIO; 3518 if (priv->hw_params->flags & GENET_HAS_40BITS) 3519 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); 3520 if (err) 3521 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3522 if (err) 3523 goto err; 3524 3525 /* Mii wait queue */ 3526 init_waitqueue_head(&priv->wq); 3527 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 3528 priv->rx_buf_len = RX_BUF_LENGTH; 3529 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 3530 3531 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 3532 if (IS_ERR(priv->clk_wol)) { 3533 dev_dbg(&priv->pdev->dev, "failed to get enet-wol clock\n"); 3534 priv->clk_wol = NULL; 3535 } 3536 3537 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee"); 3538 if (IS_ERR(priv->clk_eee)) { 3539 dev_dbg(&priv->pdev->dev, "failed to get enet-eee clock\n"); 3540 priv->clk_eee = NULL; 3541 } 3542 3543 /* If this is an internal GPHY, power it on now, before UniMAC is 3544 * brought out of reset as absolutely no UniMAC activity is allowed 3545 */ 3546 if (device_get_phy_mode(&pdev->dev) == PHY_INTERFACE_MODE_INTERNAL) 3547 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3548 3549 if ((pd) && (!IS_ERR_OR_NULL(pd->mac_address))) 3550 ether_addr_copy(dev->dev_addr, pd->mac_address); 3551 else 3552 if (!device_get_mac_address(&pdev->dev, dev->dev_addr, ETH_ALEN)) 3553 if (has_acpi_companion(&pdev->dev)) 3554 bcmgenet_get_hw_addr(priv, dev->dev_addr); 3555 3556 if (!is_valid_ether_addr(dev->dev_addr)) { 3557 dev_warn(&pdev->dev, "using random Ethernet MAC\n"); 3558 eth_hw_addr_random(dev); 3559 } 3560 3561 reset_umac(priv); 3562 3563 err = bcmgenet_mii_init(dev); 3564 if (err) 3565 goto err_clk_disable; 3566 3567 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 3568 * just the ring 16 descriptor based TX 3569 */ 3570 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 3571 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 3572 3573 /* Set default coalescing parameters */ 3574 for (i = 0; i < priv->hw_params->rx_queues; i++) 3575 priv->rx_rings[i].rx_max_coalesced_frames = 1; 3576 priv->rx_rings[DESC_INDEX].rx_max_coalesced_frames = 1; 3577 3578 /* libphy will determine the link state */ 3579 netif_carrier_off(dev); 3580 3581 /* Turn off the main clock, WOL clock is handled separately */ 3582 clk_disable_unprepare(priv->clk); 3583 3584 err = register_netdev(dev); 3585 if (err) 3586 goto err; 3587 3588 return err; 3589 3590 err_clk_disable: 3591 clk_disable_unprepare(priv->clk); 3592 err: 3593 free_netdev(dev); 3594 return err; 3595 } 3596 3597 static int bcmgenet_remove(struct platform_device *pdev) 3598 { 3599 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 3600 3601 dev_set_drvdata(&pdev->dev, NULL); 3602 unregister_netdev(priv->dev); 3603 bcmgenet_mii_exit(priv->dev); 3604 free_netdev(priv->dev); 3605 3606 return 0; 3607 } 3608 3609 static void bcmgenet_shutdown(struct platform_device *pdev) 3610 { 3611 bcmgenet_remove(pdev); 3612 } 3613 3614 #ifdef CONFIG_PM_SLEEP 3615 static int bcmgenet_resume(struct device *d) 3616 { 3617 struct net_device *dev = dev_get_drvdata(d); 3618 struct bcmgenet_priv *priv = netdev_priv(dev); 3619 unsigned long dma_ctrl; 3620 int ret; 3621 u32 reg; 3622 3623 if (!netif_running(dev)) 3624 return 0; 3625 3626 /* Turn on the clock */ 3627 ret = clk_prepare_enable(priv->clk); 3628 if (ret) 3629 return ret; 3630 3631 /* If this is an internal GPHY, power it back on now, before UniMAC is 3632 * brought out of reset as absolutely no UniMAC activity is allowed 3633 */ 3634 if (priv->internal_phy) 3635 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 3636 3637 bcmgenet_umac_reset(priv); 3638 3639 init_umac(priv); 3640 3641 /* From WOL-enabled suspend, switch to regular clock */ 3642 if (priv->wolopts) 3643 clk_disable_unprepare(priv->clk_wol); 3644 3645 phy_init_hw(dev->phydev); 3646 3647 /* Speed settings must be restored */ 3648 genphy_config_aneg(dev->phydev); 3649 bcmgenet_mii_config(priv->dev, false); 3650 3651 /* Restore enabled features */ 3652 bcmgenet_set_features(dev, dev->features); 3653 3654 bcmgenet_set_hw_addr(priv, dev->dev_addr); 3655 3656 if (priv->internal_phy) { 3657 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 3658 reg |= EXT_ENERGY_DET_MASK; 3659 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 3660 } 3661 3662 if (priv->wolopts) 3663 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 3664 3665 /* Disable RX/TX DMA and flush TX queues */ 3666 dma_ctrl = bcmgenet_dma_disable(priv); 3667 3668 /* Reinitialize TDMA and RDMA and SW housekeeping */ 3669 ret = bcmgenet_init_dma(priv); 3670 if (ret) { 3671 netdev_err(dev, "failed to initialize DMA\n"); 3672 goto out_clk_disable; 3673 } 3674 3675 /* Always enable ring 16 - descriptor ring */ 3676 bcmgenet_enable_dma(priv, dma_ctrl); 3677 3678 if (!device_may_wakeup(d)) 3679 phy_resume(dev->phydev); 3680 3681 if (priv->eee.eee_enabled) 3682 bcmgenet_eee_enable_set(dev, true); 3683 3684 bcmgenet_netif_start(dev); 3685 3686 netif_device_attach(dev); 3687 3688 return 0; 3689 3690 out_clk_disable: 3691 if (priv->internal_phy) 3692 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3693 clk_disable_unprepare(priv->clk); 3694 return ret; 3695 } 3696 3697 static int bcmgenet_suspend(struct device *d) 3698 { 3699 struct net_device *dev = dev_get_drvdata(d); 3700 struct bcmgenet_priv *priv = netdev_priv(dev); 3701 int ret = 0; 3702 3703 if (!netif_running(dev)) 3704 return 0; 3705 3706 netif_device_detach(dev); 3707 3708 bcmgenet_netif_stop(dev); 3709 3710 if (!device_may_wakeup(d)) 3711 phy_suspend(dev->phydev); 3712 3713 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 3714 if (device_may_wakeup(d) && priv->wolopts) { 3715 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 3716 clk_prepare_enable(priv->clk_wol); 3717 } else if (priv->internal_phy) { 3718 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 3719 } 3720 3721 /* Turn off the clocks */ 3722 clk_disable_unprepare(priv->clk); 3723 3724 if (ret) 3725 bcmgenet_resume(d); 3726 3727 return ret; 3728 } 3729 #endif /* CONFIG_PM_SLEEP */ 3730 3731 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 3732 3733 static const struct acpi_device_id genet_acpi_match[] = { 3734 { "BCM6E4E", (kernel_ulong_t)&bcm2711_plat_data }, 3735 { }, 3736 }; 3737 MODULE_DEVICE_TABLE(acpi, genet_acpi_match); 3738 3739 static struct platform_driver bcmgenet_driver = { 3740 .probe = bcmgenet_probe, 3741 .remove = bcmgenet_remove, 3742 .shutdown = bcmgenet_shutdown, 3743 .driver = { 3744 .name = "bcmgenet", 3745 .of_match_table = bcmgenet_match, 3746 .pm = &bcmgenet_pm_ops, 3747 .acpi_match_table = ACPI_PTR(genet_acpi_match), 3748 }, 3749 }; 3750 module_platform_driver(bcmgenet_driver); 3751 3752 MODULE_AUTHOR("Broadcom Corporation"); 3753 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 3754 MODULE_ALIAS("platform:bcmgenet"); 3755 MODULE_LICENSE("GPL"); 3756