1 2 /* cnic.c: Broadcom CNIC core network driver. 3 * 4 * Copyright (c) 2006-2009 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 */ 11 12 #ifndef CNIC_DEFS_H 13 #define CNIC_DEFS_H 14 15 /* KWQ (kernel work queue) request op codes */ 16 #define L2_KWQE_OPCODE_VALUE_FLUSH (4) 17 #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE (8) 18 19 #define L4_KWQE_OPCODE_VALUE_CONNECT1 (50) 20 #define L4_KWQE_OPCODE_VALUE_CONNECT2 (51) 21 #define L4_KWQE_OPCODE_VALUE_CONNECT3 (52) 22 #define L4_KWQE_OPCODE_VALUE_RESET (53) 23 #define L4_KWQE_OPCODE_VALUE_CLOSE (54) 24 #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET (60) 25 #define L4_KWQE_OPCODE_VALUE_INIT_ULP (61) 26 27 #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG (1) 28 #define L4_KWQE_OPCODE_VALUE_UPDATE_PG (9) 29 #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG (14) 30 31 #define L5CM_RAMROD_CMD_ID_BASE (0x80) 32 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3) 33 #define L5CM_RAMROD_CMD_ID_CLOSE (L5CM_RAMROD_CMD_ID_BASE + 12) 34 #define L5CM_RAMROD_CMD_ID_ABORT (L5CM_RAMROD_CMD_ID_BASE + 13) 35 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14) 36 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15) 37 38 #define FCOE_KCQE_OPCODE_INIT_FUNC (0x10) 39 #define FCOE_KCQE_OPCODE_DESTROY_FUNC (0x11) 40 #define FCOE_KCQE_OPCODE_STAT_FUNC (0x12) 41 #define FCOE_KCQE_OPCODE_OFFLOAD_CONN (0x15) 42 #define FCOE_KCQE_OPCODE_ENABLE_CONN (0x16) 43 #define FCOE_KCQE_OPCODE_DISABLE_CONN (0x17) 44 #define FCOE_KCQE_OPCODE_DESTROY_CONN (0x18) 45 #define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20) 46 #define FCOE_KCQE_OPCODE_FCOE_ERROR (0x21) 47 48 #define FCOE_RAMROD_CMD_ID_INIT_FUNC (FCOE_KCQE_OPCODE_INIT_FUNC) 49 #define FCOE_RAMROD_CMD_ID_DESTROY_FUNC (FCOE_KCQE_OPCODE_DESTROY_FUNC) 50 #define FCOE_RAMROD_CMD_ID_STAT_FUNC (FCOE_KCQE_OPCODE_STAT_FUNC) 51 #define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN (FCOE_KCQE_OPCODE_OFFLOAD_CONN) 52 #define FCOE_RAMROD_CMD_ID_ENABLE_CONN (FCOE_KCQE_OPCODE_ENABLE_CONN) 53 #define FCOE_RAMROD_CMD_ID_DISABLE_CONN (FCOE_KCQE_OPCODE_DISABLE_CONN) 54 #define FCOE_RAMROD_CMD_ID_DESTROY_CONN (FCOE_KCQE_OPCODE_DESTROY_CONN) 55 #define FCOE_RAMROD_CMD_ID_TERMINATE_CONN (0x81) 56 57 #define FCOE_KWQE_OPCODE_INIT1 (0) 58 #define FCOE_KWQE_OPCODE_INIT2 (1) 59 #define FCOE_KWQE_OPCODE_INIT3 (2) 60 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN1 (3) 61 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN2 (4) 62 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN3 (5) 63 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN4 (6) 64 #define FCOE_KWQE_OPCODE_ENABLE_CONN (7) 65 #define FCOE_KWQE_OPCODE_DISABLE_CONN (8) 66 #define FCOE_KWQE_OPCODE_DESTROY_CONN (9) 67 #define FCOE_KWQE_OPCODE_DESTROY (10) 68 #define FCOE_KWQE_OPCODE_STAT (11) 69 70 #define FCOE_KCQE_COMPLETION_STATUS_ERROR (0x1) 71 #define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3) 72 73 /* KCQ (kernel completion queue) response op codes */ 74 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) 75 #define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) 76 #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE (55) 77 #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE (56) 78 #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED (57) 79 #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED (58) 80 #define L4_KCQE_OPCODE_VALUE_INIT_ULP (61) 81 82 #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG (1) 83 #define L4_KCQE_OPCODE_VALUE_UPDATE_PG (9) 84 #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG (14) 85 86 /* KCQ (kernel completion queue) completion status */ 87 #define L4_KCQE_COMPLETION_STATUS_SUCCESS (0) 88 #define L4_KCQE_COMPLETION_STATUS_TIMEOUT (0x93) 89 90 #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL (0x83) 91 #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG (0x89) 92 93 #define L4_KCQE_OPCODE_VALUE_OOO_EVENT_NOTIFICATION (0xa0) 94 #define L4_KCQE_OPCODE_VALUE_OOO_FLUSH (0xa1) 95 96 #define L4_LAYER_CODE (4) 97 #define L2_LAYER_CODE (2) 98 99 /* 100 * L4 KCQ CQE 101 */ 102 struct l4_kcq { 103 u32 cid; 104 u32 pg_cid; 105 u32 conn_id; 106 u32 pg_host_opaque; 107 #if defined(__BIG_ENDIAN) 108 u16 status; 109 u16 reserved1; 110 #elif defined(__LITTLE_ENDIAN) 111 u16 reserved1; 112 u16 status; 113 #endif 114 u32 reserved2[2]; 115 #if defined(__BIG_ENDIAN) 116 u8 flags; 117 #define L4_KCQ_RESERVED3 (0x7<<0) 118 #define L4_KCQ_RESERVED3_SHIFT 0 119 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ 120 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 121 #define L4_KCQ_LAYER_CODE (0x7<<4) 122 #define L4_KCQ_LAYER_CODE_SHIFT 4 123 #define L4_KCQ_RESERVED4 (0x1<<7) 124 #define L4_KCQ_RESERVED4_SHIFT 7 125 u8 op_code; 126 u16 qe_self_seq; 127 #elif defined(__LITTLE_ENDIAN) 128 u16 qe_self_seq; 129 u8 op_code; 130 u8 flags; 131 #define L4_KCQ_RESERVED3 (0xF<<0) 132 #define L4_KCQ_RESERVED3_SHIFT 0 133 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ 134 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 135 #define L4_KCQ_LAYER_CODE (0x7<<4) 136 #define L4_KCQ_LAYER_CODE_SHIFT 4 137 #define L4_KCQ_RESERVED4 (0x1<<7) 138 #define L4_KCQ_RESERVED4_SHIFT 7 139 #endif 140 }; 141 142 143 /* 144 * L4 KCQ CQE PG upload 145 */ 146 struct l4_kcq_upload_pg { 147 u32 pg_cid; 148 #if defined(__BIG_ENDIAN) 149 u16 pg_status; 150 u16 pg_ipid_count; 151 #elif defined(__LITTLE_ENDIAN) 152 u16 pg_ipid_count; 153 u16 pg_status; 154 #endif 155 u32 reserved1[5]; 156 #if defined(__BIG_ENDIAN) 157 u8 flags; 158 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) 159 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 160 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) 161 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 162 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) 163 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 164 u8 op_code; 165 u16 qe_self_seq; 166 #elif defined(__LITTLE_ENDIAN) 167 u16 qe_self_seq; 168 u8 op_code; 169 u8 flags; 170 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) 171 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 172 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) 173 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 174 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) 175 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 176 #endif 177 }; 178 179 180 /* 181 * Gracefully close the connection request 182 */ 183 struct l4_kwq_close_req { 184 #if defined(__BIG_ENDIAN) 185 u8 flags; 186 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) 187 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 188 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) 189 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 190 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) 191 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 192 u8 op_code; 193 u16 reserved0; 194 #elif defined(__LITTLE_ENDIAN) 195 u16 reserved0; 196 u8 op_code; 197 u8 flags; 198 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) 199 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 200 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) 201 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 202 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) 203 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 204 #endif 205 u32 cid; 206 u32 reserved2[6]; 207 }; 208 209 210 /* 211 * The first request to be passed in order to establish connection in option2 212 */ 213 struct l4_kwq_connect_req1 { 214 #if defined(__BIG_ENDIAN) 215 u8 flags; 216 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) 217 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 218 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) 219 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 220 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) 221 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 222 u8 op_code; 223 u8 reserved0; 224 u8 conn_flags; 225 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) 226 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 227 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) 228 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 229 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) 230 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 231 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) 232 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 233 #elif defined(__LITTLE_ENDIAN) 234 u8 conn_flags; 235 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) 236 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 237 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) 238 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 239 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) 240 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 241 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) 242 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 243 u8 reserved0; 244 u8 op_code; 245 u8 flags; 246 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) 247 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 248 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) 249 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 250 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) 251 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 252 #endif 253 u32 cid; 254 u32 pg_cid; 255 u32 src_ip; 256 u32 dst_ip; 257 #if defined(__BIG_ENDIAN) 258 u16 dst_port; 259 u16 src_port; 260 #elif defined(__LITTLE_ENDIAN) 261 u16 src_port; 262 u16 dst_port; 263 #endif 264 #if defined(__BIG_ENDIAN) 265 u8 rsrv1[3]; 266 u8 tcp_flags; 267 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) 268 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 269 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) 270 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 271 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) 272 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 273 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) 274 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 275 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) 276 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 277 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) 278 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 279 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 280 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 281 #elif defined(__LITTLE_ENDIAN) 282 u8 tcp_flags; 283 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) 284 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 285 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) 286 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 287 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) 288 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 289 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) 290 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 291 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) 292 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 293 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) 294 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 295 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 296 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 297 u8 rsrv1[3]; 298 #endif 299 u32 rsrv2; 300 }; 301 302 303 /* 304 * The second ( optional )request to be passed in order to establish 305 * connection in option2 - for IPv6 only 306 */ 307 struct l4_kwq_connect_req2 { 308 #if defined(__BIG_ENDIAN) 309 u8 flags; 310 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) 311 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 312 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) 313 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 314 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) 315 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 316 u8 op_code; 317 u8 reserved0; 318 u8 rsrv; 319 #elif defined(__LITTLE_ENDIAN) 320 u8 rsrv; 321 u8 reserved0; 322 u8 op_code; 323 u8 flags; 324 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) 325 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 326 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) 327 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 328 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) 329 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 330 #endif 331 u32 reserved2; 332 u32 src_ip_v6_2; 333 u32 src_ip_v6_3; 334 u32 src_ip_v6_4; 335 u32 dst_ip_v6_2; 336 u32 dst_ip_v6_3; 337 u32 dst_ip_v6_4; 338 }; 339 340 341 /* 342 * The third ( and last )request to be passed in order to establish 343 * connection in option2 344 */ 345 struct l4_kwq_connect_req3 { 346 #if defined(__BIG_ENDIAN) 347 u8 flags; 348 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) 349 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 350 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) 351 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 352 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) 353 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 354 u8 op_code; 355 u16 reserved0; 356 #elif defined(__LITTLE_ENDIAN) 357 u16 reserved0; 358 u8 op_code; 359 u8 flags; 360 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) 361 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 362 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) 363 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 364 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) 365 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 366 #endif 367 u32 ka_timeout; 368 u32 ka_interval ; 369 #if defined(__BIG_ENDIAN) 370 u8 snd_seq_scale; 371 u8 ttl; 372 u8 tos; 373 u8 ka_max_probe_count; 374 #elif defined(__LITTLE_ENDIAN) 375 u8 ka_max_probe_count; 376 u8 tos; 377 u8 ttl; 378 u8 snd_seq_scale; 379 #endif 380 #if defined(__BIG_ENDIAN) 381 u16 pmtu; 382 u16 mss; 383 #elif defined(__LITTLE_ENDIAN) 384 u16 mss; 385 u16 pmtu; 386 #endif 387 u32 rcv_buf; 388 u32 snd_buf; 389 u32 seed; 390 }; 391 392 393 /* 394 * a KWQE request to offload a PG connection 395 */ 396 struct l4_kwq_offload_pg { 397 #if defined(__BIG_ENDIAN) 398 u8 flags; 399 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) 400 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 401 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) 402 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 403 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) 404 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 405 u8 op_code; 406 u16 reserved0; 407 #elif defined(__LITTLE_ENDIAN) 408 u16 reserved0; 409 u8 op_code; 410 u8 flags; 411 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) 412 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 413 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) 414 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 415 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) 416 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 417 #endif 418 #if defined(__BIG_ENDIAN) 419 u8 l2hdr_nbytes; 420 u8 pg_flags; 421 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) 422 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 423 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) 424 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 425 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) 426 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 427 u8 da0; 428 u8 da1; 429 #elif defined(__LITTLE_ENDIAN) 430 u8 da1; 431 u8 da0; 432 u8 pg_flags; 433 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) 434 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 435 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) 436 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 437 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) 438 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 439 u8 l2hdr_nbytes; 440 #endif 441 #if defined(__BIG_ENDIAN) 442 u8 da2; 443 u8 da3; 444 u8 da4; 445 u8 da5; 446 #elif defined(__LITTLE_ENDIAN) 447 u8 da5; 448 u8 da4; 449 u8 da3; 450 u8 da2; 451 #endif 452 #if defined(__BIG_ENDIAN) 453 u8 sa0; 454 u8 sa1; 455 u8 sa2; 456 u8 sa3; 457 #elif defined(__LITTLE_ENDIAN) 458 u8 sa3; 459 u8 sa2; 460 u8 sa1; 461 u8 sa0; 462 #endif 463 #if defined(__BIG_ENDIAN) 464 u8 sa4; 465 u8 sa5; 466 u16 etype; 467 #elif defined(__LITTLE_ENDIAN) 468 u16 etype; 469 u8 sa5; 470 u8 sa4; 471 #endif 472 #if defined(__BIG_ENDIAN) 473 u16 vlan_tag; 474 u16 ipid_start; 475 #elif defined(__LITTLE_ENDIAN) 476 u16 ipid_start; 477 u16 vlan_tag; 478 #endif 479 #if defined(__BIG_ENDIAN) 480 u16 ipid_count; 481 u16 reserved3; 482 #elif defined(__LITTLE_ENDIAN) 483 u16 reserved3; 484 u16 ipid_count; 485 #endif 486 u32 host_opaque; 487 }; 488 489 490 /* 491 * Abortively close the connection request 492 */ 493 struct l4_kwq_reset_req { 494 #if defined(__BIG_ENDIAN) 495 u8 flags; 496 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) 497 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 498 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) 499 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 500 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) 501 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 502 u8 op_code; 503 u16 reserved0; 504 #elif defined(__LITTLE_ENDIAN) 505 u16 reserved0; 506 u8 op_code; 507 u8 flags; 508 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) 509 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 510 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) 511 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 512 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) 513 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 514 #endif 515 u32 cid; 516 u32 reserved2[6]; 517 }; 518 519 520 /* 521 * a KWQE request to update a PG connection 522 */ 523 struct l4_kwq_update_pg { 524 #if defined(__BIG_ENDIAN) 525 u8 flags; 526 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) 527 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 528 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) 529 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 530 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) 531 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 532 u8 opcode; 533 u16 oper16; 534 #elif defined(__LITTLE_ENDIAN) 535 u16 oper16; 536 u8 opcode; 537 u8 flags; 538 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) 539 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 540 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) 541 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 542 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) 543 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 544 #endif 545 u32 pg_cid; 546 u32 pg_host_opaque; 547 #if defined(__BIG_ENDIAN) 548 u8 pg_valids; 549 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) 550 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 551 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) 552 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 553 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) 554 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 555 u8 pg_unused_a; 556 u16 pg_ipid_count; 557 #elif defined(__LITTLE_ENDIAN) 558 u16 pg_ipid_count; 559 u8 pg_unused_a; 560 u8 pg_valids; 561 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) 562 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 563 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) 564 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 565 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) 566 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 567 #endif 568 #if defined(__BIG_ENDIAN) 569 u16 reserverd3; 570 u8 da0; 571 u8 da1; 572 #elif defined(__LITTLE_ENDIAN) 573 u8 da1; 574 u8 da0; 575 u16 reserverd3; 576 #endif 577 #if defined(__BIG_ENDIAN) 578 u8 da2; 579 u8 da3; 580 u8 da4; 581 u8 da5; 582 #elif defined(__LITTLE_ENDIAN) 583 u8 da5; 584 u8 da4; 585 u8 da3; 586 u8 da2; 587 #endif 588 u32 reserved4; 589 u32 reserved5; 590 }; 591 592 593 /* 594 * a KWQE request to upload a PG or L4 context 595 */ 596 struct l4_kwq_upload { 597 #if defined(__BIG_ENDIAN) 598 u8 flags; 599 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) 600 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 601 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) 602 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 603 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) 604 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 605 u8 opcode; 606 u16 oper16; 607 #elif defined(__LITTLE_ENDIAN) 608 u16 oper16; 609 u8 opcode; 610 u8 flags; 611 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) 612 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 613 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) 614 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 615 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) 616 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 617 #endif 618 u32 cid; 619 u32 reserved2[6]; 620 }; 621 622 /* 623 * bnx2x structures 624 */ 625 626 /* 627 * The iscsi aggregative context of Cstorm 628 */ 629 struct cstorm_iscsi_ag_context { 630 u32 agg_vars1; 631 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) 632 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0 633 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) 634 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8 635 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) 636 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9 637 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) 638 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10 639 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) 640 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11 641 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) 642 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12 643 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) 644 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13 645 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) 646 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14 647 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) 648 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16 649 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) 650 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18 651 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) 652 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19 653 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) 654 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20 655 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21) 656 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21 657 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22) 658 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22 659 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) 660 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23 661 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) 662 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26 663 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) 664 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28 665 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) 666 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30 667 #if defined(__BIG_ENDIAN) 668 u8 __aux1_th; 669 u8 __aux1_val; 670 u16 __agg_vars2; 671 #elif defined(__LITTLE_ENDIAN) 672 u16 __agg_vars2; 673 u8 __aux1_val; 674 u8 __aux1_th; 675 #endif 676 u32 rel_seq; 677 u32 rel_seq_th; 678 #if defined(__BIG_ENDIAN) 679 u16 hq_cons; 680 u16 hq_prod; 681 #elif defined(__LITTLE_ENDIAN) 682 u16 hq_prod; 683 u16 hq_cons; 684 #endif 685 #if defined(__BIG_ENDIAN) 686 u8 __reserved62; 687 u8 __reserved61; 688 u8 __reserved60; 689 u8 __reserved59; 690 #elif defined(__LITTLE_ENDIAN) 691 u8 __reserved59; 692 u8 __reserved60; 693 u8 __reserved61; 694 u8 __reserved62; 695 #endif 696 #if defined(__BIG_ENDIAN) 697 u16 __reserved64; 698 u16 cq_u_prod; 699 #elif defined(__LITTLE_ENDIAN) 700 u16 cq_u_prod; 701 u16 __reserved64; 702 #endif 703 u32 __cq_u_prod1; 704 #if defined(__BIG_ENDIAN) 705 u16 __agg_vars3; 706 u16 cq_u_pend; 707 #elif defined(__LITTLE_ENDIAN) 708 u16 cq_u_pend; 709 u16 __agg_vars3; 710 #endif 711 #if defined(__BIG_ENDIAN) 712 u16 __aux2_th; 713 u16 aux2_val; 714 #elif defined(__LITTLE_ENDIAN) 715 u16 aux2_val; 716 u16 __aux2_th; 717 #endif 718 }; 719 720 /* 721 * The fcoe extra aggregative context section of Tstorm 722 */ 723 struct tstorm_fcoe_extra_ag_context_section { 724 u32 __agg_val1; 725 #if defined(__BIG_ENDIAN) 726 u8 __tcp_agg_vars2; 727 u8 __agg_val3; 728 u16 __agg_val2; 729 #elif defined(__LITTLE_ENDIAN) 730 u16 __agg_val2; 731 u8 __agg_val3; 732 u8 __tcp_agg_vars2; 733 #endif 734 #if defined(__BIG_ENDIAN) 735 u16 __agg_val5; 736 u8 __agg_val6; 737 u8 __tcp_agg_vars3; 738 #elif defined(__LITTLE_ENDIAN) 739 u8 __tcp_agg_vars3; 740 u8 __agg_val6; 741 u16 __agg_val5; 742 #endif 743 u32 __lcq_prod; 744 u32 rtt_seq; 745 u32 rtt_time; 746 u32 __reserved66; 747 u32 wnd_right_edge; 748 u32 tcp_agg_vars1; 749 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 750 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 751 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) 752 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 753 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 754 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 755 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 756 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 757 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) 758 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 759 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) 760 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 761 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) 762 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 763 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) 764 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9 765 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) 766 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 767 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) 768 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 769 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) 770 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 771 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) 772 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 773 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) 774 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 775 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) 776 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 777 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) 778 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 779 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) 780 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 781 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) 782 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 783 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) 784 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 785 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) 786 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 787 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) 788 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 789 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) 790 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 791 u32 snd_max; 792 u32 __lcq_cons; 793 u32 __reserved2; 794 }; 795 796 /* 797 * The fcoe aggregative context of Tstorm 798 */ 799 struct tstorm_fcoe_ag_context { 800 #if defined(__BIG_ENDIAN) 801 u16 ulp_credit; 802 u8 agg_vars1; 803 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 804 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 805 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 806 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 807 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 808 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 809 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 810 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 811 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) 812 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 813 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) 814 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 815 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) 816 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 817 u8 state; 818 #elif defined(__LITTLE_ENDIAN) 819 u8 state; 820 u8 agg_vars1; 821 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 822 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 823 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 824 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 825 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 826 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 827 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 828 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 829 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) 830 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 831 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) 832 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 833 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) 834 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 835 u16 ulp_credit; 836 #endif 837 #if defined(__BIG_ENDIAN) 838 u16 __agg_val4; 839 u16 agg_vars2; 840 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) 841 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 842 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) 843 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 844 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) 845 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 846 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) 847 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 848 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) 849 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 850 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) 851 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 852 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) 853 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 854 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) 855 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 856 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) 857 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 858 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) 859 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 860 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 861 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 862 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 863 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 864 #elif defined(__LITTLE_ENDIAN) 865 u16 agg_vars2; 866 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) 867 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 868 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) 869 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 870 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) 871 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 872 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) 873 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 874 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) 875 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 876 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) 877 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 878 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) 879 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 880 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) 881 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 882 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) 883 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 884 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) 885 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 886 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 887 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 888 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 889 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 890 u16 __agg_val4; 891 #endif 892 struct tstorm_fcoe_extra_ag_context_section __extra_section; 893 }; 894 895 896 897 /* 898 * The tcp aggregative context section of Tstorm 899 */ 900 struct tstorm_tcp_tcp_ag_context_section { 901 u32 __agg_val1; 902 #if defined(__BIG_ENDIAN) 903 u8 __tcp_agg_vars2; 904 u8 __agg_val3; 905 u16 __agg_val2; 906 #elif defined(__LITTLE_ENDIAN) 907 u16 __agg_val2; 908 u8 __agg_val3; 909 u8 __tcp_agg_vars2; 910 #endif 911 #if defined(__BIG_ENDIAN) 912 u16 __agg_val5; 913 u8 __agg_val6; 914 u8 __tcp_agg_vars3; 915 #elif defined(__LITTLE_ENDIAN) 916 u8 __tcp_agg_vars3; 917 u8 __agg_val6; 918 u16 __agg_val5; 919 #endif 920 u32 snd_nxt; 921 u32 rtt_seq; 922 u32 rtt_time; 923 u32 __reserved66; 924 u32 wnd_right_edge; 925 u32 tcp_agg_vars1; 926 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 927 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 928 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) 929 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 930 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 931 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 932 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 933 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 934 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) 935 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 936 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) 937 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 938 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) 939 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 940 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) 941 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 942 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) 943 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 944 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) 945 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 946 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) 947 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 948 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) 949 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 950 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) 951 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 952 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) 953 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 954 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) 955 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 956 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) 957 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 958 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) 959 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 960 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) 961 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 962 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) 963 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 964 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) 965 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 966 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) 967 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 968 u32 snd_max; 969 u32 snd_una; 970 u32 __reserved2; 971 }; 972 973 /* 974 * The iscsi aggregative context of Tstorm 975 */ 976 struct tstorm_iscsi_ag_context { 977 #if defined(__BIG_ENDIAN) 978 u16 ulp_credit; 979 u8 agg_vars1; 980 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 981 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 982 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 983 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 984 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 985 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 986 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 987 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 988 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) 989 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 990 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) 991 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 992 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) 993 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 994 u8 state; 995 #elif defined(__LITTLE_ENDIAN) 996 u8 state; 997 u8 agg_vars1; 998 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 999 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1000 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1001 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1002 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1003 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1004 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1005 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1006 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) 1007 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 1008 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) 1009 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 1010 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) 1011 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 1012 u16 ulp_credit; 1013 #endif 1014 #if defined(__BIG_ENDIAN) 1015 u16 __agg_val4; 1016 u16 agg_vars2; 1017 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) 1018 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 1019 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) 1020 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 1021 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) 1022 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 1023 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) 1024 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 1025 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) 1026 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 1027 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) 1028 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 1029 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) 1030 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 1031 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) 1032 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 1033 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) 1034 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 1035 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) 1036 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 1037 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 1038 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 1039 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 1040 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 1041 #elif defined(__LITTLE_ENDIAN) 1042 u16 agg_vars2; 1043 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) 1044 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 1045 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) 1046 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 1047 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) 1048 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 1049 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) 1050 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 1051 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) 1052 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 1053 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) 1054 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 1055 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) 1056 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 1057 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) 1058 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 1059 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) 1060 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 1061 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) 1062 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 1063 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 1064 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 1065 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 1066 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 1067 u16 __agg_val4; 1068 #endif 1069 struct tstorm_tcp_tcp_ag_context_section tcp; 1070 }; 1071 1072 1073 1074 /* 1075 * The fcoe aggregative context of Ustorm 1076 */ 1077 struct ustorm_fcoe_ag_context { 1078 #if defined(__BIG_ENDIAN) 1079 u8 __aux_counter_flags; 1080 u8 agg_vars2; 1081 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) 1082 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 1083 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) 1084 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 1085 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1086 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1087 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1088 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1089 u8 agg_vars1; 1090 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1091 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1092 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1093 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1094 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1095 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1096 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1097 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1098 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) 1099 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 1100 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1101 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1102 u8 state; 1103 #elif defined(__LITTLE_ENDIAN) 1104 u8 state; 1105 u8 agg_vars1; 1106 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1107 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1108 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1109 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1110 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1111 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1112 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1113 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1114 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) 1115 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 1116 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1117 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1118 u8 agg_vars2; 1119 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) 1120 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 1121 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) 1122 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 1123 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1124 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1125 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1126 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1127 u8 __aux_counter_flags; 1128 #endif 1129 #if defined(__BIG_ENDIAN) 1130 u8 cdu_usage; 1131 u8 agg_misc2; 1132 u16 pbf_tx_seq_ack; 1133 #elif defined(__LITTLE_ENDIAN) 1134 u16 pbf_tx_seq_ack; 1135 u8 agg_misc2; 1136 u8 cdu_usage; 1137 #endif 1138 u32 agg_misc4; 1139 #if defined(__BIG_ENDIAN) 1140 u8 agg_val3_th; 1141 u8 agg_val3; 1142 u16 agg_misc3; 1143 #elif defined(__LITTLE_ENDIAN) 1144 u16 agg_misc3; 1145 u8 agg_val3; 1146 u8 agg_val3_th; 1147 #endif 1148 u32 expired_task_id; 1149 u32 agg_misc4_th; 1150 #if defined(__BIG_ENDIAN) 1151 u16 cq_prod; 1152 u16 cq_cons; 1153 #elif defined(__LITTLE_ENDIAN) 1154 u16 cq_cons; 1155 u16 cq_prod; 1156 #endif 1157 #if defined(__BIG_ENDIAN) 1158 u16 __reserved2; 1159 u8 decision_rules; 1160 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) 1161 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 1162 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1163 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1164 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) 1165 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 1166 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) 1167 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 1168 u8 decision_rule_enable_bits; 1169 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) 1170 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 1171 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1172 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1173 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) 1174 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 1175 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1176 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1177 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) 1178 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 1179 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) 1180 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 1181 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1182 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1183 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1184 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1185 #elif defined(__LITTLE_ENDIAN) 1186 u8 decision_rule_enable_bits; 1187 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) 1188 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 1189 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1190 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1191 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) 1192 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 1193 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1194 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1195 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) 1196 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 1197 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) 1198 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 1199 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1200 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1201 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1202 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1203 u8 decision_rules; 1204 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) 1205 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 1206 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1207 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1208 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) 1209 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 1210 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) 1211 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 1212 u16 __reserved2; 1213 #endif 1214 }; 1215 1216 1217 /* 1218 * The iscsi aggregative context of Ustorm 1219 */ 1220 struct ustorm_iscsi_ag_context { 1221 #if defined(__BIG_ENDIAN) 1222 u8 __aux_counter_flags; 1223 u8 agg_vars2; 1224 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) 1225 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 1226 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) 1227 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 1228 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1229 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1230 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1231 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1232 u8 agg_vars1; 1233 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1234 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1235 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1236 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1237 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1238 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1239 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1240 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1241 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) 1242 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 1243 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1244 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1245 u8 state; 1246 #elif defined(__LITTLE_ENDIAN) 1247 u8 state; 1248 u8 agg_vars1; 1249 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1250 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1251 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1252 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1253 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1254 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1255 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1256 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1257 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) 1258 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 1259 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1260 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1261 u8 agg_vars2; 1262 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) 1263 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 1264 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) 1265 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 1266 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1267 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1268 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1269 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1270 u8 __aux_counter_flags; 1271 #endif 1272 #if defined(__BIG_ENDIAN) 1273 u8 cdu_usage; 1274 u8 agg_misc2; 1275 u16 __cq_local_comp_itt_val; 1276 #elif defined(__LITTLE_ENDIAN) 1277 u16 __cq_local_comp_itt_val; 1278 u8 agg_misc2; 1279 u8 cdu_usage; 1280 #endif 1281 u32 agg_misc4; 1282 #if defined(__BIG_ENDIAN) 1283 u8 agg_val3_th; 1284 u8 agg_val3; 1285 u16 agg_misc3; 1286 #elif defined(__LITTLE_ENDIAN) 1287 u16 agg_misc3; 1288 u8 agg_val3; 1289 u8 agg_val3_th; 1290 #endif 1291 u32 agg_val1; 1292 u32 agg_misc4_th; 1293 #if defined(__BIG_ENDIAN) 1294 u16 agg_val2_th; 1295 u16 agg_val2; 1296 #elif defined(__LITTLE_ENDIAN) 1297 u16 agg_val2; 1298 u16 agg_val2_th; 1299 #endif 1300 #if defined(__BIG_ENDIAN) 1301 u16 __reserved2; 1302 u8 decision_rules; 1303 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) 1304 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 1305 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1306 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1307 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) 1308 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 1309 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) 1310 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 1311 u8 decision_rule_enable_bits; 1312 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) 1313 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 1314 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1315 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1316 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) 1317 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 1318 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1319 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1320 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) 1321 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 1322 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) 1323 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 1324 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1325 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1326 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1327 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1328 #elif defined(__LITTLE_ENDIAN) 1329 u8 decision_rule_enable_bits; 1330 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) 1331 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 1332 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1333 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1334 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) 1335 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 1336 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1337 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1338 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) 1339 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 1340 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) 1341 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 1342 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1343 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1344 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1345 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1346 u8 decision_rules; 1347 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) 1348 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 1349 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1350 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1351 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) 1352 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 1353 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) 1354 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 1355 u16 __reserved2; 1356 #endif 1357 }; 1358 1359 1360 /* 1361 * The fcoe aggregative context section of Xstorm 1362 */ 1363 struct xstorm_fcoe_extra_ag_context_section { 1364 #if defined(__BIG_ENDIAN) 1365 u8 tcp_agg_vars1; 1366 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) 1367 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 1368 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1369 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1370 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1371 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1372 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) 1373 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 1374 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) 1375 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 1376 u8 __reserved_da_cnt; 1377 u16 __mtu; 1378 #elif defined(__LITTLE_ENDIAN) 1379 u16 __mtu; 1380 u8 __reserved_da_cnt; 1381 u8 tcp_agg_vars1; 1382 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) 1383 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 1384 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1385 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1386 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1387 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1388 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) 1389 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 1390 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) 1391 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 1392 #endif 1393 u32 snd_nxt; 1394 u32 tx_wnd; 1395 u32 __reserved55; 1396 u32 local_adv_wnd; 1397 #if defined(__BIG_ENDIAN) 1398 u8 __agg_val8_th; 1399 u8 __tx_dest; 1400 u16 tcp_agg_vars2; 1401 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) 1402 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 1403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) 1404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 1405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) 1406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 1407 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1408 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1409 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1410 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1411 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) 1412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 1413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) 1414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 1415 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1416 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1417 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) 1418 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 1419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1423 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1424 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1425 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1426 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1427 #elif defined(__LITTLE_ENDIAN) 1428 u16 tcp_agg_vars2; 1429 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) 1430 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 1431 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) 1432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 1433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) 1434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 1435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) 1440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 1441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) 1442 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 1443 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1444 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1445 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) 1446 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 1447 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1454 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1455 u8 __tx_dest; 1456 u8 __agg_val8_th; 1457 #endif 1458 u32 __sq_base_addr_lo; 1459 u32 __sq_base_addr_hi; 1460 u32 __xfrq_base_addr_lo; 1461 u32 __xfrq_base_addr_hi; 1462 #if defined(__BIG_ENDIAN) 1463 u16 __xfrq_cons; 1464 u16 __xfrq_prod; 1465 #elif defined(__LITTLE_ENDIAN) 1466 u16 __xfrq_prod; 1467 u16 __xfrq_cons; 1468 #endif 1469 #if defined(__BIG_ENDIAN) 1470 u8 __tcp_agg_vars5; 1471 u8 __tcp_agg_vars4; 1472 u8 __tcp_agg_vars3; 1473 u8 __reserved_force_pure_ack_cnt; 1474 #elif defined(__LITTLE_ENDIAN) 1475 u8 __reserved_force_pure_ack_cnt; 1476 u8 __tcp_agg_vars3; 1477 u8 __tcp_agg_vars4; 1478 u8 __tcp_agg_vars5; 1479 #endif 1480 u32 __tcp_agg_vars6; 1481 #if defined(__BIG_ENDIAN) 1482 u16 __agg_misc6; 1483 u16 __tcp_agg_vars7; 1484 #elif defined(__LITTLE_ENDIAN) 1485 u16 __tcp_agg_vars7; 1486 u16 __agg_misc6; 1487 #endif 1488 u32 __agg_val10; 1489 u32 __agg_val10_th; 1490 #if defined(__BIG_ENDIAN) 1491 u16 __reserved3; 1492 u8 __reserved2; 1493 u8 __da_only_cnt; 1494 #elif defined(__LITTLE_ENDIAN) 1495 u8 __da_only_cnt; 1496 u8 __reserved2; 1497 u16 __reserved3; 1498 #endif 1499 }; 1500 1501 /* 1502 * The fcoe aggregative context of Xstorm 1503 */ 1504 struct xstorm_fcoe_ag_context { 1505 #if defined(__BIG_ENDIAN) 1506 u16 agg_val1; 1507 u8 agg_vars1; 1508 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1509 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1510 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1511 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1512 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) 1513 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 1514 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) 1515 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 1516 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1517 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1518 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) 1519 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 1520 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1521 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1522 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) 1523 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 1524 u8 __state; 1525 #elif defined(__LITTLE_ENDIAN) 1526 u8 __state; 1527 u8 agg_vars1; 1528 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1529 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1530 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1531 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1532 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) 1533 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 1534 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) 1535 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 1536 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1537 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1538 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) 1539 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 1540 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1541 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1542 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) 1543 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 1544 u16 agg_val1; 1545 #endif 1546 #if defined(__BIG_ENDIAN) 1547 u8 cdu_reserved; 1548 u8 __agg_vars4; 1549 u8 agg_vars3; 1550 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1551 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1552 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) 1553 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 1554 u8 agg_vars2; 1555 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) 1556 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 1557 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1558 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1559 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1560 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1561 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1562 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1563 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1564 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1565 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1566 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1567 #elif defined(__LITTLE_ENDIAN) 1568 u8 agg_vars2; 1569 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) 1570 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 1571 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1572 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1573 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1574 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1575 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1576 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1577 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1578 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1579 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1580 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1581 u8 agg_vars3; 1582 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1583 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1584 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) 1585 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 1586 u8 __agg_vars4; 1587 u8 cdu_reserved; 1588 #endif 1589 u32 more_to_send; 1590 #if defined(__BIG_ENDIAN) 1591 u16 agg_vars5; 1592 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 1593 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 1594 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 1595 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 1596 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 1597 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 1598 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) 1599 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 1600 u16 sq_cons; 1601 #elif defined(__LITTLE_ENDIAN) 1602 u16 sq_cons; 1603 u16 agg_vars5; 1604 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 1605 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 1606 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 1607 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 1608 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 1609 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 1610 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) 1611 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 1612 #endif 1613 struct xstorm_fcoe_extra_ag_context_section __extra_section; 1614 #if defined(__BIG_ENDIAN) 1615 u16 agg_vars7; 1616 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 1617 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 1618 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) 1619 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 1620 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) 1621 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 1622 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 1623 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 1624 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) 1625 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 1626 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) 1627 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 1628 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 1629 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 1630 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) 1631 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 1632 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) 1633 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 1634 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) 1635 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 1636 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) 1637 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 1638 u8 agg_val3_th; 1639 u8 agg_vars6; 1640 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 1641 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 1642 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) 1643 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 1644 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) 1645 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 1646 #elif defined(__LITTLE_ENDIAN) 1647 u8 agg_vars6; 1648 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 1649 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 1650 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) 1651 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 1652 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) 1653 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 1654 u8 agg_val3_th; 1655 u16 agg_vars7; 1656 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 1657 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 1658 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) 1659 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 1660 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) 1661 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 1662 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 1663 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 1664 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) 1665 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 1666 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) 1667 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 1668 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 1669 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 1670 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) 1671 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 1672 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) 1673 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 1674 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) 1675 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 1676 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) 1677 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 1678 #endif 1679 #if defined(__BIG_ENDIAN) 1680 u16 __agg_val11_th; 1681 u16 __agg_val11; 1682 #elif defined(__LITTLE_ENDIAN) 1683 u16 __agg_val11; 1684 u16 __agg_val11_th; 1685 #endif 1686 #if defined(__BIG_ENDIAN) 1687 u8 __reserved1; 1688 u8 __agg_val6_th; 1689 u16 __agg_val9; 1690 #elif defined(__LITTLE_ENDIAN) 1691 u16 __agg_val9; 1692 u8 __agg_val6_th; 1693 u8 __reserved1; 1694 #endif 1695 #if defined(__BIG_ENDIAN) 1696 u16 confq_cons; 1697 u16 confq_prod; 1698 #elif defined(__LITTLE_ENDIAN) 1699 u16 confq_prod; 1700 u16 confq_cons; 1701 #endif 1702 u32 agg_vars8; 1703 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 1704 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0 1705 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 1706 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24 1707 #if defined(__BIG_ENDIAN) 1708 u16 agg_misc0; 1709 u16 sq_prod; 1710 #elif defined(__LITTLE_ENDIAN) 1711 u16 sq_prod; 1712 u16 agg_misc0; 1713 #endif 1714 #if defined(__BIG_ENDIAN) 1715 u8 agg_val3; 1716 u8 agg_val6; 1717 u8 agg_val5_th; 1718 u8 agg_val5; 1719 #elif defined(__LITTLE_ENDIAN) 1720 u8 agg_val5; 1721 u8 agg_val5_th; 1722 u8 agg_val6; 1723 u8 agg_val3; 1724 #endif 1725 #if defined(__BIG_ENDIAN) 1726 u16 __agg_misc1; 1727 u16 agg_limit1; 1728 #elif defined(__LITTLE_ENDIAN) 1729 u16 agg_limit1; 1730 u16 __agg_misc1; 1731 #endif 1732 u32 completion_seq; 1733 u32 confq_pbl_base_lo; 1734 u32 confq_pbl_base_hi; 1735 }; 1736 1737 1738 1739 /* 1740 * The tcp aggregative context section of Xstorm 1741 */ 1742 struct xstorm_tcp_tcp_ag_context_section { 1743 #if defined(__BIG_ENDIAN) 1744 u8 tcp_agg_vars1; 1745 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) 1746 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 1747 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1748 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1749 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1750 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1751 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) 1752 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 1753 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) 1754 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 1755 u8 __da_cnt; 1756 u16 mss; 1757 #elif defined(__LITTLE_ENDIAN) 1758 u16 mss; 1759 u8 __da_cnt; 1760 u8 tcp_agg_vars1; 1761 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) 1762 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 1763 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1764 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1765 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1766 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1767 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) 1768 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 1769 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) 1770 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 1771 #endif 1772 u32 snd_nxt; 1773 u32 tx_wnd; 1774 u32 snd_una; 1775 u32 local_adv_wnd; 1776 #if defined(__BIG_ENDIAN) 1777 u8 __agg_val8_th; 1778 u8 __tx_dest; 1779 u16 tcp_agg_vars2; 1780 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) 1781 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 1782 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) 1783 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 1784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) 1785 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 1786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1787 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1788 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1789 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1790 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) 1791 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 1792 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) 1793 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 1794 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1795 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1796 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) 1797 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 1798 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1803 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1804 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1805 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1806 #elif defined(__LITTLE_ENDIAN) 1807 u16 tcp_agg_vars2; 1808 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) 1809 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 1810 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) 1811 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 1812 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) 1813 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 1814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1817 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1818 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) 1819 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 1820 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) 1821 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 1822 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1823 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1824 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) 1825 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 1826 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1827 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1833 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1834 u8 __tx_dest; 1835 u8 __agg_val8_th; 1836 #endif 1837 u32 ack_to_far_end; 1838 u32 rto_timer; 1839 u32 ka_timer; 1840 u32 ts_to_echo; 1841 #if defined(__BIG_ENDIAN) 1842 u16 __agg_val7_th; 1843 u16 __agg_val7; 1844 #elif defined(__LITTLE_ENDIAN) 1845 u16 __agg_val7; 1846 u16 __agg_val7_th; 1847 #endif 1848 #if defined(__BIG_ENDIAN) 1849 u8 __tcp_agg_vars5; 1850 u8 __tcp_agg_vars4; 1851 u8 __tcp_agg_vars3; 1852 u8 __force_pure_ack_cnt; 1853 #elif defined(__LITTLE_ENDIAN) 1854 u8 __force_pure_ack_cnt; 1855 u8 __tcp_agg_vars3; 1856 u8 __tcp_agg_vars4; 1857 u8 __tcp_agg_vars5; 1858 #endif 1859 u32 tcp_agg_vars6; 1860 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) 1861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 1862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) 1863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1 1864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) 1865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 1866 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) 1867 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 1868 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) 1869 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 1870 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) 1871 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 1872 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) 1873 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 1874 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) 1875 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 1876 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) 1877 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 1878 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) 1879 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 1880 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) 1881 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 1882 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) 1883 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 1884 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) 1885 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 1886 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) 1887 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 1888 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) 1889 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 1890 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) 1891 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 1892 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) 1893 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 1894 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) 1895 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 1896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) 1897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 1898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) 1899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 1900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) 1901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 1902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) 1903 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 1904 #if defined(__BIG_ENDIAN) 1905 u16 __agg_misc6; 1906 u16 __tcp_agg_vars7; 1907 #elif defined(__LITTLE_ENDIAN) 1908 u16 __tcp_agg_vars7; 1909 u16 __agg_misc6; 1910 #endif 1911 u32 __agg_val10; 1912 u32 __agg_val10_th; 1913 #if defined(__BIG_ENDIAN) 1914 u16 __reserved3; 1915 u8 __reserved2; 1916 u8 __da_only_cnt; 1917 #elif defined(__LITTLE_ENDIAN) 1918 u8 __da_only_cnt; 1919 u8 __reserved2; 1920 u16 __reserved3; 1921 #endif 1922 }; 1923 1924 /* 1925 * The iscsi aggregative context of Xstorm 1926 */ 1927 struct xstorm_iscsi_ag_context { 1928 #if defined(__BIG_ENDIAN) 1929 u16 agg_val1; 1930 u8 agg_vars1; 1931 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1932 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1933 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1934 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1935 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1936 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1937 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1938 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1939 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1940 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1941 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) 1942 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 1943 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1944 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1945 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 1946 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 1947 u8 state; 1948 #elif defined(__LITTLE_ENDIAN) 1949 u8 state; 1950 u8 agg_vars1; 1951 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1952 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1953 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1954 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1955 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1956 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1957 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1958 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1959 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1960 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1961 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) 1962 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 1963 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1964 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1965 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 1966 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 1967 u16 agg_val1; 1968 #endif 1969 #if defined(__BIG_ENDIAN) 1970 u8 cdu_reserved; 1971 u8 __agg_vars4; 1972 u8 agg_vars3; 1973 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1974 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1975 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 1976 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 1977 u8 agg_vars2; 1978 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) 1979 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 1980 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1981 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1982 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1983 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1984 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1985 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1986 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1987 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1988 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1989 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1990 #elif defined(__LITTLE_ENDIAN) 1991 u8 agg_vars2; 1992 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) 1993 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 1994 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1995 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1996 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1997 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1998 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1999 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2000 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2001 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2002 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 2003 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 2004 u8 agg_vars3; 2005 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2006 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2007 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2008 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2009 u8 __agg_vars4; 2010 u8 cdu_reserved; 2011 #endif 2012 u32 more_to_send; 2013 #if defined(__BIG_ENDIAN) 2014 u16 agg_vars5; 2015 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2016 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2017 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2018 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2019 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2020 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2021 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2022 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2023 u16 sq_cons; 2024 #elif defined(__LITTLE_ENDIAN) 2025 u16 sq_cons; 2026 u16 agg_vars5; 2027 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2028 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2029 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2030 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2031 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2032 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2033 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2034 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2035 #endif 2036 struct xstorm_tcp_tcp_ag_context_section tcp; 2037 #if defined(__BIG_ENDIAN) 2038 u16 agg_vars7; 2039 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2040 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2041 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2042 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2043 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2044 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2045 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2046 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2047 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) 2048 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 2049 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2050 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2051 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2052 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2053 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2054 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2055 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2056 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2057 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2058 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2059 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2060 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2061 u8 agg_val3_th; 2062 u8 agg_vars6; 2063 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2064 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2065 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2066 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2067 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2068 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2069 #elif defined(__LITTLE_ENDIAN) 2070 u8 agg_vars6; 2071 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2072 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2073 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2074 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2075 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2076 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2077 u8 agg_val3_th; 2078 u16 agg_vars7; 2079 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2080 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2081 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2082 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2083 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2084 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2085 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2086 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2087 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) 2088 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 2089 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2090 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2091 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2092 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2093 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2094 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2095 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2096 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2097 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2098 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2099 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2100 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2101 #endif 2102 #if defined(__BIG_ENDIAN) 2103 u16 __agg_val11_th; 2104 u16 __gen_data; 2105 #elif defined(__LITTLE_ENDIAN) 2106 u16 __gen_data; 2107 u16 __agg_val11_th; 2108 #endif 2109 #if defined(__BIG_ENDIAN) 2110 u8 __reserved1; 2111 u8 __agg_val6_th; 2112 u16 __agg_val9; 2113 #elif defined(__LITTLE_ENDIAN) 2114 u16 __agg_val9; 2115 u8 __agg_val6_th; 2116 u8 __reserved1; 2117 #endif 2118 #if defined(__BIG_ENDIAN) 2119 u16 hq_prod; 2120 u16 hq_cons; 2121 #elif defined(__LITTLE_ENDIAN) 2122 u16 hq_cons; 2123 u16 hq_prod; 2124 #endif 2125 u32 agg_vars8; 2126 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 2127 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0 2128 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 2129 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24 2130 #if defined(__BIG_ENDIAN) 2131 u16 r2tq_prod; 2132 u16 sq_prod; 2133 #elif defined(__LITTLE_ENDIAN) 2134 u16 sq_prod; 2135 u16 r2tq_prod; 2136 #endif 2137 #if defined(__BIG_ENDIAN) 2138 u8 agg_val3; 2139 u8 agg_val6; 2140 u8 agg_val5_th; 2141 u8 agg_val5; 2142 #elif defined(__LITTLE_ENDIAN) 2143 u8 agg_val5; 2144 u8 agg_val5_th; 2145 u8 agg_val6; 2146 u8 agg_val3; 2147 #endif 2148 #if defined(__BIG_ENDIAN) 2149 u16 __agg_misc1; 2150 u16 agg_limit1; 2151 #elif defined(__LITTLE_ENDIAN) 2152 u16 agg_limit1; 2153 u16 __agg_misc1; 2154 #endif 2155 u32 hq_cons_tcp_seq; 2156 u32 exp_stat_sn; 2157 u32 rst_seq_num; 2158 }; 2159 2160 2161 /* 2162 * The L5cm aggregative context of XStorm 2163 */ 2164 struct xstorm_l5cm_ag_context { 2165 #if defined(__BIG_ENDIAN) 2166 u16 agg_val1; 2167 u8 agg_vars1; 2168 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 2169 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 2170 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 2171 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 2172 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 2173 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 2174 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 2175 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 2176 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 2177 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 2178 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5) 2179 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5 2180 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 2181 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 2182 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 2183 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 2184 u8 state; 2185 #elif defined(__LITTLE_ENDIAN) 2186 u8 state; 2187 u8 agg_vars1; 2188 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 2189 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 2190 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 2191 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 2192 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 2193 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 2194 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 2195 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 2196 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 2197 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 2198 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5) 2199 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5 2200 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 2201 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 2202 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 2203 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 2204 u16 agg_val1; 2205 #endif 2206 #if defined(__BIG_ENDIAN) 2207 u8 cdu_reserved; 2208 u8 __agg_vars4; 2209 u8 agg_vars3; 2210 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2211 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2212 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2213 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2214 u8 agg_vars2; 2215 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0) 2216 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0 2217 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 2218 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 2219 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3) 2220 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2221 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2222 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2223 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2224 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2225 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7) 2226 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7 2227 #elif defined(__LITTLE_ENDIAN) 2228 u8 agg_vars2; 2229 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0) 2230 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0 2231 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 2232 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 2233 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3) 2234 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2235 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2236 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2237 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2238 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2239 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7) 2240 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7 2241 u8 agg_vars3; 2242 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2243 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2244 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2245 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2246 u8 __agg_vars4; 2247 u8 cdu_reserved; 2248 #endif 2249 u32 more_to_send; 2250 #if defined(__BIG_ENDIAN) 2251 u16 agg_vars5; 2252 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2253 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2254 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2255 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2256 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2257 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2258 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2259 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2260 u16 agg_val4_th; 2261 #elif defined(__LITTLE_ENDIAN) 2262 u16 agg_val4_th; 2263 u16 agg_vars5; 2264 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2265 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2266 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2267 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2268 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2269 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2270 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2271 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2272 #endif 2273 struct xstorm_tcp_tcp_ag_context_section tcp; 2274 #if defined(__BIG_ENDIAN) 2275 u16 agg_vars7; 2276 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2277 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2278 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2279 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2280 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2281 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2282 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2283 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2284 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8) 2285 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8 2286 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2287 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2288 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2289 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2290 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2291 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2292 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2293 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2294 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2295 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2296 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2297 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2298 u8 agg_val3_th; 2299 u8 agg_vars6; 2300 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2301 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2302 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2303 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2304 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2305 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2306 #elif defined(__LITTLE_ENDIAN) 2307 u8 agg_vars6; 2308 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2309 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2310 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2311 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2312 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2313 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2314 u8 agg_val3_th; 2315 u16 agg_vars7; 2316 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2317 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2318 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2319 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2320 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2321 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2322 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2323 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2324 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8) 2325 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8 2326 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2327 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2328 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2329 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2330 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2331 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2332 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2333 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2334 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2335 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2336 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2337 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2338 #endif 2339 #if defined(__BIG_ENDIAN) 2340 u16 __agg_val11_th; 2341 u16 __gen_data; 2342 #elif defined(__LITTLE_ENDIAN) 2343 u16 __gen_data; 2344 u16 __agg_val11_th; 2345 #endif 2346 #if defined(__BIG_ENDIAN) 2347 u8 __reserved1; 2348 u8 __agg_val6_th; 2349 u16 __agg_val9; 2350 #elif defined(__LITTLE_ENDIAN) 2351 u16 __agg_val9; 2352 u8 __agg_val6_th; 2353 u8 __reserved1; 2354 #endif 2355 #if defined(__BIG_ENDIAN) 2356 u16 agg_val2_th; 2357 u16 agg_val2; 2358 #elif defined(__LITTLE_ENDIAN) 2359 u16 agg_val2; 2360 u16 agg_val2_th; 2361 #endif 2362 u32 agg_vars8; 2363 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 2364 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2_SHIFT 0 2365 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 2366 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3_SHIFT 24 2367 #if defined(__BIG_ENDIAN) 2368 u16 agg_misc0; 2369 u16 agg_val4; 2370 #elif defined(__LITTLE_ENDIAN) 2371 u16 agg_val4; 2372 u16 agg_misc0; 2373 #endif 2374 #if defined(__BIG_ENDIAN) 2375 u8 agg_val3; 2376 u8 agg_val6; 2377 u8 agg_val5_th; 2378 u8 agg_val5; 2379 #elif defined(__LITTLE_ENDIAN) 2380 u8 agg_val5; 2381 u8 agg_val5_th; 2382 u8 agg_val6; 2383 u8 agg_val3; 2384 #endif 2385 #if defined(__BIG_ENDIAN) 2386 u16 __agg_misc1; 2387 u16 agg_limit1; 2388 #elif defined(__LITTLE_ENDIAN) 2389 u16 agg_limit1; 2390 u16 __agg_misc1; 2391 #endif 2392 u32 completion_seq; 2393 u32 agg_misc4; 2394 u32 rst_seq_num; 2395 }; 2396 2397 /* 2398 * ABTS info $$KEEP_ENDIANNESS$$ 2399 */ 2400 struct fcoe_abts_info { 2401 __le16 aborted_task_id; 2402 __le16 reserved0; 2403 __le32 reserved1; 2404 }; 2405 2406 2407 /* 2408 * Fixed size structure in order to plant it in Union structure 2409 * $$KEEP_ENDIANNESS$$ 2410 */ 2411 struct fcoe_abts_rsp_union { 2412 u8 r_ctl; 2413 u8 rsrv[3]; 2414 __le32 abts_rsp_payload[7]; 2415 }; 2416 2417 2418 /* 2419 * 4 regs size $$KEEP_ENDIANNESS$$ 2420 */ 2421 struct fcoe_bd_ctx { 2422 __le32 buf_addr_hi; 2423 __le32 buf_addr_lo; 2424 __le16 buf_len; 2425 __le16 rsrv0; 2426 __le16 flags; 2427 __le16 rsrv1; 2428 }; 2429 2430 2431 /* 2432 * FCoE cached sges context $$KEEP_ENDIANNESS$$ 2433 */ 2434 struct fcoe_cached_sge_ctx { 2435 struct regpair cur_buf_addr; 2436 __le16 cur_buf_rem; 2437 __le16 second_buf_rem; 2438 struct regpair second_buf_addr; 2439 }; 2440 2441 2442 /* 2443 * Cleanup info $$KEEP_ENDIANNESS$$ 2444 */ 2445 struct fcoe_cleanup_info { 2446 __le16 cleaned_task_id; 2447 __le16 rolled_tx_seq_cnt; 2448 __le32 rolled_tx_data_offset; 2449 }; 2450 2451 2452 /* 2453 * Fcp RSP flags $$KEEP_ENDIANNESS$$ 2454 */ 2455 struct fcoe_fcp_rsp_flags { 2456 u8 flags; 2457 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) 2458 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 2459 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) 2460 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 2461 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) 2462 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 2463 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) 2464 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 2465 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) 2466 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 2467 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) 2468 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 2469 }; 2470 2471 /* 2472 * Fcp RSP payload $$KEEP_ENDIANNESS$$ 2473 */ 2474 struct fcoe_fcp_rsp_payload { 2475 struct regpair reserved0; 2476 __le32 fcp_resid; 2477 u8 scsi_status_code; 2478 struct fcoe_fcp_rsp_flags fcp_flags; 2479 __le16 retry_delay_timer; 2480 __le32 fcp_rsp_len; 2481 __le32 fcp_sns_len; 2482 }; 2483 2484 /* 2485 * Fixed size structure in order to plant it in Union structure 2486 * $$KEEP_ENDIANNESS$$ 2487 */ 2488 struct fcoe_fcp_rsp_union { 2489 struct fcoe_fcp_rsp_payload payload; 2490 struct regpair reserved0; 2491 }; 2492 2493 /* 2494 * FC header $$KEEP_ENDIANNESS$$ 2495 */ 2496 struct fcoe_fc_hdr { 2497 u8 s_id[3]; 2498 u8 cs_ctl; 2499 u8 d_id[3]; 2500 u8 r_ctl; 2501 __le16 seq_cnt; 2502 u8 df_ctl; 2503 u8 seq_id; 2504 u8 f_ctl[3]; 2505 u8 type; 2506 __le32 parameters; 2507 __le16 rx_id; 2508 __le16 ox_id; 2509 }; 2510 2511 /* 2512 * FC header union $$KEEP_ENDIANNESS$$ 2513 */ 2514 struct fcoe_mp_rsp_union { 2515 struct fcoe_fc_hdr fc_hdr; 2516 __le32 mp_payload_len; 2517 __le32 rsrv; 2518 }; 2519 2520 /* 2521 * Completion information $$KEEP_ENDIANNESS$$ 2522 */ 2523 union fcoe_comp_flow_info { 2524 struct fcoe_fcp_rsp_union fcp_rsp; 2525 struct fcoe_abts_rsp_union abts_rsp; 2526 struct fcoe_mp_rsp_union mp_rsp; 2527 __le32 opaque[8]; 2528 }; 2529 2530 2531 /* 2532 * External ABTS info $$KEEP_ENDIANNESS$$ 2533 */ 2534 struct fcoe_ext_abts_info { 2535 __le32 rsrv0[6]; 2536 struct fcoe_abts_info ctx; 2537 }; 2538 2539 2540 /* 2541 * External cleanup info $$KEEP_ENDIANNESS$$ 2542 */ 2543 struct fcoe_ext_cleanup_info { 2544 __le32 rsrv0[6]; 2545 struct fcoe_cleanup_info ctx; 2546 }; 2547 2548 2549 /* 2550 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$ 2551 */ 2552 struct fcoe_fw_tx_seq_ctx { 2553 __le32 data_offset; 2554 __le16 seq_cnt; 2555 __le16 rsrv0; 2556 }; 2557 2558 /* 2559 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$ 2560 */ 2561 struct fcoe_ext_fw_tx_seq_ctx { 2562 __le32 rsrv0[6]; 2563 struct fcoe_fw_tx_seq_ctx ctx; 2564 }; 2565 2566 2567 /* 2568 * FCoE multiple sges context $$KEEP_ENDIANNESS$$ 2569 */ 2570 struct fcoe_mul_sges_ctx { 2571 struct regpair cur_sge_addr; 2572 __le16 cur_sge_off; 2573 u8 cur_sge_idx; 2574 u8 sgl_size; 2575 }; 2576 2577 /* 2578 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$ 2579 */ 2580 struct fcoe_ext_mul_sges_ctx { 2581 struct fcoe_mul_sges_ctx mul_sgl; 2582 struct regpair rsrv0; 2583 }; 2584 2585 2586 /* 2587 * FCP CMD payload $$KEEP_ENDIANNESS$$ 2588 */ 2589 struct fcoe_fcp_cmd_payload { 2590 __le32 opaque[8]; 2591 }; 2592 2593 2594 2595 2596 2597 /* 2598 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$ 2599 */ 2600 struct fcoe_fcp_xfr_rdy_payload { 2601 __le32 burst_len; 2602 __le32 data_ro; 2603 }; 2604 2605 2606 /* 2607 * FC frame $$KEEP_ENDIANNESS$$ 2608 */ 2609 struct fcoe_fc_frame { 2610 struct fcoe_fc_hdr fc_hdr; 2611 __le32 reserved0[2]; 2612 }; 2613 2614 2615 2616 2617 /* 2618 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$ 2619 */ 2620 union fcoe_kcqe_params { 2621 __le32 reserved0[4]; 2622 }; 2623 2624 /* 2625 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$ 2626 */ 2627 struct fcoe_kcqe { 2628 __le32 fcoe_conn_id; 2629 __le32 completion_status; 2630 __le32 fcoe_conn_context_id; 2631 union fcoe_kcqe_params params; 2632 __le16 qe_self_seq; 2633 u8 op_code; 2634 u8 flags; 2635 #define FCOE_KCQE_RESERVED0 (0x7<<0) 2636 #define FCOE_KCQE_RESERVED0_SHIFT 0 2637 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) 2638 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 2639 #define FCOE_KCQE_LAYER_CODE (0x7<<4) 2640 #define FCOE_KCQE_LAYER_CODE_SHIFT 4 2641 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 2642 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 2643 }; 2644 2645 2646 2647 /* 2648 * FCoE KWQE header $$KEEP_ENDIANNESS$$ 2649 */ 2650 struct fcoe_kwqe_header { 2651 u8 op_code; 2652 u8 flags; 2653 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 2654 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 2655 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) 2656 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 2657 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 2658 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 2659 }; 2660 2661 /* 2662 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$ 2663 */ 2664 struct fcoe_kwqe_init1 { 2665 __le16 num_tasks; 2666 struct fcoe_kwqe_header hdr; 2667 __le32 task_list_pbl_addr_lo; 2668 __le32 task_list_pbl_addr_hi; 2669 __le32 dummy_buffer_addr_lo; 2670 __le32 dummy_buffer_addr_hi; 2671 __le16 sq_num_wqes; 2672 __le16 rq_num_wqes; 2673 __le16 rq_buffer_log_size; 2674 __le16 cq_num_wqes; 2675 __le16 mtu; 2676 u8 num_sessions_log; 2677 u8 flags; 2678 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 2679 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 2680 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) 2681 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 2682 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 2683 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 2684 }; 2685 2686 /* 2687 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$ 2688 */ 2689 struct fcoe_kwqe_init2 { 2690 u8 hsi_major_version; 2691 u8 hsi_minor_version; 2692 struct fcoe_kwqe_header hdr; 2693 __le32 hash_tbl_pbl_addr_lo; 2694 __le32 hash_tbl_pbl_addr_hi; 2695 __le32 t2_hash_tbl_addr_lo; 2696 __le32 t2_hash_tbl_addr_hi; 2697 __le32 t2_ptr_hash_tbl_addr_lo; 2698 __le32 t2_ptr_hash_tbl_addr_hi; 2699 __le32 free_list_count; 2700 }; 2701 2702 /* 2703 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$ 2704 */ 2705 struct fcoe_kwqe_init3 { 2706 __le16 reserved0; 2707 struct fcoe_kwqe_header hdr; 2708 __le32 error_bit_map_lo; 2709 __le32 error_bit_map_hi; 2710 u8 perf_config; 2711 u8 reserved21[3]; 2712 __le32 reserved2[4]; 2713 }; 2714 2715 /* 2716 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$ 2717 */ 2718 struct fcoe_kwqe_conn_offload1 { 2719 __le16 fcoe_conn_id; 2720 struct fcoe_kwqe_header hdr; 2721 __le32 sq_addr_lo; 2722 __le32 sq_addr_hi; 2723 __le32 rq_pbl_addr_lo; 2724 __le32 rq_pbl_addr_hi; 2725 __le32 rq_first_pbe_addr_lo; 2726 __le32 rq_first_pbe_addr_hi; 2727 __le16 rq_prod; 2728 __le16 reserved0; 2729 }; 2730 2731 /* 2732 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$ 2733 */ 2734 struct fcoe_kwqe_conn_offload2 { 2735 __le16 tx_max_fc_pay_len; 2736 struct fcoe_kwqe_header hdr; 2737 __le32 cq_addr_lo; 2738 __le32 cq_addr_hi; 2739 __le32 xferq_addr_lo; 2740 __le32 xferq_addr_hi; 2741 __le32 conn_db_addr_lo; 2742 __le32 conn_db_addr_hi; 2743 __le32 reserved1; 2744 }; 2745 2746 /* 2747 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$ 2748 */ 2749 struct fcoe_kwqe_conn_offload3 { 2750 __le16 vlan_tag; 2751 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 2752 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 2753 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 2754 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 2755 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 2756 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 2757 struct fcoe_kwqe_header hdr; 2758 u8 s_id[3]; 2759 u8 tx_max_conc_seqs_c3; 2760 u8 d_id[3]; 2761 u8 flags; 2762 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 2763 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 2764 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) 2765 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 2766 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) 2767 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 2768 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) 2769 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 2770 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) 2771 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 2772 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) 2773 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 2774 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) 2775 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 2776 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 2777 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 2778 __le32 reserved; 2779 __le32 confq_first_pbe_addr_lo; 2780 __le32 confq_first_pbe_addr_hi; 2781 __le16 tx_total_conc_seqs; 2782 __le16 rx_max_fc_pay_len; 2783 __le16 rx_total_conc_seqs; 2784 u8 rx_max_conc_seqs_c3; 2785 u8 rx_open_seqs_exch_c3; 2786 }; 2787 2788 /* 2789 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$ 2790 */ 2791 struct fcoe_kwqe_conn_offload4 { 2792 u8 e_d_tov_timer_val; 2793 u8 reserved2; 2794 struct fcoe_kwqe_header hdr; 2795 u8 src_mac_addr_lo[2]; 2796 u8 src_mac_addr_mid[2]; 2797 u8 src_mac_addr_hi[2]; 2798 u8 dst_mac_addr_hi[2]; 2799 u8 dst_mac_addr_lo[2]; 2800 u8 dst_mac_addr_mid[2]; 2801 __le32 lcq_addr_lo; 2802 __le32 lcq_addr_hi; 2803 __le32 confq_pbl_base_addr_lo; 2804 __le32 confq_pbl_base_addr_hi; 2805 }; 2806 2807 /* 2808 * FCoE connection enable request $$KEEP_ENDIANNESS$$ 2809 */ 2810 struct fcoe_kwqe_conn_enable_disable { 2811 __le16 reserved0; 2812 struct fcoe_kwqe_header hdr; 2813 u8 src_mac_addr_lo[2]; 2814 u8 src_mac_addr_mid[2]; 2815 u8 src_mac_addr_hi[2]; 2816 u16 vlan_tag; 2817 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 2818 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 2819 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) 2820 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 2821 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 2822 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 2823 u8 dst_mac_addr_lo[2]; 2824 u8 dst_mac_addr_mid[2]; 2825 u8 dst_mac_addr_hi[2]; 2826 __le16 reserved1; 2827 u8 s_id[3]; 2828 u8 vlan_flag; 2829 u8 d_id[3]; 2830 u8 reserved3; 2831 __le32 context_id; 2832 __le32 conn_id; 2833 __le32 reserved4; 2834 }; 2835 2836 /* 2837 * FCoE connection destroy request $$KEEP_ENDIANNESS$$ 2838 */ 2839 struct fcoe_kwqe_conn_destroy { 2840 __le16 reserved0; 2841 struct fcoe_kwqe_header hdr; 2842 __le32 context_id; 2843 __le32 conn_id; 2844 __le32 reserved1[5]; 2845 }; 2846 2847 /* 2848 * FCoe destroy request $$KEEP_ENDIANNESS$$ 2849 */ 2850 struct fcoe_kwqe_destroy { 2851 __le16 reserved0; 2852 struct fcoe_kwqe_header hdr; 2853 __le32 reserved1[7]; 2854 }; 2855 2856 /* 2857 * FCoe statistics request $$KEEP_ENDIANNESS$$ 2858 */ 2859 struct fcoe_kwqe_stat { 2860 __le16 reserved0; 2861 struct fcoe_kwqe_header hdr; 2862 __le32 stat_params_addr_lo; 2863 __le32 stat_params_addr_hi; 2864 __le32 reserved1[5]; 2865 }; 2866 2867 /* 2868 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$ 2869 */ 2870 union fcoe_kwqe { 2871 struct fcoe_kwqe_init1 init1; 2872 struct fcoe_kwqe_init2 init2; 2873 struct fcoe_kwqe_init3 init3; 2874 struct fcoe_kwqe_conn_offload1 conn_offload1; 2875 struct fcoe_kwqe_conn_offload2 conn_offload2; 2876 struct fcoe_kwqe_conn_offload3 conn_offload3; 2877 struct fcoe_kwqe_conn_offload4 conn_offload4; 2878 struct fcoe_kwqe_conn_enable_disable conn_enable_disable; 2879 struct fcoe_kwqe_conn_destroy conn_destroy; 2880 struct fcoe_kwqe_destroy destroy; 2881 struct fcoe_kwqe_stat statistics; 2882 }; 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 /* 2900 * TX SGL context $$KEEP_ENDIANNESS$$ 2901 */ 2902 union fcoe_sgl_union_ctx { 2903 struct fcoe_cached_sge_ctx cached_sge; 2904 struct fcoe_ext_mul_sges_ctx sgl; 2905 __le32 opaque[5]; 2906 }; 2907 2908 /* 2909 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$ 2910 */ 2911 struct fcoe_read_flow_info { 2912 union fcoe_sgl_union_ctx sgl_ctx; 2913 __le32 rsrv0[3]; 2914 }; 2915 2916 2917 /* 2918 * Fcoe stat context $$KEEP_ENDIANNESS$$ 2919 */ 2920 struct fcoe_s_stat_ctx { 2921 u8 flags; 2922 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) 2923 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 2924 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) 2925 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 2926 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) 2927 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 2928 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) 2929 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 2930 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) 2931 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4 2932 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) 2933 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 2934 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) 2935 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 2936 }; 2937 2938 /* 2939 * Fcoe rx seq context $$KEEP_ENDIANNESS$$ 2940 */ 2941 struct fcoe_rx_seq_ctx { 2942 u8 seq_id; 2943 struct fcoe_s_stat_ctx s_stat; 2944 __le16 seq_cnt; 2945 __le32 low_exp_ro; 2946 __le32 high_exp_ro; 2947 }; 2948 2949 2950 /* 2951 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$ 2952 */ 2953 union fcoe_rx_wr_union_ctx { 2954 struct fcoe_read_flow_info read_info; 2955 union fcoe_comp_flow_info comp_info; 2956 __le32 opaque[8]; 2957 }; 2958 2959 2960 2961 /* 2962 * FCoE SQ element $$KEEP_ENDIANNESS$$ 2963 */ 2964 struct fcoe_sqe { 2965 __le16 wqe; 2966 #define FCOE_SQE_TASK_ID (0x7FFF<<0) 2967 #define FCOE_SQE_TASK_ID_SHIFT 0 2968 #define FCOE_SQE_TOGGLE_BIT (0x1<<15) 2969 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15 2970 }; 2971 2972 2973 2974 /* 2975 * 14 regs $$KEEP_ENDIANNESS$$ 2976 */ 2977 struct fcoe_tce_tx_only { 2978 union fcoe_sgl_union_ctx sgl_ctx; 2979 __le32 rsrv0; 2980 }; 2981 2982 /* 2983 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$ 2984 */ 2985 union fcoe_tx_wr_rx_rd_union_ctx { 2986 struct fcoe_fc_frame tx_frame; 2987 struct fcoe_fcp_cmd_payload fcp_cmd; 2988 struct fcoe_ext_cleanup_info cleanup; 2989 struct fcoe_ext_abts_info abts; 2990 struct fcoe_ext_fw_tx_seq_ctx tx_seq; 2991 __le32 opaque[8]; 2992 }; 2993 2994 /* 2995 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$ 2996 */ 2997 struct fcoe_tce_tx_wr_rx_rd_const { 2998 u8 init_flags; 2999 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) 3000 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0 3001 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) 3002 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3 3003 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) 3004 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4 3005 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) 3006 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5 3007 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) 3008 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7 3009 u8 tx_flags; 3010 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) 3011 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0 3012 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) 3013 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1 3014 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) 3015 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5 3016 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) 3017 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6 3018 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7) 3019 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7 3020 __le16 rsrv3; 3021 __le32 verify_tx_seq; 3022 }; 3023 3024 /* 3025 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$ 3026 */ 3027 struct fcoe_tce_tx_wr_rx_rd { 3028 union fcoe_tx_wr_rx_rd_union_ctx union_ctx; 3029 struct fcoe_tce_tx_wr_rx_rd_const const_ctx; 3030 }; 3031 3032 /* 3033 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$ 3034 */ 3035 struct fcoe_tce_rx_wr_tx_rd_const { 3036 __le32 data_2_trns; 3037 __le32 init_flags; 3038 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) 3039 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0 3040 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) 3041 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24 3042 }; 3043 3044 /* 3045 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$ 3046 */ 3047 struct fcoe_tce_rx_wr_tx_rd_var { 3048 __le16 rx_flags; 3049 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) 3050 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0 3051 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) 3052 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4 3053 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) 3054 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7 3055 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) 3056 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8 3057 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) 3058 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12 3059 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) 3060 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13 3061 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) 3062 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14 3063 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) 3064 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15 3065 __le16 rx_id; 3066 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy; 3067 }; 3068 3069 /* 3070 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$ 3071 */ 3072 struct fcoe_tce_rx_wr_tx_rd { 3073 struct fcoe_tce_rx_wr_tx_rd_const const_ctx; 3074 struct fcoe_tce_rx_wr_tx_rd_var var_ctx; 3075 }; 3076 3077 /* 3078 * tce_rx_only $$KEEP_ENDIANNESS$$ 3079 */ 3080 struct fcoe_tce_rx_only { 3081 struct fcoe_rx_seq_ctx rx_seq_ctx; 3082 union fcoe_rx_wr_union_ctx union_ctx; 3083 }; 3084 3085 /* 3086 * task_ctx_entry $$KEEP_ENDIANNESS$$ 3087 */ 3088 struct fcoe_task_ctx_entry { 3089 struct fcoe_tce_tx_only txwr_only; 3090 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd; 3091 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd; 3092 struct fcoe_tce_rx_only rxwr_only; 3093 }; 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 /* 3105 * FCoE XFRQ element $$KEEP_ENDIANNESS$$ 3106 */ 3107 struct fcoe_xfrqe { 3108 __le16 wqe; 3109 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) 3110 #define FCOE_XFRQE_TASK_ID_SHIFT 0 3111 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) 3112 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 3113 }; 3114 3115 3116 /* 3117 * Cached SGEs $$KEEP_ENDIANNESS$$ 3118 */ 3119 struct common_fcoe_sgl { 3120 struct fcoe_bd_ctx sge[3]; 3121 }; 3122 3123 3124 /* 3125 * FCoE SQ\XFRQ element 3126 */ 3127 struct fcoe_cached_wqe { 3128 struct fcoe_sqe sqe; 3129 struct fcoe_xfrqe xfrqe; 3130 }; 3131 3132 3133 /* 3134 * FCoE connection enable\disable params passed by driver to FW in FCoE enable 3135 * ramrod $$KEEP_ENDIANNESS$$ 3136 */ 3137 struct fcoe_conn_enable_disable_ramrod_params { 3138 struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe; 3139 }; 3140 3141 3142 /* 3143 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod 3144 * $$KEEP_ENDIANNESS$$ 3145 */ 3146 struct fcoe_conn_offload_ramrod_params { 3147 struct fcoe_kwqe_conn_offload1 offload_kwqe1; 3148 struct fcoe_kwqe_conn_offload2 offload_kwqe2; 3149 struct fcoe_kwqe_conn_offload3 offload_kwqe3; 3150 struct fcoe_kwqe_conn_offload4 offload_kwqe4; 3151 }; 3152 3153 3154 struct ustorm_fcoe_mng_ctx { 3155 #if defined(__BIG_ENDIAN) 3156 u8 mid_seq_proc_flag; 3157 u8 tce_in_cam_flag; 3158 u8 tce_on_ior_flag; 3159 u8 en_cached_tce_flag; 3160 #elif defined(__LITTLE_ENDIAN) 3161 u8 en_cached_tce_flag; 3162 u8 tce_on_ior_flag; 3163 u8 tce_in_cam_flag; 3164 u8 mid_seq_proc_flag; 3165 #endif 3166 #if defined(__BIG_ENDIAN) 3167 u8 tce_cam_addr; 3168 u8 cached_conn_flag; 3169 u16 rsrv0; 3170 #elif defined(__LITTLE_ENDIAN) 3171 u16 rsrv0; 3172 u8 cached_conn_flag; 3173 u8 tce_cam_addr; 3174 #endif 3175 #if defined(__BIG_ENDIAN) 3176 u16 dma_tce_ram_addr; 3177 u16 tce_ram_addr; 3178 #elif defined(__LITTLE_ENDIAN) 3179 u16 tce_ram_addr; 3180 u16 dma_tce_ram_addr; 3181 #endif 3182 #if defined(__BIG_ENDIAN) 3183 u16 ox_id; 3184 u16 wr_done_seq; 3185 #elif defined(__LITTLE_ENDIAN) 3186 u16 wr_done_seq; 3187 u16 ox_id; 3188 #endif 3189 struct regpair task_addr; 3190 }; 3191 3192 /* 3193 * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and 3194 * used in FCoE context section 3195 */ 3196 struct ustorm_fcoe_params { 3197 #if defined(__BIG_ENDIAN) 3198 u16 fcoe_conn_id; 3199 u16 flags; 3200 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) 3201 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 3202 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) 3203 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 3204 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) 3205 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 3206 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) 3207 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 3208 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) 3209 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 3210 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) 3211 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 3212 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) 3213 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 3214 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7) 3215 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7 3216 #elif defined(__LITTLE_ENDIAN) 3217 u16 flags; 3218 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) 3219 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 3220 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) 3221 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 3222 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) 3223 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 3224 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) 3225 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 3226 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) 3227 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 3228 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) 3229 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 3230 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) 3231 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 3232 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7) 3233 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7 3234 u16 fcoe_conn_id; 3235 #endif 3236 #if defined(__BIG_ENDIAN) 3237 u8 hc_csdm_byte_en; 3238 u8 func_id; 3239 u8 port_id; 3240 u8 vnic_id; 3241 #elif defined(__LITTLE_ENDIAN) 3242 u8 vnic_id; 3243 u8 port_id; 3244 u8 func_id; 3245 u8 hc_csdm_byte_en; 3246 #endif 3247 #if defined(__BIG_ENDIAN) 3248 u16 rx_total_conc_seqs; 3249 u16 rx_max_fc_pay_len; 3250 #elif defined(__LITTLE_ENDIAN) 3251 u16 rx_max_fc_pay_len; 3252 u16 rx_total_conc_seqs; 3253 #endif 3254 #if defined(__BIG_ENDIAN) 3255 u8 task_pbe_idx_off; 3256 u8 task_in_page_log_size; 3257 u16 rx_max_conc_seqs; 3258 #elif defined(__LITTLE_ENDIAN) 3259 u16 rx_max_conc_seqs; 3260 u8 task_in_page_log_size; 3261 u8 task_pbe_idx_off; 3262 #endif 3263 }; 3264 3265 /* 3266 * FCoE 16-bits index structure 3267 */ 3268 struct fcoe_idx16_fields { 3269 u16 fields; 3270 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) 3271 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0 3272 #define FCOE_IDX16_FIELDS_MSB (0x1<<15) 3273 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15 3274 }; 3275 3276 /* 3277 * FCoE 16-bits index union 3278 */ 3279 union fcoe_idx16_field_union { 3280 struct fcoe_idx16_fields fields; 3281 u16 val; 3282 }; 3283 3284 /* 3285 * Parameters required for placement according to SGL 3286 */ 3287 struct ustorm_fcoe_data_place_mng { 3288 #if defined(__BIG_ENDIAN) 3289 u16 sge_off; 3290 u8 num_sges; 3291 u8 sge_idx; 3292 #elif defined(__LITTLE_ENDIAN) 3293 u8 sge_idx; 3294 u8 num_sges; 3295 u16 sge_off; 3296 #endif 3297 }; 3298 3299 /* 3300 * Parameters required for placement according to SGL 3301 */ 3302 struct ustorm_fcoe_data_place { 3303 struct ustorm_fcoe_data_place_mng cached_mng; 3304 struct fcoe_bd_ctx cached_sge[2]; 3305 }; 3306 3307 /* 3308 * TX processing shall write and RX processing shall read from this section 3309 */ 3310 union fcoe_u_tce_tx_wr_rx_rd_union { 3311 struct fcoe_abts_info abts; 3312 struct fcoe_cleanup_info cleanup; 3313 struct fcoe_fw_tx_seq_ctx tx_seq_ctx; 3314 u32 opaque[2]; 3315 }; 3316 3317 /* 3318 * TX processing shall write and RX processing shall read from this section 3319 */ 3320 struct fcoe_u_tce_tx_wr_rx_rd { 3321 union fcoe_u_tce_tx_wr_rx_rd_union union_ctx; 3322 struct fcoe_tce_tx_wr_rx_rd_const const_ctx; 3323 }; 3324 3325 struct ustorm_fcoe_tce { 3326 struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd; 3327 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd; 3328 struct fcoe_tce_rx_only rxwr; 3329 }; 3330 3331 struct ustorm_fcoe_cache_ctx { 3332 u32 rsrv0; 3333 struct ustorm_fcoe_data_place data_place; 3334 struct ustorm_fcoe_tce tce; 3335 }; 3336 3337 /* 3338 * Ustorm FCoE Storm Context 3339 */ 3340 struct ustorm_fcoe_st_context { 3341 struct ustorm_fcoe_mng_ctx mng_ctx; 3342 struct ustorm_fcoe_params fcoe_params; 3343 struct regpair cq_base_addr; 3344 struct regpair rq_pbl_base; 3345 struct regpair rq_cur_page_addr; 3346 struct regpair confq_pbl_base_addr; 3347 struct regpair conn_db_base; 3348 struct regpair xfrq_base_addr; 3349 struct regpair lcq_base_addr; 3350 #if defined(__BIG_ENDIAN) 3351 union fcoe_idx16_field_union rq_cons; 3352 union fcoe_idx16_field_union rq_prod; 3353 #elif defined(__LITTLE_ENDIAN) 3354 union fcoe_idx16_field_union rq_prod; 3355 union fcoe_idx16_field_union rq_cons; 3356 #endif 3357 #if defined(__BIG_ENDIAN) 3358 u16 xfrq_prod; 3359 u16 cq_cons; 3360 #elif defined(__LITTLE_ENDIAN) 3361 u16 cq_cons; 3362 u16 xfrq_prod; 3363 #endif 3364 #if defined(__BIG_ENDIAN) 3365 u16 lcq_cons; 3366 u16 hc_cram_address; 3367 #elif defined(__LITTLE_ENDIAN) 3368 u16 hc_cram_address; 3369 u16 lcq_cons; 3370 #endif 3371 #if defined(__BIG_ENDIAN) 3372 u16 sq_xfrq_lcq_confq_size; 3373 u16 confq_prod; 3374 #elif defined(__LITTLE_ENDIAN) 3375 u16 confq_prod; 3376 u16 sq_xfrq_lcq_confq_size; 3377 #endif 3378 #if defined(__BIG_ENDIAN) 3379 u8 hc_csdm_agg_int; 3380 u8 rsrv2; 3381 u8 available_rqes; 3382 u8 sp_q_flush_cnt; 3383 #elif defined(__LITTLE_ENDIAN) 3384 u8 sp_q_flush_cnt; 3385 u8 available_rqes; 3386 u8 rsrv2; 3387 u8 hc_csdm_agg_int; 3388 #endif 3389 #if defined(__BIG_ENDIAN) 3390 u16 num_pend_tasks; 3391 u16 pbf_ack_ram_addr; 3392 #elif defined(__LITTLE_ENDIAN) 3393 u16 pbf_ack_ram_addr; 3394 u16 num_pend_tasks; 3395 #endif 3396 struct ustorm_fcoe_cache_ctx cache_ctx; 3397 }; 3398 3399 /* 3400 * The FCoE non-aggregative context of Tstorm 3401 */ 3402 struct tstorm_fcoe_st_context { 3403 struct regpair reserved0; 3404 struct regpair reserved1; 3405 }; 3406 3407 /* 3408 * Ethernet context section 3409 */ 3410 struct xstorm_fcoe_eth_context_section { 3411 #if defined(__BIG_ENDIAN) 3412 u8 remote_addr_4; 3413 u8 remote_addr_5; 3414 u8 local_addr_0; 3415 u8 local_addr_1; 3416 #elif defined(__LITTLE_ENDIAN) 3417 u8 local_addr_1; 3418 u8 local_addr_0; 3419 u8 remote_addr_5; 3420 u8 remote_addr_4; 3421 #endif 3422 #if defined(__BIG_ENDIAN) 3423 u8 remote_addr_0; 3424 u8 remote_addr_1; 3425 u8 remote_addr_2; 3426 u8 remote_addr_3; 3427 #elif defined(__LITTLE_ENDIAN) 3428 u8 remote_addr_3; 3429 u8 remote_addr_2; 3430 u8 remote_addr_1; 3431 u8 remote_addr_0; 3432 #endif 3433 #if defined(__BIG_ENDIAN) 3434 u16 reserved_vlan_type; 3435 u16 params; 3436 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 3437 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 3438 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) 3439 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 3440 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 3441 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 3442 #elif defined(__LITTLE_ENDIAN) 3443 u16 params; 3444 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 3445 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 3446 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) 3447 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 3448 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 3449 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 3450 u16 reserved_vlan_type; 3451 #endif 3452 #if defined(__BIG_ENDIAN) 3453 u8 local_addr_2; 3454 u8 local_addr_3; 3455 u8 local_addr_4; 3456 u8 local_addr_5; 3457 #elif defined(__LITTLE_ENDIAN) 3458 u8 local_addr_5; 3459 u8 local_addr_4; 3460 u8 local_addr_3; 3461 u8 local_addr_2; 3462 #endif 3463 }; 3464 3465 /* 3466 * Flags used in FCoE context section - 1 byte 3467 */ 3468 struct xstorm_fcoe_context_flags { 3469 u8 flags; 3470 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) 3471 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0 3472 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) 3473 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2 3474 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3) 3475 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3 3476 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) 3477 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4 3478 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) 3479 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5 3480 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) 3481 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6 3482 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7) 3483 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7 3484 }; 3485 3486 struct xstorm_fcoe_tce { 3487 struct fcoe_tce_tx_only txwr; 3488 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd; 3489 }; 3490 3491 /* 3492 * FCP_DATA parameters required for transmission 3493 */ 3494 struct xstorm_fcoe_fcp_data { 3495 u32 io_rem; 3496 #if defined(__BIG_ENDIAN) 3497 u16 cached_sge_off; 3498 u8 cached_num_sges; 3499 u8 cached_sge_idx; 3500 #elif defined(__LITTLE_ENDIAN) 3501 u8 cached_sge_idx; 3502 u8 cached_num_sges; 3503 u16 cached_sge_off; 3504 #endif 3505 u32 buf_addr_hi_0; 3506 u32 buf_addr_lo_0; 3507 #if defined(__BIG_ENDIAN) 3508 u16 num_of_pending_tasks; 3509 u16 buf_len_0; 3510 #elif defined(__LITTLE_ENDIAN) 3511 u16 buf_len_0; 3512 u16 num_of_pending_tasks; 3513 #endif 3514 u32 buf_addr_hi_1; 3515 u32 buf_addr_lo_1; 3516 #if defined(__BIG_ENDIAN) 3517 u16 task_pbe_idx_off; 3518 u16 buf_len_1; 3519 #elif defined(__LITTLE_ENDIAN) 3520 u16 buf_len_1; 3521 u16 task_pbe_idx_off; 3522 #endif 3523 u32 buf_addr_hi_2; 3524 u32 buf_addr_lo_2; 3525 #if defined(__BIG_ENDIAN) 3526 u16 ox_id; 3527 u16 buf_len_2; 3528 #elif defined(__LITTLE_ENDIAN) 3529 u16 buf_len_2; 3530 u16 ox_id; 3531 #endif 3532 }; 3533 3534 /* 3535 * vlan configuration 3536 */ 3537 struct xstorm_fcoe_vlan_conf { 3538 u8 vlan_conf; 3539 #define XSTORM_FCOE_VLAN_CONF_PRIORITY (0x7<<0) 3540 #define XSTORM_FCOE_VLAN_CONF_PRIORITY_SHIFT 0 3541 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3) 3542 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3 3543 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0xF<<4) 3544 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 4 3545 }; 3546 3547 /* 3548 * FCoE 16-bits vlan structure 3549 */ 3550 struct fcoe_vlan_fields { 3551 u16 fields; 3552 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0) 3553 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 3554 #define FCOE_VLAN_FIELDS_CLI (0x1<<12) 3555 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 3556 #define FCOE_VLAN_FIELDS_PRI (0x7<<13) 3557 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 3558 }; 3559 3560 /* 3561 * FCoE 16-bits vlan union 3562 */ 3563 union fcoe_vlan_field_union { 3564 struct fcoe_vlan_fields fields; 3565 u16 val; 3566 }; 3567 3568 /* 3569 * FCoE 16-bits vlan, vif union 3570 */ 3571 union fcoe_vlan_vif_field_union { 3572 union fcoe_vlan_field_union vlan; 3573 u16 vif; 3574 }; 3575 3576 /* 3577 * FCoE context section 3578 */ 3579 struct xstorm_fcoe_context_section { 3580 #if defined(__BIG_ENDIAN) 3581 u8 cs_ctl; 3582 u8 s_id[3]; 3583 #elif defined(__LITTLE_ENDIAN) 3584 u8 s_id[3]; 3585 u8 cs_ctl; 3586 #endif 3587 #if defined(__BIG_ENDIAN) 3588 u8 rctl; 3589 u8 d_id[3]; 3590 #elif defined(__LITTLE_ENDIAN) 3591 u8 d_id[3]; 3592 u8 rctl; 3593 #endif 3594 #if defined(__BIG_ENDIAN) 3595 u16 sq_xfrq_lcq_confq_size; 3596 u16 tx_max_fc_pay_len; 3597 #elif defined(__LITTLE_ENDIAN) 3598 u16 tx_max_fc_pay_len; 3599 u16 sq_xfrq_lcq_confq_size; 3600 #endif 3601 u32 lcq_prod; 3602 #if defined(__BIG_ENDIAN) 3603 u8 port_id; 3604 u8 func_id; 3605 u8 seq_id; 3606 struct xstorm_fcoe_context_flags tx_flags; 3607 #elif defined(__LITTLE_ENDIAN) 3608 struct xstorm_fcoe_context_flags tx_flags; 3609 u8 seq_id; 3610 u8 func_id; 3611 u8 port_id; 3612 #endif 3613 #if defined(__BIG_ENDIAN) 3614 u16 mtu; 3615 u8 func_mode; 3616 u8 vnic_id; 3617 #elif defined(__LITTLE_ENDIAN) 3618 u8 vnic_id; 3619 u8 func_mode; 3620 u16 mtu; 3621 #endif 3622 struct regpair confq_curr_page_addr; 3623 struct fcoe_cached_wqe cached_wqe[8]; 3624 struct regpair lcq_base_addr; 3625 struct xstorm_fcoe_tce tce; 3626 struct xstorm_fcoe_fcp_data fcp_data; 3627 #if defined(__BIG_ENDIAN) 3628 u8 tx_max_conc_seqs_c3; 3629 u8 vlan_flag; 3630 u8 dcb_val; 3631 u8 data_pb_cmd_size; 3632 #elif defined(__LITTLE_ENDIAN) 3633 u8 data_pb_cmd_size; 3634 u8 dcb_val; 3635 u8 vlan_flag; 3636 u8 tx_max_conc_seqs_c3; 3637 #endif 3638 #if defined(__BIG_ENDIAN) 3639 u16 fcoe_tx_stat_params_ram_addr; 3640 u16 fcoe_tx_fc_seq_ram_addr; 3641 #elif defined(__LITTLE_ENDIAN) 3642 u16 fcoe_tx_fc_seq_ram_addr; 3643 u16 fcoe_tx_stat_params_ram_addr; 3644 #endif 3645 #if defined(__BIG_ENDIAN) 3646 u8 fcp_cmd_line_credit; 3647 u8 eth_hdr_size; 3648 u16 pbf_addr; 3649 #elif defined(__LITTLE_ENDIAN) 3650 u16 pbf_addr; 3651 u8 eth_hdr_size; 3652 u8 fcp_cmd_line_credit; 3653 #endif 3654 #if defined(__BIG_ENDIAN) 3655 union fcoe_vlan_vif_field_union multi_func_val; 3656 u8 page_log_size; 3657 struct xstorm_fcoe_vlan_conf orig_vlan_conf; 3658 #elif defined(__LITTLE_ENDIAN) 3659 struct xstorm_fcoe_vlan_conf orig_vlan_conf; 3660 u8 page_log_size; 3661 union fcoe_vlan_vif_field_union multi_func_val; 3662 #endif 3663 #if defined(__BIG_ENDIAN) 3664 u16 fcp_cmd_frame_size; 3665 u16 pbf_addr_ff; 3666 #elif defined(__LITTLE_ENDIAN) 3667 u16 pbf_addr_ff; 3668 u16 fcp_cmd_frame_size; 3669 #endif 3670 #if defined(__BIG_ENDIAN) 3671 u8 vlan_num; 3672 u8 cos; 3673 u8 cache_xfrq_cons; 3674 u8 cache_sq_cons; 3675 #elif defined(__LITTLE_ENDIAN) 3676 u8 cache_sq_cons; 3677 u8 cache_xfrq_cons; 3678 u8 cos; 3679 u8 vlan_num; 3680 #endif 3681 u32 verify_tx_seq; 3682 }; 3683 3684 /* 3685 * Xstorm FCoE Storm Context 3686 */ 3687 struct xstorm_fcoe_st_context { 3688 struct xstorm_fcoe_eth_context_section eth; 3689 struct xstorm_fcoe_context_section fcoe; 3690 }; 3691 3692 /* 3693 * Fcoe connection context 3694 */ 3695 struct fcoe_context { 3696 struct ustorm_fcoe_st_context ustorm_st_context; 3697 struct tstorm_fcoe_st_context tstorm_st_context; 3698 struct xstorm_fcoe_ag_context xstorm_ag_context; 3699 struct tstorm_fcoe_ag_context tstorm_ag_context; 3700 struct ustorm_fcoe_ag_context ustorm_ag_context; 3701 struct timers_block_context timers_context; 3702 struct xstorm_fcoe_st_context xstorm_st_context; 3703 }; 3704 3705 /* 3706 * FCoE init params passed by driver to FW in FCoE init ramrod 3707 * $$KEEP_ENDIANNESS$$ 3708 */ 3709 struct fcoe_init_ramrod_params { 3710 struct fcoe_kwqe_init1 init_kwqe1; 3711 struct fcoe_kwqe_init2 init_kwqe2; 3712 struct fcoe_kwqe_init3 init_kwqe3; 3713 struct regpair eq_pbl_base; 3714 __le32 eq_pbl_size; 3715 __le32 reserved2; 3716 __le16 eq_prod; 3717 __le16 sb_num; 3718 u8 sb_id; 3719 u8 reserved0; 3720 __le16 reserved1; 3721 }; 3722 3723 /* 3724 * FCoE statistics params buffer passed by driver to FW in FCoE statistics 3725 * ramrod $$KEEP_ENDIANNESS$$ 3726 */ 3727 struct fcoe_stat_ramrod_params { 3728 struct fcoe_kwqe_stat stat_kwqe; 3729 }; 3730 3731 /* 3732 * CQ DB CQ producer and pending completion counter 3733 */ 3734 struct iscsi_cq_db_prod_pnd_cmpltn_cnt { 3735 #if defined(__BIG_ENDIAN) 3736 u16 cntr; 3737 u16 prod; 3738 #elif defined(__LITTLE_ENDIAN) 3739 u16 prod; 3740 u16 cntr; 3741 #endif 3742 }; 3743 3744 /* 3745 * CQ DB pending completion ITT array 3746 */ 3747 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr { 3748 struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8]; 3749 }; 3750 3751 /* 3752 * Cstorm CQ sequence to notify array, updated by driver 3753 */ 3754 struct iscsi_cq_db_sqn_2_notify_arr { 3755 u16 sqn[8]; 3756 }; 3757 3758 /* 3759 * Cstorm iSCSI Storm Context 3760 */ 3761 struct cstorm_iscsi_st_context { 3762 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr; 3763 struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr; 3764 struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr; 3765 struct regpair hq_pbl_base; 3766 struct regpair hq_curr_pbe; 3767 struct regpair task_pbl_base; 3768 struct regpair cq_db_base; 3769 #if defined(__BIG_ENDIAN) 3770 u16 hq_bd_itt; 3771 u16 iscsi_conn_id; 3772 #elif defined(__LITTLE_ENDIAN) 3773 u16 iscsi_conn_id; 3774 u16 hq_bd_itt; 3775 #endif 3776 u32 hq_bd_data_segment_len; 3777 u32 hq_bd_buffer_offset; 3778 #if defined(__BIG_ENDIAN) 3779 u8 rsrv; 3780 u8 cq_proc_en_bit_map; 3781 u8 cq_pend_comp_itt_valid_bit_map; 3782 u8 hq_bd_opcode; 3783 #elif defined(__LITTLE_ENDIAN) 3784 u8 hq_bd_opcode; 3785 u8 cq_pend_comp_itt_valid_bit_map; 3786 u8 cq_proc_en_bit_map; 3787 u8 rsrv; 3788 #endif 3789 u32 hq_tcp_seq; 3790 #if defined(__BIG_ENDIAN) 3791 u16 flags; 3792 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) 3793 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 3794 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) 3795 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 3796 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) 3797 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 3798 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) 3799 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 3800 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) 3801 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 3802 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) 3803 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 3804 u16 hq_cons; 3805 #elif defined(__LITTLE_ENDIAN) 3806 u16 hq_cons; 3807 u16 flags; 3808 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) 3809 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 3810 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) 3811 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 3812 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) 3813 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 3814 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) 3815 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 3816 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) 3817 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 3818 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) 3819 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 3820 #endif 3821 struct regpair rsrv1; 3822 }; 3823 3824 3825 /* 3826 * SCSI read/write SQ WQE 3827 */ 3828 struct iscsi_cmd_pdu_hdr_little_endian { 3829 #if defined(__BIG_ENDIAN) 3830 u8 opcode; 3831 u8 op_attr; 3832 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) 3833 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 3834 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) 3835 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 3836 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) 3837 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 3838 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) 3839 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 3840 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 3841 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 3842 u16 rsrv0; 3843 #elif defined(__LITTLE_ENDIAN) 3844 u16 rsrv0; 3845 u8 op_attr; 3846 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) 3847 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 3848 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) 3849 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 3850 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) 3851 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 3852 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) 3853 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 3854 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 3855 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 3856 u8 opcode; 3857 #endif 3858 u32 data_fields; 3859 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 3860 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 3861 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 3862 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 3863 struct regpair lun; 3864 u32 itt; 3865 u32 expected_data_transfer_length; 3866 u32 cmd_sn; 3867 u32 exp_stat_sn; 3868 u32 scsi_command_block[4]; 3869 }; 3870 3871 3872 /* 3873 * Buffer per connection, used in Tstorm 3874 */ 3875 struct iscsi_conn_buf { 3876 struct regpair reserved[8]; 3877 }; 3878 3879 3880 /* 3881 * iSCSI context region, used only in iSCSI 3882 */ 3883 struct ustorm_iscsi_rq_db { 3884 struct regpair pbl_base; 3885 struct regpair curr_pbe; 3886 }; 3887 3888 /* 3889 * iSCSI context region, used only in iSCSI 3890 */ 3891 struct ustorm_iscsi_r2tq_db { 3892 struct regpair pbl_base; 3893 struct regpair curr_pbe; 3894 }; 3895 3896 /* 3897 * iSCSI context region, used only in iSCSI 3898 */ 3899 struct ustorm_iscsi_cq_db { 3900 #if defined(__BIG_ENDIAN) 3901 u16 cq_sn; 3902 u16 prod; 3903 #elif defined(__LITTLE_ENDIAN) 3904 u16 prod; 3905 u16 cq_sn; 3906 #endif 3907 struct regpair curr_pbe; 3908 }; 3909 3910 /* 3911 * iSCSI context region, used only in iSCSI 3912 */ 3913 struct rings_db { 3914 struct ustorm_iscsi_rq_db rq; 3915 struct ustorm_iscsi_r2tq_db r2tq; 3916 struct ustorm_iscsi_cq_db cq[8]; 3917 #if defined(__BIG_ENDIAN) 3918 u16 rq_prod; 3919 u16 r2tq_prod; 3920 #elif defined(__LITTLE_ENDIAN) 3921 u16 r2tq_prod; 3922 u16 rq_prod; 3923 #endif 3924 struct regpair cq_pbl_base; 3925 }; 3926 3927 /* 3928 * iSCSI context region, used only in iSCSI 3929 */ 3930 struct ustorm_iscsi_placement_db { 3931 u32 sgl_base_lo; 3932 u32 sgl_base_hi; 3933 u32 local_sge_0_address_hi; 3934 u32 local_sge_0_address_lo; 3935 #if defined(__BIG_ENDIAN) 3936 u16 curr_sge_offset; 3937 u16 local_sge_0_size; 3938 #elif defined(__LITTLE_ENDIAN) 3939 u16 local_sge_0_size; 3940 u16 curr_sge_offset; 3941 #endif 3942 u32 local_sge_1_address_hi; 3943 u32 local_sge_1_address_lo; 3944 #if defined(__BIG_ENDIAN) 3945 u8 exp_padding_2b; 3946 u8 nal_len_3b; 3947 u16 local_sge_1_size; 3948 #elif defined(__LITTLE_ENDIAN) 3949 u16 local_sge_1_size; 3950 u8 nal_len_3b; 3951 u8 exp_padding_2b; 3952 #endif 3953 #if defined(__BIG_ENDIAN) 3954 u8 sgl_size; 3955 u8 local_sge_index_2b; 3956 u16 reserved7; 3957 #elif defined(__LITTLE_ENDIAN) 3958 u16 reserved7; 3959 u8 local_sge_index_2b; 3960 u8 sgl_size; 3961 #endif 3962 u32 rem_pdu; 3963 u32 place_db_bitfield_1; 3964 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) 3965 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 3966 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) 3967 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 3968 u32 place_db_bitfield_2; 3969 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) 3970 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 3971 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) 3972 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 3973 u32 nal; 3974 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) 3975 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 3976 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24) 3977 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24 3978 }; 3979 3980 /* 3981 * Ustorm iSCSI Storm Context 3982 */ 3983 struct ustorm_iscsi_st_context { 3984 u32 exp_stat_sn; 3985 u32 exp_data_sn; 3986 struct rings_db ring; 3987 struct regpair task_pbl_base; 3988 struct regpair tce_phy_addr; 3989 struct ustorm_iscsi_placement_db place_db; 3990 u32 reserved8; 3991 u32 rem_rcv_len; 3992 #if defined(__BIG_ENDIAN) 3993 u16 hdr_itt; 3994 u16 iscsi_conn_id; 3995 #elif defined(__LITTLE_ENDIAN) 3996 u16 iscsi_conn_id; 3997 u16 hdr_itt; 3998 #endif 3999 u32 nal_bytes; 4000 #if defined(__BIG_ENDIAN) 4001 u8 hdr_second_byte_union; 4002 u8 bitfield_0; 4003 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) 4004 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 4005 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) 4006 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 4007 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) 4008 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 4009 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) 4010 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 4011 u8 task_pdu_cache_index; 4012 u8 task_pbe_cache_index; 4013 #elif defined(__LITTLE_ENDIAN) 4014 u8 task_pbe_cache_index; 4015 u8 task_pdu_cache_index; 4016 u8 bitfield_0; 4017 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) 4018 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 4019 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) 4020 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 4021 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) 4022 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 4023 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) 4024 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 4025 u8 hdr_second_byte_union; 4026 #endif 4027 #if defined(__BIG_ENDIAN) 4028 u16 reserved3; 4029 u8 reserved2; 4030 u8 acDecrement; 4031 #elif defined(__LITTLE_ENDIAN) 4032 u8 acDecrement; 4033 u8 reserved2; 4034 u16 reserved3; 4035 #endif 4036 u32 task_stat; 4037 #if defined(__BIG_ENDIAN) 4038 u8 hdr_opcode; 4039 u8 num_cqs; 4040 u16 reserved5; 4041 #elif defined(__LITTLE_ENDIAN) 4042 u16 reserved5; 4043 u8 num_cqs; 4044 u8 hdr_opcode; 4045 #endif 4046 u32 negotiated_rx; 4047 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) 4048 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 4049 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) 4050 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 4051 u32 negotiated_rx_and_flags; 4052 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) 4053 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 4054 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) 4055 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 4056 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) 4057 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 4058 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) 4059 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 4060 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) 4061 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 4062 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) 4063 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 4064 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) 4065 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 4066 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) 4067 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 4068 }; 4069 4070 /* 4071 * TCP context region, shared in TOE, RDMA and ISCSI 4072 */ 4073 struct tstorm_tcp_st_context_section { 4074 u32 flags1; 4075 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0) 4076 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0 4077 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) 4078 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 4079 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) 4080 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 4081 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) 4082 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26 4083 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) 4084 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 4085 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) 4086 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 4087 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) 4088 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 4089 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) 4090 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 4091 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) 4092 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31 4093 u32 flags2; 4094 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0) 4095 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0 4096 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) 4097 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 4098 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) 4099 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 4100 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) 4101 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 4102 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) 4103 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 4104 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) 4105 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 4106 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) 4107 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 4108 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) 4109 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30 4110 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) 4111 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31 4112 #if defined(__BIG_ENDIAN) 4113 u16 mss; 4114 u8 tcp_sm_state; 4115 u8 rto_exp; 4116 #elif defined(__LITTLE_ENDIAN) 4117 u8 rto_exp; 4118 u8 tcp_sm_state; 4119 u16 mss; 4120 #endif 4121 u32 rcv_nxt; 4122 u32 timestamp_recent; 4123 u32 timestamp_recent_time; 4124 u32 cwnd; 4125 u32 ss_thresh; 4126 u32 cwnd_accum; 4127 u32 prev_seg_seq; 4128 u32 expected_rel_seq; 4129 u32 recover; 4130 #if defined(__BIG_ENDIAN) 4131 u8 retransmit_count; 4132 u8 ka_max_probe_count; 4133 u8 persist_probe_count; 4134 u8 ka_probe_count; 4135 #elif defined(__LITTLE_ENDIAN) 4136 u8 ka_probe_count; 4137 u8 persist_probe_count; 4138 u8 ka_max_probe_count; 4139 u8 retransmit_count; 4140 #endif 4141 #if defined(__BIG_ENDIAN) 4142 u8 statistics_counter_id; 4143 u8 ooo_support_mode; 4144 u8 snd_wnd_scale; 4145 u8 dup_ack_count; 4146 #elif defined(__LITTLE_ENDIAN) 4147 u8 dup_ack_count; 4148 u8 snd_wnd_scale; 4149 u8 ooo_support_mode; 4150 u8 statistics_counter_id; 4151 #endif 4152 u32 retransmit_start_time; 4153 u32 ka_timeout; 4154 u32 ka_interval; 4155 u32 isle_start_seq; 4156 u32 isle_end_seq; 4157 #if defined(__BIG_ENDIAN) 4158 u16 second_isle_address; 4159 u16 recent_seg_wnd; 4160 #elif defined(__LITTLE_ENDIAN) 4161 u16 recent_seg_wnd; 4162 u16 second_isle_address; 4163 #endif 4164 #if defined(__BIG_ENDIAN) 4165 u8 max_isles_ever_happened; 4166 u8 isles_number; 4167 u16 last_isle_address; 4168 #elif defined(__LITTLE_ENDIAN) 4169 u16 last_isle_address; 4170 u8 isles_number; 4171 u8 max_isles_ever_happened; 4172 #endif 4173 u32 max_rt_time; 4174 #if defined(__BIG_ENDIAN) 4175 u16 lsb_mac_address; 4176 u16 vlan_id; 4177 #elif defined(__LITTLE_ENDIAN) 4178 u16 vlan_id; 4179 u16 lsb_mac_address; 4180 #endif 4181 #if defined(__BIG_ENDIAN) 4182 u16 msb_mac_address; 4183 u16 mid_mac_address; 4184 #elif defined(__LITTLE_ENDIAN) 4185 u16 mid_mac_address; 4186 u16 msb_mac_address; 4187 #endif 4188 u32 rightmost_received_seq; 4189 }; 4190 4191 /* 4192 * Termination variables 4193 */ 4194 struct iscsi_term_vars { 4195 u8 BitMap; 4196 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) 4197 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 4198 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) 4199 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 4200 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) 4201 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 4202 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) 4203 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 4204 #define ISCSI_TERM_VARS_RSRV (0x1<<7) 4205 #define ISCSI_TERM_VARS_RSRV_SHIFT 7 4206 }; 4207 4208 /* 4209 * iSCSI context region, used only in iSCSI 4210 */ 4211 struct tstorm_iscsi_st_context_section { 4212 u32 nalPayload; 4213 u32 b2nh; 4214 #if defined(__BIG_ENDIAN) 4215 u16 rq_cons; 4216 u8 flags; 4217 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) 4218 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 4219 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) 4220 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 4221 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) 4222 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 4223 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) 4224 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 4225 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) 4226 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 4227 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) 4228 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5 4229 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) 4230 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7 4231 u8 hdr_bytes_2_fetch; 4232 #elif defined(__LITTLE_ENDIAN) 4233 u8 hdr_bytes_2_fetch; 4234 u8 flags; 4235 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) 4236 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 4237 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) 4238 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 4239 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) 4240 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 4241 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) 4242 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 4243 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) 4244 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 4245 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) 4246 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5 4247 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) 4248 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7 4249 u16 rq_cons; 4250 #endif 4251 struct regpair rq_db_phy_addr; 4252 #if defined(__BIG_ENDIAN) 4253 struct iscsi_term_vars term_vars; 4254 u8 rsrv1; 4255 u16 iscsi_conn_id; 4256 #elif defined(__LITTLE_ENDIAN) 4257 u16 iscsi_conn_id; 4258 u8 rsrv1; 4259 struct iscsi_term_vars term_vars; 4260 #endif 4261 u32 process_nxt; 4262 }; 4263 4264 /* 4265 * The iSCSI non-aggregative context of Tstorm 4266 */ 4267 struct tstorm_iscsi_st_context { 4268 struct tstorm_tcp_st_context_section tcp; 4269 struct tstorm_iscsi_st_context_section iscsi; 4270 }; 4271 4272 /* 4273 * Ethernet context section, shared in TOE, RDMA and ISCSI 4274 */ 4275 struct xstorm_eth_context_section { 4276 #if defined(__BIG_ENDIAN) 4277 u8 remote_addr_4; 4278 u8 remote_addr_5; 4279 u8 local_addr_0; 4280 u8 local_addr_1; 4281 #elif defined(__LITTLE_ENDIAN) 4282 u8 local_addr_1; 4283 u8 local_addr_0; 4284 u8 remote_addr_5; 4285 u8 remote_addr_4; 4286 #endif 4287 #if defined(__BIG_ENDIAN) 4288 u8 remote_addr_0; 4289 u8 remote_addr_1; 4290 u8 remote_addr_2; 4291 u8 remote_addr_3; 4292 #elif defined(__LITTLE_ENDIAN) 4293 u8 remote_addr_3; 4294 u8 remote_addr_2; 4295 u8 remote_addr_1; 4296 u8 remote_addr_0; 4297 #endif 4298 #if defined(__BIG_ENDIAN) 4299 u16 reserved_vlan_type; 4300 u16 params; 4301 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 4302 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 4303 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) 4304 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 4305 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 4306 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 4307 #elif defined(__LITTLE_ENDIAN) 4308 u16 params; 4309 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 4310 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 4311 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) 4312 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 4313 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 4314 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 4315 u16 reserved_vlan_type; 4316 #endif 4317 #if defined(__BIG_ENDIAN) 4318 u8 local_addr_2; 4319 u8 local_addr_3; 4320 u8 local_addr_4; 4321 u8 local_addr_5; 4322 #elif defined(__LITTLE_ENDIAN) 4323 u8 local_addr_5; 4324 u8 local_addr_4; 4325 u8 local_addr_3; 4326 u8 local_addr_2; 4327 #endif 4328 }; 4329 4330 /* 4331 * IpV4 context section, shared in TOE, RDMA and ISCSI 4332 */ 4333 struct xstorm_ip_v4_context_section { 4334 #if defined(__BIG_ENDIAN) 4335 u16 __pbf_hdr_cmd_rsvd_id; 4336 u16 __pbf_hdr_cmd_rsvd_flags_offset; 4337 #elif defined(__LITTLE_ENDIAN) 4338 u16 __pbf_hdr_cmd_rsvd_flags_offset; 4339 u16 __pbf_hdr_cmd_rsvd_id; 4340 #endif 4341 #if defined(__BIG_ENDIAN) 4342 u8 __pbf_hdr_cmd_rsvd_ver_ihl; 4343 u8 tos; 4344 u16 __pbf_hdr_cmd_rsvd_length; 4345 #elif defined(__LITTLE_ENDIAN) 4346 u16 __pbf_hdr_cmd_rsvd_length; 4347 u8 tos; 4348 u8 __pbf_hdr_cmd_rsvd_ver_ihl; 4349 #endif 4350 u32 ip_local_addr; 4351 #if defined(__BIG_ENDIAN) 4352 u8 ttl; 4353 u8 __pbf_hdr_cmd_rsvd_protocol; 4354 u16 __pbf_hdr_cmd_rsvd_csum; 4355 #elif defined(__LITTLE_ENDIAN) 4356 u16 __pbf_hdr_cmd_rsvd_csum; 4357 u8 __pbf_hdr_cmd_rsvd_protocol; 4358 u8 ttl; 4359 #endif 4360 u32 __pbf_hdr_cmd_rsvd_1; 4361 u32 ip_remote_addr; 4362 }; 4363 4364 /* 4365 * context section, shared in TOE, RDMA and ISCSI 4366 */ 4367 struct xstorm_padded_ip_v4_context_section { 4368 struct xstorm_ip_v4_context_section ip_v4; 4369 u32 reserved1[4]; 4370 }; 4371 4372 /* 4373 * IpV6 context section, shared in TOE, RDMA and ISCSI 4374 */ 4375 struct xstorm_ip_v6_context_section { 4376 #if defined(__BIG_ENDIAN) 4377 u16 pbf_hdr_cmd_rsvd_payload_len; 4378 u8 pbf_hdr_cmd_rsvd_nxt_hdr; 4379 u8 hop_limit; 4380 #elif defined(__LITTLE_ENDIAN) 4381 u8 hop_limit; 4382 u8 pbf_hdr_cmd_rsvd_nxt_hdr; 4383 u16 pbf_hdr_cmd_rsvd_payload_len; 4384 #endif 4385 u32 priority_flow_label; 4386 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) 4387 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0 4388 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) 4389 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20 4390 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) 4391 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28 4392 u32 ip_local_addr_lo_hi; 4393 u32 ip_local_addr_lo_lo; 4394 u32 ip_local_addr_hi_hi; 4395 u32 ip_local_addr_hi_lo; 4396 u32 ip_remote_addr_lo_hi; 4397 u32 ip_remote_addr_lo_lo; 4398 u32 ip_remote_addr_hi_hi; 4399 u32 ip_remote_addr_hi_lo; 4400 }; 4401 4402 union xstorm_ip_context_section_types { 4403 struct xstorm_padded_ip_v4_context_section padded_ip_v4; 4404 struct xstorm_ip_v6_context_section ip_v6; 4405 }; 4406 4407 /* 4408 * TCP context section, shared in TOE, RDMA and ISCSI 4409 */ 4410 struct xstorm_tcp_context_section { 4411 u32 snd_max; 4412 #if defined(__BIG_ENDIAN) 4413 u16 remote_port; 4414 u16 local_port; 4415 #elif defined(__LITTLE_ENDIAN) 4416 u16 local_port; 4417 u16 remote_port; 4418 #endif 4419 #if defined(__BIG_ENDIAN) 4420 u8 original_nagle_1b; 4421 u8 ts_enabled; 4422 u16 tcp_params; 4423 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) 4424 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 4425 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) 4426 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 4427 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) 4428 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 4429 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) 4430 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 4431 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) 4432 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 4433 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) 4434 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 4435 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) 4436 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 4437 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) 4438 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 4439 #elif defined(__LITTLE_ENDIAN) 4440 u16 tcp_params; 4441 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) 4442 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 4443 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) 4444 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 4445 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) 4446 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 4447 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) 4448 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 4449 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) 4450 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 4451 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) 4452 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 4453 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) 4454 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 4455 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) 4456 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 4457 u8 ts_enabled; 4458 u8 original_nagle_1b; 4459 #endif 4460 #if defined(__BIG_ENDIAN) 4461 u16 pseudo_csum; 4462 u16 window_scaling_factor; 4463 #elif defined(__LITTLE_ENDIAN) 4464 u16 window_scaling_factor; 4465 u16 pseudo_csum; 4466 #endif 4467 #if defined(__BIG_ENDIAN) 4468 u16 reserved2; 4469 u8 statistics_counter_id; 4470 u8 statistics_params; 4471 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) 4472 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 4473 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) 4474 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 4475 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) 4476 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2 4477 #elif defined(__LITTLE_ENDIAN) 4478 u8 statistics_params; 4479 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) 4480 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 4481 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) 4482 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 4483 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) 4484 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2 4485 u8 statistics_counter_id; 4486 u16 reserved2; 4487 #endif 4488 u32 ts_time_diff; 4489 u32 __next_timer_expir; 4490 }; 4491 4492 /* 4493 * Common context section, shared in TOE, RDMA and ISCSI 4494 */ 4495 struct xstorm_common_context_section { 4496 struct xstorm_eth_context_section ethernet; 4497 union xstorm_ip_context_section_types ip_union; 4498 struct xstorm_tcp_context_section tcp; 4499 #if defined(__BIG_ENDIAN) 4500 u8 __dcb_val; 4501 u8 flags; 4502 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) 4503 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0 4504 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) 4505 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1 4506 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) 4507 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4 4508 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) 4509 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5 4510 u8 reserved; 4511 u8 ip_version_1b; 4512 #elif defined(__LITTLE_ENDIAN) 4513 u8 ip_version_1b; 4514 u8 reserved; 4515 u8 flags; 4516 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) 4517 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0 4518 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) 4519 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1 4520 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) 4521 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4 4522 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) 4523 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5 4524 u8 __dcb_val; 4525 #endif 4526 }; 4527 4528 /* 4529 * Flags used in ISCSI context section 4530 */ 4531 struct xstorm_iscsi_context_flags { 4532 u8 flags; 4533 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) 4534 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0 4535 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) 4536 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1 4537 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) 4538 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2 4539 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) 4540 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3 4541 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) 4542 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4 4543 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) 4544 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5 4545 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) 4546 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6 4547 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) 4548 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7 4549 }; 4550 4551 struct iscsi_task_context_entry_x { 4552 u32 data_out_buffer_offset; 4553 u32 itt; 4554 u32 data_sn; 4555 }; 4556 4557 struct iscsi_task_context_entry_xuc_x_write_only { 4558 u32 tx_r2t_sn; 4559 }; 4560 4561 struct iscsi_task_context_entry_xuc_xu_write_both { 4562 u32 sgl_base_lo; 4563 u32 sgl_base_hi; 4564 #if defined(__BIG_ENDIAN) 4565 u8 sgl_size; 4566 u8 sge_index; 4567 u16 sge_offset; 4568 #elif defined(__LITTLE_ENDIAN) 4569 u16 sge_offset; 4570 u8 sge_index; 4571 u8 sgl_size; 4572 #endif 4573 }; 4574 4575 /* 4576 * iSCSI context section 4577 */ 4578 struct xstorm_iscsi_context_section { 4579 u32 first_burst_length; 4580 u32 max_send_pdu_length; 4581 struct regpair sq_pbl_base; 4582 struct regpair sq_curr_pbe; 4583 struct regpair hq_pbl_base; 4584 struct regpair hq_curr_pbe_base; 4585 struct regpair r2tq_pbl_base; 4586 struct regpair r2tq_curr_pbe_base; 4587 struct regpair task_pbl_base; 4588 #if defined(__BIG_ENDIAN) 4589 u16 data_out_count; 4590 struct xstorm_iscsi_context_flags flags; 4591 u8 task_pbl_cache_idx; 4592 #elif defined(__LITTLE_ENDIAN) 4593 u8 task_pbl_cache_idx; 4594 struct xstorm_iscsi_context_flags flags; 4595 u16 data_out_count; 4596 #endif 4597 u32 seq_more_2_send; 4598 u32 pdu_more_2_send; 4599 struct iscsi_task_context_entry_x temp_tce_x; 4600 struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr; 4601 struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr; 4602 struct regpair lun; 4603 u32 exp_data_transfer_len_ttt; 4604 u32 pdu_data_2_rxmit; 4605 u32 rxmit_bytes_2_dr; 4606 #if defined(__BIG_ENDIAN) 4607 u16 rxmit_sge_offset; 4608 u16 hq_rxmit_cons; 4609 #elif defined(__LITTLE_ENDIAN) 4610 u16 hq_rxmit_cons; 4611 u16 rxmit_sge_offset; 4612 #endif 4613 #if defined(__BIG_ENDIAN) 4614 u16 r2tq_cons; 4615 u8 rxmit_flags; 4616 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) 4617 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 4618 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) 4619 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 4620 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) 4621 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 4622 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) 4623 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 4624 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) 4625 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 4626 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) 4627 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 4628 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) 4629 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 4630 u8 rxmit_sge_idx; 4631 #elif defined(__LITTLE_ENDIAN) 4632 u8 rxmit_sge_idx; 4633 u8 rxmit_flags; 4634 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) 4635 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 4636 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) 4637 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 4638 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) 4639 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 4640 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) 4641 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 4642 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) 4643 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 4644 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) 4645 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 4646 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) 4647 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 4648 u16 r2tq_cons; 4649 #endif 4650 u32 hq_rxmit_tcp_seq; 4651 }; 4652 4653 /* 4654 * Xstorm iSCSI Storm Context 4655 */ 4656 struct xstorm_iscsi_st_context { 4657 struct xstorm_common_context_section common; 4658 struct xstorm_iscsi_context_section iscsi; 4659 }; 4660 4661 /* 4662 * Iscsi connection context 4663 */ 4664 struct iscsi_context { 4665 struct ustorm_iscsi_st_context ustorm_st_context; 4666 struct tstorm_iscsi_st_context tstorm_st_context; 4667 struct xstorm_iscsi_ag_context xstorm_ag_context; 4668 struct tstorm_iscsi_ag_context tstorm_ag_context; 4669 struct cstorm_iscsi_ag_context cstorm_ag_context; 4670 struct ustorm_iscsi_ag_context ustorm_ag_context; 4671 struct timers_block_context timers_context; 4672 struct regpair upb_context; 4673 struct xstorm_iscsi_st_context xstorm_st_context; 4674 struct regpair xpb_context; 4675 struct cstorm_iscsi_st_context cstorm_st_context; 4676 }; 4677 4678 4679 /* 4680 * PDU header of an iSCSI DATA-OUT 4681 */ 4682 struct iscsi_data_pdu_hdr_little_endian { 4683 #if defined(__BIG_ENDIAN) 4684 u8 opcode; 4685 u8 op_attr; 4686 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4687 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4688 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 4689 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 4690 u16 rsrv0; 4691 #elif defined(__LITTLE_ENDIAN) 4692 u16 rsrv0; 4693 u8 op_attr; 4694 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4695 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4696 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 4697 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 4698 u8 opcode; 4699 #endif 4700 u32 data_fields; 4701 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4702 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4703 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4704 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4705 struct regpair lun; 4706 u32 itt; 4707 u32 ttt; 4708 u32 rsrv2; 4709 u32 exp_stat_sn; 4710 u32 rsrv3; 4711 u32 data_sn; 4712 u32 buffer_offset; 4713 u32 rsrv4; 4714 }; 4715 4716 4717 /* 4718 * PDU header of an iSCSI login request 4719 */ 4720 struct iscsi_login_req_hdr_little_endian { 4721 #if defined(__BIG_ENDIAN) 4722 u8 opcode; 4723 u8 op_attr; 4724 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) 4725 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 4726 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) 4727 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 4728 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) 4729 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 4730 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4731 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4732 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) 4733 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 4734 u8 version_max; 4735 u8 version_min; 4736 #elif defined(__LITTLE_ENDIAN) 4737 u8 version_min; 4738 u8 version_max; 4739 u8 op_attr; 4740 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) 4741 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 4742 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) 4743 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 4744 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) 4745 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 4746 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4747 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4748 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) 4749 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 4750 u8 opcode; 4751 #endif 4752 u32 data_fields; 4753 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4754 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4755 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4756 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4757 u32 isid_lo; 4758 #if defined(__BIG_ENDIAN) 4759 u16 isid_hi; 4760 u16 tsih; 4761 #elif defined(__LITTLE_ENDIAN) 4762 u16 tsih; 4763 u16 isid_hi; 4764 #endif 4765 u32 itt; 4766 #if defined(__BIG_ENDIAN) 4767 u16 cid; 4768 u16 rsrv1; 4769 #elif defined(__LITTLE_ENDIAN) 4770 u16 rsrv1; 4771 u16 cid; 4772 #endif 4773 u32 cmd_sn; 4774 u32 exp_stat_sn; 4775 u32 rsrv2[4]; 4776 }; 4777 4778 /* 4779 * PDU header of an iSCSI logout request 4780 */ 4781 struct iscsi_logout_req_hdr_little_endian { 4782 #if defined(__BIG_ENDIAN) 4783 u8 opcode; 4784 u8 op_attr; 4785 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) 4786 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 4787 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4788 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4789 u16 rsrv0; 4790 #elif defined(__LITTLE_ENDIAN) 4791 u16 rsrv0; 4792 u8 op_attr; 4793 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) 4794 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 4795 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4796 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4797 u8 opcode; 4798 #endif 4799 u32 data_fields; 4800 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4801 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4802 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4803 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4804 u32 rsrv2[2]; 4805 u32 itt; 4806 #if defined(__BIG_ENDIAN) 4807 u16 cid; 4808 u16 rsrv1; 4809 #elif defined(__LITTLE_ENDIAN) 4810 u16 rsrv1; 4811 u16 cid; 4812 #endif 4813 u32 cmd_sn; 4814 u32 exp_stat_sn; 4815 u32 rsrv3[4]; 4816 }; 4817 4818 /* 4819 * PDU header of an iSCSI TMF request 4820 */ 4821 struct iscsi_tmf_req_hdr_little_endian { 4822 #if defined(__BIG_ENDIAN) 4823 u8 opcode; 4824 u8 op_attr; 4825 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) 4826 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 4827 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4828 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4829 u16 rsrv0; 4830 #elif defined(__LITTLE_ENDIAN) 4831 u16 rsrv0; 4832 u8 op_attr; 4833 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) 4834 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 4835 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4836 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4837 u8 opcode; 4838 #endif 4839 u32 data_fields; 4840 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4841 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4842 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4843 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4844 struct regpair lun; 4845 u32 itt; 4846 u32 referenced_task_tag; 4847 u32 cmd_sn; 4848 u32 exp_stat_sn; 4849 u32 ref_cmd_sn; 4850 u32 exp_data_sn; 4851 u32 rsrv2[2]; 4852 }; 4853 4854 /* 4855 * PDU header of an iSCSI Text request 4856 */ 4857 struct iscsi_text_req_hdr_little_endian { 4858 #if defined(__BIG_ENDIAN) 4859 u8 opcode; 4860 u8 op_attr; 4861 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) 4862 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4863 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4864 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4865 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) 4866 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 4867 u16 rsrv0; 4868 #elif defined(__LITTLE_ENDIAN) 4869 u16 rsrv0; 4870 u8 op_attr; 4871 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) 4872 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4873 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4874 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4875 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) 4876 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 4877 u8 opcode; 4878 #endif 4879 u32 data_fields; 4880 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4881 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4882 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4883 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4884 struct regpair lun; 4885 u32 itt; 4886 u32 ttt; 4887 u32 cmd_sn; 4888 u32 exp_stat_sn; 4889 u32 rsrv3[4]; 4890 }; 4891 4892 /* 4893 * PDU header of an iSCSI Nop-Out 4894 */ 4895 struct iscsi_nop_out_hdr_little_endian { 4896 #if defined(__BIG_ENDIAN) 4897 u8 opcode; 4898 u8 op_attr; 4899 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4900 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4901 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) 4902 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 4903 u16 rsrv0; 4904 #elif defined(__LITTLE_ENDIAN) 4905 u16 rsrv0; 4906 u8 op_attr; 4907 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4908 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4909 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) 4910 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 4911 u8 opcode; 4912 #endif 4913 u32 data_fields; 4914 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4915 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4916 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4917 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4918 struct regpair lun; 4919 u32 itt; 4920 u32 ttt; 4921 u32 cmd_sn; 4922 u32 exp_stat_sn; 4923 u32 rsrv3[4]; 4924 }; 4925 4926 /* 4927 * iscsi pdu headers in little endian form. 4928 */ 4929 union iscsi_pdu_headers_little_endian { 4930 u32 fullHeaderSize[12]; 4931 struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr; 4932 struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr; 4933 struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr; 4934 struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr; 4935 struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr; 4936 struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr; 4937 struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr; 4938 }; 4939 4940 struct iscsi_hq_bd { 4941 union iscsi_pdu_headers_little_endian pdu_header; 4942 #if defined(__BIG_ENDIAN) 4943 u16 reserved1; 4944 u16 lcl_cmp_flg; 4945 #elif defined(__LITTLE_ENDIAN) 4946 u16 lcl_cmp_flg; 4947 u16 reserved1; 4948 #endif 4949 u32 sgl_base_lo; 4950 u32 sgl_base_hi; 4951 #if defined(__BIG_ENDIAN) 4952 u8 sgl_size; 4953 u8 sge_index; 4954 u16 sge_offset; 4955 #elif defined(__LITTLE_ENDIAN) 4956 u16 sge_offset; 4957 u8 sge_index; 4958 u8 sgl_size; 4959 #endif 4960 }; 4961 4962 4963 /* 4964 * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$ 4965 */ 4966 struct iscsi_l2_ooo_data { 4967 __le32 iscsi_cid; 4968 u8 drop_isle; 4969 u8 drop_size; 4970 u8 ooo_opcode; 4971 u8 ooo_isle; 4972 u8 reserved[8]; 4973 }; 4974 4975 4976 4977 4978 4979 4980 struct iscsi_task_context_entry_xuc_c_write_only { 4981 u32 total_data_acked; 4982 }; 4983 4984 struct iscsi_task_context_r2t_table_entry { 4985 u32 ttt; 4986 u32 desired_data_len; 4987 }; 4988 4989 struct iscsi_task_context_entry_xuc_u_write_only { 4990 u32 exp_r2t_sn; 4991 struct iscsi_task_context_r2t_table_entry r2t_table[4]; 4992 #if defined(__BIG_ENDIAN) 4993 u16 data_in_count; 4994 u8 cq_id; 4995 u8 valid_1b; 4996 #elif defined(__LITTLE_ENDIAN) 4997 u8 valid_1b; 4998 u8 cq_id; 4999 u16 data_in_count; 5000 #endif 5001 }; 5002 5003 struct iscsi_task_context_entry_xuc { 5004 struct iscsi_task_context_entry_xuc_c_write_only write_c; 5005 u32 exp_data_transfer_len; 5006 struct iscsi_task_context_entry_xuc_x_write_only write_x; 5007 u32 lun_lo; 5008 struct iscsi_task_context_entry_xuc_xu_write_both write_xu; 5009 u32 lun_hi; 5010 struct iscsi_task_context_entry_xuc_u_write_only write_u; 5011 }; 5012 5013 struct iscsi_task_context_entry_u { 5014 u32 exp_r2t_buff_offset; 5015 u32 rem_rcv_len; 5016 u32 exp_data_sn; 5017 }; 5018 5019 struct iscsi_task_context_entry { 5020 struct iscsi_task_context_entry_x tce_x; 5021 #if defined(__BIG_ENDIAN) 5022 u16 data_out_count; 5023 u16 rsrv0; 5024 #elif defined(__LITTLE_ENDIAN) 5025 u16 rsrv0; 5026 u16 data_out_count; 5027 #endif 5028 struct iscsi_task_context_entry_xuc tce_xuc; 5029 struct iscsi_task_context_entry_u tce_u; 5030 u32 rsrv1[7]; 5031 }; 5032 5033 5034 5035 5036 5037 5038 5039 5040 struct iscsi_task_context_entry_xuc_x_init_only { 5041 struct regpair lun; 5042 u32 exp_data_transfer_len; 5043 }; 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 /* 5062 * ipv6 structure 5063 */ 5064 struct ip_v6_addr { 5065 u32 ip_addr_lo_lo; 5066 u32 ip_addr_lo_hi; 5067 u32 ip_addr_hi_lo; 5068 u32 ip_addr_hi_hi; 5069 }; 5070 5071 5072 5073 /* 5074 * l5cm- connection identification params 5075 */ 5076 struct l5cm_conn_addr_params { 5077 u32 pmtu; 5078 #if defined(__BIG_ENDIAN) 5079 u8 remote_addr_3; 5080 u8 remote_addr_2; 5081 u8 remote_addr_1; 5082 u8 remote_addr_0; 5083 #elif defined(__LITTLE_ENDIAN) 5084 u8 remote_addr_0; 5085 u8 remote_addr_1; 5086 u8 remote_addr_2; 5087 u8 remote_addr_3; 5088 #endif 5089 #if defined(__BIG_ENDIAN) 5090 u16 params; 5091 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) 5092 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 5093 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) 5094 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 5095 u8 remote_addr_5; 5096 u8 remote_addr_4; 5097 #elif defined(__LITTLE_ENDIAN) 5098 u8 remote_addr_4; 5099 u8 remote_addr_5; 5100 u16 params; 5101 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) 5102 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 5103 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) 5104 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 5105 #endif 5106 struct ip_v6_addr local_ip_addr; 5107 struct ip_v6_addr remote_ip_addr; 5108 u32 ipv6_flow_label_20b; 5109 u32 reserved1; 5110 #if defined(__BIG_ENDIAN) 5111 u16 remote_tcp_port; 5112 u16 local_tcp_port; 5113 #elif defined(__LITTLE_ENDIAN) 5114 u16 local_tcp_port; 5115 u16 remote_tcp_port; 5116 #endif 5117 }; 5118 5119 /* 5120 * l5cm-xstorm connection buffer 5121 */ 5122 struct l5cm_xstorm_conn_buffer { 5123 #if defined(__BIG_ENDIAN) 5124 u16 rsrv1; 5125 u16 params; 5126 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) 5127 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 5128 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5129 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 5130 #elif defined(__LITTLE_ENDIAN) 5131 u16 params; 5132 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) 5133 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 5134 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5135 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 5136 u16 rsrv1; 5137 #endif 5138 #if defined(__BIG_ENDIAN) 5139 u16 mss; 5140 u16 pseudo_header_checksum; 5141 #elif defined(__LITTLE_ENDIAN) 5142 u16 pseudo_header_checksum; 5143 u16 mss; 5144 #endif 5145 u32 rcv_buf; 5146 u32 rsrv2; 5147 struct regpair context_addr; 5148 }; 5149 5150 /* 5151 * l5cm-tstorm connection buffer 5152 */ 5153 struct l5cm_tstorm_conn_buffer { 5154 u32 rsrv1[2]; 5155 #if defined(__BIG_ENDIAN) 5156 u16 params; 5157 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) 5158 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 5159 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5160 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 5161 u8 ka_max_probe_count; 5162 u8 ka_enable; 5163 #elif defined(__LITTLE_ENDIAN) 5164 u8 ka_enable; 5165 u8 ka_max_probe_count; 5166 u16 params; 5167 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) 5168 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 5169 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5170 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 5171 #endif 5172 u32 ka_timeout; 5173 u32 ka_interval; 5174 u32 max_rt_time; 5175 }; 5176 5177 /* 5178 * l5cm connection buffer for active side 5179 */ 5180 struct l5cm_active_conn_buffer { 5181 struct l5cm_conn_addr_params conn_addr_buf; 5182 struct l5cm_xstorm_conn_buffer xstorm_conn_buffer; 5183 struct l5cm_tstorm_conn_buffer tstorm_conn_buffer; 5184 }; 5185 5186 5187 5188 /* 5189 * The l5cm opaque buffer passed in add new connection ramrod passive side 5190 */ 5191 struct l5cm_hash_input_string { 5192 u32 __opaque1; 5193 #if defined(__BIG_ENDIAN) 5194 u16 __opaque3; 5195 u16 __opaque2; 5196 #elif defined(__LITTLE_ENDIAN) 5197 u16 __opaque2; 5198 u16 __opaque3; 5199 #endif 5200 struct ip_v6_addr __opaque4; 5201 struct ip_v6_addr __opaque5; 5202 u32 __opaque6; 5203 u32 __opaque7[5]; 5204 }; 5205 5206 5207 /* 5208 * syn cookie component 5209 */ 5210 struct l5cm_syn_cookie_comp { 5211 u32 __opaque; 5212 }; 5213 5214 /* 5215 * data related to listeners of a TCP port 5216 */ 5217 struct l5cm_port_listener_data { 5218 u8 params; 5219 #define L5CM_PORT_LISTENER_DATA_ENABLE (0x1<<0) 5220 #define L5CM_PORT_LISTENER_DATA_ENABLE_SHIFT 0 5221 #define L5CM_PORT_LISTENER_DATA_IP_INDEX (0xF<<1) 5222 #define L5CM_PORT_LISTENER_DATA_IP_INDEX_SHIFT 1 5223 #define L5CM_PORT_LISTENER_DATA_NET_FILTER (0x1<<5) 5224 #define L5CM_PORT_LISTENER_DATA_NET_FILTER_SHIFT 5 5225 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE (0x1<<6) 5226 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE_SHIFT 6 5227 #define L5CM_PORT_LISTENER_DATA_MPA_MODE (0x1<<7) 5228 #define L5CM_PORT_LISTENER_DATA_MPA_MODE_SHIFT 7 5229 }; 5230 5231 /* 5232 * Opaque structure passed from U to X when final ack arrives 5233 */ 5234 struct l5cm_opaque_buf { 5235 u32 __opaque1; 5236 u32 __opaque2; 5237 u32 __opaque3; 5238 u32 __opaque4; 5239 struct l5cm_syn_cookie_comp __opaque5; 5240 #if defined(__BIG_ENDIAN) 5241 u16 rsrv2; 5242 u8 rsrv; 5243 struct l5cm_port_listener_data __opaque6; 5244 #elif defined(__LITTLE_ENDIAN) 5245 struct l5cm_port_listener_data __opaque6; 5246 u8 rsrv; 5247 u16 rsrv2; 5248 #endif 5249 }; 5250 5251 5252 /* 5253 * l5cm slow path element 5254 */ 5255 struct l5cm_packet_size { 5256 u32 size; 5257 u32 rsrv; 5258 }; 5259 5260 5261 /* 5262 * The final-ack union structure in PCS entry after final ack arrived 5263 */ 5264 struct l5cm_pcse_ack { 5265 struct l5cm_xstorm_conn_buffer tx_socket_params; 5266 struct l5cm_opaque_buf opaque_buf; 5267 struct l5cm_tstorm_conn_buffer rx_socket_params; 5268 }; 5269 5270 5271 /* 5272 * The syn union structure in PCS entry after syn arrived 5273 */ 5274 struct l5cm_pcse_syn { 5275 struct l5cm_opaque_buf opaque_buf; 5276 u32 rsrv[12]; 5277 }; 5278 5279 5280 /* 5281 * pcs entry data for passive connections 5282 */ 5283 struct l5cm_pcs_attributes { 5284 #if defined(__BIG_ENDIAN) 5285 u16 pcs_id; 5286 u8 status; 5287 u8 flags; 5288 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0) 5289 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0 5290 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1) 5291 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1 5292 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2) 5293 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2 5294 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3) 5295 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3 5296 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4) 5297 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4 5298 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5) 5299 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5 5300 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6) 5301 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6 5302 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7) 5303 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7 5304 #elif defined(__LITTLE_ENDIAN) 5305 u8 flags; 5306 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0) 5307 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0 5308 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1) 5309 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1 5310 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2) 5311 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2 5312 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3) 5313 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3 5314 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4) 5315 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4 5316 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5) 5317 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5 5318 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6) 5319 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6 5320 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7) 5321 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7 5322 u8 status; 5323 u16 pcs_id; 5324 #endif 5325 }; 5326 5327 5328 union l5cm_seg_params { 5329 struct l5cm_pcse_syn syn_seg_params; 5330 struct l5cm_pcse_ack ack_seg_params; 5331 }; 5332 5333 /* 5334 * pcs entry data for passive connections 5335 */ 5336 struct l5cm_pcs_hdr { 5337 struct l5cm_hash_input_string hash_input_string; 5338 struct l5cm_conn_addr_params conn_addr_buf; 5339 u32 cid; 5340 u32 hash_result; 5341 union l5cm_seg_params seg_params; 5342 struct l5cm_pcs_attributes att; 5343 #if defined(__BIG_ENDIAN) 5344 u16 rsrv; 5345 u16 rx_seg_size; 5346 #elif defined(__LITTLE_ENDIAN) 5347 u16 rx_seg_size; 5348 u16 rsrv; 5349 #endif 5350 }; 5351 5352 /* 5353 * pcs entry for passive connections 5354 */ 5355 struct l5cm_pcs_entry { 5356 struct l5cm_pcs_hdr hdr; 5357 u8 rx_segment[1516]; 5358 }; 5359 5360 5361 5362 5363 /* 5364 * l5cm connection parameters 5365 */ 5366 union l5cm_reduce_param_union { 5367 u32 opaque1; 5368 u32 opaque2; 5369 }; 5370 5371 /* 5372 * l5cm connection parameters 5373 */ 5374 struct l5cm_reduce_conn { 5375 union l5cm_reduce_param_union opaque1; 5376 u32 opaque2; 5377 }; 5378 5379 /* 5380 * l5cm slow path element 5381 */ 5382 union l5cm_specific_data { 5383 u8 protocol_data[8]; 5384 struct regpair phy_address; 5385 struct l5cm_packet_size packet_size; 5386 struct l5cm_reduce_conn reduced_conn; 5387 }; 5388 5389 /* 5390 * l5 slow path element 5391 */ 5392 struct l5cm_spe { 5393 struct spe_hdr hdr; 5394 union l5cm_specific_data data; 5395 }; 5396 5397 5398 5399 5400 /* 5401 * Termination variables 5402 */ 5403 struct l5cm_term_vars { 5404 u8 BitMap; 5405 #define L5CM_TERM_VARS_TCP_STATE (0xF<<0) 5406 #define L5CM_TERM_VARS_TCP_STATE_SHIFT 0 5407 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) 5408 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 5409 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) 5410 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 5411 #define L5CM_TERM_VARS_TERM_ON_CHIP (0x1<<6) 5412 #define L5CM_TERM_VARS_TERM_ON_CHIP_SHIFT 6 5413 #define L5CM_TERM_VARS_RSRV (0x1<<7) 5414 #define L5CM_TERM_VARS_RSRV_SHIFT 7 5415 }; 5416 5417 5418 5419 5420 /* 5421 * Tstorm Tcp flags 5422 */ 5423 struct tstorm_l5cm_tcp_flags { 5424 u16 flags; 5425 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) 5426 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0 5427 #define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12) 5428 #define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12 5429 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) 5430 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13 5431 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) 5432 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14 5433 }; 5434 5435 5436 /* 5437 * Xstorm Tcp flags 5438 */ 5439 struct xstorm_l5cm_tcp_flags { 5440 u8 flags; 5441 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0) 5442 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0 5443 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1) 5444 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1 5445 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2) 5446 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2 5447 #define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3) 5448 #define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3 5449 }; 5450 5451 5452 5453 /* 5454 * Out-of-order states 5455 */ 5456 enum tcp_ooo_event { 5457 TCP_EVENT_ADD_PEN = 0, 5458 TCP_EVENT_ADD_NEW_ISLE = 1, 5459 TCP_EVENT_ADD_ISLE_RIGHT = 2, 5460 TCP_EVENT_ADD_ISLE_LEFT = 3, 5461 TCP_EVENT_JOIN = 4, 5462 TCP_EVENT_NOP = 5, 5463 MAX_TCP_OOO_EVENT 5464 }; 5465 5466 5467 /* 5468 * OOO support modes 5469 */ 5470 enum tcp_tstorm_ooo { 5471 TCP_TSTORM_OOO_DROP_AND_PROC_ACK = 0, 5472 TCP_TSTORM_OOO_SEND_PURE_ACK = 1, 5473 TCP_TSTORM_OOO_SUPPORTED = 2, 5474 MAX_TCP_TSTORM_OOO 5475 }; 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 #endif /* __5710_HSI_CNIC_LE__ */ 5486