1 2 /* cnic.c: Broadcom CNIC core network driver. 3 * 4 * Copyright (c) 2006-2012 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 */ 11 12 #ifndef CNIC_DEFS_H 13 #define CNIC_DEFS_H 14 15 /* KWQ (kernel work queue) request op codes */ 16 #define L2_KWQE_OPCODE_VALUE_FLUSH (4) 17 #define L2_KWQE_OPCODE_VALUE_VM_FREE_RX_QUEUE (8) 18 19 #define L4_KWQE_OPCODE_VALUE_CONNECT1 (50) 20 #define L4_KWQE_OPCODE_VALUE_CONNECT2 (51) 21 #define L4_KWQE_OPCODE_VALUE_CONNECT3 (52) 22 #define L4_KWQE_OPCODE_VALUE_RESET (53) 23 #define L4_KWQE_OPCODE_VALUE_CLOSE (54) 24 #define L4_KWQE_OPCODE_VALUE_UPDATE_SECRET (60) 25 #define L4_KWQE_OPCODE_VALUE_INIT_ULP (61) 26 27 #define L4_KWQE_OPCODE_VALUE_OFFLOAD_PG (1) 28 #define L4_KWQE_OPCODE_VALUE_UPDATE_PG (9) 29 #define L4_KWQE_OPCODE_VALUE_UPLOAD_PG (14) 30 31 #define L5CM_RAMROD_CMD_ID_BASE (0x80) 32 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3) 33 #define L5CM_RAMROD_CMD_ID_CLOSE (L5CM_RAMROD_CMD_ID_BASE + 12) 34 #define L5CM_RAMROD_CMD_ID_ABORT (L5CM_RAMROD_CMD_ID_BASE + 13) 35 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE (L5CM_RAMROD_CMD_ID_BASE + 14) 36 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD (L5CM_RAMROD_CMD_ID_BASE + 15) 37 38 #define FCOE_KCQE_OPCODE_INIT_FUNC (0x10) 39 #define FCOE_KCQE_OPCODE_DESTROY_FUNC (0x11) 40 #define FCOE_KCQE_OPCODE_STAT_FUNC (0x12) 41 #define FCOE_KCQE_OPCODE_OFFLOAD_CONN (0x15) 42 #define FCOE_KCQE_OPCODE_ENABLE_CONN (0x16) 43 #define FCOE_KCQE_OPCODE_DISABLE_CONN (0x17) 44 #define FCOE_KCQE_OPCODE_DESTROY_CONN (0x18) 45 #define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION (0x20) 46 #define FCOE_KCQE_OPCODE_FCOE_ERROR (0x21) 47 48 #define FCOE_RAMROD_CMD_ID_INIT_FUNC (FCOE_KCQE_OPCODE_INIT_FUNC) 49 #define FCOE_RAMROD_CMD_ID_DESTROY_FUNC (FCOE_KCQE_OPCODE_DESTROY_FUNC) 50 #define FCOE_RAMROD_CMD_ID_STAT_FUNC (FCOE_KCQE_OPCODE_STAT_FUNC) 51 #define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN (FCOE_KCQE_OPCODE_OFFLOAD_CONN) 52 #define FCOE_RAMROD_CMD_ID_ENABLE_CONN (FCOE_KCQE_OPCODE_ENABLE_CONN) 53 #define FCOE_RAMROD_CMD_ID_DISABLE_CONN (FCOE_KCQE_OPCODE_DISABLE_CONN) 54 #define FCOE_RAMROD_CMD_ID_DESTROY_CONN (FCOE_KCQE_OPCODE_DESTROY_CONN) 55 #define FCOE_RAMROD_CMD_ID_TERMINATE_CONN (0x81) 56 57 #define FCOE_KWQE_OPCODE_INIT1 (0) 58 #define FCOE_KWQE_OPCODE_INIT2 (1) 59 #define FCOE_KWQE_OPCODE_INIT3 (2) 60 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN1 (3) 61 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN2 (4) 62 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN3 (5) 63 #define FCOE_KWQE_OPCODE_OFFLOAD_CONN4 (6) 64 #define FCOE_KWQE_OPCODE_ENABLE_CONN (7) 65 #define FCOE_KWQE_OPCODE_DISABLE_CONN (8) 66 #define FCOE_KWQE_OPCODE_DESTROY_CONN (9) 67 #define FCOE_KWQE_OPCODE_DESTROY (10) 68 #define FCOE_KWQE_OPCODE_STAT (11) 69 70 #define FCOE_KCQE_COMPLETION_STATUS_ERROR (0x1) 71 #define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE (0x3) 72 #define FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR (0x5) 73 74 /* KCQ (kernel completion queue) response op codes */ 75 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP (53) 76 #define L4_KCQE_OPCODE_VALUE_RESET_COMP (54) 77 #define L4_KCQE_OPCODE_VALUE_FW_TCP_UPDATE (55) 78 #define L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE (56) 79 #define L4_KCQE_OPCODE_VALUE_RESET_RECEIVED (57) 80 #define L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED (58) 81 #define L4_KCQE_OPCODE_VALUE_INIT_ULP (61) 82 83 #define L4_KCQE_OPCODE_VALUE_OFFLOAD_PG (1) 84 #define L4_KCQE_OPCODE_VALUE_UPDATE_PG (9) 85 #define L4_KCQE_OPCODE_VALUE_UPLOAD_PG (14) 86 87 /* KCQ (kernel completion queue) completion status */ 88 #define L4_KCQE_COMPLETION_STATUS_SUCCESS (0) 89 #define L4_KCQE_COMPLETION_STATUS_NIC_ERROR (4) 90 #define L4_KCQE_COMPLETION_STATUS_TIMEOUT (0x93) 91 92 #define L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL (0x83) 93 #define L4_KCQE_COMPLETION_STATUS_OFFLOADED_PG (0x89) 94 95 #define L4_KCQE_OPCODE_VALUE_OOO_EVENT_NOTIFICATION (0xa0) 96 #define L4_KCQE_OPCODE_VALUE_OOO_FLUSH (0xa1) 97 98 #define L4_LAYER_CODE (4) 99 #define L2_LAYER_CODE (2) 100 101 /* 102 * L4 KCQ CQE 103 */ 104 struct l4_kcq { 105 u32 cid; 106 u32 pg_cid; 107 u32 conn_id; 108 u32 pg_host_opaque; 109 #if defined(__BIG_ENDIAN) 110 u16 status; 111 u16 reserved1; 112 #elif defined(__LITTLE_ENDIAN) 113 u16 reserved1; 114 u16 status; 115 #endif 116 u32 reserved2[2]; 117 #if defined(__BIG_ENDIAN) 118 u8 flags; 119 #define L4_KCQ_RESERVED3 (0x7<<0) 120 #define L4_KCQ_RESERVED3_SHIFT 0 121 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ 122 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 123 #define L4_KCQ_LAYER_CODE (0x7<<4) 124 #define L4_KCQ_LAYER_CODE_SHIFT 4 125 #define L4_KCQ_RESERVED4 (0x1<<7) 126 #define L4_KCQ_RESERVED4_SHIFT 7 127 u8 op_code; 128 u16 qe_self_seq; 129 #elif defined(__LITTLE_ENDIAN) 130 u16 qe_self_seq; 131 u8 op_code; 132 u8 flags; 133 #define L4_KCQ_RESERVED3 (0xF<<0) 134 #define L4_KCQ_RESERVED3_SHIFT 0 135 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */ 136 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3 137 #define L4_KCQ_LAYER_CODE (0x7<<4) 138 #define L4_KCQ_LAYER_CODE_SHIFT 4 139 #define L4_KCQ_RESERVED4 (0x1<<7) 140 #define L4_KCQ_RESERVED4_SHIFT 7 141 #endif 142 }; 143 144 145 /* 146 * L4 KCQ CQE PG upload 147 */ 148 struct l4_kcq_upload_pg { 149 u32 pg_cid; 150 #if defined(__BIG_ENDIAN) 151 u16 pg_status; 152 u16 pg_ipid_count; 153 #elif defined(__LITTLE_ENDIAN) 154 u16 pg_ipid_count; 155 u16 pg_status; 156 #endif 157 u32 reserved1[5]; 158 #if defined(__BIG_ENDIAN) 159 u8 flags; 160 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) 161 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 162 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) 163 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 164 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) 165 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 166 u8 op_code; 167 u16 qe_self_seq; 168 #elif defined(__LITTLE_ENDIAN) 169 u16 qe_self_seq; 170 u8 op_code; 171 u8 flags; 172 #define L4_KCQ_UPLOAD_PG_RESERVED3 (0xF<<0) 173 #define L4_KCQ_UPLOAD_PG_RESERVED3_SHIFT 0 174 #define L4_KCQ_UPLOAD_PG_LAYER_CODE (0x7<<4) 175 #define L4_KCQ_UPLOAD_PG_LAYER_CODE_SHIFT 4 176 #define L4_KCQ_UPLOAD_PG_RESERVED4 (0x1<<7) 177 #define L4_KCQ_UPLOAD_PG_RESERVED4_SHIFT 7 178 #endif 179 }; 180 181 182 /* 183 * Gracefully close the connection request 184 */ 185 struct l4_kwq_close_req { 186 #if defined(__BIG_ENDIAN) 187 u8 flags; 188 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) 189 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 190 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) 191 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 192 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) 193 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 194 u8 op_code; 195 u16 reserved0; 196 #elif defined(__LITTLE_ENDIAN) 197 u16 reserved0; 198 u8 op_code; 199 u8 flags; 200 #define L4_KWQ_CLOSE_REQ_RESERVED1 (0xF<<0) 201 #define L4_KWQ_CLOSE_REQ_RESERVED1_SHIFT 0 202 #define L4_KWQ_CLOSE_REQ_LAYER_CODE (0x7<<4) 203 #define L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT 4 204 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT (0x1<<7) 205 #define L4_KWQ_CLOSE_REQ_LINKED_WITH_NEXT_SHIFT 7 206 #endif 207 u32 cid; 208 u32 reserved2[6]; 209 }; 210 211 212 /* 213 * The first request to be passed in order to establish connection in option2 214 */ 215 struct l4_kwq_connect_req1 { 216 #if defined(__BIG_ENDIAN) 217 u8 flags; 218 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) 219 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 220 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) 221 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 222 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) 223 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 224 u8 op_code; 225 u8 reserved0; 226 u8 conn_flags; 227 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) 228 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 229 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) 230 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 231 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) 232 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 233 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) 234 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 235 #elif defined(__LITTLE_ENDIAN) 236 u8 conn_flags; 237 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE (0x1<<0) 238 #define L4_KWQ_CONNECT_REQ1_IS_PG_HOST_OPAQUE_SHIFT 0 239 #define L4_KWQ_CONNECT_REQ1_IP_V6 (0x1<<1) 240 #define L4_KWQ_CONNECT_REQ1_IP_V6_SHIFT 1 241 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG (0x1<<2) 242 #define L4_KWQ_CONNECT_REQ1_PASSIVE_FLAG_SHIFT 2 243 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3) 244 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3 245 u8 reserved0; 246 u8 op_code; 247 u8 flags; 248 #define L4_KWQ_CONNECT_REQ1_RESERVED1 (0xF<<0) 249 #define L4_KWQ_CONNECT_REQ1_RESERVED1_SHIFT 0 250 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE (0x7<<4) 251 #define L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT 4 252 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT (0x1<<7) 253 #define L4_KWQ_CONNECT_REQ1_LINKED_WITH_NEXT_SHIFT 7 254 #endif 255 u32 cid; 256 u32 pg_cid; 257 u32 src_ip; 258 u32 dst_ip; 259 #if defined(__BIG_ENDIAN) 260 u16 dst_port; 261 u16 src_port; 262 #elif defined(__LITTLE_ENDIAN) 263 u16 src_port; 264 u16 dst_port; 265 #endif 266 #if defined(__BIG_ENDIAN) 267 u8 rsrv1[3]; 268 u8 tcp_flags; 269 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) 270 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 271 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) 272 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 273 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) 274 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 275 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) 276 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 277 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) 278 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 279 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) 280 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 281 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 282 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 283 #elif defined(__LITTLE_ENDIAN) 284 u8 tcp_flags; 285 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK (0x1<<0) 286 #define L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK_SHIFT 0 287 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE (0x1<<1) 288 #define L4_KWQ_CONNECT_REQ1_KEEP_ALIVE_SHIFT 1 289 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE (0x1<<2) 290 #define L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE_SHIFT 2 291 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP (0x1<<3) 292 #define L4_KWQ_CONNECT_REQ1_TIME_STAMP_SHIFT 3 293 #define L4_KWQ_CONNECT_REQ1_SACK (0x1<<4) 294 #define L4_KWQ_CONNECT_REQ1_SACK_SHIFT 4 295 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING (0x1<<5) 296 #define L4_KWQ_CONNECT_REQ1_SEG_SCALING_SHIFT 5 297 #define L4_KWQ_CONNECT_REQ1_RESERVED2 (0x3<<6) 298 #define L4_KWQ_CONNECT_REQ1_RESERVED2_SHIFT 6 299 u8 rsrv1[3]; 300 #endif 301 u32 rsrv2; 302 }; 303 304 305 /* 306 * The second ( optional )request to be passed in order to establish 307 * connection in option2 - for IPv6 only 308 */ 309 struct l4_kwq_connect_req2 { 310 #if defined(__BIG_ENDIAN) 311 u8 flags; 312 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) 313 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 314 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) 315 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 316 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) 317 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 318 u8 op_code; 319 u8 reserved0; 320 u8 rsrv; 321 #elif defined(__LITTLE_ENDIAN) 322 u8 rsrv; 323 u8 reserved0; 324 u8 op_code; 325 u8 flags; 326 #define L4_KWQ_CONNECT_REQ2_RESERVED1 (0xF<<0) 327 #define L4_KWQ_CONNECT_REQ2_RESERVED1_SHIFT 0 328 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE (0x7<<4) 329 #define L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT 4 330 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT (0x1<<7) 331 #define L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT_SHIFT 7 332 #endif 333 u32 reserved2; 334 u32 src_ip_v6_2; 335 u32 src_ip_v6_3; 336 u32 src_ip_v6_4; 337 u32 dst_ip_v6_2; 338 u32 dst_ip_v6_3; 339 u32 dst_ip_v6_4; 340 }; 341 342 343 /* 344 * The third ( and last )request to be passed in order to establish 345 * connection in option2 346 */ 347 struct l4_kwq_connect_req3 { 348 #if defined(__BIG_ENDIAN) 349 u8 flags; 350 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) 351 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 352 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) 353 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 354 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) 355 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 356 u8 op_code; 357 u16 reserved0; 358 #elif defined(__LITTLE_ENDIAN) 359 u16 reserved0; 360 u8 op_code; 361 u8 flags; 362 #define L4_KWQ_CONNECT_REQ3_RESERVED1 (0xF<<0) 363 #define L4_KWQ_CONNECT_REQ3_RESERVED1_SHIFT 0 364 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE (0x7<<4) 365 #define L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT 4 366 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT (0x1<<7) 367 #define L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT_SHIFT 7 368 #endif 369 u32 ka_timeout; 370 u32 ka_interval ; 371 #if defined(__BIG_ENDIAN) 372 u8 snd_seq_scale; 373 u8 ttl; 374 u8 tos; 375 u8 ka_max_probe_count; 376 #elif defined(__LITTLE_ENDIAN) 377 u8 ka_max_probe_count; 378 u8 tos; 379 u8 ttl; 380 u8 snd_seq_scale; 381 #endif 382 #if defined(__BIG_ENDIAN) 383 u16 pmtu; 384 u16 mss; 385 #elif defined(__LITTLE_ENDIAN) 386 u16 mss; 387 u16 pmtu; 388 #endif 389 u32 rcv_buf; 390 u32 snd_buf; 391 u32 seed; 392 }; 393 394 395 /* 396 * a KWQE request to offload a PG connection 397 */ 398 struct l4_kwq_offload_pg { 399 #if defined(__BIG_ENDIAN) 400 u8 flags; 401 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) 402 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 403 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) 404 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 405 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) 406 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 407 u8 op_code; 408 u16 reserved0; 409 #elif defined(__LITTLE_ENDIAN) 410 u16 reserved0; 411 u8 op_code; 412 u8 flags; 413 #define L4_KWQ_OFFLOAD_PG_RESERVED1 (0xF<<0) 414 #define L4_KWQ_OFFLOAD_PG_RESERVED1_SHIFT 0 415 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE (0x7<<4) 416 #define L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT 4 417 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT (0x1<<7) 418 #define L4_KWQ_OFFLOAD_PG_LINKED_WITH_NEXT_SHIFT 7 419 #endif 420 #if defined(__BIG_ENDIAN) 421 u8 l2hdr_nbytes; 422 u8 pg_flags; 423 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) 424 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 425 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) 426 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 427 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) 428 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 429 u8 da0; 430 u8 da1; 431 #elif defined(__LITTLE_ENDIAN) 432 u8 da1; 433 u8 da0; 434 u8 pg_flags; 435 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP (0x1<<0) 436 #define L4_KWQ_OFFLOAD_PG_SNAP_ENCAP_SHIFT 0 437 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING (0x1<<1) 438 #define L4_KWQ_OFFLOAD_PG_VLAN_TAGGING_SHIFT 1 439 #define L4_KWQ_OFFLOAD_PG_RESERVED2 (0x3F<<2) 440 #define L4_KWQ_OFFLOAD_PG_RESERVED2_SHIFT 2 441 u8 l2hdr_nbytes; 442 #endif 443 #if defined(__BIG_ENDIAN) 444 u8 da2; 445 u8 da3; 446 u8 da4; 447 u8 da5; 448 #elif defined(__LITTLE_ENDIAN) 449 u8 da5; 450 u8 da4; 451 u8 da3; 452 u8 da2; 453 #endif 454 #if defined(__BIG_ENDIAN) 455 u8 sa0; 456 u8 sa1; 457 u8 sa2; 458 u8 sa3; 459 #elif defined(__LITTLE_ENDIAN) 460 u8 sa3; 461 u8 sa2; 462 u8 sa1; 463 u8 sa0; 464 #endif 465 #if defined(__BIG_ENDIAN) 466 u8 sa4; 467 u8 sa5; 468 u16 etype; 469 #elif defined(__LITTLE_ENDIAN) 470 u16 etype; 471 u8 sa5; 472 u8 sa4; 473 #endif 474 #if defined(__BIG_ENDIAN) 475 u16 vlan_tag; 476 u16 ipid_start; 477 #elif defined(__LITTLE_ENDIAN) 478 u16 ipid_start; 479 u16 vlan_tag; 480 #endif 481 #if defined(__BIG_ENDIAN) 482 u16 ipid_count; 483 u16 reserved3; 484 #elif defined(__LITTLE_ENDIAN) 485 u16 reserved3; 486 u16 ipid_count; 487 #endif 488 u32 host_opaque; 489 }; 490 491 492 /* 493 * Abortively close the connection request 494 */ 495 struct l4_kwq_reset_req { 496 #if defined(__BIG_ENDIAN) 497 u8 flags; 498 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) 499 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 500 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) 501 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 502 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) 503 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 504 u8 op_code; 505 u16 reserved0; 506 #elif defined(__LITTLE_ENDIAN) 507 u16 reserved0; 508 u8 op_code; 509 u8 flags; 510 #define L4_KWQ_RESET_REQ_RESERVED1 (0xF<<0) 511 #define L4_KWQ_RESET_REQ_RESERVED1_SHIFT 0 512 #define L4_KWQ_RESET_REQ_LAYER_CODE (0x7<<4) 513 #define L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT 4 514 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT (0x1<<7) 515 #define L4_KWQ_RESET_REQ_LINKED_WITH_NEXT_SHIFT 7 516 #endif 517 u32 cid; 518 u32 reserved2[6]; 519 }; 520 521 522 /* 523 * a KWQE request to update a PG connection 524 */ 525 struct l4_kwq_update_pg { 526 #if defined(__BIG_ENDIAN) 527 u8 flags; 528 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) 529 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 530 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) 531 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 532 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) 533 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 534 u8 opcode; 535 u16 oper16; 536 #elif defined(__LITTLE_ENDIAN) 537 u16 oper16; 538 u8 opcode; 539 u8 flags; 540 #define L4_KWQ_UPDATE_PG_RESERVED1 (0xF<<0) 541 #define L4_KWQ_UPDATE_PG_RESERVED1_SHIFT 0 542 #define L4_KWQ_UPDATE_PG_LAYER_CODE (0x7<<4) 543 #define L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT 4 544 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT (0x1<<7) 545 #define L4_KWQ_UPDATE_PG_LINKED_WITH_NEXT_SHIFT 7 546 #endif 547 u32 pg_cid; 548 u32 pg_host_opaque; 549 #if defined(__BIG_ENDIAN) 550 u8 pg_valids; 551 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) 552 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 553 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) 554 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 555 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) 556 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 557 u8 pg_unused_a; 558 u16 pg_ipid_count; 559 #elif defined(__LITTLE_ENDIAN) 560 u16 pg_ipid_count; 561 u8 pg_unused_a; 562 u8 pg_valids; 563 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT (0x1<<0) 564 #define L4_KWQ_UPDATE_PG_VALIDS_IPID_COUNT_SHIFT 0 565 #define L4_KWQ_UPDATE_PG_VALIDS_DA (0x1<<1) 566 #define L4_KWQ_UPDATE_PG_VALIDS_DA_SHIFT 1 567 #define L4_KWQ_UPDATE_PG_RESERVERD2 (0x3F<<2) 568 #define L4_KWQ_UPDATE_PG_RESERVERD2_SHIFT 2 569 #endif 570 #if defined(__BIG_ENDIAN) 571 u16 reserverd3; 572 u8 da0; 573 u8 da1; 574 #elif defined(__LITTLE_ENDIAN) 575 u8 da1; 576 u8 da0; 577 u16 reserverd3; 578 #endif 579 #if defined(__BIG_ENDIAN) 580 u8 da2; 581 u8 da3; 582 u8 da4; 583 u8 da5; 584 #elif defined(__LITTLE_ENDIAN) 585 u8 da5; 586 u8 da4; 587 u8 da3; 588 u8 da2; 589 #endif 590 u32 reserved4; 591 u32 reserved5; 592 }; 593 594 595 /* 596 * a KWQE request to upload a PG or L4 context 597 */ 598 struct l4_kwq_upload { 599 #if defined(__BIG_ENDIAN) 600 u8 flags; 601 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) 602 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 603 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) 604 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 605 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) 606 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 607 u8 opcode; 608 u16 oper16; 609 #elif defined(__LITTLE_ENDIAN) 610 u16 oper16; 611 u8 opcode; 612 u8 flags; 613 #define L4_KWQ_UPLOAD_RESERVED1 (0xF<<0) 614 #define L4_KWQ_UPLOAD_RESERVED1_SHIFT 0 615 #define L4_KWQ_UPLOAD_LAYER_CODE (0x7<<4) 616 #define L4_KWQ_UPLOAD_LAYER_CODE_SHIFT 4 617 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT (0x1<<7) 618 #define L4_KWQ_UPLOAD_LINKED_WITH_NEXT_SHIFT 7 619 #endif 620 u32 cid; 621 u32 reserved2[6]; 622 }; 623 624 /* 625 * bnx2x structures 626 */ 627 628 /* 629 * The iscsi aggregative context of Cstorm 630 */ 631 struct cstorm_iscsi_ag_context { 632 u32 agg_vars1; 633 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) 634 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0 635 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) 636 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8 637 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) 638 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9 639 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) 640 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10 641 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) 642 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11 643 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) 644 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12 645 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) 646 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13 647 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) 648 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14 649 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) 650 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16 651 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) 652 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18 653 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) 654 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19 655 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) 656 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20 657 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21) 658 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21 659 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22) 660 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22 661 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) 662 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23 663 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) 664 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26 665 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) 666 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28 667 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) 668 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30 669 #if defined(__BIG_ENDIAN) 670 u8 __aux1_th; 671 u8 __aux1_val; 672 u16 __agg_vars2; 673 #elif defined(__LITTLE_ENDIAN) 674 u16 __agg_vars2; 675 u8 __aux1_val; 676 u8 __aux1_th; 677 #endif 678 u32 rel_seq; 679 u32 rel_seq_th; 680 #if defined(__BIG_ENDIAN) 681 u16 hq_cons; 682 u16 hq_prod; 683 #elif defined(__LITTLE_ENDIAN) 684 u16 hq_prod; 685 u16 hq_cons; 686 #endif 687 #if defined(__BIG_ENDIAN) 688 u8 __reserved62; 689 u8 __reserved61; 690 u8 __reserved60; 691 u8 __reserved59; 692 #elif defined(__LITTLE_ENDIAN) 693 u8 __reserved59; 694 u8 __reserved60; 695 u8 __reserved61; 696 u8 __reserved62; 697 #endif 698 #if defined(__BIG_ENDIAN) 699 u16 __reserved64; 700 u16 cq_u_prod; 701 #elif defined(__LITTLE_ENDIAN) 702 u16 cq_u_prod; 703 u16 __reserved64; 704 #endif 705 u32 __cq_u_prod1; 706 #if defined(__BIG_ENDIAN) 707 u16 __agg_vars3; 708 u16 cq_u_pend; 709 #elif defined(__LITTLE_ENDIAN) 710 u16 cq_u_pend; 711 u16 __agg_vars3; 712 #endif 713 #if defined(__BIG_ENDIAN) 714 u16 __aux2_th; 715 u16 aux2_val; 716 #elif defined(__LITTLE_ENDIAN) 717 u16 aux2_val; 718 u16 __aux2_th; 719 #endif 720 }; 721 722 /* 723 * The fcoe extra aggregative context section of Tstorm 724 */ 725 struct tstorm_fcoe_extra_ag_context_section { 726 u32 __agg_val1; 727 #if defined(__BIG_ENDIAN) 728 u8 __tcp_agg_vars2; 729 u8 __agg_val3; 730 u16 __agg_val2; 731 #elif defined(__LITTLE_ENDIAN) 732 u16 __agg_val2; 733 u8 __agg_val3; 734 u8 __tcp_agg_vars2; 735 #endif 736 #if defined(__BIG_ENDIAN) 737 u16 __agg_val5; 738 u8 __agg_val6; 739 u8 __tcp_agg_vars3; 740 #elif defined(__LITTLE_ENDIAN) 741 u8 __tcp_agg_vars3; 742 u8 __agg_val6; 743 u16 __agg_val5; 744 #endif 745 u32 __lcq_prod; 746 u32 rtt_seq; 747 u32 rtt_time; 748 u32 __reserved66; 749 u32 wnd_right_edge; 750 u32 tcp_agg_vars1; 751 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 752 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 753 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) 754 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 755 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 756 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 757 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 758 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 759 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) 760 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 761 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) 762 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 763 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) 764 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 765 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) 766 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9 767 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) 768 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 769 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) 770 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 771 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) 772 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 773 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) 774 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 775 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) 776 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 777 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) 778 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 779 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) 780 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 781 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) 782 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 783 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) 784 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 785 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) 786 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 787 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) 788 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 789 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) 790 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 791 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) 792 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 793 u32 snd_max; 794 u32 __lcq_cons; 795 u32 __reserved2; 796 }; 797 798 /* 799 * The fcoe aggregative context of Tstorm 800 */ 801 struct tstorm_fcoe_ag_context { 802 #if defined(__BIG_ENDIAN) 803 u16 ulp_credit; 804 u8 agg_vars1; 805 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 806 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 807 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 808 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 809 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 810 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 811 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 812 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 813 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) 814 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 815 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) 816 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 817 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) 818 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 819 u8 state; 820 #elif defined(__LITTLE_ENDIAN) 821 u8 state; 822 u8 agg_vars1; 823 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 824 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 825 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 826 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 827 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 828 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 829 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 830 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 831 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) 832 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4 833 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) 834 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6 835 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) 836 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7 837 u16 ulp_credit; 838 #endif 839 #if defined(__BIG_ENDIAN) 840 u16 __agg_val4; 841 u16 agg_vars2; 842 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) 843 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 844 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) 845 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 846 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) 847 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 848 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) 849 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 850 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) 851 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 852 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) 853 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 854 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) 855 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 856 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) 857 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 858 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) 859 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 860 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) 861 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 862 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 863 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 864 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 865 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 866 #elif defined(__LITTLE_ENDIAN) 867 u16 agg_vars2; 868 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) 869 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0 870 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) 871 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1 872 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) 873 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2 874 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) 875 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4 876 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) 877 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6 878 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) 879 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8 880 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) 881 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10 882 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) 883 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11 884 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) 885 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12 886 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) 887 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13 888 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 889 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 890 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 891 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 892 u16 __agg_val4; 893 #endif 894 struct tstorm_fcoe_extra_ag_context_section __extra_section; 895 }; 896 897 898 899 /* 900 * The tcp aggregative context section of Tstorm 901 */ 902 struct tstorm_tcp_tcp_ag_context_section { 903 u32 __agg_val1; 904 #if defined(__BIG_ENDIAN) 905 u8 __tcp_agg_vars2; 906 u8 __agg_val3; 907 u16 __agg_val2; 908 #elif defined(__LITTLE_ENDIAN) 909 u16 __agg_val2; 910 u8 __agg_val3; 911 u8 __tcp_agg_vars2; 912 #endif 913 #if defined(__BIG_ENDIAN) 914 u16 __agg_val5; 915 u8 __agg_val6; 916 u8 __tcp_agg_vars3; 917 #elif defined(__LITTLE_ENDIAN) 918 u8 __tcp_agg_vars3; 919 u8 __agg_val6; 920 u16 __agg_val5; 921 #endif 922 u32 snd_nxt; 923 u32 rtt_seq; 924 u32 rtt_time; 925 u32 __reserved66; 926 u32 wnd_right_edge; 927 u32 tcp_agg_vars1; 928 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) 929 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0 930 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) 931 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1 932 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) 933 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2 934 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) 935 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4 936 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) 937 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6 938 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) 939 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7 940 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) 941 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8 942 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) 943 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9 944 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) 945 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10 946 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) 947 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11 948 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) 949 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12 950 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) 951 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13 952 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) 953 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14 954 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) 955 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16 956 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) 957 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18 958 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) 959 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19 960 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) 961 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20 962 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) 963 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21 964 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) 965 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22 966 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) 967 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24 968 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) 969 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28 970 u32 snd_max; 971 u32 snd_una; 972 u32 __reserved2; 973 }; 974 975 /* 976 * The iscsi aggregative context of Tstorm 977 */ 978 struct tstorm_iscsi_ag_context { 979 #if defined(__BIG_ENDIAN) 980 u16 ulp_credit; 981 u8 agg_vars1; 982 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 983 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 984 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 985 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 986 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 987 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 988 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 989 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 990 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) 991 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 992 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) 993 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 994 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) 995 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 996 u8 state; 997 #elif defined(__LITTLE_ENDIAN) 998 u8 state; 999 u8 agg_vars1; 1000 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1001 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1002 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1003 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1004 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1005 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1006 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1007 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1008 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) 1009 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4 1010 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) 1011 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6 1012 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) 1013 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7 1014 u16 ulp_credit; 1015 #endif 1016 #if defined(__BIG_ENDIAN) 1017 u16 __agg_val4; 1018 u16 agg_vars2; 1019 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) 1020 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 1021 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) 1022 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 1023 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) 1024 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 1025 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) 1026 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 1027 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) 1028 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 1029 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) 1030 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 1031 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) 1032 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 1033 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) 1034 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 1035 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) 1036 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 1037 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) 1038 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 1039 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 1040 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 1041 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 1042 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 1043 #elif defined(__LITTLE_ENDIAN) 1044 u16 agg_vars2; 1045 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) 1046 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0 1047 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) 1048 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1 1049 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) 1050 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2 1051 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) 1052 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4 1053 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) 1054 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6 1055 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) 1056 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8 1057 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) 1058 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10 1059 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) 1060 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11 1061 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) 1062 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12 1063 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) 1064 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13 1065 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) 1066 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14 1067 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) 1068 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15 1069 u16 __agg_val4; 1070 #endif 1071 struct tstorm_tcp_tcp_ag_context_section tcp; 1072 }; 1073 1074 1075 1076 /* 1077 * The fcoe aggregative context of Ustorm 1078 */ 1079 struct ustorm_fcoe_ag_context { 1080 #if defined(__BIG_ENDIAN) 1081 u8 __aux_counter_flags; 1082 u8 agg_vars2; 1083 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) 1084 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 1085 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) 1086 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 1087 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1088 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1089 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1090 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1091 u8 agg_vars1; 1092 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1093 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1094 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1095 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1096 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1097 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1098 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1099 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1100 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) 1101 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 1102 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1103 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1104 u8 state; 1105 #elif defined(__LITTLE_ENDIAN) 1106 u8 state; 1107 u8 agg_vars1; 1108 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1109 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1110 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1111 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1112 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1113 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1114 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1115 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1116 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) 1117 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4 1118 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1119 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1120 u8 agg_vars2; 1121 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) 1122 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0 1123 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) 1124 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2 1125 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1126 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1127 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1128 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1129 u8 __aux_counter_flags; 1130 #endif 1131 #if defined(__BIG_ENDIAN) 1132 u8 cdu_usage; 1133 u8 agg_misc2; 1134 u16 pbf_tx_seq_ack; 1135 #elif defined(__LITTLE_ENDIAN) 1136 u16 pbf_tx_seq_ack; 1137 u8 agg_misc2; 1138 u8 cdu_usage; 1139 #endif 1140 u32 agg_misc4; 1141 #if defined(__BIG_ENDIAN) 1142 u8 agg_val3_th; 1143 u8 agg_val3; 1144 u16 agg_misc3; 1145 #elif defined(__LITTLE_ENDIAN) 1146 u16 agg_misc3; 1147 u8 agg_val3; 1148 u8 agg_val3_th; 1149 #endif 1150 u32 expired_task_id; 1151 u32 agg_misc4_th; 1152 #if defined(__BIG_ENDIAN) 1153 u16 cq_prod; 1154 u16 cq_cons; 1155 #elif defined(__LITTLE_ENDIAN) 1156 u16 cq_cons; 1157 u16 cq_prod; 1158 #endif 1159 #if defined(__BIG_ENDIAN) 1160 u16 __reserved2; 1161 u8 decision_rules; 1162 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) 1163 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 1164 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1165 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1166 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) 1167 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 1168 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) 1169 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 1170 u8 decision_rule_enable_bits; 1171 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) 1172 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 1173 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1174 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1175 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) 1176 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 1177 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1178 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1179 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) 1180 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 1181 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) 1182 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 1183 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1184 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1185 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1186 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1187 #elif defined(__LITTLE_ENDIAN) 1188 u8 decision_rule_enable_bits; 1189 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) 1190 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0 1191 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1192 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1193 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) 1194 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2 1195 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1196 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1197 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) 1198 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4 1199 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) 1200 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5 1201 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1202 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1203 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1204 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1205 u8 decision_rules; 1206 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) 1207 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0 1208 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1209 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1210 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) 1211 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6 1212 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) 1213 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7 1214 u16 __reserved2; 1215 #endif 1216 }; 1217 1218 1219 /* 1220 * The iscsi aggregative context of Ustorm 1221 */ 1222 struct ustorm_iscsi_ag_context { 1223 #if defined(__BIG_ENDIAN) 1224 u8 __aux_counter_flags; 1225 u8 agg_vars2; 1226 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) 1227 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 1228 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) 1229 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 1230 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1231 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1232 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1233 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1234 u8 agg_vars1; 1235 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1236 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1237 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1238 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1239 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1240 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1241 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1242 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1243 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) 1244 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 1245 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1246 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1247 u8 state; 1248 #elif defined(__LITTLE_ENDIAN) 1249 u8 state; 1250 u8 agg_vars1; 1251 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1252 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1253 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1254 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1255 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1256 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1257 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1258 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1259 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) 1260 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4 1261 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) 1262 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6 1263 u8 agg_vars2; 1264 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) 1265 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0 1266 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) 1267 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2 1268 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) 1269 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4 1270 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) 1271 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7 1272 u8 __aux_counter_flags; 1273 #endif 1274 #if defined(__BIG_ENDIAN) 1275 u8 cdu_usage; 1276 u8 agg_misc2; 1277 u16 __cq_local_comp_itt_val; 1278 #elif defined(__LITTLE_ENDIAN) 1279 u16 __cq_local_comp_itt_val; 1280 u8 agg_misc2; 1281 u8 cdu_usage; 1282 #endif 1283 u32 agg_misc4; 1284 #if defined(__BIG_ENDIAN) 1285 u8 agg_val3_th; 1286 u8 agg_val3; 1287 u16 agg_misc3; 1288 #elif defined(__LITTLE_ENDIAN) 1289 u16 agg_misc3; 1290 u8 agg_val3; 1291 u8 agg_val3_th; 1292 #endif 1293 u32 agg_val1; 1294 u32 agg_misc4_th; 1295 #if defined(__BIG_ENDIAN) 1296 u16 agg_val2_th; 1297 u16 agg_val2; 1298 #elif defined(__LITTLE_ENDIAN) 1299 u16 agg_val2; 1300 u16 agg_val2_th; 1301 #endif 1302 #if defined(__BIG_ENDIAN) 1303 u16 __reserved2; 1304 u8 decision_rules; 1305 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) 1306 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 1307 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1308 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1309 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) 1310 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 1311 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) 1312 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 1313 u8 decision_rule_enable_bits; 1314 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) 1315 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 1316 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1317 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1318 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) 1319 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 1320 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1321 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1322 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) 1323 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 1324 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) 1325 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 1326 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1327 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1328 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1329 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1330 #elif defined(__LITTLE_ENDIAN) 1331 u8 decision_rule_enable_bits; 1332 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) 1333 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0 1334 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) 1335 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1 1336 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) 1337 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2 1338 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) 1339 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3 1340 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) 1341 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4 1342 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) 1343 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5 1344 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) 1345 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6 1346 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1347 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1348 u8 decision_rules; 1349 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) 1350 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0 1351 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) 1352 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3 1353 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) 1354 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6 1355 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) 1356 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7 1357 u16 __reserved2; 1358 #endif 1359 }; 1360 1361 1362 /* 1363 * The fcoe aggregative context section of Xstorm 1364 */ 1365 struct xstorm_fcoe_extra_ag_context_section { 1366 #if defined(__BIG_ENDIAN) 1367 u8 tcp_agg_vars1; 1368 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) 1369 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 1370 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1371 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1372 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1373 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1374 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) 1375 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 1376 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) 1377 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 1378 u8 __reserved_da_cnt; 1379 u16 __mtu; 1380 #elif defined(__LITTLE_ENDIAN) 1381 u16 __mtu; 1382 u8 __reserved_da_cnt; 1383 u8 tcp_agg_vars1; 1384 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) 1385 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0 1386 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1387 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1388 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1389 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1390 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) 1391 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6 1392 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) 1393 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7 1394 #endif 1395 u32 snd_nxt; 1396 u32 tx_wnd; 1397 u32 __reserved55; 1398 u32 local_adv_wnd; 1399 #if defined(__BIG_ENDIAN) 1400 u8 __agg_val8_th; 1401 u8 __tx_dest; 1402 u16 tcp_agg_vars2; 1403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) 1404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 1405 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) 1406 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 1407 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) 1408 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 1409 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1410 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1411 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) 1414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 1415 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) 1416 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 1417 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1418 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) 1420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 1421 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1422 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1423 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1424 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1425 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1426 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1427 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1428 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1429 #elif defined(__LITTLE_ENDIAN) 1430 u16 tcp_agg_vars2; 1431 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) 1432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0 1433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) 1434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1 1435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) 1436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2 1437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) 1442 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5 1443 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) 1444 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6 1445 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1446 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1447 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) 1448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8 1449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1454 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1455 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1456 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1457 u8 __tx_dest; 1458 u8 __agg_val8_th; 1459 #endif 1460 u32 __sq_base_addr_lo; 1461 u32 __sq_base_addr_hi; 1462 u32 __xfrq_base_addr_lo; 1463 u32 __xfrq_base_addr_hi; 1464 #if defined(__BIG_ENDIAN) 1465 u16 __xfrq_cons; 1466 u16 __xfrq_prod; 1467 #elif defined(__LITTLE_ENDIAN) 1468 u16 __xfrq_prod; 1469 u16 __xfrq_cons; 1470 #endif 1471 #if defined(__BIG_ENDIAN) 1472 u8 __tcp_agg_vars5; 1473 u8 __tcp_agg_vars4; 1474 u8 __tcp_agg_vars3; 1475 u8 __reserved_force_pure_ack_cnt; 1476 #elif defined(__LITTLE_ENDIAN) 1477 u8 __reserved_force_pure_ack_cnt; 1478 u8 __tcp_agg_vars3; 1479 u8 __tcp_agg_vars4; 1480 u8 __tcp_agg_vars5; 1481 #endif 1482 u32 __tcp_agg_vars6; 1483 #if defined(__BIG_ENDIAN) 1484 u16 __agg_misc6; 1485 u16 __tcp_agg_vars7; 1486 #elif defined(__LITTLE_ENDIAN) 1487 u16 __tcp_agg_vars7; 1488 u16 __agg_misc6; 1489 #endif 1490 u32 __agg_val10; 1491 u32 __agg_val10_th; 1492 #if defined(__BIG_ENDIAN) 1493 u16 __reserved3; 1494 u8 __reserved2; 1495 u8 __da_only_cnt; 1496 #elif defined(__LITTLE_ENDIAN) 1497 u8 __da_only_cnt; 1498 u8 __reserved2; 1499 u16 __reserved3; 1500 #endif 1501 }; 1502 1503 /* 1504 * The fcoe aggregative context of Xstorm 1505 */ 1506 struct xstorm_fcoe_ag_context { 1507 #if defined(__BIG_ENDIAN) 1508 u16 agg_val1; 1509 u8 agg_vars1; 1510 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1511 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1512 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1513 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1514 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) 1515 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 1516 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) 1517 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 1518 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1519 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1520 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) 1521 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 1522 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1523 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1524 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) 1525 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 1526 u8 __state; 1527 #elif defined(__LITTLE_ENDIAN) 1528 u8 __state; 1529 u8 agg_vars1; 1530 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1531 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1532 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1533 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1534 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) 1535 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2 1536 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) 1537 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3 1538 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1539 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1540 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) 1541 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5 1542 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1543 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1544 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) 1545 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7 1546 u16 agg_val1; 1547 #endif 1548 #if defined(__BIG_ENDIAN) 1549 u8 cdu_reserved; 1550 u8 __agg_vars4; 1551 u8 agg_vars3; 1552 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1553 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1554 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) 1555 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 1556 u8 agg_vars2; 1557 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) 1558 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 1559 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1560 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1561 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1562 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1563 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1564 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1565 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1566 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1567 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1568 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1569 #elif defined(__LITTLE_ENDIAN) 1570 u8 agg_vars2; 1571 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) 1572 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0 1573 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1574 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1575 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1576 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1577 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1578 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1579 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1580 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1581 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1582 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1583 u8 agg_vars3; 1584 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1585 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1586 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) 1587 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6 1588 u8 __agg_vars4; 1589 u8 cdu_reserved; 1590 #endif 1591 u32 more_to_send; 1592 #if defined(__BIG_ENDIAN) 1593 u16 agg_vars5; 1594 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 1595 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 1596 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 1597 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 1598 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 1599 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 1600 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) 1601 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 1602 u16 sq_cons; 1603 #elif defined(__LITTLE_ENDIAN) 1604 u16 sq_cons; 1605 u16 agg_vars5; 1606 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 1607 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0 1608 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 1609 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 1610 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 1611 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 1612 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) 1613 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14 1614 #endif 1615 struct xstorm_fcoe_extra_ag_context_section __extra_section; 1616 #if defined(__BIG_ENDIAN) 1617 u16 agg_vars7; 1618 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 1619 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 1620 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) 1621 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 1622 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) 1623 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 1624 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 1625 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 1626 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) 1627 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 1628 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) 1629 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 1630 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 1631 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 1632 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) 1633 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 1634 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) 1635 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 1636 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) 1637 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 1638 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) 1639 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 1640 u8 agg_val3_th; 1641 u8 agg_vars6; 1642 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 1643 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 1644 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) 1645 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 1646 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) 1647 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 1648 #elif defined(__LITTLE_ENDIAN) 1649 u8 agg_vars6; 1650 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 1651 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0 1652 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) 1653 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3 1654 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) 1655 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6 1656 u8 agg_val3_th; 1657 u16 agg_vars7; 1658 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 1659 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 1660 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) 1661 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3 1662 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) 1663 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4 1664 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 1665 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6 1666 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) 1667 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8 1668 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) 1669 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10 1670 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 1671 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 1672 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) 1673 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12 1674 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) 1675 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13 1676 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) 1677 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14 1678 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) 1679 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15 1680 #endif 1681 #if defined(__BIG_ENDIAN) 1682 u16 __agg_val11_th; 1683 u16 __agg_val11; 1684 #elif defined(__LITTLE_ENDIAN) 1685 u16 __agg_val11; 1686 u16 __agg_val11_th; 1687 #endif 1688 #if defined(__BIG_ENDIAN) 1689 u8 __reserved1; 1690 u8 __agg_val6_th; 1691 u16 __agg_val9; 1692 #elif defined(__LITTLE_ENDIAN) 1693 u16 __agg_val9; 1694 u8 __agg_val6_th; 1695 u8 __reserved1; 1696 #endif 1697 #if defined(__BIG_ENDIAN) 1698 u16 confq_cons; 1699 u16 confq_prod; 1700 #elif defined(__LITTLE_ENDIAN) 1701 u16 confq_prod; 1702 u16 confq_cons; 1703 #endif 1704 u32 agg_vars8; 1705 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 1706 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0 1707 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 1708 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24 1709 #if defined(__BIG_ENDIAN) 1710 u16 agg_misc0; 1711 u16 sq_prod; 1712 #elif defined(__LITTLE_ENDIAN) 1713 u16 sq_prod; 1714 u16 agg_misc0; 1715 #endif 1716 #if defined(__BIG_ENDIAN) 1717 u8 agg_val3; 1718 u8 agg_val6; 1719 u8 agg_val5_th; 1720 u8 agg_val5; 1721 #elif defined(__LITTLE_ENDIAN) 1722 u8 agg_val5; 1723 u8 agg_val5_th; 1724 u8 agg_val6; 1725 u8 agg_val3; 1726 #endif 1727 #if defined(__BIG_ENDIAN) 1728 u16 __agg_misc1; 1729 u16 agg_limit1; 1730 #elif defined(__LITTLE_ENDIAN) 1731 u16 agg_limit1; 1732 u16 __agg_misc1; 1733 #endif 1734 u32 completion_seq; 1735 u32 confq_pbl_base_lo; 1736 u32 confq_pbl_base_hi; 1737 }; 1738 1739 1740 1741 /* 1742 * The tcp aggregative context section of Xstorm 1743 */ 1744 struct xstorm_tcp_tcp_ag_context_section { 1745 #if defined(__BIG_ENDIAN) 1746 u8 tcp_agg_vars1; 1747 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) 1748 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 1749 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1750 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1751 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1752 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1753 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) 1754 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 1755 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) 1756 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 1757 u8 __da_cnt; 1758 u16 mss; 1759 #elif defined(__LITTLE_ENDIAN) 1760 u16 mss; 1761 u8 __da_cnt; 1762 u8 tcp_agg_vars1; 1763 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) 1764 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0 1765 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) 1766 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2 1767 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) 1768 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4 1769 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) 1770 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6 1771 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) 1772 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7 1773 #endif 1774 u32 snd_nxt; 1775 u32 tx_wnd; 1776 u32 snd_una; 1777 u32 local_adv_wnd; 1778 #if defined(__BIG_ENDIAN) 1779 u8 __agg_val8_th; 1780 u8 __tx_dest; 1781 u16 tcp_agg_vars2; 1782 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) 1783 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 1784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) 1785 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 1786 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) 1787 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 1788 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1789 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1790 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1791 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1792 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) 1793 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 1794 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) 1795 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 1796 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1797 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1798 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) 1799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 1800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1801 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1802 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1803 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1804 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1805 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1806 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1807 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1808 #elif defined(__LITTLE_ENDIAN) 1809 u16 tcp_agg_vars2; 1810 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) 1811 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0 1812 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) 1813 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1 1814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) 1815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2 1816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) 1817 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3 1818 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) 1819 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4 1820 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) 1821 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5 1822 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) 1823 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6 1824 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) 1825 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7 1826 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) 1827 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8 1828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) 1829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9 1830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) 1831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10 1832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) 1833 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12 1834 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) 1835 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14 1836 u8 __tx_dest; 1837 u8 __agg_val8_th; 1838 #endif 1839 u32 ack_to_far_end; 1840 u32 rto_timer; 1841 u32 ka_timer; 1842 u32 ts_to_echo; 1843 #if defined(__BIG_ENDIAN) 1844 u16 __agg_val7_th; 1845 u16 __agg_val7; 1846 #elif defined(__LITTLE_ENDIAN) 1847 u16 __agg_val7; 1848 u16 __agg_val7_th; 1849 #endif 1850 #if defined(__BIG_ENDIAN) 1851 u8 __tcp_agg_vars5; 1852 u8 __tcp_agg_vars4; 1853 u8 __tcp_agg_vars3; 1854 u8 __force_pure_ack_cnt; 1855 #elif defined(__LITTLE_ENDIAN) 1856 u8 __force_pure_ack_cnt; 1857 u8 __tcp_agg_vars3; 1858 u8 __tcp_agg_vars4; 1859 u8 __tcp_agg_vars5; 1860 #endif 1861 u32 tcp_agg_vars6; 1862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) 1863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0 1864 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) 1865 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1 1866 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) 1867 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2 1868 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) 1869 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3 1870 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) 1871 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4 1872 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) 1873 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5 1874 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) 1875 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6 1876 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) 1877 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8 1878 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) 1879 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10 1880 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) 1881 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12 1882 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) 1883 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14 1884 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) 1885 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16 1886 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) 1887 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18 1888 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) 1889 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20 1890 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) 1891 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22 1892 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) 1893 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24 1894 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) 1895 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26 1896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) 1897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27 1898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) 1899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28 1900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) 1901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29 1902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) 1903 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30 1904 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) 1905 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31 1906 #if defined(__BIG_ENDIAN) 1907 u16 __agg_misc6; 1908 u16 __tcp_agg_vars7; 1909 #elif defined(__LITTLE_ENDIAN) 1910 u16 __tcp_agg_vars7; 1911 u16 __agg_misc6; 1912 #endif 1913 u32 __agg_val10; 1914 u32 __agg_val10_th; 1915 #if defined(__BIG_ENDIAN) 1916 u16 __reserved3; 1917 u8 __reserved2; 1918 u8 __da_only_cnt; 1919 #elif defined(__LITTLE_ENDIAN) 1920 u8 __da_only_cnt; 1921 u8 __reserved2; 1922 u16 __reserved3; 1923 #endif 1924 }; 1925 1926 /* 1927 * The iscsi aggregative context of Xstorm 1928 */ 1929 struct xstorm_iscsi_ag_context { 1930 #if defined(__BIG_ENDIAN) 1931 u16 agg_val1; 1932 u8 agg_vars1; 1933 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1934 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1935 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1936 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1937 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1938 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1939 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1940 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1941 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1942 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1943 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) 1944 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 1945 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1946 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1947 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 1948 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 1949 u8 state; 1950 #elif defined(__LITTLE_ENDIAN) 1951 u8 state; 1952 u8 agg_vars1; 1953 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 1954 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 1955 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 1956 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 1957 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 1958 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 1959 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 1960 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 1961 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 1962 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 1963 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) 1964 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5 1965 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 1966 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 1967 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 1968 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 1969 u16 agg_val1; 1970 #endif 1971 #if defined(__BIG_ENDIAN) 1972 u8 cdu_reserved; 1973 u8 __agg_vars4; 1974 u8 agg_vars3; 1975 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 1976 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 1977 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 1978 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 1979 u8 agg_vars2; 1980 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) 1981 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 1982 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1983 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1984 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1985 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 1986 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) 1987 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 1988 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 1989 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 1990 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 1991 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 1992 #elif defined(__LITTLE_ENDIAN) 1993 u8 agg_vars2; 1994 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) 1995 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0 1996 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 1997 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 1998 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) 1999 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2000 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2001 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2002 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2003 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2004 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) 2005 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7 2006 u8 agg_vars3; 2007 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2008 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2009 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2010 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2011 u8 __agg_vars4; 2012 u8 cdu_reserved; 2013 #endif 2014 u32 more_to_send; 2015 #if defined(__BIG_ENDIAN) 2016 u16 agg_vars5; 2017 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2018 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2019 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2020 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2021 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2022 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2023 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2024 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2025 u16 sq_cons; 2026 #elif defined(__LITTLE_ENDIAN) 2027 u16 sq_cons; 2028 u16 agg_vars5; 2029 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2030 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2031 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2032 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2033 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2034 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2035 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2036 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2037 #endif 2038 struct xstorm_tcp_tcp_ag_context_section tcp; 2039 #if defined(__BIG_ENDIAN) 2040 u16 agg_vars7; 2041 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2042 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2043 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2044 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2045 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2046 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2047 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2048 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2049 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) 2050 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 2051 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2052 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2053 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2054 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2055 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2056 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2057 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2058 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2059 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2060 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2061 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2062 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2063 u8 agg_val3_th; 2064 u8 agg_vars6; 2065 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2066 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2067 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2068 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2069 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2070 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2071 #elif defined(__LITTLE_ENDIAN) 2072 u8 agg_vars6; 2073 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2074 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2075 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2076 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2077 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2078 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2079 u8 agg_val3_th; 2080 u16 agg_vars7; 2081 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2082 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2083 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2084 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2085 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2086 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2087 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2088 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2089 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) 2090 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8 2091 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2092 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2093 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2094 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2095 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2096 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2097 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2098 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2099 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2100 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2101 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2102 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2103 #endif 2104 #if defined(__BIG_ENDIAN) 2105 u16 __agg_val11_th; 2106 u16 __gen_data; 2107 #elif defined(__LITTLE_ENDIAN) 2108 u16 __gen_data; 2109 u16 __agg_val11_th; 2110 #endif 2111 #if defined(__BIG_ENDIAN) 2112 u8 __reserved1; 2113 u8 __agg_val6_th; 2114 u16 __agg_val9; 2115 #elif defined(__LITTLE_ENDIAN) 2116 u16 __agg_val9; 2117 u8 __agg_val6_th; 2118 u8 __reserved1; 2119 #endif 2120 #if defined(__BIG_ENDIAN) 2121 u16 hq_prod; 2122 u16 hq_cons; 2123 #elif defined(__LITTLE_ENDIAN) 2124 u16 hq_cons; 2125 u16 hq_prod; 2126 #endif 2127 u32 agg_vars8; 2128 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 2129 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0 2130 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 2131 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24 2132 #if defined(__BIG_ENDIAN) 2133 u16 r2tq_prod; 2134 u16 sq_prod; 2135 #elif defined(__LITTLE_ENDIAN) 2136 u16 sq_prod; 2137 u16 r2tq_prod; 2138 #endif 2139 #if defined(__BIG_ENDIAN) 2140 u8 agg_val3; 2141 u8 agg_val6; 2142 u8 agg_val5_th; 2143 u8 agg_val5; 2144 #elif defined(__LITTLE_ENDIAN) 2145 u8 agg_val5; 2146 u8 agg_val5_th; 2147 u8 agg_val6; 2148 u8 agg_val3; 2149 #endif 2150 #if defined(__BIG_ENDIAN) 2151 u16 __agg_misc1; 2152 u16 agg_limit1; 2153 #elif defined(__LITTLE_ENDIAN) 2154 u16 agg_limit1; 2155 u16 __agg_misc1; 2156 #endif 2157 u32 hq_cons_tcp_seq; 2158 u32 exp_stat_sn; 2159 u32 rst_seq_num; 2160 }; 2161 2162 2163 /* 2164 * The L5cm aggregative context of XStorm 2165 */ 2166 struct xstorm_l5cm_ag_context { 2167 #if defined(__BIG_ENDIAN) 2168 u16 agg_val1; 2169 u8 agg_vars1; 2170 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 2171 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 2172 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 2173 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 2174 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 2175 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 2176 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 2177 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 2178 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 2179 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 2180 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5) 2181 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5 2182 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 2183 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 2184 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 2185 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 2186 u8 state; 2187 #elif defined(__LITTLE_ENDIAN) 2188 u8 state; 2189 u8 agg_vars1; 2190 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) 2191 #define __XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0 2192 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) 2193 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1 2194 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) 2195 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2 2196 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) 2197 #define XSTORM_L5CM_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3 2198 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) 2199 #define __XSTORM_L5CM_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4 2200 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN (0x1<<5) 2201 #define XSTORM_L5CM_AG_CONTEXT_NAGLE_EN_SHIFT 5 2202 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) 2203 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6 2204 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) 2205 #define __XSTORM_L5CM_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7 2206 u16 agg_val1; 2207 #endif 2208 #if defined(__BIG_ENDIAN) 2209 u8 cdu_reserved; 2210 u8 __agg_vars4; 2211 u8 agg_vars3; 2212 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2213 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2214 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2215 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2216 u8 agg_vars2; 2217 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0) 2218 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0 2219 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 2220 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 2221 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3) 2222 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2223 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2224 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2225 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2226 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2227 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7) 2228 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7 2229 #elif defined(__LITTLE_ENDIAN) 2230 u8 agg_vars2; 2231 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF (0x3<<0) 2232 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_SHIFT 0 2233 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) 2234 #define __XSTORM_L5CM_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2 2235 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG (0x1<<3) 2236 #define __XSTORM_L5CM_AG_CONTEXT_AUX8_FLAG_SHIFT 3 2237 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG (0x1<<4) 2238 #define __XSTORM_L5CM_AG_CONTEXT_AUX9_FLAG_SHIFT 4 2239 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1 (0x3<<5) 2240 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE1_SHIFT 5 2241 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN (0x1<<7) 2242 #define XSTORM_L5CM_AG_CONTEXT_AUX4_CF_EN_SHIFT 7 2243 u8 agg_vars3; 2244 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) 2245 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0 2246 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) 2247 #define __XSTORM_L5CM_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6 2248 u8 __agg_vars4; 2249 u8 cdu_reserved; 2250 #endif 2251 u32 more_to_send; 2252 #if defined(__BIG_ENDIAN) 2253 u16 agg_vars5; 2254 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2255 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2256 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2257 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2258 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2259 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2260 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2261 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2262 u16 agg_val4_th; 2263 #elif defined(__LITTLE_ENDIAN) 2264 u16 agg_val4_th; 2265 u16 agg_vars5; 2266 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5 (0x3<<0) 2267 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE5_SHIFT 0 2268 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) 2269 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2 2270 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) 2271 #define XSTORM_L5CM_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8 2272 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2 (0x3<<14) 2273 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE2_SHIFT 14 2274 #endif 2275 struct xstorm_tcp_tcp_ag_context_section tcp; 2276 #if defined(__BIG_ENDIAN) 2277 u16 agg_vars7; 2278 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2279 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2280 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2281 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2282 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2283 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2284 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2285 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2286 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8) 2287 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8 2288 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2289 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2290 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2291 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2292 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2293 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2294 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2295 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2296 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2297 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2298 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2299 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2300 u8 agg_val3_th; 2301 u8 agg_vars6; 2302 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2303 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2304 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2305 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2306 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2307 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2308 #elif defined(__LITTLE_ENDIAN) 2309 u8 agg_vars6; 2310 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6 (0x7<<0) 2311 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE6_SHIFT 0 2312 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7 (0x7<<3) 2313 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE7_SHIFT 3 2314 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4 (0x3<<6) 2315 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE4_SHIFT 6 2316 u8 agg_val3_th; 2317 u16 agg_vars7; 2318 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) 2319 #define __XSTORM_L5CM_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0 2320 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG (0x1<<3) 2321 #define __XSTORM_L5CM_AG_CONTEXT_AUX13_FLAG_SHIFT 3 2322 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) 2323 #define __XSTORM_L5CM_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4 2324 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3 (0x3<<6) 2325 #define XSTORM_L5CM_AG_CONTEXT_DECISION_RULE3_SHIFT 6 2326 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF (0x3<<8) 2327 #define XSTORM_L5CM_AG_CONTEXT_AUX1_CF_SHIFT 8 2328 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) 2329 #define __XSTORM_L5CM_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10 2330 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN (0x1<<11) 2331 #define __XSTORM_L5CM_AG_CONTEXT_AUX1_CF_EN_SHIFT 11 2332 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG (0x1<<12) 2333 #define __XSTORM_L5CM_AG_CONTEXT_AUX10_FLAG_SHIFT 12 2334 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG (0x1<<13) 2335 #define __XSTORM_L5CM_AG_CONTEXT_AUX11_FLAG_SHIFT 13 2336 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG (0x1<<14) 2337 #define __XSTORM_L5CM_AG_CONTEXT_AUX12_FLAG_SHIFT 14 2338 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) 2339 #define __XSTORM_L5CM_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15 2340 #endif 2341 #if defined(__BIG_ENDIAN) 2342 u16 __agg_val11_th; 2343 u16 __gen_data; 2344 #elif defined(__LITTLE_ENDIAN) 2345 u16 __gen_data; 2346 u16 __agg_val11_th; 2347 #endif 2348 #if defined(__BIG_ENDIAN) 2349 u8 __reserved1; 2350 u8 __agg_val6_th; 2351 u16 __agg_val9; 2352 #elif defined(__LITTLE_ENDIAN) 2353 u16 __agg_val9; 2354 u8 __agg_val6_th; 2355 u8 __reserved1; 2356 #endif 2357 #if defined(__BIG_ENDIAN) 2358 u16 agg_val2_th; 2359 u16 agg_val2; 2360 #elif defined(__LITTLE_ENDIAN) 2361 u16 agg_val2; 2362 u16 agg_val2_th; 2363 #endif 2364 u32 agg_vars8; 2365 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) 2366 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC2_SHIFT 0 2367 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3 (0xFF<<24) 2368 #define XSTORM_L5CM_AG_CONTEXT_AGG_MISC3_SHIFT 24 2369 #if defined(__BIG_ENDIAN) 2370 u16 agg_misc0; 2371 u16 agg_val4; 2372 #elif defined(__LITTLE_ENDIAN) 2373 u16 agg_val4; 2374 u16 agg_misc0; 2375 #endif 2376 #if defined(__BIG_ENDIAN) 2377 u8 agg_val3; 2378 u8 agg_val6; 2379 u8 agg_val5_th; 2380 u8 agg_val5; 2381 #elif defined(__LITTLE_ENDIAN) 2382 u8 agg_val5; 2383 u8 agg_val5_th; 2384 u8 agg_val6; 2385 u8 agg_val3; 2386 #endif 2387 #if defined(__BIG_ENDIAN) 2388 u16 __agg_misc1; 2389 u16 agg_limit1; 2390 #elif defined(__LITTLE_ENDIAN) 2391 u16 agg_limit1; 2392 u16 __agg_misc1; 2393 #endif 2394 u32 completion_seq; 2395 u32 agg_misc4; 2396 u32 rst_seq_num; 2397 }; 2398 2399 /* 2400 * ABTS info $$KEEP_ENDIANNESS$$ 2401 */ 2402 struct fcoe_abts_info { 2403 __le16 aborted_task_id; 2404 __le16 reserved0; 2405 __le32 reserved1; 2406 }; 2407 2408 2409 /* 2410 * Fixed size structure in order to plant it in Union structure 2411 * $$KEEP_ENDIANNESS$$ 2412 */ 2413 struct fcoe_abts_rsp_union { 2414 u8 r_ctl; 2415 u8 rsrv[3]; 2416 __le32 abts_rsp_payload[7]; 2417 }; 2418 2419 2420 /* 2421 * 4 regs size $$KEEP_ENDIANNESS$$ 2422 */ 2423 struct fcoe_bd_ctx { 2424 __le32 buf_addr_hi; 2425 __le32 buf_addr_lo; 2426 __le16 buf_len; 2427 __le16 rsrv0; 2428 __le16 flags; 2429 __le16 rsrv1; 2430 }; 2431 2432 2433 /* 2434 * FCoE cached sges context $$KEEP_ENDIANNESS$$ 2435 */ 2436 struct fcoe_cached_sge_ctx { 2437 struct regpair cur_buf_addr; 2438 __le16 cur_buf_rem; 2439 __le16 second_buf_rem; 2440 struct regpair second_buf_addr; 2441 }; 2442 2443 2444 /* 2445 * Cleanup info $$KEEP_ENDIANNESS$$ 2446 */ 2447 struct fcoe_cleanup_info { 2448 __le16 cleaned_task_id; 2449 __le16 rolled_tx_seq_cnt; 2450 __le32 rolled_tx_data_offset; 2451 }; 2452 2453 2454 /* 2455 * Fcp RSP flags $$KEEP_ENDIANNESS$$ 2456 */ 2457 struct fcoe_fcp_rsp_flags { 2458 u8 flags; 2459 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) 2460 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 2461 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) 2462 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 2463 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) 2464 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 2465 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) 2466 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 2467 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) 2468 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 2469 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) 2470 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 2471 }; 2472 2473 /* 2474 * Fcp RSP payload $$KEEP_ENDIANNESS$$ 2475 */ 2476 struct fcoe_fcp_rsp_payload { 2477 struct regpair reserved0; 2478 __le32 fcp_resid; 2479 u8 scsi_status_code; 2480 struct fcoe_fcp_rsp_flags fcp_flags; 2481 __le16 retry_delay_timer; 2482 __le32 fcp_rsp_len; 2483 __le32 fcp_sns_len; 2484 }; 2485 2486 /* 2487 * Fixed size structure in order to plant it in Union structure 2488 * $$KEEP_ENDIANNESS$$ 2489 */ 2490 struct fcoe_fcp_rsp_union { 2491 struct fcoe_fcp_rsp_payload payload; 2492 struct regpair reserved0; 2493 }; 2494 2495 /* 2496 * FC header $$KEEP_ENDIANNESS$$ 2497 */ 2498 struct fcoe_fc_hdr { 2499 u8 s_id[3]; 2500 u8 cs_ctl; 2501 u8 d_id[3]; 2502 u8 r_ctl; 2503 __le16 seq_cnt; 2504 u8 df_ctl; 2505 u8 seq_id; 2506 u8 f_ctl[3]; 2507 u8 type; 2508 __le32 parameters; 2509 __le16 rx_id; 2510 __le16 ox_id; 2511 }; 2512 2513 /* 2514 * FC header union $$KEEP_ENDIANNESS$$ 2515 */ 2516 struct fcoe_mp_rsp_union { 2517 struct fcoe_fc_hdr fc_hdr; 2518 __le32 mp_payload_len; 2519 __le32 rsrv; 2520 }; 2521 2522 /* 2523 * Completion information $$KEEP_ENDIANNESS$$ 2524 */ 2525 union fcoe_comp_flow_info { 2526 struct fcoe_fcp_rsp_union fcp_rsp; 2527 struct fcoe_abts_rsp_union abts_rsp; 2528 struct fcoe_mp_rsp_union mp_rsp; 2529 __le32 opaque[8]; 2530 }; 2531 2532 2533 /* 2534 * External ABTS info $$KEEP_ENDIANNESS$$ 2535 */ 2536 struct fcoe_ext_abts_info { 2537 __le32 rsrv0[6]; 2538 struct fcoe_abts_info ctx; 2539 }; 2540 2541 2542 /* 2543 * External cleanup info $$KEEP_ENDIANNESS$$ 2544 */ 2545 struct fcoe_ext_cleanup_info { 2546 __le32 rsrv0[6]; 2547 struct fcoe_cleanup_info ctx; 2548 }; 2549 2550 2551 /* 2552 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$ 2553 */ 2554 struct fcoe_fw_tx_seq_ctx { 2555 __le32 data_offset; 2556 __le16 seq_cnt; 2557 __le16 rsrv0; 2558 }; 2559 2560 /* 2561 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$ 2562 */ 2563 struct fcoe_ext_fw_tx_seq_ctx { 2564 __le32 rsrv0[6]; 2565 struct fcoe_fw_tx_seq_ctx ctx; 2566 }; 2567 2568 2569 /* 2570 * FCoE multiple sges context $$KEEP_ENDIANNESS$$ 2571 */ 2572 struct fcoe_mul_sges_ctx { 2573 struct regpair cur_sge_addr; 2574 __le16 cur_sge_off; 2575 u8 cur_sge_idx; 2576 u8 sgl_size; 2577 }; 2578 2579 /* 2580 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$ 2581 */ 2582 struct fcoe_ext_mul_sges_ctx { 2583 struct fcoe_mul_sges_ctx mul_sgl; 2584 struct regpair rsrv0; 2585 }; 2586 2587 2588 /* 2589 * FCP CMD payload $$KEEP_ENDIANNESS$$ 2590 */ 2591 struct fcoe_fcp_cmd_payload { 2592 __le32 opaque[8]; 2593 }; 2594 2595 2596 2597 2598 2599 /* 2600 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$ 2601 */ 2602 struct fcoe_fcp_xfr_rdy_payload { 2603 __le32 burst_len; 2604 __le32 data_ro; 2605 }; 2606 2607 2608 /* 2609 * FC frame $$KEEP_ENDIANNESS$$ 2610 */ 2611 struct fcoe_fc_frame { 2612 struct fcoe_fc_hdr fc_hdr; 2613 __le32 reserved0[2]; 2614 }; 2615 2616 2617 2618 2619 /* 2620 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$ 2621 */ 2622 union fcoe_kcqe_params { 2623 __le32 reserved0[4]; 2624 }; 2625 2626 /* 2627 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$ 2628 */ 2629 struct fcoe_kcqe { 2630 __le32 fcoe_conn_id; 2631 __le32 completion_status; 2632 __le32 fcoe_conn_context_id; 2633 union fcoe_kcqe_params params; 2634 __le16 qe_self_seq; 2635 u8 op_code; 2636 u8 flags; 2637 #define FCOE_KCQE_RESERVED0 (0x7<<0) 2638 #define FCOE_KCQE_RESERVED0_SHIFT 0 2639 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) 2640 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 2641 #define FCOE_KCQE_LAYER_CODE (0x7<<4) 2642 #define FCOE_KCQE_LAYER_CODE_SHIFT 4 2643 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 2644 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 2645 }; 2646 2647 2648 2649 /* 2650 * FCoE KWQE header $$KEEP_ENDIANNESS$$ 2651 */ 2652 struct fcoe_kwqe_header { 2653 u8 op_code; 2654 u8 flags; 2655 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 2656 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 2657 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) 2658 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 2659 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 2660 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 2661 }; 2662 2663 /* 2664 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$ 2665 */ 2666 struct fcoe_kwqe_init1 { 2667 __le16 num_tasks; 2668 struct fcoe_kwqe_header hdr; 2669 __le32 task_list_pbl_addr_lo; 2670 __le32 task_list_pbl_addr_hi; 2671 __le32 dummy_buffer_addr_lo; 2672 __le32 dummy_buffer_addr_hi; 2673 __le16 sq_num_wqes; 2674 __le16 rq_num_wqes; 2675 __le16 rq_buffer_log_size; 2676 __le16 cq_num_wqes; 2677 __le16 mtu; 2678 u8 num_sessions_log; 2679 u8 flags; 2680 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 2681 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 2682 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) 2683 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 2684 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 2685 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 2686 }; 2687 2688 /* 2689 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$ 2690 */ 2691 struct fcoe_kwqe_init2 { 2692 u8 hsi_major_version; 2693 u8 hsi_minor_version; 2694 struct fcoe_kwqe_header hdr; 2695 __le32 hash_tbl_pbl_addr_lo; 2696 __le32 hash_tbl_pbl_addr_hi; 2697 __le32 t2_hash_tbl_addr_lo; 2698 __le32 t2_hash_tbl_addr_hi; 2699 __le32 t2_ptr_hash_tbl_addr_lo; 2700 __le32 t2_ptr_hash_tbl_addr_hi; 2701 __le32 free_list_count; 2702 }; 2703 2704 /* 2705 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$ 2706 */ 2707 struct fcoe_kwqe_init3 { 2708 __le16 reserved0; 2709 struct fcoe_kwqe_header hdr; 2710 __le32 error_bit_map_lo; 2711 __le32 error_bit_map_hi; 2712 u8 perf_config; 2713 u8 reserved21[3]; 2714 __le32 reserved2[4]; 2715 }; 2716 2717 /* 2718 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$ 2719 */ 2720 struct fcoe_kwqe_conn_offload1 { 2721 __le16 fcoe_conn_id; 2722 struct fcoe_kwqe_header hdr; 2723 __le32 sq_addr_lo; 2724 __le32 sq_addr_hi; 2725 __le32 rq_pbl_addr_lo; 2726 __le32 rq_pbl_addr_hi; 2727 __le32 rq_first_pbe_addr_lo; 2728 __le32 rq_first_pbe_addr_hi; 2729 __le16 rq_prod; 2730 __le16 reserved0; 2731 }; 2732 2733 /* 2734 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$ 2735 */ 2736 struct fcoe_kwqe_conn_offload2 { 2737 __le16 tx_max_fc_pay_len; 2738 struct fcoe_kwqe_header hdr; 2739 __le32 cq_addr_lo; 2740 __le32 cq_addr_hi; 2741 __le32 xferq_addr_lo; 2742 __le32 xferq_addr_hi; 2743 __le32 conn_db_addr_lo; 2744 __le32 conn_db_addr_hi; 2745 __le32 reserved1; 2746 }; 2747 2748 /* 2749 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$ 2750 */ 2751 struct fcoe_kwqe_conn_offload3 { 2752 __le16 vlan_tag; 2753 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 2754 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 2755 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 2756 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 2757 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 2758 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 2759 struct fcoe_kwqe_header hdr; 2760 u8 s_id[3]; 2761 u8 tx_max_conc_seqs_c3; 2762 u8 d_id[3]; 2763 u8 flags; 2764 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 2765 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 2766 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) 2767 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 2768 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) 2769 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 2770 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) 2771 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 2772 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) 2773 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 2774 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) 2775 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 2776 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) 2777 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 2778 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 2779 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 2780 __le32 reserved; 2781 __le32 confq_first_pbe_addr_lo; 2782 __le32 confq_first_pbe_addr_hi; 2783 __le16 tx_total_conc_seqs; 2784 __le16 rx_max_fc_pay_len; 2785 __le16 rx_total_conc_seqs; 2786 u8 rx_max_conc_seqs_c3; 2787 u8 rx_open_seqs_exch_c3; 2788 }; 2789 2790 /* 2791 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$ 2792 */ 2793 struct fcoe_kwqe_conn_offload4 { 2794 u8 e_d_tov_timer_val; 2795 u8 reserved2; 2796 struct fcoe_kwqe_header hdr; 2797 u8 src_mac_addr_lo[2]; 2798 u8 src_mac_addr_mid[2]; 2799 u8 src_mac_addr_hi[2]; 2800 u8 dst_mac_addr_hi[2]; 2801 u8 dst_mac_addr_lo[2]; 2802 u8 dst_mac_addr_mid[2]; 2803 __le32 lcq_addr_lo; 2804 __le32 lcq_addr_hi; 2805 __le32 confq_pbl_base_addr_lo; 2806 __le32 confq_pbl_base_addr_hi; 2807 }; 2808 2809 /* 2810 * FCoE connection enable request $$KEEP_ENDIANNESS$$ 2811 */ 2812 struct fcoe_kwqe_conn_enable_disable { 2813 __le16 reserved0; 2814 struct fcoe_kwqe_header hdr; 2815 u8 src_mac_addr_lo[2]; 2816 u8 src_mac_addr_mid[2]; 2817 u8 src_mac_addr_hi[2]; 2818 u16 vlan_tag; 2819 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 2820 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 2821 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) 2822 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 2823 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 2824 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 2825 u8 dst_mac_addr_lo[2]; 2826 u8 dst_mac_addr_mid[2]; 2827 u8 dst_mac_addr_hi[2]; 2828 __le16 reserved1; 2829 u8 s_id[3]; 2830 u8 vlan_flag; 2831 u8 d_id[3]; 2832 u8 reserved3; 2833 __le32 context_id; 2834 __le32 conn_id; 2835 __le32 reserved4; 2836 }; 2837 2838 /* 2839 * FCoE connection destroy request $$KEEP_ENDIANNESS$$ 2840 */ 2841 struct fcoe_kwqe_conn_destroy { 2842 __le16 reserved0; 2843 struct fcoe_kwqe_header hdr; 2844 __le32 context_id; 2845 __le32 conn_id; 2846 __le32 reserved1[5]; 2847 }; 2848 2849 /* 2850 * FCoe destroy request $$KEEP_ENDIANNESS$$ 2851 */ 2852 struct fcoe_kwqe_destroy { 2853 __le16 reserved0; 2854 struct fcoe_kwqe_header hdr; 2855 __le32 reserved1[7]; 2856 }; 2857 2858 /* 2859 * FCoe statistics request $$KEEP_ENDIANNESS$$ 2860 */ 2861 struct fcoe_kwqe_stat { 2862 __le16 reserved0; 2863 struct fcoe_kwqe_header hdr; 2864 __le32 stat_params_addr_lo; 2865 __le32 stat_params_addr_hi; 2866 __le32 reserved1[5]; 2867 }; 2868 2869 /* 2870 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$ 2871 */ 2872 union fcoe_kwqe { 2873 struct fcoe_kwqe_init1 init1; 2874 struct fcoe_kwqe_init2 init2; 2875 struct fcoe_kwqe_init3 init3; 2876 struct fcoe_kwqe_conn_offload1 conn_offload1; 2877 struct fcoe_kwqe_conn_offload2 conn_offload2; 2878 struct fcoe_kwqe_conn_offload3 conn_offload3; 2879 struct fcoe_kwqe_conn_offload4 conn_offload4; 2880 struct fcoe_kwqe_conn_enable_disable conn_enable_disable; 2881 struct fcoe_kwqe_conn_destroy conn_destroy; 2882 struct fcoe_kwqe_destroy destroy; 2883 struct fcoe_kwqe_stat statistics; 2884 }; 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 /* 2902 * TX SGL context $$KEEP_ENDIANNESS$$ 2903 */ 2904 union fcoe_sgl_union_ctx { 2905 struct fcoe_cached_sge_ctx cached_sge; 2906 struct fcoe_ext_mul_sges_ctx sgl; 2907 __le32 opaque[5]; 2908 }; 2909 2910 /* 2911 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$ 2912 */ 2913 struct fcoe_read_flow_info { 2914 union fcoe_sgl_union_ctx sgl_ctx; 2915 __le32 rsrv0[3]; 2916 }; 2917 2918 2919 /* 2920 * Fcoe stat context $$KEEP_ENDIANNESS$$ 2921 */ 2922 struct fcoe_s_stat_ctx { 2923 u8 flags; 2924 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) 2925 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 2926 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) 2927 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 2928 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) 2929 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 2930 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) 2931 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 2932 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) 2933 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4 2934 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) 2935 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 2936 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) 2937 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 2938 }; 2939 2940 /* 2941 * Fcoe rx seq context $$KEEP_ENDIANNESS$$ 2942 */ 2943 struct fcoe_rx_seq_ctx { 2944 u8 seq_id; 2945 struct fcoe_s_stat_ctx s_stat; 2946 __le16 seq_cnt; 2947 __le32 low_exp_ro; 2948 __le32 high_exp_ro; 2949 }; 2950 2951 2952 /* 2953 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$ 2954 */ 2955 union fcoe_rx_wr_union_ctx { 2956 struct fcoe_read_flow_info read_info; 2957 union fcoe_comp_flow_info comp_info; 2958 __le32 opaque[8]; 2959 }; 2960 2961 2962 2963 /* 2964 * FCoE SQ element $$KEEP_ENDIANNESS$$ 2965 */ 2966 struct fcoe_sqe { 2967 __le16 wqe; 2968 #define FCOE_SQE_TASK_ID (0x7FFF<<0) 2969 #define FCOE_SQE_TASK_ID_SHIFT 0 2970 #define FCOE_SQE_TOGGLE_BIT (0x1<<15) 2971 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15 2972 }; 2973 2974 2975 2976 /* 2977 * 14 regs $$KEEP_ENDIANNESS$$ 2978 */ 2979 struct fcoe_tce_tx_only { 2980 union fcoe_sgl_union_ctx sgl_ctx; 2981 __le32 rsrv0; 2982 }; 2983 2984 /* 2985 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$ 2986 */ 2987 union fcoe_tx_wr_rx_rd_union_ctx { 2988 struct fcoe_fc_frame tx_frame; 2989 struct fcoe_fcp_cmd_payload fcp_cmd; 2990 struct fcoe_ext_cleanup_info cleanup; 2991 struct fcoe_ext_abts_info abts; 2992 struct fcoe_ext_fw_tx_seq_ctx tx_seq; 2993 __le32 opaque[8]; 2994 }; 2995 2996 /* 2997 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$ 2998 */ 2999 struct fcoe_tce_tx_wr_rx_rd_const { 3000 u8 init_flags; 3001 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) 3002 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0 3003 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) 3004 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3 3005 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) 3006 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4 3007 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) 3008 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5 3009 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) 3010 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7 3011 u8 tx_flags; 3012 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) 3013 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0 3014 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) 3015 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1 3016 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) 3017 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5 3018 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) 3019 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6 3020 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7) 3021 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7 3022 __le16 rsrv3; 3023 __le32 verify_tx_seq; 3024 }; 3025 3026 /* 3027 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$ 3028 */ 3029 struct fcoe_tce_tx_wr_rx_rd { 3030 union fcoe_tx_wr_rx_rd_union_ctx union_ctx; 3031 struct fcoe_tce_tx_wr_rx_rd_const const_ctx; 3032 }; 3033 3034 /* 3035 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$ 3036 */ 3037 struct fcoe_tce_rx_wr_tx_rd_const { 3038 __le32 data_2_trns; 3039 __le32 init_flags; 3040 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) 3041 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0 3042 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) 3043 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24 3044 }; 3045 3046 /* 3047 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$ 3048 */ 3049 struct fcoe_tce_rx_wr_tx_rd_var { 3050 __le16 rx_flags; 3051 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) 3052 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0 3053 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) 3054 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4 3055 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) 3056 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7 3057 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) 3058 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8 3059 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) 3060 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12 3061 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) 3062 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13 3063 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) 3064 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14 3065 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) 3066 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15 3067 __le16 rx_id; 3068 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy; 3069 }; 3070 3071 /* 3072 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$ 3073 */ 3074 struct fcoe_tce_rx_wr_tx_rd { 3075 struct fcoe_tce_rx_wr_tx_rd_const const_ctx; 3076 struct fcoe_tce_rx_wr_tx_rd_var var_ctx; 3077 }; 3078 3079 /* 3080 * tce_rx_only $$KEEP_ENDIANNESS$$ 3081 */ 3082 struct fcoe_tce_rx_only { 3083 struct fcoe_rx_seq_ctx rx_seq_ctx; 3084 union fcoe_rx_wr_union_ctx union_ctx; 3085 }; 3086 3087 /* 3088 * task_ctx_entry $$KEEP_ENDIANNESS$$ 3089 */ 3090 struct fcoe_task_ctx_entry { 3091 struct fcoe_tce_tx_only txwr_only; 3092 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd; 3093 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd; 3094 struct fcoe_tce_rx_only rxwr_only; 3095 }; 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 /* 3107 * FCoE XFRQ element $$KEEP_ENDIANNESS$$ 3108 */ 3109 struct fcoe_xfrqe { 3110 __le16 wqe; 3111 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) 3112 #define FCOE_XFRQE_TASK_ID_SHIFT 0 3113 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) 3114 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 3115 }; 3116 3117 3118 /* 3119 * Cached SGEs $$KEEP_ENDIANNESS$$ 3120 */ 3121 struct common_fcoe_sgl { 3122 struct fcoe_bd_ctx sge[3]; 3123 }; 3124 3125 3126 /* 3127 * FCoE SQ\XFRQ element 3128 */ 3129 struct fcoe_cached_wqe { 3130 struct fcoe_sqe sqe; 3131 struct fcoe_xfrqe xfrqe; 3132 }; 3133 3134 3135 /* 3136 * FCoE connection enable\disable params passed by driver to FW in FCoE enable 3137 * ramrod $$KEEP_ENDIANNESS$$ 3138 */ 3139 struct fcoe_conn_enable_disable_ramrod_params { 3140 struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe; 3141 }; 3142 3143 3144 /* 3145 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod 3146 * $$KEEP_ENDIANNESS$$ 3147 */ 3148 struct fcoe_conn_offload_ramrod_params { 3149 struct fcoe_kwqe_conn_offload1 offload_kwqe1; 3150 struct fcoe_kwqe_conn_offload2 offload_kwqe2; 3151 struct fcoe_kwqe_conn_offload3 offload_kwqe3; 3152 struct fcoe_kwqe_conn_offload4 offload_kwqe4; 3153 }; 3154 3155 3156 struct ustorm_fcoe_mng_ctx { 3157 #if defined(__BIG_ENDIAN) 3158 u8 mid_seq_proc_flag; 3159 u8 tce_in_cam_flag; 3160 u8 tce_on_ior_flag; 3161 u8 en_cached_tce_flag; 3162 #elif defined(__LITTLE_ENDIAN) 3163 u8 en_cached_tce_flag; 3164 u8 tce_on_ior_flag; 3165 u8 tce_in_cam_flag; 3166 u8 mid_seq_proc_flag; 3167 #endif 3168 #if defined(__BIG_ENDIAN) 3169 u8 tce_cam_addr; 3170 u8 cached_conn_flag; 3171 u16 rsrv0; 3172 #elif defined(__LITTLE_ENDIAN) 3173 u16 rsrv0; 3174 u8 cached_conn_flag; 3175 u8 tce_cam_addr; 3176 #endif 3177 #if defined(__BIG_ENDIAN) 3178 u16 dma_tce_ram_addr; 3179 u16 tce_ram_addr; 3180 #elif defined(__LITTLE_ENDIAN) 3181 u16 tce_ram_addr; 3182 u16 dma_tce_ram_addr; 3183 #endif 3184 #if defined(__BIG_ENDIAN) 3185 u16 ox_id; 3186 u16 wr_done_seq; 3187 #elif defined(__LITTLE_ENDIAN) 3188 u16 wr_done_seq; 3189 u16 ox_id; 3190 #endif 3191 struct regpair task_addr; 3192 }; 3193 3194 /* 3195 * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and 3196 * used in FCoE context section 3197 */ 3198 struct ustorm_fcoe_params { 3199 #if defined(__BIG_ENDIAN) 3200 u16 fcoe_conn_id; 3201 u16 flags; 3202 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) 3203 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 3204 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) 3205 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 3206 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) 3207 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 3208 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) 3209 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 3210 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) 3211 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 3212 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) 3213 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 3214 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) 3215 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 3216 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7) 3217 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7 3218 #elif defined(__LITTLE_ENDIAN) 3219 u16 flags; 3220 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) 3221 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0 3222 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) 3223 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1 3224 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) 3225 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2 3226 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) 3227 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3 3228 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) 3229 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4 3230 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) 3231 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5 3232 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) 3233 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6 3234 #define USTORM_FCOE_PARAMS_RSRV0 (0x1FF<<7) 3235 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 7 3236 u16 fcoe_conn_id; 3237 #endif 3238 #if defined(__BIG_ENDIAN) 3239 u8 hc_csdm_byte_en; 3240 u8 func_id; 3241 u8 port_id; 3242 u8 vnic_id; 3243 #elif defined(__LITTLE_ENDIAN) 3244 u8 vnic_id; 3245 u8 port_id; 3246 u8 func_id; 3247 u8 hc_csdm_byte_en; 3248 #endif 3249 #if defined(__BIG_ENDIAN) 3250 u16 rx_total_conc_seqs; 3251 u16 rx_max_fc_pay_len; 3252 #elif defined(__LITTLE_ENDIAN) 3253 u16 rx_max_fc_pay_len; 3254 u16 rx_total_conc_seqs; 3255 #endif 3256 #if defined(__BIG_ENDIAN) 3257 u8 task_pbe_idx_off; 3258 u8 task_in_page_log_size; 3259 u16 rx_max_conc_seqs; 3260 #elif defined(__LITTLE_ENDIAN) 3261 u16 rx_max_conc_seqs; 3262 u8 task_in_page_log_size; 3263 u8 task_pbe_idx_off; 3264 #endif 3265 }; 3266 3267 /* 3268 * FCoE 16-bits index structure 3269 */ 3270 struct fcoe_idx16_fields { 3271 u16 fields; 3272 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) 3273 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0 3274 #define FCOE_IDX16_FIELDS_MSB (0x1<<15) 3275 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15 3276 }; 3277 3278 /* 3279 * FCoE 16-bits index union 3280 */ 3281 union fcoe_idx16_field_union { 3282 struct fcoe_idx16_fields fields; 3283 u16 val; 3284 }; 3285 3286 /* 3287 * Parameters required for placement according to SGL 3288 */ 3289 struct ustorm_fcoe_data_place_mng { 3290 #if defined(__BIG_ENDIAN) 3291 u16 sge_off; 3292 u8 num_sges; 3293 u8 sge_idx; 3294 #elif defined(__LITTLE_ENDIAN) 3295 u8 sge_idx; 3296 u8 num_sges; 3297 u16 sge_off; 3298 #endif 3299 }; 3300 3301 /* 3302 * Parameters required for placement according to SGL 3303 */ 3304 struct ustorm_fcoe_data_place { 3305 struct ustorm_fcoe_data_place_mng cached_mng; 3306 struct fcoe_bd_ctx cached_sge[2]; 3307 }; 3308 3309 /* 3310 * TX processing shall write and RX processing shall read from this section 3311 */ 3312 union fcoe_u_tce_tx_wr_rx_rd_union { 3313 struct fcoe_abts_info abts; 3314 struct fcoe_cleanup_info cleanup; 3315 struct fcoe_fw_tx_seq_ctx tx_seq_ctx; 3316 u32 opaque[2]; 3317 }; 3318 3319 /* 3320 * TX processing shall write and RX processing shall read from this section 3321 */ 3322 struct fcoe_u_tce_tx_wr_rx_rd { 3323 union fcoe_u_tce_tx_wr_rx_rd_union union_ctx; 3324 struct fcoe_tce_tx_wr_rx_rd_const const_ctx; 3325 }; 3326 3327 struct ustorm_fcoe_tce { 3328 struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd; 3329 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd; 3330 struct fcoe_tce_rx_only rxwr; 3331 }; 3332 3333 struct ustorm_fcoe_cache_ctx { 3334 u32 rsrv0; 3335 struct ustorm_fcoe_data_place data_place; 3336 struct ustorm_fcoe_tce tce; 3337 }; 3338 3339 /* 3340 * Ustorm FCoE Storm Context 3341 */ 3342 struct ustorm_fcoe_st_context { 3343 struct ustorm_fcoe_mng_ctx mng_ctx; 3344 struct ustorm_fcoe_params fcoe_params; 3345 struct regpair cq_base_addr; 3346 struct regpair rq_pbl_base; 3347 struct regpair rq_cur_page_addr; 3348 struct regpair confq_pbl_base_addr; 3349 struct regpair conn_db_base; 3350 struct regpair xfrq_base_addr; 3351 struct regpair lcq_base_addr; 3352 #if defined(__BIG_ENDIAN) 3353 union fcoe_idx16_field_union rq_cons; 3354 union fcoe_idx16_field_union rq_prod; 3355 #elif defined(__LITTLE_ENDIAN) 3356 union fcoe_idx16_field_union rq_prod; 3357 union fcoe_idx16_field_union rq_cons; 3358 #endif 3359 #if defined(__BIG_ENDIAN) 3360 u16 xfrq_prod; 3361 u16 cq_cons; 3362 #elif defined(__LITTLE_ENDIAN) 3363 u16 cq_cons; 3364 u16 xfrq_prod; 3365 #endif 3366 #if defined(__BIG_ENDIAN) 3367 u16 lcq_cons; 3368 u16 hc_cram_address; 3369 #elif defined(__LITTLE_ENDIAN) 3370 u16 hc_cram_address; 3371 u16 lcq_cons; 3372 #endif 3373 #if defined(__BIG_ENDIAN) 3374 u16 sq_xfrq_lcq_confq_size; 3375 u16 confq_prod; 3376 #elif defined(__LITTLE_ENDIAN) 3377 u16 confq_prod; 3378 u16 sq_xfrq_lcq_confq_size; 3379 #endif 3380 #if defined(__BIG_ENDIAN) 3381 u8 hc_csdm_agg_int; 3382 u8 rsrv2; 3383 u8 available_rqes; 3384 u8 sp_q_flush_cnt; 3385 #elif defined(__LITTLE_ENDIAN) 3386 u8 sp_q_flush_cnt; 3387 u8 available_rqes; 3388 u8 rsrv2; 3389 u8 hc_csdm_agg_int; 3390 #endif 3391 #if defined(__BIG_ENDIAN) 3392 u16 num_pend_tasks; 3393 u16 pbf_ack_ram_addr; 3394 #elif defined(__LITTLE_ENDIAN) 3395 u16 pbf_ack_ram_addr; 3396 u16 num_pend_tasks; 3397 #endif 3398 struct ustorm_fcoe_cache_ctx cache_ctx; 3399 }; 3400 3401 /* 3402 * The FCoE non-aggregative context of Tstorm 3403 */ 3404 struct tstorm_fcoe_st_context { 3405 struct regpair reserved0; 3406 struct regpair reserved1; 3407 }; 3408 3409 /* 3410 * Ethernet context section 3411 */ 3412 struct xstorm_fcoe_eth_context_section { 3413 #if defined(__BIG_ENDIAN) 3414 u8 remote_addr_4; 3415 u8 remote_addr_5; 3416 u8 local_addr_0; 3417 u8 local_addr_1; 3418 #elif defined(__LITTLE_ENDIAN) 3419 u8 local_addr_1; 3420 u8 local_addr_0; 3421 u8 remote_addr_5; 3422 u8 remote_addr_4; 3423 #endif 3424 #if defined(__BIG_ENDIAN) 3425 u8 remote_addr_0; 3426 u8 remote_addr_1; 3427 u8 remote_addr_2; 3428 u8 remote_addr_3; 3429 #elif defined(__LITTLE_ENDIAN) 3430 u8 remote_addr_3; 3431 u8 remote_addr_2; 3432 u8 remote_addr_1; 3433 u8 remote_addr_0; 3434 #endif 3435 #if defined(__BIG_ENDIAN) 3436 u16 reserved_vlan_type; 3437 u16 params; 3438 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 3439 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 3440 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) 3441 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 3442 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 3443 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 3444 #elif defined(__LITTLE_ENDIAN) 3445 u16 params; 3446 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 3447 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 3448 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) 3449 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12 3450 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 3451 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 3452 u16 reserved_vlan_type; 3453 #endif 3454 #if defined(__BIG_ENDIAN) 3455 u8 local_addr_2; 3456 u8 local_addr_3; 3457 u8 local_addr_4; 3458 u8 local_addr_5; 3459 #elif defined(__LITTLE_ENDIAN) 3460 u8 local_addr_5; 3461 u8 local_addr_4; 3462 u8 local_addr_3; 3463 u8 local_addr_2; 3464 #endif 3465 }; 3466 3467 /* 3468 * Flags used in FCoE context section - 1 byte 3469 */ 3470 struct xstorm_fcoe_context_flags { 3471 u8 flags; 3472 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) 3473 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0 3474 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) 3475 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2 3476 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3) 3477 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3 3478 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) 3479 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4 3480 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) 3481 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5 3482 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) 3483 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6 3484 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7) 3485 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7 3486 }; 3487 3488 struct xstorm_fcoe_tce { 3489 struct fcoe_tce_tx_only txwr; 3490 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd; 3491 }; 3492 3493 /* 3494 * FCP_DATA parameters required for transmission 3495 */ 3496 struct xstorm_fcoe_fcp_data { 3497 u32 io_rem; 3498 #if defined(__BIG_ENDIAN) 3499 u16 cached_sge_off; 3500 u8 cached_num_sges; 3501 u8 cached_sge_idx; 3502 #elif defined(__LITTLE_ENDIAN) 3503 u8 cached_sge_idx; 3504 u8 cached_num_sges; 3505 u16 cached_sge_off; 3506 #endif 3507 u32 buf_addr_hi_0; 3508 u32 buf_addr_lo_0; 3509 #if defined(__BIG_ENDIAN) 3510 u16 num_of_pending_tasks; 3511 u16 buf_len_0; 3512 #elif defined(__LITTLE_ENDIAN) 3513 u16 buf_len_0; 3514 u16 num_of_pending_tasks; 3515 #endif 3516 u32 buf_addr_hi_1; 3517 u32 buf_addr_lo_1; 3518 #if defined(__BIG_ENDIAN) 3519 u16 task_pbe_idx_off; 3520 u16 buf_len_1; 3521 #elif defined(__LITTLE_ENDIAN) 3522 u16 buf_len_1; 3523 u16 task_pbe_idx_off; 3524 #endif 3525 u32 buf_addr_hi_2; 3526 u32 buf_addr_lo_2; 3527 #if defined(__BIG_ENDIAN) 3528 u16 ox_id; 3529 u16 buf_len_2; 3530 #elif defined(__LITTLE_ENDIAN) 3531 u16 buf_len_2; 3532 u16 ox_id; 3533 #endif 3534 }; 3535 3536 /* 3537 * vlan configuration 3538 */ 3539 struct xstorm_fcoe_vlan_conf { 3540 u8 vlan_conf; 3541 #define XSTORM_FCOE_VLAN_CONF_PRIORITY (0x7<<0) 3542 #define XSTORM_FCOE_VLAN_CONF_PRIORITY_SHIFT 0 3543 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3) 3544 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3 3545 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0xF<<4) 3546 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 4 3547 }; 3548 3549 /* 3550 * FCoE 16-bits vlan structure 3551 */ 3552 struct fcoe_vlan_fields { 3553 u16 fields; 3554 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0) 3555 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 3556 #define FCOE_VLAN_FIELDS_CLI (0x1<<12) 3557 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 3558 #define FCOE_VLAN_FIELDS_PRI (0x7<<13) 3559 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 3560 }; 3561 3562 /* 3563 * FCoE 16-bits vlan union 3564 */ 3565 union fcoe_vlan_field_union { 3566 struct fcoe_vlan_fields fields; 3567 u16 val; 3568 }; 3569 3570 /* 3571 * FCoE 16-bits vlan, vif union 3572 */ 3573 union fcoe_vlan_vif_field_union { 3574 union fcoe_vlan_field_union vlan; 3575 u16 vif; 3576 }; 3577 3578 /* 3579 * FCoE context section 3580 */ 3581 struct xstorm_fcoe_context_section { 3582 #if defined(__BIG_ENDIAN) 3583 u8 cs_ctl; 3584 u8 s_id[3]; 3585 #elif defined(__LITTLE_ENDIAN) 3586 u8 s_id[3]; 3587 u8 cs_ctl; 3588 #endif 3589 #if defined(__BIG_ENDIAN) 3590 u8 rctl; 3591 u8 d_id[3]; 3592 #elif defined(__LITTLE_ENDIAN) 3593 u8 d_id[3]; 3594 u8 rctl; 3595 #endif 3596 #if defined(__BIG_ENDIAN) 3597 u16 sq_xfrq_lcq_confq_size; 3598 u16 tx_max_fc_pay_len; 3599 #elif defined(__LITTLE_ENDIAN) 3600 u16 tx_max_fc_pay_len; 3601 u16 sq_xfrq_lcq_confq_size; 3602 #endif 3603 u32 lcq_prod; 3604 #if defined(__BIG_ENDIAN) 3605 u8 port_id; 3606 u8 func_id; 3607 u8 seq_id; 3608 struct xstorm_fcoe_context_flags tx_flags; 3609 #elif defined(__LITTLE_ENDIAN) 3610 struct xstorm_fcoe_context_flags tx_flags; 3611 u8 seq_id; 3612 u8 func_id; 3613 u8 port_id; 3614 #endif 3615 #if defined(__BIG_ENDIAN) 3616 u16 mtu; 3617 u8 func_mode; 3618 u8 vnic_id; 3619 #elif defined(__LITTLE_ENDIAN) 3620 u8 vnic_id; 3621 u8 func_mode; 3622 u16 mtu; 3623 #endif 3624 struct regpair confq_curr_page_addr; 3625 struct fcoe_cached_wqe cached_wqe[8]; 3626 struct regpair lcq_base_addr; 3627 struct xstorm_fcoe_tce tce; 3628 struct xstorm_fcoe_fcp_data fcp_data; 3629 #if defined(__BIG_ENDIAN) 3630 u8 tx_max_conc_seqs_c3; 3631 u8 vlan_flag; 3632 u8 dcb_val; 3633 u8 data_pb_cmd_size; 3634 #elif defined(__LITTLE_ENDIAN) 3635 u8 data_pb_cmd_size; 3636 u8 dcb_val; 3637 u8 vlan_flag; 3638 u8 tx_max_conc_seqs_c3; 3639 #endif 3640 #if defined(__BIG_ENDIAN) 3641 u16 fcoe_tx_stat_params_ram_addr; 3642 u16 fcoe_tx_fc_seq_ram_addr; 3643 #elif defined(__LITTLE_ENDIAN) 3644 u16 fcoe_tx_fc_seq_ram_addr; 3645 u16 fcoe_tx_stat_params_ram_addr; 3646 #endif 3647 #if defined(__BIG_ENDIAN) 3648 u8 fcp_cmd_line_credit; 3649 u8 eth_hdr_size; 3650 u16 pbf_addr; 3651 #elif defined(__LITTLE_ENDIAN) 3652 u16 pbf_addr; 3653 u8 eth_hdr_size; 3654 u8 fcp_cmd_line_credit; 3655 #endif 3656 #if defined(__BIG_ENDIAN) 3657 union fcoe_vlan_vif_field_union multi_func_val; 3658 u8 page_log_size; 3659 struct xstorm_fcoe_vlan_conf orig_vlan_conf; 3660 #elif defined(__LITTLE_ENDIAN) 3661 struct xstorm_fcoe_vlan_conf orig_vlan_conf; 3662 u8 page_log_size; 3663 union fcoe_vlan_vif_field_union multi_func_val; 3664 #endif 3665 #if defined(__BIG_ENDIAN) 3666 u16 fcp_cmd_frame_size; 3667 u16 pbf_addr_ff; 3668 #elif defined(__LITTLE_ENDIAN) 3669 u16 pbf_addr_ff; 3670 u16 fcp_cmd_frame_size; 3671 #endif 3672 #if defined(__BIG_ENDIAN) 3673 u8 vlan_num; 3674 u8 cos; 3675 u8 cache_xfrq_cons; 3676 u8 cache_sq_cons; 3677 #elif defined(__LITTLE_ENDIAN) 3678 u8 cache_sq_cons; 3679 u8 cache_xfrq_cons; 3680 u8 cos; 3681 u8 vlan_num; 3682 #endif 3683 u32 verify_tx_seq; 3684 }; 3685 3686 /* 3687 * Xstorm FCoE Storm Context 3688 */ 3689 struct xstorm_fcoe_st_context { 3690 struct xstorm_fcoe_eth_context_section eth; 3691 struct xstorm_fcoe_context_section fcoe; 3692 }; 3693 3694 /* 3695 * Fcoe connection context 3696 */ 3697 struct fcoe_context { 3698 struct ustorm_fcoe_st_context ustorm_st_context; 3699 struct tstorm_fcoe_st_context tstorm_st_context; 3700 struct xstorm_fcoe_ag_context xstorm_ag_context; 3701 struct tstorm_fcoe_ag_context tstorm_ag_context; 3702 struct ustorm_fcoe_ag_context ustorm_ag_context; 3703 struct timers_block_context timers_context; 3704 struct xstorm_fcoe_st_context xstorm_st_context; 3705 }; 3706 3707 /* 3708 * FCoE init params passed by driver to FW in FCoE init ramrod 3709 * $$KEEP_ENDIANNESS$$ 3710 */ 3711 struct fcoe_init_ramrod_params { 3712 struct fcoe_kwqe_init1 init_kwqe1; 3713 struct fcoe_kwqe_init2 init_kwqe2; 3714 struct fcoe_kwqe_init3 init_kwqe3; 3715 struct regpair eq_pbl_base; 3716 __le32 eq_pbl_size; 3717 __le32 reserved2; 3718 __le16 eq_prod; 3719 __le16 sb_num; 3720 u8 sb_id; 3721 u8 reserved0; 3722 __le16 reserved1; 3723 }; 3724 3725 /* 3726 * FCoE statistics params buffer passed by driver to FW in FCoE statistics 3727 * ramrod $$KEEP_ENDIANNESS$$ 3728 */ 3729 struct fcoe_stat_ramrod_params { 3730 struct fcoe_kwqe_stat stat_kwqe; 3731 }; 3732 3733 /* 3734 * CQ DB CQ producer and pending completion counter 3735 */ 3736 struct iscsi_cq_db_prod_pnd_cmpltn_cnt { 3737 #if defined(__BIG_ENDIAN) 3738 u16 cntr; 3739 u16 prod; 3740 #elif defined(__LITTLE_ENDIAN) 3741 u16 prod; 3742 u16 cntr; 3743 #endif 3744 }; 3745 3746 /* 3747 * CQ DB pending completion ITT array 3748 */ 3749 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr { 3750 struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8]; 3751 }; 3752 3753 /* 3754 * Cstorm CQ sequence to notify array, updated by driver 3755 */ 3756 struct iscsi_cq_db_sqn_2_notify_arr { 3757 u16 sqn[8]; 3758 }; 3759 3760 /* 3761 * Cstorm iSCSI Storm Context 3762 */ 3763 struct cstorm_iscsi_st_context { 3764 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr; 3765 struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr; 3766 struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr; 3767 struct regpair hq_pbl_base; 3768 struct regpair hq_curr_pbe; 3769 struct regpair task_pbl_base; 3770 struct regpair cq_db_base; 3771 #if defined(__BIG_ENDIAN) 3772 u16 hq_bd_itt; 3773 u16 iscsi_conn_id; 3774 #elif defined(__LITTLE_ENDIAN) 3775 u16 iscsi_conn_id; 3776 u16 hq_bd_itt; 3777 #endif 3778 u32 hq_bd_data_segment_len; 3779 u32 hq_bd_buffer_offset; 3780 #if defined(__BIG_ENDIAN) 3781 u8 rsrv; 3782 u8 cq_proc_en_bit_map; 3783 u8 cq_pend_comp_itt_valid_bit_map; 3784 u8 hq_bd_opcode; 3785 #elif defined(__LITTLE_ENDIAN) 3786 u8 hq_bd_opcode; 3787 u8 cq_pend_comp_itt_valid_bit_map; 3788 u8 cq_proc_en_bit_map; 3789 u8 rsrv; 3790 #endif 3791 u32 hq_tcp_seq; 3792 #if defined(__BIG_ENDIAN) 3793 u16 flags; 3794 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) 3795 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 3796 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) 3797 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 3798 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) 3799 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 3800 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) 3801 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 3802 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) 3803 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 3804 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) 3805 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 3806 u16 hq_cons; 3807 #elif defined(__LITTLE_ENDIAN) 3808 u16 hq_cons; 3809 u16 flags; 3810 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) 3811 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0 3812 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) 3813 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1 3814 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) 3815 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2 3816 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) 3817 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3 3818 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) 3819 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4 3820 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) 3821 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5 3822 #endif 3823 struct regpair rsrv1; 3824 }; 3825 3826 3827 /* 3828 * SCSI read/write SQ WQE 3829 */ 3830 struct iscsi_cmd_pdu_hdr_little_endian { 3831 #if defined(__BIG_ENDIAN) 3832 u8 opcode; 3833 u8 op_attr; 3834 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) 3835 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 3836 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) 3837 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 3838 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) 3839 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 3840 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) 3841 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 3842 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 3843 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 3844 u16 rsrv0; 3845 #elif defined(__LITTLE_ENDIAN) 3846 u16 rsrv0; 3847 u8 op_attr; 3848 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) 3849 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0 3850 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) 3851 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3 3852 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) 3853 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5 3854 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) 3855 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6 3856 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 3857 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 3858 u8 opcode; 3859 #endif 3860 u32 data_fields; 3861 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 3862 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 3863 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 3864 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 3865 struct regpair lun; 3866 u32 itt; 3867 u32 expected_data_transfer_length; 3868 u32 cmd_sn; 3869 u32 exp_stat_sn; 3870 u32 scsi_command_block[4]; 3871 }; 3872 3873 3874 /* 3875 * Buffer per connection, used in Tstorm 3876 */ 3877 struct iscsi_conn_buf { 3878 struct regpair reserved[8]; 3879 }; 3880 3881 3882 /* 3883 * iSCSI context region, used only in iSCSI 3884 */ 3885 struct ustorm_iscsi_rq_db { 3886 struct regpair pbl_base; 3887 struct regpair curr_pbe; 3888 }; 3889 3890 /* 3891 * iSCSI context region, used only in iSCSI 3892 */ 3893 struct ustorm_iscsi_r2tq_db { 3894 struct regpair pbl_base; 3895 struct regpair curr_pbe; 3896 }; 3897 3898 /* 3899 * iSCSI context region, used only in iSCSI 3900 */ 3901 struct ustorm_iscsi_cq_db { 3902 #if defined(__BIG_ENDIAN) 3903 u16 cq_sn; 3904 u16 prod; 3905 #elif defined(__LITTLE_ENDIAN) 3906 u16 prod; 3907 u16 cq_sn; 3908 #endif 3909 struct regpair curr_pbe; 3910 }; 3911 3912 /* 3913 * iSCSI context region, used only in iSCSI 3914 */ 3915 struct rings_db { 3916 struct ustorm_iscsi_rq_db rq; 3917 struct ustorm_iscsi_r2tq_db r2tq; 3918 struct ustorm_iscsi_cq_db cq[8]; 3919 #if defined(__BIG_ENDIAN) 3920 u16 rq_prod; 3921 u16 r2tq_prod; 3922 #elif defined(__LITTLE_ENDIAN) 3923 u16 r2tq_prod; 3924 u16 rq_prod; 3925 #endif 3926 struct regpair cq_pbl_base; 3927 }; 3928 3929 /* 3930 * iSCSI context region, used only in iSCSI 3931 */ 3932 struct ustorm_iscsi_placement_db { 3933 u32 sgl_base_lo; 3934 u32 sgl_base_hi; 3935 u32 local_sge_0_address_hi; 3936 u32 local_sge_0_address_lo; 3937 #if defined(__BIG_ENDIAN) 3938 u16 curr_sge_offset; 3939 u16 local_sge_0_size; 3940 #elif defined(__LITTLE_ENDIAN) 3941 u16 local_sge_0_size; 3942 u16 curr_sge_offset; 3943 #endif 3944 u32 local_sge_1_address_hi; 3945 u32 local_sge_1_address_lo; 3946 #if defined(__BIG_ENDIAN) 3947 u8 exp_padding_2b; 3948 u8 nal_len_3b; 3949 u16 local_sge_1_size; 3950 #elif defined(__LITTLE_ENDIAN) 3951 u16 local_sge_1_size; 3952 u8 nal_len_3b; 3953 u8 exp_padding_2b; 3954 #endif 3955 #if defined(__BIG_ENDIAN) 3956 u8 sgl_size; 3957 u8 local_sge_index_2b; 3958 u16 reserved7; 3959 #elif defined(__LITTLE_ENDIAN) 3960 u16 reserved7; 3961 u8 local_sge_index_2b; 3962 u8 sgl_size; 3963 #endif 3964 u32 rem_pdu; 3965 u32 place_db_bitfield_1; 3966 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) 3967 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0 3968 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) 3969 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24 3970 u32 place_db_bitfield_2; 3971 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) 3972 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0 3973 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) 3974 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24 3975 u32 nal; 3976 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) 3977 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0 3978 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24) 3979 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24 3980 }; 3981 3982 /* 3983 * Ustorm iSCSI Storm Context 3984 */ 3985 struct ustorm_iscsi_st_context { 3986 u32 exp_stat_sn; 3987 u32 exp_data_sn; 3988 struct rings_db ring; 3989 struct regpair task_pbl_base; 3990 struct regpair tce_phy_addr; 3991 struct ustorm_iscsi_placement_db place_db; 3992 u32 reserved8; 3993 u32 rem_rcv_len; 3994 #if defined(__BIG_ENDIAN) 3995 u16 hdr_itt; 3996 u16 iscsi_conn_id; 3997 #elif defined(__LITTLE_ENDIAN) 3998 u16 iscsi_conn_id; 3999 u16 hdr_itt; 4000 #endif 4001 u32 nal_bytes; 4002 #if defined(__BIG_ENDIAN) 4003 u8 hdr_second_byte_union; 4004 u8 bitfield_0; 4005 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) 4006 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 4007 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) 4008 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 4009 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) 4010 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 4011 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) 4012 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 4013 u8 task_pdu_cache_index; 4014 u8 task_pbe_cache_index; 4015 #elif defined(__LITTLE_ENDIAN) 4016 u8 task_pbe_cache_index; 4017 u8 task_pdu_cache_index; 4018 u8 bitfield_0; 4019 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) 4020 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0 4021 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) 4022 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1 4023 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) 4024 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2 4025 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) 4026 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3 4027 u8 hdr_second_byte_union; 4028 #endif 4029 #if defined(__BIG_ENDIAN) 4030 u16 reserved3; 4031 u8 reserved2; 4032 u8 acDecrement; 4033 #elif defined(__LITTLE_ENDIAN) 4034 u8 acDecrement; 4035 u8 reserved2; 4036 u16 reserved3; 4037 #endif 4038 u32 task_stat; 4039 #if defined(__BIG_ENDIAN) 4040 u8 hdr_opcode; 4041 u8 num_cqs; 4042 u16 reserved5; 4043 #elif defined(__LITTLE_ENDIAN) 4044 u16 reserved5; 4045 u8 num_cqs; 4046 u8 hdr_opcode; 4047 #endif 4048 u32 negotiated_rx; 4049 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) 4050 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0 4051 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) 4052 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24 4053 u32 negotiated_rx_and_flags; 4054 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) 4055 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0 4056 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) 4057 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24 4058 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) 4059 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25 4060 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) 4061 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26 4062 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) 4063 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27 4064 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) 4065 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28 4066 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) 4067 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29 4068 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) 4069 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31 4070 }; 4071 4072 /* 4073 * TCP context region, shared in TOE, RDMA and ISCSI 4074 */ 4075 struct tstorm_tcp_st_context_section { 4076 u32 flags1; 4077 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0) 4078 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0 4079 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) 4080 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24 4081 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) 4082 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25 4083 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) 4084 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26 4085 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) 4086 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27 4087 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) 4088 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28 4089 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) 4090 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29 4091 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) 4092 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30 4093 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) 4094 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31 4095 u32 flags2; 4096 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0) 4097 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0 4098 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) 4099 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24 4100 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) 4101 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25 4102 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) 4103 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26 4104 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) 4105 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27 4106 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) 4107 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28 4108 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) 4109 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29 4110 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) 4111 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30 4112 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) 4113 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31 4114 #if defined(__BIG_ENDIAN) 4115 u16 mss; 4116 u8 tcp_sm_state; 4117 u8 rto_exp; 4118 #elif defined(__LITTLE_ENDIAN) 4119 u8 rto_exp; 4120 u8 tcp_sm_state; 4121 u16 mss; 4122 #endif 4123 u32 rcv_nxt; 4124 u32 timestamp_recent; 4125 u32 timestamp_recent_time; 4126 u32 cwnd; 4127 u32 ss_thresh; 4128 u32 cwnd_accum; 4129 u32 prev_seg_seq; 4130 u32 expected_rel_seq; 4131 u32 recover; 4132 #if defined(__BIG_ENDIAN) 4133 u8 retransmit_count; 4134 u8 ka_max_probe_count; 4135 u8 persist_probe_count; 4136 u8 ka_probe_count; 4137 #elif defined(__LITTLE_ENDIAN) 4138 u8 ka_probe_count; 4139 u8 persist_probe_count; 4140 u8 ka_max_probe_count; 4141 u8 retransmit_count; 4142 #endif 4143 #if defined(__BIG_ENDIAN) 4144 u8 statistics_counter_id; 4145 u8 ooo_support_mode; 4146 u8 snd_wnd_scale; 4147 u8 dup_ack_count; 4148 #elif defined(__LITTLE_ENDIAN) 4149 u8 dup_ack_count; 4150 u8 snd_wnd_scale; 4151 u8 ooo_support_mode; 4152 u8 statistics_counter_id; 4153 #endif 4154 u32 retransmit_start_time; 4155 u32 ka_timeout; 4156 u32 ka_interval; 4157 u32 isle_start_seq; 4158 u32 isle_end_seq; 4159 #if defined(__BIG_ENDIAN) 4160 u16 second_isle_address; 4161 u16 recent_seg_wnd; 4162 #elif defined(__LITTLE_ENDIAN) 4163 u16 recent_seg_wnd; 4164 u16 second_isle_address; 4165 #endif 4166 #if defined(__BIG_ENDIAN) 4167 u8 max_isles_ever_happened; 4168 u8 isles_number; 4169 u16 last_isle_address; 4170 #elif defined(__LITTLE_ENDIAN) 4171 u16 last_isle_address; 4172 u8 isles_number; 4173 u8 max_isles_ever_happened; 4174 #endif 4175 u32 max_rt_time; 4176 #if defined(__BIG_ENDIAN) 4177 u16 lsb_mac_address; 4178 u16 vlan_id; 4179 #elif defined(__LITTLE_ENDIAN) 4180 u16 vlan_id; 4181 u16 lsb_mac_address; 4182 #endif 4183 #if defined(__BIG_ENDIAN) 4184 u16 msb_mac_address; 4185 u16 mid_mac_address; 4186 #elif defined(__LITTLE_ENDIAN) 4187 u16 mid_mac_address; 4188 u16 msb_mac_address; 4189 #endif 4190 u32 rightmost_received_seq; 4191 }; 4192 4193 /* 4194 * Termination variables 4195 */ 4196 struct iscsi_term_vars { 4197 u8 BitMap; 4198 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) 4199 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0 4200 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) 4201 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 4202 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) 4203 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 4204 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) 4205 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6 4206 #define ISCSI_TERM_VARS_RSRV (0x1<<7) 4207 #define ISCSI_TERM_VARS_RSRV_SHIFT 7 4208 }; 4209 4210 /* 4211 * iSCSI context region, used only in iSCSI 4212 */ 4213 struct tstorm_iscsi_st_context_section { 4214 u32 nalPayload; 4215 u32 b2nh; 4216 #if defined(__BIG_ENDIAN) 4217 u16 rq_cons; 4218 u8 flags; 4219 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) 4220 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 4221 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) 4222 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 4223 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) 4224 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 4225 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) 4226 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 4227 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) 4228 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 4229 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) 4230 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5 4231 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) 4232 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7 4233 u8 hdr_bytes_2_fetch; 4234 #elif defined(__LITTLE_ENDIAN) 4235 u8 hdr_bytes_2_fetch; 4236 u8 flags; 4237 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) 4238 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0 4239 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) 4240 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1 4241 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) 4242 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2 4243 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) 4244 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3 4245 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) 4246 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4 4247 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) 4248 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5 4249 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) 4250 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7 4251 u16 rq_cons; 4252 #endif 4253 struct regpair rq_db_phy_addr; 4254 #if defined(__BIG_ENDIAN) 4255 struct iscsi_term_vars term_vars; 4256 u8 rsrv1; 4257 u16 iscsi_conn_id; 4258 #elif defined(__LITTLE_ENDIAN) 4259 u16 iscsi_conn_id; 4260 u8 rsrv1; 4261 struct iscsi_term_vars term_vars; 4262 #endif 4263 u32 process_nxt; 4264 }; 4265 4266 /* 4267 * The iSCSI non-aggregative context of Tstorm 4268 */ 4269 struct tstorm_iscsi_st_context { 4270 struct tstorm_tcp_st_context_section tcp; 4271 struct tstorm_iscsi_st_context_section iscsi; 4272 }; 4273 4274 /* 4275 * Ethernet context section, shared in TOE, RDMA and ISCSI 4276 */ 4277 struct xstorm_eth_context_section { 4278 #if defined(__BIG_ENDIAN) 4279 u8 remote_addr_4; 4280 u8 remote_addr_5; 4281 u8 local_addr_0; 4282 u8 local_addr_1; 4283 #elif defined(__LITTLE_ENDIAN) 4284 u8 local_addr_1; 4285 u8 local_addr_0; 4286 u8 remote_addr_5; 4287 u8 remote_addr_4; 4288 #endif 4289 #if defined(__BIG_ENDIAN) 4290 u8 remote_addr_0; 4291 u8 remote_addr_1; 4292 u8 remote_addr_2; 4293 u8 remote_addr_3; 4294 #elif defined(__LITTLE_ENDIAN) 4295 u8 remote_addr_3; 4296 u8 remote_addr_2; 4297 u8 remote_addr_1; 4298 u8 remote_addr_0; 4299 #endif 4300 #if defined(__BIG_ENDIAN) 4301 u16 reserved_vlan_type; 4302 u16 params; 4303 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 4304 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 4305 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) 4306 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 4307 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 4308 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 4309 #elif defined(__LITTLE_ENDIAN) 4310 u16 params; 4311 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) 4312 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0 4313 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) 4314 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12 4315 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) 4316 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13 4317 u16 reserved_vlan_type; 4318 #endif 4319 #if defined(__BIG_ENDIAN) 4320 u8 local_addr_2; 4321 u8 local_addr_3; 4322 u8 local_addr_4; 4323 u8 local_addr_5; 4324 #elif defined(__LITTLE_ENDIAN) 4325 u8 local_addr_5; 4326 u8 local_addr_4; 4327 u8 local_addr_3; 4328 u8 local_addr_2; 4329 #endif 4330 }; 4331 4332 /* 4333 * IpV4 context section, shared in TOE, RDMA and ISCSI 4334 */ 4335 struct xstorm_ip_v4_context_section { 4336 #if defined(__BIG_ENDIAN) 4337 u16 __pbf_hdr_cmd_rsvd_id; 4338 u16 __pbf_hdr_cmd_rsvd_flags_offset; 4339 #elif defined(__LITTLE_ENDIAN) 4340 u16 __pbf_hdr_cmd_rsvd_flags_offset; 4341 u16 __pbf_hdr_cmd_rsvd_id; 4342 #endif 4343 #if defined(__BIG_ENDIAN) 4344 u8 __pbf_hdr_cmd_rsvd_ver_ihl; 4345 u8 tos; 4346 u16 __pbf_hdr_cmd_rsvd_length; 4347 #elif defined(__LITTLE_ENDIAN) 4348 u16 __pbf_hdr_cmd_rsvd_length; 4349 u8 tos; 4350 u8 __pbf_hdr_cmd_rsvd_ver_ihl; 4351 #endif 4352 u32 ip_local_addr; 4353 #if defined(__BIG_ENDIAN) 4354 u8 ttl; 4355 u8 __pbf_hdr_cmd_rsvd_protocol; 4356 u16 __pbf_hdr_cmd_rsvd_csum; 4357 #elif defined(__LITTLE_ENDIAN) 4358 u16 __pbf_hdr_cmd_rsvd_csum; 4359 u8 __pbf_hdr_cmd_rsvd_protocol; 4360 u8 ttl; 4361 #endif 4362 u32 __pbf_hdr_cmd_rsvd_1; 4363 u32 ip_remote_addr; 4364 }; 4365 4366 /* 4367 * context section, shared in TOE, RDMA and ISCSI 4368 */ 4369 struct xstorm_padded_ip_v4_context_section { 4370 struct xstorm_ip_v4_context_section ip_v4; 4371 u32 reserved1[4]; 4372 }; 4373 4374 /* 4375 * IpV6 context section, shared in TOE, RDMA and ISCSI 4376 */ 4377 struct xstorm_ip_v6_context_section { 4378 #if defined(__BIG_ENDIAN) 4379 u16 pbf_hdr_cmd_rsvd_payload_len; 4380 u8 pbf_hdr_cmd_rsvd_nxt_hdr; 4381 u8 hop_limit; 4382 #elif defined(__LITTLE_ENDIAN) 4383 u8 hop_limit; 4384 u8 pbf_hdr_cmd_rsvd_nxt_hdr; 4385 u16 pbf_hdr_cmd_rsvd_payload_len; 4386 #endif 4387 u32 priority_flow_label; 4388 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) 4389 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0 4390 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) 4391 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20 4392 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) 4393 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28 4394 u32 ip_local_addr_lo_hi; 4395 u32 ip_local_addr_lo_lo; 4396 u32 ip_local_addr_hi_hi; 4397 u32 ip_local_addr_hi_lo; 4398 u32 ip_remote_addr_lo_hi; 4399 u32 ip_remote_addr_lo_lo; 4400 u32 ip_remote_addr_hi_hi; 4401 u32 ip_remote_addr_hi_lo; 4402 }; 4403 4404 union xstorm_ip_context_section_types { 4405 struct xstorm_padded_ip_v4_context_section padded_ip_v4; 4406 struct xstorm_ip_v6_context_section ip_v6; 4407 }; 4408 4409 /* 4410 * TCP context section, shared in TOE, RDMA and ISCSI 4411 */ 4412 struct xstorm_tcp_context_section { 4413 u32 snd_max; 4414 #if defined(__BIG_ENDIAN) 4415 u16 remote_port; 4416 u16 local_port; 4417 #elif defined(__LITTLE_ENDIAN) 4418 u16 local_port; 4419 u16 remote_port; 4420 #endif 4421 #if defined(__BIG_ENDIAN) 4422 u8 original_nagle_1b; 4423 u8 ts_enabled; 4424 u16 tcp_params; 4425 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) 4426 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 4427 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) 4428 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 4429 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) 4430 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 4431 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) 4432 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 4433 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) 4434 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 4435 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) 4436 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 4437 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) 4438 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 4439 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) 4440 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 4441 #elif defined(__LITTLE_ENDIAN) 4442 u16 tcp_params; 4443 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) 4444 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0 4445 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) 4446 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8 4447 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) 4448 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9 4449 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) 4450 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10 4451 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) 4452 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11 4453 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) 4454 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12 4455 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) 4456 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13 4457 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) 4458 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14 4459 u8 ts_enabled; 4460 u8 original_nagle_1b; 4461 #endif 4462 #if defined(__BIG_ENDIAN) 4463 u16 pseudo_csum; 4464 u16 window_scaling_factor; 4465 #elif defined(__LITTLE_ENDIAN) 4466 u16 window_scaling_factor; 4467 u16 pseudo_csum; 4468 #endif 4469 #if defined(__BIG_ENDIAN) 4470 u16 reserved2; 4471 u8 statistics_counter_id; 4472 u8 statistics_params; 4473 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) 4474 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 4475 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) 4476 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 4477 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) 4478 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2 4479 #elif defined(__LITTLE_ENDIAN) 4480 u8 statistics_params; 4481 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) 4482 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0 4483 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) 4484 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1 4485 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) 4486 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2 4487 u8 statistics_counter_id; 4488 u16 reserved2; 4489 #endif 4490 u32 ts_time_diff; 4491 u32 __next_timer_expir; 4492 }; 4493 4494 /* 4495 * Common context section, shared in TOE, RDMA and ISCSI 4496 */ 4497 struct xstorm_common_context_section { 4498 struct xstorm_eth_context_section ethernet; 4499 union xstorm_ip_context_section_types ip_union; 4500 struct xstorm_tcp_context_section tcp; 4501 #if defined(__BIG_ENDIAN) 4502 u8 __dcb_val; 4503 u8 flags; 4504 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) 4505 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0 4506 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) 4507 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1 4508 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) 4509 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4 4510 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) 4511 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5 4512 u8 reserved; 4513 u8 ip_version_1b; 4514 #elif defined(__LITTLE_ENDIAN) 4515 u8 ip_version_1b; 4516 u8 reserved; 4517 u8 flags; 4518 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) 4519 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0 4520 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) 4521 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1 4522 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) 4523 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4 4524 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) 4525 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5 4526 u8 __dcb_val; 4527 #endif 4528 }; 4529 4530 /* 4531 * Flags used in ISCSI context section 4532 */ 4533 struct xstorm_iscsi_context_flags { 4534 u8 flags; 4535 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) 4536 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0 4537 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) 4538 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1 4539 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) 4540 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2 4541 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) 4542 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3 4543 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) 4544 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4 4545 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) 4546 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5 4547 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) 4548 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6 4549 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) 4550 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7 4551 }; 4552 4553 struct iscsi_task_context_entry_x { 4554 u32 data_out_buffer_offset; 4555 u32 itt; 4556 u32 data_sn; 4557 }; 4558 4559 struct iscsi_task_context_entry_xuc_x_write_only { 4560 u32 tx_r2t_sn; 4561 }; 4562 4563 struct iscsi_task_context_entry_xuc_xu_write_both { 4564 u32 sgl_base_lo; 4565 u32 sgl_base_hi; 4566 #if defined(__BIG_ENDIAN) 4567 u8 sgl_size; 4568 u8 sge_index; 4569 u16 sge_offset; 4570 #elif defined(__LITTLE_ENDIAN) 4571 u16 sge_offset; 4572 u8 sge_index; 4573 u8 sgl_size; 4574 #endif 4575 }; 4576 4577 /* 4578 * iSCSI context section 4579 */ 4580 struct xstorm_iscsi_context_section { 4581 u32 first_burst_length; 4582 u32 max_send_pdu_length; 4583 struct regpair sq_pbl_base; 4584 struct regpair sq_curr_pbe; 4585 struct regpair hq_pbl_base; 4586 struct regpair hq_curr_pbe_base; 4587 struct regpair r2tq_pbl_base; 4588 struct regpair r2tq_curr_pbe_base; 4589 struct regpair task_pbl_base; 4590 #if defined(__BIG_ENDIAN) 4591 u16 data_out_count; 4592 struct xstorm_iscsi_context_flags flags; 4593 u8 task_pbl_cache_idx; 4594 #elif defined(__LITTLE_ENDIAN) 4595 u8 task_pbl_cache_idx; 4596 struct xstorm_iscsi_context_flags flags; 4597 u16 data_out_count; 4598 #endif 4599 u32 seq_more_2_send; 4600 u32 pdu_more_2_send; 4601 struct iscsi_task_context_entry_x temp_tce_x; 4602 struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr; 4603 struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr; 4604 struct regpair lun; 4605 u32 exp_data_transfer_len_ttt; 4606 u32 pdu_data_2_rxmit; 4607 u32 rxmit_bytes_2_dr; 4608 #if defined(__BIG_ENDIAN) 4609 u16 rxmit_sge_offset; 4610 u16 hq_rxmit_cons; 4611 #elif defined(__LITTLE_ENDIAN) 4612 u16 hq_rxmit_cons; 4613 u16 rxmit_sge_offset; 4614 #endif 4615 #if defined(__BIG_ENDIAN) 4616 u16 r2tq_cons; 4617 u8 rxmit_flags; 4618 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) 4619 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 4620 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) 4621 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 4622 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) 4623 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 4624 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) 4625 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 4626 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) 4627 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 4628 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) 4629 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 4630 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) 4631 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 4632 u8 rxmit_sge_idx; 4633 #elif defined(__LITTLE_ENDIAN) 4634 u8 rxmit_sge_idx; 4635 u8 rxmit_flags; 4636 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) 4637 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0 4638 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) 4639 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1 4640 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) 4641 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2 4642 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) 4643 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3 4644 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) 4645 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4 4646 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) 4647 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5 4648 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) 4649 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7 4650 u16 r2tq_cons; 4651 #endif 4652 u32 hq_rxmit_tcp_seq; 4653 }; 4654 4655 /* 4656 * Xstorm iSCSI Storm Context 4657 */ 4658 struct xstorm_iscsi_st_context { 4659 struct xstorm_common_context_section common; 4660 struct xstorm_iscsi_context_section iscsi; 4661 }; 4662 4663 /* 4664 * Iscsi connection context 4665 */ 4666 struct iscsi_context { 4667 struct ustorm_iscsi_st_context ustorm_st_context; 4668 struct tstorm_iscsi_st_context tstorm_st_context; 4669 struct xstorm_iscsi_ag_context xstorm_ag_context; 4670 struct tstorm_iscsi_ag_context tstorm_ag_context; 4671 struct cstorm_iscsi_ag_context cstorm_ag_context; 4672 struct ustorm_iscsi_ag_context ustorm_ag_context; 4673 struct timers_block_context timers_context; 4674 struct regpair upb_context; 4675 struct xstorm_iscsi_st_context xstorm_st_context; 4676 struct regpair xpb_context; 4677 struct cstorm_iscsi_st_context cstorm_st_context; 4678 }; 4679 4680 4681 /* 4682 * PDU header of an iSCSI DATA-OUT 4683 */ 4684 struct iscsi_data_pdu_hdr_little_endian { 4685 #if defined(__BIG_ENDIAN) 4686 u8 opcode; 4687 u8 op_attr; 4688 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4689 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4690 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 4691 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 4692 u16 rsrv0; 4693 #elif defined(__LITTLE_ENDIAN) 4694 u16 rsrv0; 4695 u8 op_attr; 4696 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4697 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4698 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) 4699 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7 4700 u8 opcode; 4701 #endif 4702 u32 data_fields; 4703 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4704 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4705 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4706 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4707 struct regpair lun; 4708 u32 itt; 4709 u32 ttt; 4710 u32 rsrv2; 4711 u32 exp_stat_sn; 4712 u32 rsrv3; 4713 u32 data_sn; 4714 u32 buffer_offset; 4715 u32 rsrv4; 4716 }; 4717 4718 4719 /* 4720 * PDU header of an iSCSI login request 4721 */ 4722 struct iscsi_login_req_hdr_little_endian { 4723 #if defined(__BIG_ENDIAN) 4724 u8 opcode; 4725 u8 op_attr; 4726 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) 4727 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 4728 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) 4729 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 4730 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) 4731 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 4732 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4733 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4734 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) 4735 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 4736 u8 version_max; 4737 u8 version_min; 4738 #elif defined(__LITTLE_ENDIAN) 4739 u8 version_min; 4740 u8 version_max; 4741 u8 op_attr; 4742 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) 4743 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0 4744 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) 4745 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2 4746 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) 4747 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4 4748 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4749 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4750 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) 4751 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7 4752 u8 opcode; 4753 #endif 4754 u32 data_fields; 4755 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4756 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4757 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4758 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4759 u32 isid_lo; 4760 #if defined(__BIG_ENDIAN) 4761 u16 isid_hi; 4762 u16 tsih; 4763 #elif defined(__LITTLE_ENDIAN) 4764 u16 tsih; 4765 u16 isid_hi; 4766 #endif 4767 u32 itt; 4768 #if defined(__BIG_ENDIAN) 4769 u16 cid; 4770 u16 rsrv1; 4771 #elif defined(__LITTLE_ENDIAN) 4772 u16 rsrv1; 4773 u16 cid; 4774 #endif 4775 u32 cmd_sn; 4776 u32 exp_stat_sn; 4777 u32 rsrv2[4]; 4778 }; 4779 4780 /* 4781 * PDU header of an iSCSI logout request 4782 */ 4783 struct iscsi_logout_req_hdr_little_endian { 4784 #if defined(__BIG_ENDIAN) 4785 u8 opcode; 4786 u8 op_attr; 4787 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) 4788 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 4789 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4790 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4791 u16 rsrv0; 4792 #elif defined(__LITTLE_ENDIAN) 4793 u16 rsrv0; 4794 u8 op_attr; 4795 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) 4796 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0 4797 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4798 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4799 u8 opcode; 4800 #endif 4801 u32 data_fields; 4802 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4803 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4804 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4805 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4806 u32 rsrv2[2]; 4807 u32 itt; 4808 #if defined(__BIG_ENDIAN) 4809 u16 cid; 4810 u16 rsrv1; 4811 #elif defined(__LITTLE_ENDIAN) 4812 u16 rsrv1; 4813 u16 cid; 4814 #endif 4815 u32 cmd_sn; 4816 u32 exp_stat_sn; 4817 u32 rsrv3[4]; 4818 }; 4819 4820 /* 4821 * PDU header of an iSCSI TMF request 4822 */ 4823 struct iscsi_tmf_req_hdr_little_endian { 4824 #if defined(__BIG_ENDIAN) 4825 u8 opcode; 4826 u8 op_attr; 4827 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) 4828 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 4829 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4830 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4831 u16 rsrv0; 4832 #elif defined(__LITTLE_ENDIAN) 4833 u16 rsrv0; 4834 u8 op_attr; 4835 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) 4836 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0 4837 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) 4838 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7 4839 u8 opcode; 4840 #endif 4841 u32 data_fields; 4842 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4843 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4844 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4845 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4846 struct regpair lun; 4847 u32 itt; 4848 u32 referenced_task_tag; 4849 u32 cmd_sn; 4850 u32 exp_stat_sn; 4851 u32 ref_cmd_sn; 4852 u32 exp_data_sn; 4853 u32 rsrv2[2]; 4854 }; 4855 4856 /* 4857 * PDU header of an iSCSI Text request 4858 */ 4859 struct iscsi_text_req_hdr_little_endian { 4860 #if defined(__BIG_ENDIAN) 4861 u8 opcode; 4862 u8 op_attr; 4863 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) 4864 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4865 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4866 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4867 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) 4868 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 4869 u16 rsrv0; 4870 #elif defined(__LITTLE_ENDIAN) 4871 u16 rsrv0; 4872 u8 op_attr; 4873 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) 4874 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4875 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) 4876 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6 4877 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) 4878 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7 4879 u8 opcode; 4880 #endif 4881 u32 data_fields; 4882 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4883 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4884 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4885 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4886 struct regpair lun; 4887 u32 itt; 4888 u32 ttt; 4889 u32 cmd_sn; 4890 u32 exp_stat_sn; 4891 u32 rsrv3[4]; 4892 }; 4893 4894 /* 4895 * PDU header of an iSCSI Nop-Out 4896 */ 4897 struct iscsi_nop_out_hdr_little_endian { 4898 #if defined(__BIG_ENDIAN) 4899 u8 opcode; 4900 u8 op_attr; 4901 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4902 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4903 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) 4904 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 4905 u16 rsrv0; 4906 #elif defined(__LITTLE_ENDIAN) 4907 u16 rsrv0; 4908 u8 op_attr; 4909 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) 4910 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0 4911 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) 4912 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7 4913 u8 opcode; 4914 #endif 4915 u32 data_fields; 4916 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) 4917 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0 4918 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) 4919 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24 4920 struct regpair lun; 4921 u32 itt; 4922 u32 ttt; 4923 u32 cmd_sn; 4924 u32 exp_stat_sn; 4925 u32 rsrv3[4]; 4926 }; 4927 4928 /* 4929 * iscsi pdu headers in little endian form. 4930 */ 4931 union iscsi_pdu_headers_little_endian { 4932 u32 fullHeaderSize[12]; 4933 struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr; 4934 struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr; 4935 struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr; 4936 struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr; 4937 struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr; 4938 struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr; 4939 struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr; 4940 }; 4941 4942 struct iscsi_hq_bd { 4943 union iscsi_pdu_headers_little_endian pdu_header; 4944 #if defined(__BIG_ENDIAN) 4945 u16 reserved1; 4946 u16 lcl_cmp_flg; 4947 #elif defined(__LITTLE_ENDIAN) 4948 u16 lcl_cmp_flg; 4949 u16 reserved1; 4950 #endif 4951 u32 sgl_base_lo; 4952 u32 sgl_base_hi; 4953 #if defined(__BIG_ENDIAN) 4954 u8 sgl_size; 4955 u8 sge_index; 4956 u16 sge_offset; 4957 #elif defined(__LITTLE_ENDIAN) 4958 u16 sge_offset; 4959 u8 sge_index; 4960 u8 sgl_size; 4961 #endif 4962 }; 4963 4964 4965 /* 4966 * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$ 4967 */ 4968 struct iscsi_l2_ooo_data { 4969 __le32 iscsi_cid; 4970 u8 drop_isle; 4971 u8 drop_size; 4972 u8 ooo_opcode; 4973 u8 ooo_isle; 4974 u8 reserved[8]; 4975 }; 4976 4977 4978 4979 4980 4981 4982 struct iscsi_task_context_entry_xuc_c_write_only { 4983 u32 total_data_acked; 4984 }; 4985 4986 struct iscsi_task_context_r2t_table_entry { 4987 u32 ttt; 4988 u32 desired_data_len; 4989 }; 4990 4991 struct iscsi_task_context_entry_xuc_u_write_only { 4992 u32 exp_r2t_sn; 4993 struct iscsi_task_context_r2t_table_entry r2t_table[4]; 4994 #if defined(__BIG_ENDIAN) 4995 u16 data_in_count; 4996 u8 cq_id; 4997 u8 valid_1b; 4998 #elif defined(__LITTLE_ENDIAN) 4999 u8 valid_1b; 5000 u8 cq_id; 5001 u16 data_in_count; 5002 #endif 5003 }; 5004 5005 struct iscsi_task_context_entry_xuc { 5006 struct iscsi_task_context_entry_xuc_c_write_only write_c; 5007 u32 exp_data_transfer_len; 5008 struct iscsi_task_context_entry_xuc_x_write_only write_x; 5009 u32 lun_lo; 5010 struct iscsi_task_context_entry_xuc_xu_write_both write_xu; 5011 u32 lun_hi; 5012 struct iscsi_task_context_entry_xuc_u_write_only write_u; 5013 }; 5014 5015 struct iscsi_task_context_entry_u { 5016 u32 exp_r2t_buff_offset; 5017 u32 rem_rcv_len; 5018 u32 exp_data_sn; 5019 }; 5020 5021 struct iscsi_task_context_entry { 5022 struct iscsi_task_context_entry_x tce_x; 5023 #if defined(__BIG_ENDIAN) 5024 u16 data_out_count; 5025 u16 rsrv0; 5026 #elif defined(__LITTLE_ENDIAN) 5027 u16 rsrv0; 5028 u16 data_out_count; 5029 #endif 5030 struct iscsi_task_context_entry_xuc tce_xuc; 5031 struct iscsi_task_context_entry_u tce_u; 5032 u32 rsrv1[7]; 5033 }; 5034 5035 5036 5037 5038 5039 5040 5041 5042 struct iscsi_task_context_entry_xuc_x_init_only { 5043 struct regpair lun; 5044 u32 exp_data_transfer_len; 5045 }; 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 /* 5064 * ipv6 structure 5065 */ 5066 struct ip_v6_addr { 5067 u32 ip_addr_lo_lo; 5068 u32 ip_addr_lo_hi; 5069 u32 ip_addr_hi_lo; 5070 u32 ip_addr_hi_hi; 5071 }; 5072 5073 5074 5075 /* 5076 * l5cm- connection identification params 5077 */ 5078 struct l5cm_conn_addr_params { 5079 u32 pmtu; 5080 #if defined(__BIG_ENDIAN) 5081 u8 remote_addr_3; 5082 u8 remote_addr_2; 5083 u8 remote_addr_1; 5084 u8 remote_addr_0; 5085 #elif defined(__LITTLE_ENDIAN) 5086 u8 remote_addr_0; 5087 u8 remote_addr_1; 5088 u8 remote_addr_2; 5089 u8 remote_addr_3; 5090 #endif 5091 #if defined(__BIG_ENDIAN) 5092 u16 params; 5093 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) 5094 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 5095 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) 5096 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 5097 u8 remote_addr_5; 5098 u8 remote_addr_4; 5099 #elif defined(__LITTLE_ENDIAN) 5100 u8 remote_addr_4; 5101 u8 remote_addr_5; 5102 u16 params; 5103 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION (0x1<<0) 5104 #define L5CM_CONN_ADDR_PARAMS_IP_VERSION_SHIFT 0 5105 #define L5CM_CONN_ADDR_PARAMS_RSRV (0x7FFF<<1) 5106 #define L5CM_CONN_ADDR_PARAMS_RSRV_SHIFT 1 5107 #endif 5108 struct ip_v6_addr local_ip_addr; 5109 struct ip_v6_addr remote_ip_addr; 5110 u32 ipv6_flow_label_20b; 5111 u32 reserved1; 5112 #if defined(__BIG_ENDIAN) 5113 u16 remote_tcp_port; 5114 u16 local_tcp_port; 5115 #elif defined(__LITTLE_ENDIAN) 5116 u16 local_tcp_port; 5117 u16 remote_tcp_port; 5118 #endif 5119 }; 5120 5121 /* 5122 * l5cm-xstorm connection buffer 5123 */ 5124 struct l5cm_xstorm_conn_buffer { 5125 #if defined(__BIG_ENDIAN) 5126 u16 rsrv1; 5127 u16 params; 5128 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) 5129 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 5130 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5131 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 5132 #elif defined(__LITTLE_ENDIAN) 5133 u16 params; 5134 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE (0x1<<0) 5135 #define L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE_SHIFT 0 5136 #define L5CM_XSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5137 #define L5CM_XSTORM_CONN_BUFFER_RSRV_SHIFT 1 5138 u16 rsrv1; 5139 #endif 5140 #if defined(__BIG_ENDIAN) 5141 u16 mss; 5142 u16 pseudo_header_checksum; 5143 #elif defined(__LITTLE_ENDIAN) 5144 u16 pseudo_header_checksum; 5145 u16 mss; 5146 #endif 5147 u32 rcv_buf; 5148 u32 rsrv2; 5149 struct regpair context_addr; 5150 }; 5151 5152 /* 5153 * l5cm-tstorm connection buffer 5154 */ 5155 struct l5cm_tstorm_conn_buffer { 5156 u32 rsrv1[2]; 5157 #if defined(__BIG_ENDIAN) 5158 u16 params; 5159 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) 5160 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 5161 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5162 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 5163 u8 ka_max_probe_count; 5164 u8 ka_enable; 5165 #elif defined(__LITTLE_ENDIAN) 5166 u8 ka_enable; 5167 u8 ka_max_probe_count; 5168 u16 params; 5169 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE (0x1<<0) 5170 #define L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE_SHIFT 0 5171 #define L5CM_TSTORM_CONN_BUFFER_RSRV (0x7FFF<<1) 5172 #define L5CM_TSTORM_CONN_BUFFER_RSRV_SHIFT 1 5173 #endif 5174 u32 ka_timeout; 5175 u32 ka_interval; 5176 u32 max_rt_time; 5177 }; 5178 5179 /* 5180 * l5cm connection buffer for active side 5181 */ 5182 struct l5cm_active_conn_buffer { 5183 struct l5cm_conn_addr_params conn_addr_buf; 5184 struct l5cm_xstorm_conn_buffer xstorm_conn_buffer; 5185 struct l5cm_tstorm_conn_buffer tstorm_conn_buffer; 5186 }; 5187 5188 5189 5190 /* 5191 * The l5cm opaque buffer passed in add new connection ramrod passive side 5192 */ 5193 struct l5cm_hash_input_string { 5194 u32 __opaque1; 5195 #if defined(__BIG_ENDIAN) 5196 u16 __opaque3; 5197 u16 __opaque2; 5198 #elif defined(__LITTLE_ENDIAN) 5199 u16 __opaque2; 5200 u16 __opaque3; 5201 #endif 5202 struct ip_v6_addr __opaque4; 5203 struct ip_v6_addr __opaque5; 5204 u32 __opaque6; 5205 u32 __opaque7[5]; 5206 }; 5207 5208 5209 /* 5210 * syn cookie component 5211 */ 5212 struct l5cm_syn_cookie_comp { 5213 u32 __opaque; 5214 }; 5215 5216 /* 5217 * data related to listeners of a TCP port 5218 */ 5219 struct l5cm_port_listener_data { 5220 u8 params; 5221 #define L5CM_PORT_LISTENER_DATA_ENABLE (0x1<<0) 5222 #define L5CM_PORT_LISTENER_DATA_ENABLE_SHIFT 0 5223 #define L5CM_PORT_LISTENER_DATA_IP_INDEX (0xF<<1) 5224 #define L5CM_PORT_LISTENER_DATA_IP_INDEX_SHIFT 1 5225 #define L5CM_PORT_LISTENER_DATA_NET_FILTER (0x1<<5) 5226 #define L5CM_PORT_LISTENER_DATA_NET_FILTER_SHIFT 5 5227 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE (0x1<<6) 5228 #define L5CM_PORT_LISTENER_DATA_DEFFERED_MODE_SHIFT 6 5229 #define L5CM_PORT_LISTENER_DATA_MPA_MODE (0x1<<7) 5230 #define L5CM_PORT_LISTENER_DATA_MPA_MODE_SHIFT 7 5231 }; 5232 5233 /* 5234 * Opaque structure passed from U to X when final ack arrives 5235 */ 5236 struct l5cm_opaque_buf { 5237 u32 __opaque1; 5238 u32 __opaque2; 5239 u32 __opaque3; 5240 u32 __opaque4; 5241 struct l5cm_syn_cookie_comp __opaque5; 5242 #if defined(__BIG_ENDIAN) 5243 u16 rsrv2; 5244 u8 rsrv; 5245 struct l5cm_port_listener_data __opaque6; 5246 #elif defined(__LITTLE_ENDIAN) 5247 struct l5cm_port_listener_data __opaque6; 5248 u8 rsrv; 5249 u16 rsrv2; 5250 #endif 5251 }; 5252 5253 5254 /* 5255 * l5cm slow path element 5256 */ 5257 struct l5cm_packet_size { 5258 u32 size; 5259 u32 rsrv; 5260 }; 5261 5262 5263 /* 5264 * The final-ack union structure in PCS entry after final ack arrived 5265 */ 5266 struct l5cm_pcse_ack { 5267 struct l5cm_xstorm_conn_buffer tx_socket_params; 5268 struct l5cm_opaque_buf opaque_buf; 5269 struct l5cm_tstorm_conn_buffer rx_socket_params; 5270 }; 5271 5272 5273 /* 5274 * The syn union structure in PCS entry after syn arrived 5275 */ 5276 struct l5cm_pcse_syn { 5277 struct l5cm_opaque_buf opaque_buf; 5278 u32 rsrv[12]; 5279 }; 5280 5281 5282 /* 5283 * pcs entry data for passive connections 5284 */ 5285 struct l5cm_pcs_attributes { 5286 #if defined(__BIG_ENDIAN) 5287 u16 pcs_id; 5288 u8 status; 5289 u8 flags; 5290 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0) 5291 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0 5292 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1) 5293 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1 5294 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2) 5295 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2 5296 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3) 5297 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3 5298 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4) 5299 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4 5300 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5) 5301 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5 5302 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6) 5303 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6 5304 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7) 5305 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7 5306 #elif defined(__LITTLE_ENDIAN) 5307 u8 flags; 5308 #define L5CM_PCS_ATTRIBUTES_NET_FILTER (0x1<<0) 5309 #define L5CM_PCS_ATTRIBUTES_NET_FILTER_SHIFT 0 5310 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH (0x1<<1) 5311 #define L5CM_PCS_ATTRIBUTES_CALCULATE_HASH_SHIFT 1 5312 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT (0x1<<2) 5313 #define L5CM_PCS_ATTRIBUTES_COMPARE_HASH_RESULT_SHIFT 2 5314 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT (0x1<<3) 5315 #define L5CM_PCS_ATTRIBUTES_QUERY_ULP_ACCEPT_SHIFT 3 5316 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC (0x1<<4) 5317 #define L5CM_PCS_ATTRIBUTES_FIND_DEST_MAC_SHIFT 4 5318 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD (0x1<<5) 5319 #define L5CM_PCS_ATTRIBUTES_L4_OFFLOAD_SHIFT 5 5320 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET (0x1<<6) 5321 #define L5CM_PCS_ATTRIBUTES_FORWARD_PACKET_SHIFT 6 5322 #define L5CM_PCS_ATTRIBUTES_RSRV (0x1<<7) 5323 #define L5CM_PCS_ATTRIBUTES_RSRV_SHIFT 7 5324 u8 status; 5325 u16 pcs_id; 5326 #endif 5327 }; 5328 5329 5330 union l5cm_seg_params { 5331 struct l5cm_pcse_syn syn_seg_params; 5332 struct l5cm_pcse_ack ack_seg_params; 5333 }; 5334 5335 /* 5336 * pcs entry data for passive connections 5337 */ 5338 struct l5cm_pcs_hdr { 5339 struct l5cm_hash_input_string hash_input_string; 5340 struct l5cm_conn_addr_params conn_addr_buf; 5341 u32 cid; 5342 u32 hash_result; 5343 union l5cm_seg_params seg_params; 5344 struct l5cm_pcs_attributes att; 5345 #if defined(__BIG_ENDIAN) 5346 u16 rsrv; 5347 u16 rx_seg_size; 5348 #elif defined(__LITTLE_ENDIAN) 5349 u16 rx_seg_size; 5350 u16 rsrv; 5351 #endif 5352 }; 5353 5354 /* 5355 * pcs entry for passive connections 5356 */ 5357 struct l5cm_pcs_entry { 5358 struct l5cm_pcs_hdr hdr; 5359 u8 rx_segment[1516]; 5360 }; 5361 5362 5363 5364 5365 /* 5366 * l5cm connection parameters 5367 */ 5368 union l5cm_reduce_param_union { 5369 u32 opaque1; 5370 u32 opaque2; 5371 }; 5372 5373 /* 5374 * l5cm connection parameters 5375 */ 5376 struct l5cm_reduce_conn { 5377 union l5cm_reduce_param_union opaque1; 5378 u32 opaque2; 5379 }; 5380 5381 /* 5382 * l5cm slow path element 5383 */ 5384 union l5cm_specific_data { 5385 u8 protocol_data[8]; 5386 struct regpair phy_address; 5387 struct l5cm_packet_size packet_size; 5388 struct l5cm_reduce_conn reduced_conn; 5389 }; 5390 5391 /* 5392 * l5 slow path element 5393 */ 5394 struct l5cm_spe { 5395 struct spe_hdr hdr; 5396 union l5cm_specific_data data; 5397 }; 5398 5399 5400 5401 5402 /* 5403 * Termination variables 5404 */ 5405 struct l5cm_term_vars { 5406 u8 BitMap; 5407 #define L5CM_TERM_VARS_TCP_STATE (0xF<<0) 5408 #define L5CM_TERM_VARS_TCP_STATE_SHIFT 0 5409 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) 5410 #define L5CM_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4 5411 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) 5412 #define L5CM_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5 5413 #define L5CM_TERM_VARS_TERM_ON_CHIP (0x1<<6) 5414 #define L5CM_TERM_VARS_TERM_ON_CHIP_SHIFT 6 5415 #define L5CM_TERM_VARS_RSRV (0x1<<7) 5416 #define L5CM_TERM_VARS_RSRV_SHIFT 7 5417 }; 5418 5419 5420 5421 5422 /* 5423 * Tstorm Tcp flags 5424 */ 5425 struct tstorm_l5cm_tcp_flags { 5426 u16 flags; 5427 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) 5428 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0 5429 #define TSTORM_L5CM_TCP_FLAGS_RSRV0 (0x1<<12) 5430 #define TSTORM_L5CM_TCP_FLAGS_RSRV0_SHIFT 12 5431 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) 5432 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13 5433 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) 5434 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14 5435 }; 5436 5437 5438 /* 5439 * Xstorm Tcp flags 5440 */ 5441 struct xstorm_l5cm_tcp_flags { 5442 u8 flags; 5443 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED (0x1<<0) 5444 #define XSTORM_L5CM_TCP_FLAGS_ENC_ENABLED_SHIFT 0 5445 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<1) 5446 #define XSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 1 5447 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN (0x1<<2) 5448 #define XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN_SHIFT 2 5449 #define XSTORM_L5CM_TCP_FLAGS_RSRV (0x1F<<3) 5450 #define XSTORM_L5CM_TCP_FLAGS_RSRV_SHIFT 3 5451 }; 5452 5453 5454 5455 /* 5456 * Out-of-order states 5457 */ 5458 enum tcp_ooo_event { 5459 TCP_EVENT_ADD_PEN = 0, 5460 TCP_EVENT_ADD_NEW_ISLE = 1, 5461 TCP_EVENT_ADD_ISLE_RIGHT = 2, 5462 TCP_EVENT_ADD_ISLE_LEFT = 3, 5463 TCP_EVENT_JOIN = 4, 5464 TCP_EVENT_NOP = 5, 5465 MAX_TCP_OOO_EVENT 5466 }; 5467 5468 5469 /* 5470 * OOO support modes 5471 */ 5472 enum tcp_tstorm_ooo { 5473 TCP_TSTORM_OOO_DROP_AND_PROC_ACK = 0, 5474 TCP_TSTORM_OOO_SEND_PURE_ACK = 1, 5475 TCP_TSTORM_OOO_SUPPORTED = 2, 5476 MAX_TCP_TSTORM_OOO 5477 }; 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 #endif /* __5710_HSI_CNIC_LE__ */ 5488