1 /* cnic.c: QLogic CNIC core network driver.
2  *
3  * Copyright (c) 2006-2014 Broadcom Corporation
4  * Copyright (c) 2014-2015 QLogic Corporation
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  *
10  * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
11  * Previously modified and maintained by: Michael Chan <mchan@broadcom.com>
12  * Maintained By: Dept-HSGLinuxNICDev@qlogic.com
13  */
14 
15 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16 
17 #include <linux/module.h>
18 
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/list.h>
22 #include <linux/slab.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/uio_driver.h>
27 #include <linux/in.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/delay.h>
30 #include <linux/ethtool.h>
31 #include <linux/if_vlan.h>
32 #include <linux/prefetch.h>
33 #include <linux/random.h>
34 #if IS_ENABLED(CONFIG_VLAN_8021Q)
35 #define BCM_VLAN 1
36 #endif
37 #include <net/ip.h>
38 #include <net/tcp.h>
39 #include <net/route.h>
40 #include <net/ipv6.h>
41 #include <net/ip6_route.h>
42 #include <net/ip6_checksum.h>
43 #include <scsi/iscsi_if.h>
44 
45 #define BCM_CNIC	1
46 #include "cnic_if.h"
47 #include "bnx2.h"
48 #include "bnx2x/bnx2x.h"
49 #include "bnx2x/bnx2x_reg.h"
50 #include "bnx2x/bnx2x_fw_defs.h"
51 #include "bnx2x/bnx2x_hsi.h"
52 #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
53 #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
54 #include "../../../scsi/bnx2fc/bnx2fc_constants.h"
55 #include "cnic.h"
56 #include "cnic_defs.h"
57 
58 #define CNIC_MODULE_NAME	"cnic"
59 
60 static char version[] =
61 	"QLogic " CNIC_MODULE_NAME "Driver v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
62 
63 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
64 	      "Chen (zongxi@broadcom.com");
65 MODULE_DESCRIPTION("QLogic cnic Driver");
66 MODULE_LICENSE("GPL");
67 MODULE_VERSION(CNIC_MODULE_VERSION);
68 
69 /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
70 static LIST_HEAD(cnic_dev_list);
71 static LIST_HEAD(cnic_udev_list);
72 static DEFINE_RWLOCK(cnic_dev_lock);
73 static DEFINE_MUTEX(cnic_lock);
74 
75 static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
76 
77 /* helper function, assuming cnic_lock is held */
78 static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
79 {
80 	return rcu_dereference_protected(cnic_ulp_tbl[type],
81 					 lockdep_is_held(&cnic_lock));
82 }
83 
84 static int cnic_service_bnx2(void *, void *);
85 static int cnic_service_bnx2x(void *, void *);
86 static int cnic_ctl(void *, struct cnic_ctl_info *);
87 
88 static struct cnic_ops cnic_bnx2_ops = {
89 	.cnic_owner	= THIS_MODULE,
90 	.cnic_handler	= cnic_service_bnx2,
91 	.cnic_ctl	= cnic_ctl,
92 };
93 
94 static struct cnic_ops cnic_bnx2x_ops = {
95 	.cnic_owner	= THIS_MODULE,
96 	.cnic_handler	= cnic_service_bnx2x,
97 	.cnic_ctl	= cnic_ctl,
98 };
99 
100 static struct workqueue_struct *cnic_wq;
101 
102 static void cnic_shutdown_rings(struct cnic_dev *);
103 static void cnic_init_rings(struct cnic_dev *);
104 static int cnic_cm_set_pg(struct cnic_sock *);
105 
106 static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
107 {
108 	struct cnic_uio_dev *udev = uinfo->priv;
109 	struct cnic_dev *dev;
110 
111 	if (!capable(CAP_NET_ADMIN))
112 		return -EPERM;
113 
114 	if (udev->uio_dev != -1)
115 		return -EBUSY;
116 
117 	rtnl_lock();
118 	dev = udev->dev;
119 
120 	if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
121 		rtnl_unlock();
122 		return -ENODEV;
123 	}
124 
125 	udev->uio_dev = iminor(inode);
126 
127 	cnic_shutdown_rings(dev);
128 	cnic_init_rings(dev);
129 	rtnl_unlock();
130 
131 	return 0;
132 }
133 
134 static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
135 {
136 	struct cnic_uio_dev *udev = uinfo->priv;
137 
138 	udev->uio_dev = -1;
139 	return 0;
140 }
141 
142 static inline void cnic_hold(struct cnic_dev *dev)
143 {
144 	atomic_inc(&dev->ref_count);
145 }
146 
147 static inline void cnic_put(struct cnic_dev *dev)
148 {
149 	atomic_dec(&dev->ref_count);
150 }
151 
152 static inline void csk_hold(struct cnic_sock *csk)
153 {
154 	atomic_inc(&csk->ref_count);
155 }
156 
157 static inline void csk_put(struct cnic_sock *csk)
158 {
159 	atomic_dec(&csk->ref_count);
160 }
161 
162 static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
163 {
164 	struct cnic_dev *cdev;
165 
166 	read_lock(&cnic_dev_lock);
167 	list_for_each_entry(cdev, &cnic_dev_list, list) {
168 		if (netdev == cdev->netdev) {
169 			cnic_hold(cdev);
170 			read_unlock(&cnic_dev_lock);
171 			return cdev;
172 		}
173 	}
174 	read_unlock(&cnic_dev_lock);
175 	return NULL;
176 }
177 
178 static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
179 {
180 	atomic_inc(&ulp_ops->ref_count);
181 }
182 
183 static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
184 {
185 	atomic_dec(&ulp_ops->ref_count);
186 }
187 
188 static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
189 {
190 	struct cnic_local *cp = dev->cnic_priv;
191 	struct cnic_eth_dev *ethdev = cp->ethdev;
192 	struct drv_ctl_info info;
193 	struct drv_ctl_io *io = &info.data.io;
194 
195 	memset(&info, 0, sizeof(struct drv_ctl_info));
196 	info.cmd = DRV_CTL_CTX_WR_CMD;
197 	io->cid_addr = cid_addr;
198 	io->offset = off;
199 	io->data = val;
200 	ethdev->drv_ctl(dev->netdev, &info);
201 }
202 
203 static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
204 {
205 	struct cnic_local *cp = dev->cnic_priv;
206 	struct cnic_eth_dev *ethdev = cp->ethdev;
207 	struct drv_ctl_info info;
208 	struct drv_ctl_io *io = &info.data.io;
209 
210 	memset(&info, 0, sizeof(struct drv_ctl_info));
211 	info.cmd = DRV_CTL_CTXTBL_WR_CMD;
212 	io->offset = off;
213 	io->dma_addr = addr;
214 	ethdev->drv_ctl(dev->netdev, &info);
215 }
216 
217 static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
218 {
219 	struct cnic_local *cp = dev->cnic_priv;
220 	struct cnic_eth_dev *ethdev = cp->ethdev;
221 	struct drv_ctl_info info;
222 	struct drv_ctl_l2_ring *ring = &info.data.ring;
223 
224 	memset(&info, 0, sizeof(struct drv_ctl_info));
225 	if (start)
226 		info.cmd = DRV_CTL_START_L2_CMD;
227 	else
228 		info.cmd = DRV_CTL_STOP_L2_CMD;
229 
230 	ring->cid = cid;
231 	ring->client_id = cl_id;
232 	ethdev->drv_ctl(dev->netdev, &info);
233 }
234 
235 static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
236 {
237 	struct cnic_local *cp = dev->cnic_priv;
238 	struct cnic_eth_dev *ethdev = cp->ethdev;
239 	struct drv_ctl_info info;
240 	struct drv_ctl_io *io = &info.data.io;
241 
242 	memset(&info, 0, sizeof(struct drv_ctl_info));
243 	info.cmd = DRV_CTL_IO_WR_CMD;
244 	io->offset = off;
245 	io->data = val;
246 	ethdev->drv_ctl(dev->netdev, &info);
247 }
248 
249 static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
250 {
251 	struct cnic_local *cp = dev->cnic_priv;
252 	struct cnic_eth_dev *ethdev = cp->ethdev;
253 	struct drv_ctl_info info;
254 	struct drv_ctl_io *io = &info.data.io;
255 
256 	memset(&info, 0, sizeof(struct drv_ctl_info));
257 	info.cmd = DRV_CTL_IO_RD_CMD;
258 	io->offset = off;
259 	ethdev->drv_ctl(dev->netdev, &info);
260 	return io->data;
261 }
262 
263 static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg, int state)
264 {
265 	struct cnic_local *cp = dev->cnic_priv;
266 	struct cnic_eth_dev *ethdev = cp->ethdev;
267 	struct drv_ctl_info info;
268 	struct fcoe_capabilities *fcoe_cap =
269 		&info.data.register_data.fcoe_features;
270 
271 	memset(&info, 0, sizeof(struct drv_ctl_info));
272 	if (reg) {
273 		info.cmd = DRV_CTL_ULP_REGISTER_CMD;
274 		if (ulp_type == CNIC_ULP_FCOE && dev->fcoe_cap)
275 			memcpy(fcoe_cap, dev->fcoe_cap, sizeof(*fcoe_cap));
276 	} else {
277 		info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
278 	}
279 
280 	info.data.ulp_type = ulp_type;
281 	info.drv_state = state;
282 	ethdev->drv_ctl(dev->netdev, &info);
283 }
284 
285 static int cnic_in_use(struct cnic_sock *csk)
286 {
287 	return test_bit(SK_F_INUSE, &csk->flags);
288 }
289 
290 static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
291 {
292 	struct cnic_local *cp = dev->cnic_priv;
293 	struct cnic_eth_dev *ethdev = cp->ethdev;
294 	struct drv_ctl_info info;
295 
296 	memset(&info, 0, sizeof(struct drv_ctl_info));
297 	info.cmd = cmd;
298 	info.data.credit.credit_count = count;
299 	ethdev->drv_ctl(dev->netdev, &info);
300 }
301 
302 static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
303 {
304 	u32 i;
305 
306 	if (!cp->ctx_tbl)
307 		return -EINVAL;
308 
309 	for (i = 0; i < cp->max_cid_space; i++) {
310 		if (cp->ctx_tbl[i].cid == cid) {
311 			*l5_cid = i;
312 			return 0;
313 		}
314 	}
315 	return -EINVAL;
316 }
317 
318 static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
319 			   struct cnic_sock *csk)
320 {
321 	struct iscsi_path path_req;
322 	char *buf = NULL;
323 	u16 len = 0;
324 	u32 msg_type = ISCSI_KEVENT_IF_DOWN;
325 	struct cnic_ulp_ops *ulp_ops;
326 	struct cnic_uio_dev *udev = cp->udev;
327 	int rc = 0, retry = 0;
328 
329 	if (!udev || udev->uio_dev == -1)
330 		return -ENODEV;
331 
332 	if (csk) {
333 		len = sizeof(path_req);
334 		buf = (char *) &path_req;
335 		memset(&path_req, 0, len);
336 
337 		msg_type = ISCSI_KEVENT_PATH_REQ;
338 		path_req.handle = (u64) csk->l5_cid;
339 		if (test_bit(SK_F_IPV6, &csk->flags)) {
340 			memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
341 			       sizeof(struct in6_addr));
342 			path_req.ip_addr_len = 16;
343 		} else {
344 			memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
345 			       sizeof(struct in_addr));
346 			path_req.ip_addr_len = 4;
347 		}
348 		path_req.vlan_id = csk->vlan_id;
349 		path_req.pmtu = csk->mtu;
350 	}
351 
352 	while (retry < 3) {
353 		rc = 0;
354 		rcu_read_lock();
355 		ulp_ops = rcu_dereference(cp->ulp_ops[CNIC_ULP_ISCSI]);
356 		if (ulp_ops)
357 			rc = ulp_ops->iscsi_nl_send_msg(
358 				cp->ulp_handle[CNIC_ULP_ISCSI],
359 				msg_type, buf, len);
360 		rcu_read_unlock();
361 		if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
362 			break;
363 
364 		msleep(100);
365 		retry++;
366 	}
367 	return rc;
368 }
369 
370 static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
371 
372 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
373 				  char *buf, u16 len)
374 {
375 	int rc = -EINVAL;
376 
377 	switch (msg_type) {
378 	case ISCSI_UEVENT_PATH_UPDATE: {
379 		struct cnic_local *cp;
380 		u32 l5_cid;
381 		struct cnic_sock *csk;
382 		struct iscsi_path *path_resp;
383 
384 		if (len < sizeof(*path_resp))
385 			break;
386 
387 		path_resp = (struct iscsi_path *) buf;
388 		cp = dev->cnic_priv;
389 		l5_cid = (u32) path_resp->handle;
390 		if (l5_cid >= MAX_CM_SK_TBL_SZ)
391 			break;
392 
393 		if (!rcu_access_pointer(cp->ulp_ops[CNIC_ULP_L4])) {
394 			rc = -ENODEV;
395 			break;
396 		}
397 		csk = &cp->csk_tbl[l5_cid];
398 		csk_hold(csk);
399 		if (cnic_in_use(csk) &&
400 		    test_bit(SK_F_CONNECT_START, &csk->flags)) {
401 
402 			csk->vlan_id = path_resp->vlan_id;
403 
404 			memcpy(csk->ha, path_resp->mac_addr, ETH_ALEN);
405 			if (test_bit(SK_F_IPV6, &csk->flags))
406 				memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
407 				       sizeof(struct in6_addr));
408 			else
409 				memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
410 				       sizeof(struct in_addr));
411 
412 			if (is_valid_ether_addr(csk->ha)) {
413 				cnic_cm_set_pg(csk);
414 			} else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
415 				!test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
416 
417 				cnic_cm_upcall(cp, csk,
418 					L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
419 				clear_bit(SK_F_CONNECT_START, &csk->flags);
420 			}
421 		}
422 		csk_put(csk);
423 		rc = 0;
424 	}
425 	}
426 
427 	return rc;
428 }
429 
430 static int cnic_offld_prep(struct cnic_sock *csk)
431 {
432 	if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
433 		return 0;
434 
435 	if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
436 		clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
437 		return 0;
438 	}
439 
440 	return 1;
441 }
442 
443 static int cnic_close_prep(struct cnic_sock *csk)
444 {
445 	clear_bit(SK_F_CONNECT_START, &csk->flags);
446 	smp_mb__after_atomic();
447 
448 	if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
449 		while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
450 			msleep(1);
451 
452 		return 1;
453 	}
454 	return 0;
455 }
456 
457 static int cnic_abort_prep(struct cnic_sock *csk)
458 {
459 	clear_bit(SK_F_CONNECT_START, &csk->flags);
460 	smp_mb__after_atomic();
461 
462 	while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
463 		msleep(1);
464 
465 	if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
466 		csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
467 		return 1;
468 	}
469 
470 	return 0;
471 }
472 
473 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
474 {
475 	struct cnic_dev *dev;
476 
477 	if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
478 		pr_err("%s: Bad type %d\n", __func__, ulp_type);
479 		return -EINVAL;
480 	}
481 	mutex_lock(&cnic_lock);
482 	if (cnic_ulp_tbl_prot(ulp_type)) {
483 		pr_err("%s: Type %d has already been registered\n",
484 		       __func__, ulp_type);
485 		mutex_unlock(&cnic_lock);
486 		return -EBUSY;
487 	}
488 
489 	read_lock(&cnic_dev_lock);
490 	list_for_each_entry(dev, &cnic_dev_list, list) {
491 		struct cnic_local *cp = dev->cnic_priv;
492 
493 		clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
494 	}
495 	read_unlock(&cnic_dev_lock);
496 
497 	atomic_set(&ulp_ops->ref_count, 0);
498 	rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
499 	mutex_unlock(&cnic_lock);
500 
501 	/* Prevent race conditions with netdev_event */
502 	rtnl_lock();
503 	list_for_each_entry(dev, &cnic_dev_list, list) {
504 		struct cnic_local *cp = dev->cnic_priv;
505 
506 		if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
507 			ulp_ops->cnic_init(dev);
508 	}
509 	rtnl_unlock();
510 
511 	return 0;
512 }
513 
514 int cnic_unregister_driver(int ulp_type)
515 {
516 	struct cnic_dev *dev;
517 	struct cnic_ulp_ops *ulp_ops;
518 	int i = 0;
519 
520 	if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
521 		pr_err("%s: Bad type %d\n", __func__, ulp_type);
522 		return -EINVAL;
523 	}
524 	mutex_lock(&cnic_lock);
525 	ulp_ops = cnic_ulp_tbl_prot(ulp_type);
526 	if (!ulp_ops) {
527 		pr_err("%s: Type %d has not been registered\n",
528 		       __func__, ulp_type);
529 		goto out_unlock;
530 	}
531 	read_lock(&cnic_dev_lock);
532 	list_for_each_entry(dev, &cnic_dev_list, list) {
533 		struct cnic_local *cp = dev->cnic_priv;
534 
535 		if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
536 			pr_err("%s: Type %d still has devices registered\n",
537 			       __func__, ulp_type);
538 			read_unlock(&cnic_dev_lock);
539 			goto out_unlock;
540 		}
541 	}
542 	read_unlock(&cnic_dev_lock);
543 
544 	RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
545 
546 	mutex_unlock(&cnic_lock);
547 	synchronize_rcu();
548 	while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
549 		msleep(100);
550 		i++;
551 	}
552 
553 	if (atomic_read(&ulp_ops->ref_count) != 0)
554 		pr_warn("%s: Failed waiting for ref count to go to zero\n",
555 			__func__);
556 	return 0;
557 
558 out_unlock:
559 	mutex_unlock(&cnic_lock);
560 	return -EINVAL;
561 }
562 
563 static int cnic_start_hw(struct cnic_dev *);
564 static void cnic_stop_hw(struct cnic_dev *);
565 
566 static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
567 				void *ulp_ctx)
568 {
569 	struct cnic_local *cp = dev->cnic_priv;
570 	struct cnic_ulp_ops *ulp_ops;
571 
572 	if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
573 		pr_err("%s: Bad type %d\n", __func__, ulp_type);
574 		return -EINVAL;
575 	}
576 	mutex_lock(&cnic_lock);
577 	if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
578 		pr_err("%s: Driver with type %d has not been registered\n",
579 		       __func__, ulp_type);
580 		mutex_unlock(&cnic_lock);
581 		return -EAGAIN;
582 	}
583 	if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
584 		pr_err("%s: Type %d has already been registered to this device\n",
585 		       __func__, ulp_type);
586 		mutex_unlock(&cnic_lock);
587 		return -EBUSY;
588 	}
589 
590 	clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
591 	cp->ulp_handle[ulp_type] = ulp_ctx;
592 	ulp_ops = cnic_ulp_tbl_prot(ulp_type);
593 	rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
594 	cnic_hold(dev);
595 
596 	if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
597 		if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
598 			ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
599 
600 	mutex_unlock(&cnic_lock);
601 
602 	cnic_ulp_ctl(dev, ulp_type, true, DRV_ACTIVE);
603 
604 	return 0;
605 
606 }
607 EXPORT_SYMBOL(cnic_register_driver);
608 
609 static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
610 {
611 	struct cnic_local *cp = dev->cnic_priv;
612 	int i = 0;
613 
614 	if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
615 		pr_err("%s: Bad type %d\n", __func__, ulp_type);
616 		return -EINVAL;
617 	}
618 
619 	if (ulp_type == CNIC_ULP_ISCSI)
620 		cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
621 
622 	mutex_lock(&cnic_lock);
623 	if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
624 		RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
625 		cnic_put(dev);
626 	} else {
627 		pr_err("%s: device not registered to this ulp type %d\n",
628 		       __func__, ulp_type);
629 		mutex_unlock(&cnic_lock);
630 		return -EINVAL;
631 	}
632 	mutex_unlock(&cnic_lock);
633 
634 	if (ulp_type == CNIC_ULP_FCOE)
635 		dev->fcoe_cap = NULL;
636 
637 	synchronize_rcu();
638 
639 	while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
640 	       i < 20) {
641 		msleep(100);
642 		i++;
643 	}
644 	if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
645 		netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
646 
647 	if (test_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
648 		cnic_ulp_ctl(dev, ulp_type, false, DRV_UNLOADED);
649 	else
650 		cnic_ulp_ctl(dev, ulp_type, false, DRV_INACTIVE);
651 
652 	return 0;
653 }
654 EXPORT_SYMBOL(cnic_unregister_driver);
655 
656 static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
657 			    u32 next)
658 {
659 	id_tbl->start = start_id;
660 	id_tbl->max = size;
661 	id_tbl->next = next;
662 	spin_lock_init(&id_tbl->lock);
663 	id_tbl->table = bitmap_zalloc(size, GFP_KERNEL);
664 	if (!id_tbl->table)
665 		return -ENOMEM;
666 
667 	return 0;
668 }
669 
670 static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
671 {
672 	bitmap_free(id_tbl->table);
673 	id_tbl->table = NULL;
674 }
675 
676 static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
677 {
678 	int ret = -1;
679 
680 	id -= id_tbl->start;
681 	if (id >= id_tbl->max)
682 		return ret;
683 
684 	spin_lock(&id_tbl->lock);
685 	if (!test_bit(id, id_tbl->table)) {
686 		set_bit(id, id_tbl->table);
687 		ret = 0;
688 	}
689 	spin_unlock(&id_tbl->lock);
690 	return ret;
691 }
692 
693 /* Returns -1 if not successful */
694 static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
695 {
696 	u32 id;
697 
698 	spin_lock(&id_tbl->lock);
699 	id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
700 	if (id >= id_tbl->max) {
701 		id = -1;
702 		if (id_tbl->next != 0) {
703 			id = find_first_zero_bit(id_tbl->table, id_tbl->next);
704 			if (id >= id_tbl->next)
705 				id = -1;
706 		}
707 	}
708 
709 	if (id < id_tbl->max) {
710 		set_bit(id, id_tbl->table);
711 		id_tbl->next = (id + 1) & (id_tbl->max - 1);
712 		id += id_tbl->start;
713 	}
714 
715 	spin_unlock(&id_tbl->lock);
716 
717 	return id;
718 }
719 
720 static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
721 {
722 	if (id == -1)
723 		return;
724 
725 	id -= id_tbl->start;
726 	if (id >= id_tbl->max)
727 		return;
728 
729 	clear_bit(id, id_tbl->table);
730 }
731 
732 static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
733 {
734 	int i;
735 
736 	if (!dma->pg_arr)
737 		return;
738 
739 	for (i = 0; i < dma->num_pages; i++) {
740 		if (dma->pg_arr[i]) {
741 			dma_free_coherent(&dev->pcidev->dev, CNIC_PAGE_SIZE,
742 					  dma->pg_arr[i], dma->pg_map_arr[i]);
743 			dma->pg_arr[i] = NULL;
744 		}
745 	}
746 	if (dma->pgtbl) {
747 		dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
748 				  dma->pgtbl, dma->pgtbl_map);
749 		dma->pgtbl = NULL;
750 	}
751 	kfree(dma->pg_arr);
752 	dma->pg_arr = NULL;
753 	dma->num_pages = 0;
754 }
755 
756 static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
757 {
758 	int i;
759 	__le32 *page_table = (__le32 *) dma->pgtbl;
760 
761 	for (i = 0; i < dma->num_pages; i++) {
762 		/* Each entry needs to be in big endian format. */
763 		*page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
764 		page_table++;
765 		*page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
766 		page_table++;
767 	}
768 }
769 
770 static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
771 {
772 	int i;
773 	__le32 *page_table = (__le32 *) dma->pgtbl;
774 
775 	for (i = 0; i < dma->num_pages; i++) {
776 		/* Each entry needs to be in little endian format. */
777 		*page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
778 		page_table++;
779 		*page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
780 		page_table++;
781 	}
782 }
783 
784 static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
785 			  int pages, int use_pg_tbl)
786 {
787 	int i, size;
788 	struct cnic_local *cp = dev->cnic_priv;
789 
790 	size = pages * (sizeof(void *) + sizeof(dma_addr_t));
791 	dma->pg_arr = kzalloc(size, GFP_ATOMIC);
792 	if (dma->pg_arr == NULL)
793 		return -ENOMEM;
794 
795 	dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
796 	dma->num_pages = pages;
797 
798 	for (i = 0; i < pages; i++) {
799 		dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
800 						    CNIC_PAGE_SIZE,
801 						    &dma->pg_map_arr[i],
802 						    GFP_ATOMIC);
803 		if (dma->pg_arr[i] == NULL)
804 			goto error;
805 	}
806 	if (!use_pg_tbl)
807 		return 0;
808 
809 	dma->pgtbl_size = ((pages * 8) + CNIC_PAGE_SIZE - 1) &
810 			  ~(CNIC_PAGE_SIZE - 1);
811 	dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
812 					&dma->pgtbl_map, GFP_ATOMIC);
813 	if (dma->pgtbl == NULL)
814 		goto error;
815 
816 	cp->setup_pgtbl(dev, dma);
817 
818 	return 0;
819 
820 error:
821 	cnic_free_dma(dev, dma);
822 	return -ENOMEM;
823 }
824 
825 static void cnic_free_context(struct cnic_dev *dev)
826 {
827 	struct cnic_local *cp = dev->cnic_priv;
828 	int i;
829 
830 	for (i = 0; i < cp->ctx_blks; i++) {
831 		if (cp->ctx_arr[i].ctx) {
832 			dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
833 					  cp->ctx_arr[i].ctx,
834 					  cp->ctx_arr[i].mapping);
835 			cp->ctx_arr[i].ctx = NULL;
836 		}
837 	}
838 }
839 
840 static void __cnic_free_uio_rings(struct cnic_uio_dev *udev)
841 {
842 	if (udev->l2_buf) {
843 		dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
844 				  udev->l2_buf, udev->l2_buf_map);
845 		udev->l2_buf = NULL;
846 	}
847 
848 	if (udev->l2_ring) {
849 		dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
850 				  udev->l2_ring, udev->l2_ring_map);
851 		udev->l2_ring = NULL;
852 	}
853 
854 }
855 
856 static void __cnic_free_uio(struct cnic_uio_dev *udev)
857 {
858 	uio_unregister_device(&udev->cnic_uinfo);
859 
860 	__cnic_free_uio_rings(udev);
861 
862 	pci_dev_put(udev->pdev);
863 	kfree(udev);
864 }
865 
866 static void cnic_free_uio(struct cnic_uio_dev *udev)
867 {
868 	if (!udev)
869 		return;
870 
871 	write_lock(&cnic_dev_lock);
872 	list_del_init(&udev->list);
873 	write_unlock(&cnic_dev_lock);
874 	__cnic_free_uio(udev);
875 }
876 
877 static void cnic_free_resc(struct cnic_dev *dev)
878 {
879 	struct cnic_local *cp = dev->cnic_priv;
880 	struct cnic_uio_dev *udev = cp->udev;
881 
882 	if (udev) {
883 		udev->dev = NULL;
884 		cp->udev = NULL;
885 		if (udev->uio_dev == -1)
886 			__cnic_free_uio_rings(udev);
887 	}
888 
889 	cnic_free_context(dev);
890 	kfree(cp->ctx_arr);
891 	cp->ctx_arr = NULL;
892 	cp->ctx_blks = 0;
893 
894 	cnic_free_dma(dev, &cp->gbl_buf_info);
895 	cnic_free_dma(dev, &cp->kwq_info);
896 	cnic_free_dma(dev, &cp->kwq_16_data_info);
897 	cnic_free_dma(dev, &cp->kcq2.dma);
898 	cnic_free_dma(dev, &cp->kcq1.dma);
899 	kfree(cp->iscsi_tbl);
900 	cp->iscsi_tbl = NULL;
901 	kfree(cp->ctx_tbl);
902 	cp->ctx_tbl = NULL;
903 
904 	cnic_free_id_tbl(&cp->fcoe_cid_tbl);
905 	cnic_free_id_tbl(&cp->cid_tbl);
906 }
907 
908 static int cnic_alloc_context(struct cnic_dev *dev)
909 {
910 	struct cnic_local *cp = dev->cnic_priv;
911 
912 	if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
913 		int i, k, arr_size;
914 
915 		cp->ctx_blk_size = CNIC_PAGE_SIZE;
916 		cp->cids_per_blk = CNIC_PAGE_SIZE / 128;
917 		arr_size = BNX2_MAX_CID / cp->cids_per_blk *
918 			   sizeof(struct cnic_ctx);
919 		cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
920 		if (cp->ctx_arr == NULL)
921 			return -ENOMEM;
922 
923 		k = 0;
924 		for (i = 0; i < 2; i++) {
925 			u32 j, reg, off, lo, hi;
926 
927 			if (i == 0)
928 				off = BNX2_PG_CTX_MAP;
929 			else
930 				off = BNX2_ISCSI_CTX_MAP;
931 
932 			reg = cnic_reg_rd_ind(dev, off);
933 			lo = reg >> 16;
934 			hi = reg & 0xffff;
935 			for (j = lo; j < hi; j += cp->cids_per_blk, k++)
936 				cp->ctx_arr[k].cid = j;
937 		}
938 
939 		cp->ctx_blks = k;
940 		if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
941 			cp->ctx_blks = 0;
942 			return -ENOMEM;
943 		}
944 
945 		for (i = 0; i < cp->ctx_blks; i++) {
946 			cp->ctx_arr[i].ctx =
947 				dma_alloc_coherent(&dev->pcidev->dev,
948 						   CNIC_PAGE_SIZE,
949 						   &cp->ctx_arr[i].mapping,
950 						   GFP_KERNEL);
951 			if (cp->ctx_arr[i].ctx == NULL)
952 				return -ENOMEM;
953 		}
954 	}
955 	return 0;
956 }
957 
958 static u16 cnic_bnx2_next_idx(u16 idx)
959 {
960 	return idx + 1;
961 }
962 
963 static u16 cnic_bnx2_hw_idx(u16 idx)
964 {
965 	return idx;
966 }
967 
968 static u16 cnic_bnx2x_next_idx(u16 idx)
969 {
970 	idx++;
971 	if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
972 		idx++;
973 
974 	return idx;
975 }
976 
977 static u16 cnic_bnx2x_hw_idx(u16 idx)
978 {
979 	if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
980 		idx++;
981 	return idx;
982 }
983 
984 static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
985 			  bool use_pg_tbl)
986 {
987 	int err, i, use_page_tbl = 0;
988 	struct kcqe **kcq;
989 
990 	if (use_pg_tbl)
991 		use_page_tbl = 1;
992 
993 	err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
994 	if (err)
995 		return err;
996 
997 	kcq = (struct kcqe **) info->dma.pg_arr;
998 	info->kcq = kcq;
999 
1000 	info->next_idx = cnic_bnx2_next_idx;
1001 	info->hw_idx = cnic_bnx2_hw_idx;
1002 	if (use_pg_tbl)
1003 		return 0;
1004 
1005 	info->next_idx = cnic_bnx2x_next_idx;
1006 	info->hw_idx = cnic_bnx2x_hw_idx;
1007 
1008 	for (i = 0; i < KCQ_PAGE_CNT; i++) {
1009 		struct bnx2x_bd_chain_next *next =
1010 			(struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
1011 		int j = i + 1;
1012 
1013 		if (j >= KCQ_PAGE_CNT)
1014 			j = 0;
1015 		next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
1016 		next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
1017 	}
1018 	return 0;
1019 }
1020 
1021 static int __cnic_alloc_uio_rings(struct cnic_uio_dev *udev, int pages)
1022 {
1023 	struct cnic_local *cp = udev->dev->cnic_priv;
1024 
1025 	if (udev->l2_ring)
1026 		return 0;
1027 
1028 	udev->l2_ring_size = pages * CNIC_PAGE_SIZE;
1029 	udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
1030 					   &udev->l2_ring_map,
1031 					   GFP_KERNEL | __GFP_COMP);
1032 	if (!udev->l2_ring)
1033 		return -ENOMEM;
1034 
1035 	udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
1036 	udev->l2_buf_size = CNIC_PAGE_ALIGN(udev->l2_buf_size);
1037 	udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
1038 					  &udev->l2_buf_map,
1039 					  GFP_KERNEL | __GFP_COMP);
1040 	if (!udev->l2_buf) {
1041 		__cnic_free_uio_rings(udev);
1042 		return -ENOMEM;
1043 	}
1044 
1045 	return 0;
1046 
1047 }
1048 
1049 static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
1050 {
1051 	struct cnic_local *cp = dev->cnic_priv;
1052 	struct cnic_uio_dev *udev;
1053 
1054 	list_for_each_entry(udev, &cnic_udev_list, list) {
1055 		if (udev->pdev == dev->pcidev) {
1056 			udev->dev = dev;
1057 			if (__cnic_alloc_uio_rings(udev, pages)) {
1058 				udev->dev = NULL;
1059 				return -ENOMEM;
1060 			}
1061 			cp->udev = udev;
1062 			return 0;
1063 		}
1064 	}
1065 
1066 	udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
1067 	if (!udev)
1068 		return -ENOMEM;
1069 
1070 	udev->uio_dev = -1;
1071 
1072 	udev->dev = dev;
1073 	udev->pdev = dev->pcidev;
1074 
1075 	if (__cnic_alloc_uio_rings(udev, pages))
1076 		goto err_udev;
1077 
1078 	list_add(&udev->list, &cnic_udev_list);
1079 
1080 	pci_dev_get(udev->pdev);
1081 
1082 	cp->udev = udev;
1083 
1084 	return 0;
1085 
1086  err_udev:
1087 	kfree(udev);
1088 	return -ENOMEM;
1089 }
1090 
1091 static int cnic_init_uio(struct cnic_dev *dev)
1092 {
1093 	struct cnic_local *cp = dev->cnic_priv;
1094 	struct cnic_uio_dev *udev = cp->udev;
1095 	struct uio_info *uinfo;
1096 	int ret = 0;
1097 
1098 	if (!udev)
1099 		return -ENOMEM;
1100 
1101 	uinfo = &udev->cnic_uinfo;
1102 
1103 	uinfo->mem[0].addr = pci_resource_start(dev->pcidev, 0);
1104 	uinfo->mem[0].internal_addr = dev->regview;
1105 	uinfo->mem[0].memtype = UIO_MEM_PHYS;
1106 
1107 	if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
1108 		uinfo->mem[0].size = MB_GET_CID_ADDR(TX_TSS_CID +
1109 						     TX_MAX_TSS_RINGS + 1);
1110 		uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
1111 					CNIC_PAGE_MASK;
1112 		if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
1113 			uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
1114 		else
1115 			uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
1116 
1117 		uinfo->name = "bnx2_cnic";
1118 	} else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
1119 		uinfo->mem[0].size = pci_resource_len(dev->pcidev, 0);
1120 
1121 		uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
1122 			CNIC_PAGE_MASK;
1123 		uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
1124 
1125 		uinfo->name = "bnx2x_cnic";
1126 	}
1127 
1128 	uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
1129 
1130 	uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
1131 	uinfo->mem[2].size = udev->l2_ring_size;
1132 	uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
1133 
1134 	uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
1135 	uinfo->mem[3].size = udev->l2_buf_size;
1136 	uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
1137 
1138 	uinfo->version = CNIC_MODULE_VERSION;
1139 	uinfo->irq = UIO_IRQ_CUSTOM;
1140 
1141 	uinfo->open = cnic_uio_open;
1142 	uinfo->release = cnic_uio_close;
1143 
1144 	if (udev->uio_dev == -1) {
1145 		if (!uinfo->priv) {
1146 			uinfo->priv = udev;
1147 
1148 			ret = uio_register_device(&udev->pdev->dev, uinfo);
1149 		}
1150 	} else {
1151 		cnic_init_rings(dev);
1152 	}
1153 
1154 	return ret;
1155 }
1156 
1157 static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
1158 {
1159 	struct cnic_local *cp = dev->cnic_priv;
1160 	int ret;
1161 
1162 	ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
1163 	if (ret)
1164 		goto error;
1165 	cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
1166 
1167 	ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
1168 	if (ret)
1169 		goto error;
1170 
1171 	ret = cnic_alloc_context(dev);
1172 	if (ret)
1173 		goto error;
1174 
1175 	ret = cnic_alloc_uio_rings(dev, 2);
1176 	if (ret)
1177 		goto error;
1178 
1179 	ret = cnic_init_uio(dev);
1180 	if (ret)
1181 		goto error;
1182 
1183 	return 0;
1184 
1185 error:
1186 	cnic_free_resc(dev);
1187 	return ret;
1188 }
1189 
1190 static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
1191 {
1192 	struct cnic_local *cp = dev->cnic_priv;
1193 	struct bnx2x *bp = netdev_priv(dev->netdev);
1194 	int ctx_blk_size = cp->ethdev->ctx_blk_size;
1195 	int total_mem, blks, i;
1196 
1197 	total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
1198 	blks = total_mem / ctx_blk_size;
1199 	if (total_mem % ctx_blk_size)
1200 		blks++;
1201 
1202 	if (blks > cp->ethdev->ctx_tbl_len)
1203 		return -ENOMEM;
1204 
1205 	cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
1206 	if (cp->ctx_arr == NULL)
1207 		return -ENOMEM;
1208 
1209 	cp->ctx_blks = blks;
1210 	cp->ctx_blk_size = ctx_blk_size;
1211 	if (!CHIP_IS_E1(bp))
1212 		cp->ctx_align = 0;
1213 	else
1214 		cp->ctx_align = ctx_blk_size;
1215 
1216 	cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
1217 
1218 	for (i = 0; i < blks; i++) {
1219 		cp->ctx_arr[i].ctx =
1220 			dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
1221 					   &cp->ctx_arr[i].mapping,
1222 					   GFP_KERNEL);
1223 		if (cp->ctx_arr[i].ctx == NULL)
1224 			return -ENOMEM;
1225 
1226 		if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
1227 			if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
1228 				cnic_free_context(dev);
1229 				cp->ctx_blk_size += cp->ctx_align;
1230 				i = -1;
1231 				continue;
1232 			}
1233 		}
1234 	}
1235 	return 0;
1236 }
1237 
1238 static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
1239 {
1240 	struct cnic_local *cp = dev->cnic_priv;
1241 	struct bnx2x *bp = netdev_priv(dev->netdev);
1242 	struct cnic_eth_dev *ethdev = cp->ethdev;
1243 	u32 start_cid = ethdev->starting_cid;
1244 	int i, j, n, ret, pages;
1245 	struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
1246 
1247 	cp->max_cid_space = MAX_ISCSI_TBL_SZ;
1248 	cp->iscsi_start_cid = start_cid;
1249 	cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
1250 
1251 	if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
1252 		cp->max_cid_space += dev->max_fcoe_conn;
1253 		cp->fcoe_init_cid = ethdev->fcoe_init_cid;
1254 		if (!cp->fcoe_init_cid)
1255 			cp->fcoe_init_cid = 0x10;
1256 	}
1257 
1258 	cp->iscsi_tbl = kcalloc(MAX_ISCSI_TBL_SZ, sizeof(struct cnic_iscsi),
1259 				GFP_KERNEL);
1260 	if (!cp->iscsi_tbl)
1261 		goto error;
1262 
1263 	cp->ctx_tbl = kcalloc(cp->max_cid_space, sizeof(struct cnic_context),
1264 			      GFP_KERNEL);
1265 	if (!cp->ctx_tbl)
1266 		goto error;
1267 
1268 	for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
1269 		cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
1270 		cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
1271 	}
1272 
1273 	for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
1274 		cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
1275 
1276 	pages = CNIC_PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
1277 		CNIC_PAGE_SIZE;
1278 
1279 	ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
1280 	if (ret)
1281 		goto error;
1282 
1283 	n = CNIC_PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
1284 	for (i = 0, j = 0; i < cp->max_cid_space; i++) {
1285 		long off = CNIC_KWQ16_DATA_SIZE * (i % n);
1286 
1287 		cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
1288 		cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
1289 						   off;
1290 
1291 		if ((i % n) == (n - 1))
1292 			j++;
1293 	}
1294 
1295 	ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
1296 	if (ret)
1297 		goto error;
1298 
1299 	if (CNIC_SUPPORTS_FCOE(bp)) {
1300 		ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
1301 		if (ret)
1302 			goto error;
1303 	}
1304 
1305 	pages = CNIC_PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / CNIC_PAGE_SIZE;
1306 	ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
1307 	if (ret)
1308 		goto error;
1309 
1310 	ret = cnic_alloc_bnx2x_context(dev);
1311 	if (ret)
1312 		goto error;
1313 
1314 	if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
1315 		return 0;
1316 
1317 	cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
1318 
1319 	cp->l2_rx_ring_size = 15;
1320 
1321 	ret = cnic_alloc_uio_rings(dev, 4);
1322 	if (ret)
1323 		goto error;
1324 
1325 	ret = cnic_init_uio(dev);
1326 	if (ret)
1327 		goto error;
1328 
1329 	return 0;
1330 
1331 error:
1332 	cnic_free_resc(dev);
1333 	return -ENOMEM;
1334 }
1335 
1336 static inline u32 cnic_kwq_avail(struct cnic_local *cp)
1337 {
1338 	return cp->max_kwq_idx -
1339 		((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
1340 }
1341 
1342 static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
1343 				  u32 num_wqes)
1344 {
1345 	struct cnic_local *cp = dev->cnic_priv;
1346 	struct kwqe *prod_qe;
1347 	u16 prod, sw_prod, i;
1348 
1349 	if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
1350 		return -EAGAIN;		/* bnx2 is down */
1351 
1352 	spin_lock_bh(&cp->cnic_ulp_lock);
1353 	if (num_wqes > cnic_kwq_avail(cp) &&
1354 	    !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
1355 		spin_unlock_bh(&cp->cnic_ulp_lock);
1356 		return -EAGAIN;
1357 	}
1358 
1359 	clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
1360 
1361 	prod = cp->kwq_prod_idx;
1362 	sw_prod = prod & MAX_KWQ_IDX;
1363 	for (i = 0; i < num_wqes; i++) {
1364 		prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
1365 		memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
1366 		prod++;
1367 		sw_prod = prod & MAX_KWQ_IDX;
1368 	}
1369 	cp->kwq_prod_idx = prod;
1370 
1371 	CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
1372 
1373 	spin_unlock_bh(&cp->cnic_ulp_lock);
1374 	return 0;
1375 }
1376 
1377 static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
1378 				   union l5cm_specific_data *l5_data)
1379 {
1380 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1381 	dma_addr_t map;
1382 
1383 	map = ctx->kwqe_data_mapping;
1384 	l5_data->phy_address.lo = (u64) map & 0xffffffff;
1385 	l5_data->phy_address.hi = (u64) map >> 32;
1386 	return ctx->kwqe_data;
1387 }
1388 
1389 static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
1390 				u32 type, union l5cm_specific_data *l5_data)
1391 {
1392 	struct cnic_local *cp = dev->cnic_priv;
1393 	struct bnx2x *bp = netdev_priv(dev->netdev);
1394 	struct l5cm_spe kwqe;
1395 	struct kwqe_16 *kwq[1];
1396 	u16 type_16;
1397 	int ret;
1398 
1399 	kwqe.hdr.conn_and_cmd_data =
1400 		cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
1401 			     BNX2X_HW_CID(bp, cid)));
1402 
1403 	type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
1404 	type_16 |= (bp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
1405 		   SPE_HDR_FUNCTION_ID;
1406 
1407 	kwqe.hdr.type = cpu_to_le16(type_16);
1408 	kwqe.hdr.reserved1 = 0;
1409 	kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
1410 	kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
1411 
1412 	kwq[0] = (struct kwqe_16 *) &kwqe;
1413 
1414 	spin_lock_bh(&cp->cnic_ulp_lock);
1415 	ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
1416 	spin_unlock_bh(&cp->cnic_ulp_lock);
1417 
1418 	if (ret == 1)
1419 		return 0;
1420 
1421 	return ret;
1422 }
1423 
1424 static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
1425 				   struct kcqe *cqes[], u32 num_cqes)
1426 {
1427 	struct cnic_local *cp = dev->cnic_priv;
1428 	struct cnic_ulp_ops *ulp_ops;
1429 
1430 	rcu_read_lock();
1431 	ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
1432 	if (likely(ulp_ops)) {
1433 		ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
1434 					  cqes, num_cqes);
1435 	}
1436 	rcu_read_unlock();
1437 }
1438 
1439 static void cnic_bnx2x_set_tcp_options(struct cnic_dev *dev, int time_stamps,
1440 				       int en_tcp_dack)
1441 {
1442 	struct bnx2x *bp = netdev_priv(dev->netdev);
1443 	u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
1444 	u16 tstorm_flags = 0;
1445 
1446 	if (time_stamps) {
1447 		xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1448 		tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
1449 	}
1450 	if (en_tcp_dack)
1451 		tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN;
1452 
1453 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1454 		 XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), xstorm_flags);
1455 
1456 	CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1457 		  TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(bp->pfid), tstorm_flags);
1458 }
1459 
1460 static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
1461 {
1462 	struct cnic_local *cp = dev->cnic_priv;
1463 	struct bnx2x *bp = netdev_priv(dev->netdev);
1464 	struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
1465 	int hq_bds, pages;
1466 	u32 pfid = bp->pfid;
1467 
1468 	cp->num_iscsi_tasks = req1->num_tasks_per_conn;
1469 	cp->num_ccells = req1->num_ccells_per_conn;
1470 	cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
1471 			      cp->num_iscsi_tasks;
1472 	cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
1473 			BNX2X_ISCSI_R2TQE_SIZE;
1474 	cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
1475 	pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
1476 	hq_bds = pages * (CNIC_PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
1477 	cp->num_cqs = req1->num_cqs;
1478 
1479 	if (!dev->max_iscsi_conn)
1480 		return 0;
1481 
1482 	/* init Tstorm RAM */
1483 	CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1484 		  req1->rq_num_wqes);
1485 	CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1486 		  CNIC_PAGE_SIZE);
1487 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
1488 		 TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
1489 	CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
1490 		  TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1491 		  req1->num_tasks_per_conn);
1492 
1493 	/* init Ustorm RAM */
1494 	CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1495 		  USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
1496 		  req1->rq_buffer_size);
1497 	CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1498 		  CNIC_PAGE_SIZE);
1499 	CNIC_WR8(dev, BAR_USTRORM_INTMEM +
1500 		 USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
1501 	CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1502 		  USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1503 		  req1->num_tasks_per_conn);
1504 	CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
1505 		  req1->rq_num_wqes);
1506 	CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1507 		  req1->cq_num_wqes);
1508 	CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1509 		  cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1510 
1511 	/* init Xstorm RAM */
1512 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1513 		  CNIC_PAGE_SIZE);
1514 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
1515 		 XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
1516 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
1517 		  XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1518 		  req1->num_tasks_per_conn);
1519 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1520 		  hq_bds);
1521 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
1522 		  req1->num_tasks_per_conn);
1523 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
1524 		  cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
1525 
1526 	/* init Cstorm RAM */
1527 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
1528 		  CNIC_PAGE_SIZE);
1529 	CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
1530 		 CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), CNIC_PAGE_BITS);
1531 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1532 		  CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
1533 		  req1->num_tasks_per_conn);
1534 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
1535 		  req1->cq_num_wqes);
1536 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
1537 		  hq_bds);
1538 
1539 	cnic_bnx2x_set_tcp_options(dev,
1540 			req1->flags & ISCSI_KWQE_INIT1_TIME_STAMPS_ENABLE,
1541 			req1->flags & ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE);
1542 
1543 	return 0;
1544 }
1545 
1546 static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
1547 {
1548 	struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
1549 	struct bnx2x *bp = netdev_priv(dev->netdev);
1550 	u32 pfid = bp->pfid;
1551 	struct iscsi_kcqe kcqe;
1552 	struct kcqe *cqes[1];
1553 
1554 	memset(&kcqe, 0, sizeof(kcqe));
1555 	if (!dev->max_iscsi_conn) {
1556 		kcqe.completion_status =
1557 			ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
1558 		goto done;
1559 	}
1560 
1561 	CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1562 		TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1563 	CNIC_WR(dev, BAR_TSTRORM_INTMEM +
1564 		TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1565 		req2->error_bit_map[1]);
1566 
1567 	CNIC_WR16(dev, BAR_USTRORM_INTMEM +
1568 		  USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1569 	CNIC_WR(dev, BAR_USTRORM_INTMEM +
1570 		USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
1571 	CNIC_WR(dev, BAR_USTRORM_INTMEM +
1572 		USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
1573 		req2->error_bit_map[1]);
1574 
1575 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
1576 		  CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
1577 
1578 	kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1579 
1580 done:
1581 	kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
1582 	cqes[0] = (struct kcqe *) &kcqe;
1583 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1584 
1585 	return 0;
1586 }
1587 
1588 static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1589 {
1590 	struct cnic_local *cp = dev->cnic_priv;
1591 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1592 
1593 	if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
1594 		struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1595 
1596 		cnic_free_dma(dev, &iscsi->hq_info);
1597 		cnic_free_dma(dev, &iscsi->r2tq_info);
1598 		cnic_free_dma(dev, &iscsi->task_array_info);
1599 		cnic_free_id(&cp->cid_tbl, ctx->cid);
1600 	} else {
1601 		cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
1602 	}
1603 
1604 	ctx->cid = 0;
1605 }
1606 
1607 static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
1608 {
1609 	u32 cid;
1610 	int ret, pages;
1611 	struct cnic_local *cp = dev->cnic_priv;
1612 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1613 	struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1614 
1615 	if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
1616 		cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
1617 		if (cid == -1) {
1618 			ret = -ENOMEM;
1619 			goto error;
1620 		}
1621 		ctx->cid = cid;
1622 		return 0;
1623 	}
1624 
1625 	cid = cnic_alloc_new_id(&cp->cid_tbl);
1626 	if (cid == -1) {
1627 		ret = -ENOMEM;
1628 		goto error;
1629 	}
1630 
1631 	ctx->cid = cid;
1632 	pages = CNIC_PAGE_ALIGN(cp->task_array_size) / CNIC_PAGE_SIZE;
1633 
1634 	ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
1635 	if (ret)
1636 		goto error;
1637 
1638 	pages = CNIC_PAGE_ALIGN(cp->r2tq_size) / CNIC_PAGE_SIZE;
1639 	ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
1640 	if (ret)
1641 		goto error;
1642 
1643 	pages = CNIC_PAGE_ALIGN(cp->hq_size) / CNIC_PAGE_SIZE;
1644 	ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
1645 	if (ret)
1646 		goto error;
1647 
1648 	return 0;
1649 
1650 error:
1651 	cnic_free_bnx2x_conn_resc(dev, l5_cid);
1652 	return ret;
1653 }
1654 
1655 static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
1656 				struct regpair *ctx_addr)
1657 {
1658 	struct cnic_local *cp = dev->cnic_priv;
1659 	struct cnic_eth_dev *ethdev = cp->ethdev;
1660 	int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
1661 	int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
1662 	unsigned long align_off = 0;
1663 	dma_addr_t ctx_map;
1664 	void *ctx;
1665 
1666 	if (cp->ctx_align) {
1667 		unsigned long mask = cp->ctx_align - 1;
1668 
1669 		if (cp->ctx_arr[blk].mapping & mask)
1670 			align_off = cp->ctx_align -
1671 				    (cp->ctx_arr[blk].mapping & mask);
1672 	}
1673 	ctx_map = cp->ctx_arr[blk].mapping + align_off +
1674 		(off * BNX2X_CONTEXT_MEM_SIZE);
1675 	ctx = cp->ctx_arr[blk].ctx + align_off +
1676 	      (off * BNX2X_CONTEXT_MEM_SIZE);
1677 	if (init)
1678 		memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
1679 
1680 	ctx_addr->lo = ctx_map & 0xffffffff;
1681 	ctx_addr->hi = (u64) ctx_map >> 32;
1682 	return ctx;
1683 }
1684 
1685 static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
1686 				u32 num)
1687 {
1688 	struct cnic_local *cp = dev->cnic_priv;
1689 	struct bnx2x *bp = netdev_priv(dev->netdev);
1690 	struct iscsi_kwqe_conn_offload1 *req1 =
1691 			(struct iscsi_kwqe_conn_offload1 *) wqes[0];
1692 	struct iscsi_kwqe_conn_offload2 *req2 =
1693 			(struct iscsi_kwqe_conn_offload2 *) wqes[1];
1694 	struct iscsi_kwqe_conn_offload3 *req3;
1695 	struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
1696 	struct cnic_iscsi *iscsi = ctx->proto.iscsi;
1697 	u32 cid = ctx->cid;
1698 	u32 hw_cid = BNX2X_HW_CID(bp, cid);
1699 	struct iscsi_context *ictx;
1700 	struct regpair context_addr;
1701 	int i, j, n = 2, n_max;
1702 	u8 port = BP_PORT(bp);
1703 
1704 	ctx->ctx_flags = 0;
1705 	if (!req2->num_additional_wqes)
1706 		return -EINVAL;
1707 
1708 	n_max = req2->num_additional_wqes + 2;
1709 
1710 	ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
1711 	if (ictx == NULL)
1712 		return -ENOMEM;
1713 
1714 	req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1715 
1716 	ictx->xstorm_ag_context.hq_prod = 1;
1717 
1718 	ictx->xstorm_st_context.iscsi.first_burst_length =
1719 		ISCSI_DEF_FIRST_BURST_LEN;
1720 	ictx->xstorm_st_context.iscsi.max_send_pdu_length =
1721 		ISCSI_DEF_MAX_RECV_SEG_LEN;
1722 	ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
1723 		req1->sq_page_table_addr_lo;
1724 	ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
1725 		req1->sq_page_table_addr_hi;
1726 	ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
1727 	ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
1728 	ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
1729 		iscsi->hq_info.pgtbl_map & 0xffffffff;
1730 	ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
1731 		(u64) iscsi->hq_info.pgtbl_map >> 32;
1732 	ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
1733 		iscsi->hq_info.pgtbl[0];
1734 	ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
1735 		iscsi->hq_info.pgtbl[1];
1736 	ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
1737 		iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1738 	ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
1739 		(u64) iscsi->r2tq_info.pgtbl_map >> 32;
1740 	ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
1741 		iscsi->r2tq_info.pgtbl[0];
1742 	ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
1743 		iscsi->r2tq_info.pgtbl[1];
1744 	ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
1745 		iscsi->task_array_info.pgtbl_map & 0xffffffff;
1746 	ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
1747 		(u64) iscsi->task_array_info.pgtbl_map >> 32;
1748 	ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
1749 		BNX2X_ISCSI_PBL_NOT_CACHED;
1750 	ictx->xstorm_st_context.iscsi.flags.flags |=
1751 		XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
1752 	ictx->xstorm_st_context.iscsi.flags.flags |=
1753 		XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
1754 	ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
1755 		ETH_P_8021Q;
1756 	if (BNX2X_CHIP_IS_E2_PLUS(bp) &&
1757 	    bp->common.chip_port_mode == CHIP_2_PORT_MODE) {
1758 
1759 		port = 0;
1760 	}
1761 	ictx->xstorm_st_context.common.flags =
1762 		1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
1763 	ictx->xstorm_st_context.common.flags =
1764 		port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
1765 
1766 	ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
1767 	/* TSTORM requires the base address of RQ DB & not PTE */
1768 	ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
1769 		req2->rq_page_table_addr_lo & CNIC_PAGE_MASK;
1770 	ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
1771 		req2->rq_page_table_addr_hi;
1772 	ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
1773 	ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
1774 	ictx->tstorm_st_context.tcp.flags2 |=
1775 		TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
1776 	ictx->tstorm_st_context.tcp.ooo_support_mode =
1777 		TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
1778 
1779 	ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
1780 
1781 	ictx->ustorm_st_context.ring.rq.pbl_base.lo =
1782 		req2->rq_page_table_addr_lo;
1783 	ictx->ustorm_st_context.ring.rq.pbl_base.hi =
1784 		req2->rq_page_table_addr_hi;
1785 	ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
1786 	ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
1787 	ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
1788 		iscsi->r2tq_info.pgtbl_map & 0xffffffff;
1789 	ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
1790 		(u64) iscsi->r2tq_info.pgtbl_map >> 32;
1791 	ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
1792 		iscsi->r2tq_info.pgtbl[0];
1793 	ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
1794 		iscsi->r2tq_info.pgtbl[1];
1795 	ictx->ustorm_st_context.ring.cq_pbl_base.lo =
1796 		req1->cq_page_table_addr_lo;
1797 	ictx->ustorm_st_context.ring.cq_pbl_base.hi =
1798 		req1->cq_page_table_addr_hi;
1799 	ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
1800 	ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
1801 	ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
1802 	ictx->ustorm_st_context.task_pbe_cache_index =
1803 		BNX2X_ISCSI_PBL_NOT_CACHED;
1804 	ictx->ustorm_st_context.task_pdu_cache_index =
1805 		BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
1806 
1807 	for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
1808 		if (j == 3) {
1809 			if (n >= n_max)
1810 				break;
1811 			req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
1812 			j = 0;
1813 		}
1814 		ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
1815 		ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
1816 			req3->qp_first_pte[j].hi;
1817 		ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
1818 			req3->qp_first_pte[j].lo;
1819 	}
1820 
1821 	ictx->ustorm_st_context.task_pbl_base.lo =
1822 		iscsi->task_array_info.pgtbl_map & 0xffffffff;
1823 	ictx->ustorm_st_context.task_pbl_base.hi =
1824 		(u64) iscsi->task_array_info.pgtbl_map >> 32;
1825 	ictx->ustorm_st_context.tce_phy_addr.lo =
1826 		iscsi->task_array_info.pgtbl[0];
1827 	ictx->ustorm_st_context.tce_phy_addr.hi =
1828 		iscsi->task_array_info.pgtbl[1];
1829 	ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1830 	ictx->ustorm_st_context.num_cqs = cp->num_cqs;
1831 	ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
1832 	ictx->ustorm_st_context.negotiated_rx_and_flags |=
1833 		ISCSI_DEF_MAX_BURST_LEN;
1834 	ictx->ustorm_st_context.negotiated_rx |=
1835 		ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
1836 		USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
1837 
1838 	ictx->cstorm_st_context.hq_pbl_base.lo =
1839 		iscsi->hq_info.pgtbl_map & 0xffffffff;
1840 	ictx->cstorm_st_context.hq_pbl_base.hi =
1841 		(u64) iscsi->hq_info.pgtbl_map >> 32;
1842 	ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
1843 	ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
1844 	ictx->cstorm_st_context.task_pbl_base.lo =
1845 		iscsi->task_array_info.pgtbl_map & 0xffffffff;
1846 	ictx->cstorm_st_context.task_pbl_base.hi =
1847 		(u64) iscsi->task_array_info.pgtbl_map >> 32;
1848 	/* CSTORM and USTORM initialization is different, CSTORM requires
1849 	 * CQ DB base & not PTE addr */
1850 	ictx->cstorm_st_context.cq_db_base.lo =
1851 		req1->cq_page_table_addr_lo & CNIC_PAGE_MASK;
1852 	ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
1853 	ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
1854 	ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
1855 	for (i = 0; i < cp->num_cqs; i++) {
1856 		ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
1857 			ISCSI_INITIAL_SN;
1858 		ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
1859 			ISCSI_INITIAL_SN;
1860 	}
1861 
1862 	ictx->xstorm_ag_context.cdu_reserved =
1863 		CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
1864 				       ISCSI_CONNECTION_TYPE);
1865 	ictx->ustorm_ag_context.cdu_usage =
1866 		CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
1867 				       ISCSI_CONNECTION_TYPE);
1868 	return 0;
1869 
1870 }
1871 
1872 static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
1873 				   u32 num, int *work)
1874 {
1875 	struct iscsi_kwqe_conn_offload1 *req1;
1876 	struct iscsi_kwqe_conn_offload2 *req2;
1877 	struct cnic_local *cp = dev->cnic_priv;
1878 	struct bnx2x *bp = netdev_priv(dev->netdev);
1879 	struct cnic_context *ctx;
1880 	struct iscsi_kcqe kcqe;
1881 	struct kcqe *cqes[1];
1882 	u32 l5_cid;
1883 	int ret = 0;
1884 
1885 	if (num < 2) {
1886 		*work = num;
1887 		return -EINVAL;
1888 	}
1889 
1890 	req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
1891 	req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
1892 	if ((num - 2) < req2->num_additional_wqes) {
1893 		*work = num;
1894 		return -EINVAL;
1895 	}
1896 	*work = 2 + req2->num_additional_wqes;
1897 
1898 	l5_cid = req1->iscsi_conn_id;
1899 	if (l5_cid >= MAX_ISCSI_TBL_SZ)
1900 		return -EINVAL;
1901 
1902 	memset(&kcqe, 0, sizeof(kcqe));
1903 	kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
1904 	kcqe.iscsi_conn_id = l5_cid;
1905 	kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
1906 
1907 	ctx = &cp->ctx_tbl[l5_cid];
1908 	if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
1909 		kcqe.completion_status =
1910 			ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
1911 		goto done;
1912 	}
1913 
1914 	if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
1915 		atomic_dec(&cp->iscsi_conn);
1916 		goto done;
1917 	}
1918 	ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
1919 	if (ret) {
1920 		atomic_dec(&cp->iscsi_conn);
1921 		goto done;
1922 	}
1923 	ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
1924 	if (ret < 0) {
1925 		cnic_free_bnx2x_conn_resc(dev, l5_cid);
1926 		atomic_dec(&cp->iscsi_conn);
1927 		goto done;
1928 	}
1929 
1930 	kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
1931 	kcqe.iscsi_conn_context_id = BNX2X_HW_CID(bp, cp->ctx_tbl[l5_cid].cid);
1932 
1933 done:
1934 	cqes[0] = (struct kcqe *) &kcqe;
1935 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
1936 	return 0;
1937 }
1938 
1939 
1940 static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
1941 {
1942 	struct cnic_local *cp = dev->cnic_priv;
1943 	struct iscsi_kwqe_conn_update *req =
1944 		(struct iscsi_kwqe_conn_update *) kwqe;
1945 	void *data;
1946 	union l5cm_specific_data l5_data;
1947 	u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
1948 	int ret;
1949 
1950 	if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
1951 		return -EINVAL;
1952 
1953 	data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
1954 	if (!data)
1955 		return -ENOMEM;
1956 
1957 	memcpy(data, kwqe, sizeof(struct kwqe));
1958 
1959 	ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
1960 			req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
1961 	return ret;
1962 }
1963 
1964 static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
1965 {
1966 	struct cnic_local *cp = dev->cnic_priv;
1967 	struct bnx2x *bp = netdev_priv(dev->netdev);
1968 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1969 	union l5cm_specific_data l5_data;
1970 	int ret;
1971 	u32 hw_cid;
1972 
1973 	init_waitqueue_head(&ctx->waitq);
1974 	ctx->wait_cond = 0;
1975 	memset(&l5_data, 0, sizeof(l5_data));
1976 	hw_cid = BNX2X_HW_CID(bp, ctx->cid);
1977 
1978 	ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
1979 				  hw_cid, NONE_CONNECTION_TYPE, &l5_data);
1980 
1981 	if (ret == 0) {
1982 		wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
1983 		if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
1984 			return -EBUSY;
1985 	}
1986 
1987 	return 0;
1988 }
1989 
1990 static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
1991 {
1992 	struct cnic_local *cp = dev->cnic_priv;
1993 	struct iscsi_kwqe_conn_destroy *req =
1994 		(struct iscsi_kwqe_conn_destroy *) kwqe;
1995 	u32 l5_cid = req->reserved0;
1996 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
1997 	int ret = 0;
1998 	struct iscsi_kcqe kcqe;
1999 	struct kcqe *cqes[1];
2000 
2001 	if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2002 		goto skip_cfc_delete;
2003 
2004 	if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
2005 		unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
2006 
2007 		if (delta > (2 * HZ))
2008 			delta = 0;
2009 
2010 		set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2011 		queue_delayed_work(cnic_wq, &cp->delete_task, delta);
2012 		goto destroy_reply;
2013 	}
2014 
2015 	ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
2016 
2017 skip_cfc_delete:
2018 	cnic_free_bnx2x_conn_resc(dev, l5_cid);
2019 
2020 	if (!ret) {
2021 		atomic_dec(&cp->iscsi_conn);
2022 		clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2023 	}
2024 
2025 destroy_reply:
2026 	memset(&kcqe, 0, sizeof(kcqe));
2027 	kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
2028 	kcqe.iscsi_conn_id = l5_cid;
2029 	kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
2030 	kcqe.iscsi_conn_context_id = req->context_id;
2031 
2032 	cqes[0] = (struct kcqe *) &kcqe;
2033 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
2034 
2035 	return 0;
2036 }
2037 
2038 static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
2039 				      struct l4_kwq_connect_req1 *kwqe1,
2040 				      struct l4_kwq_connect_req3 *kwqe3,
2041 				      struct l5cm_active_conn_buffer *conn_buf)
2042 {
2043 	struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
2044 	struct l5cm_xstorm_conn_buffer *xstorm_buf =
2045 		&conn_buf->xstorm_conn_buffer;
2046 	struct l5cm_tstorm_conn_buffer *tstorm_buf =
2047 		&conn_buf->tstorm_conn_buffer;
2048 	struct regpair context_addr;
2049 	u32 cid = BNX2X_SW_CID(kwqe1->cid);
2050 	struct in6_addr src_ip, dst_ip;
2051 	int i;
2052 	u32 *addrp;
2053 
2054 	addrp = (u32 *) &conn_addr->local_ip_addr;
2055 	for (i = 0; i < 4; i++, addrp++)
2056 		src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
2057 
2058 	addrp = (u32 *) &conn_addr->remote_ip_addr;
2059 	for (i = 0; i < 4; i++, addrp++)
2060 		dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
2061 
2062 	cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
2063 
2064 	xstorm_buf->context_addr.hi = context_addr.hi;
2065 	xstorm_buf->context_addr.lo = context_addr.lo;
2066 	xstorm_buf->mss = 0xffff;
2067 	xstorm_buf->rcv_buf = kwqe3->rcv_buf;
2068 	if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
2069 		xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
2070 	xstorm_buf->pseudo_header_checksum =
2071 		swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
2072 
2073 	if (kwqe3->ka_timeout) {
2074 		tstorm_buf->ka_enable = 1;
2075 		tstorm_buf->ka_timeout = kwqe3->ka_timeout;
2076 		tstorm_buf->ka_interval = kwqe3->ka_interval;
2077 		tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
2078 	}
2079 	tstorm_buf->max_rt_time = 0xffffffff;
2080 }
2081 
2082 static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
2083 {
2084 	struct bnx2x *bp = netdev_priv(dev->netdev);
2085 	u32 pfid = bp->pfid;
2086 	u8 *mac = dev->mac_addr;
2087 
2088 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2089 		 XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
2090 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2091 		 XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
2092 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2093 		 XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
2094 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2095 		 XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
2096 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2097 		 XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
2098 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
2099 		 XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
2100 
2101 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2102 		 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
2103 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2104 		 TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2105 		 mac[4]);
2106 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2107 		 TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
2108 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2109 		 TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2110 		 mac[2]);
2111 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2112 		 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
2113 	CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
2114 		 TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
2115 		 mac[0]);
2116 }
2117 
2118 static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
2119 			      u32 num, int *work)
2120 {
2121 	struct cnic_local *cp = dev->cnic_priv;
2122 	struct bnx2x *bp = netdev_priv(dev->netdev);
2123 	struct l4_kwq_connect_req1 *kwqe1 =
2124 		(struct l4_kwq_connect_req1 *) wqes[0];
2125 	struct l4_kwq_connect_req3 *kwqe3;
2126 	struct l5cm_active_conn_buffer *conn_buf;
2127 	struct l5cm_conn_addr_params *conn_addr;
2128 	union l5cm_specific_data l5_data;
2129 	u32 l5_cid = kwqe1->pg_cid;
2130 	struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
2131 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
2132 	int ret;
2133 
2134 	if (num < 2) {
2135 		*work = num;
2136 		return -EINVAL;
2137 	}
2138 
2139 	if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
2140 		*work = 3;
2141 	else
2142 		*work = 2;
2143 
2144 	if (num < *work) {
2145 		*work = num;
2146 		return -EINVAL;
2147 	}
2148 
2149 	if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
2150 		netdev_err(dev->netdev, "conn_buf size too big\n");
2151 		return -ENOMEM;
2152 	}
2153 	conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2154 	if (!conn_buf)
2155 		return -ENOMEM;
2156 
2157 	memset(conn_buf, 0, sizeof(*conn_buf));
2158 
2159 	conn_addr = &conn_buf->conn_addr_buf;
2160 	conn_addr->remote_addr_0 = csk->ha[0];
2161 	conn_addr->remote_addr_1 = csk->ha[1];
2162 	conn_addr->remote_addr_2 = csk->ha[2];
2163 	conn_addr->remote_addr_3 = csk->ha[3];
2164 	conn_addr->remote_addr_4 = csk->ha[4];
2165 	conn_addr->remote_addr_5 = csk->ha[5];
2166 
2167 	if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
2168 		struct l4_kwq_connect_req2 *kwqe2 =
2169 			(struct l4_kwq_connect_req2 *) wqes[1];
2170 
2171 		conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
2172 		conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
2173 		conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
2174 
2175 		conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
2176 		conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
2177 		conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
2178 		conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
2179 	}
2180 	kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
2181 
2182 	conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
2183 	conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
2184 	conn_addr->local_tcp_port = kwqe1->src_port;
2185 	conn_addr->remote_tcp_port = kwqe1->dst_port;
2186 
2187 	conn_addr->pmtu = kwqe3->pmtu;
2188 	cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
2189 
2190 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
2191 		  XSTORM_ISCSI_LOCAL_VLAN_OFFSET(bp->pfid), csk->vlan_id);
2192 
2193 	ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
2194 			kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2195 	if (!ret)
2196 		set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2197 
2198 	return ret;
2199 }
2200 
2201 static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
2202 {
2203 	struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
2204 	union l5cm_specific_data l5_data;
2205 	int ret;
2206 
2207 	memset(&l5_data, 0, sizeof(l5_data));
2208 	ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
2209 			req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2210 	return ret;
2211 }
2212 
2213 static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
2214 {
2215 	struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
2216 	union l5cm_specific_data l5_data;
2217 	int ret;
2218 
2219 	memset(&l5_data, 0, sizeof(l5_data));
2220 	ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
2221 			req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
2222 	return ret;
2223 }
2224 static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2225 {
2226 	struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
2227 	struct l4_kcq kcqe;
2228 	struct kcqe *cqes[1];
2229 
2230 	memset(&kcqe, 0, sizeof(kcqe));
2231 	kcqe.pg_host_opaque = req->host_opaque;
2232 	kcqe.pg_cid = req->host_opaque;
2233 	kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
2234 	cqes[0] = (struct kcqe *) &kcqe;
2235 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2236 	return 0;
2237 }
2238 
2239 static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
2240 {
2241 	struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
2242 	struct l4_kcq kcqe;
2243 	struct kcqe *cqes[1];
2244 
2245 	memset(&kcqe, 0, sizeof(kcqe));
2246 	kcqe.pg_host_opaque = req->pg_host_opaque;
2247 	kcqe.pg_cid = req->pg_cid;
2248 	kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
2249 	cqes[0] = (struct kcqe *) &kcqe;
2250 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
2251 	return 0;
2252 }
2253 
2254 static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
2255 {
2256 	struct fcoe_kwqe_stat *req;
2257 	struct fcoe_stat_ramrod_params *fcoe_stat;
2258 	union l5cm_specific_data l5_data;
2259 	struct cnic_local *cp = dev->cnic_priv;
2260 	struct bnx2x *bp = netdev_priv(dev->netdev);
2261 	int ret;
2262 	u32 cid;
2263 
2264 	req = (struct fcoe_kwqe_stat *) kwqe;
2265 	cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
2266 
2267 	fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2268 	if (!fcoe_stat)
2269 		return -ENOMEM;
2270 
2271 	memset(fcoe_stat, 0, sizeof(*fcoe_stat));
2272 	memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
2273 
2274 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
2275 				  FCOE_CONNECTION_TYPE, &l5_data);
2276 	return ret;
2277 }
2278 
2279 static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
2280 				 u32 num, int *work)
2281 {
2282 	int ret;
2283 	struct cnic_local *cp = dev->cnic_priv;
2284 	struct bnx2x *bp = netdev_priv(dev->netdev);
2285 	u32 cid;
2286 	struct fcoe_init_ramrod_params *fcoe_init;
2287 	struct fcoe_kwqe_init1 *req1;
2288 	struct fcoe_kwqe_init2 *req2;
2289 	struct fcoe_kwqe_init3 *req3;
2290 	union l5cm_specific_data l5_data;
2291 
2292 	if (num < 3) {
2293 		*work = num;
2294 		return -EINVAL;
2295 	}
2296 	req1 = (struct fcoe_kwqe_init1 *) wqes[0];
2297 	req2 = (struct fcoe_kwqe_init2 *) wqes[1];
2298 	req3 = (struct fcoe_kwqe_init3 *) wqes[2];
2299 	if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
2300 		*work = 1;
2301 		return -EINVAL;
2302 	}
2303 	if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
2304 		*work = 2;
2305 		return -EINVAL;
2306 	}
2307 
2308 	if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
2309 		netdev_err(dev->netdev, "fcoe_init size too big\n");
2310 		return -ENOMEM;
2311 	}
2312 	fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
2313 	if (!fcoe_init)
2314 		return -ENOMEM;
2315 
2316 	memset(fcoe_init, 0, sizeof(*fcoe_init));
2317 	memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
2318 	memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
2319 	memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
2320 	fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
2321 	fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
2322 	fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
2323 
2324 	fcoe_init->sb_num = cp->status_blk_num;
2325 	fcoe_init->eq_prod = MAX_KCQ_IDX;
2326 	fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
2327 	cp->kcq2.sw_prod_idx = 0;
2328 
2329 	cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
2330 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
2331 				  FCOE_CONNECTION_TYPE, &l5_data);
2332 	*work = 3;
2333 	return ret;
2334 }
2335 
2336 static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
2337 				 u32 num, int *work)
2338 {
2339 	int ret = 0;
2340 	u32 cid = -1, l5_cid;
2341 	struct cnic_local *cp = dev->cnic_priv;
2342 	struct bnx2x *bp = netdev_priv(dev->netdev);
2343 	struct fcoe_kwqe_conn_offload1 *req1;
2344 	struct fcoe_kwqe_conn_offload2 *req2;
2345 	struct fcoe_kwqe_conn_offload3 *req3;
2346 	struct fcoe_kwqe_conn_offload4 *req4;
2347 	struct fcoe_conn_offload_ramrod_params *fcoe_offload;
2348 	struct cnic_context *ctx;
2349 	struct fcoe_context *fctx;
2350 	struct regpair ctx_addr;
2351 	union l5cm_specific_data l5_data;
2352 	struct fcoe_kcqe kcqe;
2353 	struct kcqe *cqes[1];
2354 
2355 	if (num < 4) {
2356 		*work = num;
2357 		return -EINVAL;
2358 	}
2359 	req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
2360 	req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
2361 	req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
2362 	req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
2363 
2364 	*work = 4;
2365 
2366 	l5_cid = req1->fcoe_conn_id;
2367 	if (l5_cid >= dev->max_fcoe_conn)
2368 		goto err_reply;
2369 
2370 	l5_cid += BNX2X_FCOE_L5_CID_BASE;
2371 
2372 	ctx = &cp->ctx_tbl[l5_cid];
2373 	if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2374 		goto err_reply;
2375 
2376 	ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
2377 	if (ret) {
2378 		ret = 0;
2379 		goto err_reply;
2380 	}
2381 	cid = ctx->cid;
2382 
2383 	fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
2384 	if (fctx) {
2385 		u32 hw_cid = BNX2X_HW_CID(bp, cid);
2386 		u32 val;
2387 
2388 		val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
2389 					     FCOE_CONNECTION_TYPE);
2390 		fctx->xstorm_ag_context.cdu_reserved = val;
2391 		val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
2392 					     FCOE_CONNECTION_TYPE);
2393 		fctx->ustorm_ag_context.cdu_usage = val;
2394 	}
2395 	if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
2396 		netdev_err(dev->netdev, "fcoe_offload size too big\n");
2397 		goto err_reply;
2398 	}
2399 	fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2400 	if (!fcoe_offload)
2401 		goto err_reply;
2402 
2403 	memset(fcoe_offload, 0, sizeof(*fcoe_offload));
2404 	memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
2405 	memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
2406 	memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
2407 	memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
2408 
2409 	cid = BNX2X_HW_CID(bp, cid);
2410 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
2411 				  FCOE_CONNECTION_TYPE, &l5_data);
2412 	if (!ret)
2413 		set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
2414 
2415 	return ret;
2416 
2417 err_reply:
2418 	if (cid != -1)
2419 		cnic_free_bnx2x_conn_resc(dev, l5_cid);
2420 
2421 	memset(&kcqe, 0, sizeof(kcqe));
2422 	kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
2423 	kcqe.fcoe_conn_id = req1->fcoe_conn_id;
2424 	kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
2425 
2426 	cqes[0] = (struct kcqe *) &kcqe;
2427 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2428 	return ret;
2429 }
2430 
2431 static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
2432 {
2433 	struct fcoe_kwqe_conn_enable_disable *req;
2434 	struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
2435 	union l5cm_specific_data l5_data;
2436 	int ret;
2437 	u32 cid, l5_cid;
2438 	struct cnic_local *cp = dev->cnic_priv;
2439 
2440 	req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2441 	cid = req->context_id;
2442 	l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
2443 
2444 	if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
2445 		netdev_err(dev->netdev, "fcoe_enable size too big\n");
2446 		return -ENOMEM;
2447 	}
2448 	fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2449 	if (!fcoe_enable)
2450 		return -ENOMEM;
2451 
2452 	memset(fcoe_enable, 0, sizeof(*fcoe_enable));
2453 	memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
2454 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
2455 				  FCOE_CONNECTION_TYPE, &l5_data);
2456 	return ret;
2457 }
2458 
2459 static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
2460 {
2461 	struct fcoe_kwqe_conn_enable_disable *req;
2462 	struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
2463 	union l5cm_specific_data l5_data;
2464 	int ret;
2465 	u32 cid, l5_cid;
2466 	struct cnic_local *cp = dev->cnic_priv;
2467 
2468 	req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2469 	cid = req->context_id;
2470 	l5_cid = req->conn_id;
2471 	if (l5_cid >= dev->max_fcoe_conn)
2472 		return -EINVAL;
2473 
2474 	l5_cid += BNX2X_FCOE_L5_CID_BASE;
2475 
2476 	if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
2477 		netdev_err(dev->netdev, "fcoe_disable size too big\n");
2478 		return -ENOMEM;
2479 	}
2480 	fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
2481 	if (!fcoe_disable)
2482 		return -ENOMEM;
2483 
2484 	memset(fcoe_disable, 0, sizeof(*fcoe_disable));
2485 	memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
2486 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
2487 				  FCOE_CONNECTION_TYPE, &l5_data);
2488 	return ret;
2489 }
2490 
2491 static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2492 {
2493 	struct fcoe_kwqe_conn_destroy *req;
2494 	union l5cm_specific_data l5_data;
2495 	int ret;
2496 	u32 cid, l5_cid;
2497 	struct cnic_local *cp = dev->cnic_priv;
2498 	struct cnic_context *ctx;
2499 	struct fcoe_kcqe kcqe;
2500 	struct kcqe *cqes[1];
2501 
2502 	req = (struct fcoe_kwqe_conn_destroy *) kwqe;
2503 	cid = req->context_id;
2504 	l5_cid = req->conn_id;
2505 	if (l5_cid >= dev->max_fcoe_conn)
2506 		return -EINVAL;
2507 
2508 	l5_cid += BNX2X_FCOE_L5_CID_BASE;
2509 
2510 	ctx = &cp->ctx_tbl[l5_cid];
2511 
2512 	init_waitqueue_head(&ctx->waitq);
2513 	ctx->wait_cond = 0;
2514 
2515 	memset(&kcqe, 0, sizeof(kcqe));
2516 	kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
2517 	memset(&l5_data, 0, sizeof(l5_data));
2518 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
2519 				  FCOE_CONNECTION_TYPE, &l5_data);
2520 	if (ret == 0) {
2521 		wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
2522 		if (ctx->wait_cond)
2523 			kcqe.completion_status = 0;
2524 	}
2525 
2526 	set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
2527 	queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
2528 
2529 	kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
2530 	kcqe.fcoe_conn_id = req->conn_id;
2531 	kcqe.fcoe_conn_context_id = cid;
2532 
2533 	cqes[0] = (struct kcqe *) &kcqe;
2534 	cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
2535 	return ret;
2536 }
2537 
2538 static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
2539 {
2540 	struct cnic_local *cp = dev->cnic_priv;
2541 	u32 i;
2542 
2543 	for (i = start_cid; i < cp->max_cid_space; i++) {
2544 		struct cnic_context *ctx = &cp->ctx_tbl[i];
2545 		int j;
2546 
2547 		while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
2548 			msleep(10);
2549 
2550 		for (j = 0; j < 5; j++) {
2551 			if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2552 				break;
2553 			msleep(20);
2554 		}
2555 
2556 		if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
2557 			netdev_warn(dev->netdev, "CID %x not deleted\n",
2558 				   ctx->cid);
2559 	}
2560 }
2561 
2562 static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
2563 {
2564 	union l5cm_specific_data l5_data;
2565 	struct cnic_local *cp = dev->cnic_priv;
2566 	struct bnx2x *bp = netdev_priv(dev->netdev);
2567 	int ret;
2568 	u32 cid;
2569 
2570 	cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
2571 
2572 	cid = BNX2X_HW_CID(bp, cp->fcoe_init_cid);
2573 
2574 	memset(&l5_data, 0, sizeof(l5_data));
2575 	ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
2576 				  FCOE_CONNECTION_TYPE, &l5_data);
2577 	return ret;
2578 }
2579 
2580 static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
2581 {
2582 	struct cnic_local *cp = dev->cnic_priv;
2583 	struct kcqe kcqe;
2584 	struct kcqe *cqes[1];
2585 	u32 cid;
2586 	u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2587 	u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
2588 	u32 kcqe_op;
2589 	int ulp_type;
2590 
2591 	cid = kwqe->kwqe_info0;
2592 	memset(&kcqe, 0, sizeof(kcqe));
2593 
2594 	if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
2595 		u32 l5_cid = 0;
2596 
2597 		ulp_type = CNIC_ULP_FCOE;
2598 		if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
2599 			struct fcoe_kwqe_conn_enable_disable *req;
2600 
2601 			req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
2602 			kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
2603 			cid = req->context_id;
2604 			l5_cid = req->conn_id;
2605 		} else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
2606 			kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
2607 		} else {
2608 			return;
2609 		}
2610 		kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
2611 		kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
2612 		kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_PARITY_ERROR;
2613 		kcqe.kcqe_info2 = cid;
2614 		kcqe.kcqe_info0 = l5_cid;
2615 
2616 	} else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
2617 		ulp_type = CNIC_ULP_ISCSI;
2618 		if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
2619 			cid = kwqe->kwqe_info1;
2620 
2621 		kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
2622 		kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
2623 		kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_PARITY_ERR;
2624 		kcqe.kcqe_info2 = cid;
2625 		cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
2626 
2627 	} else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
2628 		struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
2629 
2630 		ulp_type = CNIC_ULP_L4;
2631 		if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
2632 			kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
2633 		else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
2634 			kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
2635 		else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
2636 			kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
2637 		else
2638 			return;
2639 
2640 		kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
2641 				    KCQE_FLAGS_LAYER_MASK_L4;
2642 		l4kcqe->status = L4_KCQE_COMPLETION_STATUS_PARITY_ERROR;
2643 		l4kcqe->cid = cid;
2644 		cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
2645 	} else {
2646 		return;
2647 	}
2648 
2649 	cqes[0] = &kcqe;
2650 	cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
2651 }
2652 
2653 static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
2654 					 struct kwqe *wqes[], u32 num_wqes)
2655 {
2656 	int i, work, ret;
2657 	u32 opcode;
2658 	struct kwqe *kwqe;
2659 
2660 	if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2661 		return -EAGAIN;		/* bnx2 is down */
2662 
2663 	for (i = 0; i < num_wqes; ) {
2664 		kwqe = wqes[i];
2665 		opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2666 		work = 1;
2667 
2668 		switch (opcode) {
2669 		case ISCSI_KWQE_OPCODE_INIT1:
2670 			ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
2671 			break;
2672 		case ISCSI_KWQE_OPCODE_INIT2:
2673 			ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
2674 			break;
2675 		case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
2676 			ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
2677 						     num_wqes - i, &work);
2678 			break;
2679 		case ISCSI_KWQE_OPCODE_UPDATE_CONN:
2680 			ret = cnic_bnx2x_iscsi_update(dev, kwqe);
2681 			break;
2682 		case ISCSI_KWQE_OPCODE_DESTROY_CONN:
2683 			ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
2684 			break;
2685 		case L4_KWQE_OPCODE_VALUE_CONNECT1:
2686 			ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
2687 						 &work);
2688 			break;
2689 		case L4_KWQE_OPCODE_VALUE_CLOSE:
2690 			ret = cnic_bnx2x_close(dev, kwqe);
2691 			break;
2692 		case L4_KWQE_OPCODE_VALUE_RESET:
2693 			ret = cnic_bnx2x_reset(dev, kwqe);
2694 			break;
2695 		case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
2696 			ret = cnic_bnx2x_offload_pg(dev, kwqe);
2697 			break;
2698 		case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
2699 			ret = cnic_bnx2x_update_pg(dev, kwqe);
2700 			break;
2701 		case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
2702 			ret = 0;
2703 			break;
2704 		default:
2705 			ret = 0;
2706 			netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2707 				   opcode);
2708 			break;
2709 		}
2710 		if (ret < 0) {
2711 			netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2712 				   opcode);
2713 
2714 			/* Possibly bnx2x parity error, send completion
2715 			 * to ulp drivers with error code to speed up
2716 			 * cleanup and reset recovery.
2717 			 */
2718 			if (ret == -EIO || ret == -EAGAIN)
2719 				cnic_bnx2x_kwqe_err(dev, kwqe);
2720 		}
2721 		i += work;
2722 	}
2723 	return 0;
2724 }
2725 
2726 static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
2727 					struct kwqe *wqes[], u32 num_wqes)
2728 {
2729 	struct bnx2x *bp = netdev_priv(dev->netdev);
2730 	int i, work, ret;
2731 	u32 opcode;
2732 	struct kwqe *kwqe;
2733 
2734 	if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2735 		return -EAGAIN;		/* bnx2 is down */
2736 
2737 	if (!BNX2X_CHIP_IS_E2_PLUS(bp))
2738 		return -EINVAL;
2739 
2740 	for (i = 0; i < num_wqes; ) {
2741 		kwqe = wqes[i];
2742 		opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
2743 		work = 1;
2744 
2745 		switch (opcode) {
2746 		case FCOE_KWQE_OPCODE_INIT1:
2747 			ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
2748 						    num_wqes - i, &work);
2749 			break;
2750 		case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
2751 			ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
2752 						    num_wqes - i, &work);
2753 			break;
2754 		case FCOE_KWQE_OPCODE_ENABLE_CONN:
2755 			ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
2756 			break;
2757 		case FCOE_KWQE_OPCODE_DISABLE_CONN:
2758 			ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
2759 			break;
2760 		case FCOE_KWQE_OPCODE_DESTROY_CONN:
2761 			ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
2762 			break;
2763 		case FCOE_KWQE_OPCODE_DESTROY:
2764 			ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
2765 			break;
2766 		case FCOE_KWQE_OPCODE_STAT:
2767 			ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
2768 			break;
2769 		default:
2770 			ret = 0;
2771 			netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
2772 				   opcode);
2773 			break;
2774 		}
2775 		if (ret < 0) {
2776 			netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
2777 				   opcode);
2778 
2779 			/* Possibly bnx2x parity error, send completion
2780 			 * to ulp drivers with error code to speed up
2781 			 * cleanup and reset recovery.
2782 			 */
2783 			if (ret == -EIO || ret == -EAGAIN)
2784 				cnic_bnx2x_kwqe_err(dev, kwqe);
2785 		}
2786 		i += work;
2787 	}
2788 	return 0;
2789 }
2790 
2791 static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
2792 				   u32 num_wqes)
2793 {
2794 	int ret = -EINVAL;
2795 	u32 layer_code;
2796 
2797 	if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
2798 		return -EAGAIN;		/* bnx2x is down */
2799 
2800 	if (!num_wqes)
2801 		return 0;
2802 
2803 	layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
2804 	switch (layer_code) {
2805 	case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
2806 	case KWQE_FLAGS_LAYER_MASK_L4:
2807 	case KWQE_FLAGS_LAYER_MASK_L2:
2808 		ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
2809 		break;
2810 
2811 	case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
2812 		ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
2813 		break;
2814 	}
2815 	return ret;
2816 }
2817 
2818 static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
2819 {
2820 	if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
2821 		return KCQE_FLAGS_LAYER_MASK_L4;
2822 
2823 	return opflag & KCQE_FLAGS_LAYER_MASK;
2824 }
2825 
2826 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
2827 {
2828 	struct cnic_local *cp = dev->cnic_priv;
2829 	int i, j, comp = 0;
2830 
2831 	i = 0;
2832 	j = 1;
2833 	while (num_cqes) {
2834 		struct cnic_ulp_ops *ulp_ops;
2835 		int ulp_type;
2836 		u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
2837 		u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
2838 
2839 		if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
2840 			comp++;
2841 
2842 		while (j < num_cqes) {
2843 			u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
2844 
2845 			if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
2846 				break;
2847 
2848 			if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
2849 				comp++;
2850 			j++;
2851 		}
2852 
2853 		if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
2854 			ulp_type = CNIC_ULP_RDMA;
2855 		else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
2856 			ulp_type = CNIC_ULP_ISCSI;
2857 		else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
2858 			ulp_type = CNIC_ULP_FCOE;
2859 		else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
2860 			ulp_type = CNIC_ULP_L4;
2861 		else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
2862 			goto end;
2863 		else {
2864 			netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
2865 				   kcqe_op_flag);
2866 			goto end;
2867 		}
2868 
2869 		rcu_read_lock();
2870 		ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
2871 		if (likely(ulp_ops)) {
2872 			ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
2873 						  cp->completed_kcq + i, j);
2874 		}
2875 		rcu_read_unlock();
2876 end:
2877 		num_cqes -= j;
2878 		i += j;
2879 		j = 1;
2880 	}
2881 	if (unlikely(comp))
2882 		cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
2883 }
2884 
2885 static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
2886 {
2887 	struct cnic_local *cp = dev->cnic_priv;
2888 	u16 i, ri, hw_prod, last;
2889 	struct kcqe *kcqe;
2890 	int kcqe_cnt = 0, last_cnt = 0;
2891 
2892 	i = ri = last = info->sw_prod_idx;
2893 	ri &= MAX_KCQ_IDX;
2894 	hw_prod = *info->hw_prod_idx_ptr;
2895 	hw_prod = info->hw_idx(hw_prod);
2896 
2897 	while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
2898 		kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
2899 		cp->completed_kcq[kcqe_cnt++] = kcqe;
2900 		i = info->next_idx(i);
2901 		ri = i & MAX_KCQ_IDX;
2902 		if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
2903 			last_cnt = kcqe_cnt;
2904 			last = i;
2905 		}
2906 	}
2907 
2908 	info->sw_prod_idx = last;
2909 	return last_cnt;
2910 }
2911 
2912 static int cnic_l2_completion(struct cnic_local *cp)
2913 {
2914 	u16 hw_cons, sw_cons;
2915 	struct cnic_uio_dev *udev = cp->udev;
2916 	union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
2917 					(udev->l2_ring + (2 * CNIC_PAGE_SIZE));
2918 	u32 cmd;
2919 	int comp = 0;
2920 
2921 	if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
2922 		return 0;
2923 
2924 	hw_cons = *cp->rx_cons_ptr;
2925 	if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
2926 		hw_cons++;
2927 
2928 	sw_cons = cp->rx_cons;
2929 	while (sw_cons != hw_cons) {
2930 		u8 cqe_fp_flags;
2931 
2932 		cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
2933 		cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2934 		if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
2935 			cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
2936 			cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
2937 			if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
2938 			    cmd == RAMROD_CMD_ID_ETH_HALT)
2939 				comp++;
2940 		}
2941 		sw_cons = BNX2X_NEXT_RCQE(sw_cons);
2942 	}
2943 	return comp;
2944 }
2945 
2946 static void cnic_chk_pkt_rings(struct cnic_local *cp)
2947 {
2948 	u16 rx_cons, tx_cons;
2949 	int comp = 0;
2950 
2951 	if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
2952 		return;
2953 
2954 	rx_cons = *cp->rx_cons_ptr;
2955 	tx_cons = *cp->tx_cons_ptr;
2956 	if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
2957 		if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
2958 			comp = cnic_l2_completion(cp);
2959 
2960 		cp->tx_cons = tx_cons;
2961 		cp->rx_cons = rx_cons;
2962 
2963 		if (cp->udev)
2964 			uio_event_notify(&cp->udev->cnic_uinfo);
2965 	}
2966 	if (comp)
2967 		clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
2968 }
2969 
2970 static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
2971 {
2972 	struct cnic_local *cp = dev->cnic_priv;
2973 	u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
2974 	int kcqe_cnt;
2975 
2976 	/* status block index must be read before reading other fields */
2977 	rmb();
2978 	cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2979 
2980 	while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
2981 
2982 		service_kcqes(dev, kcqe_cnt);
2983 
2984 		/* Tell compiler that status_blk fields can change. */
2985 		barrier();
2986 		status_idx = (u16) *cp->kcq1.status_idx_ptr;
2987 		/* status block index must be read first */
2988 		rmb();
2989 		cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
2990 	}
2991 
2992 	CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
2993 
2994 	cnic_chk_pkt_rings(cp);
2995 
2996 	return status_idx;
2997 }
2998 
2999 static int cnic_service_bnx2(void *data, void *status_blk)
3000 {
3001 	struct cnic_dev *dev = data;
3002 
3003 	if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
3004 		struct status_block *sblk = status_blk;
3005 
3006 		return sblk->status_idx;
3007 	}
3008 
3009 	return cnic_service_bnx2_queues(dev);
3010 }
3011 
3012 static void cnic_service_bnx2_msix(struct tasklet_struct *t)
3013 {
3014 	struct cnic_local *cp = from_tasklet(cp, t, cnic_irq_task);
3015 	struct cnic_dev *dev = cp->dev;
3016 
3017 	cp->last_status_idx = cnic_service_bnx2_queues(dev);
3018 
3019 	CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
3020 		BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
3021 }
3022 
3023 static void cnic_doirq(struct cnic_dev *dev)
3024 {
3025 	struct cnic_local *cp = dev->cnic_priv;
3026 
3027 	if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
3028 		u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
3029 
3030 		prefetch(cp->status_blk.gen);
3031 		prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
3032 
3033 		tasklet_schedule(&cp->cnic_irq_task);
3034 	}
3035 }
3036 
3037 static irqreturn_t cnic_irq(int irq, void *dev_instance)
3038 {
3039 	struct cnic_dev *dev = dev_instance;
3040 	struct cnic_local *cp = dev->cnic_priv;
3041 
3042 	if (cp->ack_int)
3043 		cp->ack_int(dev);
3044 
3045 	cnic_doirq(dev);
3046 
3047 	return IRQ_HANDLED;
3048 }
3049 
3050 static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
3051 				      u16 index, u8 op, u8 update)
3052 {
3053 	struct bnx2x *bp = netdev_priv(dev->netdev);
3054 	u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp) * 32 +
3055 		       COMMAND_REG_INT_ACK);
3056 	struct igu_ack_register igu_ack;
3057 
3058 	igu_ack.status_block_index = index;
3059 	igu_ack.sb_id_and_flags =
3060 			((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
3061 			 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
3062 			 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
3063 			 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
3064 
3065 	CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
3066 }
3067 
3068 static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
3069 			    u16 index, u8 op, u8 update)
3070 {
3071 	struct igu_regular cmd_data;
3072 	u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
3073 
3074 	cmd_data.sb_id_and_flags =
3075 		(index << IGU_REGULAR_SB_INDEX_SHIFT) |
3076 		(segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
3077 		(update << IGU_REGULAR_BUPDATE_SHIFT) |
3078 		(op << IGU_REGULAR_ENABLE_INT_SHIFT);
3079 
3080 
3081 	CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
3082 }
3083 
3084 static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
3085 {
3086 	struct cnic_local *cp = dev->cnic_priv;
3087 
3088 	cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
3089 			   IGU_INT_DISABLE, 0);
3090 }
3091 
3092 static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
3093 {
3094 	struct cnic_local *cp = dev->cnic_priv;
3095 
3096 	cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
3097 			IGU_INT_DISABLE, 0);
3098 }
3099 
3100 static void cnic_arm_bnx2x_msix(struct cnic_dev *dev, u32 idx)
3101 {
3102 	struct cnic_local *cp = dev->cnic_priv;
3103 
3104 	cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, idx,
3105 			   IGU_INT_ENABLE, 1);
3106 }
3107 
3108 static void cnic_arm_bnx2x_e2_msix(struct cnic_dev *dev, u32 idx)
3109 {
3110 	struct cnic_local *cp = dev->cnic_priv;
3111 
3112 	cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, idx,
3113 			IGU_INT_ENABLE, 1);
3114 }
3115 
3116 static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
3117 {
3118 	u32 last_status = *info->status_idx_ptr;
3119 	int kcqe_cnt;
3120 
3121 	/* status block index must be read before reading the KCQ */
3122 	rmb();
3123 	while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
3124 
3125 		service_kcqes(dev, kcqe_cnt);
3126 
3127 		/* Tell compiler that sblk fields can change. */
3128 		barrier();
3129 
3130 		last_status = *info->status_idx_ptr;
3131 		/* status block index must be read before reading the KCQ */
3132 		rmb();
3133 	}
3134 	return last_status;
3135 }
3136 
3137 static void cnic_service_bnx2x_bh(struct tasklet_struct *t)
3138 {
3139 	struct cnic_local *cp = from_tasklet(cp, t, cnic_irq_task);
3140 	struct cnic_dev *dev = cp->dev;
3141 	struct bnx2x *bp = netdev_priv(dev->netdev);
3142 	u32 status_idx, new_status_idx;
3143 
3144 	if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
3145 		return;
3146 
3147 	while (1) {
3148 		status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
3149 
3150 		CNIC_WR16(dev, cp->kcq1.io_addr,
3151 			  cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
3152 
3153 		if (!CNIC_SUPPORTS_FCOE(bp)) {
3154 			cp->arm_int(dev, status_idx);
3155 			break;
3156 		}
3157 
3158 		new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
3159 
3160 		if (new_status_idx != status_idx)
3161 			continue;
3162 
3163 		CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
3164 			  MAX_KCQ_IDX);
3165 
3166 		cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
3167 				status_idx, IGU_INT_ENABLE, 1);
3168 
3169 		break;
3170 	}
3171 }
3172 
3173 static int cnic_service_bnx2x(void *data, void *status_blk)
3174 {
3175 	struct cnic_dev *dev = data;
3176 	struct cnic_local *cp = dev->cnic_priv;
3177 
3178 	if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
3179 		cnic_doirq(dev);
3180 
3181 	cnic_chk_pkt_rings(cp);
3182 
3183 	return 0;
3184 }
3185 
3186 static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
3187 {
3188 	struct cnic_ulp_ops *ulp_ops;
3189 
3190 	if (if_type == CNIC_ULP_ISCSI)
3191 		cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
3192 
3193 	mutex_lock(&cnic_lock);
3194 	ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
3195 					    lockdep_is_held(&cnic_lock));
3196 	if (!ulp_ops) {
3197 		mutex_unlock(&cnic_lock);
3198 		return;
3199 	}
3200 	set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3201 	mutex_unlock(&cnic_lock);
3202 
3203 	if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
3204 		ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
3205 
3206 	clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3207 }
3208 
3209 static void cnic_ulp_stop(struct cnic_dev *dev)
3210 {
3211 	struct cnic_local *cp = dev->cnic_priv;
3212 	int if_type;
3213 
3214 	for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
3215 		cnic_ulp_stop_one(cp, if_type);
3216 }
3217 
3218 static void cnic_ulp_start(struct cnic_dev *dev)
3219 {
3220 	struct cnic_local *cp = dev->cnic_priv;
3221 	int if_type;
3222 
3223 	for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
3224 		struct cnic_ulp_ops *ulp_ops;
3225 
3226 		mutex_lock(&cnic_lock);
3227 		ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
3228 						    lockdep_is_held(&cnic_lock));
3229 		if (!ulp_ops || !ulp_ops->cnic_start) {
3230 			mutex_unlock(&cnic_lock);
3231 			continue;
3232 		}
3233 		set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3234 		mutex_unlock(&cnic_lock);
3235 
3236 		if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
3237 			ulp_ops->cnic_start(cp->ulp_handle[if_type]);
3238 
3239 		clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
3240 	}
3241 }
3242 
3243 static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
3244 {
3245 	struct cnic_local *cp = dev->cnic_priv;
3246 	struct cnic_ulp_ops *ulp_ops;
3247 	int rc;
3248 
3249 	mutex_lock(&cnic_lock);
3250 	ulp_ops = rcu_dereference_protected(cp->ulp_ops[ulp_type],
3251 					    lockdep_is_held(&cnic_lock));
3252 	if (ulp_ops && ulp_ops->cnic_get_stats)
3253 		rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
3254 	else
3255 		rc = -ENODEV;
3256 	mutex_unlock(&cnic_lock);
3257 	return rc;
3258 }
3259 
3260 static int cnic_ctl(void *data, struct cnic_ctl_info *info)
3261 {
3262 	struct cnic_dev *dev = data;
3263 	int ulp_type = CNIC_ULP_ISCSI;
3264 
3265 	switch (info->cmd) {
3266 	case CNIC_CTL_STOP_CMD:
3267 		cnic_hold(dev);
3268 
3269 		cnic_ulp_stop(dev);
3270 		cnic_stop_hw(dev);
3271 
3272 		cnic_put(dev);
3273 		break;
3274 	case CNIC_CTL_START_CMD:
3275 		cnic_hold(dev);
3276 
3277 		if (!cnic_start_hw(dev))
3278 			cnic_ulp_start(dev);
3279 
3280 		cnic_put(dev);
3281 		break;
3282 	case CNIC_CTL_STOP_ISCSI_CMD: {
3283 		struct cnic_local *cp = dev->cnic_priv;
3284 		set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
3285 		queue_delayed_work(cnic_wq, &cp->delete_task, 0);
3286 		break;
3287 	}
3288 	case CNIC_CTL_COMPLETION_CMD: {
3289 		struct cnic_ctl_completion *comp = &info->data.comp;
3290 		u32 cid = BNX2X_SW_CID(comp->cid);
3291 		u32 l5_cid;
3292 		struct cnic_local *cp = dev->cnic_priv;
3293 
3294 		if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
3295 			break;
3296 
3297 		if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
3298 			struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3299 
3300 			if (unlikely(comp->error)) {
3301 				set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
3302 				netdev_err(dev->netdev,
3303 					   "CID %x CFC delete comp error %x\n",
3304 					   cid, comp->error);
3305 			}
3306 
3307 			ctx->wait_cond = 1;
3308 			wake_up(&ctx->waitq);
3309 		}
3310 		break;
3311 	}
3312 	case CNIC_CTL_FCOE_STATS_GET_CMD:
3313 		ulp_type = CNIC_ULP_FCOE;
3314 		fallthrough;
3315 	case CNIC_CTL_ISCSI_STATS_GET_CMD:
3316 		cnic_hold(dev);
3317 		cnic_copy_ulp_stats(dev, ulp_type);
3318 		cnic_put(dev);
3319 		break;
3320 
3321 	default:
3322 		return -EINVAL;
3323 	}
3324 	return 0;
3325 }
3326 
3327 static void cnic_ulp_init(struct cnic_dev *dev)
3328 {
3329 	int i;
3330 	struct cnic_local *cp = dev->cnic_priv;
3331 
3332 	for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3333 		struct cnic_ulp_ops *ulp_ops;
3334 
3335 		mutex_lock(&cnic_lock);
3336 		ulp_ops = cnic_ulp_tbl_prot(i);
3337 		if (!ulp_ops || !ulp_ops->cnic_init) {
3338 			mutex_unlock(&cnic_lock);
3339 			continue;
3340 		}
3341 		ulp_get(ulp_ops);
3342 		mutex_unlock(&cnic_lock);
3343 
3344 		if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3345 			ulp_ops->cnic_init(dev);
3346 
3347 		ulp_put(ulp_ops);
3348 	}
3349 }
3350 
3351 static void cnic_ulp_exit(struct cnic_dev *dev)
3352 {
3353 	int i;
3354 	struct cnic_local *cp = dev->cnic_priv;
3355 
3356 	for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
3357 		struct cnic_ulp_ops *ulp_ops;
3358 
3359 		mutex_lock(&cnic_lock);
3360 		ulp_ops = cnic_ulp_tbl_prot(i);
3361 		if (!ulp_ops || !ulp_ops->cnic_exit) {
3362 			mutex_unlock(&cnic_lock);
3363 			continue;
3364 		}
3365 		ulp_get(ulp_ops);
3366 		mutex_unlock(&cnic_lock);
3367 
3368 		if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
3369 			ulp_ops->cnic_exit(dev);
3370 
3371 		ulp_put(ulp_ops);
3372 	}
3373 }
3374 
3375 static int cnic_cm_offload_pg(struct cnic_sock *csk)
3376 {
3377 	struct cnic_dev *dev = csk->dev;
3378 	struct l4_kwq_offload_pg *l4kwqe;
3379 	struct kwqe *wqes[1];
3380 
3381 	l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
3382 	memset(l4kwqe, 0, sizeof(*l4kwqe));
3383 	wqes[0] = (struct kwqe *) l4kwqe;
3384 
3385 	l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
3386 	l4kwqe->flags =
3387 		L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
3388 	l4kwqe->l2hdr_nbytes = ETH_HLEN;
3389 
3390 	l4kwqe->da0 = csk->ha[0];
3391 	l4kwqe->da1 = csk->ha[1];
3392 	l4kwqe->da2 = csk->ha[2];
3393 	l4kwqe->da3 = csk->ha[3];
3394 	l4kwqe->da4 = csk->ha[4];
3395 	l4kwqe->da5 = csk->ha[5];
3396 
3397 	l4kwqe->sa0 = dev->mac_addr[0];
3398 	l4kwqe->sa1 = dev->mac_addr[1];
3399 	l4kwqe->sa2 = dev->mac_addr[2];
3400 	l4kwqe->sa3 = dev->mac_addr[3];
3401 	l4kwqe->sa4 = dev->mac_addr[4];
3402 	l4kwqe->sa5 = dev->mac_addr[5];
3403 
3404 	l4kwqe->etype = ETH_P_IP;
3405 	l4kwqe->ipid_start = DEF_IPID_START;
3406 	l4kwqe->host_opaque = csk->l5_cid;
3407 
3408 	if (csk->vlan_id) {
3409 		l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
3410 		l4kwqe->vlan_tag = csk->vlan_id;
3411 		l4kwqe->l2hdr_nbytes += 4;
3412 	}
3413 
3414 	return dev->submit_kwqes(dev, wqes, 1);
3415 }
3416 
3417 static int cnic_cm_update_pg(struct cnic_sock *csk)
3418 {
3419 	struct cnic_dev *dev = csk->dev;
3420 	struct l4_kwq_update_pg *l4kwqe;
3421 	struct kwqe *wqes[1];
3422 
3423 	l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
3424 	memset(l4kwqe, 0, sizeof(*l4kwqe));
3425 	wqes[0] = (struct kwqe *) l4kwqe;
3426 
3427 	l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
3428 	l4kwqe->flags =
3429 		L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
3430 	l4kwqe->pg_cid = csk->pg_cid;
3431 
3432 	l4kwqe->da0 = csk->ha[0];
3433 	l4kwqe->da1 = csk->ha[1];
3434 	l4kwqe->da2 = csk->ha[2];
3435 	l4kwqe->da3 = csk->ha[3];
3436 	l4kwqe->da4 = csk->ha[4];
3437 	l4kwqe->da5 = csk->ha[5];
3438 
3439 	l4kwqe->pg_host_opaque = csk->l5_cid;
3440 	l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
3441 
3442 	return dev->submit_kwqes(dev, wqes, 1);
3443 }
3444 
3445 static int cnic_cm_upload_pg(struct cnic_sock *csk)
3446 {
3447 	struct cnic_dev *dev = csk->dev;
3448 	struct l4_kwq_upload *l4kwqe;
3449 	struct kwqe *wqes[1];
3450 
3451 	l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
3452 	memset(l4kwqe, 0, sizeof(*l4kwqe));
3453 	wqes[0] = (struct kwqe *) l4kwqe;
3454 
3455 	l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
3456 	l4kwqe->flags =
3457 		L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
3458 	l4kwqe->cid = csk->pg_cid;
3459 
3460 	return dev->submit_kwqes(dev, wqes, 1);
3461 }
3462 
3463 static int cnic_cm_conn_req(struct cnic_sock *csk)
3464 {
3465 	struct cnic_dev *dev = csk->dev;
3466 	struct l4_kwq_connect_req1 *l4kwqe1;
3467 	struct l4_kwq_connect_req2 *l4kwqe2;
3468 	struct l4_kwq_connect_req3 *l4kwqe3;
3469 	struct kwqe *wqes[3];
3470 	u8 tcp_flags = 0;
3471 	int num_wqes = 2;
3472 
3473 	l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
3474 	l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
3475 	l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
3476 	memset(l4kwqe1, 0, sizeof(*l4kwqe1));
3477 	memset(l4kwqe2, 0, sizeof(*l4kwqe2));
3478 	memset(l4kwqe3, 0, sizeof(*l4kwqe3));
3479 
3480 	l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
3481 	l4kwqe3->flags =
3482 		L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
3483 	l4kwqe3->ka_timeout = csk->ka_timeout;
3484 	l4kwqe3->ka_interval = csk->ka_interval;
3485 	l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
3486 	l4kwqe3->tos = csk->tos;
3487 	l4kwqe3->ttl = csk->ttl;
3488 	l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
3489 	l4kwqe3->pmtu = csk->mtu;
3490 	l4kwqe3->rcv_buf = csk->rcv_buf;
3491 	l4kwqe3->snd_buf = csk->snd_buf;
3492 	l4kwqe3->seed = csk->seed;
3493 
3494 	wqes[0] = (struct kwqe *) l4kwqe1;
3495 	if (test_bit(SK_F_IPV6, &csk->flags)) {
3496 		wqes[1] = (struct kwqe *) l4kwqe2;
3497 		wqes[2] = (struct kwqe *) l4kwqe3;
3498 		num_wqes = 3;
3499 
3500 		l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
3501 		l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
3502 		l4kwqe2->flags =
3503 			L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
3504 			L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
3505 		l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
3506 		l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
3507 		l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
3508 		l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
3509 		l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
3510 		l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
3511 		l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
3512 			       sizeof(struct tcphdr);
3513 	} else {
3514 		wqes[1] = (struct kwqe *) l4kwqe3;
3515 		l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
3516 			       sizeof(struct tcphdr);
3517 	}
3518 
3519 	l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
3520 	l4kwqe1->flags =
3521 		(L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
3522 		 L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
3523 	l4kwqe1->cid = csk->cid;
3524 	l4kwqe1->pg_cid = csk->pg_cid;
3525 	l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
3526 	l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
3527 	l4kwqe1->src_port = be16_to_cpu(csk->src_port);
3528 	l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
3529 	if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
3530 		tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
3531 	if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
3532 		tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
3533 	if (csk->tcp_flags & SK_TCP_NAGLE)
3534 		tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
3535 	if (csk->tcp_flags & SK_TCP_TIMESTAMP)
3536 		tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
3537 	if (csk->tcp_flags & SK_TCP_SACK)
3538 		tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
3539 	if (csk->tcp_flags & SK_TCP_SEG_SCALING)
3540 		tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
3541 
3542 	l4kwqe1->tcp_flags = tcp_flags;
3543 
3544 	return dev->submit_kwqes(dev, wqes, num_wqes);
3545 }
3546 
3547 static int cnic_cm_close_req(struct cnic_sock *csk)
3548 {
3549 	struct cnic_dev *dev = csk->dev;
3550 	struct l4_kwq_close_req *l4kwqe;
3551 	struct kwqe *wqes[1];
3552 
3553 	l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
3554 	memset(l4kwqe, 0, sizeof(*l4kwqe));
3555 	wqes[0] = (struct kwqe *) l4kwqe;
3556 
3557 	l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
3558 	l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
3559 	l4kwqe->cid = csk->cid;
3560 
3561 	return dev->submit_kwqes(dev, wqes, 1);
3562 }
3563 
3564 static int cnic_cm_abort_req(struct cnic_sock *csk)
3565 {
3566 	struct cnic_dev *dev = csk->dev;
3567 	struct l4_kwq_reset_req *l4kwqe;
3568 	struct kwqe *wqes[1];
3569 
3570 	l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
3571 	memset(l4kwqe, 0, sizeof(*l4kwqe));
3572 	wqes[0] = (struct kwqe *) l4kwqe;
3573 
3574 	l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
3575 	l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
3576 	l4kwqe->cid = csk->cid;
3577 
3578 	return dev->submit_kwqes(dev, wqes, 1);
3579 }
3580 
3581 static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
3582 			  u32 l5_cid, struct cnic_sock **csk, void *context)
3583 {
3584 	struct cnic_local *cp = dev->cnic_priv;
3585 	struct cnic_sock *csk1;
3586 
3587 	if (l5_cid >= MAX_CM_SK_TBL_SZ)
3588 		return -EINVAL;
3589 
3590 	if (cp->ctx_tbl) {
3591 		struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3592 
3593 		if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
3594 			return -EAGAIN;
3595 	}
3596 
3597 	csk1 = &cp->csk_tbl[l5_cid];
3598 	if (atomic_read(&csk1->ref_count))
3599 		return -EAGAIN;
3600 
3601 	if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
3602 		return -EBUSY;
3603 
3604 	csk1->dev = dev;
3605 	csk1->cid = cid;
3606 	csk1->l5_cid = l5_cid;
3607 	csk1->ulp_type = ulp_type;
3608 	csk1->context = context;
3609 
3610 	csk1->ka_timeout = DEF_KA_TIMEOUT;
3611 	csk1->ka_interval = DEF_KA_INTERVAL;
3612 	csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
3613 	csk1->tos = DEF_TOS;
3614 	csk1->ttl = DEF_TTL;
3615 	csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
3616 	csk1->rcv_buf = DEF_RCV_BUF;
3617 	csk1->snd_buf = DEF_SND_BUF;
3618 	csk1->seed = DEF_SEED;
3619 	csk1->tcp_flags = 0;
3620 
3621 	*csk = csk1;
3622 	return 0;
3623 }
3624 
3625 static void cnic_cm_cleanup(struct cnic_sock *csk)
3626 {
3627 	if (csk->src_port) {
3628 		struct cnic_dev *dev = csk->dev;
3629 		struct cnic_local *cp = dev->cnic_priv;
3630 
3631 		cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
3632 		csk->src_port = 0;
3633 	}
3634 }
3635 
3636 static void cnic_close_conn(struct cnic_sock *csk)
3637 {
3638 	if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
3639 		cnic_cm_upload_pg(csk);
3640 		clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3641 	}
3642 	cnic_cm_cleanup(csk);
3643 }
3644 
3645 static int cnic_cm_destroy(struct cnic_sock *csk)
3646 {
3647 	if (!cnic_in_use(csk))
3648 		return -EINVAL;
3649 
3650 	csk_hold(csk);
3651 	clear_bit(SK_F_INUSE, &csk->flags);
3652 	smp_mb__after_atomic();
3653 	while (atomic_read(&csk->ref_count) != 1)
3654 		msleep(1);
3655 	cnic_cm_cleanup(csk);
3656 
3657 	csk->flags = 0;
3658 	csk_put(csk);
3659 	return 0;
3660 }
3661 
3662 static inline u16 cnic_get_vlan(struct net_device *dev,
3663 				struct net_device **vlan_dev)
3664 {
3665 	if (is_vlan_dev(dev)) {
3666 		*vlan_dev = vlan_dev_real_dev(dev);
3667 		return vlan_dev_vlan_id(dev);
3668 	}
3669 	*vlan_dev = dev;
3670 	return 0;
3671 }
3672 
3673 static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
3674 			     struct dst_entry **dst)
3675 {
3676 #if defined(CONFIG_INET)
3677 	struct rtable *rt;
3678 
3679 	rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
3680 	if (!IS_ERR(rt)) {
3681 		*dst = &rt->dst;
3682 		return 0;
3683 	}
3684 	return PTR_ERR(rt);
3685 #else
3686 	return -ENETUNREACH;
3687 #endif
3688 }
3689 
3690 static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
3691 			     struct dst_entry **dst)
3692 {
3693 #if IS_ENABLED(CONFIG_IPV6)
3694 	struct flowi6 fl6;
3695 
3696 	memset(&fl6, 0, sizeof(fl6));
3697 	fl6.daddr = dst_addr->sin6_addr;
3698 	if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
3699 		fl6.flowi6_oif = dst_addr->sin6_scope_id;
3700 
3701 	*dst = ip6_route_output(&init_net, NULL, &fl6);
3702 	if ((*dst)->error) {
3703 		dst_release(*dst);
3704 		*dst = NULL;
3705 		return -ENETUNREACH;
3706 	} else
3707 		return 0;
3708 #endif
3709 
3710 	return -ENETUNREACH;
3711 }
3712 
3713 static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
3714 					   int ulp_type)
3715 {
3716 	struct cnic_dev *dev = NULL;
3717 	struct dst_entry *dst;
3718 	struct net_device *netdev = NULL;
3719 	int err = -ENETUNREACH;
3720 
3721 	if (dst_addr->sin_family == AF_INET)
3722 		err = cnic_get_v4_route(dst_addr, &dst);
3723 	else if (dst_addr->sin_family == AF_INET6) {
3724 		struct sockaddr_in6 *dst_addr6 =
3725 			(struct sockaddr_in6 *) dst_addr;
3726 
3727 		err = cnic_get_v6_route(dst_addr6, &dst);
3728 	} else
3729 		return NULL;
3730 
3731 	if (err)
3732 		return NULL;
3733 
3734 	if (!dst->dev)
3735 		goto done;
3736 
3737 	cnic_get_vlan(dst->dev, &netdev);
3738 
3739 	dev = cnic_from_netdev(netdev);
3740 
3741 done:
3742 	dst_release(dst);
3743 	if (dev)
3744 		cnic_put(dev);
3745 	return dev;
3746 }
3747 
3748 static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3749 {
3750 	struct cnic_dev *dev = csk->dev;
3751 	struct cnic_local *cp = dev->cnic_priv;
3752 
3753 	return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
3754 }
3755 
3756 static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3757 {
3758 	struct cnic_dev *dev = csk->dev;
3759 	struct cnic_local *cp = dev->cnic_priv;
3760 	int is_v6, rc = 0;
3761 	struct dst_entry *dst = NULL;
3762 	struct net_device *realdev;
3763 	__be16 local_port;
3764 	u32 port_id;
3765 
3766 	if (saddr->local.v6.sin6_family == AF_INET6 &&
3767 	    saddr->remote.v6.sin6_family == AF_INET6)
3768 		is_v6 = 1;
3769 	else if (saddr->local.v4.sin_family == AF_INET &&
3770 		 saddr->remote.v4.sin_family == AF_INET)
3771 		is_v6 = 0;
3772 	else
3773 		return -EINVAL;
3774 
3775 	clear_bit(SK_F_IPV6, &csk->flags);
3776 
3777 	if (is_v6) {
3778 		set_bit(SK_F_IPV6, &csk->flags);
3779 		cnic_get_v6_route(&saddr->remote.v6, &dst);
3780 
3781 		memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
3782 		       sizeof(struct in6_addr));
3783 		csk->dst_port = saddr->remote.v6.sin6_port;
3784 		local_port = saddr->local.v6.sin6_port;
3785 
3786 	} else {
3787 		cnic_get_v4_route(&saddr->remote.v4, &dst);
3788 
3789 		csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
3790 		csk->dst_port = saddr->remote.v4.sin_port;
3791 		local_port = saddr->local.v4.sin_port;
3792 	}
3793 
3794 	csk->vlan_id = 0;
3795 	csk->mtu = dev->netdev->mtu;
3796 	if (dst && dst->dev) {
3797 		u16 vlan = cnic_get_vlan(dst->dev, &realdev);
3798 		if (realdev == dev->netdev) {
3799 			csk->vlan_id = vlan;
3800 			csk->mtu = dst_mtu(dst);
3801 		}
3802 	}
3803 
3804 	port_id = be16_to_cpu(local_port);
3805 	if (port_id >= CNIC_LOCAL_PORT_MIN &&
3806 	    port_id < CNIC_LOCAL_PORT_MAX) {
3807 		if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
3808 			port_id = 0;
3809 	} else
3810 		port_id = 0;
3811 
3812 	if (!port_id) {
3813 		port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
3814 		if (port_id == -1) {
3815 			rc = -ENOMEM;
3816 			goto err_out;
3817 		}
3818 		local_port = cpu_to_be16(port_id);
3819 	}
3820 	csk->src_port = local_port;
3821 
3822 err_out:
3823 	dst_release(dst);
3824 	return rc;
3825 }
3826 
3827 static void cnic_init_csk_state(struct cnic_sock *csk)
3828 {
3829 	csk->state = 0;
3830 	clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3831 	clear_bit(SK_F_CLOSING, &csk->flags);
3832 }
3833 
3834 static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
3835 {
3836 	struct cnic_local *cp = csk->dev->cnic_priv;
3837 	int err = 0;
3838 
3839 	if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
3840 		return -EOPNOTSUPP;
3841 
3842 	if (!cnic_in_use(csk))
3843 		return -EINVAL;
3844 
3845 	if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
3846 		return -EINVAL;
3847 
3848 	cnic_init_csk_state(csk);
3849 
3850 	err = cnic_get_route(csk, saddr);
3851 	if (err)
3852 		goto err_out;
3853 
3854 	err = cnic_resolve_addr(csk, saddr);
3855 	if (!err)
3856 		return 0;
3857 
3858 err_out:
3859 	clear_bit(SK_F_CONNECT_START, &csk->flags);
3860 	return err;
3861 }
3862 
3863 static int cnic_cm_abort(struct cnic_sock *csk)
3864 {
3865 	struct cnic_local *cp = csk->dev->cnic_priv;
3866 	u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
3867 
3868 	if (!cnic_in_use(csk))
3869 		return -EINVAL;
3870 
3871 	if (cnic_abort_prep(csk))
3872 		return cnic_cm_abort_req(csk);
3873 
3874 	/* Getting here means that we haven't started connect, or
3875 	 * connect was not successful, or it has been reset by the target.
3876 	 */
3877 
3878 	cp->close_conn(csk, opcode);
3879 	if (csk->state != opcode) {
3880 		/* Wait for remote reset sequence to complete */
3881 		while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3882 			msleep(1);
3883 
3884 		return -EALREADY;
3885 	}
3886 
3887 	return 0;
3888 }
3889 
3890 static int cnic_cm_close(struct cnic_sock *csk)
3891 {
3892 	if (!cnic_in_use(csk))
3893 		return -EINVAL;
3894 
3895 	if (cnic_close_prep(csk)) {
3896 		csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
3897 		return cnic_cm_close_req(csk);
3898 	} else {
3899 		/* Wait for remote reset sequence to complete */
3900 		while (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3901 			msleep(1);
3902 
3903 		return -EALREADY;
3904 	}
3905 	return 0;
3906 }
3907 
3908 static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
3909 			   u8 opcode)
3910 {
3911 	struct cnic_ulp_ops *ulp_ops;
3912 	int ulp_type = csk->ulp_type;
3913 
3914 	rcu_read_lock();
3915 	ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
3916 	if (ulp_ops) {
3917 		if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
3918 			ulp_ops->cm_connect_complete(csk);
3919 		else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
3920 			ulp_ops->cm_close_complete(csk);
3921 		else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
3922 			ulp_ops->cm_remote_abort(csk);
3923 		else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
3924 			ulp_ops->cm_abort_complete(csk);
3925 		else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
3926 			ulp_ops->cm_remote_close(csk);
3927 	}
3928 	rcu_read_unlock();
3929 }
3930 
3931 static int cnic_cm_set_pg(struct cnic_sock *csk)
3932 {
3933 	if (cnic_offld_prep(csk)) {
3934 		if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
3935 			cnic_cm_update_pg(csk);
3936 		else
3937 			cnic_cm_offload_pg(csk);
3938 	}
3939 	return 0;
3940 }
3941 
3942 static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
3943 {
3944 	struct cnic_local *cp = dev->cnic_priv;
3945 	u32 l5_cid = kcqe->pg_host_opaque;
3946 	u8 opcode = kcqe->op_code;
3947 	struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
3948 
3949 	csk_hold(csk);
3950 	if (!cnic_in_use(csk))
3951 		goto done;
3952 
3953 	if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3954 		clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3955 		goto done;
3956 	}
3957 	/* Possible PG kcqe status:  SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
3958 	if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
3959 		clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
3960 		cnic_cm_upcall(cp, csk,
3961 			       L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
3962 		goto done;
3963 	}
3964 
3965 	csk->pg_cid = kcqe->pg_cid;
3966 	set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
3967 	cnic_cm_conn_req(csk);
3968 
3969 done:
3970 	csk_put(csk);
3971 }
3972 
3973 static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
3974 {
3975 	struct cnic_local *cp = dev->cnic_priv;
3976 	struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
3977 	u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
3978 	struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
3979 
3980 	ctx->timestamp = jiffies;
3981 	ctx->wait_cond = 1;
3982 	wake_up(&ctx->waitq);
3983 }
3984 
3985 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
3986 {
3987 	struct cnic_local *cp = dev->cnic_priv;
3988 	struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
3989 	u8 opcode = l4kcqe->op_code;
3990 	u32 l5_cid;
3991 	struct cnic_sock *csk;
3992 
3993 	if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
3994 		cnic_process_fcoe_term_conn(dev, kcqe);
3995 		return;
3996 	}
3997 	if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
3998 	    opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
3999 		cnic_cm_process_offld_pg(dev, l4kcqe);
4000 		return;
4001 	}
4002 
4003 	l5_cid = l4kcqe->conn_id;
4004 	if (opcode & 0x80)
4005 		l5_cid = l4kcqe->cid;
4006 	if (l5_cid >= MAX_CM_SK_TBL_SZ)
4007 		return;
4008 
4009 	csk = &cp->csk_tbl[l5_cid];
4010 	csk_hold(csk);
4011 
4012 	if (!cnic_in_use(csk)) {
4013 		csk_put(csk);
4014 		return;
4015 	}
4016 
4017 	switch (opcode) {
4018 	case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
4019 		if (l4kcqe->status != 0) {
4020 			clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
4021 			cnic_cm_upcall(cp, csk,
4022 				       L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
4023 		}
4024 		break;
4025 	case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
4026 		if (l4kcqe->status == 0)
4027 			set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
4028 		else if (l4kcqe->status ==
4029 			 L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
4030 			set_bit(SK_F_HW_ERR, &csk->flags);
4031 
4032 		smp_mb__before_atomic();
4033 		clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
4034 		cnic_cm_upcall(cp, csk, opcode);
4035 		break;
4036 
4037 	case L5CM_RAMROD_CMD_ID_CLOSE: {
4038 		struct iscsi_kcqe *l5kcqe = (struct iscsi_kcqe *) kcqe;
4039 
4040 		if (l4kcqe->status == 0 && l5kcqe->completion_status == 0)
4041 			break;
4042 
4043 		netdev_warn(dev->netdev, "RAMROD CLOSE compl with status 0x%x completion status 0x%x\n",
4044 			    l4kcqe->status, l5kcqe->completion_status);
4045 		opcode = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
4046 	}
4047 		fallthrough;
4048 	case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
4049 	case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
4050 	case L4_KCQE_OPCODE_VALUE_RESET_COMP:
4051 	case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
4052 	case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
4053 		if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_PARITY_ERROR)
4054 			set_bit(SK_F_HW_ERR, &csk->flags);
4055 
4056 		cp->close_conn(csk, opcode);
4057 		break;
4058 
4059 	case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
4060 		/* after we already sent CLOSE_REQ */
4061 		if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
4062 		    !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
4063 		    csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
4064 			cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
4065 		else
4066 			cnic_cm_upcall(cp, csk, opcode);
4067 		break;
4068 	}
4069 	csk_put(csk);
4070 }
4071 
4072 static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
4073 {
4074 	struct cnic_dev *dev = data;
4075 	int i;
4076 
4077 	for (i = 0; i < num; i++)
4078 		cnic_cm_process_kcqe(dev, kcqe[i]);
4079 }
4080 
4081 static struct cnic_ulp_ops cm_ulp_ops = {
4082 	.indicate_kcqes		= cnic_cm_indicate_kcqe,
4083 };
4084 
4085 static void cnic_cm_free_mem(struct cnic_dev *dev)
4086 {
4087 	struct cnic_local *cp = dev->cnic_priv;
4088 
4089 	kvfree(cp->csk_tbl);
4090 	cp->csk_tbl = NULL;
4091 	cnic_free_id_tbl(&cp->csk_port_tbl);
4092 }
4093 
4094 static int cnic_cm_alloc_mem(struct cnic_dev *dev)
4095 {
4096 	struct cnic_local *cp = dev->cnic_priv;
4097 	u32 port_id;
4098 	int i;
4099 
4100 	cp->csk_tbl = kvcalloc(MAX_CM_SK_TBL_SZ, sizeof(struct cnic_sock),
4101 			       GFP_KERNEL);
4102 	if (!cp->csk_tbl)
4103 		return -ENOMEM;
4104 
4105 	for (i = 0; i < MAX_CM_SK_TBL_SZ; i++)
4106 		atomic_set(&cp->csk_tbl[i].ref_count, 0);
4107 
4108 	port_id = prandom_u32_max(CNIC_LOCAL_PORT_RANGE);
4109 	if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
4110 			     CNIC_LOCAL_PORT_MIN, port_id)) {
4111 		cnic_cm_free_mem(dev);
4112 		return -ENOMEM;
4113 	}
4114 	return 0;
4115 }
4116 
4117 static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
4118 {
4119 	if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
4120 		/* Unsolicited RESET_COMP or RESET_RECEIVED */
4121 		opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
4122 		csk->state = opcode;
4123 	}
4124 
4125 	/* 1. If event opcode matches the expected event in csk->state
4126 	 * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
4127 	 *    event
4128 	 * 3. If the expected event is 0, meaning the connection was never
4129 	 *    never established, we accept the opcode from cm_abort.
4130 	 */
4131 	if (opcode == csk->state || csk->state == 0 ||
4132 	    csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
4133 	    csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
4134 		if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
4135 			if (csk->state == 0)
4136 				csk->state = opcode;
4137 			return 1;
4138 		}
4139 	}
4140 	return 0;
4141 }
4142 
4143 static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
4144 {
4145 	struct cnic_dev *dev = csk->dev;
4146 	struct cnic_local *cp = dev->cnic_priv;
4147 
4148 	if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
4149 		cnic_cm_upcall(cp, csk, opcode);
4150 		return;
4151 	}
4152 
4153 	clear_bit(SK_F_CONNECT_START, &csk->flags);
4154 	cnic_close_conn(csk);
4155 	csk->state = opcode;
4156 	cnic_cm_upcall(cp, csk, opcode);
4157 }
4158 
4159 static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
4160 {
4161 }
4162 
4163 static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
4164 {
4165 	u32 seed;
4166 
4167 	seed = get_random_u32();
4168 	cnic_ctx_wr(dev, 45, 0, seed);
4169 	return 0;
4170 }
4171 
4172 static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
4173 {
4174 	struct cnic_dev *dev = csk->dev;
4175 	struct cnic_local *cp = dev->cnic_priv;
4176 	struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
4177 	union l5cm_specific_data l5_data;
4178 	u32 cmd = 0;
4179 	int close_complete = 0;
4180 
4181 	switch (opcode) {
4182 	case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
4183 	case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
4184 	case L4_KCQE_OPCODE_VALUE_RESET_COMP:
4185 		if (cnic_ready_to_close(csk, opcode)) {
4186 			if (test_bit(SK_F_HW_ERR, &csk->flags))
4187 				close_complete = 1;
4188 			else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
4189 				cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
4190 			else
4191 				close_complete = 1;
4192 		}
4193 		break;
4194 	case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
4195 		cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
4196 		break;
4197 	case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
4198 		close_complete = 1;
4199 		break;
4200 	}
4201 	if (cmd) {
4202 		memset(&l5_data, 0, sizeof(l5_data));
4203 
4204 		cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
4205 				    &l5_data);
4206 	} else if (close_complete) {
4207 		ctx->timestamp = jiffies;
4208 		cnic_close_conn(csk);
4209 		cnic_cm_upcall(cp, csk, csk->state);
4210 	}
4211 }
4212 
4213 static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
4214 {
4215 	struct cnic_local *cp = dev->cnic_priv;
4216 
4217 	if (!cp->ctx_tbl)
4218 		return;
4219 
4220 	if (!netif_running(dev->netdev))
4221 		return;
4222 
4223 	cnic_bnx2x_delete_wait(dev, 0);
4224 
4225 	cancel_delayed_work(&cp->delete_task);
4226 	flush_workqueue(cnic_wq);
4227 
4228 	if (atomic_read(&cp->iscsi_conn) != 0)
4229 		netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
4230 			    atomic_read(&cp->iscsi_conn));
4231 }
4232 
4233 static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
4234 {
4235 	struct bnx2x *bp = netdev_priv(dev->netdev);
4236 	u32 pfid = bp->pfid;
4237 	u32 port = BP_PORT(bp);
4238 
4239 	cnic_init_bnx2x_mac(dev);
4240 	cnic_bnx2x_set_tcp_options(dev, 0, 1);
4241 
4242 	CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
4243 		  XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
4244 
4245 	CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4246 		XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
4247 	CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4248 		XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
4249 		DEF_MAX_DA_COUNT);
4250 
4251 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
4252 		 XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
4253 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
4254 		 XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
4255 	CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
4256 		 XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
4257 	CNIC_WR(dev, BAR_XSTRORM_INTMEM +
4258 		XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
4259 
4260 	CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
4261 		DEF_MAX_CWND);
4262 	return 0;
4263 }
4264 
4265 static void cnic_delete_task(struct work_struct *work)
4266 {
4267 	struct cnic_local *cp;
4268 	struct cnic_dev *dev;
4269 	u32 i;
4270 	int need_resched = 0;
4271 
4272 	cp = container_of(work, struct cnic_local, delete_task.work);
4273 	dev = cp->dev;
4274 
4275 	if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
4276 		struct drv_ctl_info info;
4277 
4278 		cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
4279 
4280 		memset(&info, 0, sizeof(struct drv_ctl_info));
4281 		info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
4282 		cp->ethdev->drv_ctl(dev->netdev, &info);
4283 	}
4284 
4285 	for (i = 0; i < cp->max_cid_space; i++) {
4286 		struct cnic_context *ctx = &cp->ctx_tbl[i];
4287 		int err;
4288 
4289 		if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
4290 		    !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4291 			continue;
4292 
4293 		if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
4294 			need_resched = 1;
4295 			continue;
4296 		}
4297 
4298 		if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
4299 			continue;
4300 
4301 		err = cnic_bnx2x_destroy_ramrod(dev, i);
4302 
4303 		cnic_free_bnx2x_conn_resc(dev, i);
4304 		if (!err) {
4305 			if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
4306 				atomic_dec(&cp->iscsi_conn);
4307 
4308 			clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
4309 		}
4310 	}
4311 
4312 	if (need_resched)
4313 		queue_delayed_work(cnic_wq, &cp->delete_task,
4314 				   msecs_to_jiffies(10));
4315 
4316 }
4317 
4318 static int cnic_cm_open(struct cnic_dev *dev)
4319 {
4320 	struct cnic_local *cp = dev->cnic_priv;
4321 	int err;
4322 
4323 	err = cnic_cm_alloc_mem(dev);
4324 	if (err)
4325 		return err;
4326 
4327 	err = cp->start_cm(dev);
4328 
4329 	if (err)
4330 		goto err_out;
4331 
4332 	INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
4333 
4334 	dev->cm_create = cnic_cm_create;
4335 	dev->cm_destroy = cnic_cm_destroy;
4336 	dev->cm_connect = cnic_cm_connect;
4337 	dev->cm_abort = cnic_cm_abort;
4338 	dev->cm_close = cnic_cm_close;
4339 	dev->cm_select_dev = cnic_cm_select_dev;
4340 
4341 	cp->ulp_handle[CNIC_ULP_L4] = dev;
4342 	rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
4343 	return 0;
4344 
4345 err_out:
4346 	cnic_cm_free_mem(dev);
4347 	return err;
4348 }
4349 
4350 static int cnic_cm_shutdown(struct cnic_dev *dev)
4351 {
4352 	struct cnic_local *cp = dev->cnic_priv;
4353 	int i;
4354 
4355 	if (!cp->csk_tbl)
4356 		return 0;
4357 
4358 	for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
4359 		struct cnic_sock *csk = &cp->csk_tbl[i];
4360 
4361 		clear_bit(SK_F_INUSE, &csk->flags);
4362 		cnic_cm_cleanup(csk);
4363 	}
4364 	cnic_cm_free_mem(dev);
4365 
4366 	return 0;
4367 }
4368 
4369 static void cnic_init_context(struct cnic_dev *dev, u32 cid)
4370 {
4371 	u32 cid_addr;
4372 	int i;
4373 
4374 	cid_addr = GET_CID_ADDR(cid);
4375 
4376 	for (i = 0; i < CTX_SIZE; i += 4)
4377 		cnic_ctx_wr(dev, cid_addr, i, 0);
4378 }
4379 
4380 static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
4381 {
4382 	struct cnic_local *cp = dev->cnic_priv;
4383 	int ret = 0, i;
4384 	u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
4385 
4386 	if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
4387 		return 0;
4388 
4389 	for (i = 0; i < cp->ctx_blks; i++) {
4390 		int j;
4391 		u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
4392 		u32 val;
4393 
4394 		memset(cp->ctx_arr[i].ctx, 0, CNIC_PAGE_SIZE);
4395 
4396 		CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
4397 			(cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
4398 		CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
4399 			(u64) cp->ctx_arr[i].mapping >> 32);
4400 		CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
4401 			BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4402 		for (j = 0; j < 10; j++) {
4403 
4404 			val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
4405 			if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
4406 				break;
4407 			udelay(5);
4408 		}
4409 		if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
4410 			ret = -EBUSY;
4411 			break;
4412 		}
4413 	}
4414 	return ret;
4415 }
4416 
4417 static void cnic_free_irq(struct cnic_dev *dev)
4418 {
4419 	struct cnic_local *cp = dev->cnic_priv;
4420 	struct cnic_eth_dev *ethdev = cp->ethdev;
4421 
4422 	if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4423 		cp->disable_int_sync(dev);
4424 		tasklet_kill(&cp->cnic_irq_task);
4425 		free_irq(ethdev->irq_arr[0].vector, dev);
4426 	}
4427 }
4428 
4429 static int cnic_request_irq(struct cnic_dev *dev)
4430 {
4431 	struct cnic_local *cp = dev->cnic_priv;
4432 	struct cnic_eth_dev *ethdev = cp->ethdev;
4433 	int err;
4434 
4435 	err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
4436 	if (err)
4437 		tasklet_disable(&cp->cnic_irq_task);
4438 
4439 	return err;
4440 }
4441 
4442 static int cnic_init_bnx2_irq(struct cnic_dev *dev)
4443 {
4444 	struct cnic_local *cp = dev->cnic_priv;
4445 	struct cnic_eth_dev *ethdev = cp->ethdev;
4446 
4447 	if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4448 		int err, i = 0;
4449 		int sblk_num = cp->status_blk_num;
4450 		u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4451 			   BNX2_HC_SB_CONFIG_1;
4452 
4453 		CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4454 
4455 		CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
4456 		CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
4457 		CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
4458 
4459 		cp->last_status_idx = cp->status_blk.bnx2->status_idx;
4460 		tasklet_setup(&cp->cnic_irq_task, cnic_service_bnx2_msix);
4461 		err = cnic_request_irq(dev);
4462 		if (err)
4463 			return err;
4464 
4465 		while (cp->status_blk.bnx2->status_completion_producer_index &&
4466 		       i < 10) {
4467 			CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
4468 				1 << (11 + sblk_num));
4469 			udelay(10);
4470 			i++;
4471 			barrier();
4472 		}
4473 		if (cp->status_blk.bnx2->status_completion_producer_index) {
4474 			cnic_free_irq(dev);
4475 			goto failed;
4476 		}
4477 
4478 	} else {
4479 		struct status_block *sblk = cp->status_blk.gen;
4480 		u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
4481 		int i = 0;
4482 
4483 		while (sblk->status_completion_producer_index && i < 10) {
4484 			CNIC_WR(dev, BNX2_HC_COMMAND,
4485 				hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4486 			udelay(10);
4487 			i++;
4488 			barrier();
4489 		}
4490 		if (sblk->status_completion_producer_index)
4491 			goto failed;
4492 
4493 	}
4494 	return 0;
4495 
4496 failed:
4497 	netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
4498 	return -EBUSY;
4499 }
4500 
4501 static void cnic_enable_bnx2_int(struct cnic_dev *dev)
4502 {
4503 	struct cnic_local *cp = dev->cnic_priv;
4504 	struct cnic_eth_dev *ethdev = cp->ethdev;
4505 
4506 	if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4507 		return;
4508 
4509 	CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4510 		BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
4511 }
4512 
4513 static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
4514 {
4515 	struct cnic_local *cp = dev->cnic_priv;
4516 	struct cnic_eth_dev *ethdev = cp->ethdev;
4517 
4518 	if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
4519 		return;
4520 
4521 	CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
4522 		BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4523 	CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
4524 	synchronize_irq(ethdev->irq_arr[0].vector);
4525 }
4526 
4527 static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
4528 {
4529 	struct cnic_local *cp = dev->cnic_priv;
4530 	struct cnic_eth_dev *ethdev = cp->ethdev;
4531 	struct cnic_uio_dev *udev = cp->udev;
4532 	u32 cid_addr, tx_cid, sb_id;
4533 	u32 val, offset0, offset1, offset2, offset3;
4534 	int i;
4535 	struct bnx2_tx_bd *txbd;
4536 	dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4537 	struct status_block *s_blk = cp->status_blk.gen;
4538 
4539 	sb_id = cp->status_blk_num;
4540 	tx_cid = 20;
4541 	cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
4542 	if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4543 		struct status_block_msix *sblk = cp->status_blk.bnx2;
4544 
4545 		tx_cid = TX_TSS_CID + sb_id - 1;
4546 		CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
4547 			(TX_TSS_CID << 7));
4548 		cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
4549 	}
4550 	cp->tx_cons = *cp->tx_cons_ptr;
4551 
4552 	cid_addr = GET_CID_ADDR(tx_cid);
4553 	if (BNX2_CHIP(cp) == BNX2_CHIP_5709) {
4554 		u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
4555 
4556 		for (i = 0; i < PHY_CTX_SIZE; i += 4)
4557 			cnic_ctx_wr(dev, cid_addr2, i, 0);
4558 
4559 		offset0 = BNX2_L2CTX_TYPE_XI;
4560 		offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4561 		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4562 		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4563 	} else {
4564 		cnic_init_context(dev, tx_cid);
4565 		cnic_init_context(dev, tx_cid + 1);
4566 
4567 		offset0 = BNX2_L2CTX_TYPE;
4568 		offset1 = BNX2_L2CTX_CMD_TYPE;
4569 		offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4570 		offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4571 	}
4572 	val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4573 	cnic_ctx_wr(dev, cid_addr, offset0, val);
4574 
4575 	val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4576 	cnic_ctx_wr(dev, cid_addr, offset1, val);
4577 
4578 	txbd = udev->l2_ring;
4579 
4580 	buf_map = udev->l2_buf_map;
4581 	for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i++, txbd++) {
4582 		txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
4583 		txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4584 	}
4585 	val = (u64) ring_map >> 32;
4586 	cnic_ctx_wr(dev, cid_addr, offset2, val);
4587 	txbd->tx_bd_haddr_hi = val;
4588 
4589 	val = (u64) ring_map & 0xffffffff;
4590 	cnic_ctx_wr(dev, cid_addr, offset3, val);
4591 	txbd->tx_bd_haddr_lo = val;
4592 }
4593 
4594 static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
4595 {
4596 	struct cnic_local *cp = dev->cnic_priv;
4597 	struct cnic_eth_dev *ethdev = cp->ethdev;
4598 	struct cnic_uio_dev *udev = cp->udev;
4599 	u32 cid_addr, sb_id, val, coal_reg, coal_val;
4600 	int i;
4601 	struct bnx2_rx_bd *rxbd;
4602 	struct status_block *s_blk = cp->status_blk.gen;
4603 	dma_addr_t ring_map = udev->l2_ring_map;
4604 
4605 	sb_id = cp->status_blk_num;
4606 	cnic_init_context(dev, 2);
4607 	cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
4608 	coal_reg = BNX2_HC_COMMAND;
4609 	coal_val = CNIC_RD(dev, coal_reg);
4610 	if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4611 		struct status_block_msix *sblk = cp->status_blk.bnx2;
4612 
4613 		cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
4614 		coal_reg = BNX2_HC_COALESCE_NOW;
4615 		coal_val = 1 << (11 + sb_id);
4616 	}
4617 	i = 0;
4618 	while (!(*cp->rx_cons_ptr != 0) && i < 10) {
4619 		CNIC_WR(dev, coal_reg, coal_val);
4620 		udelay(10);
4621 		i++;
4622 		barrier();
4623 	}
4624 	cp->rx_cons = *cp->rx_cons_ptr;
4625 
4626 	cid_addr = GET_CID_ADDR(2);
4627 	val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4628 	      BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4629 	cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4630 
4631 	if (sb_id == 0)
4632 		val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
4633 	else
4634 		val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
4635 	cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
4636 
4637 	rxbd = udev->l2_ring + CNIC_PAGE_SIZE;
4638 	for (i = 0; i < BNX2_MAX_RX_DESC_CNT; i++, rxbd++) {
4639 		dma_addr_t buf_map;
4640 		int n = (i % cp->l2_rx_ring_size) + 1;
4641 
4642 		buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
4643 		rxbd->rx_bd_len = cp->l2_single_buf_size;
4644 		rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4645 		rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
4646 		rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
4647 	}
4648 	val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
4649 	cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4650 	rxbd->rx_bd_haddr_hi = val;
4651 
4652 	val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
4653 	cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4654 	rxbd->rx_bd_haddr_lo = val;
4655 
4656 	val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
4657 	cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
4658 }
4659 
4660 static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
4661 {
4662 	struct kwqe *wqes[1], l2kwqe;
4663 
4664 	memset(&l2kwqe, 0, sizeof(l2kwqe));
4665 	wqes[0] = &l2kwqe;
4666 	l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
4667 			      (L2_KWQE_OPCODE_VALUE_FLUSH <<
4668 			       KWQE_OPCODE_SHIFT) | 2;
4669 	dev->submit_kwqes(dev, wqes, 1);
4670 }
4671 
4672 static void cnic_set_bnx2_mac(struct cnic_dev *dev)
4673 {
4674 	struct cnic_local *cp = dev->cnic_priv;
4675 	u32 val;
4676 
4677 	val = cp->func << 2;
4678 
4679 	cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
4680 
4681 	val = cnic_reg_rd_ind(dev, cp->shmem_base +
4682 			      BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
4683 	dev->mac_addr[0] = (u8) (val >> 8);
4684 	dev->mac_addr[1] = (u8) val;
4685 
4686 	CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
4687 
4688 	val = cnic_reg_rd_ind(dev, cp->shmem_base +
4689 			      BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
4690 	dev->mac_addr[2] = (u8) (val >> 24);
4691 	dev->mac_addr[3] = (u8) (val >> 16);
4692 	dev->mac_addr[4] = (u8) (val >> 8);
4693 	dev->mac_addr[5] = (u8) val;
4694 
4695 	CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
4696 
4697 	val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
4698 	if (BNX2_CHIP(cp) != BNX2_CHIP_5709)
4699 		val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
4700 
4701 	CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
4702 	CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
4703 	CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
4704 }
4705 
4706 static int cnic_start_bnx2_hw(struct cnic_dev *dev)
4707 {
4708 	struct cnic_local *cp = dev->cnic_priv;
4709 	struct cnic_eth_dev *ethdev = cp->ethdev;
4710 	struct status_block *sblk = cp->status_blk.gen;
4711 	u32 val, kcq_cid_addr, kwq_cid_addr;
4712 	int err;
4713 
4714 	cnic_set_bnx2_mac(dev);
4715 
4716 	val = CNIC_RD(dev, BNX2_MQ_CONFIG);
4717 	val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4718 	if (CNIC_PAGE_BITS > 12)
4719 		val |= (12 - 8)  << 4;
4720 	else
4721 		val |= (CNIC_PAGE_BITS - 8)  << 4;
4722 
4723 	CNIC_WR(dev, BNX2_MQ_CONFIG, val);
4724 
4725 	CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
4726 	CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
4727 	CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
4728 
4729 	err = cnic_setup_5709_context(dev, 1);
4730 	if (err)
4731 		return err;
4732 
4733 	cnic_init_context(dev, KWQ_CID);
4734 	cnic_init_context(dev, KCQ_CID);
4735 
4736 	kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
4737 	cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
4738 
4739 	cp->max_kwq_idx = MAX_KWQ_IDX;
4740 	cp->kwq_prod_idx = 0;
4741 	cp->kwq_con_idx = 0;
4742 	set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
4743 
4744 	if (BNX2_CHIP(cp) == BNX2_CHIP_5706 || BNX2_CHIP(cp) == BNX2_CHIP_5708)
4745 		cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
4746 	else
4747 		cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
4748 
4749 	/* Initialize the kernel work queue context. */
4750 	val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4751 	      (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4752 	cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
4753 
4754 	val = (CNIC_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
4755 	cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4756 
4757 	val = ((CNIC_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
4758 	cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4759 
4760 	val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
4761 	cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4762 
4763 	val = (u32) cp->kwq_info.pgtbl_map;
4764 	cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4765 
4766 	kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
4767 	cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
4768 
4769 	cp->kcq1.sw_prod_idx = 0;
4770 	cp->kcq1.hw_prod_idx_ptr =
4771 		&sblk->status_completion_producer_index;
4772 
4773 	cp->kcq1.status_idx_ptr = &sblk->status_idx;
4774 
4775 	/* Initialize the kernel complete queue context. */
4776 	val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
4777 	      (CNIC_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
4778 	cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
4779 
4780 	val = (CNIC_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
4781 	cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
4782 
4783 	val = ((CNIC_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
4784 	cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
4785 
4786 	val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
4787 	cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
4788 
4789 	val = (u32) cp->kcq1.dma.pgtbl_map;
4790 	cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
4791 
4792 	cp->int_num = 0;
4793 	if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
4794 		struct status_block_msix *msblk = cp->status_blk.bnx2;
4795 		u32 sb_id = cp->status_blk_num;
4796 		u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
4797 
4798 		cp->kcq1.hw_prod_idx_ptr =
4799 			&msblk->status_completion_producer_index;
4800 		cp->kcq1.status_idx_ptr = &msblk->status_idx;
4801 		cp->kwq_con_idx_ptr = &msblk->status_cmd_consumer_index;
4802 		cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
4803 		cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4804 		cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
4805 	}
4806 
4807 	/* Enable Commnad Scheduler notification when we write to the
4808 	 * host producer index of the kernel contexts. */
4809 	CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
4810 
4811 	/* Enable Command Scheduler notification when we write to either
4812 	 * the Send Queue or Receive Queue producer indexes of the kernel
4813 	 * bypass contexts. */
4814 	CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
4815 	CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
4816 
4817 	/* Notify COM when the driver post an application buffer. */
4818 	CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
4819 
4820 	/* Set the CP and COM doorbells.  These two processors polls the
4821 	 * doorbell for a non zero value before running.  This must be done
4822 	 * after setting up the kernel queue contexts. */
4823 	cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
4824 	cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
4825 
4826 	cnic_init_bnx2_tx_ring(dev);
4827 	cnic_init_bnx2_rx_ring(dev);
4828 
4829 	err = cnic_init_bnx2_irq(dev);
4830 	if (err) {
4831 		netdev_err(dev->netdev, "cnic_init_irq failed\n");
4832 		cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
4833 		cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
4834 		return err;
4835 	}
4836 
4837 	ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
4838 
4839 	return 0;
4840 }
4841 
4842 static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
4843 {
4844 	struct cnic_local *cp = dev->cnic_priv;
4845 	struct cnic_eth_dev *ethdev = cp->ethdev;
4846 	u32 start_offset = ethdev->ctx_tbl_offset;
4847 	int i;
4848 
4849 	for (i = 0; i < cp->ctx_blks; i++) {
4850 		struct cnic_ctx *ctx = &cp->ctx_arr[i];
4851 		dma_addr_t map = ctx->mapping;
4852 
4853 		if (cp->ctx_align) {
4854 			unsigned long mask = cp->ctx_align - 1;
4855 
4856 			map = (map + mask) & ~mask;
4857 		}
4858 
4859 		cnic_ctx_tbl_wr(dev, start_offset + i, map);
4860 	}
4861 }
4862 
4863 static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
4864 {
4865 	struct cnic_local *cp = dev->cnic_priv;
4866 	struct cnic_eth_dev *ethdev = cp->ethdev;
4867 	int err = 0;
4868 
4869 	tasklet_setup(&cp->cnic_irq_task, cnic_service_bnx2x_bh);
4870 	if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
4871 		err = cnic_request_irq(dev);
4872 
4873 	return err;
4874 }
4875 
4876 static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
4877 						u16 sb_id, u8 sb_index,
4878 						u8 disable)
4879 {
4880 	struct bnx2x *bp = netdev_priv(dev->netdev);
4881 
4882 	u32 addr = BAR_CSTRORM_INTMEM +
4883 			CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4884 			offsetof(struct hc_status_block_data_e1x, index_data) +
4885 			sizeof(struct hc_index_data)*sb_index +
4886 			offsetof(struct hc_index_data, flags);
4887 	u16 flags = CNIC_RD16(dev, addr);
4888 	/* clear and set */
4889 	flags &= ~HC_INDEX_DATA_HC_ENABLED;
4890 	flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
4891 		  HC_INDEX_DATA_HC_ENABLED);
4892 	CNIC_WR16(dev, addr, flags);
4893 }
4894 
4895 static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
4896 {
4897 	struct cnic_local *cp = dev->cnic_priv;
4898 	struct bnx2x *bp = netdev_priv(dev->netdev);
4899 	u8 sb_id = cp->status_blk_num;
4900 
4901 	CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
4902 			CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
4903 			offsetof(struct hc_status_block_data_e1x, index_data) +
4904 			sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
4905 			offsetof(struct hc_index_data, timeout), 64 / 4);
4906 	cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
4907 }
4908 
4909 static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
4910 {
4911 }
4912 
4913 static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
4914 				    struct client_init_ramrod_data *data)
4915 {
4916 	struct cnic_local *cp = dev->cnic_priv;
4917 	struct bnx2x *bp = netdev_priv(dev->netdev);
4918 	struct cnic_uio_dev *udev = cp->udev;
4919 	union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
4920 	dma_addr_t buf_map, ring_map = udev->l2_ring_map;
4921 	struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4922 	int i;
4923 	u32 cli = cp->ethdev->iscsi_l2_client_id;
4924 	u32 val;
4925 
4926 	memset(txbd, 0, CNIC_PAGE_SIZE);
4927 
4928 	buf_map = udev->l2_buf_map;
4929 	for (i = 0; i < BNX2_MAX_TX_DESC_CNT; i += 3, txbd += 3) {
4930 		struct eth_tx_start_bd *start_bd = &txbd->start_bd;
4931 		struct eth_tx_parse_bd_e1x *pbd_e1x =
4932 			&((txbd + 1)->parse_bd_e1x);
4933 		struct eth_tx_parse_bd_e2 *pbd_e2 = &((txbd + 1)->parse_bd_e2);
4934 		struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
4935 
4936 		start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
4937 		start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
4938 		reg_bd->addr_hi = start_bd->addr_hi;
4939 		reg_bd->addr_lo = start_bd->addr_lo + 0x10;
4940 		start_bd->nbytes = cpu_to_le16(0x10);
4941 		start_bd->nbd = cpu_to_le16(3);
4942 		start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
4943 		start_bd->general_data &= ~ETH_TX_START_BD_PARSE_NBDS;
4944 		start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
4945 
4946 		if (BNX2X_CHIP_IS_E2_PLUS(bp))
4947 			pbd_e2->parsing_data = (UNICAST_ADDRESS <<
4948 				ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT);
4949 		else
4950 			pbd_e1x->global_data = (UNICAST_ADDRESS <<
4951 				ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT);
4952 	}
4953 
4954 	val = (u64) ring_map >> 32;
4955 	txbd->next_bd.addr_hi = cpu_to_le32(val);
4956 
4957 	data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
4958 
4959 	val = (u64) ring_map & 0xffffffff;
4960 	txbd->next_bd.addr_lo = cpu_to_le32(val);
4961 
4962 	data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
4963 
4964 	/* Other ramrod params */
4965 	data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
4966 	data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
4967 
4968 	/* reset xstorm per client statistics */
4969 	if (cli < MAX_STAT_COUNTER_ID) {
4970 		data->general.statistics_zero_flg = 1;
4971 		data->general.statistics_en_flg = 1;
4972 		data->general.statistics_counter_id = cli;
4973 	}
4974 
4975 	cp->tx_cons_ptr =
4976 		&sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
4977 }
4978 
4979 static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
4980 				    struct client_init_ramrod_data *data)
4981 {
4982 	struct cnic_local *cp = dev->cnic_priv;
4983 	struct bnx2x *bp = netdev_priv(dev->netdev);
4984 	struct cnic_uio_dev *udev = cp->udev;
4985 	struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
4986 				CNIC_PAGE_SIZE);
4987 	struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
4988 				(udev->l2_ring + (2 * CNIC_PAGE_SIZE));
4989 	struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
4990 	int i;
4991 	u32 cli = cp->ethdev->iscsi_l2_client_id;
4992 	int cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
4993 	u32 val;
4994 	dma_addr_t ring_map = udev->l2_ring_map;
4995 
4996 	/* General data */
4997 	data->general.client_id = cli;
4998 	data->general.activate_flg = 1;
4999 	data->general.sp_client_id = cli;
5000 	data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
5001 	data->general.func_id = bp->pfid;
5002 
5003 	for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
5004 		dma_addr_t buf_map;
5005 		int n = (i % cp->l2_rx_ring_size) + 1;
5006 
5007 		buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
5008 		rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
5009 		rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
5010 	}
5011 
5012 	val = (u64) (ring_map + CNIC_PAGE_SIZE) >> 32;
5013 	rxbd->addr_hi = cpu_to_le32(val);
5014 	data->rx.bd_page_base.hi = cpu_to_le32(val);
5015 
5016 	val = (u64) (ring_map + CNIC_PAGE_SIZE) & 0xffffffff;
5017 	rxbd->addr_lo = cpu_to_le32(val);
5018 	data->rx.bd_page_base.lo = cpu_to_le32(val);
5019 
5020 	rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
5021 	val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) >> 32;
5022 	rxcqe->addr_hi = cpu_to_le32(val);
5023 	data->rx.cqe_page_base.hi = cpu_to_le32(val);
5024 
5025 	val = (u64) (ring_map + (2 * CNIC_PAGE_SIZE)) & 0xffffffff;
5026 	rxcqe->addr_lo = cpu_to_le32(val);
5027 	data->rx.cqe_page_base.lo = cpu_to_le32(val);
5028 
5029 	/* Other ramrod params */
5030 	data->rx.client_qzone_id = cl_qzone_id;
5031 	data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
5032 	data->rx.status_block_id = BNX2X_DEF_SB_ID;
5033 
5034 	data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
5035 
5036 	data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
5037 	data->rx.outer_vlan_removal_enable_flg = 1;
5038 	data->rx.silent_vlan_removal_flg = 1;
5039 	data->rx.silent_vlan_value = 0;
5040 	data->rx.silent_vlan_mask = 0xffff;
5041 
5042 	cp->rx_cons_ptr =
5043 		&sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
5044 	cp->rx_cons = *cp->rx_cons_ptr;
5045 }
5046 
5047 static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
5048 {
5049 	struct cnic_local *cp = dev->cnic_priv;
5050 	struct bnx2x *bp = netdev_priv(dev->netdev);
5051 	u32 pfid = bp->pfid;
5052 
5053 	cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
5054 			   CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
5055 	cp->kcq1.sw_prod_idx = 0;
5056 
5057 	if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
5058 		struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
5059 
5060 		cp->kcq1.hw_prod_idx_ptr =
5061 			&sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
5062 		cp->kcq1.status_idx_ptr =
5063 			&sb->sb.running_index[SM_RX_ID];
5064 	} else {
5065 		struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
5066 
5067 		cp->kcq1.hw_prod_idx_ptr =
5068 			&sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
5069 		cp->kcq1.status_idx_ptr =
5070 			&sb->sb.running_index[SM_RX_ID];
5071 	}
5072 
5073 	if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
5074 		struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
5075 
5076 		cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
5077 					USTORM_FCOE_EQ_PROD_OFFSET(pfid);
5078 		cp->kcq2.sw_prod_idx = 0;
5079 		cp->kcq2.hw_prod_idx_ptr =
5080 			&sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
5081 		cp->kcq2.status_idx_ptr =
5082 			&sb->sb.running_index[SM_RX_ID];
5083 	}
5084 }
5085 
5086 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
5087 {
5088 	struct cnic_local *cp = dev->cnic_priv;
5089 	struct bnx2x *bp = netdev_priv(dev->netdev);
5090 	struct cnic_eth_dev *ethdev = cp->ethdev;
5091 	int ret;
5092 	u32 pfid;
5093 
5094 	dev->stats_addr = ethdev->addr_drv_info_to_mcp;
5095 	cp->func = bp->pf_num;
5096 
5097 	pfid = bp->pfid;
5098 
5099 	ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
5100 			       cp->iscsi_start_cid, 0);
5101 
5102 	if (ret)
5103 		return -ENOMEM;
5104 
5105 	if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
5106 		ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
5107 					cp->fcoe_start_cid, 0);
5108 
5109 		if (ret)
5110 			return -ENOMEM;
5111 	}
5112 
5113 	cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
5114 
5115 	cnic_init_bnx2x_kcq(dev);
5116 
5117 	/* Only 1 EQ */
5118 	CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
5119 	CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5120 		CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
5121 	CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5122 		CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
5123 		cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
5124 	CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5125 		CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
5126 		(u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
5127 	CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5128 		CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
5129 		cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
5130 	CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5131 		CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
5132 		(u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
5133 	CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
5134 		CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
5135 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
5136 		CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
5137 	CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
5138 		CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
5139 		HC_INDEX_ISCSI_EQ_CONS);
5140 
5141 	CNIC_WR(dev, BAR_USTRORM_INTMEM +
5142 		USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
5143 		cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
5144 	CNIC_WR(dev, BAR_USTRORM_INTMEM +
5145 		USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
5146 		(u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
5147 
5148 	CNIC_WR(dev, BAR_TSTRORM_INTMEM +
5149 		TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
5150 
5151 	cnic_setup_bnx2x_context(dev);
5152 
5153 	ret = cnic_init_bnx2x_irq(dev);
5154 	if (ret)
5155 		return ret;
5156 
5157 	ethdev->drv_state |= CNIC_DRV_STATE_HANDLES_IRQ;
5158 	return 0;
5159 }
5160 
5161 static void cnic_init_rings(struct cnic_dev *dev)
5162 {
5163 	struct cnic_local *cp = dev->cnic_priv;
5164 	struct bnx2x *bp = netdev_priv(dev->netdev);
5165 	struct cnic_uio_dev *udev = cp->udev;
5166 
5167 	if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
5168 		return;
5169 
5170 	if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
5171 		cnic_init_bnx2_tx_ring(dev);
5172 		cnic_init_bnx2_rx_ring(dev);
5173 		set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5174 	} else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
5175 		u32 cli = cp->ethdev->iscsi_l2_client_id;
5176 		u32 cid = cp->ethdev->iscsi_l2_cid;
5177 		u32 cl_qzone_id;
5178 		struct client_init_ramrod_data *data;
5179 		union l5cm_specific_data l5_data;
5180 		struct ustorm_eth_rx_producers rx_prods = {0};
5181 		u32 off, i, *cid_ptr;
5182 
5183 		rx_prods.bd_prod = 0;
5184 		rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
5185 		barrier();
5186 
5187 		cl_qzone_id = BNX2X_CL_QZONE_ID(bp, cli);
5188 
5189 		off = BAR_USTRORM_INTMEM +
5190 			(BNX2X_CHIP_IS_E2_PLUS(bp) ?
5191 			 USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
5192 			 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), cli));
5193 
5194 		for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
5195 			CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
5196 
5197 		set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
5198 
5199 		data = udev->l2_buf;
5200 		cid_ptr = udev->l2_buf + 12;
5201 
5202 		memset(data, 0, sizeof(*data));
5203 
5204 		cnic_init_bnx2x_tx_ring(dev, data);
5205 		cnic_init_bnx2x_rx_ring(dev, data);
5206 
5207 		data->general.fp_hsi_ver =  ETH_FP_HSI_VERSION;
5208 
5209 		l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
5210 		l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
5211 
5212 		set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5213 
5214 		cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
5215 			cid, ETH_CONNECTION_TYPE, &l5_data);
5216 
5217 		i = 0;
5218 		while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5219 		       ++i < 10)
5220 			msleep(1);
5221 
5222 		if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5223 			netdev_err(dev->netdev,
5224 				"iSCSI CLIENT_SETUP did not complete\n");
5225 		cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5226 		cnic_ring_ctl(dev, cid, cli, 1);
5227 		*cid_ptr = cid >> 4;
5228 		*(cid_ptr + 1) = cid * bp->db_size;
5229 		*(cid_ptr + 2) = UIO_USE_TX_DOORBELL;
5230 	}
5231 }
5232 
5233 static void cnic_shutdown_rings(struct cnic_dev *dev)
5234 {
5235 	struct cnic_local *cp = dev->cnic_priv;
5236 	struct cnic_uio_dev *udev = cp->udev;
5237 	void *rx_ring;
5238 
5239 	if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
5240 		return;
5241 
5242 	if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
5243 		cnic_shutdown_bnx2_rx_ring(dev);
5244 	} else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
5245 		u32 cli = cp->ethdev->iscsi_l2_client_id;
5246 		u32 cid = cp->ethdev->iscsi_l2_cid;
5247 		union l5cm_specific_data l5_data;
5248 		int i;
5249 
5250 		cnic_ring_ctl(dev, cid, cli, 0);
5251 
5252 		set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
5253 
5254 		l5_data.phy_address.lo = cli;
5255 		l5_data.phy_address.hi = 0;
5256 		cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
5257 			cid, ETH_CONNECTION_TYPE, &l5_data);
5258 		i = 0;
5259 		while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
5260 		       ++i < 10)
5261 			msleep(1);
5262 
5263 		if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
5264 			netdev_err(dev->netdev,
5265 				"iSCSI CLIENT_HALT did not complete\n");
5266 		cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
5267 
5268 		memset(&l5_data, 0, sizeof(l5_data));
5269 		cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
5270 			cid, NONE_CONNECTION_TYPE, &l5_data);
5271 		msleep(10);
5272 	}
5273 	clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
5274 	rx_ring = udev->l2_ring + CNIC_PAGE_SIZE;
5275 	memset(rx_ring, 0, CNIC_PAGE_SIZE);
5276 }
5277 
5278 static int cnic_register_netdev(struct cnic_dev *dev)
5279 {
5280 	struct cnic_local *cp = dev->cnic_priv;
5281 	struct cnic_eth_dev *ethdev = cp->ethdev;
5282 	int err;
5283 
5284 	if (!ethdev)
5285 		return -ENODEV;
5286 
5287 	if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
5288 		return 0;
5289 
5290 	err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
5291 	if (err)
5292 		netdev_err(dev->netdev, "register_cnic failed\n");
5293 
5294 	/* Read iSCSI config again.  On some bnx2x device, iSCSI config
5295 	 * can change after firmware is downloaded.
5296 	 */
5297 	dev->max_iscsi_conn = ethdev->max_iscsi_conn;
5298 	if (ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
5299 		dev->max_iscsi_conn = 0;
5300 
5301 	return err;
5302 }
5303 
5304 static void cnic_unregister_netdev(struct cnic_dev *dev)
5305 {
5306 	struct cnic_local *cp = dev->cnic_priv;
5307 	struct cnic_eth_dev *ethdev = cp->ethdev;
5308 
5309 	if (!ethdev)
5310 		return;
5311 
5312 	ethdev->drv_unregister_cnic(dev->netdev);
5313 }
5314 
5315 static int cnic_start_hw(struct cnic_dev *dev)
5316 {
5317 	struct cnic_local *cp = dev->cnic_priv;
5318 	struct cnic_eth_dev *ethdev = cp->ethdev;
5319 	int err;
5320 
5321 	if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
5322 		return -EALREADY;
5323 
5324 	dev->regview = ethdev->io_base;
5325 	pci_dev_get(dev->pcidev);
5326 	cp->func = PCI_FUNC(dev->pcidev->devfn);
5327 	cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
5328 	cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
5329 
5330 	err = cp->alloc_resc(dev);
5331 	if (err) {
5332 		netdev_err(dev->netdev, "allocate resource failure\n");
5333 		goto err1;
5334 	}
5335 
5336 	err = cp->start_hw(dev);
5337 	if (err)
5338 		goto err1;
5339 
5340 	err = cnic_cm_open(dev);
5341 	if (err)
5342 		goto err1;
5343 
5344 	set_bit(CNIC_F_CNIC_UP, &dev->flags);
5345 
5346 	cp->enable_int(dev);
5347 
5348 	return 0;
5349 
5350 err1:
5351 	if (ethdev->drv_state & CNIC_DRV_STATE_HANDLES_IRQ)
5352 		cp->stop_hw(dev);
5353 	else
5354 		cp->free_resc(dev);
5355 	pci_dev_put(dev->pcidev);
5356 	return err;
5357 }
5358 
5359 static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
5360 {
5361 	cnic_disable_bnx2_int_sync(dev);
5362 
5363 	cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
5364 	cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
5365 
5366 	cnic_init_context(dev, KWQ_CID);
5367 	cnic_init_context(dev, KCQ_CID);
5368 
5369 	cnic_setup_5709_context(dev, 0);
5370 	cnic_free_irq(dev);
5371 
5372 	cnic_free_resc(dev);
5373 }
5374 
5375 
5376 static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
5377 {
5378 	struct cnic_local *cp = dev->cnic_priv;
5379 	struct bnx2x *bp = netdev_priv(dev->netdev);
5380 	u32 hc_index = HC_INDEX_ISCSI_EQ_CONS;
5381 	u32 sb_id = cp->status_blk_num;
5382 	u32 idx_off, syn_off;
5383 
5384 	cnic_free_irq(dev);
5385 
5386 	if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
5387 		idx_off = offsetof(struct hc_status_block_e2, index_values) +
5388 			  (hc_index * sizeof(u16));
5389 
5390 		syn_off = CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hc_index, sb_id);
5391 	} else {
5392 		idx_off = offsetof(struct hc_status_block_e1x, index_values) +
5393 			  (hc_index * sizeof(u16));
5394 
5395 		syn_off = CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hc_index, sb_id);
5396 	}
5397 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM + syn_off, 0);
5398 	CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(sb_id) +
5399 		  idx_off, 0);
5400 
5401 	*cp->kcq1.hw_prod_idx_ptr = 0;
5402 	CNIC_WR(dev, BAR_CSTRORM_INTMEM +
5403 		CSTORM_ISCSI_EQ_CONS_OFFSET(bp->pfid, 0), 0);
5404 	CNIC_WR16(dev, cp->kcq1.io_addr, 0);
5405 	cnic_free_resc(dev);
5406 }
5407 
5408 static void cnic_stop_hw(struct cnic_dev *dev)
5409 {
5410 	if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
5411 		struct cnic_local *cp = dev->cnic_priv;
5412 		int i = 0;
5413 
5414 		/* Need to wait for the ring shutdown event to complete
5415 		 * before clearing the CNIC_UP flag.
5416 		 */
5417 		while (cp->udev && cp->udev->uio_dev != -1 && i < 15) {
5418 			msleep(100);
5419 			i++;
5420 		}
5421 		cnic_shutdown_rings(dev);
5422 		cp->stop_cm(dev);
5423 		cp->ethdev->drv_state &= ~CNIC_DRV_STATE_HANDLES_IRQ;
5424 		clear_bit(CNIC_F_CNIC_UP, &dev->flags);
5425 		RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
5426 		synchronize_rcu();
5427 		cnic_cm_shutdown(dev);
5428 		cp->stop_hw(dev);
5429 		pci_dev_put(dev->pcidev);
5430 	}
5431 }
5432 
5433 static void cnic_free_dev(struct cnic_dev *dev)
5434 {
5435 	int i = 0;
5436 
5437 	while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
5438 		msleep(100);
5439 		i++;
5440 	}
5441 	if (atomic_read(&dev->ref_count) != 0)
5442 		netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
5443 
5444 	netdev_info(dev->netdev, "Removed CNIC device\n");
5445 	dev_put(dev->netdev);
5446 	kfree(dev);
5447 }
5448 
5449 static int cnic_get_fc_npiv_tbl(struct cnic_dev *dev,
5450 				struct cnic_fc_npiv_tbl *npiv_tbl)
5451 {
5452 	struct cnic_local *cp = dev->cnic_priv;
5453 	struct bnx2x *bp = netdev_priv(dev->netdev);
5454 	int ret;
5455 
5456 	if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
5457 		return -EAGAIN;     /* bnx2x is down */
5458 
5459 	if (!BNX2X_CHIP_IS_E2_PLUS(bp))
5460 		return -EINVAL;
5461 
5462 	ret = cp->ethdev->drv_get_fc_npiv_tbl(dev->netdev, npiv_tbl);
5463 	return ret;
5464 }
5465 
5466 static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
5467 				       struct pci_dev *pdev)
5468 {
5469 	struct cnic_dev *cdev;
5470 	struct cnic_local *cp;
5471 	int alloc_size;
5472 
5473 	alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
5474 
5475 	cdev = kzalloc(alloc_size, GFP_KERNEL);
5476 	if (cdev == NULL)
5477 		return NULL;
5478 
5479 	cdev->netdev = dev;
5480 	cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
5481 	cdev->register_device = cnic_register_device;
5482 	cdev->unregister_device = cnic_unregister_device;
5483 	cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
5484 	cdev->get_fc_npiv_tbl = cnic_get_fc_npiv_tbl;
5485 	atomic_set(&cdev->ref_count, 0);
5486 
5487 	cp = cdev->cnic_priv;
5488 	cp->dev = cdev;
5489 	cp->l2_single_buf_size = 0x400;
5490 	cp->l2_rx_ring_size = 3;
5491 
5492 	spin_lock_init(&cp->cnic_ulp_lock);
5493 
5494 	netdev_info(dev, "Added CNIC device\n");
5495 
5496 	return cdev;
5497 }
5498 
5499 static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
5500 {
5501 	struct pci_dev *pdev;
5502 	struct cnic_dev *cdev;
5503 	struct cnic_local *cp;
5504 	struct bnx2 *bp = netdev_priv(dev);
5505 	struct cnic_eth_dev *ethdev = NULL;
5506 
5507 	if (bp->cnic_probe)
5508 		ethdev = (bp->cnic_probe)(dev);
5509 
5510 	if (!ethdev)
5511 		return NULL;
5512 
5513 	pdev = ethdev->pdev;
5514 	if (!pdev)
5515 		return NULL;
5516 
5517 	dev_hold(dev);
5518 	pci_dev_get(pdev);
5519 	if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
5520 	     pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
5521 	    (pdev->revision < 0x10)) {
5522 		pci_dev_put(pdev);
5523 		goto cnic_err;
5524 	}
5525 	pci_dev_put(pdev);
5526 
5527 	cdev = cnic_alloc_dev(dev, pdev);
5528 	if (cdev == NULL)
5529 		goto cnic_err;
5530 
5531 	set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
5532 	cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
5533 
5534 	cp = cdev->cnic_priv;
5535 	cp->ethdev = ethdev;
5536 	cdev->pcidev = pdev;
5537 	cp->chip_id = ethdev->chip_id;
5538 
5539 	cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5540 
5541 	cp->cnic_ops = &cnic_bnx2_ops;
5542 	cp->start_hw = cnic_start_bnx2_hw;
5543 	cp->stop_hw = cnic_stop_bnx2_hw;
5544 	cp->setup_pgtbl = cnic_setup_page_tbl;
5545 	cp->alloc_resc = cnic_alloc_bnx2_resc;
5546 	cp->free_resc = cnic_free_resc;
5547 	cp->start_cm = cnic_cm_init_bnx2_hw;
5548 	cp->stop_cm = cnic_cm_stop_bnx2_hw;
5549 	cp->enable_int = cnic_enable_bnx2_int;
5550 	cp->disable_int_sync = cnic_disable_bnx2_int_sync;
5551 	cp->close_conn = cnic_close_bnx2_conn;
5552 	return cdev;
5553 
5554 cnic_err:
5555 	dev_put(dev);
5556 	return NULL;
5557 }
5558 
5559 static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
5560 {
5561 	struct pci_dev *pdev;
5562 	struct cnic_dev *cdev;
5563 	struct cnic_local *cp;
5564 	struct bnx2x *bp = netdev_priv(dev);
5565 	struct cnic_eth_dev *ethdev = NULL;
5566 
5567 	if (bp->cnic_probe)
5568 		ethdev = bp->cnic_probe(dev);
5569 
5570 	if (!ethdev)
5571 		return NULL;
5572 
5573 	pdev = ethdev->pdev;
5574 	if (!pdev)
5575 		return NULL;
5576 
5577 	dev_hold(dev);
5578 	cdev = cnic_alloc_dev(dev, pdev);
5579 	if (cdev == NULL) {
5580 		dev_put(dev);
5581 		return NULL;
5582 	}
5583 
5584 	set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
5585 	cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
5586 
5587 	cp = cdev->cnic_priv;
5588 	cp->ethdev = ethdev;
5589 	cdev->pcidev = pdev;
5590 	cp->chip_id = ethdev->chip_id;
5591 
5592 	cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
5593 
5594 	if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
5595 		cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
5596 	if (CNIC_SUPPORTS_FCOE(bp)) {
5597 		cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
5598 		cdev->max_fcoe_exchanges = ethdev->max_fcoe_exchanges;
5599 	}
5600 
5601 	if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
5602 		cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
5603 
5604 	memcpy(cdev->mac_addr, ethdev->iscsi_mac, ETH_ALEN);
5605 
5606 	cp->cnic_ops = &cnic_bnx2x_ops;
5607 	cp->start_hw = cnic_start_bnx2x_hw;
5608 	cp->stop_hw = cnic_stop_bnx2x_hw;
5609 	cp->setup_pgtbl = cnic_setup_page_tbl_le;
5610 	cp->alloc_resc = cnic_alloc_bnx2x_resc;
5611 	cp->free_resc = cnic_free_resc;
5612 	cp->start_cm = cnic_cm_init_bnx2x_hw;
5613 	cp->stop_cm = cnic_cm_stop_bnx2x_hw;
5614 	cp->enable_int = cnic_enable_bnx2x_int;
5615 	cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
5616 	if (BNX2X_CHIP_IS_E2_PLUS(bp)) {
5617 		cp->ack_int = cnic_ack_bnx2x_e2_msix;
5618 		cp->arm_int = cnic_arm_bnx2x_e2_msix;
5619 	} else {
5620 		cp->ack_int = cnic_ack_bnx2x_msix;
5621 		cp->arm_int = cnic_arm_bnx2x_msix;
5622 	}
5623 	cp->close_conn = cnic_close_bnx2x_conn;
5624 	return cdev;
5625 }
5626 
5627 static struct cnic_dev *is_cnic_dev(struct net_device *dev)
5628 {
5629 	struct ethtool_drvinfo drvinfo;
5630 	struct cnic_dev *cdev = NULL;
5631 
5632 	if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5633 		memset(&drvinfo, 0, sizeof(drvinfo));
5634 		dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5635 
5636 		if (!strcmp(drvinfo.driver, "bnx2"))
5637 			cdev = init_bnx2_cnic(dev);
5638 		if (!strcmp(drvinfo.driver, "bnx2x"))
5639 			cdev = init_bnx2x_cnic(dev);
5640 		if (cdev) {
5641 			write_lock(&cnic_dev_lock);
5642 			list_add(&cdev->list, &cnic_dev_list);
5643 			write_unlock(&cnic_dev_lock);
5644 		}
5645 	}
5646 	return cdev;
5647 }
5648 
5649 static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
5650 			      u16 vlan_id)
5651 {
5652 	int if_type;
5653 
5654 	for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
5655 		struct cnic_ulp_ops *ulp_ops;
5656 		void *ctx;
5657 
5658 		mutex_lock(&cnic_lock);
5659 		ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
5660 						lockdep_is_held(&cnic_lock));
5661 		if (!ulp_ops || !ulp_ops->indicate_netevent) {
5662 			mutex_unlock(&cnic_lock);
5663 			continue;
5664 		}
5665 
5666 		ctx = cp->ulp_handle[if_type];
5667 
5668 		set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
5669 		mutex_unlock(&cnic_lock);
5670 
5671 		ulp_ops->indicate_netevent(ctx, event, vlan_id);
5672 
5673 		clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
5674 	}
5675 }
5676 
5677 /* netdev event handler */
5678 static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
5679 							 void *ptr)
5680 {
5681 	struct net_device *netdev = netdev_notifier_info_to_dev(ptr);
5682 	struct cnic_dev *dev;
5683 	int new_dev = 0;
5684 
5685 	dev = cnic_from_netdev(netdev);
5686 
5687 	if (!dev && event == NETDEV_REGISTER) {
5688 		/* Check for the hot-plug device */
5689 		dev = is_cnic_dev(netdev);
5690 		if (dev) {
5691 			new_dev = 1;
5692 			cnic_hold(dev);
5693 		}
5694 	}
5695 	if (dev) {
5696 		struct cnic_local *cp = dev->cnic_priv;
5697 
5698 		if (new_dev)
5699 			cnic_ulp_init(dev);
5700 		else if (event == NETDEV_UNREGISTER)
5701 			cnic_ulp_exit(dev);
5702 
5703 		if (event == NETDEV_UP) {
5704 			if (cnic_register_netdev(dev) != 0) {
5705 				cnic_put(dev);
5706 				goto done;
5707 			}
5708 			if (!cnic_start_hw(dev))
5709 				cnic_ulp_start(dev);
5710 		}
5711 
5712 		cnic_rcv_netevent(cp, event, 0);
5713 
5714 		if (event == NETDEV_GOING_DOWN) {
5715 			cnic_ulp_stop(dev);
5716 			cnic_stop_hw(dev);
5717 			cnic_unregister_netdev(dev);
5718 		} else if (event == NETDEV_UNREGISTER) {
5719 			write_lock(&cnic_dev_lock);
5720 			list_del_init(&dev->list);
5721 			write_unlock(&cnic_dev_lock);
5722 
5723 			cnic_put(dev);
5724 			cnic_free_dev(dev);
5725 			goto done;
5726 		}
5727 		cnic_put(dev);
5728 	} else {
5729 		struct net_device *realdev;
5730 		u16 vid;
5731 
5732 		vid = cnic_get_vlan(netdev, &realdev);
5733 		if (realdev) {
5734 			dev = cnic_from_netdev(realdev);
5735 			if (dev) {
5736 				vid |= VLAN_CFI_MASK;	/* make non-zero */
5737 				cnic_rcv_netevent(dev->cnic_priv, event, vid);
5738 				cnic_put(dev);
5739 			}
5740 		}
5741 	}
5742 done:
5743 	return NOTIFY_DONE;
5744 }
5745 
5746 static struct notifier_block cnic_netdev_notifier = {
5747 	.notifier_call = cnic_netdev_event
5748 };
5749 
5750 static void cnic_release(void)
5751 {
5752 	struct cnic_uio_dev *udev;
5753 
5754 	while (!list_empty(&cnic_udev_list)) {
5755 		udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
5756 				  list);
5757 		cnic_free_uio(udev);
5758 	}
5759 }
5760 
5761 static int __init cnic_init(void)
5762 {
5763 	int rc = 0;
5764 
5765 	pr_info("%s", version);
5766 
5767 	rc = register_netdevice_notifier(&cnic_netdev_notifier);
5768 	if (rc) {
5769 		cnic_release();
5770 		return rc;
5771 	}
5772 
5773 	cnic_wq = create_singlethread_workqueue("cnic_wq");
5774 	if (!cnic_wq) {
5775 		cnic_release();
5776 		unregister_netdevice_notifier(&cnic_netdev_notifier);
5777 		return -ENOMEM;
5778 	}
5779 
5780 	return 0;
5781 }
5782 
5783 static void __exit cnic_exit(void)
5784 {
5785 	unregister_netdevice_notifier(&cnic_netdev_notifier);
5786 	cnic_release();
5787 	destroy_workqueue(cnic_wq);
5788 }
5789 
5790 module_init(cnic_init);
5791 module_exit(cnic_exit);
5792