1ae5c42f0SMichael Chan /* Broadcom NetXtreme-C/E network driver.
2ae5c42f0SMichael Chan  *
3ae5c42f0SMichael Chan  * Copyright (c) 2021 Broadcom Inc.
4ae5c42f0SMichael Chan  *
5ae5c42f0SMichael Chan  * This program is free software; you can redistribute it and/or modify
6ae5c42f0SMichael Chan  * it under the terms of the GNU General Public License as published by
7ae5c42f0SMichael Chan  * the Free Software Foundation.
8ae5c42f0SMichael Chan  */
9ae5c42f0SMichael Chan 
10ae5c42f0SMichael Chan #ifndef BNXT_PTP_H
11ae5c42f0SMichael Chan #define BNXT_PTP_H
12ae5c42f0SMichael Chan 
13118612d5SMichael Chan #define BNXT_PTP_GRC_WIN	5
14118612d5SMichael Chan #define BNXT_PTP_GRC_WIN_BASE	0x5000
15118612d5SMichael Chan 
16118612d5SMichael Chan #define BNXT_MAX_PHC_DRIFT	31000000
17118612d5SMichael Chan #define BNXT_LO_TIMER_MASK	0x0000ffffffffUL
18118612d5SMichael Chan #define BNXT_HI_TIMER_MASK	0xffff00000000UL
19118612d5SMichael Chan 
20118612d5SMichael Chan #define BNXT_PTP_QTS_TIMEOUT	1000
21118612d5SMichael Chan #define BNXT_PTP_QTS_TX_ENABLES	(PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID |	\
22118612d5SMichael Chan 				 PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT)
23118612d5SMichael Chan 
24caf3eedbSPavan Chebbi struct pps_pin {
25*9e518f25SPavan Chebbi 	u8 event;
26caf3eedbSPavan Chebbi 	u8 usage;
27*9e518f25SPavan Chebbi 	u8 state;
28caf3eedbSPavan Chebbi };
29caf3eedbSPavan Chebbi 
30*9e518f25SPavan Chebbi #define TSIO_PIN_VALID(pin) ((pin) < (BNXT_MAX_TSIO_PINS))
31*9e518f25SPavan Chebbi 
32caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_DISABLE	0
33caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_ENABLE	1
34caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_NONE	0
35caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_PPS_IN	1
36caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_PPS_OUT	2
37caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_SYNC_IN	3
38caf3eedbSPavan Chebbi #define BNXT_PPS_PIN_SYNC_OUT	4
39caf3eedbSPavan Chebbi 
40caf3eedbSPavan Chebbi #define BNXT_PPS_EVENT_INTERNAL	1
41caf3eedbSPavan Chebbi #define BNXT_PPS_EVENT_EXTERNAL	2
42caf3eedbSPavan Chebbi 
43caf3eedbSPavan Chebbi struct bnxt_pps {
44caf3eedbSPavan Chebbi 	u8 num_pins;
45caf3eedbSPavan Chebbi #define BNXT_MAX_TSIO_PINS	4
46caf3eedbSPavan Chebbi 	struct pps_pin pins[BNXT_MAX_TSIO_PINS];
47caf3eedbSPavan Chebbi };
48caf3eedbSPavan Chebbi 
49ae5c42f0SMichael Chan struct bnxt_ptp_cfg {
50ae5c42f0SMichael Chan 	struct ptp_clock_info	ptp_info;
51ae5c42f0SMichael Chan 	struct ptp_clock	*ptp_clock;
52ae5c42f0SMichael Chan 	struct cyclecounter	cc;
53ae5c42f0SMichael Chan 	struct timecounter	tc;
54caf3eedbSPavan Chebbi 	struct bnxt_pps		pps_info;
55ae5c42f0SMichael Chan 	/* serialize timecounter access */
56ae5c42f0SMichael Chan 	spinlock_t		ptp_lock;
57ae5c42f0SMichael Chan 	struct sk_buff		*tx_skb;
58ae5c42f0SMichael Chan 	u64			current_time;
59ae5c42f0SMichael Chan 	u64			old_time;
60ae5c42f0SMichael Chan 	unsigned long		next_period;
61ae5c42f0SMichael Chan 	u16			tx_seqid;
62ae5c42f0SMichael Chan 	struct bnxt		*bp;
63ae5c42f0SMichael Chan 	atomic_t		tx_avail;
64ae5c42f0SMichael Chan #define BNXT_MAX_TX_TS	1
65ae5c42f0SMichael Chan 	u16			rxctl;
66ae5c42f0SMichael Chan #define BNXT_PTP_MSG_SYNC			(1 << 0)
67ae5c42f0SMichael Chan #define BNXT_PTP_MSG_DELAY_REQ			(1 << 1)
68ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_REQ			(1 << 2)
69ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_RESP		(1 << 3)
70ae5c42f0SMichael Chan #define BNXT_PTP_MSG_FOLLOW_UP			(1 << 8)
71ae5c42f0SMichael Chan #define BNXT_PTP_MSG_DELAY_RESP			(1 << 9)
72ae5c42f0SMichael Chan #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP	(1 << 10)
73ae5c42f0SMichael Chan #define BNXT_PTP_MSG_ANNOUNCE			(1 << 11)
74ae5c42f0SMichael Chan #define BNXT_PTP_MSG_SIGNALING			(1 << 12)
75ae5c42f0SMichael Chan #define BNXT_PTP_MSG_MANAGEMENT			(1 << 13)
76ae5c42f0SMichael Chan #define BNXT_PTP_MSG_EVENTS		(BNXT_PTP_MSG_SYNC |		\
77ae5c42f0SMichael Chan 					 BNXT_PTP_MSG_DELAY_REQ |	\
78ae5c42f0SMichael Chan 					 BNXT_PTP_MSG_PDELAY_REQ |	\
79ae5c42f0SMichael Chan 					 BNXT_PTP_MSG_PDELAY_RESP)
80ae5c42f0SMichael Chan 	u8			tx_tstamp_en:1;
81ae5c42f0SMichael Chan 	int			rx_filter;
82ae5c42f0SMichael Chan 
83ae5c42f0SMichael Chan 	u32			refclk_regs[2];
84ae5c42f0SMichael Chan 	u32			refclk_mapped_regs[2];
85ae5c42f0SMichael Chan };
86118612d5SMichael Chan 
877f5515d1SPavan Chebbi #if BITS_PER_LONG == 32
887f5515d1SPavan Chebbi #define BNXT_READ_TIME64(ptp, dst, src)		\
897f5515d1SPavan Chebbi do {						\
907f5515d1SPavan Chebbi 	spin_lock_bh(&(ptp)->ptp_lock);		\
917f5515d1SPavan Chebbi 	(dst) = (src);				\
927f5515d1SPavan Chebbi 	spin_unlock_bh(&(ptp)->ptp_lock);	\
937f5515d1SPavan Chebbi } while (0)
947f5515d1SPavan Chebbi #else
957f5515d1SPavan Chebbi #define BNXT_READ_TIME64(ptp, dst, src)		\
967f5515d1SPavan Chebbi 	((dst) = READ_ONCE(src))
977f5515d1SPavan Chebbi #endif
987f5515d1SPavan Chebbi 
9983bb623cSPavan Chebbi int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id);
100*9e518f25SPavan Chebbi void bnxt_ptp_reapply_pps(struct bnxt *bp);
101118612d5SMichael Chan int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);
102118612d5SMichael Chan int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
10383bb623cSPavan Chebbi int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
1047f5515d1SPavan Chebbi int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
105118612d5SMichael Chan int bnxt_ptp_init(struct bnxt *bp);
106118612d5SMichael Chan void bnxt_ptp_clear(struct bnxt *bp);
107ae5c42f0SMichael Chan #endif
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