1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * DO NOT MODIFY!!! This file is automatically generated. 11 */ 12 13 #ifndef _BNXT_HSI_H_ 14 #define _BNXT_HSI_H_ 15 16 /* hwrm_cmd_hdr (size:128b/16B) */ 17 struct hwrm_cmd_hdr { 18 __le16 req_type; 19 __le16 cmpl_ring; 20 __le16 seq_id; 21 __le16 target_id; 22 __le64 resp_addr; 23 }; 24 25 /* hwrm_resp_hdr (size:64b/8B) */ 26 struct hwrm_resp_hdr { 27 __le16 error_code; 28 __le16 req_type; 29 __le16 seq_id; 30 __le16 resp_len; 31 }; 32 33 #define CMD_DISCR_TLV_ENCAP 0x8000UL 34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 35 36 37 #define TLV_TYPE_HWRM_REQUEST 0x1UL 38 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 39 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 40 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL 41 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL 42 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 43 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 44 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 45 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 46 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL 47 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 48 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 49 50 51 /* tlv (size:64b/8B) */ 52 struct tlv { 53 __le16 cmd_discr; 54 u8 reserved_8b; 55 u8 flags; 56 #define TLV_FLAGS_MORE 0x1UL 57 #define TLV_FLAGS_MORE_LAST 0x0UL 58 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 59 #define TLV_FLAGS_REQUIRED 0x2UL 60 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 61 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 62 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 63 __le16 tlv_type; 64 __le16 length; 65 }; 66 67 /* input (size:128b/16B) */ 68 struct input { 69 __le16 req_type; 70 __le16 cmpl_ring; 71 __le16 seq_id; 72 __le16 target_id; 73 __le64 resp_addr; 74 }; 75 76 /* output (size:64b/8B) */ 77 struct output { 78 __le16 error_code; 79 __le16 req_type; 80 __le16 seq_id; 81 __le16 resp_len; 82 }; 83 84 /* hwrm_short_input (size:128b/16B) */ 85 struct hwrm_short_input { 86 __le16 req_type; 87 __le16 signature; 88 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 89 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 90 __le16 unused_0; 91 __le16 size; 92 __le64 req_addr; 93 }; 94 95 /* cmd_nums (size:64b/8B) */ 96 struct cmd_nums { 97 __le16 req_type; 98 #define HWRM_VER_GET 0x0UL 99 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 100 #define HWRM_FUNC_VF_CFG 0xfUL 101 #define HWRM_RESERVED1 0x10UL 102 #define HWRM_FUNC_RESET 0x11UL 103 #define HWRM_FUNC_GETFID 0x12UL 104 #define HWRM_FUNC_VF_ALLOC 0x13UL 105 #define HWRM_FUNC_VF_FREE 0x14UL 106 #define HWRM_FUNC_QCAPS 0x15UL 107 #define HWRM_FUNC_QCFG 0x16UL 108 #define HWRM_FUNC_CFG 0x17UL 109 #define HWRM_FUNC_QSTATS 0x18UL 110 #define HWRM_FUNC_CLR_STATS 0x19UL 111 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 112 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 113 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 114 #define HWRM_FUNC_DRV_RGTR 0x1dUL 115 #define HWRM_FUNC_DRV_QVER 0x1eUL 116 #define HWRM_FUNC_BUF_RGTR 0x1fUL 117 #define HWRM_PORT_PHY_CFG 0x20UL 118 #define HWRM_PORT_MAC_CFG 0x21UL 119 #define HWRM_PORT_TS_QUERY 0x22UL 120 #define HWRM_PORT_QSTATS 0x23UL 121 #define HWRM_PORT_LPBK_QSTATS 0x24UL 122 #define HWRM_PORT_CLR_STATS 0x25UL 123 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 124 #define HWRM_PORT_PHY_QCFG 0x27UL 125 #define HWRM_PORT_MAC_QCFG 0x28UL 126 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 127 #define HWRM_PORT_PHY_QCAPS 0x2aUL 128 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 129 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 130 #define HWRM_PORT_LED_CFG 0x2dUL 131 #define HWRM_PORT_LED_QCFG 0x2eUL 132 #define HWRM_PORT_LED_QCAPS 0x2fUL 133 #define HWRM_QUEUE_QPORTCFG 0x30UL 134 #define HWRM_QUEUE_QCFG 0x31UL 135 #define HWRM_QUEUE_CFG 0x32UL 136 #define HWRM_FUNC_VLAN_CFG 0x33UL 137 #define HWRM_FUNC_VLAN_QCFG 0x34UL 138 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 139 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 140 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 141 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 142 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 143 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 144 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 145 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 146 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 147 #define HWRM_VNIC_ALLOC 0x40UL 148 #define HWRM_VNIC_FREE 0x41UL 149 #define HWRM_VNIC_CFG 0x42UL 150 #define HWRM_VNIC_QCFG 0x43UL 151 #define HWRM_VNIC_TPA_CFG 0x44UL 152 #define HWRM_VNIC_TPA_QCFG 0x45UL 153 #define HWRM_VNIC_RSS_CFG 0x46UL 154 #define HWRM_VNIC_RSS_QCFG 0x47UL 155 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 156 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 157 #define HWRM_VNIC_QCAPS 0x4aUL 158 #define HWRM_RING_ALLOC 0x50UL 159 #define HWRM_RING_FREE 0x51UL 160 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 161 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 162 #define HWRM_RING_RESET 0x5eUL 163 #define HWRM_RING_GRP_ALLOC 0x60UL 164 #define HWRM_RING_GRP_FREE 0x61UL 165 #define HWRM_RESERVED5 0x64UL 166 #define HWRM_RESERVED6 0x65UL 167 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 168 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 169 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 170 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 171 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 172 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 173 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 174 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 175 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 176 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 177 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 178 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 179 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 180 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 181 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 182 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 183 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 184 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 185 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 186 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 187 #define HWRM_STAT_CTX_ALLOC 0xb0UL 188 #define HWRM_STAT_CTX_FREE 0xb1UL 189 #define HWRM_STAT_CTX_QUERY 0xb2UL 190 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 191 #define HWRM_FW_RESET 0xc0UL 192 #define HWRM_FW_QSTATUS 0xc1UL 193 #define HWRM_FW_SET_TIME 0xc8UL 194 #define HWRM_FW_GET_TIME 0xc9UL 195 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 196 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 197 #define HWRM_FW_IPC_MAILBOX 0xccUL 198 #define HWRM_EXEC_FWD_RESP 0xd0UL 199 #define HWRM_REJECT_FWD_RESP 0xd1UL 200 #define HWRM_FWD_RESP 0xd2UL 201 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 202 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 203 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 204 #define HWRM_WOL_FILTER_FREE 0xf1UL 205 #define HWRM_WOL_FILTER_QCFG 0xf2UL 206 #define HWRM_WOL_REASON_QCFG 0xf3UL 207 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 208 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 209 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 210 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 211 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 212 #define HWRM_CFA_VFR_ALLOC 0xfdUL 213 #define HWRM_CFA_VFR_FREE 0xfeUL 214 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 215 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 216 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 217 #define HWRM_CFA_FLOW_ALLOC 0x103UL 218 #define HWRM_CFA_FLOW_FREE 0x104UL 219 #define HWRM_CFA_FLOW_FLUSH 0x105UL 220 #define HWRM_CFA_FLOW_STATS 0x106UL 221 #define HWRM_CFA_FLOW_INFO 0x107UL 222 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 223 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 224 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 225 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 226 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 227 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 228 #define HWRM_CFA_PAIR_FREE 0x10eUL 229 #define HWRM_CFA_PAIR_INFO 0x10fUL 230 #define HWRM_FW_IPC_MSG 0x110UL 231 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 232 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 233 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 234 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 235 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 236 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 237 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 238 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 239 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 240 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 241 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 242 #define HWRM_ENGINE_QG_QUERY 0x13dUL 243 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 244 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 245 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 246 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 247 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 248 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 249 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 250 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 251 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 252 #define HWRM_ENGINE_SG_QUERY 0x147UL 253 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 254 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 255 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 256 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 257 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 258 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 259 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 260 #define HWRM_ENGINE_STATS_QUERY 0x157UL 261 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 262 #define HWRM_ENGINE_RQ_FREE 0x15fUL 263 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 264 #define HWRM_ENGINE_CQ_FREE 0x161UL 265 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 266 #define HWRM_ENGINE_NQ_FREE 0x163UL 267 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 268 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 269 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 270 #define HWRM_SELFTEST_QLIST 0x200UL 271 #define HWRM_SELFTEST_EXEC 0x201UL 272 #define HWRM_SELFTEST_IRQ 0x202UL 273 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 274 #define HWRM_DBG_READ_DIRECT 0xff10UL 275 #define HWRM_DBG_READ_INDIRECT 0xff11UL 276 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 277 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 278 #define HWRM_DBG_DUMP 0xff14UL 279 #define HWRM_DBG_ERASE_NVM 0xff15UL 280 #define HWRM_DBG_CFG 0xff16UL 281 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 282 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 283 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 284 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 285 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 286 #define HWRM_NVM_FLUSH 0xfff0UL 287 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 288 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 289 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 290 #define HWRM_NVM_MODIFY 0xfff4UL 291 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 292 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 293 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 294 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 295 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 296 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 297 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 298 #define HWRM_NVM_RAW_DUMP 0xfffcUL 299 #define HWRM_NVM_READ 0xfffdUL 300 #define HWRM_NVM_WRITE 0xfffeUL 301 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 302 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 303 __le16 unused_0[3]; 304 }; 305 306 /* ret_codes (size:64b/8B) */ 307 struct ret_codes { 308 __le16 error_code; 309 #define HWRM_ERR_CODE_SUCCESS 0x0UL 310 #define HWRM_ERR_CODE_FAIL 0x1UL 311 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 312 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 313 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 314 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 315 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 316 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 317 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 318 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 319 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 320 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 321 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 322 __le16 unused_0[3]; 323 }; 324 325 /* hwrm_err_output (size:128b/16B) */ 326 struct hwrm_err_output { 327 __le16 error_code; 328 __le16 req_type; 329 __le16 seq_id; 330 __le16 resp_len; 331 __le32 opaque_0; 332 __le16 opaque_1; 333 u8 cmd_err; 334 u8 valid; 335 }; 336 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 337 #define HWRM_MAX_REQ_LEN 128 338 #define HWRM_MAX_RESP_LEN 280 339 #define HW_HASH_INDEX_SIZE 0x80 340 #define HW_HASH_KEY_SIZE 40 341 #define HWRM_RESP_VALID_KEY 1 342 #define HWRM_VERSION_MAJOR 1 343 #define HWRM_VERSION_MINOR 9 344 #define HWRM_VERSION_UPDATE 0 345 #define HWRM_VERSION_RSVD 0 346 #define HWRM_VERSION_STR "1.9.0.0" 347 348 /* hwrm_ver_get_input (size:192b/24B) */ 349 struct hwrm_ver_get_input { 350 __le16 req_type; 351 __le16 cmpl_ring; 352 __le16 seq_id; 353 __le16 target_id; 354 __le64 resp_addr; 355 u8 hwrm_intf_maj; 356 u8 hwrm_intf_min; 357 u8 hwrm_intf_upd; 358 u8 unused_0[5]; 359 }; 360 361 /* hwrm_ver_get_output (size:1408b/176B) */ 362 struct hwrm_ver_get_output { 363 __le16 error_code; 364 __le16 req_type; 365 __le16 seq_id; 366 __le16 resp_len; 367 u8 hwrm_intf_maj_8b; 368 u8 hwrm_intf_min_8b; 369 u8 hwrm_intf_upd_8b; 370 u8 hwrm_intf_rsvd_8b; 371 u8 hwrm_fw_maj_8b; 372 u8 hwrm_fw_min_8b; 373 u8 hwrm_fw_bld_8b; 374 u8 hwrm_fw_rsvd_8b; 375 u8 mgmt_fw_maj_8b; 376 u8 mgmt_fw_min_8b; 377 u8 mgmt_fw_bld_8b; 378 u8 mgmt_fw_rsvd_8b; 379 u8 netctrl_fw_maj_8b; 380 u8 netctrl_fw_min_8b; 381 u8 netctrl_fw_bld_8b; 382 u8 netctrl_fw_rsvd_8b; 383 __le32 dev_caps_cfg; 384 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 385 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 386 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 387 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 388 u8 roce_fw_maj_8b; 389 u8 roce_fw_min_8b; 390 u8 roce_fw_bld_8b; 391 u8 roce_fw_rsvd_8b; 392 char hwrm_fw_name[16]; 393 char mgmt_fw_name[16]; 394 char netctrl_fw_name[16]; 395 u8 reserved2[16]; 396 char roce_fw_name[16]; 397 __le16 chip_num; 398 u8 chip_rev; 399 u8 chip_metal; 400 u8 chip_bond_id; 401 u8 chip_platform_type; 402 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 403 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 404 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 405 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 406 __le16 max_req_win_len; 407 __le16 max_resp_len; 408 __le16 def_req_timeout; 409 u8 flags; 410 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 411 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 412 u8 unused_0[2]; 413 u8 always_1; 414 __le16 hwrm_intf_major; 415 __le16 hwrm_intf_minor; 416 __le16 hwrm_intf_build; 417 __le16 hwrm_intf_patch; 418 __le16 hwrm_fw_major; 419 __le16 hwrm_fw_minor; 420 __le16 hwrm_fw_build; 421 __le16 hwrm_fw_patch; 422 __le16 mgmt_fw_major; 423 __le16 mgmt_fw_minor; 424 __le16 mgmt_fw_build; 425 __le16 mgmt_fw_patch; 426 __le16 netctrl_fw_major; 427 __le16 netctrl_fw_minor; 428 __le16 netctrl_fw_build; 429 __le16 netctrl_fw_patch; 430 __le16 roce_fw_major; 431 __le16 roce_fw_minor; 432 __le16 roce_fw_build; 433 __le16 roce_fw_patch; 434 __le16 max_ext_req_len; 435 u8 unused_1[5]; 436 u8 valid; 437 }; 438 439 /* eject_cmpl (size:128b/16B) */ 440 struct eject_cmpl { 441 __le16 type; 442 #define EJECT_CMPL_TYPE_MASK 0x3fUL 443 #define EJECT_CMPL_TYPE_SFT 0 444 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 445 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 446 __le16 len; 447 __le32 opaque; 448 __le32 v; 449 #define EJECT_CMPL_V 0x1UL 450 __le32 unused_2; 451 }; 452 453 /* hwrm_cmpl (size:128b/16B) */ 454 struct hwrm_cmpl { 455 __le16 type; 456 #define CMPL_TYPE_MASK 0x3fUL 457 #define CMPL_TYPE_SFT 0 458 #define CMPL_TYPE_HWRM_DONE 0x20UL 459 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 460 __le16 sequence_id; 461 __le32 unused_1; 462 __le32 v; 463 #define CMPL_V 0x1UL 464 __le32 unused_3; 465 }; 466 467 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 468 struct hwrm_fwd_req_cmpl { 469 __le16 req_len_type; 470 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 471 #define FWD_REQ_CMPL_TYPE_SFT 0 472 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 473 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 474 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 475 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 476 __le16 source_id; 477 __le32 unused0; 478 __le32 req_buf_addr_v[2]; 479 #define FWD_REQ_CMPL_V 0x1UL 480 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 481 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 482 }; 483 484 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 485 struct hwrm_fwd_resp_cmpl { 486 __le16 type; 487 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 488 #define FWD_RESP_CMPL_TYPE_SFT 0 489 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 490 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 491 __le16 source_id; 492 __le16 resp_len; 493 __le16 unused_1; 494 __le32 resp_buf_addr_v[2]; 495 #define FWD_RESP_CMPL_V 0x1UL 496 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 497 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 498 }; 499 500 /* hwrm_async_event_cmpl (size:128b/16B) */ 501 struct hwrm_async_event_cmpl { 502 __le16 type; 503 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 504 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 505 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 506 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 507 __le16 event_id; 508 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 509 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 510 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 511 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 512 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 513 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 514 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 515 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 516 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 517 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 518 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 519 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 520 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 521 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 522 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 523 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 524 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 525 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 526 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 527 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 528 __le32 event_data2; 529 u8 opaque_v; 530 #define ASYNC_EVENT_CMPL_V 0x1UL 531 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 532 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 533 u8 timestamp_lo; 534 __le16 timestamp_hi; 535 __le32 event_data1; 536 }; 537 538 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 539 struct hwrm_async_event_cmpl_link_status_change { 540 __le16 type; 541 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 542 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 543 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 544 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 545 __le16 event_id; 546 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 547 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 548 __le32 event_data2; 549 u8 opaque_v; 550 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 551 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 552 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 553 u8 timestamp_lo; 554 __le16 timestamp_hi; 555 __le32 event_data1; 556 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 557 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 558 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 559 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 560 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 561 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 562 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 563 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 564 }; 565 566 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 567 struct hwrm_async_event_cmpl_port_conn_not_allowed { 568 __le16 type; 569 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 570 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 571 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 572 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 573 __le16 event_id; 574 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 575 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 576 __le32 event_data2; 577 u8 opaque_v; 578 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 579 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 580 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 581 u8 timestamp_lo; 582 __le16 timestamp_hi; 583 __le32 event_data1; 584 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 585 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 586 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 587 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 588 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 589 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 590 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 591 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 592 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 593 }; 594 595 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 596 struct hwrm_async_event_cmpl_link_speed_cfg_change { 597 __le16 type; 598 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 599 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 600 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 601 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 602 __le16 event_id; 603 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 604 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 605 __le32 event_data2; 606 u8 opaque_v; 607 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 608 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 609 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 610 u8 timestamp_lo; 611 __le16 timestamp_hi; 612 __le32 event_data1; 613 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 614 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 615 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 616 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 617 }; 618 619 /* hwrm_async_event_cmpl_pf_drvr_unload (size:128b/16B) */ 620 struct hwrm_async_event_cmpl_pf_drvr_unload { 621 __le16 type; 622 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 623 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 624 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 625 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 626 __le16 event_id; 627 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 628 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_LAST ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 629 __le32 event_data2; 630 u8 opaque_v; 631 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 632 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 633 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 634 u8 timestamp_lo; 635 __le16 timestamp_hi; 636 __le32 event_data1; 637 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 638 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 639 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 640 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 641 }; 642 643 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 644 struct hwrm_async_event_cmpl_vf_cfg_change { 645 __le16 type; 646 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 647 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 648 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 649 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 650 __le16 event_id; 651 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 652 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 653 __le32 event_data2; 654 u8 opaque_v; 655 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 656 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 657 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 658 u8 timestamp_lo; 659 __le16 timestamp_hi; 660 __le32 event_data1; 661 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 662 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 663 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 664 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 665 }; 666 667 /* hwrm_func_reset_input (size:192b/24B) */ 668 struct hwrm_func_reset_input { 669 __le16 req_type; 670 __le16 cmpl_ring; 671 __le16 seq_id; 672 __le16 target_id; 673 __le64 resp_addr; 674 __le32 enables; 675 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 676 __le16 vf_id; 677 u8 func_reset_level; 678 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 679 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 680 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 681 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 682 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 683 u8 unused_0; 684 }; 685 686 /* hwrm_func_reset_output (size:128b/16B) */ 687 struct hwrm_func_reset_output { 688 __le16 error_code; 689 __le16 req_type; 690 __le16 seq_id; 691 __le16 resp_len; 692 u8 unused_0[7]; 693 u8 valid; 694 }; 695 696 /* hwrm_func_getfid_input (size:192b/24B) */ 697 struct hwrm_func_getfid_input { 698 __le16 req_type; 699 __le16 cmpl_ring; 700 __le16 seq_id; 701 __le16 target_id; 702 __le64 resp_addr; 703 __le32 enables; 704 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 705 __le16 pci_id; 706 u8 unused_0[2]; 707 }; 708 709 /* hwrm_func_getfid_output (size:128b/16B) */ 710 struct hwrm_func_getfid_output { 711 __le16 error_code; 712 __le16 req_type; 713 __le16 seq_id; 714 __le16 resp_len; 715 __le16 fid; 716 u8 unused_0[5]; 717 u8 valid; 718 }; 719 720 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 721 struct hwrm_func_vf_alloc_input { 722 __le16 req_type; 723 __le16 cmpl_ring; 724 __le16 seq_id; 725 __le16 target_id; 726 __le64 resp_addr; 727 __le32 enables; 728 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 729 __le16 first_vf_id; 730 __le16 num_vfs; 731 }; 732 733 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 734 struct hwrm_func_vf_alloc_output { 735 __le16 error_code; 736 __le16 req_type; 737 __le16 seq_id; 738 __le16 resp_len; 739 __le16 first_vf_id; 740 u8 unused_0[5]; 741 u8 valid; 742 }; 743 744 /* hwrm_func_vf_free_input (size:192b/24B) */ 745 struct hwrm_func_vf_free_input { 746 __le16 req_type; 747 __le16 cmpl_ring; 748 __le16 seq_id; 749 __le16 target_id; 750 __le64 resp_addr; 751 __le32 enables; 752 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 753 __le16 first_vf_id; 754 __le16 num_vfs; 755 }; 756 757 /* hwrm_func_vf_free_output (size:128b/16B) */ 758 struct hwrm_func_vf_free_output { 759 __le16 error_code; 760 __le16 req_type; 761 __le16 seq_id; 762 __le16 resp_len; 763 u8 unused_0[7]; 764 u8 valid; 765 }; 766 767 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 768 struct hwrm_func_vf_cfg_input { 769 __le16 req_type; 770 __le16 cmpl_ring; 771 __le16 seq_id; 772 __le16 target_id; 773 __le64 resp_addr; 774 __le32 enables; 775 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 776 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 777 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 778 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 779 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 780 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 781 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 782 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 783 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 784 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 785 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 786 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 787 __le16 mtu; 788 __le16 guest_vlan; 789 __le16 async_event_cr; 790 u8 dflt_mac_addr[6]; 791 __le32 flags; 792 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 793 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 794 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 795 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 796 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 797 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 798 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 799 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 800 __le16 num_rsscos_ctxs; 801 __le16 num_cmpl_rings; 802 __le16 num_tx_rings; 803 __le16 num_rx_rings; 804 __le16 num_l2_ctxs; 805 __le16 num_vnics; 806 __le16 num_stat_ctxs; 807 __le16 num_hw_ring_grps; 808 u8 unused_0[4]; 809 }; 810 811 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 812 struct hwrm_func_vf_cfg_output { 813 __le16 error_code; 814 __le16 req_type; 815 __le16 seq_id; 816 __le16 resp_len; 817 u8 unused_0[7]; 818 u8 valid; 819 }; 820 821 /* hwrm_func_qcaps_input (size:192b/24B) */ 822 struct hwrm_func_qcaps_input { 823 __le16 req_type; 824 __le16 cmpl_ring; 825 __le16 seq_id; 826 __le16 target_id; 827 __le64 resp_addr; 828 __le16 fid; 829 u8 unused_0[6]; 830 }; 831 832 /* hwrm_func_qcaps_output (size:640b/80B) */ 833 struct hwrm_func_qcaps_output { 834 __le16 error_code; 835 __le16 req_type; 836 __le16 seq_id; 837 __le16 resp_len; 838 __le16 fid; 839 __le16 port_id; 840 __le32 flags; 841 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 842 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 843 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 844 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 845 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 846 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 847 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 848 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 849 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 850 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 851 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 852 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 853 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 854 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 855 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 856 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 857 u8 mac_address[6]; 858 __le16 max_rsscos_ctx; 859 __le16 max_cmpl_rings; 860 __le16 max_tx_rings; 861 __le16 max_rx_rings; 862 __le16 max_l2_ctxs; 863 __le16 max_vnics; 864 __le16 first_vf_id; 865 __le16 max_vfs; 866 __le16 max_stat_ctx; 867 __le32 max_encap_records; 868 __le32 max_decap_records; 869 __le32 max_tx_em_flows; 870 __le32 max_tx_wm_flows; 871 __le32 max_rx_em_flows; 872 __le32 max_rx_wm_flows; 873 __le32 max_mcast_filters; 874 __le32 max_flow_id; 875 __le32 max_hw_ring_grps; 876 __le16 max_sp_tx_rings; 877 u8 unused_0; 878 u8 valid; 879 }; 880 881 /* hwrm_func_qcfg_input (size:192b/24B) */ 882 struct hwrm_func_qcfg_input { 883 __le16 req_type; 884 __le16 cmpl_ring; 885 __le16 seq_id; 886 __le16 target_id; 887 __le64 resp_addr; 888 __le16 fid; 889 u8 unused_0[6]; 890 }; 891 892 /* hwrm_func_qcfg_output (size:640b/80B) */ 893 struct hwrm_func_qcfg_output { 894 __le16 error_code; 895 __le16 req_type; 896 __le16 seq_id; 897 __le16 resp_len; 898 __le16 fid; 899 __le16 port_id; 900 __le16 vlan; 901 __le16 flags; 902 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 903 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 904 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 905 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 906 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 907 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 908 u8 mac_address[6]; 909 __le16 pci_id; 910 __le16 alloc_rsscos_ctx; 911 __le16 alloc_cmpl_rings; 912 __le16 alloc_tx_rings; 913 __le16 alloc_rx_rings; 914 __le16 alloc_l2_ctx; 915 __le16 alloc_vnics; 916 __le16 mtu; 917 __le16 mru; 918 __le16 stat_ctx_id; 919 u8 port_partition_type; 920 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 921 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 922 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 923 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 924 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 925 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 926 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 927 u8 port_pf_cnt; 928 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 929 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 930 __le16 dflt_vnic_id; 931 __le16 max_mtu_configured; 932 __le32 min_bw; 933 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 934 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 935 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 936 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 937 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 938 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 939 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 940 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 941 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 942 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 943 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 944 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 945 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 946 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 947 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 948 __le32 max_bw; 949 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 950 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 951 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 952 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 953 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 954 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 955 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 956 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 957 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 958 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 959 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 960 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 961 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 962 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 963 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 964 u8 evb_mode; 965 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 966 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 967 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 968 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 969 u8 cache_linesize; 970 #define FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_64 0x0UL 971 #define FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128 0x1UL 972 #define FUNC_QCFG_RESP_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_CACHE_LINESIZE_CACHE_LINESIZE_128 973 __le16 alloc_vfs; 974 __le32 alloc_mcast_filters; 975 __le32 alloc_hw_ring_grps; 976 __le16 alloc_sp_tx_rings; 977 __le16 alloc_stat_ctx; 978 u8 unused_2[7]; 979 u8 valid; 980 }; 981 982 /* hwrm_func_vlan_cfg_input (size:384b/48B) */ 983 struct hwrm_func_vlan_cfg_input { 984 __le16 req_type; 985 __le16 cmpl_ring; 986 __le16 seq_id; 987 __le16 target_id; 988 __le64 resp_addr; 989 __le16 fid; 990 u8 unused_0[2]; 991 __le32 enables; 992 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL 993 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL 994 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL 995 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL 996 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL 997 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL 998 __le16 stag_vid; 999 u8 stag_pcp; 1000 u8 unused_1; 1001 __be16 stag_tpid; 1002 __le16 ctag_vid; 1003 u8 ctag_pcp; 1004 u8 unused_2; 1005 __be16 ctag_tpid; 1006 __le32 rsvd1; 1007 __le32 rsvd2; 1008 u8 unused_3[4]; 1009 }; 1010 1011 /* hwrm_func_vlan_cfg_output (size:128b/16B) */ 1012 struct hwrm_func_vlan_cfg_output { 1013 __le16 error_code; 1014 __le16 req_type; 1015 __le16 seq_id; 1016 __le16 resp_len; 1017 u8 unused_0[7]; 1018 u8 valid; 1019 }; 1020 1021 /* hwrm_func_cfg_input (size:704b/88B) */ 1022 struct hwrm_func_cfg_input { 1023 __le16 req_type; 1024 __le16 cmpl_ring; 1025 __le16 seq_id; 1026 __le16 target_id; 1027 __le64 resp_addr; 1028 __le16 fid; 1029 u8 unused_0[2]; 1030 __le32 flags; 1031 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1032 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1033 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1034 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1035 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1036 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1037 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1038 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1039 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1040 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1041 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1042 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1043 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1044 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1045 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1046 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1047 __le32 enables; 1048 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1049 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1050 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1051 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1052 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1053 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1054 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1055 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1056 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1057 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1058 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1059 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1060 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1061 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1062 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1063 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1064 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1065 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1066 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1067 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1068 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1069 __le16 mtu; 1070 __le16 mru; 1071 __le16 num_rsscos_ctxs; 1072 __le16 num_cmpl_rings; 1073 __le16 num_tx_rings; 1074 __le16 num_rx_rings; 1075 __le16 num_l2_ctxs; 1076 __le16 num_vnics; 1077 __le16 num_stat_ctxs; 1078 __le16 num_hw_ring_grps; 1079 u8 dflt_mac_addr[6]; 1080 __le16 dflt_vlan; 1081 __be32 dflt_ip_addr[4]; 1082 __le32 min_bw; 1083 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1084 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1085 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1086 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1087 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1088 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1089 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1090 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1091 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1092 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1093 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1094 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1095 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1096 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1097 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1098 __le32 max_bw; 1099 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1100 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1101 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1102 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1103 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1104 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1105 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1106 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1107 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1108 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1109 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1110 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1111 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1112 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1113 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1114 __le16 async_event_cr; 1115 u8 vlan_antispoof_mode; 1116 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1117 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1118 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1119 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1120 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1121 u8 allowed_vlan_pris; 1122 u8 evb_mode; 1123 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1124 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1125 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1126 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1127 u8 cache_linesize; 1128 #define FUNC_CFG_REQ_CACHE_LINESIZE_CACHE_LINESIZE_64 0x0UL 1129 #define FUNC_CFG_REQ_CACHE_LINESIZE_CACHE_LINESIZE_128 0x1UL 1130 #define FUNC_CFG_REQ_CACHE_LINESIZE_LAST FUNC_CFG_REQ_CACHE_LINESIZE_CACHE_LINESIZE_128 1131 __le16 num_mcast_filters; 1132 }; 1133 1134 /* hwrm_func_cfg_output (size:128b/16B) */ 1135 struct hwrm_func_cfg_output { 1136 __le16 error_code; 1137 __le16 req_type; 1138 __le16 seq_id; 1139 __le16 resp_len; 1140 u8 unused_0[7]; 1141 u8 valid; 1142 }; 1143 1144 /* hwrm_func_qstats_input (size:192b/24B) */ 1145 struct hwrm_func_qstats_input { 1146 __le16 req_type; 1147 __le16 cmpl_ring; 1148 __le16 seq_id; 1149 __le16 target_id; 1150 __le64 resp_addr; 1151 __le16 fid; 1152 u8 unused_0[6]; 1153 }; 1154 1155 /* hwrm_func_qstats_output (size:1408b/176B) */ 1156 struct hwrm_func_qstats_output { 1157 __le16 error_code; 1158 __le16 req_type; 1159 __le16 seq_id; 1160 __le16 resp_len; 1161 __le64 tx_ucast_pkts; 1162 __le64 tx_mcast_pkts; 1163 __le64 tx_bcast_pkts; 1164 __le64 tx_discard_pkts; 1165 __le64 tx_drop_pkts; 1166 __le64 tx_ucast_bytes; 1167 __le64 tx_mcast_bytes; 1168 __le64 tx_bcast_bytes; 1169 __le64 rx_ucast_pkts; 1170 __le64 rx_mcast_pkts; 1171 __le64 rx_bcast_pkts; 1172 __le64 rx_discard_pkts; 1173 __le64 rx_drop_pkts; 1174 __le64 rx_ucast_bytes; 1175 __le64 rx_mcast_bytes; 1176 __le64 rx_bcast_bytes; 1177 __le64 rx_agg_pkts; 1178 __le64 rx_agg_bytes; 1179 __le64 rx_agg_events; 1180 __le64 rx_agg_aborts; 1181 u8 unused_0[7]; 1182 u8 valid; 1183 }; 1184 1185 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1186 struct hwrm_func_clr_stats_input { 1187 __le16 req_type; 1188 __le16 cmpl_ring; 1189 __le16 seq_id; 1190 __le16 target_id; 1191 __le64 resp_addr; 1192 __le16 fid; 1193 u8 unused_0[6]; 1194 }; 1195 1196 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1197 struct hwrm_func_clr_stats_output { 1198 __le16 error_code; 1199 __le16 req_type; 1200 __le16 seq_id; 1201 __le16 resp_len; 1202 u8 unused_0[7]; 1203 u8 valid; 1204 }; 1205 1206 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1207 struct hwrm_func_vf_resc_free_input { 1208 __le16 req_type; 1209 __le16 cmpl_ring; 1210 __le16 seq_id; 1211 __le16 target_id; 1212 __le64 resp_addr; 1213 __le16 vf_id; 1214 u8 unused_0[6]; 1215 }; 1216 1217 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1218 struct hwrm_func_vf_resc_free_output { 1219 __le16 error_code; 1220 __le16 req_type; 1221 __le16 seq_id; 1222 __le16 resp_len; 1223 u8 unused_0[7]; 1224 u8 valid; 1225 }; 1226 1227 /* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ 1228 struct hwrm_func_vf_vnic_ids_query_input { 1229 __le16 req_type; 1230 __le16 cmpl_ring; 1231 __le16 seq_id; 1232 __le16 target_id; 1233 __le64 resp_addr; 1234 __le16 vf_id; 1235 u8 unused_0[2]; 1236 __le32 max_vnic_id_cnt; 1237 __le64 vnic_id_tbl_addr; 1238 }; 1239 1240 /* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ 1241 struct hwrm_func_vf_vnic_ids_query_output { 1242 __le16 error_code; 1243 __le16 req_type; 1244 __le16 seq_id; 1245 __le16 resp_len; 1246 __le32 vnic_id_cnt; 1247 u8 unused_0[3]; 1248 u8 valid; 1249 }; 1250 1251 /* hwrm_func_drv_rgtr_input (size:832b/104B) */ 1252 struct hwrm_func_drv_rgtr_input { 1253 __le16 req_type; 1254 __le16 cmpl_ring; 1255 __le16 seq_id; 1256 __le16 target_id; 1257 __le64 resp_addr; 1258 __le32 flags; 1259 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1260 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1261 __le32 enables; 1262 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1263 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1264 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1265 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1266 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1267 __le16 os_type; 1268 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1269 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1270 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1271 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1272 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1273 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1274 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1275 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1276 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1277 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1278 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1279 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1280 u8 ver_maj; 1281 u8 ver_min; 1282 u8 ver_upd; 1283 u8 unused_0[3]; 1284 __le32 timestamp; 1285 u8 unused_1[4]; 1286 __le32 vf_req_fwd[8]; 1287 __le32 async_event_fwd[8]; 1288 }; 1289 1290 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1291 struct hwrm_func_drv_rgtr_output { 1292 __le16 error_code; 1293 __le16 req_type; 1294 __le16 seq_id; 1295 __le16 resp_len; 1296 u8 unused_0[7]; 1297 u8 valid; 1298 }; 1299 1300 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1301 struct hwrm_func_drv_unrgtr_input { 1302 __le16 req_type; 1303 __le16 cmpl_ring; 1304 __le16 seq_id; 1305 __le16 target_id; 1306 __le64 resp_addr; 1307 __le32 flags; 1308 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1309 u8 unused_0[4]; 1310 }; 1311 1312 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1313 struct hwrm_func_drv_unrgtr_output { 1314 __le16 error_code; 1315 __le16 req_type; 1316 __le16 seq_id; 1317 __le16 resp_len; 1318 u8 unused_0[7]; 1319 u8 valid; 1320 }; 1321 1322 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1323 struct hwrm_func_buf_rgtr_input { 1324 __le16 req_type; 1325 __le16 cmpl_ring; 1326 __le16 seq_id; 1327 __le16 target_id; 1328 __le64 resp_addr; 1329 __le32 enables; 1330 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1331 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1332 __le16 vf_id; 1333 __le16 req_buf_num_pages; 1334 __le16 req_buf_page_size; 1335 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1336 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1337 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1338 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1339 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1340 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1341 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1342 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1343 __le16 req_buf_len; 1344 __le16 resp_buf_len; 1345 u8 unused_0[2]; 1346 __le64 req_buf_page_addr0; 1347 __le64 req_buf_page_addr1; 1348 __le64 req_buf_page_addr2; 1349 __le64 req_buf_page_addr3; 1350 __le64 req_buf_page_addr4; 1351 __le64 req_buf_page_addr5; 1352 __le64 req_buf_page_addr6; 1353 __le64 req_buf_page_addr7; 1354 __le64 req_buf_page_addr8; 1355 __le64 req_buf_page_addr9; 1356 __le64 error_buf_addr; 1357 __le64 resp_buf_addr; 1358 }; 1359 1360 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1361 struct hwrm_func_buf_rgtr_output { 1362 __le16 error_code; 1363 __le16 req_type; 1364 __le16 seq_id; 1365 __le16 resp_len; 1366 u8 unused_0[7]; 1367 u8 valid; 1368 }; 1369 1370 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1371 struct hwrm_func_drv_qver_input { 1372 __le16 req_type; 1373 __le16 cmpl_ring; 1374 __le16 seq_id; 1375 __le16 target_id; 1376 __le64 resp_addr; 1377 __le32 reserved; 1378 __le16 fid; 1379 u8 unused_0[2]; 1380 }; 1381 1382 /* hwrm_func_drv_qver_output (size:128b/16B) */ 1383 struct hwrm_func_drv_qver_output { 1384 __le16 error_code; 1385 __le16 req_type; 1386 __le16 seq_id; 1387 __le16 resp_len; 1388 __le16 os_type; 1389 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1390 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1391 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1392 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1393 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1394 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1395 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1396 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1397 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1398 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1399 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1400 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1401 u8 ver_maj; 1402 u8 ver_min; 1403 u8 ver_upd; 1404 u8 unused_0[2]; 1405 u8 valid; 1406 }; 1407 1408 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1409 struct hwrm_func_resource_qcaps_input { 1410 __le16 req_type; 1411 __le16 cmpl_ring; 1412 __le16 seq_id; 1413 __le16 target_id; 1414 __le64 resp_addr; 1415 __le16 fid; 1416 u8 unused_0[6]; 1417 }; 1418 1419 /* hwrm_func_resource_qcaps_output (size:384b/48B) */ 1420 struct hwrm_func_resource_qcaps_output { 1421 __le16 error_code; 1422 __le16 req_type; 1423 __le16 seq_id; 1424 __le16 resp_len; 1425 __le16 max_vfs; 1426 __le16 max_msix; 1427 __le16 vf_reservation_strategy; 1428 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1429 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1430 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 1431 __le16 min_rsscos_ctx; 1432 __le16 max_rsscos_ctx; 1433 __le16 min_cmpl_rings; 1434 __le16 max_cmpl_rings; 1435 __le16 min_tx_rings; 1436 __le16 max_tx_rings; 1437 __le16 min_rx_rings; 1438 __le16 max_rx_rings; 1439 __le16 min_l2_ctxs; 1440 __le16 max_l2_ctxs; 1441 __le16 min_vnics; 1442 __le16 max_vnics; 1443 __le16 min_stat_ctx; 1444 __le16 max_stat_ctx; 1445 __le16 min_hw_ring_grps; 1446 __le16 max_hw_ring_grps; 1447 u8 unused_0; 1448 u8 valid; 1449 }; 1450 1451 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1452 struct hwrm_func_vf_resource_cfg_input { 1453 __le16 req_type; 1454 __le16 cmpl_ring; 1455 __le16 seq_id; 1456 __le16 target_id; 1457 __le64 resp_addr; 1458 __le16 vf_id; 1459 __le16 max_msix; 1460 __le16 min_rsscos_ctx; 1461 __le16 max_rsscos_ctx; 1462 __le16 min_cmpl_rings; 1463 __le16 max_cmpl_rings; 1464 __le16 min_tx_rings; 1465 __le16 max_tx_rings; 1466 __le16 min_rx_rings; 1467 __le16 max_rx_rings; 1468 __le16 min_l2_ctxs; 1469 __le16 max_l2_ctxs; 1470 __le16 min_vnics; 1471 __le16 max_vnics; 1472 __le16 min_stat_ctx; 1473 __le16 max_stat_ctx; 1474 __le16 min_hw_ring_grps; 1475 __le16 max_hw_ring_grps; 1476 u8 unused_0[4]; 1477 }; 1478 1479 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1480 struct hwrm_func_vf_resource_cfg_output { 1481 __le16 error_code; 1482 __le16 req_type; 1483 __le16 seq_id; 1484 __le16 resp_len; 1485 __le16 reserved_rsscos_ctx; 1486 __le16 reserved_cmpl_rings; 1487 __le16 reserved_tx_rings; 1488 __le16 reserved_rx_rings; 1489 __le16 reserved_l2_ctxs; 1490 __le16 reserved_vnics; 1491 __le16 reserved_stat_ctx; 1492 __le16 reserved_hw_ring_grps; 1493 u8 unused_0[7]; 1494 u8 valid; 1495 }; 1496 1497 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 1498 struct hwrm_port_phy_cfg_input { 1499 __le16 req_type; 1500 __le16 cmpl_ring; 1501 __le16 seq_id; 1502 __le16 target_id; 1503 __le64 resp_addr; 1504 __le32 flags; 1505 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1506 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1507 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1508 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1509 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1510 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1511 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1512 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1513 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1514 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1515 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1516 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1517 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1518 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1519 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1520 __le32 enables; 1521 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1522 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1523 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1524 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1525 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1526 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1527 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1528 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1529 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1530 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1531 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1532 __le16 port_id; 1533 __le16 force_link_speed; 1534 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1535 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1536 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1537 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1538 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1539 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1540 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1541 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1542 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1543 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1544 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1545 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 1546 u8 auto_mode; 1547 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1548 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1549 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1550 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1551 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1552 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 1553 u8 auto_duplex; 1554 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1555 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1556 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1557 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 1558 u8 auto_pause; 1559 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1560 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1561 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1562 u8 unused_0; 1563 __le16 auto_link_speed; 1564 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1565 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1566 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1569 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1570 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1571 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1572 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1573 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1574 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1575 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 1576 __le16 auto_link_speed_mask; 1577 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1578 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1579 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1580 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1581 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1582 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1583 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1584 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1585 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1586 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1587 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1588 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1589 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1590 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1591 u8 wirespeed; 1592 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1593 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1594 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 1595 u8 lpbk; 1596 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1597 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1598 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1599 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_REMOTE 1600 u8 force_pause; 1601 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1602 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1603 u8 unused_1; 1604 __le32 preemphasis; 1605 __le16 eee_link_speed_mask; 1606 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1607 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1608 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1609 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1610 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1611 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1612 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1613 u8 unused_2[2]; 1614 __le32 tx_lpi_timer; 1615 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1616 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1617 __le32 unused_3; 1618 }; 1619 1620 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 1621 struct hwrm_port_phy_cfg_output { 1622 __le16 error_code; 1623 __le16 req_type; 1624 __le16 seq_id; 1625 __le16 resp_len; 1626 u8 unused_0[7]; 1627 u8 valid; 1628 }; 1629 1630 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 1631 struct hwrm_port_phy_qcfg_input { 1632 __le16 req_type; 1633 __le16 cmpl_ring; 1634 __le16 seq_id; 1635 __le16 target_id; 1636 __le64 resp_addr; 1637 __le16 port_id; 1638 u8 unused_0[6]; 1639 }; 1640 1641 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 1642 struct hwrm_port_phy_qcfg_output { 1643 __le16 error_code; 1644 __le16 req_type; 1645 __le16 seq_id; 1646 __le16 resp_len; 1647 u8 link; 1648 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1649 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1650 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1651 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 1652 u8 unused_0; 1653 __le16 link_speed; 1654 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1655 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1656 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1657 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1658 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1659 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1660 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1661 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1662 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1663 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1664 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1665 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 1666 u8 duplex_cfg; 1667 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 1668 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 1669 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 1670 u8 pause; 1671 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1672 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1673 __le16 support_speeds; 1674 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1675 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1676 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1677 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1678 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1679 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1680 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1681 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1682 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1683 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1684 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1685 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1686 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1687 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1688 __le16 force_link_speed; 1689 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1690 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1691 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1692 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1693 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1694 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1695 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1696 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1697 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1698 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1699 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1700 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 1701 u8 auto_mode; 1702 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1703 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1704 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1705 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1706 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1707 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 1708 u8 auto_pause; 1709 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1710 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1711 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1712 __le16 auto_link_speed; 1713 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1714 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1715 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1716 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1717 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1718 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1719 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1720 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1721 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1722 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1723 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1724 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 1725 __le16 auto_link_speed_mask; 1726 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1727 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1728 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1729 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1730 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1731 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1732 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1733 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1734 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1735 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1736 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1737 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1738 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1739 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1740 u8 wirespeed; 1741 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1742 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1743 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 1744 u8 lpbk; 1745 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1746 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1747 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1748 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_REMOTE 1749 u8 force_pause; 1750 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1751 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1752 u8 module_status; 1753 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1754 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1755 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1756 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1757 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1758 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1759 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 1760 __le32 preemphasis; 1761 u8 phy_maj; 1762 u8 phy_min; 1763 u8 phy_bld; 1764 u8 phy_type; 1765 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1766 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1767 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1768 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1769 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1770 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1771 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1772 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1773 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1774 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1775 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1776 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1777 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1778 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1779 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1780 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1781 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1782 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1783 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1784 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1785 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1786 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1787 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1788 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1789 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1790 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 1791 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 1792 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 1793 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 1794 u8 media_type; 1795 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1796 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1797 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1798 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1799 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 1800 u8 xcvr_pkg_type; 1801 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1802 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1803 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 1804 u8 eee_config_phy_addr; 1805 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1806 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1807 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1808 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1809 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1810 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1811 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1812 u8 parallel_detect; 1813 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1814 __le16 link_partner_adv_speeds; 1815 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1816 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1817 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1818 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1819 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1820 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1821 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1822 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1823 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1824 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1825 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1826 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1827 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1828 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1829 u8 link_partner_adv_auto_mode; 1830 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1831 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1832 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1833 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1834 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1835 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 1836 u8 link_partner_adv_pause; 1837 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1838 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1839 __le16 adv_eee_link_speed_mask; 1840 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1841 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1842 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1843 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1844 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1845 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1846 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1847 __le16 link_partner_adv_eee_link_speed_mask; 1848 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1849 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1850 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1851 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1852 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1853 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1854 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1855 __le32 xcvr_identifier_type_tx_lpi_timer; 1856 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1857 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1858 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1859 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1860 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1861 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1862 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1863 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1864 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1865 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 1866 __le16 fec_cfg; 1867 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1868 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1869 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1870 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1871 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1872 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1873 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1874 u8 duplex_state; 1875 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 1876 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 1877 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 1878 u8 option_flags; 1879 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 1880 char phy_vendor_name[16]; 1881 char phy_vendor_partnumber[16]; 1882 u8 unused_2[7]; 1883 u8 valid; 1884 }; 1885 1886 /* hwrm_port_mac_cfg_input (size:320b/40B) */ 1887 struct hwrm_port_mac_cfg_input { 1888 __le16 req_type; 1889 __le16 cmpl_ring; 1890 __le16 seq_id; 1891 __le16 target_id; 1892 __le64 resp_addr; 1893 __le32 flags; 1894 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1895 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1896 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1897 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1898 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1899 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1900 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1901 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1902 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1903 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1904 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1905 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1906 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1907 __le32 enables; 1908 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1909 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1910 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1911 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1912 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1913 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1914 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1915 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1916 __le16 port_id; 1917 u8 ipg; 1918 u8 lpbk; 1919 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1920 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1921 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1922 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 1923 u8 vlan_pri2cos_map_pri; 1924 u8 reserved1; 1925 u8 tunnel_pri2cos_map_pri; 1926 u8 dscp2pri_map_pri; 1927 __le16 rx_ts_capture_ptp_msg_type; 1928 __le16 tx_ts_capture_ptp_msg_type; 1929 u8 cos_field_cfg; 1930 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1931 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1932 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1933 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1934 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1935 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1936 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1937 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1938 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1939 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1940 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1941 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1942 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1943 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1944 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1945 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1946 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1947 u8 unused_0[3]; 1948 }; 1949 1950 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 1951 struct hwrm_port_mac_cfg_output { 1952 __le16 error_code; 1953 __le16 req_type; 1954 __le16 seq_id; 1955 __le16 resp_len; 1956 __le16 mru; 1957 __le16 mtu; 1958 u8 ipg; 1959 u8 lpbk; 1960 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1961 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1962 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1963 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 1964 u8 unused_0; 1965 u8 valid; 1966 }; 1967 1968 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 1969 struct hwrm_port_mac_ptp_qcfg_input { 1970 __le16 req_type; 1971 __le16 cmpl_ring; 1972 __le16 seq_id; 1973 __le16 target_id; 1974 __le64 resp_addr; 1975 __le16 port_id; 1976 u8 unused_0[6]; 1977 }; 1978 1979 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 1980 struct hwrm_port_mac_ptp_qcfg_output { 1981 __le16 error_code; 1982 __le16 req_type; 1983 __le16 seq_id; 1984 __le16 resp_len; 1985 u8 flags; 1986 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 1987 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 1988 u8 unused_0[3]; 1989 __le32 rx_ts_reg_off_lower; 1990 __le32 rx_ts_reg_off_upper; 1991 __le32 rx_ts_reg_off_seq_id; 1992 __le32 rx_ts_reg_off_src_id_0; 1993 __le32 rx_ts_reg_off_src_id_1; 1994 __le32 rx_ts_reg_off_src_id_2; 1995 __le32 rx_ts_reg_off_domain_id; 1996 __le32 rx_ts_reg_off_fifo; 1997 __le32 rx_ts_reg_off_fifo_adv; 1998 __le32 rx_ts_reg_off_granularity; 1999 __le32 tx_ts_reg_off_lower; 2000 __le32 tx_ts_reg_off_upper; 2001 __le32 tx_ts_reg_off_seq_id; 2002 __le32 tx_ts_reg_off_fifo; 2003 __le32 tx_ts_reg_off_granularity; 2004 u8 unused_1[7]; 2005 u8 valid; 2006 }; 2007 2008 /* hwrm_port_qstats_input (size:320b/40B) */ 2009 struct hwrm_port_qstats_input { 2010 __le16 req_type; 2011 __le16 cmpl_ring; 2012 __le16 seq_id; 2013 __le16 target_id; 2014 __le64 resp_addr; 2015 __le16 port_id; 2016 u8 unused_0[6]; 2017 __le64 tx_stat_host_addr; 2018 __le64 rx_stat_host_addr; 2019 }; 2020 2021 /* hwrm_port_qstats_output (size:128b/16B) */ 2022 struct hwrm_port_qstats_output { 2023 __le16 error_code; 2024 __le16 req_type; 2025 __le16 seq_id; 2026 __le16 resp_len; 2027 __le16 tx_stat_size; 2028 __le16 rx_stat_size; 2029 u8 unused_0[3]; 2030 u8 valid; 2031 }; 2032 2033 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 2034 struct hwrm_port_lpbk_qstats_input { 2035 __le16 req_type; 2036 __le16 cmpl_ring; 2037 __le16 seq_id; 2038 __le16 target_id; 2039 __le64 resp_addr; 2040 }; 2041 2042 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 2043 struct hwrm_port_lpbk_qstats_output { 2044 __le16 error_code; 2045 __le16 req_type; 2046 __le16 seq_id; 2047 __le16 resp_len; 2048 __le64 lpbk_ucast_frames; 2049 __le64 lpbk_mcast_frames; 2050 __le64 lpbk_bcast_frames; 2051 __le64 lpbk_ucast_bytes; 2052 __le64 lpbk_mcast_bytes; 2053 __le64 lpbk_bcast_bytes; 2054 __le64 tx_stat_discard; 2055 __le64 tx_stat_error; 2056 __le64 rx_stat_discard; 2057 __le64 rx_stat_error; 2058 u8 unused_0[7]; 2059 u8 valid; 2060 }; 2061 2062 /* hwrm_port_clr_stats_input (size:192b/24B) */ 2063 struct hwrm_port_clr_stats_input { 2064 __le16 req_type; 2065 __le16 cmpl_ring; 2066 __le16 seq_id; 2067 __le16 target_id; 2068 __le64 resp_addr; 2069 __le16 port_id; 2070 u8 unused_0[6]; 2071 }; 2072 2073 /* hwrm_port_clr_stats_output (size:128b/16B) */ 2074 struct hwrm_port_clr_stats_output { 2075 __le16 error_code; 2076 __le16 req_type; 2077 __le16 seq_id; 2078 __le16 resp_len; 2079 u8 unused_0[7]; 2080 u8 valid; 2081 }; 2082 2083 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 2084 struct hwrm_port_lpbk_clr_stats_input { 2085 __le16 req_type; 2086 __le16 cmpl_ring; 2087 __le16 seq_id; 2088 __le16 target_id; 2089 __le64 resp_addr; 2090 }; 2091 2092 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 2093 struct hwrm_port_lpbk_clr_stats_output { 2094 __le16 error_code; 2095 __le16 req_type; 2096 __le16 seq_id; 2097 __le16 resp_len; 2098 u8 unused_0[7]; 2099 u8 valid; 2100 }; 2101 2102 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 2103 struct hwrm_port_phy_qcaps_input { 2104 __le16 req_type; 2105 __le16 cmpl_ring; 2106 __le16 seq_id; 2107 __le16 target_id; 2108 __le64 resp_addr; 2109 __le16 port_id; 2110 u8 unused_0[6]; 2111 }; 2112 2113 /* hwrm_port_phy_qcaps_output (size:192b/24B) */ 2114 struct hwrm_port_phy_qcaps_output { 2115 __le16 error_code; 2116 __le16 req_type; 2117 __le16 seq_id; 2118 __le16 resp_len; 2119 u8 flags; 2120 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 2121 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 2122 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 2123 u8 port_cnt; 2124 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 2125 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 2126 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 2127 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 2128 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 2129 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 2130 __le16 supported_speeds_force_mode; 2131 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2132 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2133 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2134 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2135 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2136 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2137 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2138 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2139 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2140 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2141 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2142 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2143 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2144 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2145 __le16 supported_speeds_auto_mode; 2146 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2147 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2148 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2149 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2150 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2151 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2152 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2153 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2154 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2155 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2156 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2157 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2158 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2159 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2160 __le16 supported_speeds_eee_mode; 2161 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2162 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2163 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2164 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2165 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2166 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2167 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2168 __le32 tx_lpi_timer_low; 2169 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2170 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2171 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2172 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2173 __le32 valid_tx_lpi_timer_high; 2174 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2175 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2176 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2177 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2178 }; 2179 2180 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 2181 struct hwrm_port_phy_i2c_read_input { 2182 __le16 req_type; 2183 __le16 cmpl_ring; 2184 __le16 seq_id; 2185 __le16 target_id; 2186 __le64 resp_addr; 2187 __le32 flags; 2188 __le32 enables; 2189 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2190 __le16 port_id; 2191 u8 i2c_slave_addr; 2192 u8 unused_0; 2193 __le16 page_number; 2194 __le16 page_offset; 2195 u8 data_length; 2196 u8 unused_1[7]; 2197 }; 2198 2199 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 2200 struct hwrm_port_phy_i2c_read_output { 2201 __le16 error_code; 2202 __le16 req_type; 2203 __le16 seq_id; 2204 __le16 resp_len; 2205 __le32 data[16]; 2206 u8 unused_0[7]; 2207 u8 valid; 2208 }; 2209 2210 /* hwrm_port_led_cfg_input (size:512b/64B) */ 2211 struct hwrm_port_led_cfg_input { 2212 __le16 req_type; 2213 __le16 cmpl_ring; 2214 __le16 seq_id; 2215 __le16 target_id; 2216 __le64 resp_addr; 2217 __le32 enables; 2218 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2219 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2220 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2221 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2222 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2223 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2224 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2225 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2226 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2227 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2228 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2229 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2230 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2231 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2232 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2233 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2234 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2235 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2236 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2237 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2238 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2239 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2240 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2241 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2242 __le16 port_id; 2243 u8 num_leds; 2244 u8 rsvd; 2245 u8 led0_id; 2246 u8 led0_state; 2247 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2248 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2249 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2250 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2251 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2252 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 2253 u8 led0_color; 2254 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2255 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2256 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2257 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2258 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 2259 u8 unused_0; 2260 __le16 led0_blink_on; 2261 __le16 led0_blink_off; 2262 u8 led0_group_id; 2263 u8 rsvd0; 2264 u8 led1_id; 2265 u8 led1_state; 2266 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2267 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2268 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2269 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2270 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2271 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 2272 u8 led1_color; 2273 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2274 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2275 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2276 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2277 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 2278 u8 unused_1; 2279 __le16 led1_blink_on; 2280 __le16 led1_blink_off; 2281 u8 led1_group_id; 2282 u8 rsvd1; 2283 u8 led2_id; 2284 u8 led2_state; 2285 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2286 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2287 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2288 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2289 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2290 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 2291 u8 led2_color; 2292 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2293 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2294 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2295 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2296 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 2297 u8 unused_2; 2298 __le16 led2_blink_on; 2299 __le16 led2_blink_off; 2300 u8 led2_group_id; 2301 u8 rsvd2; 2302 u8 led3_id; 2303 u8 led3_state; 2304 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2305 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2306 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2307 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2308 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2309 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 2310 u8 led3_color; 2311 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2312 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2313 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2314 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2315 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 2316 u8 unused_3; 2317 __le16 led3_blink_on; 2318 __le16 led3_blink_off; 2319 u8 led3_group_id; 2320 u8 rsvd3; 2321 }; 2322 2323 /* hwrm_port_led_cfg_output (size:128b/16B) */ 2324 struct hwrm_port_led_cfg_output { 2325 __le16 error_code; 2326 __le16 req_type; 2327 __le16 seq_id; 2328 __le16 resp_len; 2329 u8 unused_0[7]; 2330 u8 valid; 2331 }; 2332 2333 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 2334 struct hwrm_port_led_qcfg_input { 2335 __le16 req_type; 2336 __le16 cmpl_ring; 2337 __le16 seq_id; 2338 __le16 target_id; 2339 __le64 resp_addr; 2340 __le16 port_id; 2341 u8 unused_0[6]; 2342 }; 2343 2344 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 2345 struct hwrm_port_led_qcfg_output { 2346 __le16 error_code; 2347 __le16 req_type; 2348 __le16 seq_id; 2349 __le16 resp_len; 2350 u8 num_leds; 2351 u8 led0_id; 2352 u8 led0_type; 2353 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 2354 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 2355 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 2356 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 2357 u8 led0_state; 2358 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 2359 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 2360 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 2361 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 2362 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 2363 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 2364 u8 led0_color; 2365 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 2366 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 2367 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 2368 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 2369 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 2370 u8 unused_0; 2371 __le16 led0_blink_on; 2372 __le16 led0_blink_off; 2373 u8 led0_group_id; 2374 u8 led1_id; 2375 u8 led1_type; 2376 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 2377 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 2378 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 2379 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 2380 u8 led1_state; 2381 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 2382 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 2383 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 2384 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 2385 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 2386 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 2387 u8 led1_color; 2388 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 2389 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 2390 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 2391 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 2392 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 2393 u8 unused_1; 2394 __le16 led1_blink_on; 2395 __le16 led1_blink_off; 2396 u8 led1_group_id; 2397 u8 led2_id; 2398 u8 led2_type; 2399 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 2400 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 2401 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 2402 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 2403 u8 led2_state; 2404 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 2405 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 2406 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 2407 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 2408 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 2409 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 2410 u8 led2_color; 2411 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 2412 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 2413 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 2414 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 2415 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 2416 u8 unused_2; 2417 __le16 led2_blink_on; 2418 __le16 led2_blink_off; 2419 u8 led2_group_id; 2420 u8 led3_id; 2421 u8 led3_type; 2422 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 2423 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 2424 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 2425 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 2426 u8 led3_state; 2427 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 2428 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 2429 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 2430 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 2431 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 2432 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 2433 u8 led3_color; 2434 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 2435 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 2436 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 2437 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 2438 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 2439 u8 unused_3; 2440 __le16 led3_blink_on; 2441 __le16 led3_blink_off; 2442 u8 led3_group_id; 2443 u8 unused_4[6]; 2444 u8 valid; 2445 }; 2446 2447 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 2448 struct hwrm_port_led_qcaps_input { 2449 __le16 req_type; 2450 __le16 cmpl_ring; 2451 __le16 seq_id; 2452 __le16 target_id; 2453 __le64 resp_addr; 2454 __le16 port_id; 2455 u8 unused_0[6]; 2456 }; 2457 2458 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 2459 struct hwrm_port_led_qcaps_output { 2460 __le16 error_code; 2461 __le16 req_type; 2462 __le16 seq_id; 2463 __le16 resp_len; 2464 u8 num_leds; 2465 u8 unused[3]; 2466 u8 led0_id; 2467 u8 led0_type; 2468 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2469 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2470 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2471 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 2472 u8 led0_group_id; 2473 u8 unused_0; 2474 __le16 led0_state_caps; 2475 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2476 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2477 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2478 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2479 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2480 __le16 led0_color_caps; 2481 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2482 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2483 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2484 u8 led1_id; 2485 u8 led1_type; 2486 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2487 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2488 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2489 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 2490 u8 led1_group_id; 2491 u8 unused_1; 2492 __le16 led1_state_caps; 2493 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2494 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2495 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2496 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2497 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2498 __le16 led1_color_caps; 2499 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2500 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2501 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2502 u8 led2_id; 2503 u8 led2_type; 2504 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2505 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2506 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2507 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 2508 u8 led2_group_id; 2509 u8 unused_2; 2510 __le16 led2_state_caps; 2511 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2512 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2513 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2514 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2515 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2516 __le16 led2_color_caps; 2517 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2518 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2519 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2520 u8 led3_id; 2521 u8 led3_type; 2522 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2523 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2524 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2525 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 2526 u8 led3_group_id; 2527 u8 unused_3; 2528 __le16 led3_state_caps; 2529 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2530 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2531 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2532 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2533 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2534 __le16 led3_color_caps; 2535 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2536 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2537 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2538 u8 unused_4[3]; 2539 u8 valid; 2540 }; 2541 2542 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 2543 struct hwrm_queue_qportcfg_input { 2544 __le16 req_type; 2545 __le16 cmpl_ring; 2546 __le16 seq_id; 2547 __le16 target_id; 2548 __le64 resp_addr; 2549 __le32 flags; 2550 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2551 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2552 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2553 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2554 __le16 port_id; 2555 u8 unused_0[2]; 2556 }; 2557 2558 /* hwrm_queue_qportcfg_output (size:256b/32B) */ 2559 struct hwrm_queue_qportcfg_output { 2560 __le16 error_code; 2561 __le16 req_type; 2562 __le16 seq_id; 2563 __le16 resp_len; 2564 u8 max_configurable_queues; 2565 u8 max_configurable_lossless_queues; 2566 u8 queue_cfg_allowed; 2567 u8 queue_cfg_info; 2568 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2569 u8 queue_pfcenable_cfg_allowed; 2570 u8 queue_pri2cos_cfg_allowed; 2571 u8 queue_cos2bw_cfg_allowed; 2572 u8 queue_id0; 2573 u8 queue_id0_service_profile; 2574 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2575 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2576 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2577 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 2578 u8 queue_id1; 2579 u8 queue_id1_service_profile; 2580 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2581 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2582 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2583 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 2584 u8 queue_id2; 2585 u8 queue_id2_service_profile; 2586 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2587 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2588 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2589 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 2590 u8 queue_id3; 2591 u8 queue_id3_service_profile; 2592 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2593 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2594 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2595 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 2596 u8 queue_id4; 2597 u8 queue_id4_service_profile; 2598 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2599 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2600 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2601 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 2602 u8 queue_id5; 2603 u8 queue_id5_service_profile; 2604 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2605 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2606 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2607 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 2608 u8 queue_id6; 2609 u8 queue_id6_service_profile; 2610 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2611 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2612 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2613 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 2614 u8 queue_id7; 2615 u8 queue_id7_service_profile; 2616 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2617 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2618 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2619 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 2620 u8 valid; 2621 }; 2622 2623 /* hwrm_queue_cfg_input (size:320b/40B) */ 2624 struct hwrm_queue_cfg_input { 2625 __le16 req_type; 2626 __le16 cmpl_ring; 2627 __le16 seq_id; 2628 __le16 target_id; 2629 __le64 resp_addr; 2630 __le32 flags; 2631 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2632 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2633 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2634 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2635 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2636 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2637 __le32 enables; 2638 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2639 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2640 __le32 queue_id; 2641 __le32 dflt_len; 2642 u8 service_profile; 2643 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2644 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2645 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2646 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 2647 u8 unused_0[7]; 2648 }; 2649 2650 /* hwrm_queue_cfg_output (size:128b/16B) */ 2651 struct hwrm_queue_cfg_output { 2652 __le16 error_code; 2653 __le16 req_type; 2654 __le16 seq_id; 2655 __le16 resp_len; 2656 u8 unused_0[7]; 2657 u8 valid; 2658 }; 2659 2660 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 2661 struct hwrm_queue_pfcenable_qcfg_input { 2662 __le16 req_type; 2663 __le16 cmpl_ring; 2664 __le16 seq_id; 2665 __le16 target_id; 2666 __le64 resp_addr; 2667 __le16 port_id; 2668 u8 unused_0[6]; 2669 }; 2670 2671 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 2672 struct hwrm_queue_pfcenable_qcfg_output { 2673 __le16 error_code; 2674 __le16 req_type; 2675 __le16 seq_id; 2676 __le16 resp_len; 2677 __le32 flags; 2678 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2679 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2680 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2681 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2682 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2683 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2684 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2685 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2686 u8 unused_0[3]; 2687 u8 valid; 2688 }; 2689 2690 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 2691 struct hwrm_queue_pfcenable_cfg_input { 2692 __le16 req_type; 2693 __le16 cmpl_ring; 2694 __le16 seq_id; 2695 __le16 target_id; 2696 __le64 resp_addr; 2697 __le32 flags; 2698 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2699 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2700 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2701 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2702 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2703 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2704 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2705 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2706 __le16 port_id; 2707 u8 unused_0[2]; 2708 }; 2709 2710 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 2711 struct hwrm_queue_pfcenable_cfg_output { 2712 __le16 error_code; 2713 __le16 req_type; 2714 __le16 seq_id; 2715 __le16 resp_len; 2716 u8 unused_0[7]; 2717 u8 valid; 2718 }; 2719 2720 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 2721 struct hwrm_queue_pri2cos_qcfg_input { 2722 __le16 req_type; 2723 __le16 cmpl_ring; 2724 __le16 seq_id; 2725 __le16 target_id; 2726 __le64 resp_addr; 2727 __le32 flags; 2728 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2729 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 2730 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 2731 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2732 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2733 u8 port_id; 2734 u8 unused_0[3]; 2735 }; 2736 2737 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 2738 struct hwrm_queue_pri2cos_qcfg_output { 2739 __le16 error_code; 2740 __le16 req_type; 2741 __le16 seq_id; 2742 __le16 resp_len; 2743 u8 pri0_cos_queue_id; 2744 u8 pri1_cos_queue_id; 2745 u8 pri2_cos_queue_id; 2746 u8 pri3_cos_queue_id; 2747 u8 pri4_cos_queue_id; 2748 u8 pri5_cos_queue_id; 2749 u8 pri6_cos_queue_id; 2750 u8 pri7_cos_queue_id; 2751 u8 queue_cfg_info; 2752 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2753 u8 unused_0[6]; 2754 u8 valid; 2755 }; 2756 2757 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 2758 struct hwrm_queue_pri2cos_cfg_input { 2759 __le16 req_type; 2760 __le16 cmpl_ring; 2761 __le16 seq_id; 2762 __le16 target_id; 2763 __le64 resp_addr; 2764 __le32 flags; 2765 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2766 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2767 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 2768 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 2769 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2770 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2771 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2772 __le32 enables; 2773 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2774 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2775 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2776 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2777 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2778 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2779 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2780 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2781 u8 port_id; 2782 u8 pri0_cos_queue_id; 2783 u8 pri1_cos_queue_id; 2784 u8 pri2_cos_queue_id; 2785 u8 pri3_cos_queue_id; 2786 u8 pri4_cos_queue_id; 2787 u8 pri5_cos_queue_id; 2788 u8 pri6_cos_queue_id; 2789 u8 pri7_cos_queue_id; 2790 u8 unused_0[7]; 2791 }; 2792 2793 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 2794 struct hwrm_queue_pri2cos_cfg_output { 2795 __le16 error_code; 2796 __le16 req_type; 2797 __le16 seq_id; 2798 __le16 resp_len; 2799 u8 unused_0[7]; 2800 u8 valid; 2801 }; 2802 2803 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 2804 struct hwrm_queue_cos2bw_qcfg_input { 2805 __le16 req_type; 2806 __le16 cmpl_ring; 2807 __le16 seq_id; 2808 __le16 target_id; 2809 __le64 resp_addr; 2810 __le16 port_id; 2811 u8 unused_0[6]; 2812 }; 2813 2814 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 2815 struct hwrm_queue_cos2bw_qcfg_output { 2816 __le16 error_code; 2817 __le16 req_type; 2818 __le16 seq_id; 2819 __le16 resp_len; 2820 u8 queue_id0; 2821 u8 unused_0; 2822 __le16 unused_1; 2823 __le32 queue_id0_min_bw; 2824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2839 __le32 queue_id0_max_bw; 2840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2855 u8 queue_id0_tsa_assign; 2856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2860 u8 queue_id0_pri_lvl; 2861 u8 queue_id0_bw_weight; 2862 u8 queue_id1; 2863 __le32 queue_id1_min_bw; 2864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2879 __le32 queue_id1_max_bw; 2880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2894 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2895 u8 queue_id1_tsa_assign; 2896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2900 u8 queue_id1_pri_lvl; 2901 u8 queue_id1_bw_weight; 2902 u8 queue_id2; 2903 __le32 queue_id2_min_bw; 2904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2910 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2915 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2916 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2917 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2918 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2919 __le32 queue_id2_max_bw; 2920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2934 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2935 u8 queue_id2_tsa_assign; 2936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2940 u8 queue_id2_pri_lvl; 2941 u8 queue_id2_bw_weight; 2942 u8 queue_id3; 2943 __le32 queue_id3_min_bw; 2944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 2950 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2955 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2956 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2957 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2958 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2959 __le32 queue_id3_max_bw; 2960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 2966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2974 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2975 u8 queue_id3_tsa_assign; 2976 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2980 u8 queue_id3_pri_lvl; 2981 u8 queue_id3_bw_weight; 2982 u8 queue_id4; 2983 __le32 queue_id4_min_bw; 2984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 2990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2995 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2996 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2997 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2998 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2999 __le32 queue_id4_max_bw; 3000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 3006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3015 u8 queue_id4_tsa_assign; 3016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3020 u8 queue_id4_pri_lvl; 3021 u8 queue_id4_bw_weight; 3022 u8 queue_id5; 3023 __le32 queue_id5_min_bw; 3024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 3030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3035 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3036 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3037 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3038 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3039 __le32 queue_id5_max_bw; 3040 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3044 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 3046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3051 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3054 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3055 u8 queue_id5_tsa_assign; 3056 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3057 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3058 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3059 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3060 u8 queue_id5_pri_lvl; 3061 u8 queue_id5_bw_weight; 3062 u8 queue_id6; 3063 __le32 queue_id6_min_bw; 3064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3065 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3066 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3067 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3068 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 3070 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3071 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3072 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3075 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3076 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3077 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3078 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3079 __le32 queue_id6_max_bw; 3080 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3084 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 3086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3091 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3094 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3095 u8 queue_id6_tsa_assign; 3096 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3097 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3098 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3099 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3100 u8 queue_id6_pri_lvl; 3101 u8 queue_id6_bw_weight; 3102 u8 queue_id7; 3103 __le32 queue_id7_min_bw; 3104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3105 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3106 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3107 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3108 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 3110 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3111 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3112 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3115 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3116 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3117 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3118 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3119 __le32 queue_id7_max_bw; 3120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 3126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3135 u8 queue_id7_tsa_assign; 3136 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3140 u8 queue_id7_pri_lvl; 3141 u8 queue_id7_bw_weight; 3142 u8 unused_2[4]; 3143 u8 valid; 3144 }; 3145 3146 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 3147 struct hwrm_queue_cos2bw_cfg_input { 3148 __le16 req_type; 3149 __le16 cmpl_ring; 3150 __le16 seq_id; 3151 __le16 target_id; 3152 __le64 resp_addr; 3153 __le32 flags; 3154 __le32 enables; 3155 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 3156 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 3157 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 3158 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 3159 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 3160 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 3161 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 3162 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 3163 __le16 port_id; 3164 u8 queue_id0; 3165 u8 unused_0; 3166 __le32 queue_id0_min_bw; 3167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 3173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3182 __le32 queue_id0_max_bw; 3183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 3189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3197 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3198 u8 queue_id0_tsa_assign; 3199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3203 u8 queue_id0_pri_lvl; 3204 u8 queue_id0_bw_weight; 3205 u8 queue_id1; 3206 __le32 queue_id1_min_bw; 3207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 3213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3222 __le32 queue_id1_max_bw; 3223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 3229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3237 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3238 u8 queue_id1_tsa_assign; 3239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3243 u8 queue_id1_pri_lvl; 3244 u8 queue_id1_bw_weight; 3245 u8 queue_id2; 3246 __le32 queue_id2_min_bw; 3247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3253 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3258 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3259 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3260 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3261 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3262 __le32 queue_id2_max_bw; 3263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3278 u8 queue_id2_tsa_assign; 3279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3283 u8 queue_id2_pri_lvl; 3284 u8 queue_id2_bw_weight; 3285 u8 queue_id3; 3286 __le32 queue_id3_min_bw; 3287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3298 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3299 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3300 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3301 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3302 __le32 queue_id3_max_bw; 3303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3318 u8 queue_id3_tsa_assign; 3319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3323 u8 queue_id3_pri_lvl; 3324 u8 queue_id3_bw_weight; 3325 u8 queue_id4; 3326 __le32 queue_id4_min_bw; 3327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 3333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3340 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3341 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3342 __le32 queue_id4_max_bw; 3343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3358 u8 queue_id4_tsa_assign; 3359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3363 u8 queue_id4_pri_lvl; 3364 u8 queue_id4_bw_weight; 3365 u8 queue_id5; 3366 __le32 queue_id5_min_bw; 3367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3380 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3381 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3382 __le32 queue_id5_max_bw; 3383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3397 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3398 u8 queue_id5_tsa_assign; 3399 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3403 u8 queue_id5_pri_lvl; 3404 u8 queue_id5_bw_weight; 3405 u8 queue_id6; 3406 __le32 queue_id6_min_bw; 3407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3418 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3420 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3421 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3422 __le32 queue_id6_max_bw; 3423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3427 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3438 u8 queue_id6_tsa_assign; 3439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3443 u8 queue_id6_pri_lvl; 3444 u8 queue_id6_bw_weight; 3445 u8 queue_id7; 3446 __le32 queue_id7_min_bw; 3447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3460 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3461 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3462 __le32 queue_id7_max_bw; 3463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3478 u8 queue_id7_tsa_assign; 3479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3483 u8 queue_id7_pri_lvl; 3484 u8 queue_id7_bw_weight; 3485 u8 unused_1[5]; 3486 }; 3487 3488 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 3489 struct hwrm_queue_cos2bw_cfg_output { 3490 __le16 error_code; 3491 __le16 req_type; 3492 __le16 seq_id; 3493 __le16 resp_len; 3494 u8 unused_0[7]; 3495 u8 valid; 3496 }; 3497 3498 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 3499 struct hwrm_queue_dscp_qcaps_input { 3500 __le16 req_type; 3501 __le16 cmpl_ring; 3502 __le16 seq_id; 3503 __le16 target_id; 3504 __le64 resp_addr; 3505 u8 port_id; 3506 u8 unused_0[7]; 3507 }; 3508 3509 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 3510 struct hwrm_queue_dscp_qcaps_output { 3511 __le16 error_code; 3512 __le16 req_type; 3513 __le16 seq_id; 3514 __le16 resp_len; 3515 u8 num_dscp_bits; 3516 u8 unused_0; 3517 __le16 max_entries; 3518 u8 unused_1[3]; 3519 u8 valid; 3520 }; 3521 3522 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 3523 struct hwrm_queue_dscp2pri_qcfg_input { 3524 __le16 req_type; 3525 __le16 cmpl_ring; 3526 __le16 seq_id; 3527 __le16 target_id; 3528 __le64 resp_addr; 3529 __le64 dest_data_addr; 3530 u8 port_id; 3531 u8 unused_0; 3532 __le16 dest_data_buffer_size; 3533 u8 unused_1[4]; 3534 }; 3535 3536 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 3537 struct hwrm_queue_dscp2pri_qcfg_output { 3538 __le16 error_code; 3539 __le16 req_type; 3540 __le16 seq_id; 3541 __le16 resp_len; 3542 __le16 entry_cnt; 3543 u8 default_pri; 3544 u8 unused_0[4]; 3545 u8 valid; 3546 }; 3547 3548 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 3549 struct hwrm_queue_dscp2pri_cfg_input { 3550 __le16 req_type; 3551 __le16 cmpl_ring; 3552 __le16 seq_id; 3553 __le16 target_id; 3554 __le64 resp_addr; 3555 __le64 src_data_addr; 3556 __le32 flags; 3557 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 3558 __le32 enables; 3559 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 3560 u8 port_id; 3561 u8 default_pri; 3562 __le16 entry_cnt; 3563 u8 unused_0[4]; 3564 }; 3565 3566 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 3567 struct hwrm_queue_dscp2pri_cfg_output { 3568 __le16 error_code; 3569 __le16 req_type; 3570 __le16 seq_id; 3571 __le16 resp_len; 3572 u8 unused_0[7]; 3573 u8 valid; 3574 }; 3575 3576 /* hwrm_vnic_alloc_input (size:192b/24B) */ 3577 struct hwrm_vnic_alloc_input { 3578 __le16 req_type; 3579 __le16 cmpl_ring; 3580 __le16 seq_id; 3581 __le16 target_id; 3582 __le64 resp_addr; 3583 __le32 flags; 3584 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3585 u8 unused_0[4]; 3586 }; 3587 3588 /* hwrm_vnic_alloc_output (size:128b/16B) */ 3589 struct hwrm_vnic_alloc_output { 3590 __le16 error_code; 3591 __le16 req_type; 3592 __le16 seq_id; 3593 __le16 resp_len; 3594 __le32 vnic_id; 3595 u8 unused_0[3]; 3596 u8 valid; 3597 }; 3598 3599 /* hwrm_vnic_free_input (size:192b/24B) */ 3600 struct hwrm_vnic_free_input { 3601 __le16 req_type; 3602 __le16 cmpl_ring; 3603 __le16 seq_id; 3604 __le16 target_id; 3605 __le64 resp_addr; 3606 __le32 vnic_id; 3607 u8 unused_0[4]; 3608 }; 3609 3610 /* hwrm_vnic_free_output (size:128b/16B) */ 3611 struct hwrm_vnic_free_output { 3612 __le16 error_code; 3613 __le16 req_type; 3614 __le16 seq_id; 3615 __le16 resp_len; 3616 u8 unused_0[7]; 3617 u8 valid; 3618 }; 3619 3620 /* hwrm_vnic_cfg_input (size:320b/40B) */ 3621 struct hwrm_vnic_cfg_input { 3622 __le16 req_type; 3623 __le16 cmpl_ring; 3624 __le16 seq_id; 3625 __le16 target_id; 3626 __le64 resp_addr; 3627 __le32 flags; 3628 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3629 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3630 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3631 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3632 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3633 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3634 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 3635 __le32 enables; 3636 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3637 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3638 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3639 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3640 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3641 __le16 vnic_id; 3642 __le16 dflt_ring_grp; 3643 __le16 rss_rule; 3644 __le16 cos_rule; 3645 __le16 lb_rule; 3646 __le16 mru; 3647 u8 unused_0[4]; 3648 }; 3649 3650 /* hwrm_vnic_cfg_output (size:128b/16B) */ 3651 struct hwrm_vnic_cfg_output { 3652 __le16 error_code; 3653 __le16 req_type; 3654 __le16 seq_id; 3655 __le16 resp_len; 3656 u8 unused_0[7]; 3657 u8 valid; 3658 }; 3659 3660 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 3661 struct hwrm_vnic_qcaps_input { 3662 __le16 req_type; 3663 __le16 cmpl_ring; 3664 __le16 seq_id; 3665 __le16 target_id; 3666 __le64 resp_addr; 3667 __le32 enables; 3668 u8 unused_0[4]; 3669 }; 3670 3671 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 3672 struct hwrm_vnic_qcaps_output { 3673 __le16 error_code; 3674 __le16 req_type; 3675 __le16 seq_id; 3676 __le16 resp_len; 3677 __le16 mru; 3678 u8 unused_0[2]; 3679 __le32 flags; 3680 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3681 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3682 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3683 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3684 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3685 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3686 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 3687 u8 unused_1[7]; 3688 u8 valid; 3689 }; 3690 3691 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 3692 struct hwrm_vnic_tpa_cfg_input { 3693 __le16 req_type; 3694 __le16 cmpl_ring; 3695 __le16 seq_id; 3696 __le16 target_id; 3697 __le64 resp_addr; 3698 __le32 flags; 3699 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3700 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3701 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3702 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3703 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3704 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3705 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3706 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3707 __le32 enables; 3708 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3709 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3710 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3711 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3712 __le16 vnic_id; 3713 __le16 max_agg_segs; 3714 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3715 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3716 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3717 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3718 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3719 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 3720 __le16 max_aggs; 3721 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3722 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3723 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3724 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3725 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3726 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3727 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 3728 u8 unused_0[2]; 3729 __le32 max_agg_timer; 3730 __le32 min_agg_len; 3731 }; 3732 3733 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 3734 struct hwrm_vnic_tpa_cfg_output { 3735 __le16 error_code; 3736 __le16 req_type; 3737 __le16 seq_id; 3738 __le16 resp_len; 3739 u8 unused_0[7]; 3740 u8 valid; 3741 }; 3742 3743 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 3744 struct hwrm_vnic_tpa_qcfg_input { 3745 __le16 req_type; 3746 __le16 cmpl_ring; 3747 __le16 seq_id; 3748 __le16 target_id; 3749 __le64 resp_addr; 3750 __le16 vnic_id; 3751 u8 unused_0[6]; 3752 }; 3753 3754 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 3755 struct hwrm_vnic_tpa_qcfg_output { 3756 __le16 error_code; 3757 __le16 req_type; 3758 __le16 seq_id; 3759 __le16 resp_len; 3760 __le32 flags; 3761 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 3762 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 3763 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 3764 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 3765 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 3766 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3767 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 3768 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 3769 __le16 max_agg_segs; 3770 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 3771 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 3772 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 3773 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 3774 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 3775 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 3776 __le16 max_aggs; 3777 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 3778 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 3779 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 3780 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 3781 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 3782 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 3783 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 3784 __le32 max_agg_timer; 3785 __le32 min_agg_len; 3786 u8 unused_0[7]; 3787 u8 valid; 3788 }; 3789 3790 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 3791 struct hwrm_vnic_rss_cfg_input { 3792 __le16 req_type; 3793 __le16 cmpl_ring; 3794 __le16 seq_id; 3795 __le16 target_id; 3796 __le64 resp_addr; 3797 __le32 hash_type; 3798 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3799 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3800 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3801 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3802 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3803 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3804 u8 unused_0[4]; 3805 __le64 ring_grp_tbl_addr; 3806 __le64 hash_key_tbl_addr; 3807 __le16 rss_ctx_idx; 3808 u8 unused_1[6]; 3809 }; 3810 3811 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 3812 struct hwrm_vnic_rss_cfg_output { 3813 __le16 error_code; 3814 __le16 req_type; 3815 __le16 seq_id; 3816 __le16 resp_len; 3817 u8 unused_0[7]; 3818 u8 valid; 3819 }; 3820 3821 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 3822 struct hwrm_vnic_plcmodes_cfg_input { 3823 __le16 req_type; 3824 __le16 cmpl_ring; 3825 __le16 seq_id; 3826 __le16 target_id; 3827 __le64 resp_addr; 3828 __le32 flags; 3829 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3830 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3831 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3832 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3833 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3834 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3835 __le32 enables; 3836 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3837 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3838 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3839 __le32 vnic_id; 3840 __le16 jumbo_thresh; 3841 __le16 hds_offset; 3842 __le16 hds_threshold; 3843 u8 unused_0[6]; 3844 }; 3845 3846 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 3847 struct hwrm_vnic_plcmodes_cfg_output { 3848 __le16 error_code; 3849 __le16 req_type; 3850 __le16 seq_id; 3851 __le16 resp_len; 3852 u8 unused_0[7]; 3853 u8 valid; 3854 }; 3855 3856 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 3857 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3858 __le16 req_type; 3859 __le16 cmpl_ring; 3860 __le16 seq_id; 3861 __le16 target_id; 3862 __le64 resp_addr; 3863 }; 3864 3865 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 3866 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3867 __le16 error_code; 3868 __le16 req_type; 3869 __le16 seq_id; 3870 __le16 resp_len; 3871 __le16 rss_cos_lb_ctx_id; 3872 u8 unused_0[5]; 3873 u8 valid; 3874 }; 3875 3876 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 3877 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3878 __le16 req_type; 3879 __le16 cmpl_ring; 3880 __le16 seq_id; 3881 __le16 target_id; 3882 __le64 resp_addr; 3883 __le16 rss_cos_lb_ctx_id; 3884 u8 unused_0[6]; 3885 }; 3886 3887 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 3888 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3889 __le16 error_code; 3890 __le16 req_type; 3891 __le16 seq_id; 3892 __le16 resp_len; 3893 u8 unused_0[7]; 3894 u8 valid; 3895 }; 3896 3897 /* hwrm_ring_alloc_input (size:640b/80B) */ 3898 struct hwrm_ring_alloc_input { 3899 __le16 req_type; 3900 __le16 cmpl_ring; 3901 __le16 seq_id; 3902 __le16 target_id; 3903 __le64 resp_addr; 3904 __le32 enables; 3905 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3906 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3907 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3908 u8 ring_type; 3909 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3910 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3911 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3912 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3913 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 3914 u8 unused_0[3]; 3915 __le64 page_tbl_addr; 3916 __le32 fbo; 3917 u8 page_size; 3918 u8 page_tbl_depth; 3919 u8 unused_1[2]; 3920 __le32 length; 3921 __le16 logical_id; 3922 __le16 cmpl_ring_id; 3923 __le16 queue_id; 3924 u8 unused_2[2]; 3925 __le32 reserved1; 3926 __le16 ring_arb_cfg; 3927 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3928 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3929 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 3930 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 3931 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3932 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3933 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3934 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3935 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3936 __le16 unused_3; 3937 __le32 reserved3; 3938 __le32 stat_ctx_id; 3939 __le32 reserved4; 3940 __le32 max_bw; 3941 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3942 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3943 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3944 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3945 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3946 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3947 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3948 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3949 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3950 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3951 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3952 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3953 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3954 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3955 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3956 u8 int_mode; 3957 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3958 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3959 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3960 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3961 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 3962 u8 unused_4[3]; 3963 }; 3964 3965 /* hwrm_ring_alloc_output (size:128b/16B) */ 3966 struct hwrm_ring_alloc_output { 3967 __le16 error_code; 3968 __le16 req_type; 3969 __le16 seq_id; 3970 __le16 resp_len; 3971 __le16 ring_id; 3972 __le16 logical_ring_id; 3973 u8 unused_0[3]; 3974 u8 valid; 3975 }; 3976 3977 /* hwrm_ring_free_input (size:192b/24B) */ 3978 struct hwrm_ring_free_input { 3979 __le16 req_type; 3980 __le16 cmpl_ring; 3981 __le16 seq_id; 3982 __le16 target_id; 3983 __le64 resp_addr; 3984 u8 ring_type; 3985 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3986 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3987 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3988 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3989 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_ROCE_CMPL 3990 u8 unused_0; 3991 __le16 ring_id; 3992 u8 unused_1[4]; 3993 }; 3994 3995 /* hwrm_ring_free_output (size:128b/16B) */ 3996 struct hwrm_ring_free_output { 3997 __le16 error_code; 3998 __le16 req_type; 3999 __le16 seq_id; 4000 __le16 resp_len; 4001 u8 unused_0[7]; 4002 u8 valid; 4003 }; 4004 4005 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 4006 struct hwrm_ring_cmpl_ring_qaggint_params_input { 4007 __le16 req_type; 4008 __le16 cmpl_ring; 4009 __le16 seq_id; 4010 __le16 target_id; 4011 __le64 resp_addr; 4012 __le16 ring_id; 4013 u8 unused_0[6]; 4014 }; 4015 4016 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 4017 struct hwrm_ring_cmpl_ring_qaggint_params_output { 4018 __le16 error_code; 4019 __le16 req_type; 4020 __le16 seq_id; 4021 __le16 resp_len; 4022 __le16 flags; 4023 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 4024 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 4025 __le16 num_cmpl_dma_aggr; 4026 __le16 num_cmpl_dma_aggr_during_int; 4027 __le16 cmpl_aggr_dma_tmr; 4028 __le16 cmpl_aggr_dma_tmr_during_int; 4029 __le16 int_lat_tmr_min; 4030 __le16 int_lat_tmr_max; 4031 __le16 num_cmpl_aggr_int; 4032 u8 unused_0[7]; 4033 u8 valid; 4034 }; 4035 4036 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 4037 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 4038 __le16 req_type; 4039 __le16 cmpl_ring; 4040 __le16 seq_id; 4041 __le16 target_id; 4042 __le64 resp_addr; 4043 __le16 ring_id; 4044 __le16 flags; 4045 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 4046 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 4047 __le16 num_cmpl_dma_aggr; 4048 __le16 num_cmpl_dma_aggr_during_int; 4049 __le16 cmpl_aggr_dma_tmr; 4050 __le16 cmpl_aggr_dma_tmr_during_int; 4051 __le16 int_lat_tmr_min; 4052 __le16 int_lat_tmr_max; 4053 __le16 num_cmpl_aggr_int; 4054 u8 unused_0[6]; 4055 }; 4056 4057 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 4058 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 4059 __le16 error_code; 4060 __le16 req_type; 4061 __le16 seq_id; 4062 __le16 resp_len; 4063 u8 unused_0[7]; 4064 u8 valid; 4065 }; 4066 4067 /* hwrm_ring_reset_input (size:192b/24B) */ 4068 struct hwrm_ring_reset_input { 4069 __le16 req_type; 4070 __le16 cmpl_ring; 4071 __le16 seq_id; 4072 __le16 target_id; 4073 __le64 resp_addr; 4074 u8 ring_type; 4075 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 4076 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 4077 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 4078 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4079 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL 4080 u8 unused_0; 4081 __le16 ring_id; 4082 u8 unused_1[4]; 4083 }; 4084 4085 /* hwrm_ring_reset_output (size:128b/16B) */ 4086 struct hwrm_ring_reset_output { 4087 __le16 error_code; 4088 __le16 req_type; 4089 __le16 seq_id; 4090 __le16 resp_len; 4091 u8 unused_0[7]; 4092 u8 valid; 4093 }; 4094 4095 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 4096 struct hwrm_ring_grp_alloc_input { 4097 __le16 req_type; 4098 __le16 cmpl_ring; 4099 __le16 seq_id; 4100 __le16 target_id; 4101 __le64 resp_addr; 4102 __le16 cr; 4103 __le16 rr; 4104 __le16 ar; 4105 __le16 sc; 4106 }; 4107 4108 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 4109 struct hwrm_ring_grp_alloc_output { 4110 __le16 error_code; 4111 __le16 req_type; 4112 __le16 seq_id; 4113 __le16 resp_len; 4114 __le32 ring_group_id; 4115 u8 unused_0[3]; 4116 u8 valid; 4117 }; 4118 4119 /* hwrm_ring_grp_free_input (size:192b/24B) */ 4120 struct hwrm_ring_grp_free_input { 4121 __le16 req_type; 4122 __le16 cmpl_ring; 4123 __le16 seq_id; 4124 __le16 target_id; 4125 __le64 resp_addr; 4126 __le32 ring_group_id; 4127 u8 unused_0[4]; 4128 }; 4129 4130 /* hwrm_ring_grp_free_output (size:128b/16B) */ 4131 struct hwrm_ring_grp_free_output { 4132 __le16 error_code; 4133 __le16 req_type; 4134 __le16 seq_id; 4135 __le16 resp_len; 4136 u8 unused_0[7]; 4137 u8 valid; 4138 }; 4139 4140 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 4141 struct hwrm_cfa_l2_filter_alloc_input { 4142 __le16 req_type; 4143 __le16 cmpl_ring; 4144 __le16 seq_id; 4145 __le16 target_id; 4146 __le64 resp_addr; 4147 __le32 flags; 4148 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 4149 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 4150 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 4151 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 4152 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 4153 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 4154 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 4155 __le32 enables; 4156 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 4157 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 4158 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 4159 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 4160 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 4161 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 4162 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 4163 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 4164 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 4165 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 4166 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 4167 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 4168 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 4169 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 4170 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 4171 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4172 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4173 u8 l2_addr[6]; 4174 u8 unused_0[2]; 4175 u8 l2_addr_mask[6]; 4176 __le16 l2_ovlan; 4177 __le16 l2_ovlan_mask; 4178 __le16 l2_ivlan; 4179 __le16 l2_ivlan_mask; 4180 u8 unused_1[2]; 4181 u8 t_l2_addr[6]; 4182 u8 unused_2[2]; 4183 u8 t_l2_addr_mask[6]; 4184 __le16 t_l2_ovlan; 4185 __le16 t_l2_ovlan_mask; 4186 __le16 t_l2_ivlan; 4187 __le16 t_l2_ivlan_mask; 4188 u8 src_type; 4189 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 4190 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 4191 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 4192 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 4193 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 4194 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 4195 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 4196 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 4197 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 4198 u8 unused_3; 4199 __le32 src_id; 4200 u8 tunnel_type; 4201 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4202 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4203 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4204 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4205 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4206 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4207 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4208 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4209 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4210 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4211 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4212 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4213 u8 unused_4; 4214 __le16 dst_id; 4215 __le16 mirror_vnic_id; 4216 u8 pri_hint; 4217 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4218 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 4219 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 4220 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4221 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4222 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 4223 u8 unused_5; 4224 __le32 unused_6; 4225 __le64 l2_filter_id_hint; 4226 }; 4227 4228 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 4229 struct hwrm_cfa_l2_filter_alloc_output { 4230 __le16 error_code; 4231 __le16 req_type; 4232 __le16 seq_id; 4233 __le16 resp_len; 4234 __le64 l2_filter_id; 4235 __le32 flow_id; 4236 u8 unused_0[3]; 4237 u8 valid; 4238 }; 4239 4240 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 4241 struct hwrm_cfa_l2_filter_free_input { 4242 __le16 req_type; 4243 __le16 cmpl_ring; 4244 __le16 seq_id; 4245 __le16 target_id; 4246 __le64 resp_addr; 4247 __le64 l2_filter_id; 4248 }; 4249 4250 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 4251 struct hwrm_cfa_l2_filter_free_output { 4252 __le16 error_code; 4253 __le16 req_type; 4254 __le16 seq_id; 4255 __le16 resp_len; 4256 u8 unused_0[7]; 4257 u8 valid; 4258 }; 4259 4260 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 4261 struct hwrm_cfa_l2_filter_cfg_input { 4262 __le16 req_type; 4263 __le16 cmpl_ring; 4264 __le16 seq_id; 4265 __le16 target_id; 4266 __le64 resp_addr; 4267 __le32 flags; 4268 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 4269 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 4270 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 4271 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 4272 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 4273 __le32 enables; 4274 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 4275 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4276 __le64 l2_filter_id; 4277 __le32 dst_id; 4278 __le32 new_mirror_vnic_id; 4279 }; 4280 4281 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 4282 struct hwrm_cfa_l2_filter_cfg_output { 4283 __le16 error_code; 4284 __le16 req_type; 4285 __le16 seq_id; 4286 __le16 resp_len; 4287 u8 unused_0[7]; 4288 u8 valid; 4289 }; 4290 4291 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 4292 struct hwrm_cfa_l2_set_rx_mask_input { 4293 __le16 req_type; 4294 __le16 cmpl_ring; 4295 __le16 seq_id; 4296 __le16 target_id; 4297 __le64 resp_addr; 4298 __le32 vnic_id; 4299 __le32 mask; 4300 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 4301 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 4302 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 4303 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 4304 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 4305 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 4306 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 4307 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 4308 __le64 mc_tbl_addr; 4309 __le32 num_mc_entries; 4310 u8 unused_0[4]; 4311 __le64 vlan_tag_tbl_addr; 4312 __le32 num_vlan_tags; 4313 u8 unused_1[4]; 4314 }; 4315 4316 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 4317 struct hwrm_cfa_l2_set_rx_mask_output { 4318 __le16 error_code; 4319 __le16 req_type; 4320 __le16 seq_id; 4321 __le16 resp_len; 4322 u8 unused_0[7]; 4323 u8 valid; 4324 }; 4325 4326 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 4327 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 4328 u8 code; 4329 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 4330 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 4331 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 4332 u8 unused_0[7]; 4333 }; 4334 4335 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 4336 struct hwrm_cfa_tunnel_filter_alloc_input { 4337 __le16 req_type; 4338 __le16 cmpl_ring; 4339 __le16 seq_id; 4340 __le16 target_id; 4341 __le64 resp_addr; 4342 __le32 flags; 4343 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4344 __le32 enables; 4345 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4346 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 4347 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 4348 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 4349 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 4350 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 4351 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 4352 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 4353 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 4354 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 4355 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 4356 __le64 l2_filter_id; 4357 u8 l2_addr[6]; 4358 __le16 l2_ivlan; 4359 __le32 l3_addr[4]; 4360 __le32 t_l3_addr[4]; 4361 u8 l3_addr_type; 4362 u8 t_l3_addr_type; 4363 u8 tunnel_type; 4364 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4365 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4366 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4367 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4368 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4369 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4370 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4371 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4372 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4373 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4374 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4375 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4376 u8 tunnel_flags; 4377 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 4378 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 4379 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 4380 __le32 vni; 4381 __le32 dst_vnic_id; 4382 __le32 mirror_vnic_id; 4383 }; 4384 4385 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 4386 struct hwrm_cfa_tunnel_filter_alloc_output { 4387 __le16 error_code; 4388 __le16 req_type; 4389 __le16 seq_id; 4390 __le16 resp_len; 4391 __le64 tunnel_filter_id; 4392 __le32 flow_id; 4393 u8 unused_0[3]; 4394 u8 valid; 4395 }; 4396 4397 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 4398 struct hwrm_cfa_tunnel_filter_free_input { 4399 __le16 req_type; 4400 __le16 cmpl_ring; 4401 __le16 seq_id; 4402 __le16 target_id; 4403 __le64 resp_addr; 4404 __le64 tunnel_filter_id; 4405 }; 4406 4407 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 4408 struct hwrm_cfa_tunnel_filter_free_output { 4409 __le16 error_code; 4410 __le16 req_type; 4411 __le16 seq_id; 4412 __le16 resp_len; 4413 u8 unused_0[7]; 4414 u8 valid; 4415 }; 4416 4417 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 4418 struct hwrm_vxlan_ipv4_hdr { 4419 u8 ver_hlen; 4420 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 4421 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 4422 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 4423 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 4424 u8 tos; 4425 __be16 ip_id; 4426 __be16 flags_frag_offset; 4427 u8 ttl; 4428 u8 protocol; 4429 __be32 src_ip_addr; 4430 __be32 dest_ip_addr; 4431 }; 4432 4433 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 4434 struct hwrm_vxlan_ipv6_hdr { 4435 __be32 ver_tc_flow_label; 4436 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 4437 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 4438 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 4439 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 4440 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 4441 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 4442 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 4443 __be16 payload_len; 4444 u8 next_hdr; 4445 u8 ttl; 4446 __be32 src_ip_addr[4]; 4447 __be32 dest_ip_addr[4]; 4448 }; 4449 4450 /* hwrm_cfa_encap_data_vxlan (size:576b/72B) */ 4451 struct hwrm_cfa_encap_data_vxlan { 4452 u8 src_mac_addr[6]; 4453 __le16 unused_0; 4454 u8 dst_mac_addr[6]; 4455 u8 num_vlan_tags; 4456 u8 unused_1; 4457 __be16 ovlan_tpid; 4458 __be16 ovlan_tci; 4459 __be16 ivlan_tpid; 4460 __be16 ivlan_tci; 4461 __le32 l3[10]; 4462 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 4463 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 4464 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 4465 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 4466 __be16 src_port; 4467 __be16 dst_port; 4468 __be32 vni; 4469 }; 4470 4471 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 4472 struct hwrm_cfa_encap_record_alloc_input { 4473 __le16 req_type; 4474 __le16 cmpl_ring; 4475 __le16 seq_id; 4476 __le16 target_id; 4477 __le64 resp_addr; 4478 __le32 flags; 4479 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4480 u8 encap_type; 4481 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4482 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4483 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4484 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4485 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4486 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4487 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4488 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4489 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 4490 u8 unused_0[3]; 4491 __le32 encap_data[20]; 4492 }; 4493 4494 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 4495 struct hwrm_cfa_encap_record_alloc_output { 4496 __le16 error_code; 4497 __le16 req_type; 4498 __le16 seq_id; 4499 __le16 resp_len; 4500 __le32 encap_record_id; 4501 u8 unused_0[3]; 4502 u8 valid; 4503 }; 4504 4505 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 4506 struct hwrm_cfa_encap_record_free_input { 4507 __le16 req_type; 4508 __le16 cmpl_ring; 4509 __le16 seq_id; 4510 __le16 target_id; 4511 __le64 resp_addr; 4512 __le32 encap_record_id; 4513 u8 unused_0[4]; 4514 }; 4515 4516 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 4517 struct hwrm_cfa_encap_record_free_output { 4518 __le16 error_code; 4519 __le16 req_type; 4520 __le16 seq_id; 4521 __le16 resp_len; 4522 u8 unused_0[7]; 4523 u8 valid; 4524 }; 4525 4526 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 4527 struct hwrm_cfa_ntuple_filter_alloc_input { 4528 __le16 req_type; 4529 __le16 cmpl_ring; 4530 __le16 seq_id; 4531 __le16 target_id; 4532 __le64 resp_addr; 4533 __le32 flags; 4534 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4535 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4536 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4537 __le32 enables; 4538 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4539 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4540 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4541 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4542 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4543 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4544 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4545 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4552 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4553 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4554 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4555 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4556 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4557 __le64 l2_filter_id; 4558 u8 src_macaddr[6]; 4559 __be16 ethertype; 4560 u8 ip_addr_type; 4561 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4562 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4563 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4564 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 4565 u8 ip_protocol; 4566 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4567 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4568 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4569 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 4570 __le16 dst_id; 4571 __le16 mirror_vnic_id; 4572 u8 tunnel_type; 4573 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4574 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4575 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4576 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4577 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4578 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4579 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4580 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4581 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4582 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4583 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4584 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4585 u8 pri_hint; 4586 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4587 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4588 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4589 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4590 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4591 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 4592 __be32 src_ipaddr[4]; 4593 __be32 src_ipaddr_mask[4]; 4594 __be32 dst_ipaddr[4]; 4595 __be32 dst_ipaddr_mask[4]; 4596 __be16 src_port; 4597 __be16 src_port_mask; 4598 __be16 dst_port; 4599 __be16 dst_port_mask; 4600 __le64 ntuple_filter_id_hint; 4601 }; 4602 4603 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 4604 struct hwrm_cfa_ntuple_filter_alloc_output { 4605 __le16 error_code; 4606 __le16 req_type; 4607 __le16 seq_id; 4608 __le16 resp_len; 4609 __le64 ntuple_filter_id; 4610 __le32 flow_id; 4611 u8 unused_0[3]; 4612 u8 valid; 4613 }; 4614 4615 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 4616 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 4617 u8 code; 4618 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 4619 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 4620 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 4621 u8 unused_0[7]; 4622 }; 4623 4624 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 4625 struct hwrm_cfa_ntuple_filter_free_input { 4626 __le16 req_type; 4627 __le16 cmpl_ring; 4628 __le16 seq_id; 4629 __le16 target_id; 4630 __le64 resp_addr; 4631 __le64 ntuple_filter_id; 4632 }; 4633 4634 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 4635 struct hwrm_cfa_ntuple_filter_free_output { 4636 __le16 error_code; 4637 __le16 req_type; 4638 __le16 seq_id; 4639 __le16 resp_len; 4640 u8 unused_0[7]; 4641 u8 valid; 4642 }; 4643 4644 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 4645 struct hwrm_cfa_ntuple_filter_cfg_input { 4646 __le16 req_type; 4647 __le16 cmpl_ring; 4648 __le16 seq_id; 4649 __le16 target_id; 4650 __le64 resp_addr; 4651 __le32 enables; 4652 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4653 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4654 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4655 u8 unused_0[4]; 4656 __le64 ntuple_filter_id; 4657 __le32 new_dst_id; 4658 __le32 new_mirror_vnic_id; 4659 __le16 new_meter_instance_id; 4660 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4661 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 4662 u8 unused_1[6]; 4663 }; 4664 4665 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 4666 struct hwrm_cfa_ntuple_filter_cfg_output { 4667 __le16 error_code; 4668 __le16 req_type; 4669 __le16 seq_id; 4670 __le16 resp_len; 4671 u8 unused_0[7]; 4672 u8 valid; 4673 }; 4674 4675 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 4676 struct hwrm_cfa_decap_filter_alloc_input { 4677 __le16 req_type; 4678 __le16 cmpl_ring; 4679 __le16 seq_id; 4680 __le16 target_id; 4681 __le64 resp_addr; 4682 __le32 flags; 4683 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 4684 __le32 enables; 4685 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 4686 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 4687 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 4688 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 4689 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 4690 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 4691 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 4692 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 4693 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 4694 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 4695 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 4696 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 4697 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 4698 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 4699 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 4700 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4701 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4702 __be32 tunnel_id; 4703 u8 tunnel_type; 4704 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4705 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4706 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4707 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4708 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4709 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4710 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4711 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4712 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4713 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4714 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4715 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4716 u8 unused_0; 4717 __le16 unused_1; 4718 u8 src_macaddr[6]; 4719 u8 unused_2[2]; 4720 u8 dst_macaddr[6]; 4721 __be16 ovlan_vid; 4722 __be16 ivlan_vid; 4723 __be16 t_ovlan_vid; 4724 __be16 t_ivlan_vid; 4725 __be16 ethertype; 4726 u8 ip_addr_type; 4727 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4728 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4729 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4730 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 4731 u8 ip_protocol; 4732 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4733 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4734 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4735 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 4736 __le16 unused_3; 4737 __le32 unused_4; 4738 __be32 src_ipaddr[4]; 4739 __be32 dst_ipaddr[4]; 4740 __be16 src_port; 4741 __be16 dst_port; 4742 __le16 dst_id; 4743 __le16 l2_ctxt_ref_id; 4744 }; 4745 4746 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 4747 struct hwrm_cfa_decap_filter_alloc_output { 4748 __le16 error_code; 4749 __le16 req_type; 4750 __le16 seq_id; 4751 __le16 resp_len; 4752 __le32 decap_filter_id; 4753 u8 unused_0[3]; 4754 u8 valid; 4755 }; 4756 4757 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 4758 struct hwrm_cfa_decap_filter_free_input { 4759 __le16 req_type; 4760 __le16 cmpl_ring; 4761 __le16 seq_id; 4762 __le16 target_id; 4763 __le64 resp_addr; 4764 __le32 decap_filter_id; 4765 u8 unused_0[4]; 4766 }; 4767 4768 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 4769 struct hwrm_cfa_decap_filter_free_output { 4770 __le16 error_code; 4771 __le16 req_type; 4772 __le16 seq_id; 4773 __le16 resp_len; 4774 u8 unused_0[7]; 4775 u8 valid; 4776 }; 4777 4778 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 4779 struct hwrm_cfa_flow_alloc_input { 4780 __le16 req_type; 4781 __le16 cmpl_ring; 4782 __le16 seq_id; 4783 __le16 target_id; 4784 __le64 resp_addr; 4785 __le16 flags; 4786 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 4787 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 4788 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 4789 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 4790 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 4791 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 4792 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 4793 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 4794 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 4795 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 4796 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 4797 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 4798 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 4799 __le16 src_fid; 4800 __le32 tunnel_handle; 4801 __le16 action_flags; 4802 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 4803 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 4804 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 4805 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 4806 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 4807 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 4808 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 4809 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 4810 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 4811 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 4812 __le16 dst_fid; 4813 __be16 l2_rewrite_vlan_tpid; 4814 __be16 l2_rewrite_vlan_tci; 4815 __le16 act_meter_id; 4816 __le16 ref_flow_handle; 4817 __be16 ethertype; 4818 __be16 outer_vlan_tci; 4819 __be16 dmac[3]; 4820 __be16 inner_vlan_tci; 4821 __be16 smac[3]; 4822 u8 ip_dst_mask_len; 4823 u8 ip_src_mask_len; 4824 __be32 ip_dst[4]; 4825 __be32 ip_src[4]; 4826 __be16 l4_src_port; 4827 __be16 l4_src_port_mask; 4828 __be16 l4_dst_port; 4829 __be16 l4_dst_port_mask; 4830 __be32 nat_ip_address[4]; 4831 __be16 l2_rewrite_dmac[3]; 4832 __be16 nat_port; 4833 __be16 l2_rewrite_smac[3]; 4834 u8 ip_proto; 4835 u8 unused_0; 4836 }; 4837 4838 /* hwrm_cfa_flow_alloc_output (size:128b/16B) */ 4839 struct hwrm_cfa_flow_alloc_output { 4840 __le16 error_code; 4841 __le16 req_type; 4842 __le16 seq_id; 4843 __le16 resp_len; 4844 __le16 flow_handle; 4845 u8 unused_0[5]; 4846 u8 valid; 4847 }; 4848 4849 /* hwrm_cfa_flow_free_input (size:192b/24B) */ 4850 struct hwrm_cfa_flow_free_input { 4851 __le16 req_type; 4852 __le16 cmpl_ring; 4853 __le16 seq_id; 4854 __le16 target_id; 4855 __le64 resp_addr; 4856 __le16 flow_handle; 4857 u8 unused_0[6]; 4858 }; 4859 4860 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 4861 struct hwrm_cfa_flow_free_output { 4862 __le16 error_code; 4863 __le16 req_type; 4864 __le16 seq_id; 4865 __le16 resp_len; 4866 __le64 packet; 4867 __le64 byte; 4868 u8 unused_0[7]; 4869 u8 valid; 4870 }; 4871 4872 /* hwrm_cfa_flow_stats_input (size:320b/40B) */ 4873 struct hwrm_cfa_flow_stats_input { 4874 __le16 req_type; 4875 __le16 cmpl_ring; 4876 __le16 seq_id; 4877 __le16 target_id; 4878 __le64 resp_addr; 4879 __le16 num_flows; 4880 __le16 flow_handle_0; 4881 __le16 flow_handle_1; 4882 __le16 flow_handle_2; 4883 __le16 flow_handle_3; 4884 __le16 flow_handle_4; 4885 __le16 flow_handle_5; 4886 __le16 flow_handle_6; 4887 __le16 flow_handle_7; 4888 __le16 flow_handle_8; 4889 __le16 flow_handle_9; 4890 u8 unused_0[2]; 4891 }; 4892 4893 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 4894 struct hwrm_cfa_flow_stats_output { 4895 __le16 error_code; 4896 __le16 req_type; 4897 __le16 seq_id; 4898 __le16 resp_len; 4899 __le64 packet_0; 4900 __le64 packet_1; 4901 __le64 packet_2; 4902 __le64 packet_3; 4903 __le64 packet_4; 4904 __le64 packet_5; 4905 __le64 packet_6; 4906 __le64 packet_7; 4907 __le64 packet_8; 4908 __le64 packet_9; 4909 __le64 byte_0; 4910 __le64 byte_1; 4911 __le64 byte_2; 4912 __le64 byte_3; 4913 __le64 byte_4; 4914 __le64 byte_5; 4915 __le64 byte_6; 4916 __le64 byte_7; 4917 __le64 byte_8; 4918 __le64 byte_9; 4919 u8 unused_0[7]; 4920 u8 valid; 4921 }; 4922 4923 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 4924 struct hwrm_cfa_vfr_alloc_input { 4925 __le16 req_type; 4926 __le16 cmpl_ring; 4927 __le16 seq_id; 4928 __le16 target_id; 4929 __le64 resp_addr; 4930 __le16 vf_id; 4931 __le16 reserved; 4932 u8 unused_0[4]; 4933 char vfr_name[32]; 4934 }; 4935 4936 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 4937 struct hwrm_cfa_vfr_alloc_output { 4938 __le16 error_code; 4939 __le16 req_type; 4940 __le16 seq_id; 4941 __le16 resp_len; 4942 __le16 rx_cfa_code; 4943 __le16 tx_cfa_action; 4944 u8 unused_0[3]; 4945 u8 valid; 4946 }; 4947 4948 /* hwrm_cfa_vfr_free_input (size:384b/48B) */ 4949 struct hwrm_cfa_vfr_free_input { 4950 __le16 req_type; 4951 __le16 cmpl_ring; 4952 __le16 seq_id; 4953 __le16 target_id; 4954 __le64 resp_addr; 4955 char vfr_name[32]; 4956 }; 4957 4958 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 4959 struct hwrm_cfa_vfr_free_output { 4960 __le16 error_code; 4961 __le16 req_type; 4962 __le16 seq_id; 4963 __le16 resp_len; 4964 u8 unused_0[7]; 4965 u8 valid; 4966 }; 4967 4968 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 4969 struct hwrm_tunnel_dst_port_query_input { 4970 __le16 req_type; 4971 __le16 cmpl_ring; 4972 __le16 seq_id; 4973 __le16 target_id; 4974 __le64 resp_addr; 4975 u8 tunnel_type; 4976 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4977 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4978 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4979 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 4980 u8 unused_0[7]; 4981 }; 4982 4983 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 4984 struct hwrm_tunnel_dst_port_query_output { 4985 __le16 error_code; 4986 __le16 req_type; 4987 __le16 seq_id; 4988 __le16 resp_len; 4989 __le16 tunnel_dst_port_id; 4990 __be16 tunnel_dst_port_val; 4991 u8 unused_0[3]; 4992 u8 valid; 4993 }; 4994 4995 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 4996 struct hwrm_tunnel_dst_port_alloc_input { 4997 __le16 req_type; 4998 __le16 cmpl_ring; 4999 __le16 seq_id; 5000 __le16 target_id; 5001 __le64 resp_addr; 5002 u8 tunnel_type; 5003 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5004 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5005 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5006 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 5007 u8 unused_0; 5008 __be16 tunnel_dst_port_val; 5009 u8 unused_1[4]; 5010 }; 5011 5012 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 5013 struct hwrm_tunnel_dst_port_alloc_output { 5014 __le16 error_code; 5015 __le16 req_type; 5016 __le16 seq_id; 5017 __le16 resp_len; 5018 __le16 tunnel_dst_port_id; 5019 u8 unused_0[5]; 5020 u8 valid; 5021 }; 5022 5023 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 5024 struct hwrm_tunnel_dst_port_free_input { 5025 __le16 req_type; 5026 __le16 cmpl_ring; 5027 __le16 seq_id; 5028 __le16 target_id; 5029 __le64 resp_addr; 5030 u8 tunnel_type; 5031 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5032 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5033 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5034 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 5035 u8 unused_0; 5036 __le16 tunnel_dst_port_id; 5037 u8 unused_1[4]; 5038 }; 5039 5040 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 5041 struct hwrm_tunnel_dst_port_free_output { 5042 __le16 error_code; 5043 __le16 req_type; 5044 __le16 seq_id; 5045 __le16 resp_len; 5046 u8 unused_1[7]; 5047 u8 valid; 5048 }; 5049 5050 /* ctx_hw_stats (size:1280b/160B) */ 5051 struct ctx_hw_stats { 5052 __le64 rx_ucast_pkts; 5053 __le64 rx_mcast_pkts; 5054 __le64 rx_bcast_pkts; 5055 __le64 rx_discard_pkts; 5056 __le64 rx_drop_pkts; 5057 __le64 rx_ucast_bytes; 5058 __le64 rx_mcast_bytes; 5059 __le64 rx_bcast_bytes; 5060 __le64 tx_ucast_pkts; 5061 __le64 tx_mcast_pkts; 5062 __le64 tx_bcast_pkts; 5063 __le64 tx_discard_pkts; 5064 __le64 tx_drop_pkts; 5065 __le64 tx_ucast_bytes; 5066 __le64 tx_mcast_bytes; 5067 __le64 tx_bcast_bytes; 5068 __le64 tpa_pkts; 5069 __le64 tpa_bytes; 5070 __le64 tpa_events; 5071 __le64 tpa_aborts; 5072 }; 5073 5074 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 5075 struct hwrm_stat_ctx_alloc_input { 5076 __le16 req_type; 5077 __le16 cmpl_ring; 5078 __le16 seq_id; 5079 __le16 target_id; 5080 __le64 resp_addr; 5081 __le64 stats_dma_addr; 5082 __le32 update_period_ms; 5083 u8 stat_ctx_flags; 5084 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 5085 u8 unused_0[3]; 5086 }; 5087 5088 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 5089 struct hwrm_stat_ctx_alloc_output { 5090 __le16 error_code; 5091 __le16 req_type; 5092 __le16 seq_id; 5093 __le16 resp_len; 5094 __le32 stat_ctx_id; 5095 u8 unused_0[3]; 5096 u8 valid; 5097 }; 5098 5099 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 5100 struct hwrm_stat_ctx_free_input { 5101 __le16 req_type; 5102 __le16 cmpl_ring; 5103 __le16 seq_id; 5104 __le16 target_id; 5105 __le64 resp_addr; 5106 __le32 stat_ctx_id; 5107 u8 unused_0[4]; 5108 }; 5109 5110 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 5111 struct hwrm_stat_ctx_free_output { 5112 __le16 error_code; 5113 __le16 req_type; 5114 __le16 seq_id; 5115 __le16 resp_len; 5116 __le32 stat_ctx_id; 5117 u8 unused_0[3]; 5118 u8 valid; 5119 }; 5120 5121 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 5122 struct hwrm_stat_ctx_query_input { 5123 __le16 req_type; 5124 __le16 cmpl_ring; 5125 __le16 seq_id; 5126 __le16 target_id; 5127 __le64 resp_addr; 5128 __le32 stat_ctx_id; 5129 u8 unused_0[4]; 5130 }; 5131 5132 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 5133 struct hwrm_stat_ctx_query_output { 5134 __le16 error_code; 5135 __le16 req_type; 5136 __le16 seq_id; 5137 __le16 resp_len; 5138 __le64 tx_ucast_pkts; 5139 __le64 tx_mcast_pkts; 5140 __le64 tx_bcast_pkts; 5141 __le64 tx_err_pkts; 5142 __le64 tx_drop_pkts; 5143 __le64 tx_ucast_bytes; 5144 __le64 tx_mcast_bytes; 5145 __le64 tx_bcast_bytes; 5146 __le64 rx_ucast_pkts; 5147 __le64 rx_mcast_pkts; 5148 __le64 rx_bcast_pkts; 5149 __le64 rx_err_pkts; 5150 __le64 rx_drop_pkts; 5151 __le64 rx_ucast_bytes; 5152 __le64 rx_mcast_bytes; 5153 __le64 rx_bcast_bytes; 5154 __le64 rx_agg_pkts; 5155 __le64 rx_agg_bytes; 5156 __le64 rx_agg_events; 5157 __le64 rx_agg_aborts; 5158 u8 unused_0[7]; 5159 u8 valid; 5160 }; 5161 5162 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 5163 struct hwrm_stat_ctx_clr_stats_input { 5164 __le16 req_type; 5165 __le16 cmpl_ring; 5166 __le16 seq_id; 5167 __le16 target_id; 5168 __le64 resp_addr; 5169 __le32 stat_ctx_id; 5170 u8 unused_0[4]; 5171 }; 5172 5173 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 5174 struct hwrm_stat_ctx_clr_stats_output { 5175 __le16 error_code; 5176 __le16 req_type; 5177 __le16 seq_id; 5178 __le16 resp_len; 5179 u8 unused_0[7]; 5180 u8 valid; 5181 }; 5182 5183 /* tx_port_stats (size:3264b/408B) */ 5184 struct tx_port_stats { 5185 __le64 tx_64b_frames; 5186 __le64 tx_65b_127b_frames; 5187 __le64 tx_128b_255b_frames; 5188 __le64 tx_256b_511b_frames; 5189 __le64 tx_512b_1023b_frames; 5190 __le64 tx_1024b_1518_frames; 5191 __le64 tx_good_vlan_frames; 5192 __le64 tx_1519b_2047_frames; 5193 __le64 tx_2048b_4095b_frames; 5194 __le64 tx_4096b_9216b_frames; 5195 __le64 tx_9217b_16383b_frames; 5196 __le64 tx_good_frames; 5197 __le64 tx_total_frames; 5198 __le64 tx_ucast_frames; 5199 __le64 tx_mcast_frames; 5200 __le64 tx_bcast_frames; 5201 __le64 tx_pause_frames; 5202 __le64 tx_pfc_frames; 5203 __le64 tx_jabber_frames; 5204 __le64 tx_fcs_err_frames; 5205 __le64 tx_control_frames; 5206 __le64 tx_oversz_frames; 5207 __le64 tx_single_dfrl_frames; 5208 __le64 tx_multi_dfrl_frames; 5209 __le64 tx_single_coll_frames; 5210 __le64 tx_multi_coll_frames; 5211 __le64 tx_late_coll_frames; 5212 __le64 tx_excessive_coll_frames; 5213 __le64 tx_frag_frames; 5214 __le64 tx_err; 5215 __le64 tx_tagged_frames; 5216 __le64 tx_dbl_tagged_frames; 5217 __le64 tx_runt_frames; 5218 __le64 tx_fifo_underruns; 5219 __le64 tx_pfc_ena_frames_pri0; 5220 __le64 tx_pfc_ena_frames_pri1; 5221 __le64 tx_pfc_ena_frames_pri2; 5222 __le64 tx_pfc_ena_frames_pri3; 5223 __le64 tx_pfc_ena_frames_pri4; 5224 __le64 tx_pfc_ena_frames_pri5; 5225 __le64 tx_pfc_ena_frames_pri6; 5226 __le64 tx_pfc_ena_frames_pri7; 5227 __le64 tx_eee_lpi_events; 5228 __le64 tx_eee_lpi_duration; 5229 __le64 tx_llfc_logical_msgs; 5230 __le64 tx_hcfc_msgs; 5231 __le64 tx_total_collisions; 5232 __le64 tx_bytes; 5233 __le64 tx_xthol_frames; 5234 __le64 tx_stat_discard; 5235 __le64 tx_stat_error; 5236 }; 5237 5238 /* rx_port_stats (size:4224b/528B) */ 5239 struct rx_port_stats { 5240 __le64 rx_64b_frames; 5241 __le64 rx_65b_127b_frames; 5242 __le64 rx_128b_255b_frames; 5243 __le64 rx_256b_511b_frames; 5244 __le64 rx_512b_1023b_frames; 5245 __le64 rx_1024b_1518_frames; 5246 __le64 rx_good_vlan_frames; 5247 __le64 rx_1519b_2047b_frames; 5248 __le64 rx_2048b_4095b_frames; 5249 __le64 rx_4096b_9216b_frames; 5250 __le64 rx_9217b_16383b_frames; 5251 __le64 rx_total_frames; 5252 __le64 rx_ucast_frames; 5253 __le64 rx_mcast_frames; 5254 __le64 rx_bcast_frames; 5255 __le64 rx_fcs_err_frames; 5256 __le64 rx_ctrl_frames; 5257 __le64 rx_pause_frames; 5258 __le64 rx_pfc_frames; 5259 __le64 rx_unsupported_opcode_frames; 5260 __le64 rx_unsupported_da_pausepfc_frames; 5261 __le64 rx_wrong_sa_frames; 5262 __le64 rx_align_err_frames; 5263 __le64 rx_oor_len_frames; 5264 __le64 rx_code_err_frames; 5265 __le64 rx_false_carrier_frames; 5266 __le64 rx_ovrsz_frames; 5267 __le64 rx_jbr_frames; 5268 __le64 rx_mtu_err_frames; 5269 __le64 rx_match_crc_frames; 5270 __le64 rx_promiscuous_frames; 5271 __le64 rx_tagged_frames; 5272 __le64 rx_double_tagged_frames; 5273 __le64 rx_trunc_frames; 5274 __le64 rx_good_frames; 5275 __le64 rx_pfc_xon2xoff_frames_pri0; 5276 __le64 rx_pfc_xon2xoff_frames_pri1; 5277 __le64 rx_pfc_xon2xoff_frames_pri2; 5278 __le64 rx_pfc_xon2xoff_frames_pri3; 5279 __le64 rx_pfc_xon2xoff_frames_pri4; 5280 __le64 rx_pfc_xon2xoff_frames_pri5; 5281 __le64 rx_pfc_xon2xoff_frames_pri6; 5282 __le64 rx_pfc_xon2xoff_frames_pri7; 5283 __le64 rx_pfc_ena_frames_pri0; 5284 __le64 rx_pfc_ena_frames_pri1; 5285 __le64 rx_pfc_ena_frames_pri2; 5286 __le64 rx_pfc_ena_frames_pri3; 5287 __le64 rx_pfc_ena_frames_pri4; 5288 __le64 rx_pfc_ena_frames_pri5; 5289 __le64 rx_pfc_ena_frames_pri6; 5290 __le64 rx_pfc_ena_frames_pri7; 5291 __le64 rx_sch_crc_err_frames; 5292 __le64 rx_undrsz_frames; 5293 __le64 rx_frag_frames; 5294 __le64 rx_eee_lpi_events; 5295 __le64 rx_eee_lpi_duration; 5296 __le64 rx_llfc_physical_msgs; 5297 __le64 rx_llfc_logical_msgs; 5298 __le64 rx_llfc_msgs_with_crc_err; 5299 __le64 rx_hcfc_msgs; 5300 __le64 rx_hcfc_msgs_with_crc_err; 5301 __le64 rx_bytes; 5302 __le64 rx_runt_bytes; 5303 __le64 rx_runt_frames; 5304 __le64 rx_stat_discard; 5305 __le64 rx_stat_err; 5306 }; 5307 5308 /* hwrm_fw_reset_input (size:192b/24B) */ 5309 struct hwrm_fw_reset_input { 5310 __le16 req_type; 5311 __le16 cmpl_ring; 5312 __le16 seq_id; 5313 __le16 target_id; 5314 __le64 resp_addr; 5315 u8 embedded_proc_type; 5316 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5317 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5318 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5319 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5320 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5321 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5322 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5323 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 5324 u8 selfrst_status; 5325 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 5326 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 5327 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5328 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 5329 u8 host_idx; 5330 u8 unused_0[5]; 5331 }; 5332 5333 /* hwrm_fw_reset_output (size:128b/16B) */ 5334 struct hwrm_fw_reset_output { 5335 __le16 error_code; 5336 __le16 req_type; 5337 __le16 seq_id; 5338 __le16 resp_len; 5339 u8 selfrst_status; 5340 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5341 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5342 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5343 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 5344 u8 unused_0[6]; 5345 u8 valid; 5346 }; 5347 5348 /* hwrm_fw_qstatus_input (size:192b/24B) */ 5349 struct hwrm_fw_qstatus_input { 5350 __le16 req_type; 5351 __le16 cmpl_ring; 5352 __le16 seq_id; 5353 __le16 target_id; 5354 __le64 resp_addr; 5355 u8 embedded_proc_type; 5356 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5357 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5358 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5359 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5360 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5361 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5362 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5363 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 5364 u8 unused_0[7]; 5365 }; 5366 5367 /* hwrm_fw_qstatus_output (size:128b/16B) */ 5368 struct hwrm_fw_qstatus_output { 5369 __le16 error_code; 5370 __le16 req_type; 5371 __le16 seq_id; 5372 __le16 resp_len; 5373 u8 selfrst_status; 5374 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5375 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5376 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5377 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 5378 u8 unused_0[6]; 5379 u8 valid; 5380 }; 5381 5382 /* hwrm_fw_set_time_input (size:256b/32B) */ 5383 struct hwrm_fw_set_time_input { 5384 __le16 req_type; 5385 __le16 cmpl_ring; 5386 __le16 seq_id; 5387 __le16 target_id; 5388 __le64 resp_addr; 5389 __le16 year; 5390 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 5391 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 5392 u8 month; 5393 u8 day; 5394 u8 hour; 5395 u8 minute; 5396 u8 second; 5397 u8 unused_0; 5398 __le16 millisecond; 5399 __le16 zone; 5400 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 5401 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 5402 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 5403 u8 unused_1[4]; 5404 }; 5405 5406 /* hwrm_fw_set_time_output (size:128b/16B) */ 5407 struct hwrm_fw_set_time_output { 5408 __le16 error_code; 5409 __le16 req_type; 5410 __le16 seq_id; 5411 __le16 resp_len; 5412 u8 unused_0[7]; 5413 u8 valid; 5414 }; 5415 5416 /* hwrm_struct_hdr (size:128b/16B) */ 5417 struct hwrm_struct_hdr { 5418 __le16 struct_id; 5419 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 5420 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 5421 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 5422 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 5423 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 5424 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 5425 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 5426 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 5427 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 5428 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 5429 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 5430 __le16 len; 5431 u8 version; 5432 u8 count; 5433 __le16 subtype; 5434 __le16 next_offset; 5435 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 5436 u8 unused_0[6]; 5437 }; 5438 5439 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 5440 struct hwrm_struct_data_dcbx_app { 5441 __be16 protocol_id; 5442 u8 protocol_selector; 5443 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 5444 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 5445 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 5446 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 5447 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 5448 u8 priority; 5449 u8 valid; 5450 u8 unused_0[3]; 5451 }; 5452 5453 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 5454 struct hwrm_fw_set_structured_data_input { 5455 __le16 req_type; 5456 __le16 cmpl_ring; 5457 __le16 seq_id; 5458 __le16 target_id; 5459 __le64 resp_addr; 5460 __le64 src_data_addr; 5461 __le16 data_len; 5462 u8 hdr_cnt; 5463 u8 unused_0[5]; 5464 }; 5465 5466 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 5467 struct hwrm_fw_set_structured_data_output { 5468 __le16 error_code; 5469 __le16 req_type; 5470 __le16 seq_id; 5471 __le16 resp_len; 5472 u8 unused_0[7]; 5473 u8 valid; 5474 }; 5475 5476 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 5477 struct hwrm_fw_set_structured_data_cmd_err { 5478 u8 code; 5479 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5480 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 5481 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 5482 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5483 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 5484 u8 unused_0[7]; 5485 }; 5486 5487 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 5488 struct hwrm_fw_get_structured_data_input { 5489 __le16 req_type; 5490 __le16 cmpl_ring; 5491 __le16 seq_id; 5492 __le16 target_id; 5493 __le64 resp_addr; 5494 __le64 dest_data_addr; 5495 __le16 data_len; 5496 __le16 structure_id; 5497 __le16 subtype; 5498 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 5499 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 5500 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 5501 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 5502 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 5503 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 5504 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 5505 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 5506 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 5507 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 5508 u8 count; 5509 u8 unused_0; 5510 }; 5511 5512 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 5513 struct hwrm_fw_get_structured_data_output { 5514 __le16 error_code; 5515 __le16 req_type; 5516 __le16 seq_id; 5517 __le16 resp_len; 5518 u8 hdr_cnt; 5519 u8 unused_0[6]; 5520 u8 valid; 5521 }; 5522 5523 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 5524 struct hwrm_fw_get_structured_data_cmd_err { 5525 u8 code; 5526 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5527 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5528 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 5529 u8 unused_0[7]; 5530 }; 5531 5532 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 5533 struct hwrm_exec_fwd_resp_input { 5534 __le16 req_type; 5535 __le16 cmpl_ring; 5536 __le16 seq_id; 5537 __le16 target_id; 5538 __le64 resp_addr; 5539 __le32 encap_request[26]; 5540 __le16 encap_resp_target_id; 5541 u8 unused_0[6]; 5542 }; 5543 5544 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 5545 struct hwrm_exec_fwd_resp_output { 5546 __le16 error_code; 5547 __le16 req_type; 5548 __le16 seq_id; 5549 __le16 resp_len; 5550 u8 unused_0[7]; 5551 u8 valid; 5552 }; 5553 5554 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 5555 struct hwrm_reject_fwd_resp_input { 5556 __le16 req_type; 5557 __le16 cmpl_ring; 5558 __le16 seq_id; 5559 __le16 target_id; 5560 __le64 resp_addr; 5561 __le32 encap_request[26]; 5562 __le16 encap_resp_target_id; 5563 u8 unused_0[6]; 5564 }; 5565 5566 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 5567 struct hwrm_reject_fwd_resp_output { 5568 __le16 error_code; 5569 __le16 req_type; 5570 __le16 seq_id; 5571 __le16 resp_len; 5572 u8 unused_0[7]; 5573 u8 valid; 5574 }; 5575 5576 /* hwrm_fwd_resp_input (size:1024b/128B) */ 5577 struct hwrm_fwd_resp_input { 5578 __le16 req_type; 5579 __le16 cmpl_ring; 5580 __le16 seq_id; 5581 __le16 target_id; 5582 __le64 resp_addr; 5583 __le16 encap_resp_target_id; 5584 __le16 encap_resp_cmpl_ring; 5585 __le16 encap_resp_len; 5586 u8 unused_0; 5587 u8 unused_1; 5588 __le64 encap_resp_addr; 5589 __le32 encap_resp[24]; 5590 }; 5591 5592 /* hwrm_fwd_resp_output (size:128b/16B) */ 5593 struct hwrm_fwd_resp_output { 5594 __le16 error_code; 5595 __le16 req_type; 5596 __le16 seq_id; 5597 __le16 resp_len; 5598 u8 unused_0[7]; 5599 u8 valid; 5600 }; 5601 5602 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 5603 struct hwrm_fwd_async_event_cmpl_input { 5604 __le16 req_type; 5605 __le16 cmpl_ring; 5606 __le16 seq_id; 5607 __le16 target_id; 5608 __le64 resp_addr; 5609 __le16 encap_async_event_target_id; 5610 u8 unused_0[6]; 5611 __le32 encap_async_event_cmpl[4]; 5612 }; 5613 5614 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 5615 struct hwrm_fwd_async_event_cmpl_output { 5616 __le16 error_code; 5617 __le16 req_type; 5618 __le16 seq_id; 5619 __le16 resp_len; 5620 u8 unused_0[7]; 5621 u8 valid; 5622 }; 5623 5624 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 5625 struct hwrm_temp_monitor_query_input { 5626 __le16 req_type; 5627 __le16 cmpl_ring; 5628 __le16 seq_id; 5629 __le16 target_id; 5630 __le64 resp_addr; 5631 }; 5632 5633 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 5634 struct hwrm_temp_monitor_query_output { 5635 __le16 error_code; 5636 __le16 req_type; 5637 __le16 seq_id; 5638 __le16 resp_len; 5639 u8 temp; 5640 u8 unused_0[6]; 5641 u8 valid; 5642 }; 5643 5644 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 5645 struct hwrm_wol_filter_alloc_input { 5646 __le16 req_type; 5647 __le16 cmpl_ring; 5648 __le16 seq_id; 5649 __le16 target_id; 5650 __le64 resp_addr; 5651 __le32 flags; 5652 __le32 enables; 5653 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 5654 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 5655 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 5656 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 5657 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 5658 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 5659 __le16 port_id; 5660 u8 wol_type; 5661 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 5662 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 5663 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 5664 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 5665 u8 unused_0[5]; 5666 u8 mac_address[6]; 5667 __le16 pattern_offset; 5668 __le16 pattern_buf_size; 5669 __le16 pattern_mask_size; 5670 u8 unused_1[4]; 5671 __le64 pattern_buf_addr; 5672 __le64 pattern_mask_addr; 5673 }; 5674 5675 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 5676 struct hwrm_wol_filter_alloc_output { 5677 __le16 error_code; 5678 __le16 req_type; 5679 __le16 seq_id; 5680 __le16 resp_len; 5681 u8 wol_filter_id; 5682 u8 unused_0[6]; 5683 u8 valid; 5684 }; 5685 5686 /* hwrm_wol_filter_free_input (size:256b/32B) */ 5687 struct hwrm_wol_filter_free_input { 5688 __le16 req_type; 5689 __le16 cmpl_ring; 5690 __le16 seq_id; 5691 __le16 target_id; 5692 __le64 resp_addr; 5693 __le32 flags; 5694 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 5695 __le32 enables; 5696 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 5697 __le16 port_id; 5698 u8 wol_filter_id; 5699 u8 unused_0[5]; 5700 }; 5701 5702 /* hwrm_wol_filter_free_output (size:128b/16B) */ 5703 struct hwrm_wol_filter_free_output { 5704 __le16 error_code; 5705 __le16 req_type; 5706 __le16 seq_id; 5707 __le16 resp_len; 5708 u8 unused_0[7]; 5709 u8 valid; 5710 }; 5711 5712 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 5713 struct hwrm_wol_filter_qcfg_input { 5714 __le16 req_type; 5715 __le16 cmpl_ring; 5716 __le16 seq_id; 5717 __le16 target_id; 5718 __le64 resp_addr; 5719 __le16 port_id; 5720 __le16 handle; 5721 u8 unused_0[4]; 5722 __le64 pattern_buf_addr; 5723 __le16 pattern_buf_size; 5724 u8 unused_1[6]; 5725 __le64 pattern_mask_addr; 5726 __le16 pattern_mask_size; 5727 u8 unused_2[6]; 5728 }; 5729 5730 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 5731 struct hwrm_wol_filter_qcfg_output { 5732 __le16 error_code; 5733 __le16 req_type; 5734 __le16 seq_id; 5735 __le16 resp_len; 5736 __le16 next_handle; 5737 u8 wol_filter_id; 5738 u8 wol_type; 5739 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 5740 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 5741 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 5742 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 5743 __le32 unused_0; 5744 u8 mac_address[6]; 5745 __le16 pattern_offset; 5746 __le16 pattern_size; 5747 __le16 pattern_mask_size; 5748 u8 unused_1[3]; 5749 u8 valid; 5750 }; 5751 5752 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 5753 struct hwrm_wol_reason_qcfg_input { 5754 __le16 req_type; 5755 __le16 cmpl_ring; 5756 __le16 seq_id; 5757 __le16 target_id; 5758 __le64 resp_addr; 5759 __le16 port_id; 5760 u8 unused_0[6]; 5761 __le64 wol_pkt_buf_addr; 5762 __le16 wol_pkt_buf_size; 5763 u8 unused_1[6]; 5764 }; 5765 5766 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 5767 struct hwrm_wol_reason_qcfg_output { 5768 __le16 error_code; 5769 __le16 req_type; 5770 __le16 seq_id; 5771 __le16 resp_len; 5772 u8 wol_filter_id; 5773 u8 wol_reason; 5774 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 5775 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 5776 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 5777 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 5778 u8 wol_pkt_len; 5779 u8 unused_0[4]; 5780 u8 valid; 5781 }; 5782 5783 /* hwrm_nvm_read_input (size:320b/40B) */ 5784 struct hwrm_nvm_read_input { 5785 __le16 req_type; 5786 __le16 cmpl_ring; 5787 __le16 seq_id; 5788 __le16 target_id; 5789 __le64 resp_addr; 5790 __le64 host_dest_addr; 5791 __le16 dir_idx; 5792 u8 unused_0[2]; 5793 __le32 offset; 5794 __le32 len; 5795 u8 unused_1[4]; 5796 }; 5797 5798 /* hwrm_nvm_read_output (size:128b/16B) */ 5799 struct hwrm_nvm_read_output { 5800 __le16 error_code; 5801 __le16 req_type; 5802 __le16 seq_id; 5803 __le16 resp_len; 5804 u8 unused_0[7]; 5805 u8 valid; 5806 }; 5807 5808 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 5809 struct hwrm_nvm_get_dir_entries_input { 5810 __le16 req_type; 5811 __le16 cmpl_ring; 5812 __le16 seq_id; 5813 __le16 target_id; 5814 __le64 resp_addr; 5815 __le64 host_dest_addr; 5816 }; 5817 5818 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 5819 struct hwrm_nvm_get_dir_entries_output { 5820 __le16 error_code; 5821 __le16 req_type; 5822 __le16 seq_id; 5823 __le16 resp_len; 5824 u8 unused_0[7]; 5825 u8 valid; 5826 }; 5827 5828 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 5829 struct hwrm_nvm_get_dir_info_input { 5830 __le16 req_type; 5831 __le16 cmpl_ring; 5832 __le16 seq_id; 5833 __le16 target_id; 5834 __le64 resp_addr; 5835 }; 5836 5837 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 5838 struct hwrm_nvm_get_dir_info_output { 5839 __le16 error_code; 5840 __le16 req_type; 5841 __le16 seq_id; 5842 __le16 resp_len; 5843 __le32 entries; 5844 __le32 entry_length; 5845 u8 unused_0[7]; 5846 u8 valid; 5847 }; 5848 5849 /* hwrm_nvm_write_input (size:384b/48B) */ 5850 struct hwrm_nvm_write_input { 5851 __le16 req_type; 5852 __le16 cmpl_ring; 5853 __le16 seq_id; 5854 __le16 target_id; 5855 __le64 resp_addr; 5856 __le64 host_src_addr; 5857 __le16 dir_type; 5858 __le16 dir_ordinal; 5859 __le16 dir_ext; 5860 __le16 dir_attr; 5861 __le32 dir_data_length; 5862 __le16 option; 5863 __le16 flags; 5864 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5865 __le32 dir_item_length; 5866 __le32 unused_0; 5867 }; 5868 5869 /* hwrm_nvm_write_output (size:128b/16B) */ 5870 struct hwrm_nvm_write_output { 5871 __le16 error_code; 5872 __le16 req_type; 5873 __le16 seq_id; 5874 __le16 resp_len; 5875 __le32 dir_item_length; 5876 __le16 dir_idx; 5877 u8 unused_0; 5878 u8 valid; 5879 }; 5880 5881 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 5882 struct hwrm_nvm_write_cmd_err { 5883 u8 code; 5884 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 5885 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5886 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 5887 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 5888 u8 unused_0[7]; 5889 }; 5890 5891 /* hwrm_nvm_modify_input (size:320b/40B) */ 5892 struct hwrm_nvm_modify_input { 5893 __le16 req_type; 5894 __le16 cmpl_ring; 5895 __le16 seq_id; 5896 __le16 target_id; 5897 __le64 resp_addr; 5898 __le64 host_src_addr; 5899 __le16 dir_idx; 5900 u8 unused_0[2]; 5901 __le32 offset; 5902 __le32 len; 5903 u8 unused_1[4]; 5904 }; 5905 5906 /* hwrm_nvm_modify_output (size:128b/16B) */ 5907 struct hwrm_nvm_modify_output { 5908 __le16 error_code; 5909 __le16 req_type; 5910 __le16 seq_id; 5911 __le16 resp_len; 5912 u8 unused_0[7]; 5913 u8 valid; 5914 }; 5915 5916 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 5917 struct hwrm_nvm_find_dir_entry_input { 5918 __le16 req_type; 5919 __le16 cmpl_ring; 5920 __le16 seq_id; 5921 __le16 target_id; 5922 __le64 resp_addr; 5923 __le32 enables; 5924 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 5925 __le16 dir_idx; 5926 __le16 dir_type; 5927 __le16 dir_ordinal; 5928 __le16 dir_ext; 5929 u8 opt_ordinal; 5930 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 5931 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 5932 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 5933 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 5934 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 5935 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 5936 u8 unused_0[3]; 5937 }; 5938 5939 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 5940 struct hwrm_nvm_find_dir_entry_output { 5941 __le16 error_code; 5942 __le16 req_type; 5943 __le16 seq_id; 5944 __le16 resp_len; 5945 __le32 dir_item_length; 5946 __le32 dir_data_length; 5947 __le32 fw_ver; 5948 __le16 dir_ordinal; 5949 __le16 dir_idx; 5950 u8 unused_0[7]; 5951 u8 valid; 5952 }; 5953 5954 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 5955 struct hwrm_nvm_erase_dir_entry_input { 5956 __le16 req_type; 5957 __le16 cmpl_ring; 5958 __le16 seq_id; 5959 __le16 target_id; 5960 __le64 resp_addr; 5961 __le16 dir_idx; 5962 u8 unused_0[6]; 5963 }; 5964 5965 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 5966 struct hwrm_nvm_erase_dir_entry_output { 5967 __le16 error_code; 5968 __le16 req_type; 5969 __le16 seq_id; 5970 __le16 resp_len; 5971 u8 unused_0[7]; 5972 u8 valid; 5973 }; 5974 5975 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 5976 struct hwrm_nvm_get_dev_info_input { 5977 __le16 req_type; 5978 __le16 cmpl_ring; 5979 __le16 seq_id; 5980 __le16 target_id; 5981 __le64 resp_addr; 5982 }; 5983 5984 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 5985 struct hwrm_nvm_get_dev_info_output { 5986 __le16 error_code; 5987 __le16 req_type; 5988 __le16 seq_id; 5989 __le16 resp_len; 5990 __le16 manufacturer_id; 5991 __le16 device_id; 5992 __le32 sector_size; 5993 __le32 nvram_size; 5994 __le32 reserved_size; 5995 __le32 available_size; 5996 u8 unused_0[3]; 5997 u8 valid; 5998 }; 5999 6000 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 6001 struct hwrm_nvm_mod_dir_entry_input { 6002 __le16 req_type; 6003 __le16 cmpl_ring; 6004 __le16 seq_id; 6005 __le16 target_id; 6006 __le64 resp_addr; 6007 __le32 enables; 6008 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 6009 __le16 dir_idx; 6010 __le16 dir_ordinal; 6011 __le16 dir_ext; 6012 __le16 dir_attr; 6013 __le32 checksum; 6014 }; 6015 6016 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 6017 struct hwrm_nvm_mod_dir_entry_output { 6018 __le16 error_code; 6019 __le16 req_type; 6020 __le16 seq_id; 6021 __le16 resp_len; 6022 u8 unused_0[7]; 6023 u8 valid; 6024 }; 6025 6026 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 6027 struct hwrm_nvm_verify_update_input { 6028 __le16 req_type; 6029 __le16 cmpl_ring; 6030 __le16 seq_id; 6031 __le16 target_id; 6032 __le64 resp_addr; 6033 __le16 dir_type; 6034 __le16 dir_ordinal; 6035 __le16 dir_ext; 6036 u8 unused_0[2]; 6037 }; 6038 6039 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 6040 struct hwrm_nvm_verify_update_output { 6041 __le16 error_code; 6042 __le16 req_type; 6043 __le16 seq_id; 6044 __le16 resp_len; 6045 u8 unused_0[7]; 6046 u8 valid; 6047 }; 6048 6049 /* hwrm_nvm_install_update_input (size:192b/24B) */ 6050 struct hwrm_nvm_install_update_input { 6051 __le16 req_type; 6052 __le16 cmpl_ring; 6053 __le16 seq_id; 6054 __le16 target_id; 6055 __le64 resp_addr; 6056 __le32 install_type; 6057 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 6058 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 6059 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 6060 __le16 flags; 6061 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 6062 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 6063 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 6064 u8 unused_0[2]; 6065 }; 6066 6067 /* hwrm_nvm_install_update_output (size:192b/24B) */ 6068 struct hwrm_nvm_install_update_output { 6069 __le16 error_code; 6070 __le16 req_type; 6071 __le16 seq_id; 6072 __le16 resp_len; 6073 __le64 installed_items; 6074 u8 result; 6075 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 6076 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 6077 u8 problem_item; 6078 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 6079 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 6080 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 6081 u8 reset_required; 6082 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 6083 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 6084 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 6085 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 6086 u8 unused_0[4]; 6087 u8 valid; 6088 }; 6089 6090 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 6091 struct hwrm_nvm_install_update_cmd_err { 6092 u8 code; 6093 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 6094 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 6095 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 6096 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 6097 u8 unused_0[7]; 6098 }; 6099 6100 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 6101 struct hwrm_nvm_get_variable_input { 6102 __le16 req_type; 6103 __le16 cmpl_ring; 6104 __le16 seq_id; 6105 __le16 target_id; 6106 __le64 resp_addr; 6107 __le64 dest_data_addr; 6108 __le16 data_len; 6109 __le16 option_num; 6110 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6111 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6112 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 6113 __le16 dimensions; 6114 __le16 index_0; 6115 __le16 index_1; 6116 __le16 index_2; 6117 __le16 index_3; 6118 u8 flags; 6119 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 6120 u8 unused_0; 6121 }; 6122 6123 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 6124 struct hwrm_nvm_get_variable_output { 6125 __le16 error_code; 6126 __le16 req_type; 6127 __le16 seq_id; 6128 __le16 resp_len; 6129 __le16 data_len; 6130 __le16 option_num; 6131 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 6132 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 6133 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 6134 u8 unused_0[3]; 6135 u8 valid; 6136 }; 6137 6138 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 6139 struct hwrm_nvm_get_variable_cmd_err { 6140 u8 code; 6141 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6142 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6143 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6144 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 6145 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 6146 u8 unused_0[7]; 6147 }; 6148 6149 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 6150 struct hwrm_nvm_set_variable_input { 6151 __le16 req_type; 6152 __le16 cmpl_ring; 6153 __le16 seq_id; 6154 __le16 target_id; 6155 __le64 resp_addr; 6156 __le64 src_data_addr; 6157 __le16 data_len; 6158 __le16 option_num; 6159 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6160 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6161 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 6162 __le16 dimensions; 6163 __le16 index_0; 6164 __le16 index_1; 6165 __le16 index_2; 6166 __le16 index_3; 6167 u8 flags; 6168 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 6169 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 6170 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 6171 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 6172 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 6173 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 6174 u8 unused_0; 6175 }; 6176 6177 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 6178 struct hwrm_nvm_set_variable_output { 6179 __le16 error_code; 6180 __le16 req_type; 6181 __le16 seq_id; 6182 __le16 resp_len; 6183 u8 unused_0[7]; 6184 u8 valid; 6185 }; 6186 6187 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 6188 struct hwrm_nvm_set_variable_cmd_err { 6189 u8 code; 6190 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6191 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6192 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6193 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 6194 u8 unused_0[7]; 6195 }; 6196 6197 /* hwrm_selftest_qlist_input (size:128b/16B) */ 6198 struct hwrm_selftest_qlist_input { 6199 __le16 req_type; 6200 __le16 cmpl_ring; 6201 __le16 seq_id; 6202 __le16 target_id; 6203 __le64 resp_addr; 6204 }; 6205 6206 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 6207 struct hwrm_selftest_qlist_output { 6208 __le16 error_code; 6209 __le16 req_type; 6210 __le16 seq_id; 6211 __le16 resp_len; 6212 u8 num_tests; 6213 u8 available_tests; 6214 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 6215 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 6216 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 6217 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 6218 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 6219 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 6220 u8 offline_tests; 6221 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 6222 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 6223 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 6224 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 6225 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 6226 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 6227 u8 unused_0; 6228 __le16 test_timeout; 6229 u8 unused_1[2]; 6230 char test0_name[32]; 6231 char test1_name[32]; 6232 char test2_name[32]; 6233 char test3_name[32]; 6234 char test4_name[32]; 6235 char test5_name[32]; 6236 char test6_name[32]; 6237 char test7_name[32]; 6238 u8 unused_2[7]; 6239 u8 valid; 6240 }; 6241 6242 /* hwrm_selftest_exec_input (size:192b/24B) */ 6243 struct hwrm_selftest_exec_input { 6244 __le16 req_type; 6245 __le16 cmpl_ring; 6246 __le16 seq_id; 6247 __le16 target_id; 6248 __le64 resp_addr; 6249 u8 flags; 6250 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 6251 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 6252 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 6253 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 6254 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 6255 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 6256 u8 pcie_lane_num; 6257 u8 unused_0[6]; 6258 }; 6259 6260 /* hwrm_selftest_exec_output (size:128b/16B) */ 6261 struct hwrm_selftest_exec_output { 6262 __le16 error_code; 6263 __le16 req_type; 6264 __le16 seq_id; 6265 __le16 resp_len; 6266 u8 requested_tests; 6267 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 6268 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 6269 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 6270 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 6271 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 6272 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 6273 u8 test_success; 6274 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 6275 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 6276 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 6277 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 6278 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 6279 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 6280 u8 unused_0[5]; 6281 u8 valid; 6282 }; 6283 6284 /* hwrm_selftest_irq_input (size:128b/16B) */ 6285 struct hwrm_selftest_irq_input { 6286 __le16 req_type; 6287 __le16 cmpl_ring; 6288 __le16 seq_id; 6289 __le16 target_id; 6290 __le64 resp_addr; 6291 }; 6292 6293 /* hwrm_selftest_irq_output (size:128b/16B) */ 6294 struct hwrm_selftest_irq_output { 6295 __le16 error_code; 6296 __le16 req_type; 6297 __le16 seq_id; 6298 __le16 resp_len; 6299 u8 unused_0[7]; 6300 u8 valid; 6301 }; 6302 6303 #endif /* _BNXT_HSI_H_ */ 6304