1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #ifndef BNXT_HSI_H 11 #define BNXT_HSI_H 12 13 /* per-context HW statistics -- chip view */ 14 struct ctx_hw_stats { 15 __le64 rx_ucast_pkts; 16 __le64 rx_mcast_pkts; 17 __le64 rx_bcast_pkts; 18 __le64 rx_discard_pkts; 19 __le64 rx_drop_pkts; 20 __le64 rx_ucast_bytes; 21 __le64 rx_mcast_bytes; 22 __le64 rx_bcast_bytes; 23 __le64 tx_ucast_pkts; 24 __le64 tx_mcast_pkts; 25 __le64 tx_bcast_pkts; 26 __le64 tx_discard_pkts; 27 __le64 tx_drop_pkts; 28 __le64 tx_ucast_bytes; 29 __le64 tx_mcast_bytes; 30 __le64 tx_bcast_bytes; 31 __le64 tpa_pkts; 32 __le64 tpa_bytes; 33 __le64 tpa_events; 34 __le64 tpa_aborts; 35 }; 36 37 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 38 struct eject_cmpl { 39 __le16 type; 40 #define EJECT_CMPL_TYPE_MASK 0x3fUL 41 #define EJECT_CMPL_TYPE_SFT 0 42 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 43 __le16 len; 44 __le32 opaque; 45 __le32 v; 46 #define EJECT_CMPL_V 0x1UL 47 __le32 unused_2; 48 }; 49 50 /* HWRM Completion Record (16 bytes) */ 51 struct hwrm_cmpl { 52 __le16 type; 53 #define HWRM_CMPL_TYPE_MASK 0x3fUL 54 #define HWRM_CMPL_TYPE_SFT 0 55 #define HWRM_CMPL_TYPE_HWRM_DONE 0x20UL 56 __le16 sequence_id; 57 __le32 unused_1; 58 __le32 v; 59 #define HWRM_CMPL_V 0x1UL 60 __le32 unused_3; 61 }; 62 63 /* HWRM Forwarded Request (16 bytes) */ 64 struct hwrm_fwd_req_cmpl { 65 __le16 req_len_type; 66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL 67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 71 __le16 source_id; 72 __le32 unused_0; 73 __le32 req_buf_addr_v[2]; 74 #define HWRM_FWD_REQ_CMPL_V 0x1UL 75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 77 }; 78 79 /* HWRM Forwarded Response (16 bytes) */ 80 struct hwrm_fwd_resp_cmpl { 81 __le16 type; 82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL 83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 85 __le16 source_id; 86 __le16 resp_len; 87 __le16 unused_1; 88 __le32 resp_buf_addr_v[2]; 89 #define HWRM_FWD_RESP_CMPL_V 0x1UL 90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 92 }; 93 94 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 95 struct hwrm_async_event_cmpl { 96 __le16 type; 97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 100 __le16 event_id; 101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 113 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 114 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 115 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 116 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 117 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 118 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 119 __le32 event_data2; 120 u8 opaque_v; 121 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL 122 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 123 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 124 u8 timestamp_lo; 125 __le16 timestamp_hi; 126 __le32 event_data1; 127 }; 128 129 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 130 struct hwrm_async_event_cmpl_link_status_change { 131 __le16 type; 132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 133 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 134 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 135 __le16 event_id; 136 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 137 __le32 event_data2; 138 u8 opaque_v; 139 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 140 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 141 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 142 u8 timestamp_lo; 143 __le16 timestamp_hi; 144 __le32 event_data1; 145 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 146 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 147 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 148 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 149 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 150 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 151 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 152 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 153 }; 154 155 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 156 struct hwrm_async_event_cmpl_link_mtu_change { 157 __le16 type; 158 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 159 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 160 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 161 __le16 event_id; 162 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 163 __le32 event_data2; 164 u8 opaque_v; 165 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 166 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 167 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 168 u8 timestamp_lo; 169 __le16 timestamp_hi; 170 __le32 event_data1; 171 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 172 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 173 }; 174 175 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 176 struct hwrm_async_event_cmpl_link_speed_change { 177 __le16 type; 178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 179 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 181 __le16 event_id; 182 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 183 __le32 event_data2; 184 u8 opaque_v; 185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 186 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 187 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 188 u8 timestamp_lo; 189 __le16 timestamp_hi; 190 __le32 event_data1; 191 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 192 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 193 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 194 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 195 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 196 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 197 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 198 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 199 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 200 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 201 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 202 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 203 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 204 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 205 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 206 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 207 }; 208 209 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 210 struct hwrm_async_event_cmpl_dcb_config_change { 211 __le16 type; 212 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 213 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 214 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 215 __le16 event_id; 216 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 217 __le32 event_data2; 218 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 219 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 220 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 221 u8 opaque_v; 222 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 223 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 224 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 225 u8 timestamp_lo; 226 __le16 timestamp_hi; 227 __le32 event_data1; 228 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 229 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 230 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 231 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 232 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 233 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 234 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 235 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 236 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 237 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 238 }; 239 240 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 241 struct hwrm_async_event_cmpl_port_conn_not_allowed { 242 __le16 type; 243 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 244 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 245 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 246 __le16 event_id; 247 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 248 __le32 event_data2; 249 u8 opaque_v; 250 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 251 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 252 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 253 u8 timestamp_lo; 254 __le16 timestamp_hi; 255 __le32 event_data1; 256 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 257 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 258 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 259 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 260 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 261 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 262 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 263 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 264 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 265 }; 266 267 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 268 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 269 __le16 type; 270 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 271 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 272 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 273 __le16 event_id; 274 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 275 __le32 event_data2; 276 u8 opaque_v; 277 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 278 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 279 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 280 u8 timestamp_lo; 281 __le16 timestamp_hi; 282 __le32 event_data1; 283 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 284 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 285 }; 286 287 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 288 struct hwrm_async_event_cmpl_link_speed_cfg_change { 289 __le16 type; 290 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 291 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 292 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 293 __le16 event_id; 294 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 295 __le32 event_data2; 296 u8 opaque_v; 297 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 298 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 299 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 300 u8 timestamp_lo; 301 __le16 timestamp_hi; 302 __le32 event_data1; 303 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 304 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 305 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 306 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 307 }; 308 309 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 310 struct hwrm_async_event_cmpl_func_drvr_unload { 311 __le16 type; 312 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 313 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 314 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 315 __le16 event_id; 316 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 317 __le32 event_data2; 318 u8 opaque_v; 319 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 320 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 321 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 322 u8 timestamp_lo; 323 __le16 timestamp_hi; 324 __le32 event_data1; 325 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 326 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 327 }; 328 329 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 330 struct hwrm_async_event_cmpl_func_drvr_load { 331 __le16 type; 332 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 333 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 334 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 335 __le16 event_id; 336 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 337 __le32 event_data2; 338 u8 opaque_v; 339 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 340 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 341 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 342 u8 timestamp_lo; 343 __le16 timestamp_hi; 344 __le32 event_data1; 345 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 346 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 347 }; 348 349 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 350 struct hwrm_async_event_cmpl_pf_drvr_unload { 351 __le16 type; 352 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 353 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 354 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 355 __le16 event_id; 356 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 357 __le32 event_data2; 358 u8 opaque_v; 359 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 360 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 361 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 362 u8 timestamp_lo; 363 __le16 timestamp_hi; 364 __le32 event_data1; 365 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 366 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 367 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 368 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 369 }; 370 371 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 372 struct hwrm_async_event_cmpl_pf_drvr_load { 373 __le16 type; 374 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 375 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 376 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 377 __le16 event_id; 378 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 379 __le32 event_data2; 380 u8 opaque_v; 381 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 382 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 383 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 384 u8 timestamp_lo; 385 __le16 timestamp_hi; 386 __le32 event_data1; 387 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 388 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 389 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 390 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 391 }; 392 393 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 394 struct hwrm_async_event_cmpl_vf_flr { 395 __le16 type; 396 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 397 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 398 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 399 __le16 event_id; 400 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 401 __le32 event_data2; 402 u8 opaque_v; 403 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 404 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 405 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 406 u8 timestamp_lo; 407 __le16 timestamp_hi; 408 __le32 event_data1; 409 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 410 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 411 }; 412 413 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 414 struct hwrm_async_event_cmpl_vf_mac_addr_change { 415 __le16 type; 416 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 417 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 418 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 419 __le16 event_id; 420 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 421 __le32 event_data2; 422 u8 opaque_v; 423 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 424 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 425 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 426 u8 timestamp_lo; 427 __le16 timestamp_hi; 428 __le32 event_data1; 429 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 430 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 431 }; 432 433 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 434 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 435 __le16 type; 436 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 437 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 438 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 439 __le16 event_id; 440 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 441 __le32 event_data2; 442 u8 opaque_v; 443 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 444 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 445 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 446 u8 timestamp_lo; 447 __le16 timestamp_hi; 448 __le32 event_data1; 449 #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 450 }; 451 452 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 453 struct hwrm_async_event_cmpl_vf_cfg_change { 454 __le16 type; 455 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 456 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 457 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 458 __le16 event_id; 459 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 460 __le32 event_data2; 461 u8 opaque_v; 462 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 463 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 464 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 465 u8 timestamp_lo; 466 __le16 timestamp_hi; 467 __le32 event_data1; 468 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 469 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 470 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 471 #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 472 }; 473 474 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 475 struct hwrm_async_event_cmpl_hwrm_error { 476 __le16 type; 477 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 478 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 479 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 480 __le16 event_id; 481 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 482 __le32 event_data2; 483 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 484 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 485 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 486 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 487 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 488 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 489 u8 opaque_v; 490 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 491 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 492 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 493 u8 timestamp_lo; 494 __le16 timestamp_hi; 495 __le32 event_data1; 496 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 497 }; 498 499 /* HW Resource Manager Specification 1.5.4 */ 500 #define HWRM_VERSION_MAJOR 1 501 #define HWRM_VERSION_MINOR 5 502 #define HWRM_VERSION_UPDATE 4 503 504 #define HWRM_VERSION_STR "1.5.4" 505 /* 506 * Following is the signature for HWRM message field that indicates not 507 * applicable (All F's). Need to cast it the size of the field if needed. 508 */ 509 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 510 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 511 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 512 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 513 #define HW_HASH_KEY_SIZE 40 514 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 515 /* Input (16 bytes) */ 516 struct input { 517 __le16 req_type; 518 __le16 cmpl_ring; 519 __le16 seq_id; 520 __le16 target_id; 521 __le64 resp_addr; 522 }; 523 524 /* Output (8 bytes) */ 525 struct output { 526 __le16 error_code; 527 __le16 req_type; 528 __le16 seq_id; 529 __le16 resp_len; 530 }; 531 532 /* Command numbering (8 bytes) */ 533 struct cmd_nums { 534 __le16 req_type; 535 #define HWRM_VER_GET (0x0UL) 536 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 537 #define HWRM_FUNC_VF_CFG (0xfUL) 538 #define RESERVED1 (0x10UL) 539 #define HWRM_FUNC_RESET (0x11UL) 540 #define HWRM_FUNC_GETFID (0x12UL) 541 #define HWRM_FUNC_VF_ALLOC (0x13UL) 542 #define HWRM_FUNC_VF_FREE (0x14UL) 543 #define HWRM_FUNC_QCAPS (0x15UL) 544 #define HWRM_FUNC_QCFG (0x16UL) 545 #define HWRM_FUNC_CFG (0x17UL) 546 #define HWRM_FUNC_QSTATS (0x18UL) 547 #define HWRM_FUNC_CLR_STATS (0x19UL) 548 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 549 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 550 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 551 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 552 #define HWRM_FUNC_DRV_QVER (0x1eUL) 553 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 554 #define HWRM_PORT_PHY_CFG (0x20UL) 555 #define HWRM_PORT_MAC_CFG (0x21UL) 556 #define HWRM_PORT_TS_QUERY (0x22UL) 557 #define HWRM_PORT_QSTATS (0x23UL) 558 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 559 #define HWRM_PORT_CLR_STATS (0x25UL) 560 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 561 #define HWRM_PORT_PHY_QCFG (0x27UL) 562 #define HWRM_PORT_MAC_QCFG (0x28UL) 563 #define HWRM_PORT_BLINK_LED (0x29UL) 564 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 565 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 566 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 567 #define HWRM_QUEUE_QPORTCFG (0x30UL) 568 #define HWRM_QUEUE_QCFG (0x31UL) 569 #define HWRM_QUEUE_CFG (0x32UL) 570 #define RESERVED2 (0x33UL) 571 #define RESERVED3 (0x34UL) 572 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 573 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 574 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 575 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 576 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 577 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 578 #define HWRM_VNIC_ALLOC (0x40UL) 579 #define HWRM_VNIC_FREE (0x41UL) 580 #define HWRM_VNIC_CFG (0x42UL) 581 #define HWRM_VNIC_QCFG (0x43UL) 582 #define HWRM_VNIC_TPA_CFG (0x44UL) 583 #define HWRM_VNIC_TPA_QCFG (0x45UL) 584 #define HWRM_VNIC_RSS_CFG (0x46UL) 585 #define HWRM_VNIC_RSS_QCFG (0x47UL) 586 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 587 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 588 #define HWRM_VNIC_QCAPS (0x4aUL) 589 #define HWRM_RING_ALLOC (0x50UL) 590 #define HWRM_RING_FREE (0x51UL) 591 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 592 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 593 #define HWRM_RING_RESET (0x5eUL) 594 #define HWRM_RING_GRP_ALLOC (0x60UL) 595 #define HWRM_RING_GRP_FREE (0x61UL) 596 #define RESERVED5 (0x64UL) 597 #define RESERVED6 (0x65UL) 598 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 599 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 600 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 601 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 602 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 603 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 604 #define RESERVED4 (0x94UL) 605 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 606 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 607 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 608 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 609 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 610 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 611 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 612 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 613 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 614 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 615 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 616 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 617 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 618 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 619 #define HWRM_STAT_CTX_FREE (0xb1UL) 620 #define HWRM_STAT_CTX_QUERY (0xb2UL) 621 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 622 #define HWRM_FW_RESET (0xc0UL) 623 #define HWRM_FW_QSTATUS (0xc1UL) 624 #define HWRM_FW_SET_TIME (0xc8UL) 625 #define HWRM_FW_GET_TIME (0xc9UL) 626 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 627 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 628 #define HWRM_FW_IPC_MAILBOX (0xccUL) 629 #define HWRM_EXEC_FWD_RESP (0xd0UL) 630 #define HWRM_REJECT_FWD_RESP (0xd1UL) 631 #define HWRM_FWD_RESP (0xd2UL) 632 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 633 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 634 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 635 #define HWRM_WOL_FILTER_FREE (0xf1UL) 636 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 637 #define HWRM_WOL_REASON_QCFG (0xf3UL) 638 #define HWRM_DBG_READ_DIRECT (0xff10UL) 639 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 640 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 641 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 642 #define HWRM_DBG_DUMP (0xff14UL) 643 #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 644 #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 645 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 646 #define HWRM_NVM_MODIFY (0xfff4UL) 647 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 648 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 649 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 650 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 651 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 652 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 653 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 654 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 655 #define HWRM_NVM_READ (0xfffdUL) 656 #define HWRM_NVM_WRITE (0xfffeUL) 657 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 658 __le16 unused_0[3]; 659 }; 660 661 /* Return Codes (8 bytes) */ 662 struct ret_codes { 663 __le16 error_code; 664 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 665 #define HWRM_ERR_CODE_FAIL (0x1UL) 666 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 667 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 668 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 669 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 670 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 671 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 672 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 673 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 674 __le16 unused_0[3]; 675 }; 676 677 /* Output (16 bytes) */ 678 struct hwrm_err_output { 679 __le16 error_code; 680 __le16 req_type; 681 __le16 seq_id; 682 __le16 resp_len; 683 __le32 opaque_0; 684 __le16 opaque_1; 685 u8 cmd_err; 686 u8 valid; 687 }; 688 689 /* Port Tx Statistics Formats (408 bytes) */ 690 struct tx_port_stats { 691 __le64 tx_64b_frames; 692 __le64 tx_65b_127b_frames; 693 __le64 tx_128b_255b_frames; 694 __le64 tx_256b_511b_frames; 695 __le64 tx_512b_1023b_frames; 696 __le64 tx_1024b_1518_frames; 697 __le64 tx_good_vlan_frames; 698 __le64 tx_1519b_2047_frames; 699 __le64 tx_2048b_4095b_frames; 700 __le64 tx_4096b_9216b_frames; 701 __le64 tx_9217b_16383b_frames; 702 __le64 tx_good_frames; 703 __le64 tx_total_frames; 704 __le64 tx_ucast_frames; 705 __le64 tx_mcast_frames; 706 __le64 tx_bcast_frames; 707 __le64 tx_pause_frames; 708 __le64 tx_pfc_frames; 709 __le64 tx_jabber_frames; 710 __le64 tx_fcs_err_frames; 711 __le64 tx_control_frames; 712 __le64 tx_oversz_frames; 713 __le64 tx_single_dfrl_frames; 714 __le64 tx_multi_dfrl_frames; 715 __le64 tx_single_coll_frames; 716 __le64 tx_multi_coll_frames; 717 __le64 tx_late_coll_frames; 718 __le64 tx_excessive_coll_frames; 719 __le64 tx_frag_frames; 720 __le64 tx_err; 721 __le64 tx_tagged_frames; 722 __le64 tx_dbl_tagged_frames; 723 __le64 tx_runt_frames; 724 __le64 tx_fifo_underruns; 725 __le64 tx_pfc_ena_frames_pri0; 726 __le64 tx_pfc_ena_frames_pri1; 727 __le64 tx_pfc_ena_frames_pri2; 728 __le64 tx_pfc_ena_frames_pri3; 729 __le64 tx_pfc_ena_frames_pri4; 730 __le64 tx_pfc_ena_frames_pri5; 731 __le64 tx_pfc_ena_frames_pri6; 732 __le64 tx_pfc_ena_frames_pri7; 733 __le64 tx_eee_lpi_events; 734 __le64 tx_eee_lpi_duration; 735 __le64 tx_llfc_logical_msgs; 736 __le64 tx_hcfc_msgs; 737 __le64 tx_total_collisions; 738 __le64 tx_bytes; 739 __le64 tx_xthol_frames; 740 __le64 tx_stat_discard; 741 __le64 tx_stat_error; 742 }; 743 744 /* Port Rx Statistics Formats (528 bytes) */ 745 struct rx_port_stats { 746 __le64 rx_64b_frames; 747 __le64 rx_65b_127b_frames; 748 __le64 rx_128b_255b_frames; 749 __le64 rx_256b_511b_frames; 750 __le64 rx_512b_1023b_frames; 751 __le64 rx_1024b_1518_frames; 752 __le64 rx_good_vlan_frames; 753 __le64 rx_1519b_2047b_frames; 754 __le64 rx_2048b_4095b_frames; 755 __le64 rx_4096b_9216b_frames; 756 __le64 rx_9217b_16383b_frames; 757 __le64 rx_total_frames; 758 __le64 rx_ucast_frames; 759 __le64 rx_mcast_frames; 760 __le64 rx_bcast_frames; 761 __le64 rx_fcs_err_frames; 762 __le64 rx_ctrl_frames; 763 __le64 rx_pause_frames; 764 __le64 rx_pfc_frames; 765 __le64 rx_unsupported_opcode_frames; 766 __le64 rx_unsupported_da_pausepfc_frames; 767 __le64 rx_wrong_sa_frames; 768 __le64 rx_align_err_frames; 769 __le64 rx_oor_len_frames; 770 __le64 rx_code_err_frames; 771 __le64 rx_false_carrier_frames; 772 __le64 rx_ovrsz_frames; 773 __le64 rx_jbr_frames; 774 __le64 rx_mtu_err_frames; 775 __le64 rx_match_crc_frames; 776 __le64 rx_promiscuous_frames; 777 __le64 rx_tagged_frames; 778 __le64 rx_double_tagged_frames; 779 __le64 rx_trunc_frames; 780 __le64 rx_good_frames; 781 __le64 rx_pfc_xon2xoff_frames_pri0; 782 __le64 rx_pfc_xon2xoff_frames_pri1; 783 __le64 rx_pfc_xon2xoff_frames_pri2; 784 __le64 rx_pfc_xon2xoff_frames_pri3; 785 __le64 rx_pfc_xon2xoff_frames_pri4; 786 __le64 rx_pfc_xon2xoff_frames_pri5; 787 __le64 rx_pfc_xon2xoff_frames_pri6; 788 __le64 rx_pfc_xon2xoff_frames_pri7; 789 __le64 rx_pfc_ena_frames_pri0; 790 __le64 rx_pfc_ena_frames_pri1; 791 __le64 rx_pfc_ena_frames_pri2; 792 __le64 rx_pfc_ena_frames_pri3; 793 __le64 rx_pfc_ena_frames_pri4; 794 __le64 rx_pfc_ena_frames_pri5; 795 __le64 rx_pfc_ena_frames_pri6; 796 __le64 rx_pfc_ena_frames_pri7; 797 __le64 rx_sch_crc_err_frames; 798 __le64 rx_undrsz_frames; 799 __le64 rx_frag_frames; 800 __le64 rx_eee_lpi_events; 801 __le64 rx_eee_lpi_duration; 802 __le64 rx_llfc_physical_msgs; 803 __le64 rx_llfc_logical_msgs; 804 __le64 rx_llfc_msgs_with_crc_err; 805 __le64 rx_hcfc_msgs; 806 __le64 rx_hcfc_msgs_with_crc_err; 807 __le64 rx_bytes; 808 __le64 rx_runt_bytes; 809 __le64 rx_runt_frames; 810 __le64 rx_stat_discard; 811 __le64 rx_stat_err; 812 }; 813 814 /* hwrm_ver_get */ 815 /* Input (24 bytes) */ 816 struct hwrm_ver_get_input { 817 __le16 req_type; 818 __le16 cmpl_ring; 819 __le16 seq_id; 820 __le16 target_id; 821 __le64 resp_addr; 822 u8 hwrm_intf_maj; 823 u8 hwrm_intf_min; 824 u8 hwrm_intf_upd; 825 u8 unused_0[5]; 826 }; 827 828 /* Output (128 bytes) */ 829 struct hwrm_ver_get_output { 830 __le16 error_code; 831 __le16 req_type; 832 __le16 seq_id; 833 __le16 resp_len; 834 u8 hwrm_intf_maj; 835 u8 hwrm_intf_min; 836 u8 hwrm_intf_upd; 837 u8 hwrm_intf_rsvd; 838 u8 hwrm_fw_maj; 839 u8 hwrm_fw_min; 840 u8 hwrm_fw_bld; 841 u8 hwrm_fw_rsvd; 842 u8 mgmt_fw_maj; 843 u8 mgmt_fw_min; 844 u8 mgmt_fw_bld; 845 u8 mgmt_fw_rsvd; 846 u8 netctrl_fw_maj; 847 u8 netctrl_fw_min; 848 u8 netctrl_fw_bld; 849 u8 netctrl_fw_rsvd; 850 __le32 dev_caps_cfg; 851 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 852 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 853 u8 roce_fw_maj; 854 u8 roce_fw_min; 855 u8 roce_fw_bld; 856 u8 roce_fw_rsvd; 857 char hwrm_fw_name[16]; 858 char mgmt_fw_name[16]; 859 char netctrl_fw_name[16]; 860 __le32 reserved2[4]; 861 char roce_fw_name[16]; 862 __le16 chip_num; 863 u8 chip_rev; 864 u8 chip_metal; 865 u8 chip_bond_id; 866 u8 chip_platform_type; 867 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 868 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 869 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 870 __le16 max_req_win_len; 871 __le16 max_resp_len; 872 __le16 def_req_timeout; 873 u8 unused_0; 874 u8 unused_1; 875 u8 unused_2; 876 u8 valid; 877 }; 878 879 /* hwrm_func_reset */ 880 /* Input (24 bytes) */ 881 struct hwrm_func_reset_input { 882 __le16 req_type; 883 __le16 cmpl_ring; 884 __le16 seq_id; 885 __le16 target_id; 886 __le64 resp_addr; 887 __le32 enables; 888 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 889 __le16 vf_id; 890 u8 func_reset_level; 891 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 892 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 893 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 894 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 895 u8 unused_0; 896 }; 897 898 /* Output (16 bytes) */ 899 struct hwrm_func_reset_output { 900 __le16 error_code; 901 __le16 req_type; 902 __le16 seq_id; 903 __le16 resp_len; 904 __le32 unused_0; 905 u8 unused_1; 906 u8 unused_2; 907 u8 unused_3; 908 u8 valid; 909 }; 910 911 /* hwrm_func_getfid */ 912 /* Input (24 bytes) */ 913 struct hwrm_func_getfid_input { 914 __le16 req_type; 915 __le16 cmpl_ring; 916 __le16 seq_id; 917 __le16 target_id; 918 __le64 resp_addr; 919 __le32 enables; 920 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 921 __le16 pci_id; 922 __le16 unused_0; 923 }; 924 925 /* Output (16 bytes) */ 926 struct hwrm_func_getfid_output { 927 __le16 error_code; 928 __le16 req_type; 929 __le16 seq_id; 930 __le16 resp_len; 931 __le16 fid; 932 u8 unused_0; 933 u8 unused_1; 934 u8 unused_2; 935 u8 unused_3; 936 u8 unused_4; 937 u8 valid; 938 }; 939 940 /* hwrm_func_vf_alloc */ 941 /* Input (24 bytes) */ 942 struct hwrm_func_vf_alloc_input { 943 __le16 req_type; 944 __le16 cmpl_ring; 945 __le16 seq_id; 946 __le16 target_id; 947 __le64 resp_addr; 948 __le32 enables; 949 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 950 __le16 first_vf_id; 951 __le16 num_vfs; 952 }; 953 954 /* Output (16 bytes) */ 955 struct hwrm_func_vf_alloc_output { 956 __le16 error_code; 957 __le16 req_type; 958 __le16 seq_id; 959 __le16 resp_len; 960 __le16 first_vf_id; 961 u8 unused_0; 962 u8 unused_1; 963 u8 unused_2; 964 u8 unused_3; 965 u8 unused_4; 966 u8 valid; 967 }; 968 969 /* hwrm_func_vf_free */ 970 /* Input (24 bytes) */ 971 struct hwrm_func_vf_free_input { 972 __le16 req_type; 973 __le16 cmpl_ring; 974 __le16 seq_id; 975 __le16 target_id; 976 __le64 resp_addr; 977 __le32 enables; 978 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 979 __le16 first_vf_id; 980 __le16 num_vfs; 981 }; 982 983 /* Output (16 bytes) */ 984 struct hwrm_func_vf_free_output { 985 __le16 error_code; 986 __le16 req_type; 987 __le16 seq_id; 988 __le16 resp_len; 989 __le32 unused_0; 990 u8 unused_1; 991 u8 unused_2; 992 u8 unused_3; 993 u8 valid; 994 }; 995 996 /* hwrm_func_vf_cfg */ 997 /* Input (32 bytes) */ 998 struct hwrm_func_vf_cfg_input { 999 __le16 req_type; 1000 __le16 cmpl_ring; 1001 __le16 seq_id; 1002 __le16 target_id; 1003 __le64 resp_addr; 1004 __le32 enables; 1005 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1006 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1007 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1008 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1009 __le16 mtu; 1010 __le16 guest_vlan; 1011 __le16 async_event_cr; 1012 u8 dflt_mac_addr[6]; 1013 }; 1014 1015 /* Output (16 bytes) */ 1016 struct hwrm_func_vf_cfg_output { 1017 __le16 error_code; 1018 __le16 req_type; 1019 __le16 seq_id; 1020 __le16 resp_len; 1021 __le32 unused_0; 1022 u8 unused_1; 1023 u8 unused_2; 1024 u8 unused_3; 1025 u8 valid; 1026 }; 1027 1028 /* hwrm_func_qcaps */ 1029 /* Input (24 bytes) */ 1030 struct hwrm_func_qcaps_input { 1031 __le16 req_type; 1032 __le16 cmpl_ring; 1033 __le16 seq_id; 1034 __le16 target_id; 1035 __le64 resp_addr; 1036 __le16 fid; 1037 __le16 unused_0[3]; 1038 }; 1039 1040 /* Output (80 bytes) */ 1041 struct hwrm_func_qcaps_output { 1042 __le16 error_code; 1043 __le16 req_type; 1044 __le16 seq_id; 1045 __le16 resp_len; 1046 __le16 fid; 1047 __le16 port_id; 1048 __le32 flags; 1049 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1050 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1051 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1052 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1053 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1054 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1055 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1056 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1057 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1058 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1059 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1060 u8 mac_address[6]; 1061 __le16 max_rsscos_ctx; 1062 __le16 max_cmpl_rings; 1063 __le16 max_tx_rings; 1064 __le16 max_rx_rings; 1065 __le16 max_l2_ctxs; 1066 __le16 max_vnics; 1067 __le16 first_vf_id; 1068 __le16 max_vfs; 1069 __le16 max_stat_ctx; 1070 __le32 max_encap_records; 1071 __le32 max_decap_records; 1072 __le32 max_tx_em_flows; 1073 __le32 max_tx_wm_flows; 1074 __le32 max_rx_em_flows; 1075 __le32 max_rx_wm_flows; 1076 __le32 max_mcast_filters; 1077 __le32 max_flow_id; 1078 __le32 max_hw_ring_grps; 1079 __le16 max_sp_tx_rings; 1080 u8 unused_0; 1081 u8 valid; 1082 }; 1083 1084 /* hwrm_func_qcfg */ 1085 /* Input (24 bytes) */ 1086 struct hwrm_func_qcfg_input { 1087 __le16 req_type; 1088 __le16 cmpl_ring; 1089 __le16 seq_id; 1090 __le16 target_id; 1091 __le64 resp_addr; 1092 __le16 fid; 1093 __le16 unused_0[3]; 1094 }; 1095 1096 /* Output (72 bytes) */ 1097 struct hwrm_func_qcfg_output { 1098 __le16 error_code; 1099 __le16 req_type; 1100 __le16 seq_id; 1101 __le16 resp_len; 1102 __le16 fid; 1103 __le16 port_id; 1104 __le16 vlan; 1105 __le16 flags; 1106 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1107 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1108 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1109 u8 mac_address[6]; 1110 __le16 pci_id; 1111 __le16 alloc_rsscos_ctx; 1112 __le16 alloc_cmpl_rings; 1113 __le16 alloc_tx_rings; 1114 __le16 alloc_rx_rings; 1115 __le16 alloc_l2_ctx; 1116 __le16 alloc_vnics; 1117 __le16 mtu; 1118 __le16 mru; 1119 __le16 stat_ctx_id; 1120 u8 port_partition_type; 1121 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1122 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1123 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1124 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1125 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1126 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1127 u8 unused_0; 1128 __le16 dflt_vnic_id; 1129 u8 unused_1; 1130 u8 unused_2; 1131 __le32 min_bw; 1132 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1133 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1134 #define FUNC_QCFG_RESP_MIN_BW_RSVD 0x10000000UL 1135 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1136 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1137 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1138 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1139 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1140 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1141 __le32 max_bw; 1142 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1143 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1144 #define FUNC_QCFG_RESP_MAX_BW_RSVD 0x10000000UL 1145 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1146 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1147 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1148 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1149 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1150 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1151 u8 evb_mode; 1152 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1153 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1154 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1155 u8 unused_3; 1156 __le16 alloc_vfs; 1157 __le32 alloc_mcast_filters; 1158 __le32 alloc_hw_ring_grps; 1159 __le16 alloc_sp_tx_rings; 1160 u8 unused_4; 1161 u8 valid; 1162 }; 1163 1164 /* hwrm_func_cfg */ 1165 /* Input (88 bytes) */ 1166 struct hwrm_func_cfg_input { 1167 __le16 req_type; 1168 __le16 cmpl_ring; 1169 __le16 seq_id; 1170 __le16 target_id; 1171 __le64 resp_addr; 1172 __le16 fid; 1173 u8 unused_0; 1174 u8 unused_1; 1175 __le32 flags; 1176 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 1177 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 1178 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 1179 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 1180 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 1181 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 1182 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 1183 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 1184 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 1185 __le32 enables; 1186 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1187 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1188 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1189 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1190 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1191 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1192 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1193 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1194 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1195 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1196 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1197 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1198 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1199 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1200 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1201 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1202 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1203 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1204 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1205 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1206 __le16 mtu; 1207 __le16 mru; 1208 __le16 num_rsscos_ctxs; 1209 __le16 num_cmpl_rings; 1210 __le16 num_tx_rings; 1211 __le16 num_rx_rings; 1212 __le16 num_l2_ctxs; 1213 __le16 num_vnics; 1214 __le16 num_stat_ctxs; 1215 __le16 num_hw_ring_grps; 1216 u8 dflt_mac_addr[6]; 1217 __le16 dflt_vlan; 1218 __be32 dflt_ip_addr[4]; 1219 __le32 min_bw; 1220 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1221 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1222 #define FUNC_CFG_REQ_MIN_BW_RSVD 0x10000000UL 1223 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1224 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1225 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1226 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1227 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1228 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1229 __le32 max_bw; 1230 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1231 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1232 #define FUNC_CFG_REQ_MAX_BW_RSVD 0x10000000UL 1233 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1234 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1235 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 1236 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1237 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1238 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1239 __le16 async_event_cr; 1240 u8 vlan_antispoof_mode; 1241 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1242 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1243 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1244 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1245 u8 allowed_vlan_pris; 1246 u8 evb_mode; 1247 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1248 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1249 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1250 u8 unused_2; 1251 __le16 num_mcast_filters; 1252 }; 1253 1254 /* Output (16 bytes) */ 1255 struct hwrm_func_cfg_output { 1256 __le16 error_code; 1257 __le16 req_type; 1258 __le16 seq_id; 1259 __le16 resp_len; 1260 __le32 unused_0; 1261 u8 unused_1; 1262 u8 unused_2; 1263 u8 unused_3; 1264 u8 valid; 1265 }; 1266 1267 /* hwrm_func_qstats */ 1268 /* Input (24 bytes) */ 1269 struct hwrm_func_qstats_input { 1270 __le16 req_type; 1271 __le16 cmpl_ring; 1272 __le16 seq_id; 1273 __le16 target_id; 1274 __le64 resp_addr; 1275 __le16 fid; 1276 __le16 unused_0[3]; 1277 }; 1278 1279 /* Output (176 bytes) */ 1280 struct hwrm_func_qstats_output { 1281 __le16 error_code; 1282 __le16 req_type; 1283 __le16 seq_id; 1284 __le16 resp_len; 1285 __le64 tx_ucast_pkts; 1286 __le64 tx_mcast_pkts; 1287 __le64 tx_bcast_pkts; 1288 __le64 tx_err_pkts; 1289 __le64 tx_drop_pkts; 1290 __le64 tx_ucast_bytes; 1291 __le64 tx_mcast_bytes; 1292 __le64 tx_bcast_bytes; 1293 __le64 rx_ucast_pkts; 1294 __le64 rx_mcast_pkts; 1295 __le64 rx_bcast_pkts; 1296 __le64 rx_err_pkts; 1297 __le64 rx_drop_pkts; 1298 __le64 rx_ucast_bytes; 1299 __le64 rx_mcast_bytes; 1300 __le64 rx_bcast_bytes; 1301 __le64 rx_agg_pkts; 1302 __le64 rx_agg_bytes; 1303 __le64 rx_agg_events; 1304 __le64 rx_agg_aborts; 1305 __le32 unused_0; 1306 u8 unused_1; 1307 u8 unused_2; 1308 u8 unused_3; 1309 u8 valid; 1310 }; 1311 1312 /* hwrm_func_clr_stats */ 1313 /* Input (24 bytes) */ 1314 struct hwrm_func_clr_stats_input { 1315 __le16 req_type; 1316 __le16 cmpl_ring; 1317 __le16 seq_id; 1318 __le16 target_id; 1319 __le64 resp_addr; 1320 __le16 fid; 1321 __le16 unused_0[3]; 1322 }; 1323 1324 /* Output (16 bytes) */ 1325 struct hwrm_func_clr_stats_output { 1326 __le16 error_code; 1327 __le16 req_type; 1328 __le16 seq_id; 1329 __le16 resp_len; 1330 __le32 unused_0; 1331 u8 unused_1; 1332 u8 unused_2; 1333 u8 unused_3; 1334 u8 valid; 1335 }; 1336 1337 /* hwrm_func_vf_resc_free */ 1338 /* Input (24 bytes) */ 1339 struct hwrm_func_vf_resc_free_input { 1340 __le16 req_type; 1341 __le16 cmpl_ring; 1342 __le16 seq_id; 1343 __le16 target_id; 1344 __le64 resp_addr; 1345 __le16 vf_id; 1346 __le16 unused_0[3]; 1347 }; 1348 1349 /* Output (16 bytes) */ 1350 struct hwrm_func_vf_resc_free_output { 1351 __le16 error_code; 1352 __le16 req_type; 1353 __le16 seq_id; 1354 __le16 resp_len; 1355 __le32 unused_0; 1356 u8 unused_1; 1357 u8 unused_2; 1358 u8 unused_3; 1359 u8 valid; 1360 }; 1361 1362 /* hwrm_func_vf_vnic_ids_query */ 1363 /* Input (32 bytes) */ 1364 struct hwrm_func_vf_vnic_ids_query_input { 1365 __le16 req_type; 1366 __le16 cmpl_ring; 1367 __le16 seq_id; 1368 __le16 target_id; 1369 __le64 resp_addr; 1370 __le16 vf_id; 1371 u8 unused_0; 1372 u8 unused_1; 1373 __le32 max_vnic_id_cnt; 1374 __le64 vnic_id_tbl_addr; 1375 }; 1376 1377 /* Output (16 bytes) */ 1378 struct hwrm_func_vf_vnic_ids_query_output { 1379 __le16 error_code; 1380 __le16 req_type; 1381 __le16 seq_id; 1382 __le16 resp_len; 1383 __le32 vnic_id_cnt; 1384 u8 unused_0; 1385 u8 unused_1; 1386 u8 unused_2; 1387 u8 valid; 1388 }; 1389 1390 /* hwrm_func_drv_rgtr */ 1391 /* Input (80 bytes) */ 1392 struct hwrm_func_drv_rgtr_input { 1393 __le16 req_type; 1394 __le16 cmpl_ring; 1395 __le16 seq_id; 1396 __le16 target_id; 1397 __le64 resp_addr; 1398 __le32 flags; 1399 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1400 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1401 __le32 enables; 1402 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1403 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1404 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1405 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1406 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1407 __le16 os_type; 1408 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1409 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1410 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1411 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1412 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1413 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1414 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1415 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1416 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1417 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1418 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1419 u8 ver_maj; 1420 u8 ver_min; 1421 u8 ver_upd; 1422 u8 unused_0; 1423 __le16 unused_1; 1424 __le32 timestamp; 1425 __le32 unused_2; 1426 __le32 vf_req_fwd[8]; 1427 __le32 async_event_fwd[8]; 1428 }; 1429 1430 /* Output (16 bytes) */ 1431 struct hwrm_func_drv_rgtr_output { 1432 __le16 error_code; 1433 __le16 req_type; 1434 __le16 seq_id; 1435 __le16 resp_len; 1436 __le32 unused_0; 1437 u8 unused_1; 1438 u8 unused_2; 1439 u8 unused_3; 1440 u8 valid; 1441 }; 1442 1443 /* hwrm_func_drv_unrgtr */ 1444 /* Input (24 bytes) */ 1445 struct hwrm_func_drv_unrgtr_input { 1446 __le16 req_type; 1447 __le16 cmpl_ring; 1448 __le16 seq_id; 1449 __le16 target_id; 1450 __le64 resp_addr; 1451 __le32 flags; 1452 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1453 __le32 unused_0; 1454 }; 1455 1456 /* Output (16 bytes) */ 1457 struct hwrm_func_drv_unrgtr_output { 1458 __le16 error_code; 1459 __le16 req_type; 1460 __le16 seq_id; 1461 __le16 resp_len; 1462 __le32 unused_0; 1463 u8 unused_1; 1464 u8 unused_2; 1465 u8 unused_3; 1466 u8 valid; 1467 }; 1468 1469 /* hwrm_func_buf_rgtr */ 1470 /* Input (128 bytes) */ 1471 struct hwrm_func_buf_rgtr_input { 1472 __le16 req_type; 1473 __le16 cmpl_ring; 1474 __le16 seq_id; 1475 __le16 target_id; 1476 __le64 resp_addr; 1477 __le32 enables; 1478 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1479 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1480 __le16 vf_id; 1481 __le16 req_buf_num_pages; 1482 __le16 req_buf_page_size; 1483 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1484 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1485 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1486 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1487 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1488 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1489 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1490 __le16 req_buf_len; 1491 __le16 resp_buf_len; 1492 u8 unused_0; 1493 u8 unused_1; 1494 __le64 req_buf_page_addr0; 1495 __le64 req_buf_page_addr1; 1496 __le64 req_buf_page_addr2; 1497 __le64 req_buf_page_addr3; 1498 __le64 req_buf_page_addr4; 1499 __le64 req_buf_page_addr5; 1500 __le64 req_buf_page_addr6; 1501 __le64 req_buf_page_addr7; 1502 __le64 req_buf_page_addr8; 1503 __le64 req_buf_page_addr9; 1504 __le64 error_buf_addr; 1505 __le64 resp_buf_addr; 1506 }; 1507 1508 /* Output (16 bytes) */ 1509 struct hwrm_func_buf_rgtr_output { 1510 __le16 error_code; 1511 __le16 req_type; 1512 __le16 seq_id; 1513 __le16 resp_len; 1514 __le32 unused_0; 1515 u8 unused_1; 1516 u8 unused_2; 1517 u8 unused_3; 1518 u8 valid; 1519 }; 1520 1521 /* hwrm_func_drv_qver */ 1522 /* Input (24 bytes) */ 1523 struct hwrm_func_drv_qver_input { 1524 __le16 req_type; 1525 __le16 cmpl_ring; 1526 __le16 seq_id; 1527 __le16 target_id; 1528 __le64 resp_addr; 1529 __le32 reserved; 1530 __le16 fid; 1531 __le16 unused_0; 1532 }; 1533 1534 /* Output (16 bytes) */ 1535 struct hwrm_func_drv_qver_output { 1536 __le16 error_code; 1537 __le16 req_type; 1538 __le16 seq_id; 1539 __le16 resp_len; 1540 __le16 os_type; 1541 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1542 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1543 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1544 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1545 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1546 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1547 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1548 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1549 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1550 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1551 u8 ver_maj; 1552 u8 ver_min; 1553 u8 ver_upd; 1554 u8 unused_0; 1555 u8 unused_1; 1556 u8 valid; 1557 }; 1558 1559 /* hwrm_port_phy_cfg */ 1560 /* Input (56 bytes) */ 1561 struct hwrm_port_phy_cfg_input { 1562 __le16 req_type; 1563 __le16 cmpl_ring; 1564 __le16 seq_id; 1565 __le16 target_id; 1566 __le64 resp_addr; 1567 __le32 flags; 1568 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1569 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1570 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1571 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1572 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1573 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1574 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1575 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1576 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1577 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1578 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1579 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1580 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1581 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1582 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1583 __le32 enables; 1584 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1585 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1586 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1587 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1588 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1589 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1590 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1591 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1592 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1593 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1594 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1595 __le16 port_id; 1596 __le16 force_link_speed; 1597 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1598 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1599 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1600 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1601 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1602 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1603 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1604 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1605 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1606 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1607 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1608 u8 auto_mode; 1609 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1610 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1611 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1612 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1613 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1614 u8 auto_duplex; 1615 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1616 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1617 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1618 u8 auto_pause; 1619 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1620 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1621 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1622 u8 unused_0; 1623 __le16 auto_link_speed; 1624 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1625 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1626 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1627 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1628 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1629 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1630 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1631 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1632 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1633 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1634 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1635 __le16 auto_link_speed_mask; 1636 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1637 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1638 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1639 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1640 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1641 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1642 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1643 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1644 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1645 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1646 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1647 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1648 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1649 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1650 u8 wirespeed; 1651 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1652 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1653 u8 lpbk; 1654 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1655 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1656 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1657 u8 force_pause; 1658 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1659 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1660 u8 unused_1; 1661 __le32 preemphasis; 1662 __le16 eee_link_speed_mask; 1663 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1664 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1665 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1666 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1667 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1668 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1669 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1670 u8 unused_2; 1671 u8 unused_3; 1672 __le32 tx_lpi_timer; 1673 __le32 unused_4; 1674 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1675 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1676 }; 1677 1678 /* Output (16 bytes) */ 1679 struct hwrm_port_phy_cfg_output { 1680 __le16 error_code; 1681 __le16 req_type; 1682 __le16 seq_id; 1683 __le16 resp_len; 1684 __le32 unused_0; 1685 u8 unused_1; 1686 u8 unused_2; 1687 u8 unused_3; 1688 u8 valid; 1689 }; 1690 1691 /* hwrm_port_phy_qcfg */ 1692 /* Input (24 bytes) */ 1693 struct hwrm_port_phy_qcfg_input { 1694 __le16 req_type; 1695 __le16 cmpl_ring; 1696 __le16 seq_id; 1697 __le16 target_id; 1698 __le64 resp_addr; 1699 __le16 port_id; 1700 __le16 unused_0[3]; 1701 }; 1702 1703 /* Output (96 bytes) */ 1704 struct hwrm_port_phy_qcfg_output { 1705 __le16 error_code; 1706 __le16 req_type; 1707 __le16 seq_id; 1708 __le16 resp_len; 1709 u8 link; 1710 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1711 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1712 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1713 u8 unused_0; 1714 __le16 link_speed; 1715 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1716 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1717 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1718 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1719 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1720 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1721 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1722 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1723 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1724 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1725 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1726 u8 duplex; 1727 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF 0x0UL 1728 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL 0x1UL 1729 u8 pause; 1730 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1731 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1732 __le16 support_speeds; 1733 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1734 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1735 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1736 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1737 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1738 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1739 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1740 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1741 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1742 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1743 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1744 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1745 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1746 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1747 __le16 force_link_speed; 1748 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1749 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1750 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1751 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1752 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1753 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1754 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1755 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1756 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1757 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1758 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1759 u8 auto_mode; 1760 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1761 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1762 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1763 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1764 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1765 u8 auto_pause; 1766 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1767 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1768 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1769 __le16 auto_link_speed; 1770 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1771 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1772 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1773 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1774 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1775 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1776 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1777 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1778 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1779 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1780 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1781 __le16 auto_link_speed_mask; 1782 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1783 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1784 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1785 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1786 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1787 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1788 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1789 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1790 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1791 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1792 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1793 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1794 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1795 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1796 u8 wirespeed; 1797 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1798 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1799 u8 lpbk; 1800 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1801 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1802 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1803 u8 force_pause; 1804 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1805 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1806 u8 module_status; 1807 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1808 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1809 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1810 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1811 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1812 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1813 __le32 preemphasis; 1814 u8 phy_maj; 1815 u8 phy_min; 1816 u8 phy_bld; 1817 u8 phy_type; 1818 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1819 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1820 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1821 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1822 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1823 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1824 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1825 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1826 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1827 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1828 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1829 u8 media_type; 1830 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1831 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1832 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1833 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1834 u8 xcvr_pkg_type; 1835 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1836 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1837 u8 eee_config_phy_addr; 1838 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1839 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1840 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1841 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1842 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1843 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1844 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1845 u8 parallel_detect; 1846 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1847 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1848 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1849 __le16 link_partner_adv_speeds; 1850 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1851 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1852 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1853 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1854 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1855 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1856 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1857 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1858 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1859 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1860 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1861 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1862 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1863 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1864 u8 link_partner_adv_auto_mode; 1865 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1866 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1867 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1868 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1869 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1870 u8 link_partner_adv_pause; 1871 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1872 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1873 __le16 adv_eee_link_speed_mask; 1874 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1875 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1876 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1877 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1878 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1879 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1880 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1881 __le16 link_partner_adv_eee_link_speed_mask; 1882 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1883 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1884 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1885 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1886 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1887 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1888 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1889 __le32 xcvr_identifier_type_tx_lpi_timer; 1890 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1891 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1892 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1893 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1894 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1895 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1896 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1897 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1898 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1899 __le16 fec_cfg; 1900 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1901 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1902 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1903 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1904 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1905 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1906 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1907 u8 unused_1; 1908 u8 unused_2; 1909 char phy_vendor_name[16]; 1910 char phy_vendor_partnumber[16]; 1911 __le32 unused_3; 1912 u8 unused_4; 1913 u8 unused_5; 1914 u8 unused_6; 1915 u8 valid; 1916 }; 1917 1918 /* hwrm_port_mac_cfg */ 1919 /* Input (40 bytes) */ 1920 struct hwrm_port_mac_cfg_input { 1921 __le16 req_type; 1922 __le16 cmpl_ring; 1923 __le16 seq_id; 1924 __le16 target_id; 1925 __le64 resp_addr; 1926 __le32 flags; 1927 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1928 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1929 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1930 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1931 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1932 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1933 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1934 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1935 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1936 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1937 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1938 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1939 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1940 __le32 enables; 1941 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1942 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1943 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1944 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1945 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1946 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1947 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1948 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1949 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1950 __le16 port_id; 1951 u8 ipg; 1952 u8 lpbk; 1953 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1954 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1955 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1956 u8 vlan_pri2cos_map_pri; 1957 u8 reserved1; 1958 u8 tunnel_pri2cos_map_pri; 1959 u8 dscp2pri_map_pri; 1960 __le16 rx_ts_capture_ptp_msg_type; 1961 __le16 tx_ts_capture_ptp_msg_type; 1962 u8 cos_field_cfg; 1963 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1964 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1965 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1966 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1967 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1968 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1969 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1970 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1971 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1972 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1973 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1974 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1975 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1976 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1977 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1978 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1979 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1980 u8 unused_0[3]; 1981 }; 1982 1983 /* Output (16 bytes) */ 1984 struct hwrm_port_mac_cfg_output { 1985 __le16 error_code; 1986 __le16 req_type; 1987 __le16 seq_id; 1988 __le16 resp_len; 1989 __le16 mru; 1990 __le16 mtu; 1991 u8 ipg; 1992 u8 lpbk; 1993 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1994 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1995 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1996 u8 unused_0; 1997 u8 valid; 1998 }; 1999 2000 /* hwrm_port_qstats */ 2001 /* Input (40 bytes) */ 2002 struct hwrm_port_qstats_input { 2003 __le16 req_type; 2004 __le16 cmpl_ring; 2005 __le16 seq_id; 2006 __le16 target_id; 2007 __le64 resp_addr; 2008 __le16 port_id; 2009 u8 unused_0; 2010 u8 unused_1; 2011 u8 unused_2[3]; 2012 u8 unused_3; 2013 __le64 tx_stat_host_addr; 2014 __le64 rx_stat_host_addr; 2015 }; 2016 2017 /* Output (16 bytes) */ 2018 struct hwrm_port_qstats_output { 2019 __le16 error_code; 2020 __le16 req_type; 2021 __le16 seq_id; 2022 __le16 resp_len; 2023 __le16 tx_stat_size; 2024 __le16 rx_stat_size; 2025 u8 unused_0; 2026 u8 unused_1; 2027 u8 unused_2; 2028 u8 valid; 2029 }; 2030 2031 /* hwrm_port_lpbk_qstats */ 2032 /* Input (16 bytes) */ 2033 struct hwrm_port_lpbk_qstats_input { 2034 __le16 req_type; 2035 __le16 cmpl_ring; 2036 __le16 seq_id; 2037 __le16 target_id; 2038 __le64 resp_addr; 2039 }; 2040 2041 /* Output (96 bytes) */ 2042 struct hwrm_port_lpbk_qstats_output { 2043 __le16 error_code; 2044 __le16 req_type; 2045 __le16 seq_id; 2046 __le16 resp_len; 2047 __le64 lpbk_ucast_frames; 2048 __le64 lpbk_mcast_frames; 2049 __le64 lpbk_bcast_frames; 2050 __le64 lpbk_ucast_bytes; 2051 __le64 lpbk_mcast_bytes; 2052 __le64 lpbk_bcast_bytes; 2053 __le64 tx_stat_discard; 2054 __le64 tx_stat_error; 2055 __le64 rx_stat_discard; 2056 __le64 rx_stat_error; 2057 __le32 unused_0; 2058 u8 unused_1; 2059 u8 unused_2; 2060 u8 unused_3; 2061 u8 valid; 2062 }; 2063 2064 /* hwrm_port_clr_stats */ 2065 /* Input (24 bytes) */ 2066 struct hwrm_port_clr_stats_input { 2067 __le16 req_type; 2068 __le16 cmpl_ring; 2069 __le16 seq_id; 2070 __le16 target_id; 2071 __le64 resp_addr; 2072 __le16 port_id; 2073 __le16 unused_0[3]; 2074 }; 2075 2076 /* Output (16 bytes) */ 2077 struct hwrm_port_clr_stats_output { 2078 __le16 error_code; 2079 __le16 req_type; 2080 __le16 seq_id; 2081 __le16 resp_len; 2082 __le32 unused_0; 2083 u8 unused_1; 2084 u8 unused_2; 2085 u8 unused_3; 2086 u8 valid; 2087 }; 2088 2089 /* hwrm_port_lpbk_clr_stats */ 2090 /* Input (16 bytes) */ 2091 struct hwrm_port_lpbk_clr_stats_input { 2092 __le16 req_type; 2093 __le16 cmpl_ring; 2094 __le16 seq_id; 2095 __le16 target_id; 2096 __le64 resp_addr; 2097 }; 2098 2099 /* Output (16 bytes) */ 2100 struct hwrm_port_lpbk_clr_stats_output { 2101 __le16 error_code; 2102 __le16 req_type; 2103 __le16 seq_id; 2104 __le16 resp_len; 2105 __le32 unused_0; 2106 u8 unused_1; 2107 u8 unused_2; 2108 u8 unused_3; 2109 u8 valid; 2110 }; 2111 2112 /* hwrm_port_blink_led */ 2113 /* Input (24 bytes) */ 2114 struct hwrm_port_blink_led_input { 2115 __le16 req_type; 2116 __le16 cmpl_ring; 2117 __le16 seq_id; 2118 __le16 target_id; 2119 __le64 resp_addr; 2120 __le32 num_blinks; 2121 __le32 unused_0; 2122 }; 2123 2124 /* Output (16 bytes) */ 2125 struct hwrm_port_blink_led_output { 2126 __le16 error_code; 2127 __le16 req_type; 2128 __le16 seq_id; 2129 __le16 resp_len; 2130 __le32 unused_0; 2131 u8 unused_1; 2132 u8 unused_2; 2133 u8 unused_3; 2134 u8 valid; 2135 }; 2136 2137 /* hwrm_port_phy_qcaps */ 2138 /* Input (24 bytes) */ 2139 struct hwrm_port_phy_qcaps_input { 2140 __le16 req_type; 2141 __le16 cmpl_ring; 2142 __le16 seq_id; 2143 __le16 target_id; 2144 __le64 resp_addr; 2145 __le16 port_id; 2146 __le16 unused_0[3]; 2147 }; 2148 2149 /* Output (24 bytes) */ 2150 struct hwrm_port_phy_qcaps_output { 2151 __le16 error_code; 2152 __le16 req_type; 2153 __le16 seq_id; 2154 __le16 resp_len; 2155 u8 eee_supported; 2156 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 2157 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 2158 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 2159 u8 unused_0; 2160 __le16 supported_speeds_force_mode; 2161 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2162 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2163 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2164 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2165 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2166 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2167 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2168 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2169 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2170 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2171 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2172 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2173 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2174 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2175 __le16 supported_speeds_auto_mode; 2176 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2177 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2178 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2179 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2180 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2181 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2182 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2183 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2184 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2185 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2186 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2187 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2188 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2189 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2190 __le16 supported_speeds_eee_mode; 2191 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2192 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2193 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2194 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2195 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2196 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2197 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2198 __le32 tx_lpi_timer_low; 2199 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2200 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2201 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2202 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2203 __le32 valid_tx_lpi_timer_high; 2204 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2205 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2206 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2207 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2208 }; 2209 2210 /* hwrm_port_phy_i2c_read */ 2211 /* Input (40 bytes) */ 2212 struct hwrm_port_phy_i2c_read_input { 2213 __le16 req_type; 2214 __le16 cmpl_ring; 2215 __le16 seq_id; 2216 __le16 target_id; 2217 __le64 resp_addr; 2218 __le32 flags; 2219 __le32 enables; 2220 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2221 __le16 port_id; 2222 u8 i2c_slave_addr; 2223 u8 unused_0; 2224 __le16 page_number; 2225 __le16 page_offset; 2226 u8 data_length; 2227 u8 unused_1[7]; 2228 }; 2229 2230 /* Output (80 bytes) */ 2231 struct hwrm_port_phy_i2c_read_output { 2232 __le16 error_code; 2233 __le16 req_type; 2234 __le16 seq_id; 2235 __le16 resp_len; 2236 __le32 data[16]; 2237 __le32 unused_0; 2238 u8 unused_1; 2239 u8 unused_2; 2240 u8 unused_3; 2241 u8 valid; 2242 }; 2243 2244 /* hwrm_queue_qportcfg */ 2245 /* Input (24 bytes) */ 2246 struct hwrm_queue_qportcfg_input { 2247 __le16 req_type; 2248 __le16 cmpl_ring; 2249 __le16 seq_id; 2250 __le16 target_id; 2251 __le64 resp_addr; 2252 __le32 flags; 2253 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2254 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2255 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2256 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2257 __le16 port_id; 2258 __le16 unused_0; 2259 }; 2260 2261 /* Output (32 bytes) */ 2262 struct hwrm_queue_qportcfg_output { 2263 __le16 error_code; 2264 __le16 req_type; 2265 __le16 seq_id; 2266 __le16 resp_len; 2267 u8 max_configurable_queues; 2268 u8 max_configurable_lossless_queues; 2269 u8 queue_cfg_allowed; 2270 u8 queue_cfg_info; 2271 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2272 u8 queue_pfcenable_cfg_allowed; 2273 u8 queue_pri2cos_cfg_allowed; 2274 u8 queue_cos2bw_cfg_allowed; 2275 u8 queue_id0; 2276 u8 queue_id0_service_profile; 2277 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2278 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2279 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2280 u8 queue_id1; 2281 u8 queue_id1_service_profile; 2282 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2283 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2284 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2285 u8 queue_id2; 2286 u8 queue_id2_service_profile; 2287 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2288 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2289 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2290 u8 queue_id3; 2291 u8 queue_id3_service_profile; 2292 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2293 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2294 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2295 u8 queue_id4; 2296 u8 queue_id4_service_profile; 2297 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2298 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2299 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2300 u8 queue_id5; 2301 u8 queue_id5_service_profile; 2302 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2303 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2304 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2305 u8 queue_id6; 2306 u8 queue_id6_service_profile; 2307 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2308 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2309 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2310 u8 queue_id7; 2311 u8 queue_id7_service_profile; 2312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2313 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2315 u8 valid; 2316 }; 2317 2318 /* hwrm_queue_cfg */ 2319 /* Input (40 bytes) */ 2320 struct hwrm_queue_cfg_input { 2321 __le16 req_type; 2322 __le16 cmpl_ring; 2323 __le16 seq_id; 2324 __le16 target_id; 2325 __le64 resp_addr; 2326 __le32 flags; 2327 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2328 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2329 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2330 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2331 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2332 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2333 __le32 enables; 2334 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2335 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2336 __le32 queue_id; 2337 __le32 dflt_len; 2338 u8 service_profile; 2339 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2340 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2341 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2342 u8 unused_0[7]; 2343 }; 2344 2345 /* Output (16 bytes) */ 2346 struct hwrm_queue_cfg_output { 2347 __le16 error_code; 2348 __le16 req_type; 2349 __le16 seq_id; 2350 __le16 resp_len; 2351 __le32 unused_0; 2352 u8 unused_1; 2353 u8 unused_2; 2354 u8 unused_3; 2355 u8 valid; 2356 }; 2357 2358 /* hwrm_queue_pfcenable_cfg */ 2359 /* Input (24 bytes) */ 2360 struct hwrm_queue_pfcenable_cfg_input { 2361 __le16 req_type; 2362 __le16 cmpl_ring; 2363 __le16 seq_id; 2364 __le16 target_id; 2365 __le64 resp_addr; 2366 __le32 flags; 2367 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2368 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2369 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2370 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2371 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2372 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2373 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2374 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2375 __le16 port_id; 2376 __le16 unused_0; 2377 }; 2378 2379 /* Output (16 bytes) */ 2380 struct hwrm_queue_pfcenable_cfg_output { 2381 __le16 error_code; 2382 __le16 req_type; 2383 __le16 seq_id; 2384 __le16 resp_len; 2385 __le32 unused_0; 2386 u8 unused_1; 2387 u8 unused_2; 2388 u8 unused_3; 2389 u8 valid; 2390 }; 2391 2392 /* hwrm_queue_pri2cos_cfg */ 2393 /* Input (40 bytes) */ 2394 struct hwrm_queue_pri2cos_cfg_input { 2395 __le16 req_type; 2396 __le16 cmpl_ring; 2397 __le16 seq_id; 2398 __le16 target_id; 2399 __le64 resp_addr; 2400 __le32 flags; 2401 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2402 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2403 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2404 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2405 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2406 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2407 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2408 __le32 enables; 2409 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2410 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2411 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2412 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2413 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2414 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2415 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2416 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2417 u8 port_id; 2418 u8 pri0_cos_queue_id; 2419 u8 pri1_cos_queue_id; 2420 u8 pri2_cos_queue_id; 2421 u8 pri3_cos_queue_id; 2422 u8 pri4_cos_queue_id; 2423 u8 pri5_cos_queue_id; 2424 u8 pri6_cos_queue_id; 2425 u8 pri7_cos_queue_id; 2426 u8 unused_0[7]; 2427 }; 2428 2429 /* Output (16 bytes) */ 2430 struct hwrm_queue_pri2cos_cfg_output { 2431 __le16 error_code; 2432 __le16 req_type; 2433 __le16 seq_id; 2434 __le16 resp_len; 2435 __le32 unused_0; 2436 u8 unused_1; 2437 u8 unused_2; 2438 u8 unused_3; 2439 u8 valid; 2440 }; 2441 2442 /* hwrm_queue_cos2bw_cfg */ 2443 /* Input (128 bytes) */ 2444 struct hwrm_queue_cos2bw_cfg_input { 2445 __le16 req_type; 2446 __le16 cmpl_ring; 2447 __le16 seq_id; 2448 __le16 target_id; 2449 __le64 resp_addr; 2450 __le32 flags; 2451 __le32 enables; 2452 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2453 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2454 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2455 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2456 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2457 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2458 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2459 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2460 __le16 port_id; 2461 u8 queue_id0; 2462 u8 unused_0; 2463 __le32 queue_id0_min_bw; 2464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_RSVD 0x10000000UL 2467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2473 __le32 queue_id0_max_bw; 2474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_RSVD 0x10000000UL 2477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2483 u8 queue_id0_tsa_assign; 2484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2488 u8 queue_id0_pri_lvl; 2489 u8 queue_id0_bw_weight; 2490 u8 queue_id1; 2491 __le32 queue_id1_min_bw; 2492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_RSVD 0x10000000UL 2495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2500 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2501 __le32 queue_id1_max_bw; 2502 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_RSVD 0x10000000UL 2505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2511 u8 queue_id1_tsa_assign; 2512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2516 u8 queue_id1_pri_lvl; 2517 u8 queue_id1_bw_weight; 2518 u8 queue_id2; 2519 __le32 queue_id2_min_bw; 2520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2521 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_RSVD 0x10000000UL 2523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2529 __le32 queue_id2_max_bw; 2530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_RSVD 0x10000000UL 2533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2539 u8 queue_id2_tsa_assign; 2540 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2543 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2544 u8 queue_id2_pri_lvl; 2545 u8 queue_id2_bw_weight; 2546 u8 queue_id3; 2547 __le32 queue_id3_min_bw; 2548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_RSVD 0x10000000UL 2551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2557 __le32 queue_id3_max_bw; 2558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2559 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_RSVD 0x10000000UL 2561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2567 u8 queue_id3_tsa_assign; 2568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2572 u8 queue_id3_pri_lvl; 2573 u8 queue_id3_bw_weight; 2574 u8 queue_id4; 2575 __le32 queue_id4_min_bw; 2576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2577 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_RSVD 0x10000000UL 2579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2580 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2582 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2585 __le32 queue_id4_max_bw; 2586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_RSVD 0x10000000UL 2589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2595 u8 queue_id4_tsa_assign; 2596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2600 u8 queue_id4_pri_lvl; 2601 u8 queue_id4_bw_weight; 2602 u8 queue_id5; 2603 __le32 queue_id5_min_bw; 2604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_RSVD 0x10000000UL 2607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2613 __le32 queue_id5_max_bw; 2614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_RSVD 0x10000000UL 2617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2620 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2623 u8 queue_id5_tsa_assign; 2624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2628 u8 queue_id5_pri_lvl; 2629 u8 queue_id5_bw_weight; 2630 u8 queue_id6; 2631 __le32 queue_id6_min_bw; 2632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_RSVD 0x10000000UL 2635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2641 __le32 queue_id6_max_bw; 2642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_RSVD 0x10000000UL 2645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2651 u8 queue_id6_tsa_assign; 2652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2655 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2656 u8 queue_id6_pri_lvl; 2657 u8 queue_id6_bw_weight; 2658 u8 queue_id7; 2659 __le32 queue_id7_min_bw; 2660 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2661 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2662 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_RSVD 0x10000000UL 2663 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2665 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2666 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2667 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2668 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2669 __le32 queue_id7_max_bw; 2670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_RSVD 0x10000000UL 2673 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2676 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2679 u8 queue_id7_tsa_assign; 2680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2682 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2683 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2684 u8 queue_id7_pri_lvl; 2685 u8 queue_id7_bw_weight; 2686 u8 unused_1[5]; 2687 }; 2688 2689 /* Output (16 bytes) */ 2690 struct hwrm_queue_cos2bw_cfg_output { 2691 __le16 error_code; 2692 __le16 req_type; 2693 __le16 seq_id; 2694 __le16 resp_len; 2695 __le32 unused_0; 2696 u8 unused_1; 2697 u8 unused_2; 2698 u8 unused_3; 2699 u8 valid; 2700 }; 2701 2702 /* hwrm_vnic_alloc */ 2703 /* Input (24 bytes) */ 2704 struct hwrm_vnic_alloc_input { 2705 __le16 req_type; 2706 __le16 cmpl_ring; 2707 __le16 seq_id; 2708 __le16 target_id; 2709 __le64 resp_addr; 2710 __le32 flags; 2711 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 2712 __le32 unused_0; 2713 }; 2714 2715 /* Output (16 bytes) */ 2716 struct hwrm_vnic_alloc_output { 2717 __le16 error_code; 2718 __le16 req_type; 2719 __le16 seq_id; 2720 __le16 resp_len; 2721 __le32 vnic_id; 2722 u8 unused_0; 2723 u8 unused_1; 2724 u8 unused_2; 2725 u8 valid; 2726 }; 2727 2728 /* hwrm_vnic_free */ 2729 /* Input (24 bytes) */ 2730 struct hwrm_vnic_free_input { 2731 __le16 req_type; 2732 __le16 cmpl_ring; 2733 __le16 seq_id; 2734 __le16 target_id; 2735 __le64 resp_addr; 2736 __le32 vnic_id; 2737 __le32 unused_0; 2738 }; 2739 2740 /* Output (16 bytes) */ 2741 struct hwrm_vnic_free_output { 2742 __le16 error_code; 2743 __le16 req_type; 2744 __le16 seq_id; 2745 __le16 resp_len; 2746 __le32 unused_0; 2747 u8 unused_1; 2748 u8 unused_2; 2749 u8 unused_3; 2750 u8 valid; 2751 }; 2752 2753 /* hwrm_vnic_cfg */ 2754 /* Input (40 bytes) */ 2755 struct hwrm_vnic_cfg_input { 2756 __le16 req_type; 2757 __le16 cmpl_ring; 2758 __le16 seq_id; 2759 __le16 target_id; 2760 __le64 resp_addr; 2761 __le32 flags; 2762 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 2763 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 2764 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 2765 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 2766 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 2767 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 2768 __le32 enables; 2769 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 2770 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 2771 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 2772 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 2773 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 2774 __le16 vnic_id; 2775 __le16 dflt_ring_grp; 2776 __le16 rss_rule; 2777 __le16 cos_rule; 2778 __le16 lb_rule; 2779 __le16 mru; 2780 __le32 unused_0; 2781 }; 2782 2783 /* Output (16 bytes) */ 2784 struct hwrm_vnic_cfg_output { 2785 __le16 error_code; 2786 __le16 req_type; 2787 __le16 seq_id; 2788 __le16 resp_len; 2789 __le32 unused_0; 2790 u8 unused_1; 2791 u8 unused_2; 2792 u8 unused_3; 2793 u8 valid; 2794 }; 2795 2796 /* hwrm_vnic_tpa_cfg */ 2797 /* Input (40 bytes) */ 2798 struct hwrm_vnic_tpa_cfg_input { 2799 __le16 req_type; 2800 __le16 cmpl_ring; 2801 __le16 seq_id; 2802 __le16 target_id; 2803 __le64 resp_addr; 2804 __le32 flags; 2805 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 2806 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 2807 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 2808 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 2809 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 2810 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 2811 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 2812 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 2813 __le32 enables; 2814 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 2815 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 2816 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 2817 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 2818 __le16 vnic_id; 2819 __le16 max_agg_segs; 2820 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 2821 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 2822 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 2823 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 2824 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 2825 __le16 max_aggs; 2826 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 2827 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 2828 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 2829 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 2830 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 2831 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 2832 u8 unused_0; 2833 u8 unused_1; 2834 __le32 max_agg_timer; 2835 __le32 min_agg_len; 2836 }; 2837 2838 /* Output (16 bytes) */ 2839 struct hwrm_vnic_tpa_cfg_output { 2840 __le16 error_code; 2841 __le16 req_type; 2842 __le16 seq_id; 2843 __le16 resp_len; 2844 __le32 unused_0; 2845 u8 unused_1; 2846 u8 unused_2; 2847 u8 unused_3; 2848 u8 valid; 2849 }; 2850 2851 /* hwrm_vnic_rss_cfg */ 2852 /* Input (48 bytes) */ 2853 struct hwrm_vnic_rss_cfg_input { 2854 __le16 req_type; 2855 __le16 cmpl_ring; 2856 __le16 seq_id; 2857 __le16 target_id; 2858 __le64 resp_addr; 2859 __le32 hash_type; 2860 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 2861 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 2862 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 2863 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 2864 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 2865 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 2866 __le32 unused_0; 2867 __le64 ring_grp_tbl_addr; 2868 __le64 hash_key_tbl_addr; 2869 __le16 rss_ctx_idx; 2870 __le16 unused_1[3]; 2871 }; 2872 2873 /* Output (16 bytes) */ 2874 struct hwrm_vnic_rss_cfg_output { 2875 __le16 error_code; 2876 __le16 req_type; 2877 __le16 seq_id; 2878 __le16 resp_len; 2879 __le32 unused_0; 2880 u8 unused_1; 2881 u8 unused_2; 2882 u8 unused_3; 2883 u8 valid; 2884 }; 2885 2886 /* hwrm_vnic_plcmodes_cfg */ 2887 /* Input (40 bytes) */ 2888 struct hwrm_vnic_plcmodes_cfg_input { 2889 __le16 req_type; 2890 __le16 cmpl_ring; 2891 __le16 seq_id; 2892 __le16 target_id; 2893 __le64 resp_addr; 2894 __le32 flags; 2895 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 2896 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 2897 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 2898 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 2899 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 2900 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 2901 __le32 enables; 2902 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 2903 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 2904 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 2905 __le32 vnic_id; 2906 __le16 jumbo_thresh; 2907 __le16 hds_offset; 2908 __le16 hds_threshold; 2909 __le16 unused_0[3]; 2910 }; 2911 2912 /* Output (16 bytes) */ 2913 struct hwrm_vnic_plcmodes_cfg_output { 2914 __le16 error_code; 2915 __le16 req_type; 2916 __le16 seq_id; 2917 __le16 resp_len; 2918 __le32 unused_0; 2919 u8 unused_1; 2920 u8 unused_2; 2921 u8 unused_3; 2922 u8 valid; 2923 }; 2924 2925 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 2926 /* Input (16 bytes) */ 2927 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 2928 __le16 req_type; 2929 __le16 cmpl_ring; 2930 __le16 seq_id; 2931 __le16 target_id; 2932 __le64 resp_addr; 2933 }; 2934 2935 /* Output (16 bytes) */ 2936 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 2937 __le16 error_code; 2938 __le16 req_type; 2939 __le16 seq_id; 2940 __le16 resp_len; 2941 __le16 rss_cos_lb_ctx_id; 2942 u8 unused_0; 2943 u8 unused_1; 2944 u8 unused_2; 2945 u8 unused_3; 2946 u8 unused_4; 2947 u8 valid; 2948 }; 2949 2950 /* hwrm_vnic_rss_cos_lb_ctx_free */ 2951 /* Input (24 bytes) */ 2952 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 2953 __le16 req_type; 2954 __le16 cmpl_ring; 2955 __le16 seq_id; 2956 __le16 target_id; 2957 __le64 resp_addr; 2958 __le16 rss_cos_lb_ctx_id; 2959 __le16 unused_0[3]; 2960 }; 2961 2962 /* Output (16 bytes) */ 2963 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 2964 __le16 error_code; 2965 __le16 req_type; 2966 __le16 seq_id; 2967 __le16 resp_len; 2968 __le32 unused_0; 2969 u8 unused_1; 2970 u8 unused_2; 2971 u8 unused_3; 2972 u8 valid; 2973 }; 2974 2975 /* hwrm_ring_alloc */ 2976 /* Input (80 bytes) */ 2977 struct hwrm_ring_alloc_input { 2978 __le16 req_type; 2979 __le16 cmpl_ring; 2980 __le16 seq_id; 2981 __le16 target_id; 2982 __le64 resp_addr; 2983 __le32 enables; 2984 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 2985 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 2986 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 2987 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 2988 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 2989 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 2990 u8 ring_type; 2991 #define RING_ALLOC_REQ_RING_TYPE_CMPL 0x0UL 2992 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 2993 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 2994 u8 unused_0; 2995 __le16 unused_1; 2996 __le64 page_tbl_addr; 2997 __le32 fbo; 2998 u8 page_size; 2999 u8 page_tbl_depth; 3000 u8 unused_2; 3001 u8 unused_3; 3002 __le32 length; 3003 __le16 logical_id; 3004 __le16 cmpl_ring_id; 3005 __le16 queue_id; 3006 u8 unused_4; 3007 u8 unused_5; 3008 __le32 reserved1; 3009 __le16 ring_arb_cfg; 3010 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3011 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3012 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3013 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3014 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3015 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3016 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3017 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3018 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3019 u8 unused_6; 3020 u8 unused_7; 3021 __le32 reserved3; 3022 __le32 stat_ctx_id; 3023 __le32 reserved4; 3024 __le32 max_bw; 3025 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3026 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3027 #define RING_ALLOC_REQ_MAX_BW_RSVD 0x10000000UL 3028 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3029 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3030 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 3031 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3032 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3033 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3034 u8 int_mode; 3035 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3036 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3037 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3038 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3039 u8 unused_8[3]; 3040 }; 3041 3042 /* Output (16 bytes) */ 3043 struct hwrm_ring_alloc_output { 3044 __le16 error_code; 3045 __le16 req_type; 3046 __le16 seq_id; 3047 __le16 resp_len; 3048 __le16 ring_id; 3049 __le16 logical_ring_id; 3050 u8 unused_0; 3051 u8 unused_1; 3052 u8 unused_2; 3053 u8 valid; 3054 }; 3055 3056 /* hwrm_ring_free */ 3057 /* Input (24 bytes) */ 3058 struct hwrm_ring_free_input { 3059 __le16 req_type; 3060 __le16 cmpl_ring; 3061 __le16 seq_id; 3062 __le16 target_id; 3063 __le64 resp_addr; 3064 u8 ring_type; 3065 #define RING_FREE_REQ_RING_TYPE_CMPL 0x0UL 3066 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3067 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3068 u8 unused_0; 3069 __le16 ring_id; 3070 __le32 unused_1; 3071 }; 3072 3073 /* Output (16 bytes) */ 3074 struct hwrm_ring_free_output { 3075 __le16 error_code; 3076 __le16 req_type; 3077 __le16 seq_id; 3078 __le16 resp_len; 3079 __le32 unused_0; 3080 u8 unused_1; 3081 u8 unused_2; 3082 u8 unused_3; 3083 u8 valid; 3084 }; 3085 3086 /* hwrm_ring_cmpl_ring_qaggint_params */ 3087 /* Input (24 bytes) */ 3088 struct hwrm_ring_cmpl_ring_qaggint_params_input { 3089 __le16 req_type; 3090 __le16 cmpl_ring; 3091 __le16 seq_id; 3092 __le16 target_id; 3093 __le64 resp_addr; 3094 __le16 ring_id; 3095 __le16 unused_0[3]; 3096 }; 3097 3098 /* Output (32 bytes) */ 3099 struct hwrm_ring_cmpl_ring_qaggint_params_output { 3100 __le16 error_code; 3101 __le16 req_type; 3102 __le16 seq_id; 3103 __le16 resp_len; 3104 __le16 flags; 3105 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3106 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3107 __le16 num_cmpl_dma_aggr; 3108 __le16 num_cmpl_dma_aggr_during_int; 3109 __le16 cmpl_aggr_dma_tmr; 3110 __le16 cmpl_aggr_dma_tmr_during_int; 3111 __le16 int_lat_tmr_min; 3112 __le16 int_lat_tmr_max; 3113 __le16 num_cmpl_aggr_int; 3114 __le32 unused_0; 3115 u8 unused_1; 3116 u8 unused_2; 3117 u8 unused_3; 3118 u8 valid; 3119 }; 3120 3121 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3122 /* Input (40 bytes) */ 3123 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3124 __le16 req_type; 3125 __le16 cmpl_ring; 3126 __le16 seq_id; 3127 __le16 target_id; 3128 __le64 resp_addr; 3129 __le16 ring_id; 3130 __le16 flags; 3131 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3132 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3133 __le16 num_cmpl_dma_aggr; 3134 __le16 num_cmpl_dma_aggr_during_int; 3135 __le16 cmpl_aggr_dma_tmr; 3136 __le16 cmpl_aggr_dma_tmr_during_int; 3137 __le16 int_lat_tmr_min; 3138 __le16 int_lat_tmr_max; 3139 __le16 num_cmpl_aggr_int; 3140 __le16 unused_0[3]; 3141 }; 3142 3143 /* Output (16 bytes) */ 3144 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3145 __le16 error_code; 3146 __le16 req_type; 3147 __le16 seq_id; 3148 __le16 resp_len; 3149 __le32 unused_0; 3150 u8 unused_1; 3151 u8 unused_2; 3152 u8 unused_3; 3153 u8 valid; 3154 }; 3155 3156 /* hwrm_ring_reset */ 3157 /* Input (24 bytes) */ 3158 struct hwrm_ring_reset_input { 3159 __le16 req_type; 3160 __le16 cmpl_ring; 3161 __le16 seq_id; 3162 __le16 target_id; 3163 __le64 resp_addr; 3164 u8 ring_type; 3165 #define RING_RESET_REQ_RING_TYPE_CMPL 0x0UL 3166 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3167 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3168 u8 unused_0; 3169 __le16 ring_id; 3170 __le32 unused_1; 3171 }; 3172 3173 /* Output (16 bytes) */ 3174 struct hwrm_ring_reset_output { 3175 __le16 error_code; 3176 __le16 req_type; 3177 __le16 seq_id; 3178 __le16 resp_len; 3179 __le32 unused_0; 3180 u8 unused_1; 3181 u8 unused_2; 3182 u8 unused_3; 3183 u8 valid; 3184 }; 3185 3186 /* hwrm_ring_grp_alloc */ 3187 /* Input (24 bytes) */ 3188 struct hwrm_ring_grp_alloc_input { 3189 __le16 req_type; 3190 __le16 cmpl_ring; 3191 __le16 seq_id; 3192 __le16 target_id; 3193 __le64 resp_addr; 3194 __le16 cr; 3195 __le16 rr; 3196 __le16 ar; 3197 __le16 sc; 3198 }; 3199 3200 /* Output (16 bytes) */ 3201 struct hwrm_ring_grp_alloc_output { 3202 __le16 error_code; 3203 __le16 req_type; 3204 __le16 seq_id; 3205 __le16 resp_len; 3206 __le32 ring_group_id; 3207 u8 unused_0; 3208 u8 unused_1; 3209 u8 unused_2; 3210 u8 valid; 3211 }; 3212 3213 /* hwrm_ring_grp_free */ 3214 /* Input (24 bytes) */ 3215 struct hwrm_ring_grp_free_input { 3216 __le16 req_type; 3217 __le16 cmpl_ring; 3218 __le16 seq_id; 3219 __le16 target_id; 3220 __le64 resp_addr; 3221 __le32 ring_group_id; 3222 __le32 unused_0; 3223 }; 3224 3225 /* Output (16 bytes) */ 3226 struct hwrm_ring_grp_free_output { 3227 __le16 error_code; 3228 __le16 req_type; 3229 __le16 seq_id; 3230 __le16 resp_len; 3231 __le32 unused_0; 3232 u8 unused_1; 3233 u8 unused_2; 3234 u8 unused_3; 3235 u8 valid; 3236 }; 3237 3238 /* hwrm_cfa_l2_filter_alloc */ 3239 /* Input (96 bytes) */ 3240 struct hwrm_cfa_l2_filter_alloc_input { 3241 __le16 req_type; 3242 __le16 cmpl_ring; 3243 __le16 seq_id; 3244 __le16 target_id; 3245 __le64 resp_addr; 3246 __le32 flags; 3247 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3248 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3249 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3250 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3251 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3252 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3253 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3254 __le32 enables; 3255 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3256 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3257 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3258 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3259 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3260 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3261 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3262 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3263 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3264 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3265 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3266 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3267 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3268 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3269 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3270 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3271 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3272 u8 l2_addr[6]; 3273 u8 unused_0; 3274 u8 unused_1; 3275 u8 l2_addr_mask[6]; 3276 __le16 l2_ovlan; 3277 __le16 l2_ovlan_mask; 3278 __le16 l2_ivlan; 3279 __le16 l2_ivlan_mask; 3280 u8 unused_2; 3281 u8 unused_3; 3282 u8 t_l2_addr[6]; 3283 u8 unused_4; 3284 u8 unused_5; 3285 u8 t_l2_addr_mask[6]; 3286 __le16 t_l2_ovlan; 3287 __le16 t_l2_ovlan_mask; 3288 __le16 t_l2_ivlan; 3289 __le16 t_l2_ivlan_mask; 3290 u8 src_type; 3291 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3292 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3293 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3294 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3295 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3296 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3297 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3298 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3299 u8 unused_6; 3300 __le32 src_id; 3301 u8 tunnel_type; 3302 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3303 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3304 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3305 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3306 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3307 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3308 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3309 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3310 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3311 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3312 u8 unused_7; 3313 __le16 dst_id; 3314 __le16 mirror_vnic_id; 3315 u8 pri_hint; 3316 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3317 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 3318 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 3319 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 3320 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 3321 u8 unused_8; 3322 __le32 unused_9; 3323 __le64 l2_filter_id_hint; 3324 }; 3325 3326 /* Output (24 bytes) */ 3327 struct hwrm_cfa_l2_filter_alloc_output { 3328 __le16 error_code; 3329 __le16 req_type; 3330 __le16 seq_id; 3331 __le16 resp_len; 3332 __le64 l2_filter_id; 3333 __le32 flow_id; 3334 u8 unused_0; 3335 u8 unused_1; 3336 u8 unused_2; 3337 u8 valid; 3338 }; 3339 3340 /* hwrm_cfa_l2_filter_free */ 3341 /* Input (24 bytes) */ 3342 struct hwrm_cfa_l2_filter_free_input { 3343 __le16 req_type; 3344 __le16 cmpl_ring; 3345 __le16 seq_id; 3346 __le16 target_id; 3347 __le64 resp_addr; 3348 __le64 l2_filter_id; 3349 }; 3350 3351 /* Output (16 bytes) */ 3352 struct hwrm_cfa_l2_filter_free_output { 3353 __le16 error_code; 3354 __le16 req_type; 3355 __le16 seq_id; 3356 __le16 resp_len; 3357 __le32 unused_0; 3358 u8 unused_1; 3359 u8 unused_2; 3360 u8 unused_3; 3361 u8 valid; 3362 }; 3363 3364 /* hwrm_cfa_l2_filter_cfg */ 3365 /* Input (40 bytes) */ 3366 struct hwrm_cfa_l2_filter_cfg_input { 3367 __le16 req_type; 3368 __le16 cmpl_ring; 3369 __le16 seq_id; 3370 __le16 target_id; 3371 __le64 resp_addr; 3372 __le32 flags; 3373 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3374 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3375 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 3376 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3377 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3378 __le32 enables; 3379 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3380 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3381 __le64 l2_filter_id; 3382 __le32 dst_id; 3383 __le32 new_mirror_vnic_id; 3384 }; 3385 3386 /* Output (16 bytes) */ 3387 struct hwrm_cfa_l2_filter_cfg_output { 3388 __le16 error_code; 3389 __le16 req_type; 3390 __le16 seq_id; 3391 __le16 resp_len; 3392 __le32 unused_0; 3393 u8 unused_1; 3394 u8 unused_2; 3395 u8 unused_3; 3396 u8 valid; 3397 }; 3398 3399 /* hwrm_cfa_l2_set_rx_mask */ 3400 /* Input (56 bytes) */ 3401 struct hwrm_cfa_l2_set_rx_mask_input { 3402 __le16 req_type; 3403 __le16 cmpl_ring; 3404 __le16 seq_id; 3405 __le16 target_id; 3406 __le64 resp_addr; 3407 __le32 vnic_id; 3408 __le32 mask; 3409 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3410 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3411 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3412 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3413 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3414 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3415 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 3416 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 3417 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 3418 __le64 mc_tbl_addr; 3419 __le32 num_mc_entries; 3420 __le32 unused_0; 3421 __le64 vlan_tag_tbl_addr; 3422 __le32 num_vlan_tags; 3423 __le32 unused_1; 3424 }; 3425 3426 /* Output (16 bytes) */ 3427 struct hwrm_cfa_l2_set_rx_mask_output { 3428 __le16 error_code; 3429 __le16 req_type; 3430 __le16 seq_id; 3431 __le16 resp_len; 3432 __le32 unused_0; 3433 u8 unused_1; 3434 u8 unused_2; 3435 u8 unused_3; 3436 u8 valid; 3437 }; 3438 3439 /* hwrm_cfa_tunnel_filter_alloc */ 3440 /* Input (88 bytes) */ 3441 struct hwrm_cfa_tunnel_filter_alloc_input { 3442 __le16 req_type; 3443 __le16 cmpl_ring; 3444 __le16 seq_id; 3445 __le16 target_id; 3446 __le64 resp_addr; 3447 __le32 flags; 3448 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3449 __le32 enables; 3450 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3451 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3452 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3453 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3454 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3455 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3456 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3457 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3458 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3459 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3460 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3461 __le64 l2_filter_id; 3462 u8 l2_addr[6]; 3463 __le16 l2_ivlan; 3464 __le32 l3_addr[4]; 3465 __le32 t_l3_addr[4]; 3466 u8 l3_addr_type; 3467 u8 t_l3_addr_type; 3468 u8 tunnel_type; 3469 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3470 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3471 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3472 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3473 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3474 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3475 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3476 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3477 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3478 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3479 u8 unused_0; 3480 __le32 vni; 3481 __le32 dst_vnic_id; 3482 __le32 mirror_vnic_id; 3483 }; 3484 3485 /* Output (24 bytes) */ 3486 struct hwrm_cfa_tunnel_filter_alloc_output { 3487 __le16 error_code; 3488 __le16 req_type; 3489 __le16 seq_id; 3490 __le16 resp_len; 3491 __le64 tunnel_filter_id; 3492 __le32 flow_id; 3493 u8 unused_0; 3494 u8 unused_1; 3495 u8 unused_2; 3496 u8 valid; 3497 }; 3498 3499 /* hwrm_cfa_tunnel_filter_free */ 3500 /* Input (24 bytes) */ 3501 struct hwrm_cfa_tunnel_filter_free_input { 3502 __le16 req_type; 3503 __le16 cmpl_ring; 3504 __le16 seq_id; 3505 __le16 target_id; 3506 __le64 resp_addr; 3507 __le64 tunnel_filter_id; 3508 }; 3509 3510 /* Output (16 bytes) */ 3511 struct hwrm_cfa_tunnel_filter_free_output { 3512 __le16 error_code; 3513 __le16 req_type; 3514 __le16 seq_id; 3515 __le16 resp_len; 3516 __le32 unused_0; 3517 u8 unused_1; 3518 u8 unused_2; 3519 u8 unused_3; 3520 u8 valid; 3521 }; 3522 3523 /* hwrm_cfa_encap_record_alloc */ 3524 /* Input (32 bytes) */ 3525 struct hwrm_cfa_encap_record_alloc_input { 3526 __le16 req_type; 3527 __le16 cmpl_ring; 3528 __le16 seq_id; 3529 __le16 target_id; 3530 __le64 resp_addr; 3531 __le32 flags; 3532 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3533 u8 encap_type; 3534 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 3535 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 3536 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 3537 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 3538 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 3539 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 3540 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 3541 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 3542 u8 unused_0; 3543 __le16 unused_1; 3544 __le32 encap_data[16]; 3545 }; 3546 3547 /* Output (16 bytes) */ 3548 struct hwrm_cfa_encap_record_alloc_output { 3549 __le16 error_code; 3550 __le16 req_type; 3551 __le16 seq_id; 3552 __le16 resp_len; 3553 __le32 encap_record_id; 3554 u8 unused_0; 3555 u8 unused_1; 3556 u8 unused_2; 3557 u8 valid; 3558 }; 3559 3560 /* hwrm_cfa_encap_record_free */ 3561 /* Input (24 bytes) */ 3562 struct hwrm_cfa_encap_record_free_input { 3563 __le16 req_type; 3564 __le16 cmpl_ring; 3565 __le16 seq_id; 3566 __le16 target_id; 3567 __le64 resp_addr; 3568 __le32 encap_record_id; 3569 __le32 unused_0; 3570 }; 3571 3572 /* Output (16 bytes) */ 3573 struct hwrm_cfa_encap_record_free_output { 3574 __le16 error_code; 3575 __le16 req_type; 3576 __le16 seq_id; 3577 __le16 resp_len; 3578 __le32 unused_0; 3579 u8 unused_1; 3580 u8 unused_2; 3581 u8 unused_3; 3582 u8 valid; 3583 }; 3584 3585 /* hwrm_cfa_ntuple_filter_alloc */ 3586 /* Input (128 bytes) */ 3587 struct hwrm_cfa_ntuple_filter_alloc_input { 3588 __le16 req_type; 3589 __le16 cmpl_ring; 3590 __le16 seq_id; 3591 __le16 target_id; 3592 __le64 resp_addr; 3593 __le32 flags; 3594 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3595 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 3596 __le32 enables; 3597 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3598 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 3599 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 3600 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 3601 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 3602 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 3603 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 3604 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 3605 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 3606 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 3607 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 3608 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 3609 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 3610 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 3611 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 3612 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 3613 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 3614 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 3615 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 3616 __le64 l2_filter_id; 3617 u8 src_macaddr[6]; 3618 __be16 ethertype; 3619 u8 ip_addr_type; 3620 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 3621 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 3622 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 3623 u8 ip_protocol; 3624 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 3625 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x6UL 3626 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x11UL 3627 __le16 dst_id; 3628 __le16 mirror_vnic_id; 3629 u8 tunnel_type; 3630 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3631 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3632 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3633 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3634 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3635 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3636 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3637 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3638 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3639 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3640 u8 pri_hint; 3641 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3642 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 3643 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 3644 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 3645 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 3646 __be32 src_ipaddr[4]; 3647 __be32 src_ipaddr_mask[4]; 3648 __be32 dst_ipaddr[4]; 3649 __be32 dst_ipaddr_mask[4]; 3650 __be16 src_port; 3651 __be16 src_port_mask; 3652 __be16 dst_port; 3653 __be16 dst_port_mask; 3654 __le64 ntuple_filter_id_hint; 3655 }; 3656 3657 /* Output (24 bytes) */ 3658 struct hwrm_cfa_ntuple_filter_alloc_output { 3659 __le16 error_code; 3660 __le16 req_type; 3661 __le16 seq_id; 3662 __le16 resp_len; 3663 __le64 ntuple_filter_id; 3664 __le32 flow_id; 3665 u8 unused_0; 3666 u8 unused_1; 3667 u8 unused_2; 3668 u8 valid; 3669 }; 3670 3671 /* hwrm_cfa_ntuple_filter_free */ 3672 /* Input (24 bytes) */ 3673 struct hwrm_cfa_ntuple_filter_free_input { 3674 __le16 req_type; 3675 __le16 cmpl_ring; 3676 __le16 seq_id; 3677 __le16 target_id; 3678 __le64 resp_addr; 3679 __le64 ntuple_filter_id; 3680 }; 3681 3682 /* Output (16 bytes) */ 3683 struct hwrm_cfa_ntuple_filter_free_output { 3684 __le16 error_code; 3685 __le16 req_type; 3686 __le16 seq_id; 3687 __le16 resp_len; 3688 __le32 unused_0; 3689 u8 unused_1; 3690 u8 unused_2; 3691 u8 unused_3; 3692 u8 valid; 3693 }; 3694 3695 /* hwrm_cfa_ntuple_filter_cfg */ 3696 /* Input (40 bytes) */ 3697 struct hwrm_cfa_ntuple_filter_cfg_input { 3698 __le16 req_type; 3699 __le16 cmpl_ring; 3700 __le16 seq_id; 3701 __le16 target_id; 3702 __le64 resp_addr; 3703 __le32 enables; 3704 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 3705 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3706 __le32 unused_0; 3707 __le64 ntuple_filter_id; 3708 __le32 new_dst_id; 3709 __le32 new_mirror_vnic_id; 3710 }; 3711 3712 /* Output (16 bytes) */ 3713 struct hwrm_cfa_ntuple_filter_cfg_output { 3714 __le16 error_code; 3715 __le16 req_type; 3716 __le16 seq_id; 3717 __le16 resp_len; 3718 __le32 unused_0; 3719 u8 unused_1; 3720 u8 unused_2; 3721 u8 unused_3; 3722 u8 valid; 3723 }; 3724 3725 /* hwrm_tunnel_dst_port_query */ 3726 /* Input (24 bytes) */ 3727 struct hwrm_tunnel_dst_port_query_input { 3728 __le16 req_type; 3729 __le16 cmpl_ring; 3730 __le16 seq_id; 3731 __le16 target_id; 3732 __le64 resp_addr; 3733 u8 tunnel_type; 3734 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3735 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3736 u8 unused_0[7]; 3737 }; 3738 3739 /* Output (16 bytes) */ 3740 struct hwrm_tunnel_dst_port_query_output { 3741 __le16 error_code; 3742 __le16 req_type; 3743 __le16 seq_id; 3744 __le16 resp_len; 3745 __le16 tunnel_dst_port_id; 3746 __be16 tunnel_dst_port_val; 3747 u8 unused_0; 3748 u8 unused_1; 3749 u8 unused_2; 3750 u8 valid; 3751 }; 3752 3753 /* hwrm_tunnel_dst_port_alloc */ 3754 /* Input (24 bytes) */ 3755 struct hwrm_tunnel_dst_port_alloc_input { 3756 __le16 req_type; 3757 __le16 cmpl_ring; 3758 __le16 seq_id; 3759 __le16 target_id; 3760 __le64 resp_addr; 3761 u8 tunnel_type; 3762 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3763 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3764 u8 unused_0; 3765 __be16 tunnel_dst_port_val; 3766 __le32 unused_1; 3767 }; 3768 3769 /* Output (16 bytes) */ 3770 struct hwrm_tunnel_dst_port_alloc_output { 3771 __le16 error_code; 3772 __le16 req_type; 3773 __le16 seq_id; 3774 __le16 resp_len; 3775 __le16 tunnel_dst_port_id; 3776 u8 unused_0; 3777 u8 unused_1; 3778 u8 unused_2; 3779 u8 unused_3; 3780 u8 unused_4; 3781 u8 valid; 3782 }; 3783 3784 /* hwrm_tunnel_dst_port_free */ 3785 /* Input (24 bytes) */ 3786 struct hwrm_tunnel_dst_port_free_input { 3787 __le16 req_type; 3788 __le16 cmpl_ring; 3789 __le16 seq_id; 3790 __le16 target_id; 3791 __le64 resp_addr; 3792 u8 tunnel_type; 3793 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3794 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3795 u8 unused_0; 3796 __le16 tunnel_dst_port_id; 3797 __le32 unused_1; 3798 }; 3799 3800 /* Output (16 bytes) */ 3801 struct hwrm_tunnel_dst_port_free_output { 3802 __le16 error_code; 3803 __le16 req_type; 3804 __le16 seq_id; 3805 __le16 resp_len; 3806 __le32 unused_0; 3807 u8 unused_1; 3808 u8 unused_2; 3809 u8 unused_3; 3810 u8 valid; 3811 }; 3812 3813 /* hwrm_stat_ctx_alloc */ 3814 /* Input (32 bytes) */ 3815 struct hwrm_stat_ctx_alloc_input { 3816 __le16 req_type; 3817 __le16 cmpl_ring; 3818 __le16 seq_id; 3819 __le16 target_id; 3820 __le64 resp_addr; 3821 __le64 stats_dma_addr; 3822 __le32 update_period_ms; 3823 __le32 unused_0; 3824 }; 3825 3826 /* Output (16 bytes) */ 3827 struct hwrm_stat_ctx_alloc_output { 3828 __le16 error_code; 3829 __le16 req_type; 3830 __le16 seq_id; 3831 __le16 resp_len; 3832 __le32 stat_ctx_id; 3833 u8 unused_0; 3834 u8 unused_1; 3835 u8 unused_2; 3836 u8 valid; 3837 }; 3838 3839 /* hwrm_stat_ctx_free */ 3840 /* Input (24 bytes) */ 3841 struct hwrm_stat_ctx_free_input { 3842 __le16 req_type; 3843 __le16 cmpl_ring; 3844 __le16 seq_id; 3845 __le16 target_id; 3846 __le64 resp_addr; 3847 __le32 stat_ctx_id; 3848 __le32 unused_0; 3849 }; 3850 3851 /* Output (16 bytes) */ 3852 struct hwrm_stat_ctx_free_output { 3853 __le16 error_code; 3854 __le16 req_type; 3855 __le16 seq_id; 3856 __le16 resp_len; 3857 __le32 stat_ctx_id; 3858 u8 unused_0; 3859 u8 unused_1; 3860 u8 unused_2; 3861 u8 valid; 3862 }; 3863 3864 /* hwrm_stat_ctx_query */ 3865 /* Input (24 bytes) */ 3866 struct hwrm_stat_ctx_query_input { 3867 __le16 req_type; 3868 __le16 cmpl_ring; 3869 __le16 seq_id; 3870 __le16 target_id; 3871 __le64 resp_addr; 3872 __le32 stat_ctx_id; 3873 __le32 unused_0; 3874 }; 3875 3876 /* Output (176 bytes) */ 3877 struct hwrm_stat_ctx_query_output { 3878 __le16 error_code; 3879 __le16 req_type; 3880 __le16 seq_id; 3881 __le16 resp_len; 3882 __le64 tx_ucast_pkts; 3883 __le64 tx_mcast_pkts; 3884 __le64 tx_bcast_pkts; 3885 __le64 tx_err_pkts; 3886 __le64 tx_drop_pkts; 3887 __le64 tx_ucast_bytes; 3888 __le64 tx_mcast_bytes; 3889 __le64 tx_bcast_bytes; 3890 __le64 rx_ucast_pkts; 3891 __le64 rx_mcast_pkts; 3892 __le64 rx_bcast_pkts; 3893 __le64 rx_err_pkts; 3894 __le64 rx_drop_pkts; 3895 __le64 rx_ucast_bytes; 3896 __le64 rx_mcast_bytes; 3897 __le64 rx_bcast_bytes; 3898 __le64 rx_agg_pkts; 3899 __le64 rx_agg_bytes; 3900 __le64 rx_agg_events; 3901 __le64 rx_agg_aborts; 3902 __le32 unused_0; 3903 u8 unused_1; 3904 u8 unused_2; 3905 u8 unused_3; 3906 u8 valid; 3907 }; 3908 3909 /* hwrm_stat_ctx_clr_stats */ 3910 /* Input (24 bytes) */ 3911 struct hwrm_stat_ctx_clr_stats_input { 3912 __le16 req_type; 3913 __le16 cmpl_ring; 3914 __le16 seq_id; 3915 __le16 target_id; 3916 __le64 resp_addr; 3917 __le32 stat_ctx_id; 3918 __le32 unused_0; 3919 }; 3920 3921 /* Output (16 bytes) */ 3922 struct hwrm_stat_ctx_clr_stats_output { 3923 __le16 error_code; 3924 __le16 req_type; 3925 __le16 seq_id; 3926 __le16 resp_len; 3927 __le32 unused_0; 3928 u8 unused_1; 3929 u8 unused_2; 3930 u8 unused_3; 3931 u8 valid; 3932 }; 3933 3934 /* hwrm_fw_reset */ 3935 /* Input (24 bytes) */ 3936 struct hwrm_fw_reset_input { 3937 __le16 req_type; 3938 __le16 cmpl_ring; 3939 __le16 seq_id; 3940 __le16 target_id; 3941 __le64 resp_addr; 3942 u8 embedded_proc_type; 3943 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 3944 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 3945 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 3946 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 3947 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 3948 u8 selfrst_status; 3949 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 3950 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 3951 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3952 __le16 unused_0[3]; 3953 }; 3954 3955 /* Output (16 bytes) */ 3956 struct hwrm_fw_reset_output { 3957 __le16 error_code; 3958 __le16 req_type; 3959 __le16 seq_id; 3960 __le16 resp_len; 3961 u8 selfrst_status; 3962 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 3963 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 3964 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3965 u8 unused_0; 3966 __le16 unused_1; 3967 u8 unused_2; 3968 u8 unused_3; 3969 u8 unused_4; 3970 u8 valid; 3971 }; 3972 3973 /* hwrm_fw_qstatus */ 3974 /* Input (24 bytes) */ 3975 struct hwrm_fw_qstatus_input { 3976 __le16 req_type; 3977 __le16 cmpl_ring; 3978 __le16 seq_id; 3979 __le16 target_id; 3980 __le64 resp_addr; 3981 u8 embedded_proc_type; 3982 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 3983 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 3984 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 3985 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 3986 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 3987 u8 unused_0[7]; 3988 }; 3989 3990 /* Output (16 bytes) */ 3991 struct hwrm_fw_qstatus_output { 3992 __le16 error_code; 3993 __le16 req_type; 3994 __le16 seq_id; 3995 __le16 resp_len; 3996 u8 selfrst_status; 3997 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 3998 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 3999 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4000 u8 unused_0; 4001 __le16 unused_1; 4002 u8 unused_2; 4003 u8 unused_3; 4004 u8 unused_4; 4005 u8 valid; 4006 }; 4007 4008 /* hwrm_fw_set_time */ 4009 /* Input (32 bytes) */ 4010 struct hwrm_fw_set_time_input { 4011 __le16 req_type; 4012 __le16 cmpl_ring; 4013 __le16 seq_id; 4014 __le16 target_id; 4015 __le64 resp_addr; 4016 __le16 year; 4017 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4018 u8 month; 4019 u8 day; 4020 u8 hour; 4021 u8 minute; 4022 u8 second; 4023 u8 unused_0; 4024 __le16 millisecond; 4025 __le16 zone; 4026 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4027 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4028 __le32 unused_1; 4029 }; 4030 4031 /* Output (16 bytes) */ 4032 struct hwrm_fw_set_time_output { 4033 __le16 error_code; 4034 __le16 req_type; 4035 __le16 seq_id; 4036 __le16 resp_len; 4037 __le32 unused_0; 4038 u8 unused_1; 4039 u8 unused_2; 4040 u8 unused_3; 4041 u8 valid; 4042 }; 4043 4044 /* hwrm_fw_set_structured_data */ 4045 /* Input (32 bytes) */ 4046 struct hwrm_fw_set_structured_data_input { 4047 __le16 req_type; 4048 __le16 cmpl_ring; 4049 __le16 seq_id; 4050 __le16 target_id; 4051 __le64 resp_addr; 4052 __le64 src_data_addr; 4053 __le16 data_len; 4054 u8 hdr_cnt; 4055 u8 unused_0[5]; 4056 }; 4057 4058 /* Output (16 bytes) */ 4059 struct hwrm_fw_set_structured_data_output { 4060 __le16 error_code; 4061 __le16 req_type; 4062 __le16 seq_id; 4063 __le16 resp_len; 4064 __le32 unused_0; 4065 u8 unused_1; 4066 u8 unused_2; 4067 u8 unused_3; 4068 u8 valid; 4069 }; 4070 4071 /* hwrm_fw_get_structured_data */ 4072 /* Input (32 bytes) */ 4073 struct hwrm_fw_get_structured_data_input { 4074 __le16 req_type; 4075 __le16 cmpl_ring; 4076 __le16 seq_id; 4077 __le16 target_id; 4078 __le64 resp_addr; 4079 __le64 dest_data_addr; 4080 __le16 data_len; 4081 __le16 structure_id; 4082 __le16 subtype; 4083 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 4084 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 4085 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 4086 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 4087 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 4088 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 4089 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 4090 u8 count; 4091 u8 unused_0; 4092 }; 4093 4094 /* Output (16 bytes) */ 4095 struct hwrm_fw_get_structured_data_output { 4096 __le16 error_code; 4097 __le16 req_type; 4098 __le16 seq_id; 4099 __le16 resp_len; 4100 u8 hdr_cnt; 4101 u8 unused_0; 4102 __le16 unused_1; 4103 u8 unused_2; 4104 u8 unused_3; 4105 u8 unused_4; 4106 u8 valid; 4107 }; 4108 4109 /* hwrm_exec_fwd_resp */ 4110 /* Input (128 bytes) */ 4111 struct hwrm_exec_fwd_resp_input { 4112 __le16 req_type; 4113 __le16 cmpl_ring; 4114 __le16 seq_id; 4115 __le16 target_id; 4116 __le64 resp_addr; 4117 __le32 encap_request[26]; 4118 __le16 encap_resp_target_id; 4119 __le16 unused_0[3]; 4120 }; 4121 4122 /* Output (16 bytes) */ 4123 struct hwrm_exec_fwd_resp_output { 4124 __le16 error_code; 4125 __le16 req_type; 4126 __le16 seq_id; 4127 __le16 resp_len; 4128 __le32 unused_0; 4129 u8 unused_1; 4130 u8 unused_2; 4131 u8 unused_3; 4132 u8 valid; 4133 }; 4134 4135 /* hwrm_reject_fwd_resp */ 4136 /* Input (128 bytes) */ 4137 struct hwrm_reject_fwd_resp_input { 4138 __le16 req_type; 4139 __le16 cmpl_ring; 4140 __le16 seq_id; 4141 __le16 target_id; 4142 __le64 resp_addr; 4143 __le32 encap_request[26]; 4144 __le16 encap_resp_target_id; 4145 __le16 unused_0[3]; 4146 }; 4147 4148 /* Output (16 bytes) */ 4149 struct hwrm_reject_fwd_resp_output { 4150 __le16 error_code; 4151 __le16 req_type; 4152 __le16 seq_id; 4153 __le16 resp_len; 4154 __le32 unused_0; 4155 u8 unused_1; 4156 u8 unused_2; 4157 u8 unused_3; 4158 u8 valid; 4159 }; 4160 4161 /* hwrm_fwd_resp */ 4162 /* Input (40 bytes) */ 4163 struct hwrm_fwd_resp_input { 4164 __le16 req_type; 4165 __le16 cmpl_ring; 4166 __le16 seq_id; 4167 __le16 target_id; 4168 __le64 resp_addr; 4169 __le16 encap_resp_target_id; 4170 __le16 encap_resp_cmpl_ring; 4171 __le16 encap_resp_len; 4172 u8 unused_0; 4173 u8 unused_1; 4174 __le64 encap_resp_addr; 4175 __le32 encap_resp[24]; 4176 }; 4177 4178 /* Output (16 bytes) */ 4179 struct hwrm_fwd_resp_output { 4180 __le16 error_code; 4181 __le16 req_type; 4182 __le16 seq_id; 4183 __le16 resp_len; 4184 __le32 unused_0; 4185 u8 unused_1; 4186 u8 unused_2; 4187 u8 unused_3; 4188 u8 valid; 4189 }; 4190 4191 /* hwrm_fwd_async_event_cmpl */ 4192 /* Input (32 bytes) */ 4193 struct hwrm_fwd_async_event_cmpl_input { 4194 __le16 req_type; 4195 __le16 cmpl_ring; 4196 __le16 seq_id; 4197 __le16 target_id; 4198 __le64 resp_addr; 4199 __le16 encap_async_event_target_id; 4200 u8 unused_0; 4201 u8 unused_1; 4202 u8 unused_2[3]; 4203 u8 unused_3; 4204 __le32 encap_async_event_cmpl[4]; 4205 }; 4206 4207 /* Output (16 bytes) */ 4208 struct hwrm_fwd_async_event_cmpl_output { 4209 __le16 error_code; 4210 __le16 req_type; 4211 __le16 seq_id; 4212 __le16 resp_len; 4213 __le32 unused_0; 4214 u8 unused_1; 4215 u8 unused_2; 4216 u8 unused_3; 4217 u8 valid; 4218 }; 4219 4220 /* hwrm_temp_monitor_query */ 4221 /* Input (16 bytes) */ 4222 struct hwrm_temp_monitor_query_input { 4223 __le16 req_type; 4224 __le16 cmpl_ring; 4225 __le16 seq_id; 4226 __le16 target_id; 4227 __le64 resp_addr; 4228 }; 4229 4230 /* Output (16 bytes) */ 4231 struct hwrm_temp_monitor_query_output { 4232 __le16 error_code; 4233 __le16 req_type; 4234 __le16 seq_id; 4235 __le16 resp_len; 4236 u8 temp; 4237 u8 unused_0; 4238 __le16 unused_1; 4239 u8 unused_2; 4240 u8 unused_3; 4241 u8 unused_4; 4242 u8 valid; 4243 }; 4244 4245 /* hwrm_nvm_read */ 4246 /* Input (40 bytes) */ 4247 struct hwrm_nvm_read_input { 4248 __le16 req_type; 4249 __le16 cmpl_ring; 4250 __le16 seq_id; 4251 __le16 target_id; 4252 __le64 resp_addr; 4253 __le64 host_dest_addr; 4254 __le16 dir_idx; 4255 u8 unused_0; 4256 u8 unused_1; 4257 __le32 offset; 4258 __le32 len; 4259 __le32 unused_2; 4260 }; 4261 4262 /* Output (16 bytes) */ 4263 struct hwrm_nvm_read_output { 4264 __le16 error_code; 4265 __le16 req_type; 4266 __le16 seq_id; 4267 __le16 resp_len; 4268 __le32 unused_0; 4269 u8 unused_1; 4270 u8 unused_2; 4271 u8 unused_3; 4272 u8 valid; 4273 }; 4274 4275 /* hwrm_nvm_raw_dump */ 4276 /* Input (32 bytes) */ 4277 struct hwrm_nvm_raw_dump_input { 4278 __le16 req_type; 4279 __le16 cmpl_ring; 4280 __le16 seq_id; 4281 __le16 target_id; 4282 __le64 resp_addr; 4283 __le64 host_dest_addr; 4284 __le32 offset; 4285 __le32 len; 4286 }; 4287 4288 /* Output (16 bytes) */ 4289 struct hwrm_nvm_raw_dump_output { 4290 __le16 error_code; 4291 __le16 req_type; 4292 __le16 seq_id; 4293 __le16 resp_len; 4294 __le32 unused_0; 4295 u8 unused_1; 4296 u8 unused_2; 4297 u8 unused_3; 4298 u8 valid; 4299 }; 4300 4301 /* hwrm_nvm_get_dir_entries */ 4302 /* Input (24 bytes) */ 4303 struct hwrm_nvm_get_dir_entries_input { 4304 __le16 req_type; 4305 __le16 cmpl_ring; 4306 __le16 seq_id; 4307 __le16 target_id; 4308 __le64 resp_addr; 4309 __le64 host_dest_addr; 4310 }; 4311 4312 /* Output (16 bytes) */ 4313 struct hwrm_nvm_get_dir_entries_output { 4314 __le16 error_code; 4315 __le16 req_type; 4316 __le16 seq_id; 4317 __le16 resp_len; 4318 __le32 unused_0; 4319 u8 unused_1; 4320 u8 unused_2; 4321 u8 unused_3; 4322 u8 valid; 4323 }; 4324 4325 /* hwrm_nvm_get_dir_info */ 4326 /* Input (16 bytes) */ 4327 struct hwrm_nvm_get_dir_info_input { 4328 __le16 req_type; 4329 __le16 cmpl_ring; 4330 __le16 seq_id; 4331 __le16 target_id; 4332 __le64 resp_addr; 4333 }; 4334 4335 /* Output (24 bytes) */ 4336 struct hwrm_nvm_get_dir_info_output { 4337 __le16 error_code; 4338 __le16 req_type; 4339 __le16 seq_id; 4340 __le16 resp_len; 4341 __le32 entries; 4342 __le32 entry_length; 4343 __le32 unused_0; 4344 u8 unused_1; 4345 u8 unused_2; 4346 u8 unused_3; 4347 u8 valid; 4348 }; 4349 4350 /* hwrm_nvm_write */ 4351 /* Input (48 bytes) */ 4352 struct hwrm_nvm_write_input { 4353 __le16 req_type; 4354 __le16 cmpl_ring; 4355 __le16 seq_id; 4356 __le16 target_id; 4357 __le64 resp_addr; 4358 __le64 host_src_addr; 4359 __le16 dir_type; 4360 __le16 dir_ordinal; 4361 __le16 dir_ext; 4362 __le16 dir_attr; 4363 __le32 dir_data_length; 4364 __le16 option; 4365 __le16 flags; 4366 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 4367 __le32 dir_item_length; 4368 __le32 unused_0; 4369 }; 4370 4371 /* Output (16 bytes) */ 4372 struct hwrm_nvm_write_output { 4373 __le16 error_code; 4374 __le16 req_type; 4375 __le16 seq_id; 4376 __le16 resp_len; 4377 __le32 dir_item_length; 4378 __le16 dir_idx; 4379 u8 unused_0; 4380 u8 valid; 4381 }; 4382 4383 /* hwrm_nvm_modify */ 4384 /* Input (40 bytes) */ 4385 struct hwrm_nvm_modify_input { 4386 __le16 req_type; 4387 __le16 cmpl_ring; 4388 __le16 seq_id; 4389 __le16 target_id; 4390 __le64 resp_addr; 4391 __le64 host_src_addr; 4392 __le16 dir_idx; 4393 u8 unused_0; 4394 u8 unused_1; 4395 __le32 offset; 4396 __le32 len; 4397 __le32 unused_2; 4398 }; 4399 4400 /* Output (16 bytes) */ 4401 struct hwrm_nvm_modify_output { 4402 __le16 error_code; 4403 __le16 req_type; 4404 __le16 seq_id; 4405 __le16 resp_len; 4406 __le32 unused_0; 4407 u8 unused_1; 4408 u8 unused_2; 4409 u8 unused_3; 4410 u8 valid; 4411 }; 4412 4413 /* hwrm_nvm_find_dir_entry */ 4414 /* Input (32 bytes) */ 4415 struct hwrm_nvm_find_dir_entry_input { 4416 __le16 req_type; 4417 __le16 cmpl_ring; 4418 __le16 seq_id; 4419 __le16 target_id; 4420 __le64 resp_addr; 4421 __le32 enables; 4422 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 4423 __le16 dir_idx; 4424 __le16 dir_type; 4425 __le16 dir_ordinal; 4426 __le16 dir_ext; 4427 u8 opt_ordinal; 4428 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 4429 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 4430 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 4431 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 4432 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 4433 u8 unused_1[3]; 4434 }; 4435 4436 /* Output (32 bytes) */ 4437 struct hwrm_nvm_find_dir_entry_output { 4438 __le16 error_code; 4439 __le16 req_type; 4440 __le16 seq_id; 4441 __le16 resp_len; 4442 __le32 dir_item_length; 4443 __le32 dir_data_length; 4444 __le32 fw_ver; 4445 __le16 dir_ordinal; 4446 __le16 dir_idx; 4447 __le32 unused_0; 4448 u8 unused_1; 4449 u8 unused_2; 4450 u8 unused_3; 4451 u8 valid; 4452 }; 4453 4454 /* hwrm_nvm_erase_dir_entry */ 4455 /* Input (24 bytes) */ 4456 struct hwrm_nvm_erase_dir_entry_input { 4457 __le16 req_type; 4458 __le16 cmpl_ring; 4459 __le16 seq_id; 4460 __le16 target_id; 4461 __le64 resp_addr; 4462 __le16 dir_idx; 4463 __le16 unused_0[3]; 4464 }; 4465 4466 /* Output (16 bytes) */ 4467 struct hwrm_nvm_erase_dir_entry_output { 4468 __le16 error_code; 4469 __le16 req_type; 4470 __le16 seq_id; 4471 __le16 resp_len; 4472 __le32 unused_0; 4473 u8 unused_1; 4474 u8 unused_2; 4475 u8 unused_3; 4476 u8 valid; 4477 }; 4478 4479 /* hwrm_nvm_get_dev_info */ 4480 /* Input (16 bytes) */ 4481 struct hwrm_nvm_get_dev_info_input { 4482 __le16 req_type; 4483 __le16 cmpl_ring; 4484 __le16 seq_id; 4485 __le16 target_id; 4486 __le64 resp_addr; 4487 }; 4488 4489 /* Output (32 bytes) */ 4490 struct hwrm_nvm_get_dev_info_output { 4491 __le16 error_code; 4492 __le16 req_type; 4493 __le16 seq_id; 4494 __le16 resp_len; 4495 __le16 manufacturer_id; 4496 __le16 device_id; 4497 __le32 sector_size; 4498 __le32 nvram_size; 4499 __le32 reserved_size; 4500 __le32 available_size; 4501 u8 unused_0; 4502 u8 unused_1; 4503 u8 unused_2; 4504 u8 valid; 4505 }; 4506 4507 /* hwrm_nvm_mod_dir_entry */ 4508 /* Input (32 bytes) */ 4509 struct hwrm_nvm_mod_dir_entry_input { 4510 __le16 req_type; 4511 __le16 cmpl_ring; 4512 __le16 seq_id; 4513 __le16 target_id; 4514 __le64 resp_addr; 4515 __le32 enables; 4516 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 4517 __le16 dir_idx; 4518 __le16 dir_ordinal; 4519 __le16 dir_ext; 4520 __le16 dir_attr; 4521 __le32 checksum; 4522 }; 4523 4524 /* Output (16 bytes) */ 4525 struct hwrm_nvm_mod_dir_entry_output { 4526 __le16 error_code; 4527 __le16 req_type; 4528 __le16 seq_id; 4529 __le16 resp_len; 4530 __le32 unused_0; 4531 u8 unused_1; 4532 u8 unused_2; 4533 u8 unused_3; 4534 u8 valid; 4535 }; 4536 4537 /* hwrm_nvm_verify_update */ 4538 /* Input (24 bytes) */ 4539 struct hwrm_nvm_verify_update_input { 4540 __le16 req_type; 4541 __le16 cmpl_ring; 4542 __le16 seq_id; 4543 __le16 target_id; 4544 __le64 resp_addr; 4545 __le16 dir_type; 4546 __le16 dir_ordinal; 4547 __le16 dir_ext; 4548 __le16 unused_0; 4549 }; 4550 4551 /* Output (16 bytes) */ 4552 struct hwrm_nvm_verify_update_output { 4553 __le16 error_code; 4554 __le16 req_type; 4555 __le16 seq_id; 4556 __le16 resp_len; 4557 __le32 unused_0; 4558 u8 unused_1; 4559 u8 unused_2; 4560 u8 unused_3; 4561 u8 valid; 4562 }; 4563 4564 /* hwrm_nvm_install_update */ 4565 /* Input (24 bytes) */ 4566 struct hwrm_nvm_install_update_input { 4567 __le16 req_type; 4568 __le16 cmpl_ring; 4569 __le16 seq_id; 4570 __le16 target_id; 4571 __le64 resp_addr; 4572 __le32 install_type; 4573 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 4574 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 4575 __le32 unused_0; 4576 }; 4577 4578 /* Output (24 bytes) */ 4579 struct hwrm_nvm_install_update_output { 4580 __le16 error_code; 4581 __le16 req_type; 4582 __le16 seq_id; 4583 __le16 resp_len; 4584 __le64 installed_items; 4585 u8 result; 4586 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 4587 u8 problem_item; 4588 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 4589 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 4590 u8 reset_required; 4591 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 4592 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 4593 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 4594 u8 unused_0; 4595 u8 unused_1; 4596 u8 unused_2; 4597 u8 unused_3; 4598 u8 valid; 4599 }; 4600 4601 #endif 4602