1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2021 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 107 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 108 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 109 #define HWRM_FUNC_VF_CFG 0xfUL 110 #define HWRM_RESERVED1 0x10UL 111 #define HWRM_FUNC_RESET 0x11UL 112 #define HWRM_FUNC_GETFID 0x12UL 113 #define HWRM_FUNC_VF_ALLOC 0x13UL 114 #define HWRM_FUNC_VF_FREE 0x14UL 115 #define HWRM_FUNC_QCAPS 0x15UL 116 #define HWRM_FUNC_QCFG 0x16UL 117 #define HWRM_FUNC_CFG 0x17UL 118 #define HWRM_FUNC_QSTATS 0x18UL 119 #define HWRM_FUNC_CLR_STATS 0x19UL 120 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 121 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 122 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 123 #define HWRM_FUNC_DRV_RGTR 0x1dUL 124 #define HWRM_FUNC_DRV_QVER 0x1eUL 125 #define HWRM_FUNC_BUF_RGTR 0x1fUL 126 #define HWRM_PORT_PHY_CFG 0x20UL 127 #define HWRM_PORT_MAC_CFG 0x21UL 128 #define HWRM_PORT_TS_QUERY 0x22UL 129 #define HWRM_PORT_QSTATS 0x23UL 130 #define HWRM_PORT_LPBK_QSTATS 0x24UL 131 #define HWRM_PORT_CLR_STATS 0x25UL 132 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 133 #define HWRM_PORT_PHY_QCFG 0x27UL 134 #define HWRM_PORT_MAC_QCFG 0x28UL 135 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 136 #define HWRM_PORT_PHY_QCAPS 0x2aUL 137 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 138 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 139 #define HWRM_PORT_LED_CFG 0x2dUL 140 #define HWRM_PORT_LED_QCFG 0x2eUL 141 #define HWRM_PORT_LED_QCAPS 0x2fUL 142 #define HWRM_QUEUE_QPORTCFG 0x30UL 143 #define HWRM_QUEUE_QCFG 0x31UL 144 #define HWRM_QUEUE_CFG 0x32UL 145 #define HWRM_FUNC_VLAN_CFG 0x33UL 146 #define HWRM_FUNC_VLAN_QCFG 0x34UL 147 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 148 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 149 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 150 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 151 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 152 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 153 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 154 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 155 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 156 #define HWRM_VNIC_ALLOC 0x40UL 157 #define HWRM_VNIC_FREE 0x41UL 158 #define HWRM_VNIC_CFG 0x42UL 159 #define HWRM_VNIC_QCFG 0x43UL 160 #define HWRM_VNIC_TPA_CFG 0x44UL 161 #define HWRM_VNIC_TPA_QCFG 0x45UL 162 #define HWRM_VNIC_RSS_CFG 0x46UL 163 #define HWRM_VNIC_RSS_QCFG 0x47UL 164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166 #define HWRM_VNIC_QCAPS 0x4aUL 167 #define HWRM_VNIC_UPDATE 0x4bUL 168 #define HWRM_RING_ALLOC 0x50UL 169 #define HWRM_RING_FREE 0x51UL 170 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 171 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 172 #define HWRM_RING_AGGINT_QCAPS 0x54UL 173 #define HWRM_RING_SCHQ_ALLOC 0x55UL 174 #define HWRM_RING_SCHQ_CFG 0x56UL 175 #define HWRM_RING_SCHQ_FREE 0x57UL 176 #define HWRM_RING_RESET 0x5eUL 177 #define HWRM_RING_GRP_ALLOC 0x60UL 178 #define HWRM_RING_GRP_FREE 0x61UL 179 #define HWRM_RING_CFG 0x62UL 180 #define HWRM_RING_QCFG 0x63UL 181 #define HWRM_RESERVED5 0x64UL 182 #define HWRM_RESERVED6 0x65UL 183 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 185 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 186 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 187 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 188 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 189 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 190 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 191 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 192 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 193 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 194 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 195 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 196 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 197 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 198 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 199 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 200 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 201 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 202 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 203 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 204 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 205 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 206 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 207 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 208 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 209 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 210 #define HWRM_STAT_CTX_ALLOC 0xb0UL 211 #define HWRM_STAT_CTX_FREE 0xb1UL 212 #define HWRM_STAT_CTX_QUERY 0xb2UL 213 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 214 #define HWRM_PORT_QSTATS_EXT 0xb4UL 215 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 216 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 217 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 218 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 219 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 220 #define HWRM_RESERVED7 0xbaUL 221 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 222 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 223 #define HWRM_PORT_ECN_QSTATS 0xbdUL 224 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 225 #define HWRM_FW_LIVEPATCH 0xbfUL 226 #define HWRM_FW_RESET 0xc0UL 227 #define HWRM_FW_QSTATUS 0xc1UL 228 #define HWRM_FW_HEALTH_CHECK 0xc2UL 229 #define HWRM_FW_SYNC 0xc3UL 230 #define HWRM_FW_STATE_QCAPS 0xc4UL 231 #define HWRM_FW_STATE_QUIESCE 0xc5UL 232 #define HWRM_FW_STATE_BACKUP 0xc6UL 233 #define HWRM_FW_STATE_RESTORE 0xc7UL 234 #define HWRM_FW_SET_TIME 0xc8UL 235 #define HWRM_FW_GET_TIME 0xc9UL 236 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 237 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 238 #define HWRM_FW_IPC_MAILBOX 0xccUL 239 #define HWRM_FW_ECN_CFG 0xcdUL 240 #define HWRM_FW_ECN_QCFG 0xceUL 241 #define HWRM_FW_SECURE_CFG 0xcfUL 242 #define HWRM_EXEC_FWD_RESP 0xd0UL 243 #define HWRM_REJECT_FWD_RESP 0xd1UL 244 #define HWRM_FWD_RESP 0xd2UL 245 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 246 #define HWRM_OEM_CMD 0xd4UL 247 #define HWRM_PORT_PRBS_TEST 0xd5UL 248 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 249 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 250 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 251 #define HWRM_PORT_DSC_DUMP 0xd9UL 252 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 253 #define HWRM_REG_POWER_QUERY 0xe1UL 254 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 255 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 256 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 257 #define HWRM_WOL_FILTER_FREE 0xf1UL 258 #define HWRM_WOL_FILTER_QCFG 0xf2UL 259 #define HWRM_WOL_REASON_QCFG 0xf3UL 260 #define HWRM_CFA_METER_QCAPS 0xf4UL 261 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 262 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 263 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 264 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 265 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 266 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 267 #define HWRM_CFA_VFR_ALLOC 0xfdUL 268 #define HWRM_CFA_VFR_FREE 0xfeUL 269 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 270 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 271 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 272 #define HWRM_CFA_FLOW_ALLOC 0x103UL 273 #define HWRM_CFA_FLOW_FREE 0x104UL 274 #define HWRM_CFA_FLOW_FLUSH 0x105UL 275 #define HWRM_CFA_FLOW_STATS 0x106UL 276 #define HWRM_CFA_FLOW_INFO 0x107UL 277 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 278 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 279 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 280 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 281 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 282 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 283 #define HWRM_CFA_PAIR_FREE 0x10eUL 284 #define HWRM_CFA_PAIR_INFO 0x10fUL 285 #define HWRM_FW_IPC_MSG 0x110UL 286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 287 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 288 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 289 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 290 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 291 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 292 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 293 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 294 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 295 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 296 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 297 #define HWRM_CFA_COUNTER_CFG 0x11cUL 298 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 299 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 300 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 301 #define HWRM_CFA_EEM_QCAPS 0x120UL 302 #define HWRM_CFA_EEM_CFG 0x121UL 303 #define HWRM_CFA_EEM_QCFG 0x122UL 304 #define HWRM_CFA_EEM_OP 0x123UL 305 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 306 #define HWRM_CFA_TFLIB 0x125UL 307 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 308 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 309 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 310 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 311 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 312 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 313 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 314 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 315 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 316 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 317 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 318 #define HWRM_ENGINE_QG_QUERY 0x13dUL 319 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 320 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 321 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 322 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 323 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 324 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 325 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 326 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 327 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 328 #define HWRM_ENGINE_SG_QUERY 0x147UL 329 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 330 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 331 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 332 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 333 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 334 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 335 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 336 #define HWRM_ENGINE_STATS_QUERY 0x157UL 337 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 338 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 339 #define HWRM_ENGINE_RQ_FREE 0x15fUL 340 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 341 #define HWRM_ENGINE_CQ_FREE 0x161UL 342 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 343 #define HWRM_ENGINE_NQ_FREE 0x163UL 344 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 345 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 346 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 347 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 348 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 349 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 350 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 351 #define HWRM_FUNC_VF_BW_CFG 0x195UL 352 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 353 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 354 #define HWRM_FUNC_QSTATS_EXT 0x198UL 355 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 356 #define HWRM_FUNC_SPD_CFG 0x19aUL 357 #define HWRM_FUNC_SPD_QCFG 0x19bUL 358 #define HWRM_SELFTEST_QLIST 0x200UL 359 #define HWRM_SELFTEST_EXEC 0x201UL 360 #define HWRM_SELFTEST_IRQ 0x202UL 361 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 362 #define HWRM_PCIE_QSTATS 0x204UL 363 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 364 #define HWRM_MFG_TIMERS_QUERY 0x206UL 365 #define HWRM_MFG_OTP_CFG 0x207UL 366 #define HWRM_MFG_OTP_QCFG 0x208UL 367 #define HWRM_MFG_HDMA_TEST 0x209UL 368 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 369 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 370 #define HWRM_MFG_SOC_IMAGE 0x20cUL 371 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 372 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 373 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 374 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 375 #define HWRM_TF 0x2bcUL 376 #define HWRM_TF_VERSION_GET 0x2bdUL 377 #define HWRM_TF_SESSION_OPEN 0x2c6UL 378 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 379 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 380 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 381 #define HWRM_TF_SESSION_CLOSE 0x2caUL 382 #define HWRM_TF_SESSION_QCFG 0x2cbUL 383 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 384 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 385 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 386 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 387 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 388 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 389 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 390 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 391 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 392 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 393 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 394 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 395 #define HWRM_TF_EXT_EM_OP 0x2e7UL 396 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 397 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 398 #define HWRM_TF_EM_INSERT 0x2eaUL 399 #define HWRM_TF_EM_DELETE 0x2ebUL 400 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 401 #define HWRM_TF_TCAM_SET 0x2f8UL 402 #define HWRM_TF_TCAM_GET 0x2f9UL 403 #define HWRM_TF_TCAM_MOVE 0x2faUL 404 #define HWRM_TF_TCAM_FREE 0x2fbUL 405 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 406 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 407 #define HWRM_TF_IF_TBL_SET 0x2feUL 408 #define HWRM_TF_IF_TBL_GET 0x2ffUL 409 #define HWRM_SV 0x400UL 410 #define HWRM_DBG_READ_DIRECT 0xff10UL 411 #define HWRM_DBG_READ_INDIRECT 0xff11UL 412 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 413 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 414 #define HWRM_DBG_DUMP 0xff14UL 415 #define HWRM_DBG_ERASE_NVM 0xff15UL 416 #define HWRM_DBG_CFG 0xff16UL 417 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 418 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 419 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 420 #define HWRM_DBG_FW_CLI 0xff1aUL 421 #define HWRM_DBG_I2C_CMD 0xff1bUL 422 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 423 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 424 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 425 #define HWRM_DBG_DRV_TRACE 0xff1fUL 426 #define HWRM_DBG_QCAPS 0xff20UL 427 #define HWRM_DBG_QCFG 0xff21UL 428 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 429 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 430 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 431 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 432 #define HWRM_NVM_FLUSH 0xfff0UL 433 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 434 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 435 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 436 #define HWRM_NVM_MODIFY 0xfff4UL 437 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 438 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 439 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 440 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 441 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 442 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 443 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 444 #define HWRM_NVM_RAW_DUMP 0xfffcUL 445 #define HWRM_NVM_READ 0xfffdUL 446 #define HWRM_NVM_WRITE 0xfffeUL 447 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 448 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 449 __le16 unused_0[3]; 450 }; 451 452 /* ret_codes (size:64b/8B) */ 453 struct ret_codes { 454 __le16 error_code; 455 #define HWRM_ERR_CODE_SUCCESS 0x0UL 456 #define HWRM_ERR_CODE_FAIL 0x1UL 457 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 458 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 459 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 460 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 461 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 462 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 463 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 464 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 465 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 466 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 467 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 468 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 469 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 470 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 471 #define HWRM_ERR_CODE_BUSY 0x10UL 472 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 473 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 474 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 475 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 476 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 477 __le16 unused_0[3]; 478 }; 479 480 /* hwrm_err_output (size:128b/16B) */ 481 struct hwrm_err_output { 482 __le16 error_code; 483 __le16 req_type; 484 __le16 seq_id; 485 __le16 resp_len; 486 __le32 opaque_0; 487 __le16 opaque_1; 488 u8 cmd_err; 489 u8 valid; 490 }; 491 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 492 #define HWRM_MAX_REQ_LEN 128 493 #define HWRM_MAX_RESP_LEN 704 494 #define HW_HASH_INDEX_SIZE 0x80 495 #define HW_HASH_KEY_SIZE 40 496 #define HWRM_RESP_VALID_KEY 1 497 #define HWRM_TARGET_ID_BONO 0xFFF8 498 #define HWRM_TARGET_ID_KONG 0xFFF9 499 #define HWRM_TARGET_ID_APE 0xFFFA 500 #define HWRM_TARGET_ID_TOOLS 0xFFFD 501 #define HWRM_VERSION_MAJOR 1 502 #define HWRM_VERSION_MINOR 10 503 #define HWRM_VERSION_UPDATE 2 504 #define HWRM_VERSION_RSVD 11 505 #define HWRM_VERSION_STR "1.10.2.11" 506 507 /* hwrm_ver_get_input (size:192b/24B) */ 508 struct hwrm_ver_get_input { 509 __le16 req_type; 510 __le16 cmpl_ring; 511 __le16 seq_id; 512 __le16 target_id; 513 __le64 resp_addr; 514 u8 hwrm_intf_maj; 515 u8 hwrm_intf_min; 516 u8 hwrm_intf_upd; 517 u8 unused_0[5]; 518 }; 519 520 /* hwrm_ver_get_output (size:1408b/176B) */ 521 struct hwrm_ver_get_output { 522 __le16 error_code; 523 __le16 req_type; 524 __le16 seq_id; 525 __le16 resp_len; 526 u8 hwrm_intf_maj_8b; 527 u8 hwrm_intf_min_8b; 528 u8 hwrm_intf_upd_8b; 529 u8 hwrm_intf_rsvd_8b; 530 u8 hwrm_fw_maj_8b; 531 u8 hwrm_fw_min_8b; 532 u8 hwrm_fw_bld_8b; 533 u8 hwrm_fw_rsvd_8b; 534 u8 mgmt_fw_maj_8b; 535 u8 mgmt_fw_min_8b; 536 u8 mgmt_fw_bld_8b; 537 u8 mgmt_fw_rsvd_8b; 538 u8 netctrl_fw_maj_8b; 539 u8 netctrl_fw_min_8b; 540 u8 netctrl_fw_bld_8b; 541 u8 netctrl_fw_rsvd_8b; 542 __le32 dev_caps_cfg; 543 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 544 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 545 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 546 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 547 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 548 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 549 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 550 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 551 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 552 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 553 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 554 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 555 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 556 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 557 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 558 u8 roce_fw_maj_8b; 559 u8 roce_fw_min_8b; 560 u8 roce_fw_bld_8b; 561 u8 roce_fw_rsvd_8b; 562 char hwrm_fw_name[16]; 563 char mgmt_fw_name[16]; 564 char netctrl_fw_name[16]; 565 char active_pkg_name[16]; 566 char roce_fw_name[16]; 567 __le16 chip_num; 568 u8 chip_rev; 569 u8 chip_metal; 570 u8 chip_bond_id; 571 u8 chip_platform_type; 572 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 573 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 574 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 575 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 576 __le16 max_req_win_len; 577 __le16 max_resp_len; 578 __le16 def_req_timeout; 579 u8 flags; 580 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 581 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 582 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 583 u8 unused_0[2]; 584 u8 always_1; 585 __le16 hwrm_intf_major; 586 __le16 hwrm_intf_minor; 587 __le16 hwrm_intf_build; 588 __le16 hwrm_intf_patch; 589 __le16 hwrm_fw_major; 590 __le16 hwrm_fw_minor; 591 __le16 hwrm_fw_build; 592 __le16 hwrm_fw_patch; 593 __le16 mgmt_fw_major; 594 __le16 mgmt_fw_minor; 595 __le16 mgmt_fw_build; 596 __le16 mgmt_fw_patch; 597 __le16 netctrl_fw_major; 598 __le16 netctrl_fw_minor; 599 __le16 netctrl_fw_build; 600 __le16 netctrl_fw_patch; 601 __le16 roce_fw_major; 602 __le16 roce_fw_minor; 603 __le16 roce_fw_build; 604 __le16 roce_fw_patch; 605 __le16 max_ext_req_len; 606 u8 unused_1[5]; 607 u8 valid; 608 }; 609 610 /* eject_cmpl (size:128b/16B) */ 611 struct eject_cmpl { 612 __le16 type; 613 #define EJECT_CMPL_TYPE_MASK 0x3fUL 614 #define EJECT_CMPL_TYPE_SFT 0 615 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 616 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 617 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 618 #define EJECT_CMPL_FLAGS_SFT 6 619 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 620 __le16 len; 621 __le32 opaque; 622 __le16 v; 623 #define EJECT_CMPL_V 0x1UL 624 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 625 #define EJECT_CMPL_ERRORS_SFT 1 626 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 627 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 628 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 629 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 630 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 631 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 632 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 633 __le16 reserved16; 634 __le32 unused_2; 635 }; 636 637 /* hwrm_cmpl (size:128b/16B) */ 638 struct hwrm_cmpl { 639 __le16 type; 640 #define CMPL_TYPE_MASK 0x3fUL 641 #define CMPL_TYPE_SFT 0 642 #define CMPL_TYPE_HWRM_DONE 0x20UL 643 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 644 __le16 sequence_id; 645 __le32 unused_1; 646 __le32 v; 647 #define CMPL_V 0x1UL 648 __le32 unused_3; 649 }; 650 651 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 652 struct hwrm_fwd_req_cmpl { 653 __le16 req_len_type; 654 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 655 #define FWD_REQ_CMPL_TYPE_SFT 0 656 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 657 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 658 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 659 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 660 __le16 source_id; 661 __le32 unused0; 662 __le32 req_buf_addr_v[2]; 663 #define FWD_REQ_CMPL_V 0x1UL 664 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 665 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 666 }; 667 668 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 669 struct hwrm_fwd_resp_cmpl { 670 __le16 type; 671 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 672 #define FWD_RESP_CMPL_TYPE_SFT 0 673 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 674 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 675 __le16 source_id; 676 __le16 resp_len; 677 __le16 unused_1; 678 __le32 resp_buf_addr_v[2]; 679 #define FWD_RESP_CMPL_V 0x1UL 680 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 681 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 682 }; 683 684 /* hwrm_async_event_cmpl (size:128b/16B) */ 685 struct hwrm_async_event_cmpl { 686 __le16 type; 687 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 688 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 689 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 690 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 691 __le16 event_id; 692 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 693 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 694 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 695 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 696 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 697 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 698 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 699 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 700 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 701 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 702 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 703 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 704 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 705 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 706 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 707 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 708 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 709 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 710 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 711 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 712 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 713 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 714 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 715 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 716 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 717 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 718 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 719 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 720 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 721 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 722 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 723 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 724 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 725 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 726 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x42UL 727 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 728 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 729 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 730 __le32 event_data2; 731 u8 opaque_v; 732 #define ASYNC_EVENT_CMPL_V 0x1UL 733 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 734 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 735 u8 timestamp_lo; 736 __le16 timestamp_hi; 737 __le32 event_data1; 738 }; 739 740 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 741 struct hwrm_async_event_cmpl_link_status_change { 742 __le16 type; 743 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 744 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 745 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 746 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 747 __le16 event_id; 748 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 749 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 750 __le32 event_data2; 751 u8 opaque_v; 752 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 753 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 754 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 755 u8 timestamp_lo; 756 __le16 timestamp_hi; 757 __le32 event_data1; 758 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 759 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 760 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 761 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 762 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 763 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 764 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 765 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 766 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 767 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 768 }; 769 770 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 771 struct hwrm_async_event_cmpl_port_conn_not_allowed { 772 __le16 type; 773 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 774 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 775 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 776 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 777 __le16 event_id; 778 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 779 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 780 __le32 event_data2; 781 u8 opaque_v; 782 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 783 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 784 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 785 u8 timestamp_lo; 786 __le16 timestamp_hi; 787 __le32 event_data1; 788 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 789 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 790 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 791 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 792 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 793 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 794 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 795 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 796 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 797 }; 798 799 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 800 struct hwrm_async_event_cmpl_link_speed_cfg_change { 801 __le16 type; 802 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 803 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 804 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 805 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 806 __le16 event_id; 807 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 808 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 809 __le32 event_data2; 810 u8 opaque_v; 811 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 812 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 813 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 814 u8 timestamp_lo; 815 __le16 timestamp_hi; 816 __le32 event_data1; 817 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 818 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 819 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 820 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 821 }; 822 823 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 824 struct hwrm_async_event_cmpl_reset_notify { 825 __le16 type; 826 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 827 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 828 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 829 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 830 __le16 event_id; 831 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 832 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 833 __le32 event_data2; 834 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 835 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 836 u8 opaque_v; 837 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 838 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 839 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 840 u8 timestamp_lo; 841 __le16 timestamp_hi; 842 __le32 event_data1; 843 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 844 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 845 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 846 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 847 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 848 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 849 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 850 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 851 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 852 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 853 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 854 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET 855 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 856 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 857 }; 858 859 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 860 struct hwrm_async_event_cmpl_error_recovery { 861 __le16 type; 862 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 863 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 864 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 865 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 866 __le16 event_id; 867 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 868 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 869 __le32 event_data2; 870 u8 opaque_v; 871 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 872 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 873 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 874 u8 timestamp_lo; 875 __le16 timestamp_hi; 876 __le32 event_data1; 877 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 878 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 879 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 880 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 881 }; 882 883 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 884 struct hwrm_async_event_cmpl_ring_monitor_msg { 885 __le16 type; 886 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 887 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 888 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 889 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 890 __le16 event_id; 891 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 892 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 893 __le32 event_data2; 894 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 895 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 896 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 897 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 898 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 899 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 900 u8 opaque_v; 901 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 902 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 903 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 904 u8 timestamp_lo; 905 __le16 timestamp_hi; 906 __le32 event_data1; 907 }; 908 909 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 910 struct hwrm_async_event_cmpl_vf_cfg_change { 911 __le16 type; 912 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 913 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 914 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 915 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 916 __le16 event_id; 917 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 918 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 919 __le32 event_data2; 920 u8 opaque_v; 921 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 922 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 923 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 924 u8 timestamp_lo; 925 __le16 timestamp_hi; 926 __le32 event_data1; 927 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 928 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 929 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 930 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 931 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 932 }; 933 934 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 935 struct hwrm_async_event_cmpl_default_vnic_change { 936 __le16 type; 937 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 938 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 939 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 940 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 941 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 942 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 943 __le16 event_id; 944 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 945 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 946 __le32 event_data2; 947 u8 opaque_v; 948 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 949 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 950 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 951 u8 timestamp_lo; 952 __le16 timestamp_hi; 953 __le32 event_data1; 954 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 955 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 956 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 957 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 958 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 959 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 960 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 961 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 962 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 963 }; 964 965 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 966 struct hwrm_async_event_cmpl_hw_flow_aged { 967 __le16 type; 968 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 969 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 970 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 971 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 972 __le16 event_id; 973 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 974 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 975 __le32 event_data2; 976 u8 opaque_v; 977 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 978 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 979 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 980 u8 timestamp_lo; 981 __le16 timestamp_hi; 982 __le32 event_data1; 983 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 984 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 985 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 986 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 987 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 988 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 989 }; 990 991 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 992 struct hwrm_async_event_cmpl_eem_cache_flush_req { 993 __le16 type; 994 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 995 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 996 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 997 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 998 __le16 event_id; 999 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1000 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1001 __le32 event_data2; 1002 u8 opaque_v; 1003 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1004 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1005 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1006 u8 timestamp_lo; 1007 __le16 timestamp_hi; 1008 __le32 event_data1; 1009 }; 1010 1011 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1012 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1013 __le16 type; 1014 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1015 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1016 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1017 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1018 __le16 event_id; 1019 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1020 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1021 __le32 event_data2; 1022 u8 opaque_v; 1023 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1024 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1025 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1026 u8 timestamp_lo; 1027 __le16 timestamp_hi; 1028 __le32 event_data1; 1029 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1030 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1031 }; 1032 1033 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1034 struct hwrm_async_event_cmpl_deferred_response { 1035 __le16 type; 1036 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1037 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1038 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1039 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1040 __le16 event_id; 1041 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1042 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1043 __le32 event_data2; 1044 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1045 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1046 u8 opaque_v; 1047 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1048 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1049 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1050 u8 timestamp_lo; 1051 __le16 timestamp_hi; 1052 __le32 event_data1; 1053 }; 1054 1055 /* hwrm_func_reset_input (size:192b/24B) */ 1056 struct hwrm_func_reset_input { 1057 __le16 req_type; 1058 __le16 cmpl_ring; 1059 __le16 seq_id; 1060 __le16 target_id; 1061 __le64 resp_addr; 1062 __le32 enables; 1063 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1064 __le16 vf_id; 1065 u8 func_reset_level; 1066 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1067 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1068 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1069 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1070 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1071 u8 unused_0; 1072 }; 1073 1074 /* hwrm_func_reset_output (size:128b/16B) */ 1075 struct hwrm_func_reset_output { 1076 __le16 error_code; 1077 __le16 req_type; 1078 __le16 seq_id; 1079 __le16 resp_len; 1080 u8 unused_0[7]; 1081 u8 valid; 1082 }; 1083 1084 /* hwrm_func_getfid_input (size:192b/24B) */ 1085 struct hwrm_func_getfid_input { 1086 __le16 req_type; 1087 __le16 cmpl_ring; 1088 __le16 seq_id; 1089 __le16 target_id; 1090 __le64 resp_addr; 1091 __le32 enables; 1092 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1093 __le16 pci_id; 1094 u8 unused_0[2]; 1095 }; 1096 1097 /* hwrm_func_getfid_output (size:128b/16B) */ 1098 struct hwrm_func_getfid_output { 1099 __le16 error_code; 1100 __le16 req_type; 1101 __le16 seq_id; 1102 __le16 resp_len; 1103 __le16 fid; 1104 u8 unused_0[5]; 1105 u8 valid; 1106 }; 1107 1108 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1109 struct hwrm_func_vf_alloc_input { 1110 __le16 req_type; 1111 __le16 cmpl_ring; 1112 __le16 seq_id; 1113 __le16 target_id; 1114 __le64 resp_addr; 1115 __le32 enables; 1116 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1117 __le16 first_vf_id; 1118 __le16 num_vfs; 1119 }; 1120 1121 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1122 struct hwrm_func_vf_alloc_output { 1123 __le16 error_code; 1124 __le16 req_type; 1125 __le16 seq_id; 1126 __le16 resp_len; 1127 __le16 first_vf_id; 1128 u8 unused_0[5]; 1129 u8 valid; 1130 }; 1131 1132 /* hwrm_func_vf_free_input (size:192b/24B) */ 1133 struct hwrm_func_vf_free_input { 1134 __le16 req_type; 1135 __le16 cmpl_ring; 1136 __le16 seq_id; 1137 __le16 target_id; 1138 __le64 resp_addr; 1139 __le32 enables; 1140 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1141 __le16 first_vf_id; 1142 __le16 num_vfs; 1143 }; 1144 1145 /* hwrm_func_vf_free_output (size:128b/16B) */ 1146 struct hwrm_func_vf_free_output { 1147 __le16 error_code; 1148 __le16 req_type; 1149 __le16 seq_id; 1150 __le16 resp_len; 1151 u8 unused_0[7]; 1152 u8 valid; 1153 }; 1154 1155 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1156 struct hwrm_func_vf_cfg_input { 1157 __le16 req_type; 1158 __le16 cmpl_ring; 1159 __le16 seq_id; 1160 __le16 target_id; 1161 __le64 resp_addr; 1162 __le32 enables; 1163 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1164 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1165 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1166 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1167 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1168 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1169 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1170 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1171 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1172 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1173 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1174 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1175 __le16 mtu; 1176 __le16 guest_vlan; 1177 __le16 async_event_cr; 1178 u8 dflt_mac_addr[6]; 1179 __le32 flags; 1180 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1181 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1182 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1183 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1184 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1185 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1186 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1187 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1188 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1189 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1190 __le16 num_rsscos_ctxs; 1191 __le16 num_cmpl_rings; 1192 __le16 num_tx_rings; 1193 __le16 num_rx_rings; 1194 __le16 num_l2_ctxs; 1195 __le16 num_vnics; 1196 __le16 num_stat_ctxs; 1197 __le16 num_hw_ring_grps; 1198 u8 unused_0[4]; 1199 }; 1200 1201 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1202 struct hwrm_func_vf_cfg_output { 1203 __le16 error_code; 1204 __le16 req_type; 1205 __le16 seq_id; 1206 __le16 resp_len; 1207 u8 unused_0[7]; 1208 u8 valid; 1209 }; 1210 1211 /* hwrm_func_qcaps_input (size:192b/24B) */ 1212 struct hwrm_func_qcaps_input { 1213 __le16 req_type; 1214 __le16 cmpl_ring; 1215 __le16 seq_id; 1216 __le16 target_id; 1217 __le64 resp_addr; 1218 __le16 fid; 1219 u8 unused_0[6]; 1220 }; 1221 1222 /* hwrm_func_qcaps_output (size:704b/88B) */ 1223 struct hwrm_func_qcaps_output { 1224 __le16 error_code; 1225 __le16 req_type; 1226 __le16 seq_id; 1227 __le16 resp_len; 1228 __le16 fid; 1229 __le16 port_id; 1230 __le32 flags; 1231 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1232 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1233 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1234 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1235 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1236 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1237 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1238 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1239 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1240 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1241 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1242 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1243 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1244 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1245 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1246 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1247 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1248 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1249 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1250 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1251 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1252 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1253 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1254 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1255 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1256 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1257 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1258 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1259 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1260 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1261 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1262 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1263 u8 mac_address[6]; 1264 __le16 max_rsscos_ctx; 1265 __le16 max_cmpl_rings; 1266 __le16 max_tx_rings; 1267 __le16 max_rx_rings; 1268 __le16 max_l2_ctxs; 1269 __le16 max_vnics; 1270 __le16 first_vf_id; 1271 __le16 max_vfs; 1272 __le16 max_stat_ctx; 1273 __le32 max_encap_records; 1274 __le32 max_decap_records; 1275 __le32 max_tx_em_flows; 1276 __le32 max_tx_wm_flows; 1277 __le32 max_rx_em_flows; 1278 __le32 max_rx_wm_flows; 1279 __le32 max_mcast_filters; 1280 __le32 max_flow_id; 1281 __le32 max_hw_ring_grps; 1282 __le16 max_sp_tx_rings; 1283 u8 unused_0[2]; 1284 __le32 flags_ext; 1285 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1286 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1287 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1288 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1289 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1290 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1291 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1292 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1293 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1294 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1295 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1296 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1297 u8 max_schqs; 1298 u8 mpc_chnls_cap; 1299 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1300 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1301 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1302 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1303 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1304 u8 unused_1; 1305 u8 valid; 1306 }; 1307 1308 /* hwrm_func_qcfg_input (size:192b/24B) */ 1309 struct hwrm_func_qcfg_input { 1310 __le16 req_type; 1311 __le16 cmpl_ring; 1312 __le16 seq_id; 1313 __le16 target_id; 1314 __le64 resp_addr; 1315 __le16 fid; 1316 u8 unused_0[6]; 1317 }; 1318 1319 /* hwrm_func_qcfg_output (size:768b/96B) */ 1320 struct hwrm_func_qcfg_output { 1321 __le16 error_code; 1322 __le16 req_type; 1323 __le16 seq_id; 1324 __le16 resp_len; 1325 __le16 fid; 1326 __le16 port_id; 1327 __le16 vlan; 1328 __le16 flags; 1329 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1330 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1331 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1332 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1333 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1334 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1335 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1336 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1337 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1338 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1339 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1340 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1341 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1342 u8 mac_address[6]; 1343 __le16 pci_id; 1344 __le16 alloc_rsscos_ctx; 1345 __le16 alloc_cmpl_rings; 1346 __le16 alloc_tx_rings; 1347 __le16 alloc_rx_rings; 1348 __le16 alloc_l2_ctx; 1349 __le16 alloc_vnics; 1350 __le16 mtu; 1351 __le16 mru; 1352 __le16 stat_ctx_id; 1353 u8 port_partition_type; 1354 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1355 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1356 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1357 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1358 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1359 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1360 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1361 u8 port_pf_cnt; 1362 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1363 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1364 __le16 dflt_vnic_id; 1365 __le16 max_mtu_configured; 1366 __le32 min_bw; 1367 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1368 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1369 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1370 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1371 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1372 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1373 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1374 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1375 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1376 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1377 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1378 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1379 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1380 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1381 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1382 __le32 max_bw; 1383 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1384 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1385 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1386 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1387 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1388 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1389 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1390 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1391 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1392 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1393 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1394 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1395 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1396 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1397 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1398 u8 evb_mode; 1399 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1400 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1401 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1402 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1403 u8 options; 1404 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1405 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1406 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1407 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1408 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1409 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1410 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1411 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1412 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1413 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1414 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1415 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1416 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1417 __le16 alloc_vfs; 1418 __le32 alloc_mcast_filters; 1419 __le32 alloc_hw_ring_grps; 1420 __le16 alloc_sp_tx_rings; 1421 __le16 alloc_stat_ctx; 1422 __le16 alloc_msix; 1423 __le16 registered_vfs; 1424 __le16 l2_doorbell_bar_size_kb; 1425 u8 unused_1; 1426 u8 always_1; 1427 __le32 reset_addr_poll; 1428 __le16 legacy_l2_db_size_kb; 1429 __le16 svif_info; 1430 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1431 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1432 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1433 u8 mpc_chnls; 1434 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1435 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1436 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1437 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1438 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1439 u8 unused_2[6]; 1440 u8 valid; 1441 }; 1442 1443 /* hwrm_func_cfg_input (size:768b/96B) */ 1444 struct hwrm_func_cfg_input { 1445 __le16 req_type; 1446 __le16 cmpl_ring; 1447 __le16 seq_id; 1448 __le16 target_id; 1449 __le64 resp_addr; 1450 __le16 fid; 1451 __le16 num_msix; 1452 __le32 flags; 1453 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1454 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1455 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1456 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1457 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1458 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1459 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1460 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1461 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1462 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1463 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1464 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1465 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1466 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1467 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1468 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1469 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1470 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1471 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1472 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1473 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1474 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1475 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1476 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1477 __le32 enables; 1478 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1479 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1480 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1481 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1482 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1483 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1484 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1485 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1486 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1487 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1488 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1489 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1490 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1491 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1492 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1493 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1494 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1495 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1496 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1497 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1498 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1499 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1500 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1501 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1502 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1503 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1504 __le16 mtu; 1505 __le16 mru; 1506 __le16 num_rsscos_ctxs; 1507 __le16 num_cmpl_rings; 1508 __le16 num_tx_rings; 1509 __le16 num_rx_rings; 1510 __le16 num_l2_ctxs; 1511 __le16 num_vnics; 1512 __le16 num_stat_ctxs; 1513 __le16 num_hw_ring_grps; 1514 u8 dflt_mac_addr[6]; 1515 __le16 dflt_vlan; 1516 __be32 dflt_ip_addr[4]; 1517 __le32 min_bw; 1518 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1519 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1520 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1521 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1522 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1523 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1524 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1525 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1526 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1527 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1528 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1529 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1530 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1531 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1532 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1533 __le32 max_bw; 1534 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1535 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1536 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1537 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1538 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1539 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1540 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1541 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1542 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1543 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1544 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1545 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1546 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1547 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1548 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1549 __le16 async_event_cr; 1550 u8 vlan_antispoof_mode; 1551 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1552 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1553 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1554 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1555 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1556 u8 allowed_vlan_pris; 1557 u8 evb_mode; 1558 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1559 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1560 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1561 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1562 u8 options; 1563 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1564 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1565 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1566 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1567 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1568 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1569 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1570 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1571 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1572 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1573 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1574 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1575 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1576 __le16 num_mcast_filters; 1577 __le16 schq_id; 1578 __le16 mpc_chnls; 1579 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1580 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1581 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1582 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1583 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1584 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1585 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1586 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1587 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1588 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1589 u8 unused_0[4]; 1590 }; 1591 1592 /* hwrm_func_cfg_output (size:128b/16B) */ 1593 struct hwrm_func_cfg_output { 1594 __le16 error_code; 1595 __le16 req_type; 1596 __le16 seq_id; 1597 __le16 resp_len; 1598 u8 unused_0[7]; 1599 u8 valid; 1600 }; 1601 1602 /* hwrm_func_qstats_input (size:192b/24B) */ 1603 struct hwrm_func_qstats_input { 1604 __le16 req_type; 1605 __le16 cmpl_ring; 1606 __le16 seq_id; 1607 __le16 target_id; 1608 __le64 resp_addr; 1609 __le16 fid; 1610 u8 flags; 1611 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1612 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1613 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1614 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1615 u8 unused_0[5]; 1616 }; 1617 1618 /* hwrm_func_qstats_output (size:1408b/176B) */ 1619 struct hwrm_func_qstats_output { 1620 __le16 error_code; 1621 __le16 req_type; 1622 __le16 seq_id; 1623 __le16 resp_len; 1624 __le64 tx_ucast_pkts; 1625 __le64 tx_mcast_pkts; 1626 __le64 tx_bcast_pkts; 1627 __le64 tx_discard_pkts; 1628 __le64 tx_drop_pkts; 1629 __le64 tx_ucast_bytes; 1630 __le64 tx_mcast_bytes; 1631 __le64 tx_bcast_bytes; 1632 __le64 rx_ucast_pkts; 1633 __le64 rx_mcast_pkts; 1634 __le64 rx_bcast_pkts; 1635 __le64 rx_discard_pkts; 1636 __le64 rx_drop_pkts; 1637 __le64 rx_ucast_bytes; 1638 __le64 rx_mcast_bytes; 1639 __le64 rx_bcast_bytes; 1640 __le64 rx_agg_pkts; 1641 __le64 rx_agg_bytes; 1642 __le64 rx_agg_events; 1643 __le64 rx_agg_aborts; 1644 u8 unused_0[7]; 1645 u8 valid; 1646 }; 1647 1648 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1649 struct hwrm_func_qstats_ext_input { 1650 __le16 req_type; 1651 __le16 cmpl_ring; 1652 __le16 seq_id; 1653 __le16 target_id; 1654 __le64 resp_addr; 1655 __le16 fid; 1656 u8 flags; 1657 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1658 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1659 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1660 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1661 u8 unused_0[1]; 1662 __le32 enables; 1663 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 1664 __le16 schq_id; 1665 __le16 traffic_class; 1666 u8 unused_1[4]; 1667 }; 1668 1669 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 1670 struct hwrm_func_qstats_ext_output { 1671 __le16 error_code; 1672 __le16 req_type; 1673 __le16 seq_id; 1674 __le16 resp_len; 1675 __le64 rx_ucast_pkts; 1676 __le64 rx_mcast_pkts; 1677 __le64 rx_bcast_pkts; 1678 __le64 rx_discard_pkts; 1679 __le64 rx_error_pkts; 1680 __le64 rx_ucast_bytes; 1681 __le64 rx_mcast_bytes; 1682 __le64 rx_bcast_bytes; 1683 __le64 tx_ucast_pkts; 1684 __le64 tx_mcast_pkts; 1685 __le64 tx_bcast_pkts; 1686 __le64 tx_error_pkts; 1687 __le64 tx_discard_pkts; 1688 __le64 tx_ucast_bytes; 1689 __le64 tx_mcast_bytes; 1690 __le64 tx_bcast_bytes; 1691 __le64 rx_tpa_eligible_pkt; 1692 __le64 rx_tpa_eligible_bytes; 1693 __le64 rx_tpa_pkt; 1694 __le64 rx_tpa_bytes; 1695 __le64 rx_tpa_errors; 1696 __le64 rx_tpa_events; 1697 u8 unused_0[7]; 1698 u8 valid; 1699 }; 1700 1701 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1702 struct hwrm_func_clr_stats_input { 1703 __le16 req_type; 1704 __le16 cmpl_ring; 1705 __le16 seq_id; 1706 __le16 target_id; 1707 __le64 resp_addr; 1708 __le16 fid; 1709 u8 unused_0[6]; 1710 }; 1711 1712 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1713 struct hwrm_func_clr_stats_output { 1714 __le16 error_code; 1715 __le16 req_type; 1716 __le16 seq_id; 1717 __le16 resp_len; 1718 u8 unused_0[7]; 1719 u8 valid; 1720 }; 1721 1722 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1723 struct hwrm_func_vf_resc_free_input { 1724 __le16 req_type; 1725 __le16 cmpl_ring; 1726 __le16 seq_id; 1727 __le16 target_id; 1728 __le64 resp_addr; 1729 __le16 vf_id; 1730 u8 unused_0[6]; 1731 }; 1732 1733 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1734 struct hwrm_func_vf_resc_free_output { 1735 __le16 error_code; 1736 __le16 req_type; 1737 __le16 seq_id; 1738 __le16 resp_len; 1739 u8 unused_0[7]; 1740 u8 valid; 1741 }; 1742 1743 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1744 struct hwrm_func_drv_rgtr_input { 1745 __le16 req_type; 1746 __le16 cmpl_ring; 1747 __le16 seq_id; 1748 __le16 target_id; 1749 __le64 resp_addr; 1750 __le32 flags; 1751 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1752 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1753 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1754 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1755 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1756 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1757 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1758 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 1759 __le32 enables; 1760 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1761 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1762 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1763 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1764 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1765 __le16 os_type; 1766 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1767 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1768 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1769 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1770 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1771 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1772 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1773 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1774 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1775 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1776 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1777 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1778 u8 ver_maj_8b; 1779 u8 ver_min_8b; 1780 u8 ver_upd_8b; 1781 u8 unused_0[3]; 1782 __le32 timestamp; 1783 u8 unused_1[4]; 1784 __le32 vf_req_fwd[8]; 1785 __le32 async_event_fwd[8]; 1786 __le16 ver_maj; 1787 __le16 ver_min; 1788 __le16 ver_upd; 1789 __le16 ver_patch; 1790 }; 1791 1792 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1793 struct hwrm_func_drv_rgtr_output { 1794 __le16 error_code; 1795 __le16 req_type; 1796 __le16 seq_id; 1797 __le16 resp_len; 1798 __le32 flags; 1799 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1800 u8 unused_0[3]; 1801 u8 valid; 1802 }; 1803 1804 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1805 struct hwrm_func_drv_unrgtr_input { 1806 __le16 req_type; 1807 __le16 cmpl_ring; 1808 __le16 seq_id; 1809 __le16 target_id; 1810 __le64 resp_addr; 1811 __le32 flags; 1812 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1813 u8 unused_0[4]; 1814 }; 1815 1816 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1817 struct hwrm_func_drv_unrgtr_output { 1818 __le16 error_code; 1819 __le16 req_type; 1820 __le16 seq_id; 1821 __le16 resp_len; 1822 u8 unused_0[7]; 1823 u8 valid; 1824 }; 1825 1826 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1827 struct hwrm_func_buf_rgtr_input { 1828 __le16 req_type; 1829 __le16 cmpl_ring; 1830 __le16 seq_id; 1831 __le16 target_id; 1832 __le64 resp_addr; 1833 __le32 enables; 1834 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1835 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1836 __le16 vf_id; 1837 __le16 req_buf_num_pages; 1838 __le16 req_buf_page_size; 1839 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1840 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1841 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1842 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1843 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1844 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1845 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1846 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1847 __le16 req_buf_len; 1848 __le16 resp_buf_len; 1849 u8 unused_0[2]; 1850 __le64 req_buf_page_addr0; 1851 __le64 req_buf_page_addr1; 1852 __le64 req_buf_page_addr2; 1853 __le64 req_buf_page_addr3; 1854 __le64 req_buf_page_addr4; 1855 __le64 req_buf_page_addr5; 1856 __le64 req_buf_page_addr6; 1857 __le64 req_buf_page_addr7; 1858 __le64 req_buf_page_addr8; 1859 __le64 req_buf_page_addr9; 1860 __le64 error_buf_addr; 1861 __le64 resp_buf_addr; 1862 }; 1863 1864 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1865 struct hwrm_func_buf_rgtr_output { 1866 __le16 error_code; 1867 __le16 req_type; 1868 __le16 seq_id; 1869 __le16 resp_len; 1870 u8 unused_0[7]; 1871 u8 valid; 1872 }; 1873 1874 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1875 struct hwrm_func_drv_qver_input { 1876 __le16 req_type; 1877 __le16 cmpl_ring; 1878 __le16 seq_id; 1879 __le16 target_id; 1880 __le64 resp_addr; 1881 __le32 reserved; 1882 __le16 fid; 1883 u8 unused_0[2]; 1884 }; 1885 1886 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1887 struct hwrm_func_drv_qver_output { 1888 __le16 error_code; 1889 __le16 req_type; 1890 __le16 seq_id; 1891 __le16 resp_len; 1892 __le16 os_type; 1893 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1894 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1895 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1896 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1897 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1898 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1899 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1900 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1901 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1902 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1903 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1904 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1905 u8 ver_maj_8b; 1906 u8 ver_min_8b; 1907 u8 ver_upd_8b; 1908 u8 unused_0[3]; 1909 __le16 ver_maj; 1910 __le16 ver_min; 1911 __le16 ver_upd; 1912 __le16 ver_patch; 1913 u8 unused_1[7]; 1914 u8 valid; 1915 }; 1916 1917 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1918 struct hwrm_func_resource_qcaps_input { 1919 __le16 req_type; 1920 __le16 cmpl_ring; 1921 __le16 seq_id; 1922 __le16 target_id; 1923 __le64 resp_addr; 1924 __le16 fid; 1925 u8 unused_0[6]; 1926 }; 1927 1928 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1929 struct hwrm_func_resource_qcaps_output { 1930 __le16 error_code; 1931 __le16 req_type; 1932 __le16 seq_id; 1933 __le16 resp_len; 1934 __le16 max_vfs; 1935 __le16 max_msix; 1936 __le16 vf_reservation_strategy; 1937 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1938 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1939 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1940 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1941 __le16 min_rsscos_ctx; 1942 __le16 max_rsscos_ctx; 1943 __le16 min_cmpl_rings; 1944 __le16 max_cmpl_rings; 1945 __le16 min_tx_rings; 1946 __le16 max_tx_rings; 1947 __le16 min_rx_rings; 1948 __le16 max_rx_rings; 1949 __le16 min_l2_ctxs; 1950 __le16 max_l2_ctxs; 1951 __le16 min_vnics; 1952 __le16 max_vnics; 1953 __le16 min_stat_ctx; 1954 __le16 max_stat_ctx; 1955 __le16 min_hw_ring_grps; 1956 __le16 max_hw_ring_grps; 1957 __le16 max_tx_scheduler_inputs; 1958 __le16 flags; 1959 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1960 u8 unused_0[5]; 1961 u8 valid; 1962 }; 1963 1964 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1965 struct hwrm_func_vf_resource_cfg_input { 1966 __le16 req_type; 1967 __le16 cmpl_ring; 1968 __le16 seq_id; 1969 __le16 target_id; 1970 __le64 resp_addr; 1971 __le16 vf_id; 1972 __le16 max_msix; 1973 __le16 min_rsscos_ctx; 1974 __le16 max_rsscos_ctx; 1975 __le16 min_cmpl_rings; 1976 __le16 max_cmpl_rings; 1977 __le16 min_tx_rings; 1978 __le16 max_tx_rings; 1979 __le16 min_rx_rings; 1980 __le16 max_rx_rings; 1981 __le16 min_l2_ctxs; 1982 __le16 max_l2_ctxs; 1983 __le16 min_vnics; 1984 __le16 max_vnics; 1985 __le16 min_stat_ctx; 1986 __le16 max_stat_ctx; 1987 __le16 min_hw_ring_grps; 1988 __le16 max_hw_ring_grps; 1989 __le16 flags; 1990 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1991 u8 unused_0[2]; 1992 }; 1993 1994 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1995 struct hwrm_func_vf_resource_cfg_output { 1996 __le16 error_code; 1997 __le16 req_type; 1998 __le16 seq_id; 1999 __le16 resp_len; 2000 __le16 reserved_rsscos_ctx; 2001 __le16 reserved_cmpl_rings; 2002 __le16 reserved_tx_rings; 2003 __le16 reserved_rx_rings; 2004 __le16 reserved_l2_ctxs; 2005 __le16 reserved_vnics; 2006 __le16 reserved_stat_ctx; 2007 __le16 reserved_hw_ring_grps; 2008 u8 unused_0[7]; 2009 u8 valid; 2010 }; 2011 2012 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2013 struct hwrm_func_backing_store_qcaps_input { 2014 __le16 req_type; 2015 __le16 cmpl_ring; 2016 __le16 seq_id; 2017 __le16 target_id; 2018 __le64 resp_addr; 2019 }; 2020 2021 /* hwrm_func_backing_store_qcaps_output (size:704b/88B) */ 2022 struct hwrm_func_backing_store_qcaps_output { 2023 __le16 error_code; 2024 __le16 req_type; 2025 __le16 seq_id; 2026 __le16 resp_len; 2027 __le32 qp_max_entries; 2028 __le16 qp_min_qp1_entries; 2029 __le16 qp_max_l2_entries; 2030 __le16 qp_entry_size; 2031 __le16 srq_max_l2_entries; 2032 __le32 srq_max_entries; 2033 __le16 srq_entry_size; 2034 __le16 cq_max_l2_entries; 2035 __le32 cq_max_entries; 2036 __le16 cq_entry_size; 2037 __le16 vnic_max_vnic_entries; 2038 __le16 vnic_max_ring_table_entries; 2039 __le16 vnic_entry_size; 2040 __le32 stat_max_entries; 2041 __le16 stat_entry_size; 2042 __le16 tqm_entry_size; 2043 __le32 tqm_min_entries_per_ring; 2044 __le32 tqm_max_entries_per_ring; 2045 __le32 mrav_max_entries; 2046 __le16 mrav_entry_size; 2047 __le16 tim_entry_size; 2048 __le32 tim_max_entries; 2049 __le16 mrav_num_entries_units; 2050 u8 tqm_entries_multiple; 2051 u8 ctx_kind_initializer; 2052 __le16 ctx_init_mask; 2053 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2054 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2055 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2056 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2057 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2058 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2059 u8 qp_init_offset; 2060 u8 srq_init_offset; 2061 u8 cq_init_offset; 2062 u8 vnic_init_offset; 2063 u8 tqm_fp_rings_count; 2064 u8 stat_init_offset; 2065 u8 mrav_init_offset; 2066 u8 rsvd[6]; 2067 u8 valid; 2068 }; 2069 2070 /* hwrm_func_backing_store_cfg_input (size:2432b/304B) */ 2071 struct hwrm_func_backing_store_cfg_input { 2072 __le16 req_type; 2073 __le16 cmpl_ring; 2074 __le16 seq_id; 2075 __le16 target_id; 2076 __le64 resp_addr; 2077 __le32 flags; 2078 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2079 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2080 __le32 enables; 2081 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2082 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2083 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2084 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2085 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2086 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2087 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2088 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2089 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2090 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2091 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2092 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2093 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2094 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2095 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2096 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2097 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2098 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2099 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2100 u8 qpc_pg_size_qpc_lvl; 2101 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2102 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2103 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2104 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2105 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2106 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2107 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2108 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2109 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2110 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2111 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2112 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2113 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2114 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2115 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2116 u8 srq_pg_size_srq_lvl; 2117 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2118 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2119 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2120 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2121 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2122 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2123 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2124 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2125 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2126 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2127 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2128 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2129 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2130 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2131 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2132 u8 cq_pg_size_cq_lvl; 2133 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2134 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2135 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2136 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2137 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2138 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2139 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2140 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2141 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2142 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2143 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2144 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2145 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2146 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2147 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2148 u8 vnic_pg_size_vnic_lvl; 2149 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2150 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2151 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2152 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2153 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2154 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2155 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2156 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2157 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2158 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2159 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2160 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2161 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2162 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2163 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2164 u8 stat_pg_size_stat_lvl; 2165 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2166 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2167 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2168 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2169 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2170 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2171 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2172 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2173 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2174 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2175 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2176 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2177 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2178 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2179 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2180 u8 tqm_sp_pg_size_tqm_sp_lvl; 2181 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2182 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2183 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2184 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2185 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2186 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2187 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2188 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2189 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2190 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2191 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2192 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2193 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2194 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2195 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2196 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2197 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2198 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2199 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2200 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2201 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2202 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2203 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2204 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2205 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2206 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2207 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2208 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2209 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2210 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2211 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2212 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2213 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2214 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2215 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2216 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2217 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2218 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2219 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2220 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2221 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2222 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2223 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2224 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2225 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2226 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2227 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2228 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2229 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2230 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2231 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2232 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2233 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2234 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2235 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2236 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2237 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2238 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2239 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2240 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2241 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2242 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2243 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2244 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2245 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2246 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2247 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2248 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2249 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2250 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2251 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2252 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2253 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2254 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2255 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2256 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2257 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2258 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2259 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2260 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2261 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2262 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2263 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2264 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2265 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2266 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2267 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2268 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2269 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2270 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2271 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2272 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2273 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2274 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2275 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2276 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2277 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2278 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2279 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2280 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2281 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2282 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2283 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2284 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2285 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2286 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2287 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2288 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2289 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2290 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2291 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2292 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2293 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2294 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2295 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2296 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2297 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2298 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2299 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2300 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2301 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2302 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2303 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2304 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2305 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2306 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2307 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2308 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2309 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2310 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2311 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2312 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2313 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2314 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2315 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2316 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2317 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2318 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2319 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2320 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2321 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2322 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2323 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2324 u8 mrav_pg_size_mrav_lvl; 2325 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2326 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2327 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2328 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2329 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2330 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2331 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2332 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2333 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2334 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2335 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2336 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2337 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2338 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2339 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2340 u8 tim_pg_size_tim_lvl; 2341 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2342 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2343 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2344 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2345 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2346 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2347 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2348 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2349 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2350 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2351 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2352 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2353 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2354 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2355 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2356 __le64 qpc_page_dir; 2357 __le64 srq_page_dir; 2358 __le64 cq_page_dir; 2359 __le64 vnic_page_dir; 2360 __le64 stat_page_dir; 2361 __le64 tqm_sp_page_dir; 2362 __le64 tqm_ring0_page_dir; 2363 __le64 tqm_ring1_page_dir; 2364 __le64 tqm_ring2_page_dir; 2365 __le64 tqm_ring3_page_dir; 2366 __le64 tqm_ring4_page_dir; 2367 __le64 tqm_ring5_page_dir; 2368 __le64 tqm_ring6_page_dir; 2369 __le64 tqm_ring7_page_dir; 2370 __le64 mrav_page_dir; 2371 __le64 tim_page_dir; 2372 __le32 qp_num_entries; 2373 __le32 srq_num_entries; 2374 __le32 cq_num_entries; 2375 __le32 stat_num_entries; 2376 __le32 tqm_sp_num_entries; 2377 __le32 tqm_ring0_num_entries; 2378 __le32 tqm_ring1_num_entries; 2379 __le32 tqm_ring2_num_entries; 2380 __le32 tqm_ring3_num_entries; 2381 __le32 tqm_ring4_num_entries; 2382 __le32 tqm_ring5_num_entries; 2383 __le32 tqm_ring6_num_entries; 2384 __le32 tqm_ring7_num_entries; 2385 __le32 mrav_num_entries; 2386 __le32 tim_num_entries; 2387 __le16 qp_num_qp1_entries; 2388 __le16 qp_num_l2_entries; 2389 __le16 qp_entry_size; 2390 __le16 srq_num_l2_entries; 2391 __le16 srq_entry_size; 2392 __le16 cq_num_l2_entries; 2393 __le16 cq_entry_size; 2394 __le16 vnic_num_vnic_entries; 2395 __le16 vnic_num_ring_table_entries; 2396 __le16 vnic_entry_size; 2397 __le16 stat_entry_size; 2398 __le16 tqm_entry_size; 2399 __le16 mrav_entry_size; 2400 __le16 tim_entry_size; 2401 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2402 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2403 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2404 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2405 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2406 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2407 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2408 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2409 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2410 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2411 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2412 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2413 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2414 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2415 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2416 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2417 u8 ring8_unused[3]; 2418 __le32 tqm_ring8_num_entries; 2419 __le64 tqm_ring8_page_dir; 2420 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2421 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2422 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2423 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2424 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2425 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2426 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2427 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2428 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2429 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2430 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2431 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2432 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2433 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2434 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2435 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2436 u8 ring9_unused[3]; 2437 __le32 tqm_ring9_num_entries; 2438 __le64 tqm_ring9_page_dir; 2439 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2440 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2441 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2442 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2443 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2444 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2445 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2446 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2447 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2448 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2449 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2450 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2451 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2452 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2453 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2454 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2455 u8 ring10_unused[3]; 2456 __le32 tqm_ring10_num_entries; 2457 __le64 tqm_ring10_page_dir; 2458 }; 2459 2460 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2461 struct hwrm_func_backing_store_cfg_output { 2462 __le16 error_code; 2463 __le16 req_type; 2464 __le16 seq_id; 2465 __le16 resp_len; 2466 u8 unused_0[7]; 2467 u8 valid; 2468 }; 2469 2470 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2471 struct hwrm_error_recovery_qcfg_input { 2472 __le16 req_type; 2473 __le16 cmpl_ring; 2474 __le16 seq_id; 2475 __le16 target_id; 2476 __le64 resp_addr; 2477 u8 unused_0[8]; 2478 }; 2479 2480 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2481 struct hwrm_error_recovery_qcfg_output { 2482 __le16 error_code; 2483 __le16 req_type; 2484 __le16 seq_id; 2485 __le16 resp_len; 2486 __le32 flags; 2487 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2488 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2489 __le32 driver_polling_freq; 2490 __le32 master_func_wait_period; 2491 __le32 normal_func_wait_period; 2492 __le32 master_func_wait_period_after_reset; 2493 __le32 max_bailout_time_after_reset; 2494 __le32 fw_health_status_reg; 2495 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2496 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2497 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2498 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2499 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2500 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2501 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2502 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2503 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2504 __le32 fw_heartbeat_reg; 2505 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2506 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2507 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2508 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2509 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2510 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2511 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2512 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2513 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2514 __le32 fw_reset_cnt_reg; 2515 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2516 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2517 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2518 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2519 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2520 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2521 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2522 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2523 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2524 __le32 reset_inprogress_reg; 2525 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2526 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2527 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2528 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2529 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2530 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2531 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2532 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2533 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2534 __le32 reset_inprogress_reg_mask; 2535 u8 unused_0[3]; 2536 u8 reg_array_cnt; 2537 __le32 reset_reg[16]; 2538 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2539 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2540 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2541 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2542 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2543 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2544 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2545 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2546 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2547 __le32 reset_reg_val[16]; 2548 u8 delay_after_reset[16]; 2549 __le32 err_recovery_cnt_reg; 2550 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2551 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2552 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2553 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2554 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2555 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2556 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2557 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2558 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2559 u8 unused_1[3]; 2560 u8 valid; 2561 }; 2562 2563 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2564 struct hwrm_func_drv_if_change_input { 2565 __le16 req_type; 2566 __le16 cmpl_ring; 2567 __le16 seq_id; 2568 __le16 target_id; 2569 __le64 resp_addr; 2570 __le32 flags; 2571 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2572 __le32 unused; 2573 }; 2574 2575 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2576 struct hwrm_func_drv_if_change_output { 2577 __le16 error_code; 2578 __le16 req_type; 2579 __le16 seq_id; 2580 __le16 resp_len; 2581 __le32 flags; 2582 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2583 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2584 u8 unused_0[3]; 2585 u8 valid; 2586 }; 2587 2588 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2589 struct hwrm_port_phy_cfg_input { 2590 __le16 req_type; 2591 __le16 cmpl_ring; 2592 __le16 seq_id; 2593 __le16 target_id; 2594 __le64 resp_addr; 2595 __le32 flags; 2596 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2597 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2598 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2599 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2600 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2601 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2602 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2603 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2604 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2605 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2606 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2607 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2608 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2609 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2610 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2611 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 2612 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 2613 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 2614 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 2615 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 2616 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 2617 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 2618 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 2619 __le32 enables; 2620 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2621 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2622 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2623 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2624 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2625 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2626 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2627 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2628 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2629 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2630 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2631 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 2632 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 2633 __le16 port_id; 2634 __le16 force_link_speed; 2635 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2636 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2637 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2638 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2639 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2640 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2641 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2642 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2643 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2644 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2645 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2646 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2647 u8 auto_mode; 2648 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2649 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2650 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2651 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2652 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2653 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2654 u8 auto_duplex; 2655 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2656 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2657 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2658 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2659 u8 auto_pause; 2660 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2661 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2662 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2663 u8 unused_0; 2664 __le16 auto_link_speed; 2665 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2666 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2667 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2668 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2669 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2670 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2671 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2672 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2673 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2674 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2675 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2676 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2677 __le16 auto_link_speed_mask; 2678 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2679 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2680 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2681 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2682 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2683 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2684 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2685 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2686 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2687 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2688 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2689 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2690 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2691 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2692 u8 wirespeed; 2693 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2694 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2695 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2696 u8 lpbk; 2697 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2698 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2699 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2700 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2701 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2702 u8 force_pause; 2703 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2704 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2705 u8 unused_1; 2706 __le32 preemphasis; 2707 __le16 eee_link_speed_mask; 2708 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2709 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2710 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2711 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2712 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2713 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2714 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2715 __le16 force_pam4_link_speed; 2716 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2717 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2718 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2719 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 2720 __le32 tx_lpi_timer; 2721 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2722 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2723 __le16 auto_link_pam4_speed_mask; 2724 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 2725 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 2726 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 2727 u8 unused_2[2]; 2728 }; 2729 2730 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2731 struct hwrm_port_phy_cfg_output { 2732 __le16 error_code; 2733 __le16 req_type; 2734 __le16 seq_id; 2735 __le16 resp_len; 2736 u8 unused_0[7]; 2737 u8 valid; 2738 }; 2739 2740 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2741 struct hwrm_port_phy_cfg_cmd_err { 2742 u8 code; 2743 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2744 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2745 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2746 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2747 u8 unused_0[7]; 2748 }; 2749 2750 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2751 struct hwrm_port_phy_qcfg_input { 2752 __le16 req_type; 2753 __le16 cmpl_ring; 2754 __le16 seq_id; 2755 __le16 target_id; 2756 __le64 resp_addr; 2757 __le16 port_id; 2758 u8 unused_0[6]; 2759 }; 2760 2761 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2762 struct hwrm_port_phy_qcfg_output { 2763 __le16 error_code; 2764 __le16 req_type; 2765 __le16 seq_id; 2766 __le16 resp_len; 2767 u8 link; 2768 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2769 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2770 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2771 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2772 u8 active_fec_signal_mode; 2773 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 2774 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 2775 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 2776 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 2777 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 2778 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 2779 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 2780 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 2781 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 2782 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 2783 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 2784 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 2785 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 2786 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 2787 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 2788 __le16 link_speed; 2789 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2790 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2791 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2792 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2793 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2794 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2795 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2796 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2797 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2798 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2799 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2800 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2801 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2802 u8 duplex_cfg; 2803 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2804 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2805 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2806 u8 pause; 2807 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2808 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2809 __le16 support_speeds; 2810 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2811 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2812 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2813 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2814 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2815 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2816 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2817 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2818 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2819 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2820 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2821 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2822 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2823 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2824 __le16 force_link_speed; 2825 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2826 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2827 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2828 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2829 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2830 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2831 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2832 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2833 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2834 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2835 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2836 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2837 u8 auto_mode; 2838 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2839 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2840 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2841 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2842 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2843 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2844 u8 auto_pause; 2845 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2846 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2847 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2848 __le16 auto_link_speed; 2849 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2850 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2851 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2852 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2853 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2854 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2855 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2856 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2857 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2858 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2859 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2860 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2861 __le16 auto_link_speed_mask; 2862 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2863 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2864 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2865 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2866 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2867 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2868 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2869 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2870 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2871 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2872 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2873 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2874 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2875 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2876 u8 wirespeed; 2877 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2878 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2879 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2880 u8 lpbk; 2881 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2882 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2883 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2884 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2885 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2886 u8 force_pause; 2887 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2888 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2889 u8 module_status; 2890 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2891 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2892 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2893 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2894 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2895 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2896 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2897 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2898 __le32 preemphasis; 2899 u8 phy_maj; 2900 u8 phy_min; 2901 u8 phy_bld; 2902 u8 phy_type; 2903 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2904 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2905 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2906 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2907 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2908 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2909 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2910 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2911 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2912 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2913 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2914 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2915 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2916 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2917 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2918 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2919 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2920 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2921 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2922 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2923 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2924 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2925 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2926 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2927 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2928 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2929 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2930 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2931 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2932 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2933 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2934 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2935 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2936 u8 media_type; 2937 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2938 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2939 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2940 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2941 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2942 u8 xcvr_pkg_type; 2943 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2944 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2945 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2946 u8 eee_config_phy_addr; 2947 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2948 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2949 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2950 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2951 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2952 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2953 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2954 u8 parallel_detect; 2955 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2956 __le16 link_partner_adv_speeds; 2957 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2958 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2959 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2960 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2961 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2962 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2963 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2964 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2965 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2966 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2967 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2968 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2969 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2970 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2971 u8 link_partner_adv_auto_mode; 2972 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2973 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2974 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2975 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2976 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2977 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2978 u8 link_partner_adv_pause; 2979 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2980 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2981 __le16 adv_eee_link_speed_mask; 2982 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2983 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2984 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2985 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2986 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2987 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2988 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2989 __le16 link_partner_adv_eee_link_speed_mask; 2990 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2991 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2992 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2993 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2994 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2995 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2996 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2997 __le32 xcvr_identifier_type_tx_lpi_timer; 2998 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2999 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 3000 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 3001 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 3002 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 3003 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 3004 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 3005 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 3006 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3007 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3008 __le16 fec_cfg; 3009 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3010 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3011 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3012 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3013 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3014 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3015 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3016 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3017 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 3018 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 3019 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 3020 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 3021 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 3022 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 3023 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3024 u8 duplex_state; 3025 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3026 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3027 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3028 u8 option_flags; 3029 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 3030 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 3031 char phy_vendor_name[16]; 3032 char phy_vendor_partnumber[16]; 3033 __le16 support_pam4_speeds; 3034 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3035 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3036 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3037 __le16 force_pam4_link_speed; 3038 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3039 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3040 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3041 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3042 __le16 auto_pam4_link_speed_mask; 3043 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3044 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3045 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 3046 u8 link_partner_pam4_adv_speeds; 3047 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3048 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3049 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3050 u8 valid; 3051 }; 3052 3053 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3054 struct hwrm_port_mac_cfg_input { 3055 __le16 req_type; 3056 __le16 cmpl_ring; 3057 __le16 seq_id; 3058 __le16 target_id; 3059 __le64 resp_addr; 3060 __le32 flags; 3061 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3062 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3063 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3064 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 3065 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 3066 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 3067 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 3068 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3069 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3070 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3071 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3072 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3073 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 3074 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3075 __le32 enables; 3076 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3077 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3078 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3079 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3080 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 3081 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 3082 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3083 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 3084 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 3085 __le16 port_id; 3086 u8 ipg; 3087 u8 lpbk; 3088 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3089 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3090 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3091 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3092 u8 vlan_pri2cos_map_pri; 3093 u8 reserved1; 3094 u8 tunnel_pri2cos_map_pri; 3095 u8 dscp2pri_map_pri; 3096 __le16 rx_ts_capture_ptp_msg_type; 3097 __le16 tx_ts_capture_ptp_msg_type; 3098 u8 cos_field_cfg; 3099 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3100 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3101 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3102 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3103 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3104 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3105 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3106 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3107 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3108 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3109 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3110 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3111 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3112 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3113 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3114 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3115 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3116 u8 unused_0[3]; 3117 __s32 ptp_freq_adj_ppb; 3118 u8 unused_1[4]; 3119 }; 3120 3121 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3122 struct hwrm_port_mac_cfg_output { 3123 __le16 error_code; 3124 __le16 req_type; 3125 __le16 seq_id; 3126 __le16 resp_len; 3127 __le16 mru; 3128 __le16 mtu; 3129 u8 ipg; 3130 u8 lpbk; 3131 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3132 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3133 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3134 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3135 u8 unused_0; 3136 u8 valid; 3137 }; 3138 3139 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3140 struct hwrm_port_mac_ptp_qcfg_input { 3141 __le16 req_type; 3142 __le16 cmpl_ring; 3143 __le16 seq_id; 3144 __le16 target_id; 3145 __le64 resp_addr; 3146 __le16 port_id; 3147 u8 unused_0[6]; 3148 }; 3149 3150 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 3151 struct hwrm_port_mac_ptp_qcfg_output { 3152 __le16 error_code; 3153 __le16 req_type; 3154 __le16 seq_id; 3155 __le16 resp_len; 3156 u8 flags; 3157 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3158 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3159 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3160 u8 unused_0[3]; 3161 __le32 rx_ts_reg_off_lower; 3162 __le32 rx_ts_reg_off_upper; 3163 __le32 rx_ts_reg_off_seq_id; 3164 __le32 rx_ts_reg_off_src_id_0; 3165 __le32 rx_ts_reg_off_src_id_1; 3166 __le32 rx_ts_reg_off_src_id_2; 3167 __le32 rx_ts_reg_off_domain_id; 3168 __le32 rx_ts_reg_off_fifo; 3169 __le32 rx_ts_reg_off_fifo_adv; 3170 __le32 rx_ts_reg_off_granularity; 3171 __le32 tx_ts_reg_off_lower; 3172 __le32 tx_ts_reg_off_upper; 3173 __le32 tx_ts_reg_off_seq_id; 3174 __le32 tx_ts_reg_off_fifo; 3175 __le32 tx_ts_reg_off_granularity; 3176 u8 unused_1[7]; 3177 u8 valid; 3178 }; 3179 3180 /* tx_port_stats (size:3264b/408B) */ 3181 struct tx_port_stats { 3182 __le64 tx_64b_frames; 3183 __le64 tx_65b_127b_frames; 3184 __le64 tx_128b_255b_frames; 3185 __le64 tx_256b_511b_frames; 3186 __le64 tx_512b_1023b_frames; 3187 __le64 tx_1024b_1518b_frames; 3188 __le64 tx_good_vlan_frames; 3189 __le64 tx_1519b_2047b_frames; 3190 __le64 tx_2048b_4095b_frames; 3191 __le64 tx_4096b_9216b_frames; 3192 __le64 tx_9217b_16383b_frames; 3193 __le64 tx_good_frames; 3194 __le64 tx_total_frames; 3195 __le64 tx_ucast_frames; 3196 __le64 tx_mcast_frames; 3197 __le64 tx_bcast_frames; 3198 __le64 tx_pause_frames; 3199 __le64 tx_pfc_frames; 3200 __le64 tx_jabber_frames; 3201 __le64 tx_fcs_err_frames; 3202 __le64 tx_control_frames; 3203 __le64 tx_oversz_frames; 3204 __le64 tx_single_dfrl_frames; 3205 __le64 tx_multi_dfrl_frames; 3206 __le64 tx_single_coll_frames; 3207 __le64 tx_multi_coll_frames; 3208 __le64 tx_late_coll_frames; 3209 __le64 tx_excessive_coll_frames; 3210 __le64 tx_frag_frames; 3211 __le64 tx_err; 3212 __le64 tx_tagged_frames; 3213 __le64 tx_dbl_tagged_frames; 3214 __le64 tx_runt_frames; 3215 __le64 tx_fifo_underruns; 3216 __le64 tx_pfc_ena_frames_pri0; 3217 __le64 tx_pfc_ena_frames_pri1; 3218 __le64 tx_pfc_ena_frames_pri2; 3219 __le64 tx_pfc_ena_frames_pri3; 3220 __le64 tx_pfc_ena_frames_pri4; 3221 __le64 tx_pfc_ena_frames_pri5; 3222 __le64 tx_pfc_ena_frames_pri6; 3223 __le64 tx_pfc_ena_frames_pri7; 3224 __le64 tx_eee_lpi_events; 3225 __le64 tx_eee_lpi_duration; 3226 __le64 tx_llfc_logical_msgs; 3227 __le64 tx_hcfc_msgs; 3228 __le64 tx_total_collisions; 3229 __le64 tx_bytes; 3230 __le64 tx_xthol_frames; 3231 __le64 tx_stat_discard; 3232 __le64 tx_stat_error; 3233 }; 3234 3235 /* rx_port_stats (size:4224b/528B) */ 3236 struct rx_port_stats { 3237 __le64 rx_64b_frames; 3238 __le64 rx_65b_127b_frames; 3239 __le64 rx_128b_255b_frames; 3240 __le64 rx_256b_511b_frames; 3241 __le64 rx_512b_1023b_frames; 3242 __le64 rx_1024b_1518b_frames; 3243 __le64 rx_good_vlan_frames; 3244 __le64 rx_1519b_2047b_frames; 3245 __le64 rx_2048b_4095b_frames; 3246 __le64 rx_4096b_9216b_frames; 3247 __le64 rx_9217b_16383b_frames; 3248 __le64 rx_total_frames; 3249 __le64 rx_ucast_frames; 3250 __le64 rx_mcast_frames; 3251 __le64 rx_bcast_frames; 3252 __le64 rx_fcs_err_frames; 3253 __le64 rx_ctrl_frames; 3254 __le64 rx_pause_frames; 3255 __le64 rx_pfc_frames; 3256 __le64 rx_unsupported_opcode_frames; 3257 __le64 rx_unsupported_da_pausepfc_frames; 3258 __le64 rx_wrong_sa_frames; 3259 __le64 rx_align_err_frames; 3260 __le64 rx_oor_len_frames; 3261 __le64 rx_code_err_frames; 3262 __le64 rx_false_carrier_frames; 3263 __le64 rx_ovrsz_frames; 3264 __le64 rx_jbr_frames; 3265 __le64 rx_mtu_err_frames; 3266 __le64 rx_match_crc_frames; 3267 __le64 rx_promiscuous_frames; 3268 __le64 rx_tagged_frames; 3269 __le64 rx_double_tagged_frames; 3270 __le64 rx_trunc_frames; 3271 __le64 rx_good_frames; 3272 __le64 rx_pfc_xon2xoff_frames_pri0; 3273 __le64 rx_pfc_xon2xoff_frames_pri1; 3274 __le64 rx_pfc_xon2xoff_frames_pri2; 3275 __le64 rx_pfc_xon2xoff_frames_pri3; 3276 __le64 rx_pfc_xon2xoff_frames_pri4; 3277 __le64 rx_pfc_xon2xoff_frames_pri5; 3278 __le64 rx_pfc_xon2xoff_frames_pri6; 3279 __le64 rx_pfc_xon2xoff_frames_pri7; 3280 __le64 rx_pfc_ena_frames_pri0; 3281 __le64 rx_pfc_ena_frames_pri1; 3282 __le64 rx_pfc_ena_frames_pri2; 3283 __le64 rx_pfc_ena_frames_pri3; 3284 __le64 rx_pfc_ena_frames_pri4; 3285 __le64 rx_pfc_ena_frames_pri5; 3286 __le64 rx_pfc_ena_frames_pri6; 3287 __le64 rx_pfc_ena_frames_pri7; 3288 __le64 rx_sch_crc_err_frames; 3289 __le64 rx_undrsz_frames; 3290 __le64 rx_frag_frames; 3291 __le64 rx_eee_lpi_events; 3292 __le64 rx_eee_lpi_duration; 3293 __le64 rx_llfc_physical_msgs; 3294 __le64 rx_llfc_logical_msgs; 3295 __le64 rx_llfc_msgs_with_crc_err; 3296 __le64 rx_hcfc_msgs; 3297 __le64 rx_hcfc_msgs_with_crc_err; 3298 __le64 rx_bytes; 3299 __le64 rx_runt_bytes; 3300 __le64 rx_runt_frames; 3301 __le64 rx_stat_discard; 3302 __le64 rx_stat_err; 3303 }; 3304 3305 /* hwrm_port_qstats_input (size:320b/40B) */ 3306 struct hwrm_port_qstats_input { 3307 __le16 req_type; 3308 __le16 cmpl_ring; 3309 __le16 seq_id; 3310 __le16 target_id; 3311 __le64 resp_addr; 3312 __le16 port_id; 3313 u8 flags; 3314 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3315 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3316 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3317 u8 unused_0[5]; 3318 __le64 tx_stat_host_addr; 3319 __le64 rx_stat_host_addr; 3320 }; 3321 3322 /* hwrm_port_qstats_output (size:128b/16B) */ 3323 struct hwrm_port_qstats_output { 3324 __le16 error_code; 3325 __le16 req_type; 3326 __le16 seq_id; 3327 __le16 resp_len; 3328 __le16 tx_stat_size; 3329 __le16 rx_stat_size; 3330 u8 unused_0[3]; 3331 u8 valid; 3332 }; 3333 3334 /* tx_port_stats_ext (size:2048b/256B) */ 3335 struct tx_port_stats_ext { 3336 __le64 tx_bytes_cos0; 3337 __le64 tx_bytes_cos1; 3338 __le64 tx_bytes_cos2; 3339 __le64 tx_bytes_cos3; 3340 __le64 tx_bytes_cos4; 3341 __le64 tx_bytes_cos5; 3342 __le64 tx_bytes_cos6; 3343 __le64 tx_bytes_cos7; 3344 __le64 tx_packets_cos0; 3345 __le64 tx_packets_cos1; 3346 __le64 tx_packets_cos2; 3347 __le64 tx_packets_cos3; 3348 __le64 tx_packets_cos4; 3349 __le64 tx_packets_cos5; 3350 __le64 tx_packets_cos6; 3351 __le64 tx_packets_cos7; 3352 __le64 pfc_pri0_tx_duration_us; 3353 __le64 pfc_pri0_tx_transitions; 3354 __le64 pfc_pri1_tx_duration_us; 3355 __le64 pfc_pri1_tx_transitions; 3356 __le64 pfc_pri2_tx_duration_us; 3357 __le64 pfc_pri2_tx_transitions; 3358 __le64 pfc_pri3_tx_duration_us; 3359 __le64 pfc_pri3_tx_transitions; 3360 __le64 pfc_pri4_tx_duration_us; 3361 __le64 pfc_pri4_tx_transitions; 3362 __le64 pfc_pri5_tx_duration_us; 3363 __le64 pfc_pri5_tx_transitions; 3364 __le64 pfc_pri6_tx_duration_us; 3365 __le64 pfc_pri6_tx_transitions; 3366 __le64 pfc_pri7_tx_duration_us; 3367 __le64 pfc_pri7_tx_transitions; 3368 }; 3369 3370 /* rx_port_stats_ext (size:3648b/456B) */ 3371 struct rx_port_stats_ext { 3372 __le64 link_down_events; 3373 __le64 continuous_pause_events; 3374 __le64 resume_pause_events; 3375 __le64 continuous_roce_pause_events; 3376 __le64 resume_roce_pause_events; 3377 __le64 rx_bytes_cos0; 3378 __le64 rx_bytes_cos1; 3379 __le64 rx_bytes_cos2; 3380 __le64 rx_bytes_cos3; 3381 __le64 rx_bytes_cos4; 3382 __le64 rx_bytes_cos5; 3383 __le64 rx_bytes_cos6; 3384 __le64 rx_bytes_cos7; 3385 __le64 rx_packets_cos0; 3386 __le64 rx_packets_cos1; 3387 __le64 rx_packets_cos2; 3388 __le64 rx_packets_cos3; 3389 __le64 rx_packets_cos4; 3390 __le64 rx_packets_cos5; 3391 __le64 rx_packets_cos6; 3392 __le64 rx_packets_cos7; 3393 __le64 pfc_pri0_rx_duration_us; 3394 __le64 pfc_pri0_rx_transitions; 3395 __le64 pfc_pri1_rx_duration_us; 3396 __le64 pfc_pri1_rx_transitions; 3397 __le64 pfc_pri2_rx_duration_us; 3398 __le64 pfc_pri2_rx_transitions; 3399 __le64 pfc_pri3_rx_duration_us; 3400 __le64 pfc_pri3_rx_transitions; 3401 __le64 pfc_pri4_rx_duration_us; 3402 __le64 pfc_pri4_rx_transitions; 3403 __le64 pfc_pri5_rx_duration_us; 3404 __le64 pfc_pri5_rx_transitions; 3405 __le64 pfc_pri6_rx_duration_us; 3406 __le64 pfc_pri6_rx_transitions; 3407 __le64 pfc_pri7_rx_duration_us; 3408 __le64 pfc_pri7_rx_transitions; 3409 __le64 rx_bits; 3410 __le64 rx_buffer_passed_threshold; 3411 __le64 rx_pcs_symbol_err; 3412 __le64 rx_corrected_bits; 3413 __le64 rx_discard_bytes_cos0; 3414 __le64 rx_discard_bytes_cos1; 3415 __le64 rx_discard_bytes_cos2; 3416 __le64 rx_discard_bytes_cos3; 3417 __le64 rx_discard_bytes_cos4; 3418 __le64 rx_discard_bytes_cos5; 3419 __le64 rx_discard_bytes_cos6; 3420 __le64 rx_discard_bytes_cos7; 3421 __le64 rx_discard_packets_cos0; 3422 __le64 rx_discard_packets_cos1; 3423 __le64 rx_discard_packets_cos2; 3424 __le64 rx_discard_packets_cos3; 3425 __le64 rx_discard_packets_cos4; 3426 __le64 rx_discard_packets_cos5; 3427 __le64 rx_discard_packets_cos6; 3428 __le64 rx_discard_packets_cos7; 3429 }; 3430 3431 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3432 struct hwrm_port_qstats_ext_input { 3433 __le16 req_type; 3434 __le16 cmpl_ring; 3435 __le16 seq_id; 3436 __le16 target_id; 3437 __le64 resp_addr; 3438 __le16 port_id; 3439 __le16 tx_stat_size; 3440 __le16 rx_stat_size; 3441 u8 flags; 3442 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3443 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3444 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3445 u8 unused_0; 3446 __le64 tx_stat_host_addr; 3447 __le64 rx_stat_host_addr; 3448 }; 3449 3450 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3451 struct hwrm_port_qstats_ext_output { 3452 __le16 error_code; 3453 __le16 req_type; 3454 __le16 seq_id; 3455 __le16 resp_len; 3456 __le16 tx_stat_size; 3457 __le16 rx_stat_size; 3458 __le16 total_active_cos_queues; 3459 u8 flags; 3460 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3461 u8 valid; 3462 }; 3463 3464 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3465 struct hwrm_port_lpbk_qstats_input { 3466 __le16 req_type; 3467 __le16 cmpl_ring; 3468 __le16 seq_id; 3469 __le16 target_id; 3470 __le64 resp_addr; 3471 }; 3472 3473 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3474 struct hwrm_port_lpbk_qstats_output { 3475 __le16 error_code; 3476 __le16 req_type; 3477 __le16 seq_id; 3478 __le16 resp_len; 3479 __le64 lpbk_ucast_frames; 3480 __le64 lpbk_mcast_frames; 3481 __le64 lpbk_bcast_frames; 3482 __le64 lpbk_ucast_bytes; 3483 __le64 lpbk_mcast_bytes; 3484 __le64 lpbk_bcast_bytes; 3485 __le64 tx_stat_discard; 3486 __le64 tx_stat_error; 3487 __le64 rx_stat_discard; 3488 __le64 rx_stat_error; 3489 u8 unused_0[7]; 3490 u8 valid; 3491 }; 3492 3493 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 3494 struct hwrm_port_ecn_qstats_input { 3495 __le16 req_type; 3496 __le16 cmpl_ring; 3497 __le16 seq_id; 3498 __le16 target_id; 3499 __le64 resp_addr; 3500 __le16 port_id; 3501 __le16 ecn_stat_buf_size; 3502 u8 flags; 3503 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3504 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3505 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 3506 u8 unused_0[3]; 3507 __le64 ecn_stat_host_addr; 3508 }; 3509 3510 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 3511 struct hwrm_port_ecn_qstats_output { 3512 __le16 error_code; 3513 __le16 req_type; 3514 __le16 seq_id; 3515 __le16 resp_len; 3516 __le16 ecn_stat_buf_size; 3517 u8 mark_en; 3518 u8 unused_0[4]; 3519 u8 valid; 3520 }; 3521 3522 /* port_stats_ecn (size:512b/64B) */ 3523 struct port_stats_ecn { 3524 __le64 mark_cnt_cos0; 3525 __le64 mark_cnt_cos1; 3526 __le64 mark_cnt_cos2; 3527 __le64 mark_cnt_cos3; 3528 __le64 mark_cnt_cos4; 3529 __le64 mark_cnt_cos5; 3530 __le64 mark_cnt_cos6; 3531 __le64 mark_cnt_cos7; 3532 }; 3533 3534 /* hwrm_port_clr_stats_input (size:192b/24B) */ 3535 struct hwrm_port_clr_stats_input { 3536 __le16 req_type; 3537 __le16 cmpl_ring; 3538 __le16 seq_id; 3539 __le16 target_id; 3540 __le64 resp_addr; 3541 __le16 port_id; 3542 u8 flags; 3543 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3544 u8 unused_0[5]; 3545 }; 3546 3547 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3548 struct hwrm_port_clr_stats_output { 3549 __le16 error_code; 3550 __le16 req_type; 3551 __le16 seq_id; 3552 __le16 resp_len; 3553 u8 unused_0[7]; 3554 u8 valid; 3555 }; 3556 3557 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3558 struct hwrm_port_lpbk_clr_stats_input { 3559 __le16 req_type; 3560 __le16 cmpl_ring; 3561 __le16 seq_id; 3562 __le16 target_id; 3563 __le64 resp_addr; 3564 }; 3565 3566 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3567 struct hwrm_port_lpbk_clr_stats_output { 3568 __le16 error_code; 3569 __le16 req_type; 3570 __le16 seq_id; 3571 __le16 resp_len; 3572 u8 unused_0[7]; 3573 u8 valid; 3574 }; 3575 3576 /* hwrm_port_ts_query_input (size:192b/24B) */ 3577 struct hwrm_port_ts_query_input { 3578 __le16 req_type; 3579 __le16 cmpl_ring; 3580 __le16 seq_id; 3581 __le16 target_id; 3582 __le64 resp_addr; 3583 __le32 flags; 3584 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3585 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3586 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3587 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3588 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3589 __le16 port_id; 3590 u8 unused_0[2]; 3591 }; 3592 3593 /* hwrm_port_ts_query_output (size:192b/24B) */ 3594 struct hwrm_port_ts_query_output { 3595 __le16 error_code; 3596 __le16 req_type; 3597 __le16 seq_id; 3598 __le16 resp_len; 3599 __le64 ptp_msg_ts; 3600 __le16 ptp_msg_seqid; 3601 u8 unused_0[5]; 3602 u8 valid; 3603 }; 3604 3605 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3606 struct hwrm_port_phy_qcaps_input { 3607 __le16 req_type; 3608 __le16 cmpl_ring; 3609 __le16 seq_id; 3610 __le16 target_id; 3611 __le64 resp_addr; 3612 __le16 port_id; 3613 u8 unused_0[6]; 3614 }; 3615 3616 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 3617 struct hwrm_port_phy_qcaps_output { 3618 __le16 error_code; 3619 __le16 req_type; 3620 __le16 seq_id; 3621 __le16 resp_len; 3622 u8 flags; 3623 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3624 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3625 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 3626 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3627 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 3628 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 3629 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 3630 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1 0x80UL 3631 u8 port_cnt; 3632 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3633 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3634 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3635 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3636 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3637 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3638 __le16 supported_speeds_force_mode; 3639 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3640 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3641 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3642 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3643 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3644 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3645 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3646 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3647 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3648 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3649 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3650 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3651 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3652 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3653 __le16 supported_speeds_auto_mode; 3654 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3655 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3656 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3657 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3658 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3659 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3660 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3661 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3662 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3663 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3664 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3665 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3666 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3667 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3668 __le16 supported_speeds_eee_mode; 3669 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3670 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3671 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3672 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3673 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3674 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3675 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3676 __le32 tx_lpi_timer_low; 3677 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3678 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3679 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3680 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3681 __le32 valid_tx_lpi_timer_high; 3682 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3683 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3684 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 3685 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 3686 __le16 supported_pam4_speeds_auto_mode; 3687 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 3688 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 3689 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 3690 __le16 supported_pam4_speeds_force_mode; 3691 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 3692 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 3693 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 3694 u8 unused_0[3]; 3695 u8 valid; 3696 }; 3697 3698 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3699 struct hwrm_port_phy_i2c_read_input { 3700 __le16 req_type; 3701 __le16 cmpl_ring; 3702 __le16 seq_id; 3703 __le16 target_id; 3704 __le64 resp_addr; 3705 __le32 flags; 3706 __le32 enables; 3707 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3708 __le16 port_id; 3709 u8 i2c_slave_addr; 3710 u8 unused_0; 3711 __le16 page_number; 3712 __le16 page_offset; 3713 u8 data_length; 3714 u8 unused_1[7]; 3715 }; 3716 3717 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3718 struct hwrm_port_phy_i2c_read_output { 3719 __le16 error_code; 3720 __le16 req_type; 3721 __le16 seq_id; 3722 __le16 resp_len; 3723 __le32 data[16]; 3724 u8 unused_0[7]; 3725 u8 valid; 3726 }; 3727 3728 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3729 struct hwrm_port_phy_mdio_write_input { 3730 __le16 req_type; 3731 __le16 cmpl_ring; 3732 __le16 seq_id; 3733 __le16 target_id; 3734 __le64 resp_addr; 3735 __le32 unused_0[2]; 3736 __le16 port_id; 3737 u8 phy_addr; 3738 u8 dev_addr; 3739 __le16 reg_addr; 3740 __le16 reg_data; 3741 u8 cl45_mdio; 3742 u8 unused_1[7]; 3743 }; 3744 3745 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3746 struct hwrm_port_phy_mdio_write_output { 3747 __le16 error_code; 3748 __le16 req_type; 3749 __le16 seq_id; 3750 __le16 resp_len; 3751 u8 unused_0[7]; 3752 u8 valid; 3753 }; 3754 3755 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3756 struct hwrm_port_phy_mdio_read_input { 3757 __le16 req_type; 3758 __le16 cmpl_ring; 3759 __le16 seq_id; 3760 __le16 target_id; 3761 __le64 resp_addr; 3762 __le32 unused_0[2]; 3763 __le16 port_id; 3764 u8 phy_addr; 3765 u8 dev_addr; 3766 __le16 reg_addr; 3767 u8 cl45_mdio; 3768 u8 unused_1; 3769 }; 3770 3771 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3772 struct hwrm_port_phy_mdio_read_output { 3773 __le16 error_code; 3774 __le16 req_type; 3775 __le16 seq_id; 3776 __le16 resp_len; 3777 __le16 reg_data; 3778 u8 unused_0[5]; 3779 u8 valid; 3780 }; 3781 3782 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3783 struct hwrm_port_led_cfg_input { 3784 __le16 req_type; 3785 __le16 cmpl_ring; 3786 __le16 seq_id; 3787 __le16 target_id; 3788 __le64 resp_addr; 3789 __le32 enables; 3790 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3791 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3792 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3793 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3794 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3795 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3796 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3797 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3798 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3799 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3800 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3801 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3802 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3803 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3804 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3805 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3806 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3807 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3808 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3809 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3810 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3811 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3812 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3813 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3814 __le16 port_id; 3815 u8 num_leds; 3816 u8 rsvd; 3817 u8 led0_id; 3818 u8 led0_state; 3819 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3820 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3821 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3822 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3823 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3824 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3825 u8 led0_color; 3826 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3827 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3828 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3829 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3830 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3831 u8 unused_0; 3832 __le16 led0_blink_on; 3833 __le16 led0_blink_off; 3834 u8 led0_group_id; 3835 u8 rsvd0; 3836 u8 led1_id; 3837 u8 led1_state; 3838 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3839 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3840 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3841 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3842 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3843 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3844 u8 led1_color; 3845 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3846 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3847 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3848 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3849 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3850 u8 unused_1; 3851 __le16 led1_blink_on; 3852 __le16 led1_blink_off; 3853 u8 led1_group_id; 3854 u8 rsvd1; 3855 u8 led2_id; 3856 u8 led2_state; 3857 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3858 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3859 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3860 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3861 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3862 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3863 u8 led2_color; 3864 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3865 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3866 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3867 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3868 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3869 u8 unused_2; 3870 __le16 led2_blink_on; 3871 __le16 led2_blink_off; 3872 u8 led2_group_id; 3873 u8 rsvd2; 3874 u8 led3_id; 3875 u8 led3_state; 3876 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3877 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3878 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3879 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3880 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3881 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3882 u8 led3_color; 3883 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3884 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3885 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3886 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3887 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3888 u8 unused_3; 3889 __le16 led3_blink_on; 3890 __le16 led3_blink_off; 3891 u8 led3_group_id; 3892 u8 rsvd3; 3893 }; 3894 3895 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3896 struct hwrm_port_led_cfg_output { 3897 __le16 error_code; 3898 __le16 req_type; 3899 __le16 seq_id; 3900 __le16 resp_len; 3901 u8 unused_0[7]; 3902 u8 valid; 3903 }; 3904 3905 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3906 struct hwrm_port_led_qcfg_input { 3907 __le16 req_type; 3908 __le16 cmpl_ring; 3909 __le16 seq_id; 3910 __le16 target_id; 3911 __le64 resp_addr; 3912 __le16 port_id; 3913 u8 unused_0[6]; 3914 }; 3915 3916 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3917 struct hwrm_port_led_qcfg_output { 3918 __le16 error_code; 3919 __le16 req_type; 3920 __le16 seq_id; 3921 __le16 resp_len; 3922 u8 num_leds; 3923 u8 led0_id; 3924 u8 led0_type; 3925 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3926 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3927 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3928 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3929 u8 led0_state; 3930 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3931 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3932 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3933 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3934 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3935 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3936 u8 led0_color; 3937 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3938 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3939 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3940 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3941 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3942 u8 unused_0; 3943 __le16 led0_blink_on; 3944 __le16 led0_blink_off; 3945 u8 led0_group_id; 3946 u8 led1_id; 3947 u8 led1_type; 3948 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3949 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3950 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3951 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3952 u8 led1_state; 3953 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3954 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3955 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3956 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3957 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3958 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3959 u8 led1_color; 3960 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3961 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3962 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3963 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3964 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3965 u8 unused_1; 3966 __le16 led1_blink_on; 3967 __le16 led1_blink_off; 3968 u8 led1_group_id; 3969 u8 led2_id; 3970 u8 led2_type; 3971 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3972 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3973 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3974 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3975 u8 led2_state; 3976 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3977 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3978 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3979 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3980 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3981 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3982 u8 led2_color; 3983 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3984 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3985 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3986 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3987 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3988 u8 unused_2; 3989 __le16 led2_blink_on; 3990 __le16 led2_blink_off; 3991 u8 led2_group_id; 3992 u8 led3_id; 3993 u8 led3_type; 3994 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3995 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3996 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3997 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3998 u8 led3_state; 3999 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4000 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4001 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4002 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4003 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4004 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4005 u8 led3_color; 4006 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4007 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4008 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4009 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4010 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4011 u8 unused_3; 4012 __le16 led3_blink_on; 4013 __le16 led3_blink_off; 4014 u8 led3_group_id; 4015 u8 unused_4[6]; 4016 u8 valid; 4017 }; 4018 4019 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4020 struct hwrm_port_led_qcaps_input { 4021 __le16 req_type; 4022 __le16 cmpl_ring; 4023 __le16 seq_id; 4024 __le16 target_id; 4025 __le64 resp_addr; 4026 __le16 port_id; 4027 u8 unused_0[6]; 4028 }; 4029 4030 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4031 struct hwrm_port_led_qcaps_output { 4032 __le16 error_code; 4033 __le16 req_type; 4034 __le16 seq_id; 4035 __le16 resp_len; 4036 u8 num_leds; 4037 u8 unused[3]; 4038 u8 led0_id; 4039 u8 led0_type; 4040 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4041 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4042 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4043 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4044 u8 led0_group_id; 4045 u8 unused_0; 4046 __le16 led0_state_caps; 4047 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4048 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4049 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4050 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4051 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4052 __le16 led0_color_caps; 4053 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4054 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4055 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4056 u8 led1_id; 4057 u8 led1_type; 4058 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4059 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4060 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4061 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4062 u8 led1_group_id; 4063 u8 unused_1; 4064 __le16 led1_state_caps; 4065 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4066 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4067 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4068 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4069 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4070 __le16 led1_color_caps; 4071 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4072 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4073 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4074 u8 led2_id; 4075 u8 led2_type; 4076 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4077 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4078 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4079 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4080 u8 led2_group_id; 4081 u8 unused_2; 4082 __le16 led2_state_caps; 4083 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4084 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4085 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4086 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4087 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4088 __le16 led2_color_caps; 4089 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4090 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4091 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4092 u8 led3_id; 4093 u8 led3_type; 4094 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4095 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4096 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4097 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4098 u8 led3_group_id; 4099 u8 unused_3; 4100 __le16 led3_state_caps; 4101 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4102 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4103 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4104 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4105 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4106 __le16 led3_color_caps; 4107 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4108 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4109 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4110 u8 unused_4[3]; 4111 u8 valid; 4112 }; 4113 4114 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4115 struct hwrm_queue_qportcfg_input { 4116 __le16 req_type; 4117 __le16 cmpl_ring; 4118 __le16 seq_id; 4119 __le16 target_id; 4120 __le64 resp_addr; 4121 __le32 flags; 4122 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4123 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4124 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4125 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4126 __le16 port_id; 4127 u8 drv_qmap_cap; 4128 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4129 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4130 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4131 u8 unused_0; 4132 }; 4133 4134 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4135 struct hwrm_queue_qportcfg_output { 4136 __le16 error_code; 4137 __le16 req_type; 4138 __le16 seq_id; 4139 __le16 resp_len; 4140 u8 max_configurable_queues; 4141 u8 max_configurable_lossless_queues; 4142 u8 queue_cfg_allowed; 4143 u8 queue_cfg_info; 4144 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4145 u8 queue_pfcenable_cfg_allowed; 4146 u8 queue_pri2cos_cfg_allowed; 4147 u8 queue_cos2bw_cfg_allowed; 4148 u8 queue_id0; 4149 u8 queue_id0_service_profile; 4150 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4151 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4152 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4153 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4154 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4155 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4156 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4157 u8 queue_id1; 4158 u8 queue_id1_service_profile; 4159 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4160 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4161 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4162 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4163 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4164 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4165 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4166 u8 queue_id2; 4167 u8 queue_id2_service_profile; 4168 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4169 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4170 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4171 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4172 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4173 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4174 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4175 u8 queue_id3; 4176 u8 queue_id3_service_profile; 4177 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4178 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4179 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4180 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4181 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4182 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4183 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4184 u8 queue_id4; 4185 u8 queue_id4_service_profile; 4186 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4187 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4188 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4189 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4190 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4191 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4192 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4193 u8 queue_id5; 4194 u8 queue_id5_service_profile; 4195 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4196 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4197 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4198 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4199 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4200 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4201 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4202 u8 queue_id6; 4203 u8 queue_id6_service_profile; 4204 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4205 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4206 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4207 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4209 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4211 u8 queue_id7; 4212 u8 queue_id7_service_profile; 4213 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4214 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4216 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4217 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4220 u8 queue_id0_service_profile_type; 4221 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4222 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4223 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4224 char qid0_name[16]; 4225 char qid1_name[16]; 4226 char qid2_name[16]; 4227 char qid3_name[16]; 4228 char qid4_name[16]; 4229 char qid5_name[16]; 4230 char qid6_name[16]; 4231 char qid7_name[16]; 4232 u8 queue_id1_service_profile_type; 4233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4236 u8 queue_id2_service_profile_type; 4237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4240 u8 queue_id3_service_profile_type; 4241 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4242 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4244 u8 queue_id4_service_profile_type; 4245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4246 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4248 u8 queue_id5_service_profile_type; 4249 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4250 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4251 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4252 u8 queue_id6_service_profile_type; 4253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4254 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4255 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4256 u8 queue_id7_service_profile_type; 4257 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4258 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4259 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4260 u8 valid; 4261 }; 4262 4263 /* hwrm_queue_qcfg_input (size:192b/24B) */ 4264 struct hwrm_queue_qcfg_input { 4265 __le16 req_type; 4266 __le16 cmpl_ring; 4267 __le16 seq_id; 4268 __le16 target_id; 4269 __le64 resp_addr; 4270 __le32 flags; 4271 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4272 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4273 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4274 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4275 __le32 queue_id; 4276 }; 4277 4278 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4279 struct hwrm_queue_qcfg_output { 4280 __le16 error_code; 4281 __le16 req_type; 4282 __le16 seq_id; 4283 __le16 resp_len; 4284 __le32 queue_len; 4285 u8 service_profile; 4286 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4287 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4288 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4289 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4290 u8 queue_cfg_info; 4291 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4292 u8 unused_0; 4293 u8 valid; 4294 }; 4295 4296 /* hwrm_queue_cfg_input (size:320b/40B) */ 4297 struct hwrm_queue_cfg_input { 4298 __le16 req_type; 4299 __le16 cmpl_ring; 4300 __le16 seq_id; 4301 __le16 target_id; 4302 __le64 resp_addr; 4303 __le32 flags; 4304 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4305 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4306 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4307 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4308 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4309 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4310 __le32 enables; 4311 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4312 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4313 __le32 queue_id; 4314 __le32 dflt_len; 4315 u8 service_profile; 4316 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4317 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4318 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4319 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4320 u8 unused_0[7]; 4321 }; 4322 4323 /* hwrm_queue_cfg_output (size:128b/16B) */ 4324 struct hwrm_queue_cfg_output { 4325 __le16 error_code; 4326 __le16 req_type; 4327 __le16 seq_id; 4328 __le16 resp_len; 4329 u8 unused_0[7]; 4330 u8 valid; 4331 }; 4332 4333 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 4334 struct hwrm_queue_pfcenable_qcfg_input { 4335 __le16 req_type; 4336 __le16 cmpl_ring; 4337 __le16 seq_id; 4338 __le16 target_id; 4339 __le64 resp_addr; 4340 __le16 port_id; 4341 u8 unused_0[6]; 4342 }; 4343 4344 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 4345 struct hwrm_queue_pfcenable_qcfg_output { 4346 __le16 error_code; 4347 __le16 req_type; 4348 __le16 seq_id; 4349 __le16 resp_len; 4350 __le32 flags; 4351 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 4352 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 4353 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 4354 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 4355 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 4356 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 4357 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 4358 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 4359 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4360 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4361 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4362 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4363 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4364 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4365 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4366 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4367 u8 unused_0[3]; 4368 u8 valid; 4369 }; 4370 4371 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 4372 struct hwrm_queue_pfcenable_cfg_input { 4373 __le16 req_type; 4374 __le16 cmpl_ring; 4375 __le16 seq_id; 4376 __le16 target_id; 4377 __le64 resp_addr; 4378 __le32 flags; 4379 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 4380 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 4381 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 4382 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 4383 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 4384 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 4385 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 4386 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 4387 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4388 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4389 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4390 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4391 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4392 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4393 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4394 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4395 __le16 port_id; 4396 u8 unused_0[2]; 4397 }; 4398 4399 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4400 struct hwrm_queue_pfcenable_cfg_output { 4401 __le16 error_code; 4402 __le16 req_type; 4403 __le16 seq_id; 4404 __le16 resp_len; 4405 u8 unused_0[7]; 4406 u8 valid; 4407 }; 4408 4409 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 4410 struct hwrm_queue_pri2cos_qcfg_input { 4411 __le16 req_type; 4412 __le16 cmpl_ring; 4413 __le16 seq_id; 4414 __le16 target_id; 4415 __le64 resp_addr; 4416 __le32 flags; 4417 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4418 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4419 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4420 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 4421 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 4422 u8 port_id; 4423 u8 unused_0[3]; 4424 }; 4425 4426 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 4427 struct hwrm_queue_pri2cos_qcfg_output { 4428 __le16 error_code; 4429 __le16 req_type; 4430 __le16 seq_id; 4431 __le16 resp_len; 4432 u8 pri0_cos_queue_id; 4433 u8 pri1_cos_queue_id; 4434 u8 pri2_cos_queue_id; 4435 u8 pri3_cos_queue_id; 4436 u8 pri4_cos_queue_id; 4437 u8 pri5_cos_queue_id; 4438 u8 pri6_cos_queue_id; 4439 u8 pri7_cos_queue_id; 4440 u8 queue_cfg_info; 4441 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4442 u8 unused_0[6]; 4443 u8 valid; 4444 }; 4445 4446 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4447 struct hwrm_queue_pri2cos_cfg_input { 4448 __le16 req_type; 4449 __le16 cmpl_ring; 4450 __le16 seq_id; 4451 __le16 target_id; 4452 __le64 resp_addr; 4453 __le32 flags; 4454 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4455 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4456 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4457 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4458 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4459 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4460 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4461 __le32 enables; 4462 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4463 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4464 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4465 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4466 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4467 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4468 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4469 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4470 u8 port_id; 4471 u8 pri0_cos_queue_id; 4472 u8 pri1_cos_queue_id; 4473 u8 pri2_cos_queue_id; 4474 u8 pri3_cos_queue_id; 4475 u8 pri4_cos_queue_id; 4476 u8 pri5_cos_queue_id; 4477 u8 pri6_cos_queue_id; 4478 u8 pri7_cos_queue_id; 4479 u8 unused_0[7]; 4480 }; 4481 4482 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4483 struct hwrm_queue_pri2cos_cfg_output { 4484 __le16 error_code; 4485 __le16 req_type; 4486 __le16 seq_id; 4487 __le16 resp_len; 4488 u8 unused_0[7]; 4489 u8 valid; 4490 }; 4491 4492 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 4493 struct hwrm_queue_cos2bw_qcfg_input { 4494 __le16 req_type; 4495 __le16 cmpl_ring; 4496 __le16 seq_id; 4497 __le16 target_id; 4498 __le64 resp_addr; 4499 __le16 port_id; 4500 u8 unused_0[6]; 4501 }; 4502 4503 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 4504 struct hwrm_queue_cos2bw_qcfg_output { 4505 __le16 error_code; 4506 __le16 req_type; 4507 __le16 seq_id; 4508 __le16 resp_len; 4509 u8 queue_id0; 4510 u8 unused_0; 4511 __le16 unused_1; 4512 __le32 queue_id0_min_bw; 4513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 4519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4528 __le32 queue_id0_max_bw; 4529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 4535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4541 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4542 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4544 u8 queue_id0_tsa_assign; 4545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4547 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4548 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4549 u8 queue_id0_pri_lvl; 4550 u8 queue_id0_bw_weight; 4551 u8 queue_id1; 4552 __le32 queue_id1_min_bw; 4553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 4559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4560 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4564 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4565 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4566 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4568 __le32 queue_id1_max_bw; 4569 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 4575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4584 u8 queue_id1_tsa_assign; 4585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4589 u8 queue_id1_pri_lvl; 4590 u8 queue_id1_bw_weight; 4591 u8 queue_id2; 4592 __le32 queue_id2_min_bw; 4593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4608 __le32 queue_id2_max_bw; 4609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4624 u8 queue_id2_tsa_assign; 4625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4629 u8 queue_id2_pri_lvl; 4630 u8 queue_id2_bw_weight; 4631 u8 queue_id3; 4632 __le32 queue_id3_min_bw; 4633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4648 __le32 queue_id3_max_bw; 4649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4664 u8 queue_id3_tsa_assign; 4665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4669 u8 queue_id3_pri_lvl; 4670 u8 queue_id3_bw_weight; 4671 u8 queue_id4; 4672 __le32 queue_id4_min_bw; 4673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4688 __le32 queue_id4_max_bw; 4689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4704 u8 queue_id4_tsa_assign; 4705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4709 u8 queue_id4_pri_lvl; 4710 u8 queue_id4_bw_weight; 4711 u8 queue_id5; 4712 __le32 queue_id5_min_bw; 4713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4728 __le32 queue_id5_max_bw; 4729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4744 u8 queue_id5_tsa_assign; 4745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4749 u8 queue_id5_pri_lvl; 4750 u8 queue_id5_bw_weight; 4751 u8 queue_id6; 4752 __le32 queue_id6_min_bw; 4753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4768 __le32 queue_id6_max_bw; 4769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4784 u8 queue_id6_tsa_assign; 4785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4789 u8 queue_id6_pri_lvl; 4790 u8 queue_id6_bw_weight; 4791 u8 queue_id7; 4792 __le32 queue_id7_min_bw; 4793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4808 __le32 queue_id7_max_bw; 4809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4824 u8 queue_id7_tsa_assign; 4825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4829 u8 queue_id7_pri_lvl; 4830 u8 queue_id7_bw_weight; 4831 u8 unused_2[4]; 4832 u8 valid; 4833 }; 4834 4835 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4836 struct hwrm_queue_cos2bw_cfg_input { 4837 __le16 req_type; 4838 __le16 cmpl_ring; 4839 __le16 seq_id; 4840 __le16 target_id; 4841 __le64 resp_addr; 4842 __le32 flags; 4843 __le32 enables; 4844 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4845 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4846 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4847 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4848 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4849 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4850 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4851 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4852 __le16 port_id; 4853 u8 queue_id0; 4854 u8 unused_0; 4855 __le32 queue_id0_min_bw; 4856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4871 __le32 queue_id0_max_bw; 4872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4885 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4887 u8 queue_id0_tsa_assign; 4888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4892 u8 queue_id0_pri_lvl; 4893 u8 queue_id0_bw_weight; 4894 u8 queue_id1; 4895 __le32 queue_id1_min_bw; 4896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4903 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4911 __le32 queue_id1_max_bw; 4912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4927 u8 queue_id1_tsa_assign; 4928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4932 u8 queue_id1_pri_lvl; 4933 u8 queue_id1_bw_weight; 4934 u8 queue_id2; 4935 __le32 queue_id2_min_bw; 4936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4951 __le32 queue_id2_max_bw; 4952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4967 u8 queue_id2_tsa_assign; 4968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4972 u8 queue_id2_pri_lvl; 4973 u8 queue_id2_bw_weight; 4974 u8 queue_id3; 4975 __le32 queue_id3_min_bw; 4976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4991 __le32 queue_id3_max_bw; 4992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5007 u8 queue_id3_tsa_assign; 5008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5012 u8 queue_id3_pri_lvl; 5013 u8 queue_id3_bw_weight; 5014 u8 queue_id4; 5015 __le32 queue_id4_min_bw; 5016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5031 __le32 queue_id4_max_bw; 5032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5047 u8 queue_id4_tsa_assign; 5048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5052 u8 queue_id4_pri_lvl; 5053 u8 queue_id4_bw_weight; 5054 u8 queue_id5; 5055 __le32 queue_id5_min_bw; 5056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5071 __le32 queue_id5_max_bw; 5072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5087 u8 queue_id5_tsa_assign; 5088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5092 u8 queue_id5_pri_lvl; 5093 u8 queue_id5_bw_weight; 5094 u8 queue_id6; 5095 __le32 queue_id6_min_bw; 5096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5111 __le32 queue_id6_max_bw; 5112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5127 u8 queue_id6_tsa_assign; 5128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5132 u8 queue_id6_pri_lvl; 5133 u8 queue_id6_bw_weight; 5134 u8 queue_id7; 5135 __le32 queue_id7_min_bw; 5136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5151 __le32 queue_id7_max_bw; 5152 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5157 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5167 u8 queue_id7_tsa_assign; 5168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5172 u8 queue_id7_pri_lvl; 5173 u8 queue_id7_bw_weight; 5174 u8 unused_1[5]; 5175 }; 5176 5177 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5178 struct hwrm_queue_cos2bw_cfg_output { 5179 __le16 error_code; 5180 __le16 req_type; 5181 __le16 seq_id; 5182 __le16 resp_len; 5183 u8 unused_0[7]; 5184 u8 valid; 5185 }; 5186 5187 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5188 struct hwrm_queue_dscp_qcaps_input { 5189 __le16 req_type; 5190 __le16 cmpl_ring; 5191 __le16 seq_id; 5192 __le16 target_id; 5193 __le64 resp_addr; 5194 u8 port_id; 5195 u8 unused_0[7]; 5196 }; 5197 5198 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5199 struct hwrm_queue_dscp_qcaps_output { 5200 __le16 error_code; 5201 __le16 req_type; 5202 __le16 seq_id; 5203 __le16 resp_len; 5204 u8 num_dscp_bits; 5205 u8 unused_0; 5206 __le16 max_entries; 5207 u8 unused_1[3]; 5208 u8 valid; 5209 }; 5210 5211 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5212 struct hwrm_queue_dscp2pri_qcfg_input { 5213 __le16 req_type; 5214 __le16 cmpl_ring; 5215 __le16 seq_id; 5216 __le16 target_id; 5217 __le64 resp_addr; 5218 __le64 dest_data_addr; 5219 u8 port_id; 5220 u8 unused_0; 5221 __le16 dest_data_buffer_size; 5222 u8 unused_1[4]; 5223 }; 5224 5225 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5226 struct hwrm_queue_dscp2pri_qcfg_output { 5227 __le16 error_code; 5228 __le16 req_type; 5229 __le16 seq_id; 5230 __le16 resp_len; 5231 __le16 entry_cnt; 5232 u8 default_pri; 5233 u8 unused_0[4]; 5234 u8 valid; 5235 }; 5236 5237 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5238 struct hwrm_queue_dscp2pri_cfg_input { 5239 __le16 req_type; 5240 __le16 cmpl_ring; 5241 __le16 seq_id; 5242 __le16 target_id; 5243 __le64 resp_addr; 5244 __le64 src_data_addr; 5245 __le32 flags; 5246 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5247 __le32 enables; 5248 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5249 u8 port_id; 5250 u8 default_pri; 5251 __le16 entry_cnt; 5252 u8 unused_0[4]; 5253 }; 5254 5255 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5256 struct hwrm_queue_dscp2pri_cfg_output { 5257 __le16 error_code; 5258 __le16 req_type; 5259 __le16 seq_id; 5260 __le16 resp_len; 5261 u8 unused_0[7]; 5262 u8 valid; 5263 }; 5264 5265 /* hwrm_vnic_alloc_input (size:192b/24B) */ 5266 struct hwrm_vnic_alloc_input { 5267 __le16 req_type; 5268 __le16 cmpl_ring; 5269 __le16 seq_id; 5270 __le16 target_id; 5271 __le64 resp_addr; 5272 __le32 flags; 5273 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5274 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5275 __le16 virtio_net_fid; 5276 u8 unused_0[2]; 5277 }; 5278 5279 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5280 struct hwrm_vnic_alloc_output { 5281 __le16 error_code; 5282 __le16 req_type; 5283 __le16 seq_id; 5284 __le16 resp_len; 5285 __le32 vnic_id; 5286 u8 unused_0[3]; 5287 u8 valid; 5288 }; 5289 5290 /* hwrm_vnic_free_input (size:192b/24B) */ 5291 struct hwrm_vnic_free_input { 5292 __le16 req_type; 5293 __le16 cmpl_ring; 5294 __le16 seq_id; 5295 __le16 target_id; 5296 __le64 resp_addr; 5297 __le32 vnic_id; 5298 u8 unused_0[4]; 5299 }; 5300 5301 /* hwrm_vnic_free_output (size:128b/16B) */ 5302 struct hwrm_vnic_free_output { 5303 __le16 error_code; 5304 __le16 req_type; 5305 __le16 seq_id; 5306 __le16 resp_len; 5307 u8 unused_0[7]; 5308 u8 valid; 5309 }; 5310 5311 /* hwrm_vnic_cfg_input (size:384b/48B) */ 5312 struct hwrm_vnic_cfg_input { 5313 __le16 req_type; 5314 __le16 cmpl_ring; 5315 __le16 seq_id; 5316 __le16 target_id; 5317 __le64 resp_addr; 5318 __le32 flags; 5319 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5320 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5321 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 5322 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 5323 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5324 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 5325 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5326 __le32 enables; 5327 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5328 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5329 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5330 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5331 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 5332 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 5333 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 5334 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5335 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5336 __le16 vnic_id; 5337 __le16 dflt_ring_grp; 5338 __le16 rss_rule; 5339 __le16 cos_rule; 5340 __le16 lb_rule; 5341 __le16 mru; 5342 __le16 default_rx_ring_id; 5343 __le16 default_cmpl_ring_id; 5344 __le16 queue_id; 5345 u8 rx_csum_v2_mode; 5346 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 5347 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 5348 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 5349 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 5350 u8 unused0[5]; 5351 }; 5352 5353 /* hwrm_vnic_cfg_output (size:128b/16B) */ 5354 struct hwrm_vnic_cfg_output { 5355 __le16 error_code; 5356 __le16 req_type; 5357 __le16 seq_id; 5358 __le16 resp_len; 5359 u8 unused_0[7]; 5360 u8 valid; 5361 }; 5362 5363 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 5364 struct hwrm_vnic_qcaps_input { 5365 __le16 req_type; 5366 __le16 cmpl_ring; 5367 __le16 seq_id; 5368 __le16 target_id; 5369 __le64 resp_addr; 5370 __le32 enables; 5371 u8 unused_0[4]; 5372 }; 5373 5374 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 5375 struct hwrm_vnic_qcaps_output { 5376 __le16 error_code; 5377 __le16 req_type; 5378 __le16 seq_id; 5379 __le16 resp_len; 5380 __le16 mru; 5381 u8 unused_0[2]; 5382 __le32 flags; 5383 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 5384 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 5385 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 5386 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 5387 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 5388 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 5389 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 5390 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 5391 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5392 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5393 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 5394 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 5395 __le16 max_aggs_supported; 5396 u8 unused_1[5]; 5397 u8 valid; 5398 }; 5399 5400 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 5401 struct hwrm_vnic_tpa_cfg_input { 5402 __le16 req_type; 5403 __le16 cmpl_ring; 5404 __le16 seq_id; 5405 __le16 target_id; 5406 __le64 resp_addr; 5407 __le32 flags; 5408 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5409 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5410 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5411 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5412 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5413 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5414 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5415 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 5416 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5417 __le32 enables; 5418 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5419 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5420 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5421 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5422 __le16 vnic_id; 5423 __le16 max_agg_segs; 5424 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5425 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5426 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5427 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5428 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5429 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5430 __le16 max_aggs; 5431 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5432 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5433 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5434 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5435 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5436 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5437 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5438 u8 unused_0[2]; 5439 __le32 max_agg_timer; 5440 __le32 min_agg_len; 5441 }; 5442 5443 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5444 struct hwrm_vnic_tpa_cfg_output { 5445 __le16 error_code; 5446 __le16 req_type; 5447 __le16 seq_id; 5448 __le16 resp_len; 5449 u8 unused_0[7]; 5450 u8 valid; 5451 }; 5452 5453 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5454 struct hwrm_vnic_tpa_qcfg_input { 5455 __le16 req_type; 5456 __le16 cmpl_ring; 5457 __le16 seq_id; 5458 __le16 target_id; 5459 __le64 resp_addr; 5460 __le16 vnic_id; 5461 u8 unused_0[6]; 5462 }; 5463 5464 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5465 struct hwrm_vnic_tpa_qcfg_output { 5466 __le16 error_code; 5467 __le16 req_type; 5468 __le16 seq_id; 5469 __le16 resp_len; 5470 __le32 flags; 5471 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5472 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5473 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5474 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5475 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5476 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5477 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5478 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5479 __le16 max_agg_segs; 5480 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5481 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5482 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5483 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5484 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5485 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5486 __le16 max_aggs; 5487 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5488 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5489 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5490 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5491 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5492 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5493 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5494 __le32 max_agg_timer; 5495 __le32 min_agg_len; 5496 u8 unused_0[7]; 5497 u8 valid; 5498 }; 5499 5500 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5501 struct hwrm_vnic_rss_cfg_input { 5502 __le16 req_type; 5503 __le16 cmpl_ring; 5504 __le16 seq_id; 5505 __le16 target_id; 5506 __le64 resp_addr; 5507 __le32 hash_type; 5508 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5509 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5510 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5511 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5512 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5513 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 5514 __le16 vnic_id; 5515 u8 ring_table_pair_index; 5516 u8 hash_mode_flags; 5517 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 5518 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 5519 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 5520 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 5521 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5522 __le64 ring_grp_tbl_addr; 5523 __le64 hash_key_tbl_addr; 5524 __le16 rss_ctx_idx; 5525 u8 unused_1[6]; 5526 }; 5527 5528 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5529 struct hwrm_vnic_rss_cfg_output { 5530 __le16 error_code; 5531 __le16 req_type; 5532 __le16 seq_id; 5533 __le16 resp_len; 5534 u8 unused_0[7]; 5535 u8 valid; 5536 }; 5537 5538 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 5539 struct hwrm_vnic_rss_cfg_cmd_err { 5540 u8 code; 5541 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 5542 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 5543 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 5544 u8 unused_0[7]; 5545 }; 5546 5547 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5548 struct hwrm_vnic_plcmodes_cfg_input { 5549 __le16 req_type; 5550 __le16 cmpl_ring; 5551 __le16 seq_id; 5552 __le16 target_id; 5553 __le64 resp_addr; 5554 __le32 flags; 5555 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5556 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5557 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5558 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5559 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5560 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5561 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 5562 __le32 enables; 5563 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5564 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5565 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5566 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 5567 __le32 vnic_id; 5568 __le16 jumbo_thresh; 5569 __le16 hds_offset; 5570 __le16 hds_threshold; 5571 __le16 max_bds; 5572 u8 unused_0[4]; 5573 }; 5574 5575 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5576 struct hwrm_vnic_plcmodes_cfg_output { 5577 __le16 error_code; 5578 __le16 req_type; 5579 __le16 seq_id; 5580 __le16 resp_len; 5581 u8 unused_0[7]; 5582 u8 valid; 5583 }; 5584 5585 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5586 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5587 __le16 req_type; 5588 __le16 cmpl_ring; 5589 __le16 seq_id; 5590 __le16 target_id; 5591 __le64 resp_addr; 5592 }; 5593 5594 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5595 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5596 __le16 error_code; 5597 __le16 req_type; 5598 __le16 seq_id; 5599 __le16 resp_len; 5600 __le16 rss_cos_lb_ctx_id; 5601 u8 unused_0[5]; 5602 u8 valid; 5603 }; 5604 5605 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5606 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5607 __le16 req_type; 5608 __le16 cmpl_ring; 5609 __le16 seq_id; 5610 __le16 target_id; 5611 __le64 resp_addr; 5612 __le16 rss_cos_lb_ctx_id; 5613 u8 unused_0[6]; 5614 }; 5615 5616 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5617 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5618 __le16 error_code; 5619 __le16 req_type; 5620 __le16 seq_id; 5621 __le16 resp_len; 5622 u8 unused_0[7]; 5623 u8 valid; 5624 }; 5625 5626 /* hwrm_ring_alloc_input (size:704b/88B) */ 5627 struct hwrm_ring_alloc_input { 5628 __le16 req_type; 5629 __le16 cmpl_ring; 5630 __le16 seq_id; 5631 __le16 target_id; 5632 __le64 resp_addr; 5633 __le32 enables; 5634 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5635 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5636 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5637 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5638 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5639 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5640 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 5641 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 5642 u8 ring_type; 5643 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5644 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5645 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5646 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5647 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5648 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5649 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5650 u8 unused_0; 5651 __le16 flags; 5652 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5653 __le64 page_tbl_addr; 5654 __le32 fbo; 5655 u8 page_size; 5656 u8 page_tbl_depth; 5657 __le16 schq_id; 5658 __le32 length; 5659 __le16 logical_id; 5660 __le16 cmpl_ring_id; 5661 __le16 queue_id; 5662 __le16 rx_buf_size; 5663 __le16 rx_ring_id; 5664 __le16 nq_ring_id; 5665 __le16 ring_arb_cfg; 5666 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5667 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5668 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5669 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5670 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5671 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5672 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5673 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5674 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5675 __le16 unused_3; 5676 __le32 reserved3; 5677 __le32 stat_ctx_id; 5678 __le32 reserved4; 5679 __le32 max_bw; 5680 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5681 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5682 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5683 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5684 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5685 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5686 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5687 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5688 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5689 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5690 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5691 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5692 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5693 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5694 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5695 u8 int_mode; 5696 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5697 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5698 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5699 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5700 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5701 u8 mpc_chnls_type; 5702 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 5703 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 5704 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 5705 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 5706 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 5707 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 5708 u8 unused_4[2]; 5709 __le64 cq_handle; 5710 }; 5711 5712 /* hwrm_ring_alloc_output (size:128b/16B) */ 5713 struct hwrm_ring_alloc_output { 5714 __le16 error_code; 5715 __le16 req_type; 5716 __le16 seq_id; 5717 __le16 resp_len; 5718 __le16 ring_id; 5719 __le16 logical_ring_id; 5720 u8 push_buffer_index; 5721 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5722 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5723 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5724 u8 unused_0[2]; 5725 u8 valid; 5726 }; 5727 5728 /* hwrm_ring_free_input (size:192b/24B) */ 5729 struct hwrm_ring_free_input { 5730 __le16 req_type; 5731 __le16 cmpl_ring; 5732 __le16 seq_id; 5733 __le16 target_id; 5734 __le64 resp_addr; 5735 u8 ring_type; 5736 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5737 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5738 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5739 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5740 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5741 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5742 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5743 u8 unused_0; 5744 __le16 ring_id; 5745 u8 unused_1[4]; 5746 }; 5747 5748 /* hwrm_ring_free_output (size:128b/16B) */ 5749 struct hwrm_ring_free_output { 5750 __le16 error_code; 5751 __le16 req_type; 5752 __le16 seq_id; 5753 __le16 resp_len; 5754 u8 unused_0[7]; 5755 u8 valid; 5756 }; 5757 5758 /* hwrm_ring_reset_input (size:192b/24B) */ 5759 struct hwrm_ring_reset_input { 5760 __le16 req_type; 5761 __le16 cmpl_ring; 5762 __le16 seq_id; 5763 __le16 target_id; 5764 __le64 resp_addr; 5765 u8 ring_type; 5766 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5767 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5768 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5769 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5770 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 5771 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 5772 u8 unused_0; 5773 __le16 ring_id; 5774 u8 unused_1[4]; 5775 }; 5776 5777 /* hwrm_ring_reset_output (size:128b/16B) */ 5778 struct hwrm_ring_reset_output { 5779 __le16 error_code; 5780 __le16 req_type; 5781 __le16 seq_id; 5782 __le16 resp_len; 5783 u8 push_buffer_index; 5784 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5785 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5786 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5787 u8 unused_0[3]; 5788 u8 consumer_idx[3]; 5789 u8 valid; 5790 }; 5791 5792 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5793 struct hwrm_ring_aggint_qcaps_input { 5794 __le16 req_type; 5795 __le16 cmpl_ring; 5796 __le16 seq_id; 5797 __le16 target_id; 5798 __le64 resp_addr; 5799 }; 5800 5801 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5802 struct hwrm_ring_aggint_qcaps_output { 5803 __le16 error_code; 5804 __le16 req_type; 5805 __le16 seq_id; 5806 __le16 resp_len; 5807 __le32 cmpl_params; 5808 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5809 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5810 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5811 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5812 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5813 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5814 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5815 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5816 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5817 __le32 nq_params; 5818 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5819 __le16 num_cmpl_dma_aggr_min; 5820 __le16 num_cmpl_dma_aggr_max; 5821 __le16 num_cmpl_dma_aggr_during_int_min; 5822 __le16 num_cmpl_dma_aggr_during_int_max; 5823 __le16 cmpl_aggr_dma_tmr_min; 5824 __le16 cmpl_aggr_dma_tmr_max; 5825 __le16 cmpl_aggr_dma_tmr_during_int_min; 5826 __le16 cmpl_aggr_dma_tmr_during_int_max; 5827 __le16 int_lat_tmr_min_min; 5828 __le16 int_lat_tmr_min_max; 5829 __le16 int_lat_tmr_max_min; 5830 __le16 int_lat_tmr_max_max; 5831 __le16 num_cmpl_aggr_int_min; 5832 __le16 num_cmpl_aggr_int_max; 5833 __le16 timer_units; 5834 u8 unused_0[1]; 5835 u8 valid; 5836 }; 5837 5838 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5839 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5840 __le16 req_type; 5841 __le16 cmpl_ring; 5842 __le16 seq_id; 5843 __le16 target_id; 5844 __le64 resp_addr; 5845 __le16 ring_id; 5846 __le16 flags; 5847 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5848 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5849 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5850 u8 unused_0[4]; 5851 }; 5852 5853 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5854 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5855 __le16 error_code; 5856 __le16 req_type; 5857 __le16 seq_id; 5858 __le16 resp_len; 5859 __le16 flags; 5860 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5861 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5862 __le16 num_cmpl_dma_aggr; 5863 __le16 num_cmpl_dma_aggr_during_int; 5864 __le16 cmpl_aggr_dma_tmr; 5865 __le16 cmpl_aggr_dma_tmr_during_int; 5866 __le16 int_lat_tmr_min; 5867 __le16 int_lat_tmr_max; 5868 __le16 num_cmpl_aggr_int; 5869 u8 unused_0[7]; 5870 u8 valid; 5871 }; 5872 5873 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5874 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5875 __le16 req_type; 5876 __le16 cmpl_ring; 5877 __le16 seq_id; 5878 __le16 target_id; 5879 __le64 resp_addr; 5880 __le16 ring_id; 5881 __le16 flags; 5882 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5883 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5884 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5885 __le16 num_cmpl_dma_aggr; 5886 __le16 num_cmpl_dma_aggr_during_int; 5887 __le16 cmpl_aggr_dma_tmr; 5888 __le16 cmpl_aggr_dma_tmr_during_int; 5889 __le16 int_lat_tmr_min; 5890 __le16 int_lat_tmr_max; 5891 __le16 num_cmpl_aggr_int; 5892 __le16 enables; 5893 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5894 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5895 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5896 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5897 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5898 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5899 u8 unused_0[4]; 5900 }; 5901 5902 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5903 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5904 __le16 error_code; 5905 __le16 req_type; 5906 __le16 seq_id; 5907 __le16 resp_len; 5908 u8 unused_0[7]; 5909 u8 valid; 5910 }; 5911 5912 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5913 struct hwrm_ring_grp_alloc_input { 5914 __le16 req_type; 5915 __le16 cmpl_ring; 5916 __le16 seq_id; 5917 __le16 target_id; 5918 __le64 resp_addr; 5919 __le16 cr; 5920 __le16 rr; 5921 __le16 ar; 5922 __le16 sc; 5923 }; 5924 5925 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5926 struct hwrm_ring_grp_alloc_output { 5927 __le16 error_code; 5928 __le16 req_type; 5929 __le16 seq_id; 5930 __le16 resp_len; 5931 __le32 ring_group_id; 5932 u8 unused_0[3]; 5933 u8 valid; 5934 }; 5935 5936 /* hwrm_ring_grp_free_input (size:192b/24B) */ 5937 struct hwrm_ring_grp_free_input { 5938 __le16 req_type; 5939 __le16 cmpl_ring; 5940 __le16 seq_id; 5941 __le16 target_id; 5942 __le64 resp_addr; 5943 __le32 ring_group_id; 5944 u8 unused_0[4]; 5945 }; 5946 5947 /* hwrm_ring_grp_free_output (size:128b/16B) */ 5948 struct hwrm_ring_grp_free_output { 5949 __le16 error_code; 5950 __le16 req_type; 5951 __le16 seq_id; 5952 __le16 resp_len; 5953 u8 unused_0[7]; 5954 u8 valid; 5955 }; 5956 5957 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5958 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5959 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5960 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5961 5962 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5963 struct hwrm_cfa_l2_filter_alloc_input { 5964 __le16 req_type; 5965 __le16 cmpl_ring; 5966 __le16 seq_id; 5967 __le16 target_id; 5968 __le64 resp_addr; 5969 __le32 flags; 5970 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5971 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5972 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5973 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5974 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5975 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5976 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5977 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5978 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5979 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5980 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5981 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5982 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5983 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5984 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5985 __le32 enables; 5986 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5987 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5988 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5989 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5990 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5991 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5992 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5993 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5994 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5995 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5996 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5997 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5998 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5999 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6000 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6001 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6002 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6003 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 6004 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6005 u8 l2_addr[6]; 6006 u8 num_vlans; 6007 u8 t_num_vlans; 6008 u8 l2_addr_mask[6]; 6009 __le16 l2_ovlan; 6010 __le16 l2_ovlan_mask; 6011 __le16 l2_ivlan; 6012 __le16 l2_ivlan_mask; 6013 u8 unused_1[2]; 6014 u8 t_l2_addr[6]; 6015 u8 unused_2[2]; 6016 u8 t_l2_addr_mask[6]; 6017 __le16 t_l2_ovlan; 6018 __le16 t_l2_ovlan_mask; 6019 __le16 t_l2_ivlan; 6020 __le16 t_l2_ivlan_mask; 6021 u8 src_type; 6022 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6023 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6024 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6025 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6026 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6027 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6028 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6029 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6030 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6031 u8 unused_3; 6032 __le32 src_id; 6033 u8 tunnel_type; 6034 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6035 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6036 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6037 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6038 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6039 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6040 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6041 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6042 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6043 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6044 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6045 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6046 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6047 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6048 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6049 u8 unused_4; 6050 __le16 dst_id; 6051 __le16 mirror_vnic_id; 6052 u8 pri_hint; 6053 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6054 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6055 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6056 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6057 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6058 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6059 u8 unused_5; 6060 __le32 unused_6; 6061 __le64 l2_filter_id_hint; 6062 }; 6063 6064 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6065 struct hwrm_cfa_l2_filter_alloc_output { 6066 __le16 error_code; 6067 __le16 req_type; 6068 __le16 seq_id; 6069 __le16 resp_len; 6070 __le64 l2_filter_id; 6071 __le32 flow_id; 6072 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6073 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6074 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6075 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6076 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6077 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6078 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6079 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6080 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6081 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6082 u8 unused_0[3]; 6083 u8 valid; 6084 }; 6085 6086 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6087 struct hwrm_cfa_l2_filter_free_input { 6088 __le16 req_type; 6089 __le16 cmpl_ring; 6090 __le16 seq_id; 6091 __le16 target_id; 6092 __le64 resp_addr; 6093 __le64 l2_filter_id; 6094 }; 6095 6096 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6097 struct hwrm_cfa_l2_filter_free_output { 6098 __le16 error_code; 6099 __le16 req_type; 6100 __le16 seq_id; 6101 __le16 resp_len; 6102 u8 unused_0[7]; 6103 u8 valid; 6104 }; 6105 6106 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6107 struct hwrm_cfa_l2_filter_cfg_input { 6108 __le16 req_type; 6109 __le16 cmpl_ring; 6110 __le16 seq_id; 6111 __le16 target_id; 6112 __le64 resp_addr; 6113 __le32 flags; 6114 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6115 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6116 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 6117 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6118 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 6119 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 6120 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 6121 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 6122 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 6123 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 6124 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6125 __le32 enables; 6126 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6127 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6128 __le64 l2_filter_id; 6129 __le32 dst_id; 6130 __le32 new_mirror_vnic_id; 6131 }; 6132 6133 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6134 struct hwrm_cfa_l2_filter_cfg_output { 6135 __le16 error_code; 6136 __le16 req_type; 6137 __le16 seq_id; 6138 __le16 resp_len; 6139 u8 unused_0[7]; 6140 u8 valid; 6141 }; 6142 6143 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6144 struct hwrm_cfa_l2_set_rx_mask_input { 6145 __le16 req_type; 6146 __le16 cmpl_ring; 6147 __le16 seq_id; 6148 __le16 target_id; 6149 __le64 resp_addr; 6150 __le32 vnic_id; 6151 __le32 mask; 6152 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6153 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6154 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6155 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6156 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6157 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6158 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6159 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6160 __le64 mc_tbl_addr; 6161 __le32 num_mc_entries; 6162 u8 unused_0[4]; 6163 __le64 vlan_tag_tbl_addr; 6164 __le32 num_vlan_tags; 6165 u8 unused_1[4]; 6166 }; 6167 6168 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6169 struct hwrm_cfa_l2_set_rx_mask_output { 6170 __le16 error_code; 6171 __le16 req_type; 6172 __le16 seq_id; 6173 __le16 resp_len; 6174 u8 unused_0[7]; 6175 u8 valid; 6176 }; 6177 6178 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6179 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6180 u8 code; 6181 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6182 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6183 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6184 u8 unused_0[7]; 6185 }; 6186 6187 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6188 struct hwrm_cfa_tunnel_filter_alloc_input { 6189 __le16 req_type; 6190 __le16 cmpl_ring; 6191 __le16 seq_id; 6192 __le16 target_id; 6193 __le64 resp_addr; 6194 __le32 flags; 6195 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6196 __le32 enables; 6197 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6198 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6199 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6200 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6201 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6202 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6203 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6204 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6205 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6206 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6207 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6208 __le64 l2_filter_id; 6209 u8 l2_addr[6]; 6210 __le16 l2_ivlan; 6211 __le32 l3_addr[4]; 6212 __le32 t_l3_addr[4]; 6213 u8 l3_addr_type; 6214 u8 t_l3_addr_type; 6215 u8 tunnel_type; 6216 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6217 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6218 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6219 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6220 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6221 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6222 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6223 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6224 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6225 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6226 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6227 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6228 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6229 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6230 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6231 u8 tunnel_flags; 6232 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6233 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6234 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6235 __le32 vni; 6236 __le32 dst_vnic_id; 6237 __le32 mirror_vnic_id; 6238 }; 6239 6240 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6241 struct hwrm_cfa_tunnel_filter_alloc_output { 6242 __le16 error_code; 6243 __le16 req_type; 6244 __le16 seq_id; 6245 __le16 resp_len; 6246 __le64 tunnel_filter_id; 6247 __le32 flow_id; 6248 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6249 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6250 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6251 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6252 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6253 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6254 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6255 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6256 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6257 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6258 u8 unused_0[3]; 6259 u8 valid; 6260 }; 6261 6262 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6263 struct hwrm_cfa_tunnel_filter_free_input { 6264 __le16 req_type; 6265 __le16 cmpl_ring; 6266 __le16 seq_id; 6267 __le16 target_id; 6268 __le64 resp_addr; 6269 __le64 tunnel_filter_id; 6270 }; 6271 6272 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6273 struct hwrm_cfa_tunnel_filter_free_output { 6274 __le16 error_code; 6275 __le16 req_type; 6276 __le16 seq_id; 6277 __le16 resp_len; 6278 u8 unused_0[7]; 6279 u8 valid; 6280 }; 6281 6282 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6283 struct hwrm_vxlan_ipv4_hdr { 6284 u8 ver_hlen; 6285 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6286 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6287 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6288 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6289 u8 tos; 6290 __be16 ip_id; 6291 __be16 flags_frag_offset; 6292 u8 ttl; 6293 u8 protocol; 6294 __be32 src_ip_addr; 6295 __be32 dest_ip_addr; 6296 }; 6297 6298 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6299 struct hwrm_vxlan_ipv6_hdr { 6300 __be32 ver_tc_flow_label; 6301 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6302 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6303 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6304 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6305 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6306 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6307 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6308 __be16 payload_len; 6309 u8 next_hdr; 6310 u8 ttl; 6311 __be32 src_ip_addr[4]; 6312 __be32 dest_ip_addr[4]; 6313 }; 6314 6315 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6316 struct hwrm_cfa_encap_data_vxlan { 6317 u8 src_mac_addr[6]; 6318 __le16 unused_0; 6319 u8 dst_mac_addr[6]; 6320 u8 num_vlan_tags; 6321 u8 unused_1; 6322 __be16 ovlan_tpid; 6323 __be16 ovlan_tci; 6324 __be16 ivlan_tpid; 6325 __be16 ivlan_tci; 6326 __le32 l3[10]; 6327 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6328 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6329 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6330 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6331 __be16 src_port; 6332 __be16 dst_port; 6333 __be32 vni; 6334 u8 hdr_rsvd0[3]; 6335 u8 hdr_rsvd1; 6336 u8 hdr_flags; 6337 u8 unused[3]; 6338 }; 6339 6340 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 6341 struct hwrm_cfa_encap_record_alloc_input { 6342 __le16 req_type; 6343 __le16 cmpl_ring; 6344 __le16 seq_id; 6345 __le16 target_id; 6346 __le64 resp_addr; 6347 __le32 flags; 6348 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6349 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 6350 u8 encap_type; 6351 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 6352 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 6353 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 6354 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 6355 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 6356 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 6357 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 6358 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 6359 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 6360 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 6361 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 6362 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 6363 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 6364 u8 unused_0[3]; 6365 __le32 encap_data[20]; 6366 }; 6367 6368 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 6369 struct hwrm_cfa_encap_record_alloc_output { 6370 __le16 error_code; 6371 __le16 req_type; 6372 __le16 seq_id; 6373 __le16 resp_len; 6374 __le32 encap_record_id; 6375 u8 unused_0[3]; 6376 u8 valid; 6377 }; 6378 6379 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 6380 struct hwrm_cfa_encap_record_free_input { 6381 __le16 req_type; 6382 __le16 cmpl_ring; 6383 __le16 seq_id; 6384 __le16 target_id; 6385 __le64 resp_addr; 6386 __le32 encap_record_id; 6387 u8 unused_0[4]; 6388 }; 6389 6390 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 6391 struct hwrm_cfa_encap_record_free_output { 6392 __le16 error_code; 6393 __le16 req_type; 6394 __le16 seq_id; 6395 __le16 resp_len; 6396 u8 unused_0[7]; 6397 u8 valid; 6398 }; 6399 6400 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 6401 struct hwrm_cfa_ntuple_filter_alloc_input { 6402 __le16 req_type; 6403 __le16 cmpl_ring; 6404 __le16 seq_id; 6405 __le16 target_id; 6406 __le64 resp_addr; 6407 __le32 flags; 6408 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6409 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 6410 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 6411 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 6412 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 6413 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 6414 __le32 enables; 6415 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6416 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 6417 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 6418 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 6419 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 6420 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 6421 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 6422 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 6423 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 6424 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6425 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6426 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6427 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6428 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6429 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6430 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6431 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6432 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6433 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 6434 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6435 __le64 l2_filter_id; 6436 u8 src_macaddr[6]; 6437 __be16 ethertype; 6438 u8 ip_addr_type; 6439 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6440 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6441 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6442 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6443 u8 ip_protocol; 6444 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6445 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6446 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6447 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6448 __le16 dst_id; 6449 __le16 mirror_vnic_id; 6450 u8 tunnel_type; 6451 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6452 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6453 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6454 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6455 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6456 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6457 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6458 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6459 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6460 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6461 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6462 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6463 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6464 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6465 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6466 u8 pri_hint; 6467 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6468 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6469 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6470 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6471 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6472 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6473 __be32 src_ipaddr[4]; 6474 __be32 src_ipaddr_mask[4]; 6475 __be32 dst_ipaddr[4]; 6476 __be32 dst_ipaddr_mask[4]; 6477 __be16 src_port; 6478 __be16 src_port_mask; 6479 __be16 dst_port; 6480 __be16 dst_port_mask; 6481 __le64 ntuple_filter_id_hint; 6482 }; 6483 6484 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6485 struct hwrm_cfa_ntuple_filter_alloc_output { 6486 __le16 error_code; 6487 __le16 req_type; 6488 __le16 seq_id; 6489 __le16 resp_len; 6490 __le64 ntuple_filter_id; 6491 __le32 flow_id; 6492 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6493 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6494 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6495 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6496 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6497 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6498 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6499 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6500 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6501 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6502 u8 unused_0[3]; 6503 u8 valid; 6504 }; 6505 6506 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 6507 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 6508 u8 code; 6509 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6510 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6511 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 6512 u8 unused_0[7]; 6513 }; 6514 6515 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6516 struct hwrm_cfa_ntuple_filter_free_input { 6517 __le16 req_type; 6518 __le16 cmpl_ring; 6519 __le16 seq_id; 6520 __le16 target_id; 6521 __le64 resp_addr; 6522 __le64 ntuple_filter_id; 6523 }; 6524 6525 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6526 struct hwrm_cfa_ntuple_filter_free_output { 6527 __le16 error_code; 6528 __le16 req_type; 6529 __le16 seq_id; 6530 __le16 resp_len; 6531 u8 unused_0[7]; 6532 u8 valid; 6533 }; 6534 6535 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6536 struct hwrm_cfa_ntuple_filter_cfg_input { 6537 __le16 req_type; 6538 __le16 cmpl_ring; 6539 __le16 seq_id; 6540 __le16 target_id; 6541 __le64 resp_addr; 6542 __le32 enables; 6543 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6544 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6545 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 6546 __le32 flags; 6547 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 6548 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6549 __le64 ntuple_filter_id; 6550 __le32 new_dst_id; 6551 __le32 new_mirror_vnic_id; 6552 __le16 new_meter_instance_id; 6553 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6554 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6555 u8 unused_1[6]; 6556 }; 6557 6558 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6559 struct hwrm_cfa_ntuple_filter_cfg_output { 6560 __le16 error_code; 6561 __le16 req_type; 6562 __le16 seq_id; 6563 __le16 resp_len; 6564 u8 unused_0[7]; 6565 u8 valid; 6566 }; 6567 6568 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 6569 struct hwrm_cfa_decap_filter_alloc_input { 6570 __le16 req_type; 6571 __le16 cmpl_ring; 6572 __le16 seq_id; 6573 __le16 target_id; 6574 __le64 resp_addr; 6575 __le32 flags; 6576 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 6577 __le32 enables; 6578 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 6579 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 6580 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 6581 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 6582 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 6583 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 6584 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 6585 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 6586 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 6587 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 6588 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 6589 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 6590 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 6591 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 6592 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 6593 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6594 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6595 __be32 tunnel_id; 6596 u8 tunnel_type; 6597 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6598 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6599 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6600 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6601 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6602 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6603 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6604 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6605 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6606 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6607 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6608 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6609 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6610 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6611 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6612 u8 unused_0; 6613 __le16 unused_1; 6614 u8 src_macaddr[6]; 6615 u8 unused_2[2]; 6616 u8 dst_macaddr[6]; 6617 __be16 ovlan_vid; 6618 __be16 ivlan_vid; 6619 __be16 t_ovlan_vid; 6620 __be16 t_ivlan_vid; 6621 __be16 ethertype; 6622 u8 ip_addr_type; 6623 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6624 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6625 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6626 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6627 u8 ip_protocol; 6628 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6629 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6630 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6631 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6632 __le16 unused_3; 6633 __le32 unused_4; 6634 __be32 src_ipaddr[4]; 6635 __be32 dst_ipaddr[4]; 6636 __be16 src_port; 6637 __be16 dst_port; 6638 __le16 dst_id; 6639 __le16 l2_ctxt_ref_id; 6640 }; 6641 6642 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6643 struct hwrm_cfa_decap_filter_alloc_output { 6644 __le16 error_code; 6645 __le16 req_type; 6646 __le16 seq_id; 6647 __le16 resp_len; 6648 __le32 decap_filter_id; 6649 u8 unused_0[3]; 6650 u8 valid; 6651 }; 6652 6653 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6654 struct hwrm_cfa_decap_filter_free_input { 6655 __le16 req_type; 6656 __le16 cmpl_ring; 6657 __le16 seq_id; 6658 __le16 target_id; 6659 __le64 resp_addr; 6660 __le32 decap_filter_id; 6661 u8 unused_0[4]; 6662 }; 6663 6664 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6665 struct hwrm_cfa_decap_filter_free_output { 6666 __le16 error_code; 6667 __le16 req_type; 6668 __le16 seq_id; 6669 __le16 resp_len; 6670 u8 unused_0[7]; 6671 u8 valid; 6672 }; 6673 6674 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6675 struct hwrm_cfa_flow_alloc_input { 6676 __le16 req_type; 6677 __le16 cmpl_ring; 6678 __le16 seq_id; 6679 __le16 target_id; 6680 __le64 resp_addr; 6681 __le16 flags; 6682 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6683 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6684 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6685 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6686 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6687 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6688 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6689 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6690 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6691 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6692 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6693 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6694 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6695 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6696 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6697 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6698 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6699 __le16 src_fid; 6700 __le32 tunnel_handle; 6701 __le16 action_flags; 6702 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6703 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6704 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6705 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6706 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6707 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6708 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6709 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6710 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6711 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6712 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6713 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6714 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6715 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6716 __le16 dst_fid; 6717 __be16 l2_rewrite_vlan_tpid; 6718 __be16 l2_rewrite_vlan_tci; 6719 __le16 act_meter_id; 6720 __le16 ref_flow_handle; 6721 __be16 ethertype; 6722 __be16 outer_vlan_tci; 6723 __be16 dmac[3]; 6724 __be16 inner_vlan_tci; 6725 __be16 smac[3]; 6726 u8 ip_dst_mask_len; 6727 u8 ip_src_mask_len; 6728 __be32 ip_dst[4]; 6729 __be32 ip_src[4]; 6730 __be16 l4_src_port; 6731 __be16 l4_src_port_mask; 6732 __be16 l4_dst_port; 6733 __be16 l4_dst_port_mask; 6734 __be32 nat_ip_address[4]; 6735 __be16 l2_rewrite_dmac[3]; 6736 __be16 nat_port; 6737 __be16 l2_rewrite_smac[3]; 6738 u8 ip_proto; 6739 u8 tunnel_type; 6740 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6741 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6742 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6743 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6744 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6745 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6746 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6747 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6748 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6749 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6750 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6751 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6752 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6753 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6754 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6755 }; 6756 6757 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6758 struct hwrm_cfa_flow_alloc_output { 6759 __le16 error_code; 6760 __le16 req_type; 6761 __le16 seq_id; 6762 __le16 resp_len; 6763 __le16 flow_handle; 6764 u8 unused_0[2]; 6765 __le32 flow_id; 6766 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6767 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6768 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6769 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6770 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6771 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6772 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6773 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6774 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6775 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6776 __le64 ext_flow_handle; 6777 __le32 flow_counter_id; 6778 u8 unused_1[3]; 6779 u8 valid; 6780 }; 6781 6782 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6783 struct hwrm_cfa_flow_alloc_cmd_err { 6784 u8 code; 6785 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6786 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6787 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6788 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6789 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6790 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6791 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6792 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6793 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6794 u8 unused_0[7]; 6795 }; 6796 6797 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6798 struct hwrm_cfa_flow_free_input { 6799 __le16 req_type; 6800 __le16 cmpl_ring; 6801 __le16 seq_id; 6802 __le16 target_id; 6803 __le64 resp_addr; 6804 __le16 flow_handle; 6805 __le16 unused_0; 6806 __le32 flow_counter_id; 6807 __le64 ext_flow_handle; 6808 }; 6809 6810 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6811 struct hwrm_cfa_flow_free_output { 6812 __le16 error_code; 6813 __le16 req_type; 6814 __le16 seq_id; 6815 __le16 resp_len; 6816 __le64 packet; 6817 __le64 byte; 6818 u8 unused_0[7]; 6819 u8 valid; 6820 }; 6821 6822 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6823 struct hwrm_cfa_flow_info_input { 6824 __le16 req_type; 6825 __le16 cmpl_ring; 6826 __le16 seq_id; 6827 __le16 target_id; 6828 __le64 resp_addr; 6829 __le16 flow_handle; 6830 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6831 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6832 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6833 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6834 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6835 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6836 u8 unused_0[6]; 6837 __le64 ext_flow_handle; 6838 }; 6839 6840 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6841 struct hwrm_cfa_flow_info_output { 6842 __le16 error_code; 6843 __le16 req_type; 6844 __le16 seq_id; 6845 __le16 resp_len; 6846 u8 flags; 6847 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6848 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6849 u8 profile; 6850 __le16 src_fid; 6851 __le16 dst_fid; 6852 __le16 l2_ctxt_id; 6853 __le64 em_info; 6854 __le64 tcam_info; 6855 __le64 vfp_tcam_info; 6856 __le16 ar_id; 6857 __le16 flow_handle; 6858 __le32 tunnel_handle; 6859 __le16 flow_timer; 6860 u8 unused_0[6]; 6861 __le32 flow_key_data[130]; 6862 __le32 flow_action_info[30]; 6863 u8 unused_1[7]; 6864 u8 valid; 6865 }; 6866 6867 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6868 struct hwrm_cfa_flow_stats_input { 6869 __le16 req_type; 6870 __le16 cmpl_ring; 6871 __le16 seq_id; 6872 __le16 target_id; 6873 __le64 resp_addr; 6874 __le16 num_flows; 6875 __le16 flow_handle_0; 6876 __le16 flow_handle_1; 6877 __le16 flow_handle_2; 6878 __le16 flow_handle_3; 6879 __le16 flow_handle_4; 6880 __le16 flow_handle_5; 6881 __le16 flow_handle_6; 6882 __le16 flow_handle_7; 6883 __le16 flow_handle_8; 6884 __le16 flow_handle_9; 6885 u8 unused_0[2]; 6886 __le32 flow_id_0; 6887 __le32 flow_id_1; 6888 __le32 flow_id_2; 6889 __le32 flow_id_3; 6890 __le32 flow_id_4; 6891 __le32 flow_id_5; 6892 __le32 flow_id_6; 6893 __le32 flow_id_7; 6894 __le32 flow_id_8; 6895 __le32 flow_id_9; 6896 }; 6897 6898 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6899 struct hwrm_cfa_flow_stats_output { 6900 __le16 error_code; 6901 __le16 req_type; 6902 __le16 seq_id; 6903 __le16 resp_len; 6904 __le64 packet_0; 6905 __le64 packet_1; 6906 __le64 packet_2; 6907 __le64 packet_3; 6908 __le64 packet_4; 6909 __le64 packet_5; 6910 __le64 packet_6; 6911 __le64 packet_7; 6912 __le64 packet_8; 6913 __le64 packet_9; 6914 __le64 byte_0; 6915 __le64 byte_1; 6916 __le64 byte_2; 6917 __le64 byte_3; 6918 __le64 byte_4; 6919 __le64 byte_5; 6920 __le64 byte_6; 6921 __le64 byte_7; 6922 __le64 byte_8; 6923 __le64 byte_9; 6924 u8 unused_0[7]; 6925 u8 valid; 6926 }; 6927 6928 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6929 struct hwrm_cfa_vfr_alloc_input { 6930 __le16 req_type; 6931 __le16 cmpl_ring; 6932 __le16 seq_id; 6933 __le16 target_id; 6934 __le64 resp_addr; 6935 __le16 vf_id; 6936 __le16 reserved; 6937 u8 unused_0[4]; 6938 char vfr_name[32]; 6939 }; 6940 6941 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6942 struct hwrm_cfa_vfr_alloc_output { 6943 __le16 error_code; 6944 __le16 req_type; 6945 __le16 seq_id; 6946 __le16 resp_len; 6947 __le16 rx_cfa_code; 6948 __le16 tx_cfa_action; 6949 u8 unused_0[3]; 6950 u8 valid; 6951 }; 6952 6953 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 6954 struct hwrm_cfa_vfr_free_input { 6955 __le16 req_type; 6956 __le16 cmpl_ring; 6957 __le16 seq_id; 6958 __le16 target_id; 6959 __le64 resp_addr; 6960 char vfr_name[32]; 6961 __le16 vf_id; 6962 __le16 reserved; 6963 u8 unused_0[4]; 6964 }; 6965 6966 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6967 struct hwrm_cfa_vfr_free_output { 6968 __le16 error_code; 6969 __le16 req_type; 6970 __le16 seq_id; 6971 __le16 resp_len; 6972 u8 unused_0[7]; 6973 u8 valid; 6974 }; 6975 6976 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6977 struct hwrm_cfa_eem_qcaps_input { 6978 __le16 req_type; 6979 __le16 cmpl_ring; 6980 __le16 seq_id; 6981 __le16 target_id; 6982 __le64 resp_addr; 6983 __le32 flags; 6984 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6985 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6986 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6987 __le32 unused_0; 6988 }; 6989 6990 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 6991 struct hwrm_cfa_eem_qcaps_output { 6992 __le16 error_code; 6993 __le16 req_type; 6994 __le16 seq_id; 6995 __le16 resp_len; 6996 __le32 flags; 6997 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6998 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6999 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 7000 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 7001 __le32 unused_0; 7002 __le32 supported; 7003 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 7004 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 7005 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 7006 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 7007 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 7008 __le32 max_entries_supported; 7009 __le16 key_entry_size; 7010 __le16 record_entry_size; 7011 __le16 efc_entry_size; 7012 __le16 fid_entry_size; 7013 u8 unused_1[7]; 7014 u8 valid; 7015 }; 7016 7017 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 7018 struct hwrm_cfa_eem_cfg_input { 7019 __le16 req_type; 7020 __le16 cmpl_ring; 7021 __le16 seq_id; 7022 __le16 target_id; 7023 __le64 resp_addr; 7024 __le32 flags; 7025 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 7026 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 7027 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7028 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 7029 __le16 group_id; 7030 __le16 unused_0; 7031 __le32 num_entries; 7032 __le32 unused_1; 7033 __le16 key0_ctx_id; 7034 __le16 key1_ctx_id; 7035 __le16 record_ctx_id; 7036 __le16 efc_ctx_id; 7037 __le16 fid_ctx_id; 7038 __le16 unused_2; 7039 __le32 unused_3; 7040 }; 7041 7042 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 7043 struct hwrm_cfa_eem_cfg_output { 7044 __le16 error_code; 7045 __le16 req_type; 7046 __le16 seq_id; 7047 __le16 resp_len; 7048 u8 unused_0[7]; 7049 u8 valid; 7050 }; 7051 7052 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 7053 struct hwrm_cfa_eem_qcfg_input { 7054 __le16 req_type; 7055 __le16 cmpl_ring; 7056 __le16 seq_id; 7057 __le16 target_id; 7058 __le64 resp_addr; 7059 __le32 flags; 7060 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 7061 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 7062 __le32 unused_0; 7063 }; 7064 7065 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 7066 struct hwrm_cfa_eem_qcfg_output { 7067 __le16 error_code; 7068 __le16 req_type; 7069 __le16 seq_id; 7070 __le16 resp_len; 7071 __le32 flags; 7072 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 7073 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 7074 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 7075 __le32 num_entries; 7076 __le16 key0_ctx_id; 7077 __le16 key1_ctx_id; 7078 __le16 record_ctx_id; 7079 __le16 efc_ctx_id; 7080 __le16 fid_ctx_id; 7081 u8 unused_2[5]; 7082 u8 valid; 7083 }; 7084 7085 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 7086 struct hwrm_cfa_eem_op_input { 7087 __le16 req_type; 7088 __le16 cmpl_ring; 7089 __le16 seq_id; 7090 __le16 target_id; 7091 __le64 resp_addr; 7092 __le32 flags; 7093 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 7094 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 7095 __le16 unused_0; 7096 __le16 op; 7097 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 7098 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 7099 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 7100 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 7101 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 7102 }; 7103 7104 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 7105 struct hwrm_cfa_eem_op_output { 7106 __le16 error_code; 7107 __le16 req_type; 7108 __le16 seq_id; 7109 __le16 resp_len; 7110 u8 unused_0[7]; 7111 u8 valid; 7112 }; 7113 7114 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 7115 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 7116 __le16 req_type; 7117 __le16 cmpl_ring; 7118 __le16 seq_id; 7119 __le16 target_id; 7120 __le64 resp_addr; 7121 __le32 unused_0[4]; 7122 }; 7123 7124 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 7125 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 7126 __le16 error_code; 7127 __le16 req_type; 7128 __le16 seq_id; 7129 __le16 resp_len; 7130 __le32 flags; 7131 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 7132 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 7133 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 7134 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 7135 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 7136 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 7137 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 7138 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 7139 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7140 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7141 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7142 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7143 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7144 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7145 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7146 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7147 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 7148 u8 unused_0[3]; 7149 u8 valid; 7150 }; 7151 7152 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7153 struct hwrm_tunnel_dst_port_query_input { 7154 __le16 req_type; 7155 __le16 cmpl_ring; 7156 __le16 seq_id; 7157 __le16 target_id; 7158 __le64 resp_addr; 7159 u8 tunnel_type; 7160 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7161 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7162 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7163 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7164 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7165 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7166 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7167 u8 unused_0[7]; 7168 }; 7169 7170 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7171 struct hwrm_tunnel_dst_port_query_output { 7172 __le16 error_code; 7173 __le16 req_type; 7174 __le16 seq_id; 7175 __le16 resp_len; 7176 __le16 tunnel_dst_port_id; 7177 __be16 tunnel_dst_port_val; 7178 u8 unused_0[3]; 7179 u8 valid; 7180 }; 7181 7182 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7183 struct hwrm_tunnel_dst_port_alloc_input { 7184 __le16 req_type; 7185 __le16 cmpl_ring; 7186 __le16 seq_id; 7187 __le16 target_id; 7188 __le64 resp_addr; 7189 u8 tunnel_type; 7190 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7191 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7192 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7193 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7194 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7195 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7196 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7197 u8 unused_0; 7198 __be16 tunnel_dst_port_val; 7199 u8 unused_1[4]; 7200 }; 7201 7202 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7203 struct hwrm_tunnel_dst_port_alloc_output { 7204 __le16 error_code; 7205 __le16 req_type; 7206 __le16 seq_id; 7207 __le16 resp_len; 7208 __le16 tunnel_dst_port_id; 7209 u8 unused_0[5]; 7210 u8 valid; 7211 }; 7212 7213 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7214 struct hwrm_tunnel_dst_port_free_input { 7215 __le16 req_type; 7216 __le16 cmpl_ring; 7217 __le16 seq_id; 7218 __le16 target_id; 7219 __le64 resp_addr; 7220 u8 tunnel_type; 7221 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7222 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7223 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7224 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7225 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7226 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7227 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7228 u8 unused_0; 7229 __le16 tunnel_dst_port_id; 7230 u8 unused_1[4]; 7231 }; 7232 7233 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7234 struct hwrm_tunnel_dst_port_free_output { 7235 __le16 error_code; 7236 __le16 req_type; 7237 __le16 seq_id; 7238 __le16 resp_len; 7239 u8 unused_1[7]; 7240 u8 valid; 7241 }; 7242 7243 /* ctx_hw_stats (size:1280b/160B) */ 7244 struct ctx_hw_stats { 7245 __le64 rx_ucast_pkts; 7246 __le64 rx_mcast_pkts; 7247 __le64 rx_bcast_pkts; 7248 __le64 rx_discard_pkts; 7249 __le64 rx_error_pkts; 7250 __le64 rx_ucast_bytes; 7251 __le64 rx_mcast_bytes; 7252 __le64 rx_bcast_bytes; 7253 __le64 tx_ucast_pkts; 7254 __le64 tx_mcast_pkts; 7255 __le64 tx_bcast_pkts; 7256 __le64 tx_error_pkts; 7257 __le64 tx_discard_pkts; 7258 __le64 tx_ucast_bytes; 7259 __le64 tx_mcast_bytes; 7260 __le64 tx_bcast_bytes; 7261 __le64 tpa_pkts; 7262 __le64 tpa_bytes; 7263 __le64 tpa_events; 7264 __le64 tpa_aborts; 7265 }; 7266 7267 /* ctx_hw_stats_ext (size:1408b/176B) */ 7268 struct ctx_hw_stats_ext { 7269 __le64 rx_ucast_pkts; 7270 __le64 rx_mcast_pkts; 7271 __le64 rx_bcast_pkts; 7272 __le64 rx_discard_pkts; 7273 __le64 rx_error_pkts; 7274 __le64 rx_ucast_bytes; 7275 __le64 rx_mcast_bytes; 7276 __le64 rx_bcast_bytes; 7277 __le64 tx_ucast_pkts; 7278 __le64 tx_mcast_pkts; 7279 __le64 tx_bcast_pkts; 7280 __le64 tx_error_pkts; 7281 __le64 tx_discard_pkts; 7282 __le64 tx_ucast_bytes; 7283 __le64 tx_mcast_bytes; 7284 __le64 tx_bcast_bytes; 7285 __le64 rx_tpa_eligible_pkt; 7286 __le64 rx_tpa_eligible_bytes; 7287 __le64 rx_tpa_pkt; 7288 __le64 rx_tpa_bytes; 7289 __le64 rx_tpa_errors; 7290 __le64 rx_tpa_events; 7291 }; 7292 7293 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7294 struct hwrm_stat_ctx_alloc_input { 7295 __le16 req_type; 7296 __le16 cmpl_ring; 7297 __le16 seq_id; 7298 __le16 target_id; 7299 __le64 resp_addr; 7300 __le64 stats_dma_addr; 7301 __le32 update_period_ms; 7302 u8 stat_ctx_flags; 7303 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7304 u8 unused_0; 7305 __le16 stats_dma_length; 7306 }; 7307 7308 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7309 struct hwrm_stat_ctx_alloc_output { 7310 __le16 error_code; 7311 __le16 req_type; 7312 __le16 seq_id; 7313 __le16 resp_len; 7314 __le32 stat_ctx_id; 7315 u8 unused_0[3]; 7316 u8 valid; 7317 }; 7318 7319 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7320 struct hwrm_stat_ctx_free_input { 7321 __le16 req_type; 7322 __le16 cmpl_ring; 7323 __le16 seq_id; 7324 __le16 target_id; 7325 __le64 resp_addr; 7326 __le32 stat_ctx_id; 7327 u8 unused_0[4]; 7328 }; 7329 7330 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7331 struct hwrm_stat_ctx_free_output { 7332 __le16 error_code; 7333 __le16 req_type; 7334 __le16 seq_id; 7335 __le16 resp_len; 7336 __le32 stat_ctx_id; 7337 u8 unused_0[3]; 7338 u8 valid; 7339 }; 7340 7341 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 7342 struct hwrm_stat_ctx_query_input { 7343 __le16 req_type; 7344 __le16 cmpl_ring; 7345 __le16 seq_id; 7346 __le16 target_id; 7347 __le64 resp_addr; 7348 __le32 stat_ctx_id; 7349 u8 flags; 7350 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7351 u8 unused_0[3]; 7352 }; 7353 7354 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 7355 struct hwrm_stat_ctx_query_output { 7356 __le16 error_code; 7357 __le16 req_type; 7358 __le16 seq_id; 7359 __le16 resp_len; 7360 __le64 tx_ucast_pkts; 7361 __le64 tx_mcast_pkts; 7362 __le64 tx_bcast_pkts; 7363 __le64 tx_discard_pkts; 7364 __le64 tx_error_pkts; 7365 __le64 tx_ucast_bytes; 7366 __le64 tx_mcast_bytes; 7367 __le64 tx_bcast_bytes; 7368 __le64 rx_ucast_pkts; 7369 __le64 rx_mcast_pkts; 7370 __le64 rx_bcast_pkts; 7371 __le64 rx_discard_pkts; 7372 __le64 rx_error_pkts; 7373 __le64 rx_ucast_bytes; 7374 __le64 rx_mcast_bytes; 7375 __le64 rx_bcast_bytes; 7376 __le64 rx_agg_pkts; 7377 __le64 rx_agg_bytes; 7378 __le64 rx_agg_events; 7379 __le64 rx_agg_aborts; 7380 u8 unused_0[7]; 7381 u8 valid; 7382 }; 7383 7384 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 7385 struct hwrm_stat_ext_ctx_query_input { 7386 __le16 req_type; 7387 __le16 cmpl_ring; 7388 __le16 seq_id; 7389 __le16 target_id; 7390 __le64 resp_addr; 7391 __le32 stat_ctx_id; 7392 u8 flags; 7393 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7394 u8 unused_0[3]; 7395 }; 7396 7397 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 7398 struct hwrm_stat_ext_ctx_query_output { 7399 __le16 error_code; 7400 __le16 req_type; 7401 __le16 seq_id; 7402 __le16 resp_len; 7403 __le64 rx_ucast_pkts; 7404 __le64 rx_mcast_pkts; 7405 __le64 rx_bcast_pkts; 7406 __le64 rx_discard_pkts; 7407 __le64 rx_error_pkts; 7408 __le64 rx_ucast_bytes; 7409 __le64 rx_mcast_bytes; 7410 __le64 rx_bcast_bytes; 7411 __le64 tx_ucast_pkts; 7412 __le64 tx_mcast_pkts; 7413 __le64 tx_bcast_pkts; 7414 __le64 tx_error_pkts; 7415 __le64 tx_discard_pkts; 7416 __le64 tx_ucast_bytes; 7417 __le64 tx_mcast_bytes; 7418 __le64 tx_bcast_bytes; 7419 __le64 rx_tpa_eligible_pkt; 7420 __le64 rx_tpa_eligible_bytes; 7421 __le64 rx_tpa_pkt; 7422 __le64 rx_tpa_bytes; 7423 __le64 rx_tpa_errors; 7424 __le64 rx_tpa_events; 7425 u8 unused_0[7]; 7426 u8 valid; 7427 }; 7428 7429 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 7430 struct hwrm_stat_ctx_clr_stats_input { 7431 __le16 req_type; 7432 __le16 cmpl_ring; 7433 __le16 seq_id; 7434 __le16 target_id; 7435 __le64 resp_addr; 7436 __le32 stat_ctx_id; 7437 u8 unused_0[4]; 7438 }; 7439 7440 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 7441 struct hwrm_stat_ctx_clr_stats_output { 7442 __le16 error_code; 7443 __le16 req_type; 7444 __le16 seq_id; 7445 __le16 resp_len; 7446 u8 unused_0[7]; 7447 u8 valid; 7448 }; 7449 7450 /* hwrm_pcie_qstats_input (size:256b/32B) */ 7451 struct hwrm_pcie_qstats_input { 7452 __le16 req_type; 7453 __le16 cmpl_ring; 7454 __le16 seq_id; 7455 __le16 target_id; 7456 __le64 resp_addr; 7457 __le16 pcie_stat_size; 7458 u8 unused_0[6]; 7459 __le64 pcie_stat_host_addr; 7460 }; 7461 7462 /* hwrm_pcie_qstats_output (size:128b/16B) */ 7463 struct hwrm_pcie_qstats_output { 7464 __le16 error_code; 7465 __le16 req_type; 7466 __le16 seq_id; 7467 __le16 resp_len; 7468 __le16 pcie_stat_size; 7469 u8 unused_0[5]; 7470 u8 valid; 7471 }; 7472 7473 /* pcie_ctx_hw_stats (size:768b/96B) */ 7474 struct pcie_ctx_hw_stats { 7475 __le64 pcie_pl_signal_integrity; 7476 __le64 pcie_dl_signal_integrity; 7477 __le64 pcie_tl_signal_integrity; 7478 __le64 pcie_link_integrity; 7479 __le64 pcie_tx_traffic_rate; 7480 __le64 pcie_rx_traffic_rate; 7481 __le64 pcie_tx_dllp_statistics; 7482 __le64 pcie_rx_dllp_statistics; 7483 __le64 pcie_equalization_time; 7484 __le32 pcie_ltssm_histogram[4]; 7485 __le64 pcie_recovery_histogram; 7486 }; 7487 7488 /* hwrm_fw_reset_input (size:192b/24B) */ 7489 struct hwrm_fw_reset_input { 7490 __le16 req_type; 7491 __le16 cmpl_ring; 7492 __le16 seq_id; 7493 __le16 target_id; 7494 __le64 resp_addr; 7495 u8 embedded_proc_type; 7496 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7497 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7498 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7499 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7500 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7501 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7502 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7503 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 7504 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 7505 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7506 u8 selfrst_status; 7507 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7508 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7509 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7510 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7511 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7512 u8 host_idx; 7513 u8 flags; 7514 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 7515 u8 unused_0[4]; 7516 }; 7517 7518 /* hwrm_fw_reset_output (size:128b/16B) */ 7519 struct hwrm_fw_reset_output { 7520 __le16 error_code; 7521 __le16 req_type; 7522 __le16 seq_id; 7523 __le16 resp_len; 7524 u8 selfrst_status; 7525 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7526 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7527 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7528 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7529 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7530 u8 unused_0[6]; 7531 u8 valid; 7532 }; 7533 7534 /* hwrm_fw_qstatus_input (size:192b/24B) */ 7535 struct hwrm_fw_qstatus_input { 7536 __le16 req_type; 7537 __le16 cmpl_ring; 7538 __le16 seq_id; 7539 __le16 target_id; 7540 __le64 resp_addr; 7541 u8 embedded_proc_type; 7542 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7543 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7544 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7545 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7546 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7547 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7548 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7549 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7550 u8 unused_0[7]; 7551 }; 7552 7553 /* hwrm_fw_qstatus_output (size:128b/16B) */ 7554 struct hwrm_fw_qstatus_output { 7555 __le16 error_code; 7556 __le16 req_type; 7557 __le16 seq_id; 7558 __le16 resp_len; 7559 u8 selfrst_status; 7560 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7561 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7562 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7563 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 7564 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7565 u8 unused_0[6]; 7566 u8 valid; 7567 }; 7568 7569 /* hwrm_fw_set_time_input (size:256b/32B) */ 7570 struct hwrm_fw_set_time_input { 7571 __le16 req_type; 7572 __le16 cmpl_ring; 7573 __le16 seq_id; 7574 __le16 target_id; 7575 __le64 resp_addr; 7576 __le16 year; 7577 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7578 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7579 u8 month; 7580 u8 day; 7581 u8 hour; 7582 u8 minute; 7583 u8 second; 7584 u8 unused_0; 7585 __le16 millisecond; 7586 __le16 zone; 7587 #define FW_SET_TIME_REQ_ZONE_UTC 0 7588 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7589 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7590 u8 unused_1[4]; 7591 }; 7592 7593 /* hwrm_fw_set_time_output (size:128b/16B) */ 7594 struct hwrm_fw_set_time_output { 7595 __le16 error_code; 7596 __le16 req_type; 7597 __le16 seq_id; 7598 __le16 resp_len; 7599 u8 unused_0[7]; 7600 u8 valid; 7601 }; 7602 7603 /* hwrm_struct_hdr (size:128b/16B) */ 7604 struct hwrm_struct_hdr { 7605 __le16 struct_id; 7606 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7607 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7608 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7609 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7610 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7611 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7612 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 7613 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 7614 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7615 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7616 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7617 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 7618 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 7619 __le16 len; 7620 u8 version; 7621 u8 count; 7622 __le16 subtype; 7623 __le16 next_offset; 7624 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7625 u8 unused_0[6]; 7626 }; 7627 7628 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7629 struct hwrm_struct_data_dcbx_app { 7630 __be16 protocol_id; 7631 u8 protocol_selector; 7632 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7633 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7634 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7635 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7636 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 7637 u8 priority; 7638 u8 valid; 7639 u8 unused_0[3]; 7640 }; 7641 7642 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7643 struct hwrm_fw_set_structured_data_input { 7644 __le16 req_type; 7645 __le16 cmpl_ring; 7646 __le16 seq_id; 7647 __le16 target_id; 7648 __le64 resp_addr; 7649 __le64 src_data_addr; 7650 __le16 data_len; 7651 u8 hdr_cnt; 7652 u8 unused_0[5]; 7653 }; 7654 7655 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7656 struct hwrm_fw_set_structured_data_output { 7657 __le16 error_code; 7658 __le16 req_type; 7659 __le16 seq_id; 7660 __le16 resp_len; 7661 u8 unused_0[7]; 7662 u8 valid; 7663 }; 7664 7665 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7666 struct hwrm_fw_set_structured_data_cmd_err { 7667 u8 code; 7668 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7669 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7670 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7671 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7672 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7673 u8 unused_0[7]; 7674 }; 7675 7676 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7677 struct hwrm_fw_get_structured_data_input { 7678 __le16 req_type; 7679 __le16 cmpl_ring; 7680 __le16 seq_id; 7681 __le16 target_id; 7682 __le64 resp_addr; 7683 __le64 dest_data_addr; 7684 __le16 data_len; 7685 __le16 structure_id; 7686 __le16 subtype; 7687 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7688 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7689 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7690 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7691 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7692 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7693 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7694 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7695 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7696 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7697 u8 count; 7698 u8 unused_0; 7699 }; 7700 7701 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7702 struct hwrm_fw_get_structured_data_output { 7703 __le16 error_code; 7704 __le16 req_type; 7705 __le16 seq_id; 7706 __le16 resp_len; 7707 u8 hdr_cnt; 7708 u8 unused_0[6]; 7709 u8 valid; 7710 }; 7711 7712 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7713 struct hwrm_fw_get_structured_data_cmd_err { 7714 u8 code; 7715 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7716 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7717 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7718 u8 unused_0[7]; 7719 }; 7720 7721 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7722 struct hwrm_exec_fwd_resp_input { 7723 __le16 req_type; 7724 __le16 cmpl_ring; 7725 __le16 seq_id; 7726 __le16 target_id; 7727 __le64 resp_addr; 7728 __le32 encap_request[26]; 7729 __le16 encap_resp_target_id; 7730 u8 unused_0[6]; 7731 }; 7732 7733 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7734 struct hwrm_exec_fwd_resp_output { 7735 __le16 error_code; 7736 __le16 req_type; 7737 __le16 seq_id; 7738 __le16 resp_len; 7739 u8 unused_0[7]; 7740 u8 valid; 7741 }; 7742 7743 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7744 struct hwrm_reject_fwd_resp_input { 7745 __le16 req_type; 7746 __le16 cmpl_ring; 7747 __le16 seq_id; 7748 __le16 target_id; 7749 __le64 resp_addr; 7750 __le32 encap_request[26]; 7751 __le16 encap_resp_target_id; 7752 u8 unused_0[6]; 7753 }; 7754 7755 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7756 struct hwrm_reject_fwd_resp_output { 7757 __le16 error_code; 7758 __le16 req_type; 7759 __le16 seq_id; 7760 __le16 resp_len; 7761 u8 unused_0[7]; 7762 u8 valid; 7763 }; 7764 7765 /* hwrm_fwd_resp_input (size:1024b/128B) */ 7766 struct hwrm_fwd_resp_input { 7767 __le16 req_type; 7768 __le16 cmpl_ring; 7769 __le16 seq_id; 7770 __le16 target_id; 7771 __le64 resp_addr; 7772 __le16 encap_resp_target_id; 7773 __le16 encap_resp_cmpl_ring; 7774 __le16 encap_resp_len; 7775 u8 unused_0; 7776 u8 unused_1; 7777 __le64 encap_resp_addr; 7778 __le32 encap_resp[24]; 7779 }; 7780 7781 /* hwrm_fwd_resp_output (size:128b/16B) */ 7782 struct hwrm_fwd_resp_output { 7783 __le16 error_code; 7784 __le16 req_type; 7785 __le16 seq_id; 7786 __le16 resp_len; 7787 u8 unused_0[7]; 7788 u8 valid; 7789 }; 7790 7791 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7792 struct hwrm_fwd_async_event_cmpl_input { 7793 __le16 req_type; 7794 __le16 cmpl_ring; 7795 __le16 seq_id; 7796 __le16 target_id; 7797 __le64 resp_addr; 7798 __le16 encap_async_event_target_id; 7799 u8 unused_0[6]; 7800 __le32 encap_async_event_cmpl[4]; 7801 }; 7802 7803 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7804 struct hwrm_fwd_async_event_cmpl_output { 7805 __le16 error_code; 7806 __le16 req_type; 7807 __le16 seq_id; 7808 __le16 resp_len; 7809 u8 unused_0[7]; 7810 u8 valid; 7811 }; 7812 7813 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7814 struct hwrm_temp_monitor_query_input { 7815 __le16 req_type; 7816 __le16 cmpl_ring; 7817 __le16 seq_id; 7818 __le16 target_id; 7819 __le64 resp_addr; 7820 }; 7821 7822 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7823 struct hwrm_temp_monitor_query_output { 7824 __le16 error_code; 7825 __le16 req_type; 7826 __le16 seq_id; 7827 __le16 resp_len; 7828 u8 temp; 7829 u8 phy_temp; 7830 u8 om_temp; 7831 u8 flags; 7832 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 7833 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 7834 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 7835 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 7836 u8 unused_0[3]; 7837 u8 valid; 7838 }; 7839 7840 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7841 struct hwrm_wol_filter_alloc_input { 7842 __le16 req_type; 7843 __le16 cmpl_ring; 7844 __le16 seq_id; 7845 __le16 target_id; 7846 __le64 resp_addr; 7847 __le32 flags; 7848 __le32 enables; 7849 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7850 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7851 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7852 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7853 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7854 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7855 __le16 port_id; 7856 u8 wol_type; 7857 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7858 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7859 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7860 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7861 u8 unused_0[5]; 7862 u8 mac_address[6]; 7863 __le16 pattern_offset; 7864 __le16 pattern_buf_size; 7865 __le16 pattern_mask_size; 7866 u8 unused_1[4]; 7867 __le64 pattern_buf_addr; 7868 __le64 pattern_mask_addr; 7869 }; 7870 7871 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7872 struct hwrm_wol_filter_alloc_output { 7873 __le16 error_code; 7874 __le16 req_type; 7875 __le16 seq_id; 7876 __le16 resp_len; 7877 u8 wol_filter_id; 7878 u8 unused_0[6]; 7879 u8 valid; 7880 }; 7881 7882 /* hwrm_wol_filter_free_input (size:256b/32B) */ 7883 struct hwrm_wol_filter_free_input { 7884 __le16 req_type; 7885 __le16 cmpl_ring; 7886 __le16 seq_id; 7887 __le16 target_id; 7888 __le64 resp_addr; 7889 __le32 flags; 7890 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7891 __le32 enables; 7892 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7893 __le16 port_id; 7894 u8 wol_filter_id; 7895 u8 unused_0[5]; 7896 }; 7897 7898 /* hwrm_wol_filter_free_output (size:128b/16B) */ 7899 struct hwrm_wol_filter_free_output { 7900 __le16 error_code; 7901 __le16 req_type; 7902 __le16 seq_id; 7903 __le16 resp_len; 7904 u8 unused_0[7]; 7905 u8 valid; 7906 }; 7907 7908 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7909 struct hwrm_wol_filter_qcfg_input { 7910 __le16 req_type; 7911 __le16 cmpl_ring; 7912 __le16 seq_id; 7913 __le16 target_id; 7914 __le64 resp_addr; 7915 __le16 port_id; 7916 __le16 handle; 7917 u8 unused_0[4]; 7918 __le64 pattern_buf_addr; 7919 __le16 pattern_buf_size; 7920 u8 unused_1[6]; 7921 __le64 pattern_mask_addr; 7922 __le16 pattern_mask_size; 7923 u8 unused_2[6]; 7924 }; 7925 7926 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7927 struct hwrm_wol_filter_qcfg_output { 7928 __le16 error_code; 7929 __le16 req_type; 7930 __le16 seq_id; 7931 __le16 resp_len; 7932 __le16 next_handle; 7933 u8 wol_filter_id; 7934 u8 wol_type; 7935 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7936 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7937 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7938 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7939 __le32 unused_0; 7940 u8 mac_address[6]; 7941 __le16 pattern_offset; 7942 __le16 pattern_size; 7943 __le16 pattern_mask_size; 7944 u8 unused_1[3]; 7945 u8 valid; 7946 }; 7947 7948 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7949 struct hwrm_wol_reason_qcfg_input { 7950 __le16 req_type; 7951 __le16 cmpl_ring; 7952 __le16 seq_id; 7953 __le16 target_id; 7954 __le64 resp_addr; 7955 __le16 port_id; 7956 u8 unused_0[6]; 7957 __le64 wol_pkt_buf_addr; 7958 __le16 wol_pkt_buf_size; 7959 u8 unused_1[6]; 7960 }; 7961 7962 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7963 struct hwrm_wol_reason_qcfg_output { 7964 __le16 error_code; 7965 __le16 req_type; 7966 __le16 seq_id; 7967 __le16 resp_len; 7968 u8 wol_filter_id; 7969 u8 wol_reason; 7970 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7971 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7972 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7973 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7974 u8 wol_pkt_len; 7975 u8 unused_0[4]; 7976 u8 valid; 7977 }; 7978 7979 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 7980 struct hwrm_dbg_read_direct_input { 7981 __le16 req_type; 7982 __le16 cmpl_ring; 7983 __le16 seq_id; 7984 __le16 target_id; 7985 __le64 resp_addr; 7986 __le64 host_dest_addr; 7987 __le32 read_addr; 7988 __le32 read_len32; 7989 }; 7990 7991 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 7992 struct hwrm_dbg_read_direct_output { 7993 __le16 error_code; 7994 __le16 req_type; 7995 __le16 seq_id; 7996 __le16 resp_len; 7997 __le32 crc32; 7998 u8 unused_0[3]; 7999 u8 valid; 8000 }; 8001 8002 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 8003 struct hwrm_dbg_qcaps_input { 8004 __le16 req_type; 8005 __le16 cmpl_ring; 8006 __le16 seq_id; 8007 __le16 target_id; 8008 __le64 resp_addr; 8009 __le16 fid; 8010 u8 unused_0[6]; 8011 }; 8012 8013 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 8014 struct hwrm_dbg_qcaps_output { 8015 __le16 error_code; 8016 __le16 req_type; 8017 __le16 seq_id; 8018 __le16 resp_len; 8019 __le16 fid; 8020 u8 unused_0[2]; 8021 __le32 coredump_component_disable_caps; 8022 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 8023 __le32 flags; 8024 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 8025 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 8026 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 8027 u8 unused_1[3]; 8028 u8 valid; 8029 }; 8030 8031 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 8032 struct hwrm_dbg_qcfg_input { 8033 __le16 req_type; 8034 __le16 cmpl_ring; 8035 __le16 seq_id; 8036 __le16 target_id; 8037 __le64 resp_addr; 8038 __le16 fid; 8039 __le16 flags; 8040 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 8041 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 8042 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 8043 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 8044 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 8045 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 8046 __le32 coredump_component_disable_flags; 8047 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 8048 }; 8049 8050 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 8051 struct hwrm_dbg_qcfg_output { 8052 __le16 error_code; 8053 __le16 req_type; 8054 __le16 seq_id; 8055 __le16 resp_len; 8056 __le16 fid; 8057 u8 unused_0[2]; 8058 __le32 coredump_size; 8059 __le32 flags; 8060 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 8061 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 8062 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 8063 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 8064 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 8065 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 8066 __le16 async_cmpl_ring; 8067 u8 unused_2[2]; 8068 __le32 crashdump_size; 8069 u8 unused_3[3]; 8070 u8 valid; 8071 }; 8072 8073 /* coredump_segment_record (size:128b/16B) */ 8074 struct coredump_segment_record { 8075 __le16 component_id; 8076 __le16 segment_id; 8077 __le16 max_instances; 8078 u8 version_hi; 8079 u8 version_low; 8080 u8 seg_flags; 8081 u8 compress_flags; 8082 #define SFLAG_COMPRESSED_ZLIB 0x1UL 8083 u8 unused_0[2]; 8084 __le32 segment_len; 8085 }; 8086 8087 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 8088 struct hwrm_dbg_coredump_list_input { 8089 __le16 req_type; 8090 __le16 cmpl_ring; 8091 __le16 seq_id; 8092 __le16 target_id; 8093 __le64 resp_addr; 8094 __le64 host_dest_addr; 8095 __le32 host_buf_len; 8096 __le16 seq_no; 8097 u8 flags; 8098 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 8099 u8 unused_0[1]; 8100 }; 8101 8102 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 8103 struct hwrm_dbg_coredump_list_output { 8104 __le16 error_code; 8105 __le16 req_type; 8106 __le16 seq_id; 8107 __le16 resp_len; 8108 u8 flags; 8109 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 8110 u8 unused_0; 8111 __le16 total_segments; 8112 __le16 data_len; 8113 u8 unused_1; 8114 u8 valid; 8115 }; 8116 8117 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 8118 struct hwrm_dbg_coredump_initiate_input { 8119 __le16 req_type; 8120 __le16 cmpl_ring; 8121 __le16 seq_id; 8122 __le16 target_id; 8123 __le64 resp_addr; 8124 __le16 component_id; 8125 __le16 segment_id; 8126 __le16 instance; 8127 __le16 unused_0; 8128 u8 seg_flags; 8129 u8 unused_1[7]; 8130 }; 8131 8132 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 8133 struct hwrm_dbg_coredump_initiate_output { 8134 __le16 error_code; 8135 __le16 req_type; 8136 __le16 seq_id; 8137 __le16 resp_len; 8138 u8 unused_0[7]; 8139 u8 valid; 8140 }; 8141 8142 /* coredump_data_hdr (size:128b/16B) */ 8143 struct coredump_data_hdr { 8144 __le32 address; 8145 __le32 flags_length; 8146 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8147 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8148 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 8149 __le32 instance; 8150 __le32 next_offset; 8151 }; 8152 8153 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8154 struct hwrm_dbg_coredump_retrieve_input { 8155 __le16 req_type; 8156 __le16 cmpl_ring; 8157 __le16 seq_id; 8158 __le16 target_id; 8159 __le64 resp_addr; 8160 __le64 host_dest_addr; 8161 __le32 host_buf_len; 8162 __le32 unused_0; 8163 __le16 component_id; 8164 __le16 segment_id; 8165 __le16 instance; 8166 __le16 unused_1; 8167 u8 seg_flags; 8168 u8 unused_2; 8169 __le16 unused_3; 8170 __le32 unused_4; 8171 __le32 seq_no; 8172 __le32 unused_5; 8173 }; 8174 8175 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 8176 struct hwrm_dbg_coredump_retrieve_output { 8177 __le16 error_code; 8178 __le16 req_type; 8179 __le16 seq_id; 8180 __le16 resp_len; 8181 u8 flags; 8182 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 8183 u8 unused_0; 8184 __le16 data_len; 8185 u8 unused_1[3]; 8186 u8 valid; 8187 }; 8188 8189 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 8190 struct hwrm_dbg_ring_info_get_input { 8191 __le16 req_type; 8192 __le16 cmpl_ring; 8193 __le16 seq_id; 8194 __le16 target_id; 8195 __le64 resp_addr; 8196 u8 ring_type; 8197 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 8198 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 8199 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8200 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8201 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 8202 u8 unused_0[3]; 8203 __le32 fw_ring_id; 8204 }; 8205 8206 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 8207 struct hwrm_dbg_ring_info_get_output { 8208 __le16 error_code; 8209 __le16 req_type; 8210 __le16 seq_id; 8211 __le16 resp_len; 8212 __le32 producer_index; 8213 __le32 consumer_index; 8214 __le32 cag_vector_ctrl; 8215 u8 unused_0[3]; 8216 u8 valid; 8217 }; 8218 8219 /* hwrm_nvm_read_input (size:320b/40B) */ 8220 struct hwrm_nvm_read_input { 8221 __le16 req_type; 8222 __le16 cmpl_ring; 8223 __le16 seq_id; 8224 __le16 target_id; 8225 __le64 resp_addr; 8226 __le64 host_dest_addr; 8227 __le16 dir_idx; 8228 u8 unused_0[2]; 8229 __le32 offset; 8230 __le32 len; 8231 u8 unused_1[4]; 8232 }; 8233 8234 /* hwrm_nvm_read_output (size:128b/16B) */ 8235 struct hwrm_nvm_read_output { 8236 __le16 error_code; 8237 __le16 req_type; 8238 __le16 seq_id; 8239 __le16 resp_len; 8240 u8 unused_0[7]; 8241 u8 valid; 8242 }; 8243 8244 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8245 struct hwrm_nvm_get_dir_entries_input { 8246 __le16 req_type; 8247 __le16 cmpl_ring; 8248 __le16 seq_id; 8249 __le16 target_id; 8250 __le64 resp_addr; 8251 __le64 host_dest_addr; 8252 }; 8253 8254 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8255 struct hwrm_nvm_get_dir_entries_output { 8256 __le16 error_code; 8257 __le16 req_type; 8258 __le16 seq_id; 8259 __le16 resp_len; 8260 u8 unused_0[7]; 8261 u8 valid; 8262 }; 8263 8264 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8265 struct hwrm_nvm_get_dir_info_input { 8266 __le16 req_type; 8267 __le16 cmpl_ring; 8268 __le16 seq_id; 8269 __le16 target_id; 8270 __le64 resp_addr; 8271 }; 8272 8273 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8274 struct hwrm_nvm_get_dir_info_output { 8275 __le16 error_code; 8276 __le16 req_type; 8277 __le16 seq_id; 8278 __le16 resp_len; 8279 __le32 entries; 8280 __le32 entry_length; 8281 u8 unused_0[7]; 8282 u8 valid; 8283 }; 8284 8285 /* hwrm_nvm_write_input (size:384b/48B) */ 8286 struct hwrm_nvm_write_input { 8287 __le16 req_type; 8288 __le16 cmpl_ring; 8289 __le16 seq_id; 8290 __le16 target_id; 8291 __le64 resp_addr; 8292 __le64 host_src_addr; 8293 __le16 dir_type; 8294 __le16 dir_ordinal; 8295 __le16 dir_ext; 8296 __le16 dir_attr; 8297 __le32 dir_data_length; 8298 __le16 option; 8299 __le16 flags; 8300 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 8301 __le32 dir_item_length; 8302 __le32 unused_0; 8303 }; 8304 8305 /* hwrm_nvm_write_output (size:128b/16B) */ 8306 struct hwrm_nvm_write_output { 8307 __le16 error_code; 8308 __le16 req_type; 8309 __le16 seq_id; 8310 __le16 resp_len; 8311 __le32 dir_item_length; 8312 __le16 dir_idx; 8313 u8 unused_0; 8314 u8 valid; 8315 }; 8316 8317 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 8318 struct hwrm_nvm_write_cmd_err { 8319 u8 code; 8320 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 8321 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8322 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 8323 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 8324 u8 unused_0[7]; 8325 }; 8326 8327 /* hwrm_nvm_modify_input (size:320b/40B) */ 8328 struct hwrm_nvm_modify_input { 8329 __le16 req_type; 8330 __le16 cmpl_ring; 8331 __le16 seq_id; 8332 __le16 target_id; 8333 __le64 resp_addr; 8334 __le64 host_src_addr; 8335 __le16 dir_idx; 8336 __le16 flags; 8337 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 8338 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 8339 __le32 offset; 8340 __le32 len; 8341 u8 unused_1[4]; 8342 }; 8343 8344 /* hwrm_nvm_modify_output (size:128b/16B) */ 8345 struct hwrm_nvm_modify_output { 8346 __le16 error_code; 8347 __le16 req_type; 8348 __le16 seq_id; 8349 __le16 resp_len; 8350 u8 unused_0[7]; 8351 u8 valid; 8352 }; 8353 8354 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 8355 struct hwrm_nvm_find_dir_entry_input { 8356 __le16 req_type; 8357 __le16 cmpl_ring; 8358 __le16 seq_id; 8359 __le16 target_id; 8360 __le64 resp_addr; 8361 __le32 enables; 8362 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 8363 __le16 dir_idx; 8364 __le16 dir_type; 8365 __le16 dir_ordinal; 8366 __le16 dir_ext; 8367 u8 opt_ordinal; 8368 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 8369 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 8370 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 8371 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 8372 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 8373 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 8374 u8 unused_0[3]; 8375 }; 8376 8377 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 8378 struct hwrm_nvm_find_dir_entry_output { 8379 __le16 error_code; 8380 __le16 req_type; 8381 __le16 seq_id; 8382 __le16 resp_len; 8383 __le32 dir_item_length; 8384 __le32 dir_data_length; 8385 __le32 fw_ver; 8386 __le16 dir_ordinal; 8387 __le16 dir_idx; 8388 u8 unused_0[7]; 8389 u8 valid; 8390 }; 8391 8392 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 8393 struct hwrm_nvm_erase_dir_entry_input { 8394 __le16 req_type; 8395 __le16 cmpl_ring; 8396 __le16 seq_id; 8397 __le16 target_id; 8398 __le64 resp_addr; 8399 __le16 dir_idx; 8400 u8 unused_0[6]; 8401 }; 8402 8403 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 8404 struct hwrm_nvm_erase_dir_entry_output { 8405 __le16 error_code; 8406 __le16 req_type; 8407 __le16 seq_id; 8408 __le16 resp_len; 8409 u8 unused_0[7]; 8410 u8 valid; 8411 }; 8412 8413 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 8414 struct hwrm_nvm_get_dev_info_input { 8415 __le16 req_type; 8416 __le16 cmpl_ring; 8417 __le16 seq_id; 8418 __le16 target_id; 8419 __le64 resp_addr; 8420 }; 8421 8422 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 8423 struct hwrm_nvm_get_dev_info_output { 8424 __le16 error_code; 8425 __le16 req_type; 8426 __le16 seq_id; 8427 __le16 resp_len; 8428 __le16 manufacturer_id; 8429 __le16 device_id; 8430 __le32 sector_size; 8431 __le32 nvram_size; 8432 __le32 reserved_size; 8433 __le32 available_size; 8434 u8 nvm_cfg_ver_maj; 8435 u8 nvm_cfg_ver_min; 8436 u8 nvm_cfg_ver_upd; 8437 u8 flags; 8438 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 8439 char pkg_name[16]; 8440 __le16 hwrm_fw_major; 8441 __le16 hwrm_fw_minor; 8442 __le16 hwrm_fw_build; 8443 __le16 hwrm_fw_patch; 8444 __le16 mgmt_fw_major; 8445 __le16 mgmt_fw_minor; 8446 __le16 mgmt_fw_build; 8447 __le16 mgmt_fw_patch; 8448 __le16 roce_fw_major; 8449 __le16 roce_fw_minor; 8450 __le16 roce_fw_build; 8451 __le16 roce_fw_patch; 8452 u8 unused_0[7]; 8453 u8 valid; 8454 }; 8455 8456 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 8457 struct hwrm_nvm_mod_dir_entry_input { 8458 __le16 req_type; 8459 __le16 cmpl_ring; 8460 __le16 seq_id; 8461 __le16 target_id; 8462 __le64 resp_addr; 8463 __le32 enables; 8464 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 8465 __le16 dir_idx; 8466 __le16 dir_ordinal; 8467 __le16 dir_ext; 8468 __le16 dir_attr; 8469 __le32 checksum; 8470 }; 8471 8472 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 8473 struct hwrm_nvm_mod_dir_entry_output { 8474 __le16 error_code; 8475 __le16 req_type; 8476 __le16 seq_id; 8477 __le16 resp_len; 8478 u8 unused_0[7]; 8479 u8 valid; 8480 }; 8481 8482 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 8483 struct hwrm_nvm_verify_update_input { 8484 __le16 req_type; 8485 __le16 cmpl_ring; 8486 __le16 seq_id; 8487 __le16 target_id; 8488 __le64 resp_addr; 8489 __le16 dir_type; 8490 __le16 dir_ordinal; 8491 __le16 dir_ext; 8492 u8 unused_0[2]; 8493 }; 8494 8495 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 8496 struct hwrm_nvm_verify_update_output { 8497 __le16 error_code; 8498 __le16 req_type; 8499 __le16 seq_id; 8500 __le16 resp_len; 8501 u8 unused_0[7]; 8502 u8 valid; 8503 }; 8504 8505 /* hwrm_nvm_install_update_input (size:192b/24B) */ 8506 struct hwrm_nvm_install_update_input { 8507 __le16 req_type; 8508 __le16 cmpl_ring; 8509 __le16 seq_id; 8510 __le16 target_id; 8511 __le64 resp_addr; 8512 __le32 install_type; 8513 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 8514 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 8515 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 8516 __le16 flags; 8517 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 8518 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 8519 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 8520 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 8521 u8 unused_0[2]; 8522 }; 8523 8524 /* hwrm_nvm_install_update_output (size:192b/24B) */ 8525 struct hwrm_nvm_install_update_output { 8526 __le16 error_code; 8527 __le16 req_type; 8528 __le16 seq_id; 8529 __le16 resp_len; 8530 __le64 installed_items; 8531 u8 result; 8532 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 8533 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 8534 u8 problem_item; 8535 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 8536 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 8537 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 8538 u8 reset_required; 8539 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 8540 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 8541 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 8542 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 8543 u8 unused_0[4]; 8544 u8 valid; 8545 }; 8546 8547 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 8548 struct hwrm_nvm_install_update_cmd_err { 8549 u8 code; 8550 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 8551 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8552 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 8553 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 8554 u8 unused_0[7]; 8555 }; 8556 8557 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 8558 struct hwrm_nvm_get_variable_input { 8559 __le16 req_type; 8560 __le16 cmpl_ring; 8561 __le16 seq_id; 8562 __le16 target_id; 8563 __le64 resp_addr; 8564 __le64 dest_data_addr; 8565 __le16 data_len; 8566 __le16 option_num; 8567 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8568 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8569 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8570 __le16 dimensions; 8571 __le16 index_0; 8572 __le16 index_1; 8573 __le16 index_2; 8574 __le16 index_3; 8575 u8 flags; 8576 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 8577 u8 unused_0; 8578 }; 8579 8580 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 8581 struct hwrm_nvm_get_variable_output { 8582 __le16 error_code; 8583 __le16 req_type; 8584 __le16 seq_id; 8585 __le16 resp_len; 8586 __le16 data_len; 8587 __le16 option_num; 8588 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 8589 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 8590 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 8591 u8 unused_0[3]; 8592 u8 valid; 8593 }; 8594 8595 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8596 struct hwrm_nvm_get_variable_cmd_err { 8597 u8 code; 8598 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8599 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8600 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8601 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8602 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8603 u8 unused_0[7]; 8604 }; 8605 8606 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8607 struct hwrm_nvm_set_variable_input { 8608 __le16 req_type; 8609 __le16 cmpl_ring; 8610 __le16 seq_id; 8611 __le16 target_id; 8612 __le64 resp_addr; 8613 __le64 src_data_addr; 8614 __le16 data_len; 8615 __le16 option_num; 8616 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8617 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8618 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8619 __le16 dimensions; 8620 __le16 index_0; 8621 __le16 index_1; 8622 __le16 index_2; 8623 __le16 index_3; 8624 u8 flags; 8625 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8626 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8627 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8628 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8629 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 8630 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 8631 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 8632 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 8633 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 8634 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 8635 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8636 u8 unused_0; 8637 }; 8638 8639 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8640 struct hwrm_nvm_set_variable_output { 8641 __le16 error_code; 8642 __le16 req_type; 8643 __le16 seq_id; 8644 __le16 resp_len; 8645 u8 unused_0[7]; 8646 u8 valid; 8647 }; 8648 8649 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8650 struct hwrm_nvm_set_variable_cmd_err { 8651 u8 code; 8652 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8653 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8654 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8655 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8656 u8 unused_0[7]; 8657 }; 8658 8659 /* hwrm_selftest_qlist_input (size:128b/16B) */ 8660 struct hwrm_selftest_qlist_input { 8661 __le16 req_type; 8662 __le16 cmpl_ring; 8663 __le16 seq_id; 8664 __le16 target_id; 8665 __le64 resp_addr; 8666 }; 8667 8668 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8669 struct hwrm_selftest_qlist_output { 8670 __le16 error_code; 8671 __le16 req_type; 8672 __le16 seq_id; 8673 __le16 resp_len; 8674 u8 num_tests; 8675 u8 available_tests; 8676 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8677 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8678 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8679 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8680 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8681 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8682 u8 offline_tests; 8683 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8684 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8685 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8686 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8687 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8688 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8689 u8 unused_0; 8690 __le16 test_timeout; 8691 u8 unused_1[2]; 8692 char test0_name[32]; 8693 char test1_name[32]; 8694 char test2_name[32]; 8695 char test3_name[32]; 8696 char test4_name[32]; 8697 char test5_name[32]; 8698 char test6_name[32]; 8699 char test7_name[32]; 8700 u8 eyescope_target_BER_support; 8701 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 8702 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 8703 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 8704 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 8705 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 8706 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 8707 u8 unused_2[6]; 8708 u8 valid; 8709 }; 8710 8711 /* hwrm_selftest_exec_input (size:192b/24B) */ 8712 struct hwrm_selftest_exec_input { 8713 __le16 req_type; 8714 __le16 cmpl_ring; 8715 __le16 seq_id; 8716 __le16 target_id; 8717 __le64 resp_addr; 8718 u8 flags; 8719 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8720 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8721 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8722 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8723 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8724 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8725 u8 unused_0[7]; 8726 }; 8727 8728 /* hwrm_selftest_exec_output (size:128b/16B) */ 8729 struct hwrm_selftest_exec_output { 8730 __le16 error_code; 8731 __le16 req_type; 8732 __le16 seq_id; 8733 __le16 resp_len; 8734 u8 requested_tests; 8735 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8736 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8737 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8738 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8739 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8740 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8741 u8 test_success; 8742 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8743 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8744 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8745 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8746 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8747 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8748 u8 unused_0[5]; 8749 u8 valid; 8750 }; 8751 8752 /* hwrm_selftest_irq_input (size:128b/16B) */ 8753 struct hwrm_selftest_irq_input { 8754 __le16 req_type; 8755 __le16 cmpl_ring; 8756 __le16 seq_id; 8757 __le16 target_id; 8758 __le64 resp_addr; 8759 }; 8760 8761 /* hwrm_selftest_irq_output (size:128b/16B) */ 8762 struct hwrm_selftest_irq_output { 8763 __le16 error_code; 8764 __le16 req_type; 8765 __le16 seq_id; 8766 __le16 resp_len; 8767 u8 unused_0[7]; 8768 u8 valid; 8769 }; 8770 8771 /* db_push_info (size:64b/8B) */ 8772 struct db_push_info { 8773 u32 push_size_push_index; 8774 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 8775 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 8776 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 8777 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 8778 u32 reserved32; 8779 }; 8780 8781 /* fw_status_reg (size:32b/4B) */ 8782 struct fw_status_reg { 8783 u32 fw_status; 8784 #define FW_STATUS_REG_CODE_MASK 0xffffUL 8785 #define FW_STATUS_REG_CODE_SFT 0 8786 #define FW_STATUS_REG_CODE_READY 0x8000UL 8787 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8788 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8789 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8790 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8791 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8792 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8793 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 8794 }; 8795 8796 /* hcomm_status (size:64b/8B) */ 8797 struct hcomm_status { 8798 u32 sig_ver; 8799 #define HCOMM_STATUS_VER_MASK 0xffUL 8800 #define HCOMM_STATUS_VER_SFT 0 8801 #define HCOMM_STATUS_VER_LATEST 0x1UL 8802 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 8803 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 8804 #define HCOMM_STATUS_SIGNATURE_SFT 8 8805 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 8806 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 8807 u32 fw_status_loc; 8808 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 8809 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 8810 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 8811 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 8812 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 8813 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 8814 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 8815 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 8816 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 8817 }; 8818 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 8819 8820 #endif /* _BNXT_HSI_H_ */ 8821