1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2015 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10 #ifndef BNXT_HSI_H 11 #define BNXT_HSI_H 12 13 /* per-context HW statistics -- chip view */ 14 struct ctx_hw_stats { 15 __le64 rx_ucast_pkts; 16 __le64 rx_mcast_pkts; 17 __le64 rx_bcast_pkts; 18 __le64 rx_discard_pkts; 19 __le64 rx_drop_pkts; 20 __le64 rx_ucast_bytes; 21 __le64 rx_mcast_bytes; 22 __le64 rx_bcast_bytes; 23 __le64 tx_ucast_pkts; 24 __le64 tx_mcast_pkts; 25 __le64 tx_bcast_pkts; 26 __le64 tx_discard_pkts; 27 __le64 tx_drop_pkts; 28 __le64 tx_ucast_bytes; 29 __le64 tx_mcast_bytes; 30 __le64 tx_bcast_bytes; 31 __le64 tpa_pkts; 32 __le64 tpa_bytes; 33 __le64 tpa_events; 34 __le64 tpa_aborts; 35 }; 36 37 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 38 struct eject_cmpl { 39 __le16 type; 40 #define EJECT_CMPL_TYPE_MASK 0x3fUL 41 #define EJECT_CMPL_TYPE_SFT 0 42 #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0) 43 __le16 len; 44 __le32 opaque; 45 __le32 v; 46 #define EJECT_CMPL_V 0x1UL 47 __le32 unused_2; 48 }; 49 50 /* HWRM Completion Record (16 bytes) */ 51 struct hwrm_cmpl { 52 __le16 type; 53 #define HWRM_CMPL_TYPE_MASK 0x3fUL 54 #define HWRM_CMPL_TYPE_SFT 0 55 #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0) 56 __le16 sequence_id; 57 __le32 unused_1; 58 __le32 v; 59 #define HWRM_CMPL_V 0x1UL 60 __le32 unused_3; 61 }; 62 63 /* HWRM Forwarded Request (16 bytes) */ 64 struct hwrm_fwd_req_cmpl { 65 __le16 req_len_type; 66 #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL 67 #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 68 #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0) 69 #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 70 #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 71 __le16 source_id; 72 __le32 unused_0; 73 __le32 req_buf_addr_v[2]; 74 #define HWRM_FWD_REQ_CMPL_V 0x1UL 75 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 76 #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 77 }; 78 79 /* HWRM Forwarded Response (16 bytes) */ 80 struct hwrm_fwd_resp_cmpl { 81 __le16 type; 82 #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL 83 #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 84 #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0) 85 __le16 source_id; 86 __le16 resp_len; 87 __le16 unused_1; 88 __le32 resp_buf_addr_v[2]; 89 #define HWRM_FWD_RESP_CMPL_V 0x1UL 90 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 91 #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 92 }; 93 94 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 95 struct hwrm_async_event_cmpl { 96 __le16 type; 97 #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 98 #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 99 #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 100 __le16 event_id; 101 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0) 102 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0) 103 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) 104 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) 105 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) 106 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) 107 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) 108 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) 109 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x20UL << 0) 110 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0) 111 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) 112 #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0) 113 __le32 event_data2; 114 u8 opaque_v; 115 #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL 116 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 117 #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 118 u8 unused_1[3]; 119 __le32 event_data1; 120 }; 121 122 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 123 struct hwrm_async_event_cmpl_link_status_change { 124 __le16 type; 125 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 126 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 127 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 128 __le16 event_id; 129 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0) 130 __le32 event_data2; 131 u8 opaque_v; 132 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 133 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 134 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 135 u8 unused_1[3]; 136 __le32 event_data1; 137 #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_UP 0x1UL 138 }; 139 140 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 141 struct hwrm_async_event_cmpl_link_mtu_change { 142 __le16 type; 143 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 144 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 145 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 146 __le16 event_id; 147 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0) 148 __le32 event_data2; 149 u8 opaque_v; 150 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 151 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 152 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 153 u8 unused_1[3]; 154 __le32 event_data1; 155 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 156 #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 157 }; 158 159 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 160 struct hwrm_async_event_cmpl_link_speed_change { 161 __le16 type; 162 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 163 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 164 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 165 __le16 event_id; 166 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) 167 __le32 event_data2; 168 u8 opaque_v; 169 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 170 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 171 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 172 u8 unused_1[3]; 173 __le32 event_data1; 174 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 175 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 176 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 177 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 178 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 179 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 180 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 181 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 182 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 183 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 184 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 185 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 186 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 187 #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 188 }; 189 190 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 191 struct hwrm_async_event_cmpl_dcb_config_change { 192 __le16 type; 193 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 194 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 195 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 196 __le16 event_id; 197 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) 198 __le32 event_data2; 199 u8 opaque_v; 200 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 201 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 202 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 203 u8 unused_1[3]; 204 __le32 event_data1; 205 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 206 #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 207 }; 208 209 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 210 struct hwrm_async_event_cmpl_port_conn_not_allowed { 211 __le16 type; 212 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 213 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 214 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 215 __le16 event_id; 216 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) 217 __le32 event_data2; 218 u8 opaque_v; 219 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 220 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 221 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 222 u8 unused_1[3]; 223 __le32 event_data1; 224 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 225 #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 226 }; 227 228 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 229 struct hwrm_async_event_cmpl_func_drvr_unload { 230 __le16 type; 231 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 232 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 233 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 234 __le16 event_id; 235 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) 236 __le32 event_data2; 237 u8 opaque_v; 238 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 239 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 240 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 241 u8 unused_1[3]; 242 __le32 event_data1; 243 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 244 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 245 }; 246 247 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 248 struct hwrm_async_event_cmpl_func_drvr_load { 249 __le16 type; 250 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 251 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 252 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 253 __le16 event_id; 254 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) 255 __le32 event_data2; 256 u8 opaque_v; 257 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 258 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 259 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 260 u8 unused_1[3]; 261 __le32 event_data1; 262 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 263 #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 264 }; 265 266 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 267 struct hwrm_async_event_cmpl_pf_drvr_unload { 268 __le16 type; 269 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 270 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 271 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 272 __le16 event_id; 273 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) 274 __le32 event_data2; 275 u8 opaque_v; 276 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 277 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 278 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 279 u8 unused_1[3]; 280 __le32 event_data1; 281 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 282 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 283 }; 284 285 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 286 struct hwrm_async_event_cmpl_pf_drvr_load { 287 __le16 type; 288 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 289 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 290 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 291 __le16 event_id; 292 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x20UL << 0) 293 __le32 event_data2; 294 u8 opaque_v; 295 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 296 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 297 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 298 u8 unused_1[3]; 299 __le32 event_data1; 300 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 301 #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 302 }; 303 304 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 305 struct hwrm_async_event_cmpl_vf_flr { 306 __le16 type; 307 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 308 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 309 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 310 __le16 event_id; 311 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0) 312 __le32 event_data2; 313 u8 opaque_v; 314 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 315 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 316 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 317 u8 unused_1[3]; 318 __le32 event_data1; 319 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 320 #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 321 }; 322 323 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 324 struct hwrm_async_event_cmpl_vf_mac_addr_change { 325 __le16 type; 326 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 327 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 328 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 329 __le16 event_id; 330 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) 331 __le32 event_data2; 332 u8 opaque_v; 333 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 334 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 335 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 336 u8 unused_1[3]; 337 __le32 event_data1; 338 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 339 #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 340 }; 341 342 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 343 struct hwrm_async_event_cmpl_hwrm_error { 344 __le16 type; 345 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 346 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 347 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 348 __le16 event_id; 349 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0) 350 __le32 event_data2; 351 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 352 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 353 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0) 354 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0) 355 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0) 356 u8 opaque_v; 357 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 358 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 359 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 360 u8 unused_1[3]; 361 __le32 event_data1; 362 #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 363 }; 364 365 /* HW Resource Manager Specification 0.7.8 */ 366 #define HWRM_VERSION_MAJOR 0 367 #define HWRM_VERSION_MINOR 7 368 #define HWRM_VERSION_UPDATE 8 369 370 #define HWRM_VERSION_STR "0.7.8" 371 /* Following is the signature for HWRM message field that indicates not 372 * applicable (All F's). Need to cast it the size of the field if needed. 373 */ 374 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 375 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 376 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 377 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 378 #define HW_HASH_KEY_SIZE 40 379 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 380 /* Input (16 bytes) */ 381 struct input { 382 __le16 req_type; 383 __le16 cmpl_ring; 384 __le16 seq_id; 385 __le16 target_id; 386 __le64 resp_addr; 387 }; 388 389 /* Output (8 bytes) */ 390 struct output { 391 __le16 error_code; 392 __le16 req_type; 393 __le16 seq_id; 394 __le16 resp_len; 395 }; 396 397 /* Command numbering (8 bytes) */ 398 struct cmd_nums { 399 __le16 req_type; 400 #define HWRM_VER_GET (0x0UL) 401 #define HWRM_FUNC_DISABLE (0x10UL) 402 #define HWRM_FUNC_RESET (0x11UL) 403 #define HWRM_FUNC_GETFID (0x12UL) 404 #define HWRM_FUNC_VF_ALLOC (0x13UL) 405 #define HWRM_FUNC_VF_FREE (0x14UL) 406 #define HWRM_FUNC_QCAPS (0x15UL) 407 #define HWRM_FUNC_QCFG (0x16UL) 408 #define HWRM_FUNC_CFG (0x17UL) 409 #define HWRM_FUNC_QSTATS (0x18UL) 410 #define HWRM_FUNC_CLR_STATS (0x19UL) 411 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 412 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 413 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 414 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 415 #define HWRM_FUNC_DRV_QVER (0x1eUL) 416 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 417 #define HWRM_FUNC_VF_CFG (0x20UL) 418 #define HWRM_PORT_PHY_CFG (0x20UL) 419 #define HWRM_PORT_MAC_CFG (0x21UL) 420 #define HWRM_PORT_ENABLE (0x22UL) 421 #define HWRM_PORT_QSTATS (0x23UL) 422 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 423 #define HWRM_PORT_CLR_STATS (0x25UL) 424 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 425 #define HWRM_PORT_PHY_QCFG (0x27UL) 426 #define HWRM_PORT_MAC_QCFG (0x28UL) 427 #define HWRM_PORT_BLINK_LED (0x29UL) 428 #define HWRM_QUEUE_QPORTCFG (0x30UL) 429 #define HWRM_QUEUE_QCFG (0x31UL) 430 #define HWRM_QUEUE_CFG (0x32UL) 431 #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL) 432 #define HWRM_QUEUE_BUFFERS_CFG (0x34UL) 433 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 434 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 435 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 436 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 437 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 438 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 439 #define HWRM_VNIC_ALLOC (0x40UL) 440 #define HWRM_VNIC_FREE (0x41UL) 441 #define HWRM_VNIC_CFG (0x42UL) 442 #define HWRM_VNIC_QCFG (0x43UL) 443 #define HWRM_VNIC_TPA_CFG (0x44UL) 444 #define HWRM_VNIC_TPA_QCFG (0x45UL) 445 #define HWRM_VNIC_RSS_CFG (0x46UL) 446 #define HWRM_VNIC_RSS_QCFG (0x47UL) 447 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 448 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 449 #define HWRM_RING_ALLOC (0x50UL) 450 #define HWRM_RING_FREE (0x51UL) 451 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 452 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 453 #define HWRM_RING_RESET (0x5eUL) 454 #define HWRM_RING_GRP_ALLOC (0x60UL) 455 #define HWRM_RING_GRP_FREE (0x61UL) 456 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 457 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 458 #define HWRM_ARB_GRP_ALLOC (0x80UL) 459 #define HWRM_ARB_GRP_CFG (0x81UL) 460 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 461 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 462 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 463 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 464 #define HWRM_CFA_L2_SET_BCASTMCAST_MIRRORING (0x94UL) 465 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 466 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 467 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 468 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 469 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 470 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 471 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 472 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 473 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 474 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 475 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 476 #define HWRM_STAT_CTX_FREE (0xb1UL) 477 #define HWRM_STAT_CTX_QUERY (0xb2UL) 478 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 479 #define HWRM_FW_RESET (0xc0UL) 480 #define HWRM_FW_QSTATUS (0xc1UL) 481 #define HWRM_EXEC_FWD_RESP (0xd0UL) 482 #define HWRM_REJECT_FWD_RESP (0xd1UL) 483 #define HWRM_FWD_RESP (0xd2UL) 484 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 485 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 486 #define HWRM_MGMT_L2_FILTER_ALLOC (0x100UL) 487 #define HWRM_MGMT_L2_FILTER_FREE (0x101UL) 488 #define HWRM_DBG_READ_DIRECT (0xff10UL) 489 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 490 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 491 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 492 #define HWRM_DBG_DUMP (0xff14UL) 493 #define HWRM_NVM_MODIFY (0xfff4UL) 494 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 495 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 496 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 497 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 498 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 499 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 500 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 501 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 502 #define HWRM_NVM_READ (0xfffdUL) 503 #define HWRM_NVM_WRITE (0xfffeUL) 504 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 505 __le16 unused_0[3]; 506 }; 507 508 /* Return Codes (8 bytes) */ 509 struct ret_codes { 510 __le16 error_code; 511 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 512 #define HWRM_ERR_CODE_FAIL (0x1UL) 513 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 514 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 515 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 516 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 517 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 518 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 519 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 520 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 521 __le16 unused_0[3]; 522 }; 523 524 /* Output (16 bytes) */ 525 struct hwrm_err_output { 526 __le16 error_code; 527 __le16 req_type; 528 __le16 seq_id; 529 __le16 resp_len; 530 __le32 opaque_0; 531 __le16 opaque_1; 532 u8 opaque_2; 533 u8 valid; 534 }; 535 536 /* Port Tx Statistics Formats (408 bytes) */ 537 struct tx_port_stats { 538 __le64 tx_64b_frames; 539 __le64 tx_65b_127b_frames; 540 __le64 tx_128b_255b_frames; 541 __le64 tx_256b_511b_frames; 542 __le64 tx_512b_1023b_frames; 543 __le64 tx_1024b_1518_frames; 544 __le64 tx_good_vlan_frames; 545 __le64 tx_1519b_2047_frames; 546 __le64 tx_2048b_4095b_frames; 547 __le64 tx_4096b_9216b_frames; 548 __le64 tx_9217b_16383b_frames; 549 __le64 tx_good_frames; 550 __le64 tx_total_frames; 551 __le64 tx_ucast_frames; 552 __le64 tx_mcast_frames; 553 __le64 tx_bcast_frames; 554 __le64 tx_pause_frames; 555 __le64 tx_pfc_frames; 556 __le64 tx_jabber_frames; 557 __le64 tx_fcs_err_frames; 558 __le64 tx_control_frames; 559 __le64 tx_oversz_frames; 560 __le64 tx_single_dfrl_frames; 561 __le64 tx_multi_dfrl_frames; 562 __le64 tx_single_coll_frames; 563 __le64 tx_multi_coll_frames; 564 __le64 tx_late_coll_frames; 565 __le64 tx_excessive_coll_frames; 566 __le64 tx_frag_frames; 567 __le64 tx_err; 568 __le64 tx_tagged_frames; 569 __le64 tx_dbl_tagged_frames; 570 __le64 tx_runt_frames; 571 __le64 tx_fifo_underruns; 572 __le64 tx_pfc_ena_frames_pri0; 573 __le64 tx_pfc_ena_frames_pri1; 574 __le64 tx_pfc_ena_frames_pri2; 575 __le64 tx_pfc_ena_frames_pri3; 576 __le64 tx_pfc_ena_frames_pri4; 577 __le64 tx_pfc_ena_frames_pri5; 578 __le64 tx_pfc_ena_frames_pri6; 579 __le64 tx_pfc_ena_frames_pri7; 580 __le64 tx_eee_lpi_events; 581 __le64 tx_eee_lpi_duration; 582 __le64 tx_llfc_logical_msgs; 583 __le64 tx_hcfc_msgs; 584 __le64 tx_total_collisions; 585 __le64 tx_bytes; 586 __le64 tx_xthol_frames; 587 __le64 tx_stat_discard; 588 __le64 tx_stat_error; 589 }; 590 591 /* Port Rx Statistics Formats (528 bytes) */ 592 struct rx_port_stats { 593 __le64 rx_64b_frames; 594 __le64 rx_65b_127b_frames; 595 __le64 rx_128b_255b_frames; 596 __le64 rx_256b_511b_frames; 597 __le64 rx_512b_1023b_frames; 598 __le64 rx_1024b_1518_frames; 599 __le64 rx_good_vlan_frames; 600 __le64 rx_1519b_2047b_frames; 601 __le64 rx_2048b_4095b_frames; 602 __le64 rx_4096b_9216b_frames; 603 __le64 rx_9217b_16383b_frames; 604 __le64 rx_total_frames; 605 __le64 rx_ucast_frames; 606 __le64 rx_mcast_frames; 607 __le64 rx_bcast_frames; 608 __le64 rx_fcs_err_frames; 609 __le64 rx_ctrl_frames; 610 __le64 rx_pause_frames; 611 __le64 rx_pfc_frames; 612 __le64 rx_unsupported_opcode_frames; 613 __le64 rx_unsupported_da_pausepfc_frames; 614 __le64 rx_wrong_sa_frames; 615 __le64 rx_align_err_frames; 616 __le64 rx_oor_len_frames; 617 __le64 rx_code_err_frames; 618 __le64 rx_false_carrier_frames; 619 __le64 rx_ovrsz_frames; 620 __le64 rx_jbr_frames; 621 __le64 rx_mtu_err_frames; 622 __le64 rx_match_crc_frames; 623 __le64 rx_promiscuous_frames; 624 __le64 rx_tagged_frames; 625 __le64 rx_double_tagged_frames; 626 __le64 rx_trunc_frames; 627 __le64 rx_good_frames; 628 __le64 rx_pfc_xon2xoff_frames_pri0; 629 __le64 rx_pfc_xon2xoff_frames_pri1; 630 __le64 rx_pfc_xon2xoff_frames_pri2; 631 __le64 rx_pfc_xon2xoff_frames_pri3; 632 __le64 rx_pfc_xon2xoff_frames_pri4; 633 __le64 rx_pfc_xon2xoff_frames_pri5; 634 __le64 rx_pfc_xon2xoff_frames_pri6; 635 __le64 rx_pfc_xon2xoff_frames_pri7; 636 __le64 rx_pfc_ena_frames_pri0; 637 __le64 rx_pfc_ena_frames_pri1; 638 __le64 rx_pfc_ena_frames_pri2; 639 __le64 rx_pfc_ena_frames_pri3; 640 __le64 rx_pfc_ena_frames_pri4; 641 __le64 rx_pfc_ena_frames_pri5; 642 __le64 rx_pfc_ena_frames_pri6; 643 __le64 rx_pfc_ena_frames_pri7; 644 __le64 rx_sch_crc_err_frames; 645 __le64 rx_undrsz_frames; 646 __le64 rx_frag_frames; 647 __le64 rx_eee_lpi_events; 648 __le64 rx_eee_lpi_duration; 649 __le64 rx_llfc_physical_msgs; 650 __le64 rx_llfc_logical_msgs; 651 __le64 rx_llfc_msgs_with_crc_err; 652 __le64 rx_hcfc_msgs; 653 __le64 rx_hcfc_msgs_with_crc_err; 654 __le64 rx_bytes; 655 __le64 rx_runt_bytes; 656 __le64 rx_runt_frames; 657 __le64 rx_stat_discard; 658 __le64 rx_stat_err; 659 }; 660 661 /* hwrm_ver_get */ 662 /* Input (24 bytes) */ 663 struct hwrm_ver_get_input { 664 __le16 req_type; 665 __le16 cmpl_ring; 666 __le16 seq_id; 667 __le16 target_id; 668 __le64 resp_addr; 669 u8 hwrm_intf_maj; 670 u8 hwrm_intf_min; 671 u8 hwrm_intf_upd; 672 u8 unused_0[5]; 673 }; 674 675 /* Output (128 bytes) */ 676 struct hwrm_ver_get_output { 677 __le16 error_code; 678 __le16 req_type; 679 __le16 seq_id; 680 __le16 resp_len; 681 u8 hwrm_intf_maj; 682 u8 hwrm_intf_min; 683 u8 hwrm_intf_upd; 684 u8 hwrm_intf_rsvd; 685 u8 hwrm_fw_maj; 686 u8 hwrm_fw_min; 687 u8 hwrm_fw_bld; 688 u8 hwrm_fw_rsvd; 689 u8 ape_fw_maj; 690 u8 ape_fw_min; 691 u8 ape_fw_bld; 692 u8 ape_fw_rsvd; 693 u8 kong_fw_maj; 694 u8 kong_fw_min; 695 u8 kong_fw_bld; 696 u8 kong_fw_rsvd; 697 u8 tang_fw_maj; 698 u8 tang_fw_min; 699 u8 tang_fw_bld; 700 u8 tang_fw_rsvd; 701 u8 bono_fw_maj; 702 u8 bono_fw_min; 703 u8 bono_fw_bld; 704 u8 bono_fw_rsvd; 705 char hwrm_fw_name[16]; 706 char ape_fw_name[16]; 707 char kong_fw_name[16]; 708 char tang_fw_name[16]; 709 char bono_fw_name[16]; 710 __le16 chip_num; 711 u8 chip_rev; 712 u8 chip_metal; 713 u8 chip_bond_id; 714 u8 unused_0; 715 __le16 max_req_win_len; 716 __le16 max_resp_len; 717 __le16 def_req_timeout; 718 u8 unused_1; 719 u8 unused_2; 720 u8 unused_3; 721 u8 valid; 722 }; 723 724 /* hwrm_func_disable */ 725 /* Input (24 bytes) */ 726 struct hwrm_func_disable_input { 727 __le16 req_type; 728 __le16 cmpl_ring; 729 __le16 seq_id; 730 __le16 target_id; 731 __le64 resp_addr; 732 __le32 enables; 733 #define FUNC_DISABLE_REQ_ENABLES_VF_ID_VALID 0x1UL 734 __le16 vf_id; 735 __le16 unused_0; 736 }; 737 738 /* Output (16 bytes) */ 739 struct hwrm_func_disable_output { 740 __le16 error_code; 741 __le16 req_type; 742 __le16 seq_id; 743 __le16 resp_len; 744 __le32 unused_0; 745 u8 unused_1; 746 u8 unused_2; 747 u8 unused_3; 748 u8 valid; 749 }; 750 751 /* hwrm_func_reset */ 752 /* Input (24 bytes) */ 753 struct hwrm_func_reset_input { 754 __le16 req_type; 755 __le16 cmpl_ring; 756 __le16 seq_id; 757 __le16 target_id; 758 __le64 resp_addr; 759 __le32 enables; 760 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 761 __le16 vf_id; 762 __le16 unused_0; 763 }; 764 765 /* Output (16 bytes) */ 766 struct hwrm_func_reset_output { 767 __le16 error_code; 768 __le16 req_type; 769 __le16 seq_id; 770 __le16 resp_len; 771 __le32 unused_0; 772 u8 unused_1; 773 u8 unused_2; 774 u8 unused_3; 775 u8 valid; 776 }; 777 778 /* hwrm_func_getfid */ 779 /* Input (24 bytes) */ 780 struct hwrm_func_getfid_input { 781 __le16 req_type; 782 __le16 cmpl_ring; 783 __le16 seq_id; 784 __le16 target_id; 785 __le64 resp_addr; 786 __le32 enables; 787 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 788 __le16 pci_id; 789 __le16 unused_0; 790 }; 791 792 /* Output (16 bytes) */ 793 struct hwrm_func_getfid_output { 794 __le16 error_code; 795 __le16 req_type; 796 __le16 seq_id; 797 __le16 resp_len; 798 __le16 fid; 799 u8 unused_0; 800 u8 unused_1; 801 u8 unused_2; 802 u8 unused_3; 803 u8 unused_4; 804 u8 valid; 805 }; 806 807 /* hwrm_func_vf_alloc */ 808 /* Input (24 bytes) */ 809 struct hwrm_func_vf_alloc_input { 810 __le16 req_type; 811 __le16 cmpl_ring; 812 __le16 seq_id; 813 __le16 target_id; 814 __le64 resp_addr; 815 __le32 enables; 816 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 817 __le16 first_vf_id; 818 __le16 num_vfs; 819 }; 820 821 /* Output (16 bytes) */ 822 struct hwrm_func_vf_alloc_output { 823 __le16 error_code; 824 __le16 req_type; 825 __le16 seq_id; 826 __le16 resp_len; 827 __le16 first_vf_id; 828 u8 unused_0; 829 u8 unused_1; 830 u8 unused_2; 831 u8 unused_3; 832 u8 unused_4; 833 u8 valid; 834 }; 835 836 /* hwrm_func_vf_free */ 837 /* Input (24 bytes) */ 838 struct hwrm_func_vf_free_input { 839 __le16 req_type; 840 __le16 cmpl_ring; 841 __le16 seq_id; 842 __le16 target_id; 843 __le64 resp_addr; 844 __le32 enables; 845 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 846 __le16 first_vf_id; 847 __le16 num_vfs; 848 }; 849 850 /* Output (16 bytes) */ 851 struct hwrm_func_vf_free_output { 852 __le16 error_code; 853 __le16 req_type; 854 __le16 seq_id; 855 __le16 resp_len; 856 __le32 unused_0; 857 u8 unused_1; 858 u8 unused_2; 859 u8 unused_3; 860 u8 valid; 861 }; 862 863 /* hwrm_func_vf_cfg */ 864 /* Input (24 bytes) */ 865 struct hwrm_func_vf_cfg_input { 866 __le16 req_type; 867 __le16 cmpl_ring; 868 __le16 seq_id; 869 __le16 target_id; 870 __le64 resp_addr; 871 __le32 enables; 872 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 873 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 874 __le16 mtu; 875 __le16 guest_vlan; 876 }; 877 878 /* Output (16 bytes) */ 879 struct hwrm_func_vf_cfg_output { 880 __le16 error_code; 881 __le16 req_type; 882 __le16 seq_id; 883 __le16 resp_len; 884 __le32 unused_0; 885 u8 unused_1; 886 u8 unused_2; 887 u8 unused_3; 888 u8 valid; 889 }; 890 891 /* hwrm_func_qcaps */ 892 /* Input (24 bytes) */ 893 struct hwrm_func_qcaps_input { 894 __le16 req_type; 895 __le16 cmpl_ring; 896 __le16 seq_id; 897 __le16 target_id; 898 __le64 resp_addr; 899 __le16 fid; 900 __le16 unused_0[3]; 901 }; 902 903 /* Output (80 bytes) */ 904 struct hwrm_func_qcaps_output { 905 __le16 error_code; 906 __le16 req_type; 907 __le16 seq_id; 908 __le16 resp_len; 909 __le16 fid; 910 __le16 port_id; 911 __le32 flags; 912 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 913 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 914 u8 perm_mac_address[6]; 915 __le16 max_rsscos_ctx; 916 __le16 max_cmpl_rings; 917 __le16 max_tx_rings; 918 __le16 max_rx_rings; 919 __le16 max_l2_ctxs; 920 __le16 max_vnics; 921 __le16 first_vf_id; 922 __le16 max_vfs; 923 __le16 max_stat_ctx; 924 __le32 max_encap_records; 925 __le32 max_decap_records; 926 __le32 max_tx_em_flows; 927 __le32 max_tx_wm_flows; 928 __le32 max_rx_em_flows; 929 __le32 max_rx_wm_flows; 930 __le32 max_mcast_filters; 931 __le32 max_flow_id; 932 __le32 max_hw_ring_grps; 933 u8 unused_0; 934 u8 unused_1; 935 u8 unused_2; 936 u8 valid; 937 }; 938 939 /* hwrm_func_cfg */ 940 /* Input (88 bytes) */ 941 struct hwrm_func_cfg_input { 942 __le16 req_type; 943 __le16 cmpl_ring; 944 __le16 seq_id; 945 __le16 target_id; 946 __le64 resp_addr; 947 __le16 vf_id; 948 u8 unused_0; 949 u8 unused_1; 950 __le32 flags; 951 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 952 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 953 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 954 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 955 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 956 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 957 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 958 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 959 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 960 __le32 enables; 961 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 962 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 963 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 964 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 965 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 966 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 967 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 968 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 969 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 970 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 971 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 972 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 973 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 974 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 975 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 976 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 977 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 978 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 979 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 980 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 981 __le16 mtu; 982 __le16 mru; 983 __le16 num_rsscos_ctxs; 984 __le16 num_cmpl_rings; 985 __le16 num_tx_rings; 986 __le16 num_rx_rings; 987 __le16 num_l2_ctxs; 988 __le16 num_vnics; 989 __le16 num_stat_ctxs; 990 __le16 num_hw_ring_grps; 991 u8 dflt_mac_addr[6]; 992 __le16 dflt_vlan; 993 __be32 dflt_ip_addr[4]; 994 __le32 min_bw; 995 __le32 max_bw; 996 __le16 async_event_cr; 997 u8 vlan_antispoof_mode; 998 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0) 999 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0) 1000 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0) 1001 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0) 1002 u8 allowed_vlan_pris; 1003 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_NOCHECK (0x0UL << 0) 1004 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_VALIDATE_VLAN (0x1UL << 0) 1005 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_INSERT_IF_VLANDNE (0x2UL << 0) 1006 #define FUNC_CFG_REQ_ALLOWED_VLAN_PRIS_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0) 1007 u8 evb_mode; 1008 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0) 1009 #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0) 1010 #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0) 1011 u8 unused_2; 1012 __le16 num_mcast_filters; 1013 }; 1014 1015 /* Output (16 bytes) */ 1016 struct hwrm_func_cfg_output { 1017 __le16 error_code; 1018 __le16 req_type; 1019 __le16 seq_id; 1020 __le16 resp_len; 1021 __le32 unused_0; 1022 u8 unused_1; 1023 u8 unused_2; 1024 u8 unused_3; 1025 u8 valid; 1026 }; 1027 1028 /* hwrm_func_qstats */ 1029 /* Input (24 bytes) */ 1030 struct hwrm_func_qstats_input { 1031 __le16 req_type; 1032 __le16 cmpl_ring; 1033 __le16 seq_id; 1034 __le16 target_id; 1035 __le64 resp_addr; 1036 __le16 fid; 1037 __le16 unused_0[3]; 1038 }; 1039 1040 /* Output (176 bytes) */ 1041 struct hwrm_func_qstats_output { 1042 __le16 error_code; 1043 __le16 req_type; 1044 __le16 seq_id; 1045 __le16 resp_len; 1046 __le64 tx_ucast_pkts; 1047 __le64 tx_mcast_pkts; 1048 __le64 tx_bcast_pkts; 1049 __le64 tx_err_pkts; 1050 __le64 tx_drop_pkts; 1051 __le64 tx_ucast_bytes; 1052 __le64 tx_mcast_bytes; 1053 __le64 tx_bcast_bytes; 1054 __le64 rx_ucast_pkts; 1055 __le64 rx_mcast_pkts; 1056 __le64 rx_bcast_pkts; 1057 __le64 rx_err_pkts; 1058 __le64 rx_drop_pkts; 1059 __le64 rx_ucast_bytes; 1060 __le64 rx_mcast_bytes; 1061 __le64 rx_bcast_bytes; 1062 __le64 rx_agg_pkts; 1063 __le64 rx_agg_bytes; 1064 __le64 rx_agg_events; 1065 __le64 rx_agg_aborts; 1066 __le32 unused_0; 1067 u8 unused_1; 1068 u8 unused_2; 1069 u8 unused_3; 1070 u8 valid; 1071 }; 1072 1073 /* hwrm_func_clr_stats */ 1074 /* Input (24 bytes) */ 1075 struct hwrm_func_clr_stats_input { 1076 __le16 req_type; 1077 __le16 cmpl_ring; 1078 __le16 seq_id; 1079 __le16 target_id; 1080 __le64 resp_addr; 1081 __le16 fid; 1082 __le16 unused_0[3]; 1083 }; 1084 1085 /* Output (16 bytes) */ 1086 struct hwrm_func_clr_stats_output { 1087 __le16 error_code; 1088 __le16 req_type; 1089 __le16 seq_id; 1090 __le16 resp_len; 1091 __le32 unused_0; 1092 u8 unused_1; 1093 u8 unused_2; 1094 u8 unused_3; 1095 u8 valid; 1096 }; 1097 1098 /* hwrm_func_vf_resc_free */ 1099 /* Input (24 bytes) */ 1100 struct hwrm_func_vf_resc_free_input { 1101 __le16 req_type; 1102 __le16 cmpl_ring; 1103 __le16 seq_id; 1104 __le16 target_id; 1105 __le64 resp_addr; 1106 __le16 vf_id; 1107 __le16 unused_0[3]; 1108 }; 1109 1110 /* Output (16 bytes) */ 1111 struct hwrm_func_vf_resc_free_output { 1112 __le16 error_code; 1113 __le16 req_type; 1114 __le16 seq_id; 1115 __le16 resp_len; 1116 __le32 unused_0; 1117 u8 unused_1; 1118 u8 unused_2; 1119 u8 unused_3; 1120 u8 valid; 1121 }; 1122 1123 /* hwrm_func_vf_vnic_ids_query */ 1124 /* Input (32 bytes) */ 1125 struct hwrm_func_vf_vnic_ids_query_input { 1126 __le16 req_type; 1127 __le16 cmpl_ring; 1128 __le16 seq_id; 1129 __le16 target_id; 1130 __le64 resp_addr; 1131 __le16 vf_id; 1132 u8 unused_0; 1133 u8 unused_1; 1134 __le32 max_vnic_id_cnt; 1135 __le64 vnic_id_tbl_addr; 1136 }; 1137 1138 /* Output (16 bytes) */ 1139 struct hwrm_func_vf_vnic_ids_query_output { 1140 __le16 error_code; 1141 __le16 req_type; 1142 __le16 seq_id; 1143 __le16 resp_len; 1144 __le32 vnic_id_cnt; 1145 u8 unused_0; 1146 u8 unused_1; 1147 u8 unused_2; 1148 u8 valid; 1149 }; 1150 1151 /* hwrm_func_drv_rgtr */ 1152 /* Input (80 bytes) */ 1153 struct hwrm_func_drv_rgtr_input { 1154 __le16 req_type; 1155 __le16 cmpl_ring; 1156 __le16 seq_id; 1157 __le16 target_id; 1158 __le64 resp_addr; 1159 __le32 flags; 1160 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1161 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1162 __le32 enables; 1163 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1164 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1165 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1166 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1167 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1168 __le16 os_type; 1169 u8 ver_maj; 1170 u8 ver_min; 1171 u8 ver_upd; 1172 u8 unused_0; 1173 __le16 unused_1; 1174 __le32 timestamp; 1175 __le32 unused_2; 1176 __le32 vf_req_fwd[8]; 1177 __le32 async_event_fwd[8]; 1178 }; 1179 1180 /* Output (16 bytes) */ 1181 struct hwrm_func_drv_rgtr_output { 1182 __le16 error_code; 1183 __le16 req_type; 1184 __le16 seq_id; 1185 __le16 resp_len; 1186 __le32 unused_0; 1187 u8 unused_1; 1188 u8 unused_2; 1189 u8 unused_3; 1190 u8 valid; 1191 }; 1192 1193 /* hwrm_func_drv_unrgtr */ 1194 /* Input (24 bytes) */ 1195 struct hwrm_func_drv_unrgtr_input { 1196 __le16 req_type; 1197 __le16 cmpl_ring; 1198 __le16 seq_id; 1199 __le16 target_id; 1200 __le64 resp_addr; 1201 __le32 flags; 1202 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1203 __le32 unused_0; 1204 }; 1205 1206 /* Output (16 bytes) */ 1207 struct hwrm_func_drv_unrgtr_output { 1208 __le16 error_code; 1209 __le16 req_type; 1210 __le16 seq_id; 1211 __le16 resp_len; 1212 __le32 unused_0; 1213 u8 unused_1; 1214 u8 unused_2; 1215 u8 unused_3; 1216 u8 valid; 1217 }; 1218 1219 /* hwrm_func_buf_rgtr */ 1220 /* Input (128 bytes) */ 1221 struct hwrm_func_buf_rgtr_input { 1222 __le16 req_type; 1223 __le16 cmpl_ring; 1224 __le16 seq_id; 1225 __le16 target_id; 1226 __le64 resp_addr; 1227 __le32 enables; 1228 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1229 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1230 __le16 vf_id; 1231 __le16 req_buf_num_pages; 1232 __le16 req_buf_page_size; 1233 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0) 1234 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0) 1235 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0) 1236 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0) 1237 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x16UL << 0) 1238 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x17UL << 0) 1239 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0) 1240 __le16 req_buf_len; 1241 __le16 resp_buf_len; 1242 u8 unused_0; 1243 u8 unused_1; 1244 __le64 req_buf_page_addr0; 1245 __le64 req_buf_page_addr1; 1246 __le64 req_buf_page_addr2; 1247 __le64 req_buf_page_addr3; 1248 __le64 req_buf_page_addr4; 1249 __le64 req_buf_page_addr5; 1250 __le64 req_buf_page_addr6; 1251 __le64 req_buf_page_addr7; 1252 __le64 req_buf_page_addr8; 1253 __le64 req_buf_page_addr9; 1254 __le64 error_buf_addr; 1255 __le64 resp_buf_addr; 1256 }; 1257 1258 /* Output (16 bytes) */ 1259 struct hwrm_func_buf_rgtr_output { 1260 __le16 error_code; 1261 __le16 req_type; 1262 __le16 seq_id; 1263 __le16 resp_len; 1264 __le32 unused_0; 1265 u8 unused_1; 1266 u8 unused_2; 1267 u8 unused_3; 1268 u8 valid; 1269 }; 1270 1271 /* hwrm_func_drv_qver */ 1272 /* Input (24 bytes) */ 1273 struct hwrm_func_drv_qver_input { 1274 __le16 req_type; 1275 __le16 cmpl_ring; 1276 __le16 seq_id; 1277 __le16 target_id; 1278 __le64 resp_addr; 1279 __le32 enables; 1280 #define FUNC_DRV_QVER_REQ_ENABLES_OS_TYPE_VALID 0x1UL 1281 #define FUNC_DRV_QVER_REQ_ENABLES_VER_VALID 0x2UL 1282 __le16 fid; 1283 __le16 unused_0; 1284 }; 1285 1286 /* Output (16 bytes) */ 1287 struct hwrm_func_drv_qver_output { 1288 __le16 error_code; 1289 __le16 req_type; 1290 __le16 seq_id; 1291 __le16 resp_len; 1292 __le16 os_type; 1293 u8 ver_maj; 1294 u8 ver_min; 1295 u8 ver_upd; 1296 u8 unused_0; 1297 u8 unused_1; 1298 u8 valid; 1299 }; 1300 1301 /* hwrm_port_phy_cfg */ 1302 /* Input (48 bytes) */ 1303 struct hwrm_port_phy_cfg_input { 1304 __le16 req_type; 1305 __le16 cmpl_ring; 1306 __le16 seq_id; 1307 __le16 target_id; 1308 __le64 resp_addr; 1309 __le32 flags; 1310 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1311 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL 1312 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1313 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1314 __le32 enables; 1315 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1316 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1317 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1318 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1319 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1320 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1321 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1322 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1323 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1324 __le16 port_id; 1325 __le16 force_link_speed; 1326 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0) 1327 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0) 1328 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0) 1329 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0) 1330 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0) 1331 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0) 1332 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0) 1333 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0) 1334 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0) 1335 u8 auto_mode; 1336 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0) 1337 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1338 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1339 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 1340 #define PORT_PHY_CFG_REQ_AUTO_MODE_MASK (0x4UL << 0) 1341 u8 auto_duplex; 1342 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0) 1343 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0) 1344 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0) 1345 u8 auto_pause; 1346 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1347 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1348 u8 unused_0; 1349 __le16 auto_link_speed; 1350 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0) 1351 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0) 1352 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0) 1353 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0) 1354 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0) 1355 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0) 1356 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0) 1357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0) 1358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0) 1359 __le16 auto_link_speed_mask; 1360 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1361 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1362 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1363 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1364 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1365 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1366 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1367 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1368 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1371 u8 wirespeed; 1372 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0) 1373 #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0) 1374 u8 lpbk; 1375 #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0) 1376 #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0) 1377 #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0) 1378 u8 force_pause; 1379 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1380 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1381 u8 unused_1; 1382 __le32 preemphasis; 1383 __le32 unused_2; 1384 }; 1385 1386 /* Output (16 bytes) */ 1387 struct hwrm_port_phy_cfg_output { 1388 __le16 error_code; 1389 __le16 req_type; 1390 __le16 seq_id; 1391 __le16 resp_len; 1392 __le32 unused_0; 1393 u8 unused_1; 1394 u8 unused_2; 1395 u8 unused_3; 1396 u8 valid; 1397 }; 1398 1399 /* hwrm_port_phy_qcfg */ 1400 /* Input (24 bytes) */ 1401 struct hwrm_port_phy_qcfg_input { 1402 __le16 req_type; 1403 __le16 cmpl_ring; 1404 __le16 seq_id; 1405 __le16 target_id; 1406 __le64 resp_addr; 1407 __le16 port_id; 1408 __le16 unused_0[3]; 1409 }; 1410 1411 /* Output (48 bytes) */ 1412 struct hwrm_port_phy_qcfg_output { 1413 __le16 error_code; 1414 __le16 req_type; 1415 __le16 seq_id; 1416 __le16 resp_len; 1417 u8 link; 1418 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0) 1419 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0) 1420 #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0) 1421 u8 unused_0; 1422 __le16 link_speed; 1423 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0) 1424 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0) 1425 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0) 1426 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0) 1427 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0) 1428 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0) 1429 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0) 1430 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0) 1431 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0) 1432 u8 duplex; 1433 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0) 1434 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0) 1435 u8 pause; 1436 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1437 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1438 __le16 support_speeds; 1439 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1440 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1441 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1442 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1443 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1444 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1445 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1446 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1447 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1448 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1449 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1450 __le16 force_link_speed; 1451 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0) 1452 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0) 1453 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0) 1454 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0) 1455 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0) 1456 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0) 1457 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0) 1458 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0) 1459 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0) 1460 u8 auto_mode; 1461 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0) 1462 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1463 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1464 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 1465 #define PORT_PHY_QCFG_RESP_AUTO_MODE_MASK (0x4UL << 0) 1466 u8 auto_pause; 1467 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1468 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1469 __le16 auto_link_speed; 1470 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0) 1471 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0) 1472 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0) 1473 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0) 1474 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0) 1475 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0) 1476 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0) 1477 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0) 1478 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0) 1479 __le16 auto_link_speed_mask; 1480 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1481 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1482 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1483 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1484 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1485 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1486 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1487 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1488 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1489 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1490 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1491 u8 wirespeed; 1492 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0) 1493 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0) 1494 u8 lpbk; 1495 #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0) 1496 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0) 1497 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0) 1498 u8 force_pause; 1499 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1500 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1501 u8 duplex_setting; 1502 #define PORT_PHY_QCFG_RESP_DUPLEX_SETTING_HALF (0x0UL << 0) 1503 #define PORT_PHY_QCFG_RESP_DUPLEX_SETTING_FULL (0x1UL << 0) 1504 __le32 preemphasis; 1505 u8 phy_maj; 1506 u8 phy_min; 1507 u8 phy_bld; 1508 u8 phy_type; 1509 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR4 (0x1UL << 0) 1510 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0) 1511 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR4 (0x3UL << 0) 1512 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR4 (0x4UL << 0) 1513 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0) 1514 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX4 (0x6UL << 0) 1515 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0) 1516 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0) 1517 u8 media_type; 1518 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0) 1519 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0) 1520 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0) 1521 u8 transceiver_type; 1522 #define PORT_PHY_QCFG_RESP_TRANSCEIVER_TYPE_XCVR_INTERNAL (0x1UL << 0) 1523 #define PORT_PHY_QCFG_RESP_TRANSCEIVER_TYPE_XCVR_EXTERNAL (0x2UL << 0) 1524 u8 phy_addr; 1525 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1526 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1527 u8 unused_2; 1528 __le16 link_partner_adv_speeds; 1529 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1530 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1531 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1532 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1533 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1534 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1535 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1536 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1537 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1538 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1539 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1540 u8 link_partner_adv_auto_mode; 1541 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0) 1542 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1543 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1544 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 1545 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_MASK (0x4UL << 0) 1546 u8 link_partner_adv_pause; 1547 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1548 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1549 u8 unused_3; 1550 u8 unused_4; 1551 u8 unused_5; 1552 u8 valid; 1553 }; 1554 1555 /* hwrm_port_mac_cfg */ 1556 /* Input (32 bytes) */ 1557 struct hwrm_port_mac_cfg_input { 1558 __le16 req_type; 1559 __le16 cmpl_ring; 1560 __le16 seq_id; 1561 __le16 target_id; 1562 __le64 resp_addr; 1563 __le32 flags; 1564 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1565 #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL 1566 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1567 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1568 __le32 enables; 1569 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1570 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1571 #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL 1572 #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL 1573 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1574 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1575 __le16 port_id; 1576 u8 ipg; 1577 u8 lpbk; 1578 #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0) 1579 #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0) 1580 #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0) 1581 u8 ivlan_pri2cos_map_pri; 1582 u8 lcos_map_pri; 1583 u8 tunnel_pri2cos_map_pri; 1584 u8 dscp2pri_map_pri; 1585 }; 1586 1587 /* Output (16 bytes) */ 1588 struct hwrm_port_mac_cfg_output { 1589 __le16 error_code; 1590 __le16 req_type; 1591 __le16 seq_id; 1592 __le16 resp_len; 1593 __le16 mru; 1594 __le16 mtu; 1595 u8 ipg; 1596 u8 lpbk; 1597 #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0) 1598 #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0) 1599 #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0) 1600 u8 unused_0; 1601 u8 valid; 1602 }; 1603 1604 /* hwrm_port_enable */ 1605 /* Input (24 bytes) */ 1606 struct hwrm_port_enable_input { 1607 __le16 req_type; 1608 __le16 cmpl_ring; 1609 __le16 seq_id; 1610 __le16 target_id; 1611 __le64 resp_addr; 1612 __le32 flags; 1613 #define PORT_ENABLE_REQ_FLAGS_FORWARD_TRAFFIC 0x1UL 1614 __le16 port_id; 1615 __le16 unused_0; 1616 }; 1617 1618 /* Output (16 bytes) */ 1619 struct hwrm_port_enable_output { 1620 __le16 error_code; 1621 __le16 req_type; 1622 __le16 seq_id; 1623 __le16 resp_len; 1624 __le32 unused_0; 1625 u8 unused_1; 1626 u8 unused_2; 1627 u8 unused_3; 1628 u8 valid; 1629 }; 1630 1631 /* hwrm_port_qstats */ 1632 /* Input (40 bytes) */ 1633 struct hwrm_port_qstats_input { 1634 __le16 req_type; 1635 __le16 cmpl_ring; 1636 __le16 seq_id; 1637 __le16 target_id; 1638 __le64 resp_addr; 1639 __le16 port_id; 1640 u8 unused_0; 1641 u8 unused_1; 1642 u8 unused_2[3]; 1643 u8 unused_3; 1644 __le64 tx_stat_host_addr; 1645 __le64 rx_stat_host_addr; 1646 }; 1647 1648 /* Output (16 bytes) */ 1649 struct hwrm_port_qstats_output { 1650 __le16 error_code; 1651 __le16 req_type; 1652 __le16 seq_id; 1653 __le16 resp_len; 1654 __le32 unused_0; 1655 u8 unused_1; 1656 u8 unused_2; 1657 u8 unused_3; 1658 u8 valid; 1659 }; 1660 1661 /* hwrm_port_lpbk_qstats */ 1662 /* Input (16 bytes) */ 1663 struct hwrm_port_lpbk_qstats_input { 1664 __le16 req_type; 1665 __le16 cmpl_ring; 1666 __le16 seq_id; 1667 __le16 target_id; 1668 __le64 resp_addr; 1669 }; 1670 1671 /* Output (64 bytes) */ 1672 struct hwrm_port_lpbk_qstats_output { 1673 __le16 error_code; 1674 __le16 req_type; 1675 __le16 seq_id; 1676 __le16 resp_len; 1677 __le64 lpbk_ucast_frames; 1678 __le64 lpbk_mcast_frames; 1679 __le64 lpbk_bcast_frames; 1680 __le64 lpbk_ucast_bytes; 1681 __le64 lpbk_mcast_bytes; 1682 __le64 lpbk_bcast_bytes; 1683 __le32 unused_0; 1684 u8 unused_1; 1685 u8 unused_2; 1686 u8 unused_3; 1687 u8 valid; 1688 }; 1689 1690 /* hwrm_port_clr_stats */ 1691 /* Input (24 bytes) */ 1692 struct hwrm_port_clr_stats_input { 1693 __le16 req_type; 1694 __le16 cmpl_ring; 1695 __le16 seq_id; 1696 __le16 target_id; 1697 __le64 resp_addr; 1698 __le16 port_id; 1699 __le16 unused_0[3]; 1700 }; 1701 1702 /* Output (16 bytes) */ 1703 struct hwrm_port_clr_stats_output { 1704 __le16 error_code; 1705 __le16 req_type; 1706 __le16 seq_id; 1707 __le16 resp_len; 1708 __le32 unused_0; 1709 u8 unused_1; 1710 u8 unused_2; 1711 u8 unused_3; 1712 u8 valid; 1713 }; 1714 1715 /* hwrm_port_lpbk_clr_stats */ 1716 /* Input (16 bytes) */ 1717 struct hwrm_port_lpbk_clr_stats_input { 1718 __le16 req_type; 1719 __le16 cmpl_ring; 1720 __le16 seq_id; 1721 __le16 target_id; 1722 __le64 resp_addr; 1723 }; 1724 1725 /* Output (16 bytes) */ 1726 struct hwrm_port_lpbk_clr_stats_output { 1727 __le16 error_code; 1728 __le16 req_type; 1729 __le16 seq_id; 1730 __le16 resp_len; 1731 __le32 unused_0; 1732 u8 unused_1; 1733 u8 unused_2; 1734 u8 unused_3; 1735 u8 valid; 1736 }; 1737 1738 /* hwrm_port_blink_led */ 1739 /* Input (24 bytes) */ 1740 struct hwrm_port_blink_led_input { 1741 __le16 req_type; 1742 __le16 cmpl_ring; 1743 __le16 seq_id; 1744 __le16 target_id; 1745 __le64 resp_addr; 1746 __le32 num_blinks; 1747 __le32 unused_0; 1748 }; 1749 1750 /* Output (16 bytes) */ 1751 struct hwrm_port_blink_led_output { 1752 __le16 error_code; 1753 __le16 req_type; 1754 __le16 seq_id; 1755 __le16 resp_len; 1756 __le32 unused_0; 1757 u8 unused_1; 1758 u8 unused_2; 1759 u8 unused_3; 1760 u8 valid; 1761 }; 1762 1763 /* hwrm_queue_qportcfg */ 1764 /* Input (24 bytes) */ 1765 struct hwrm_queue_qportcfg_input { 1766 __le16 req_type; 1767 __le16 cmpl_ring; 1768 __le16 seq_id; 1769 __le16 target_id; 1770 __le64 resp_addr; 1771 __le32 flags; 1772 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 1773 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 1774 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 1775 __le16 port_id; 1776 __le16 unused_0; 1777 }; 1778 1779 /* Output (32 bytes) */ 1780 struct hwrm_queue_qportcfg_output { 1781 __le16 error_code; 1782 __le16 req_type; 1783 __le16 seq_id; 1784 __le16 resp_len; 1785 u8 max_configurable_queues; 1786 u8 max_configurable_lossless_queues; 1787 u8 queue_cfg_allowed; 1788 u8 queue_buffers_cfg_allowed; 1789 u8 queue_pfcenable_cfg_allowed; 1790 u8 queue_pri2cos_cfg_allowed; 1791 u8 queue_cos2bw_cfg_allowed; 1792 u8 queue_id0; 1793 u8 queue_id0_service_profile; 1794 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1795 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1796 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1797 u8 queue_id1; 1798 u8 queue_id1_service_profile; 1799 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1800 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1801 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1802 u8 queue_id2; 1803 u8 queue_id2_service_profile; 1804 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1805 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1806 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1807 u8 queue_id3; 1808 u8 queue_id3_service_profile; 1809 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1810 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1811 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1812 u8 queue_id4; 1813 u8 queue_id4_service_profile; 1814 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1815 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1816 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1817 u8 queue_id5; 1818 u8 queue_id5_service_profile; 1819 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1820 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1821 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1822 u8 queue_id6; 1823 u8 queue_id6_service_profile; 1824 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1825 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1826 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1827 u8 queue_id7; 1828 u8 queue_id7_service_profile; 1829 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1830 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1831 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1832 u8 valid; 1833 }; 1834 1835 /* hwrm_queue_cfg */ 1836 /* Input (40 bytes) */ 1837 struct hwrm_queue_cfg_input { 1838 __le16 req_type; 1839 __le16 cmpl_ring; 1840 __le16 seq_id; 1841 __le16 target_id; 1842 __le64 resp_addr; 1843 __le32 flags; 1844 #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL 1845 #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 1846 #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 1847 __le32 enables; 1848 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 1849 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 1850 __le32 queue_id; 1851 __le32 dflt_len; 1852 u8 service_profile; 1853 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0) 1854 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 1855 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 1856 u8 unused_0[7]; 1857 }; 1858 1859 /* Output (16 bytes) */ 1860 struct hwrm_queue_cfg_output { 1861 __le16 error_code; 1862 __le16 req_type; 1863 __le16 seq_id; 1864 __le16 resp_len; 1865 __le32 unused_0; 1866 u8 unused_1; 1867 u8 unused_2; 1868 u8 unused_3; 1869 u8 valid; 1870 }; 1871 1872 /* hwrm_queue_buffers_cfg */ 1873 /* Input (56 bytes) */ 1874 struct hwrm_queue_buffers_cfg_input { 1875 __le16 req_type; 1876 __le16 cmpl_ring; 1877 __le16 seq_id; 1878 __le16 target_id; 1879 __le64 resp_addr; 1880 __le32 flags; 1881 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL 1882 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 1883 #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 1884 __le32 enables; 1885 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL 1886 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL 1887 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_GROUP 0x4UL 1888 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x8UL 1889 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x10UL 1890 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x20UL 1891 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x40UL 1892 #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x80UL 1893 __le32 queue_id; 1894 __le32 reserved; 1895 __le32 shared; 1896 __le32 xoff; 1897 __le32 xon; 1898 __le32 full; 1899 __le32 notfull; 1900 __le32 max; 1901 }; 1902 1903 /* Output (16 bytes) */ 1904 struct hwrm_queue_buffers_cfg_output { 1905 __le16 error_code; 1906 __le16 req_type; 1907 __le16 seq_id; 1908 __le16 resp_len; 1909 __le32 unused_0; 1910 u8 unused_1; 1911 u8 unused_2; 1912 u8 unused_3; 1913 u8 valid; 1914 }; 1915 1916 /* hwrm_queue_pfcenable_cfg */ 1917 /* Input (24 bytes) */ 1918 struct hwrm_queue_pfcenable_cfg_input { 1919 __le16 req_type; 1920 __le16 cmpl_ring; 1921 __le16 seq_id; 1922 __le16 target_id; 1923 __le64 resp_addr; 1924 __le32 enables; 1925 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI0_PFC_ENABLED 0x1UL 1926 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI1_PFC_ENABLED 0x2UL 1927 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI2_PFC_ENABLED 0x4UL 1928 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI3_PFC_ENABLED 0x8UL 1929 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI4_PFC_ENABLED 0x10UL 1930 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI5_PFC_ENABLED 0x20UL 1931 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI6_PFC_ENABLED 0x40UL 1932 #define QUEUE_PFCENABLE_CFG_REQ_ENABLES_PRI7_PFC_ENABLED 0x80UL 1933 __le16 port_id; 1934 __le16 unused_0; 1935 }; 1936 1937 /* Output (16 bytes) */ 1938 struct hwrm_queue_pfcenable_cfg_output { 1939 __le16 error_code; 1940 __le16 req_type; 1941 __le16 seq_id; 1942 __le16 resp_len; 1943 __le32 unused_0; 1944 u8 unused_1; 1945 u8 unused_2; 1946 u8 unused_3; 1947 u8 valid; 1948 }; 1949 1950 /* hwrm_queue_pri2cos_cfg */ 1951 /* Input (40 bytes) */ 1952 struct hwrm_queue_pri2cos_cfg_input { 1953 __le16 req_type; 1954 __le16 cmpl_ring; 1955 __le16 seq_id; 1956 __le16 target_id; 1957 __le64 resp_addr; 1958 __le32 flags; 1959 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL 1960 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 1961 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 1962 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL 1963 __le32 enables; 1964 u8 port_id; 1965 u8 pri0_cos; 1966 u8 pri1_cos; 1967 u8 pri2_cos; 1968 u8 pri3_cos; 1969 u8 pri4_cos; 1970 u8 pri5_cos; 1971 u8 pri6_cos; 1972 u8 pri7_cos; 1973 u8 unused_0[7]; 1974 }; 1975 1976 /* Output (16 bytes) */ 1977 struct hwrm_queue_pri2cos_cfg_output { 1978 __le16 error_code; 1979 __le16 req_type; 1980 __le16 seq_id; 1981 __le16 resp_len; 1982 __le32 unused_0; 1983 u8 unused_1; 1984 u8 unused_2; 1985 u8 unused_3; 1986 u8 valid; 1987 }; 1988 1989 /* hwrm_queue_cos2bw_cfg */ 1990 /* Input (128 bytes) */ 1991 struct hwrm_queue_cos2bw_cfg_input { 1992 __le16 req_type; 1993 __le16 cmpl_ring; 1994 __le16 seq_id; 1995 __le16 target_id; 1996 __le64 resp_addr; 1997 __le32 flags; 1998 __le32 enables; 1999 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2000 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2001 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2002 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2003 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2004 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2005 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2006 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2007 __le16 port_id; 2008 u8 queue_id0; 2009 u8 unused_0; 2010 __le32 queue_id0_min_bw; 2011 __le32 queue_id0_max_bw; 2012 u8 queue_id0_tsa_assign; 2013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0) 2014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0) 2015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2017 u8 queue_id0_pri_lvl; 2018 u8 queue_id0_bw_weight; 2019 u8 queue_id1; 2020 __le32 queue_id1_min_bw; 2021 __le32 queue_id1_max_bw; 2022 u8 queue_id1_tsa_assign; 2023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0) 2024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0) 2025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2027 u8 queue_id1_pri_lvl; 2028 u8 queue_id1_bw_weight; 2029 u8 queue_id2; 2030 __le32 queue_id2_min_bw; 2031 __le32 queue_id2_max_bw; 2032 u8 queue_id2_tsa_assign; 2033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0) 2034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0) 2035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2037 u8 queue_id2_pri_lvl; 2038 u8 queue_id2_bw_weight; 2039 u8 queue_id3; 2040 __le32 queue_id3_min_bw; 2041 __le32 queue_id3_max_bw; 2042 u8 queue_id3_tsa_assign; 2043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0) 2044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0) 2045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2047 u8 queue_id3_pri_lvl; 2048 u8 queue_id3_bw_weight; 2049 u8 queue_id4; 2050 __le32 queue_id4_min_bw; 2051 __le32 queue_id4_max_bw; 2052 u8 queue_id4_tsa_assign; 2053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0) 2054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0) 2055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2057 u8 queue_id4_pri_lvl; 2058 u8 queue_id4_bw_weight; 2059 u8 queue_id5; 2060 __le32 queue_id5_min_bw; 2061 __le32 queue_id5_max_bw; 2062 u8 queue_id5_tsa_assign; 2063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0) 2064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0) 2065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2067 u8 queue_id5_pri_lvl; 2068 u8 queue_id5_bw_weight; 2069 u8 queue_id6; 2070 __le32 queue_id6_min_bw; 2071 __le32 queue_id6_max_bw; 2072 u8 queue_id6_tsa_assign; 2073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0) 2074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0) 2075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2077 u8 queue_id6_pri_lvl; 2078 u8 queue_id6_bw_weight; 2079 u8 queue_id7; 2080 __le32 queue_id7_min_bw; 2081 __le32 queue_id7_max_bw; 2082 u8 queue_id7_tsa_assign; 2083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0) 2084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0) 2085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2087 u8 queue_id7_pri_lvl; 2088 u8 queue_id7_bw_weight; 2089 u8 unused_1[5]; 2090 }; 2091 2092 /* Output (16 bytes) */ 2093 struct hwrm_queue_cos2bw_cfg_output { 2094 __le16 error_code; 2095 __le16 req_type; 2096 __le16 seq_id; 2097 __le16 resp_len; 2098 __le32 unused_0; 2099 u8 unused_1; 2100 u8 unused_2; 2101 u8 unused_3; 2102 u8 valid; 2103 }; 2104 2105 /* hwrm_vnic_alloc */ 2106 /* Input (24 bytes) */ 2107 struct hwrm_vnic_alloc_input { 2108 __le16 req_type; 2109 __le16 cmpl_ring; 2110 __le16 seq_id; 2111 __le16 target_id; 2112 __le64 resp_addr; 2113 __le32 flags; 2114 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 2115 __le32 unused_0; 2116 }; 2117 2118 /* Output (16 bytes) */ 2119 struct hwrm_vnic_alloc_output { 2120 __le16 error_code; 2121 __le16 req_type; 2122 __le16 seq_id; 2123 __le16 resp_len; 2124 __le32 vnic_id; 2125 u8 unused_0; 2126 u8 unused_1; 2127 u8 unused_2; 2128 u8 valid; 2129 }; 2130 2131 /* hwrm_vnic_free */ 2132 /* Input (24 bytes) */ 2133 struct hwrm_vnic_free_input { 2134 __le16 req_type; 2135 __le16 cmpl_ring; 2136 __le16 seq_id; 2137 __le16 target_id; 2138 __le64 resp_addr; 2139 __le32 vnic_id; 2140 __le32 unused_0; 2141 }; 2142 2143 /* Output (16 bytes) */ 2144 struct hwrm_vnic_free_output { 2145 __le16 error_code; 2146 __le16 req_type; 2147 __le16 seq_id; 2148 __le16 resp_len; 2149 __le32 unused_0; 2150 u8 unused_1; 2151 u8 unused_2; 2152 u8 unused_3; 2153 u8 valid; 2154 }; 2155 2156 /* hwrm_vnic_cfg */ 2157 /* Input (40 bytes) */ 2158 struct hwrm_vnic_cfg_input { 2159 __le16 req_type; 2160 __le16 cmpl_ring; 2161 __le16 seq_id; 2162 __le16 target_id; 2163 __le64 resp_addr; 2164 __le32 flags; 2165 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 2166 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 2167 __le32 enables; 2168 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 2169 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 2170 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 2171 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 2172 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 2173 __le16 vnic_id; 2174 __le16 dflt_ring_grp; 2175 __le16 rss_rule; 2176 __le16 cos_rule; 2177 __le16 lb_rule; 2178 __le16 mru; 2179 __le32 unused_0; 2180 }; 2181 2182 /* Output (16 bytes) */ 2183 struct hwrm_vnic_cfg_output { 2184 __le16 error_code; 2185 __le16 req_type; 2186 __le16 seq_id; 2187 __le16 resp_len; 2188 __le32 unused_0; 2189 u8 unused_1; 2190 u8 unused_2; 2191 u8 unused_3; 2192 u8 valid; 2193 }; 2194 2195 /* hwrm_vnic_tpa_cfg */ 2196 /* Input (40 bytes) */ 2197 struct hwrm_vnic_tpa_cfg_input { 2198 __le16 req_type; 2199 __le16 cmpl_ring; 2200 __le16 seq_id; 2201 __le16 target_id; 2202 __le64 resp_addr; 2203 __le32 flags; 2204 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 2205 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 2206 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 2207 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 2208 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 2209 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 2210 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 2211 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 2212 __le32 enables; 2213 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 2214 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 2215 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 2216 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 2217 __le16 vnic_id; 2218 __le16 max_agg_segs; 2219 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0) 2220 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0) 2221 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0) 2222 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0) 2223 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0) 2224 __le16 max_aggs; 2225 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0) 2226 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0) 2227 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0) 2228 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0) 2229 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0) 2230 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0) 2231 u8 unused_0; 2232 u8 unused_1; 2233 __le32 max_agg_timer; 2234 __le32 min_agg_len; 2235 }; 2236 2237 /* Output (16 bytes) */ 2238 struct hwrm_vnic_tpa_cfg_output { 2239 __le16 error_code; 2240 __le16 req_type; 2241 __le16 seq_id; 2242 __le16 resp_len; 2243 __le32 unused_0; 2244 u8 unused_1; 2245 u8 unused_2; 2246 u8 unused_3; 2247 u8 valid; 2248 }; 2249 2250 /* hwrm_vnic_rss_cfg */ 2251 /* Input (48 bytes) */ 2252 struct hwrm_vnic_rss_cfg_input { 2253 __le16 req_type; 2254 __le16 cmpl_ring; 2255 __le16 seq_id; 2256 __le16 target_id; 2257 __le64 resp_addr; 2258 __le32 hash_type; 2259 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 2260 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 2261 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 2262 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 2263 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 2264 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 2265 __le32 unused_0; 2266 __le64 ring_grp_tbl_addr; 2267 __le64 hash_key_tbl_addr; 2268 __le16 rss_ctx_idx; 2269 __le16 unused_1[3]; 2270 }; 2271 2272 /* Output (16 bytes) */ 2273 struct hwrm_vnic_rss_cfg_output { 2274 __le16 error_code; 2275 __le16 req_type; 2276 __le16 seq_id; 2277 __le16 resp_len; 2278 __le32 unused_0; 2279 u8 unused_1; 2280 u8 unused_2; 2281 u8 unused_3; 2282 u8 valid; 2283 }; 2284 2285 /* hwrm_vnic_plcmodes_cfg */ 2286 /* Input (40 bytes) */ 2287 struct hwrm_vnic_plcmodes_cfg_input { 2288 __le16 req_type; 2289 __le16 cmpl_ring; 2290 __le16 seq_id; 2291 __le16 target_id; 2292 __le64 resp_addr; 2293 __le32 flags; 2294 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 2295 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 2296 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 2297 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 2298 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 2299 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 2300 __le32 enables; 2301 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 2302 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 2303 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 2304 __le32 vnic_id; 2305 __le16 jumbo_thresh; 2306 __le16 hds_offset; 2307 __le16 hds_threshold; 2308 __le16 unused_0[3]; 2309 }; 2310 2311 /* Output (16 bytes) */ 2312 struct hwrm_vnic_plcmodes_cfg_output { 2313 __le16 error_code; 2314 __le16 req_type; 2315 __le16 seq_id; 2316 __le16 resp_len; 2317 __le32 unused_0; 2318 u8 unused_1; 2319 u8 unused_2; 2320 u8 unused_3; 2321 u8 valid; 2322 }; 2323 2324 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 2325 /* Input (16 bytes) */ 2326 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 2327 __le16 req_type; 2328 __le16 cmpl_ring; 2329 __le16 seq_id; 2330 __le16 target_id; 2331 __le64 resp_addr; 2332 }; 2333 2334 /* Output (16 bytes) */ 2335 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 2336 __le16 error_code; 2337 __le16 req_type; 2338 __le16 seq_id; 2339 __le16 resp_len; 2340 __le16 rss_cos_lb_ctx_id; 2341 u8 unused_0; 2342 u8 unused_1; 2343 u8 unused_2; 2344 u8 unused_3; 2345 u8 unused_4; 2346 u8 valid; 2347 }; 2348 2349 /* hwrm_vnic_rss_cos_lb_ctx_free */ 2350 /* Input (24 bytes) */ 2351 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 2352 __le16 req_type; 2353 __le16 cmpl_ring; 2354 __le16 seq_id; 2355 __le16 target_id; 2356 __le64 resp_addr; 2357 __le16 rss_cos_lb_ctx_id; 2358 __le16 unused_0[3]; 2359 }; 2360 2361 /* Output (16 bytes) */ 2362 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 2363 __le16 error_code; 2364 __le16 req_type; 2365 __le16 seq_id; 2366 __le16 resp_len; 2367 __le32 unused_0; 2368 u8 unused_1; 2369 u8 unused_2; 2370 u8 unused_3; 2371 u8 valid; 2372 }; 2373 2374 /* hwrm_ring_alloc */ 2375 /* Input (80 bytes) */ 2376 struct hwrm_ring_alloc_input { 2377 __le16 req_type; 2378 __le16 cmpl_ring; 2379 __le16 seq_id; 2380 __le16 target_id; 2381 __le64 resp_addr; 2382 __le32 enables; 2383 #define RING_ALLOC_REQ_ENABLES_ARB_GRP_ID_VALID 0x1UL 2384 #define RING_ALLOC_REQ_ENABLES_INPUT_NUM_VALID 0x2UL 2385 #define RING_ALLOC_REQ_ENABLES_WEIGHT_VALID 0x4UL 2386 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 2387 #define RING_ALLOC_REQ_ENABLES_MIN_BW_VALID 0x10UL 2388 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 2389 u8 ring_type; 2390 #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0) 2391 #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0) 2392 #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0) 2393 #define RING_ALLOC_REQ_RING_TYPE_STATUS (0x3UL << 0) 2394 #define RING_ALLOC_REQ_RING_TYPE_CMD (0x4UL << 0) 2395 u8 unused_0; 2396 __le16 unused_1; 2397 __le64 page_tbl_addr; 2398 __le32 fbo; 2399 u8 page_size; 2400 u8 page_tbl_depth; 2401 u8 unused_2; 2402 u8 unused_3; 2403 __le32 length; 2404 __le16 logical_id; 2405 __le16 cmpl_ring_id; 2406 __le16 queue_id; 2407 u8 unused_4; 2408 u8 unused_5; 2409 __le32 arb_grp_id; 2410 __le16 input_number; 2411 u8 unused_6; 2412 u8 unused_7; 2413 __le32 weight; 2414 __le32 stat_ctx_id; 2415 __le32 min_bw; 2416 __le32 max_bw; 2417 u8 int_mode; 2418 #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0) 2419 #define RING_ALLOC_REQ_INT_MODE_MSI (0x1UL << 0) 2420 #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0) 2421 #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0) 2422 u8 unused_8[3]; 2423 }; 2424 2425 /* Output (16 bytes) */ 2426 struct hwrm_ring_alloc_output { 2427 __le16 error_code; 2428 __le16 req_type; 2429 __le16 seq_id; 2430 __le16 resp_len; 2431 __le16 ring_id; 2432 __le16 logical_ring_id; 2433 u8 unused_0; 2434 u8 unused_1; 2435 u8 unused_2; 2436 u8 valid; 2437 }; 2438 2439 /* hwrm_ring_free */ 2440 /* Input (24 bytes) */ 2441 struct hwrm_ring_free_input { 2442 __le16 req_type; 2443 __le16 cmpl_ring; 2444 __le16 seq_id; 2445 __le16 target_id; 2446 __le64 resp_addr; 2447 u8 ring_type; 2448 #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0) 2449 #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0) 2450 #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0) 2451 #define RING_FREE_REQ_RING_TYPE_STATUS (0x3UL << 0) 2452 #define RING_FREE_REQ_RING_TYPE_CMD (0x4UL << 0) 2453 u8 unused_0; 2454 __le16 ring_id; 2455 __le32 unused_1; 2456 }; 2457 2458 /* Output (16 bytes) */ 2459 struct hwrm_ring_free_output { 2460 __le16 error_code; 2461 __le16 req_type; 2462 __le16 seq_id; 2463 __le16 resp_len; 2464 __le32 unused_0; 2465 u8 unused_1; 2466 u8 unused_2; 2467 u8 unused_3; 2468 u8 valid; 2469 }; 2470 2471 /* hwrm_ring_cmpl_ring_qaggint_params */ 2472 /* Input (24 bytes) */ 2473 struct hwrm_ring_cmpl_ring_qaggint_params_input { 2474 __le16 req_type; 2475 __le16 cmpl_ring; 2476 __le16 seq_id; 2477 __le16 target_id; 2478 __le64 resp_addr; 2479 __le16 ring_id; 2480 __le16 unused_0[3]; 2481 }; 2482 2483 /* Output (32 bytes) */ 2484 struct hwrm_ring_cmpl_ring_qaggint_params_output { 2485 __le16 error_code; 2486 __le16 req_type; 2487 __le16 seq_id; 2488 __le16 resp_len; 2489 __le16 flags; 2490 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 2491 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 2492 __le16 num_cmpl_dma_aggr; 2493 __le16 num_cmpl_dma_aggr_during_int; 2494 __le16 cmpl_aggr_dma_tmr; 2495 __le16 cmpl_aggr_dma_tmr_during_int; 2496 __le16 int_lat_tmr_min; 2497 __le16 int_lat_tmr_max; 2498 __le16 num_cmpl_aggr_int; 2499 __le32 unused_0; 2500 u8 unused_1; 2501 u8 unused_2; 2502 u8 unused_3; 2503 u8 valid; 2504 }; 2505 2506 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 2507 /* Input (40 bytes) */ 2508 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 2509 __le16 req_type; 2510 __le16 cmpl_ring; 2511 __le16 seq_id; 2512 __le16 target_id; 2513 __le64 resp_addr; 2514 __le16 ring_id; 2515 __le16 flags; 2516 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 2517 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 2518 __le16 num_cmpl_dma_aggr; 2519 __le16 num_cmpl_dma_aggr_during_int; 2520 __le16 cmpl_aggr_dma_tmr; 2521 __le16 cmpl_aggr_dma_tmr_during_int; 2522 __le16 int_lat_tmr_min; 2523 __le16 int_lat_tmr_max; 2524 __le16 num_cmpl_aggr_int; 2525 __le16 unused_0[3]; 2526 }; 2527 2528 /* Output (16 bytes) */ 2529 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 2530 __le16 error_code; 2531 __le16 req_type; 2532 __le16 seq_id; 2533 __le16 resp_len; 2534 __le32 unused_0; 2535 u8 unused_1; 2536 u8 unused_2; 2537 u8 unused_3; 2538 u8 valid; 2539 }; 2540 2541 /* hwrm_ring_reset */ 2542 /* Input (24 bytes) */ 2543 struct hwrm_ring_reset_input { 2544 __le16 req_type; 2545 __le16 cmpl_ring; 2546 __le16 seq_id; 2547 __le16 target_id; 2548 __le64 resp_addr; 2549 u8 ring_type; 2550 #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0) 2551 #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0) 2552 #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0) 2553 #define RING_RESET_REQ_RING_TYPE_STATUS (0x3UL << 0) 2554 #define RING_RESET_REQ_RING_TYPE_CMD (0x4UL << 0) 2555 u8 unused_0; 2556 __le16 ring_id; 2557 __le32 unused_1; 2558 }; 2559 2560 /* Output (16 bytes) */ 2561 struct hwrm_ring_reset_output { 2562 __le16 error_code; 2563 __le16 req_type; 2564 __le16 seq_id; 2565 __le16 resp_len; 2566 __le32 unused_0; 2567 u8 unused_1; 2568 u8 unused_2; 2569 u8 unused_3; 2570 u8 valid; 2571 }; 2572 2573 /* hwrm_ring_grp_alloc */ 2574 /* Input (24 bytes) */ 2575 struct hwrm_ring_grp_alloc_input { 2576 __le16 req_type; 2577 __le16 cmpl_ring; 2578 __le16 seq_id; 2579 __le16 target_id; 2580 __le64 resp_addr; 2581 __le16 cr; 2582 __le16 rr; 2583 __le16 ar; 2584 __le16 sc; 2585 }; 2586 2587 /* Output (16 bytes) */ 2588 struct hwrm_ring_grp_alloc_output { 2589 __le16 error_code; 2590 __le16 req_type; 2591 __le16 seq_id; 2592 __le16 resp_len; 2593 __le32 ring_group_id; 2594 u8 unused_0; 2595 u8 unused_1; 2596 u8 unused_2; 2597 u8 valid; 2598 }; 2599 2600 /* hwrm_ring_grp_free */ 2601 /* Input (24 bytes) */ 2602 struct hwrm_ring_grp_free_input { 2603 __le16 req_type; 2604 __le16 cmpl_ring; 2605 __le16 seq_id; 2606 __le16 target_id; 2607 __le64 resp_addr; 2608 __le32 ring_group_id; 2609 __le32 unused_0; 2610 }; 2611 2612 /* Output (16 bytes) */ 2613 struct hwrm_ring_grp_free_output { 2614 __le16 error_code; 2615 __le16 req_type; 2616 __le16 seq_id; 2617 __le16 resp_len; 2618 __le32 unused_0; 2619 u8 unused_1; 2620 u8 unused_2; 2621 u8 unused_3; 2622 u8 valid; 2623 }; 2624 2625 /* hwrm_arb_grp_alloc */ 2626 /* Input (24 bytes) */ 2627 struct hwrm_arb_grp_alloc_input { 2628 __le16 req_type; 2629 __le16 cmpl_ring; 2630 __le16 seq_id; 2631 __le16 target_id; 2632 __le64 resp_addr; 2633 __le16 input_number; 2634 __le16 unused_0[3]; 2635 }; 2636 2637 /* Output (16 bytes) */ 2638 struct hwrm_arb_grp_alloc_output { 2639 __le16 error_code; 2640 __le16 req_type; 2641 __le16 seq_id; 2642 __le16 resp_len; 2643 __le16 arb_grp_id; 2644 u8 unused_0; 2645 u8 unused_1; 2646 u8 unused_2; 2647 u8 unused_3; 2648 u8 unused_4; 2649 u8 valid; 2650 }; 2651 2652 /* hwrm_arb_grp_cfg */ 2653 /* Input (32 bytes) */ 2654 struct hwrm_arb_grp_cfg_input { 2655 __le16 req_type; 2656 __le16 cmpl_ring; 2657 __le16 seq_id; 2658 __le16 target_id; 2659 __le64 resp_addr; 2660 __le32 arb_grp_id; 2661 __le16 input_number; 2662 __le16 tx_ring; 2663 __le32 weight; 2664 __le32 unused_0; 2665 }; 2666 2667 /* Output (16 bytes) */ 2668 struct hwrm_arb_grp_cfg_output { 2669 __le16 error_code; 2670 __le16 req_type; 2671 __le16 seq_id; 2672 __le16 resp_len; 2673 __le32 unused_0; 2674 u8 unused_1; 2675 u8 unused_2; 2676 u8 unused_3; 2677 u8 valid; 2678 }; 2679 2680 /* hwrm_cfa_l2_filter_alloc */ 2681 /* Input (96 bytes) */ 2682 struct hwrm_cfa_l2_filter_alloc_input { 2683 __le16 req_type; 2684 __le16 cmpl_ring; 2685 __le16 seq_id; 2686 __le16 target_id; 2687 __le64 resp_addr; 2688 __le32 flags; 2689 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 2690 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 2691 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 2692 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 2693 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 2694 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 2695 __le32 enables; 2696 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 2697 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 2698 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 2699 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 2700 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 2701 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 2702 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 2703 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 2704 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 2705 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 2706 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 2707 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 2708 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 2709 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 2710 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 2711 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x8000UL 2712 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 2713 u8 l2_addr[6]; 2714 u8 unused_0; 2715 u8 unused_1; 2716 u8 l2_addr_mask[6]; 2717 __le16 l2_ovlan; 2718 __le16 l2_ovlan_mask; 2719 __le16 l2_ivlan; 2720 __le16 l2_ivlan_mask; 2721 u8 unused_2; 2722 u8 unused_3; 2723 u8 t_l2_addr[6]; 2724 u8 unused_4; 2725 u8 unused_5; 2726 u8 t_l2_addr_mask[6]; 2727 __le16 t_l2_ovlan; 2728 __le16 t_l2_ovlan_mask; 2729 __le16 t_l2_ivlan; 2730 __le16 t_l2_ivlan_mask; 2731 u8 src_type; 2732 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0) 2733 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0) 2734 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0) 2735 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0) 2736 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0) 2737 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0) 2738 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0) 2739 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0) 2740 u8 unused_6; 2741 __le32 src_id; 2742 u8 tunnel_type; 2743 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 2744 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 2745 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 2746 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 2747 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 2748 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 2749 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 2750 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 2751 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 2752 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 2753 u8 unused_7; 2754 __le16 dst_vnic_id; 2755 __le16 mirror_vnic_id; 2756 u8 pri_hint; 2757 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) 2758 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0) 2759 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0) 2760 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0) 2761 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0) 2762 u8 unused_8; 2763 __le32 unused_9; 2764 __le64 l2_filter_id_hint; 2765 }; 2766 2767 /* Output (24 bytes) */ 2768 struct hwrm_cfa_l2_filter_alloc_output { 2769 __le16 error_code; 2770 __le16 req_type; 2771 __le16 seq_id; 2772 __le16 resp_len; 2773 __le64 l2_filter_id; 2774 __le32 flow_id; 2775 u8 unused_0; 2776 u8 unused_1; 2777 u8 unused_2; 2778 u8 valid; 2779 }; 2780 2781 /* hwrm_cfa_l2_filter_free */ 2782 /* Input (24 bytes) */ 2783 struct hwrm_cfa_l2_filter_free_input { 2784 __le16 req_type; 2785 __le16 cmpl_ring; 2786 __le16 seq_id; 2787 __le16 target_id; 2788 __le64 resp_addr; 2789 __le64 l2_filter_id; 2790 }; 2791 2792 /* Output (16 bytes) */ 2793 struct hwrm_cfa_l2_filter_free_output { 2794 __le16 error_code; 2795 __le16 req_type; 2796 __le16 seq_id; 2797 __le16 resp_len; 2798 __le32 unused_0; 2799 u8 unused_1; 2800 u8 unused_2; 2801 u8 unused_3; 2802 u8 valid; 2803 }; 2804 2805 /* hwrm_cfa_l2_filter_cfg */ 2806 /* Input (40 bytes) */ 2807 struct hwrm_cfa_l2_filter_cfg_input { 2808 __le16 req_type; 2809 __le16 cmpl_ring; 2810 __le16 seq_id; 2811 __le16 target_id; 2812 __le64 resp_addr; 2813 __le32 flags; 2814 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 2815 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2816 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2817 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 2818 __le32 enables; 2819 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_VNIC_ID_VALID 0x1UL 2820 __le64 l2_filter_id; 2821 __le32 dst_vnic_id; 2822 __le32 unused_0; 2823 }; 2824 2825 /* Output (16 bytes) */ 2826 struct hwrm_cfa_l2_filter_cfg_output { 2827 __le16 error_code; 2828 __le16 req_type; 2829 __le16 seq_id; 2830 __le16 resp_len; 2831 __le32 unused_0; 2832 u8 unused_1; 2833 u8 unused_2; 2834 u8 unused_3; 2835 u8 valid; 2836 }; 2837 2838 /* hwrm_cfa_l2_set_rx_mask */ 2839 /* Input (40 bytes) */ 2840 struct hwrm_cfa_l2_set_rx_mask_input { 2841 __le16 req_type; 2842 __le16 cmpl_ring; 2843 __le16 seq_id; 2844 __le16 target_id; 2845 __le64 resp_addr; 2846 __le32 dflt_vnic_id; 2847 __le32 mask; 2848 #define CFA_L2_SET_RX_MASK_REQ_MASK_UNICAST 0x1UL 2849 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 2850 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 2851 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 2852 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 2853 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 2854 __le64 mc_tbl_addr; 2855 __le32 num_mc_entries; 2856 __le32 unused_0; 2857 }; 2858 2859 /* Output (16 bytes) */ 2860 struct hwrm_cfa_l2_set_rx_mask_output { 2861 __le16 error_code; 2862 __le16 req_type; 2863 __le16 seq_id; 2864 __le16 resp_len; 2865 __le32 unused_0; 2866 u8 unused_1; 2867 u8 unused_2; 2868 u8 unused_3; 2869 u8 valid; 2870 }; 2871 2872 /* hwrm_cfa_l2_set_bcastmcast_mirroring */ 2873 /* Input (32 bytes) */ 2874 struct hwrm_cfa_l2_set_bcastmcast_mirroring_input { 2875 __le16 req_type; 2876 __le16 cmpl_ring; 2877 __le16 seq_id; 2878 __le16 target_id; 2879 __le64 resp_addr; 2880 __le32 dflt_vnic_id; 2881 __le32 mirroring_flags; 2882 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_BCAST_MIRRORING 0x1UL 2883 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_MCAST_MIRRORING 0x2UL 2884 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_BCAST_SRC_KNOCKOUT 0x4UL 2885 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_MCAST_SRC_KNOCKOUT 0x8UL 2886 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MIRRORING_FLAGS_VLAN_ID_VALID 0x10UL 2887 __le16 vlan_id; 2888 u8 bcast_domain; 2889 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_PFONLY (0x0UL << 0) 2890 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_ALLPFS (0x1UL << 0) 2891 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_BCAST_DOMAIN_ALLPFSVFS (0x2UL << 0) 2892 u8 mcast_domain; 2893 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_PFONLY (0x0UL << 0) 2894 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_ALLPFS (0x1UL << 0) 2895 #define CFA_L2_SET_BCASTMCAST_MIRRORING_REQ_MCAST_DOMAIN_ALLPFSVFS (0x2UL << 0) 2896 __le32 unused_0; 2897 }; 2898 2899 /* Output (16 bytes) */ 2900 struct hwrm_cfa_l2_set_bcastmcast_mirroring_output { 2901 __le16 error_code; 2902 __le16 req_type; 2903 __le16 seq_id; 2904 __le16 resp_len; 2905 __le32 unused_0; 2906 u8 unused_1; 2907 u8 unused_2; 2908 u8 unused_3; 2909 u8 valid; 2910 }; 2911 2912 /* hwrm_cfa_tunnel_filter_alloc */ 2913 /* Input (88 bytes) */ 2914 struct hwrm_cfa_tunnel_filter_alloc_input { 2915 __le16 req_type; 2916 __le16 cmpl_ring; 2917 __le16 seq_id; 2918 __le16 target_id; 2919 __le64 resp_addr; 2920 __le32 flags; 2921 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 2922 __le32 enables; 2923 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 2924 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 2925 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 2926 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 2927 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 2928 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 2929 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 2930 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 2931 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 2932 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 2933 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 2934 __le64 l2_filter_id; 2935 u8 l2_addr[6]; 2936 __le16 l2_ivlan; 2937 __le32 l3_addr[4]; 2938 __le32 t_l3_addr[4]; 2939 u8 l3_addr_type; 2940 u8 t_l3_addr_type; 2941 u8 tunnel_type; 2942 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 2943 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 2944 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 2945 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 2946 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 2947 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 2948 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 2949 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 2950 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 2951 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 2952 u8 unused_0; 2953 __le32 vni; 2954 __le32 dst_vnic_id; 2955 __le32 mirror_vnic_id; 2956 }; 2957 2958 /* Output (24 bytes) */ 2959 struct hwrm_cfa_tunnel_filter_alloc_output { 2960 __le16 error_code; 2961 __le16 req_type; 2962 __le16 seq_id; 2963 __le16 resp_len; 2964 __le64 tunnel_filter_id; 2965 __le32 flow_id; 2966 u8 unused_0; 2967 u8 unused_1; 2968 u8 unused_2; 2969 u8 valid; 2970 }; 2971 2972 /* hwrm_cfa_tunnel_filter_free */ 2973 /* Input (24 bytes) */ 2974 struct hwrm_cfa_tunnel_filter_free_input { 2975 __le16 req_type; 2976 __le16 cmpl_ring; 2977 __le16 seq_id; 2978 __le16 target_id; 2979 __le64 resp_addr; 2980 __le64 tunnel_filter_id; 2981 }; 2982 2983 /* Output (16 bytes) */ 2984 struct hwrm_cfa_tunnel_filter_free_output { 2985 __le16 error_code; 2986 __le16 req_type; 2987 __le16 seq_id; 2988 __le16 resp_len; 2989 __le32 unused_0; 2990 u8 unused_1; 2991 u8 unused_2; 2992 u8 unused_3; 2993 u8 valid; 2994 }; 2995 2996 /* hwrm_cfa_encap_record_alloc */ 2997 /* Input (32 bytes) */ 2998 struct hwrm_cfa_encap_record_alloc_input { 2999 __le16 req_type; 3000 __le16 cmpl_ring; 3001 __le16 seq_id; 3002 __le16 target_id; 3003 __le64 resp_addr; 3004 __le32 flags; 3005 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3006 u8 encap_type; 3007 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0) 3008 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0) 3009 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0) 3010 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0) 3011 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0) 3012 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0) 3013 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0) 3014 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0) 3015 u8 unused_0; 3016 __le16 unused_1; 3017 __le32 encap_data[16]; 3018 }; 3019 3020 /* Output (24 bytes) */ 3021 struct hwrm_cfa_encap_record_alloc_output { 3022 __le16 error_code; 3023 __le16 req_type; 3024 __le16 seq_id; 3025 __le16 resp_len; 3026 __le64 encap_record_id; 3027 __le32 unused_0; 3028 u8 unused_1; 3029 u8 unused_2; 3030 u8 unused_3; 3031 u8 valid; 3032 }; 3033 3034 /* hwrm_cfa_encap_record_free */ 3035 /* Input (24 bytes) */ 3036 struct hwrm_cfa_encap_record_free_input { 3037 __le16 req_type; 3038 __le16 cmpl_ring; 3039 __le16 seq_id; 3040 __le16 target_id; 3041 __le64 resp_addr; 3042 __le64 encap_record_id; 3043 }; 3044 3045 /* Output (16 bytes) */ 3046 struct hwrm_cfa_encap_record_free_output { 3047 __le16 error_code; 3048 __le16 req_type; 3049 __le16 seq_id; 3050 __le16 resp_len; 3051 __le32 unused_0; 3052 u8 unused_1; 3053 u8 unused_2; 3054 u8 unused_3; 3055 u8 valid; 3056 }; 3057 3058 /* hwrm_cfa_ntuple_filter_alloc */ 3059 /* Input (128 bytes) */ 3060 struct hwrm_cfa_ntuple_filter_alloc_input { 3061 __le16 req_type; 3062 __le16 cmpl_ring; 3063 __le16 seq_id; 3064 __le16 target_id; 3065 __le64 resp_addr; 3066 __le32 flags; 3067 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3068 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 3069 __le32 enables; 3070 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3071 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 3072 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 3073 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 3074 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 3075 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 3076 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 3077 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 3078 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 3079 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 3080 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 3081 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 3082 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 3083 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 3084 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 3085 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 3086 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x10000UL 3087 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 3088 __le64 l2_filter_id; 3089 u8 src_macaddr[6]; 3090 __be16 ethertype; 3091 u8 ipaddr_type; 3092 u8 ip_protocol; 3093 __le16 dst_vnic_id; 3094 __le16 mirror_vnic_id; 3095 u8 tunnel_type; 3096 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3097 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3098 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3099 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3100 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3101 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3102 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3103 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3104 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3105 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3106 u8 pri_hint; 3107 __be32 src_ipaddr[4]; 3108 __be32 src_ipaddr_mask[4]; 3109 __be32 dst_ipaddr[4]; 3110 __be32 dst_ipaddr_mask[4]; 3111 __be16 src_port; 3112 __be16 src_port_mask; 3113 __be16 dst_port; 3114 __be16 dst_port_mask; 3115 __le64 ntuple_filter_id_hint; 3116 }; 3117 3118 /* Output (24 bytes) */ 3119 struct hwrm_cfa_ntuple_filter_alloc_output { 3120 __le16 error_code; 3121 __le16 req_type; 3122 __le16 seq_id; 3123 __le16 resp_len; 3124 __le64 ntuple_filter_id; 3125 __le32 flow_id; 3126 u8 unused_0; 3127 u8 unused_1; 3128 u8 unused_2; 3129 u8 valid; 3130 }; 3131 3132 /* hwrm_cfa_ntuple_filter_free */ 3133 /* Input (24 bytes) */ 3134 struct hwrm_cfa_ntuple_filter_free_input { 3135 __le16 req_type; 3136 __le16 cmpl_ring; 3137 __le16 seq_id; 3138 __le16 target_id; 3139 __le64 resp_addr; 3140 __le64 ntuple_filter_id; 3141 }; 3142 3143 /* Output (16 bytes) */ 3144 struct hwrm_cfa_ntuple_filter_free_output { 3145 __le16 error_code; 3146 __le16 req_type; 3147 __le16 seq_id; 3148 __le16 resp_len; 3149 __le32 unused_0; 3150 u8 unused_1; 3151 u8 unused_2; 3152 u8 unused_3; 3153 u8 valid; 3154 }; 3155 3156 /* hwrm_cfa_ntuple_filter_cfg */ 3157 /* Input (40 bytes) */ 3158 struct hwrm_cfa_ntuple_filter_cfg_input { 3159 __le16 req_type; 3160 __le16 cmpl_ring; 3161 __le16 seq_id; 3162 __le16 target_id; 3163 __le64 resp_addr; 3164 __le32 enables; 3165 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_VNIC_ID_VALID 0x1UL 3166 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID_VALID 0x2UL 3167 __le32 unused_0; 3168 __le64 ntuple_filter_id; 3169 __le32 new_dst_vnic_id; 3170 __le32 new_mirror_vnic_id; 3171 }; 3172 3173 /* Output (16 bytes) */ 3174 struct hwrm_cfa_ntuple_filter_cfg_output { 3175 __le16 error_code; 3176 __le16 req_type; 3177 __le16 seq_id; 3178 __le16 resp_len; 3179 __le32 unused_0; 3180 u8 unused_1; 3181 u8 unused_2; 3182 u8 unused_3; 3183 u8 valid; 3184 }; 3185 3186 /* hwrm_tunnel_dst_port_query */ 3187 /* Input (24 bytes) */ 3188 struct hwrm_tunnel_dst_port_query_input { 3189 __le16 req_type; 3190 __le16 cmpl_ring; 3191 __le16 seq_id; 3192 __le16 target_id; 3193 __le64 resp_addr; 3194 u8 tunnel_type; 3195 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3196 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3197 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3198 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3199 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3200 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3201 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3202 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3203 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3204 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3205 u8 unused_0[7]; 3206 }; 3207 3208 /* Output (16 bytes) */ 3209 struct hwrm_tunnel_dst_port_query_output { 3210 __le16 error_code; 3211 __le16 req_type; 3212 __le16 seq_id; 3213 __le16 resp_len; 3214 __le16 tunnel_dst_port_id; 3215 __be16 tunnel_dst_port_val; 3216 u8 unused_0; 3217 u8 unused_1; 3218 u8 unused_2; 3219 u8 valid; 3220 }; 3221 3222 /* hwrm_tunnel_dst_port_alloc */ 3223 /* Input (24 bytes) */ 3224 struct hwrm_tunnel_dst_port_alloc_input { 3225 __le16 req_type; 3226 __le16 cmpl_ring; 3227 __le16 seq_id; 3228 __le16 target_id; 3229 __le64 resp_addr; 3230 u8 tunnel_type; 3231 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3232 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3233 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3234 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3235 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3236 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3237 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3238 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3239 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3240 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3241 u8 unused_0; 3242 __be16 tunnel_dst_port_val; 3243 __le32 unused_1; 3244 }; 3245 3246 /* Output (16 bytes) */ 3247 struct hwrm_tunnel_dst_port_alloc_output { 3248 __le16 error_code; 3249 __le16 req_type; 3250 __le16 seq_id; 3251 __le16 resp_len; 3252 __le16 tunnel_dst_port_id; 3253 u8 unused_0; 3254 u8 unused_1; 3255 u8 unused_2; 3256 u8 unused_3; 3257 u8 unused_4; 3258 u8 valid; 3259 }; 3260 3261 /* hwrm_tunnel_dst_port_free */ 3262 /* Input (24 bytes) */ 3263 struct hwrm_tunnel_dst_port_free_input { 3264 __le16 req_type; 3265 __le16 cmpl_ring; 3266 __le16 seq_id; 3267 __le16 target_id; 3268 __le64 resp_addr; 3269 u8 tunnel_type; 3270 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3271 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3272 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3273 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3274 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3275 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3276 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3277 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3278 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3279 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3280 u8 unused_0; 3281 __le16 tunnel_dst_port_id; 3282 __le32 unused_1; 3283 }; 3284 3285 /* Output (16 bytes) */ 3286 struct hwrm_tunnel_dst_port_free_output { 3287 __le16 error_code; 3288 __le16 req_type; 3289 __le16 seq_id; 3290 __le16 resp_len; 3291 __le32 unused_0; 3292 u8 unused_1; 3293 u8 unused_2; 3294 u8 unused_3; 3295 u8 valid; 3296 }; 3297 3298 /* hwrm_stat_ctx_alloc */ 3299 /* Input (32 bytes) */ 3300 struct hwrm_stat_ctx_alloc_input { 3301 __le16 req_type; 3302 __le16 cmpl_ring; 3303 __le16 seq_id; 3304 __le16 target_id; 3305 __le64 resp_addr; 3306 __le64 stats_dma_addr; 3307 __le32 update_period_ms; 3308 __le32 unused_0; 3309 }; 3310 3311 /* Output (16 bytes) */ 3312 struct hwrm_stat_ctx_alloc_output { 3313 __le16 error_code; 3314 __le16 req_type; 3315 __le16 seq_id; 3316 __le16 resp_len; 3317 __le32 stat_ctx_id; 3318 u8 unused_0; 3319 u8 unused_1; 3320 u8 unused_2; 3321 u8 valid; 3322 }; 3323 3324 /* hwrm_stat_ctx_free */ 3325 /* Input (24 bytes) */ 3326 struct hwrm_stat_ctx_free_input { 3327 __le16 req_type; 3328 __le16 cmpl_ring; 3329 __le16 seq_id; 3330 __le16 target_id; 3331 __le64 resp_addr; 3332 __le32 stat_ctx_id; 3333 __le32 unused_0; 3334 }; 3335 3336 /* Output (16 bytes) */ 3337 struct hwrm_stat_ctx_free_output { 3338 __le16 error_code; 3339 __le16 req_type; 3340 __le16 seq_id; 3341 __le16 resp_len; 3342 __le32 stat_ctx_id; 3343 u8 unused_0; 3344 u8 unused_1; 3345 u8 unused_2; 3346 u8 valid; 3347 }; 3348 3349 /* hwrm_stat_ctx_query */ 3350 /* Input (24 bytes) */ 3351 struct hwrm_stat_ctx_query_input { 3352 __le16 req_type; 3353 __le16 cmpl_ring; 3354 __le16 seq_id; 3355 __le16 target_id; 3356 __le64 resp_addr; 3357 __le32 stat_ctx_id; 3358 __le32 unused_0; 3359 }; 3360 3361 /* Output (176 bytes) */ 3362 struct hwrm_stat_ctx_query_output { 3363 __le16 error_code; 3364 __le16 req_type; 3365 __le16 seq_id; 3366 __le16 resp_len; 3367 __le64 tx_ucast_pkts; 3368 __le64 tx_mcast_pkts; 3369 __le64 tx_bcast_pkts; 3370 __le64 tx_err_pkts; 3371 __le64 tx_drop_pkts; 3372 __le64 tx_ucast_bytes; 3373 __le64 tx_mcast_bytes; 3374 __le64 tx_bcast_bytes; 3375 __le64 rx_ucast_pkts; 3376 __le64 rx_mcast_pkts; 3377 __le64 rx_bcast_pkts; 3378 __le64 rx_err_pkts; 3379 __le64 rx_drop_pkts; 3380 __le64 rx_ucast_bytes; 3381 __le64 rx_mcast_bytes; 3382 __le64 rx_bcast_bytes; 3383 __le64 rx_agg_pkts; 3384 __le64 rx_agg_bytes; 3385 __le64 rx_agg_events; 3386 __le64 rx_agg_aborts; 3387 __le32 unused_0; 3388 u8 unused_1; 3389 u8 unused_2; 3390 u8 unused_3; 3391 u8 valid; 3392 }; 3393 3394 /* hwrm_stat_ctx_clr_stats */ 3395 /* Input (24 bytes) */ 3396 struct hwrm_stat_ctx_clr_stats_input { 3397 __le16 req_type; 3398 __le16 cmpl_ring; 3399 __le16 seq_id; 3400 __le16 target_id; 3401 __le64 resp_addr; 3402 __le32 stat_ctx_id; 3403 __le32 unused_0; 3404 }; 3405 3406 /* Output (16 bytes) */ 3407 struct hwrm_stat_ctx_clr_stats_output { 3408 __le16 error_code; 3409 __le16 req_type; 3410 __le16 seq_id; 3411 __le16 resp_len; 3412 __le32 unused_0; 3413 u8 unused_1; 3414 u8 unused_2; 3415 u8 unused_3; 3416 u8 valid; 3417 }; 3418 3419 /* hwrm_mgmt_l2_filter_alloc */ 3420 /* Input (56 bytes) */ 3421 struct hwrm_mgmt_l2_filter_alloc_input { 3422 __le16 req_type; 3423 __le16 cmpl_ring; 3424 __le16 seq_id; 3425 __le16 target_id; 3426 __le64 resp_addr; 3427 __le32 flags; 3428 #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3429 #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3430 #define MGMT_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3431 __le32 enables; 3432 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDRESS 0x1UL 3433 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_OVLAN 0x2UL 3434 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_IVLAN 0x4UL 3435 #define MGMT_L2_FILTER_ALLOC_REQ_ENABLES_ACTION_ID 0x8UL 3436 u8 l2_address[6]; 3437 u8 unused_0; 3438 u8 unused_1; 3439 u8 l2_address_mask[6]; 3440 __le16 ovlan; 3441 __le16 ovlan_mask; 3442 __le16 ivlan; 3443 __le16 ivlan_mask; 3444 u8 unused_2; 3445 u8 unused_3; 3446 __le32 action_id; 3447 u8 action_bypass; 3448 #define MGMT_L2_FILTER_ALLOC_REQ_ACTION_BYPASS 0x1UL 3449 u8 unused_5[3]; 3450 }; 3451 3452 /* Output (16 bytes) */ 3453 struct hwrm_mgmt_l2_filter_alloc_output { 3454 __le16 error_code; 3455 __le16 req_type; 3456 __le16 seq_id; 3457 __le16 resp_len; 3458 __le16 mgmt_l2_filter_id; 3459 u8 unused_0; 3460 u8 unused_1; 3461 u8 unused_2; 3462 u8 unused_3; 3463 u8 unused_4; 3464 u8 valid; 3465 }; 3466 3467 /* hwrm_mgmt_l2_filter_free */ 3468 /* Input (24 bytes) */ 3469 struct hwrm_mgmt_l2_filter_free_input { 3470 __le16 req_type; 3471 __le16 cmpl_ring; 3472 __le16 seq_id; 3473 __le16 target_id; 3474 __le64 resp_addr; 3475 __le16 mgmt_l2_filter_id; 3476 __le16 unused_0[3]; 3477 }; 3478 3479 /* Output (16 bytes) */ 3480 struct hwrm_mgmt_l2_filter_free_output { 3481 __le16 error_code; 3482 __le16 req_type; 3483 __le16 seq_id; 3484 __le16 resp_len; 3485 __le32 unused_0; 3486 u8 unused_1; 3487 u8 unused_2; 3488 u8 unused_3; 3489 u8 valid; 3490 }; 3491 3492 /* hwrm_nvm_raw_write_blk */ 3493 /* Input (32 bytes) */ 3494 struct hwrm_nvm_raw_write_blk_input { 3495 __le16 req_type; 3496 __le16 cmpl_ring; 3497 __le16 seq_id; 3498 __le16 target_id; 3499 __le64 resp_addr; 3500 __le64 host_src_addr; 3501 __le32 dest_addr; 3502 __le32 len; 3503 }; 3504 3505 /* Output (16 bytes) */ 3506 struct hwrm_nvm_raw_write_blk_output { 3507 __le16 error_code; 3508 __le16 req_type; 3509 __le16 seq_id; 3510 __le16 resp_len; 3511 __le32 unused_0; 3512 u8 unused_1; 3513 u8 unused_2; 3514 u8 unused_3; 3515 u8 valid; 3516 }; 3517 3518 /* hwrm_nvm_read */ 3519 /* Input (40 bytes) */ 3520 struct hwrm_nvm_read_input { 3521 __le16 req_type; 3522 __le16 cmpl_ring; 3523 __le16 seq_id; 3524 __le16 target_id; 3525 __le64 resp_addr; 3526 __le64 host_dest_addr; 3527 __le16 dir_idx; 3528 u8 unused_0; 3529 u8 unused_1; 3530 __le32 offset; 3531 __le32 len; 3532 __le32 unused_2; 3533 }; 3534 3535 /* Output (16 bytes) */ 3536 struct hwrm_nvm_read_output { 3537 __le16 error_code; 3538 __le16 req_type; 3539 __le16 seq_id; 3540 __le16 resp_len; 3541 __le32 unused_0; 3542 u8 unused_1; 3543 u8 unused_2; 3544 u8 unused_3; 3545 u8 valid; 3546 }; 3547 3548 /* hwrm_nvm_raw_dump */ 3549 /* Input (32 bytes) */ 3550 struct hwrm_nvm_raw_dump_input { 3551 __le16 req_type; 3552 __le16 cmpl_ring; 3553 __le16 seq_id; 3554 __le16 target_id; 3555 __le64 resp_addr; 3556 __le64 host_dest_addr; 3557 __le32 offset; 3558 __le32 len; 3559 }; 3560 3561 /* Output (16 bytes) */ 3562 struct hwrm_nvm_raw_dump_output { 3563 __le16 error_code; 3564 __le16 req_type; 3565 __le16 seq_id; 3566 __le16 resp_len; 3567 __le32 unused_0; 3568 u8 unused_1; 3569 u8 unused_2; 3570 u8 unused_3; 3571 u8 valid; 3572 }; 3573 3574 /* hwrm_nvm_get_dir_entries */ 3575 /* Input (24 bytes) */ 3576 struct hwrm_nvm_get_dir_entries_input { 3577 __le16 req_type; 3578 __le16 cmpl_ring; 3579 __le16 seq_id; 3580 __le16 target_id; 3581 __le64 resp_addr; 3582 __le64 host_dest_addr; 3583 }; 3584 3585 /* Output (16 bytes) */ 3586 struct hwrm_nvm_get_dir_entries_output { 3587 __le16 error_code; 3588 __le16 req_type; 3589 __le16 seq_id; 3590 __le16 resp_len; 3591 __le32 unused_0; 3592 u8 unused_1; 3593 u8 unused_2; 3594 u8 unused_3; 3595 u8 valid; 3596 }; 3597 3598 /* hwrm_nvm_get_dir_info */ 3599 /* Input (16 bytes) */ 3600 struct hwrm_nvm_get_dir_info_input { 3601 __le16 req_type; 3602 __le16 cmpl_ring; 3603 __le16 seq_id; 3604 __le16 target_id; 3605 __le64 resp_addr; 3606 }; 3607 3608 /* Output (24 bytes) */ 3609 struct hwrm_nvm_get_dir_info_output { 3610 __le16 error_code; 3611 __le16 req_type; 3612 __le16 seq_id; 3613 __le16 resp_len; 3614 __le32 entries; 3615 __le32 entry_length; 3616 __le32 unused_0; 3617 u8 unused_1; 3618 u8 unused_2; 3619 u8 unused_3; 3620 u8 valid; 3621 }; 3622 3623 /* hwrm_nvm_write */ 3624 /* Input (40 bytes) */ 3625 struct hwrm_nvm_write_input { 3626 __le16 req_type; 3627 __le16 cmpl_ring; 3628 __le16 seq_id; 3629 __le16 target_id; 3630 __le64 resp_addr; 3631 __le64 host_src_addr; 3632 __le16 dir_type; 3633 __le16 dir_ordinal; 3634 __le16 dir_ext; 3635 __le16 dir_attr; 3636 __le32 dir_data_length; 3637 __le16 option; 3638 __le16 flags; 3639 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 3640 }; 3641 3642 /* Output (16 bytes) */ 3643 struct hwrm_nvm_write_output { 3644 __le16 error_code; 3645 __le16 req_type; 3646 __le16 seq_id; 3647 __le16 resp_len; 3648 __le32 unused_0; 3649 u8 unused_1; 3650 u8 unused_2; 3651 u8 unused_3; 3652 u8 valid; 3653 }; 3654 3655 /* hwrm_nvm_modify */ 3656 /* Input (40 bytes) */ 3657 struct hwrm_nvm_modify_input { 3658 __le16 req_type; 3659 __le16 cmpl_ring; 3660 __le16 seq_id; 3661 __le16 target_id; 3662 __le64 resp_addr; 3663 __le64 host_src_addr; 3664 __le16 dir_idx; 3665 u8 unused_0; 3666 u8 unused_1; 3667 __le32 offset; 3668 __le32 len; 3669 __le32 unused_2; 3670 }; 3671 3672 /* Output (16 bytes) */ 3673 struct hwrm_nvm_modify_output { 3674 __le16 error_code; 3675 __le16 req_type; 3676 __le16 seq_id; 3677 __le16 resp_len; 3678 __le32 unused_0; 3679 u8 unused_1; 3680 u8 unused_2; 3681 u8 unused_3; 3682 u8 valid; 3683 }; 3684 3685 /* hwrm_nvm_find_dir_entry */ 3686 /* Input (32 bytes) */ 3687 struct hwrm_nvm_find_dir_entry_input { 3688 __le16 req_type; 3689 __le16 cmpl_ring; 3690 __le16 seq_id; 3691 __le16 target_id; 3692 __le64 resp_addr; 3693 __le32 enables; 3694 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 3695 __le16 dir_idx; 3696 __le16 dir_type; 3697 __le16 dir_ordinal; 3698 __le16 dir_ext; 3699 u8 opt_ordinal; 3700 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 3701 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 3702 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0) 3703 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0) 3704 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0) 3705 u8 unused_1[3]; 3706 }; 3707 3708 /* Output (32 bytes) */ 3709 struct hwrm_nvm_find_dir_entry_output { 3710 __le16 error_code; 3711 __le16 req_type; 3712 __le16 seq_id; 3713 __le16 resp_len; 3714 __le32 dir_item_length; 3715 __le32 dir_data_length; 3716 __le32 fw_ver; 3717 __le16 dir_ordinal; 3718 __le16 dir_idx; 3719 __le32 unused_0; 3720 u8 unused_1; 3721 u8 unused_2; 3722 u8 unused_3; 3723 u8 valid; 3724 }; 3725 3726 /* hwrm_nvm_erase_dir_entry */ 3727 /* Input (24 bytes) */ 3728 struct hwrm_nvm_erase_dir_entry_input { 3729 __le16 req_type; 3730 __le16 cmpl_ring; 3731 __le16 seq_id; 3732 __le16 target_id; 3733 __le64 resp_addr; 3734 __le16 dir_idx; 3735 __le16 unused_0[3]; 3736 }; 3737 3738 /* Output (16 bytes) */ 3739 struct hwrm_nvm_erase_dir_entry_output { 3740 __le16 error_code; 3741 __le16 req_type; 3742 __le16 seq_id; 3743 __le16 resp_len; 3744 __le32 unused_0; 3745 u8 unused_1; 3746 u8 unused_2; 3747 u8 unused_3; 3748 u8 valid; 3749 }; 3750 3751 /* hwrm_nvm_get_dev_info */ 3752 /* Input (16 bytes) */ 3753 struct hwrm_nvm_get_dev_info_input { 3754 __le16 req_type; 3755 __le16 cmpl_ring; 3756 __le16 seq_id; 3757 __le16 target_id; 3758 __le64 resp_addr; 3759 }; 3760 3761 /* Output (32 bytes) */ 3762 struct hwrm_nvm_get_dev_info_output { 3763 __le16 error_code; 3764 __le16 req_type; 3765 __le16 seq_id; 3766 __le16 resp_len; 3767 __le16 manufacturer_id; 3768 __le16 device_id; 3769 __le32 sector_size; 3770 __le32 nvram_size; 3771 __le32 reserved_size; 3772 __le32 available_size; 3773 u8 unused_0; 3774 u8 unused_1; 3775 u8 unused_2; 3776 u8 valid; 3777 }; 3778 3779 /* hwrm_nvm_mod_dir_entry */ 3780 /* Input (32 bytes) */ 3781 struct hwrm_nvm_mod_dir_entry_input { 3782 __le16 req_type; 3783 __le16 cmpl_ring; 3784 __le16 seq_id; 3785 __le16 target_id; 3786 __le64 resp_addr; 3787 __le32 enables; 3788 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 3789 __le16 dir_idx; 3790 __le16 dir_ordinal; 3791 __le16 dir_ext; 3792 __le16 dir_attr; 3793 __le32 checksum; 3794 }; 3795 3796 /* Output (16 bytes) */ 3797 struct hwrm_nvm_mod_dir_entry_output { 3798 __le16 error_code; 3799 __le16 req_type; 3800 __le16 seq_id; 3801 __le16 resp_len; 3802 __le32 unused_0; 3803 u8 unused_1; 3804 u8 unused_2; 3805 u8 unused_3; 3806 u8 valid; 3807 }; 3808 3809 /* hwrm_nvm_verify_update */ 3810 /* Input (24 bytes) */ 3811 struct hwrm_nvm_verify_update_input { 3812 __le16 req_type; 3813 __le16 cmpl_ring; 3814 __le16 seq_id; 3815 __le16 target_id; 3816 __le64 resp_addr; 3817 __le16 dir_type; 3818 __le16 dir_ordinal; 3819 __le16 dir_ext; 3820 __le16 unused_0; 3821 }; 3822 3823 /* Output (16 bytes) */ 3824 struct hwrm_nvm_verify_update_output { 3825 __le16 error_code; 3826 __le16 req_type; 3827 __le16 seq_id; 3828 __le16 resp_len; 3829 __le32 unused_0; 3830 u8 unused_1; 3831 u8 unused_2; 3832 u8 unused_3; 3833 u8 valid; 3834 }; 3835 3836 /* hwrm_exec_fwd_resp */ 3837 /* Input (120 bytes) */ 3838 struct hwrm_exec_fwd_resp_input { 3839 __le16 req_type; 3840 __le16 cmpl_ring; 3841 __le16 seq_id; 3842 __le16 target_id; 3843 __le64 resp_addr; 3844 __le32 encap_request[24]; 3845 __le16 encap_resp_target_id; 3846 __le16 unused_0[3]; 3847 }; 3848 3849 /* Output (16 bytes) */ 3850 struct hwrm_exec_fwd_resp_output { 3851 __le16 error_code; 3852 __le16 req_type; 3853 __le16 seq_id; 3854 __le16 resp_len; 3855 __le32 unused_0; 3856 u8 unused_1; 3857 u8 unused_2; 3858 u8 unused_3; 3859 u8 valid; 3860 }; 3861 3862 /* hwrm_reject_fwd_resp */ 3863 /* Input (120 bytes) */ 3864 struct hwrm_reject_fwd_resp_input { 3865 __le16 req_type; 3866 __le16 cmpl_ring; 3867 __le16 seq_id; 3868 __le16 target_id; 3869 __le64 resp_addr; 3870 __le32 encap_request[24]; 3871 __le16 encap_resp_target_id; 3872 __le16 unused_0[3]; 3873 }; 3874 3875 /* Output (16 bytes) */ 3876 struct hwrm_reject_fwd_resp_output { 3877 __le16 error_code; 3878 __le16 req_type; 3879 __le16 seq_id; 3880 __le16 resp_len; 3881 __le32 unused_0; 3882 u8 unused_1; 3883 u8 unused_2; 3884 u8 unused_3; 3885 u8 valid; 3886 }; 3887 3888 /* hwrm_fwd_resp */ 3889 /* Input (40 bytes) */ 3890 struct hwrm_fwd_resp_input { 3891 __le16 req_type; 3892 __le16 cmpl_ring; 3893 __le16 seq_id; 3894 __le16 target_id; 3895 __le64 resp_addr; 3896 __le16 encap_resp_target_id; 3897 __le16 encap_resp_cmpl_ring; 3898 __le16 encap_resp_len; 3899 u8 unused_0; 3900 u8 unused_1; 3901 __le64 encap_resp_addr; 3902 __le32 encap_resp[24]; 3903 }; 3904 3905 /* Output (16 bytes) */ 3906 struct hwrm_fwd_resp_output { 3907 __le16 error_code; 3908 __le16 req_type; 3909 __le16 seq_id; 3910 __le16 resp_len; 3911 __le32 unused_0; 3912 u8 unused_1; 3913 u8 unused_2; 3914 u8 unused_3; 3915 u8 valid; 3916 }; 3917 3918 /* hwrm_fwd_async_event_cmpl */ 3919 /* Input (32 bytes) */ 3920 struct hwrm_fwd_async_event_cmpl_input { 3921 __le16 req_type; 3922 __le16 cmpl_ring; 3923 __le16 seq_id; 3924 __le16 target_id; 3925 __le64 resp_addr; 3926 __le16 encap_async_event_target_id; 3927 u8 unused_0; 3928 u8 unused_1; 3929 u8 unused_2[3]; 3930 u8 unused_3; 3931 __le32 encap_async_event_cmpl[4]; 3932 }; 3933 3934 /* Output (16 bytes) */ 3935 struct hwrm_fwd_async_event_cmpl_output { 3936 __le16 error_code; 3937 __le16 req_type; 3938 __le16 seq_id; 3939 __le16 resp_len; 3940 __le32 unused_0; 3941 u8 unused_1; 3942 u8 unused_2; 3943 u8 unused_3; 3944 u8 valid; 3945 }; 3946 3947 /* hwrm_fw_reset */ 3948 /* Input (24 bytes) */ 3949 struct hwrm_fw_reset_input { 3950 __le16 req_type; 3951 __le16 cmpl_ring; 3952 __le16 seq_id; 3953 __le16 target_id; 3954 __le64 resp_addr; 3955 u8 embedded_proc_type; 3956 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIMP (0x0UL << 0) 3957 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_APE (0x1UL << 0) 3958 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_KONG (0x2UL << 0) 3959 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BONO (0x3UL << 0) 3960 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_TANG (0x4UL << 0) 3961 u8 selfrst_status; 3962 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3963 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3964 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3965 __le16 unused_0[3]; 3966 }; 3967 3968 /* Output (16 bytes) */ 3969 struct hwrm_fw_reset_output { 3970 __le16 error_code; 3971 __le16 req_type; 3972 __le16 seq_id; 3973 __le16 resp_len; 3974 u8 selfrst_status; 3975 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3976 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3977 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3978 u8 unused_0; 3979 __le16 unused_1; 3980 u8 unused_2; 3981 u8 unused_3; 3982 u8 unused_4; 3983 u8 valid; 3984 }; 3985 3986 /* hwrm_fw_qstatus */ 3987 /* Input (24 bytes) */ 3988 struct hwrm_fw_qstatus_input { 3989 __le16 req_type; 3990 __le16 cmpl_ring; 3991 __le16 seq_id; 3992 __le16 target_id; 3993 __le64 resp_addr; 3994 u8 embedded_proc_type; 3995 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIMP (0x0UL << 0) 3996 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_APE (0x1UL << 0) 3997 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_KONG (0x2UL << 0) 3998 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BONO (0x3UL << 0) 3999 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_TANG (0x4UL << 0) 4000 u8 unused_0[7]; 4001 }; 4002 4003 /* Output (16 bytes) */ 4004 struct hwrm_fw_qstatus_output { 4005 __le16 error_code; 4006 __le16 req_type; 4007 __le16 seq_id; 4008 __le16 resp_len; 4009 u8 selfrst_status; 4010 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 4011 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 4012 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 4013 u8 unused_0; 4014 __le16 unused_1; 4015 u8 unused_2; 4016 u8 unused_3; 4017 u8 unused_4; 4018 u8 valid; 4019 }; 4020 4021 /* hwrm_temp_monitor_query */ 4022 /* Input (16 bytes) */ 4023 struct hwrm_temp_monitor_query_input { 4024 __le16 req_type; 4025 __le16 cmpl_ring; 4026 __le16 seq_id; 4027 __le16 target_id; 4028 __le64 resp_addr; 4029 }; 4030 4031 /* Output (16 bytes) */ 4032 struct hwrm_temp_monitor_query_output { 4033 __le16 error_code; 4034 __le16 req_type; 4035 __le16 seq_id; 4036 __le16 resp_len; 4037 u8 temp; 4038 u8 unused_0; 4039 __le16 unused_1; 4040 u8 unused_2; 4041 u8 unused_3; 4042 u8 unused_4; 4043 u8 valid; 4044 }; 4045 4046 #endif 4047