1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2019 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_SRT_ECC_PUBLIC_KEY 52 53 54 /* tlv (size:64b/8B) */ 55 struct tlv { 56 __le16 cmd_discr; 57 u8 reserved_8b; 58 u8 flags; 59 #define TLV_FLAGS_MORE 0x1UL 60 #define TLV_FLAGS_MORE_LAST 0x0UL 61 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 62 #define TLV_FLAGS_REQUIRED 0x2UL 63 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 64 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 65 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 66 __le16 tlv_type; 67 __le16 length; 68 }; 69 70 /* input (size:128b/16B) */ 71 struct input { 72 __le16 req_type; 73 __le16 cmpl_ring; 74 __le16 seq_id; 75 __le16 target_id; 76 __le64 resp_addr; 77 }; 78 79 /* output (size:64b/8B) */ 80 struct output { 81 __le16 error_code; 82 __le16 req_type; 83 __le16 seq_id; 84 __le16 resp_len; 85 }; 86 87 /* hwrm_short_input (size:128b/16B) */ 88 struct hwrm_short_input { 89 __le16 req_type; 90 __le16 signature; 91 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 92 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 93 __le16 target_id; 94 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 95 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 96 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 97 __le16 size; 98 __le64 req_addr; 99 }; 100 101 /* cmd_nums (size:64b/8B) */ 102 struct cmd_nums { 103 __le16 req_type; 104 #define HWRM_VER_GET 0x0UL 105 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 106 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 107 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 108 #define HWRM_FUNC_VF_CFG 0xfUL 109 #define HWRM_RESERVED1 0x10UL 110 #define HWRM_FUNC_RESET 0x11UL 111 #define HWRM_FUNC_GETFID 0x12UL 112 #define HWRM_FUNC_VF_ALLOC 0x13UL 113 #define HWRM_FUNC_VF_FREE 0x14UL 114 #define HWRM_FUNC_QCAPS 0x15UL 115 #define HWRM_FUNC_QCFG 0x16UL 116 #define HWRM_FUNC_CFG 0x17UL 117 #define HWRM_FUNC_QSTATS 0x18UL 118 #define HWRM_FUNC_CLR_STATS 0x19UL 119 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 120 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 121 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 122 #define HWRM_FUNC_DRV_RGTR 0x1dUL 123 #define HWRM_FUNC_DRV_QVER 0x1eUL 124 #define HWRM_FUNC_BUF_RGTR 0x1fUL 125 #define HWRM_PORT_PHY_CFG 0x20UL 126 #define HWRM_PORT_MAC_CFG 0x21UL 127 #define HWRM_PORT_TS_QUERY 0x22UL 128 #define HWRM_PORT_QSTATS 0x23UL 129 #define HWRM_PORT_LPBK_QSTATS 0x24UL 130 #define HWRM_PORT_CLR_STATS 0x25UL 131 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 132 #define HWRM_PORT_PHY_QCFG 0x27UL 133 #define HWRM_PORT_MAC_QCFG 0x28UL 134 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 135 #define HWRM_PORT_PHY_QCAPS 0x2aUL 136 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 137 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 138 #define HWRM_PORT_LED_CFG 0x2dUL 139 #define HWRM_PORT_LED_QCFG 0x2eUL 140 #define HWRM_PORT_LED_QCAPS 0x2fUL 141 #define HWRM_QUEUE_QPORTCFG 0x30UL 142 #define HWRM_QUEUE_QCFG 0x31UL 143 #define HWRM_QUEUE_CFG 0x32UL 144 #define HWRM_FUNC_VLAN_CFG 0x33UL 145 #define HWRM_FUNC_VLAN_QCFG 0x34UL 146 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 147 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 148 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 149 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 150 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 151 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 152 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 153 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 154 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 155 #define HWRM_VNIC_ALLOC 0x40UL 156 #define HWRM_VNIC_FREE 0x41UL 157 #define HWRM_VNIC_CFG 0x42UL 158 #define HWRM_VNIC_QCFG 0x43UL 159 #define HWRM_VNIC_TPA_CFG 0x44UL 160 #define HWRM_VNIC_TPA_QCFG 0x45UL 161 #define HWRM_VNIC_RSS_CFG 0x46UL 162 #define HWRM_VNIC_RSS_QCFG 0x47UL 163 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 164 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 165 #define HWRM_VNIC_QCAPS 0x4aUL 166 #define HWRM_RING_ALLOC 0x50UL 167 #define HWRM_RING_FREE 0x51UL 168 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 169 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 170 #define HWRM_RING_AGGINT_QCAPS 0x54UL 171 #define HWRM_RING_RESET 0x5eUL 172 #define HWRM_RING_GRP_ALLOC 0x60UL 173 #define HWRM_RING_GRP_FREE 0x61UL 174 #define HWRM_RESERVED5 0x64UL 175 #define HWRM_RESERVED6 0x65UL 176 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 177 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 178 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 179 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 180 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 181 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 182 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 183 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 184 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 185 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 186 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 187 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 188 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 189 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 190 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 191 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 192 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 193 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 194 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 195 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 196 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 197 #define HWRM_STAT_CTX_ALLOC 0xb0UL 198 #define HWRM_STAT_CTX_FREE 0xb1UL 199 #define HWRM_STAT_CTX_QUERY 0xb2UL 200 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 201 #define HWRM_PORT_QSTATS_EXT 0xb4UL 202 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 203 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 204 #define HWRM_FW_RESET 0xc0UL 205 #define HWRM_FW_QSTATUS 0xc1UL 206 #define HWRM_FW_HEALTH_CHECK 0xc2UL 207 #define HWRM_FW_SYNC 0xc3UL 208 #define HWRM_FW_SET_TIME 0xc8UL 209 #define HWRM_FW_GET_TIME 0xc9UL 210 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 211 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 212 #define HWRM_FW_IPC_MAILBOX 0xccUL 213 #define HWRM_EXEC_FWD_RESP 0xd0UL 214 #define HWRM_REJECT_FWD_RESP 0xd1UL 215 #define HWRM_FWD_RESP 0xd2UL 216 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 217 #define HWRM_OEM_CMD 0xd4UL 218 #define HWRM_PORT_PRBS_TEST 0xd5UL 219 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 220 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 221 #define HWRM_WOL_FILTER_FREE 0xf1UL 222 #define HWRM_WOL_FILTER_QCFG 0xf2UL 223 #define HWRM_WOL_REASON_QCFG 0xf3UL 224 #define HWRM_CFA_METER_QCAPS 0xf4UL 225 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 226 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 227 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 228 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 229 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 230 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 231 #define HWRM_CFA_VFR_ALLOC 0xfdUL 232 #define HWRM_CFA_VFR_FREE 0xfeUL 233 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 234 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 235 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 236 #define HWRM_CFA_FLOW_ALLOC 0x103UL 237 #define HWRM_CFA_FLOW_FREE 0x104UL 238 #define HWRM_CFA_FLOW_FLUSH 0x105UL 239 #define HWRM_CFA_FLOW_STATS 0x106UL 240 #define HWRM_CFA_FLOW_INFO 0x107UL 241 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 242 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 243 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 244 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 245 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 246 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 247 #define HWRM_CFA_PAIR_FREE 0x10eUL 248 #define HWRM_CFA_PAIR_INFO 0x10fUL 249 #define HWRM_FW_IPC_MSG 0x110UL 250 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 251 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 252 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 253 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 254 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 255 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 256 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 257 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 258 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 259 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 260 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 261 #define HWRM_CFA_COUNTER_CFG 0x11cUL 262 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 263 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 264 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 265 #define HWRM_CFA_EEM_QCAPS 0x120UL 266 #define HWRM_CFA_EEM_CFG 0x121UL 267 #define HWRM_CFA_EEM_QCFG 0x122UL 268 #define HWRM_CFA_EEM_OP 0x123UL 269 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 270 #define HWRM_CFA_TFLIB 0x125UL 271 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 272 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 273 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 274 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 275 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 276 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 277 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 278 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 279 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 280 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 281 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 282 #define HWRM_ENGINE_QG_QUERY 0x13dUL 283 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 284 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 285 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 286 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 287 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 288 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 289 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 290 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 291 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 292 #define HWRM_ENGINE_SG_QUERY 0x147UL 293 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 294 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 295 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 296 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 297 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 298 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 299 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 300 #define HWRM_ENGINE_STATS_QUERY 0x157UL 301 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 302 #define HWRM_ENGINE_RQ_FREE 0x15fUL 303 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 304 #define HWRM_ENGINE_CQ_FREE 0x161UL 305 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 306 #define HWRM_ENGINE_NQ_FREE 0x163UL 307 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 308 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 309 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 310 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 311 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 312 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 313 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 314 #define HWRM_FUNC_VF_BW_CFG 0x195UL 315 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 316 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 317 #define HWRM_SELFTEST_QLIST 0x200UL 318 #define HWRM_SELFTEST_EXEC 0x201UL 319 #define HWRM_SELFTEST_IRQ 0x202UL 320 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 321 #define HWRM_PCIE_QSTATS 0x204UL 322 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 323 #define HWRM_MFG_TIMERS_QUERY 0x206UL 324 #define HWRM_MFG_OTP_CFG 0x207UL 325 #define HWRM_MFG_OTP_QCFG 0x208UL 326 #define HWRM_MFG_HDMA_TEST 0x209UL 327 #define HWRM_DBG_READ_DIRECT 0xff10UL 328 #define HWRM_DBG_READ_INDIRECT 0xff11UL 329 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 330 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 331 #define HWRM_DBG_DUMP 0xff14UL 332 #define HWRM_DBG_ERASE_NVM 0xff15UL 333 #define HWRM_DBG_CFG 0xff16UL 334 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 335 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 336 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 337 #define HWRM_DBG_FW_CLI 0xff1aUL 338 #define HWRM_DBG_I2C_CMD 0xff1bUL 339 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 340 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 341 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 342 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 343 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 344 #define HWRM_NVM_FLUSH 0xfff0UL 345 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 346 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 347 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 348 #define HWRM_NVM_MODIFY 0xfff4UL 349 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 350 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 351 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 352 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 353 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 354 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 355 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 356 #define HWRM_NVM_RAW_DUMP 0xfffcUL 357 #define HWRM_NVM_READ 0xfffdUL 358 #define HWRM_NVM_WRITE 0xfffeUL 359 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 360 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 361 __le16 unused_0[3]; 362 }; 363 364 /* ret_codes (size:64b/8B) */ 365 struct ret_codes { 366 __le16 error_code; 367 #define HWRM_ERR_CODE_SUCCESS 0x0UL 368 #define HWRM_ERR_CODE_FAIL 0x1UL 369 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 370 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 371 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 372 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 373 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 374 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 375 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 376 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 377 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 378 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 379 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 380 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 381 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 382 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 383 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 384 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 385 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 386 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 387 __le16 unused_0[3]; 388 }; 389 390 /* hwrm_err_output (size:128b/16B) */ 391 struct hwrm_err_output { 392 __le16 error_code; 393 __le16 req_type; 394 __le16 seq_id; 395 __le16 resp_len; 396 __le32 opaque_0; 397 __le16 opaque_1; 398 u8 cmd_err; 399 u8 valid; 400 }; 401 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 402 #define HWRM_MAX_REQ_LEN 128 403 #define HWRM_MAX_RESP_LEN 704 404 #define HW_HASH_INDEX_SIZE 0x80 405 #define HW_HASH_KEY_SIZE 40 406 #define HWRM_RESP_VALID_KEY 1 407 #define HWRM_TARGET_ID_BONO 0xFFF8 408 #define HWRM_TARGET_ID_KONG 0xFFF9 409 #define HWRM_TARGET_ID_APE 0xFFFA 410 #define HWRM_TARGET_ID_TOOLS 0xFFFD 411 #define HWRM_VERSION_MAJOR 1 412 #define HWRM_VERSION_MINOR 10 413 #define HWRM_VERSION_UPDATE 0 414 #define HWRM_VERSION_RSVD 89 415 #define HWRM_VERSION_STR "1.10.0.89" 416 417 /* hwrm_ver_get_input (size:192b/24B) */ 418 struct hwrm_ver_get_input { 419 __le16 req_type; 420 __le16 cmpl_ring; 421 __le16 seq_id; 422 __le16 target_id; 423 __le64 resp_addr; 424 u8 hwrm_intf_maj; 425 u8 hwrm_intf_min; 426 u8 hwrm_intf_upd; 427 u8 unused_0[5]; 428 }; 429 430 /* hwrm_ver_get_output (size:1408b/176B) */ 431 struct hwrm_ver_get_output { 432 __le16 error_code; 433 __le16 req_type; 434 __le16 seq_id; 435 __le16 resp_len; 436 u8 hwrm_intf_maj_8b; 437 u8 hwrm_intf_min_8b; 438 u8 hwrm_intf_upd_8b; 439 u8 hwrm_intf_rsvd_8b; 440 u8 hwrm_fw_maj_8b; 441 u8 hwrm_fw_min_8b; 442 u8 hwrm_fw_bld_8b; 443 u8 hwrm_fw_rsvd_8b; 444 u8 mgmt_fw_maj_8b; 445 u8 mgmt_fw_min_8b; 446 u8 mgmt_fw_bld_8b; 447 u8 mgmt_fw_rsvd_8b; 448 u8 netctrl_fw_maj_8b; 449 u8 netctrl_fw_min_8b; 450 u8 netctrl_fw_bld_8b; 451 u8 netctrl_fw_rsvd_8b; 452 __le32 dev_caps_cfg; 453 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 454 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 455 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 456 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 457 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 458 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 459 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 460 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 461 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 462 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 463 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 464 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 465 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 466 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 467 u8 roce_fw_maj_8b; 468 u8 roce_fw_min_8b; 469 u8 roce_fw_bld_8b; 470 u8 roce_fw_rsvd_8b; 471 char hwrm_fw_name[16]; 472 char mgmt_fw_name[16]; 473 char netctrl_fw_name[16]; 474 char active_pkg_name[16]; 475 char roce_fw_name[16]; 476 __le16 chip_num; 477 u8 chip_rev; 478 u8 chip_metal; 479 u8 chip_bond_id; 480 u8 chip_platform_type; 481 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 482 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 483 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 484 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 485 __le16 max_req_win_len; 486 __le16 max_resp_len; 487 __le16 def_req_timeout; 488 u8 flags; 489 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 490 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 491 u8 unused_0[2]; 492 u8 always_1; 493 __le16 hwrm_intf_major; 494 __le16 hwrm_intf_minor; 495 __le16 hwrm_intf_build; 496 __le16 hwrm_intf_patch; 497 __le16 hwrm_fw_major; 498 __le16 hwrm_fw_minor; 499 __le16 hwrm_fw_build; 500 __le16 hwrm_fw_patch; 501 __le16 mgmt_fw_major; 502 __le16 mgmt_fw_minor; 503 __le16 mgmt_fw_build; 504 __le16 mgmt_fw_patch; 505 __le16 netctrl_fw_major; 506 __le16 netctrl_fw_minor; 507 __le16 netctrl_fw_build; 508 __le16 netctrl_fw_patch; 509 __le16 roce_fw_major; 510 __le16 roce_fw_minor; 511 __le16 roce_fw_build; 512 __le16 roce_fw_patch; 513 __le16 max_ext_req_len; 514 u8 unused_1[5]; 515 u8 valid; 516 }; 517 518 /* eject_cmpl (size:128b/16B) */ 519 struct eject_cmpl { 520 __le16 type; 521 #define EJECT_CMPL_TYPE_MASK 0x3fUL 522 #define EJECT_CMPL_TYPE_SFT 0 523 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 524 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 525 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 526 #define EJECT_CMPL_FLAGS_SFT 6 527 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 528 __le16 len; 529 __le32 opaque; 530 __le16 v; 531 #define EJECT_CMPL_V 0x1UL 532 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 533 #define EJECT_CMPL_ERRORS_SFT 1 534 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 535 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 536 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 537 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 538 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 539 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 540 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 541 __le16 reserved16; 542 __le32 unused_2; 543 }; 544 545 /* hwrm_cmpl (size:128b/16B) */ 546 struct hwrm_cmpl { 547 __le16 type; 548 #define CMPL_TYPE_MASK 0x3fUL 549 #define CMPL_TYPE_SFT 0 550 #define CMPL_TYPE_HWRM_DONE 0x20UL 551 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 552 __le16 sequence_id; 553 __le32 unused_1; 554 __le32 v; 555 #define CMPL_V 0x1UL 556 __le32 unused_3; 557 }; 558 559 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 560 struct hwrm_fwd_req_cmpl { 561 __le16 req_len_type; 562 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 563 #define FWD_REQ_CMPL_TYPE_SFT 0 564 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 565 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 566 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 567 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 568 __le16 source_id; 569 __le32 unused0; 570 __le32 req_buf_addr_v[2]; 571 #define FWD_REQ_CMPL_V 0x1UL 572 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 573 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 574 }; 575 576 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 577 struct hwrm_fwd_resp_cmpl { 578 __le16 type; 579 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 580 #define FWD_RESP_CMPL_TYPE_SFT 0 581 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 582 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 583 __le16 source_id; 584 __le16 resp_len; 585 __le16 unused_1; 586 __le32 resp_buf_addr_v[2]; 587 #define FWD_RESP_CMPL_V 0x1UL 588 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 589 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 590 }; 591 592 /* hwrm_async_event_cmpl (size:128b/16B) */ 593 struct hwrm_async_event_cmpl { 594 __le16 type; 595 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 596 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 597 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 598 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 599 __le16 event_id; 600 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 601 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 602 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 603 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 604 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 605 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 606 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 607 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 608 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 609 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 610 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 611 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 612 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 613 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 614 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 615 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 616 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 617 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 618 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 619 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 620 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 621 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 622 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 623 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 624 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 625 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 626 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 627 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 628 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 629 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 630 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 631 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 632 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 633 __le32 event_data2; 634 u8 opaque_v; 635 #define ASYNC_EVENT_CMPL_V 0x1UL 636 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 637 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 638 u8 timestamp_lo; 639 __le16 timestamp_hi; 640 __le32 event_data1; 641 }; 642 643 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 644 struct hwrm_async_event_cmpl_link_status_change { 645 __le16 type; 646 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 647 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 648 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 649 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 650 __le16 event_id; 651 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 652 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 653 __le32 event_data2; 654 u8 opaque_v; 655 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 656 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 657 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 658 u8 timestamp_lo; 659 __le16 timestamp_hi; 660 __le32 event_data1; 661 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 662 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 663 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 664 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 665 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 666 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 667 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 668 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 669 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 670 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 671 }; 672 673 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 674 struct hwrm_async_event_cmpl_port_conn_not_allowed { 675 __le16 type; 676 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 677 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 678 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 679 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 680 __le16 event_id; 681 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 682 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 683 __le32 event_data2; 684 u8 opaque_v; 685 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 686 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 687 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 688 u8 timestamp_lo; 689 __le16 timestamp_hi; 690 __le32 event_data1; 691 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 692 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 693 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 694 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 695 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 696 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 697 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 698 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 699 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 700 }; 701 702 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 703 struct hwrm_async_event_cmpl_link_speed_cfg_change { 704 __le16 type; 705 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 706 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 707 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 708 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 709 __le16 event_id; 710 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 711 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 712 __le32 event_data2; 713 u8 opaque_v; 714 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 715 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 716 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 717 u8 timestamp_lo; 718 __le16 timestamp_hi; 719 __le32 event_data1; 720 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 721 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 722 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 723 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 724 }; 725 726 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 727 struct hwrm_async_event_cmpl_reset_notify { 728 __le16 type; 729 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 730 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 731 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 732 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 733 __le16 event_id; 734 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 735 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 736 __le32 event_data2; 737 u8 opaque_v; 738 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 739 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 740 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 741 u8 timestamp_lo; 742 __le16 timestamp_hi; 743 __le32 event_data1; 744 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 745 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 746 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 747 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 748 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 749 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 750 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 751 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 752 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 753 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 754 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 755 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 756 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 757 }; 758 759 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 760 struct hwrm_async_event_cmpl_error_recovery { 761 __le16 type; 762 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 763 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 764 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 765 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 766 __le16 event_id; 767 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 768 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 769 __le32 event_data2; 770 u8 opaque_v; 771 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 772 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 773 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 774 u8 timestamp_lo; 775 __le16 timestamp_hi; 776 __le32 event_data1; 777 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 778 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 779 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 780 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 781 }; 782 783 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 784 struct hwrm_async_event_cmpl_vf_cfg_change { 785 __le16 type; 786 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 787 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 788 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 789 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 790 __le16 event_id; 791 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 792 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 793 __le32 event_data2; 794 u8 opaque_v; 795 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 796 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 797 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 798 u8 timestamp_lo; 799 __le16 timestamp_hi; 800 __le32 event_data1; 801 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 802 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 803 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 804 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 805 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 806 }; 807 808 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 809 struct hwrm_async_event_cmpl_hw_flow_aged { 810 __le16 type; 811 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 812 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 813 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 814 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 815 __le16 event_id; 816 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 817 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 818 __le32 event_data2; 819 u8 opaque_v; 820 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 821 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 822 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 823 u8 timestamp_lo; 824 __le16 timestamp_hi; 825 __le32 event_data1; 826 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 827 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 828 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 829 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 830 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 831 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 832 }; 833 834 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 835 struct hwrm_async_event_cmpl_eem_cache_flush_req { 836 __le16 type; 837 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 838 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 839 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 840 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 841 __le16 event_id; 842 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 843 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 844 __le32 event_data2; 845 u8 opaque_v; 846 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 847 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 848 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 849 u8 timestamp_lo; 850 __le16 timestamp_hi; 851 __le32 event_data1; 852 }; 853 854 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 855 struct hwrm_async_event_cmpl_eem_cache_flush_done { 856 __le16 type; 857 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 858 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 859 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 860 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 861 __le16 event_id; 862 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 863 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 864 __le32 event_data2; 865 u8 opaque_v; 866 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 867 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 868 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 869 u8 timestamp_lo; 870 __le16 timestamp_hi; 871 __le32 event_data1; 872 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 873 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 874 }; 875 876 /* hwrm_func_reset_input (size:192b/24B) */ 877 struct hwrm_func_reset_input { 878 __le16 req_type; 879 __le16 cmpl_ring; 880 __le16 seq_id; 881 __le16 target_id; 882 __le64 resp_addr; 883 __le32 enables; 884 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 885 __le16 vf_id; 886 u8 func_reset_level; 887 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 888 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 889 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 890 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 891 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 892 u8 unused_0; 893 }; 894 895 /* hwrm_func_reset_output (size:128b/16B) */ 896 struct hwrm_func_reset_output { 897 __le16 error_code; 898 __le16 req_type; 899 __le16 seq_id; 900 __le16 resp_len; 901 u8 unused_0[7]; 902 u8 valid; 903 }; 904 905 /* hwrm_func_getfid_input (size:192b/24B) */ 906 struct hwrm_func_getfid_input { 907 __le16 req_type; 908 __le16 cmpl_ring; 909 __le16 seq_id; 910 __le16 target_id; 911 __le64 resp_addr; 912 __le32 enables; 913 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 914 __le16 pci_id; 915 u8 unused_0[2]; 916 }; 917 918 /* hwrm_func_getfid_output (size:128b/16B) */ 919 struct hwrm_func_getfid_output { 920 __le16 error_code; 921 __le16 req_type; 922 __le16 seq_id; 923 __le16 resp_len; 924 __le16 fid; 925 u8 unused_0[5]; 926 u8 valid; 927 }; 928 929 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 930 struct hwrm_func_vf_alloc_input { 931 __le16 req_type; 932 __le16 cmpl_ring; 933 __le16 seq_id; 934 __le16 target_id; 935 __le64 resp_addr; 936 __le32 enables; 937 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 938 __le16 first_vf_id; 939 __le16 num_vfs; 940 }; 941 942 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 943 struct hwrm_func_vf_alloc_output { 944 __le16 error_code; 945 __le16 req_type; 946 __le16 seq_id; 947 __le16 resp_len; 948 __le16 first_vf_id; 949 u8 unused_0[5]; 950 u8 valid; 951 }; 952 953 /* hwrm_func_vf_free_input (size:192b/24B) */ 954 struct hwrm_func_vf_free_input { 955 __le16 req_type; 956 __le16 cmpl_ring; 957 __le16 seq_id; 958 __le16 target_id; 959 __le64 resp_addr; 960 __le32 enables; 961 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 962 __le16 first_vf_id; 963 __le16 num_vfs; 964 }; 965 966 /* hwrm_func_vf_free_output (size:128b/16B) */ 967 struct hwrm_func_vf_free_output { 968 __le16 error_code; 969 __le16 req_type; 970 __le16 seq_id; 971 __le16 resp_len; 972 u8 unused_0[7]; 973 u8 valid; 974 }; 975 976 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 977 struct hwrm_func_vf_cfg_input { 978 __le16 req_type; 979 __le16 cmpl_ring; 980 __le16 seq_id; 981 __le16 target_id; 982 __le64 resp_addr; 983 __le32 enables; 984 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 985 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 986 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 987 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 988 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 989 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 990 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 991 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 992 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 993 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 994 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 995 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 996 __le16 mtu; 997 __le16 guest_vlan; 998 __le16 async_event_cr; 999 u8 dflt_mac_addr[6]; 1000 __le32 flags; 1001 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1002 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1003 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1004 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1005 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1006 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1007 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1008 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1009 __le16 num_rsscos_ctxs; 1010 __le16 num_cmpl_rings; 1011 __le16 num_tx_rings; 1012 __le16 num_rx_rings; 1013 __le16 num_l2_ctxs; 1014 __le16 num_vnics; 1015 __le16 num_stat_ctxs; 1016 __le16 num_hw_ring_grps; 1017 u8 unused_0[4]; 1018 }; 1019 1020 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1021 struct hwrm_func_vf_cfg_output { 1022 __le16 error_code; 1023 __le16 req_type; 1024 __le16 seq_id; 1025 __le16 resp_len; 1026 u8 unused_0[7]; 1027 u8 valid; 1028 }; 1029 1030 /* hwrm_func_qcaps_input (size:192b/24B) */ 1031 struct hwrm_func_qcaps_input { 1032 __le16 req_type; 1033 __le16 cmpl_ring; 1034 __le16 seq_id; 1035 __le16 target_id; 1036 __le64 resp_addr; 1037 __le16 fid; 1038 u8 unused_0[6]; 1039 }; 1040 1041 /* hwrm_func_qcaps_output (size:640b/80B) */ 1042 struct hwrm_func_qcaps_output { 1043 __le16 error_code; 1044 __le16 req_type; 1045 __le16 seq_id; 1046 __le16 resp_len; 1047 __le16 fid; 1048 __le16 port_id; 1049 __le32 flags; 1050 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1051 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1052 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1053 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1054 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1055 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1056 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1057 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1058 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1059 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1060 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1061 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1062 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1063 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1064 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1065 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1066 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1067 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1068 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1069 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1070 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1071 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1072 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1073 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1074 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1075 u8 mac_address[6]; 1076 __le16 max_rsscos_ctx; 1077 __le16 max_cmpl_rings; 1078 __le16 max_tx_rings; 1079 __le16 max_rx_rings; 1080 __le16 max_l2_ctxs; 1081 __le16 max_vnics; 1082 __le16 first_vf_id; 1083 __le16 max_vfs; 1084 __le16 max_stat_ctx; 1085 __le32 max_encap_records; 1086 __le32 max_decap_records; 1087 __le32 max_tx_em_flows; 1088 __le32 max_tx_wm_flows; 1089 __le32 max_rx_em_flows; 1090 __le32 max_rx_wm_flows; 1091 __le32 max_mcast_filters; 1092 __le32 max_flow_id; 1093 __le32 max_hw_ring_grps; 1094 __le16 max_sp_tx_rings; 1095 u8 unused_0; 1096 u8 valid; 1097 }; 1098 1099 /* hwrm_func_qcfg_input (size:192b/24B) */ 1100 struct hwrm_func_qcfg_input { 1101 __le16 req_type; 1102 __le16 cmpl_ring; 1103 __le16 seq_id; 1104 __le16 target_id; 1105 __le64 resp_addr; 1106 __le16 fid; 1107 u8 unused_0[6]; 1108 }; 1109 1110 /* hwrm_func_qcfg_output (size:704b/88B) */ 1111 struct hwrm_func_qcfg_output { 1112 __le16 error_code; 1113 __le16 req_type; 1114 __le16 seq_id; 1115 __le16 resp_len; 1116 __le16 fid; 1117 __le16 port_id; 1118 __le16 vlan; 1119 __le16 flags; 1120 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1121 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1122 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1123 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1124 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1125 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1126 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1127 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1128 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1129 u8 mac_address[6]; 1130 __le16 pci_id; 1131 __le16 alloc_rsscos_ctx; 1132 __le16 alloc_cmpl_rings; 1133 __le16 alloc_tx_rings; 1134 __le16 alloc_rx_rings; 1135 __le16 alloc_l2_ctx; 1136 __le16 alloc_vnics; 1137 __le16 mtu; 1138 __le16 mru; 1139 __le16 stat_ctx_id; 1140 u8 port_partition_type; 1141 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1142 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1143 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1144 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1145 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1146 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1147 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1148 u8 port_pf_cnt; 1149 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1150 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1151 __le16 dflt_vnic_id; 1152 __le16 max_mtu_configured; 1153 __le32 min_bw; 1154 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1155 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1156 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1157 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1158 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1159 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1160 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1161 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1162 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1163 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1164 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1165 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1166 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1167 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1168 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1169 __le32 max_bw; 1170 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1171 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1172 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1173 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1174 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1175 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1176 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1177 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1178 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1179 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1180 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1181 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1182 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1183 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1184 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1185 u8 evb_mode; 1186 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1187 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1188 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1189 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1190 u8 options; 1191 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1192 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1193 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1194 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1195 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1196 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1197 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1198 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1199 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1200 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1201 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1202 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1203 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1204 __le16 alloc_vfs; 1205 __le32 alloc_mcast_filters; 1206 __le32 alloc_hw_ring_grps; 1207 __le16 alloc_sp_tx_rings; 1208 __le16 alloc_stat_ctx; 1209 __le16 alloc_msix; 1210 __le16 registered_vfs; 1211 u8 unused_1[3]; 1212 u8 always_1; 1213 __le32 reset_addr_poll; 1214 u8 unused_2[3]; 1215 u8 valid; 1216 }; 1217 1218 /* hwrm_func_cfg_input (size:704b/88B) */ 1219 struct hwrm_func_cfg_input { 1220 __le16 req_type; 1221 __le16 cmpl_ring; 1222 __le16 seq_id; 1223 __le16 target_id; 1224 __le64 resp_addr; 1225 __le16 fid; 1226 __le16 num_msix; 1227 __le32 flags; 1228 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1229 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1230 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1231 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1232 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1233 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1234 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1235 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1236 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1237 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1238 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1239 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1240 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1241 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1242 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1243 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1244 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1245 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1246 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1247 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1248 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1249 __le32 enables; 1250 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1251 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1252 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1253 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1254 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1255 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1256 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1257 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1258 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1259 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1260 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1261 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1262 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1263 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1264 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1265 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1266 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1267 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1268 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1269 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1270 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1271 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1272 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1273 __le16 mtu; 1274 __le16 mru; 1275 __le16 num_rsscos_ctxs; 1276 __le16 num_cmpl_rings; 1277 __le16 num_tx_rings; 1278 __le16 num_rx_rings; 1279 __le16 num_l2_ctxs; 1280 __le16 num_vnics; 1281 __le16 num_stat_ctxs; 1282 __le16 num_hw_ring_grps; 1283 u8 dflt_mac_addr[6]; 1284 __le16 dflt_vlan; 1285 __be32 dflt_ip_addr[4]; 1286 __le32 min_bw; 1287 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1288 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1289 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1290 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1291 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1292 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1293 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1294 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1295 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1296 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1297 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1298 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1299 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1300 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1301 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1302 __le32 max_bw; 1303 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1304 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1305 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1306 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1307 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1308 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1309 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1310 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1311 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1312 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1313 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1314 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1315 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1316 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1317 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1318 __le16 async_event_cr; 1319 u8 vlan_antispoof_mode; 1320 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1321 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1322 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1323 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1324 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1325 u8 allowed_vlan_pris; 1326 u8 evb_mode; 1327 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1328 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1329 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1330 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1331 u8 options; 1332 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1333 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1334 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1335 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1336 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1337 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1338 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1339 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1340 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1341 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1342 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1343 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1344 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1345 __le16 num_mcast_filters; 1346 }; 1347 1348 /* hwrm_func_cfg_output (size:128b/16B) */ 1349 struct hwrm_func_cfg_output { 1350 __le16 error_code; 1351 __le16 req_type; 1352 __le16 seq_id; 1353 __le16 resp_len; 1354 u8 unused_0[7]; 1355 u8 valid; 1356 }; 1357 1358 /* hwrm_func_qstats_input (size:192b/24B) */ 1359 struct hwrm_func_qstats_input { 1360 __le16 req_type; 1361 __le16 cmpl_ring; 1362 __le16 seq_id; 1363 __le16 target_id; 1364 __le64 resp_addr; 1365 __le16 fid; 1366 u8 unused_0[6]; 1367 }; 1368 1369 /* hwrm_func_qstats_output (size:1408b/176B) */ 1370 struct hwrm_func_qstats_output { 1371 __le16 error_code; 1372 __le16 req_type; 1373 __le16 seq_id; 1374 __le16 resp_len; 1375 __le64 tx_ucast_pkts; 1376 __le64 tx_mcast_pkts; 1377 __le64 tx_bcast_pkts; 1378 __le64 tx_discard_pkts; 1379 __le64 tx_drop_pkts; 1380 __le64 tx_ucast_bytes; 1381 __le64 tx_mcast_bytes; 1382 __le64 tx_bcast_bytes; 1383 __le64 rx_ucast_pkts; 1384 __le64 rx_mcast_pkts; 1385 __le64 rx_bcast_pkts; 1386 __le64 rx_discard_pkts; 1387 __le64 rx_drop_pkts; 1388 __le64 rx_ucast_bytes; 1389 __le64 rx_mcast_bytes; 1390 __le64 rx_bcast_bytes; 1391 __le64 rx_agg_pkts; 1392 __le64 rx_agg_bytes; 1393 __le64 rx_agg_events; 1394 __le64 rx_agg_aborts; 1395 u8 unused_0[7]; 1396 u8 valid; 1397 }; 1398 1399 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1400 struct hwrm_func_clr_stats_input { 1401 __le16 req_type; 1402 __le16 cmpl_ring; 1403 __le16 seq_id; 1404 __le16 target_id; 1405 __le64 resp_addr; 1406 __le16 fid; 1407 u8 unused_0[6]; 1408 }; 1409 1410 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1411 struct hwrm_func_clr_stats_output { 1412 __le16 error_code; 1413 __le16 req_type; 1414 __le16 seq_id; 1415 __le16 resp_len; 1416 u8 unused_0[7]; 1417 u8 valid; 1418 }; 1419 1420 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1421 struct hwrm_func_vf_resc_free_input { 1422 __le16 req_type; 1423 __le16 cmpl_ring; 1424 __le16 seq_id; 1425 __le16 target_id; 1426 __le64 resp_addr; 1427 __le16 vf_id; 1428 u8 unused_0[6]; 1429 }; 1430 1431 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1432 struct hwrm_func_vf_resc_free_output { 1433 __le16 error_code; 1434 __le16 req_type; 1435 __le16 seq_id; 1436 __le16 resp_len; 1437 u8 unused_0[7]; 1438 u8 valid; 1439 }; 1440 1441 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1442 struct hwrm_func_drv_rgtr_input { 1443 __le16 req_type; 1444 __le16 cmpl_ring; 1445 __le16 seq_id; 1446 __le16 target_id; 1447 __le64 resp_addr; 1448 __le32 flags; 1449 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1450 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1451 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1452 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1453 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1454 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1455 __le32 enables; 1456 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1457 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1458 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1459 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1460 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1461 __le16 os_type; 1462 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1463 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1464 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1465 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1466 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1467 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1468 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1469 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1470 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1471 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1472 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1473 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1474 u8 ver_maj_8b; 1475 u8 ver_min_8b; 1476 u8 ver_upd_8b; 1477 u8 unused_0[3]; 1478 __le32 timestamp; 1479 u8 unused_1[4]; 1480 __le32 vf_req_fwd[8]; 1481 __le32 async_event_fwd[8]; 1482 __le16 ver_maj; 1483 __le16 ver_min; 1484 __le16 ver_upd; 1485 __le16 ver_patch; 1486 }; 1487 1488 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1489 struct hwrm_func_drv_rgtr_output { 1490 __le16 error_code; 1491 __le16 req_type; 1492 __le16 seq_id; 1493 __le16 resp_len; 1494 __le32 flags; 1495 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1496 u8 unused_0[3]; 1497 u8 valid; 1498 }; 1499 1500 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1501 struct hwrm_func_drv_unrgtr_input { 1502 __le16 req_type; 1503 __le16 cmpl_ring; 1504 __le16 seq_id; 1505 __le16 target_id; 1506 __le64 resp_addr; 1507 __le32 flags; 1508 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1509 u8 unused_0[4]; 1510 }; 1511 1512 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1513 struct hwrm_func_drv_unrgtr_output { 1514 __le16 error_code; 1515 __le16 req_type; 1516 __le16 seq_id; 1517 __le16 resp_len; 1518 u8 unused_0[7]; 1519 u8 valid; 1520 }; 1521 1522 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1523 struct hwrm_func_buf_rgtr_input { 1524 __le16 req_type; 1525 __le16 cmpl_ring; 1526 __le16 seq_id; 1527 __le16 target_id; 1528 __le64 resp_addr; 1529 __le32 enables; 1530 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1531 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1532 __le16 vf_id; 1533 __le16 req_buf_num_pages; 1534 __le16 req_buf_page_size; 1535 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1536 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1537 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1538 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1539 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1540 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1541 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1542 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1543 __le16 req_buf_len; 1544 __le16 resp_buf_len; 1545 u8 unused_0[2]; 1546 __le64 req_buf_page_addr0; 1547 __le64 req_buf_page_addr1; 1548 __le64 req_buf_page_addr2; 1549 __le64 req_buf_page_addr3; 1550 __le64 req_buf_page_addr4; 1551 __le64 req_buf_page_addr5; 1552 __le64 req_buf_page_addr6; 1553 __le64 req_buf_page_addr7; 1554 __le64 req_buf_page_addr8; 1555 __le64 req_buf_page_addr9; 1556 __le64 error_buf_addr; 1557 __le64 resp_buf_addr; 1558 }; 1559 1560 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1561 struct hwrm_func_buf_rgtr_output { 1562 __le16 error_code; 1563 __le16 req_type; 1564 __le16 seq_id; 1565 __le16 resp_len; 1566 u8 unused_0[7]; 1567 u8 valid; 1568 }; 1569 1570 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1571 struct hwrm_func_drv_qver_input { 1572 __le16 req_type; 1573 __le16 cmpl_ring; 1574 __le16 seq_id; 1575 __le16 target_id; 1576 __le64 resp_addr; 1577 __le32 reserved; 1578 __le16 fid; 1579 u8 unused_0[2]; 1580 }; 1581 1582 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1583 struct hwrm_func_drv_qver_output { 1584 __le16 error_code; 1585 __le16 req_type; 1586 __le16 seq_id; 1587 __le16 resp_len; 1588 __le16 os_type; 1589 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1590 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1591 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1592 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1593 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1594 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1595 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1596 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1597 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1598 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1599 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1600 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1601 u8 ver_maj_8b; 1602 u8 ver_min_8b; 1603 u8 ver_upd_8b; 1604 u8 unused_0[3]; 1605 __le16 ver_maj; 1606 __le16 ver_min; 1607 __le16 ver_upd; 1608 __le16 ver_patch; 1609 u8 unused_1[7]; 1610 u8 valid; 1611 }; 1612 1613 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1614 struct hwrm_func_resource_qcaps_input { 1615 __le16 req_type; 1616 __le16 cmpl_ring; 1617 __le16 seq_id; 1618 __le16 target_id; 1619 __le64 resp_addr; 1620 __le16 fid; 1621 u8 unused_0[6]; 1622 }; 1623 1624 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1625 struct hwrm_func_resource_qcaps_output { 1626 __le16 error_code; 1627 __le16 req_type; 1628 __le16 seq_id; 1629 __le16 resp_len; 1630 __le16 max_vfs; 1631 __le16 max_msix; 1632 __le16 vf_reservation_strategy; 1633 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1634 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1635 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1636 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1637 __le16 min_rsscos_ctx; 1638 __le16 max_rsscos_ctx; 1639 __le16 min_cmpl_rings; 1640 __le16 max_cmpl_rings; 1641 __le16 min_tx_rings; 1642 __le16 max_tx_rings; 1643 __le16 min_rx_rings; 1644 __le16 max_rx_rings; 1645 __le16 min_l2_ctxs; 1646 __le16 max_l2_ctxs; 1647 __le16 min_vnics; 1648 __le16 max_vnics; 1649 __le16 min_stat_ctx; 1650 __le16 max_stat_ctx; 1651 __le16 min_hw_ring_grps; 1652 __le16 max_hw_ring_grps; 1653 __le16 max_tx_scheduler_inputs; 1654 __le16 flags; 1655 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1656 u8 unused_0[5]; 1657 u8 valid; 1658 }; 1659 1660 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1661 struct hwrm_func_vf_resource_cfg_input { 1662 __le16 req_type; 1663 __le16 cmpl_ring; 1664 __le16 seq_id; 1665 __le16 target_id; 1666 __le64 resp_addr; 1667 __le16 vf_id; 1668 __le16 max_msix; 1669 __le16 min_rsscos_ctx; 1670 __le16 max_rsscos_ctx; 1671 __le16 min_cmpl_rings; 1672 __le16 max_cmpl_rings; 1673 __le16 min_tx_rings; 1674 __le16 max_tx_rings; 1675 __le16 min_rx_rings; 1676 __le16 max_rx_rings; 1677 __le16 min_l2_ctxs; 1678 __le16 max_l2_ctxs; 1679 __le16 min_vnics; 1680 __le16 max_vnics; 1681 __le16 min_stat_ctx; 1682 __le16 max_stat_ctx; 1683 __le16 min_hw_ring_grps; 1684 __le16 max_hw_ring_grps; 1685 __le16 flags; 1686 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1687 u8 unused_0[2]; 1688 }; 1689 1690 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1691 struct hwrm_func_vf_resource_cfg_output { 1692 __le16 error_code; 1693 __le16 req_type; 1694 __le16 seq_id; 1695 __le16 resp_len; 1696 __le16 reserved_rsscos_ctx; 1697 __le16 reserved_cmpl_rings; 1698 __le16 reserved_tx_rings; 1699 __le16 reserved_rx_rings; 1700 __le16 reserved_l2_ctxs; 1701 __le16 reserved_vnics; 1702 __le16 reserved_stat_ctx; 1703 __le16 reserved_hw_ring_grps; 1704 u8 unused_0[7]; 1705 u8 valid; 1706 }; 1707 1708 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1709 struct hwrm_func_backing_store_qcaps_input { 1710 __le16 req_type; 1711 __le16 cmpl_ring; 1712 __le16 seq_id; 1713 __le16 target_id; 1714 __le64 resp_addr; 1715 }; 1716 1717 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ 1718 struct hwrm_func_backing_store_qcaps_output { 1719 __le16 error_code; 1720 __le16 req_type; 1721 __le16 seq_id; 1722 __le16 resp_len; 1723 __le32 qp_max_entries; 1724 __le16 qp_min_qp1_entries; 1725 __le16 qp_max_l2_entries; 1726 __le16 qp_entry_size; 1727 __le16 srq_max_l2_entries; 1728 __le32 srq_max_entries; 1729 __le16 srq_entry_size; 1730 __le16 cq_max_l2_entries; 1731 __le32 cq_max_entries; 1732 __le16 cq_entry_size; 1733 __le16 vnic_max_vnic_entries; 1734 __le16 vnic_max_ring_table_entries; 1735 __le16 vnic_entry_size; 1736 __le32 stat_max_entries; 1737 __le16 stat_entry_size; 1738 __le16 tqm_entry_size; 1739 __le32 tqm_min_entries_per_ring; 1740 __le32 tqm_max_entries_per_ring; 1741 __le32 mrav_max_entries; 1742 __le16 mrav_entry_size; 1743 __le16 tim_entry_size; 1744 __le32 tim_max_entries; 1745 __le16 mrav_num_entries_units; 1746 u8 tqm_entries_multiple; 1747 u8 valid; 1748 }; 1749 1750 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1751 struct hwrm_func_backing_store_cfg_input { 1752 __le16 req_type; 1753 __le16 cmpl_ring; 1754 __le16 seq_id; 1755 __le16 target_id; 1756 __le64 resp_addr; 1757 __le32 flags; 1758 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1759 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 1760 __le32 enables; 1761 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1762 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1763 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1764 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1765 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1766 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1767 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1768 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1769 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1770 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1771 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1772 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1773 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1774 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1775 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1776 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1777 u8 qpc_pg_size_qpc_lvl; 1778 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1779 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1780 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1781 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1782 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1783 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1784 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1785 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1786 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1787 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1788 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1789 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1790 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1791 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1792 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1793 u8 srq_pg_size_srq_lvl; 1794 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1795 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1796 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1797 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1798 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1799 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1800 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 1801 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 1802 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1803 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1804 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1805 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1806 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1807 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1808 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 1809 u8 cq_pg_size_cq_lvl; 1810 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 1811 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 1812 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 1813 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 1814 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 1815 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 1816 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 1817 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 1818 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1819 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1820 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1821 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1822 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1823 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1824 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 1825 u8 vnic_pg_size_vnic_lvl; 1826 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 1827 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 1828 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 1829 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 1830 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 1831 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 1832 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 1833 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 1834 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 1835 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 1836 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 1837 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 1838 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 1839 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 1840 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 1841 u8 stat_pg_size_stat_lvl; 1842 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 1843 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 1844 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 1845 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 1846 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 1847 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 1848 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 1849 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 1850 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 1851 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 1852 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 1853 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 1854 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 1855 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 1856 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 1857 u8 tqm_sp_pg_size_tqm_sp_lvl; 1858 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 1859 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 1860 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 1861 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 1862 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 1863 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 1864 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 1865 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 1866 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 1867 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 1868 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 1869 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 1870 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 1871 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 1872 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 1873 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 1874 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 1875 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 1876 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 1877 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 1878 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 1879 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 1880 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 1881 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 1882 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 1883 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 1884 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 1885 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 1886 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 1887 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 1888 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 1889 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 1890 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 1891 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 1892 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 1893 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 1894 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 1895 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 1896 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 1897 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 1898 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 1899 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 1900 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 1901 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 1902 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 1903 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 1904 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 1905 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 1906 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 1907 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 1908 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 1909 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 1910 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 1911 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 1912 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 1913 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 1914 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 1915 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 1916 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 1917 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 1918 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 1919 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 1920 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 1921 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 1922 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 1923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 1924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 1925 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 1926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 1927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 1928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 1929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 1930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 1931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 1932 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 1933 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 1934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 1935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 1936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 1937 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 1938 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 1939 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 1940 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 1941 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 1942 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 1943 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 1944 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 1945 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 1946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 1947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 1948 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 1949 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 1950 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 1951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 1952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 1953 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 1954 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 1955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 1956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 1957 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 1958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 1959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 1960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 1961 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 1962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 1963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 1964 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 1965 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 1966 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 1967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 1968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 1969 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 1970 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 1971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 1972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 1973 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 1974 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 1975 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 1976 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 1977 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 1978 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 1979 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 1980 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 1981 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 1982 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 1983 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 1984 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 1985 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 1986 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 1987 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 1988 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 1989 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 1990 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 1991 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 1992 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 1993 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 1994 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 1995 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 1996 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 1997 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 1998 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 1999 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2000 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2001 u8 mrav_pg_size_mrav_lvl; 2002 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2003 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2004 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2005 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2006 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2007 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2008 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2009 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2010 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2011 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2012 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2013 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2014 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2015 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2016 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2017 u8 tim_pg_size_tim_lvl; 2018 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2019 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2020 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2021 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2022 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2023 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2024 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2025 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2026 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2027 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2028 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2029 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2030 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2031 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2032 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2033 __le64 qpc_page_dir; 2034 __le64 srq_page_dir; 2035 __le64 cq_page_dir; 2036 __le64 vnic_page_dir; 2037 __le64 stat_page_dir; 2038 __le64 tqm_sp_page_dir; 2039 __le64 tqm_ring0_page_dir; 2040 __le64 tqm_ring1_page_dir; 2041 __le64 tqm_ring2_page_dir; 2042 __le64 tqm_ring3_page_dir; 2043 __le64 tqm_ring4_page_dir; 2044 __le64 tqm_ring5_page_dir; 2045 __le64 tqm_ring6_page_dir; 2046 __le64 tqm_ring7_page_dir; 2047 __le64 mrav_page_dir; 2048 __le64 tim_page_dir; 2049 __le32 qp_num_entries; 2050 __le32 srq_num_entries; 2051 __le32 cq_num_entries; 2052 __le32 stat_num_entries; 2053 __le32 tqm_sp_num_entries; 2054 __le32 tqm_ring0_num_entries; 2055 __le32 tqm_ring1_num_entries; 2056 __le32 tqm_ring2_num_entries; 2057 __le32 tqm_ring3_num_entries; 2058 __le32 tqm_ring4_num_entries; 2059 __le32 tqm_ring5_num_entries; 2060 __le32 tqm_ring6_num_entries; 2061 __le32 tqm_ring7_num_entries; 2062 __le32 mrav_num_entries; 2063 __le32 tim_num_entries; 2064 __le16 qp_num_qp1_entries; 2065 __le16 qp_num_l2_entries; 2066 __le16 qp_entry_size; 2067 __le16 srq_num_l2_entries; 2068 __le16 srq_entry_size; 2069 __le16 cq_num_l2_entries; 2070 __le16 cq_entry_size; 2071 __le16 vnic_num_vnic_entries; 2072 __le16 vnic_num_ring_table_entries; 2073 __le16 vnic_entry_size; 2074 __le16 stat_entry_size; 2075 __le16 tqm_entry_size; 2076 __le16 mrav_entry_size; 2077 __le16 tim_entry_size; 2078 }; 2079 2080 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2081 struct hwrm_func_backing_store_cfg_output { 2082 __le16 error_code; 2083 __le16 req_type; 2084 __le16 seq_id; 2085 __le16 resp_len; 2086 u8 unused_0[7]; 2087 u8 valid; 2088 }; 2089 2090 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2091 struct hwrm_error_recovery_qcfg_input { 2092 __le16 req_type; 2093 __le16 cmpl_ring; 2094 __le16 seq_id; 2095 __le16 target_id; 2096 __le64 resp_addr; 2097 u8 unused_0[8]; 2098 }; 2099 2100 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2101 struct hwrm_error_recovery_qcfg_output { 2102 __le16 error_code; 2103 __le16 req_type; 2104 __le16 seq_id; 2105 __le16 resp_len; 2106 __le32 flags; 2107 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2108 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2109 __le32 driver_polling_freq; 2110 __le32 master_func_wait_period; 2111 __le32 normal_func_wait_period; 2112 __le32 master_func_wait_period_after_reset; 2113 __le32 max_bailout_time_after_reset; 2114 __le32 fw_health_status_reg; 2115 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2116 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2117 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2118 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2119 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2120 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2121 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2122 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2123 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2124 __le32 fw_heartbeat_reg; 2125 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2126 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2127 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2128 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2129 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2130 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2131 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2132 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2133 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2134 __le32 fw_reset_cnt_reg; 2135 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2136 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2137 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2138 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2139 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2140 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2141 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2142 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2143 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2144 __le32 reset_inprogress_reg; 2145 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2146 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2147 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2148 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2149 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2150 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2151 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2152 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2153 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2154 __le32 reset_inprogress_reg_mask; 2155 u8 unused_0[3]; 2156 u8 reg_array_cnt; 2157 __le32 reset_reg[16]; 2158 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2159 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2160 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2161 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2162 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2163 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2164 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2165 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2166 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2167 __le32 reset_reg_val[16]; 2168 u8 delay_after_reset[16]; 2169 u8 unused_1[7]; 2170 u8 valid; 2171 }; 2172 2173 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2174 struct hwrm_func_drv_if_change_input { 2175 __le16 req_type; 2176 __le16 cmpl_ring; 2177 __le16 seq_id; 2178 __le16 target_id; 2179 __le64 resp_addr; 2180 __le32 flags; 2181 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2182 __le32 unused; 2183 }; 2184 2185 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2186 struct hwrm_func_drv_if_change_output { 2187 __le16 error_code; 2188 __le16 req_type; 2189 __le16 seq_id; 2190 __le16 resp_len; 2191 __le32 flags; 2192 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2193 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2194 u8 unused_0[3]; 2195 u8 valid; 2196 }; 2197 2198 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2199 struct hwrm_port_phy_cfg_input { 2200 __le16 req_type; 2201 __le16 cmpl_ring; 2202 __le16 seq_id; 2203 __le16 target_id; 2204 __le64 resp_addr; 2205 __le32 flags; 2206 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2207 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2208 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2209 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2210 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2211 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2212 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2213 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2214 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2215 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2216 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2217 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2218 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2219 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2220 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2221 __le32 enables; 2222 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2223 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2224 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2225 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2226 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2227 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2228 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2229 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2230 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2231 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2232 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2233 __le16 port_id; 2234 __le16 force_link_speed; 2235 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2236 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2237 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2238 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2239 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2240 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2241 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2242 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2243 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2244 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2245 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL 2246 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2247 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2248 u8 auto_mode; 2249 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2250 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2251 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2252 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2253 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2254 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2255 u8 auto_duplex; 2256 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2257 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2258 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2259 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2260 u8 auto_pause; 2261 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2262 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2263 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2264 u8 unused_0; 2265 __le16 auto_link_speed; 2266 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2267 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2268 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2269 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2270 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2271 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2272 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2273 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2274 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2275 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2276 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL 2277 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2278 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2279 __le16 auto_link_speed_mask; 2280 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2281 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2282 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2283 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2284 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2285 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2286 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2287 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2288 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2289 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2290 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2291 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2292 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2293 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2294 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2295 u8 wirespeed; 2296 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2297 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2298 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2299 u8 lpbk; 2300 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2301 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2302 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2303 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2304 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2305 u8 force_pause; 2306 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2307 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2308 u8 unused_1; 2309 __le32 preemphasis; 2310 __le16 eee_link_speed_mask; 2311 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2312 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2313 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2314 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2315 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2316 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2317 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2318 u8 unused_2[2]; 2319 __le32 tx_lpi_timer; 2320 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2321 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2322 __le32 unused_3; 2323 }; 2324 2325 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2326 struct hwrm_port_phy_cfg_output { 2327 __le16 error_code; 2328 __le16 req_type; 2329 __le16 seq_id; 2330 __le16 resp_len; 2331 u8 unused_0[7]; 2332 u8 valid; 2333 }; 2334 2335 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2336 struct hwrm_port_phy_cfg_cmd_err { 2337 u8 code; 2338 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2339 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2340 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2341 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2342 u8 unused_0[7]; 2343 }; 2344 2345 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2346 struct hwrm_port_phy_qcfg_input { 2347 __le16 req_type; 2348 __le16 cmpl_ring; 2349 __le16 seq_id; 2350 __le16 target_id; 2351 __le64 resp_addr; 2352 __le16 port_id; 2353 u8 unused_0[6]; 2354 }; 2355 2356 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2357 struct hwrm_port_phy_qcfg_output { 2358 __le16 error_code; 2359 __le16 req_type; 2360 __le16 seq_id; 2361 __le16 resp_len; 2362 u8 link; 2363 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2364 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2365 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2366 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2367 u8 unused_0; 2368 __le16 link_speed; 2369 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2370 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2371 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2372 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2373 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2374 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2375 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2376 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2377 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2378 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2379 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2380 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2381 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2382 u8 duplex_cfg; 2383 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2384 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2385 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2386 u8 pause; 2387 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2388 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2389 __le16 support_speeds; 2390 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2391 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2392 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2393 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2394 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2395 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2396 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2397 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2398 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2399 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2400 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2401 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2402 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2403 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2404 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL 2405 __le16 force_link_speed; 2406 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2407 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2408 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2409 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2410 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2411 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2412 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2413 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2414 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2415 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2416 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL 2417 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2418 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2419 u8 auto_mode; 2420 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2421 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2422 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2423 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2424 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2425 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2426 u8 auto_pause; 2427 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2428 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2429 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2430 __le16 auto_link_speed; 2431 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2432 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2433 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2434 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2435 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2436 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2437 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2438 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2439 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2440 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2441 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL 2442 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2443 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2444 __le16 auto_link_speed_mask; 2445 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2446 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2447 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2448 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2449 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2450 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2451 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2452 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2453 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2454 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2455 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2456 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2457 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2458 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2459 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2460 u8 wirespeed; 2461 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2462 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2463 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2464 u8 lpbk; 2465 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2466 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2467 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2468 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2469 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2470 u8 force_pause; 2471 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2472 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2473 u8 module_status; 2474 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2475 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2476 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2477 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2478 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2479 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2480 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2481 __le32 preemphasis; 2482 u8 phy_maj; 2483 u8 phy_min; 2484 u8 phy_bld; 2485 u8 phy_type; 2486 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2487 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2488 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2489 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2490 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2491 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2492 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2493 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2494 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2495 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2496 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2497 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2498 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2499 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2500 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2501 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2502 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2503 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2504 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2505 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2506 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2507 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2508 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2509 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2510 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2511 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2512 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2513 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2514 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2515 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2516 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2517 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2518 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2519 u8 media_type; 2520 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2521 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2522 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2523 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2524 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2525 u8 xcvr_pkg_type; 2526 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2527 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2528 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2529 u8 eee_config_phy_addr; 2530 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2531 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2532 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2533 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2534 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2535 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2536 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2537 u8 parallel_detect; 2538 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2539 __le16 link_partner_adv_speeds; 2540 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2541 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2542 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2543 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2544 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2545 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2546 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2547 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2548 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2549 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2550 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2551 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2552 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2553 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2554 u8 link_partner_adv_auto_mode; 2555 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2556 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2557 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2558 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2559 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2560 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2561 u8 link_partner_adv_pause; 2562 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2563 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2564 __le16 adv_eee_link_speed_mask; 2565 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2566 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2567 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2568 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2569 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2570 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2571 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2572 __le16 link_partner_adv_eee_link_speed_mask; 2573 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2574 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2575 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2576 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2577 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2578 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2579 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2580 __le32 xcvr_identifier_type_tx_lpi_timer; 2581 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2582 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2583 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2584 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2585 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2586 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2587 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2588 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2589 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2590 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2591 __le16 fec_cfg; 2592 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2593 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2594 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2595 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2596 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2597 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2598 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2599 u8 duplex_state; 2600 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2601 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2602 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2603 u8 option_flags; 2604 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2605 char phy_vendor_name[16]; 2606 char phy_vendor_partnumber[16]; 2607 u8 unused_2[7]; 2608 u8 valid; 2609 }; 2610 2611 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 2612 struct hwrm_port_mac_cfg_input { 2613 __le16 req_type; 2614 __le16 cmpl_ring; 2615 __le16 seq_id; 2616 __le16 target_id; 2617 __le64 resp_addr; 2618 __le32 flags; 2619 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2620 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2621 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2622 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2623 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2624 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2625 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2626 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2627 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2628 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2629 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2630 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2631 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2632 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 2633 __le32 enables; 2634 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2635 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2636 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2637 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2638 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2639 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2640 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2641 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2642 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 2643 __le16 port_id; 2644 u8 ipg; 2645 u8 lpbk; 2646 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2647 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2648 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2649 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2650 u8 vlan_pri2cos_map_pri; 2651 u8 reserved1; 2652 u8 tunnel_pri2cos_map_pri; 2653 u8 dscp2pri_map_pri; 2654 __le16 rx_ts_capture_ptp_msg_type; 2655 __le16 tx_ts_capture_ptp_msg_type; 2656 u8 cos_field_cfg; 2657 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2658 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2659 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2660 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2661 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2662 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2663 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2664 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2665 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2666 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2667 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2668 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2669 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2670 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2671 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2672 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2673 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2674 u8 unused_0[3]; 2675 __s32 ptp_freq_adj_ppb; 2676 u8 unused_1[4]; 2677 }; 2678 2679 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 2680 struct hwrm_port_mac_cfg_output { 2681 __le16 error_code; 2682 __le16 req_type; 2683 __le16 seq_id; 2684 __le16 resp_len; 2685 __le16 mru; 2686 __le16 mtu; 2687 u8 ipg; 2688 u8 lpbk; 2689 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2690 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2691 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2692 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2693 u8 unused_0; 2694 u8 valid; 2695 }; 2696 2697 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2698 struct hwrm_port_mac_ptp_qcfg_input { 2699 __le16 req_type; 2700 __le16 cmpl_ring; 2701 __le16 seq_id; 2702 __le16 target_id; 2703 __le64 resp_addr; 2704 __le16 port_id; 2705 u8 unused_0[6]; 2706 }; 2707 2708 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2709 struct hwrm_port_mac_ptp_qcfg_output { 2710 __le16 error_code; 2711 __le16 req_type; 2712 __le16 seq_id; 2713 __le16 resp_len; 2714 u8 flags; 2715 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2716 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 2717 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 2718 u8 unused_0[3]; 2719 __le32 rx_ts_reg_off_lower; 2720 __le32 rx_ts_reg_off_upper; 2721 __le32 rx_ts_reg_off_seq_id; 2722 __le32 rx_ts_reg_off_src_id_0; 2723 __le32 rx_ts_reg_off_src_id_1; 2724 __le32 rx_ts_reg_off_src_id_2; 2725 __le32 rx_ts_reg_off_domain_id; 2726 __le32 rx_ts_reg_off_fifo; 2727 __le32 rx_ts_reg_off_fifo_adv; 2728 __le32 rx_ts_reg_off_granularity; 2729 __le32 tx_ts_reg_off_lower; 2730 __le32 tx_ts_reg_off_upper; 2731 __le32 tx_ts_reg_off_seq_id; 2732 __le32 tx_ts_reg_off_fifo; 2733 __le32 tx_ts_reg_off_granularity; 2734 u8 unused_1[7]; 2735 u8 valid; 2736 }; 2737 2738 /* tx_port_stats (size:3264b/408B) */ 2739 struct tx_port_stats { 2740 __le64 tx_64b_frames; 2741 __le64 tx_65b_127b_frames; 2742 __le64 tx_128b_255b_frames; 2743 __le64 tx_256b_511b_frames; 2744 __le64 tx_512b_1023b_frames; 2745 __le64 tx_1024b_1518b_frames; 2746 __le64 tx_good_vlan_frames; 2747 __le64 tx_1519b_2047b_frames; 2748 __le64 tx_2048b_4095b_frames; 2749 __le64 tx_4096b_9216b_frames; 2750 __le64 tx_9217b_16383b_frames; 2751 __le64 tx_good_frames; 2752 __le64 tx_total_frames; 2753 __le64 tx_ucast_frames; 2754 __le64 tx_mcast_frames; 2755 __le64 tx_bcast_frames; 2756 __le64 tx_pause_frames; 2757 __le64 tx_pfc_frames; 2758 __le64 tx_jabber_frames; 2759 __le64 tx_fcs_err_frames; 2760 __le64 tx_control_frames; 2761 __le64 tx_oversz_frames; 2762 __le64 tx_single_dfrl_frames; 2763 __le64 tx_multi_dfrl_frames; 2764 __le64 tx_single_coll_frames; 2765 __le64 tx_multi_coll_frames; 2766 __le64 tx_late_coll_frames; 2767 __le64 tx_excessive_coll_frames; 2768 __le64 tx_frag_frames; 2769 __le64 tx_err; 2770 __le64 tx_tagged_frames; 2771 __le64 tx_dbl_tagged_frames; 2772 __le64 tx_runt_frames; 2773 __le64 tx_fifo_underruns; 2774 __le64 tx_pfc_ena_frames_pri0; 2775 __le64 tx_pfc_ena_frames_pri1; 2776 __le64 tx_pfc_ena_frames_pri2; 2777 __le64 tx_pfc_ena_frames_pri3; 2778 __le64 tx_pfc_ena_frames_pri4; 2779 __le64 tx_pfc_ena_frames_pri5; 2780 __le64 tx_pfc_ena_frames_pri6; 2781 __le64 tx_pfc_ena_frames_pri7; 2782 __le64 tx_eee_lpi_events; 2783 __le64 tx_eee_lpi_duration; 2784 __le64 tx_llfc_logical_msgs; 2785 __le64 tx_hcfc_msgs; 2786 __le64 tx_total_collisions; 2787 __le64 tx_bytes; 2788 __le64 tx_xthol_frames; 2789 __le64 tx_stat_discard; 2790 __le64 tx_stat_error; 2791 }; 2792 2793 /* rx_port_stats (size:4224b/528B) */ 2794 struct rx_port_stats { 2795 __le64 rx_64b_frames; 2796 __le64 rx_65b_127b_frames; 2797 __le64 rx_128b_255b_frames; 2798 __le64 rx_256b_511b_frames; 2799 __le64 rx_512b_1023b_frames; 2800 __le64 rx_1024b_1518b_frames; 2801 __le64 rx_good_vlan_frames; 2802 __le64 rx_1519b_2047b_frames; 2803 __le64 rx_2048b_4095b_frames; 2804 __le64 rx_4096b_9216b_frames; 2805 __le64 rx_9217b_16383b_frames; 2806 __le64 rx_total_frames; 2807 __le64 rx_ucast_frames; 2808 __le64 rx_mcast_frames; 2809 __le64 rx_bcast_frames; 2810 __le64 rx_fcs_err_frames; 2811 __le64 rx_ctrl_frames; 2812 __le64 rx_pause_frames; 2813 __le64 rx_pfc_frames; 2814 __le64 rx_unsupported_opcode_frames; 2815 __le64 rx_unsupported_da_pausepfc_frames; 2816 __le64 rx_wrong_sa_frames; 2817 __le64 rx_align_err_frames; 2818 __le64 rx_oor_len_frames; 2819 __le64 rx_code_err_frames; 2820 __le64 rx_false_carrier_frames; 2821 __le64 rx_ovrsz_frames; 2822 __le64 rx_jbr_frames; 2823 __le64 rx_mtu_err_frames; 2824 __le64 rx_match_crc_frames; 2825 __le64 rx_promiscuous_frames; 2826 __le64 rx_tagged_frames; 2827 __le64 rx_double_tagged_frames; 2828 __le64 rx_trunc_frames; 2829 __le64 rx_good_frames; 2830 __le64 rx_pfc_xon2xoff_frames_pri0; 2831 __le64 rx_pfc_xon2xoff_frames_pri1; 2832 __le64 rx_pfc_xon2xoff_frames_pri2; 2833 __le64 rx_pfc_xon2xoff_frames_pri3; 2834 __le64 rx_pfc_xon2xoff_frames_pri4; 2835 __le64 rx_pfc_xon2xoff_frames_pri5; 2836 __le64 rx_pfc_xon2xoff_frames_pri6; 2837 __le64 rx_pfc_xon2xoff_frames_pri7; 2838 __le64 rx_pfc_ena_frames_pri0; 2839 __le64 rx_pfc_ena_frames_pri1; 2840 __le64 rx_pfc_ena_frames_pri2; 2841 __le64 rx_pfc_ena_frames_pri3; 2842 __le64 rx_pfc_ena_frames_pri4; 2843 __le64 rx_pfc_ena_frames_pri5; 2844 __le64 rx_pfc_ena_frames_pri6; 2845 __le64 rx_pfc_ena_frames_pri7; 2846 __le64 rx_sch_crc_err_frames; 2847 __le64 rx_undrsz_frames; 2848 __le64 rx_frag_frames; 2849 __le64 rx_eee_lpi_events; 2850 __le64 rx_eee_lpi_duration; 2851 __le64 rx_llfc_physical_msgs; 2852 __le64 rx_llfc_logical_msgs; 2853 __le64 rx_llfc_msgs_with_crc_err; 2854 __le64 rx_hcfc_msgs; 2855 __le64 rx_hcfc_msgs_with_crc_err; 2856 __le64 rx_bytes; 2857 __le64 rx_runt_bytes; 2858 __le64 rx_runt_frames; 2859 __le64 rx_stat_discard; 2860 __le64 rx_stat_err; 2861 }; 2862 2863 /* hwrm_port_qstats_input (size:320b/40B) */ 2864 struct hwrm_port_qstats_input { 2865 __le16 req_type; 2866 __le16 cmpl_ring; 2867 __le16 seq_id; 2868 __le16 target_id; 2869 __le64 resp_addr; 2870 __le16 port_id; 2871 u8 unused_0[6]; 2872 __le64 tx_stat_host_addr; 2873 __le64 rx_stat_host_addr; 2874 }; 2875 2876 /* hwrm_port_qstats_output (size:128b/16B) */ 2877 struct hwrm_port_qstats_output { 2878 __le16 error_code; 2879 __le16 req_type; 2880 __le16 seq_id; 2881 __le16 resp_len; 2882 __le16 tx_stat_size; 2883 __le16 rx_stat_size; 2884 u8 unused_0[3]; 2885 u8 valid; 2886 }; 2887 2888 /* tx_port_stats_ext (size:2048b/256B) */ 2889 struct tx_port_stats_ext { 2890 __le64 tx_bytes_cos0; 2891 __le64 tx_bytes_cos1; 2892 __le64 tx_bytes_cos2; 2893 __le64 tx_bytes_cos3; 2894 __le64 tx_bytes_cos4; 2895 __le64 tx_bytes_cos5; 2896 __le64 tx_bytes_cos6; 2897 __le64 tx_bytes_cos7; 2898 __le64 tx_packets_cos0; 2899 __le64 tx_packets_cos1; 2900 __le64 tx_packets_cos2; 2901 __le64 tx_packets_cos3; 2902 __le64 tx_packets_cos4; 2903 __le64 tx_packets_cos5; 2904 __le64 tx_packets_cos6; 2905 __le64 tx_packets_cos7; 2906 __le64 pfc_pri0_tx_duration_us; 2907 __le64 pfc_pri0_tx_transitions; 2908 __le64 pfc_pri1_tx_duration_us; 2909 __le64 pfc_pri1_tx_transitions; 2910 __le64 pfc_pri2_tx_duration_us; 2911 __le64 pfc_pri2_tx_transitions; 2912 __le64 pfc_pri3_tx_duration_us; 2913 __le64 pfc_pri3_tx_transitions; 2914 __le64 pfc_pri4_tx_duration_us; 2915 __le64 pfc_pri4_tx_transitions; 2916 __le64 pfc_pri5_tx_duration_us; 2917 __le64 pfc_pri5_tx_transitions; 2918 __le64 pfc_pri6_tx_duration_us; 2919 __le64 pfc_pri6_tx_transitions; 2920 __le64 pfc_pri7_tx_duration_us; 2921 __le64 pfc_pri7_tx_transitions; 2922 }; 2923 2924 /* rx_port_stats_ext (size:3648b/456B) */ 2925 struct rx_port_stats_ext { 2926 __le64 link_down_events; 2927 __le64 continuous_pause_events; 2928 __le64 resume_pause_events; 2929 __le64 continuous_roce_pause_events; 2930 __le64 resume_roce_pause_events; 2931 __le64 rx_bytes_cos0; 2932 __le64 rx_bytes_cos1; 2933 __le64 rx_bytes_cos2; 2934 __le64 rx_bytes_cos3; 2935 __le64 rx_bytes_cos4; 2936 __le64 rx_bytes_cos5; 2937 __le64 rx_bytes_cos6; 2938 __le64 rx_bytes_cos7; 2939 __le64 rx_packets_cos0; 2940 __le64 rx_packets_cos1; 2941 __le64 rx_packets_cos2; 2942 __le64 rx_packets_cos3; 2943 __le64 rx_packets_cos4; 2944 __le64 rx_packets_cos5; 2945 __le64 rx_packets_cos6; 2946 __le64 rx_packets_cos7; 2947 __le64 pfc_pri0_rx_duration_us; 2948 __le64 pfc_pri0_rx_transitions; 2949 __le64 pfc_pri1_rx_duration_us; 2950 __le64 pfc_pri1_rx_transitions; 2951 __le64 pfc_pri2_rx_duration_us; 2952 __le64 pfc_pri2_rx_transitions; 2953 __le64 pfc_pri3_rx_duration_us; 2954 __le64 pfc_pri3_rx_transitions; 2955 __le64 pfc_pri4_rx_duration_us; 2956 __le64 pfc_pri4_rx_transitions; 2957 __le64 pfc_pri5_rx_duration_us; 2958 __le64 pfc_pri5_rx_transitions; 2959 __le64 pfc_pri6_rx_duration_us; 2960 __le64 pfc_pri6_rx_transitions; 2961 __le64 pfc_pri7_rx_duration_us; 2962 __le64 pfc_pri7_rx_transitions; 2963 __le64 rx_bits; 2964 __le64 rx_buffer_passed_threshold; 2965 __le64 rx_pcs_symbol_err; 2966 __le64 rx_corrected_bits; 2967 __le64 rx_discard_bytes_cos0; 2968 __le64 rx_discard_bytes_cos1; 2969 __le64 rx_discard_bytes_cos2; 2970 __le64 rx_discard_bytes_cos3; 2971 __le64 rx_discard_bytes_cos4; 2972 __le64 rx_discard_bytes_cos5; 2973 __le64 rx_discard_bytes_cos6; 2974 __le64 rx_discard_bytes_cos7; 2975 __le64 rx_discard_packets_cos0; 2976 __le64 rx_discard_packets_cos1; 2977 __le64 rx_discard_packets_cos2; 2978 __le64 rx_discard_packets_cos3; 2979 __le64 rx_discard_packets_cos4; 2980 __le64 rx_discard_packets_cos5; 2981 __le64 rx_discard_packets_cos6; 2982 __le64 rx_discard_packets_cos7; 2983 }; 2984 2985 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 2986 struct hwrm_port_qstats_ext_input { 2987 __le16 req_type; 2988 __le16 cmpl_ring; 2989 __le16 seq_id; 2990 __le16 target_id; 2991 __le64 resp_addr; 2992 __le16 port_id; 2993 __le16 tx_stat_size; 2994 __le16 rx_stat_size; 2995 u8 unused_0[2]; 2996 __le64 tx_stat_host_addr; 2997 __le64 rx_stat_host_addr; 2998 }; 2999 3000 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3001 struct hwrm_port_qstats_ext_output { 3002 __le16 error_code; 3003 __le16 req_type; 3004 __le16 seq_id; 3005 __le16 resp_len; 3006 __le16 tx_stat_size; 3007 __le16 rx_stat_size; 3008 __le16 total_active_cos_queues; 3009 u8 flags; 3010 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3011 u8 valid; 3012 }; 3013 3014 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3015 struct hwrm_port_lpbk_qstats_input { 3016 __le16 req_type; 3017 __le16 cmpl_ring; 3018 __le16 seq_id; 3019 __le16 target_id; 3020 __le64 resp_addr; 3021 }; 3022 3023 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3024 struct hwrm_port_lpbk_qstats_output { 3025 __le16 error_code; 3026 __le16 req_type; 3027 __le16 seq_id; 3028 __le16 resp_len; 3029 __le64 lpbk_ucast_frames; 3030 __le64 lpbk_mcast_frames; 3031 __le64 lpbk_bcast_frames; 3032 __le64 lpbk_ucast_bytes; 3033 __le64 lpbk_mcast_bytes; 3034 __le64 lpbk_bcast_bytes; 3035 __le64 tx_stat_discard; 3036 __le64 tx_stat_error; 3037 __le64 rx_stat_discard; 3038 __le64 rx_stat_error; 3039 u8 unused_0[7]; 3040 u8 valid; 3041 }; 3042 3043 /* hwrm_port_clr_stats_input (size:192b/24B) */ 3044 struct hwrm_port_clr_stats_input { 3045 __le16 req_type; 3046 __le16 cmpl_ring; 3047 __le16 seq_id; 3048 __le16 target_id; 3049 __le64 resp_addr; 3050 __le16 port_id; 3051 u8 flags; 3052 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3053 u8 unused_0[5]; 3054 }; 3055 3056 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3057 struct hwrm_port_clr_stats_output { 3058 __le16 error_code; 3059 __le16 req_type; 3060 __le16 seq_id; 3061 __le16 resp_len; 3062 u8 unused_0[7]; 3063 u8 valid; 3064 }; 3065 3066 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3067 struct hwrm_port_lpbk_clr_stats_input { 3068 __le16 req_type; 3069 __le16 cmpl_ring; 3070 __le16 seq_id; 3071 __le16 target_id; 3072 __le64 resp_addr; 3073 }; 3074 3075 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3076 struct hwrm_port_lpbk_clr_stats_output { 3077 __le16 error_code; 3078 __le16 req_type; 3079 __le16 seq_id; 3080 __le16 resp_len; 3081 u8 unused_0[7]; 3082 u8 valid; 3083 }; 3084 3085 /* hwrm_port_ts_query_input (size:192b/24B) */ 3086 struct hwrm_port_ts_query_input { 3087 __le16 req_type; 3088 __le16 cmpl_ring; 3089 __le16 seq_id; 3090 __le16 target_id; 3091 __le64 resp_addr; 3092 __le32 flags; 3093 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3094 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3095 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3096 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3097 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3098 __le16 port_id; 3099 u8 unused_0[2]; 3100 }; 3101 3102 /* hwrm_port_ts_query_output (size:192b/24B) */ 3103 struct hwrm_port_ts_query_output { 3104 __le16 error_code; 3105 __le16 req_type; 3106 __le16 seq_id; 3107 __le16 resp_len; 3108 __le64 ptp_msg_ts; 3109 __le16 ptp_msg_seqid; 3110 u8 unused_0[5]; 3111 u8 valid; 3112 }; 3113 3114 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3115 struct hwrm_port_phy_qcaps_input { 3116 __le16 req_type; 3117 __le16 cmpl_ring; 3118 __le16 seq_id; 3119 __le16 target_id; 3120 __le64 resp_addr; 3121 __le16 port_id; 3122 u8 unused_0[6]; 3123 }; 3124 3125 /* hwrm_port_phy_qcaps_output (size:192b/24B) */ 3126 struct hwrm_port_phy_qcaps_output { 3127 __le16 error_code; 3128 __le16 req_type; 3129 __le16 seq_id; 3130 __le16 resp_len; 3131 u8 flags; 3132 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3133 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3134 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL 3135 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2 3136 u8 port_cnt; 3137 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3138 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3139 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3140 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3141 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3142 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3143 __le16 supported_speeds_force_mode; 3144 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3145 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3146 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3147 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3148 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3149 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3150 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3151 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3152 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3153 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3154 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3155 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3156 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3157 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3158 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB 0x4000UL 3159 __le16 supported_speeds_auto_mode; 3160 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3161 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3162 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3163 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3164 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3165 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3166 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3167 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3168 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3169 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3170 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3171 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3172 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3173 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3174 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB 0x4000UL 3175 __le16 supported_speeds_eee_mode; 3176 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3177 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3178 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3179 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3180 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3181 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3182 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3183 __le32 tx_lpi_timer_low; 3184 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3185 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3186 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3187 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3188 __le32 valid_tx_lpi_timer_high; 3189 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3190 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3191 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 3192 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 3193 }; 3194 3195 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3196 struct hwrm_port_phy_i2c_read_input { 3197 __le16 req_type; 3198 __le16 cmpl_ring; 3199 __le16 seq_id; 3200 __le16 target_id; 3201 __le64 resp_addr; 3202 __le32 flags; 3203 __le32 enables; 3204 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3205 __le16 port_id; 3206 u8 i2c_slave_addr; 3207 u8 unused_0; 3208 __le16 page_number; 3209 __le16 page_offset; 3210 u8 data_length; 3211 u8 unused_1[7]; 3212 }; 3213 3214 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3215 struct hwrm_port_phy_i2c_read_output { 3216 __le16 error_code; 3217 __le16 req_type; 3218 __le16 seq_id; 3219 __le16 resp_len; 3220 __le32 data[16]; 3221 u8 unused_0[7]; 3222 u8 valid; 3223 }; 3224 3225 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3226 struct hwrm_port_phy_mdio_write_input { 3227 __le16 req_type; 3228 __le16 cmpl_ring; 3229 __le16 seq_id; 3230 __le16 target_id; 3231 __le64 resp_addr; 3232 __le32 unused_0[2]; 3233 __le16 port_id; 3234 u8 phy_addr; 3235 u8 dev_addr; 3236 __le16 reg_addr; 3237 __le16 reg_data; 3238 u8 cl45_mdio; 3239 u8 unused_1[7]; 3240 }; 3241 3242 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3243 struct hwrm_port_phy_mdio_write_output { 3244 __le16 error_code; 3245 __le16 req_type; 3246 __le16 seq_id; 3247 __le16 resp_len; 3248 u8 unused_0[7]; 3249 u8 valid; 3250 }; 3251 3252 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3253 struct hwrm_port_phy_mdio_read_input { 3254 __le16 req_type; 3255 __le16 cmpl_ring; 3256 __le16 seq_id; 3257 __le16 target_id; 3258 __le64 resp_addr; 3259 __le32 unused_0[2]; 3260 __le16 port_id; 3261 u8 phy_addr; 3262 u8 dev_addr; 3263 __le16 reg_addr; 3264 u8 cl45_mdio; 3265 u8 unused_1; 3266 }; 3267 3268 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3269 struct hwrm_port_phy_mdio_read_output { 3270 __le16 error_code; 3271 __le16 req_type; 3272 __le16 seq_id; 3273 __le16 resp_len; 3274 __le16 reg_data; 3275 u8 unused_0[5]; 3276 u8 valid; 3277 }; 3278 3279 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3280 struct hwrm_port_led_cfg_input { 3281 __le16 req_type; 3282 __le16 cmpl_ring; 3283 __le16 seq_id; 3284 __le16 target_id; 3285 __le64 resp_addr; 3286 __le32 enables; 3287 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3288 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3289 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3290 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3291 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3292 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3293 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3294 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3295 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3296 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3297 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3298 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3299 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3300 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3301 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3302 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3303 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3304 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3305 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3306 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3307 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3308 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3309 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3310 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3311 __le16 port_id; 3312 u8 num_leds; 3313 u8 rsvd; 3314 u8 led0_id; 3315 u8 led0_state; 3316 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3317 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3318 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3319 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3320 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3321 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3322 u8 led0_color; 3323 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3324 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3325 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3326 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3327 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3328 u8 unused_0; 3329 __le16 led0_blink_on; 3330 __le16 led0_blink_off; 3331 u8 led0_group_id; 3332 u8 rsvd0; 3333 u8 led1_id; 3334 u8 led1_state; 3335 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3336 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3337 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3338 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3339 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3340 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3341 u8 led1_color; 3342 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3343 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3344 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3345 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3346 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3347 u8 unused_1; 3348 __le16 led1_blink_on; 3349 __le16 led1_blink_off; 3350 u8 led1_group_id; 3351 u8 rsvd1; 3352 u8 led2_id; 3353 u8 led2_state; 3354 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3355 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3356 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3357 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3358 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3359 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3360 u8 led2_color; 3361 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3362 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3363 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3364 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3365 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3366 u8 unused_2; 3367 __le16 led2_blink_on; 3368 __le16 led2_blink_off; 3369 u8 led2_group_id; 3370 u8 rsvd2; 3371 u8 led3_id; 3372 u8 led3_state; 3373 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3374 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3375 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3376 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3377 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3378 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3379 u8 led3_color; 3380 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3381 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3382 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3383 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3384 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3385 u8 unused_3; 3386 __le16 led3_blink_on; 3387 __le16 led3_blink_off; 3388 u8 led3_group_id; 3389 u8 rsvd3; 3390 }; 3391 3392 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3393 struct hwrm_port_led_cfg_output { 3394 __le16 error_code; 3395 __le16 req_type; 3396 __le16 seq_id; 3397 __le16 resp_len; 3398 u8 unused_0[7]; 3399 u8 valid; 3400 }; 3401 3402 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3403 struct hwrm_port_led_qcfg_input { 3404 __le16 req_type; 3405 __le16 cmpl_ring; 3406 __le16 seq_id; 3407 __le16 target_id; 3408 __le64 resp_addr; 3409 __le16 port_id; 3410 u8 unused_0[6]; 3411 }; 3412 3413 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3414 struct hwrm_port_led_qcfg_output { 3415 __le16 error_code; 3416 __le16 req_type; 3417 __le16 seq_id; 3418 __le16 resp_len; 3419 u8 num_leds; 3420 u8 led0_id; 3421 u8 led0_type; 3422 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3423 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3424 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3425 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3426 u8 led0_state; 3427 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3428 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3429 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3430 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3431 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3432 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3433 u8 led0_color; 3434 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3435 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3436 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3437 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3438 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3439 u8 unused_0; 3440 __le16 led0_blink_on; 3441 __le16 led0_blink_off; 3442 u8 led0_group_id; 3443 u8 led1_id; 3444 u8 led1_type; 3445 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3446 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3447 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3448 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3449 u8 led1_state; 3450 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3451 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3452 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3453 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3454 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3455 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3456 u8 led1_color; 3457 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3458 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3459 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3460 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3461 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3462 u8 unused_1; 3463 __le16 led1_blink_on; 3464 __le16 led1_blink_off; 3465 u8 led1_group_id; 3466 u8 led2_id; 3467 u8 led2_type; 3468 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3469 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3470 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3471 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3472 u8 led2_state; 3473 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3474 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3475 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3476 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3477 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3478 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3479 u8 led2_color; 3480 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3481 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3482 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3483 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3484 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3485 u8 unused_2; 3486 __le16 led2_blink_on; 3487 __le16 led2_blink_off; 3488 u8 led2_group_id; 3489 u8 led3_id; 3490 u8 led3_type; 3491 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3492 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3493 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3494 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3495 u8 led3_state; 3496 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3497 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3498 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3499 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3500 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3501 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3502 u8 led3_color; 3503 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3504 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3505 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3506 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3507 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3508 u8 unused_3; 3509 __le16 led3_blink_on; 3510 __le16 led3_blink_off; 3511 u8 led3_group_id; 3512 u8 unused_4[6]; 3513 u8 valid; 3514 }; 3515 3516 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3517 struct hwrm_port_led_qcaps_input { 3518 __le16 req_type; 3519 __le16 cmpl_ring; 3520 __le16 seq_id; 3521 __le16 target_id; 3522 __le64 resp_addr; 3523 __le16 port_id; 3524 u8 unused_0[6]; 3525 }; 3526 3527 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3528 struct hwrm_port_led_qcaps_output { 3529 __le16 error_code; 3530 __le16 req_type; 3531 __le16 seq_id; 3532 __le16 resp_len; 3533 u8 num_leds; 3534 u8 unused[3]; 3535 u8 led0_id; 3536 u8 led0_type; 3537 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3538 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3539 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3540 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3541 u8 led0_group_id; 3542 u8 unused_0; 3543 __le16 led0_state_caps; 3544 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3545 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3546 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3547 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3548 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3549 __le16 led0_color_caps; 3550 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3551 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3552 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3553 u8 led1_id; 3554 u8 led1_type; 3555 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3556 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3557 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3558 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3559 u8 led1_group_id; 3560 u8 unused_1; 3561 __le16 led1_state_caps; 3562 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3563 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3564 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3565 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3566 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3567 __le16 led1_color_caps; 3568 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3569 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3570 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3571 u8 led2_id; 3572 u8 led2_type; 3573 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3574 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3575 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3576 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3577 u8 led2_group_id; 3578 u8 unused_2; 3579 __le16 led2_state_caps; 3580 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3581 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3582 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3583 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3584 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3585 __le16 led2_color_caps; 3586 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3587 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3588 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3589 u8 led3_id; 3590 u8 led3_type; 3591 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3592 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3593 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3594 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3595 u8 led3_group_id; 3596 u8 unused_3; 3597 __le16 led3_state_caps; 3598 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3599 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3600 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3601 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3602 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3603 __le16 led3_color_caps; 3604 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3605 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3606 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3607 u8 unused_4[3]; 3608 u8 valid; 3609 }; 3610 3611 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 3612 struct hwrm_queue_qportcfg_input { 3613 __le16 req_type; 3614 __le16 cmpl_ring; 3615 __le16 seq_id; 3616 __le16 target_id; 3617 __le64 resp_addr; 3618 __le32 flags; 3619 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3620 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3621 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3622 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3623 __le16 port_id; 3624 u8 drv_qmap_cap; 3625 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3626 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3627 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3628 u8 unused_0; 3629 }; 3630 3631 /* hwrm_queue_qportcfg_output (size:256b/32B) */ 3632 struct hwrm_queue_qportcfg_output { 3633 __le16 error_code; 3634 __le16 req_type; 3635 __le16 seq_id; 3636 __le16 resp_len; 3637 u8 max_configurable_queues; 3638 u8 max_configurable_lossless_queues; 3639 u8 queue_cfg_allowed; 3640 u8 queue_cfg_info; 3641 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3642 u8 queue_pfcenable_cfg_allowed; 3643 u8 queue_pri2cos_cfg_allowed; 3644 u8 queue_cos2bw_cfg_allowed; 3645 u8 queue_id0; 3646 u8 queue_id0_service_profile; 3647 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3648 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3649 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3650 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3651 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3652 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3653 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3654 u8 queue_id1; 3655 u8 queue_id1_service_profile; 3656 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3657 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3658 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3659 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3660 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3661 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3662 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3663 u8 queue_id2; 3664 u8 queue_id2_service_profile; 3665 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3666 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3667 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3668 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3669 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3670 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3671 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3672 u8 queue_id3; 3673 u8 queue_id3_service_profile; 3674 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3675 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3676 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3677 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3678 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3679 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3680 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3681 u8 queue_id4; 3682 u8 queue_id4_service_profile; 3683 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3684 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3685 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3686 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3687 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3688 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3689 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3690 u8 queue_id5; 3691 u8 queue_id5_service_profile; 3692 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3693 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3694 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3695 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3696 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3697 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3698 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3699 u8 queue_id6; 3700 u8 queue_id6_service_profile; 3701 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3702 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3703 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3704 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3705 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3706 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3707 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3708 u8 queue_id7; 3709 u8 queue_id7_service_profile; 3710 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3711 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3712 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3713 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3714 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3715 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3716 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3717 u8 valid; 3718 }; 3719 3720 /* hwrm_queue_cfg_input (size:320b/40B) */ 3721 struct hwrm_queue_cfg_input { 3722 __le16 req_type; 3723 __le16 cmpl_ring; 3724 __le16 seq_id; 3725 __le16 target_id; 3726 __le64 resp_addr; 3727 __le32 flags; 3728 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3729 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 3730 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 3731 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 3732 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3733 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 3734 __le32 enables; 3735 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 3736 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 3737 __le32 queue_id; 3738 __le32 dflt_len; 3739 u8 service_profile; 3740 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 3741 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 3742 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 3743 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 3744 u8 unused_0[7]; 3745 }; 3746 3747 /* hwrm_queue_cfg_output (size:128b/16B) */ 3748 struct hwrm_queue_cfg_output { 3749 __le16 error_code; 3750 __le16 req_type; 3751 __le16 seq_id; 3752 __le16 resp_len; 3753 u8 unused_0[7]; 3754 u8 valid; 3755 }; 3756 3757 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 3758 struct hwrm_queue_pfcenable_qcfg_input { 3759 __le16 req_type; 3760 __le16 cmpl_ring; 3761 __le16 seq_id; 3762 __le16 target_id; 3763 __le64 resp_addr; 3764 __le16 port_id; 3765 u8 unused_0[6]; 3766 }; 3767 3768 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 3769 struct hwrm_queue_pfcenable_qcfg_output { 3770 __le16 error_code; 3771 __le16 req_type; 3772 __le16 seq_id; 3773 __le16 resp_len; 3774 __le32 flags; 3775 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 3776 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 3777 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 3778 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 3779 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 3780 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 3781 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 3782 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 3783 u8 unused_0[3]; 3784 u8 valid; 3785 }; 3786 3787 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 3788 struct hwrm_queue_pfcenable_cfg_input { 3789 __le16 req_type; 3790 __le16 cmpl_ring; 3791 __le16 seq_id; 3792 __le16 target_id; 3793 __le64 resp_addr; 3794 __le32 flags; 3795 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 3796 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 3797 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 3798 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 3799 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 3800 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 3801 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 3802 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 3803 __le16 port_id; 3804 u8 unused_0[2]; 3805 }; 3806 3807 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 3808 struct hwrm_queue_pfcenable_cfg_output { 3809 __le16 error_code; 3810 __le16 req_type; 3811 __le16 seq_id; 3812 __le16 resp_len; 3813 u8 unused_0[7]; 3814 u8 valid; 3815 }; 3816 3817 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 3818 struct hwrm_queue_pri2cos_qcfg_input { 3819 __le16 req_type; 3820 __le16 cmpl_ring; 3821 __le16 seq_id; 3822 __le16 target_id; 3823 __le64 resp_addr; 3824 __le32 flags; 3825 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 3826 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 3827 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 3828 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 3829 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 3830 u8 port_id; 3831 u8 unused_0[3]; 3832 }; 3833 3834 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 3835 struct hwrm_queue_pri2cos_qcfg_output { 3836 __le16 error_code; 3837 __le16 req_type; 3838 __le16 seq_id; 3839 __le16 resp_len; 3840 u8 pri0_cos_queue_id; 3841 u8 pri1_cos_queue_id; 3842 u8 pri2_cos_queue_id; 3843 u8 pri3_cos_queue_id; 3844 u8 pri4_cos_queue_id; 3845 u8 pri5_cos_queue_id; 3846 u8 pri6_cos_queue_id; 3847 u8 pri7_cos_queue_id; 3848 u8 queue_cfg_info; 3849 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3850 u8 unused_0[6]; 3851 u8 valid; 3852 }; 3853 3854 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 3855 struct hwrm_queue_pri2cos_cfg_input { 3856 __le16 req_type; 3857 __le16 cmpl_ring; 3858 __le16 seq_id; 3859 __le16 target_id; 3860 __le64 resp_addr; 3861 __le32 flags; 3862 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3863 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 3864 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 3865 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 3866 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3867 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 3868 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 3869 __le32 enables; 3870 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 3871 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 3872 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 3873 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 3874 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 3875 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 3876 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 3877 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 3878 u8 port_id; 3879 u8 pri0_cos_queue_id; 3880 u8 pri1_cos_queue_id; 3881 u8 pri2_cos_queue_id; 3882 u8 pri3_cos_queue_id; 3883 u8 pri4_cos_queue_id; 3884 u8 pri5_cos_queue_id; 3885 u8 pri6_cos_queue_id; 3886 u8 pri7_cos_queue_id; 3887 u8 unused_0[7]; 3888 }; 3889 3890 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 3891 struct hwrm_queue_pri2cos_cfg_output { 3892 __le16 error_code; 3893 __le16 req_type; 3894 __le16 seq_id; 3895 __le16 resp_len; 3896 u8 unused_0[7]; 3897 u8 valid; 3898 }; 3899 3900 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 3901 struct hwrm_queue_cos2bw_qcfg_input { 3902 __le16 req_type; 3903 __le16 cmpl_ring; 3904 __le16 seq_id; 3905 __le16 target_id; 3906 __le64 resp_addr; 3907 __le16 port_id; 3908 u8 unused_0[6]; 3909 }; 3910 3911 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 3912 struct hwrm_queue_cos2bw_qcfg_output { 3913 __le16 error_code; 3914 __le16 req_type; 3915 __le16 seq_id; 3916 __le16 resp_len; 3917 u8 queue_id0; 3918 u8 unused_0; 3919 __le16 unused_1; 3920 __le32 queue_id0_min_bw; 3921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 3927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3934 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3935 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3936 __le32 queue_id0_max_bw; 3937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 3943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3950 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3952 u8 queue_id0_tsa_assign; 3953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3955 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3956 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3957 u8 queue_id0_pri_lvl; 3958 u8 queue_id0_bw_weight; 3959 u8 queue_id1; 3960 __le32 queue_id1_min_bw; 3961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 3967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3974 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3975 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3976 __le32 queue_id1_max_bw; 3977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3980 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3981 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3982 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 3983 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3992 u8 queue_id1_tsa_assign; 3993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3995 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3996 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3997 u8 queue_id1_pri_lvl; 3998 u8 queue_id1_bw_weight; 3999 u8 queue_id2; 4000 __le32 queue_id2_min_bw; 4001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4015 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4016 __le32 queue_id2_max_bw; 4017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4020 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4032 u8 queue_id2_tsa_assign; 4033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4035 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4036 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4037 u8 queue_id2_pri_lvl; 4038 u8 queue_id2_bw_weight; 4039 u8 queue_id3; 4040 __le32 queue_id3_min_bw; 4041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4044 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4051 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4054 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4055 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4056 __le32 queue_id3_max_bw; 4057 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4058 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4059 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4060 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4061 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4062 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4063 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4065 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4066 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4067 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4068 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4070 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4071 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4072 u8 queue_id3_tsa_assign; 4073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4075 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4076 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4077 u8 queue_id3_pri_lvl; 4078 u8 queue_id3_bw_weight; 4079 u8 queue_id4; 4080 __le32 queue_id4_min_bw; 4081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4084 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4091 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4094 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4095 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4096 __le32 queue_id4_max_bw; 4097 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4098 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4099 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4100 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4101 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4102 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4103 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4105 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4106 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4107 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4108 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4110 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4111 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4112 u8 queue_id4_tsa_assign; 4113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4115 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4116 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4117 u8 queue_id4_pri_lvl; 4118 u8 queue_id4_bw_weight; 4119 u8 queue_id5; 4120 __le32 queue_id5_min_bw; 4121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4135 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4136 __le32 queue_id5_max_bw; 4137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4140 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4145 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4146 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4147 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4148 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4150 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4151 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4152 u8 queue_id5_tsa_assign; 4153 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4154 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4155 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4156 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4157 u8 queue_id5_pri_lvl; 4158 u8 queue_id5_bw_weight; 4159 u8 queue_id6; 4160 __le32 queue_id6_min_bw; 4161 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4162 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4163 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4164 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4165 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4175 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4176 __le32 queue_id6_max_bw; 4177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4186 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4188 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4191 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4192 u8 queue_id6_tsa_assign; 4193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4197 u8 queue_id6_pri_lvl; 4198 u8 queue_id6_bw_weight; 4199 u8 queue_id7; 4200 __le32 queue_id7_min_bw; 4201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4202 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4203 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4204 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4205 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4207 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4208 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4209 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4210 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4211 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4216 __le32 queue_id7_max_bw; 4217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4226 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4227 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4232 u8 queue_id7_tsa_assign; 4233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4237 u8 queue_id7_pri_lvl; 4238 u8 queue_id7_bw_weight; 4239 u8 unused_2[4]; 4240 u8 valid; 4241 }; 4242 4243 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4244 struct hwrm_queue_cos2bw_cfg_input { 4245 __le16 req_type; 4246 __le16 cmpl_ring; 4247 __le16 seq_id; 4248 __le16 target_id; 4249 __le64 resp_addr; 4250 __le32 flags; 4251 __le32 enables; 4252 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4253 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4254 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4255 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4256 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4257 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4258 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4259 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4260 __le16 port_id; 4261 u8 queue_id0; 4262 u8 unused_0; 4263 __le32 queue_id0_min_bw; 4264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4279 __le32 queue_id0_max_bw; 4280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4295 u8 queue_id0_tsa_assign; 4296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4298 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4299 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4300 u8 queue_id0_pri_lvl; 4301 u8 queue_id0_bw_weight; 4302 u8 queue_id1; 4303 __le32 queue_id1_min_bw; 4304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4319 __le32 queue_id1_max_bw; 4320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4335 u8 queue_id1_tsa_assign; 4336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4339 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4340 u8 queue_id1_pri_lvl; 4341 u8 queue_id1_bw_weight; 4342 u8 queue_id2; 4343 __le32 queue_id2_min_bw; 4344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4359 __le32 queue_id2_max_bw; 4360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4375 u8 queue_id2_tsa_assign; 4376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4379 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4380 u8 queue_id2_pri_lvl; 4381 u8 queue_id2_bw_weight; 4382 u8 queue_id3; 4383 __le32 queue_id3_min_bw; 4384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4397 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4398 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4399 __le32 queue_id3_max_bw; 4400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4403 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4404 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4405 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4406 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4415 u8 queue_id3_tsa_assign; 4416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4418 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4419 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4420 u8 queue_id3_pri_lvl; 4421 u8 queue_id3_bw_weight; 4422 u8 queue_id4; 4423 __le32 queue_id4_min_bw; 4424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4427 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4438 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4439 __le32 queue_id4_max_bw; 4440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4443 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4455 u8 queue_id4_tsa_assign; 4456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4459 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4460 u8 queue_id4_pri_lvl; 4461 u8 queue_id4_bw_weight; 4462 u8 queue_id5; 4463 __le32 queue_id5_min_bw; 4464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4479 __le32 queue_id5_max_bw; 4480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4495 u8 queue_id5_tsa_assign; 4496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4500 u8 queue_id5_pri_lvl; 4501 u8 queue_id5_bw_weight; 4502 u8 queue_id6; 4503 __le32 queue_id6_min_bw; 4504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4519 __le32 queue_id6_max_bw; 4520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4521 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4529 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4535 u8 queue_id6_tsa_assign; 4536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4540 u8 queue_id6_pri_lvl; 4541 u8 queue_id6_bw_weight; 4542 u8 queue_id7; 4543 __le32 queue_id7_min_bw; 4544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4547 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4559 __le32 queue_id7_max_bw; 4560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4575 u8 queue_id7_tsa_assign; 4576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4577 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4580 u8 queue_id7_pri_lvl; 4581 u8 queue_id7_bw_weight; 4582 u8 unused_1[5]; 4583 }; 4584 4585 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4586 struct hwrm_queue_cos2bw_cfg_output { 4587 __le16 error_code; 4588 __le16 req_type; 4589 __le16 seq_id; 4590 __le16 resp_len; 4591 u8 unused_0[7]; 4592 u8 valid; 4593 }; 4594 4595 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4596 struct hwrm_queue_dscp_qcaps_input { 4597 __le16 req_type; 4598 __le16 cmpl_ring; 4599 __le16 seq_id; 4600 __le16 target_id; 4601 __le64 resp_addr; 4602 u8 port_id; 4603 u8 unused_0[7]; 4604 }; 4605 4606 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4607 struct hwrm_queue_dscp_qcaps_output { 4608 __le16 error_code; 4609 __le16 req_type; 4610 __le16 seq_id; 4611 __le16 resp_len; 4612 u8 num_dscp_bits; 4613 u8 unused_0; 4614 __le16 max_entries; 4615 u8 unused_1[3]; 4616 u8 valid; 4617 }; 4618 4619 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4620 struct hwrm_queue_dscp2pri_qcfg_input { 4621 __le16 req_type; 4622 __le16 cmpl_ring; 4623 __le16 seq_id; 4624 __le16 target_id; 4625 __le64 resp_addr; 4626 __le64 dest_data_addr; 4627 u8 port_id; 4628 u8 unused_0; 4629 __le16 dest_data_buffer_size; 4630 u8 unused_1[4]; 4631 }; 4632 4633 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4634 struct hwrm_queue_dscp2pri_qcfg_output { 4635 __le16 error_code; 4636 __le16 req_type; 4637 __le16 seq_id; 4638 __le16 resp_len; 4639 __le16 entry_cnt; 4640 u8 default_pri; 4641 u8 unused_0[4]; 4642 u8 valid; 4643 }; 4644 4645 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4646 struct hwrm_queue_dscp2pri_cfg_input { 4647 __le16 req_type; 4648 __le16 cmpl_ring; 4649 __le16 seq_id; 4650 __le16 target_id; 4651 __le64 resp_addr; 4652 __le64 src_data_addr; 4653 __le32 flags; 4654 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4655 __le32 enables; 4656 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4657 u8 port_id; 4658 u8 default_pri; 4659 __le16 entry_cnt; 4660 u8 unused_0[4]; 4661 }; 4662 4663 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4664 struct hwrm_queue_dscp2pri_cfg_output { 4665 __le16 error_code; 4666 __le16 req_type; 4667 __le16 seq_id; 4668 __le16 resp_len; 4669 u8 unused_0[7]; 4670 u8 valid; 4671 }; 4672 4673 /* hwrm_vnic_alloc_input (size:192b/24B) */ 4674 struct hwrm_vnic_alloc_input { 4675 __le16 req_type; 4676 __le16 cmpl_ring; 4677 __le16 seq_id; 4678 __le16 target_id; 4679 __le64 resp_addr; 4680 __le32 flags; 4681 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 4682 u8 unused_0[4]; 4683 }; 4684 4685 /* hwrm_vnic_alloc_output (size:128b/16B) */ 4686 struct hwrm_vnic_alloc_output { 4687 __le16 error_code; 4688 __le16 req_type; 4689 __le16 seq_id; 4690 __le16 resp_len; 4691 __le32 vnic_id; 4692 u8 unused_0[3]; 4693 u8 valid; 4694 }; 4695 4696 /* hwrm_vnic_free_input (size:192b/24B) */ 4697 struct hwrm_vnic_free_input { 4698 __le16 req_type; 4699 __le16 cmpl_ring; 4700 __le16 seq_id; 4701 __le16 target_id; 4702 __le64 resp_addr; 4703 __le32 vnic_id; 4704 u8 unused_0[4]; 4705 }; 4706 4707 /* hwrm_vnic_free_output (size:128b/16B) */ 4708 struct hwrm_vnic_free_output { 4709 __le16 error_code; 4710 __le16 req_type; 4711 __le16 seq_id; 4712 __le16 resp_len; 4713 u8 unused_0[7]; 4714 u8 valid; 4715 }; 4716 4717 /* hwrm_vnic_cfg_input (size:320b/40B) */ 4718 struct hwrm_vnic_cfg_input { 4719 __le16 req_type; 4720 __le16 cmpl_ring; 4721 __le16 seq_id; 4722 __le16 target_id; 4723 __le64 resp_addr; 4724 __le32 flags; 4725 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 4726 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 4727 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 4728 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 4729 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 4730 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4731 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4732 __le32 enables; 4733 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4734 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4735 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4736 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4737 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4738 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 4739 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 4740 __le16 vnic_id; 4741 __le16 dflt_ring_grp; 4742 __le16 rss_rule; 4743 __le16 cos_rule; 4744 __le16 lb_rule; 4745 __le16 mru; 4746 __le16 default_rx_ring_id; 4747 __le16 default_cmpl_ring_id; 4748 }; 4749 4750 /* hwrm_vnic_cfg_output (size:128b/16B) */ 4751 struct hwrm_vnic_cfg_output { 4752 __le16 error_code; 4753 __le16 req_type; 4754 __le16 seq_id; 4755 __le16 resp_len; 4756 u8 unused_0[7]; 4757 u8 valid; 4758 }; 4759 4760 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 4761 struct hwrm_vnic_qcaps_input { 4762 __le16 req_type; 4763 __le16 cmpl_ring; 4764 __le16 seq_id; 4765 __le16 target_id; 4766 __le64 resp_addr; 4767 __le32 enables; 4768 u8 unused_0[4]; 4769 }; 4770 4771 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 4772 struct hwrm_vnic_qcaps_output { 4773 __le16 error_code; 4774 __le16 req_type; 4775 __le16 seq_id; 4776 __le16 resp_len; 4777 __le16 mru; 4778 u8 unused_0[2]; 4779 __le32 flags; 4780 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 4781 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 4782 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 4783 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 4784 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4785 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4786 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4787 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 4788 __le16 max_aggs_supported; 4789 u8 unused_1[5]; 4790 u8 valid; 4791 }; 4792 4793 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 4794 struct hwrm_vnic_tpa_cfg_input { 4795 __le16 req_type; 4796 __le16 cmpl_ring; 4797 __le16 seq_id; 4798 __le16 target_id; 4799 __le64 resp_addr; 4800 __le32 flags; 4801 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 4802 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 4803 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 4804 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 4805 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 4806 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4807 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 4808 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 4809 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 4810 __le32 enables; 4811 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 4812 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 4813 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 4814 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 4815 __le16 vnic_id; 4816 __le16 max_agg_segs; 4817 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 4818 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 4819 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 4820 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 4821 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 4822 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 4823 __le16 max_aggs; 4824 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 4825 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 4826 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 4827 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 4828 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 4829 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 4830 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 4831 u8 unused_0[2]; 4832 __le32 max_agg_timer; 4833 __le32 min_agg_len; 4834 }; 4835 4836 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 4837 struct hwrm_vnic_tpa_cfg_output { 4838 __le16 error_code; 4839 __le16 req_type; 4840 __le16 seq_id; 4841 __le16 resp_len; 4842 u8 unused_0[7]; 4843 u8 valid; 4844 }; 4845 4846 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 4847 struct hwrm_vnic_tpa_qcfg_input { 4848 __le16 req_type; 4849 __le16 cmpl_ring; 4850 __le16 seq_id; 4851 __le16 target_id; 4852 __le64 resp_addr; 4853 __le16 vnic_id; 4854 u8 unused_0[6]; 4855 }; 4856 4857 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 4858 struct hwrm_vnic_tpa_qcfg_output { 4859 __le16 error_code; 4860 __le16 req_type; 4861 __le16 seq_id; 4862 __le16 resp_len; 4863 __le32 flags; 4864 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 4865 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 4866 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 4867 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 4868 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 4869 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4870 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 4871 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 4872 __le16 max_agg_segs; 4873 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 4874 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 4875 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 4876 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 4877 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 4878 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 4879 __le16 max_aggs; 4880 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 4881 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 4882 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 4883 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 4884 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 4885 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 4886 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 4887 __le32 max_agg_timer; 4888 __le32 min_agg_len; 4889 u8 unused_0[7]; 4890 u8 valid; 4891 }; 4892 4893 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 4894 struct hwrm_vnic_rss_cfg_input { 4895 __le16 req_type; 4896 __le16 cmpl_ring; 4897 __le16 seq_id; 4898 __le16 target_id; 4899 __le64 resp_addr; 4900 __le32 hash_type; 4901 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 4902 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 4903 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 4904 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 4905 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 4906 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 4907 __le16 vnic_id; 4908 u8 ring_table_pair_index; 4909 u8 hash_mode_flags; 4910 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 4911 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 4912 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 4913 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 4914 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 4915 __le64 ring_grp_tbl_addr; 4916 __le64 hash_key_tbl_addr; 4917 __le16 rss_ctx_idx; 4918 u8 unused_1[6]; 4919 }; 4920 4921 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 4922 struct hwrm_vnic_rss_cfg_output { 4923 __le16 error_code; 4924 __le16 req_type; 4925 __le16 seq_id; 4926 __le16 resp_len; 4927 u8 unused_0[7]; 4928 u8 valid; 4929 }; 4930 4931 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 4932 struct hwrm_vnic_plcmodes_cfg_input { 4933 __le16 req_type; 4934 __le16 cmpl_ring; 4935 __le16 seq_id; 4936 __le16 target_id; 4937 __le64 resp_addr; 4938 __le32 flags; 4939 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 4940 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 4941 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 4942 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 4943 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 4944 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 4945 __le32 enables; 4946 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 4947 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 4948 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 4949 __le32 vnic_id; 4950 __le16 jumbo_thresh; 4951 __le16 hds_offset; 4952 __le16 hds_threshold; 4953 u8 unused_0[6]; 4954 }; 4955 4956 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 4957 struct hwrm_vnic_plcmodes_cfg_output { 4958 __le16 error_code; 4959 __le16 req_type; 4960 __le16 seq_id; 4961 __le16 resp_len; 4962 u8 unused_0[7]; 4963 u8 valid; 4964 }; 4965 4966 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 4967 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 4968 __le16 req_type; 4969 __le16 cmpl_ring; 4970 __le16 seq_id; 4971 __le16 target_id; 4972 __le64 resp_addr; 4973 }; 4974 4975 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 4976 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 4977 __le16 error_code; 4978 __le16 req_type; 4979 __le16 seq_id; 4980 __le16 resp_len; 4981 __le16 rss_cos_lb_ctx_id; 4982 u8 unused_0[5]; 4983 u8 valid; 4984 }; 4985 4986 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 4987 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 4988 __le16 req_type; 4989 __le16 cmpl_ring; 4990 __le16 seq_id; 4991 __le16 target_id; 4992 __le64 resp_addr; 4993 __le16 rss_cos_lb_ctx_id; 4994 u8 unused_0[6]; 4995 }; 4996 4997 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 4998 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 4999 __le16 error_code; 5000 __le16 req_type; 5001 __le16 seq_id; 5002 __le16 resp_len; 5003 u8 unused_0[7]; 5004 u8 valid; 5005 }; 5006 5007 /* hwrm_ring_alloc_input (size:704b/88B) */ 5008 struct hwrm_ring_alloc_input { 5009 __le16 req_type; 5010 __le16 cmpl_ring; 5011 __le16 seq_id; 5012 __le16 target_id; 5013 __le64 resp_addr; 5014 __le32 enables; 5015 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5016 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5017 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5018 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5019 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5020 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5021 u8 ring_type; 5022 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5023 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5024 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5025 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5026 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5027 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5028 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5029 u8 unused_0; 5030 __le16 flags; 5031 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5032 __le64 page_tbl_addr; 5033 __le32 fbo; 5034 u8 page_size; 5035 u8 page_tbl_depth; 5036 u8 unused_1[2]; 5037 __le32 length; 5038 __le16 logical_id; 5039 __le16 cmpl_ring_id; 5040 __le16 queue_id; 5041 __le16 rx_buf_size; 5042 __le16 rx_ring_id; 5043 __le16 nq_ring_id; 5044 __le16 ring_arb_cfg; 5045 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5046 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5047 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5048 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5049 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5050 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5051 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5052 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5053 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5054 __le16 unused_3; 5055 __le32 reserved3; 5056 __le32 stat_ctx_id; 5057 __le32 reserved4; 5058 __le32 max_bw; 5059 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5060 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5061 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5062 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5063 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5064 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5065 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5066 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5067 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5068 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5069 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5070 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5071 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5072 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5073 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5074 u8 int_mode; 5075 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5076 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5077 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5078 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5079 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5080 u8 unused_4[3]; 5081 __le64 cq_handle; 5082 }; 5083 5084 /* hwrm_ring_alloc_output (size:128b/16B) */ 5085 struct hwrm_ring_alloc_output { 5086 __le16 error_code; 5087 __le16 req_type; 5088 __le16 seq_id; 5089 __le16 resp_len; 5090 __le16 ring_id; 5091 __le16 logical_ring_id; 5092 u8 unused_0[3]; 5093 u8 valid; 5094 }; 5095 5096 /* hwrm_ring_free_input (size:192b/24B) */ 5097 struct hwrm_ring_free_input { 5098 __le16 req_type; 5099 __le16 cmpl_ring; 5100 __le16 seq_id; 5101 __le16 target_id; 5102 __le64 resp_addr; 5103 u8 ring_type; 5104 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5105 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5106 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5107 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5108 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5109 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5110 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5111 u8 unused_0; 5112 __le16 ring_id; 5113 u8 unused_1[4]; 5114 }; 5115 5116 /* hwrm_ring_free_output (size:128b/16B) */ 5117 struct hwrm_ring_free_output { 5118 __le16 error_code; 5119 __le16 req_type; 5120 __le16 seq_id; 5121 __le16 resp_len; 5122 u8 unused_0[7]; 5123 u8 valid; 5124 }; 5125 5126 /* hwrm_ring_reset_input (size:192b/24B) */ 5127 struct hwrm_ring_reset_input { 5128 __le16 req_type; 5129 __le16 cmpl_ring; 5130 __le16 seq_id; 5131 __le16 target_id; 5132 __le64 resp_addr; 5133 u8 ring_type; 5134 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5135 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5136 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5137 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5138 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL 5139 u8 unused_0; 5140 __le16 ring_id; 5141 u8 unused_1[4]; 5142 }; 5143 5144 /* hwrm_ring_reset_output (size:128b/16B) */ 5145 struct hwrm_ring_reset_output { 5146 __le16 error_code; 5147 __le16 req_type; 5148 __le16 seq_id; 5149 __le16 resp_len; 5150 u8 unused_0[4]; 5151 u8 consumer_idx[3]; 5152 u8 valid; 5153 }; 5154 5155 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5156 struct hwrm_ring_aggint_qcaps_input { 5157 __le16 req_type; 5158 __le16 cmpl_ring; 5159 __le16 seq_id; 5160 __le16 target_id; 5161 __le64 resp_addr; 5162 }; 5163 5164 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5165 struct hwrm_ring_aggint_qcaps_output { 5166 __le16 error_code; 5167 __le16 req_type; 5168 __le16 seq_id; 5169 __le16 resp_len; 5170 __le32 cmpl_params; 5171 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5172 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5173 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5174 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5175 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5176 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5177 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5178 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5179 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5180 __le32 nq_params; 5181 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5182 __le16 num_cmpl_dma_aggr_min; 5183 __le16 num_cmpl_dma_aggr_max; 5184 __le16 num_cmpl_dma_aggr_during_int_min; 5185 __le16 num_cmpl_dma_aggr_during_int_max; 5186 __le16 cmpl_aggr_dma_tmr_min; 5187 __le16 cmpl_aggr_dma_tmr_max; 5188 __le16 cmpl_aggr_dma_tmr_during_int_min; 5189 __le16 cmpl_aggr_dma_tmr_during_int_max; 5190 __le16 int_lat_tmr_min_min; 5191 __le16 int_lat_tmr_min_max; 5192 __le16 int_lat_tmr_max_min; 5193 __le16 int_lat_tmr_max_max; 5194 __le16 num_cmpl_aggr_int_min; 5195 __le16 num_cmpl_aggr_int_max; 5196 __le16 timer_units; 5197 u8 unused_0[1]; 5198 u8 valid; 5199 }; 5200 5201 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5202 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5203 __le16 req_type; 5204 __le16 cmpl_ring; 5205 __le16 seq_id; 5206 __le16 target_id; 5207 __le64 resp_addr; 5208 __le16 ring_id; 5209 u8 unused_0[6]; 5210 }; 5211 5212 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5213 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5214 __le16 error_code; 5215 __le16 req_type; 5216 __le16 seq_id; 5217 __le16 resp_len; 5218 __le16 flags; 5219 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5220 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5221 __le16 num_cmpl_dma_aggr; 5222 __le16 num_cmpl_dma_aggr_during_int; 5223 __le16 cmpl_aggr_dma_tmr; 5224 __le16 cmpl_aggr_dma_tmr_during_int; 5225 __le16 int_lat_tmr_min; 5226 __le16 int_lat_tmr_max; 5227 __le16 num_cmpl_aggr_int; 5228 u8 unused_0[7]; 5229 u8 valid; 5230 }; 5231 5232 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5233 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5234 __le16 req_type; 5235 __le16 cmpl_ring; 5236 __le16 seq_id; 5237 __le16 target_id; 5238 __le64 resp_addr; 5239 __le16 ring_id; 5240 __le16 flags; 5241 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5242 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5243 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5244 __le16 num_cmpl_dma_aggr; 5245 __le16 num_cmpl_dma_aggr_during_int; 5246 __le16 cmpl_aggr_dma_tmr; 5247 __le16 cmpl_aggr_dma_tmr_during_int; 5248 __le16 int_lat_tmr_min; 5249 __le16 int_lat_tmr_max; 5250 __le16 num_cmpl_aggr_int; 5251 __le16 enables; 5252 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5253 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5254 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5255 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5256 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5257 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5258 u8 unused_0[4]; 5259 }; 5260 5261 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5262 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5263 __le16 error_code; 5264 __le16 req_type; 5265 __le16 seq_id; 5266 __le16 resp_len; 5267 u8 unused_0[7]; 5268 u8 valid; 5269 }; 5270 5271 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5272 struct hwrm_ring_grp_alloc_input { 5273 __le16 req_type; 5274 __le16 cmpl_ring; 5275 __le16 seq_id; 5276 __le16 target_id; 5277 __le64 resp_addr; 5278 __le16 cr; 5279 __le16 rr; 5280 __le16 ar; 5281 __le16 sc; 5282 }; 5283 5284 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5285 struct hwrm_ring_grp_alloc_output { 5286 __le16 error_code; 5287 __le16 req_type; 5288 __le16 seq_id; 5289 __le16 resp_len; 5290 __le32 ring_group_id; 5291 u8 unused_0[3]; 5292 u8 valid; 5293 }; 5294 5295 /* hwrm_ring_grp_free_input (size:192b/24B) */ 5296 struct hwrm_ring_grp_free_input { 5297 __le16 req_type; 5298 __le16 cmpl_ring; 5299 __le16 seq_id; 5300 __le16 target_id; 5301 __le64 resp_addr; 5302 __le32 ring_group_id; 5303 u8 unused_0[4]; 5304 }; 5305 5306 /* hwrm_ring_grp_free_output (size:128b/16B) */ 5307 struct hwrm_ring_grp_free_output { 5308 __le16 error_code; 5309 __le16 req_type; 5310 __le16 seq_id; 5311 __le16 resp_len; 5312 u8 unused_0[7]; 5313 u8 valid; 5314 }; 5315 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5316 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5317 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5318 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5319 5320 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5321 struct hwrm_cfa_l2_filter_alloc_input { 5322 __le16 req_type; 5323 __le16 cmpl_ring; 5324 __le16 seq_id; 5325 __le16 target_id; 5326 __le64 resp_addr; 5327 __le32 flags; 5328 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5329 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5330 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5331 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5332 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5333 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5334 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5335 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5336 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5337 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5338 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5339 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5340 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5341 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5342 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5343 __le32 enables; 5344 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5345 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5346 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5347 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5348 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5349 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5350 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5351 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5352 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5353 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5354 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5355 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5356 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5357 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5358 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5359 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5360 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5361 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 5362 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 5363 u8 l2_addr[6]; 5364 u8 num_vlans; 5365 u8 t_num_vlans; 5366 u8 l2_addr_mask[6]; 5367 __le16 l2_ovlan; 5368 __le16 l2_ovlan_mask; 5369 __le16 l2_ivlan; 5370 __le16 l2_ivlan_mask; 5371 u8 unused_1[2]; 5372 u8 t_l2_addr[6]; 5373 u8 unused_2[2]; 5374 u8 t_l2_addr_mask[6]; 5375 __le16 t_l2_ovlan; 5376 __le16 t_l2_ovlan_mask; 5377 __le16 t_l2_ivlan; 5378 __le16 t_l2_ivlan_mask; 5379 u8 src_type; 5380 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5381 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5382 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5383 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5384 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5385 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5386 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5387 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5388 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5389 u8 unused_3; 5390 __le32 src_id; 5391 u8 tunnel_type; 5392 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5393 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5394 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5395 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5396 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5397 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5398 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5399 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5400 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5401 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5402 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5403 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5404 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5405 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5406 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5407 u8 unused_4; 5408 __le16 dst_id; 5409 __le16 mirror_vnic_id; 5410 u8 pri_hint; 5411 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5412 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5413 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5414 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5415 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5416 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5417 u8 unused_5; 5418 __le32 unused_6; 5419 __le64 l2_filter_id_hint; 5420 }; 5421 5422 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5423 struct hwrm_cfa_l2_filter_alloc_output { 5424 __le16 error_code; 5425 __le16 req_type; 5426 __le16 seq_id; 5427 __le16 resp_len; 5428 __le64 l2_filter_id; 5429 __le32 flow_id; 5430 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5431 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5432 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5433 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5434 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5435 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5436 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5437 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5438 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5439 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5440 u8 unused_0[3]; 5441 u8 valid; 5442 }; 5443 5444 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5445 struct hwrm_cfa_l2_filter_free_input { 5446 __le16 req_type; 5447 __le16 cmpl_ring; 5448 __le16 seq_id; 5449 __le16 target_id; 5450 __le64 resp_addr; 5451 __le64 l2_filter_id; 5452 }; 5453 5454 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5455 struct hwrm_cfa_l2_filter_free_output { 5456 __le16 error_code; 5457 __le16 req_type; 5458 __le16 seq_id; 5459 __le16 resp_len; 5460 u8 unused_0[7]; 5461 u8 valid; 5462 }; 5463 5464 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5465 struct hwrm_cfa_l2_filter_cfg_input { 5466 __le16 req_type; 5467 __le16 cmpl_ring; 5468 __le16 seq_id; 5469 __le16 target_id; 5470 __le64 resp_addr; 5471 __le32 flags; 5472 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5473 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5474 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5475 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5476 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5477 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5478 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5479 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5480 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5481 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5482 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5483 __le32 enables; 5484 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5485 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5486 __le64 l2_filter_id; 5487 __le32 dst_id; 5488 __le32 new_mirror_vnic_id; 5489 }; 5490 5491 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5492 struct hwrm_cfa_l2_filter_cfg_output { 5493 __le16 error_code; 5494 __le16 req_type; 5495 __le16 seq_id; 5496 __le16 resp_len; 5497 u8 unused_0[7]; 5498 u8 valid; 5499 }; 5500 5501 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5502 struct hwrm_cfa_l2_set_rx_mask_input { 5503 __le16 req_type; 5504 __le16 cmpl_ring; 5505 __le16 seq_id; 5506 __le16 target_id; 5507 __le64 resp_addr; 5508 __le32 vnic_id; 5509 __le32 mask; 5510 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5511 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5512 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5513 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5514 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5515 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5516 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5517 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5518 __le64 mc_tbl_addr; 5519 __le32 num_mc_entries; 5520 u8 unused_0[4]; 5521 __le64 vlan_tag_tbl_addr; 5522 __le32 num_vlan_tags; 5523 u8 unused_1[4]; 5524 }; 5525 5526 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5527 struct hwrm_cfa_l2_set_rx_mask_output { 5528 __le16 error_code; 5529 __le16 req_type; 5530 __le16 seq_id; 5531 __le16 resp_len; 5532 u8 unused_0[7]; 5533 u8 valid; 5534 }; 5535 5536 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5537 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5538 u8 code; 5539 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5540 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5541 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5542 u8 unused_0[7]; 5543 }; 5544 5545 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5546 struct hwrm_cfa_tunnel_filter_alloc_input { 5547 __le16 req_type; 5548 __le16 cmpl_ring; 5549 __le16 seq_id; 5550 __le16 target_id; 5551 __le64 resp_addr; 5552 __le32 flags; 5553 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5554 __le32 enables; 5555 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5556 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5557 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5558 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5559 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5560 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5561 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5562 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5563 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5564 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5565 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5566 __le64 l2_filter_id; 5567 u8 l2_addr[6]; 5568 __le16 l2_ivlan; 5569 __le32 l3_addr[4]; 5570 __le32 t_l3_addr[4]; 5571 u8 l3_addr_type; 5572 u8 t_l3_addr_type; 5573 u8 tunnel_type; 5574 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5575 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5576 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5577 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5578 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5579 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5580 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5581 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5582 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5583 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5584 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5585 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5586 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5587 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5588 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5589 u8 tunnel_flags; 5590 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5591 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5592 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5593 __le32 vni; 5594 __le32 dst_vnic_id; 5595 __le32 mirror_vnic_id; 5596 }; 5597 5598 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5599 struct hwrm_cfa_tunnel_filter_alloc_output { 5600 __le16 error_code; 5601 __le16 req_type; 5602 __le16 seq_id; 5603 __le16 resp_len; 5604 __le64 tunnel_filter_id; 5605 __le32 flow_id; 5606 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5607 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5608 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5609 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5610 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5611 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5612 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5613 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5614 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5615 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5616 u8 unused_0[3]; 5617 u8 valid; 5618 }; 5619 5620 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5621 struct hwrm_cfa_tunnel_filter_free_input { 5622 __le16 req_type; 5623 __le16 cmpl_ring; 5624 __le16 seq_id; 5625 __le16 target_id; 5626 __le64 resp_addr; 5627 __le64 tunnel_filter_id; 5628 }; 5629 5630 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5631 struct hwrm_cfa_tunnel_filter_free_output { 5632 __le16 error_code; 5633 __le16 req_type; 5634 __le16 seq_id; 5635 __le16 resp_len; 5636 u8 unused_0[7]; 5637 u8 valid; 5638 }; 5639 5640 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5641 struct hwrm_vxlan_ipv4_hdr { 5642 u8 ver_hlen; 5643 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5644 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5645 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5646 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 5647 u8 tos; 5648 __be16 ip_id; 5649 __be16 flags_frag_offset; 5650 u8 ttl; 5651 u8 protocol; 5652 __be32 src_ip_addr; 5653 __be32 dest_ip_addr; 5654 }; 5655 5656 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 5657 struct hwrm_vxlan_ipv6_hdr { 5658 __be32 ver_tc_flow_label; 5659 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 5660 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 5661 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 5662 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 5663 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 5664 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 5665 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 5666 __be16 payload_len; 5667 u8 next_hdr; 5668 u8 ttl; 5669 __be32 src_ip_addr[4]; 5670 __be32 dest_ip_addr[4]; 5671 }; 5672 5673 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 5674 struct hwrm_cfa_encap_data_vxlan { 5675 u8 src_mac_addr[6]; 5676 __le16 unused_0; 5677 u8 dst_mac_addr[6]; 5678 u8 num_vlan_tags; 5679 u8 unused_1; 5680 __be16 ovlan_tpid; 5681 __be16 ovlan_tci; 5682 __be16 ivlan_tpid; 5683 __be16 ivlan_tci; 5684 __le32 l3[10]; 5685 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 5686 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 5687 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 5688 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 5689 __be16 src_port; 5690 __be16 dst_port; 5691 __be32 vni; 5692 u8 hdr_rsvd0[3]; 5693 u8 hdr_rsvd1; 5694 u8 hdr_flags; 5695 u8 unused[3]; 5696 }; 5697 5698 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 5699 struct hwrm_cfa_encap_record_alloc_input { 5700 __le16 req_type; 5701 __le16 cmpl_ring; 5702 __le16 seq_id; 5703 __le16 target_id; 5704 __le64 resp_addr; 5705 __le32 flags; 5706 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5707 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 5708 u8 encap_type; 5709 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 5710 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 5711 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 5712 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 5713 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 5714 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 5715 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 5716 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 5717 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 5718 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 5719 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 5720 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 5721 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 5722 u8 unused_0[3]; 5723 __le32 encap_data[20]; 5724 }; 5725 5726 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 5727 struct hwrm_cfa_encap_record_alloc_output { 5728 __le16 error_code; 5729 __le16 req_type; 5730 __le16 seq_id; 5731 __le16 resp_len; 5732 __le32 encap_record_id; 5733 u8 unused_0[3]; 5734 u8 valid; 5735 }; 5736 5737 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 5738 struct hwrm_cfa_encap_record_free_input { 5739 __le16 req_type; 5740 __le16 cmpl_ring; 5741 __le16 seq_id; 5742 __le16 target_id; 5743 __le64 resp_addr; 5744 __le32 encap_record_id; 5745 u8 unused_0[4]; 5746 }; 5747 5748 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 5749 struct hwrm_cfa_encap_record_free_output { 5750 __le16 error_code; 5751 __le16 req_type; 5752 __le16 seq_id; 5753 __le16 resp_len; 5754 u8 unused_0[7]; 5755 u8 valid; 5756 }; 5757 5758 /* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */ 5759 struct hwrm_cfa_ntuple_filter_alloc_input { 5760 __le16 req_type; 5761 __le16 cmpl_ring; 5762 __le16 seq_id; 5763 __le16 target_id; 5764 __le64 resp_addr; 5765 __le32 flags; 5766 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5767 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 5768 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 5769 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 5770 __le32 enables; 5771 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5772 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 5773 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 5774 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 5775 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 5776 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 5777 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 5778 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 5779 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 5780 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 5781 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 5782 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 5783 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 5784 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 5785 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 5786 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 5787 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 5788 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 5789 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 5790 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 5791 __le64 l2_filter_id; 5792 u8 src_macaddr[6]; 5793 __be16 ethertype; 5794 u8 ip_addr_type; 5795 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5796 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5797 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5798 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5799 u8 ip_protocol; 5800 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5801 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5802 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5803 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5804 __le16 dst_id; 5805 __le16 mirror_vnic_id; 5806 u8 tunnel_type; 5807 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5808 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5809 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5810 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5811 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5812 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5813 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5814 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5815 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5816 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5817 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5818 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5819 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5820 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5821 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5822 u8 pri_hint; 5823 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5824 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 5825 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 5826 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 5827 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 5828 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 5829 __be32 src_ipaddr[4]; 5830 __be32 src_ipaddr_mask[4]; 5831 __be32 dst_ipaddr[4]; 5832 __be32 dst_ipaddr_mask[4]; 5833 __be16 src_port; 5834 __be16 src_port_mask; 5835 __be16 dst_port; 5836 __be16 dst_port_mask; 5837 __le64 ntuple_filter_id_hint; 5838 __le16 rfs_ring_tbl_idx; 5839 u8 unused_0[6]; 5840 }; 5841 5842 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 5843 struct hwrm_cfa_ntuple_filter_alloc_output { 5844 __le16 error_code; 5845 __le16 req_type; 5846 __le16 seq_id; 5847 __le16 resp_len; 5848 __le64 ntuple_filter_id; 5849 __le32 flow_id; 5850 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5851 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5852 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5853 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5854 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5855 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5856 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5857 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5858 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5859 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5860 u8 unused_0[3]; 5861 u8 valid; 5862 }; 5863 5864 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 5865 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 5866 u8 code; 5867 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 5868 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 5869 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 5870 u8 unused_0[7]; 5871 }; 5872 5873 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 5874 struct hwrm_cfa_ntuple_filter_free_input { 5875 __le16 req_type; 5876 __le16 cmpl_ring; 5877 __le16 seq_id; 5878 __le16 target_id; 5879 __le64 resp_addr; 5880 __le64 ntuple_filter_id; 5881 }; 5882 5883 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 5884 struct hwrm_cfa_ntuple_filter_free_output { 5885 __le16 error_code; 5886 __le16 req_type; 5887 __le16 seq_id; 5888 __le16 resp_len; 5889 u8 unused_0[7]; 5890 u8 valid; 5891 }; 5892 5893 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 5894 struct hwrm_cfa_ntuple_filter_cfg_input { 5895 __le16 req_type; 5896 __le16 cmpl_ring; 5897 __le16 seq_id; 5898 __le16 target_id; 5899 __le64 resp_addr; 5900 __le32 enables; 5901 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 5902 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5903 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 5904 __le32 flags; 5905 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 5906 __le64 ntuple_filter_id; 5907 __le32 new_dst_id; 5908 __le32 new_mirror_vnic_id; 5909 __le16 new_meter_instance_id; 5910 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 5911 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 5912 u8 unused_1[6]; 5913 }; 5914 5915 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 5916 struct hwrm_cfa_ntuple_filter_cfg_output { 5917 __le16 error_code; 5918 __le16 req_type; 5919 __le16 seq_id; 5920 __le16 resp_len; 5921 u8 unused_0[7]; 5922 u8 valid; 5923 }; 5924 5925 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 5926 struct hwrm_cfa_decap_filter_alloc_input { 5927 __le16 req_type; 5928 __le16 cmpl_ring; 5929 __le16 seq_id; 5930 __le16 target_id; 5931 __le64 resp_addr; 5932 __le32 flags; 5933 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 5934 __le32 enables; 5935 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 5936 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 5937 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 5938 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 5939 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 5940 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 5941 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 5942 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 5943 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 5944 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 5945 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 5946 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 5947 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 5948 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 5949 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 5950 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5951 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5952 __be32 tunnel_id; 5953 u8 tunnel_type; 5954 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5955 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5956 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5957 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5958 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5959 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5960 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5961 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5962 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5963 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5964 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5965 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5966 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5967 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5968 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5969 u8 unused_0; 5970 __le16 unused_1; 5971 u8 src_macaddr[6]; 5972 u8 unused_2[2]; 5973 u8 dst_macaddr[6]; 5974 __be16 ovlan_vid; 5975 __be16 ivlan_vid; 5976 __be16 t_ovlan_vid; 5977 __be16 t_ivlan_vid; 5978 __be16 ethertype; 5979 u8 ip_addr_type; 5980 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5981 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5982 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5983 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5984 u8 ip_protocol; 5985 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5986 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5987 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5988 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5989 __le16 unused_3; 5990 __le32 unused_4; 5991 __be32 src_ipaddr[4]; 5992 __be32 dst_ipaddr[4]; 5993 __be16 src_port; 5994 __be16 dst_port; 5995 __le16 dst_id; 5996 __le16 l2_ctxt_ref_id; 5997 }; 5998 5999 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6000 struct hwrm_cfa_decap_filter_alloc_output { 6001 __le16 error_code; 6002 __le16 req_type; 6003 __le16 seq_id; 6004 __le16 resp_len; 6005 __le32 decap_filter_id; 6006 u8 unused_0[3]; 6007 u8 valid; 6008 }; 6009 6010 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6011 struct hwrm_cfa_decap_filter_free_input { 6012 __le16 req_type; 6013 __le16 cmpl_ring; 6014 __le16 seq_id; 6015 __le16 target_id; 6016 __le64 resp_addr; 6017 __le32 decap_filter_id; 6018 u8 unused_0[4]; 6019 }; 6020 6021 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6022 struct hwrm_cfa_decap_filter_free_output { 6023 __le16 error_code; 6024 __le16 req_type; 6025 __le16 seq_id; 6026 __le16 resp_len; 6027 u8 unused_0[7]; 6028 u8 valid; 6029 }; 6030 6031 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6032 struct hwrm_cfa_flow_alloc_input { 6033 __le16 req_type; 6034 __le16 cmpl_ring; 6035 __le16 seq_id; 6036 __le16 target_id; 6037 __le64 resp_addr; 6038 __le16 flags; 6039 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6040 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6041 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6042 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6043 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6044 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6045 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6046 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6047 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6048 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6049 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6050 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6051 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6052 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6053 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6054 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6055 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6056 __le16 src_fid; 6057 __le32 tunnel_handle; 6058 __le16 action_flags; 6059 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6060 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6061 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6062 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6063 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6064 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6065 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6066 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6067 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6068 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6069 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6070 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6071 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6072 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6073 __le16 dst_fid; 6074 __be16 l2_rewrite_vlan_tpid; 6075 __be16 l2_rewrite_vlan_tci; 6076 __le16 act_meter_id; 6077 __le16 ref_flow_handle; 6078 __be16 ethertype; 6079 __be16 outer_vlan_tci; 6080 __be16 dmac[3]; 6081 __be16 inner_vlan_tci; 6082 __be16 smac[3]; 6083 u8 ip_dst_mask_len; 6084 u8 ip_src_mask_len; 6085 __be32 ip_dst[4]; 6086 __be32 ip_src[4]; 6087 __be16 l4_src_port; 6088 __be16 l4_src_port_mask; 6089 __be16 l4_dst_port; 6090 __be16 l4_dst_port_mask; 6091 __be32 nat_ip_address[4]; 6092 __be16 l2_rewrite_dmac[3]; 6093 __be16 nat_port; 6094 __be16 l2_rewrite_smac[3]; 6095 u8 ip_proto; 6096 u8 tunnel_type; 6097 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6098 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6099 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6100 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6101 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6102 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6103 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6104 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6105 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6106 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6107 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6108 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6109 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6110 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6111 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6112 }; 6113 6114 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6115 struct hwrm_cfa_flow_alloc_output { 6116 __le16 error_code; 6117 __le16 req_type; 6118 __le16 seq_id; 6119 __le16 resp_len; 6120 __le16 flow_handle; 6121 u8 unused_0[2]; 6122 __le32 flow_id; 6123 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6124 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6125 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6126 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6127 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6128 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6129 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6130 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6131 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6132 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6133 __le64 ext_flow_handle; 6134 __le32 flow_counter_id; 6135 u8 unused_1[3]; 6136 u8 valid; 6137 }; 6138 6139 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6140 struct hwrm_cfa_flow_alloc_cmd_err { 6141 u8 code; 6142 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6143 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6144 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6145 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6146 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6147 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6148 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6149 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6150 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6151 u8 unused_0[7]; 6152 }; 6153 6154 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6155 struct hwrm_cfa_flow_free_input { 6156 __le16 req_type; 6157 __le16 cmpl_ring; 6158 __le16 seq_id; 6159 __le16 target_id; 6160 __le64 resp_addr; 6161 __le16 flow_handle; 6162 __le16 unused_0; 6163 __le32 flow_counter_id; 6164 __le64 ext_flow_handle; 6165 }; 6166 6167 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6168 struct hwrm_cfa_flow_free_output { 6169 __le16 error_code; 6170 __le16 req_type; 6171 __le16 seq_id; 6172 __le16 resp_len; 6173 __le64 packet; 6174 __le64 byte; 6175 u8 unused_0[7]; 6176 u8 valid; 6177 }; 6178 6179 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6180 struct hwrm_cfa_flow_info_input { 6181 __le16 req_type; 6182 __le16 cmpl_ring; 6183 __le16 seq_id; 6184 __le16 target_id; 6185 __le64 resp_addr; 6186 __le16 flow_handle; 6187 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6188 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6189 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6190 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6191 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6192 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6193 u8 unused_0[6]; 6194 __le64 ext_flow_handle; 6195 }; 6196 6197 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6198 struct hwrm_cfa_flow_info_output { 6199 __le16 error_code; 6200 __le16 req_type; 6201 __le16 seq_id; 6202 __le16 resp_len; 6203 u8 flags; 6204 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6205 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6206 u8 profile; 6207 __le16 src_fid; 6208 __le16 dst_fid; 6209 __le16 l2_ctxt_id; 6210 __le64 em_info; 6211 __le64 tcam_info; 6212 __le64 vfp_tcam_info; 6213 __le16 ar_id; 6214 __le16 flow_handle; 6215 __le32 tunnel_handle; 6216 __le16 flow_timer; 6217 u8 unused_0[6]; 6218 __le32 flow_key_data[130]; 6219 __le32 flow_action_info[30]; 6220 u8 unused_1[7]; 6221 u8 valid; 6222 }; 6223 6224 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6225 struct hwrm_cfa_flow_stats_input { 6226 __le16 req_type; 6227 __le16 cmpl_ring; 6228 __le16 seq_id; 6229 __le16 target_id; 6230 __le64 resp_addr; 6231 __le16 num_flows; 6232 __le16 flow_handle_0; 6233 __le16 flow_handle_1; 6234 __le16 flow_handle_2; 6235 __le16 flow_handle_3; 6236 __le16 flow_handle_4; 6237 __le16 flow_handle_5; 6238 __le16 flow_handle_6; 6239 __le16 flow_handle_7; 6240 __le16 flow_handle_8; 6241 __le16 flow_handle_9; 6242 u8 unused_0[2]; 6243 __le32 flow_id_0; 6244 __le32 flow_id_1; 6245 __le32 flow_id_2; 6246 __le32 flow_id_3; 6247 __le32 flow_id_4; 6248 __le32 flow_id_5; 6249 __le32 flow_id_6; 6250 __le32 flow_id_7; 6251 __le32 flow_id_8; 6252 __le32 flow_id_9; 6253 }; 6254 6255 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6256 struct hwrm_cfa_flow_stats_output { 6257 __le16 error_code; 6258 __le16 req_type; 6259 __le16 seq_id; 6260 __le16 resp_len; 6261 __le64 packet_0; 6262 __le64 packet_1; 6263 __le64 packet_2; 6264 __le64 packet_3; 6265 __le64 packet_4; 6266 __le64 packet_5; 6267 __le64 packet_6; 6268 __le64 packet_7; 6269 __le64 packet_8; 6270 __le64 packet_9; 6271 __le64 byte_0; 6272 __le64 byte_1; 6273 __le64 byte_2; 6274 __le64 byte_3; 6275 __le64 byte_4; 6276 __le64 byte_5; 6277 __le64 byte_6; 6278 __le64 byte_7; 6279 __le64 byte_8; 6280 __le64 byte_9; 6281 u8 unused_0[7]; 6282 u8 valid; 6283 }; 6284 6285 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6286 struct hwrm_cfa_vfr_alloc_input { 6287 __le16 req_type; 6288 __le16 cmpl_ring; 6289 __le16 seq_id; 6290 __le16 target_id; 6291 __le64 resp_addr; 6292 __le16 vf_id; 6293 __le16 reserved; 6294 u8 unused_0[4]; 6295 char vfr_name[32]; 6296 }; 6297 6298 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6299 struct hwrm_cfa_vfr_alloc_output { 6300 __le16 error_code; 6301 __le16 req_type; 6302 __le16 seq_id; 6303 __le16 resp_len; 6304 __le16 rx_cfa_code; 6305 __le16 tx_cfa_action; 6306 u8 unused_0[3]; 6307 u8 valid; 6308 }; 6309 6310 /* hwrm_cfa_vfr_free_input (size:384b/48B) */ 6311 struct hwrm_cfa_vfr_free_input { 6312 __le16 req_type; 6313 __le16 cmpl_ring; 6314 __le16 seq_id; 6315 __le16 target_id; 6316 __le64 resp_addr; 6317 char vfr_name[32]; 6318 }; 6319 6320 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6321 struct hwrm_cfa_vfr_free_output { 6322 __le16 error_code; 6323 __le16 req_type; 6324 __le16 seq_id; 6325 __le16 resp_len; 6326 u8 unused_0[7]; 6327 u8 valid; 6328 }; 6329 6330 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6331 struct hwrm_cfa_eem_qcaps_input { 6332 __le16 req_type; 6333 __le16 cmpl_ring; 6334 __le16 seq_id; 6335 __le16 target_id; 6336 __le64 resp_addr; 6337 __le32 flags; 6338 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6339 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6340 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6341 __le32 unused_0; 6342 }; 6343 6344 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 6345 struct hwrm_cfa_eem_qcaps_output { 6346 __le16 error_code; 6347 __le16 req_type; 6348 __le16 seq_id; 6349 __le16 resp_len; 6350 __le32 flags; 6351 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6352 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6353 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 6354 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 6355 __le32 unused_0; 6356 __le32 supported; 6357 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6358 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6359 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6360 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6361 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 6362 __le32 max_entries_supported; 6363 __le16 key_entry_size; 6364 __le16 record_entry_size; 6365 __le16 efc_entry_size; 6366 __le16 fid_entry_size; 6367 u8 unused_1[7]; 6368 u8 valid; 6369 }; 6370 6371 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 6372 struct hwrm_cfa_eem_cfg_input { 6373 __le16 req_type; 6374 __le16 cmpl_ring; 6375 __le16 seq_id; 6376 __le16 target_id; 6377 __le64 resp_addr; 6378 __le32 flags; 6379 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6380 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6381 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6382 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 6383 __le16 group_id; 6384 __le16 unused_0; 6385 __le32 num_entries; 6386 __le32 unused_1; 6387 __le16 key0_ctx_id; 6388 __le16 key1_ctx_id; 6389 __le16 record_ctx_id; 6390 __le16 efc_ctx_id; 6391 __le16 fid_ctx_id; 6392 __le16 unused_2; 6393 __le32 unused_3; 6394 }; 6395 6396 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6397 struct hwrm_cfa_eem_cfg_output { 6398 __le16 error_code; 6399 __le16 req_type; 6400 __le16 seq_id; 6401 __le16 resp_len; 6402 u8 unused_0[7]; 6403 u8 valid; 6404 }; 6405 6406 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6407 struct hwrm_cfa_eem_qcfg_input { 6408 __le16 req_type; 6409 __le16 cmpl_ring; 6410 __le16 seq_id; 6411 __le16 target_id; 6412 __le64 resp_addr; 6413 __le32 flags; 6414 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6415 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6416 __le32 unused_0; 6417 }; 6418 6419 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 6420 struct hwrm_cfa_eem_qcfg_output { 6421 __le16 error_code; 6422 __le16 req_type; 6423 __le16 seq_id; 6424 __le16 resp_len; 6425 __le32 flags; 6426 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6427 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6428 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6429 __le32 num_entries; 6430 __le16 key0_ctx_id; 6431 __le16 key1_ctx_id; 6432 __le16 record_ctx_id; 6433 __le16 efc_ctx_id; 6434 __le16 fid_ctx_id; 6435 u8 unused_2[5]; 6436 u8 valid; 6437 }; 6438 6439 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 6440 struct hwrm_cfa_eem_op_input { 6441 __le16 req_type; 6442 __le16 cmpl_ring; 6443 __le16 seq_id; 6444 __le16 target_id; 6445 __le64 resp_addr; 6446 __le32 flags; 6447 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6448 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6449 __le16 unused_0; 6450 __le16 op; 6451 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6452 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6453 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6454 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6455 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6456 }; 6457 6458 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 6459 struct hwrm_cfa_eem_op_output { 6460 __le16 error_code; 6461 __le16 req_type; 6462 __le16 seq_id; 6463 __le16 resp_len; 6464 u8 unused_0[7]; 6465 u8 valid; 6466 }; 6467 6468 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 6469 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 6470 __le16 req_type; 6471 __le16 cmpl_ring; 6472 __le16 seq_id; 6473 __le16 target_id; 6474 __le64 resp_addr; 6475 __le32 unused_0[4]; 6476 }; 6477 6478 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 6479 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 6480 __le16 error_code; 6481 __le16 req_type; 6482 __le16 seq_id; 6483 __le16 resp_len; 6484 __le32 flags; 6485 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6486 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6487 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6488 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6489 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6490 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6491 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6492 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6493 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 6494 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 6495 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 6496 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 6497 u8 unused_0[3]; 6498 u8 valid; 6499 }; 6500 6501 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6502 struct hwrm_tunnel_dst_port_query_input { 6503 __le16 req_type; 6504 __le16 cmpl_ring; 6505 __le16 seq_id; 6506 __le16 target_id; 6507 __le64 resp_addr; 6508 u8 tunnel_type; 6509 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6510 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6511 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6512 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6513 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6514 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6515 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6516 u8 unused_0[7]; 6517 }; 6518 6519 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 6520 struct hwrm_tunnel_dst_port_query_output { 6521 __le16 error_code; 6522 __le16 req_type; 6523 __le16 seq_id; 6524 __le16 resp_len; 6525 __le16 tunnel_dst_port_id; 6526 __be16 tunnel_dst_port_val; 6527 u8 unused_0[3]; 6528 u8 valid; 6529 }; 6530 6531 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 6532 struct hwrm_tunnel_dst_port_alloc_input { 6533 __le16 req_type; 6534 __le16 cmpl_ring; 6535 __le16 seq_id; 6536 __le16 target_id; 6537 __le64 resp_addr; 6538 u8 tunnel_type; 6539 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6540 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6541 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6542 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6543 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6544 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6545 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6546 u8 unused_0; 6547 __be16 tunnel_dst_port_val; 6548 u8 unused_1[4]; 6549 }; 6550 6551 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 6552 struct hwrm_tunnel_dst_port_alloc_output { 6553 __le16 error_code; 6554 __le16 req_type; 6555 __le16 seq_id; 6556 __le16 resp_len; 6557 __le16 tunnel_dst_port_id; 6558 u8 unused_0[5]; 6559 u8 valid; 6560 }; 6561 6562 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 6563 struct hwrm_tunnel_dst_port_free_input { 6564 __le16 req_type; 6565 __le16 cmpl_ring; 6566 __le16 seq_id; 6567 __le16 target_id; 6568 __le64 resp_addr; 6569 u8 tunnel_type; 6570 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6571 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6572 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6573 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6574 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6575 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6576 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6577 u8 unused_0; 6578 __le16 tunnel_dst_port_id; 6579 u8 unused_1[4]; 6580 }; 6581 6582 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 6583 struct hwrm_tunnel_dst_port_free_output { 6584 __le16 error_code; 6585 __le16 req_type; 6586 __le16 seq_id; 6587 __le16 resp_len; 6588 u8 unused_1[7]; 6589 u8 valid; 6590 }; 6591 6592 /* ctx_hw_stats (size:1280b/160B) */ 6593 struct ctx_hw_stats { 6594 __le64 rx_ucast_pkts; 6595 __le64 rx_mcast_pkts; 6596 __le64 rx_bcast_pkts; 6597 __le64 rx_discard_pkts; 6598 __le64 rx_drop_pkts; 6599 __le64 rx_ucast_bytes; 6600 __le64 rx_mcast_bytes; 6601 __le64 rx_bcast_bytes; 6602 __le64 tx_ucast_pkts; 6603 __le64 tx_mcast_pkts; 6604 __le64 tx_bcast_pkts; 6605 __le64 tx_discard_pkts; 6606 __le64 tx_drop_pkts; 6607 __le64 tx_ucast_bytes; 6608 __le64 tx_mcast_bytes; 6609 __le64 tx_bcast_bytes; 6610 __le64 tpa_pkts; 6611 __le64 tpa_bytes; 6612 __le64 tpa_events; 6613 __le64 tpa_aborts; 6614 }; 6615 6616 /* ctx_hw_stats_ext (size:1344b/168B) */ 6617 struct ctx_hw_stats_ext { 6618 __le64 rx_ucast_pkts; 6619 __le64 rx_mcast_pkts; 6620 __le64 rx_bcast_pkts; 6621 __le64 rx_discard_pkts; 6622 __le64 rx_drop_pkts; 6623 __le64 rx_ucast_bytes; 6624 __le64 rx_mcast_bytes; 6625 __le64 rx_bcast_bytes; 6626 __le64 tx_ucast_pkts; 6627 __le64 tx_mcast_pkts; 6628 __le64 tx_bcast_pkts; 6629 __le64 tx_discard_pkts; 6630 __le64 tx_drop_pkts; 6631 __le64 tx_ucast_bytes; 6632 __le64 tx_mcast_bytes; 6633 __le64 tx_bcast_bytes; 6634 __le64 rx_tpa_eligible_pkt; 6635 __le64 rx_tpa_eligible_bytes; 6636 __le64 rx_tpa_pkt; 6637 __le64 rx_tpa_bytes; 6638 __le64 rx_tpa_errors; 6639 }; 6640 6641 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 6642 struct hwrm_stat_ctx_alloc_input { 6643 __le16 req_type; 6644 __le16 cmpl_ring; 6645 __le16 seq_id; 6646 __le16 target_id; 6647 __le64 resp_addr; 6648 __le64 stats_dma_addr; 6649 __le32 update_period_ms; 6650 u8 stat_ctx_flags; 6651 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 6652 u8 unused_0; 6653 __le16 stats_dma_length; 6654 }; 6655 6656 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 6657 struct hwrm_stat_ctx_alloc_output { 6658 __le16 error_code; 6659 __le16 req_type; 6660 __le16 seq_id; 6661 __le16 resp_len; 6662 __le32 stat_ctx_id; 6663 u8 unused_0[3]; 6664 u8 valid; 6665 }; 6666 6667 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 6668 struct hwrm_stat_ctx_free_input { 6669 __le16 req_type; 6670 __le16 cmpl_ring; 6671 __le16 seq_id; 6672 __le16 target_id; 6673 __le64 resp_addr; 6674 __le32 stat_ctx_id; 6675 u8 unused_0[4]; 6676 }; 6677 6678 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 6679 struct hwrm_stat_ctx_free_output { 6680 __le16 error_code; 6681 __le16 req_type; 6682 __le16 seq_id; 6683 __le16 resp_len; 6684 __le32 stat_ctx_id; 6685 u8 unused_0[3]; 6686 u8 valid; 6687 }; 6688 6689 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 6690 struct hwrm_stat_ctx_query_input { 6691 __le16 req_type; 6692 __le16 cmpl_ring; 6693 __le16 seq_id; 6694 __le16 target_id; 6695 __le64 resp_addr; 6696 __le32 stat_ctx_id; 6697 u8 unused_0[4]; 6698 }; 6699 6700 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 6701 struct hwrm_stat_ctx_query_output { 6702 __le16 error_code; 6703 __le16 req_type; 6704 __le16 seq_id; 6705 __le16 resp_len; 6706 __le64 tx_ucast_pkts; 6707 __le64 tx_mcast_pkts; 6708 __le64 tx_bcast_pkts; 6709 __le64 tx_err_pkts; 6710 __le64 tx_drop_pkts; 6711 __le64 tx_ucast_bytes; 6712 __le64 tx_mcast_bytes; 6713 __le64 tx_bcast_bytes; 6714 __le64 rx_ucast_pkts; 6715 __le64 rx_mcast_pkts; 6716 __le64 rx_bcast_pkts; 6717 __le64 rx_err_pkts; 6718 __le64 rx_drop_pkts; 6719 __le64 rx_ucast_bytes; 6720 __le64 rx_mcast_bytes; 6721 __le64 rx_bcast_bytes; 6722 __le64 rx_agg_pkts; 6723 __le64 rx_agg_bytes; 6724 __le64 rx_agg_events; 6725 __le64 rx_agg_aborts; 6726 u8 unused_0[7]; 6727 u8 valid; 6728 }; 6729 6730 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 6731 struct hwrm_stat_ctx_clr_stats_input { 6732 __le16 req_type; 6733 __le16 cmpl_ring; 6734 __le16 seq_id; 6735 __le16 target_id; 6736 __le64 resp_addr; 6737 __le32 stat_ctx_id; 6738 u8 unused_0[4]; 6739 }; 6740 6741 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 6742 struct hwrm_stat_ctx_clr_stats_output { 6743 __le16 error_code; 6744 __le16 req_type; 6745 __le16 seq_id; 6746 __le16 resp_len; 6747 u8 unused_0[7]; 6748 u8 valid; 6749 }; 6750 6751 /* hwrm_pcie_qstats_input (size:256b/32B) */ 6752 struct hwrm_pcie_qstats_input { 6753 __le16 req_type; 6754 __le16 cmpl_ring; 6755 __le16 seq_id; 6756 __le16 target_id; 6757 __le64 resp_addr; 6758 __le16 pcie_stat_size; 6759 u8 unused_0[6]; 6760 __le64 pcie_stat_host_addr; 6761 }; 6762 6763 /* hwrm_pcie_qstats_output (size:128b/16B) */ 6764 struct hwrm_pcie_qstats_output { 6765 __le16 error_code; 6766 __le16 req_type; 6767 __le16 seq_id; 6768 __le16 resp_len; 6769 __le16 pcie_stat_size; 6770 u8 unused_0[5]; 6771 u8 valid; 6772 }; 6773 6774 /* pcie_ctx_hw_stats (size:768b/96B) */ 6775 struct pcie_ctx_hw_stats { 6776 __le64 pcie_pl_signal_integrity; 6777 __le64 pcie_dl_signal_integrity; 6778 __le64 pcie_tl_signal_integrity; 6779 __le64 pcie_link_integrity; 6780 __le64 pcie_tx_traffic_rate; 6781 __le64 pcie_rx_traffic_rate; 6782 __le64 pcie_tx_dllp_statistics; 6783 __le64 pcie_rx_dllp_statistics; 6784 __le64 pcie_equalization_time; 6785 __le32 pcie_ltssm_histogram[4]; 6786 __le64 pcie_recovery_histogram; 6787 }; 6788 6789 /* hwrm_fw_reset_input (size:192b/24B) */ 6790 struct hwrm_fw_reset_input { 6791 __le16 req_type; 6792 __le16 cmpl_ring; 6793 __le16 seq_id; 6794 __le16 target_id; 6795 __le64 resp_addr; 6796 u8 embedded_proc_type; 6797 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6798 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6799 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6800 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6801 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6802 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6803 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6804 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 6805 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 6806 u8 selfrst_status; 6807 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 6808 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 6809 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6810 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6811 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 6812 u8 host_idx; 6813 u8 flags; 6814 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 6815 u8 unused_0[4]; 6816 }; 6817 6818 /* hwrm_fw_reset_output (size:128b/16B) */ 6819 struct hwrm_fw_reset_output { 6820 __le16 error_code; 6821 __le16 req_type; 6822 __le16 seq_id; 6823 __le16 resp_len; 6824 u8 selfrst_status; 6825 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6826 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6827 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6828 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6829 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 6830 u8 unused_0[6]; 6831 u8 valid; 6832 }; 6833 6834 /* hwrm_fw_qstatus_input (size:192b/24B) */ 6835 struct hwrm_fw_qstatus_input { 6836 __le16 req_type; 6837 __le16 cmpl_ring; 6838 __le16 seq_id; 6839 __le16 target_id; 6840 __le64 resp_addr; 6841 u8 embedded_proc_type; 6842 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6843 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6844 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6845 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6846 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6847 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6848 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6849 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 6850 u8 unused_0[7]; 6851 }; 6852 6853 /* hwrm_fw_qstatus_output (size:128b/16B) */ 6854 struct hwrm_fw_qstatus_output { 6855 __le16 error_code; 6856 __le16 req_type; 6857 __le16 seq_id; 6858 __le16 resp_len; 6859 u8 selfrst_status; 6860 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6861 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6862 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6863 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 6864 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 6865 u8 unused_0[6]; 6866 u8 valid; 6867 }; 6868 6869 /* hwrm_fw_set_time_input (size:256b/32B) */ 6870 struct hwrm_fw_set_time_input { 6871 __le16 req_type; 6872 __le16 cmpl_ring; 6873 __le16 seq_id; 6874 __le16 target_id; 6875 __le64 resp_addr; 6876 __le16 year; 6877 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 6878 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 6879 u8 month; 6880 u8 day; 6881 u8 hour; 6882 u8 minute; 6883 u8 second; 6884 u8 unused_0; 6885 __le16 millisecond; 6886 __le16 zone; 6887 #define FW_SET_TIME_REQ_ZONE_UTC 0 6888 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 6889 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 6890 u8 unused_1[4]; 6891 }; 6892 6893 /* hwrm_fw_set_time_output (size:128b/16B) */ 6894 struct hwrm_fw_set_time_output { 6895 __le16 error_code; 6896 __le16 req_type; 6897 __le16 seq_id; 6898 __le16 resp_len; 6899 u8 unused_0[7]; 6900 u8 valid; 6901 }; 6902 6903 /* hwrm_struct_hdr (size:128b/16B) */ 6904 struct hwrm_struct_hdr { 6905 __le16 struct_id; 6906 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6907 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6908 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6909 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6910 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6911 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6912 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6913 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 6914 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6915 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6916 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6917 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 6918 __le16 len; 6919 u8 version; 6920 u8 count; 6921 __le16 subtype; 6922 __le16 next_offset; 6923 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6924 u8 unused_0[6]; 6925 }; 6926 6927 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 6928 struct hwrm_struct_data_dcbx_app { 6929 __be16 protocol_id; 6930 u8 protocol_selector; 6931 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6932 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6933 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6934 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6935 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 6936 u8 priority; 6937 u8 valid; 6938 u8 unused_0[3]; 6939 }; 6940 6941 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 6942 struct hwrm_fw_set_structured_data_input { 6943 __le16 req_type; 6944 __le16 cmpl_ring; 6945 __le16 seq_id; 6946 __le16 target_id; 6947 __le64 resp_addr; 6948 __le64 src_data_addr; 6949 __le16 data_len; 6950 u8 hdr_cnt; 6951 u8 unused_0[5]; 6952 }; 6953 6954 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 6955 struct hwrm_fw_set_structured_data_output { 6956 __le16 error_code; 6957 __le16 req_type; 6958 __le16 seq_id; 6959 __le16 resp_len; 6960 u8 unused_0[7]; 6961 u8 valid; 6962 }; 6963 6964 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 6965 struct hwrm_fw_set_structured_data_cmd_err { 6966 u8 code; 6967 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6968 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 6969 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 6970 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6971 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6972 u8 unused_0[7]; 6973 }; 6974 6975 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 6976 struct hwrm_fw_get_structured_data_input { 6977 __le16 req_type; 6978 __le16 cmpl_ring; 6979 __le16 seq_id; 6980 __le16 target_id; 6981 __le64 resp_addr; 6982 __le64 dest_data_addr; 6983 __le16 data_len; 6984 __le16 structure_id; 6985 __le16 subtype; 6986 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 6987 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 6988 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 6989 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 6990 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 6991 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 6992 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 6993 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 6994 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 6995 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 6996 u8 count; 6997 u8 unused_0; 6998 }; 6999 7000 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7001 struct hwrm_fw_get_structured_data_output { 7002 __le16 error_code; 7003 __le16 req_type; 7004 __le16 seq_id; 7005 __le16 resp_len; 7006 u8 hdr_cnt; 7007 u8 unused_0[6]; 7008 u8 valid; 7009 }; 7010 7011 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7012 struct hwrm_fw_get_structured_data_cmd_err { 7013 u8 code; 7014 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7015 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7016 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7017 u8 unused_0[7]; 7018 }; 7019 7020 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7021 struct hwrm_exec_fwd_resp_input { 7022 __le16 req_type; 7023 __le16 cmpl_ring; 7024 __le16 seq_id; 7025 __le16 target_id; 7026 __le64 resp_addr; 7027 __le32 encap_request[26]; 7028 __le16 encap_resp_target_id; 7029 u8 unused_0[6]; 7030 }; 7031 7032 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7033 struct hwrm_exec_fwd_resp_output { 7034 __le16 error_code; 7035 __le16 req_type; 7036 __le16 seq_id; 7037 __le16 resp_len; 7038 u8 unused_0[7]; 7039 u8 valid; 7040 }; 7041 7042 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7043 struct hwrm_reject_fwd_resp_input { 7044 __le16 req_type; 7045 __le16 cmpl_ring; 7046 __le16 seq_id; 7047 __le16 target_id; 7048 __le64 resp_addr; 7049 __le32 encap_request[26]; 7050 __le16 encap_resp_target_id; 7051 u8 unused_0[6]; 7052 }; 7053 7054 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7055 struct hwrm_reject_fwd_resp_output { 7056 __le16 error_code; 7057 __le16 req_type; 7058 __le16 seq_id; 7059 __le16 resp_len; 7060 u8 unused_0[7]; 7061 u8 valid; 7062 }; 7063 7064 /* hwrm_fwd_resp_input (size:1024b/128B) */ 7065 struct hwrm_fwd_resp_input { 7066 __le16 req_type; 7067 __le16 cmpl_ring; 7068 __le16 seq_id; 7069 __le16 target_id; 7070 __le64 resp_addr; 7071 __le16 encap_resp_target_id; 7072 __le16 encap_resp_cmpl_ring; 7073 __le16 encap_resp_len; 7074 u8 unused_0; 7075 u8 unused_1; 7076 __le64 encap_resp_addr; 7077 __le32 encap_resp[24]; 7078 }; 7079 7080 /* hwrm_fwd_resp_output (size:128b/16B) */ 7081 struct hwrm_fwd_resp_output { 7082 __le16 error_code; 7083 __le16 req_type; 7084 __le16 seq_id; 7085 __le16 resp_len; 7086 u8 unused_0[7]; 7087 u8 valid; 7088 }; 7089 7090 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7091 struct hwrm_fwd_async_event_cmpl_input { 7092 __le16 req_type; 7093 __le16 cmpl_ring; 7094 __le16 seq_id; 7095 __le16 target_id; 7096 __le64 resp_addr; 7097 __le16 encap_async_event_target_id; 7098 u8 unused_0[6]; 7099 __le32 encap_async_event_cmpl[4]; 7100 }; 7101 7102 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7103 struct hwrm_fwd_async_event_cmpl_output { 7104 __le16 error_code; 7105 __le16 req_type; 7106 __le16 seq_id; 7107 __le16 resp_len; 7108 u8 unused_0[7]; 7109 u8 valid; 7110 }; 7111 7112 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7113 struct hwrm_temp_monitor_query_input { 7114 __le16 req_type; 7115 __le16 cmpl_ring; 7116 __le16 seq_id; 7117 __le16 target_id; 7118 __le64 resp_addr; 7119 }; 7120 7121 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7122 struct hwrm_temp_monitor_query_output { 7123 __le16 error_code; 7124 __le16 req_type; 7125 __le16 seq_id; 7126 __le16 resp_len; 7127 u8 temp; 7128 u8 unused_0[6]; 7129 u8 valid; 7130 }; 7131 7132 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7133 struct hwrm_wol_filter_alloc_input { 7134 __le16 req_type; 7135 __le16 cmpl_ring; 7136 __le16 seq_id; 7137 __le16 target_id; 7138 __le64 resp_addr; 7139 __le32 flags; 7140 __le32 enables; 7141 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7142 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7143 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7144 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7145 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7146 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7147 __le16 port_id; 7148 u8 wol_type; 7149 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7150 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7151 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7152 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7153 u8 unused_0[5]; 7154 u8 mac_address[6]; 7155 __le16 pattern_offset; 7156 __le16 pattern_buf_size; 7157 __le16 pattern_mask_size; 7158 u8 unused_1[4]; 7159 __le64 pattern_buf_addr; 7160 __le64 pattern_mask_addr; 7161 }; 7162 7163 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7164 struct hwrm_wol_filter_alloc_output { 7165 __le16 error_code; 7166 __le16 req_type; 7167 __le16 seq_id; 7168 __le16 resp_len; 7169 u8 wol_filter_id; 7170 u8 unused_0[6]; 7171 u8 valid; 7172 }; 7173 7174 /* hwrm_wol_filter_free_input (size:256b/32B) */ 7175 struct hwrm_wol_filter_free_input { 7176 __le16 req_type; 7177 __le16 cmpl_ring; 7178 __le16 seq_id; 7179 __le16 target_id; 7180 __le64 resp_addr; 7181 __le32 flags; 7182 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7183 __le32 enables; 7184 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7185 __le16 port_id; 7186 u8 wol_filter_id; 7187 u8 unused_0[5]; 7188 }; 7189 7190 /* hwrm_wol_filter_free_output (size:128b/16B) */ 7191 struct hwrm_wol_filter_free_output { 7192 __le16 error_code; 7193 __le16 req_type; 7194 __le16 seq_id; 7195 __le16 resp_len; 7196 u8 unused_0[7]; 7197 u8 valid; 7198 }; 7199 7200 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7201 struct hwrm_wol_filter_qcfg_input { 7202 __le16 req_type; 7203 __le16 cmpl_ring; 7204 __le16 seq_id; 7205 __le16 target_id; 7206 __le64 resp_addr; 7207 __le16 port_id; 7208 __le16 handle; 7209 u8 unused_0[4]; 7210 __le64 pattern_buf_addr; 7211 __le16 pattern_buf_size; 7212 u8 unused_1[6]; 7213 __le64 pattern_mask_addr; 7214 __le16 pattern_mask_size; 7215 u8 unused_2[6]; 7216 }; 7217 7218 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7219 struct hwrm_wol_filter_qcfg_output { 7220 __le16 error_code; 7221 __le16 req_type; 7222 __le16 seq_id; 7223 __le16 resp_len; 7224 __le16 next_handle; 7225 u8 wol_filter_id; 7226 u8 wol_type; 7227 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7228 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7229 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7230 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7231 __le32 unused_0; 7232 u8 mac_address[6]; 7233 __le16 pattern_offset; 7234 __le16 pattern_size; 7235 __le16 pattern_mask_size; 7236 u8 unused_1[3]; 7237 u8 valid; 7238 }; 7239 7240 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7241 struct hwrm_wol_reason_qcfg_input { 7242 __le16 req_type; 7243 __le16 cmpl_ring; 7244 __le16 seq_id; 7245 __le16 target_id; 7246 __le64 resp_addr; 7247 __le16 port_id; 7248 u8 unused_0[6]; 7249 __le64 wol_pkt_buf_addr; 7250 __le16 wol_pkt_buf_size; 7251 u8 unused_1[6]; 7252 }; 7253 7254 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7255 struct hwrm_wol_reason_qcfg_output { 7256 __le16 error_code; 7257 __le16 req_type; 7258 __le16 seq_id; 7259 __le16 resp_len; 7260 u8 wol_filter_id; 7261 u8 wol_reason; 7262 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7263 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7264 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7265 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7266 u8 wol_pkt_len; 7267 u8 unused_0[4]; 7268 u8 valid; 7269 }; 7270 7271 /* coredump_segment_record (size:128b/16B) */ 7272 struct coredump_segment_record { 7273 __le16 component_id; 7274 __le16 segment_id; 7275 __le16 max_instances; 7276 u8 version_hi; 7277 u8 version_low; 7278 u8 seg_flags; 7279 u8 compress_flags; 7280 #define SFLAG_COMPRESSED_ZLIB 0x1UL 7281 u8 unused_0[6]; 7282 }; 7283 7284 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7285 struct hwrm_dbg_coredump_list_input { 7286 __le16 req_type; 7287 __le16 cmpl_ring; 7288 __le16 seq_id; 7289 __le16 target_id; 7290 __le64 resp_addr; 7291 __le64 host_dest_addr; 7292 __le32 host_buf_len; 7293 __le16 seq_no; 7294 u8 flags; 7295 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 7296 u8 unused_0[1]; 7297 }; 7298 7299 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7300 struct hwrm_dbg_coredump_list_output { 7301 __le16 error_code; 7302 __le16 req_type; 7303 __le16 seq_id; 7304 __le16 resp_len; 7305 u8 flags; 7306 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7307 u8 unused_0; 7308 __le16 total_segments; 7309 __le16 data_len; 7310 u8 unused_1; 7311 u8 valid; 7312 }; 7313 7314 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7315 struct hwrm_dbg_coredump_initiate_input { 7316 __le16 req_type; 7317 __le16 cmpl_ring; 7318 __le16 seq_id; 7319 __le16 target_id; 7320 __le64 resp_addr; 7321 __le16 component_id; 7322 __le16 segment_id; 7323 __le16 instance; 7324 __le16 unused_0; 7325 u8 seg_flags; 7326 u8 unused_1[7]; 7327 }; 7328 7329 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7330 struct hwrm_dbg_coredump_initiate_output { 7331 __le16 error_code; 7332 __le16 req_type; 7333 __le16 seq_id; 7334 __le16 resp_len; 7335 u8 unused_0[7]; 7336 u8 valid; 7337 }; 7338 7339 /* coredump_data_hdr (size:128b/16B) */ 7340 struct coredump_data_hdr { 7341 __le32 address; 7342 __le32 flags_length; 7343 __le32 instance; 7344 __le32 next_offset; 7345 }; 7346 7347 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 7348 struct hwrm_dbg_coredump_retrieve_input { 7349 __le16 req_type; 7350 __le16 cmpl_ring; 7351 __le16 seq_id; 7352 __le16 target_id; 7353 __le64 resp_addr; 7354 __le64 host_dest_addr; 7355 __le32 host_buf_len; 7356 __le32 unused_0; 7357 __le16 component_id; 7358 __le16 segment_id; 7359 __le16 instance; 7360 __le16 unused_1; 7361 u8 seg_flags; 7362 u8 unused_2; 7363 __le16 unused_3; 7364 __le32 unused_4; 7365 __le32 seq_no; 7366 __le32 unused_5; 7367 }; 7368 7369 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 7370 struct hwrm_dbg_coredump_retrieve_output { 7371 __le16 error_code; 7372 __le16 req_type; 7373 __le16 seq_id; 7374 __le16 resp_len; 7375 u8 flags; 7376 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 7377 u8 unused_0; 7378 __le16 data_len; 7379 u8 unused_1[3]; 7380 u8 valid; 7381 }; 7382 7383 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 7384 struct hwrm_dbg_ring_info_get_input { 7385 __le16 req_type; 7386 __le16 cmpl_ring; 7387 __le16 seq_id; 7388 __le16 target_id; 7389 __le64 resp_addr; 7390 u8 ring_type; 7391 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 7392 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 7393 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 7394 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX 7395 u8 unused_0[3]; 7396 __le32 fw_ring_id; 7397 }; 7398 7399 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 7400 struct hwrm_dbg_ring_info_get_output { 7401 __le16 error_code; 7402 __le16 req_type; 7403 __le16 seq_id; 7404 __le16 resp_len; 7405 __le32 producer_index; 7406 __le32 consumer_index; 7407 u8 unused_0[7]; 7408 u8 valid; 7409 }; 7410 7411 /* hwrm_nvm_read_input (size:320b/40B) */ 7412 struct hwrm_nvm_read_input { 7413 __le16 req_type; 7414 __le16 cmpl_ring; 7415 __le16 seq_id; 7416 __le16 target_id; 7417 __le64 resp_addr; 7418 __le64 host_dest_addr; 7419 __le16 dir_idx; 7420 u8 unused_0[2]; 7421 __le32 offset; 7422 __le32 len; 7423 u8 unused_1[4]; 7424 }; 7425 7426 /* hwrm_nvm_read_output (size:128b/16B) */ 7427 struct hwrm_nvm_read_output { 7428 __le16 error_code; 7429 __le16 req_type; 7430 __le16 seq_id; 7431 __le16 resp_len; 7432 u8 unused_0[7]; 7433 u8 valid; 7434 }; 7435 7436 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 7437 struct hwrm_nvm_get_dir_entries_input { 7438 __le16 req_type; 7439 __le16 cmpl_ring; 7440 __le16 seq_id; 7441 __le16 target_id; 7442 __le64 resp_addr; 7443 __le64 host_dest_addr; 7444 }; 7445 7446 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 7447 struct hwrm_nvm_get_dir_entries_output { 7448 __le16 error_code; 7449 __le16 req_type; 7450 __le16 seq_id; 7451 __le16 resp_len; 7452 u8 unused_0[7]; 7453 u8 valid; 7454 }; 7455 7456 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 7457 struct hwrm_nvm_get_dir_info_input { 7458 __le16 req_type; 7459 __le16 cmpl_ring; 7460 __le16 seq_id; 7461 __le16 target_id; 7462 __le64 resp_addr; 7463 }; 7464 7465 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 7466 struct hwrm_nvm_get_dir_info_output { 7467 __le16 error_code; 7468 __le16 req_type; 7469 __le16 seq_id; 7470 __le16 resp_len; 7471 __le32 entries; 7472 __le32 entry_length; 7473 u8 unused_0[7]; 7474 u8 valid; 7475 }; 7476 7477 /* hwrm_nvm_write_input (size:384b/48B) */ 7478 struct hwrm_nvm_write_input { 7479 __le16 req_type; 7480 __le16 cmpl_ring; 7481 __le16 seq_id; 7482 __le16 target_id; 7483 __le64 resp_addr; 7484 __le64 host_src_addr; 7485 __le16 dir_type; 7486 __le16 dir_ordinal; 7487 __le16 dir_ext; 7488 __le16 dir_attr; 7489 __le32 dir_data_length; 7490 __le16 option; 7491 __le16 flags; 7492 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 7493 __le32 dir_item_length; 7494 __le32 unused_0; 7495 }; 7496 7497 /* hwrm_nvm_write_output (size:128b/16B) */ 7498 struct hwrm_nvm_write_output { 7499 __le16 error_code; 7500 __le16 req_type; 7501 __le16 seq_id; 7502 __le16 resp_len; 7503 __le32 dir_item_length; 7504 __le16 dir_idx; 7505 u8 unused_0; 7506 u8 valid; 7507 }; 7508 7509 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 7510 struct hwrm_nvm_write_cmd_err { 7511 u8 code; 7512 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 7513 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7514 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 7515 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 7516 u8 unused_0[7]; 7517 }; 7518 7519 /* hwrm_nvm_modify_input (size:320b/40B) */ 7520 struct hwrm_nvm_modify_input { 7521 __le16 req_type; 7522 __le16 cmpl_ring; 7523 __le16 seq_id; 7524 __le16 target_id; 7525 __le64 resp_addr; 7526 __le64 host_src_addr; 7527 __le16 dir_idx; 7528 u8 unused_0[2]; 7529 __le32 offset; 7530 __le32 len; 7531 u8 unused_1[4]; 7532 }; 7533 7534 /* hwrm_nvm_modify_output (size:128b/16B) */ 7535 struct hwrm_nvm_modify_output { 7536 __le16 error_code; 7537 __le16 req_type; 7538 __le16 seq_id; 7539 __le16 resp_len; 7540 u8 unused_0[7]; 7541 u8 valid; 7542 }; 7543 7544 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 7545 struct hwrm_nvm_find_dir_entry_input { 7546 __le16 req_type; 7547 __le16 cmpl_ring; 7548 __le16 seq_id; 7549 __le16 target_id; 7550 __le64 resp_addr; 7551 __le32 enables; 7552 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 7553 __le16 dir_idx; 7554 __le16 dir_type; 7555 __le16 dir_ordinal; 7556 __le16 dir_ext; 7557 u8 opt_ordinal; 7558 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 7559 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 7560 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 7561 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 7562 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 7563 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 7564 u8 unused_0[3]; 7565 }; 7566 7567 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 7568 struct hwrm_nvm_find_dir_entry_output { 7569 __le16 error_code; 7570 __le16 req_type; 7571 __le16 seq_id; 7572 __le16 resp_len; 7573 __le32 dir_item_length; 7574 __le32 dir_data_length; 7575 __le32 fw_ver; 7576 __le16 dir_ordinal; 7577 __le16 dir_idx; 7578 u8 unused_0[7]; 7579 u8 valid; 7580 }; 7581 7582 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 7583 struct hwrm_nvm_erase_dir_entry_input { 7584 __le16 req_type; 7585 __le16 cmpl_ring; 7586 __le16 seq_id; 7587 __le16 target_id; 7588 __le64 resp_addr; 7589 __le16 dir_idx; 7590 u8 unused_0[6]; 7591 }; 7592 7593 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 7594 struct hwrm_nvm_erase_dir_entry_output { 7595 __le16 error_code; 7596 __le16 req_type; 7597 __le16 seq_id; 7598 __le16 resp_len; 7599 u8 unused_0[7]; 7600 u8 valid; 7601 }; 7602 7603 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 7604 struct hwrm_nvm_get_dev_info_input { 7605 __le16 req_type; 7606 __le16 cmpl_ring; 7607 __le16 seq_id; 7608 __le16 target_id; 7609 __le64 resp_addr; 7610 }; 7611 7612 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 7613 struct hwrm_nvm_get_dev_info_output { 7614 __le16 error_code; 7615 __le16 req_type; 7616 __le16 seq_id; 7617 __le16 resp_len; 7618 __le16 manufacturer_id; 7619 __le16 device_id; 7620 __le32 sector_size; 7621 __le32 nvram_size; 7622 __le32 reserved_size; 7623 __le32 available_size; 7624 u8 nvm_cfg_ver_maj; 7625 u8 nvm_cfg_ver_min; 7626 u8 nvm_cfg_ver_upd; 7627 u8 valid; 7628 }; 7629 7630 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 7631 struct hwrm_nvm_mod_dir_entry_input { 7632 __le16 req_type; 7633 __le16 cmpl_ring; 7634 __le16 seq_id; 7635 __le16 target_id; 7636 __le64 resp_addr; 7637 __le32 enables; 7638 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 7639 __le16 dir_idx; 7640 __le16 dir_ordinal; 7641 __le16 dir_ext; 7642 __le16 dir_attr; 7643 __le32 checksum; 7644 }; 7645 7646 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 7647 struct hwrm_nvm_mod_dir_entry_output { 7648 __le16 error_code; 7649 __le16 req_type; 7650 __le16 seq_id; 7651 __le16 resp_len; 7652 u8 unused_0[7]; 7653 u8 valid; 7654 }; 7655 7656 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 7657 struct hwrm_nvm_verify_update_input { 7658 __le16 req_type; 7659 __le16 cmpl_ring; 7660 __le16 seq_id; 7661 __le16 target_id; 7662 __le64 resp_addr; 7663 __le16 dir_type; 7664 __le16 dir_ordinal; 7665 __le16 dir_ext; 7666 u8 unused_0[2]; 7667 }; 7668 7669 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 7670 struct hwrm_nvm_verify_update_output { 7671 __le16 error_code; 7672 __le16 req_type; 7673 __le16 seq_id; 7674 __le16 resp_len; 7675 u8 unused_0[7]; 7676 u8 valid; 7677 }; 7678 7679 /* hwrm_nvm_install_update_input (size:192b/24B) */ 7680 struct hwrm_nvm_install_update_input { 7681 __le16 req_type; 7682 __le16 cmpl_ring; 7683 __le16 seq_id; 7684 __le16 target_id; 7685 __le64 resp_addr; 7686 __le32 install_type; 7687 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 7688 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 7689 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 7690 __le16 flags; 7691 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 7692 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 7693 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 7694 u8 unused_0[2]; 7695 }; 7696 7697 /* hwrm_nvm_install_update_output (size:192b/24B) */ 7698 struct hwrm_nvm_install_update_output { 7699 __le16 error_code; 7700 __le16 req_type; 7701 __le16 seq_id; 7702 __le16 resp_len; 7703 __le64 installed_items; 7704 u8 result; 7705 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 7706 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 7707 u8 problem_item; 7708 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 7709 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 7710 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 7711 u8 reset_required; 7712 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 7713 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 7714 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 7715 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 7716 u8 unused_0[4]; 7717 u8 valid; 7718 }; 7719 7720 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 7721 struct hwrm_nvm_install_update_cmd_err { 7722 u8 code; 7723 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 7724 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7725 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 7726 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 7727 u8 unused_0[7]; 7728 }; 7729 7730 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 7731 struct hwrm_nvm_get_variable_input { 7732 __le16 req_type; 7733 __le16 cmpl_ring; 7734 __le16 seq_id; 7735 __le16 target_id; 7736 __le64 resp_addr; 7737 __le64 dest_data_addr; 7738 __le16 data_len; 7739 __le16 option_num; 7740 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7741 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7742 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7743 __le16 dimensions; 7744 __le16 index_0; 7745 __le16 index_1; 7746 __le16 index_2; 7747 __le16 index_3; 7748 u8 flags; 7749 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 7750 u8 unused_0; 7751 }; 7752 7753 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 7754 struct hwrm_nvm_get_variable_output { 7755 __le16 error_code; 7756 __le16 req_type; 7757 __le16 seq_id; 7758 __le16 resp_len; 7759 __le16 data_len; 7760 __le16 option_num; 7761 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 7762 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 7763 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 7764 u8 unused_0[3]; 7765 u8 valid; 7766 }; 7767 7768 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 7769 struct hwrm_nvm_get_variable_cmd_err { 7770 u8 code; 7771 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7772 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7773 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7774 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 7775 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 7776 u8 unused_0[7]; 7777 }; 7778 7779 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 7780 struct hwrm_nvm_set_variable_input { 7781 __le16 req_type; 7782 __le16 cmpl_ring; 7783 __le16 seq_id; 7784 __le16 target_id; 7785 __le64 resp_addr; 7786 __le64 src_data_addr; 7787 __le16 data_len; 7788 __le16 option_num; 7789 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7790 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7791 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7792 __le16 dimensions; 7793 __le16 index_0; 7794 __le16 index_1; 7795 __le16 index_2; 7796 __le16 index_3; 7797 u8 flags; 7798 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 7799 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 7800 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 7801 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 7802 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 7803 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 7804 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 7805 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 7806 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 7807 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 7808 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 7809 u8 unused_0; 7810 }; 7811 7812 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 7813 struct hwrm_nvm_set_variable_output { 7814 __le16 error_code; 7815 __le16 req_type; 7816 __le16 seq_id; 7817 __le16 resp_len; 7818 u8 unused_0[7]; 7819 u8 valid; 7820 }; 7821 7822 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 7823 struct hwrm_nvm_set_variable_cmd_err { 7824 u8 code; 7825 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7826 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7827 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7828 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 7829 u8 unused_0[7]; 7830 }; 7831 7832 /* hwrm_selftest_qlist_input (size:128b/16B) */ 7833 struct hwrm_selftest_qlist_input { 7834 __le16 req_type; 7835 __le16 cmpl_ring; 7836 __le16 seq_id; 7837 __le16 target_id; 7838 __le64 resp_addr; 7839 }; 7840 7841 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 7842 struct hwrm_selftest_qlist_output { 7843 __le16 error_code; 7844 __le16 req_type; 7845 __le16 seq_id; 7846 __le16 resp_len; 7847 u8 num_tests; 7848 u8 available_tests; 7849 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 7850 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 7851 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 7852 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 7853 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 7854 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7855 u8 offline_tests; 7856 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 7857 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 7858 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 7859 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 7860 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 7861 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7862 u8 unused_0; 7863 __le16 test_timeout; 7864 u8 unused_1[2]; 7865 char test0_name[32]; 7866 char test1_name[32]; 7867 char test2_name[32]; 7868 char test3_name[32]; 7869 char test4_name[32]; 7870 char test5_name[32]; 7871 char test6_name[32]; 7872 char test7_name[32]; 7873 u8 unused_2[7]; 7874 u8 valid; 7875 }; 7876 7877 /* hwrm_selftest_exec_input (size:192b/24B) */ 7878 struct hwrm_selftest_exec_input { 7879 __le16 req_type; 7880 __le16 cmpl_ring; 7881 __le16 seq_id; 7882 __le16 target_id; 7883 __le64 resp_addr; 7884 u8 flags; 7885 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 7886 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 7887 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 7888 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 7889 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 7890 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 7891 u8 unused_0[7]; 7892 }; 7893 7894 /* hwrm_selftest_exec_output (size:128b/16B) */ 7895 struct hwrm_selftest_exec_output { 7896 __le16 error_code; 7897 __le16 req_type; 7898 __le16 seq_id; 7899 __le16 resp_len; 7900 u8 requested_tests; 7901 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 7902 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 7903 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 7904 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 7905 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 7906 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 7907 u8 test_success; 7908 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 7909 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 7910 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 7911 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 7912 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 7913 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 7914 u8 unused_0[5]; 7915 u8 valid; 7916 }; 7917 7918 /* hwrm_selftest_irq_input (size:128b/16B) */ 7919 struct hwrm_selftest_irq_input { 7920 __le16 req_type; 7921 __le16 cmpl_ring; 7922 __le16 seq_id; 7923 __le16 target_id; 7924 __le64 resp_addr; 7925 }; 7926 7927 /* hwrm_selftest_irq_output (size:128b/16B) */ 7928 struct hwrm_selftest_irq_output { 7929 __le16 error_code; 7930 __le16 req_type; 7931 __le16 seq_id; 7932 __le16 resp_len; 7933 u8 unused_0[7]; 7934 u8 valid; 7935 }; 7936 7937 #endif /* _BNXT_HSI_H_ */ 7938