1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2021 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110 #define HWRM_FUNC_VF_CFG 0xfUL 111 #define HWRM_RESERVED1 0x10UL 112 #define HWRM_FUNC_RESET 0x11UL 113 #define HWRM_FUNC_GETFID 0x12UL 114 #define HWRM_FUNC_VF_ALLOC 0x13UL 115 #define HWRM_FUNC_VF_FREE 0x14UL 116 #define HWRM_FUNC_QCAPS 0x15UL 117 #define HWRM_FUNC_QCFG 0x16UL 118 #define HWRM_FUNC_CFG 0x17UL 119 #define HWRM_FUNC_QSTATS 0x18UL 120 #define HWRM_FUNC_CLR_STATS 0x19UL 121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124 #define HWRM_FUNC_DRV_RGTR 0x1dUL 125 #define HWRM_FUNC_DRV_QVER 0x1eUL 126 #define HWRM_FUNC_BUF_RGTR 0x1fUL 127 #define HWRM_PORT_PHY_CFG 0x20UL 128 #define HWRM_PORT_MAC_CFG 0x21UL 129 #define HWRM_PORT_TS_QUERY 0x22UL 130 #define HWRM_PORT_QSTATS 0x23UL 131 #define HWRM_PORT_LPBK_QSTATS 0x24UL 132 #define HWRM_PORT_CLR_STATS 0x25UL 133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134 #define HWRM_PORT_PHY_QCFG 0x27UL 135 #define HWRM_PORT_MAC_QCFG 0x28UL 136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137 #define HWRM_PORT_PHY_QCAPS 0x2aUL 138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140 #define HWRM_PORT_LED_CFG 0x2dUL 141 #define HWRM_PORT_LED_QCFG 0x2eUL 142 #define HWRM_PORT_LED_QCAPS 0x2fUL 143 #define HWRM_QUEUE_QPORTCFG 0x30UL 144 #define HWRM_QUEUE_QCFG 0x31UL 145 #define HWRM_QUEUE_CFG 0x32UL 146 #define HWRM_FUNC_VLAN_CFG 0x33UL 147 #define HWRM_FUNC_VLAN_QCFG 0x34UL 148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157 #define HWRM_VNIC_ALLOC 0x40UL 158 #define HWRM_VNIC_FREE 0x41UL 159 #define HWRM_VNIC_CFG 0x42UL 160 #define HWRM_VNIC_QCFG 0x43UL 161 #define HWRM_VNIC_TPA_CFG 0x44UL 162 #define HWRM_VNIC_TPA_QCFG 0x45UL 163 #define HWRM_VNIC_RSS_CFG 0x46UL 164 #define HWRM_VNIC_RSS_QCFG 0x47UL 165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167 #define HWRM_VNIC_QCAPS 0x4aUL 168 #define HWRM_VNIC_UPDATE 0x4bUL 169 #define HWRM_RING_ALLOC 0x50UL 170 #define HWRM_RING_FREE 0x51UL 171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 173 #define HWRM_RING_AGGINT_QCAPS 0x54UL 174 #define HWRM_RING_SCHQ_ALLOC 0x55UL 175 #define HWRM_RING_SCHQ_CFG 0x56UL 176 #define HWRM_RING_SCHQ_FREE 0x57UL 177 #define HWRM_RING_RESET 0x5eUL 178 #define HWRM_RING_GRP_ALLOC 0x60UL 179 #define HWRM_RING_GRP_FREE 0x61UL 180 #define HWRM_RING_CFG 0x62UL 181 #define HWRM_RING_QCFG 0x63UL 182 #define HWRM_RESERVED5 0x64UL 183 #define HWRM_RESERVED6 0x65UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 192 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 193 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 212 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213 #define HWRM_STAT_CTX_ALLOC 0xb0UL 214 #define HWRM_STAT_CTX_FREE 0xb1UL 215 #define HWRM_STAT_CTX_QUERY 0xb2UL 216 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217 #define HWRM_PORT_QSTATS_EXT 0xb4UL 218 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 219 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 220 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 221 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 223 #define HWRM_RESERVED7 0xbaUL 224 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 225 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 226 #define HWRM_PORT_ECN_QSTATS 0xbdUL 227 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 228 #define HWRM_FW_LIVEPATCH 0xbfUL 229 #define HWRM_FW_RESET 0xc0UL 230 #define HWRM_FW_QSTATUS 0xc1UL 231 #define HWRM_FW_HEALTH_CHECK 0xc2UL 232 #define HWRM_FW_SYNC 0xc3UL 233 #define HWRM_FW_STATE_QCAPS 0xc4UL 234 #define HWRM_FW_STATE_QUIESCE 0xc5UL 235 #define HWRM_FW_STATE_BACKUP 0xc6UL 236 #define HWRM_FW_STATE_RESTORE 0xc7UL 237 #define HWRM_FW_SET_TIME 0xc8UL 238 #define HWRM_FW_GET_TIME 0xc9UL 239 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241 #define HWRM_FW_IPC_MAILBOX 0xccUL 242 #define HWRM_FW_ECN_CFG 0xcdUL 243 #define HWRM_FW_ECN_QCFG 0xceUL 244 #define HWRM_FW_SECURE_CFG 0xcfUL 245 #define HWRM_EXEC_FWD_RESP 0xd0UL 246 #define HWRM_REJECT_FWD_RESP 0xd1UL 247 #define HWRM_FWD_RESP 0xd2UL 248 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249 #define HWRM_OEM_CMD 0xd4UL 250 #define HWRM_PORT_PRBS_TEST 0xd5UL 251 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 252 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 253 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 254 #define HWRM_PORT_DSC_DUMP 0xd9UL 255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 256 #define HWRM_PORT_EP_TX_CFG 0xdbUL 257 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 258 #define HWRM_REG_POWER_QUERY 0xe1UL 259 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 260 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 261 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 262 #define HWRM_WOL_FILTER_FREE 0xf1UL 263 #define HWRM_WOL_FILTER_QCFG 0xf2UL 264 #define HWRM_WOL_REASON_QCFG 0xf3UL 265 #define HWRM_CFA_METER_QCAPS 0xf4UL 266 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 267 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 268 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 269 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 270 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 271 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 272 #define HWRM_CFA_VFR_ALLOC 0xfdUL 273 #define HWRM_CFA_VFR_FREE 0xfeUL 274 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 275 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 276 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 277 #define HWRM_CFA_FLOW_ALLOC 0x103UL 278 #define HWRM_CFA_FLOW_FREE 0x104UL 279 #define HWRM_CFA_FLOW_FLUSH 0x105UL 280 #define HWRM_CFA_FLOW_STATS 0x106UL 281 #define HWRM_CFA_FLOW_INFO 0x107UL 282 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 283 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 284 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 285 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 287 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 288 #define HWRM_CFA_PAIR_FREE 0x10eUL 289 #define HWRM_CFA_PAIR_INFO 0x10fUL 290 #define HWRM_FW_IPC_MSG 0x110UL 291 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 292 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 293 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 294 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 295 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 296 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 297 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 298 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 299 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 300 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 301 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 302 #define HWRM_CFA_COUNTER_CFG 0x11cUL 303 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 304 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 305 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 306 #define HWRM_CFA_EEM_QCAPS 0x120UL 307 #define HWRM_CFA_EEM_CFG 0x121UL 308 #define HWRM_CFA_EEM_QCFG 0x122UL 309 #define HWRM_CFA_EEM_OP 0x123UL 310 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 311 #define HWRM_CFA_TFLIB 0x125UL 312 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 313 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 314 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 315 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 316 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 317 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 318 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 319 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 320 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 321 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 322 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 323 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 324 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 325 #define HWRM_ENGINE_QG_QUERY 0x13dUL 326 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 327 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 328 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 329 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 330 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 331 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 332 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 333 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 334 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 335 #define HWRM_ENGINE_SG_QUERY 0x147UL 336 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 337 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 338 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 339 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 340 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 341 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 342 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 343 #define HWRM_ENGINE_STATS_QUERY 0x157UL 344 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 345 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 346 #define HWRM_ENGINE_RQ_FREE 0x15fUL 347 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 348 #define HWRM_ENGINE_CQ_FREE 0x161UL 349 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 350 #define HWRM_ENGINE_NQ_FREE 0x163UL 351 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 352 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 353 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 354 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 355 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 356 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 357 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 358 #define HWRM_FUNC_VF_BW_CFG 0x195UL 359 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 360 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 361 #define HWRM_FUNC_QSTATS_EXT 0x198UL 362 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 363 #define HWRM_FUNC_SPD_CFG 0x19aUL 364 #define HWRM_FUNC_SPD_QCFG 0x19bUL 365 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 366 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 367 #define HWRM_FUNC_PTP_CFG 0x19eUL 368 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 369 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 370 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 371 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 372 #define HWRM_SELFTEST_QLIST 0x200UL 373 #define HWRM_SELFTEST_EXEC 0x201UL 374 #define HWRM_SELFTEST_IRQ 0x202UL 375 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 376 #define HWRM_PCIE_QSTATS 0x204UL 377 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 378 #define HWRM_MFG_TIMERS_QUERY 0x206UL 379 #define HWRM_MFG_OTP_CFG 0x207UL 380 #define HWRM_MFG_OTP_QCFG 0x208UL 381 #define HWRM_MFG_HDMA_TEST 0x209UL 382 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 383 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 384 #define HWRM_MFG_SOC_IMAGE 0x20cUL 385 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 386 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 387 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 388 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 389 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 390 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 391 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 392 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 393 #define HWRM_TF 0x2bcUL 394 #define HWRM_TF_VERSION_GET 0x2bdUL 395 #define HWRM_TF_SESSION_OPEN 0x2c6UL 396 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 397 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 398 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 399 #define HWRM_TF_SESSION_CLOSE 0x2caUL 400 #define HWRM_TF_SESSION_QCFG 0x2cbUL 401 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 402 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 403 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 404 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 405 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 406 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 407 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 408 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 409 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 410 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 411 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 412 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 413 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 414 #define HWRM_TF_EXT_EM_OP 0x2e7UL 415 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 416 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 417 #define HWRM_TF_EM_INSERT 0x2eaUL 418 #define HWRM_TF_EM_DELETE 0x2ebUL 419 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 420 #define HWRM_TF_EM_MOVE 0x2edUL 421 #define HWRM_TF_TCAM_SET 0x2f8UL 422 #define HWRM_TF_TCAM_GET 0x2f9UL 423 #define HWRM_TF_TCAM_MOVE 0x2faUL 424 #define HWRM_TF_TCAM_FREE 0x2fbUL 425 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 426 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 427 #define HWRM_TF_IF_TBL_SET 0x2feUL 428 #define HWRM_TF_IF_TBL_GET 0x2ffUL 429 #define HWRM_SV 0x400UL 430 #define HWRM_DBG_READ_DIRECT 0xff10UL 431 #define HWRM_DBG_READ_INDIRECT 0xff11UL 432 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 433 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 434 #define HWRM_DBG_DUMP 0xff14UL 435 #define HWRM_DBG_ERASE_NVM 0xff15UL 436 #define HWRM_DBG_CFG 0xff16UL 437 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 438 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 439 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 440 #define HWRM_DBG_FW_CLI 0xff1aUL 441 #define HWRM_DBG_I2C_CMD 0xff1bUL 442 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 443 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 444 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 445 #define HWRM_DBG_DRV_TRACE 0xff1fUL 446 #define HWRM_DBG_QCAPS 0xff20UL 447 #define HWRM_DBG_QCFG 0xff21UL 448 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 449 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 450 #define HWRM_DBG_USEQ_FREE 0xff24UL 451 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 452 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 453 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 454 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 455 #define HWRM_DBG_USEQ_RUN 0xff29UL 456 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 457 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 458 #define HWRM_NVM_DEFRAG 0xffecUL 459 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 460 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 461 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 462 #define HWRM_NVM_FLUSH 0xfff0UL 463 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 464 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 465 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 466 #define HWRM_NVM_MODIFY 0xfff4UL 467 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 468 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 469 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 470 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 471 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 472 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 473 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 474 #define HWRM_NVM_RAW_DUMP 0xfffcUL 475 #define HWRM_NVM_READ 0xfffdUL 476 #define HWRM_NVM_WRITE 0xfffeUL 477 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 478 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 479 __le16 unused_0[3]; 480 }; 481 482 /* ret_codes (size:64b/8B) */ 483 struct ret_codes { 484 __le16 error_code; 485 #define HWRM_ERR_CODE_SUCCESS 0x0UL 486 #define HWRM_ERR_CODE_FAIL 0x1UL 487 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 488 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 489 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 490 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 491 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 492 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 493 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 494 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 495 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 496 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 497 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 498 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 499 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 500 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 501 #define HWRM_ERR_CODE_BUSY 0x10UL 502 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 503 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 504 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 505 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 506 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 507 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 508 __le16 unused_0[3]; 509 }; 510 511 /* hwrm_err_output (size:128b/16B) */ 512 struct hwrm_err_output { 513 __le16 error_code; 514 __le16 req_type; 515 __le16 seq_id; 516 __le16 resp_len; 517 __le32 opaque_0; 518 __le16 opaque_1; 519 u8 cmd_err; 520 u8 valid; 521 }; 522 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 523 #define HWRM_MAX_REQ_LEN 128 524 #define HWRM_MAX_RESP_LEN 704 525 #define HW_HASH_INDEX_SIZE 0x80 526 #define HW_HASH_KEY_SIZE 40 527 #define HWRM_RESP_VALID_KEY 1 528 #define HWRM_TARGET_ID_BONO 0xFFF8 529 #define HWRM_TARGET_ID_KONG 0xFFF9 530 #define HWRM_TARGET_ID_APE 0xFFFA 531 #define HWRM_TARGET_ID_TOOLS 0xFFFD 532 #define HWRM_VERSION_MAJOR 1 533 #define HWRM_VERSION_MINOR 10 534 #define HWRM_VERSION_UPDATE 2 535 #define HWRM_VERSION_RSVD 52 536 #define HWRM_VERSION_STR "1.10.2.52" 537 538 /* hwrm_ver_get_input (size:192b/24B) */ 539 struct hwrm_ver_get_input { 540 __le16 req_type; 541 __le16 cmpl_ring; 542 __le16 seq_id; 543 __le16 target_id; 544 __le64 resp_addr; 545 u8 hwrm_intf_maj; 546 u8 hwrm_intf_min; 547 u8 hwrm_intf_upd; 548 u8 unused_0[5]; 549 }; 550 551 /* hwrm_ver_get_output (size:1408b/176B) */ 552 struct hwrm_ver_get_output { 553 __le16 error_code; 554 __le16 req_type; 555 __le16 seq_id; 556 __le16 resp_len; 557 u8 hwrm_intf_maj_8b; 558 u8 hwrm_intf_min_8b; 559 u8 hwrm_intf_upd_8b; 560 u8 hwrm_intf_rsvd_8b; 561 u8 hwrm_fw_maj_8b; 562 u8 hwrm_fw_min_8b; 563 u8 hwrm_fw_bld_8b; 564 u8 hwrm_fw_rsvd_8b; 565 u8 mgmt_fw_maj_8b; 566 u8 mgmt_fw_min_8b; 567 u8 mgmt_fw_bld_8b; 568 u8 mgmt_fw_rsvd_8b; 569 u8 netctrl_fw_maj_8b; 570 u8 netctrl_fw_min_8b; 571 u8 netctrl_fw_bld_8b; 572 u8 netctrl_fw_rsvd_8b; 573 __le32 dev_caps_cfg; 574 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 575 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 576 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 577 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 578 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 579 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 580 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 581 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 582 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 583 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 584 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 585 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 586 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 587 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 588 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 589 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 590 u8 roce_fw_maj_8b; 591 u8 roce_fw_min_8b; 592 u8 roce_fw_bld_8b; 593 u8 roce_fw_rsvd_8b; 594 char hwrm_fw_name[16]; 595 char mgmt_fw_name[16]; 596 char netctrl_fw_name[16]; 597 char active_pkg_name[16]; 598 char roce_fw_name[16]; 599 __le16 chip_num; 600 u8 chip_rev; 601 u8 chip_metal; 602 u8 chip_bond_id; 603 u8 chip_platform_type; 604 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 605 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 606 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 607 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 608 __le16 max_req_win_len; 609 __le16 max_resp_len; 610 __le16 def_req_timeout; 611 u8 flags; 612 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 613 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 614 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 615 u8 unused_0[2]; 616 u8 always_1; 617 __le16 hwrm_intf_major; 618 __le16 hwrm_intf_minor; 619 __le16 hwrm_intf_build; 620 __le16 hwrm_intf_patch; 621 __le16 hwrm_fw_major; 622 __le16 hwrm_fw_minor; 623 __le16 hwrm_fw_build; 624 __le16 hwrm_fw_patch; 625 __le16 mgmt_fw_major; 626 __le16 mgmt_fw_minor; 627 __le16 mgmt_fw_build; 628 __le16 mgmt_fw_patch; 629 __le16 netctrl_fw_major; 630 __le16 netctrl_fw_minor; 631 __le16 netctrl_fw_build; 632 __le16 netctrl_fw_patch; 633 __le16 roce_fw_major; 634 __le16 roce_fw_minor; 635 __le16 roce_fw_build; 636 __le16 roce_fw_patch; 637 __le16 max_ext_req_len; 638 __le16 max_req_timeout; 639 u8 unused_1[3]; 640 u8 valid; 641 }; 642 643 /* eject_cmpl (size:128b/16B) */ 644 struct eject_cmpl { 645 __le16 type; 646 #define EJECT_CMPL_TYPE_MASK 0x3fUL 647 #define EJECT_CMPL_TYPE_SFT 0 648 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 649 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 650 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 651 #define EJECT_CMPL_FLAGS_SFT 6 652 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 653 __le16 len; 654 __le32 opaque; 655 __le16 v; 656 #define EJECT_CMPL_V 0x1UL 657 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 658 #define EJECT_CMPL_ERRORS_SFT 1 659 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 660 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 661 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 662 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 663 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 664 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 665 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 666 __le16 reserved16; 667 __le32 unused_2; 668 }; 669 670 /* hwrm_cmpl (size:128b/16B) */ 671 struct hwrm_cmpl { 672 __le16 type; 673 #define CMPL_TYPE_MASK 0x3fUL 674 #define CMPL_TYPE_SFT 0 675 #define CMPL_TYPE_HWRM_DONE 0x20UL 676 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 677 __le16 sequence_id; 678 __le32 unused_1; 679 __le32 v; 680 #define CMPL_V 0x1UL 681 __le32 unused_3; 682 }; 683 684 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 685 struct hwrm_fwd_req_cmpl { 686 __le16 req_len_type; 687 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 688 #define FWD_REQ_CMPL_TYPE_SFT 0 689 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 690 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 691 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 692 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 693 __le16 source_id; 694 __le32 unused0; 695 __le32 req_buf_addr_v[2]; 696 #define FWD_REQ_CMPL_V 0x1UL 697 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 698 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 699 }; 700 701 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 702 struct hwrm_fwd_resp_cmpl { 703 __le16 type; 704 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 705 #define FWD_RESP_CMPL_TYPE_SFT 0 706 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 707 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 708 __le16 source_id; 709 __le16 resp_len; 710 __le16 unused_1; 711 __le32 resp_buf_addr_v[2]; 712 #define FWD_RESP_CMPL_V 0x1UL 713 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 714 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 715 }; 716 717 /* hwrm_async_event_cmpl (size:128b/16B) */ 718 struct hwrm_async_event_cmpl { 719 __le16 type; 720 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 721 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 722 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 723 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 724 __le16 event_id; 725 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 726 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 727 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 728 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 729 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 730 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 731 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 732 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 733 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 734 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 735 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 736 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 737 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 738 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 739 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 740 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 741 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 742 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 743 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 744 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 745 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 746 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 747 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 748 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 749 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 750 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 751 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 752 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 753 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 754 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 755 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 756 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 757 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 758 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 759 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 760 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER 0x43UL 761 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 762 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 763 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x46UL 764 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 765 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 766 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 767 __le32 event_data2; 768 u8 opaque_v; 769 #define ASYNC_EVENT_CMPL_V 0x1UL 770 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 771 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 772 u8 timestamp_lo; 773 __le16 timestamp_hi; 774 __le32 event_data1; 775 }; 776 777 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 778 struct hwrm_async_event_cmpl_link_status_change { 779 __le16 type; 780 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 781 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 782 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 783 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 784 __le16 event_id; 785 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 786 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 787 __le32 event_data2; 788 u8 opaque_v; 789 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 790 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 791 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 792 u8 timestamp_lo; 793 __le16 timestamp_hi; 794 __le32 event_data1; 795 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 796 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 797 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 798 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 799 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 800 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 801 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 802 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 803 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 804 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 805 }; 806 807 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 808 struct hwrm_async_event_cmpl_port_conn_not_allowed { 809 __le16 type; 810 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 811 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 812 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 813 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 814 __le16 event_id; 815 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 816 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 817 __le32 event_data2; 818 u8 opaque_v; 819 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 820 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 821 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 822 u8 timestamp_lo; 823 __le16 timestamp_hi; 824 __le32 event_data1; 825 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 826 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 827 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 828 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 829 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 830 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 831 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 832 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 833 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 834 }; 835 836 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 837 struct hwrm_async_event_cmpl_link_speed_cfg_change { 838 __le16 type; 839 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 840 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 841 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 842 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 843 __le16 event_id; 844 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 845 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 846 __le32 event_data2; 847 u8 opaque_v; 848 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 849 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 850 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 851 u8 timestamp_lo; 852 __le16 timestamp_hi; 853 __le32 event_data1; 854 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 855 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 856 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 857 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 858 }; 859 860 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 861 struct hwrm_async_event_cmpl_reset_notify { 862 __le16 type; 863 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 864 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 865 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 866 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 867 __le16 event_id; 868 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 869 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 870 __le32 event_data2; 871 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 872 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 873 u8 opaque_v; 874 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 875 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 876 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 877 u8 timestamp_lo; 878 __le16 timestamp_hi; 879 __le32 event_data1; 880 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 881 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 882 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 883 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 884 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 885 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 886 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 887 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 888 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 889 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 890 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 891 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 892 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 893 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 894 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 895 }; 896 897 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 898 struct hwrm_async_event_cmpl_error_recovery { 899 __le16 type; 900 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 901 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 902 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 903 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 904 __le16 event_id; 905 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 906 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 907 __le32 event_data2; 908 u8 opaque_v; 909 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 910 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 911 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 912 u8 timestamp_lo; 913 __le16 timestamp_hi; 914 __le32 event_data1; 915 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 916 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 917 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 918 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 919 }; 920 921 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 922 struct hwrm_async_event_cmpl_ring_monitor_msg { 923 __le16 type; 924 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 925 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 926 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 927 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 928 __le16 event_id; 929 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 930 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 931 __le32 event_data2; 932 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 933 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 934 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 935 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 936 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 937 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 938 u8 opaque_v; 939 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 940 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 941 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 942 u8 timestamp_lo; 943 __le16 timestamp_hi; 944 __le32 event_data1; 945 }; 946 947 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 948 struct hwrm_async_event_cmpl_vf_cfg_change { 949 __le16 type; 950 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 951 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 952 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 953 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 954 __le16 event_id; 955 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 956 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 957 __le32 event_data2; 958 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 959 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 960 u8 opaque_v; 961 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 962 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 963 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 964 u8 timestamp_lo; 965 __le16 timestamp_hi; 966 __le32 event_data1; 967 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 968 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 969 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 970 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 971 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 972 }; 973 974 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 975 struct hwrm_async_event_cmpl_default_vnic_change { 976 __le16 type; 977 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 978 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 979 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 980 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 981 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 982 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 983 __le16 event_id; 984 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 985 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 986 __le32 event_data2; 987 u8 opaque_v; 988 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 989 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 990 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 991 u8 timestamp_lo; 992 __le16 timestamp_hi; 993 __le32 event_data1; 994 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 995 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 996 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 997 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 998 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 999 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1000 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1001 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1002 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1003 }; 1004 1005 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1006 struct hwrm_async_event_cmpl_hw_flow_aged { 1007 __le16 type; 1008 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1009 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1010 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1011 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1012 __le16 event_id; 1013 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1014 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1015 __le32 event_data2; 1016 u8 opaque_v; 1017 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1018 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1019 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1020 u8 timestamp_lo; 1021 __le16 timestamp_hi; 1022 __le32 event_data1; 1023 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1024 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1025 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1026 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1027 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1028 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1029 }; 1030 1031 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1032 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1033 __le16 type; 1034 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1035 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1036 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1037 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1038 __le16 event_id; 1039 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1040 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1041 __le32 event_data2; 1042 u8 opaque_v; 1043 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1044 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1045 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1046 u8 timestamp_lo; 1047 __le16 timestamp_hi; 1048 __le32 event_data1; 1049 }; 1050 1051 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1052 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1053 __le16 type; 1054 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1055 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1056 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1057 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1058 __le16 event_id; 1059 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1060 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1061 __le32 event_data2; 1062 u8 opaque_v; 1063 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1064 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1065 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1066 u8 timestamp_lo; 1067 __le16 timestamp_hi; 1068 __le32 event_data1; 1069 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1070 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1071 }; 1072 1073 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1074 struct hwrm_async_event_cmpl_deferred_response { 1075 __le16 type; 1076 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1077 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1078 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1079 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1080 __le16 event_id; 1081 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1082 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1083 __le32 event_data2; 1084 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1085 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1086 u8 opaque_v; 1087 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1088 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1089 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1090 u8 timestamp_lo; 1091 __le16 timestamp_hi; 1092 __le32 event_data1; 1093 }; 1094 1095 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1096 struct hwrm_async_event_cmpl_echo_request { 1097 __le16 type; 1098 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1099 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1100 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1101 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1102 __le16 event_id; 1103 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1104 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1105 __le32 event_data2; 1106 u8 opaque_v; 1107 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1108 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1109 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1110 u8 timestamp_lo; 1111 __le16 timestamp_hi; 1112 __le32 event_data1; 1113 }; 1114 1115 /* hwrm_async_event_cmpl_phc_master (size:128b/16B) */ 1116 struct hwrm_async_event_cmpl_phc_master { 1117 __le16 type; 1118 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK 0x3fUL 1119 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0 1120 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1121 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 1122 __le16 event_id; 1123 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL 1124 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 1125 __le32 event_data2; 1126 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1127 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1128 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1129 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT 16 1130 u8 opaque_v; 1131 #define ASYNC_EVENT_CMPL_PHC_MASTER_V 0x1UL 1132 #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL 1133 #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1 1134 u8 timestamp_lo; 1135 __le16 timestamp_hi; 1136 __le32 event_data1; 1137 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK 0xfUL 1138 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT 0 1139 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1140 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1141 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1142 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 1143 }; 1144 1145 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1146 struct hwrm_async_event_cmpl_pps_timestamp { 1147 __le16 type; 1148 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1149 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1150 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1151 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1152 __le16 event_id; 1153 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1154 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1155 __le32 event_data2; 1156 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1157 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1158 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1159 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1160 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1161 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1162 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1163 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1164 u8 opaque_v; 1165 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1166 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1167 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1168 u8 timestamp_lo; 1169 __le16 timestamp_hi; 1170 __le32 event_data1; 1171 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1172 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1173 }; 1174 1175 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1176 struct hwrm_async_event_cmpl_error_report { 1177 __le16 type; 1178 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1179 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1180 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1181 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1182 __le16 event_id; 1183 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1184 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1185 __le32 event_data2; 1186 u8 opaque_v; 1187 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1188 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1189 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1190 u8 timestamp_lo; 1191 __le16 timestamp_hi; 1192 __le32 event_data1; 1193 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1194 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1195 }; 1196 1197 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1198 struct hwrm_async_event_cmpl_hwrm_error { 1199 __le16 type; 1200 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1201 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1202 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1203 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1204 __le16 event_id; 1205 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1206 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1207 __le32 event_data2; 1208 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1209 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1210 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1211 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1212 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1213 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1214 u8 opaque_v; 1215 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1216 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1217 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1218 u8 timestamp_lo; 1219 __le16 timestamp_hi; 1220 __le32 event_data1; 1221 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1222 }; 1223 1224 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1225 struct hwrm_async_event_cmpl_error_report_base { 1226 __le16 type; 1227 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1228 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1229 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1230 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1231 __le16 event_id; 1232 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1233 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1234 __le32 event_data2; 1235 u8 opaque_v; 1236 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1237 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1238 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1239 u8 timestamp_lo; 1240 __le16 timestamp_hi; 1241 __le32 event_data1; 1242 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1243 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1244 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1245 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1246 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1247 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1248 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1249 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1250 }; 1251 1252 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1253 struct hwrm_async_event_cmpl_error_report_pause_storm { 1254 __le16 type; 1255 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1256 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1257 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1258 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1259 __le16 event_id; 1260 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1261 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1262 __le32 event_data2; 1263 u8 opaque_v; 1264 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1265 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1266 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1267 u8 timestamp_lo; 1268 __le16 timestamp_hi; 1269 __le32 event_data1; 1270 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1271 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1272 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1273 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1274 }; 1275 1276 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1277 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1278 __le16 type; 1279 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1280 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1282 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1283 __le16 event_id; 1284 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1285 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1286 __le32 event_data2; 1287 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1288 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1289 u8 opaque_v; 1290 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1291 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1293 u8 timestamp_lo; 1294 __le16 timestamp_hi; 1295 __le32 event_data1; 1296 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1297 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1298 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1299 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1300 }; 1301 1302 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1303 struct hwrm_async_event_cmpl_error_report_nvm { 1304 __le16 type; 1305 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1307 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1308 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1309 __le16 event_id; 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1312 __le32 event_data2; 1313 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1315 u8 opaque_v; 1316 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1317 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1319 u8 timestamp_lo; 1320 __le16 timestamp_hi; 1321 __le32 event_data1; 1322 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1325 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1328 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1331 }; 1332 1333 /* hwrm_func_reset_input (size:192b/24B) */ 1334 struct hwrm_func_reset_input { 1335 __le16 req_type; 1336 __le16 cmpl_ring; 1337 __le16 seq_id; 1338 __le16 target_id; 1339 __le64 resp_addr; 1340 __le32 enables; 1341 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1342 __le16 vf_id; 1343 u8 func_reset_level; 1344 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1345 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1346 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1347 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1348 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1349 u8 unused_0; 1350 }; 1351 1352 /* hwrm_func_reset_output (size:128b/16B) */ 1353 struct hwrm_func_reset_output { 1354 __le16 error_code; 1355 __le16 req_type; 1356 __le16 seq_id; 1357 __le16 resp_len; 1358 u8 unused_0[7]; 1359 u8 valid; 1360 }; 1361 1362 /* hwrm_func_getfid_input (size:192b/24B) */ 1363 struct hwrm_func_getfid_input { 1364 __le16 req_type; 1365 __le16 cmpl_ring; 1366 __le16 seq_id; 1367 __le16 target_id; 1368 __le64 resp_addr; 1369 __le32 enables; 1370 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1371 __le16 pci_id; 1372 u8 unused_0[2]; 1373 }; 1374 1375 /* hwrm_func_getfid_output (size:128b/16B) */ 1376 struct hwrm_func_getfid_output { 1377 __le16 error_code; 1378 __le16 req_type; 1379 __le16 seq_id; 1380 __le16 resp_len; 1381 __le16 fid; 1382 u8 unused_0[5]; 1383 u8 valid; 1384 }; 1385 1386 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1387 struct hwrm_func_vf_alloc_input { 1388 __le16 req_type; 1389 __le16 cmpl_ring; 1390 __le16 seq_id; 1391 __le16 target_id; 1392 __le64 resp_addr; 1393 __le32 enables; 1394 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1395 __le16 first_vf_id; 1396 __le16 num_vfs; 1397 }; 1398 1399 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1400 struct hwrm_func_vf_alloc_output { 1401 __le16 error_code; 1402 __le16 req_type; 1403 __le16 seq_id; 1404 __le16 resp_len; 1405 __le16 first_vf_id; 1406 u8 unused_0[5]; 1407 u8 valid; 1408 }; 1409 1410 /* hwrm_func_vf_free_input (size:192b/24B) */ 1411 struct hwrm_func_vf_free_input { 1412 __le16 req_type; 1413 __le16 cmpl_ring; 1414 __le16 seq_id; 1415 __le16 target_id; 1416 __le64 resp_addr; 1417 __le32 enables; 1418 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1419 __le16 first_vf_id; 1420 __le16 num_vfs; 1421 }; 1422 1423 /* hwrm_func_vf_free_output (size:128b/16B) */ 1424 struct hwrm_func_vf_free_output { 1425 __le16 error_code; 1426 __le16 req_type; 1427 __le16 seq_id; 1428 __le16 resp_len; 1429 u8 unused_0[7]; 1430 u8 valid; 1431 }; 1432 1433 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1434 struct hwrm_func_vf_cfg_input { 1435 __le16 req_type; 1436 __le16 cmpl_ring; 1437 __le16 seq_id; 1438 __le16 target_id; 1439 __le64 resp_addr; 1440 __le32 enables; 1441 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1442 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1443 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1444 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1445 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1446 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1447 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1448 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1449 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1450 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1451 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1452 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1453 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL 1454 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL 1455 __le16 mtu; 1456 __le16 guest_vlan; 1457 __le16 async_event_cr; 1458 u8 dflt_mac_addr[6]; 1459 __le32 flags; 1460 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1461 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1462 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1463 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1464 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1465 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1466 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1467 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1468 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1469 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1470 __le16 num_rsscos_ctxs; 1471 __le16 num_cmpl_rings; 1472 __le16 num_tx_rings; 1473 __le16 num_rx_rings; 1474 __le16 num_l2_ctxs; 1475 __le16 num_vnics; 1476 __le16 num_stat_ctxs; 1477 __le16 num_hw_ring_grps; 1478 __le16 num_tx_key_ctxs; 1479 __le16 num_rx_key_ctxs; 1480 }; 1481 1482 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1483 struct hwrm_func_vf_cfg_output { 1484 __le16 error_code; 1485 __le16 req_type; 1486 __le16 seq_id; 1487 __le16 resp_len; 1488 u8 unused_0[7]; 1489 u8 valid; 1490 }; 1491 1492 /* hwrm_func_qcaps_input (size:192b/24B) */ 1493 struct hwrm_func_qcaps_input { 1494 __le16 req_type; 1495 __le16 cmpl_ring; 1496 __le16 seq_id; 1497 __le16 target_id; 1498 __le64 resp_addr; 1499 __le16 fid; 1500 u8 unused_0[6]; 1501 }; 1502 1503 /* hwrm_func_qcaps_output (size:768b/96B) */ 1504 struct hwrm_func_qcaps_output { 1505 __le16 error_code; 1506 __le16 req_type; 1507 __le16 seq_id; 1508 __le16 resp_len; 1509 __le16 fid; 1510 __le16 port_id; 1511 __le32 flags; 1512 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1513 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1514 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1515 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1516 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1517 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1518 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1519 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1520 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1521 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1522 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1523 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1524 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1525 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1526 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1527 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1528 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1529 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1530 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1531 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1532 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1533 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1534 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1535 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1536 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1537 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1538 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1539 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1540 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1541 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1542 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1543 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1544 u8 mac_address[6]; 1545 __le16 max_rsscos_ctx; 1546 __le16 max_cmpl_rings; 1547 __le16 max_tx_rings; 1548 __le16 max_rx_rings; 1549 __le16 max_l2_ctxs; 1550 __le16 max_vnics; 1551 __le16 first_vf_id; 1552 __le16 max_vfs; 1553 __le16 max_stat_ctx; 1554 __le32 max_encap_records; 1555 __le32 max_decap_records; 1556 __le32 max_tx_em_flows; 1557 __le32 max_tx_wm_flows; 1558 __le32 max_rx_em_flows; 1559 __le32 max_rx_wm_flows; 1560 __le32 max_mcast_filters; 1561 __le32 max_flow_id; 1562 __le32 max_hw_ring_grps; 1563 __le16 max_sp_tx_rings; 1564 __le16 max_msix_vfs; 1565 __le32 flags_ext; 1566 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1567 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1568 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1569 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1570 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1571 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1572 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1573 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1574 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1575 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1576 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1577 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1578 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1579 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1580 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1581 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1582 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1583 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1584 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1585 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1586 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1587 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1588 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1589 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1590 u8 max_schqs; 1591 u8 mpc_chnls_cap; 1592 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1593 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1594 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1595 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1596 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1597 __le16 max_key_ctxs_alloc; 1598 u8 unused_1[7]; 1599 u8 valid; 1600 }; 1601 1602 /* hwrm_func_qcfg_input (size:192b/24B) */ 1603 struct hwrm_func_qcfg_input { 1604 __le16 req_type; 1605 __le16 cmpl_ring; 1606 __le16 seq_id; 1607 __le16 target_id; 1608 __le64 resp_addr; 1609 __le16 fid; 1610 u8 unused_0[6]; 1611 }; 1612 1613 /* hwrm_func_qcfg_output (size:896b/112B) */ 1614 struct hwrm_func_qcfg_output { 1615 __le16 error_code; 1616 __le16 req_type; 1617 __le16 seq_id; 1618 __le16 resp_len; 1619 __le16 fid; 1620 __le16 port_id; 1621 __le16 vlan; 1622 __le16 flags; 1623 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1624 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1625 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1626 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1627 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1628 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1629 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1630 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1631 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1632 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1633 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1634 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1635 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1636 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1637 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1638 u8 mac_address[6]; 1639 __le16 pci_id; 1640 __le16 alloc_rsscos_ctx; 1641 __le16 alloc_cmpl_rings; 1642 __le16 alloc_tx_rings; 1643 __le16 alloc_rx_rings; 1644 __le16 alloc_l2_ctx; 1645 __le16 alloc_vnics; 1646 __le16 admin_mtu; 1647 __le16 mru; 1648 __le16 stat_ctx_id; 1649 u8 port_partition_type; 1650 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1651 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1652 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1653 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1654 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1655 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1656 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1657 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1658 u8 port_pf_cnt; 1659 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1660 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1661 __le16 dflt_vnic_id; 1662 __le16 max_mtu_configured; 1663 __le32 min_bw; 1664 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1665 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1666 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1667 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1668 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1669 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1670 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1671 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1672 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1673 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1674 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1675 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1676 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1677 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1678 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1679 __le32 max_bw; 1680 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1681 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1682 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1683 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1684 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1685 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1686 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1687 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1688 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1689 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1690 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1691 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1692 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1693 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1694 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1695 u8 evb_mode; 1696 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1697 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1698 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1699 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1700 u8 options; 1701 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1702 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1703 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1704 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1705 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1706 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1707 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1708 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1709 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1710 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1711 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1712 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1713 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1714 __le16 alloc_vfs; 1715 __le32 alloc_mcast_filters; 1716 __le32 alloc_hw_ring_grps; 1717 __le16 alloc_sp_tx_rings; 1718 __le16 alloc_stat_ctx; 1719 __le16 alloc_msix; 1720 __le16 registered_vfs; 1721 __le16 l2_doorbell_bar_size_kb; 1722 u8 unused_1; 1723 u8 always_1; 1724 __le32 reset_addr_poll; 1725 __le16 legacy_l2_db_size_kb; 1726 __le16 svif_info; 1727 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1728 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1729 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1730 u8 mpc_chnls; 1731 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1732 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1733 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1734 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1735 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1736 u8 unused_2[3]; 1737 __le32 partition_min_bw; 1738 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1739 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1740 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1741 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1742 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1743 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1744 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1745 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1746 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1747 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1748 __le32 partition_max_bw; 1749 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1750 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 1751 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 1752 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1753 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1754 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 1755 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1756 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1757 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1758 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1759 __le16 host_mtu; 1760 __le16 alloc_tx_key_ctxs; 1761 __le16 alloc_rx_key_ctxs; 1762 u8 unused_3[5]; 1763 u8 valid; 1764 }; 1765 1766 /* hwrm_func_cfg_input (size:896b/112B) */ 1767 struct hwrm_func_cfg_input { 1768 __le16 req_type; 1769 __le16 cmpl_ring; 1770 __le16 seq_id; 1771 __le16 target_id; 1772 __le64 resp_addr; 1773 __le16 fid; 1774 __le16 num_msix; 1775 __le32 flags; 1776 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1777 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1778 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1779 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1780 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1781 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1782 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1783 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1784 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1785 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1786 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1787 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1788 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1789 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1790 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1791 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1792 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1793 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1794 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1795 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1796 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1797 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1798 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1799 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1800 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1801 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1802 __le32 enables; 1803 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1804 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1805 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1806 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1807 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1808 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1809 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1810 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1811 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1812 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1813 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1814 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1815 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1816 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1817 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1818 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1819 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1820 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1821 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1822 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1823 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1824 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1825 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1826 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1827 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1828 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1829 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 1830 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 1831 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 1832 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1833 #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL 1834 #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL 1835 __le16 admin_mtu; 1836 __le16 mru; 1837 __le16 num_rsscos_ctxs; 1838 __le16 num_cmpl_rings; 1839 __le16 num_tx_rings; 1840 __le16 num_rx_rings; 1841 __le16 num_l2_ctxs; 1842 __le16 num_vnics; 1843 __le16 num_stat_ctxs; 1844 __le16 num_hw_ring_grps; 1845 u8 dflt_mac_addr[6]; 1846 __le16 dflt_vlan; 1847 __be32 dflt_ip_addr[4]; 1848 __le32 min_bw; 1849 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1850 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1851 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1852 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1853 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1854 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1855 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1856 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1857 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1858 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1859 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1860 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1861 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1862 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1863 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1864 __le32 max_bw; 1865 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1866 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1867 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1868 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1869 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1870 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1871 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1872 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1873 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1874 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1875 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1876 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1877 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1878 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1879 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1880 __le16 async_event_cr; 1881 u8 vlan_antispoof_mode; 1882 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1883 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1884 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1885 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1886 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1887 u8 allowed_vlan_pris; 1888 u8 evb_mode; 1889 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1890 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1891 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1892 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1893 u8 options; 1894 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1895 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1896 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1897 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1898 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1899 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1900 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1901 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1902 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1903 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1904 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1905 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1906 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1907 __le16 num_mcast_filters; 1908 __le16 schq_id; 1909 __le16 mpc_chnls; 1910 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1911 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1912 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1913 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1914 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1915 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1916 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1917 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1918 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1919 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1920 __le32 partition_min_bw; 1921 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1922 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 1923 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 1924 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1925 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1926 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 1927 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1928 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1929 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1930 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1931 __le32 partition_max_bw; 1932 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1933 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 1934 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 1935 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1936 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1937 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 1938 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1939 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1940 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1941 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1942 __be16 tpid; 1943 __le16 host_mtu; 1944 __le16 num_tx_key_ctxs; 1945 __le16 num_rx_key_ctxs; 1946 u8 unused_0[4]; 1947 }; 1948 1949 /* hwrm_func_cfg_output (size:128b/16B) */ 1950 struct hwrm_func_cfg_output { 1951 __le16 error_code; 1952 __le16 req_type; 1953 __le16 seq_id; 1954 __le16 resp_len; 1955 u8 unused_0[7]; 1956 u8 valid; 1957 }; 1958 1959 /* hwrm_func_qstats_input (size:192b/24B) */ 1960 struct hwrm_func_qstats_input { 1961 __le16 req_type; 1962 __le16 cmpl_ring; 1963 __le16 seq_id; 1964 __le16 target_id; 1965 __le64 resp_addr; 1966 __le16 fid; 1967 u8 flags; 1968 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1969 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1970 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1971 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1972 u8 unused_0[5]; 1973 }; 1974 1975 /* hwrm_func_qstats_output (size:1408b/176B) */ 1976 struct hwrm_func_qstats_output { 1977 __le16 error_code; 1978 __le16 req_type; 1979 __le16 seq_id; 1980 __le16 resp_len; 1981 __le64 tx_ucast_pkts; 1982 __le64 tx_mcast_pkts; 1983 __le64 tx_bcast_pkts; 1984 __le64 tx_discard_pkts; 1985 __le64 tx_drop_pkts; 1986 __le64 tx_ucast_bytes; 1987 __le64 tx_mcast_bytes; 1988 __le64 tx_bcast_bytes; 1989 __le64 rx_ucast_pkts; 1990 __le64 rx_mcast_pkts; 1991 __le64 rx_bcast_pkts; 1992 __le64 rx_discard_pkts; 1993 __le64 rx_drop_pkts; 1994 __le64 rx_ucast_bytes; 1995 __le64 rx_mcast_bytes; 1996 __le64 rx_bcast_bytes; 1997 __le64 rx_agg_pkts; 1998 __le64 rx_agg_bytes; 1999 __le64 rx_agg_events; 2000 __le64 rx_agg_aborts; 2001 u8 unused_0[7]; 2002 u8 valid; 2003 }; 2004 2005 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2006 struct hwrm_func_qstats_ext_input { 2007 __le16 req_type; 2008 __le16 cmpl_ring; 2009 __le16 seq_id; 2010 __le16 target_id; 2011 __le64 resp_addr; 2012 __le16 fid; 2013 u8 flags; 2014 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2015 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2016 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2017 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2018 u8 unused_0[1]; 2019 __le32 enables; 2020 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2021 __le16 schq_id; 2022 __le16 traffic_class; 2023 u8 unused_1[4]; 2024 }; 2025 2026 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2027 struct hwrm_func_qstats_ext_output { 2028 __le16 error_code; 2029 __le16 req_type; 2030 __le16 seq_id; 2031 __le16 resp_len; 2032 __le64 rx_ucast_pkts; 2033 __le64 rx_mcast_pkts; 2034 __le64 rx_bcast_pkts; 2035 __le64 rx_discard_pkts; 2036 __le64 rx_error_pkts; 2037 __le64 rx_ucast_bytes; 2038 __le64 rx_mcast_bytes; 2039 __le64 rx_bcast_bytes; 2040 __le64 tx_ucast_pkts; 2041 __le64 tx_mcast_pkts; 2042 __le64 tx_bcast_pkts; 2043 __le64 tx_error_pkts; 2044 __le64 tx_discard_pkts; 2045 __le64 tx_ucast_bytes; 2046 __le64 tx_mcast_bytes; 2047 __le64 tx_bcast_bytes; 2048 __le64 rx_tpa_eligible_pkt; 2049 __le64 rx_tpa_eligible_bytes; 2050 __le64 rx_tpa_pkt; 2051 __le64 rx_tpa_bytes; 2052 __le64 rx_tpa_errors; 2053 __le64 rx_tpa_events; 2054 u8 unused_0[7]; 2055 u8 valid; 2056 }; 2057 2058 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2059 struct hwrm_func_clr_stats_input { 2060 __le16 req_type; 2061 __le16 cmpl_ring; 2062 __le16 seq_id; 2063 __le16 target_id; 2064 __le64 resp_addr; 2065 __le16 fid; 2066 u8 unused_0[6]; 2067 }; 2068 2069 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2070 struct hwrm_func_clr_stats_output { 2071 __le16 error_code; 2072 __le16 req_type; 2073 __le16 seq_id; 2074 __le16 resp_len; 2075 u8 unused_0[7]; 2076 u8 valid; 2077 }; 2078 2079 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2080 struct hwrm_func_vf_resc_free_input { 2081 __le16 req_type; 2082 __le16 cmpl_ring; 2083 __le16 seq_id; 2084 __le16 target_id; 2085 __le64 resp_addr; 2086 __le16 vf_id; 2087 u8 unused_0[6]; 2088 }; 2089 2090 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2091 struct hwrm_func_vf_resc_free_output { 2092 __le16 error_code; 2093 __le16 req_type; 2094 __le16 seq_id; 2095 __le16 resp_len; 2096 u8 unused_0[7]; 2097 u8 valid; 2098 }; 2099 2100 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2101 struct hwrm_func_drv_rgtr_input { 2102 __le16 req_type; 2103 __le16 cmpl_ring; 2104 __le16 seq_id; 2105 __le16 target_id; 2106 __le64 resp_addr; 2107 __le32 flags; 2108 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2109 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2110 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2111 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2112 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2113 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2114 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2115 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2116 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2117 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2118 __le32 enables; 2119 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2120 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2121 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2122 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2123 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2124 __le16 os_type; 2125 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2126 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2127 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2128 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2129 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2130 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2131 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2132 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2133 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2134 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2135 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2136 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2137 u8 ver_maj_8b; 2138 u8 ver_min_8b; 2139 u8 ver_upd_8b; 2140 u8 unused_0[3]; 2141 __le32 timestamp; 2142 u8 unused_1[4]; 2143 __le32 vf_req_fwd[8]; 2144 __le32 async_event_fwd[8]; 2145 __le16 ver_maj; 2146 __le16 ver_min; 2147 __le16 ver_upd; 2148 __le16 ver_patch; 2149 }; 2150 2151 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2152 struct hwrm_func_drv_rgtr_output { 2153 __le16 error_code; 2154 __le16 req_type; 2155 __le16 seq_id; 2156 __le16 resp_len; 2157 __le32 flags; 2158 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2159 u8 unused_0[3]; 2160 u8 valid; 2161 }; 2162 2163 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2164 struct hwrm_func_drv_unrgtr_input { 2165 __le16 req_type; 2166 __le16 cmpl_ring; 2167 __le16 seq_id; 2168 __le16 target_id; 2169 __le64 resp_addr; 2170 __le32 flags; 2171 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2172 u8 unused_0[4]; 2173 }; 2174 2175 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2176 struct hwrm_func_drv_unrgtr_output { 2177 __le16 error_code; 2178 __le16 req_type; 2179 __le16 seq_id; 2180 __le16 resp_len; 2181 u8 unused_0[7]; 2182 u8 valid; 2183 }; 2184 2185 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2186 struct hwrm_func_buf_rgtr_input { 2187 __le16 req_type; 2188 __le16 cmpl_ring; 2189 __le16 seq_id; 2190 __le16 target_id; 2191 __le64 resp_addr; 2192 __le32 enables; 2193 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2194 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2195 __le16 vf_id; 2196 __le16 req_buf_num_pages; 2197 __le16 req_buf_page_size; 2198 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2199 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2200 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2201 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2202 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2203 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2204 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2205 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2206 __le16 req_buf_len; 2207 __le16 resp_buf_len; 2208 u8 unused_0[2]; 2209 __le64 req_buf_page_addr0; 2210 __le64 req_buf_page_addr1; 2211 __le64 req_buf_page_addr2; 2212 __le64 req_buf_page_addr3; 2213 __le64 req_buf_page_addr4; 2214 __le64 req_buf_page_addr5; 2215 __le64 req_buf_page_addr6; 2216 __le64 req_buf_page_addr7; 2217 __le64 req_buf_page_addr8; 2218 __le64 req_buf_page_addr9; 2219 __le64 error_buf_addr; 2220 __le64 resp_buf_addr; 2221 }; 2222 2223 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2224 struct hwrm_func_buf_rgtr_output { 2225 __le16 error_code; 2226 __le16 req_type; 2227 __le16 seq_id; 2228 __le16 resp_len; 2229 u8 unused_0[7]; 2230 u8 valid; 2231 }; 2232 2233 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2234 struct hwrm_func_drv_qver_input { 2235 __le16 req_type; 2236 __le16 cmpl_ring; 2237 __le16 seq_id; 2238 __le16 target_id; 2239 __le64 resp_addr; 2240 __le32 reserved; 2241 __le16 fid; 2242 u8 unused_0[2]; 2243 }; 2244 2245 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2246 struct hwrm_func_drv_qver_output { 2247 __le16 error_code; 2248 __le16 req_type; 2249 __le16 seq_id; 2250 __le16 resp_len; 2251 __le16 os_type; 2252 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2253 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2254 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2255 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2256 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2257 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2258 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2259 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2260 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2261 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2262 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2263 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2264 u8 ver_maj_8b; 2265 u8 ver_min_8b; 2266 u8 ver_upd_8b; 2267 u8 unused_0[3]; 2268 __le16 ver_maj; 2269 __le16 ver_min; 2270 __le16 ver_upd; 2271 __le16 ver_patch; 2272 u8 unused_1[7]; 2273 u8 valid; 2274 }; 2275 2276 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2277 struct hwrm_func_resource_qcaps_input { 2278 __le16 req_type; 2279 __le16 cmpl_ring; 2280 __le16 seq_id; 2281 __le16 target_id; 2282 __le64 resp_addr; 2283 __le16 fid; 2284 u8 unused_0[6]; 2285 }; 2286 2287 /* hwrm_func_resource_qcaps_output (size:512b/64B) */ 2288 struct hwrm_func_resource_qcaps_output { 2289 __le16 error_code; 2290 __le16 req_type; 2291 __le16 seq_id; 2292 __le16 resp_len; 2293 __le16 max_vfs; 2294 __le16 max_msix; 2295 __le16 vf_reservation_strategy; 2296 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2297 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2298 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2299 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2300 __le16 min_rsscos_ctx; 2301 __le16 max_rsscos_ctx; 2302 __le16 min_cmpl_rings; 2303 __le16 max_cmpl_rings; 2304 __le16 min_tx_rings; 2305 __le16 max_tx_rings; 2306 __le16 min_rx_rings; 2307 __le16 max_rx_rings; 2308 __le16 min_l2_ctxs; 2309 __le16 max_l2_ctxs; 2310 __le16 min_vnics; 2311 __le16 max_vnics; 2312 __le16 min_stat_ctx; 2313 __le16 max_stat_ctx; 2314 __le16 min_hw_ring_grps; 2315 __le16 max_hw_ring_grps; 2316 __le16 max_tx_scheduler_inputs; 2317 __le16 flags; 2318 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2319 __le16 min_tx_key_ctxs; 2320 __le16 max_tx_key_ctxs; 2321 __le16 min_rx_key_ctxs; 2322 __le16 max_rx_key_ctxs; 2323 u8 unused_0[5]; 2324 u8 valid; 2325 }; 2326 2327 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ 2328 struct hwrm_func_vf_resource_cfg_input { 2329 __le16 req_type; 2330 __le16 cmpl_ring; 2331 __le16 seq_id; 2332 __le16 target_id; 2333 __le64 resp_addr; 2334 __le16 vf_id; 2335 __le16 max_msix; 2336 __le16 min_rsscos_ctx; 2337 __le16 max_rsscos_ctx; 2338 __le16 min_cmpl_rings; 2339 __le16 max_cmpl_rings; 2340 __le16 min_tx_rings; 2341 __le16 max_tx_rings; 2342 __le16 min_rx_rings; 2343 __le16 max_rx_rings; 2344 __le16 min_l2_ctxs; 2345 __le16 max_l2_ctxs; 2346 __le16 min_vnics; 2347 __le16 max_vnics; 2348 __le16 min_stat_ctx; 2349 __le16 max_stat_ctx; 2350 __le16 min_hw_ring_grps; 2351 __le16 max_hw_ring_grps; 2352 __le16 flags; 2353 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2354 __le16 min_tx_key_ctxs; 2355 __le16 max_tx_key_ctxs; 2356 __le16 min_rx_key_ctxs; 2357 __le16 max_rx_key_ctxs; 2358 u8 unused_0[2]; 2359 }; 2360 2361 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2362 struct hwrm_func_vf_resource_cfg_output { 2363 __le16 error_code; 2364 __le16 req_type; 2365 __le16 seq_id; 2366 __le16 resp_len; 2367 __le16 reserved_rsscos_ctx; 2368 __le16 reserved_cmpl_rings; 2369 __le16 reserved_tx_rings; 2370 __le16 reserved_rx_rings; 2371 __le16 reserved_l2_ctxs; 2372 __le16 reserved_vnics; 2373 __le16 reserved_stat_ctx; 2374 __le16 reserved_hw_ring_grps; 2375 __le16 reserved_tx_key_ctxs; 2376 __le16 reserved_rx_key_ctxs; 2377 u8 unused_0[3]; 2378 u8 valid; 2379 }; 2380 2381 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2382 struct hwrm_func_backing_store_qcaps_input { 2383 __le16 req_type; 2384 __le16 cmpl_ring; 2385 __le16 seq_id; 2386 __le16 target_id; 2387 __le64 resp_addr; 2388 }; 2389 2390 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2391 struct hwrm_func_backing_store_qcaps_output { 2392 __le16 error_code; 2393 __le16 req_type; 2394 __le16 seq_id; 2395 __le16 resp_len; 2396 __le32 qp_max_entries; 2397 __le16 qp_min_qp1_entries; 2398 __le16 qp_max_l2_entries; 2399 __le16 qp_entry_size; 2400 __le16 srq_max_l2_entries; 2401 __le32 srq_max_entries; 2402 __le16 srq_entry_size; 2403 __le16 cq_max_l2_entries; 2404 __le32 cq_max_entries; 2405 __le16 cq_entry_size; 2406 __le16 vnic_max_vnic_entries; 2407 __le16 vnic_max_ring_table_entries; 2408 __le16 vnic_entry_size; 2409 __le32 stat_max_entries; 2410 __le16 stat_entry_size; 2411 __le16 tqm_entry_size; 2412 __le32 tqm_min_entries_per_ring; 2413 __le32 tqm_max_entries_per_ring; 2414 __le32 mrav_max_entries; 2415 __le16 mrav_entry_size; 2416 __le16 tim_entry_size; 2417 __le32 tim_max_entries; 2418 __le16 mrav_num_entries_units; 2419 u8 tqm_entries_multiple; 2420 u8 ctx_kind_initializer; 2421 __le16 ctx_init_mask; 2422 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2423 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2424 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2425 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2426 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2427 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2428 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2429 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2430 u8 qp_init_offset; 2431 u8 srq_init_offset; 2432 u8 cq_init_offset; 2433 u8 vnic_init_offset; 2434 u8 tqm_fp_rings_count; 2435 u8 stat_init_offset; 2436 u8 mrav_init_offset; 2437 u8 tqm_fp_rings_count_ext; 2438 u8 tkc_init_offset; 2439 u8 rkc_init_offset; 2440 __le16 tkc_entry_size; 2441 __le16 rkc_entry_size; 2442 __le32 tkc_max_entries; 2443 __le32 rkc_max_entries; 2444 u8 rsvd[7]; 2445 u8 valid; 2446 }; 2447 2448 /* tqm_fp_ring_cfg (size:128b/16B) */ 2449 struct tqm_fp_ring_cfg { 2450 u8 tqm_ring_pg_size_tqm_ring_lvl; 2451 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2452 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2453 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2454 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2455 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2456 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2457 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2458 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2459 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2460 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2461 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2462 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2463 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2464 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2465 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2466 u8 unused[3]; 2467 __le32 tqm_ring_num_entries; 2468 __le64 tqm_ring_page_dir; 2469 }; 2470 2471 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2472 struct hwrm_func_backing_store_cfg_input { 2473 __le16 req_type; 2474 __le16 cmpl_ring; 2475 __le16 seq_id; 2476 __le16 target_id; 2477 __le64 resp_addr; 2478 __le32 flags; 2479 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2480 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2481 __le32 enables; 2482 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2483 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2484 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2485 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2486 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2487 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2488 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2489 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2490 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2491 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2492 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2493 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2494 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2495 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2496 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2497 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2498 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2499 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2500 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2501 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2502 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2503 u8 qpc_pg_size_qpc_lvl; 2504 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2505 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2506 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2507 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2508 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2509 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2510 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2511 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2512 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2513 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2514 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2515 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2516 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2517 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2518 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2519 u8 srq_pg_size_srq_lvl; 2520 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2521 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2522 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2523 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2524 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2525 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2526 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2527 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2528 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2529 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2530 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2531 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2532 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2533 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2534 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2535 u8 cq_pg_size_cq_lvl; 2536 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2537 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2538 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2539 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2540 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2541 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2542 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2543 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2544 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2545 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2546 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2547 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2548 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2549 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2550 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2551 u8 vnic_pg_size_vnic_lvl; 2552 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2553 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2554 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2555 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2556 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2557 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2558 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2559 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2560 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2561 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2562 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2563 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2564 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2565 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2566 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2567 u8 stat_pg_size_stat_lvl; 2568 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2569 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2570 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2571 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2572 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2573 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2574 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2575 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2576 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2577 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2578 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2579 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2580 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2581 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2582 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2583 u8 tqm_sp_pg_size_tqm_sp_lvl; 2584 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2585 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2586 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2587 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2588 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2589 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2590 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2591 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2592 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2593 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2594 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2595 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2596 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2597 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2598 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2599 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2600 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2601 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2602 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2603 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2604 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2605 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2606 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2607 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2608 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2609 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2610 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2611 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2612 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2613 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2614 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2615 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2616 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2617 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2618 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2619 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2620 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2621 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2622 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2623 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2624 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2625 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2626 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2627 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2628 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2629 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2630 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2631 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2632 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2633 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2634 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2635 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2636 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2637 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2638 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2639 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2645 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2647 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2648 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2653 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2654 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2655 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2661 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2663 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2664 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2669 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2670 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2671 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2677 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2679 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2680 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2695 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2696 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2702 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2703 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2709 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2710 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2711 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2712 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2718 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2719 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2725 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2726 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2727 u8 mrav_pg_size_mrav_lvl; 2728 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2729 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2730 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2731 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2732 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2733 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2734 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2735 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2736 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2737 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2738 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2739 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2740 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2741 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2742 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2743 u8 tim_pg_size_tim_lvl; 2744 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2745 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2746 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2747 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2748 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2749 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2750 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2751 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2752 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2753 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2754 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2755 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2756 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2757 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2758 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2759 __le64 qpc_page_dir; 2760 __le64 srq_page_dir; 2761 __le64 cq_page_dir; 2762 __le64 vnic_page_dir; 2763 __le64 stat_page_dir; 2764 __le64 tqm_sp_page_dir; 2765 __le64 tqm_ring0_page_dir; 2766 __le64 tqm_ring1_page_dir; 2767 __le64 tqm_ring2_page_dir; 2768 __le64 tqm_ring3_page_dir; 2769 __le64 tqm_ring4_page_dir; 2770 __le64 tqm_ring5_page_dir; 2771 __le64 tqm_ring6_page_dir; 2772 __le64 tqm_ring7_page_dir; 2773 __le64 mrav_page_dir; 2774 __le64 tim_page_dir; 2775 __le32 qp_num_entries; 2776 __le32 srq_num_entries; 2777 __le32 cq_num_entries; 2778 __le32 stat_num_entries; 2779 __le32 tqm_sp_num_entries; 2780 __le32 tqm_ring0_num_entries; 2781 __le32 tqm_ring1_num_entries; 2782 __le32 tqm_ring2_num_entries; 2783 __le32 tqm_ring3_num_entries; 2784 __le32 tqm_ring4_num_entries; 2785 __le32 tqm_ring5_num_entries; 2786 __le32 tqm_ring6_num_entries; 2787 __le32 tqm_ring7_num_entries; 2788 __le32 mrav_num_entries; 2789 __le32 tim_num_entries; 2790 __le16 qp_num_qp1_entries; 2791 __le16 qp_num_l2_entries; 2792 __le16 qp_entry_size; 2793 __le16 srq_num_l2_entries; 2794 __le16 srq_entry_size; 2795 __le16 cq_num_l2_entries; 2796 __le16 cq_entry_size; 2797 __le16 vnic_num_vnic_entries; 2798 __le16 vnic_num_ring_table_entries; 2799 __le16 vnic_entry_size; 2800 __le16 stat_entry_size; 2801 __le16 tqm_entry_size; 2802 __le16 mrav_entry_size; 2803 __le16 tim_entry_size; 2804 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2805 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2806 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2807 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2808 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2809 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2810 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2811 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2812 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2813 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2814 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2815 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2816 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2817 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2818 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2819 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2820 u8 ring8_unused[3]; 2821 __le32 tqm_ring8_num_entries; 2822 __le64 tqm_ring8_page_dir; 2823 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2824 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2825 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2826 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2827 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2828 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2829 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2830 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2831 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2832 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2833 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2834 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2835 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2836 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2837 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2838 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2839 u8 ring9_unused[3]; 2840 __le32 tqm_ring9_num_entries; 2841 __le64 tqm_ring9_page_dir; 2842 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2843 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2844 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2845 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2846 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2847 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2848 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2849 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2850 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2851 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2852 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2853 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2854 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2855 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2856 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2857 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2858 u8 ring10_unused[3]; 2859 __le32 tqm_ring10_num_entries; 2860 __le64 tqm_ring10_page_dir; 2861 __le32 tkc_num_entries; 2862 __le32 rkc_num_entries; 2863 __le64 tkc_page_dir; 2864 __le64 rkc_page_dir; 2865 __le16 tkc_entry_size; 2866 __le16 rkc_entry_size; 2867 u8 tkc_pg_size_tkc_lvl; 2868 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 2869 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 2870 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 2871 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 2872 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 2873 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 2874 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 2875 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 2876 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 2877 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 2878 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 2879 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 2880 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 2881 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 2882 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 2883 u8 rkc_pg_size_rkc_lvl; 2884 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 2885 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 2886 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 2887 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 2888 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 2889 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 2890 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 2891 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 2892 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 2893 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 2894 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 2895 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 2896 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 2897 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 2898 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 2899 u8 rsvd[2]; 2900 }; 2901 2902 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2903 struct hwrm_func_backing_store_cfg_output { 2904 __le16 error_code; 2905 __le16 req_type; 2906 __le16 seq_id; 2907 __le16 resp_len; 2908 u8 unused_0[7]; 2909 u8 valid; 2910 }; 2911 2912 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2913 struct hwrm_error_recovery_qcfg_input { 2914 __le16 req_type; 2915 __le16 cmpl_ring; 2916 __le16 seq_id; 2917 __le16 target_id; 2918 __le64 resp_addr; 2919 u8 unused_0[8]; 2920 }; 2921 2922 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2923 struct hwrm_error_recovery_qcfg_output { 2924 __le16 error_code; 2925 __le16 req_type; 2926 __le16 seq_id; 2927 __le16 resp_len; 2928 __le32 flags; 2929 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2930 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2931 __le32 driver_polling_freq; 2932 __le32 master_func_wait_period; 2933 __le32 normal_func_wait_period; 2934 __le32 master_func_wait_period_after_reset; 2935 __le32 max_bailout_time_after_reset; 2936 __le32 fw_health_status_reg; 2937 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2938 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2939 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2940 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2941 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2942 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2943 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2944 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2945 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2946 __le32 fw_heartbeat_reg; 2947 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2948 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2949 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2950 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2951 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2952 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2953 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2954 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2955 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2956 __le32 fw_reset_cnt_reg; 2957 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2958 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2959 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2960 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2961 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2962 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2963 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2964 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2965 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2966 __le32 reset_inprogress_reg; 2967 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2968 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2969 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2970 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2971 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2972 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2973 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2974 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2975 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2976 __le32 reset_inprogress_reg_mask; 2977 u8 unused_0[3]; 2978 u8 reg_array_cnt; 2979 __le32 reset_reg[16]; 2980 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2981 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2982 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2983 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2984 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2985 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2986 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2987 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2988 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2989 __le32 reset_reg_val[16]; 2990 u8 delay_after_reset[16]; 2991 __le32 err_recovery_cnt_reg; 2992 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2993 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2994 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2995 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2996 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2997 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2998 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2999 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3000 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3001 u8 unused_1[3]; 3002 u8 valid; 3003 }; 3004 3005 /* hwrm_func_echo_response_input (size:192b/24B) */ 3006 struct hwrm_func_echo_response_input { 3007 __le16 req_type; 3008 __le16 cmpl_ring; 3009 __le16 seq_id; 3010 __le16 target_id; 3011 __le64 resp_addr; 3012 __le32 event_data1; 3013 __le32 event_data2; 3014 }; 3015 3016 /* hwrm_func_echo_response_output (size:128b/16B) */ 3017 struct hwrm_func_echo_response_output { 3018 __le16 error_code; 3019 __le16 req_type; 3020 __le16 seq_id; 3021 __le16 resp_len; 3022 u8 unused_0[7]; 3023 u8 valid; 3024 }; 3025 3026 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3027 struct hwrm_func_ptp_pin_qcfg_input { 3028 __le16 req_type; 3029 __le16 cmpl_ring; 3030 __le16 seq_id; 3031 __le16 target_id; 3032 __le64 resp_addr; 3033 u8 unused_0[8]; 3034 }; 3035 3036 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3037 struct hwrm_func_ptp_pin_qcfg_output { 3038 __le16 error_code; 3039 __le16 req_type; 3040 __le16 seq_id; 3041 __le16 resp_len; 3042 u8 num_pins; 3043 u8 state; 3044 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3045 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3046 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3047 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3048 u8 pin0_usage; 3049 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3050 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3051 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3052 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3053 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3054 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3055 u8 pin1_usage; 3056 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3057 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3058 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3059 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3060 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3061 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3062 u8 pin2_usage; 3063 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3064 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3065 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3066 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3067 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3068 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 3069 u8 pin3_usage; 3070 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3071 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3072 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3073 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3074 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3075 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 3076 u8 unused_0; 3077 u8 valid; 3078 }; 3079 3080 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3081 struct hwrm_func_ptp_pin_cfg_input { 3082 __le16 req_type; 3083 __le16 cmpl_ring; 3084 __le16 seq_id; 3085 __le16 target_id; 3086 __le64 resp_addr; 3087 __le32 enables; 3088 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3089 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3090 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3091 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3092 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3093 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3094 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3095 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3096 u8 pin0_state; 3097 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3098 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3099 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3100 u8 pin0_usage; 3101 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3102 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3103 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3104 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3105 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3106 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3107 u8 pin1_state; 3108 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3109 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3110 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3111 u8 pin1_usage; 3112 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3113 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3114 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3115 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3116 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3117 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3118 u8 pin2_state; 3119 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3120 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3121 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3122 u8 pin2_usage; 3123 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3124 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3125 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3126 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3127 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3128 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 3129 u8 pin3_state; 3130 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3131 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3132 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3133 u8 pin3_usage; 3134 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3135 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3136 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3137 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3138 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3139 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 3140 u8 unused_0[4]; 3141 }; 3142 3143 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3144 struct hwrm_func_ptp_pin_cfg_output { 3145 __le16 error_code; 3146 __le16 req_type; 3147 __le16 seq_id; 3148 __le16 resp_len; 3149 u8 unused_0[7]; 3150 u8 valid; 3151 }; 3152 3153 /* hwrm_func_ptp_cfg_input (size:320b/40B) */ 3154 struct hwrm_func_ptp_cfg_input { 3155 __le16 req_type; 3156 __le16 cmpl_ring; 3157 __le16 seq_id; 3158 __le16 target_id; 3159 __le64 resp_addr; 3160 __le16 enables; 3161 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3162 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3163 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3164 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3165 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3166 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3167 u8 ptp_pps_event; 3168 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3169 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3170 u8 ptp_freq_adj_dll_source; 3171 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3172 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3173 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3174 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3175 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3176 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3177 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3178 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3179 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3180 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3181 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3182 u8 ptp_freq_adj_dll_phase; 3183 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3184 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3185 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3186 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3187 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 3188 u8 unused_0[3]; 3189 __le32 ptp_freq_adj_ext_period; 3190 __le32 ptp_freq_adj_ext_up; 3191 __le32 ptp_freq_adj_ext_phase_lower; 3192 __le32 ptp_freq_adj_ext_phase_upper; 3193 }; 3194 3195 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3196 struct hwrm_func_ptp_cfg_output { 3197 __le16 error_code; 3198 __le16 req_type; 3199 __le16 seq_id; 3200 __le16 resp_len; 3201 u8 unused_0[7]; 3202 u8 valid; 3203 }; 3204 3205 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3206 struct hwrm_func_ptp_ts_query_input { 3207 __le16 req_type; 3208 __le16 cmpl_ring; 3209 __le16 seq_id; 3210 __le16 target_id; 3211 __le64 resp_addr; 3212 __le32 flags; 3213 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3214 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3215 u8 unused_0[4]; 3216 }; 3217 3218 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3219 struct hwrm_func_ptp_ts_query_output { 3220 __le16 error_code; 3221 __le16 req_type; 3222 __le16 seq_id; 3223 __le16 resp_len; 3224 __le64 pps_event_ts; 3225 __le64 ptm_res_local_ts; 3226 __le64 ptm_pmstr_ts; 3227 __le32 ptm_mstr_prop_dly; 3228 u8 unused_0[3]; 3229 u8 valid; 3230 }; 3231 3232 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 3233 struct hwrm_func_drv_if_change_input { 3234 __le16 req_type; 3235 __le16 cmpl_ring; 3236 __le16 seq_id; 3237 __le16 target_id; 3238 __le64 resp_addr; 3239 __le32 flags; 3240 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 3241 __le32 unused; 3242 }; 3243 3244 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 3245 struct hwrm_func_drv_if_change_output { 3246 __le16 error_code; 3247 __le16 req_type; 3248 __le16 seq_id; 3249 __le16 resp_len; 3250 __le32 flags; 3251 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 3252 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3253 u8 unused_0[3]; 3254 u8 valid; 3255 }; 3256 3257 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3258 struct hwrm_port_phy_cfg_input { 3259 __le16 req_type; 3260 __le16 cmpl_ring; 3261 __le16 seq_id; 3262 __le16 target_id; 3263 __le64 resp_addr; 3264 __le32 flags; 3265 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 3266 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3267 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3268 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 3269 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 3270 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 3271 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 3272 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3273 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3274 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3275 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3276 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3277 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3278 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 3279 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3280 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3281 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 3282 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 3283 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 3284 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 3285 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 3286 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 3287 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3288 __le32 enables; 3289 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3290 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3291 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3292 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3293 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3294 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3295 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3296 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3297 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 3298 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 3299 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3300 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3301 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3302 __le16 port_id; 3303 __le16 force_link_speed; 3304 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3305 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3306 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3307 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3308 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3309 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3310 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3311 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3312 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3313 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3314 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3315 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3316 u8 auto_mode; 3317 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3318 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3319 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3320 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3321 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3322 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3323 u8 auto_duplex; 3324 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3325 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3326 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3327 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3328 u8 auto_pause; 3329 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3330 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 3331 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3332 u8 unused_0; 3333 __le16 auto_link_speed; 3334 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3335 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3336 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3337 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3338 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3339 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3340 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3341 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3342 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3343 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3344 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3345 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3346 __le16 auto_link_speed_mask; 3347 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3348 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3349 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3350 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3351 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3352 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3353 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3354 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3355 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3356 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3359 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3360 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3361 u8 wirespeed; 3362 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3363 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3364 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3365 u8 lpbk; 3366 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3367 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3368 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 3369 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 3370 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3371 u8 force_pause; 3372 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3373 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3374 u8 unused_1; 3375 __le32 preemphasis; 3376 __le16 eee_link_speed_mask; 3377 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3378 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 3379 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3380 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 3381 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3382 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3383 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3384 __le16 force_pam4_link_speed; 3385 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3386 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3387 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3388 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 3389 __le32 tx_lpi_timer; 3390 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 3391 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3392 __le16 auto_link_pam4_speed_mask; 3393 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3394 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3395 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3396 u8 unused_2[2]; 3397 }; 3398 3399 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3400 struct hwrm_port_phy_cfg_output { 3401 __le16 error_code; 3402 __le16 req_type; 3403 __le16 seq_id; 3404 __le16 resp_len; 3405 u8 unused_0[7]; 3406 u8 valid; 3407 }; 3408 3409 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3410 struct hwrm_port_phy_cfg_cmd_err { 3411 u8 code; 3412 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3413 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3414 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3415 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3416 u8 unused_0[7]; 3417 }; 3418 3419 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3420 struct hwrm_port_phy_qcfg_input { 3421 __le16 req_type; 3422 __le16 cmpl_ring; 3423 __le16 seq_id; 3424 __le16 target_id; 3425 __le64 resp_addr; 3426 __le16 port_id; 3427 u8 unused_0[6]; 3428 }; 3429 3430 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3431 struct hwrm_port_phy_qcfg_output { 3432 __le16 error_code; 3433 __le16 req_type; 3434 __le16 seq_id; 3435 __le16 resp_len; 3436 u8 link; 3437 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3438 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3439 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3440 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 3441 u8 active_fec_signal_mode; 3442 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 3443 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 3444 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 3445 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 3446 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 3447 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 3448 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 3449 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 3450 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 3451 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 3452 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 3453 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 3454 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 3455 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 3456 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3457 __le16 link_speed; 3458 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3459 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3460 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3461 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3462 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3463 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3464 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3465 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3466 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3467 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 3468 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3469 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3470 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3471 u8 duplex_cfg; 3472 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3473 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3474 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3475 u8 pause; 3476 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3477 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3478 __le16 support_speeds; 3479 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3480 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3481 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3482 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3483 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3484 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3485 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3486 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3487 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3488 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3489 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 3490 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 3491 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 3492 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3493 __le16 force_link_speed; 3494 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3495 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3496 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3497 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3498 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3499 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3500 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3501 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3502 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3503 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3504 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3505 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3506 u8 auto_mode; 3507 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 3508 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 3509 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 3510 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 3511 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 3512 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 3513 u8 auto_pause; 3514 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 3515 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 3516 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3517 __le16 auto_link_speed; 3518 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 3519 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 3520 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 3521 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 3522 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 3523 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 3524 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 3525 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 3526 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 3527 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 3528 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 3529 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 3530 __le16 auto_link_speed_mask; 3531 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3532 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3533 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3534 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3535 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3536 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3537 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3538 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3539 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3540 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3541 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3542 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3543 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3544 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3545 u8 wirespeed; 3546 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 3547 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 3548 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 3549 u8 lpbk; 3550 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 3551 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 3552 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 3553 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 3554 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 3555 u8 force_pause; 3556 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 3557 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 3558 u8 module_status; 3559 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 3560 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 3561 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 3562 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 3563 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 3564 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 3565 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 3566 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 3567 __le32 preemphasis; 3568 u8 phy_maj; 3569 u8 phy_min; 3570 u8 phy_bld; 3571 u8 phy_type; 3572 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 3573 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 3574 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 3575 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 3576 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 3577 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 3578 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 3579 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 3580 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 3581 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 3582 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 3583 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 3584 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 3585 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 3586 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 3587 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 3588 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 3589 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 3590 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 3591 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 3592 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 3593 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 3594 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 3595 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 3596 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 3597 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 3598 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 3599 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 3600 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 3601 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 3602 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 3603 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 3604 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 3605 u8 media_type; 3606 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 3607 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 3608 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 3609 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 3610 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 3611 u8 xcvr_pkg_type; 3612 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 3613 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 3614 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 3615 u8 eee_config_phy_addr; 3616 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 3617 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 3618 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 3619 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 3620 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 3621 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 3622 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 3623 u8 parallel_detect; 3624 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 3625 __le16 link_partner_adv_speeds; 3626 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 3627 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 3628 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 3629 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 3630 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 3631 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 3632 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 3633 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 3634 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 3635 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 3636 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 3637 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 3638 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 3639 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 3640 u8 link_partner_adv_auto_mode; 3641 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 3642 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 3643 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 3644 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 3645 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 3646 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 3647 u8 link_partner_adv_pause; 3648 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 3649 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 3650 __le16 adv_eee_link_speed_mask; 3651 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3652 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3653 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3654 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3655 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3656 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3657 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3658 __le16 link_partner_adv_eee_link_speed_mask; 3659 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3660 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3661 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3662 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3663 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3664 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3665 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3666 __le32 xcvr_identifier_type_tx_lpi_timer; 3667 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 3668 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 3669 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 3670 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 3671 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 3672 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 3673 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 3674 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 3675 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3676 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3677 __le16 fec_cfg; 3678 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3679 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3680 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3681 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3682 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3683 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3684 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3685 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3686 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 3687 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 3688 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 3689 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 3690 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 3691 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 3692 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3693 u8 duplex_state; 3694 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3695 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3696 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3697 u8 option_flags; 3698 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 3699 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 3700 char phy_vendor_name[16]; 3701 char phy_vendor_partnumber[16]; 3702 __le16 support_pam4_speeds; 3703 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3704 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3705 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3706 __le16 force_pam4_link_speed; 3707 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3708 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3709 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3710 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3711 __le16 auto_pam4_link_speed_mask; 3712 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3713 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3714 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 3715 u8 link_partner_pam4_adv_speeds; 3716 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3717 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3718 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3719 u8 valid; 3720 }; 3721 3722 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3723 struct hwrm_port_mac_cfg_input { 3724 __le16 req_type; 3725 __le16 cmpl_ring; 3726 __le16 seq_id; 3727 __le16 target_id; 3728 __le64 resp_addr; 3729 __le32 flags; 3730 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3731 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3732 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3733 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 3734 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 3735 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 3736 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 3737 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3738 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3739 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3740 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3741 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3742 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 3743 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3744 __le32 enables; 3745 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3746 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3747 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3748 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3749 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 3750 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 3751 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3752 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 3753 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 3754 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 3755 __le16 port_id; 3756 u8 ipg; 3757 u8 lpbk; 3758 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3759 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3760 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3761 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3762 u8 vlan_pri2cos_map_pri; 3763 u8 reserved1; 3764 u8 tunnel_pri2cos_map_pri; 3765 u8 dscp2pri_map_pri; 3766 __le16 rx_ts_capture_ptp_msg_type; 3767 __le16 tx_ts_capture_ptp_msg_type; 3768 u8 cos_field_cfg; 3769 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3770 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3771 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3772 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3773 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3774 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3775 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3776 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3777 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3778 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3779 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3780 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3781 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3782 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3783 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3784 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3785 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3786 u8 unused_0[3]; 3787 __le32 ptp_freq_adj_ppb; 3788 __le32 ptp_adj_phase; 3789 }; 3790 3791 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3792 struct hwrm_port_mac_cfg_output { 3793 __le16 error_code; 3794 __le16 req_type; 3795 __le16 seq_id; 3796 __le16 resp_len; 3797 __le16 mru; 3798 __le16 mtu; 3799 u8 ipg; 3800 u8 lpbk; 3801 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3802 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3803 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3804 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3805 u8 unused_0; 3806 u8 valid; 3807 }; 3808 3809 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3810 struct hwrm_port_mac_ptp_qcfg_input { 3811 __le16 req_type; 3812 __le16 cmpl_ring; 3813 __le16 seq_id; 3814 __le16 target_id; 3815 __le64 resp_addr; 3816 __le16 port_id; 3817 u8 unused_0[6]; 3818 }; 3819 3820 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 3821 struct hwrm_port_mac_ptp_qcfg_output { 3822 __le16 error_code; 3823 __le16 req_type; 3824 __le16 seq_id; 3825 __le16 resp_len; 3826 u8 flags; 3827 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3828 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3829 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3830 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 3831 u8 unused_0[3]; 3832 __le32 rx_ts_reg_off_lower; 3833 __le32 rx_ts_reg_off_upper; 3834 __le32 rx_ts_reg_off_seq_id; 3835 __le32 rx_ts_reg_off_src_id_0; 3836 __le32 rx_ts_reg_off_src_id_1; 3837 __le32 rx_ts_reg_off_src_id_2; 3838 __le32 rx_ts_reg_off_domain_id; 3839 __le32 rx_ts_reg_off_fifo; 3840 __le32 rx_ts_reg_off_fifo_adv; 3841 __le32 rx_ts_reg_off_granularity; 3842 __le32 tx_ts_reg_off_lower; 3843 __le32 tx_ts_reg_off_upper; 3844 __le32 tx_ts_reg_off_seq_id; 3845 __le32 tx_ts_reg_off_fifo; 3846 __le32 tx_ts_reg_off_granularity; 3847 __le32 ts_ref_clock_reg_lower; 3848 __le32 ts_ref_clock_reg_upper; 3849 u8 unused_1[7]; 3850 u8 valid; 3851 }; 3852 3853 /* tx_port_stats (size:3264b/408B) */ 3854 struct tx_port_stats { 3855 __le64 tx_64b_frames; 3856 __le64 tx_65b_127b_frames; 3857 __le64 tx_128b_255b_frames; 3858 __le64 tx_256b_511b_frames; 3859 __le64 tx_512b_1023b_frames; 3860 __le64 tx_1024b_1518b_frames; 3861 __le64 tx_good_vlan_frames; 3862 __le64 tx_1519b_2047b_frames; 3863 __le64 tx_2048b_4095b_frames; 3864 __le64 tx_4096b_9216b_frames; 3865 __le64 tx_9217b_16383b_frames; 3866 __le64 tx_good_frames; 3867 __le64 tx_total_frames; 3868 __le64 tx_ucast_frames; 3869 __le64 tx_mcast_frames; 3870 __le64 tx_bcast_frames; 3871 __le64 tx_pause_frames; 3872 __le64 tx_pfc_frames; 3873 __le64 tx_jabber_frames; 3874 __le64 tx_fcs_err_frames; 3875 __le64 tx_control_frames; 3876 __le64 tx_oversz_frames; 3877 __le64 tx_single_dfrl_frames; 3878 __le64 tx_multi_dfrl_frames; 3879 __le64 tx_single_coll_frames; 3880 __le64 tx_multi_coll_frames; 3881 __le64 tx_late_coll_frames; 3882 __le64 tx_excessive_coll_frames; 3883 __le64 tx_frag_frames; 3884 __le64 tx_err; 3885 __le64 tx_tagged_frames; 3886 __le64 tx_dbl_tagged_frames; 3887 __le64 tx_runt_frames; 3888 __le64 tx_fifo_underruns; 3889 __le64 tx_pfc_ena_frames_pri0; 3890 __le64 tx_pfc_ena_frames_pri1; 3891 __le64 tx_pfc_ena_frames_pri2; 3892 __le64 tx_pfc_ena_frames_pri3; 3893 __le64 tx_pfc_ena_frames_pri4; 3894 __le64 tx_pfc_ena_frames_pri5; 3895 __le64 tx_pfc_ena_frames_pri6; 3896 __le64 tx_pfc_ena_frames_pri7; 3897 __le64 tx_eee_lpi_events; 3898 __le64 tx_eee_lpi_duration; 3899 __le64 tx_llfc_logical_msgs; 3900 __le64 tx_hcfc_msgs; 3901 __le64 tx_total_collisions; 3902 __le64 tx_bytes; 3903 __le64 tx_xthol_frames; 3904 __le64 tx_stat_discard; 3905 __le64 tx_stat_error; 3906 }; 3907 3908 /* rx_port_stats (size:4224b/528B) */ 3909 struct rx_port_stats { 3910 __le64 rx_64b_frames; 3911 __le64 rx_65b_127b_frames; 3912 __le64 rx_128b_255b_frames; 3913 __le64 rx_256b_511b_frames; 3914 __le64 rx_512b_1023b_frames; 3915 __le64 rx_1024b_1518b_frames; 3916 __le64 rx_good_vlan_frames; 3917 __le64 rx_1519b_2047b_frames; 3918 __le64 rx_2048b_4095b_frames; 3919 __le64 rx_4096b_9216b_frames; 3920 __le64 rx_9217b_16383b_frames; 3921 __le64 rx_total_frames; 3922 __le64 rx_ucast_frames; 3923 __le64 rx_mcast_frames; 3924 __le64 rx_bcast_frames; 3925 __le64 rx_fcs_err_frames; 3926 __le64 rx_ctrl_frames; 3927 __le64 rx_pause_frames; 3928 __le64 rx_pfc_frames; 3929 __le64 rx_unsupported_opcode_frames; 3930 __le64 rx_unsupported_da_pausepfc_frames; 3931 __le64 rx_wrong_sa_frames; 3932 __le64 rx_align_err_frames; 3933 __le64 rx_oor_len_frames; 3934 __le64 rx_code_err_frames; 3935 __le64 rx_false_carrier_frames; 3936 __le64 rx_ovrsz_frames; 3937 __le64 rx_jbr_frames; 3938 __le64 rx_mtu_err_frames; 3939 __le64 rx_match_crc_frames; 3940 __le64 rx_promiscuous_frames; 3941 __le64 rx_tagged_frames; 3942 __le64 rx_double_tagged_frames; 3943 __le64 rx_trunc_frames; 3944 __le64 rx_good_frames; 3945 __le64 rx_pfc_xon2xoff_frames_pri0; 3946 __le64 rx_pfc_xon2xoff_frames_pri1; 3947 __le64 rx_pfc_xon2xoff_frames_pri2; 3948 __le64 rx_pfc_xon2xoff_frames_pri3; 3949 __le64 rx_pfc_xon2xoff_frames_pri4; 3950 __le64 rx_pfc_xon2xoff_frames_pri5; 3951 __le64 rx_pfc_xon2xoff_frames_pri6; 3952 __le64 rx_pfc_xon2xoff_frames_pri7; 3953 __le64 rx_pfc_ena_frames_pri0; 3954 __le64 rx_pfc_ena_frames_pri1; 3955 __le64 rx_pfc_ena_frames_pri2; 3956 __le64 rx_pfc_ena_frames_pri3; 3957 __le64 rx_pfc_ena_frames_pri4; 3958 __le64 rx_pfc_ena_frames_pri5; 3959 __le64 rx_pfc_ena_frames_pri6; 3960 __le64 rx_pfc_ena_frames_pri7; 3961 __le64 rx_sch_crc_err_frames; 3962 __le64 rx_undrsz_frames; 3963 __le64 rx_frag_frames; 3964 __le64 rx_eee_lpi_events; 3965 __le64 rx_eee_lpi_duration; 3966 __le64 rx_llfc_physical_msgs; 3967 __le64 rx_llfc_logical_msgs; 3968 __le64 rx_llfc_msgs_with_crc_err; 3969 __le64 rx_hcfc_msgs; 3970 __le64 rx_hcfc_msgs_with_crc_err; 3971 __le64 rx_bytes; 3972 __le64 rx_runt_bytes; 3973 __le64 rx_runt_frames; 3974 __le64 rx_stat_discard; 3975 __le64 rx_stat_err; 3976 }; 3977 3978 /* hwrm_port_qstats_input (size:320b/40B) */ 3979 struct hwrm_port_qstats_input { 3980 __le16 req_type; 3981 __le16 cmpl_ring; 3982 __le16 seq_id; 3983 __le16 target_id; 3984 __le64 resp_addr; 3985 __le16 port_id; 3986 u8 flags; 3987 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3988 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3989 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3990 u8 unused_0[5]; 3991 __le64 tx_stat_host_addr; 3992 __le64 rx_stat_host_addr; 3993 }; 3994 3995 /* hwrm_port_qstats_output (size:128b/16B) */ 3996 struct hwrm_port_qstats_output { 3997 __le16 error_code; 3998 __le16 req_type; 3999 __le16 seq_id; 4000 __le16 resp_len; 4001 __le16 tx_stat_size; 4002 __le16 rx_stat_size; 4003 u8 unused_0[3]; 4004 u8 valid; 4005 }; 4006 4007 /* tx_port_stats_ext (size:2048b/256B) */ 4008 struct tx_port_stats_ext { 4009 __le64 tx_bytes_cos0; 4010 __le64 tx_bytes_cos1; 4011 __le64 tx_bytes_cos2; 4012 __le64 tx_bytes_cos3; 4013 __le64 tx_bytes_cos4; 4014 __le64 tx_bytes_cos5; 4015 __le64 tx_bytes_cos6; 4016 __le64 tx_bytes_cos7; 4017 __le64 tx_packets_cos0; 4018 __le64 tx_packets_cos1; 4019 __le64 tx_packets_cos2; 4020 __le64 tx_packets_cos3; 4021 __le64 tx_packets_cos4; 4022 __le64 tx_packets_cos5; 4023 __le64 tx_packets_cos6; 4024 __le64 tx_packets_cos7; 4025 __le64 pfc_pri0_tx_duration_us; 4026 __le64 pfc_pri0_tx_transitions; 4027 __le64 pfc_pri1_tx_duration_us; 4028 __le64 pfc_pri1_tx_transitions; 4029 __le64 pfc_pri2_tx_duration_us; 4030 __le64 pfc_pri2_tx_transitions; 4031 __le64 pfc_pri3_tx_duration_us; 4032 __le64 pfc_pri3_tx_transitions; 4033 __le64 pfc_pri4_tx_duration_us; 4034 __le64 pfc_pri4_tx_transitions; 4035 __le64 pfc_pri5_tx_duration_us; 4036 __le64 pfc_pri5_tx_transitions; 4037 __le64 pfc_pri6_tx_duration_us; 4038 __le64 pfc_pri6_tx_transitions; 4039 __le64 pfc_pri7_tx_duration_us; 4040 __le64 pfc_pri7_tx_transitions; 4041 }; 4042 4043 /* rx_port_stats_ext (size:3648b/456B) */ 4044 struct rx_port_stats_ext { 4045 __le64 link_down_events; 4046 __le64 continuous_pause_events; 4047 __le64 resume_pause_events; 4048 __le64 continuous_roce_pause_events; 4049 __le64 resume_roce_pause_events; 4050 __le64 rx_bytes_cos0; 4051 __le64 rx_bytes_cos1; 4052 __le64 rx_bytes_cos2; 4053 __le64 rx_bytes_cos3; 4054 __le64 rx_bytes_cos4; 4055 __le64 rx_bytes_cos5; 4056 __le64 rx_bytes_cos6; 4057 __le64 rx_bytes_cos7; 4058 __le64 rx_packets_cos0; 4059 __le64 rx_packets_cos1; 4060 __le64 rx_packets_cos2; 4061 __le64 rx_packets_cos3; 4062 __le64 rx_packets_cos4; 4063 __le64 rx_packets_cos5; 4064 __le64 rx_packets_cos6; 4065 __le64 rx_packets_cos7; 4066 __le64 pfc_pri0_rx_duration_us; 4067 __le64 pfc_pri0_rx_transitions; 4068 __le64 pfc_pri1_rx_duration_us; 4069 __le64 pfc_pri1_rx_transitions; 4070 __le64 pfc_pri2_rx_duration_us; 4071 __le64 pfc_pri2_rx_transitions; 4072 __le64 pfc_pri3_rx_duration_us; 4073 __le64 pfc_pri3_rx_transitions; 4074 __le64 pfc_pri4_rx_duration_us; 4075 __le64 pfc_pri4_rx_transitions; 4076 __le64 pfc_pri5_rx_duration_us; 4077 __le64 pfc_pri5_rx_transitions; 4078 __le64 pfc_pri6_rx_duration_us; 4079 __le64 pfc_pri6_rx_transitions; 4080 __le64 pfc_pri7_rx_duration_us; 4081 __le64 pfc_pri7_rx_transitions; 4082 __le64 rx_bits; 4083 __le64 rx_buffer_passed_threshold; 4084 __le64 rx_pcs_symbol_err; 4085 __le64 rx_corrected_bits; 4086 __le64 rx_discard_bytes_cos0; 4087 __le64 rx_discard_bytes_cos1; 4088 __le64 rx_discard_bytes_cos2; 4089 __le64 rx_discard_bytes_cos3; 4090 __le64 rx_discard_bytes_cos4; 4091 __le64 rx_discard_bytes_cos5; 4092 __le64 rx_discard_bytes_cos6; 4093 __le64 rx_discard_bytes_cos7; 4094 __le64 rx_discard_packets_cos0; 4095 __le64 rx_discard_packets_cos1; 4096 __le64 rx_discard_packets_cos2; 4097 __le64 rx_discard_packets_cos3; 4098 __le64 rx_discard_packets_cos4; 4099 __le64 rx_discard_packets_cos5; 4100 __le64 rx_discard_packets_cos6; 4101 __le64 rx_discard_packets_cos7; 4102 }; 4103 4104 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4105 struct hwrm_port_qstats_ext_input { 4106 __le16 req_type; 4107 __le16 cmpl_ring; 4108 __le16 seq_id; 4109 __le16 target_id; 4110 __le64 resp_addr; 4111 __le16 port_id; 4112 __le16 tx_stat_size; 4113 __le16 rx_stat_size; 4114 u8 flags; 4115 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4116 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4117 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4118 u8 unused_0; 4119 __le64 tx_stat_host_addr; 4120 __le64 rx_stat_host_addr; 4121 }; 4122 4123 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4124 struct hwrm_port_qstats_ext_output { 4125 __le16 error_code; 4126 __le16 req_type; 4127 __le16 seq_id; 4128 __le16 resp_len; 4129 __le16 tx_stat_size; 4130 __le16 rx_stat_size; 4131 __le16 total_active_cos_queues; 4132 u8 flags; 4133 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4134 u8 valid; 4135 }; 4136 4137 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4138 struct hwrm_port_lpbk_qstats_input { 4139 __le16 req_type; 4140 __le16 cmpl_ring; 4141 __le16 seq_id; 4142 __le16 target_id; 4143 __le64 resp_addr; 4144 }; 4145 4146 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4147 struct hwrm_port_lpbk_qstats_output { 4148 __le16 error_code; 4149 __le16 req_type; 4150 __le16 seq_id; 4151 __le16 resp_len; 4152 __le64 lpbk_ucast_frames; 4153 __le64 lpbk_mcast_frames; 4154 __le64 lpbk_bcast_frames; 4155 __le64 lpbk_ucast_bytes; 4156 __le64 lpbk_mcast_bytes; 4157 __le64 lpbk_bcast_bytes; 4158 __le64 tx_stat_discard; 4159 __le64 tx_stat_error; 4160 __le64 rx_stat_discard; 4161 __le64 rx_stat_error; 4162 u8 unused_0[7]; 4163 u8 valid; 4164 }; 4165 4166 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 4167 struct hwrm_port_ecn_qstats_input { 4168 __le16 req_type; 4169 __le16 cmpl_ring; 4170 __le16 seq_id; 4171 __le16 target_id; 4172 __le64 resp_addr; 4173 __le16 port_id; 4174 __le16 ecn_stat_buf_size; 4175 u8 flags; 4176 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4177 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4178 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 4179 u8 unused_0[3]; 4180 __le64 ecn_stat_host_addr; 4181 }; 4182 4183 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 4184 struct hwrm_port_ecn_qstats_output { 4185 __le16 error_code; 4186 __le16 req_type; 4187 __le16 seq_id; 4188 __le16 resp_len; 4189 __le16 ecn_stat_buf_size; 4190 u8 mark_en; 4191 u8 unused_0[4]; 4192 u8 valid; 4193 }; 4194 4195 /* port_stats_ecn (size:512b/64B) */ 4196 struct port_stats_ecn { 4197 __le64 mark_cnt_cos0; 4198 __le64 mark_cnt_cos1; 4199 __le64 mark_cnt_cos2; 4200 __le64 mark_cnt_cos3; 4201 __le64 mark_cnt_cos4; 4202 __le64 mark_cnt_cos5; 4203 __le64 mark_cnt_cos6; 4204 __le64 mark_cnt_cos7; 4205 }; 4206 4207 /* hwrm_port_clr_stats_input (size:192b/24B) */ 4208 struct hwrm_port_clr_stats_input { 4209 __le16 req_type; 4210 __le16 cmpl_ring; 4211 __le16 seq_id; 4212 __le16 target_id; 4213 __le64 resp_addr; 4214 __le16 port_id; 4215 u8 flags; 4216 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 4217 u8 unused_0[5]; 4218 }; 4219 4220 /* hwrm_port_clr_stats_output (size:128b/16B) */ 4221 struct hwrm_port_clr_stats_output { 4222 __le16 error_code; 4223 __le16 req_type; 4224 __le16 seq_id; 4225 __le16 resp_len; 4226 u8 unused_0[7]; 4227 u8 valid; 4228 }; 4229 4230 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4231 struct hwrm_port_lpbk_clr_stats_input { 4232 __le16 req_type; 4233 __le16 cmpl_ring; 4234 __le16 seq_id; 4235 __le16 target_id; 4236 __le64 resp_addr; 4237 }; 4238 4239 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4240 struct hwrm_port_lpbk_clr_stats_output { 4241 __le16 error_code; 4242 __le16 req_type; 4243 __le16 seq_id; 4244 __le16 resp_len; 4245 u8 unused_0[7]; 4246 u8 valid; 4247 }; 4248 4249 /* hwrm_port_ts_query_input (size:320b/40B) */ 4250 struct hwrm_port_ts_query_input { 4251 __le16 req_type; 4252 __le16 cmpl_ring; 4253 __le16 seq_id; 4254 __le16 target_id; 4255 __le64 resp_addr; 4256 __le32 flags; 4257 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 4258 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 4259 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 4260 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 4261 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 4262 __le16 port_id; 4263 u8 unused_0[2]; 4264 __le16 enables; 4265 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 4266 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4267 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 4268 __le16 ts_req_timeout; 4269 __le32 ptp_seq_id; 4270 __le16 ptp_hdr_offset; 4271 u8 unused_1[6]; 4272 }; 4273 4274 /* hwrm_port_ts_query_output (size:192b/24B) */ 4275 struct hwrm_port_ts_query_output { 4276 __le16 error_code; 4277 __le16 req_type; 4278 __le16 seq_id; 4279 __le16 resp_len; 4280 __le64 ptp_msg_ts; 4281 __le16 ptp_msg_seqid; 4282 u8 unused_0[5]; 4283 u8 valid; 4284 }; 4285 4286 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 4287 struct hwrm_port_phy_qcaps_input { 4288 __le16 req_type; 4289 __le16 cmpl_ring; 4290 __le16 seq_id; 4291 __le16 target_id; 4292 __le64 resp_addr; 4293 __le16 port_id; 4294 u8 unused_0[6]; 4295 }; 4296 4297 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 4298 struct hwrm_port_phy_qcaps_output { 4299 __le16 error_code; 4300 __le16 req_type; 4301 __le16 seq_id; 4302 __le16 resp_len; 4303 u8 flags; 4304 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 4305 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 4306 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 4307 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4308 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 4309 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 4310 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 4311 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 4312 u8 port_cnt; 4313 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 4314 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 4315 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 4316 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 4317 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 4318 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 4319 __le16 supported_speeds_force_mode; 4320 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 4321 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 4322 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 4323 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 4324 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 4325 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 4326 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 4327 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 4328 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 4329 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 4330 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 4331 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 4332 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 4333 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 4334 __le16 supported_speeds_auto_mode; 4335 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 4336 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 4337 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 4338 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 4339 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 4340 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 4341 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 4342 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 4343 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 4344 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 4345 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 4346 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 4347 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 4348 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 4349 __le16 supported_speeds_eee_mode; 4350 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 4351 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 4352 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 4353 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 4354 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 4355 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 4356 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 4357 __le32 tx_lpi_timer_low; 4358 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 4359 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 4360 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 4361 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 4362 __le32 valid_tx_lpi_timer_high; 4363 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 4364 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4365 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4366 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4367 __le16 supported_pam4_speeds_auto_mode; 4368 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4369 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4370 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4371 __le16 supported_pam4_speeds_force_mode; 4372 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4373 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4374 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4375 u8 unused_0[3]; 4376 u8 valid; 4377 }; 4378 4379 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 4380 struct hwrm_port_phy_i2c_read_input { 4381 __le16 req_type; 4382 __le16 cmpl_ring; 4383 __le16 seq_id; 4384 __le16 target_id; 4385 __le64 resp_addr; 4386 __le32 flags; 4387 __le32 enables; 4388 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 4389 __le16 port_id; 4390 u8 i2c_slave_addr; 4391 u8 unused_0; 4392 __le16 page_number; 4393 __le16 page_offset; 4394 u8 data_length; 4395 u8 unused_1[7]; 4396 }; 4397 4398 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 4399 struct hwrm_port_phy_i2c_read_output { 4400 __le16 error_code; 4401 __le16 req_type; 4402 __le16 seq_id; 4403 __le16 resp_len; 4404 __le32 data[16]; 4405 u8 unused_0[7]; 4406 u8 valid; 4407 }; 4408 4409 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 4410 struct hwrm_port_phy_mdio_write_input { 4411 __le16 req_type; 4412 __le16 cmpl_ring; 4413 __le16 seq_id; 4414 __le16 target_id; 4415 __le64 resp_addr; 4416 __le32 unused_0[2]; 4417 __le16 port_id; 4418 u8 phy_addr; 4419 u8 dev_addr; 4420 __le16 reg_addr; 4421 __le16 reg_data; 4422 u8 cl45_mdio; 4423 u8 unused_1[7]; 4424 }; 4425 4426 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 4427 struct hwrm_port_phy_mdio_write_output { 4428 __le16 error_code; 4429 __le16 req_type; 4430 __le16 seq_id; 4431 __le16 resp_len; 4432 u8 unused_0[7]; 4433 u8 valid; 4434 }; 4435 4436 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 4437 struct hwrm_port_phy_mdio_read_input { 4438 __le16 req_type; 4439 __le16 cmpl_ring; 4440 __le16 seq_id; 4441 __le16 target_id; 4442 __le64 resp_addr; 4443 __le32 unused_0[2]; 4444 __le16 port_id; 4445 u8 phy_addr; 4446 u8 dev_addr; 4447 __le16 reg_addr; 4448 u8 cl45_mdio; 4449 u8 unused_1; 4450 }; 4451 4452 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 4453 struct hwrm_port_phy_mdio_read_output { 4454 __le16 error_code; 4455 __le16 req_type; 4456 __le16 seq_id; 4457 __le16 resp_len; 4458 __le16 reg_data; 4459 u8 unused_0[5]; 4460 u8 valid; 4461 }; 4462 4463 /* hwrm_port_led_cfg_input (size:512b/64B) */ 4464 struct hwrm_port_led_cfg_input { 4465 __le16 req_type; 4466 __le16 cmpl_ring; 4467 __le16 seq_id; 4468 __le16 target_id; 4469 __le64 resp_addr; 4470 __le32 enables; 4471 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4472 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4473 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4474 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4475 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4476 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4477 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4478 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4479 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4480 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4481 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4482 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4483 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4484 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4485 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4486 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4487 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4488 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4489 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4490 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 4491 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 4492 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 4493 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 4494 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 4495 __le16 port_id; 4496 u8 num_leds; 4497 u8 rsvd; 4498 u8 led0_id; 4499 u8 led0_state; 4500 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 4501 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 4502 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 4503 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 4504 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 4505 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 4506 u8 led0_color; 4507 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 4508 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 4509 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 4510 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 4511 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 4512 u8 unused_0; 4513 __le16 led0_blink_on; 4514 __le16 led0_blink_off; 4515 u8 led0_group_id; 4516 u8 rsvd0; 4517 u8 led1_id; 4518 u8 led1_state; 4519 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 4520 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 4521 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 4522 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 4523 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 4524 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 4525 u8 led1_color; 4526 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 4527 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 4528 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 4529 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 4530 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 4531 u8 unused_1; 4532 __le16 led1_blink_on; 4533 __le16 led1_blink_off; 4534 u8 led1_group_id; 4535 u8 rsvd1; 4536 u8 led2_id; 4537 u8 led2_state; 4538 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 4539 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 4540 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 4541 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 4542 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 4543 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 4544 u8 led2_color; 4545 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 4546 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 4547 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 4548 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 4549 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 4550 u8 unused_2; 4551 __le16 led2_blink_on; 4552 __le16 led2_blink_off; 4553 u8 led2_group_id; 4554 u8 rsvd2; 4555 u8 led3_id; 4556 u8 led3_state; 4557 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 4558 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 4559 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 4560 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 4561 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 4562 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 4563 u8 led3_color; 4564 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 4565 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 4566 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 4567 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 4568 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 4569 u8 unused_3; 4570 __le16 led3_blink_on; 4571 __le16 led3_blink_off; 4572 u8 led3_group_id; 4573 u8 rsvd3; 4574 }; 4575 4576 /* hwrm_port_led_cfg_output (size:128b/16B) */ 4577 struct hwrm_port_led_cfg_output { 4578 __le16 error_code; 4579 __le16 req_type; 4580 __le16 seq_id; 4581 __le16 resp_len; 4582 u8 unused_0[7]; 4583 u8 valid; 4584 }; 4585 4586 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 4587 struct hwrm_port_led_qcfg_input { 4588 __le16 req_type; 4589 __le16 cmpl_ring; 4590 __le16 seq_id; 4591 __le16 target_id; 4592 __le64 resp_addr; 4593 __le16 port_id; 4594 u8 unused_0[6]; 4595 }; 4596 4597 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 4598 struct hwrm_port_led_qcfg_output { 4599 __le16 error_code; 4600 __le16 req_type; 4601 __le16 seq_id; 4602 __le16 resp_len; 4603 u8 num_leds; 4604 u8 led0_id; 4605 u8 led0_type; 4606 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 4607 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 4608 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 4609 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 4610 u8 led0_state; 4611 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 4612 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 4613 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 4614 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 4615 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 4616 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 4617 u8 led0_color; 4618 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 4619 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 4620 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 4621 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 4622 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 4623 u8 unused_0; 4624 __le16 led0_blink_on; 4625 __le16 led0_blink_off; 4626 u8 led0_group_id; 4627 u8 led1_id; 4628 u8 led1_type; 4629 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 4630 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 4631 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 4632 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 4633 u8 led1_state; 4634 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 4635 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 4636 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 4637 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 4638 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 4639 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 4640 u8 led1_color; 4641 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 4642 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 4643 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 4644 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 4645 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 4646 u8 unused_1; 4647 __le16 led1_blink_on; 4648 __le16 led1_blink_off; 4649 u8 led1_group_id; 4650 u8 led2_id; 4651 u8 led2_type; 4652 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 4653 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 4654 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 4655 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 4656 u8 led2_state; 4657 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 4658 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 4659 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 4660 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 4661 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 4662 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 4663 u8 led2_color; 4664 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 4665 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 4666 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 4667 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 4668 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 4669 u8 unused_2; 4670 __le16 led2_blink_on; 4671 __le16 led2_blink_off; 4672 u8 led2_group_id; 4673 u8 led3_id; 4674 u8 led3_type; 4675 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 4676 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 4677 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 4678 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 4679 u8 led3_state; 4680 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4681 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4682 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4683 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4684 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4685 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4686 u8 led3_color; 4687 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4688 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4689 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4690 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4691 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4692 u8 unused_3; 4693 __le16 led3_blink_on; 4694 __le16 led3_blink_off; 4695 u8 led3_group_id; 4696 u8 unused_4[6]; 4697 u8 valid; 4698 }; 4699 4700 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4701 struct hwrm_port_led_qcaps_input { 4702 __le16 req_type; 4703 __le16 cmpl_ring; 4704 __le16 seq_id; 4705 __le16 target_id; 4706 __le64 resp_addr; 4707 __le16 port_id; 4708 u8 unused_0[6]; 4709 }; 4710 4711 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4712 struct hwrm_port_led_qcaps_output { 4713 __le16 error_code; 4714 __le16 req_type; 4715 __le16 seq_id; 4716 __le16 resp_len; 4717 u8 num_leds; 4718 u8 unused[3]; 4719 u8 led0_id; 4720 u8 led0_type; 4721 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4722 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4723 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4724 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4725 u8 led0_group_id; 4726 u8 unused_0; 4727 __le16 led0_state_caps; 4728 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4729 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4730 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4731 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4732 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4733 __le16 led0_color_caps; 4734 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4735 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4736 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4737 u8 led1_id; 4738 u8 led1_type; 4739 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4740 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4741 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4742 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4743 u8 led1_group_id; 4744 u8 unused_1; 4745 __le16 led1_state_caps; 4746 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4747 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4748 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4749 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4750 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4751 __le16 led1_color_caps; 4752 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4753 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4754 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4755 u8 led2_id; 4756 u8 led2_type; 4757 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4758 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4759 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4760 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4761 u8 led2_group_id; 4762 u8 unused_2; 4763 __le16 led2_state_caps; 4764 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4765 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4766 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4767 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4768 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4769 __le16 led2_color_caps; 4770 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4771 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4772 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4773 u8 led3_id; 4774 u8 led3_type; 4775 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4776 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4777 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4778 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4779 u8 led3_group_id; 4780 u8 unused_3; 4781 __le16 led3_state_caps; 4782 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4783 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4784 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4785 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4786 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4787 __le16 led3_color_caps; 4788 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4789 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4790 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4791 u8 unused_4[3]; 4792 u8 valid; 4793 }; 4794 4795 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4796 struct hwrm_queue_qportcfg_input { 4797 __le16 req_type; 4798 __le16 cmpl_ring; 4799 __le16 seq_id; 4800 __le16 target_id; 4801 __le64 resp_addr; 4802 __le32 flags; 4803 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4804 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4805 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4806 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4807 __le16 port_id; 4808 u8 drv_qmap_cap; 4809 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4810 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4811 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4812 u8 unused_0; 4813 }; 4814 4815 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4816 struct hwrm_queue_qportcfg_output { 4817 __le16 error_code; 4818 __le16 req_type; 4819 __le16 seq_id; 4820 __le16 resp_len; 4821 u8 max_configurable_queues; 4822 u8 max_configurable_lossless_queues; 4823 u8 queue_cfg_allowed; 4824 u8 queue_cfg_info; 4825 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4826 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 4827 u8 queue_pfcenable_cfg_allowed; 4828 u8 queue_pri2cos_cfg_allowed; 4829 u8 queue_cos2bw_cfg_allowed; 4830 u8 queue_id0; 4831 u8 queue_id0_service_profile; 4832 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4833 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4834 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4835 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4836 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4837 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4838 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4839 u8 queue_id1; 4840 u8 queue_id1_service_profile; 4841 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4842 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4843 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4844 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4845 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4846 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4847 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4848 u8 queue_id2; 4849 u8 queue_id2_service_profile; 4850 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4851 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4852 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4853 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4854 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4855 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4856 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4857 u8 queue_id3; 4858 u8 queue_id3_service_profile; 4859 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4860 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4861 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4863 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4864 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4865 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4866 u8 queue_id4; 4867 u8 queue_id4_service_profile; 4868 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4869 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4870 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4871 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4872 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4873 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4874 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4875 u8 queue_id5; 4876 u8 queue_id5_service_profile; 4877 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4878 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4879 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4880 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4881 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4882 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4883 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4884 u8 queue_id6; 4885 u8 queue_id6_service_profile; 4886 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4887 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4888 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4889 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4890 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4891 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4892 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4893 u8 queue_id7; 4894 u8 queue_id7_service_profile; 4895 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4896 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4897 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4898 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4899 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4900 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4901 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4902 u8 queue_id0_service_profile_type; 4903 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4904 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4905 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4906 char qid0_name[16]; 4907 char qid1_name[16]; 4908 char qid2_name[16]; 4909 char qid3_name[16]; 4910 char qid4_name[16]; 4911 char qid5_name[16]; 4912 char qid6_name[16]; 4913 char qid7_name[16]; 4914 u8 queue_id1_service_profile_type; 4915 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4916 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4917 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4918 u8 queue_id2_service_profile_type; 4919 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4920 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4921 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4922 u8 queue_id3_service_profile_type; 4923 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4924 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4925 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4926 u8 queue_id4_service_profile_type; 4927 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4928 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4929 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4930 u8 queue_id5_service_profile_type; 4931 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4932 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4933 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4934 u8 queue_id6_service_profile_type; 4935 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4936 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4937 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4938 u8 queue_id7_service_profile_type; 4939 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4940 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4941 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4942 u8 valid; 4943 }; 4944 4945 /* hwrm_queue_qcfg_input (size:192b/24B) */ 4946 struct hwrm_queue_qcfg_input { 4947 __le16 req_type; 4948 __le16 cmpl_ring; 4949 __le16 seq_id; 4950 __le16 target_id; 4951 __le64 resp_addr; 4952 __le32 flags; 4953 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4954 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4955 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4956 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4957 __le32 queue_id; 4958 }; 4959 4960 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4961 struct hwrm_queue_qcfg_output { 4962 __le16 error_code; 4963 __le16 req_type; 4964 __le16 seq_id; 4965 __le16 resp_len; 4966 __le32 queue_len; 4967 u8 service_profile; 4968 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4969 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4970 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4971 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4972 u8 queue_cfg_info; 4973 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4974 u8 unused_0; 4975 u8 valid; 4976 }; 4977 4978 /* hwrm_queue_cfg_input (size:320b/40B) */ 4979 struct hwrm_queue_cfg_input { 4980 __le16 req_type; 4981 __le16 cmpl_ring; 4982 __le16 seq_id; 4983 __le16 target_id; 4984 __le64 resp_addr; 4985 __le32 flags; 4986 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4987 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4988 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4989 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4990 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4991 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4992 __le32 enables; 4993 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4994 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4995 __le32 queue_id; 4996 __le32 dflt_len; 4997 u8 service_profile; 4998 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4999 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5000 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5001 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5002 u8 unused_0[7]; 5003 }; 5004 5005 /* hwrm_queue_cfg_output (size:128b/16B) */ 5006 struct hwrm_queue_cfg_output { 5007 __le16 error_code; 5008 __le16 req_type; 5009 __le16 seq_id; 5010 __le16 resp_len; 5011 u8 unused_0[7]; 5012 u8 valid; 5013 }; 5014 5015 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 5016 struct hwrm_queue_pfcenable_qcfg_input { 5017 __le16 req_type; 5018 __le16 cmpl_ring; 5019 __le16 seq_id; 5020 __le16 target_id; 5021 __le64 resp_addr; 5022 __le16 port_id; 5023 u8 unused_0[6]; 5024 }; 5025 5026 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 5027 struct hwrm_queue_pfcenable_qcfg_output { 5028 __le16 error_code; 5029 __le16 req_type; 5030 __le16 seq_id; 5031 __le16 resp_len; 5032 __le32 flags; 5033 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 5034 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 5035 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 5036 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 5037 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 5038 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 5039 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 5040 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5041 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5042 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5043 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5044 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5045 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5046 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5047 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5048 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5049 u8 unused_0[3]; 5050 u8 valid; 5051 }; 5052 5053 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5054 struct hwrm_queue_pfcenable_cfg_input { 5055 __le16 req_type; 5056 __le16 cmpl_ring; 5057 __le16 seq_id; 5058 __le16 target_id; 5059 __le64 resp_addr; 5060 __le32 flags; 5061 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5062 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5063 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5064 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5065 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5066 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5067 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5068 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5069 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5070 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5071 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5072 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5073 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5074 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5075 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5076 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5077 __le16 port_id; 5078 u8 unused_0[2]; 5079 }; 5080 5081 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5082 struct hwrm_queue_pfcenable_cfg_output { 5083 __le16 error_code; 5084 __le16 req_type; 5085 __le16 seq_id; 5086 __le16 resp_len; 5087 u8 unused_0[7]; 5088 u8 valid; 5089 }; 5090 5091 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 5092 struct hwrm_queue_pri2cos_qcfg_input { 5093 __le16 req_type; 5094 __le16 cmpl_ring; 5095 __le16 seq_id; 5096 __le16 target_id; 5097 __le64 resp_addr; 5098 __le32 flags; 5099 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5100 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5101 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5102 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 5103 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 5104 u8 port_id; 5105 u8 unused_0[3]; 5106 }; 5107 5108 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 5109 struct hwrm_queue_pri2cos_qcfg_output { 5110 __le16 error_code; 5111 __le16 req_type; 5112 __le16 seq_id; 5113 __le16 resp_len; 5114 u8 pri0_cos_queue_id; 5115 u8 pri1_cos_queue_id; 5116 u8 pri2_cos_queue_id; 5117 u8 pri3_cos_queue_id; 5118 u8 pri4_cos_queue_id; 5119 u8 pri5_cos_queue_id; 5120 u8 pri6_cos_queue_id; 5121 u8 pri7_cos_queue_id; 5122 u8 queue_cfg_info; 5123 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5124 u8 unused_0[6]; 5125 u8 valid; 5126 }; 5127 5128 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5129 struct hwrm_queue_pri2cos_cfg_input { 5130 __le16 req_type; 5131 __le16 cmpl_ring; 5132 __le16 seq_id; 5133 __le16 target_id; 5134 __le64 resp_addr; 5135 __le32 flags; 5136 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5137 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5138 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5139 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5140 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5141 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5142 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5143 __le32 enables; 5144 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5145 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5146 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5147 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5148 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5149 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5150 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5151 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5152 u8 port_id; 5153 u8 pri0_cos_queue_id; 5154 u8 pri1_cos_queue_id; 5155 u8 pri2_cos_queue_id; 5156 u8 pri3_cos_queue_id; 5157 u8 pri4_cos_queue_id; 5158 u8 pri5_cos_queue_id; 5159 u8 pri6_cos_queue_id; 5160 u8 pri7_cos_queue_id; 5161 u8 unused_0[7]; 5162 }; 5163 5164 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5165 struct hwrm_queue_pri2cos_cfg_output { 5166 __le16 error_code; 5167 __le16 req_type; 5168 __le16 seq_id; 5169 __le16 resp_len; 5170 u8 unused_0[7]; 5171 u8 valid; 5172 }; 5173 5174 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 5175 struct hwrm_queue_cos2bw_qcfg_input { 5176 __le16 req_type; 5177 __le16 cmpl_ring; 5178 __le16 seq_id; 5179 __le16 target_id; 5180 __le64 resp_addr; 5181 __le16 port_id; 5182 u8 unused_0[6]; 5183 }; 5184 5185 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 5186 struct hwrm_queue_cos2bw_qcfg_output { 5187 __le16 error_code; 5188 __le16 req_type; 5189 __le16 seq_id; 5190 __le16 resp_len; 5191 u8 queue_id0; 5192 u8 unused_0; 5193 __le16 unused_1; 5194 __le32 queue_id0_min_bw; 5195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5196 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5197 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5198 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5199 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5200 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 5201 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5202 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5203 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5204 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5205 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5206 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5207 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5208 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5209 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5210 __le32 queue_id0_max_bw; 5211 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5212 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5213 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5214 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5215 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5216 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 5217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5226 u8 queue_id0_tsa_assign; 5227 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5231 u8 queue_id0_pri_lvl; 5232 u8 queue_id0_bw_weight; 5233 u8 queue_id1; 5234 __le32 queue_id1_min_bw; 5235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5237 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 5241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5242 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5243 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5244 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5250 __le32 queue_id1_max_bw; 5251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 5257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5259 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5260 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5261 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5266 u8 queue_id1_tsa_assign; 5267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5268 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5271 u8 queue_id1_pri_lvl; 5272 u8 queue_id1_bw_weight; 5273 u8 queue_id2; 5274 __le32 queue_id2_min_bw; 5275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5277 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5280 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 5281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5282 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5283 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5284 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5290 __le32 queue_id2_max_bw; 5291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5292 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5293 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5296 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 5297 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5298 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5299 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5300 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5301 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5305 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5306 u8 queue_id2_tsa_assign; 5307 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5308 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5309 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5310 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5311 u8 queue_id2_pri_lvl; 5312 u8 queue_id2_bw_weight; 5313 u8 queue_id3; 5314 __le32 queue_id3_min_bw; 5315 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5316 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5317 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5318 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5319 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5320 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 5321 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5322 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5323 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5324 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5325 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5326 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5327 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5328 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5330 __le32 queue_id3_max_bw; 5331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5333 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5336 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 5337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5338 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5339 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5340 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5341 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5342 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5346 u8 queue_id3_tsa_assign; 5347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5348 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5351 u8 queue_id3_pri_lvl; 5352 u8 queue_id3_bw_weight; 5353 u8 queue_id4; 5354 __le32 queue_id4_min_bw; 5355 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5356 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5357 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5358 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5359 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5360 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 5361 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5362 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5363 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5364 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5365 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5366 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5367 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5370 __le32 queue_id4_max_bw; 5371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5373 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5376 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 5377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5378 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5379 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5380 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5381 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5382 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5383 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5386 u8 queue_id4_tsa_assign; 5387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5391 u8 queue_id4_pri_lvl; 5392 u8 queue_id4_bw_weight; 5393 u8 queue_id5; 5394 __le32 queue_id5_min_bw; 5395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5397 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5399 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5400 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 5401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5404 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5410 __le32 queue_id5_max_bw; 5411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5416 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 5417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5419 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5420 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5421 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5422 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5423 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5426 u8 queue_id5_tsa_assign; 5427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5431 u8 queue_id5_pri_lvl; 5432 u8 queue_id5_bw_weight; 5433 u8 queue_id6; 5434 __le32 queue_id6_min_bw; 5435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5437 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5438 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5439 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5440 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 5441 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5442 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5443 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5444 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5445 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5446 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5447 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5448 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5449 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5450 __le32 queue_id6_max_bw; 5451 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5452 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5453 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5454 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5455 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5456 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 5457 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5458 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5459 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5460 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5461 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5462 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5463 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5464 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5465 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5466 u8 queue_id6_tsa_assign; 5467 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5468 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5469 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5471 u8 queue_id6_pri_lvl; 5472 u8 queue_id6_bw_weight; 5473 u8 queue_id7; 5474 __le32 queue_id7_min_bw; 5475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 5481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5490 __le32 queue_id7_max_bw; 5491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 5497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5501 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5502 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5506 u8 queue_id7_tsa_assign; 5507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5511 u8 queue_id7_pri_lvl; 5512 u8 queue_id7_bw_weight; 5513 u8 unused_2[4]; 5514 u8 valid; 5515 }; 5516 5517 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 5518 struct hwrm_queue_cos2bw_cfg_input { 5519 __le16 req_type; 5520 __le16 cmpl_ring; 5521 __le16 seq_id; 5522 __le16 target_id; 5523 __le64 resp_addr; 5524 __le32 flags; 5525 __le32 enables; 5526 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 5527 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 5528 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 5529 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 5530 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 5531 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 5532 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 5533 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 5534 __le16 port_id; 5535 u8 queue_id0; 5536 u8 unused_0; 5537 __le32 queue_id0_min_bw; 5538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5540 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5543 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 5544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5547 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5548 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5549 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5550 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5551 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5553 __le32 queue_id0_max_bw; 5554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5559 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 5560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5561 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5569 u8 queue_id0_tsa_assign; 5570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5574 u8 queue_id0_pri_lvl; 5575 u8 queue_id0_bw_weight; 5576 u8 queue_id1; 5577 __le32 queue_id1_min_bw; 5578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5580 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5582 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 5584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5585 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5593 __le32 queue_id1_max_bw; 5594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 5600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5609 u8 queue_id1_tsa_assign; 5610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5614 u8 queue_id1_pri_lvl; 5615 u8 queue_id1_bw_weight; 5616 u8 queue_id2; 5617 __le32 queue_id2_min_bw; 5618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5620 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5623 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 5624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5633 __le32 queue_id2_max_bw; 5634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 5640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5649 u8 queue_id2_tsa_assign; 5650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5654 u8 queue_id2_pri_lvl; 5655 u8 queue_id2_bw_weight; 5656 u8 queue_id3; 5657 __le32 queue_id3_min_bw; 5658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5660 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5661 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5662 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5663 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 5664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5665 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5666 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5667 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5668 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5669 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5673 __le32 queue_id3_max_bw; 5674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5676 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5679 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 5680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5682 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5683 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5684 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5688 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5689 u8 queue_id3_tsa_assign; 5690 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5691 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5692 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5693 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5694 u8 queue_id3_pri_lvl; 5695 u8 queue_id3_bw_weight; 5696 u8 queue_id4; 5697 __le32 queue_id4_min_bw; 5698 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5699 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5700 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5701 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5702 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5703 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5704 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5705 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5706 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5707 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5708 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5709 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5710 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5711 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5712 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5713 __le32 queue_id4_max_bw; 5714 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5715 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5716 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5717 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5718 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5719 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5720 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5721 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5722 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5723 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5724 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5725 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5726 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5729 u8 queue_id4_tsa_assign; 5730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5734 u8 queue_id4_pri_lvl; 5735 u8 queue_id4_bw_weight; 5736 u8 queue_id5; 5737 __le32 queue_id5_min_bw; 5738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5740 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5742 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5743 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5745 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5746 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5753 __le32 queue_id5_max_bw; 5754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5756 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5758 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5759 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5761 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5762 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5763 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5764 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5765 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5766 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5767 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5769 u8 queue_id5_tsa_assign; 5770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5774 u8 queue_id5_pri_lvl; 5775 u8 queue_id5_bw_weight; 5776 u8 queue_id6; 5777 __le32 queue_id6_min_bw; 5778 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5780 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5781 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5782 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5783 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5784 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5785 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5786 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5787 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5788 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5789 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5790 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5791 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5792 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5793 __le32 queue_id6_max_bw; 5794 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5795 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5796 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5797 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5798 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5799 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5800 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5801 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5802 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5803 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5804 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5805 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5806 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5807 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5808 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5809 u8 queue_id6_tsa_assign; 5810 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5811 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5812 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5813 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5814 u8 queue_id6_pri_lvl; 5815 u8 queue_id6_bw_weight; 5816 u8 queue_id7; 5817 __le32 queue_id7_min_bw; 5818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5820 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5833 __le32 queue_id7_max_bw; 5834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5836 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5842 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5843 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5844 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5845 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5846 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5849 u8 queue_id7_tsa_assign; 5850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5854 u8 queue_id7_pri_lvl; 5855 u8 queue_id7_bw_weight; 5856 u8 unused_1[5]; 5857 }; 5858 5859 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5860 struct hwrm_queue_cos2bw_cfg_output { 5861 __le16 error_code; 5862 __le16 req_type; 5863 __le16 seq_id; 5864 __le16 resp_len; 5865 u8 unused_0[7]; 5866 u8 valid; 5867 }; 5868 5869 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5870 struct hwrm_queue_dscp_qcaps_input { 5871 __le16 req_type; 5872 __le16 cmpl_ring; 5873 __le16 seq_id; 5874 __le16 target_id; 5875 __le64 resp_addr; 5876 u8 port_id; 5877 u8 unused_0[7]; 5878 }; 5879 5880 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5881 struct hwrm_queue_dscp_qcaps_output { 5882 __le16 error_code; 5883 __le16 req_type; 5884 __le16 seq_id; 5885 __le16 resp_len; 5886 u8 num_dscp_bits; 5887 u8 unused_0; 5888 __le16 max_entries; 5889 u8 unused_1[3]; 5890 u8 valid; 5891 }; 5892 5893 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5894 struct hwrm_queue_dscp2pri_qcfg_input { 5895 __le16 req_type; 5896 __le16 cmpl_ring; 5897 __le16 seq_id; 5898 __le16 target_id; 5899 __le64 resp_addr; 5900 __le64 dest_data_addr; 5901 u8 port_id; 5902 u8 unused_0; 5903 __le16 dest_data_buffer_size; 5904 u8 unused_1[4]; 5905 }; 5906 5907 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5908 struct hwrm_queue_dscp2pri_qcfg_output { 5909 __le16 error_code; 5910 __le16 req_type; 5911 __le16 seq_id; 5912 __le16 resp_len; 5913 __le16 entry_cnt; 5914 u8 default_pri; 5915 u8 unused_0[4]; 5916 u8 valid; 5917 }; 5918 5919 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5920 struct hwrm_queue_dscp2pri_cfg_input { 5921 __le16 req_type; 5922 __le16 cmpl_ring; 5923 __le16 seq_id; 5924 __le16 target_id; 5925 __le64 resp_addr; 5926 __le64 src_data_addr; 5927 __le32 flags; 5928 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5929 __le32 enables; 5930 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5931 u8 port_id; 5932 u8 default_pri; 5933 __le16 entry_cnt; 5934 u8 unused_0[4]; 5935 }; 5936 5937 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5938 struct hwrm_queue_dscp2pri_cfg_output { 5939 __le16 error_code; 5940 __le16 req_type; 5941 __le16 seq_id; 5942 __le16 resp_len; 5943 u8 unused_0[7]; 5944 u8 valid; 5945 }; 5946 5947 /* hwrm_vnic_alloc_input (size:192b/24B) */ 5948 struct hwrm_vnic_alloc_input { 5949 __le16 req_type; 5950 __le16 cmpl_ring; 5951 __le16 seq_id; 5952 __le16 target_id; 5953 __le64 resp_addr; 5954 __le32 flags; 5955 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5956 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5957 __le16 virtio_net_fid; 5958 u8 unused_0[2]; 5959 }; 5960 5961 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5962 struct hwrm_vnic_alloc_output { 5963 __le16 error_code; 5964 __le16 req_type; 5965 __le16 seq_id; 5966 __le16 resp_len; 5967 __le32 vnic_id; 5968 u8 unused_0[3]; 5969 u8 valid; 5970 }; 5971 5972 /* hwrm_vnic_free_input (size:192b/24B) */ 5973 struct hwrm_vnic_free_input { 5974 __le16 req_type; 5975 __le16 cmpl_ring; 5976 __le16 seq_id; 5977 __le16 target_id; 5978 __le64 resp_addr; 5979 __le32 vnic_id; 5980 u8 unused_0[4]; 5981 }; 5982 5983 /* hwrm_vnic_free_output (size:128b/16B) */ 5984 struct hwrm_vnic_free_output { 5985 __le16 error_code; 5986 __le16 req_type; 5987 __le16 seq_id; 5988 __le16 resp_len; 5989 u8 unused_0[7]; 5990 u8 valid; 5991 }; 5992 5993 /* hwrm_vnic_cfg_input (size:384b/48B) */ 5994 struct hwrm_vnic_cfg_input { 5995 __le16 req_type; 5996 __le16 cmpl_ring; 5997 __le16 seq_id; 5998 __le16 target_id; 5999 __le64 resp_addr; 6000 __le32 flags; 6001 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6002 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6003 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6004 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6005 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6006 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6007 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6008 __le32 enables; 6009 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6010 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6011 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6012 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6013 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6014 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6015 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6016 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6017 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6018 __le16 vnic_id; 6019 __le16 dflt_ring_grp; 6020 __le16 rss_rule; 6021 __le16 cos_rule; 6022 __le16 lb_rule; 6023 __le16 mru; 6024 __le16 default_rx_ring_id; 6025 __le16 default_cmpl_ring_id; 6026 __le16 queue_id; 6027 u8 rx_csum_v2_mode; 6028 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6029 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6030 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6031 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6032 u8 unused0[5]; 6033 }; 6034 6035 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6036 struct hwrm_vnic_cfg_output { 6037 __le16 error_code; 6038 __le16 req_type; 6039 __le16 seq_id; 6040 __le16 resp_len; 6041 u8 unused_0[7]; 6042 u8 valid; 6043 }; 6044 6045 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6046 struct hwrm_vnic_qcaps_input { 6047 __le16 req_type; 6048 __le16 cmpl_ring; 6049 __le16 seq_id; 6050 __le16 target_id; 6051 __le64 resp_addr; 6052 __le32 enables; 6053 u8 unused_0[4]; 6054 }; 6055 6056 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6057 struct hwrm_vnic_qcaps_output { 6058 __le16 error_code; 6059 __le16 req_type; 6060 __le16 seq_id; 6061 __le16 resp_len; 6062 __le16 mru; 6063 u8 unused_0[2]; 6064 __le32 flags; 6065 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6066 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6067 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6068 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6069 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6070 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6071 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6072 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6073 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6074 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6075 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6076 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6077 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6078 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6079 __le16 max_aggs_supported; 6080 u8 unused_1[5]; 6081 u8 valid; 6082 }; 6083 6084 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6085 struct hwrm_vnic_tpa_cfg_input { 6086 __le16 req_type; 6087 __le16 cmpl_ring; 6088 __le16 seq_id; 6089 __le16 target_id; 6090 __le64 resp_addr; 6091 __le32 flags; 6092 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6093 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6094 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6095 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6096 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6097 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6098 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6099 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6100 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6101 __le32 enables; 6102 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6103 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6104 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6105 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6106 __le16 vnic_id; 6107 __le16 max_agg_segs; 6108 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6109 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6110 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6111 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6112 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6113 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6114 __le16 max_aggs; 6115 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6116 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6117 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6118 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6119 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6120 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6121 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6122 u8 unused_0[2]; 6123 __le32 max_agg_timer; 6124 __le32 min_agg_len; 6125 }; 6126 6127 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6128 struct hwrm_vnic_tpa_cfg_output { 6129 __le16 error_code; 6130 __le16 req_type; 6131 __le16 seq_id; 6132 __le16 resp_len; 6133 u8 unused_0[7]; 6134 u8 valid; 6135 }; 6136 6137 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6138 struct hwrm_vnic_tpa_qcfg_input { 6139 __le16 req_type; 6140 __le16 cmpl_ring; 6141 __le16 seq_id; 6142 __le16 target_id; 6143 __le64 resp_addr; 6144 __le16 vnic_id; 6145 u8 unused_0[6]; 6146 }; 6147 6148 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6149 struct hwrm_vnic_tpa_qcfg_output { 6150 __le16 error_code; 6151 __le16 req_type; 6152 __le16 seq_id; 6153 __le16 resp_len; 6154 __le32 flags; 6155 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6156 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6157 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6158 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6159 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6160 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6161 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6162 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6163 __le16 max_agg_segs; 6164 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6165 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6166 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6167 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6168 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6169 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6170 __le16 max_aggs; 6171 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6172 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6173 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6174 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6175 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6176 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6177 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6178 __le32 max_agg_timer; 6179 __le32 min_agg_len; 6180 u8 unused_0[7]; 6181 u8 valid; 6182 }; 6183 6184 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6185 struct hwrm_vnic_rss_cfg_input { 6186 __le16 req_type; 6187 __le16 cmpl_ring; 6188 __le16 seq_id; 6189 __le16 target_id; 6190 __le64 resp_addr; 6191 __le32 hash_type; 6192 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6193 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6194 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6195 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6196 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6197 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6198 __le16 vnic_id; 6199 u8 ring_table_pair_index; 6200 u8 hash_mode_flags; 6201 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6202 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6203 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6204 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6205 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6206 __le64 ring_grp_tbl_addr; 6207 __le64 hash_key_tbl_addr; 6208 __le16 rss_ctx_idx; 6209 u8 unused_1[6]; 6210 }; 6211 6212 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6213 struct hwrm_vnic_rss_cfg_output { 6214 __le16 error_code; 6215 __le16 req_type; 6216 __le16 seq_id; 6217 __le16 resp_len; 6218 u8 unused_0[7]; 6219 u8 valid; 6220 }; 6221 6222 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6223 struct hwrm_vnic_rss_cfg_cmd_err { 6224 u8 code; 6225 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6226 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6227 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6228 u8 unused_0[7]; 6229 }; 6230 6231 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6232 struct hwrm_vnic_plcmodes_cfg_input { 6233 __le16 req_type; 6234 __le16 cmpl_ring; 6235 __le16 seq_id; 6236 __le16 target_id; 6237 __le64 resp_addr; 6238 __le32 flags; 6239 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6240 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6241 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6242 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6243 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6244 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6245 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6246 __le32 enables; 6247 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6248 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6249 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6250 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6251 __le32 vnic_id; 6252 __le16 jumbo_thresh; 6253 __le16 hds_offset; 6254 __le16 hds_threshold; 6255 __le16 max_bds; 6256 u8 unused_0[4]; 6257 }; 6258 6259 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6260 struct hwrm_vnic_plcmodes_cfg_output { 6261 __le16 error_code; 6262 __le16 req_type; 6263 __le16 seq_id; 6264 __le16 resp_len; 6265 u8 unused_0[7]; 6266 u8 valid; 6267 }; 6268 6269 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6270 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6271 __le16 req_type; 6272 __le16 cmpl_ring; 6273 __le16 seq_id; 6274 __le16 target_id; 6275 __le64 resp_addr; 6276 }; 6277 6278 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6279 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6280 __le16 error_code; 6281 __le16 req_type; 6282 __le16 seq_id; 6283 __le16 resp_len; 6284 __le16 rss_cos_lb_ctx_id; 6285 u8 unused_0[5]; 6286 u8 valid; 6287 }; 6288 6289 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6290 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6291 __le16 req_type; 6292 __le16 cmpl_ring; 6293 __le16 seq_id; 6294 __le16 target_id; 6295 __le64 resp_addr; 6296 __le16 rss_cos_lb_ctx_id; 6297 u8 unused_0[6]; 6298 }; 6299 6300 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6301 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6302 __le16 error_code; 6303 __le16 req_type; 6304 __le16 seq_id; 6305 __le16 resp_len; 6306 u8 unused_0[7]; 6307 u8 valid; 6308 }; 6309 6310 /* hwrm_ring_alloc_input (size:704b/88B) */ 6311 struct hwrm_ring_alloc_input { 6312 __le16 req_type; 6313 __le16 cmpl_ring; 6314 __le16 seq_id; 6315 __le16 target_id; 6316 __le64 resp_addr; 6317 __le32 enables; 6318 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6319 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6320 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6321 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6322 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6323 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6324 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6325 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6326 u8 ring_type; 6327 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6328 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6329 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6330 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6331 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6332 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6333 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6334 u8 unused_0; 6335 __le16 flags; 6336 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6337 __le64 page_tbl_addr; 6338 __le32 fbo; 6339 u8 page_size; 6340 u8 page_tbl_depth; 6341 __le16 schq_id; 6342 __le32 length; 6343 __le16 logical_id; 6344 __le16 cmpl_ring_id; 6345 __le16 queue_id; 6346 __le16 rx_buf_size; 6347 __le16 rx_ring_id; 6348 __le16 nq_ring_id; 6349 __le16 ring_arb_cfg; 6350 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6351 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6352 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6353 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6354 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6355 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6356 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6357 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6358 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6359 __le16 unused_3; 6360 __le32 reserved3; 6361 __le32 stat_ctx_id; 6362 __le32 reserved4; 6363 __le32 max_bw; 6364 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6365 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6366 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6367 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6368 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6369 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6370 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6371 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6372 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6373 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6374 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6375 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6376 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6377 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6378 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6379 u8 int_mode; 6380 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6381 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6382 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6383 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6384 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 6385 u8 mpc_chnls_type; 6386 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 6387 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 6388 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 6389 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 6390 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 6391 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 6392 u8 unused_4[2]; 6393 __le64 cq_handle; 6394 }; 6395 6396 /* hwrm_ring_alloc_output (size:128b/16B) */ 6397 struct hwrm_ring_alloc_output { 6398 __le16 error_code; 6399 __le16 req_type; 6400 __le16 seq_id; 6401 __le16 resp_len; 6402 __le16 ring_id; 6403 __le16 logical_ring_id; 6404 u8 push_buffer_index; 6405 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6406 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6407 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6408 u8 unused_0[2]; 6409 u8 valid; 6410 }; 6411 6412 /* hwrm_ring_free_input (size:256b/32B) */ 6413 struct hwrm_ring_free_input { 6414 __le16 req_type; 6415 __le16 cmpl_ring; 6416 __le16 seq_id; 6417 __le16 target_id; 6418 __le64 resp_addr; 6419 u8 ring_type; 6420 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 6421 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 6422 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 6423 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6424 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 6425 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 6426 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 6427 u8 flags; 6428 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 6429 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 6430 __le16 ring_id; 6431 __le32 prod_idx; 6432 __le32 opaque; 6433 __le32 unused_1; 6434 }; 6435 6436 /* hwrm_ring_free_output (size:128b/16B) */ 6437 struct hwrm_ring_free_output { 6438 __le16 error_code; 6439 __le16 req_type; 6440 __le16 seq_id; 6441 __le16 resp_len; 6442 u8 unused_0[7]; 6443 u8 valid; 6444 }; 6445 6446 /* hwrm_ring_reset_input (size:192b/24B) */ 6447 struct hwrm_ring_reset_input { 6448 __le16 req_type; 6449 __le16 cmpl_ring; 6450 __le16 seq_id; 6451 __le16 target_id; 6452 __le64 resp_addr; 6453 u8 ring_type; 6454 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 6455 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 6456 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 6457 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6458 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 6459 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 6460 u8 unused_0; 6461 __le16 ring_id; 6462 u8 unused_1[4]; 6463 }; 6464 6465 /* hwrm_ring_reset_output (size:128b/16B) */ 6466 struct hwrm_ring_reset_output { 6467 __le16 error_code; 6468 __le16 req_type; 6469 __le16 seq_id; 6470 __le16 resp_len; 6471 u8 push_buffer_index; 6472 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6473 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6474 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6475 u8 unused_0[3]; 6476 u8 consumer_idx[3]; 6477 u8 valid; 6478 }; 6479 6480 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 6481 struct hwrm_ring_aggint_qcaps_input { 6482 __le16 req_type; 6483 __le16 cmpl_ring; 6484 __le16 seq_id; 6485 __le16 target_id; 6486 __le64 resp_addr; 6487 }; 6488 6489 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 6490 struct hwrm_ring_aggint_qcaps_output { 6491 __le16 error_code; 6492 __le16 req_type; 6493 __le16 seq_id; 6494 __le16 resp_len; 6495 __le32 cmpl_params; 6496 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 6497 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 6498 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 6499 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 6500 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 6501 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 6502 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 6503 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 6504 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 6505 __le32 nq_params; 6506 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 6507 __le16 num_cmpl_dma_aggr_min; 6508 __le16 num_cmpl_dma_aggr_max; 6509 __le16 num_cmpl_dma_aggr_during_int_min; 6510 __le16 num_cmpl_dma_aggr_during_int_max; 6511 __le16 cmpl_aggr_dma_tmr_min; 6512 __le16 cmpl_aggr_dma_tmr_max; 6513 __le16 cmpl_aggr_dma_tmr_during_int_min; 6514 __le16 cmpl_aggr_dma_tmr_during_int_max; 6515 __le16 int_lat_tmr_min_min; 6516 __le16 int_lat_tmr_min_max; 6517 __le16 int_lat_tmr_max_min; 6518 __le16 int_lat_tmr_max_max; 6519 __le16 num_cmpl_aggr_int_min; 6520 __le16 num_cmpl_aggr_int_max; 6521 __le16 timer_units; 6522 u8 unused_0[1]; 6523 u8 valid; 6524 }; 6525 6526 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 6527 struct hwrm_ring_cmpl_ring_qaggint_params_input { 6528 __le16 req_type; 6529 __le16 cmpl_ring; 6530 __le16 seq_id; 6531 __le16 target_id; 6532 __le64 resp_addr; 6533 __le16 ring_id; 6534 __le16 flags; 6535 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 6536 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 6537 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6538 u8 unused_0[4]; 6539 }; 6540 6541 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 6542 struct hwrm_ring_cmpl_ring_qaggint_params_output { 6543 __le16 error_code; 6544 __le16 req_type; 6545 __le16 seq_id; 6546 __le16 resp_len; 6547 __le16 flags; 6548 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 6549 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 6550 __le16 num_cmpl_dma_aggr; 6551 __le16 num_cmpl_dma_aggr_during_int; 6552 __le16 cmpl_aggr_dma_tmr; 6553 __le16 cmpl_aggr_dma_tmr_during_int; 6554 __le16 int_lat_tmr_min; 6555 __le16 int_lat_tmr_max; 6556 __le16 num_cmpl_aggr_int; 6557 u8 unused_0[7]; 6558 u8 valid; 6559 }; 6560 6561 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 6562 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 6563 __le16 req_type; 6564 __le16 cmpl_ring; 6565 __le16 seq_id; 6566 __le16 target_id; 6567 __le64 resp_addr; 6568 __le16 ring_id; 6569 __le16 flags; 6570 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 6571 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 6572 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6573 __le16 num_cmpl_dma_aggr; 6574 __le16 num_cmpl_dma_aggr_during_int; 6575 __le16 cmpl_aggr_dma_tmr; 6576 __le16 cmpl_aggr_dma_tmr_during_int; 6577 __le16 int_lat_tmr_min; 6578 __le16 int_lat_tmr_max; 6579 __le16 num_cmpl_aggr_int; 6580 __le16 enables; 6581 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 6582 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 6583 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 6584 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 6585 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 6586 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 6587 u8 unused_0[4]; 6588 }; 6589 6590 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 6591 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 6592 __le16 error_code; 6593 __le16 req_type; 6594 __le16 seq_id; 6595 __le16 resp_len; 6596 u8 unused_0[7]; 6597 u8 valid; 6598 }; 6599 6600 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 6601 struct hwrm_ring_grp_alloc_input { 6602 __le16 req_type; 6603 __le16 cmpl_ring; 6604 __le16 seq_id; 6605 __le16 target_id; 6606 __le64 resp_addr; 6607 __le16 cr; 6608 __le16 rr; 6609 __le16 ar; 6610 __le16 sc; 6611 }; 6612 6613 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 6614 struct hwrm_ring_grp_alloc_output { 6615 __le16 error_code; 6616 __le16 req_type; 6617 __le16 seq_id; 6618 __le16 resp_len; 6619 __le32 ring_group_id; 6620 u8 unused_0[3]; 6621 u8 valid; 6622 }; 6623 6624 /* hwrm_ring_grp_free_input (size:192b/24B) */ 6625 struct hwrm_ring_grp_free_input { 6626 __le16 req_type; 6627 __le16 cmpl_ring; 6628 __le16 seq_id; 6629 __le16 target_id; 6630 __le64 resp_addr; 6631 __le32 ring_group_id; 6632 u8 unused_0[4]; 6633 }; 6634 6635 /* hwrm_ring_grp_free_output (size:128b/16B) */ 6636 struct hwrm_ring_grp_free_output { 6637 __le16 error_code; 6638 __le16 req_type; 6639 __le16 seq_id; 6640 __le16 resp_len; 6641 u8 unused_0[7]; 6642 u8 valid; 6643 }; 6644 6645 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 6646 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 6647 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 6648 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 6649 6650 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 6651 struct hwrm_cfa_l2_filter_alloc_input { 6652 __le16 req_type; 6653 __le16 cmpl_ring; 6654 __le16 seq_id; 6655 __le16 target_id; 6656 __le64 resp_addr; 6657 __le32 flags; 6658 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 6659 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 6660 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 6661 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 6662 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 6663 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 6664 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 6665 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 6666 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 6667 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 6668 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 6669 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 6670 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 6671 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 6672 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 6673 __le32 enables; 6674 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 6675 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 6676 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 6677 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 6678 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 6679 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 6680 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 6681 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 6682 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 6683 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 6684 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 6685 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 6686 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 6687 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6688 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6689 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6690 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6691 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 6692 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6693 u8 l2_addr[6]; 6694 u8 num_vlans; 6695 u8 t_num_vlans; 6696 u8 l2_addr_mask[6]; 6697 __le16 l2_ovlan; 6698 __le16 l2_ovlan_mask; 6699 __le16 l2_ivlan; 6700 __le16 l2_ivlan_mask; 6701 u8 unused_1[2]; 6702 u8 t_l2_addr[6]; 6703 u8 unused_2[2]; 6704 u8 t_l2_addr_mask[6]; 6705 __le16 t_l2_ovlan; 6706 __le16 t_l2_ovlan_mask; 6707 __le16 t_l2_ivlan; 6708 __le16 t_l2_ivlan_mask; 6709 u8 src_type; 6710 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6711 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6712 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6713 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6714 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6715 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6716 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6717 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6718 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6719 u8 unused_3; 6720 __le32 src_id; 6721 u8 tunnel_type; 6722 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6723 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6724 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6725 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6726 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6727 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6728 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6729 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6730 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6731 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6732 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6733 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6734 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6735 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6736 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6737 u8 unused_4; 6738 __le16 dst_id; 6739 __le16 mirror_vnic_id; 6740 u8 pri_hint; 6741 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6742 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6743 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6744 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6745 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6746 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6747 u8 unused_5; 6748 __le32 unused_6; 6749 __le64 l2_filter_id_hint; 6750 }; 6751 6752 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6753 struct hwrm_cfa_l2_filter_alloc_output { 6754 __le16 error_code; 6755 __le16 req_type; 6756 __le16 seq_id; 6757 __le16 resp_len; 6758 __le64 l2_filter_id; 6759 __le32 flow_id; 6760 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6761 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6762 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6763 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6764 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6765 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6766 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6767 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6768 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6769 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6770 u8 unused_0[3]; 6771 u8 valid; 6772 }; 6773 6774 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6775 struct hwrm_cfa_l2_filter_free_input { 6776 __le16 req_type; 6777 __le16 cmpl_ring; 6778 __le16 seq_id; 6779 __le16 target_id; 6780 __le64 resp_addr; 6781 __le64 l2_filter_id; 6782 }; 6783 6784 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6785 struct hwrm_cfa_l2_filter_free_output { 6786 __le16 error_code; 6787 __le16 req_type; 6788 __le16 seq_id; 6789 __le16 resp_len; 6790 u8 unused_0[7]; 6791 u8 valid; 6792 }; 6793 6794 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6795 struct hwrm_cfa_l2_filter_cfg_input { 6796 __le16 req_type; 6797 __le16 cmpl_ring; 6798 __le16 seq_id; 6799 __le16 target_id; 6800 __le64 resp_addr; 6801 __le32 flags; 6802 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6803 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6804 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 6805 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6806 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 6807 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 6808 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 6809 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 6810 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 6811 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 6812 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6813 __le32 enables; 6814 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6815 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6816 __le64 l2_filter_id; 6817 __le32 dst_id; 6818 __le32 new_mirror_vnic_id; 6819 }; 6820 6821 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6822 struct hwrm_cfa_l2_filter_cfg_output { 6823 __le16 error_code; 6824 __le16 req_type; 6825 __le16 seq_id; 6826 __le16 resp_len; 6827 u8 unused_0[7]; 6828 u8 valid; 6829 }; 6830 6831 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6832 struct hwrm_cfa_l2_set_rx_mask_input { 6833 __le16 req_type; 6834 __le16 cmpl_ring; 6835 __le16 seq_id; 6836 __le16 target_id; 6837 __le64 resp_addr; 6838 __le32 vnic_id; 6839 __le32 mask; 6840 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6841 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6842 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6843 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6844 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6845 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6846 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6847 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6848 __le64 mc_tbl_addr; 6849 __le32 num_mc_entries; 6850 u8 unused_0[4]; 6851 __le64 vlan_tag_tbl_addr; 6852 __le32 num_vlan_tags; 6853 u8 unused_1[4]; 6854 }; 6855 6856 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6857 struct hwrm_cfa_l2_set_rx_mask_output { 6858 __le16 error_code; 6859 __le16 req_type; 6860 __le16 seq_id; 6861 __le16 resp_len; 6862 u8 unused_0[7]; 6863 u8 valid; 6864 }; 6865 6866 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6867 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6868 u8 code; 6869 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6870 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6871 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6872 u8 unused_0[7]; 6873 }; 6874 6875 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6876 struct hwrm_cfa_tunnel_filter_alloc_input { 6877 __le16 req_type; 6878 __le16 cmpl_ring; 6879 __le16 seq_id; 6880 __le16 target_id; 6881 __le64 resp_addr; 6882 __le32 flags; 6883 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6884 __le32 enables; 6885 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6886 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6887 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6888 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6889 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6890 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6891 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6892 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6893 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6894 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6895 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6896 __le64 l2_filter_id; 6897 u8 l2_addr[6]; 6898 __le16 l2_ivlan; 6899 __le32 l3_addr[4]; 6900 __le32 t_l3_addr[4]; 6901 u8 l3_addr_type; 6902 u8 t_l3_addr_type; 6903 u8 tunnel_type; 6904 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6905 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6906 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6907 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6908 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6909 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6910 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6911 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6912 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6913 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6914 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6915 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6916 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6917 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6918 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6919 u8 tunnel_flags; 6920 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6921 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6922 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6923 __le32 vni; 6924 __le32 dst_vnic_id; 6925 __le32 mirror_vnic_id; 6926 }; 6927 6928 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6929 struct hwrm_cfa_tunnel_filter_alloc_output { 6930 __le16 error_code; 6931 __le16 req_type; 6932 __le16 seq_id; 6933 __le16 resp_len; 6934 __le64 tunnel_filter_id; 6935 __le32 flow_id; 6936 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6937 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6938 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6939 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6940 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6941 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6942 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6943 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6944 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6945 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6946 u8 unused_0[3]; 6947 u8 valid; 6948 }; 6949 6950 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6951 struct hwrm_cfa_tunnel_filter_free_input { 6952 __le16 req_type; 6953 __le16 cmpl_ring; 6954 __le16 seq_id; 6955 __le16 target_id; 6956 __le64 resp_addr; 6957 __le64 tunnel_filter_id; 6958 }; 6959 6960 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6961 struct hwrm_cfa_tunnel_filter_free_output { 6962 __le16 error_code; 6963 __le16 req_type; 6964 __le16 seq_id; 6965 __le16 resp_len; 6966 u8 unused_0[7]; 6967 u8 valid; 6968 }; 6969 6970 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6971 struct hwrm_vxlan_ipv4_hdr { 6972 u8 ver_hlen; 6973 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6974 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6975 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6976 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6977 u8 tos; 6978 __be16 ip_id; 6979 __be16 flags_frag_offset; 6980 u8 ttl; 6981 u8 protocol; 6982 __be32 src_ip_addr; 6983 __be32 dest_ip_addr; 6984 }; 6985 6986 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6987 struct hwrm_vxlan_ipv6_hdr { 6988 __be32 ver_tc_flow_label; 6989 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6990 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6991 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6992 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6993 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6994 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6995 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6996 __be16 payload_len; 6997 u8 next_hdr; 6998 u8 ttl; 6999 __be32 src_ip_addr[4]; 7000 __be32 dest_ip_addr[4]; 7001 }; 7002 7003 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7004 struct hwrm_cfa_encap_data_vxlan { 7005 u8 src_mac_addr[6]; 7006 __le16 unused_0; 7007 u8 dst_mac_addr[6]; 7008 u8 num_vlan_tags; 7009 u8 unused_1; 7010 __be16 ovlan_tpid; 7011 __be16 ovlan_tci; 7012 __be16 ivlan_tpid; 7013 __be16 ivlan_tci; 7014 __le32 l3[10]; 7015 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7016 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7017 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7018 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7019 __be16 src_port; 7020 __be16 dst_port; 7021 __be32 vni; 7022 u8 hdr_rsvd0[3]; 7023 u8 hdr_rsvd1; 7024 u8 hdr_flags; 7025 u8 unused[3]; 7026 }; 7027 7028 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7029 struct hwrm_cfa_encap_record_alloc_input { 7030 __le16 req_type; 7031 __le16 cmpl_ring; 7032 __le16 seq_id; 7033 __le16 target_id; 7034 __le64 resp_addr; 7035 __le32 flags; 7036 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7037 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7038 u8 encap_type; 7039 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7040 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7041 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7042 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7043 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7044 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7045 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7046 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7047 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7048 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7049 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7050 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7051 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7052 u8 unused_0[3]; 7053 __le32 encap_data[20]; 7054 }; 7055 7056 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7057 struct hwrm_cfa_encap_record_alloc_output { 7058 __le16 error_code; 7059 __le16 req_type; 7060 __le16 seq_id; 7061 __le16 resp_len; 7062 __le32 encap_record_id; 7063 u8 unused_0[3]; 7064 u8 valid; 7065 }; 7066 7067 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7068 struct hwrm_cfa_encap_record_free_input { 7069 __le16 req_type; 7070 __le16 cmpl_ring; 7071 __le16 seq_id; 7072 __le16 target_id; 7073 __le64 resp_addr; 7074 __le32 encap_record_id; 7075 u8 unused_0[4]; 7076 }; 7077 7078 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7079 struct hwrm_cfa_encap_record_free_output { 7080 __le16 error_code; 7081 __le16 req_type; 7082 __le16 seq_id; 7083 __le16 resp_len; 7084 u8 unused_0[7]; 7085 u8 valid; 7086 }; 7087 7088 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7089 struct hwrm_cfa_ntuple_filter_alloc_input { 7090 __le16 req_type; 7091 __le16 cmpl_ring; 7092 __le16 seq_id; 7093 __le16 target_id; 7094 __le64 resp_addr; 7095 __le32 flags; 7096 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7097 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7098 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7099 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7100 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7101 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7102 __le32 enables; 7103 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7104 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7105 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7106 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7107 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7108 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7109 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7110 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7111 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7112 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7113 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7114 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7115 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7116 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7117 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7118 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7119 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7120 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7121 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7122 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7123 __le64 l2_filter_id; 7124 u8 src_macaddr[6]; 7125 __be16 ethertype; 7126 u8 ip_addr_type; 7127 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7128 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7129 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7130 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7131 u8 ip_protocol; 7132 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7133 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7134 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7135 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7136 __le16 dst_id; 7137 __le16 mirror_vnic_id; 7138 u8 tunnel_type; 7139 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7140 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7141 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7142 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7143 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7144 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7145 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7146 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7147 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7148 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7149 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7150 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7151 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7152 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7153 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7154 u8 pri_hint; 7155 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7156 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7157 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7158 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7159 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7160 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7161 __be32 src_ipaddr[4]; 7162 __be32 src_ipaddr_mask[4]; 7163 __be32 dst_ipaddr[4]; 7164 __be32 dst_ipaddr_mask[4]; 7165 __be16 src_port; 7166 __be16 src_port_mask; 7167 __be16 dst_port; 7168 __be16 dst_port_mask; 7169 __le64 ntuple_filter_id_hint; 7170 }; 7171 7172 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7173 struct hwrm_cfa_ntuple_filter_alloc_output { 7174 __le16 error_code; 7175 __le16 req_type; 7176 __le16 seq_id; 7177 __le16 resp_len; 7178 __le64 ntuple_filter_id; 7179 __le32 flow_id; 7180 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7181 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7182 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7183 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7184 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7185 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7186 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7187 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7188 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7189 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7190 u8 unused_0[3]; 7191 u8 valid; 7192 }; 7193 7194 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7195 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7196 u8 code; 7197 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7198 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7199 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7200 u8 unused_0[7]; 7201 }; 7202 7203 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7204 struct hwrm_cfa_ntuple_filter_free_input { 7205 __le16 req_type; 7206 __le16 cmpl_ring; 7207 __le16 seq_id; 7208 __le16 target_id; 7209 __le64 resp_addr; 7210 __le64 ntuple_filter_id; 7211 }; 7212 7213 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7214 struct hwrm_cfa_ntuple_filter_free_output { 7215 __le16 error_code; 7216 __le16 req_type; 7217 __le16 seq_id; 7218 __le16 resp_len; 7219 u8 unused_0[7]; 7220 u8 valid; 7221 }; 7222 7223 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7224 struct hwrm_cfa_ntuple_filter_cfg_input { 7225 __le16 req_type; 7226 __le16 cmpl_ring; 7227 __le16 seq_id; 7228 __le16 target_id; 7229 __le64 resp_addr; 7230 __le32 enables; 7231 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7232 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7233 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7234 __le32 flags; 7235 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7236 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7237 __le64 ntuple_filter_id; 7238 __le32 new_dst_id; 7239 __le32 new_mirror_vnic_id; 7240 __le16 new_meter_instance_id; 7241 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7242 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7243 u8 unused_1[6]; 7244 }; 7245 7246 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7247 struct hwrm_cfa_ntuple_filter_cfg_output { 7248 __le16 error_code; 7249 __le16 req_type; 7250 __le16 seq_id; 7251 __le16 resp_len; 7252 u8 unused_0[7]; 7253 u8 valid; 7254 }; 7255 7256 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7257 struct hwrm_cfa_decap_filter_alloc_input { 7258 __le16 req_type; 7259 __le16 cmpl_ring; 7260 __le16 seq_id; 7261 __le16 target_id; 7262 __le64 resp_addr; 7263 __le32 flags; 7264 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7265 __le32 enables; 7266 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7267 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7268 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7269 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7270 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7271 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7272 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7273 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7274 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7275 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7276 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7277 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7278 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7279 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7280 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7281 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7282 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7283 __be32 tunnel_id; 7284 u8 tunnel_type; 7285 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7286 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7287 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7288 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7289 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7290 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7291 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7292 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7293 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7294 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7295 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7296 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7297 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7298 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7299 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7300 u8 unused_0; 7301 __le16 unused_1; 7302 u8 src_macaddr[6]; 7303 u8 unused_2[2]; 7304 u8 dst_macaddr[6]; 7305 __be16 ovlan_vid; 7306 __be16 ivlan_vid; 7307 __be16 t_ovlan_vid; 7308 __be16 t_ivlan_vid; 7309 __be16 ethertype; 7310 u8 ip_addr_type; 7311 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7312 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7313 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7314 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7315 u8 ip_protocol; 7316 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7317 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7318 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7319 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7320 __le16 unused_3; 7321 __le32 unused_4; 7322 __be32 src_ipaddr[4]; 7323 __be32 dst_ipaddr[4]; 7324 __be16 src_port; 7325 __be16 dst_port; 7326 __le16 dst_id; 7327 __le16 l2_ctxt_ref_id; 7328 }; 7329 7330 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7331 struct hwrm_cfa_decap_filter_alloc_output { 7332 __le16 error_code; 7333 __le16 req_type; 7334 __le16 seq_id; 7335 __le16 resp_len; 7336 __le32 decap_filter_id; 7337 u8 unused_0[3]; 7338 u8 valid; 7339 }; 7340 7341 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 7342 struct hwrm_cfa_decap_filter_free_input { 7343 __le16 req_type; 7344 __le16 cmpl_ring; 7345 __le16 seq_id; 7346 __le16 target_id; 7347 __le64 resp_addr; 7348 __le32 decap_filter_id; 7349 u8 unused_0[4]; 7350 }; 7351 7352 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 7353 struct hwrm_cfa_decap_filter_free_output { 7354 __le16 error_code; 7355 __le16 req_type; 7356 __le16 seq_id; 7357 __le16 resp_len; 7358 u8 unused_0[7]; 7359 u8 valid; 7360 }; 7361 7362 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 7363 struct hwrm_cfa_flow_alloc_input { 7364 __le16 req_type; 7365 __le16 cmpl_ring; 7366 __le16 seq_id; 7367 __le16 target_id; 7368 __le64 resp_addr; 7369 __le16 flags; 7370 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 7371 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 7372 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 7373 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 7374 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 7375 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 7376 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 7377 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 7378 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 7379 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 7380 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 7381 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 7382 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 7383 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 7384 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 7385 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 7386 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 7387 __le16 src_fid; 7388 __le32 tunnel_handle; 7389 __le16 action_flags; 7390 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 7391 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 7392 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 7393 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 7394 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 7395 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 7396 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 7397 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 7398 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 7399 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 7400 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 7401 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 7402 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 7403 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 7404 __le16 dst_fid; 7405 __be16 l2_rewrite_vlan_tpid; 7406 __be16 l2_rewrite_vlan_tci; 7407 __le16 act_meter_id; 7408 __le16 ref_flow_handle; 7409 __be16 ethertype; 7410 __be16 outer_vlan_tci; 7411 __be16 dmac[3]; 7412 __be16 inner_vlan_tci; 7413 __be16 smac[3]; 7414 u8 ip_dst_mask_len; 7415 u8 ip_src_mask_len; 7416 __be32 ip_dst[4]; 7417 __be32 ip_src[4]; 7418 __be16 l4_src_port; 7419 __be16 l4_src_port_mask; 7420 __be16 l4_dst_port; 7421 __be16 l4_dst_port_mask; 7422 __be32 nat_ip_address[4]; 7423 __be16 l2_rewrite_dmac[3]; 7424 __be16 nat_port; 7425 __be16 l2_rewrite_smac[3]; 7426 u8 ip_proto; 7427 u8 tunnel_type; 7428 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7429 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7430 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7431 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7432 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7433 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7434 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7435 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7436 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7437 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7438 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7439 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7440 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7441 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7442 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7443 }; 7444 7445 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 7446 struct hwrm_cfa_flow_alloc_output { 7447 __le16 error_code; 7448 __le16 req_type; 7449 __le16 seq_id; 7450 __le16 resp_len; 7451 __le16 flow_handle; 7452 u8 unused_0[2]; 7453 __le32 flow_id; 7454 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7455 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7456 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7457 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7458 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7459 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 7460 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7461 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7462 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7463 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 7464 __le64 ext_flow_handle; 7465 __le32 flow_counter_id; 7466 u8 unused_1[3]; 7467 u8 valid; 7468 }; 7469 7470 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 7471 struct hwrm_cfa_flow_alloc_cmd_err { 7472 u8 code; 7473 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7474 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 7475 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 7476 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 7477 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 7478 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 7479 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 7480 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 7481 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 7482 u8 unused_0[7]; 7483 }; 7484 7485 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 7486 struct hwrm_cfa_flow_free_input { 7487 __le16 req_type; 7488 __le16 cmpl_ring; 7489 __le16 seq_id; 7490 __le16 target_id; 7491 __le64 resp_addr; 7492 __le16 flow_handle; 7493 __le16 unused_0; 7494 __le32 flow_counter_id; 7495 __le64 ext_flow_handle; 7496 }; 7497 7498 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 7499 struct hwrm_cfa_flow_free_output { 7500 __le16 error_code; 7501 __le16 req_type; 7502 __le16 seq_id; 7503 __le16 resp_len; 7504 __le64 packet; 7505 __le64 byte; 7506 u8 unused_0[7]; 7507 u8 valid; 7508 }; 7509 7510 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 7511 struct hwrm_cfa_flow_info_input { 7512 __le16 req_type; 7513 __le16 cmpl_ring; 7514 __le16 seq_id; 7515 __le16 target_id; 7516 __le64 resp_addr; 7517 __le16 flow_handle; 7518 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 7519 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 7520 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 7521 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 7522 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 7523 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 7524 u8 unused_0[6]; 7525 __le64 ext_flow_handle; 7526 }; 7527 7528 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 7529 struct hwrm_cfa_flow_info_output { 7530 __le16 error_code; 7531 __le16 req_type; 7532 __le16 seq_id; 7533 __le16 resp_len; 7534 u8 flags; 7535 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 7536 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 7537 u8 profile; 7538 __le16 src_fid; 7539 __le16 dst_fid; 7540 __le16 l2_ctxt_id; 7541 __le64 em_info; 7542 __le64 tcam_info; 7543 __le64 vfp_tcam_info; 7544 __le16 ar_id; 7545 __le16 flow_handle; 7546 __le32 tunnel_handle; 7547 __le16 flow_timer; 7548 u8 unused_0[6]; 7549 __le32 flow_key_data[130]; 7550 __le32 flow_action_info[30]; 7551 u8 unused_1[7]; 7552 u8 valid; 7553 }; 7554 7555 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 7556 struct hwrm_cfa_flow_stats_input { 7557 __le16 req_type; 7558 __le16 cmpl_ring; 7559 __le16 seq_id; 7560 __le16 target_id; 7561 __le64 resp_addr; 7562 __le16 num_flows; 7563 __le16 flow_handle_0; 7564 __le16 flow_handle_1; 7565 __le16 flow_handle_2; 7566 __le16 flow_handle_3; 7567 __le16 flow_handle_4; 7568 __le16 flow_handle_5; 7569 __le16 flow_handle_6; 7570 __le16 flow_handle_7; 7571 __le16 flow_handle_8; 7572 __le16 flow_handle_9; 7573 u8 unused_0[2]; 7574 __le32 flow_id_0; 7575 __le32 flow_id_1; 7576 __le32 flow_id_2; 7577 __le32 flow_id_3; 7578 __le32 flow_id_4; 7579 __le32 flow_id_5; 7580 __le32 flow_id_6; 7581 __le32 flow_id_7; 7582 __le32 flow_id_8; 7583 __le32 flow_id_9; 7584 }; 7585 7586 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 7587 struct hwrm_cfa_flow_stats_output { 7588 __le16 error_code; 7589 __le16 req_type; 7590 __le16 seq_id; 7591 __le16 resp_len; 7592 __le64 packet_0; 7593 __le64 packet_1; 7594 __le64 packet_2; 7595 __le64 packet_3; 7596 __le64 packet_4; 7597 __le64 packet_5; 7598 __le64 packet_6; 7599 __le64 packet_7; 7600 __le64 packet_8; 7601 __le64 packet_9; 7602 __le64 byte_0; 7603 __le64 byte_1; 7604 __le64 byte_2; 7605 __le64 byte_3; 7606 __le64 byte_4; 7607 __le64 byte_5; 7608 __le64 byte_6; 7609 __le64 byte_7; 7610 __le64 byte_8; 7611 __le64 byte_9; 7612 u8 unused_0[7]; 7613 u8 valid; 7614 }; 7615 7616 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 7617 struct hwrm_cfa_vfr_alloc_input { 7618 __le16 req_type; 7619 __le16 cmpl_ring; 7620 __le16 seq_id; 7621 __le16 target_id; 7622 __le64 resp_addr; 7623 __le16 vf_id; 7624 __le16 reserved; 7625 u8 unused_0[4]; 7626 char vfr_name[32]; 7627 }; 7628 7629 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 7630 struct hwrm_cfa_vfr_alloc_output { 7631 __le16 error_code; 7632 __le16 req_type; 7633 __le16 seq_id; 7634 __le16 resp_len; 7635 __le16 rx_cfa_code; 7636 __le16 tx_cfa_action; 7637 u8 unused_0[3]; 7638 u8 valid; 7639 }; 7640 7641 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 7642 struct hwrm_cfa_vfr_free_input { 7643 __le16 req_type; 7644 __le16 cmpl_ring; 7645 __le16 seq_id; 7646 __le16 target_id; 7647 __le64 resp_addr; 7648 char vfr_name[32]; 7649 __le16 vf_id; 7650 __le16 reserved; 7651 u8 unused_0[4]; 7652 }; 7653 7654 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 7655 struct hwrm_cfa_vfr_free_output { 7656 __le16 error_code; 7657 __le16 req_type; 7658 __le16 seq_id; 7659 __le16 resp_len; 7660 u8 unused_0[7]; 7661 u8 valid; 7662 }; 7663 7664 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 7665 struct hwrm_cfa_eem_qcaps_input { 7666 __le16 req_type; 7667 __le16 cmpl_ring; 7668 __le16 seq_id; 7669 __le16 target_id; 7670 __le64 resp_addr; 7671 __le32 flags; 7672 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 7673 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 7674 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7675 __le32 unused_0; 7676 }; 7677 7678 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 7679 struct hwrm_cfa_eem_qcaps_output { 7680 __le16 error_code; 7681 __le16 req_type; 7682 __le16 seq_id; 7683 __le16 resp_len; 7684 __le32 flags; 7685 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 7686 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 7687 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 7688 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 7689 __le32 unused_0; 7690 __le32 supported; 7691 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 7692 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 7693 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 7694 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 7695 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 7696 __le32 max_entries_supported; 7697 __le16 key_entry_size; 7698 __le16 record_entry_size; 7699 __le16 efc_entry_size; 7700 __le16 fid_entry_size; 7701 u8 unused_1[7]; 7702 u8 valid; 7703 }; 7704 7705 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 7706 struct hwrm_cfa_eem_cfg_input { 7707 __le16 req_type; 7708 __le16 cmpl_ring; 7709 __le16 seq_id; 7710 __le16 target_id; 7711 __le64 resp_addr; 7712 __le32 flags; 7713 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 7714 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 7715 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7716 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 7717 __le16 group_id; 7718 __le16 unused_0; 7719 __le32 num_entries; 7720 __le32 unused_1; 7721 __le16 key0_ctx_id; 7722 __le16 key1_ctx_id; 7723 __le16 record_ctx_id; 7724 __le16 efc_ctx_id; 7725 __le16 fid_ctx_id; 7726 __le16 unused_2; 7727 __le32 unused_3; 7728 }; 7729 7730 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 7731 struct hwrm_cfa_eem_cfg_output { 7732 __le16 error_code; 7733 __le16 req_type; 7734 __le16 seq_id; 7735 __le16 resp_len; 7736 u8 unused_0[7]; 7737 u8 valid; 7738 }; 7739 7740 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 7741 struct hwrm_cfa_eem_qcfg_input { 7742 __le16 req_type; 7743 __le16 cmpl_ring; 7744 __le16 seq_id; 7745 __le16 target_id; 7746 __le64 resp_addr; 7747 __le32 flags; 7748 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 7749 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 7750 __le32 unused_0; 7751 }; 7752 7753 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 7754 struct hwrm_cfa_eem_qcfg_output { 7755 __le16 error_code; 7756 __le16 req_type; 7757 __le16 seq_id; 7758 __le16 resp_len; 7759 __le32 flags; 7760 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 7761 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 7762 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 7763 __le32 num_entries; 7764 __le16 key0_ctx_id; 7765 __le16 key1_ctx_id; 7766 __le16 record_ctx_id; 7767 __le16 efc_ctx_id; 7768 __le16 fid_ctx_id; 7769 u8 unused_2[5]; 7770 u8 valid; 7771 }; 7772 7773 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 7774 struct hwrm_cfa_eem_op_input { 7775 __le16 req_type; 7776 __le16 cmpl_ring; 7777 __le16 seq_id; 7778 __le16 target_id; 7779 __le64 resp_addr; 7780 __le32 flags; 7781 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 7782 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 7783 __le16 unused_0; 7784 __le16 op; 7785 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 7786 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 7787 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 7788 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 7789 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 7790 }; 7791 7792 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 7793 struct hwrm_cfa_eem_op_output { 7794 __le16 error_code; 7795 __le16 req_type; 7796 __le16 seq_id; 7797 __le16 resp_len; 7798 u8 unused_0[7]; 7799 u8 valid; 7800 }; 7801 7802 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 7803 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 7804 __le16 req_type; 7805 __le16 cmpl_ring; 7806 __le16 seq_id; 7807 __le16 target_id; 7808 __le64 resp_addr; 7809 __le32 unused_0[4]; 7810 }; 7811 7812 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 7813 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 7814 __le16 error_code; 7815 __le16 req_type; 7816 __le16 seq_id; 7817 __le16 resp_len; 7818 __le32 flags; 7819 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 7820 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 7821 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 7822 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 7823 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 7824 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 7825 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 7826 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 7827 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7828 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7829 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7830 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7831 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7832 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7833 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7834 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7835 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 7836 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 7837 u8 unused_0[3]; 7838 u8 valid; 7839 }; 7840 7841 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7842 struct hwrm_tunnel_dst_port_query_input { 7843 __le16 req_type; 7844 __le16 cmpl_ring; 7845 __le16 seq_id; 7846 __le16 target_id; 7847 __le64 resp_addr; 7848 u8 tunnel_type; 7849 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7850 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7851 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7852 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7853 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7854 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7855 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7856 u8 unused_0[7]; 7857 }; 7858 7859 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7860 struct hwrm_tunnel_dst_port_query_output { 7861 __le16 error_code; 7862 __le16 req_type; 7863 __le16 seq_id; 7864 __le16 resp_len; 7865 __le16 tunnel_dst_port_id; 7866 __be16 tunnel_dst_port_val; 7867 u8 unused_0[3]; 7868 u8 valid; 7869 }; 7870 7871 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7872 struct hwrm_tunnel_dst_port_alloc_input { 7873 __le16 req_type; 7874 __le16 cmpl_ring; 7875 __le16 seq_id; 7876 __le16 target_id; 7877 __le64 resp_addr; 7878 u8 tunnel_type; 7879 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7880 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7881 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7882 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7883 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7884 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7885 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7886 u8 unused_0; 7887 __be16 tunnel_dst_port_val; 7888 u8 unused_1[4]; 7889 }; 7890 7891 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7892 struct hwrm_tunnel_dst_port_alloc_output { 7893 __le16 error_code; 7894 __le16 req_type; 7895 __le16 seq_id; 7896 __le16 resp_len; 7897 __le16 tunnel_dst_port_id; 7898 u8 unused_0[5]; 7899 u8 valid; 7900 }; 7901 7902 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7903 struct hwrm_tunnel_dst_port_free_input { 7904 __le16 req_type; 7905 __le16 cmpl_ring; 7906 __le16 seq_id; 7907 __le16 target_id; 7908 __le64 resp_addr; 7909 u8 tunnel_type; 7910 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7911 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7912 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7913 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7914 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7915 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7916 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7917 u8 unused_0; 7918 __le16 tunnel_dst_port_id; 7919 u8 unused_1[4]; 7920 }; 7921 7922 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7923 struct hwrm_tunnel_dst_port_free_output { 7924 __le16 error_code; 7925 __le16 req_type; 7926 __le16 seq_id; 7927 __le16 resp_len; 7928 u8 unused_1[7]; 7929 u8 valid; 7930 }; 7931 7932 /* ctx_hw_stats (size:1280b/160B) */ 7933 struct ctx_hw_stats { 7934 __le64 rx_ucast_pkts; 7935 __le64 rx_mcast_pkts; 7936 __le64 rx_bcast_pkts; 7937 __le64 rx_discard_pkts; 7938 __le64 rx_error_pkts; 7939 __le64 rx_ucast_bytes; 7940 __le64 rx_mcast_bytes; 7941 __le64 rx_bcast_bytes; 7942 __le64 tx_ucast_pkts; 7943 __le64 tx_mcast_pkts; 7944 __le64 tx_bcast_pkts; 7945 __le64 tx_error_pkts; 7946 __le64 tx_discard_pkts; 7947 __le64 tx_ucast_bytes; 7948 __le64 tx_mcast_bytes; 7949 __le64 tx_bcast_bytes; 7950 __le64 tpa_pkts; 7951 __le64 tpa_bytes; 7952 __le64 tpa_events; 7953 __le64 tpa_aborts; 7954 }; 7955 7956 /* ctx_hw_stats_ext (size:1408b/176B) */ 7957 struct ctx_hw_stats_ext { 7958 __le64 rx_ucast_pkts; 7959 __le64 rx_mcast_pkts; 7960 __le64 rx_bcast_pkts; 7961 __le64 rx_discard_pkts; 7962 __le64 rx_error_pkts; 7963 __le64 rx_ucast_bytes; 7964 __le64 rx_mcast_bytes; 7965 __le64 rx_bcast_bytes; 7966 __le64 tx_ucast_pkts; 7967 __le64 tx_mcast_pkts; 7968 __le64 tx_bcast_pkts; 7969 __le64 tx_error_pkts; 7970 __le64 tx_discard_pkts; 7971 __le64 tx_ucast_bytes; 7972 __le64 tx_mcast_bytes; 7973 __le64 tx_bcast_bytes; 7974 __le64 rx_tpa_eligible_pkt; 7975 __le64 rx_tpa_eligible_bytes; 7976 __le64 rx_tpa_pkt; 7977 __le64 rx_tpa_bytes; 7978 __le64 rx_tpa_errors; 7979 __le64 rx_tpa_events; 7980 }; 7981 7982 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7983 struct hwrm_stat_ctx_alloc_input { 7984 __le16 req_type; 7985 __le16 cmpl_ring; 7986 __le16 seq_id; 7987 __le16 target_id; 7988 __le64 resp_addr; 7989 __le64 stats_dma_addr; 7990 __le32 update_period_ms; 7991 u8 stat_ctx_flags; 7992 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7993 u8 unused_0; 7994 __le16 stats_dma_length; 7995 }; 7996 7997 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7998 struct hwrm_stat_ctx_alloc_output { 7999 __le16 error_code; 8000 __le16 req_type; 8001 __le16 seq_id; 8002 __le16 resp_len; 8003 __le32 stat_ctx_id; 8004 u8 unused_0[3]; 8005 u8 valid; 8006 }; 8007 8008 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8009 struct hwrm_stat_ctx_free_input { 8010 __le16 req_type; 8011 __le16 cmpl_ring; 8012 __le16 seq_id; 8013 __le16 target_id; 8014 __le64 resp_addr; 8015 __le32 stat_ctx_id; 8016 u8 unused_0[4]; 8017 }; 8018 8019 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8020 struct hwrm_stat_ctx_free_output { 8021 __le16 error_code; 8022 __le16 req_type; 8023 __le16 seq_id; 8024 __le16 resp_len; 8025 __le32 stat_ctx_id; 8026 u8 unused_0[3]; 8027 u8 valid; 8028 }; 8029 8030 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8031 struct hwrm_stat_ctx_query_input { 8032 __le16 req_type; 8033 __le16 cmpl_ring; 8034 __le16 seq_id; 8035 __le16 target_id; 8036 __le64 resp_addr; 8037 __le32 stat_ctx_id; 8038 u8 flags; 8039 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8040 u8 unused_0[3]; 8041 }; 8042 8043 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8044 struct hwrm_stat_ctx_query_output { 8045 __le16 error_code; 8046 __le16 req_type; 8047 __le16 seq_id; 8048 __le16 resp_len; 8049 __le64 tx_ucast_pkts; 8050 __le64 tx_mcast_pkts; 8051 __le64 tx_bcast_pkts; 8052 __le64 tx_discard_pkts; 8053 __le64 tx_error_pkts; 8054 __le64 tx_ucast_bytes; 8055 __le64 tx_mcast_bytes; 8056 __le64 tx_bcast_bytes; 8057 __le64 rx_ucast_pkts; 8058 __le64 rx_mcast_pkts; 8059 __le64 rx_bcast_pkts; 8060 __le64 rx_discard_pkts; 8061 __le64 rx_error_pkts; 8062 __le64 rx_ucast_bytes; 8063 __le64 rx_mcast_bytes; 8064 __le64 rx_bcast_bytes; 8065 __le64 rx_agg_pkts; 8066 __le64 rx_agg_bytes; 8067 __le64 rx_agg_events; 8068 __le64 rx_agg_aborts; 8069 u8 unused_0[7]; 8070 u8 valid; 8071 }; 8072 8073 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8074 struct hwrm_stat_ext_ctx_query_input { 8075 __le16 req_type; 8076 __le16 cmpl_ring; 8077 __le16 seq_id; 8078 __le16 target_id; 8079 __le64 resp_addr; 8080 __le32 stat_ctx_id; 8081 u8 flags; 8082 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8083 u8 unused_0[3]; 8084 }; 8085 8086 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8087 struct hwrm_stat_ext_ctx_query_output { 8088 __le16 error_code; 8089 __le16 req_type; 8090 __le16 seq_id; 8091 __le16 resp_len; 8092 __le64 rx_ucast_pkts; 8093 __le64 rx_mcast_pkts; 8094 __le64 rx_bcast_pkts; 8095 __le64 rx_discard_pkts; 8096 __le64 rx_error_pkts; 8097 __le64 rx_ucast_bytes; 8098 __le64 rx_mcast_bytes; 8099 __le64 rx_bcast_bytes; 8100 __le64 tx_ucast_pkts; 8101 __le64 tx_mcast_pkts; 8102 __le64 tx_bcast_pkts; 8103 __le64 tx_error_pkts; 8104 __le64 tx_discard_pkts; 8105 __le64 tx_ucast_bytes; 8106 __le64 tx_mcast_bytes; 8107 __le64 tx_bcast_bytes; 8108 __le64 rx_tpa_eligible_pkt; 8109 __le64 rx_tpa_eligible_bytes; 8110 __le64 rx_tpa_pkt; 8111 __le64 rx_tpa_bytes; 8112 __le64 rx_tpa_errors; 8113 __le64 rx_tpa_events; 8114 u8 unused_0[7]; 8115 u8 valid; 8116 }; 8117 8118 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8119 struct hwrm_stat_ctx_clr_stats_input { 8120 __le16 req_type; 8121 __le16 cmpl_ring; 8122 __le16 seq_id; 8123 __le16 target_id; 8124 __le64 resp_addr; 8125 __le32 stat_ctx_id; 8126 u8 unused_0[4]; 8127 }; 8128 8129 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8130 struct hwrm_stat_ctx_clr_stats_output { 8131 __le16 error_code; 8132 __le16 req_type; 8133 __le16 seq_id; 8134 __le16 resp_len; 8135 u8 unused_0[7]; 8136 u8 valid; 8137 }; 8138 8139 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8140 struct hwrm_pcie_qstats_input { 8141 __le16 req_type; 8142 __le16 cmpl_ring; 8143 __le16 seq_id; 8144 __le16 target_id; 8145 __le64 resp_addr; 8146 __le16 pcie_stat_size; 8147 u8 unused_0[6]; 8148 __le64 pcie_stat_host_addr; 8149 }; 8150 8151 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8152 struct hwrm_pcie_qstats_output { 8153 __le16 error_code; 8154 __le16 req_type; 8155 __le16 seq_id; 8156 __le16 resp_len; 8157 __le16 pcie_stat_size; 8158 u8 unused_0[5]; 8159 u8 valid; 8160 }; 8161 8162 /* pcie_ctx_hw_stats (size:768b/96B) */ 8163 struct pcie_ctx_hw_stats { 8164 __le64 pcie_pl_signal_integrity; 8165 __le64 pcie_dl_signal_integrity; 8166 __le64 pcie_tl_signal_integrity; 8167 __le64 pcie_link_integrity; 8168 __le64 pcie_tx_traffic_rate; 8169 __le64 pcie_rx_traffic_rate; 8170 __le64 pcie_tx_dllp_statistics; 8171 __le64 pcie_rx_dllp_statistics; 8172 __le64 pcie_equalization_time; 8173 __le32 pcie_ltssm_histogram[4]; 8174 __le64 pcie_recovery_histogram; 8175 }; 8176 8177 /* hwrm_fw_reset_input (size:192b/24B) */ 8178 struct hwrm_fw_reset_input { 8179 __le16 req_type; 8180 __le16 cmpl_ring; 8181 __le16 seq_id; 8182 __le16 target_id; 8183 __le64 resp_addr; 8184 u8 embedded_proc_type; 8185 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8186 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8187 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8188 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8189 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8190 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8191 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8192 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8193 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8194 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8195 u8 selfrst_status; 8196 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8197 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8198 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8199 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8200 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8201 u8 host_idx; 8202 u8 flags; 8203 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8204 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 8205 u8 unused_0[4]; 8206 }; 8207 8208 /* hwrm_fw_reset_output (size:128b/16B) */ 8209 struct hwrm_fw_reset_output { 8210 __le16 error_code; 8211 __le16 req_type; 8212 __le16 seq_id; 8213 __le16 resp_len; 8214 u8 selfrst_status; 8215 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8216 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8217 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8218 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8219 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8220 u8 unused_0[6]; 8221 u8 valid; 8222 }; 8223 8224 /* hwrm_fw_qstatus_input (size:192b/24B) */ 8225 struct hwrm_fw_qstatus_input { 8226 __le16 req_type; 8227 __le16 cmpl_ring; 8228 __le16 seq_id; 8229 __le16 target_id; 8230 __le64 resp_addr; 8231 u8 embedded_proc_type; 8232 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8233 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8234 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8235 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8236 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8237 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8238 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8239 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8240 u8 unused_0[7]; 8241 }; 8242 8243 /* hwrm_fw_qstatus_output (size:128b/16B) */ 8244 struct hwrm_fw_qstatus_output { 8245 __le16 error_code; 8246 __le16 req_type; 8247 __le16 seq_id; 8248 __le16 resp_len; 8249 u8 selfrst_status; 8250 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8251 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8252 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8253 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 8254 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 8255 u8 nvm_option_action_status; 8256 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 8257 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 8258 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 8259 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 8260 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 8261 u8 unused_0[5]; 8262 u8 valid; 8263 }; 8264 8265 /* hwrm_fw_set_time_input (size:256b/32B) */ 8266 struct hwrm_fw_set_time_input { 8267 __le16 req_type; 8268 __le16 cmpl_ring; 8269 __le16 seq_id; 8270 __le16 target_id; 8271 __le64 resp_addr; 8272 __le16 year; 8273 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8274 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8275 u8 month; 8276 u8 day; 8277 u8 hour; 8278 u8 minute; 8279 u8 second; 8280 u8 unused_0; 8281 __le16 millisecond; 8282 __le16 zone; 8283 #define FW_SET_TIME_REQ_ZONE_UTC 0 8284 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8285 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8286 u8 unused_1[4]; 8287 }; 8288 8289 /* hwrm_fw_set_time_output (size:128b/16B) */ 8290 struct hwrm_fw_set_time_output { 8291 __le16 error_code; 8292 __le16 req_type; 8293 __le16 seq_id; 8294 __le16 resp_len; 8295 u8 unused_0[7]; 8296 u8 valid; 8297 }; 8298 8299 /* hwrm_struct_hdr (size:128b/16B) */ 8300 struct hwrm_struct_hdr { 8301 __le16 struct_id; 8302 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 8303 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 8304 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 8305 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 8306 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 8307 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 8308 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 8309 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 8310 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 8311 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 8312 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 8313 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 8314 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 8315 __le16 len; 8316 u8 version; 8317 u8 count; 8318 __le16 subtype; 8319 __le16 next_offset; 8320 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 8321 u8 unused_0[6]; 8322 }; 8323 8324 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 8325 struct hwrm_struct_data_dcbx_app { 8326 __be16 protocol_id; 8327 u8 protocol_selector; 8328 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 8329 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 8330 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 8331 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 8332 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 8333 u8 priority; 8334 u8 valid; 8335 u8 unused_0[3]; 8336 }; 8337 8338 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 8339 struct hwrm_fw_set_structured_data_input { 8340 __le16 req_type; 8341 __le16 cmpl_ring; 8342 __le16 seq_id; 8343 __le16 target_id; 8344 __le64 resp_addr; 8345 __le64 src_data_addr; 8346 __le16 data_len; 8347 u8 hdr_cnt; 8348 u8 unused_0[5]; 8349 }; 8350 8351 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 8352 struct hwrm_fw_set_structured_data_output { 8353 __le16 error_code; 8354 __le16 req_type; 8355 __le16 seq_id; 8356 __le16 resp_len; 8357 u8 unused_0[7]; 8358 u8 valid; 8359 }; 8360 8361 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 8362 struct hwrm_fw_set_structured_data_cmd_err { 8363 u8 code; 8364 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8365 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 8366 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 8367 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8368 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8369 u8 unused_0[7]; 8370 }; 8371 8372 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 8373 struct hwrm_fw_get_structured_data_input { 8374 __le16 req_type; 8375 __le16 cmpl_ring; 8376 __le16 seq_id; 8377 __le16 target_id; 8378 __le64 resp_addr; 8379 __le64 dest_data_addr; 8380 __le16 data_len; 8381 __le16 structure_id; 8382 __le16 subtype; 8383 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 8384 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 8385 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 8386 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 8387 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 8388 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 8389 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 8390 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 8391 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 8392 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 8393 u8 count; 8394 u8 unused_0; 8395 }; 8396 8397 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 8398 struct hwrm_fw_get_structured_data_output { 8399 __le16 error_code; 8400 __le16 req_type; 8401 __le16 seq_id; 8402 __le16 resp_len; 8403 u8 hdr_cnt; 8404 u8 unused_0[6]; 8405 u8 valid; 8406 }; 8407 8408 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 8409 struct hwrm_fw_get_structured_data_cmd_err { 8410 u8 code; 8411 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8412 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8413 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8414 u8 unused_0[7]; 8415 }; 8416 8417 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 8418 struct hwrm_exec_fwd_resp_input { 8419 __le16 req_type; 8420 __le16 cmpl_ring; 8421 __le16 seq_id; 8422 __le16 target_id; 8423 __le64 resp_addr; 8424 __le32 encap_request[26]; 8425 __le16 encap_resp_target_id; 8426 u8 unused_0[6]; 8427 }; 8428 8429 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 8430 struct hwrm_exec_fwd_resp_output { 8431 __le16 error_code; 8432 __le16 req_type; 8433 __le16 seq_id; 8434 __le16 resp_len; 8435 u8 unused_0[7]; 8436 u8 valid; 8437 }; 8438 8439 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 8440 struct hwrm_reject_fwd_resp_input { 8441 __le16 req_type; 8442 __le16 cmpl_ring; 8443 __le16 seq_id; 8444 __le16 target_id; 8445 __le64 resp_addr; 8446 __le32 encap_request[26]; 8447 __le16 encap_resp_target_id; 8448 u8 unused_0[6]; 8449 }; 8450 8451 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 8452 struct hwrm_reject_fwd_resp_output { 8453 __le16 error_code; 8454 __le16 req_type; 8455 __le16 seq_id; 8456 __le16 resp_len; 8457 u8 unused_0[7]; 8458 u8 valid; 8459 }; 8460 8461 /* hwrm_fwd_resp_input (size:1024b/128B) */ 8462 struct hwrm_fwd_resp_input { 8463 __le16 req_type; 8464 __le16 cmpl_ring; 8465 __le16 seq_id; 8466 __le16 target_id; 8467 __le64 resp_addr; 8468 __le16 encap_resp_target_id; 8469 __le16 encap_resp_cmpl_ring; 8470 __le16 encap_resp_len; 8471 u8 unused_0; 8472 u8 unused_1; 8473 __le64 encap_resp_addr; 8474 __le32 encap_resp[24]; 8475 }; 8476 8477 /* hwrm_fwd_resp_output (size:128b/16B) */ 8478 struct hwrm_fwd_resp_output { 8479 __le16 error_code; 8480 __le16 req_type; 8481 __le16 seq_id; 8482 __le16 resp_len; 8483 u8 unused_0[7]; 8484 u8 valid; 8485 }; 8486 8487 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 8488 struct hwrm_fwd_async_event_cmpl_input { 8489 __le16 req_type; 8490 __le16 cmpl_ring; 8491 __le16 seq_id; 8492 __le16 target_id; 8493 __le64 resp_addr; 8494 __le16 encap_async_event_target_id; 8495 u8 unused_0[6]; 8496 __le32 encap_async_event_cmpl[4]; 8497 }; 8498 8499 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 8500 struct hwrm_fwd_async_event_cmpl_output { 8501 __le16 error_code; 8502 __le16 req_type; 8503 __le16 seq_id; 8504 __le16 resp_len; 8505 u8 unused_0[7]; 8506 u8 valid; 8507 }; 8508 8509 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 8510 struct hwrm_temp_monitor_query_input { 8511 __le16 req_type; 8512 __le16 cmpl_ring; 8513 __le16 seq_id; 8514 __le16 target_id; 8515 __le64 resp_addr; 8516 }; 8517 8518 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 8519 struct hwrm_temp_monitor_query_output { 8520 __le16 error_code; 8521 __le16 req_type; 8522 __le16 seq_id; 8523 __le16 resp_len; 8524 u8 temp; 8525 u8 phy_temp; 8526 u8 om_temp; 8527 u8 flags; 8528 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 8529 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 8530 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 8531 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 8532 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 8533 u8 temp2; 8534 u8 phy_temp2; 8535 u8 om_temp2; 8536 u8 valid; 8537 }; 8538 8539 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 8540 struct hwrm_wol_filter_alloc_input { 8541 __le16 req_type; 8542 __le16 cmpl_ring; 8543 __le16 seq_id; 8544 __le16 target_id; 8545 __le64 resp_addr; 8546 __le32 flags; 8547 __le32 enables; 8548 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 8549 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 8550 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 8551 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 8552 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 8553 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 8554 __le16 port_id; 8555 u8 wol_type; 8556 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 8557 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 8558 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 8559 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 8560 u8 unused_0[5]; 8561 u8 mac_address[6]; 8562 __le16 pattern_offset; 8563 __le16 pattern_buf_size; 8564 __le16 pattern_mask_size; 8565 u8 unused_1[4]; 8566 __le64 pattern_buf_addr; 8567 __le64 pattern_mask_addr; 8568 }; 8569 8570 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 8571 struct hwrm_wol_filter_alloc_output { 8572 __le16 error_code; 8573 __le16 req_type; 8574 __le16 seq_id; 8575 __le16 resp_len; 8576 u8 wol_filter_id; 8577 u8 unused_0[6]; 8578 u8 valid; 8579 }; 8580 8581 /* hwrm_wol_filter_free_input (size:256b/32B) */ 8582 struct hwrm_wol_filter_free_input { 8583 __le16 req_type; 8584 __le16 cmpl_ring; 8585 __le16 seq_id; 8586 __le16 target_id; 8587 __le64 resp_addr; 8588 __le32 flags; 8589 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 8590 __le32 enables; 8591 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 8592 __le16 port_id; 8593 u8 wol_filter_id; 8594 u8 unused_0[5]; 8595 }; 8596 8597 /* hwrm_wol_filter_free_output (size:128b/16B) */ 8598 struct hwrm_wol_filter_free_output { 8599 __le16 error_code; 8600 __le16 req_type; 8601 __le16 seq_id; 8602 __le16 resp_len; 8603 u8 unused_0[7]; 8604 u8 valid; 8605 }; 8606 8607 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 8608 struct hwrm_wol_filter_qcfg_input { 8609 __le16 req_type; 8610 __le16 cmpl_ring; 8611 __le16 seq_id; 8612 __le16 target_id; 8613 __le64 resp_addr; 8614 __le16 port_id; 8615 __le16 handle; 8616 u8 unused_0[4]; 8617 __le64 pattern_buf_addr; 8618 __le16 pattern_buf_size; 8619 u8 unused_1[6]; 8620 __le64 pattern_mask_addr; 8621 __le16 pattern_mask_size; 8622 u8 unused_2[6]; 8623 }; 8624 8625 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 8626 struct hwrm_wol_filter_qcfg_output { 8627 __le16 error_code; 8628 __le16 req_type; 8629 __le16 seq_id; 8630 __le16 resp_len; 8631 __le16 next_handle; 8632 u8 wol_filter_id; 8633 u8 wol_type; 8634 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 8635 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 8636 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 8637 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 8638 __le32 unused_0; 8639 u8 mac_address[6]; 8640 __le16 pattern_offset; 8641 __le16 pattern_size; 8642 __le16 pattern_mask_size; 8643 u8 unused_1[3]; 8644 u8 valid; 8645 }; 8646 8647 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 8648 struct hwrm_wol_reason_qcfg_input { 8649 __le16 req_type; 8650 __le16 cmpl_ring; 8651 __le16 seq_id; 8652 __le16 target_id; 8653 __le64 resp_addr; 8654 __le16 port_id; 8655 u8 unused_0[6]; 8656 __le64 wol_pkt_buf_addr; 8657 __le16 wol_pkt_buf_size; 8658 u8 unused_1[6]; 8659 }; 8660 8661 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 8662 struct hwrm_wol_reason_qcfg_output { 8663 __le16 error_code; 8664 __le16 req_type; 8665 __le16 seq_id; 8666 __le16 resp_len; 8667 u8 wol_filter_id; 8668 u8 wol_reason; 8669 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 8670 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 8671 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 8672 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 8673 u8 wol_pkt_len; 8674 u8 unused_0[4]; 8675 u8 valid; 8676 }; 8677 8678 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 8679 struct hwrm_dbg_read_direct_input { 8680 __le16 req_type; 8681 __le16 cmpl_ring; 8682 __le16 seq_id; 8683 __le16 target_id; 8684 __le64 resp_addr; 8685 __le64 host_dest_addr; 8686 __le32 read_addr; 8687 __le32 read_len32; 8688 }; 8689 8690 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 8691 struct hwrm_dbg_read_direct_output { 8692 __le16 error_code; 8693 __le16 req_type; 8694 __le16 seq_id; 8695 __le16 resp_len; 8696 __le32 crc32; 8697 u8 unused_0[3]; 8698 u8 valid; 8699 }; 8700 8701 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 8702 struct hwrm_dbg_qcaps_input { 8703 __le16 req_type; 8704 __le16 cmpl_ring; 8705 __le16 seq_id; 8706 __le16 target_id; 8707 __le64 resp_addr; 8708 __le16 fid; 8709 u8 unused_0[6]; 8710 }; 8711 8712 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 8713 struct hwrm_dbg_qcaps_output { 8714 __le16 error_code; 8715 __le16 req_type; 8716 __le16 seq_id; 8717 __le16 resp_len; 8718 __le16 fid; 8719 u8 unused_0[2]; 8720 __le32 coredump_component_disable_caps; 8721 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 8722 __le32 flags; 8723 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 8724 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 8725 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 8726 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 8727 u8 unused_1[3]; 8728 u8 valid; 8729 }; 8730 8731 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 8732 struct hwrm_dbg_qcfg_input { 8733 __le16 req_type; 8734 __le16 cmpl_ring; 8735 __le16 seq_id; 8736 __le16 target_id; 8737 __le64 resp_addr; 8738 __le16 fid; 8739 __le16 flags; 8740 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 8741 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 8742 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 8743 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 8744 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 8745 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 8746 __le32 coredump_component_disable_flags; 8747 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 8748 }; 8749 8750 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 8751 struct hwrm_dbg_qcfg_output { 8752 __le16 error_code; 8753 __le16 req_type; 8754 __le16 seq_id; 8755 __le16 resp_len; 8756 __le16 fid; 8757 u8 unused_0[2]; 8758 __le32 coredump_size; 8759 __le32 flags; 8760 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 8761 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 8762 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 8763 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 8764 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 8765 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 8766 __le16 async_cmpl_ring; 8767 u8 unused_2[2]; 8768 __le32 crashdump_size; 8769 u8 unused_3[3]; 8770 u8 valid; 8771 }; 8772 8773 /* coredump_segment_record (size:128b/16B) */ 8774 struct coredump_segment_record { 8775 __le16 component_id; 8776 __le16 segment_id; 8777 __le16 max_instances; 8778 u8 version_hi; 8779 u8 version_low; 8780 u8 seg_flags; 8781 u8 compress_flags; 8782 #define SFLAG_COMPRESSED_ZLIB 0x1UL 8783 u8 unused_0[2]; 8784 __le32 segment_len; 8785 }; 8786 8787 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 8788 struct hwrm_dbg_coredump_list_input { 8789 __le16 req_type; 8790 __le16 cmpl_ring; 8791 __le16 seq_id; 8792 __le16 target_id; 8793 __le64 resp_addr; 8794 __le64 host_dest_addr; 8795 __le32 host_buf_len; 8796 __le16 seq_no; 8797 u8 flags; 8798 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 8799 u8 unused_0[1]; 8800 }; 8801 8802 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 8803 struct hwrm_dbg_coredump_list_output { 8804 __le16 error_code; 8805 __le16 req_type; 8806 __le16 seq_id; 8807 __le16 resp_len; 8808 u8 flags; 8809 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 8810 u8 unused_0; 8811 __le16 total_segments; 8812 __le16 data_len; 8813 u8 unused_1; 8814 u8 valid; 8815 }; 8816 8817 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 8818 struct hwrm_dbg_coredump_initiate_input { 8819 __le16 req_type; 8820 __le16 cmpl_ring; 8821 __le16 seq_id; 8822 __le16 target_id; 8823 __le64 resp_addr; 8824 __le16 component_id; 8825 __le16 segment_id; 8826 __le16 instance; 8827 __le16 unused_0; 8828 u8 seg_flags; 8829 u8 unused_1[7]; 8830 }; 8831 8832 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 8833 struct hwrm_dbg_coredump_initiate_output { 8834 __le16 error_code; 8835 __le16 req_type; 8836 __le16 seq_id; 8837 __le16 resp_len; 8838 u8 unused_0[7]; 8839 u8 valid; 8840 }; 8841 8842 /* coredump_data_hdr (size:128b/16B) */ 8843 struct coredump_data_hdr { 8844 __le32 address; 8845 __le32 flags_length; 8846 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8847 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8848 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 8849 __le32 instance; 8850 __le32 next_offset; 8851 }; 8852 8853 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8854 struct hwrm_dbg_coredump_retrieve_input { 8855 __le16 req_type; 8856 __le16 cmpl_ring; 8857 __le16 seq_id; 8858 __le16 target_id; 8859 __le64 resp_addr; 8860 __le64 host_dest_addr; 8861 __le32 host_buf_len; 8862 __le32 unused_0; 8863 __le16 component_id; 8864 __le16 segment_id; 8865 __le16 instance; 8866 __le16 unused_1; 8867 u8 seg_flags; 8868 u8 unused_2; 8869 __le16 unused_3; 8870 __le32 unused_4; 8871 __le32 seq_no; 8872 __le32 unused_5; 8873 }; 8874 8875 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 8876 struct hwrm_dbg_coredump_retrieve_output { 8877 __le16 error_code; 8878 __le16 req_type; 8879 __le16 seq_id; 8880 __le16 resp_len; 8881 u8 flags; 8882 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 8883 u8 unused_0; 8884 __le16 data_len; 8885 u8 unused_1[3]; 8886 u8 valid; 8887 }; 8888 8889 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 8890 struct hwrm_dbg_ring_info_get_input { 8891 __le16 req_type; 8892 __le16 cmpl_ring; 8893 __le16 seq_id; 8894 __le16 target_id; 8895 __le64 resp_addr; 8896 u8 ring_type; 8897 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 8898 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 8899 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8900 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8901 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 8902 u8 unused_0[3]; 8903 __le32 fw_ring_id; 8904 }; 8905 8906 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 8907 struct hwrm_dbg_ring_info_get_output { 8908 __le16 error_code; 8909 __le16 req_type; 8910 __le16 seq_id; 8911 __le16 resp_len; 8912 __le32 producer_index; 8913 __le32 consumer_index; 8914 __le32 cag_vector_ctrl; 8915 u8 unused_0[3]; 8916 u8 valid; 8917 }; 8918 8919 /* hwrm_nvm_read_input (size:320b/40B) */ 8920 struct hwrm_nvm_read_input { 8921 __le16 req_type; 8922 __le16 cmpl_ring; 8923 __le16 seq_id; 8924 __le16 target_id; 8925 __le64 resp_addr; 8926 __le64 host_dest_addr; 8927 __le16 dir_idx; 8928 u8 unused_0[2]; 8929 __le32 offset; 8930 __le32 len; 8931 u8 unused_1[4]; 8932 }; 8933 8934 /* hwrm_nvm_read_output (size:128b/16B) */ 8935 struct hwrm_nvm_read_output { 8936 __le16 error_code; 8937 __le16 req_type; 8938 __le16 seq_id; 8939 __le16 resp_len; 8940 u8 unused_0[7]; 8941 u8 valid; 8942 }; 8943 8944 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8945 struct hwrm_nvm_get_dir_entries_input { 8946 __le16 req_type; 8947 __le16 cmpl_ring; 8948 __le16 seq_id; 8949 __le16 target_id; 8950 __le64 resp_addr; 8951 __le64 host_dest_addr; 8952 }; 8953 8954 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8955 struct hwrm_nvm_get_dir_entries_output { 8956 __le16 error_code; 8957 __le16 req_type; 8958 __le16 seq_id; 8959 __le16 resp_len; 8960 u8 unused_0[7]; 8961 u8 valid; 8962 }; 8963 8964 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8965 struct hwrm_nvm_get_dir_info_input { 8966 __le16 req_type; 8967 __le16 cmpl_ring; 8968 __le16 seq_id; 8969 __le16 target_id; 8970 __le64 resp_addr; 8971 }; 8972 8973 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8974 struct hwrm_nvm_get_dir_info_output { 8975 __le16 error_code; 8976 __le16 req_type; 8977 __le16 seq_id; 8978 __le16 resp_len; 8979 __le32 entries; 8980 __le32 entry_length; 8981 u8 unused_0[7]; 8982 u8 valid; 8983 }; 8984 8985 /* hwrm_nvm_write_input (size:448b/56B) */ 8986 struct hwrm_nvm_write_input { 8987 __le16 req_type; 8988 __le16 cmpl_ring; 8989 __le16 seq_id; 8990 __le16 target_id; 8991 __le64 resp_addr; 8992 __le64 host_src_addr; 8993 __le16 dir_type; 8994 __le16 dir_ordinal; 8995 __le16 dir_ext; 8996 __le16 dir_attr; 8997 __le32 dir_data_length; 8998 __le16 option; 8999 __le16 flags; 9000 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9001 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9002 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9003 __le32 dir_item_length; 9004 __le32 offset; 9005 __le32 len; 9006 __le32 unused_0; 9007 }; 9008 9009 /* hwrm_nvm_write_output (size:128b/16B) */ 9010 struct hwrm_nvm_write_output { 9011 __le16 error_code; 9012 __le16 req_type; 9013 __le16 seq_id; 9014 __le16 resp_len; 9015 __le32 dir_item_length; 9016 __le16 dir_idx; 9017 u8 unused_0; 9018 u8 valid; 9019 }; 9020 9021 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9022 struct hwrm_nvm_write_cmd_err { 9023 u8 code; 9024 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9025 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9026 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9027 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9028 u8 unused_0[7]; 9029 }; 9030 9031 /* hwrm_nvm_modify_input (size:320b/40B) */ 9032 struct hwrm_nvm_modify_input { 9033 __le16 req_type; 9034 __le16 cmpl_ring; 9035 __le16 seq_id; 9036 __le16 target_id; 9037 __le64 resp_addr; 9038 __le64 host_src_addr; 9039 __le16 dir_idx; 9040 __le16 flags; 9041 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9042 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9043 __le32 offset; 9044 __le32 len; 9045 u8 unused_1[4]; 9046 }; 9047 9048 /* hwrm_nvm_modify_output (size:128b/16B) */ 9049 struct hwrm_nvm_modify_output { 9050 __le16 error_code; 9051 __le16 req_type; 9052 __le16 seq_id; 9053 __le16 resp_len; 9054 u8 unused_0[7]; 9055 u8 valid; 9056 }; 9057 9058 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9059 struct hwrm_nvm_find_dir_entry_input { 9060 __le16 req_type; 9061 __le16 cmpl_ring; 9062 __le16 seq_id; 9063 __le16 target_id; 9064 __le64 resp_addr; 9065 __le32 enables; 9066 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9067 __le16 dir_idx; 9068 __le16 dir_type; 9069 __le16 dir_ordinal; 9070 __le16 dir_ext; 9071 u8 opt_ordinal; 9072 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9073 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9074 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9075 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9076 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9077 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9078 u8 unused_0[3]; 9079 }; 9080 9081 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9082 struct hwrm_nvm_find_dir_entry_output { 9083 __le16 error_code; 9084 __le16 req_type; 9085 __le16 seq_id; 9086 __le16 resp_len; 9087 __le32 dir_item_length; 9088 __le32 dir_data_length; 9089 __le32 fw_ver; 9090 __le16 dir_ordinal; 9091 __le16 dir_idx; 9092 u8 unused_0[7]; 9093 u8 valid; 9094 }; 9095 9096 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9097 struct hwrm_nvm_erase_dir_entry_input { 9098 __le16 req_type; 9099 __le16 cmpl_ring; 9100 __le16 seq_id; 9101 __le16 target_id; 9102 __le64 resp_addr; 9103 __le16 dir_idx; 9104 u8 unused_0[6]; 9105 }; 9106 9107 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9108 struct hwrm_nvm_erase_dir_entry_output { 9109 __le16 error_code; 9110 __le16 req_type; 9111 __le16 seq_id; 9112 __le16 resp_len; 9113 u8 unused_0[7]; 9114 u8 valid; 9115 }; 9116 9117 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9118 struct hwrm_nvm_get_dev_info_input { 9119 __le16 req_type; 9120 __le16 cmpl_ring; 9121 __le16 seq_id; 9122 __le16 target_id; 9123 __le64 resp_addr; 9124 }; 9125 9126 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9127 struct hwrm_nvm_get_dev_info_output { 9128 __le16 error_code; 9129 __le16 req_type; 9130 __le16 seq_id; 9131 __le16 resp_len; 9132 __le16 manufacturer_id; 9133 __le16 device_id; 9134 __le32 sector_size; 9135 __le32 nvram_size; 9136 __le32 reserved_size; 9137 __le32 available_size; 9138 u8 nvm_cfg_ver_maj; 9139 u8 nvm_cfg_ver_min; 9140 u8 nvm_cfg_ver_upd; 9141 u8 flags; 9142 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9143 char pkg_name[16]; 9144 __le16 hwrm_fw_major; 9145 __le16 hwrm_fw_minor; 9146 __le16 hwrm_fw_build; 9147 __le16 hwrm_fw_patch; 9148 __le16 mgmt_fw_major; 9149 __le16 mgmt_fw_minor; 9150 __le16 mgmt_fw_build; 9151 __le16 mgmt_fw_patch; 9152 __le16 roce_fw_major; 9153 __le16 roce_fw_minor; 9154 __le16 roce_fw_build; 9155 __le16 roce_fw_patch; 9156 u8 unused_0[7]; 9157 u8 valid; 9158 }; 9159 9160 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9161 struct hwrm_nvm_mod_dir_entry_input { 9162 __le16 req_type; 9163 __le16 cmpl_ring; 9164 __le16 seq_id; 9165 __le16 target_id; 9166 __le64 resp_addr; 9167 __le32 enables; 9168 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9169 __le16 dir_idx; 9170 __le16 dir_ordinal; 9171 __le16 dir_ext; 9172 __le16 dir_attr; 9173 __le32 checksum; 9174 }; 9175 9176 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 9177 struct hwrm_nvm_mod_dir_entry_output { 9178 __le16 error_code; 9179 __le16 req_type; 9180 __le16 seq_id; 9181 __le16 resp_len; 9182 u8 unused_0[7]; 9183 u8 valid; 9184 }; 9185 9186 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 9187 struct hwrm_nvm_verify_update_input { 9188 __le16 req_type; 9189 __le16 cmpl_ring; 9190 __le16 seq_id; 9191 __le16 target_id; 9192 __le64 resp_addr; 9193 __le16 dir_type; 9194 __le16 dir_ordinal; 9195 __le16 dir_ext; 9196 u8 unused_0[2]; 9197 }; 9198 9199 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 9200 struct hwrm_nvm_verify_update_output { 9201 __le16 error_code; 9202 __le16 req_type; 9203 __le16 seq_id; 9204 __le16 resp_len; 9205 u8 unused_0[7]; 9206 u8 valid; 9207 }; 9208 9209 /* hwrm_nvm_install_update_input (size:192b/24B) */ 9210 struct hwrm_nvm_install_update_input { 9211 __le16 req_type; 9212 __le16 cmpl_ring; 9213 __le16 seq_id; 9214 __le16 target_id; 9215 __le64 resp_addr; 9216 __le32 install_type; 9217 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 9218 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 9219 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 9220 __le16 flags; 9221 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 9222 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 9223 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 9224 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 9225 u8 unused_0[2]; 9226 }; 9227 9228 /* hwrm_nvm_install_update_output (size:192b/24B) */ 9229 struct hwrm_nvm_install_update_output { 9230 __le16 error_code; 9231 __le16 req_type; 9232 __le16 seq_id; 9233 __le16 resp_len; 9234 __le64 installed_items; 9235 u8 result; 9236 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 9237 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 9238 u8 problem_item; 9239 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 9240 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 9241 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 9242 u8 reset_required; 9243 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 9244 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 9245 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 9246 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 9247 u8 unused_0[4]; 9248 u8 valid; 9249 }; 9250 9251 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 9252 struct hwrm_nvm_install_update_cmd_err { 9253 u8 code; 9254 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 9255 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9256 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 9257 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 9258 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 9259 u8 unused_0[7]; 9260 }; 9261 9262 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 9263 struct hwrm_nvm_get_variable_input { 9264 __le16 req_type; 9265 __le16 cmpl_ring; 9266 __le16 seq_id; 9267 __le16 target_id; 9268 __le64 resp_addr; 9269 __le64 dest_data_addr; 9270 __le16 data_len; 9271 __le16 option_num; 9272 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9273 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9274 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9275 __le16 dimensions; 9276 __le16 index_0; 9277 __le16 index_1; 9278 __le16 index_2; 9279 __le16 index_3; 9280 u8 flags; 9281 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 9282 u8 unused_0; 9283 }; 9284 9285 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 9286 struct hwrm_nvm_get_variable_output { 9287 __le16 error_code; 9288 __le16 req_type; 9289 __le16 seq_id; 9290 __le16 resp_len; 9291 __le16 data_len; 9292 __le16 option_num; 9293 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 9294 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 9295 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 9296 u8 unused_0[3]; 9297 u8 valid; 9298 }; 9299 9300 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 9301 struct hwrm_nvm_get_variable_cmd_err { 9302 u8 code; 9303 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9304 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9305 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9306 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 9307 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 9308 u8 unused_0[7]; 9309 }; 9310 9311 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 9312 struct hwrm_nvm_set_variable_input { 9313 __le16 req_type; 9314 __le16 cmpl_ring; 9315 __le16 seq_id; 9316 __le16 target_id; 9317 __le64 resp_addr; 9318 __le64 src_data_addr; 9319 __le16 data_len; 9320 __le16 option_num; 9321 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9322 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9323 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9324 __le16 dimensions; 9325 __le16 index_0; 9326 __le16 index_1; 9327 __le16 index_2; 9328 __le16 index_3; 9329 u8 flags; 9330 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 9331 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 9332 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 9333 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 9334 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 9335 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 9336 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 9337 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 9338 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 9339 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 9340 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 9341 u8 unused_0; 9342 }; 9343 9344 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 9345 struct hwrm_nvm_set_variable_output { 9346 __le16 error_code; 9347 __le16 req_type; 9348 __le16 seq_id; 9349 __le16 resp_len; 9350 u8 unused_0[7]; 9351 u8 valid; 9352 }; 9353 9354 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 9355 struct hwrm_nvm_set_variable_cmd_err { 9356 u8 code; 9357 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9358 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9359 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9360 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 9361 u8 unused_0[7]; 9362 }; 9363 9364 /* hwrm_selftest_qlist_input (size:128b/16B) */ 9365 struct hwrm_selftest_qlist_input { 9366 __le16 req_type; 9367 __le16 cmpl_ring; 9368 __le16 seq_id; 9369 __le16 target_id; 9370 __le64 resp_addr; 9371 }; 9372 9373 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 9374 struct hwrm_selftest_qlist_output { 9375 __le16 error_code; 9376 __le16 req_type; 9377 __le16 seq_id; 9378 __le16 resp_len; 9379 u8 num_tests; 9380 u8 available_tests; 9381 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 9382 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 9383 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 9384 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 9385 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 9386 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9387 u8 offline_tests; 9388 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 9389 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 9390 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 9391 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 9392 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 9393 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9394 u8 unused_0; 9395 __le16 test_timeout; 9396 u8 unused_1[2]; 9397 char test0_name[32]; 9398 char test1_name[32]; 9399 char test2_name[32]; 9400 char test3_name[32]; 9401 char test4_name[32]; 9402 char test5_name[32]; 9403 char test6_name[32]; 9404 char test7_name[32]; 9405 u8 eyescope_target_BER_support; 9406 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 9407 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 9408 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 9409 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 9410 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 9411 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 9412 u8 unused_2[6]; 9413 u8 valid; 9414 }; 9415 9416 /* hwrm_selftest_exec_input (size:192b/24B) */ 9417 struct hwrm_selftest_exec_input { 9418 __le16 req_type; 9419 __le16 cmpl_ring; 9420 __le16 seq_id; 9421 __le16 target_id; 9422 __le64 resp_addr; 9423 u8 flags; 9424 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 9425 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 9426 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 9427 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 9428 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 9429 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 9430 u8 unused_0[7]; 9431 }; 9432 9433 /* hwrm_selftest_exec_output (size:128b/16B) */ 9434 struct hwrm_selftest_exec_output { 9435 __le16 error_code; 9436 __le16 req_type; 9437 __le16 seq_id; 9438 __le16 resp_len; 9439 u8 requested_tests; 9440 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 9441 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 9442 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 9443 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 9444 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 9445 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 9446 u8 test_success; 9447 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 9448 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 9449 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 9450 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 9451 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 9452 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 9453 u8 unused_0[5]; 9454 u8 valid; 9455 }; 9456 9457 /* hwrm_selftest_irq_input (size:128b/16B) */ 9458 struct hwrm_selftest_irq_input { 9459 __le16 req_type; 9460 __le16 cmpl_ring; 9461 __le16 seq_id; 9462 __le16 target_id; 9463 __le64 resp_addr; 9464 }; 9465 9466 /* hwrm_selftest_irq_output (size:128b/16B) */ 9467 struct hwrm_selftest_irq_output { 9468 __le16 error_code; 9469 __le16 req_type; 9470 __le16 seq_id; 9471 __le16 resp_len; 9472 u8 unused_0[7]; 9473 u8 valid; 9474 }; 9475 9476 /* db_push_info (size:64b/8B) */ 9477 struct db_push_info { 9478 u32 push_size_push_index; 9479 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 9480 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 9481 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 9482 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 9483 u32 reserved32; 9484 }; 9485 9486 /* fw_status_reg (size:32b/4B) */ 9487 struct fw_status_reg { 9488 u32 fw_status; 9489 #define FW_STATUS_REG_CODE_MASK 0xffffUL 9490 #define FW_STATUS_REG_CODE_SFT 0 9491 #define FW_STATUS_REG_CODE_READY 0x8000UL 9492 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 9493 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 9494 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 9495 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 9496 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 9497 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 9498 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 9499 #define FW_STATUS_REG_RECOVERING 0x400000UL 9500 }; 9501 9502 /* hcomm_status (size:64b/8B) */ 9503 struct hcomm_status { 9504 u32 sig_ver; 9505 #define HCOMM_STATUS_VER_MASK 0xffUL 9506 #define HCOMM_STATUS_VER_SFT 0 9507 #define HCOMM_STATUS_VER_LATEST 0x1UL 9508 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 9509 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 9510 #define HCOMM_STATUS_SIGNATURE_SFT 8 9511 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 9512 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 9513 u32 fw_status_loc; 9514 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 9515 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 9516 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 9517 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 9518 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 9519 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 9520 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 9521 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 9522 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 9523 }; 9524 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 9525 9526 #endif /* _BNXT_HSI_H_ */ 9527