1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * DO NOT MODIFY!!! This file is automatically generated. 11 */ 12 13 #ifndef _BNXT_HSI_H_ 14 #define _BNXT_HSI_H_ 15 16 /* hwrm_cmd_hdr (size:128b/16B) */ 17 struct hwrm_cmd_hdr { 18 __le16 req_type; 19 __le16 cmpl_ring; 20 __le16 seq_id; 21 __le16 target_id; 22 __le64 resp_addr; 23 }; 24 25 /* hwrm_resp_hdr (size:64b/8B) */ 26 struct hwrm_resp_hdr { 27 __le16 error_code; 28 __le16 req_type; 29 __le16 seq_id; 30 __le16 resp_len; 31 }; 32 33 #define CMD_DISCR_TLV_ENCAP 0x8000UL 34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 35 36 37 #define TLV_TYPE_HWRM_REQUEST 0x1UL 38 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 39 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 40 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 41 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 42 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL 43 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 51 52 53 /* tlv (size:64b/8B) */ 54 struct tlv { 55 __le16 cmd_discr; 56 u8 reserved_8b; 57 u8 flags; 58 #define TLV_FLAGS_MORE 0x1UL 59 #define TLV_FLAGS_MORE_LAST 0x0UL 60 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 61 #define TLV_FLAGS_REQUIRED 0x2UL 62 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 63 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 64 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 65 __le16 tlv_type; 66 __le16 length; 67 }; 68 69 /* input (size:128b/16B) */ 70 struct input { 71 __le16 req_type; 72 __le16 cmpl_ring; 73 __le16 seq_id; 74 __le16 target_id; 75 __le64 resp_addr; 76 }; 77 78 /* output (size:64b/8B) */ 79 struct output { 80 __le16 error_code; 81 __le16 req_type; 82 __le16 seq_id; 83 __le16 resp_len; 84 }; 85 86 /* hwrm_short_input (size:128b/16B) */ 87 struct hwrm_short_input { 88 __le16 req_type; 89 __le16 signature; 90 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 91 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 92 __le16 unused_0; 93 __le16 size; 94 __le64 req_addr; 95 }; 96 97 /* cmd_nums (size:64b/8B) */ 98 struct cmd_nums { 99 __le16 req_type; 100 #define HWRM_VER_GET 0x0UL 101 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 102 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 103 #define HWRM_FUNC_VF_CFG 0xfUL 104 #define HWRM_RESERVED1 0x10UL 105 #define HWRM_FUNC_RESET 0x11UL 106 #define HWRM_FUNC_GETFID 0x12UL 107 #define HWRM_FUNC_VF_ALLOC 0x13UL 108 #define HWRM_FUNC_VF_FREE 0x14UL 109 #define HWRM_FUNC_QCAPS 0x15UL 110 #define HWRM_FUNC_QCFG 0x16UL 111 #define HWRM_FUNC_CFG 0x17UL 112 #define HWRM_FUNC_QSTATS 0x18UL 113 #define HWRM_FUNC_CLR_STATS 0x19UL 114 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 115 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 116 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 117 #define HWRM_FUNC_DRV_RGTR 0x1dUL 118 #define HWRM_FUNC_DRV_QVER 0x1eUL 119 #define HWRM_FUNC_BUF_RGTR 0x1fUL 120 #define HWRM_PORT_PHY_CFG 0x20UL 121 #define HWRM_PORT_MAC_CFG 0x21UL 122 #define HWRM_PORT_TS_QUERY 0x22UL 123 #define HWRM_PORT_QSTATS 0x23UL 124 #define HWRM_PORT_LPBK_QSTATS 0x24UL 125 #define HWRM_PORT_CLR_STATS 0x25UL 126 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 127 #define HWRM_PORT_PHY_QCFG 0x27UL 128 #define HWRM_PORT_MAC_QCFG 0x28UL 129 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 130 #define HWRM_PORT_PHY_QCAPS 0x2aUL 131 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 132 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 133 #define HWRM_PORT_LED_CFG 0x2dUL 134 #define HWRM_PORT_LED_QCFG 0x2eUL 135 #define HWRM_PORT_LED_QCAPS 0x2fUL 136 #define HWRM_QUEUE_QPORTCFG 0x30UL 137 #define HWRM_QUEUE_QCFG 0x31UL 138 #define HWRM_QUEUE_CFG 0x32UL 139 #define HWRM_FUNC_VLAN_CFG 0x33UL 140 #define HWRM_FUNC_VLAN_QCFG 0x34UL 141 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 142 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 143 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 144 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 145 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 146 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 147 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 148 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 149 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 150 #define HWRM_VNIC_ALLOC 0x40UL 151 #define HWRM_VNIC_FREE 0x41UL 152 #define HWRM_VNIC_CFG 0x42UL 153 #define HWRM_VNIC_QCFG 0x43UL 154 #define HWRM_VNIC_TPA_CFG 0x44UL 155 #define HWRM_VNIC_TPA_QCFG 0x45UL 156 #define HWRM_VNIC_RSS_CFG 0x46UL 157 #define HWRM_VNIC_RSS_QCFG 0x47UL 158 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 159 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 160 #define HWRM_VNIC_QCAPS 0x4aUL 161 #define HWRM_RING_ALLOC 0x50UL 162 #define HWRM_RING_FREE 0x51UL 163 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 164 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 165 #define HWRM_RING_AGGINT_QCAPS 0x54UL 166 #define HWRM_RING_RESET 0x5eUL 167 #define HWRM_RING_GRP_ALLOC 0x60UL 168 #define HWRM_RING_GRP_FREE 0x61UL 169 #define HWRM_RESERVED5 0x64UL 170 #define HWRM_RESERVED6 0x65UL 171 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 172 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 173 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 174 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 175 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 176 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 177 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 178 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 179 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 180 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 181 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 182 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 183 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 184 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 185 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 186 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 187 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 188 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 189 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 190 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 191 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 192 #define HWRM_STAT_CTX_ALLOC 0xb0UL 193 #define HWRM_STAT_CTX_FREE 0xb1UL 194 #define HWRM_STAT_CTX_QUERY 0xb2UL 195 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 196 #define HWRM_PORT_QSTATS_EXT 0xb4UL 197 #define HWRM_FW_RESET 0xc0UL 198 #define HWRM_FW_QSTATUS 0xc1UL 199 #define HWRM_FW_HEALTH_CHECK 0xc2UL 200 #define HWRM_FW_SYNC 0xc3UL 201 #define HWRM_FW_SET_TIME 0xc8UL 202 #define HWRM_FW_GET_TIME 0xc9UL 203 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 204 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 205 #define HWRM_FW_IPC_MAILBOX 0xccUL 206 #define HWRM_EXEC_FWD_RESP 0xd0UL 207 #define HWRM_REJECT_FWD_RESP 0xd1UL 208 #define HWRM_FWD_RESP 0xd2UL 209 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 210 #define HWRM_OEM_CMD 0xd4UL 211 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 212 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 213 #define HWRM_WOL_FILTER_FREE 0xf1UL 214 #define HWRM_WOL_FILTER_QCFG 0xf2UL 215 #define HWRM_WOL_REASON_QCFG 0xf3UL 216 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 217 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 218 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 219 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 220 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 221 #define HWRM_CFA_VFR_ALLOC 0xfdUL 222 #define HWRM_CFA_VFR_FREE 0xfeUL 223 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 224 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 225 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 226 #define HWRM_CFA_FLOW_ALLOC 0x103UL 227 #define HWRM_CFA_FLOW_FREE 0x104UL 228 #define HWRM_CFA_FLOW_FLUSH 0x105UL 229 #define HWRM_CFA_FLOW_STATS 0x106UL 230 #define HWRM_CFA_FLOW_INFO 0x107UL 231 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 232 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 233 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 234 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 235 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 236 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 237 #define HWRM_CFA_PAIR_FREE 0x10eUL 238 #define HWRM_CFA_PAIR_INFO 0x10fUL 239 #define HWRM_FW_IPC_MSG 0x110UL 240 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 241 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 242 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 243 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 244 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 245 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 246 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 247 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 248 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 249 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 250 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 251 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 252 #define HWRM_ENGINE_QG_QUERY 0x13dUL 253 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 254 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 255 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 256 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 257 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 258 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 259 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 260 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 261 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 262 #define HWRM_ENGINE_SG_QUERY 0x147UL 263 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 264 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 265 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 266 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 267 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 268 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 269 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 270 #define HWRM_ENGINE_STATS_QUERY 0x157UL 271 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 272 #define HWRM_ENGINE_RQ_FREE 0x15fUL 273 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 274 #define HWRM_ENGINE_CQ_FREE 0x161UL 275 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 276 #define HWRM_ENGINE_NQ_FREE 0x163UL 277 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 278 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 279 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 280 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 281 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 282 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 283 #define HWRM_FUNC_VF_BW_CFG 0x195UL 284 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 285 #define HWRM_SELFTEST_QLIST 0x200UL 286 #define HWRM_SELFTEST_EXEC 0x201UL 287 #define HWRM_SELFTEST_IRQ 0x202UL 288 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 289 #define HWRM_PCIE_QSTATS 0x204UL 290 #define HWRM_DBG_READ_DIRECT 0xff10UL 291 #define HWRM_DBG_READ_INDIRECT 0xff11UL 292 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 293 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 294 #define HWRM_DBG_DUMP 0xff14UL 295 #define HWRM_DBG_ERASE_NVM 0xff15UL 296 #define HWRM_DBG_CFG 0xff16UL 297 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 298 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 299 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 300 #define HWRM_DBG_FW_CLI 0xff1aUL 301 #define HWRM_DBG_I2C_CMD 0xff1bUL 302 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 303 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 304 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 305 #define HWRM_NVM_FLUSH 0xfff0UL 306 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 307 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 308 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 309 #define HWRM_NVM_MODIFY 0xfff4UL 310 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 311 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 312 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 313 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 314 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 315 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 316 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 317 #define HWRM_NVM_RAW_DUMP 0xfffcUL 318 #define HWRM_NVM_READ 0xfffdUL 319 #define HWRM_NVM_WRITE 0xfffeUL 320 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 321 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 322 __le16 unused_0[3]; 323 }; 324 325 /* ret_codes (size:64b/8B) */ 326 struct ret_codes { 327 __le16 error_code; 328 #define HWRM_ERR_CODE_SUCCESS 0x0UL 329 #define HWRM_ERR_CODE_FAIL 0x1UL 330 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 331 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 332 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 333 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 334 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 335 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 336 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 337 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 338 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 339 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 340 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 341 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 342 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 343 __le16 unused_0[3]; 344 }; 345 346 /* hwrm_err_output (size:128b/16B) */ 347 struct hwrm_err_output { 348 __le16 error_code; 349 __le16 req_type; 350 __le16 seq_id; 351 __le16 resp_len; 352 __le32 opaque_0; 353 __le16 opaque_1; 354 u8 cmd_err; 355 u8 valid; 356 }; 357 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 358 #define HWRM_MAX_REQ_LEN 128 359 #define HWRM_MAX_RESP_LEN 280 360 #define HW_HASH_INDEX_SIZE 0x80 361 #define HW_HASH_KEY_SIZE 40 362 #define HWRM_RESP_VALID_KEY 1 363 #define HWRM_VERSION_MAJOR 1 364 #define HWRM_VERSION_MINOR 10 365 #define HWRM_VERSION_UPDATE 0 366 #define HWRM_VERSION_RSVD 3 367 #define HWRM_VERSION_STR "1.10.0.3" 368 369 /* hwrm_ver_get_input (size:192b/24B) */ 370 struct hwrm_ver_get_input { 371 __le16 req_type; 372 __le16 cmpl_ring; 373 __le16 seq_id; 374 __le16 target_id; 375 __le64 resp_addr; 376 u8 hwrm_intf_maj; 377 u8 hwrm_intf_min; 378 u8 hwrm_intf_upd; 379 u8 unused_0[5]; 380 }; 381 382 /* hwrm_ver_get_output (size:1408b/176B) */ 383 struct hwrm_ver_get_output { 384 __le16 error_code; 385 __le16 req_type; 386 __le16 seq_id; 387 __le16 resp_len; 388 u8 hwrm_intf_maj_8b; 389 u8 hwrm_intf_min_8b; 390 u8 hwrm_intf_upd_8b; 391 u8 hwrm_intf_rsvd_8b; 392 u8 hwrm_fw_maj_8b; 393 u8 hwrm_fw_min_8b; 394 u8 hwrm_fw_bld_8b; 395 u8 hwrm_fw_rsvd_8b; 396 u8 mgmt_fw_maj_8b; 397 u8 mgmt_fw_min_8b; 398 u8 mgmt_fw_bld_8b; 399 u8 mgmt_fw_rsvd_8b; 400 u8 netctrl_fw_maj_8b; 401 u8 netctrl_fw_min_8b; 402 u8 netctrl_fw_bld_8b; 403 u8 netctrl_fw_rsvd_8b; 404 __le32 dev_caps_cfg; 405 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 406 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 407 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 408 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 409 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 410 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 411 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 412 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 413 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 414 u8 roce_fw_maj_8b; 415 u8 roce_fw_min_8b; 416 u8 roce_fw_bld_8b; 417 u8 roce_fw_rsvd_8b; 418 char hwrm_fw_name[16]; 419 char mgmt_fw_name[16]; 420 char netctrl_fw_name[16]; 421 u8 reserved2[16]; 422 char roce_fw_name[16]; 423 __le16 chip_num; 424 u8 chip_rev; 425 u8 chip_metal; 426 u8 chip_bond_id; 427 u8 chip_platform_type; 428 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 429 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 430 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 431 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 432 __le16 max_req_win_len; 433 __le16 max_resp_len; 434 __le16 def_req_timeout; 435 u8 flags; 436 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 437 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 438 u8 unused_0[2]; 439 u8 always_1; 440 __le16 hwrm_intf_major; 441 __le16 hwrm_intf_minor; 442 __le16 hwrm_intf_build; 443 __le16 hwrm_intf_patch; 444 __le16 hwrm_fw_major; 445 __le16 hwrm_fw_minor; 446 __le16 hwrm_fw_build; 447 __le16 hwrm_fw_patch; 448 __le16 mgmt_fw_major; 449 __le16 mgmt_fw_minor; 450 __le16 mgmt_fw_build; 451 __le16 mgmt_fw_patch; 452 __le16 netctrl_fw_major; 453 __le16 netctrl_fw_minor; 454 __le16 netctrl_fw_build; 455 __le16 netctrl_fw_patch; 456 __le16 roce_fw_major; 457 __le16 roce_fw_minor; 458 __le16 roce_fw_build; 459 __le16 roce_fw_patch; 460 __le16 max_ext_req_len; 461 u8 unused_1[5]; 462 u8 valid; 463 }; 464 465 /* eject_cmpl (size:128b/16B) */ 466 struct eject_cmpl { 467 __le16 type; 468 #define EJECT_CMPL_TYPE_MASK 0x3fUL 469 #define EJECT_CMPL_TYPE_SFT 0 470 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 471 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 472 __le16 len; 473 __le32 opaque; 474 __le32 v; 475 #define EJECT_CMPL_V 0x1UL 476 __le32 unused_2; 477 }; 478 479 /* hwrm_cmpl (size:128b/16B) */ 480 struct hwrm_cmpl { 481 __le16 type; 482 #define CMPL_TYPE_MASK 0x3fUL 483 #define CMPL_TYPE_SFT 0 484 #define CMPL_TYPE_HWRM_DONE 0x20UL 485 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 486 __le16 sequence_id; 487 __le32 unused_1; 488 __le32 v; 489 #define CMPL_V 0x1UL 490 __le32 unused_3; 491 }; 492 493 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 494 struct hwrm_fwd_req_cmpl { 495 __le16 req_len_type; 496 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 497 #define FWD_REQ_CMPL_TYPE_SFT 0 498 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 499 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 500 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 501 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 502 __le16 source_id; 503 __le32 unused0; 504 __le32 req_buf_addr_v[2]; 505 #define FWD_REQ_CMPL_V 0x1UL 506 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 507 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 508 }; 509 510 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 511 struct hwrm_fwd_resp_cmpl { 512 __le16 type; 513 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 514 #define FWD_RESP_CMPL_TYPE_SFT 0 515 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 516 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 517 __le16 source_id; 518 __le16 resp_len; 519 __le16 unused_1; 520 __le32 resp_buf_addr_v[2]; 521 #define FWD_RESP_CMPL_V 0x1UL 522 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 523 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 524 }; 525 526 /* hwrm_async_event_cmpl (size:128b/16B) */ 527 struct hwrm_async_event_cmpl { 528 __le16 type; 529 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 530 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 531 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 532 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 533 __le16 event_id; 534 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 535 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 536 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 537 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 538 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 539 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 540 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 541 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 542 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 543 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 544 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 545 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 546 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 547 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 548 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 549 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 550 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 551 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 552 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 553 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 554 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 555 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 556 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 557 __le32 event_data2; 558 u8 opaque_v; 559 #define ASYNC_EVENT_CMPL_V 0x1UL 560 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 561 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 562 u8 timestamp_lo; 563 __le16 timestamp_hi; 564 __le32 event_data1; 565 }; 566 567 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 568 struct hwrm_async_event_cmpl_link_status_change { 569 __le16 type; 570 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 571 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 572 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 573 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 574 __le16 event_id; 575 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 576 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 577 __le32 event_data2; 578 u8 opaque_v; 579 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 580 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 581 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 582 u8 timestamp_lo; 583 __le16 timestamp_hi; 584 __le32 event_data1; 585 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 586 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 587 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 588 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 589 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 590 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 591 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 592 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 593 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 594 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 595 }; 596 597 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 598 struct hwrm_async_event_cmpl_port_conn_not_allowed { 599 __le16 type; 600 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 601 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 602 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 603 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 604 __le16 event_id; 605 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 606 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 607 __le32 event_data2; 608 u8 opaque_v; 609 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 610 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 611 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 612 u8 timestamp_lo; 613 __le16 timestamp_hi; 614 __le32 event_data1; 615 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 616 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 617 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 618 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 619 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 620 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 621 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 622 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 623 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 624 }; 625 626 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 627 struct hwrm_async_event_cmpl_link_speed_cfg_change { 628 __le16 type; 629 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 630 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 631 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 632 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 633 __le16 event_id; 634 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 635 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 636 __le32 event_data2; 637 u8 opaque_v; 638 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 639 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 640 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 641 u8 timestamp_lo; 642 __le16 timestamp_hi; 643 __le32 event_data1; 644 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 645 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 646 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 647 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 648 }; 649 650 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 651 struct hwrm_async_event_cmpl_vf_cfg_change { 652 __le16 type; 653 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 654 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 655 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 656 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 657 __le16 event_id; 658 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 659 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 660 __le32 event_data2; 661 u8 opaque_v; 662 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 663 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 664 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 665 u8 timestamp_lo; 666 __le16 timestamp_hi; 667 __le32 event_data1; 668 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 669 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 670 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 671 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 672 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 673 }; 674 675 /* hwrm_func_reset_input (size:192b/24B) */ 676 struct hwrm_func_reset_input { 677 __le16 req_type; 678 __le16 cmpl_ring; 679 __le16 seq_id; 680 __le16 target_id; 681 __le64 resp_addr; 682 __le32 enables; 683 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 684 __le16 vf_id; 685 u8 func_reset_level; 686 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 687 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 688 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 689 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 690 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 691 u8 unused_0; 692 }; 693 694 /* hwrm_func_reset_output (size:128b/16B) */ 695 struct hwrm_func_reset_output { 696 __le16 error_code; 697 __le16 req_type; 698 __le16 seq_id; 699 __le16 resp_len; 700 u8 unused_0[7]; 701 u8 valid; 702 }; 703 704 /* hwrm_func_getfid_input (size:192b/24B) */ 705 struct hwrm_func_getfid_input { 706 __le16 req_type; 707 __le16 cmpl_ring; 708 __le16 seq_id; 709 __le16 target_id; 710 __le64 resp_addr; 711 __le32 enables; 712 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 713 __le16 pci_id; 714 u8 unused_0[2]; 715 }; 716 717 /* hwrm_func_getfid_output (size:128b/16B) */ 718 struct hwrm_func_getfid_output { 719 __le16 error_code; 720 __le16 req_type; 721 __le16 seq_id; 722 __le16 resp_len; 723 __le16 fid; 724 u8 unused_0[5]; 725 u8 valid; 726 }; 727 728 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 729 struct hwrm_func_vf_alloc_input { 730 __le16 req_type; 731 __le16 cmpl_ring; 732 __le16 seq_id; 733 __le16 target_id; 734 __le64 resp_addr; 735 __le32 enables; 736 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 737 __le16 first_vf_id; 738 __le16 num_vfs; 739 }; 740 741 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 742 struct hwrm_func_vf_alloc_output { 743 __le16 error_code; 744 __le16 req_type; 745 __le16 seq_id; 746 __le16 resp_len; 747 __le16 first_vf_id; 748 u8 unused_0[5]; 749 u8 valid; 750 }; 751 752 /* hwrm_func_vf_free_input (size:192b/24B) */ 753 struct hwrm_func_vf_free_input { 754 __le16 req_type; 755 __le16 cmpl_ring; 756 __le16 seq_id; 757 __le16 target_id; 758 __le64 resp_addr; 759 __le32 enables; 760 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 761 __le16 first_vf_id; 762 __le16 num_vfs; 763 }; 764 765 /* hwrm_func_vf_free_output (size:128b/16B) */ 766 struct hwrm_func_vf_free_output { 767 __le16 error_code; 768 __le16 req_type; 769 __le16 seq_id; 770 __le16 resp_len; 771 u8 unused_0[7]; 772 u8 valid; 773 }; 774 775 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 776 struct hwrm_func_vf_cfg_input { 777 __le16 req_type; 778 __le16 cmpl_ring; 779 __le16 seq_id; 780 __le16 target_id; 781 __le64 resp_addr; 782 __le32 enables; 783 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 784 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 785 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 786 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 787 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 788 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 789 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 790 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 791 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 792 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 793 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 794 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 795 __le16 mtu; 796 __le16 guest_vlan; 797 __le16 async_event_cr; 798 u8 dflt_mac_addr[6]; 799 __le32 flags; 800 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 801 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 802 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 803 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 804 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 805 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 806 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 807 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 808 __le16 num_rsscos_ctxs; 809 __le16 num_cmpl_rings; 810 __le16 num_tx_rings; 811 __le16 num_rx_rings; 812 __le16 num_l2_ctxs; 813 __le16 num_vnics; 814 __le16 num_stat_ctxs; 815 __le16 num_hw_ring_grps; 816 u8 unused_0[4]; 817 }; 818 819 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 820 struct hwrm_func_vf_cfg_output { 821 __le16 error_code; 822 __le16 req_type; 823 __le16 seq_id; 824 __le16 resp_len; 825 u8 unused_0[7]; 826 u8 valid; 827 }; 828 829 /* hwrm_func_qcaps_input (size:192b/24B) */ 830 struct hwrm_func_qcaps_input { 831 __le16 req_type; 832 __le16 cmpl_ring; 833 __le16 seq_id; 834 __le16 target_id; 835 __le64 resp_addr; 836 __le16 fid; 837 u8 unused_0[6]; 838 }; 839 840 /* hwrm_func_qcaps_output (size:640b/80B) */ 841 struct hwrm_func_qcaps_output { 842 __le16 error_code; 843 __le16 req_type; 844 __le16 seq_id; 845 __le16 resp_len; 846 __le16 fid; 847 __le16 port_id; 848 __le32 flags; 849 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 850 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 851 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 852 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 853 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 854 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 855 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 856 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 857 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 858 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 859 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 860 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 861 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 862 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 863 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 864 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 865 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 866 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 867 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 868 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 869 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 870 u8 mac_address[6]; 871 __le16 max_rsscos_ctx; 872 __le16 max_cmpl_rings; 873 __le16 max_tx_rings; 874 __le16 max_rx_rings; 875 __le16 max_l2_ctxs; 876 __le16 max_vnics; 877 __le16 first_vf_id; 878 __le16 max_vfs; 879 __le16 max_stat_ctx; 880 __le32 max_encap_records; 881 __le32 max_decap_records; 882 __le32 max_tx_em_flows; 883 __le32 max_tx_wm_flows; 884 __le32 max_rx_em_flows; 885 __le32 max_rx_wm_flows; 886 __le32 max_mcast_filters; 887 __le32 max_flow_id; 888 __le32 max_hw_ring_grps; 889 __le16 max_sp_tx_rings; 890 u8 unused_0; 891 u8 valid; 892 }; 893 894 /* hwrm_func_qcfg_input (size:192b/24B) */ 895 struct hwrm_func_qcfg_input { 896 __le16 req_type; 897 __le16 cmpl_ring; 898 __le16 seq_id; 899 __le16 target_id; 900 __le64 resp_addr; 901 __le16 fid; 902 u8 unused_0[6]; 903 }; 904 905 /* hwrm_func_qcfg_output (size:640b/80B) */ 906 struct hwrm_func_qcfg_output { 907 __le16 error_code; 908 __le16 req_type; 909 __le16 seq_id; 910 __le16 resp_len; 911 __le16 fid; 912 __le16 port_id; 913 __le16 vlan; 914 __le16 flags; 915 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 916 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 917 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 918 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 919 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 920 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 921 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 922 u8 mac_address[6]; 923 __le16 pci_id; 924 __le16 alloc_rsscos_ctx; 925 __le16 alloc_cmpl_rings; 926 __le16 alloc_tx_rings; 927 __le16 alloc_rx_rings; 928 __le16 alloc_l2_ctx; 929 __le16 alloc_vnics; 930 __le16 mtu; 931 __le16 mru; 932 __le16 stat_ctx_id; 933 u8 port_partition_type; 934 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 935 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 936 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 937 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 938 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 939 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 940 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 941 u8 port_pf_cnt; 942 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 943 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 944 __le16 dflt_vnic_id; 945 __le16 max_mtu_configured; 946 __le32 min_bw; 947 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 948 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 949 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 950 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 951 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 952 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 953 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 954 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 955 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 956 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 957 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 958 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 959 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 960 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 961 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 962 __le32 max_bw; 963 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 964 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 965 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 966 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 967 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 968 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 969 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 970 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 971 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 972 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 973 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 974 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 975 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 976 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 977 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 978 u8 evb_mode; 979 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 980 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 981 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 982 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 983 u8 options; 984 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 985 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 986 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 987 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 988 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 989 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 990 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 991 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 992 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 993 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 994 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 995 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 996 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 997 __le16 alloc_vfs; 998 __le32 alloc_mcast_filters; 999 __le32 alloc_hw_ring_grps; 1000 __le16 alloc_sp_tx_rings; 1001 __le16 alloc_stat_ctx; 1002 __le16 alloc_msix; 1003 u8 unused_2[5]; 1004 u8 valid; 1005 }; 1006 1007 /* hwrm_func_cfg_input (size:704b/88B) */ 1008 struct hwrm_func_cfg_input { 1009 __le16 req_type; 1010 __le16 cmpl_ring; 1011 __le16 seq_id; 1012 __le16 target_id; 1013 __le64 resp_addr; 1014 __le16 fid; 1015 __le16 num_msix; 1016 __le32 flags; 1017 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1018 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1019 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1020 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1021 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1022 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1023 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1024 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1025 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1026 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1027 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1028 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1029 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1030 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1031 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1032 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1033 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1034 __le32 enables; 1035 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1036 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1037 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1038 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1039 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1040 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1041 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1042 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1043 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1044 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1045 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1046 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1047 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1048 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1049 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1050 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1051 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1052 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1053 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1054 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1055 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1056 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1057 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1058 __le16 mtu; 1059 __le16 mru; 1060 __le16 num_rsscos_ctxs; 1061 __le16 num_cmpl_rings; 1062 __le16 num_tx_rings; 1063 __le16 num_rx_rings; 1064 __le16 num_l2_ctxs; 1065 __le16 num_vnics; 1066 __le16 num_stat_ctxs; 1067 __le16 num_hw_ring_grps; 1068 u8 dflt_mac_addr[6]; 1069 __le16 dflt_vlan; 1070 __be32 dflt_ip_addr[4]; 1071 __le32 min_bw; 1072 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1073 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1074 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1075 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1076 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1077 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1078 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1079 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1080 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1081 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1082 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1083 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1084 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1085 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1086 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1087 __le32 max_bw; 1088 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1089 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1090 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1091 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1092 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1093 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1094 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1095 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1096 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1097 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1098 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1099 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1100 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1101 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1102 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1103 __le16 async_event_cr; 1104 u8 vlan_antispoof_mode; 1105 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1106 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1107 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1108 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1109 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1110 u8 allowed_vlan_pris; 1111 u8 evb_mode; 1112 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1113 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1114 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1115 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1116 u8 options; 1117 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1118 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1119 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1120 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1121 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1122 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1123 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1124 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1125 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1126 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1127 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1128 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1129 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1130 __le16 num_mcast_filters; 1131 }; 1132 1133 /* hwrm_func_cfg_output (size:128b/16B) */ 1134 struct hwrm_func_cfg_output { 1135 __le16 error_code; 1136 __le16 req_type; 1137 __le16 seq_id; 1138 __le16 resp_len; 1139 u8 unused_0[7]; 1140 u8 valid; 1141 }; 1142 1143 /* hwrm_func_qstats_input (size:192b/24B) */ 1144 struct hwrm_func_qstats_input { 1145 __le16 req_type; 1146 __le16 cmpl_ring; 1147 __le16 seq_id; 1148 __le16 target_id; 1149 __le64 resp_addr; 1150 __le16 fid; 1151 u8 unused_0[6]; 1152 }; 1153 1154 /* hwrm_func_qstats_output (size:1408b/176B) */ 1155 struct hwrm_func_qstats_output { 1156 __le16 error_code; 1157 __le16 req_type; 1158 __le16 seq_id; 1159 __le16 resp_len; 1160 __le64 tx_ucast_pkts; 1161 __le64 tx_mcast_pkts; 1162 __le64 tx_bcast_pkts; 1163 __le64 tx_discard_pkts; 1164 __le64 tx_drop_pkts; 1165 __le64 tx_ucast_bytes; 1166 __le64 tx_mcast_bytes; 1167 __le64 tx_bcast_bytes; 1168 __le64 rx_ucast_pkts; 1169 __le64 rx_mcast_pkts; 1170 __le64 rx_bcast_pkts; 1171 __le64 rx_discard_pkts; 1172 __le64 rx_drop_pkts; 1173 __le64 rx_ucast_bytes; 1174 __le64 rx_mcast_bytes; 1175 __le64 rx_bcast_bytes; 1176 __le64 rx_agg_pkts; 1177 __le64 rx_agg_bytes; 1178 __le64 rx_agg_events; 1179 __le64 rx_agg_aborts; 1180 u8 unused_0[7]; 1181 u8 valid; 1182 }; 1183 1184 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1185 struct hwrm_func_clr_stats_input { 1186 __le16 req_type; 1187 __le16 cmpl_ring; 1188 __le16 seq_id; 1189 __le16 target_id; 1190 __le64 resp_addr; 1191 __le16 fid; 1192 u8 unused_0[6]; 1193 }; 1194 1195 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1196 struct hwrm_func_clr_stats_output { 1197 __le16 error_code; 1198 __le16 req_type; 1199 __le16 seq_id; 1200 __le16 resp_len; 1201 u8 unused_0[7]; 1202 u8 valid; 1203 }; 1204 1205 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1206 struct hwrm_func_vf_resc_free_input { 1207 __le16 req_type; 1208 __le16 cmpl_ring; 1209 __le16 seq_id; 1210 __le16 target_id; 1211 __le64 resp_addr; 1212 __le16 vf_id; 1213 u8 unused_0[6]; 1214 }; 1215 1216 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1217 struct hwrm_func_vf_resc_free_output { 1218 __le16 error_code; 1219 __le16 req_type; 1220 __le16 seq_id; 1221 __le16 resp_len; 1222 u8 unused_0[7]; 1223 u8 valid; 1224 }; 1225 1226 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1227 struct hwrm_func_drv_rgtr_input { 1228 __le16 req_type; 1229 __le16 cmpl_ring; 1230 __le16 seq_id; 1231 __le16 target_id; 1232 __le64 resp_addr; 1233 __le32 flags; 1234 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1235 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1236 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1237 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1238 __le32 enables; 1239 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1240 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1241 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1242 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1243 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1244 __le16 os_type; 1245 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1246 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1247 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1248 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1249 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1250 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1251 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1252 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1253 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1254 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1255 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1256 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1257 u8 ver_maj_8b; 1258 u8 ver_min_8b; 1259 u8 ver_upd_8b; 1260 u8 unused_0[3]; 1261 __le32 timestamp; 1262 u8 unused_1[4]; 1263 __le32 vf_req_fwd[8]; 1264 __le32 async_event_fwd[8]; 1265 __le16 ver_maj; 1266 __le16 ver_min; 1267 __le16 ver_upd; 1268 __le16 ver_patch; 1269 }; 1270 1271 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1272 struct hwrm_func_drv_rgtr_output { 1273 __le16 error_code; 1274 __le16 req_type; 1275 __le16 seq_id; 1276 __le16 resp_len; 1277 __le32 flags; 1278 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1279 u8 unused_0[3]; 1280 u8 valid; 1281 }; 1282 1283 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1284 struct hwrm_func_drv_unrgtr_input { 1285 __le16 req_type; 1286 __le16 cmpl_ring; 1287 __le16 seq_id; 1288 __le16 target_id; 1289 __le64 resp_addr; 1290 __le32 flags; 1291 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1292 u8 unused_0[4]; 1293 }; 1294 1295 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1296 struct hwrm_func_drv_unrgtr_output { 1297 __le16 error_code; 1298 __le16 req_type; 1299 __le16 seq_id; 1300 __le16 resp_len; 1301 u8 unused_0[7]; 1302 u8 valid; 1303 }; 1304 1305 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1306 struct hwrm_func_buf_rgtr_input { 1307 __le16 req_type; 1308 __le16 cmpl_ring; 1309 __le16 seq_id; 1310 __le16 target_id; 1311 __le64 resp_addr; 1312 __le32 enables; 1313 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1314 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1315 __le16 vf_id; 1316 __le16 req_buf_num_pages; 1317 __le16 req_buf_page_size; 1318 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1319 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1320 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1321 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1322 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1323 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1324 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1325 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1326 __le16 req_buf_len; 1327 __le16 resp_buf_len; 1328 u8 unused_0[2]; 1329 __le64 req_buf_page_addr0; 1330 __le64 req_buf_page_addr1; 1331 __le64 req_buf_page_addr2; 1332 __le64 req_buf_page_addr3; 1333 __le64 req_buf_page_addr4; 1334 __le64 req_buf_page_addr5; 1335 __le64 req_buf_page_addr6; 1336 __le64 req_buf_page_addr7; 1337 __le64 req_buf_page_addr8; 1338 __le64 req_buf_page_addr9; 1339 __le64 error_buf_addr; 1340 __le64 resp_buf_addr; 1341 }; 1342 1343 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1344 struct hwrm_func_buf_rgtr_output { 1345 __le16 error_code; 1346 __le16 req_type; 1347 __le16 seq_id; 1348 __le16 resp_len; 1349 u8 unused_0[7]; 1350 u8 valid; 1351 }; 1352 1353 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1354 struct hwrm_func_drv_qver_input { 1355 __le16 req_type; 1356 __le16 cmpl_ring; 1357 __le16 seq_id; 1358 __le16 target_id; 1359 __le64 resp_addr; 1360 __le32 reserved; 1361 __le16 fid; 1362 u8 unused_0[2]; 1363 }; 1364 1365 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1366 struct hwrm_func_drv_qver_output { 1367 __le16 error_code; 1368 __le16 req_type; 1369 __le16 seq_id; 1370 __le16 resp_len; 1371 __le16 os_type; 1372 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1373 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1374 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1375 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1376 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1377 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1378 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1379 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1380 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1381 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1382 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1383 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1384 u8 ver_maj_8b; 1385 u8 ver_min_8b; 1386 u8 ver_upd_8b; 1387 u8 unused_0[3]; 1388 __le16 ver_maj; 1389 __le16 ver_min; 1390 __le16 ver_upd; 1391 __le16 ver_patch; 1392 u8 unused_1[7]; 1393 u8 valid; 1394 }; 1395 1396 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1397 struct hwrm_func_resource_qcaps_input { 1398 __le16 req_type; 1399 __le16 cmpl_ring; 1400 __le16 seq_id; 1401 __le16 target_id; 1402 __le64 resp_addr; 1403 __le16 fid; 1404 u8 unused_0[6]; 1405 }; 1406 1407 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1408 struct hwrm_func_resource_qcaps_output { 1409 __le16 error_code; 1410 __le16 req_type; 1411 __le16 seq_id; 1412 __le16 resp_len; 1413 __le16 max_vfs; 1414 __le16 max_msix; 1415 __le16 vf_reservation_strategy; 1416 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1417 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1418 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1419 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1420 __le16 min_rsscos_ctx; 1421 __le16 max_rsscos_ctx; 1422 __le16 min_cmpl_rings; 1423 __le16 max_cmpl_rings; 1424 __le16 min_tx_rings; 1425 __le16 max_tx_rings; 1426 __le16 min_rx_rings; 1427 __le16 max_rx_rings; 1428 __le16 min_l2_ctxs; 1429 __le16 max_l2_ctxs; 1430 __le16 min_vnics; 1431 __le16 max_vnics; 1432 __le16 min_stat_ctx; 1433 __le16 max_stat_ctx; 1434 __le16 min_hw_ring_grps; 1435 __le16 max_hw_ring_grps; 1436 __le16 max_tx_scheduler_inputs; 1437 __le16 flags; 1438 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1439 u8 unused_0[5]; 1440 u8 valid; 1441 }; 1442 1443 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1444 struct hwrm_func_vf_resource_cfg_input { 1445 __le16 req_type; 1446 __le16 cmpl_ring; 1447 __le16 seq_id; 1448 __le16 target_id; 1449 __le64 resp_addr; 1450 __le16 vf_id; 1451 __le16 max_msix; 1452 __le16 min_rsscos_ctx; 1453 __le16 max_rsscos_ctx; 1454 __le16 min_cmpl_rings; 1455 __le16 max_cmpl_rings; 1456 __le16 min_tx_rings; 1457 __le16 max_tx_rings; 1458 __le16 min_rx_rings; 1459 __le16 max_rx_rings; 1460 __le16 min_l2_ctxs; 1461 __le16 max_l2_ctxs; 1462 __le16 min_vnics; 1463 __le16 max_vnics; 1464 __le16 min_stat_ctx; 1465 __le16 max_stat_ctx; 1466 __le16 min_hw_ring_grps; 1467 __le16 max_hw_ring_grps; 1468 __le16 flags; 1469 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1470 u8 unused_0[2]; 1471 }; 1472 1473 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1474 struct hwrm_func_vf_resource_cfg_output { 1475 __le16 error_code; 1476 __le16 req_type; 1477 __le16 seq_id; 1478 __le16 resp_len; 1479 __le16 reserved_rsscos_ctx; 1480 __le16 reserved_cmpl_rings; 1481 __le16 reserved_tx_rings; 1482 __le16 reserved_rx_rings; 1483 __le16 reserved_l2_ctxs; 1484 __le16 reserved_vnics; 1485 __le16 reserved_stat_ctx; 1486 __le16 reserved_hw_ring_grps; 1487 u8 unused_0[7]; 1488 u8 valid; 1489 }; 1490 1491 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1492 struct hwrm_func_backing_store_qcaps_input { 1493 __le16 req_type; 1494 __le16 cmpl_ring; 1495 __le16 seq_id; 1496 __le16 target_id; 1497 __le64 resp_addr; 1498 }; 1499 1500 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ 1501 struct hwrm_func_backing_store_qcaps_output { 1502 __le16 error_code; 1503 __le16 req_type; 1504 __le16 seq_id; 1505 __le16 resp_len; 1506 __le32 qp_max_entries; 1507 __le16 qp_min_qp1_entries; 1508 __le16 qp_max_l2_entries; 1509 __le16 qp_entry_size; 1510 __le16 srq_max_l2_entries; 1511 __le32 srq_max_entries; 1512 __le16 srq_entry_size; 1513 __le16 cq_max_l2_entries; 1514 __le32 cq_max_entries; 1515 __le16 cq_entry_size; 1516 __le16 vnic_max_vnic_entries; 1517 __le16 vnic_max_ring_table_entries; 1518 __le16 vnic_entry_size; 1519 __le32 stat_max_entries; 1520 __le16 stat_entry_size; 1521 __le16 tqm_entry_size; 1522 __le32 tqm_min_entries_per_ring; 1523 __le32 tqm_max_entries_per_ring; 1524 __le32 mrav_max_entries; 1525 __le16 mrav_entry_size; 1526 __le16 tim_entry_size; 1527 __le32 tim_max_entries; 1528 u8 unused_0[2]; 1529 u8 tqm_entries_multiple; 1530 u8 valid; 1531 }; 1532 1533 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1534 struct hwrm_func_backing_store_cfg_input { 1535 __le16 req_type; 1536 __le16 cmpl_ring; 1537 __le16 seq_id; 1538 __le16 target_id; 1539 __le64 resp_addr; 1540 __le32 flags; 1541 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1542 __le32 enables; 1543 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1544 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1545 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1546 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1547 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1548 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1549 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1550 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1551 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1552 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1553 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1554 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1555 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1556 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1557 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1558 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1559 u8 qpc_pg_size_qpc_lvl; 1560 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1561 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1562 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1563 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1564 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1565 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1566 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1567 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1568 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1569 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1570 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1571 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1572 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1573 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1574 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1575 u8 srq_pg_size_srq_lvl; 1576 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1577 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1578 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1579 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1580 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1581 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1582 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 1583 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 1584 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1585 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1586 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1587 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1588 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1589 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1590 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 1591 u8 cq_pg_size_cq_lvl; 1592 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 1593 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 1594 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 1595 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 1596 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 1597 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 1598 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 1599 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 1600 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1601 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1602 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1603 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1604 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1605 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1606 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 1607 u8 vnic_pg_size_vnic_lvl; 1608 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 1609 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 1610 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 1611 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 1612 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 1613 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 1614 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 1615 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 1616 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 1617 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 1618 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 1619 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 1620 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 1621 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 1622 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 1623 u8 stat_pg_size_stat_lvl; 1624 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 1625 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 1626 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 1627 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 1628 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 1629 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 1630 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 1631 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 1632 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 1633 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 1634 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 1635 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 1636 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 1637 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 1638 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 1639 u8 tqm_sp_pg_size_tqm_sp_lvl; 1640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 1641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 1642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 1643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 1644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 1645 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 1646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 1647 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 1648 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 1649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 1650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 1651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 1652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 1653 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 1654 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 1655 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 1656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 1657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 1658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 1659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 1660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 1661 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 1662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 1663 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 1664 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 1665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 1666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 1667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 1668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 1669 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 1670 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 1671 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 1672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 1673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 1674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 1675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 1676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 1677 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 1678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 1679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 1680 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 1681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 1682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 1683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 1684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 1685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 1686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 1687 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 1688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 1689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 1690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 1691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 1692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 1693 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 1694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 1695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 1696 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 1697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 1698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 1699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 1700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 1701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 1702 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 1703 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 1704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 1705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 1706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 1707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 1708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 1709 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 1710 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 1711 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 1712 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 1713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 1714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 1715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 1716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 1717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 1718 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 1719 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 1720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 1721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 1722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 1723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 1724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 1725 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 1726 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 1727 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 1728 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 1729 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 1730 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 1731 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 1732 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 1733 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 1734 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 1735 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 1736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 1737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 1738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 1739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 1740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 1741 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 1742 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 1743 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 1744 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 1745 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 1746 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 1747 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 1748 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 1749 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 1750 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 1751 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 1752 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 1753 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 1754 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 1755 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 1756 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 1757 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 1758 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 1759 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 1760 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 1761 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 1762 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 1763 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 1764 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 1765 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 1766 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 1767 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 1768 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 1769 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 1770 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 1771 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 1772 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 1773 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 1774 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 1775 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 1776 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 1777 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 1778 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 1779 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 1780 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 1781 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 1782 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 1783 u8 mrav_pg_size_mrav_lvl; 1784 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 1785 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 1786 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 1787 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 1788 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 1789 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 1790 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 1791 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 1792 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 1793 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 1794 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 1795 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 1796 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 1797 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 1798 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 1799 u8 tim_pg_size_tim_lvl; 1800 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 1801 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 1802 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 1803 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 1804 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 1805 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 1806 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 1807 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 1808 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 1809 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 1810 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 1811 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 1812 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 1813 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 1814 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 1815 __le64 qpc_page_dir; 1816 __le64 srq_page_dir; 1817 __le64 cq_page_dir; 1818 __le64 vnic_page_dir; 1819 __le64 stat_page_dir; 1820 __le64 tqm_sp_page_dir; 1821 __le64 tqm_ring0_page_dir; 1822 __le64 tqm_ring1_page_dir; 1823 __le64 tqm_ring2_page_dir; 1824 __le64 tqm_ring3_page_dir; 1825 __le64 tqm_ring4_page_dir; 1826 __le64 tqm_ring5_page_dir; 1827 __le64 tqm_ring6_page_dir; 1828 __le64 tqm_ring7_page_dir; 1829 __le64 mrav_page_dir; 1830 __le64 tim_page_dir; 1831 __le32 qp_num_entries; 1832 __le32 srq_num_entries; 1833 __le32 cq_num_entries; 1834 __le32 stat_num_entries; 1835 __le32 tqm_sp_num_entries; 1836 __le32 tqm_ring0_num_entries; 1837 __le32 tqm_ring1_num_entries; 1838 __le32 tqm_ring2_num_entries; 1839 __le32 tqm_ring3_num_entries; 1840 __le32 tqm_ring4_num_entries; 1841 __le32 tqm_ring5_num_entries; 1842 __le32 tqm_ring6_num_entries; 1843 __le32 tqm_ring7_num_entries; 1844 __le32 mrav_num_entries; 1845 __le32 tim_num_entries; 1846 __le16 qp_num_qp1_entries; 1847 __le16 qp_num_l2_entries; 1848 __le16 qp_entry_size; 1849 __le16 srq_num_l2_entries; 1850 __le16 srq_entry_size; 1851 __le16 cq_num_l2_entries; 1852 __le16 cq_entry_size; 1853 __le16 vnic_num_vnic_entries; 1854 __le16 vnic_num_ring_table_entries; 1855 __le16 vnic_entry_size; 1856 __le16 stat_entry_size; 1857 __le16 tqm_entry_size; 1858 __le16 mrav_entry_size; 1859 __le16 tim_entry_size; 1860 }; 1861 1862 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 1863 struct hwrm_func_backing_store_cfg_output { 1864 __le16 error_code; 1865 __le16 req_type; 1866 __le16 seq_id; 1867 __le16 resp_len; 1868 u8 unused_0[7]; 1869 u8 valid; 1870 }; 1871 1872 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 1873 struct hwrm_func_drv_if_change_input { 1874 __le16 req_type; 1875 __le16 cmpl_ring; 1876 __le16 seq_id; 1877 __le16 target_id; 1878 __le64 resp_addr; 1879 __le32 flags; 1880 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 1881 __le32 unused; 1882 }; 1883 1884 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 1885 struct hwrm_func_drv_if_change_output { 1886 __le16 error_code; 1887 __le16 req_type; 1888 __le16 seq_id; 1889 __le16 resp_len; 1890 __le32 flags; 1891 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 1892 u8 unused_0[3]; 1893 u8 valid; 1894 }; 1895 1896 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 1897 struct hwrm_port_phy_cfg_input { 1898 __le16 req_type; 1899 __le16 cmpl_ring; 1900 __le16 seq_id; 1901 __le16 target_id; 1902 __le64 resp_addr; 1903 __le32 flags; 1904 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1905 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1906 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1907 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1908 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1909 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1910 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1911 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1912 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1913 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1914 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1915 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1916 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1917 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1918 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1919 __le32 enables; 1920 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1921 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1922 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1923 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1924 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1925 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1926 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1927 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1928 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1929 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1930 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1931 __le16 port_id; 1932 __le16 force_link_speed; 1933 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1934 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1935 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1936 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1937 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1938 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1939 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1940 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1941 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1942 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1943 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL 1944 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1945 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 1946 u8 auto_mode; 1947 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1948 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1949 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1950 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1951 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1952 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 1953 u8 auto_duplex; 1954 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1955 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1956 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1957 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 1958 u8 auto_pause; 1959 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1960 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1961 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1962 u8 unused_0; 1963 __le16 auto_link_speed; 1964 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1965 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1966 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1967 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1968 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1969 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1970 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1971 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1972 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1973 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1974 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL 1975 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1976 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 1977 __le16 auto_link_speed_mask; 1978 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1979 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1980 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1981 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1982 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1983 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1984 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1985 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1986 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1987 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1988 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1989 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1990 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1991 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1992 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 1993 u8 wirespeed; 1994 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1995 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1996 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 1997 u8 lpbk; 1998 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1999 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2000 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2001 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2002 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2003 u8 force_pause; 2004 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2005 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2006 u8 unused_1; 2007 __le32 preemphasis; 2008 __le16 eee_link_speed_mask; 2009 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2010 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2011 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2012 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2013 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2014 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2015 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2016 u8 unused_2[2]; 2017 __le32 tx_lpi_timer; 2018 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2019 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2020 __le32 unused_3; 2021 }; 2022 2023 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2024 struct hwrm_port_phy_cfg_output { 2025 __le16 error_code; 2026 __le16 req_type; 2027 __le16 seq_id; 2028 __le16 resp_len; 2029 u8 unused_0[7]; 2030 u8 valid; 2031 }; 2032 2033 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2034 struct hwrm_port_phy_cfg_cmd_err { 2035 u8 code; 2036 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2037 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2038 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2039 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2040 u8 unused_0[7]; 2041 }; 2042 2043 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2044 struct hwrm_port_phy_qcfg_input { 2045 __le16 req_type; 2046 __le16 cmpl_ring; 2047 __le16 seq_id; 2048 __le16 target_id; 2049 __le64 resp_addr; 2050 __le16 port_id; 2051 u8 unused_0[6]; 2052 }; 2053 2054 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2055 struct hwrm_port_phy_qcfg_output { 2056 __le16 error_code; 2057 __le16 req_type; 2058 __le16 seq_id; 2059 __le16 resp_len; 2060 u8 link; 2061 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2062 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2063 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2064 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2065 u8 unused_0; 2066 __le16 link_speed; 2067 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2068 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2069 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2070 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2071 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2072 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2073 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2074 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2075 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2076 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2077 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2078 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2079 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2080 u8 duplex_cfg; 2081 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2082 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2083 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2084 u8 pause; 2085 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2086 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2087 __le16 support_speeds; 2088 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2089 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2090 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2091 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2092 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2093 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2094 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2095 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2096 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2097 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2098 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2099 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2100 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2101 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2102 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL 2103 __le16 force_link_speed; 2104 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2105 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2106 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2107 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2108 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2109 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2110 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2111 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2112 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2113 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2114 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL 2115 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2116 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2117 u8 auto_mode; 2118 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2119 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2120 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2121 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2122 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2123 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2124 u8 auto_pause; 2125 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2126 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2127 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2128 __le16 auto_link_speed; 2129 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2130 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2131 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2132 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2133 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2134 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2135 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2136 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2137 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2138 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2139 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL 2140 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2141 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2142 __le16 auto_link_speed_mask; 2143 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2144 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2145 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2146 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2147 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2148 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2149 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2150 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2151 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2152 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2153 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2154 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2155 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2156 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2157 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2158 u8 wirespeed; 2159 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2160 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2161 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2162 u8 lpbk; 2163 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2164 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2165 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2166 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2167 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2168 u8 force_pause; 2169 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2170 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2171 u8 module_status; 2172 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2173 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2174 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2175 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2176 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2177 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2178 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2179 __le32 preemphasis; 2180 u8 phy_maj; 2181 u8 phy_min; 2182 u8 phy_bld; 2183 u8 phy_type; 2184 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2185 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2186 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2187 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2188 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2189 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2190 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2191 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2192 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2193 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2194 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2195 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2196 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2197 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2198 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2199 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2200 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2201 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2202 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2203 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2204 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2205 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2206 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2207 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2208 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2209 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2210 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2211 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2212 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2213 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2214 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2215 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2216 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2217 u8 media_type; 2218 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2219 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2220 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2221 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2222 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2223 u8 xcvr_pkg_type; 2224 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2225 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2226 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2227 u8 eee_config_phy_addr; 2228 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2229 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2230 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2231 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2232 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2233 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2234 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2235 u8 parallel_detect; 2236 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2237 __le16 link_partner_adv_speeds; 2238 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2239 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2240 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2241 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2242 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2243 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2244 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2245 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2246 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2247 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2248 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2249 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2250 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2251 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2252 u8 link_partner_adv_auto_mode; 2253 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2254 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2255 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2256 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2257 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2258 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2259 u8 link_partner_adv_pause; 2260 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2261 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2262 __le16 adv_eee_link_speed_mask; 2263 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2264 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2265 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2266 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2267 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2268 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2269 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2270 __le16 link_partner_adv_eee_link_speed_mask; 2271 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2272 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2273 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2274 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2275 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2276 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2277 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2278 __le32 xcvr_identifier_type_tx_lpi_timer; 2279 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2280 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2281 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2282 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2283 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2284 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2285 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2286 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2287 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2288 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2289 __le16 fec_cfg; 2290 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2291 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2292 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2293 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2294 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2295 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2296 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2297 u8 duplex_state; 2298 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2299 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2300 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2301 u8 option_flags; 2302 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2303 char phy_vendor_name[16]; 2304 char phy_vendor_partnumber[16]; 2305 u8 unused_2[7]; 2306 u8 valid; 2307 }; 2308 2309 /* hwrm_port_mac_cfg_input (size:320b/40B) */ 2310 struct hwrm_port_mac_cfg_input { 2311 __le16 req_type; 2312 __le16 cmpl_ring; 2313 __le16 seq_id; 2314 __le16 target_id; 2315 __le64 resp_addr; 2316 __le32 flags; 2317 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2318 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2319 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2320 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2321 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2322 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2323 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2324 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2325 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2326 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2327 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2328 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2329 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2330 __le32 enables; 2331 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2332 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2333 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2334 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2335 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2336 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2337 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2338 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2339 __le16 port_id; 2340 u8 ipg; 2341 u8 lpbk; 2342 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2343 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2344 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2345 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2346 u8 vlan_pri2cos_map_pri; 2347 u8 reserved1; 2348 u8 tunnel_pri2cos_map_pri; 2349 u8 dscp2pri_map_pri; 2350 __le16 rx_ts_capture_ptp_msg_type; 2351 __le16 tx_ts_capture_ptp_msg_type; 2352 u8 cos_field_cfg; 2353 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2354 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2355 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2356 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2357 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2358 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2359 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2360 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2361 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2362 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2363 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2364 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2365 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2366 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2367 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2368 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2369 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2370 u8 unused_0[3]; 2371 }; 2372 2373 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 2374 struct hwrm_port_mac_cfg_output { 2375 __le16 error_code; 2376 __le16 req_type; 2377 __le16 seq_id; 2378 __le16 resp_len; 2379 __le16 mru; 2380 __le16 mtu; 2381 u8 ipg; 2382 u8 lpbk; 2383 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2384 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2385 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2386 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2387 u8 unused_0; 2388 u8 valid; 2389 }; 2390 2391 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2392 struct hwrm_port_mac_ptp_qcfg_input { 2393 __le16 req_type; 2394 __le16 cmpl_ring; 2395 __le16 seq_id; 2396 __le16 target_id; 2397 __le64 resp_addr; 2398 __le16 port_id; 2399 u8 unused_0[6]; 2400 }; 2401 2402 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2403 struct hwrm_port_mac_ptp_qcfg_output { 2404 __le16 error_code; 2405 __le16 req_type; 2406 __le16 seq_id; 2407 __le16 resp_len; 2408 u8 flags; 2409 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2410 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 2411 u8 unused_0[3]; 2412 __le32 rx_ts_reg_off_lower; 2413 __le32 rx_ts_reg_off_upper; 2414 __le32 rx_ts_reg_off_seq_id; 2415 __le32 rx_ts_reg_off_src_id_0; 2416 __le32 rx_ts_reg_off_src_id_1; 2417 __le32 rx_ts_reg_off_src_id_2; 2418 __le32 rx_ts_reg_off_domain_id; 2419 __le32 rx_ts_reg_off_fifo; 2420 __le32 rx_ts_reg_off_fifo_adv; 2421 __le32 rx_ts_reg_off_granularity; 2422 __le32 tx_ts_reg_off_lower; 2423 __le32 tx_ts_reg_off_upper; 2424 __le32 tx_ts_reg_off_seq_id; 2425 __le32 tx_ts_reg_off_fifo; 2426 __le32 tx_ts_reg_off_granularity; 2427 u8 unused_1[7]; 2428 u8 valid; 2429 }; 2430 2431 /* tx_port_stats (size:3264b/408B) */ 2432 struct tx_port_stats { 2433 __le64 tx_64b_frames; 2434 __le64 tx_65b_127b_frames; 2435 __le64 tx_128b_255b_frames; 2436 __le64 tx_256b_511b_frames; 2437 __le64 tx_512b_1023b_frames; 2438 __le64 tx_1024b_1518b_frames; 2439 __le64 tx_good_vlan_frames; 2440 __le64 tx_1519b_2047b_frames; 2441 __le64 tx_2048b_4095b_frames; 2442 __le64 tx_4096b_9216b_frames; 2443 __le64 tx_9217b_16383b_frames; 2444 __le64 tx_good_frames; 2445 __le64 tx_total_frames; 2446 __le64 tx_ucast_frames; 2447 __le64 tx_mcast_frames; 2448 __le64 tx_bcast_frames; 2449 __le64 tx_pause_frames; 2450 __le64 tx_pfc_frames; 2451 __le64 tx_jabber_frames; 2452 __le64 tx_fcs_err_frames; 2453 __le64 tx_control_frames; 2454 __le64 tx_oversz_frames; 2455 __le64 tx_single_dfrl_frames; 2456 __le64 tx_multi_dfrl_frames; 2457 __le64 tx_single_coll_frames; 2458 __le64 tx_multi_coll_frames; 2459 __le64 tx_late_coll_frames; 2460 __le64 tx_excessive_coll_frames; 2461 __le64 tx_frag_frames; 2462 __le64 tx_err; 2463 __le64 tx_tagged_frames; 2464 __le64 tx_dbl_tagged_frames; 2465 __le64 tx_runt_frames; 2466 __le64 tx_fifo_underruns; 2467 __le64 tx_pfc_ena_frames_pri0; 2468 __le64 tx_pfc_ena_frames_pri1; 2469 __le64 tx_pfc_ena_frames_pri2; 2470 __le64 tx_pfc_ena_frames_pri3; 2471 __le64 tx_pfc_ena_frames_pri4; 2472 __le64 tx_pfc_ena_frames_pri5; 2473 __le64 tx_pfc_ena_frames_pri6; 2474 __le64 tx_pfc_ena_frames_pri7; 2475 __le64 tx_eee_lpi_events; 2476 __le64 tx_eee_lpi_duration; 2477 __le64 tx_llfc_logical_msgs; 2478 __le64 tx_hcfc_msgs; 2479 __le64 tx_total_collisions; 2480 __le64 tx_bytes; 2481 __le64 tx_xthol_frames; 2482 __le64 tx_stat_discard; 2483 __le64 tx_stat_error; 2484 }; 2485 2486 /* rx_port_stats (size:4224b/528B) */ 2487 struct rx_port_stats { 2488 __le64 rx_64b_frames; 2489 __le64 rx_65b_127b_frames; 2490 __le64 rx_128b_255b_frames; 2491 __le64 rx_256b_511b_frames; 2492 __le64 rx_512b_1023b_frames; 2493 __le64 rx_1024b_1518b_frames; 2494 __le64 rx_good_vlan_frames; 2495 __le64 rx_1519b_2047b_frames; 2496 __le64 rx_2048b_4095b_frames; 2497 __le64 rx_4096b_9216b_frames; 2498 __le64 rx_9217b_16383b_frames; 2499 __le64 rx_total_frames; 2500 __le64 rx_ucast_frames; 2501 __le64 rx_mcast_frames; 2502 __le64 rx_bcast_frames; 2503 __le64 rx_fcs_err_frames; 2504 __le64 rx_ctrl_frames; 2505 __le64 rx_pause_frames; 2506 __le64 rx_pfc_frames; 2507 __le64 rx_unsupported_opcode_frames; 2508 __le64 rx_unsupported_da_pausepfc_frames; 2509 __le64 rx_wrong_sa_frames; 2510 __le64 rx_align_err_frames; 2511 __le64 rx_oor_len_frames; 2512 __le64 rx_code_err_frames; 2513 __le64 rx_false_carrier_frames; 2514 __le64 rx_ovrsz_frames; 2515 __le64 rx_jbr_frames; 2516 __le64 rx_mtu_err_frames; 2517 __le64 rx_match_crc_frames; 2518 __le64 rx_promiscuous_frames; 2519 __le64 rx_tagged_frames; 2520 __le64 rx_double_tagged_frames; 2521 __le64 rx_trunc_frames; 2522 __le64 rx_good_frames; 2523 __le64 rx_pfc_xon2xoff_frames_pri0; 2524 __le64 rx_pfc_xon2xoff_frames_pri1; 2525 __le64 rx_pfc_xon2xoff_frames_pri2; 2526 __le64 rx_pfc_xon2xoff_frames_pri3; 2527 __le64 rx_pfc_xon2xoff_frames_pri4; 2528 __le64 rx_pfc_xon2xoff_frames_pri5; 2529 __le64 rx_pfc_xon2xoff_frames_pri6; 2530 __le64 rx_pfc_xon2xoff_frames_pri7; 2531 __le64 rx_pfc_ena_frames_pri0; 2532 __le64 rx_pfc_ena_frames_pri1; 2533 __le64 rx_pfc_ena_frames_pri2; 2534 __le64 rx_pfc_ena_frames_pri3; 2535 __le64 rx_pfc_ena_frames_pri4; 2536 __le64 rx_pfc_ena_frames_pri5; 2537 __le64 rx_pfc_ena_frames_pri6; 2538 __le64 rx_pfc_ena_frames_pri7; 2539 __le64 rx_sch_crc_err_frames; 2540 __le64 rx_undrsz_frames; 2541 __le64 rx_frag_frames; 2542 __le64 rx_eee_lpi_events; 2543 __le64 rx_eee_lpi_duration; 2544 __le64 rx_llfc_physical_msgs; 2545 __le64 rx_llfc_logical_msgs; 2546 __le64 rx_llfc_msgs_with_crc_err; 2547 __le64 rx_hcfc_msgs; 2548 __le64 rx_hcfc_msgs_with_crc_err; 2549 __le64 rx_bytes; 2550 __le64 rx_runt_bytes; 2551 __le64 rx_runt_frames; 2552 __le64 rx_stat_discard; 2553 __le64 rx_stat_err; 2554 }; 2555 2556 /* hwrm_port_qstats_input (size:320b/40B) */ 2557 struct hwrm_port_qstats_input { 2558 __le16 req_type; 2559 __le16 cmpl_ring; 2560 __le16 seq_id; 2561 __le16 target_id; 2562 __le64 resp_addr; 2563 __le16 port_id; 2564 u8 unused_0[6]; 2565 __le64 tx_stat_host_addr; 2566 __le64 rx_stat_host_addr; 2567 }; 2568 2569 /* hwrm_port_qstats_output (size:128b/16B) */ 2570 struct hwrm_port_qstats_output { 2571 __le16 error_code; 2572 __le16 req_type; 2573 __le16 seq_id; 2574 __le16 resp_len; 2575 __le16 tx_stat_size; 2576 __le16 rx_stat_size; 2577 u8 unused_0[3]; 2578 u8 valid; 2579 }; 2580 2581 /* tx_port_stats_ext (size:2048b/256B) */ 2582 struct tx_port_stats_ext { 2583 __le64 tx_bytes_cos0; 2584 __le64 tx_bytes_cos1; 2585 __le64 tx_bytes_cos2; 2586 __le64 tx_bytes_cos3; 2587 __le64 tx_bytes_cos4; 2588 __le64 tx_bytes_cos5; 2589 __le64 tx_bytes_cos6; 2590 __le64 tx_bytes_cos7; 2591 __le64 tx_packets_cos0; 2592 __le64 tx_packets_cos1; 2593 __le64 tx_packets_cos2; 2594 __le64 tx_packets_cos3; 2595 __le64 tx_packets_cos4; 2596 __le64 tx_packets_cos5; 2597 __le64 tx_packets_cos6; 2598 __le64 tx_packets_cos7; 2599 __le64 pfc_pri0_tx_duration_us; 2600 __le64 pfc_pri0_tx_transitions; 2601 __le64 pfc_pri1_tx_duration_us; 2602 __le64 pfc_pri1_tx_transitions; 2603 __le64 pfc_pri2_tx_duration_us; 2604 __le64 pfc_pri2_tx_transitions; 2605 __le64 pfc_pri3_tx_duration_us; 2606 __le64 pfc_pri3_tx_transitions; 2607 __le64 pfc_pri4_tx_duration_us; 2608 __le64 pfc_pri4_tx_transitions; 2609 __le64 pfc_pri5_tx_duration_us; 2610 __le64 pfc_pri5_tx_transitions; 2611 __le64 pfc_pri6_tx_duration_us; 2612 __le64 pfc_pri6_tx_transitions; 2613 __le64 pfc_pri7_tx_duration_us; 2614 __le64 pfc_pri7_tx_transitions; 2615 }; 2616 2617 /* rx_port_stats_ext (size:2368b/296B) */ 2618 struct rx_port_stats_ext { 2619 __le64 link_down_events; 2620 __le64 continuous_pause_events; 2621 __le64 resume_pause_events; 2622 __le64 continuous_roce_pause_events; 2623 __le64 resume_roce_pause_events; 2624 __le64 rx_bytes_cos0; 2625 __le64 rx_bytes_cos1; 2626 __le64 rx_bytes_cos2; 2627 __le64 rx_bytes_cos3; 2628 __le64 rx_bytes_cos4; 2629 __le64 rx_bytes_cos5; 2630 __le64 rx_bytes_cos6; 2631 __le64 rx_bytes_cos7; 2632 __le64 rx_packets_cos0; 2633 __le64 rx_packets_cos1; 2634 __le64 rx_packets_cos2; 2635 __le64 rx_packets_cos3; 2636 __le64 rx_packets_cos4; 2637 __le64 rx_packets_cos5; 2638 __le64 rx_packets_cos6; 2639 __le64 rx_packets_cos7; 2640 __le64 pfc_pri0_rx_duration_us; 2641 __le64 pfc_pri0_rx_transitions; 2642 __le64 pfc_pri1_rx_duration_us; 2643 __le64 pfc_pri1_rx_transitions; 2644 __le64 pfc_pri2_rx_duration_us; 2645 __le64 pfc_pri2_rx_transitions; 2646 __le64 pfc_pri3_rx_duration_us; 2647 __le64 pfc_pri3_rx_transitions; 2648 __le64 pfc_pri4_rx_duration_us; 2649 __le64 pfc_pri4_rx_transitions; 2650 __le64 pfc_pri5_rx_duration_us; 2651 __le64 pfc_pri5_rx_transitions; 2652 __le64 pfc_pri6_rx_duration_us; 2653 __le64 pfc_pri6_rx_transitions; 2654 __le64 pfc_pri7_rx_duration_us; 2655 __le64 pfc_pri7_rx_transitions; 2656 }; 2657 2658 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 2659 struct hwrm_port_qstats_ext_input { 2660 __le16 req_type; 2661 __le16 cmpl_ring; 2662 __le16 seq_id; 2663 __le16 target_id; 2664 __le64 resp_addr; 2665 __le16 port_id; 2666 __le16 tx_stat_size; 2667 __le16 rx_stat_size; 2668 u8 unused_0[2]; 2669 __le64 tx_stat_host_addr; 2670 __le64 rx_stat_host_addr; 2671 }; 2672 2673 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 2674 struct hwrm_port_qstats_ext_output { 2675 __le16 error_code; 2676 __le16 req_type; 2677 __le16 seq_id; 2678 __le16 resp_len; 2679 __le16 tx_stat_size; 2680 __le16 rx_stat_size; 2681 __le16 total_active_cos_queues; 2682 u8 flags; 2683 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 2684 u8 valid; 2685 }; 2686 2687 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 2688 struct hwrm_port_lpbk_qstats_input { 2689 __le16 req_type; 2690 __le16 cmpl_ring; 2691 __le16 seq_id; 2692 __le16 target_id; 2693 __le64 resp_addr; 2694 }; 2695 2696 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 2697 struct hwrm_port_lpbk_qstats_output { 2698 __le16 error_code; 2699 __le16 req_type; 2700 __le16 seq_id; 2701 __le16 resp_len; 2702 __le64 lpbk_ucast_frames; 2703 __le64 lpbk_mcast_frames; 2704 __le64 lpbk_bcast_frames; 2705 __le64 lpbk_ucast_bytes; 2706 __le64 lpbk_mcast_bytes; 2707 __le64 lpbk_bcast_bytes; 2708 __le64 tx_stat_discard; 2709 __le64 tx_stat_error; 2710 __le64 rx_stat_discard; 2711 __le64 rx_stat_error; 2712 u8 unused_0[7]; 2713 u8 valid; 2714 }; 2715 2716 /* hwrm_port_clr_stats_input (size:192b/24B) */ 2717 struct hwrm_port_clr_stats_input { 2718 __le16 req_type; 2719 __le16 cmpl_ring; 2720 __le16 seq_id; 2721 __le16 target_id; 2722 __le64 resp_addr; 2723 __le16 port_id; 2724 u8 flags; 2725 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 2726 u8 unused_0[5]; 2727 }; 2728 2729 /* hwrm_port_clr_stats_output (size:128b/16B) */ 2730 struct hwrm_port_clr_stats_output { 2731 __le16 error_code; 2732 __le16 req_type; 2733 __le16 seq_id; 2734 __le16 resp_len; 2735 u8 unused_0[7]; 2736 u8 valid; 2737 }; 2738 2739 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 2740 struct hwrm_port_lpbk_clr_stats_input { 2741 __le16 req_type; 2742 __le16 cmpl_ring; 2743 __le16 seq_id; 2744 __le16 target_id; 2745 __le64 resp_addr; 2746 }; 2747 2748 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 2749 struct hwrm_port_lpbk_clr_stats_output { 2750 __le16 error_code; 2751 __le16 req_type; 2752 __le16 seq_id; 2753 __le16 resp_len; 2754 u8 unused_0[7]; 2755 u8 valid; 2756 }; 2757 2758 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 2759 struct hwrm_port_phy_qcaps_input { 2760 __le16 req_type; 2761 __le16 cmpl_ring; 2762 __le16 seq_id; 2763 __le16 target_id; 2764 __le64 resp_addr; 2765 __le16 port_id; 2766 u8 unused_0[6]; 2767 }; 2768 2769 /* hwrm_port_phy_qcaps_output (size:192b/24B) */ 2770 struct hwrm_port_phy_qcaps_output { 2771 __le16 error_code; 2772 __le16 req_type; 2773 __le16 seq_id; 2774 __le16 resp_len; 2775 u8 flags; 2776 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 2777 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 2778 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL 2779 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2 2780 u8 port_cnt; 2781 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 2782 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 2783 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 2784 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 2785 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 2786 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 2787 __le16 supported_speeds_force_mode; 2788 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2789 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2790 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2791 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2792 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2793 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2794 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2795 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2796 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2797 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2798 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2799 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2800 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2801 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2802 __le16 supported_speeds_auto_mode; 2803 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2804 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2805 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2806 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2807 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2808 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2809 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2810 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2811 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2812 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2813 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2814 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2815 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2816 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2817 __le16 supported_speeds_eee_mode; 2818 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2819 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2820 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2821 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2822 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2823 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2824 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2825 __le32 tx_lpi_timer_low; 2826 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2827 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2828 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2829 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2830 __le32 valid_tx_lpi_timer_high; 2831 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2832 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2833 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2834 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2835 }; 2836 2837 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 2838 struct hwrm_port_phy_i2c_read_input { 2839 __le16 req_type; 2840 __le16 cmpl_ring; 2841 __le16 seq_id; 2842 __le16 target_id; 2843 __le64 resp_addr; 2844 __le32 flags; 2845 __le32 enables; 2846 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2847 __le16 port_id; 2848 u8 i2c_slave_addr; 2849 u8 unused_0; 2850 __le16 page_number; 2851 __le16 page_offset; 2852 u8 data_length; 2853 u8 unused_1[7]; 2854 }; 2855 2856 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 2857 struct hwrm_port_phy_i2c_read_output { 2858 __le16 error_code; 2859 __le16 req_type; 2860 __le16 seq_id; 2861 __le16 resp_len; 2862 __le32 data[16]; 2863 u8 unused_0[7]; 2864 u8 valid; 2865 }; 2866 2867 /* hwrm_port_led_cfg_input (size:512b/64B) */ 2868 struct hwrm_port_led_cfg_input { 2869 __le16 req_type; 2870 __le16 cmpl_ring; 2871 __le16 seq_id; 2872 __le16 target_id; 2873 __le64 resp_addr; 2874 __le32 enables; 2875 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2876 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2877 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2878 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2879 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2880 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2881 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2882 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2883 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2884 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2885 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2886 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2887 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2888 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2889 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2890 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2891 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2892 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2893 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2894 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2895 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2896 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2897 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2898 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2899 __le16 port_id; 2900 u8 num_leds; 2901 u8 rsvd; 2902 u8 led0_id; 2903 u8 led0_state; 2904 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2905 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2906 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2907 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2908 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2909 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 2910 u8 led0_color; 2911 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2912 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2913 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2914 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2915 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 2916 u8 unused_0; 2917 __le16 led0_blink_on; 2918 __le16 led0_blink_off; 2919 u8 led0_group_id; 2920 u8 rsvd0; 2921 u8 led1_id; 2922 u8 led1_state; 2923 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2924 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2925 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2926 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2927 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2928 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 2929 u8 led1_color; 2930 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2931 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2932 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2933 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2934 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 2935 u8 unused_1; 2936 __le16 led1_blink_on; 2937 __le16 led1_blink_off; 2938 u8 led1_group_id; 2939 u8 rsvd1; 2940 u8 led2_id; 2941 u8 led2_state; 2942 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2943 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2944 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2945 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2946 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2947 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 2948 u8 led2_color; 2949 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2950 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2951 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2952 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2953 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 2954 u8 unused_2; 2955 __le16 led2_blink_on; 2956 __le16 led2_blink_off; 2957 u8 led2_group_id; 2958 u8 rsvd2; 2959 u8 led3_id; 2960 u8 led3_state; 2961 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2962 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2963 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2964 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2965 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2966 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 2967 u8 led3_color; 2968 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2969 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2970 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2971 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2972 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 2973 u8 unused_3; 2974 __le16 led3_blink_on; 2975 __le16 led3_blink_off; 2976 u8 led3_group_id; 2977 u8 rsvd3; 2978 }; 2979 2980 /* hwrm_port_led_cfg_output (size:128b/16B) */ 2981 struct hwrm_port_led_cfg_output { 2982 __le16 error_code; 2983 __le16 req_type; 2984 __le16 seq_id; 2985 __le16 resp_len; 2986 u8 unused_0[7]; 2987 u8 valid; 2988 }; 2989 2990 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 2991 struct hwrm_port_led_qcfg_input { 2992 __le16 req_type; 2993 __le16 cmpl_ring; 2994 __le16 seq_id; 2995 __le16 target_id; 2996 __le64 resp_addr; 2997 __le16 port_id; 2998 u8 unused_0[6]; 2999 }; 3000 3001 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3002 struct hwrm_port_led_qcfg_output { 3003 __le16 error_code; 3004 __le16 req_type; 3005 __le16 seq_id; 3006 __le16 resp_len; 3007 u8 num_leds; 3008 u8 led0_id; 3009 u8 led0_type; 3010 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3011 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3012 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3013 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3014 u8 led0_state; 3015 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3016 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3017 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3018 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3019 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3020 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3021 u8 led0_color; 3022 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3023 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3024 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3025 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3026 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3027 u8 unused_0; 3028 __le16 led0_blink_on; 3029 __le16 led0_blink_off; 3030 u8 led0_group_id; 3031 u8 led1_id; 3032 u8 led1_type; 3033 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3034 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3035 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3036 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3037 u8 led1_state; 3038 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3039 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3040 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3041 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3042 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3043 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3044 u8 led1_color; 3045 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3046 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3047 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3048 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3049 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3050 u8 unused_1; 3051 __le16 led1_blink_on; 3052 __le16 led1_blink_off; 3053 u8 led1_group_id; 3054 u8 led2_id; 3055 u8 led2_type; 3056 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3057 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3058 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3059 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3060 u8 led2_state; 3061 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3062 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3063 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3064 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3065 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3066 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3067 u8 led2_color; 3068 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3069 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3070 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3071 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3072 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3073 u8 unused_2; 3074 __le16 led2_blink_on; 3075 __le16 led2_blink_off; 3076 u8 led2_group_id; 3077 u8 led3_id; 3078 u8 led3_type; 3079 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3080 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3081 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3082 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3083 u8 led3_state; 3084 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3085 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3086 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3087 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3088 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3089 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3090 u8 led3_color; 3091 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3092 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3093 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3094 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3095 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3096 u8 unused_3; 3097 __le16 led3_blink_on; 3098 __le16 led3_blink_off; 3099 u8 led3_group_id; 3100 u8 unused_4[6]; 3101 u8 valid; 3102 }; 3103 3104 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3105 struct hwrm_port_led_qcaps_input { 3106 __le16 req_type; 3107 __le16 cmpl_ring; 3108 __le16 seq_id; 3109 __le16 target_id; 3110 __le64 resp_addr; 3111 __le16 port_id; 3112 u8 unused_0[6]; 3113 }; 3114 3115 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3116 struct hwrm_port_led_qcaps_output { 3117 __le16 error_code; 3118 __le16 req_type; 3119 __le16 seq_id; 3120 __le16 resp_len; 3121 u8 num_leds; 3122 u8 unused[3]; 3123 u8 led0_id; 3124 u8 led0_type; 3125 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3126 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3127 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3128 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3129 u8 led0_group_id; 3130 u8 unused_0; 3131 __le16 led0_state_caps; 3132 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3133 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3134 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3135 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3136 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3137 __le16 led0_color_caps; 3138 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3139 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3140 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3141 u8 led1_id; 3142 u8 led1_type; 3143 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3144 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3145 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3146 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3147 u8 led1_group_id; 3148 u8 unused_1; 3149 __le16 led1_state_caps; 3150 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3151 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3152 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3153 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3154 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3155 __le16 led1_color_caps; 3156 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3157 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3158 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3159 u8 led2_id; 3160 u8 led2_type; 3161 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3162 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3163 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3164 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3165 u8 led2_group_id; 3166 u8 unused_2; 3167 __le16 led2_state_caps; 3168 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3169 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3170 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3171 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3172 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3173 __le16 led2_color_caps; 3174 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3175 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3176 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3177 u8 led3_id; 3178 u8 led3_type; 3179 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3180 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3181 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3182 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3183 u8 led3_group_id; 3184 u8 unused_3; 3185 __le16 led3_state_caps; 3186 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3187 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3188 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3189 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3190 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3191 __le16 led3_color_caps; 3192 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3193 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3194 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3195 u8 unused_4[3]; 3196 u8 valid; 3197 }; 3198 3199 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 3200 struct hwrm_queue_qportcfg_input { 3201 __le16 req_type; 3202 __le16 cmpl_ring; 3203 __le16 seq_id; 3204 __le16 target_id; 3205 __le64 resp_addr; 3206 __le32 flags; 3207 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3208 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3209 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3210 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3211 __le16 port_id; 3212 u8 drv_qmap_cap; 3213 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3214 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3215 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3216 u8 unused_0; 3217 }; 3218 3219 /* hwrm_queue_qportcfg_output (size:256b/32B) */ 3220 struct hwrm_queue_qportcfg_output { 3221 __le16 error_code; 3222 __le16 req_type; 3223 __le16 seq_id; 3224 __le16 resp_len; 3225 u8 max_configurable_queues; 3226 u8 max_configurable_lossless_queues; 3227 u8 queue_cfg_allowed; 3228 u8 queue_cfg_info; 3229 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3230 u8 queue_pfcenable_cfg_allowed; 3231 u8 queue_pri2cos_cfg_allowed; 3232 u8 queue_cos2bw_cfg_allowed; 3233 u8 queue_id0; 3234 u8 queue_id0_service_profile; 3235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3236 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3240 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3241 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3242 u8 queue_id1; 3243 u8 queue_id1_service_profile; 3244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3246 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3248 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3249 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3250 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3251 u8 queue_id2; 3252 u8 queue_id2_service_profile; 3253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3254 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3255 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3256 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3257 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3258 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3259 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3260 u8 queue_id3; 3261 u8 queue_id3_service_profile; 3262 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3263 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3264 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3265 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3266 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3267 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3268 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3269 u8 queue_id4; 3270 u8 queue_id4_service_profile; 3271 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3272 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3273 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3274 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3275 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3276 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3277 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3278 u8 queue_id5; 3279 u8 queue_id5_service_profile; 3280 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3281 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3282 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3283 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3284 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3285 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3286 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3287 u8 queue_id6; 3288 u8 queue_id6_service_profile; 3289 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3290 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3291 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3292 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3293 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3294 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3295 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3296 u8 queue_id7; 3297 u8 queue_id7_service_profile; 3298 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3299 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3300 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3301 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3302 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3303 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3304 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3305 u8 valid; 3306 }; 3307 3308 /* hwrm_queue_cfg_input (size:320b/40B) */ 3309 struct hwrm_queue_cfg_input { 3310 __le16 req_type; 3311 __le16 cmpl_ring; 3312 __le16 seq_id; 3313 __le16 target_id; 3314 __le64 resp_addr; 3315 __le32 flags; 3316 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3317 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 3318 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 3319 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 3320 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3321 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 3322 __le32 enables; 3323 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 3324 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 3325 __le32 queue_id; 3326 __le32 dflt_len; 3327 u8 service_profile; 3328 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 3329 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 3330 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 3331 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 3332 u8 unused_0[7]; 3333 }; 3334 3335 /* hwrm_queue_cfg_output (size:128b/16B) */ 3336 struct hwrm_queue_cfg_output { 3337 __le16 error_code; 3338 __le16 req_type; 3339 __le16 seq_id; 3340 __le16 resp_len; 3341 u8 unused_0[7]; 3342 u8 valid; 3343 }; 3344 3345 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 3346 struct hwrm_queue_pfcenable_qcfg_input { 3347 __le16 req_type; 3348 __le16 cmpl_ring; 3349 __le16 seq_id; 3350 __le16 target_id; 3351 __le64 resp_addr; 3352 __le16 port_id; 3353 u8 unused_0[6]; 3354 }; 3355 3356 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 3357 struct hwrm_queue_pfcenable_qcfg_output { 3358 __le16 error_code; 3359 __le16 req_type; 3360 __le16 seq_id; 3361 __le16 resp_len; 3362 __le32 flags; 3363 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 3364 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 3365 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 3366 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 3367 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 3368 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 3369 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 3370 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 3371 u8 unused_0[3]; 3372 u8 valid; 3373 }; 3374 3375 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 3376 struct hwrm_queue_pfcenable_cfg_input { 3377 __le16 req_type; 3378 __le16 cmpl_ring; 3379 __le16 seq_id; 3380 __le16 target_id; 3381 __le64 resp_addr; 3382 __le32 flags; 3383 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 3384 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 3385 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 3386 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 3387 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 3388 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 3389 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 3390 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 3391 __le16 port_id; 3392 u8 unused_0[2]; 3393 }; 3394 3395 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 3396 struct hwrm_queue_pfcenable_cfg_output { 3397 __le16 error_code; 3398 __le16 req_type; 3399 __le16 seq_id; 3400 __le16 resp_len; 3401 u8 unused_0[7]; 3402 u8 valid; 3403 }; 3404 3405 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 3406 struct hwrm_queue_pri2cos_qcfg_input { 3407 __le16 req_type; 3408 __le16 cmpl_ring; 3409 __le16 seq_id; 3410 __le16 target_id; 3411 __le64 resp_addr; 3412 __le32 flags; 3413 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 3414 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 3415 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 3416 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 3417 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 3418 u8 port_id; 3419 u8 unused_0[3]; 3420 }; 3421 3422 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 3423 struct hwrm_queue_pri2cos_qcfg_output { 3424 __le16 error_code; 3425 __le16 req_type; 3426 __le16 seq_id; 3427 __le16 resp_len; 3428 u8 pri0_cos_queue_id; 3429 u8 pri1_cos_queue_id; 3430 u8 pri2_cos_queue_id; 3431 u8 pri3_cos_queue_id; 3432 u8 pri4_cos_queue_id; 3433 u8 pri5_cos_queue_id; 3434 u8 pri6_cos_queue_id; 3435 u8 pri7_cos_queue_id; 3436 u8 queue_cfg_info; 3437 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3438 u8 unused_0[6]; 3439 u8 valid; 3440 }; 3441 3442 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 3443 struct hwrm_queue_pri2cos_cfg_input { 3444 __le16 req_type; 3445 __le16 cmpl_ring; 3446 __le16 seq_id; 3447 __le16 target_id; 3448 __le64 resp_addr; 3449 __le32 flags; 3450 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3451 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 3452 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 3453 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 3454 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3455 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 3456 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 3457 __le32 enables; 3458 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 3459 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 3460 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 3461 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 3462 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 3463 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 3464 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 3465 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 3466 u8 port_id; 3467 u8 pri0_cos_queue_id; 3468 u8 pri1_cos_queue_id; 3469 u8 pri2_cos_queue_id; 3470 u8 pri3_cos_queue_id; 3471 u8 pri4_cos_queue_id; 3472 u8 pri5_cos_queue_id; 3473 u8 pri6_cos_queue_id; 3474 u8 pri7_cos_queue_id; 3475 u8 unused_0[7]; 3476 }; 3477 3478 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 3479 struct hwrm_queue_pri2cos_cfg_output { 3480 __le16 error_code; 3481 __le16 req_type; 3482 __le16 seq_id; 3483 __le16 resp_len; 3484 u8 unused_0[7]; 3485 u8 valid; 3486 }; 3487 3488 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 3489 struct hwrm_queue_cos2bw_qcfg_input { 3490 __le16 req_type; 3491 __le16 cmpl_ring; 3492 __le16 seq_id; 3493 __le16 target_id; 3494 __le64 resp_addr; 3495 __le16 port_id; 3496 u8 unused_0[6]; 3497 }; 3498 3499 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 3500 struct hwrm_queue_cos2bw_qcfg_output { 3501 __le16 error_code; 3502 __le16 req_type; 3503 __le16 seq_id; 3504 __le16 resp_len; 3505 u8 queue_id0; 3506 u8 unused_0; 3507 __le16 unused_1; 3508 __le32 queue_id0_min_bw; 3509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 3515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3524 __le32 queue_id0_max_bw; 3525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 3531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3540 u8 queue_id0_tsa_assign; 3541 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3542 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3545 u8 queue_id0_pri_lvl; 3546 u8 queue_id0_bw_weight; 3547 u8 queue_id1; 3548 __le32 queue_id1_min_bw; 3549 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3550 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 3555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3560 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3564 __le32 queue_id1_max_bw; 3565 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3566 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3568 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3569 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 3571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3580 u8 queue_id1_tsa_assign; 3581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3585 u8 queue_id1_pri_lvl; 3586 u8 queue_id1_bw_weight; 3587 u8 queue_id2; 3588 __le32 queue_id2_min_bw; 3589 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 3595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3604 __le32 queue_id2_max_bw; 3605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 3611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3620 u8 queue_id2_tsa_assign; 3621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3625 u8 queue_id2_pri_lvl; 3626 u8 queue_id2_bw_weight; 3627 u8 queue_id3; 3628 __le32 queue_id3_min_bw; 3629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 3635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3644 __le32 queue_id3_max_bw; 3645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 3651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3660 u8 queue_id3_tsa_assign; 3661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3665 u8 queue_id3_pri_lvl; 3666 u8 queue_id3_bw_weight; 3667 u8 queue_id4; 3668 __le32 queue_id4_min_bw; 3669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 3675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3684 __le32 queue_id4_max_bw; 3685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 3691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3700 u8 queue_id4_tsa_assign; 3701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3705 u8 queue_id4_pri_lvl; 3706 u8 queue_id4_bw_weight; 3707 u8 queue_id5; 3708 __le32 queue_id5_min_bw; 3709 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 3715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3724 __le32 queue_id5_max_bw; 3725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 3731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3740 u8 queue_id5_tsa_assign; 3741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3745 u8 queue_id5_pri_lvl; 3746 u8 queue_id5_bw_weight; 3747 u8 queue_id6; 3748 __le32 queue_id6_min_bw; 3749 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 3755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3764 __le32 queue_id6_max_bw; 3765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 3771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3780 u8 queue_id6_tsa_assign; 3781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3785 u8 queue_id6_pri_lvl; 3786 u8 queue_id6_bw_weight; 3787 u8 queue_id7; 3788 __le32 queue_id7_min_bw; 3789 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 3795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3804 __le32 queue_id7_max_bw; 3805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 3811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3820 u8 queue_id7_tsa_assign; 3821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3825 u8 queue_id7_pri_lvl; 3826 u8 queue_id7_bw_weight; 3827 u8 unused_2[4]; 3828 u8 valid; 3829 }; 3830 3831 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 3832 struct hwrm_queue_cos2bw_cfg_input { 3833 __le16 req_type; 3834 __le16 cmpl_ring; 3835 __le16 seq_id; 3836 __le16 target_id; 3837 __le64 resp_addr; 3838 __le32 flags; 3839 __le32 enables; 3840 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 3841 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 3842 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 3843 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 3844 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 3845 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 3846 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 3847 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 3848 __le16 port_id; 3849 u8 queue_id0; 3850 u8 unused_0; 3851 __le32 queue_id0_min_bw; 3852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 3858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3867 __le32 queue_id0_max_bw; 3868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 3874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3883 u8 queue_id0_tsa_assign; 3884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3885 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3888 u8 queue_id0_pri_lvl; 3889 u8 queue_id0_bw_weight; 3890 u8 queue_id1; 3891 __le32 queue_id1_min_bw; 3892 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3893 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3894 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 3898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3903 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3907 __le32 queue_id1_max_bw; 3908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 3914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3923 u8 queue_id1_tsa_assign; 3924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3928 u8 queue_id1_pri_lvl; 3929 u8 queue_id1_bw_weight; 3930 u8 queue_id2; 3931 __le32 queue_id2_min_bw; 3932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3947 __le32 queue_id2_max_bw; 3948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3963 u8 queue_id2_tsa_assign; 3964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3968 u8 queue_id2_pri_lvl; 3969 u8 queue_id2_bw_weight; 3970 u8 queue_id3; 3971 __le32 queue_id3_min_bw; 3972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3987 __le32 queue_id3_max_bw; 3988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4003 u8 queue_id3_tsa_assign; 4004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4008 u8 queue_id3_pri_lvl; 4009 u8 queue_id3_bw_weight; 4010 u8 queue_id4; 4011 __le32 queue_id4_min_bw; 4012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4027 __le32 queue_id4_max_bw; 4028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4043 u8 queue_id4_tsa_assign; 4044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4048 u8 queue_id4_pri_lvl; 4049 u8 queue_id4_bw_weight; 4050 u8 queue_id5; 4051 __le32 queue_id5_min_bw; 4052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4067 __le32 queue_id5_max_bw; 4068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4083 u8 queue_id5_tsa_assign; 4084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4088 u8 queue_id5_pri_lvl; 4089 u8 queue_id5_bw_weight; 4090 u8 queue_id6; 4091 __le32 queue_id6_min_bw; 4092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4107 __le32 queue_id6_max_bw; 4108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4123 u8 queue_id6_tsa_assign; 4124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4128 u8 queue_id6_pri_lvl; 4129 u8 queue_id6_bw_weight; 4130 u8 queue_id7; 4131 __le32 queue_id7_min_bw; 4132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4147 __le32 queue_id7_max_bw; 4148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4152 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4157 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4163 u8 queue_id7_tsa_assign; 4164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4168 u8 queue_id7_pri_lvl; 4169 u8 queue_id7_bw_weight; 4170 u8 unused_1[5]; 4171 }; 4172 4173 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4174 struct hwrm_queue_cos2bw_cfg_output { 4175 __le16 error_code; 4176 __le16 req_type; 4177 __le16 seq_id; 4178 __le16 resp_len; 4179 u8 unused_0[7]; 4180 u8 valid; 4181 }; 4182 4183 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4184 struct hwrm_queue_dscp_qcaps_input { 4185 __le16 req_type; 4186 __le16 cmpl_ring; 4187 __le16 seq_id; 4188 __le16 target_id; 4189 __le64 resp_addr; 4190 u8 port_id; 4191 u8 unused_0[7]; 4192 }; 4193 4194 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4195 struct hwrm_queue_dscp_qcaps_output { 4196 __le16 error_code; 4197 __le16 req_type; 4198 __le16 seq_id; 4199 __le16 resp_len; 4200 u8 num_dscp_bits; 4201 u8 unused_0; 4202 __le16 max_entries; 4203 u8 unused_1[3]; 4204 u8 valid; 4205 }; 4206 4207 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4208 struct hwrm_queue_dscp2pri_qcfg_input { 4209 __le16 req_type; 4210 __le16 cmpl_ring; 4211 __le16 seq_id; 4212 __le16 target_id; 4213 __le64 resp_addr; 4214 __le64 dest_data_addr; 4215 u8 port_id; 4216 u8 unused_0; 4217 __le16 dest_data_buffer_size; 4218 u8 unused_1[4]; 4219 }; 4220 4221 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4222 struct hwrm_queue_dscp2pri_qcfg_output { 4223 __le16 error_code; 4224 __le16 req_type; 4225 __le16 seq_id; 4226 __le16 resp_len; 4227 __le16 entry_cnt; 4228 u8 default_pri; 4229 u8 unused_0[4]; 4230 u8 valid; 4231 }; 4232 4233 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4234 struct hwrm_queue_dscp2pri_cfg_input { 4235 __le16 req_type; 4236 __le16 cmpl_ring; 4237 __le16 seq_id; 4238 __le16 target_id; 4239 __le64 resp_addr; 4240 __le64 src_data_addr; 4241 __le32 flags; 4242 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4243 __le32 enables; 4244 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4245 u8 port_id; 4246 u8 default_pri; 4247 __le16 entry_cnt; 4248 u8 unused_0[4]; 4249 }; 4250 4251 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4252 struct hwrm_queue_dscp2pri_cfg_output { 4253 __le16 error_code; 4254 __le16 req_type; 4255 __le16 seq_id; 4256 __le16 resp_len; 4257 u8 unused_0[7]; 4258 u8 valid; 4259 }; 4260 4261 /* hwrm_vnic_alloc_input (size:192b/24B) */ 4262 struct hwrm_vnic_alloc_input { 4263 __le16 req_type; 4264 __le16 cmpl_ring; 4265 __le16 seq_id; 4266 __le16 target_id; 4267 __le64 resp_addr; 4268 __le32 flags; 4269 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 4270 u8 unused_0[4]; 4271 }; 4272 4273 /* hwrm_vnic_alloc_output (size:128b/16B) */ 4274 struct hwrm_vnic_alloc_output { 4275 __le16 error_code; 4276 __le16 req_type; 4277 __le16 seq_id; 4278 __le16 resp_len; 4279 __le32 vnic_id; 4280 u8 unused_0[3]; 4281 u8 valid; 4282 }; 4283 4284 /* hwrm_vnic_free_input (size:192b/24B) */ 4285 struct hwrm_vnic_free_input { 4286 __le16 req_type; 4287 __le16 cmpl_ring; 4288 __le16 seq_id; 4289 __le16 target_id; 4290 __le64 resp_addr; 4291 __le32 vnic_id; 4292 u8 unused_0[4]; 4293 }; 4294 4295 /* hwrm_vnic_free_output (size:128b/16B) */ 4296 struct hwrm_vnic_free_output { 4297 __le16 error_code; 4298 __le16 req_type; 4299 __le16 seq_id; 4300 __le16 resp_len; 4301 u8 unused_0[7]; 4302 u8 valid; 4303 }; 4304 4305 /* hwrm_vnic_cfg_input (size:320b/40B) */ 4306 struct hwrm_vnic_cfg_input { 4307 __le16 req_type; 4308 __le16 cmpl_ring; 4309 __le16 seq_id; 4310 __le16 target_id; 4311 __le64 resp_addr; 4312 __le32 flags; 4313 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 4314 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 4315 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 4316 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 4317 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 4318 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4319 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4320 __le32 enables; 4321 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4322 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4323 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4324 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4325 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4326 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 4327 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 4328 __le16 vnic_id; 4329 __le16 dflt_ring_grp; 4330 __le16 rss_rule; 4331 __le16 cos_rule; 4332 __le16 lb_rule; 4333 __le16 mru; 4334 __le16 default_rx_ring_id; 4335 __le16 default_cmpl_ring_id; 4336 }; 4337 4338 /* hwrm_vnic_cfg_output (size:128b/16B) */ 4339 struct hwrm_vnic_cfg_output { 4340 __le16 error_code; 4341 __le16 req_type; 4342 __le16 seq_id; 4343 __le16 resp_len; 4344 u8 unused_0[7]; 4345 u8 valid; 4346 }; 4347 4348 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 4349 struct hwrm_vnic_qcaps_input { 4350 __le16 req_type; 4351 __le16 cmpl_ring; 4352 __le16 seq_id; 4353 __le16 target_id; 4354 __le64 resp_addr; 4355 __le32 enables; 4356 u8 unused_0[4]; 4357 }; 4358 4359 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 4360 struct hwrm_vnic_qcaps_output { 4361 __le16 error_code; 4362 __le16 req_type; 4363 __le16 seq_id; 4364 __le16 resp_len; 4365 __le16 mru; 4366 u8 unused_0[2]; 4367 __le32 flags; 4368 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 4369 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 4370 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 4371 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 4372 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4373 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4374 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4375 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 4376 u8 unused_1[7]; 4377 u8 valid; 4378 }; 4379 4380 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 4381 struct hwrm_vnic_tpa_cfg_input { 4382 __le16 req_type; 4383 __le16 cmpl_ring; 4384 __le16 seq_id; 4385 __le16 target_id; 4386 __le64 resp_addr; 4387 __le32 flags; 4388 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 4389 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 4390 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 4391 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 4392 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 4393 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4394 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 4395 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 4396 __le32 enables; 4397 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 4398 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 4399 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 4400 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 4401 __le16 vnic_id; 4402 __le16 max_agg_segs; 4403 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 4404 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 4405 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 4406 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 4407 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 4408 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 4409 __le16 max_aggs; 4410 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 4411 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 4412 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 4413 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 4414 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 4415 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 4416 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 4417 u8 unused_0[2]; 4418 __le32 max_agg_timer; 4419 __le32 min_agg_len; 4420 }; 4421 4422 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 4423 struct hwrm_vnic_tpa_cfg_output { 4424 __le16 error_code; 4425 __le16 req_type; 4426 __le16 seq_id; 4427 __le16 resp_len; 4428 u8 unused_0[7]; 4429 u8 valid; 4430 }; 4431 4432 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 4433 struct hwrm_vnic_tpa_qcfg_input { 4434 __le16 req_type; 4435 __le16 cmpl_ring; 4436 __le16 seq_id; 4437 __le16 target_id; 4438 __le64 resp_addr; 4439 __le16 vnic_id; 4440 u8 unused_0[6]; 4441 }; 4442 4443 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 4444 struct hwrm_vnic_tpa_qcfg_output { 4445 __le16 error_code; 4446 __le16 req_type; 4447 __le16 seq_id; 4448 __le16 resp_len; 4449 __le32 flags; 4450 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 4451 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 4452 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 4453 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 4454 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 4455 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4456 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 4457 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 4458 __le16 max_agg_segs; 4459 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 4460 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 4461 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 4462 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 4463 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 4464 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 4465 __le16 max_aggs; 4466 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 4467 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 4468 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 4469 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 4470 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 4471 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 4472 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 4473 __le32 max_agg_timer; 4474 __le32 min_agg_len; 4475 u8 unused_0[7]; 4476 u8 valid; 4477 }; 4478 4479 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 4480 struct hwrm_vnic_rss_cfg_input { 4481 __le16 req_type; 4482 __le16 cmpl_ring; 4483 __le16 seq_id; 4484 __le16 target_id; 4485 __le64 resp_addr; 4486 __le32 hash_type; 4487 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 4488 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 4489 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 4490 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 4491 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 4492 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 4493 __le16 vnic_id; 4494 u8 ring_table_pair_index; 4495 u8 hash_mode_flags; 4496 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 4497 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 4498 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 4499 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 4500 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 4501 __le64 ring_grp_tbl_addr; 4502 __le64 hash_key_tbl_addr; 4503 __le16 rss_ctx_idx; 4504 u8 unused_1[6]; 4505 }; 4506 4507 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 4508 struct hwrm_vnic_rss_cfg_output { 4509 __le16 error_code; 4510 __le16 req_type; 4511 __le16 seq_id; 4512 __le16 resp_len; 4513 u8 unused_0[7]; 4514 u8 valid; 4515 }; 4516 4517 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 4518 struct hwrm_vnic_plcmodes_cfg_input { 4519 __le16 req_type; 4520 __le16 cmpl_ring; 4521 __le16 seq_id; 4522 __le16 target_id; 4523 __le64 resp_addr; 4524 __le32 flags; 4525 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 4526 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 4527 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 4528 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 4529 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 4530 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 4531 __le32 enables; 4532 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 4533 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 4534 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 4535 __le32 vnic_id; 4536 __le16 jumbo_thresh; 4537 __le16 hds_offset; 4538 __le16 hds_threshold; 4539 u8 unused_0[6]; 4540 }; 4541 4542 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 4543 struct hwrm_vnic_plcmodes_cfg_output { 4544 __le16 error_code; 4545 __le16 req_type; 4546 __le16 seq_id; 4547 __le16 resp_len; 4548 u8 unused_0[7]; 4549 u8 valid; 4550 }; 4551 4552 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 4553 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 4554 __le16 req_type; 4555 __le16 cmpl_ring; 4556 __le16 seq_id; 4557 __le16 target_id; 4558 __le64 resp_addr; 4559 }; 4560 4561 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 4562 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 4563 __le16 error_code; 4564 __le16 req_type; 4565 __le16 seq_id; 4566 __le16 resp_len; 4567 __le16 rss_cos_lb_ctx_id; 4568 u8 unused_0[5]; 4569 u8 valid; 4570 }; 4571 4572 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 4573 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 4574 __le16 req_type; 4575 __le16 cmpl_ring; 4576 __le16 seq_id; 4577 __le16 target_id; 4578 __le64 resp_addr; 4579 __le16 rss_cos_lb_ctx_id; 4580 u8 unused_0[6]; 4581 }; 4582 4583 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 4584 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 4585 __le16 error_code; 4586 __le16 req_type; 4587 __le16 seq_id; 4588 __le16 resp_len; 4589 u8 unused_0[7]; 4590 u8 valid; 4591 }; 4592 4593 /* hwrm_ring_alloc_input (size:704b/88B) */ 4594 struct hwrm_ring_alloc_input { 4595 __le16 req_type; 4596 __le16 cmpl_ring; 4597 __le16 seq_id; 4598 __le16 target_id; 4599 __le64 resp_addr; 4600 __le32 enables; 4601 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 4602 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 4603 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 4604 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 4605 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 4606 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 4607 u8 ring_type; 4608 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 4609 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 4610 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 4611 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4612 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 4613 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 4614 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 4615 u8 unused_0; 4616 __le16 flags; 4617 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 4618 __le64 page_tbl_addr; 4619 __le32 fbo; 4620 u8 page_size; 4621 u8 page_tbl_depth; 4622 u8 unused_1[2]; 4623 __le32 length; 4624 __le16 logical_id; 4625 __le16 cmpl_ring_id; 4626 __le16 queue_id; 4627 __le16 rx_buf_size; 4628 __le16 rx_ring_id; 4629 __le16 nq_ring_id; 4630 __le16 ring_arb_cfg; 4631 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 4632 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 4633 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 4634 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 4635 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 4636 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 4637 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 4638 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 4639 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 4640 __le16 unused_3; 4641 __le32 reserved3; 4642 __le32 stat_ctx_id; 4643 __le32 reserved4; 4644 __le32 max_bw; 4645 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4646 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 4647 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 4648 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 4649 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 4650 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 4651 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4652 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 4653 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4654 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4655 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4656 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4657 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4658 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4659 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 4660 u8 int_mode; 4661 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 4662 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 4663 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 4664 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 4665 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 4666 u8 unused_4[3]; 4667 __le64 cq_handle; 4668 }; 4669 4670 /* hwrm_ring_alloc_output (size:128b/16B) */ 4671 struct hwrm_ring_alloc_output { 4672 __le16 error_code; 4673 __le16 req_type; 4674 __le16 seq_id; 4675 __le16 resp_len; 4676 __le16 ring_id; 4677 __le16 logical_ring_id; 4678 u8 unused_0[3]; 4679 u8 valid; 4680 }; 4681 4682 /* hwrm_ring_free_input (size:192b/24B) */ 4683 struct hwrm_ring_free_input { 4684 __le16 req_type; 4685 __le16 cmpl_ring; 4686 __le16 seq_id; 4687 __le16 target_id; 4688 __le64 resp_addr; 4689 u8 ring_type; 4690 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 4691 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 4692 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 4693 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4694 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 4695 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 4696 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 4697 u8 unused_0; 4698 __le16 ring_id; 4699 u8 unused_1[4]; 4700 }; 4701 4702 /* hwrm_ring_free_output (size:128b/16B) */ 4703 struct hwrm_ring_free_output { 4704 __le16 error_code; 4705 __le16 req_type; 4706 __le16 seq_id; 4707 __le16 resp_len; 4708 u8 unused_0[7]; 4709 u8 valid; 4710 }; 4711 4712 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 4713 struct hwrm_ring_aggint_qcaps_input { 4714 __le16 req_type; 4715 __le16 cmpl_ring; 4716 __le16 seq_id; 4717 __le16 target_id; 4718 __le64 resp_addr; 4719 }; 4720 4721 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 4722 struct hwrm_ring_aggint_qcaps_output { 4723 __le16 error_code; 4724 __le16 req_type; 4725 __le16 seq_id; 4726 __le16 resp_len; 4727 __le32 cmpl_params; 4728 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 4729 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 4730 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 4731 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 4732 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 4733 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 4734 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 4735 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 4736 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 4737 __le32 nq_params; 4738 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 4739 __le16 num_cmpl_dma_aggr_min; 4740 __le16 num_cmpl_dma_aggr_max; 4741 __le16 num_cmpl_dma_aggr_during_int_min; 4742 __le16 num_cmpl_dma_aggr_during_int_max; 4743 __le16 cmpl_aggr_dma_tmr_min; 4744 __le16 cmpl_aggr_dma_tmr_max; 4745 __le16 cmpl_aggr_dma_tmr_during_int_min; 4746 __le16 cmpl_aggr_dma_tmr_during_int_max; 4747 __le16 int_lat_tmr_min_min; 4748 __le16 int_lat_tmr_min_max; 4749 __le16 int_lat_tmr_max_min; 4750 __le16 int_lat_tmr_max_max; 4751 __le16 num_cmpl_aggr_int_min; 4752 __le16 num_cmpl_aggr_int_max; 4753 __le16 timer_units; 4754 u8 unused_0[1]; 4755 u8 valid; 4756 }; 4757 4758 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 4759 struct hwrm_ring_cmpl_ring_qaggint_params_input { 4760 __le16 req_type; 4761 __le16 cmpl_ring; 4762 __le16 seq_id; 4763 __le16 target_id; 4764 __le64 resp_addr; 4765 __le16 ring_id; 4766 u8 unused_0[6]; 4767 }; 4768 4769 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 4770 struct hwrm_ring_cmpl_ring_qaggint_params_output { 4771 __le16 error_code; 4772 __le16 req_type; 4773 __le16 seq_id; 4774 __le16 resp_len; 4775 __le16 flags; 4776 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 4777 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 4778 __le16 num_cmpl_dma_aggr; 4779 __le16 num_cmpl_dma_aggr_during_int; 4780 __le16 cmpl_aggr_dma_tmr; 4781 __le16 cmpl_aggr_dma_tmr_during_int; 4782 __le16 int_lat_tmr_min; 4783 __le16 int_lat_tmr_max; 4784 __le16 num_cmpl_aggr_int; 4785 u8 unused_0[7]; 4786 u8 valid; 4787 }; 4788 4789 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 4790 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 4791 __le16 req_type; 4792 __le16 cmpl_ring; 4793 __le16 seq_id; 4794 __le16 target_id; 4795 __le64 resp_addr; 4796 __le16 ring_id; 4797 __le16 flags; 4798 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 4799 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 4800 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 4801 __le16 num_cmpl_dma_aggr; 4802 __le16 num_cmpl_dma_aggr_during_int; 4803 __le16 cmpl_aggr_dma_tmr; 4804 __le16 cmpl_aggr_dma_tmr_during_int; 4805 __le16 int_lat_tmr_min; 4806 __le16 int_lat_tmr_max; 4807 __le16 num_cmpl_aggr_int; 4808 __le16 enables; 4809 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 4810 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 4811 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 4812 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 4813 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 4814 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 4815 u8 unused_0[4]; 4816 }; 4817 4818 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 4819 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 4820 __le16 error_code; 4821 __le16 req_type; 4822 __le16 seq_id; 4823 __le16 resp_len; 4824 u8 unused_0[7]; 4825 u8 valid; 4826 }; 4827 4828 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 4829 struct hwrm_ring_grp_alloc_input { 4830 __le16 req_type; 4831 __le16 cmpl_ring; 4832 __le16 seq_id; 4833 __le16 target_id; 4834 __le64 resp_addr; 4835 __le16 cr; 4836 __le16 rr; 4837 __le16 ar; 4838 __le16 sc; 4839 }; 4840 4841 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 4842 struct hwrm_ring_grp_alloc_output { 4843 __le16 error_code; 4844 __le16 req_type; 4845 __le16 seq_id; 4846 __le16 resp_len; 4847 __le32 ring_group_id; 4848 u8 unused_0[3]; 4849 u8 valid; 4850 }; 4851 4852 /* hwrm_ring_grp_free_input (size:192b/24B) */ 4853 struct hwrm_ring_grp_free_input { 4854 __le16 req_type; 4855 __le16 cmpl_ring; 4856 __le16 seq_id; 4857 __le16 target_id; 4858 __le64 resp_addr; 4859 __le32 ring_group_id; 4860 u8 unused_0[4]; 4861 }; 4862 4863 /* hwrm_ring_grp_free_output (size:128b/16B) */ 4864 struct hwrm_ring_grp_free_output { 4865 __le16 error_code; 4866 __le16 req_type; 4867 __le16 seq_id; 4868 __le16 resp_len; 4869 u8 unused_0[7]; 4870 u8 valid; 4871 }; 4872 4873 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 4874 struct hwrm_cfa_l2_filter_alloc_input { 4875 __le16 req_type; 4876 __le16 cmpl_ring; 4877 __le16 seq_id; 4878 __le16 target_id; 4879 __le64 resp_addr; 4880 __le32 flags; 4881 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 4882 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 4883 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 4884 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 4885 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 4886 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 4887 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 4888 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 4889 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 4890 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 4891 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 4892 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 4893 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 4894 __le32 enables; 4895 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 4896 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 4897 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 4898 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 4899 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 4900 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 4901 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 4902 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 4903 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 4904 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 4905 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 4906 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 4907 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 4908 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 4909 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 4910 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4911 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4912 u8 l2_addr[6]; 4913 u8 unused_0[2]; 4914 u8 l2_addr_mask[6]; 4915 __le16 l2_ovlan; 4916 __le16 l2_ovlan_mask; 4917 __le16 l2_ivlan; 4918 __le16 l2_ivlan_mask; 4919 u8 unused_1[2]; 4920 u8 t_l2_addr[6]; 4921 u8 unused_2[2]; 4922 u8 t_l2_addr_mask[6]; 4923 __le16 t_l2_ovlan; 4924 __le16 t_l2_ovlan_mask; 4925 __le16 t_l2_ivlan; 4926 __le16 t_l2_ivlan_mask; 4927 u8 src_type; 4928 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 4929 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 4930 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 4931 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 4932 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 4933 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 4934 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 4935 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 4936 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 4937 u8 unused_3; 4938 __le32 src_id; 4939 u8 tunnel_type; 4940 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4941 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4942 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4943 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4944 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4945 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4946 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4947 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4948 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4949 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4950 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 4951 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 4952 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4953 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4954 u8 unused_4; 4955 __le16 dst_id; 4956 __le16 mirror_vnic_id; 4957 u8 pri_hint; 4958 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4959 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 4960 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 4961 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4962 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4963 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 4964 u8 unused_5; 4965 __le32 unused_6; 4966 __le64 l2_filter_id_hint; 4967 }; 4968 4969 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 4970 struct hwrm_cfa_l2_filter_alloc_output { 4971 __le16 error_code; 4972 __le16 req_type; 4973 __le16 seq_id; 4974 __le16 resp_len; 4975 __le64 l2_filter_id; 4976 __le32 flow_id; 4977 u8 unused_0[3]; 4978 u8 valid; 4979 }; 4980 4981 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 4982 struct hwrm_cfa_l2_filter_free_input { 4983 __le16 req_type; 4984 __le16 cmpl_ring; 4985 __le16 seq_id; 4986 __le16 target_id; 4987 __le64 resp_addr; 4988 __le64 l2_filter_id; 4989 }; 4990 4991 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 4992 struct hwrm_cfa_l2_filter_free_output { 4993 __le16 error_code; 4994 __le16 req_type; 4995 __le16 seq_id; 4996 __le16 resp_len; 4997 u8 unused_0[7]; 4998 u8 valid; 4999 }; 5000 5001 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5002 struct hwrm_cfa_l2_filter_cfg_input { 5003 __le16 req_type; 5004 __le16 cmpl_ring; 5005 __le16 seq_id; 5006 __le16 target_id; 5007 __le64 resp_addr; 5008 __le32 flags; 5009 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5010 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5011 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5012 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5013 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5014 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5015 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5016 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5017 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5018 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5019 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5020 __le32 enables; 5021 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5022 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5023 __le64 l2_filter_id; 5024 __le32 dst_id; 5025 __le32 new_mirror_vnic_id; 5026 }; 5027 5028 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5029 struct hwrm_cfa_l2_filter_cfg_output { 5030 __le16 error_code; 5031 __le16 req_type; 5032 __le16 seq_id; 5033 __le16 resp_len; 5034 u8 unused_0[7]; 5035 u8 valid; 5036 }; 5037 5038 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5039 struct hwrm_cfa_l2_set_rx_mask_input { 5040 __le16 req_type; 5041 __le16 cmpl_ring; 5042 __le16 seq_id; 5043 __le16 target_id; 5044 __le64 resp_addr; 5045 __le32 vnic_id; 5046 __le32 mask; 5047 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5048 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5049 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5050 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5051 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5052 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5053 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5054 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5055 __le64 mc_tbl_addr; 5056 __le32 num_mc_entries; 5057 u8 unused_0[4]; 5058 __le64 vlan_tag_tbl_addr; 5059 __le32 num_vlan_tags; 5060 u8 unused_1[4]; 5061 }; 5062 5063 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5064 struct hwrm_cfa_l2_set_rx_mask_output { 5065 __le16 error_code; 5066 __le16 req_type; 5067 __le16 seq_id; 5068 __le16 resp_len; 5069 u8 unused_0[7]; 5070 u8 valid; 5071 }; 5072 5073 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5074 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5075 u8 code; 5076 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5077 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5078 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5079 u8 unused_0[7]; 5080 }; 5081 5082 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5083 struct hwrm_cfa_tunnel_filter_alloc_input { 5084 __le16 req_type; 5085 __le16 cmpl_ring; 5086 __le16 seq_id; 5087 __le16 target_id; 5088 __le64 resp_addr; 5089 __le32 flags; 5090 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5091 __le32 enables; 5092 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5093 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5094 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5095 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5096 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5097 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5098 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5099 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5100 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5101 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5102 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5103 __le64 l2_filter_id; 5104 u8 l2_addr[6]; 5105 __le16 l2_ivlan; 5106 __le32 l3_addr[4]; 5107 __le32 t_l3_addr[4]; 5108 u8 l3_addr_type; 5109 u8 t_l3_addr_type; 5110 u8 tunnel_type; 5111 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5112 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5113 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5114 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5115 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5116 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5117 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5118 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5119 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5120 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5121 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5122 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5123 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5124 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5125 u8 tunnel_flags; 5126 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5127 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5128 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5129 __le32 vni; 5130 __le32 dst_vnic_id; 5131 __le32 mirror_vnic_id; 5132 }; 5133 5134 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5135 struct hwrm_cfa_tunnel_filter_alloc_output { 5136 __le16 error_code; 5137 __le16 req_type; 5138 __le16 seq_id; 5139 __le16 resp_len; 5140 __le64 tunnel_filter_id; 5141 __le32 flow_id; 5142 u8 unused_0[3]; 5143 u8 valid; 5144 }; 5145 5146 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5147 struct hwrm_cfa_tunnel_filter_free_input { 5148 __le16 req_type; 5149 __le16 cmpl_ring; 5150 __le16 seq_id; 5151 __le16 target_id; 5152 __le64 resp_addr; 5153 __le64 tunnel_filter_id; 5154 }; 5155 5156 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5157 struct hwrm_cfa_tunnel_filter_free_output { 5158 __le16 error_code; 5159 __le16 req_type; 5160 __le16 seq_id; 5161 __le16 resp_len; 5162 u8 unused_0[7]; 5163 u8 valid; 5164 }; 5165 5166 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5167 struct hwrm_vxlan_ipv4_hdr { 5168 u8 ver_hlen; 5169 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5170 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5171 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5172 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 5173 u8 tos; 5174 __be16 ip_id; 5175 __be16 flags_frag_offset; 5176 u8 ttl; 5177 u8 protocol; 5178 __be32 src_ip_addr; 5179 __be32 dest_ip_addr; 5180 }; 5181 5182 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 5183 struct hwrm_vxlan_ipv6_hdr { 5184 __be32 ver_tc_flow_label; 5185 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 5186 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 5187 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 5188 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 5189 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 5190 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 5191 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 5192 __be16 payload_len; 5193 u8 next_hdr; 5194 u8 ttl; 5195 __be32 src_ip_addr[4]; 5196 __be32 dest_ip_addr[4]; 5197 }; 5198 5199 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 5200 struct hwrm_cfa_encap_data_vxlan { 5201 u8 src_mac_addr[6]; 5202 __le16 unused_0; 5203 u8 dst_mac_addr[6]; 5204 u8 num_vlan_tags; 5205 u8 unused_1; 5206 __be16 ovlan_tpid; 5207 __be16 ovlan_tci; 5208 __be16 ivlan_tpid; 5209 __be16 ivlan_tci; 5210 __le32 l3[10]; 5211 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 5212 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 5213 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 5214 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 5215 __be16 src_port; 5216 __be16 dst_port; 5217 __be32 vni; 5218 u8 hdr_rsvd0[3]; 5219 u8 hdr_rsvd1; 5220 u8 hdr_flags; 5221 u8 unused[3]; 5222 }; 5223 5224 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 5225 struct hwrm_cfa_encap_record_alloc_input { 5226 __le16 req_type; 5227 __le16 cmpl_ring; 5228 __le16 seq_id; 5229 __le16 target_id; 5230 __le64 resp_addr; 5231 __le32 flags; 5232 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5233 u8 encap_type; 5234 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 5235 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 5236 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 5237 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 5238 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 5239 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 5240 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 5241 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 5242 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 5243 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 5244 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 5245 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 5246 u8 unused_0[3]; 5247 __le32 encap_data[20]; 5248 }; 5249 5250 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 5251 struct hwrm_cfa_encap_record_alloc_output { 5252 __le16 error_code; 5253 __le16 req_type; 5254 __le16 seq_id; 5255 __le16 resp_len; 5256 __le32 encap_record_id; 5257 u8 unused_0[3]; 5258 u8 valid; 5259 }; 5260 5261 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 5262 struct hwrm_cfa_encap_record_free_input { 5263 __le16 req_type; 5264 __le16 cmpl_ring; 5265 __le16 seq_id; 5266 __le16 target_id; 5267 __le64 resp_addr; 5268 __le32 encap_record_id; 5269 u8 unused_0[4]; 5270 }; 5271 5272 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 5273 struct hwrm_cfa_encap_record_free_output { 5274 __le16 error_code; 5275 __le16 req_type; 5276 __le16 seq_id; 5277 __le16 resp_len; 5278 u8 unused_0[7]; 5279 u8 valid; 5280 }; 5281 5282 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 5283 struct hwrm_cfa_ntuple_filter_alloc_input { 5284 __le16 req_type; 5285 __le16 cmpl_ring; 5286 __le16 seq_id; 5287 __le16 target_id; 5288 __le64 resp_addr; 5289 __le32 flags; 5290 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5291 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 5292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 5293 __le32 enables; 5294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5295 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 5296 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 5297 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 5298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 5299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 5300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 5301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 5302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 5303 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 5304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 5305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 5306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 5307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 5308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 5309 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 5310 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 5311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 5312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 5313 __le64 l2_filter_id; 5314 u8 src_macaddr[6]; 5315 __be16 ethertype; 5316 u8 ip_addr_type; 5317 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5321 u8 ip_protocol; 5322 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5325 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5326 __le16 dst_id; 5327 __le16 mirror_vnic_id; 5328 u8 tunnel_type; 5329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5333 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5334 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5335 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5336 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5338 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5339 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5340 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5343 u8 pri_hint; 5344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 5346 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 5347 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 5348 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 5349 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 5350 __be32 src_ipaddr[4]; 5351 __be32 src_ipaddr_mask[4]; 5352 __be32 dst_ipaddr[4]; 5353 __be32 dst_ipaddr_mask[4]; 5354 __be16 src_port; 5355 __be16 src_port_mask; 5356 __be16 dst_port; 5357 __be16 dst_port_mask; 5358 __le64 ntuple_filter_id_hint; 5359 }; 5360 5361 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 5362 struct hwrm_cfa_ntuple_filter_alloc_output { 5363 __le16 error_code; 5364 __le16 req_type; 5365 __le16 seq_id; 5366 __le16 resp_len; 5367 __le64 ntuple_filter_id; 5368 __le32 flow_id; 5369 u8 unused_0[3]; 5370 u8 valid; 5371 }; 5372 5373 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 5374 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 5375 u8 code; 5376 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 5377 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 5378 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 5379 u8 unused_0[7]; 5380 }; 5381 5382 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 5383 struct hwrm_cfa_ntuple_filter_free_input { 5384 __le16 req_type; 5385 __le16 cmpl_ring; 5386 __le16 seq_id; 5387 __le16 target_id; 5388 __le64 resp_addr; 5389 __le64 ntuple_filter_id; 5390 }; 5391 5392 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 5393 struct hwrm_cfa_ntuple_filter_free_output { 5394 __le16 error_code; 5395 __le16 req_type; 5396 __le16 seq_id; 5397 __le16 resp_len; 5398 u8 unused_0[7]; 5399 u8 valid; 5400 }; 5401 5402 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 5403 struct hwrm_cfa_ntuple_filter_cfg_input { 5404 __le16 req_type; 5405 __le16 cmpl_ring; 5406 __le16 seq_id; 5407 __le16 target_id; 5408 __le64 resp_addr; 5409 __le32 enables; 5410 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 5411 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5412 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 5413 u8 unused_0[4]; 5414 __le64 ntuple_filter_id; 5415 __le32 new_dst_id; 5416 __le32 new_mirror_vnic_id; 5417 __le16 new_meter_instance_id; 5418 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 5419 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 5420 u8 unused_1[6]; 5421 }; 5422 5423 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 5424 struct hwrm_cfa_ntuple_filter_cfg_output { 5425 __le16 error_code; 5426 __le16 req_type; 5427 __le16 seq_id; 5428 __le16 resp_len; 5429 u8 unused_0[7]; 5430 u8 valid; 5431 }; 5432 5433 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 5434 struct hwrm_cfa_decap_filter_alloc_input { 5435 __le16 req_type; 5436 __le16 cmpl_ring; 5437 __le16 seq_id; 5438 __le16 target_id; 5439 __le64 resp_addr; 5440 __le32 flags; 5441 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 5442 __le32 enables; 5443 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 5444 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 5445 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 5446 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 5447 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 5448 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 5449 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 5450 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 5451 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 5452 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 5453 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 5454 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 5455 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 5456 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 5457 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 5458 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5459 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5460 __be32 tunnel_id; 5461 u8 tunnel_type; 5462 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5463 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5464 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5465 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5466 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5467 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5468 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5469 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5470 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5471 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5472 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5473 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5474 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5475 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5476 u8 unused_0; 5477 __le16 unused_1; 5478 u8 src_macaddr[6]; 5479 u8 unused_2[2]; 5480 u8 dst_macaddr[6]; 5481 __be16 ovlan_vid; 5482 __be16 ivlan_vid; 5483 __be16 t_ovlan_vid; 5484 __be16 t_ivlan_vid; 5485 __be16 ethertype; 5486 u8 ip_addr_type; 5487 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5488 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5489 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5490 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5491 u8 ip_protocol; 5492 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5493 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5494 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5495 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5496 __le16 unused_3; 5497 __le32 unused_4; 5498 __be32 src_ipaddr[4]; 5499 __be32 dst_ipaddr[4]; 5500 __be16 src_port; 5501 __be16 dst_port; 5502 __le16 dst_id; 5503 __le16 l2_ctxt_ref_id; 5504 }; 5505 5506 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 5507 struct hwrm_cfa_decap_filter_alloc_output { 5508 __le16 error_code; 5509 __le16 req_type; 5510 __le16 seq_id; 5511 __le16 resp_len; 5512 __le32 decap_filter_id; 5513 u8 unused_0[3]; 5514 u8 valid; 5515 }; 5516 5517 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 5518 struct hwrm_cfa_decap_filter_free_input { 5519 __le16 req_type; 5520 __le16 cmpl_ring; 5521 __le16 seq_id; 5522 __le16 target_id; 5523 __le64 resp_addr; 5524 __le32 decap_filter_id; 5525 u8 unused_0[4]; 5526 }; 5527 5528 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 5529 struct hwrm_cfa_decap_filter_free_output { 5530 __le16 error_code; 5531 __le16 req_type; 5532 __le16 seq_id; 5533 __le16 resp_len; 5534 u8 unused_0[7]; 5535 u8 valid; 5536 }; 5537 5538 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 5539 struct hwrm_cfa_flow_alloc_input { 5540 __le16 req_type; 5541 __le16 cmpl_ring; 5542 __le16 seq_id; 5543 __le16 target_id; 5544 __le64 resp_addr; 5545 __le16 flags; 5546 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 5547 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 5548 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 5549 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 5550 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 5551 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 5552 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 5553 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 5554 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 5555 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 5556 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 5557 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 5558 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 5559 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 5560 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 5561 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 5562 __le16 src_fid; 5563 __le32 tunnel_handle; 5564 __le16 action_flags; 5565 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 5566 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 5567 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 5568 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 5569 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 5570 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 5571 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 5572 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 5573 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 5574 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 5575 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 5576 __le16 dst_fid; 5577 __be16 l2_rewrite_vlan_tpid; 5578 __be16 l2_rewrite_vlan_tci; 5579 __le16 act_meter_id; 5580 __le16 ref_flow_handle; 5581 __be16 ethertype; 5582 __be16 outer_vlan_tci; 5583 __be16 dmac[3]; 5584 __be16 inner_vlan_tci; 5585 __be16 smac[3]; 5586 u8 ip_dst_mask_len; 5587 u8 ip_src_mask_len; 5588 __be32 ip_dst[4]; 5589 __be32 ip_src[4]; 5590 __be16 l4_src_port; 5591 __be16 l4_src_port_mask; 5592 __be16 l4_dst_port; 5593 __be16 l4_dst_port_mask; 5594 __be32 nat_ip_address[4]; 5595 __be16 l2_rewrite_dmac[3]; 5596 __be16 nat_port; 5597 __be16 l2_rewrite_smac[3]; 5598 u8 ip_proto; 5599 u8 tunnel_type; 5600 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5601 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5602 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5603 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5604 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5605 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5606 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5607 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5608 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5609 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5610 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5611 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5612 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5613 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5614 }; 5615 5616 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 5617 struct hwrm_cfa_flow_alloc_output { 5618 __le16 error_code; 5619 __le16 req_type; 5620 __le16 seq_id; 5621 __le16 resp_len; 5622 __le16 flow_handle; 5623 u8 unused_0[2]; 5624 __le32 flow_id; 5625 __le64 ext_flow_handle; 5626 u8 unused_1[7]; 5627 u8 valid; 5628 }; 5629 5630 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 5631 struct hwrm_cfa_flow_free_input { 5632 __le16 req_type; 5633 __le16 cmpl_ring; 5634 __le16 seq_id; 5635 __le16 target_id; 5636 __le64 resp_addr; 5637 __le16 flow_handle; 5638 u8 unused_0[6]; 5639 __le64 ext_flow_handle; 5640 }; 5641 5642 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 5643 struct hwrm_cfa_flow_free_output { 5644 __le16 error_code; 5645 __le16 req_type; 5646 __le16 seq_id; 5647 __le16 resp_len; 5648 __le64 packet; 5649 __le64 byte; 5650 u8 unused_0[7]; 5651 u8 valid; 5652 }; 5653 5654 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 5655 struct hwrm_cfa_flow_stats_input { 5656 __le16 req_type; 5657 __le16 cmpl_ring; 5658 __le16 seq_id; 5659 __le16 target_id; 5660 __le64 resp_addr; 5661 __le16 num_flows; 5662 __le16 flow_handle_0; 5663 __le16 flow_handle_1; 5664 __le16 flow_handle_2; 5665 __le16 flow_handle_3; 5666 __le16 flow_handle_4; 5667 __le16 flow_handle_5; 5668 __le16 flow_handle_6; 5669 __le16 flow_handle_7; 5670 __le16 flow_handle_8; 5671 __le16 flow_handle_9; 5672 u8 unused_0[2]; 5673 __le32 flow_id_0; 5674 __le32 flow_id_1; 5675 __le32 flow_id_2; 5676 __le32 flow_id_3; 5677 __le32 flow_id_4; 5678 __le32 flow_id_5; 5679 __le32 flow_id_6; 5680 __le32 flow_id_7; 5681 __le32 flow_id_8; 5682 __le32 flow_id_9; 5683 }; 5684 5685 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 5686 struct hwrm_cfa_flow_stats_output { 5687 __le16 error_code; 5688 __le16 req_type; 5689 __le16 seq_id; 5690 __le16 resp_len; 5691 __le64 packet_0; 5692 __le64 packet_1; 5693 __le64 packet_2; 5694 __le64 packet_3; 5695 __le64 packet_4; 5696 __le64 packet_5; 5697 __le64 packet_6; 5698 __le64 packet_7; 5699 __le64 packet_8; 5700 __le64 packet_9; 5701 __le64 byte_0; 5702 __le64 byte_1; 5703 __le64 byte_2; 5704 __le64 byte_3; 5705 __le64 byte_4; 5706 __le64 byte_5; 5707 __le64 byte_6; 5708 __le64 byte_7; 5709 __le64 byte_8; 5710 __le64 byte_9; 5711 u8 unused_0[7]; 5712 u8 valid; 5713 }; 5714 5715 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 5716 struct hwrm_cfa_vfr_alloc_input { 5717 __le16 req_type; 5718 __le16 cmpl_ring; 5719 __le16 seq_id; 5720 __le16 target_id; 5721 __le64 resp_addr; 5722 __le16 vf_id; 5723 __le16 reserved; 5724 u8 unused_0[4]; 5725 char vfr_name[32]; 5726 }; 5727 5728 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 5729 struct hwrm_cfa_vfr_alloc_output { 5730 __le16 error_code; 5731 __le16 req_type; 5732 __le16 seq_id; 5733 __le16 resp_len; 5734 __le16 rx_cfa_code; 5735 __le16 tx_cfa_action; 5736 u8 unused_0[3]; 5737 u8 valid; 5738 }; 5739 5740 /* hwrm_cfa_vfr_free_input (size:384b/48B) */ 5741 struct hwrm_cfa_vfr_free_input { 5742 __le16 req_type; 5743 __le16 cmpl_ring; 5744 __le16 seq_id; 5745 __le16 target_id; 5746 __le64 resp_addr; 5747 char vfr_name[32]; 5748 }; 5749 5750 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 5751 struct hwrm_cfa_vfr_free_output { 5752 __le16 error_code; 5753 __le16 req_type; 5754 __le16 seq_id; 5755 __le16 resp_len; 5756 u8 unused_0[7]; 5757 u8 valid; 5758 }; 5759 5760 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 5761 struct hwrm_tunnel_dst_port_query_input { 5762 __le16 req_type; 5763 __le16 cmpl_ring; 5764 __le16 seq_id; 5765 __le16 target_id; 5766 __le64 resp_addr; 5767 u8 tunnel_type; 5768 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5769 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5770 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5771 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5772 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5773 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 5774 u8 unused_0[7]; 5775 }; 5776 5777 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 5778 struct hwrm_tunnel_dst_port_query_output { 5779 __le16 error_code; 5780 __le16 req_type; 5781 __le16 seq_id; 5782 __le16 resp_len; 5783 __le16 tunnel_dst_port_id; 5784 __be16 tunnel_dst_port_val; 5785 u8 unused_0[3]; 5786 u8 valid; 5787 }; 5788 5789 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 5790 struct hwrm_tunnel_dst_port_alloc_input { 5791 __le16 req_type; 5792 __le16 cmpl_ring; 5793 __le16 seq_id; 5794 __le16 target_id; 5795 __le64 resp_addr; 5796 u8 tunnel_type; 5797 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5798 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5799 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5800 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5801 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5802 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 5803 u8 unused_0; 5804 __be16 tunnel_dst_port_val; 5805 u8 unused_1[4]; 5806 }; 5807 5808 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 5809 struct hwrm_tunnel_dst_port_alloc_output { 5810 __le16 error_code; 5811 __le16 req_type; 5812 __le16 seq_id; 5813 __le16 resp_len; 5814 __le16 tunnel_dst_port_id; 5815 u8 unused_0[5]; 5816 u8 valid; 5817 }; 5818 5819 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 5820 struct hwrm_tunnel_dst_port_free_input { 5821 __le16 req_type; 5822 __le16 cmpl_ring; 5823 __le16 seq_id; 5824 __le16 target_id; 5825 __le64 resp_addr; 5826 u8 tunnel_type; 5827 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5828 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5829 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5830 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5831 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5832 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 5833 u8 unused_0; 5834 __le16 tunnel_dst_port_id; 5835 u8 unused_1[4]; 5836 }; 5837 5838 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 5839 struct hwrm_tunnel_dst_port_free_output { 5840 __le16 error_code; 5841 __le16 req_type; 5842 __le16 seq_id; 5843 __le16 resp_len; 5844 u8 unused_1[7]; 5845 u8 valid; 5846 }; 5847 5848 /* ctx_hw_stats (size:1280b/160B) */ 5849 struct ctx_hw_stats { 5850 __le64 rx_ucast_pkts; 5851 __le64 rx_mcast_pkts; 5852 __le64 rx_bcast_pkts; 5853 __le64 rx_discard_pkts; 5854 __le64 rx_drop_pkts; 5855 __le64 rx_ucast_bytes; 5856 __le64 rx_mcast_bytes; 5857 __le64 rx_bcast_bytes; 5858 __le64 tx_ucast_pkts; 5859 __le64 tx_mcast_pkts; 5860 __le64 tx_bcast_pkts; 5861 __le64 tx_discard_pkts; 5862 __le64 tx_drop_pkts; 5863 __le64 tx_ucast_bytes; 5864 __le64 tx_mcast_bytes; 5865 __le64 tx_bcast_bytes; 5866 __le64 tpa_pkts; 5867 __le64 tpa_bytes; 5868 __le64 tpa_events; 5869 __le64 tpa_aborts; 5870 }; 5871 5872 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 5873 struct hwrm_stat_ctx_alloc_input { 5874 __le16 req_type; 5875 __le16 cmpl_ring; 5876 __le16 seq_id; 5877 __le16 target_id; 5878 __le64 resp_addr; 5879 __le64 stats_dma_addr; 5880 __le32 update_period_ms; 5881 u8 stat_ctx_flags; 5882 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 5883 u8 unused_0[3]; 5884 }; 5885 5886 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 5887 struct hwrm_stat_ctx_alloc_output { 5888 __le16 error_code; 5889 __le16 req_type; 5890 __le16 seq_id; 5891 __le16 resp_len; 5892 __le32 stat_ctx_id; 5893 u8 unused_0[3]; 5894 u8 valid; 5895 }; 5896 5897 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 5898 struct hwrm_stat_ctx_free_input { 5899 __le16 req_type; 5900 __le16 cmpl_ring; 5901 __le16 seq_id; 5902 __le16 target_id; 5903 __le64 resp_addr; 5904 __le32 stat_ctx_id; 5905 u8 unused_0[4]; 5906 }; 5907 5908 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 5909 struct hwrm_stat_ctx_free_output { 5910 __le16 error_code; 5911 __le16 req_type; 5912 __le16 seq_id; 5913 __le16 resp_len; 5914 __le32 stat_ctx_id; 5915 u8 unused_0[3]; 5916 u8 valid; 5917 }; 5918 5919 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 5920 struct hwrm_stat_ctx_query_input { 5921 __le16 req_type; 5922 __le16 cmpl_ring; 5923 __le16 seq_id; 5924 __le16 target_id; 5925 __le64 resp_addr; 5926 __le32 stat_ctx_id; 5927 u8 unused_0[4]; 5928 }; 5929 5930 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 5931 struct hwrm_stat_ctx_query_output { 5932 __le16 error_code; 5933 __le16 req_type; 5934 __le16 seq_id; 5935 __le16 resp_len; 5936 __le64 tx_ucast_pkts; 5937 __le64 tx_mcast_pkts; 5938 __le64 tx_bcast_pkts; 5939 __le64 tx_err_pkts; 5940 __le64 tx_drop_pkts; 5941 __le64 tx_ucast_bytes; 5942 __le64 tx_mcast_bytes; 5943 __le64 tx_bcast_bytes; 5944 __le64 rx_ucast_pkts; 5945 __le64 rx_mcast_pkts; 5946 __le64 rx_bcast_pkts; 5947 __le64 rx_err_pkts; 5948 __le64 rx_drop_pkts; 5949 __le64 rx_ucast_bytes; 5950 __le64 rx_mcast_bytes; 5951 __le64 rx_bcast_bytes; 5952 __le64 rx_agg_pkts; 5953 __le64 rx_agg_bytes; 5954 __le64 rx_agg_events; 5955 __le64 rx_agg_aborts; 5956 u8 unused_0[7]; 5957 u8 valid; 5958 }; 5959 5960 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 5961 struct hwrm_stat_ctx_clr_stats_input { 5962 __le16 req_type; 5963 __le16 cmpl_ring; 5964 __le16 seq_id; 5965 __le16 target_id; 5966 __le64 resp_addr; 5967 __le32 stat_ctx_id; 5968 u8 unused_0[4]; 5969 }; 5970 5971 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 5972 struct hwrm_stat_ctx_clr_stats_output { 5973 __le16 error_code; 5974 __le16 req_type; 5975 __le16 seq_id; 5976 __le16 resp_len; 5977 u8 unused_0[7]; 5978 u8 valid; 5979 }; 5980 5981 /* hwrm_pcie_qstats_input (size:256b/32B) */ 5982 struct hwrm_pcie_qstats_input { 5983 __le16 req_type; 5984 __le16 cmpl_ring; 5985 __le16 seq_id; 5986 __le16 target_id; 5987 __le64 resp_addr; 5988 __le16 pcie_stat_size; 5989 u8 unused_0[6]; 5990 __le64 pcie_stat_host_addr; 5991 }; 5992 5993 /* hwrm_pcie_qstats_output (size:128b/16B) */ 5994 struct hwrm_pcie_qstats_output { 5995 __le16 error_code; 5996 __le16 req_type; 5997 __le16 seq_id; 5998 __le16 resp_len; 5999 __le16 pcie_stat_size; 6000 u8 unused_0[5]; 6001 u8 valid; 6002 }; 6003 6004 /* pcie_ctx_hw_stats (size:768b/96B) */ 6005 struct pcie_ctx_hw_stats { 6006 __le64 pcie_pl_signal_integrity; 6007 __le64 pcie_dl_signal_integrity; 6008 __le64 pcie_tl_signal_integrity; 6009 __le64 pcie_link_integrity; 6010 __le64 pcie_tx_traffic_rate; 6011 __le64 pcie_rx_traffic_rate; 6012 __le64 pcie_tx_dllp_statistics; 6013 __le64 pcie_rx_dllp_statistics; 6014 __le64 pcie_equalization_time; 6015 __le32 pcie_ltssm_histogram[4]; 6016 __le64 pcie_recovery_histogram; 6017 }; 6018 6019 /* hwrm_fw_reset_input (size:192b/24B) */ 6020 struct hwrm_fw_reset_input { 6021 __le16 req_type; 6022 __le16 cmpl_ring; 6023 __le16 seq_id; 6024 __le16 target_id; 6025 __le64 resp_addr; 6026 u8 embedded_proc_type; 6027 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6028 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6029 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6030 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6031 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6032 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6033 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6034 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 6035 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 6036 u8 selfrst_status; 6037 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 6038 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 6039 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6040 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6041 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 6042 u8 host_idx; 6043 u8 unused_0[5]; 6044 }; 6045 6046 /* hwrm_fw_reset_output (size:128b/16B) */ 6047 struct hwrm_fw_reset_output { 6048 __le16 error_code; 6049 __le16 req_type; 6050 __le16 seq_id; 6051 __le16 resp_len; 6052 u8 selfrst_status; 6053 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6054 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6055 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6056 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6057 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 6058 u8 unused_0[6]; 6059 u8 valid; 6060 }; 6061 6062 /* hwrm_fw_qstatus_input (size:192b/24B) */ 6063 struct hwrm_fw_qstatus_input { 6064 __le16 req_type; 6065 __le16 cmpl_ring; 6066 __le16 seq_id; 6067 __le16 target_id; 6068 __le64 resp_addr; 6069 u8 embedded_proc_type; 6070 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6071 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6072 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6073 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6074 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6075 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6076 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6077 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 6078 u8 unused_0[7]; 6079 }; 6080 6081 /* hwrm_fw_qstatus_output (size:128b/16B) */ 6082 struct hwrm_fw_qstatus_output { 6083 __le16 error_code; 6084 __le16 req_type; 6085 __le16 seq_id; 6086 __le16 resp_len; 6087 u8 selfrst_status; 6088 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6089 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6090 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6091 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 6092 u8 unused_0[6]; 6093 u8 valid; 6094 }; 6095 6096 /* hwrm_fw_set_time_input (size:256b/32B) */ 6097 struct hwrm_fw_set_time_input { 6098 __le16 req_type; 6099 __le16 cmpl_ring; 6100 __le16 seq_id; 6101 __le16 target_id; 6102 __le64 resp_addr; 6103 __le16 year; 6104 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 6105 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 6106 u8 month; 6107 u8 day; 6108 u8 hour; 6109 u8 minute; 6110 u8 second; 6111 u8 unused_0; 6112 __le16 millisecond; 6113 __le16 zone; 6114 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 6115 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 6116 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 6117 u8 unused_1[4]; 6118 }; 6119 6120 /* hwrm_fw_set_time_output (size:128b/16B) */ 6121 struct hwrm_fw_set_time_output { 6122 __le16 error_code; 6123 __le16 req_type; 6124 __le16 seq_id; 6125 __le16 resp_len; 6126 u8 unused_0[7]; 6127 u8 valid; 6128 }; 6129 6130 /* hwrm_struct_hdr (size:128b/16B) */ 6131 struct hwrm_struct_hdr { 6132 __le16 struct_id; 6133 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6134 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6135 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6136 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6137 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6138 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6139 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6140 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6141 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6142 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6143 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 6144 __le16 len; 6145 u8 version; 6146 u8 count; 6147 __le16 subtype; 6148 __le16 next_offset; 6149 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6150 u8 unused_0[6]; 6151 }; 6152 6153 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 6154 struct hwrm_struct_data_dcbx_app { 6155 __be16 protocol_id; 6156 u8 protocol_selector; 6157 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6158 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6159 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6160 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6161 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 6162 u8 priority; 6163 u8 valid; 6164 u8 unused_0[3]; 6165 }; 6166 6167 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 6168 struct hwrm_fw_set_structured_data_input { 6169 __le16 req_type; 6170 __le16 cmpl_ring; 6171 __le16 seq_id; 6172 __le16 target_id; 6173 __le64 resp_addr; 6174 __le64 src_data_addr; 6175 __le16 data_len; 6176 u8 hdr_cnt; 6177 u8 unused_0[5]; 6178 }; 6179 6180 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 6181 struct hwrm_fw_set_structured_data_output { 6182 __le16 error_code; 6183 __le16 req_type; 6184 __le16 seq_id; 6185 __le16 resp_len; 6186 u8 unused_0[7]; 6187 u8 valid; 6188 }; 6189 6190 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 6191 struct hwrm_fw_set_structured_data_cmd_err { 6192 u8 code; 6193 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6194 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 6195 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 6196 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6197 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6198 u8 unused_0[7]; 6199 }; 6200 6201 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 6202 struct hwrm_fw_get_structured_data_input { 6203 __le16 req_type; 6204 __le16 cmpl_ring; 6205 __le16 seq_id; 6206 __le16 target_id; 6207 __le64 resp_addr; 6208 __le64 dest_data_addr; 6209 __le16 data_len; 6210 __le16 structure_id; 6211 __le16 subtype; 6212 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 6213 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 6214 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 6215 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 6216 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 6217 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 6218 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 6219 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 6220 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 6221 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 6222 u8 count; 6223 u8 unused_0; 6224 }; 6225 6226 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 6227 struct hwrm_fw_get_structured_data_output { 6228 __le16 error_code; 6229 __le16 req_type; 6230 __le16 seq_id; 6231 __le16 resp_len; 6232 u8 hdr_cnt; 6233 u8 unused_0[6]; 6234 u8 valid; 6235 }; 6236 6237 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 6238 struct hwrm_fw_get_structured_data_cmd_err { 6239 u8 code; 6240 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6241 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6242 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6243 u8 unused_0[7]; 6244 }; 6245 6246 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 6247 struct hwrm_exec_fwd_resp_input { 6248 __le16 req_type; 6249 __le16 cmpl_ring; 6250 __le16 seq_id; 6251 __le16 target_id; 6252 __le64 resp_addr; 6253 __le32 encap_request[26]; 6254 __le16 encap_resp_target_id; 6255 u8 unused_0[6]; 6256 }; 6257 6258 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 6259 struct hwrm_exec_fwd_resp_output { 6260 __le16 error_code; 6261 __le16 req_type; 6262 __le16 seq_id; 6263 __le16 resp_len; 6264 u8 unused_0[7]; 6265 u8 valid; 6266 }; 6267 6268 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 6269 struct hwrm_reject_fwd_resp_input { 6270 __le16 req_type; 6271 __le16 cmpl_ring; 6272 __le16 seq_id; 6273 __le16 target_id; 6274 __le64 resp_addr; 6275 __le32 encap_request[26]; 6276 __le16 encap_resp_target_id; 6277 u8 unused_0[6]; 6278 }; 6279 6280 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 6281 struct hwrm_reject_fwd_resp_output { 6282 __le16 error_code; 6283 __le16 req_type; 6284 __le16 seq_id; 6285 __le16 resp_len; 6286 u8 unused_0[7]; 6287 u8 valid; 6288 }; 6289 6290 /* hwrm_fwd_resp_input (size:1024b/128B) */ 6291 struct hwrm_fwd_resp_input { 6292 __le16 req_type; 6293 __le16 cmpl_ring; 6294 __le16 seq_id; 6295 __le16 target_id; 6296 __le64 resp_addr; 6297 __le16 encap_resp_target_id; 6298 __le16 encap_resp_cmpl_ring; 6299 __le16 encap_resp_len; 6300 u8 unused_0; 6301 u8 unused_1; 6302 __le64 encap_resp_addr; 6303 __le32 encap_resp[24]; 6304 }; 6305 6306 /* hwrm_fwd_resp_output (size:128b/16B) */ 6307 struct hwrm_fwd_resp_output { 6308 __le16 error_code; 6309 __le16 req_type; 6310 __le16 seq_id; 6311 __le16 resp_len; 6312 u8 unused_0[7]; 6313 u8 valid; 6314 }; 6315 6316 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 6317 struct hwrm_fwd_async_event_cmpl_input { 6318 __le16 req_type; 6319 __le16 cmpl_ring; 6320 __le16 seq_id; 6321 __le16 target_id; 6322 __le64 resp_addr; 6323 __le16 encap_async_event_target_id; 6324 u8 unused_0[6]; 6325 __le32 encap_async_event_cmpl[4]; 6326 }; 6327 6328 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 6329 struct hwrm_fwd_async_event_cmpl_output { 6330 __le16 error_code; 6331 __le16 req_type; 6332 __le16 seq_id; 6333 __le16 resp_len; 6334 u8 unused_0[7]; 6335 u8 valid; 6336 }; 6337 6338 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 6339 struct hwrm_temp_monitor_query_input { 6340 __le16 req_type; 6341 __le16 cmpl_ring; 6342 __le16 seq_id; 6343 __le16 target_id; 6344 __le64 resp_addr; 6345 }; 6346 6347 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 6348 struct hwrm_temp_monitor_query_output { 6349 __le16 error_code; 6350 __le16 req_type; 6351 __le16 seq_id; 6352 __le16 resp_len; 6353 u8 temp; 6354 u8 unused_0[6]; 6355 u8 valid; 6356 }; 6357 6358 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 6359 struct hwrm_wol_filter_alloc_input { 6360 __le16 req_type; 6361 __le16 cmpl_ring; 6362 __le16 seq_id; 6363 __le16 target_id; 6364 __le64 resp_addr; 6365 __le32 flags; 6366 __le32 enables; 6367 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 6368 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 6369 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 6370 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 6371 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 6372 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 6373 __le16 port_id; 6374 u8 wol_type; 6375 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 6376 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 6377 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 6378 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 6379 u8 unused_0[5]; 6380 u8 mac_address[6]; 6381 __le16 pattern_offset; 6382 __le16 pattern_buf_size; 6383 __le16 pattern_mask_size; 6384 u8 unused_1[4]; 6385 __le64 pattern_buf_addr; 6386 __le64 pattern_mask_addr; 6387 }; 6388 6389 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 6390 struct hwrm_wol_filter_alloc_output { 6391 __le16 error_code; 6392 __le16 req_type; 6393 __le16 seq_id; 6394 __le16 resp_len; 6395 u8 wol_filter_id; 6396 u8 unused_0[6]; 6397 u8 valid; 6398 }; 6399 6400 /* hwrm_wol_filter_free_input (size:256b/32B) */ 6401 struct hwrm_wol_filter_free_input { 6402 __le16 req_type; 6403 __le16 cmpl_ring; 6404 __le16 seq_id; 6405 __le16 target_id; 6406 __le64 resp_addr; 6407 __le32 flags; 6408 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 6409 __le32 enables; 6410 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 6411 __le16 port_id; 6412 u8 wol_filter_id; 6413 u8 unused_0[5]; 6414 }; 6415 6416 /* hwrm_wol_filter_free_output (size:128b/16B) */ 6417 struct hwrm_wol_filter_free_output { 6418 __le16 error_code; 6419 __le16 req_type; 6420 __le16 seq_id; 6421 __le16 resp_len; 6422 u8 unused_0[7]; 6423 u8 valid; 6424 }; 6425 6426 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 6427 struct hwrm_wol_filter_qcfg_input { 6428 __le16 req_type; 6429 __le16 cmpl_ring; 6430 __le16 seq_id; 6431 __le16 target_id; 6432 __le64 resp_addr; 6433 __le16 port_id; 6434 __le16 handle; 6435 u8 unused_0[4]; 6436 __le64 pattern_buf_addr; 6437 __le16 pattern_buf_size; 6438 u8 unused_1[6]; 6439 __le64 pattern_mask_addr; 6440 __le16 pattern_mask_size; 6441 u8 unused_2[6]; 6442 }; 6443 6444 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 6445 struct hwrm_wol_filter_qcfg_output { 6446 __le16 error_code; 6447 __le16 req_type; 6448 __le16 seq_id; 6449 __le16 resp_len; 6450 __le16 next_handle; 6451 u8 wol_filter_id; 6452 u8 wol_type; 6453 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 6454 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 6455 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 6456 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 6457 __le32 unused_0; 6458 u8 mac_address[6]; 6459 __le16 pattern_offset; 6460 __le16 pattern_size; 6461 __le16 pattern_mask_size; 6462 u8 unused_1[3]; 6463 u8 valid; 6464 }; 6465 6466 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 6467 struct hwrm_wol_reason_qcfg_input { 6468 __le16 req_type; 6469 __le16 cmpl_ring; 6470 __le16 seq_id; 6471 __le16 target_id; 6472 __le64 resp_addr; 6473 __le16 port_id; 6474 u8 unused_0[6]; 6475 __le64 wol_pkt_buf_addr; 6476 __le16 wol_pkt_buf_size; 6477 u8 unused_1[6]; 6478 }; 6479 6480 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 6481 struct hwrm_wol_reason_qcfg_output { 6482 __le16 error_code; 6483 __le16 req_type; 6484 __le16 seq_id; 6485 __le16 resp_len; 6486 u8 wol_filter_id; 6487 u8 wol_reason; 6488 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 6489 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 6490 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 6491 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 6492 u8 wol_pkt_len; 6493 u8 unused_0[4]; 6494 u8 valid; 6495 }; 6496 6497 /* coredump_segment_record (size:128b/16B) */ 6498 struct coredump_segment_record { 6499 __le16 component_id; 6500 __le16 segment_id; 6501 __le16 max_instances; 6502 u8 version_hi; 6503 u8 version_low; 6504 u8 seg_flags; 6505 u8 unused_0[7]; 6506 }; 6507 6508 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 6509 struct hwrm_dbg_coredump_list_input { 6510 __le16 req_type; 6511 __le16 cmpl_ring; 6512 __le16 seq_id; 6513 __le16 target_id; 6514 __le64 resp_addr; 6515 __le64 host_dest_addr; 6516 __le32 host_buf_len; 6517 __le16 seq_no; 6518 u8 unused_0[2]; 6519 }; 6520 6521 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 6522 struct hwrm_dbg_coredump_list_output { 6523 __le16 error_code; 6524 __le16 req_type; 6525 __le16 seq_id; 6526 __le16 resp_len; 6527 u8 flags; 6528 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 6529 u8 unused_0; 6530 __le16 total_segments; 6531 __le16 data_len; 6532 u8 unused_1; 6533 u8 valid; 6534 }; 6535 6536 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 6537 struct hwrm_dbg_coredump_initiate_input { 6538 __le16 req_type; 6539 __le16 cmpl_ring; 6540 __le16 seq_id; 6541 __le16 target_id; 6542 __le64 resp_addr; 6543 __le16 component_id; 6544 __le16 segment_id; 6545 __le16 instance; 6546 __le16 unused_0; 6547 u8 seg_flags; 6548 u8 unused_1[7]; 6549 }; 6550 6551 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 6552 struct hwrm_dbg_coredump_initiate_output { 6553 __le16 error_code; 6554 __le16 req_type; 6555 __le16 seq_id; 6556 __le16 resp_len; 6557 u8 unused_0[7]; 6558 u8 valid; 6559 }; 6560 6561 /* coredump_data_hdr (size:128b/16B) */ 6562 struct coredump_data_hdr { 6563 __le32 address; 6564 __le32 flags_length; 6565 __le32 instance; 6566 __le32 next_offset; 6567 }; 6568 6569 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 6570 struct hwrm_dbg_coredump_retrieve_input { 6571 __le16 req_type; 6572 __le16 cmpl_ring; 6573 __le16 seq_id; 6574 __le16 target_id; 6575 __le64 resp_addr; 6576 __le64 host_dest_addr; 6577 __le32 host_buf_len; 6578 __le32 unused_0; 6579 __le16 component_id; 6580 __le16 segment_id; 6581 __le16 instance; 6582 __le16 unused_1; 6583 u8 seg_flags; 6584 u8 unused_2; 6585 __le16 unused_3; 6586 __le32 unused_4; 6587 __le32 seq_no; 6588 __le32 unused_5; 6589 }; 6590 6591 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 6592 struct hwrm_dbg_coredump_retrieve_output { 6593 __le16 error_code; 6594 __le16 req_type; 6595 __le16 seq_id; 6596 __le16 resp_len; 6597 u8 flags; 6598 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 6599 u8 unused_0; 6600 __le16 data_len; 6601 u8 unused_1[3]; 6602 u8 valid; 6603 }; 6604 6605 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 6606 struct hwrm_dbg_ring_info_get_input { 6607 __le16 req_type; 6608 __le16 cmpl_ring; 6609 __le16 seq_id; 6610 __le16 target_id; 6611 __le64 resp_addr; 6612 u8 ring_type; 6613 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 6614 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 6615 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 6616 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX 6617 u8 unused_0[3]; 6618 __le32 fw_ring_id; 6619 }; 6620 6621 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 6622 struct hwrm_dbg_ring_info_get_output { 6623 __le16 error_code; 6624 __le16 req_type; 6625 __le16 seq_id; 6626 __le16 resp_len; 6627 __le32 producer_index; 6628 __le32 consumer_index; 6629 u8 unused_0[7]; 6630 u8 valid; 6631 }; 6632 6633 /* hwrm_nvm_read_input (size:320b/40B) */ 6634 struct hwrm_nvm_read_input { 6635 __le16 req_type; 6636 __le16 cmpl_ring; 6637 __le16 seq_id; 6638 __le16 target_id; 6639 __le64 resp_addr; 6640 __le64 host_dest_addr; 6641 __le16 dir_idx; 6642 u8 unused_0[2]; 6643 __le32 offset; 6644 __le32 len; 6645 u8 unused_1[4]; 6646 }; 6647 6648 /* hwrm_nvm_read_output (size:128b/16B) */ 6649 struct hwrm_nvm_read_output { 6650 __le16 error_code; 6651 __le16 req_type; 6652 __le16 seq_id; 6653 __le16 resp_len; 6654 u8 unused_0[7]; 6655 u8 valid; 6656 }; 6657 6658 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 6659 struct hwrm_nvm_get_dir_entries_input { 6660 __le16 req_type; 6661 __le16 cmpl_ring; 6662 __le16 seq_id; 6663 __le16 target_id; 6664 __le64 resp_addr; 6665 __le64 host_dest_addr; 6666 }; 6667 6668 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 6669 struct hwrm_nvm_get_dir_entries_output { 6670 __le16 error_code; 6671 __le16 req_type; 6672 __le16 seq_id; 6673 __le16 resp_len; 6674 u8 unused_0[7]; 6675 u8 valid; 6676 }; 6677 6678 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 6679 struct hwrm_nvm_get_dir_info_input { 6680 __le16 req_type; 6681 __le16 cmpl_ring; 6682 __le16 seq_id; 6683 __le16 target_id; 6684 __le64 resp_addr; 6685 }; 6686 6687 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 6688 struct hwrm_nvm_get_dir_info_output { 6689 __le16 error_code; 6690 __le16 req_type; 6691 __le16 seq_id; 6692 __le16 resp_len; 6693 __le32 entries; 6694 __le32 entry_length; 6695 u8 unused_0[7]; 6696 u8 valid; 6697 }; 6698 6699 /* hwrm_nvm_write_input (size:384b/48B) */ 6700 struct hwrm_nvm_write_input { 6701 __le16 req_type; 6702 __le16 cmpl_ring; 6703 __le16 seq_id; 6704 __le16 target_id; 6705 __le64 resp_addr; 6706 __le64 host_src_addr; 6707 __le16 dir_type; 6708 __le16 dir_ordinal; 6709 __le16 dir_ext; 6710 __le16 dir_attr; 6711 __le32 dir_data_length; 6712 __le16 option; 6713 __le16 flags; 6714 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 6715 __le32 dir_item_length; 6716 __le32 unused_0; 6717 }; 6718 6719 /* hwrm_nvm_write_output (size:128b/16B) */ 6720 struct hwrm_nvm_write_output { 6721 __le16 error_code; 6722 __le16 req_type; 6723 __le16 seq_id; 6724 __le16 resp_len; 6725 __le32 dir_item_length; 6726 __le16 dir_idx; 6727 u8 unused_0; 6728 u8 valid; 6729 }; 6730 6731 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 6732 struct hwrm_nvm_write_cmd_err { 6733 u8 code; 6734 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 6735 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 6736 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 6737 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 6738 u8 unused_0[7]; 6739 }; 6740 6741 /* hwrm_nvm_modify_input (size:320b/40B) */ 6742 struct hwrm_nvm_modify_input { 6743 __le16 req_type; 6744 __le16 cmpl_ring; 6745 __le16 seq_id; 6746 __le16 target_id; 6747 __le64 resp_addr; 6748 __le64 host_src_addr; 6749 __le16 dir_idx; 6750 u8 unused_0[2]; 6751 __le32 offset; 6752 __le32 len; 6753 u8 unused_1[4]; 6754 }; 6755 6756 /* hwrm_nvm_modify_output (size:128b/16B) */ 6757 struct hwrm_nvm_modify_output { 6758 __le16 error_code; 6759 __le16 req_type; 6760 __le16 seq_id; 6761 __le16 resp_len; 6762 u8 unused_0[7]; 6763 u8 valid; 6764 }; 6765 6766 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 6767 struct hwrm_nvm_find_dir_entry_input { 6768 __le16 req_type; 6769 __le16 cmpl_ring; 6770 __le16 seq_id; 6771 __le16 target_id; 6772 __le64 resp_addr; 6773 __le32 enables; 6774 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 6775 __le16 dir_idx; 6776 __le16 dir_type; 6777 __le16 dir_ordinal; 6778 __le16 dir_ext; 6779 u8 opt_ordinal; 6780 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 6781 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 6782 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 6783 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 6784 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 6785 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 6786 u8 unused_0[3]; 6787 }; 6788 6789 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 6790 struct hwrm_nvm_find_dir_entry_output { 6791 __le16 error_code; 6792 __le16 req_type; 6793 __le16 seq_id; 6794 __le16 resp_len; 6795 __le32 dir_item_length; 6796 __le32 dir_data_length; 6797 __le32 fw_ver; 6798 __le16 dir_ordinal; 6799 __le16 dir_idx; 6800 u8 unused_0[7]; 6801 u8 valid; 6802 }; 6803 6804 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 6805 struct hwrm_nvm_erase_dir_entry_input { 6806 __le16 req_type; 6807 __le16 cmpl_ring; 6808 __le16 seq_id; 6809 __le16 target_id; 6810 __le64 resp_addr; 6811 __le16 dir_idx; 6812 u8 unused_0[6]; 6813 }; 6814 6815 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 6816 struct hwrm_nvm_erase_dir_entry_output { 6817 __le16 error_code; 6818 __le16 req_type; 6819 __le16 seq_id; 6820 __le16 resp_len; 6821 u8 unused_0[7]; 6822 u8 valid; 6823 }; 6824 6825 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 6826 struct hwrm_nvm_get_dev_info_input { 6827 __le16 req_type; 6828 __le16 cmpl_ring; 6829 __le16 seq_id; 6830 __le16 target_id; 6831 __le64 resp_addr; 6832 }; 6833 6834 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 6835 struct hwrm_nvm_get_dev_info_output { 6836 __le16 error_code; 6837 __le16 req_type; 6838 __le16 seq_id; 6839 __le16 resp_len; 6840 __le16 manufacturer_id; 6841 __le16 device_id; 6842 __le32 sector_size; 6843 __le32 nvram_size; 6844 __le32 reserved_size; 6845 __le32 available_size; 6846 u8 unused_0[3]; 6847 u8 valid; 6848 }; 6849 6850 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 6851 struct hwrm_nvm_mod_dir_entry_input { 6852 __le16 req_type; 6853 __le16 cmpl_ring; 6854 __le16 seq_id; 6855 __le16 target_id; 6856 __le64 resp_addr; 6857 __le32 enables; 6858 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 6859 __le16 dir_idx; 6860 __le16 dir_ordinal; 6861 __le16 dir_ext; 6862 __le16 dir_attr; 6863 __le32 checksum; 6864 }; 6865 6866 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 6867 struct hwrm_nvm_mod_dir_entry_output { 6868 __le16 error_code; 6869 __le16 req_type; 6870 __le16 seq_id; 6871 __le16 resp_len; 6872 u8 unused_0[7]; 6873 u8 valid; 6874 }; 6875 6876 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 6877 struct hwrm_nvm_verify_update_input { 6878 __le16 req_type; 6879 __le16 cmpl_ring; 6880 __le16 seq_id; 6881 __le16 target_id; 6882 __le64 resp_addr; 6883 __le16 dir_type; 6884 __le16 dir_ordinal; 6885 __le16 dir_ext; 6886 u8 unused_0[2]; 6887 }; 6888 6889 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 6890 struct hwrm_nvm_verify_update_output { 6891 __le16 error_code; 6892 __le16 req_type; 6893 __le16 seq_id; 6894 __le16 resp_len; 6895 u8 unused_0[7]; 6896 u8 valid; 6897 }; 6898 6899 /* hwrm_nvm_install_update_input (size:192b/24B) */ 6900 struct hwrm_nvm_install_update_input { 6901 __le16 req_type; 6902 __le16 cmpl_ring; 6903 __le16 seq_id; 6904 __le16 target_id; 6905 __le64 resp_addr; 6906 __le32 install_type; 6907 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 6908 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 6909 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 6910 __le16 flags; 6911 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 6912 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 6913 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 6914 u8 unused_0[2]; 6915 }; 6916 6917 /* hwrm_nvm_install_update_output (size:192b/24B) */ 6918 struct hwrm_nvm_install_update_output { 6919 __le16 error_code; 6920 __le16 req_type; 6921 __le16 seq_id; 6922 __le16 resp_len; 6923 __le64 installed_items; 6924 u8 result; 6925 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 6926 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 6927 u8 problem_item; 6928 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 6929 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 6930 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 6931 u8 reset_required; 6932 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 6933 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 6934 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 6935 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 6936 u8 unused_0[4]; 6937 u8 valid; 6938 }; 6939 6940 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 6941 struct hwrm_nvm_install_update_cmd_err { 6942 u8 code; 6943 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 6944 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 6945 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 6946 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 6947 u8 unused_0[7]; 6948 }; 6949 6950 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 6951 struct hwrm_nvm_get_variable_input { 6952 __le16 req_type; 6953 __le16 cmpl_ring; 6954 __le16 seq_id; 6955 __le16 target_id; 6956 __le64 resp_addr; 6957 __le64 dest_data_addr; 6958 __le16 data_len; 6959 __le16 option_num; 6960 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6961 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6962 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 6963 __le16 dimensions; 6964 __le16 index_0; 6965 __le16 index_1; 6966 __le16 index_2; 6967 __le16 index_3; 6968 u8 flags; 6969 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 6970 u8 unused_0; 6971 }; 6972 6973 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 6974 struct hwrm_nvm_get_variable_output { 6975 __le16 error_code; 6976 __le16 req_type; 6977 __le16 seq_id; 6978 __le16 resp_len; 6979 __le16 data_len; 6980 __le16 option_num; 6981 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 6982 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 6983 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 6984 u8 unused_0[3]; 6985 u8 valid; 6986 }; 6987 6988 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 6989 struct hwrm_nvm_get_variable_cmd_err { 6990 u8 code; 6991 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6992 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6993 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6994 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 6995 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 6996 u8 unused_0[7]; 6997 }; 6998 6999 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 7000 struct hwrm_nvm_set_variable_input { 7001 __le16 req_type; 7002 __le16 cmpl_ring; 7003 __le16 seq_id; 7004 __le16 target_id; 7005 __le64 resp_addr; 7006 __le64 src_data_addr; 7007 __le16 data_len; 7008 __le16 option_num; 7009 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7010 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7011 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7012 __le16 dimensions; 7013 __le16 index_0; 7014 __le16 index_1; 7015 __le16 index_2; 7016 __le16 index_3; 7017 u8 flags; 7018 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 7019 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 7020 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 7021 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 7022 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 7023 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 7024 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 7025 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 7026 u8 unused_0; 7027 }; 7028 7029 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 7030 struct hwrm_nvm_set_variable_output { 7031 __le16 error_code; 7032 __le16 req_type; 7033 __le16 seq_id; 7034 __le16 resp_len; 7035 u8 unused_0[7]; 7036 u8 valid; 7037 }; 7038 7039 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 7040 struct hwrm_nvm_set_variable_cmd_err { 7041 u8 code; 7042 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7043 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7044 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7045 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 7046 u8 unused_0[7]; 7047 }; 7048 7049 /* hwrm_selftest_qlist_input (size:128b/16B) */ 7050 struct hwrm_selftest_qlist_input { 7051 __le16 req_type; 7052 __le16 cmpl_ring; 7053 __le16 seq_id; 7054 __le16 target_id; 7055 __le64 resp_addr; 7056 }; 7057 7058 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 7059 struct hwrm_selftest_qlist_output { 7060 __le16 error_code; 7061 __le16 req_type; 7062 __le16 seq_id; 7063 __le16 resp_len; 7064 u8 num_tests; 7065 u8 available_tests; 7066 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 7067 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 7068 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 7069 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 7070 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 7071 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7072 u8 offline_tests; 7073 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 7074 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 7075 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 7076 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 7077 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 7078 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7079 u8 unused_0; 7080 __le16 test_timeout; 7081 u8 unused_1[2]; 7082 char test0_name[32]; 7083 char test1_name[32]; 7084 char test2_name[32]; 7085 char test3_name[32]; 7086 char test4_name[32]; 7087 char test5_name[32]; 7088 char test6_name[32]; 7089 char test7_name[32]; 7090 u8 unused_2[7]; 7091 u8 valid; 7092 }; 7093 7094 /* hwrm_selftest_exec_input (size:192b/24B) */ 7095 struct hwrm_selftest_exec_input { 7096 __le16 req_type; 7097 __le16 cmpl_ring; 7098 __le16 seq_id; 7099 __le16 target_id; 7100 __le64 resp_addr; 7101 u8 flags; 7102 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 7103 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 7104 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 7105 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 7106 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 7107 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 7108 u8 unused_0[7]; 7109 }; 7110 7111 /* hwrm_selftest_exec_output (size:128b/16B) */ 7112 struct hwrm_selftest_exec_output { 7113 __le16 error_code; 7114 __le16 req_type; 7115 __le16 seq_id; 7116 __le16 resp_len; 7117 u8 requested_tests; 7118 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 7119 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 7120 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 7121 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 7122 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 7123 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 7124 u8 test_success; 7125 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 7126 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 7127 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 7128 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 7129 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 7130 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 7131 u8 unused_0[5]; 7132 u8 valid; 7133 }; 7134 7135 /* hwrm_selftest_irq_input (size:128b/16B) */ 7136 struct hwrm_selftest_irq_input { 7137 __le16 req_type; 7138 __le16 cmpl_ring; 7139 __le16 seq_id; 7140 __le16 target_id; 7141 __le64 resp_addr; 7142 }; 7143 7144 /* hwrm_selftest_irq_output (size:128b/16B) */ 7145 struct hwrm_selftest_irq_output { 7146 __le16 error_code; 7147 __le16 req_type; 7148 __le16 seq_id; 7149 __le16 resp_len; 7150 u8 unused_0[7]; 7151 u8 valid; 7152 }; 7153 7154 #endif /* _BNXT_HSI_H_ */ 7155