1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2020 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 107 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 108 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 109 #define HWRM_FUNC_VF_CFG 0xfUL 110 #define HWRM_RESERVED1 0x10UL 111 #define HWRM_FUNC_RESET 0x11UL 112 #define HWRM_FUNC_GETFID 0x12UL 113 #define HWRM_FUNC_VF_ALLOC 0x13UL 114 #define HWRM_FUNC_VF_FREE 0x14UL 115 #define HWRM_FUNC_QCAPS 0x15UL 116 #define HWRM_FUNC_QCFG 0x16UL 117 #define HWRM_FUNC_CFG 0x17UL 118 #define HWRM_FUNC_QSTATS 0x18UL 119 #define HWRM_FUNC_CLR_STATS 0x19UL 120 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 121 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 122 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 123 #define HWRM_FUNC_DRV_RGTR 0x1dUL 124 #define HWRM_FUNC_DRV_QVER 0x1eUL 125 #define HWRM_FUNC_BUF_RGTR 0x1fUL 126 #define HWRM_PORT_PHY_CFG 0x20UL 127 #define HWRM_PORT_MAC_CFG 0x21UL 128 #define HWRM_PORT_TS_QUERY 0x22UL 129 #define HWRM_PORT_QSTATS 0x23UL 130 #define HWRM_PORT_LPBK_QSTATS 0x24UL 131 #define HWRM_PORT_CLR_STATS 0x25UL 132 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 133 #define HWRM_PORT_PHY_QCFG 0x27UL 134 #define HWRM_PORT_MAC_QCFG 0x28UL 135 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 136 #define HWRM_PORT_PHY_QCAPS 0x2aUL 137 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 138 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 139 #define HWRM_PORT_LED_CFG 0x2dUL 140 #define HWRM_PORT_LED_QCFG 0x2eUL 141 #define HWRM_PORT_LED_QCAPS 0x2fUL 142 #define HWRM_QUEUE_QPORTCFG 0x30UL 143 #define HWRM_QUEUE_QCFG 0x31UL 144 #define HWRM_QUEUE_CFG 0x32UL 145 #define HWRM_FUNC_VLAN_CFG 0x33UL 146 #define HWRM_FUNC_VLAN_QCFG 0x34UL 147 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 148 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 149 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 150 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 151 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 152 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 153 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 154 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 155 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 156 #define HWRM_VNIC_ALLOC 0x40UL 157 #define HWRM_VNIC_FREE 0x41UL 158 #define HWRM_VNIC_CFG 0x42UL 159 #define HWRM_VNIC_QCFG 0x43UL 160 #define HWRM_VNIC_TPA_CFG 0x44UL 161 #define HWRM_VNIC_TPA_QCFG 0x45UL 162 #define HWRM_VNIC_RSS_CFG 0x46UL 163 #define HWRM_VNIC_RSS_QCFG 0x47UL 164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166 #define HWRM_VNIC_QCAPS 0x4aUL 167 #define HWRM_RING_ALLOC 0x50UL 168 #define HWRM_RING_FREE 0x51UL 169 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 170 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 171 #define HWRM_RING_AGGINT_QCAPS 0x54UL 172 #define HWRM_RING_SCHQ_ALLOC 0x55UL 173 #define HWRM_RING_SCHQ_CFG 0x56UL 174 #define HWRM_RING_SCHQ_FREE 0x57UL 175 #define HWRM_RING_RESET 0x5eUL 176 #define HWRM_RING_GRP_ALLOC 0x60UL 177 #define HWRM_RING_GRP_FREE 0x61UL 178 #define HWRM_RING_CFG 0x62UL 179 #define HWRM_RING_QCFG 0x63UL 180 #define HWRM_RESERVED5 0x64UL 181 #define HWRM_RESERVED6 0x65UL 182 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 183 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 184 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 185 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 186 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 187 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 188 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 189 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 190 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 191 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 192 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 193 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 194 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 195 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 196 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 197 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 198 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 199 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 200 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 201 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 202 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 203 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 204 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 205 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 206 #define HWRM_STAT_CTX_ALLOC 0xb0UL 207 #define HWRM_STAT_CTX_FREE 0xb1UL 208 #define HWRM_STAT_CTX_QUERY 0xb2UL 209 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 210 #define HWRM_PORT_QSTATS_EXT 0xb4UL 211 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 212 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 213 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 214 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 215 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 216 #define HWRM_RESERVED7 0xbaUL 217 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 218 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 219 #define HWRM_PORT_ECN_QSTATS 0xbdUL 220 #define HWRM_FW_RESET 0xc0UL 221 #define HWRM_FW_QSTATUS 0xc1UL 222 #define HWRM_FW_HEALTH_CHECK 0xc2UL 223 #define HWRM_FW_SYNC 0xc3UL 224 #define HWRM_FW_STATE_QCAPS 0xc4UL 225 #define HWRM_FW_STATE_QUIESCE 0xc5UL 226 #define HWRM_FW_STATE_BACKUP 0xc6UL 227 #define HWRM_FW_STATE_RESTORE 0xc7UL 228 #define HWRM_FW_SET_TIME 0xc8UL 229 #define HWRM_FW_GET_TIME 0xc9UL 230 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 231 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 232 #define HWRM_FW_IPC_MAILBOX 0xccUL 233 #define HWRM_FW_ECN_CFG 0xcdUL 234 #define HWRM_FW_ECN_QCFG 0xceUL 235 #define HWRM_FW_SECURE_CFG 0xcfUL 236 #define HWRM_EXEC_FWD_RESP 0xd0UL 237 #define HWRM_REJECT_FWD_RESP 0xd1UL 238 #define HWRM_FWD_RESP 0xd2UL 239 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 240 #define HWRM_OEM_CMD 0xd4UL 241 #define HWRM_PORT_PRBS_TEST 0xd5UL 242 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 243 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 244 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 245 #define HWRM_PORT_DSC_DUMP 0xd9UL 246 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 247 #define HWRM_REG_POWER_QUERY 0xe1UL 248 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 249 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 250 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 251 #define HWRM_WOL_FILTER_FREE 0xf1UL 252 #define HWRM_WOL_FILTER_QCFG 0xf2UL 253 #define HWRM_WOL_REASON_QCFG 0xf3UL 254 #define HWRM_CFA_METER_QCAPS 0xf4UL 255 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 256 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 257 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 258 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 259 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 260 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 261 #define HWRM_CFA_VFR_ALLOC 0xfdUL 262 #define HWRM_CFA_VFR_FREE 0xfeUL 263 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 264 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 265 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 266 #define HWRM_CFA_FLOW_ALLOC 0x103UL 267 #define HWRM_CFA_FLOW_FREE 0x104UL 268 #define HWRM_CFA_FLOW_FLUSH 0x105UL 269 #define HWRM_CFA_FLOW_STATS 0x106UL 270 #define HWRM_CFA_FLOW_INFO 0x107UL 271 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 272 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 273 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 274 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 275 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 276 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 277 #define HWRM_CFA_PAIR_FREE 0x10eUL 278 #define HWRM_CFA_PAIR_INFO 0x10fUL 279 #define HWRM_FW_IPC_MSG 0x110UL 280 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 281 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 282 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 283 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 284 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 285 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 286 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 287 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 288 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 289 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 290 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 291 #define HWRM_CFA_COUNTER_CFG 0x11cUL 292 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 293 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 294 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 295 #define HWRM_CFA_EEM_QCAPS 0x120UL 296 #define HWRM_CFA_EEM_CFG 0x121UL 297 #define HWRM_CFA_EEM_QCFG 0x122UL 298 #define HWRM_CFA_EEM_OP 0x123UL 299 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 300 #define HWRM_CFA_TFLIB 0x125UL 301 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 302 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 303 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 304 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 305 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 306 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 307 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 308 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 309 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 310 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 311 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 312 #define HWRM_ENGINE_QG_QUERY 0x13dUL 313 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 314 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 315 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 316 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 317 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 318 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 319 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 320 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 321 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 322 #define HWRM_ENGINE_SG_QUERY 0x147UL 323 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 324 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 325 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 326 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 327 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 328 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 329 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 330 #define HWRM_ENGINE_STATS_QUERY 0x157UL 331 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 332 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 333 #define HWRM_ENGINE_RQ_FREE 0x15fUL 334 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 335 #define HWRM_ENGINE_CQ_FREE 0x161UL 336 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 337 #define HWRM_ENGINE_NQ_FREE 0x163UL 338 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 339 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 340 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 341 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 342 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 343 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 344 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 345 #define HWRM_FUNC_VF_BW_CFG 0x195UL 346 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 347 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 348 #define HWRM_FUNC_QSTATS_EXT 0x198UL 349 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 350 #define HWRM_SELFTEST_QLIST 0x200UL 351 #define HWRM_SELFTEST_EXEC 0x201UL 352 #define HWRM_SELFTEST_IRQ 0x202UL 353 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 354 #define HWRM_PCIE_QSTATS 0x204UL 355 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 356 #define HWRM_MFG_TIMERS_QUERY 0x206UL 357 #define HWRM_MFG_OTP_CFG 0x207UL 358 #define HWRM_MFG_OTP_QCFG 0x208UL 359 #define HWRM_MFG_HDMA_TEST 0x209UL 360 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 361 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 362 #define HWRM_TF 0x2bcUL 363 #define HWRM_TF_VERSION_GET 0x2bdUL 364 #define HWRM_TF_SESSION_OPEN 0x2c6UL 365 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 366 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 367 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 368 #define HWRM_TF_SESSION_CLOSE 0x2caUL 369 #define HWRM_TF_SESSION_QCFG 0x2cbUL 370 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 371 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 372 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 373 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 374 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 375 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 376 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 377 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 378 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 379 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 380 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 381 #define HWRM_TF_EXT_EM_OP 0x2e7UL 382 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 383 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 384 #define HWRM_TF_EM_INSERT 0x2eaUL 385 #define HWRM_TF_EM_DELETE 0x2ebUL 386 #define HWRM_TF_TCAM_SET 0x2f8UL 387 #define HWRM_TF_TCAM_GET 0x2f9UL 388 #define HWRM_TF_TCAM_MOVE 0x2faUL 389 #define HWRM_TF_TCAM_FREE 0x2fbUL 390 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 391 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 392 #define HWRM_TF_IF_TBL_SET 0x2feUL 393 #define HWRM_TF_IF_TBL_GET 0x2ffUL 394 #define HWRM_SV 0x400UL 395 #define HWRM_DBG_READ_DIRECT 0xff10UL 396 #define HWRM_DBG_READ_INDIRECT 0xff11UL 397 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 398 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 399 #define HWRM_DBG_DUMP 0xff14UL 400 #define HWRM_DBG_ERASE_NVM 0xff15UL 401 #define HWRM_DBG_CFG 0xff16UL 402 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 403 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 404 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 405 #define HWRM_DBG_FW_CLI 0xff1aUL 406 #define HWRM_DBG_I2C_CMD 0xff1bUL 407 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 408 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 409 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 410 #define HWRM_DBG_DRV_TRACE 0xff1fUL 411 #define HWRM_DBG_QCAPS 0xff20UL 412 #define HWRM_DBG_QCFG 0xff21UL 413 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 414 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 415 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 416 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 417 #define HWRM_NVM_FLUSH 0xfff0UL 418 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 419 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 420 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 421 #define HWRM_NVM_MODIFY 0xfff4UL 422 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 423 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 424 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 425 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 426 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 427 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 428 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 429 #define HWRM_NVM_RAW_DUMP 0xfffcUL 430 #define HWRM_NVM_READ 0xfffdUL 431 #define HWRM_NVM_WRITE 0xfffeUL 432 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 433 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 434 __le16 unused_0[3]; 435 }; 436 437 /* ret_codes (size:64b/8B) */ 438 struct ret_codes { 439 __le16 error_code; 440 #define HWRM_ERR_CODE_SUCCESS 0x0UL 441 #define HWRM_ERR_CODE_FAIL 0x1UL 442 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 443 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 444 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 445 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 446 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 447 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 448 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 449 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 450 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 451 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 452 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 453 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 454 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 455 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 456 #define HWRM_ERR_CODE_BUSY 0x10UL 457 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 458 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 459 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 460 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 461 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 462 __le16 unused_0[3]; 463 }; 464 465 /* hwrm_err_output (size:128b/16B) */ 466 struct hwrm_err_output { 467 __le16 error_code; 468 __le16 req_type; 469 __le16 seq_id; 470 __le16 resp_len; 471 __le32 opaque_0; 472 __le16 opaque_1; 473 u8 cmd_err; 474 u8 valid; 475 }; 476 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 477 #define HWRM_MAX_REQ_LEN 128 478 #define HWRM_MAX_RESP_LEN 704 479 #define HW_HASH_INDEX_SIZE 0x80 480 #define HW_HASH_KEY_SIZE 40 481 #define HWRM_RESP_VALID_KEY 1 482 #define HWRM_TARGET_ID_BONO 0xFFF8 483 #define HWRM_TARGET_ID_KONG 0xFFF9 484 #define HWRM_TARGET_ID_APE 0xFFFA 485 #define HWRM_TARGET_ID_TOOLS 0xFFFD 486 #define HWRM_VERSION_MAJOR 1 487 #define HWRM_VERSION_MINOR 10 488 #define HWRM_VERSION_UPDATE 1 489 #define HWRM_VERSION_RSVD 65 490 #define HWRM_VERSION_STR "1.10.1.65" 491 492 /* hwrm_ver_get_input (size:192b/24B) */ 493 struct hwrm_ver_get_input { 494 __le16 req_type; 495 __le16 cmpl_ring; 496 __le16 seq_id; 497 __le16 target_id; 498 __le64 resp_addr; 499 u8 hwrm_intf_maj; 500 u8 hwrm_intf_min; 501 u8 hwrm_intf_upd; 502 u8 unused_0[5]; 503 }; 504 505 /* hwrm_ver_get_output (size:1408b/176B) */ 506 struct hwrm_ver_get_output { 507 __le16 error_code; 508 __le16 req_type; 509 __le16 seq_id; 510 __le16 resp_len; 511 u8 hwrm_intf_maj_8b; 512 u8 hwrm_intf_min_8b; 513 u8 hwrm_intf_upd_8b; 514 u8 hwrm_intf_rsvd_8b; 515 u8 hwrm_fw_maj_8b; 516 u8 hwrm_fw_min_8b; 517 u8 hwrm_fw_bld_8b; 518 u8 hwrm_fw_rsvd_8b; 519 u8 mgmt_fw_maj_8b; 520 u8 mgmt_fw_min_8b; 521 u8 mgmt_fw_bld_8b; 522 u8 mgmt_fw_rsvd_8b; 523 u8 netctrl_fw_maj_8b; 524 u8 netctrl_fw_min_8b; 525 u8 netctrl_fw_bld_8b; 526 u8 netctrl_fw_rsvd_8b; 527 __le32 dev_caps_cfg; 528 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 529 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 530 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 531 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 532 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 533 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 534 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 535 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 536 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 537 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 538 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 539 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 540 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 541 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 542 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 543 u8 roce_fw_maj_8b; 544 u8 roce_fw_min_8b; 545 u8 roce_fw_bld_8b; 546 u8 roce_fw_rsvd_8b; 547 char hwrm_fw_name[16]; 548 char mgmt_fw_name[16]; 549 char netctrl_fw_name[16]; 550 char active_pkg_name[16]; 551 char roce_fw_name[16]; 552 __le16 chip_num; 553 u8 chip_rev; 554 u8 chip_metal; 555 u8 chip_bond_id; 556 u8 chip_platform_type; 557 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 558 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 559 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 560 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 561 __le16 max_req_win_len; 562 __le16 max_resp_len; 563 __le16 def_req_timeout; 564 u8 flags; 565 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 566 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 567 u8 unused_0[2]; 568 u8 always_1; 569 __le16 hwrm_intf_major; 570 __le16 hwrm_intf_minor; 571 __le16 hwrm_intf_build; 572 __le16 hwrm_intf_patch; 573 __le16 hwrm_fw_major; 574 __le16 hwrm_fw_minor; 575 __le16 hwrm_fw_build; 576 __le16 hwrm_fw_patch; 577 __le16 mgmt_fw_major; 578 __le16 mgmt_fw_minor; 579 __le16 mgmt_fw_build; 580 __le16 mgmt_fw_patch; 581 __le16 netctrl_fw_major; 582 __le16 netctrl_fw_minor; 583 __le16 netctrl_fw_build; 584 __le16 netctrl_fw_patch; 585 __le16 roce_fw_major; 586 __le16 roce_fw_minor; 587 __le16 roce_fw_build; 588 __le16 roce_fw_patch; 589 __le16 max_ext_req_len; 590 u8 unused_1[5]; 591 u8 valid; 592 }; 593 594 /* eject_cmpl (size:128b/16B) */ 595 struct eject_cmpl { 596 __le16 type; 597 #define EJECT_CMPL_TYPE_MASK 0x3fUL 598 #define EJECT_CMPL_TYPE_SFT 0 599 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 600 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 601 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 602 #define EJECT_CMPL_FLAGS_SFT 6 603 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 604 __le16 len; 605 __le32 opaque; 606 __le16 v; 607 #define EJECT_CMPL_V 0x1UL 608 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 609 #define EJECT_CMPL_ERRORS_SFT 1 610 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 611 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 612 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 613 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 614 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 615 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 616 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 617 __le16 reserved16; 618 __le32 unused_2; 619 }; 620 621 /* hwrm_cmpl (size:128b/16B) */ 622 struct hwrm_cmpl { 623 __le16 type; 624 #define CMPL_TYPE_MASK 0x3fUL 625 #define CMPL_TYPE_SFT 0 626 #define CMPL_TYPE_HWRM_DONE 0x20UL 627 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 628 __le16 sequence_id; 629 __le32 unused_1; 630 __le32 v; 631 #define CMPL_V 0x1UL 632 __le32 unused_3; 633 }; 634 635 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 636 struct hwrm_fwd_req_cmpl { 637 __le16 req_len_type; 638 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 639 #define FWD_REQ_CMPL_TYPE_SFT 0 640 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 641 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 642 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 643 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 644 __le16 source_id; 645 __le32 unused0; 646 __le32 req_buf_addr_v[2]; 647 #define FWD_REQ_CMPL_V 0x1UL 648 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 649 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 650 }; 651 652 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 653 struct hwrm_fwd_resp_cmpl { 654 __le16 type; 655 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 656 #define FWD_RESP_CMPL_TYPE_SFT 0 657 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 658 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 659 __le16 source_id; 660 __le16 resp_len; 661 __le16 unused_1; 662 __le32 resp_buf_addr_v[2]; 663 #define FWD_RESP_CMPL_V 0x1UL 664 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 665 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 666 }; 667 668 /* hwrm_async_event_cmpl (size:128b/16B) */ 669 struct hwrm_async_event_cmpl { 670 __le16 type; 671 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 672 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 673 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 674 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 675 __le16 event_id; 676 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 677 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 678 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 679 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 680 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 681 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 682 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 683 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 684 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 685 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 686 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 687 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 688 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 689 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 690 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 691 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 692 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 693 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 694 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 695 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 696 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 697 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 698 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 699 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 700 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 701 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 702 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 703 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 704 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 705 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 706 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 707 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 708 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 709 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 710 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 711 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 712 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 713 __le32 event_data2; 714 u8 opaque_v; 715 #define ASYNC_EVENT_CMPL_V 0x1UL 716 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 717 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 718 u8 timestamp_lo; 719 __le16 timestamp_hi; 720 __le32 event_data1; 721 }; 722 723 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 724 struct hwrm_async_event_cmpl_link_status_change { 725 __le16 type; 726 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 727 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 728 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 729 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 730 __le16 event_id; 731 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 732 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 733 __le32 event_data2; 734 u8 opaque_v; 735 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 736 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 737 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 738 u8 timestamp_lo; 739 __le16 timestamp_hi; 740 __le32 event_data1; 741 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 742 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 743 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 744 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 745 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 746 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 747 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 748 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 749 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 750 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 751 }; 752 753 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 754 struct hwrm_async_event_cmpl_port_conn_not_allowed { 755 __le16 type; 756 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 757 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 758 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 759 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 760 __le16 event_id; 761 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 762 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 763 __le32 event_data2; 764 u8 opaque_v; 765 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 766 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 767 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 768 u8 timestamp_lo; 769 __le16 timestamp_hi; 770 __le32 event_data1; 771 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 772 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 773 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 774 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 775 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 776 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 777 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 778 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 779 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 780 }; 781 782 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 783 struct hwrm_async_event_cmpl_link_speed_cfg_change { 784 __le16 type; 785 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 786 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 787 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 788 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 789 __le16 event_id; 790 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 791 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 792 __le32 event_data2; 793 u8 opaque_v; 794 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 795 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 796 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 797 u8 timestamp_lo; 798 __le16 timestamp_hi; 799 __le32 event_data1; 800 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 801 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 802 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 803 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 804 }; 805 806 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 807 struct hwrm_async_event_cmpl_reset_notify { 808 __le16 type; 809 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 810 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 811 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 812 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 813 __le16 event_id; 814 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 815 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 816 __le32 event_data2; 817 u8 opaque_v; 818 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 819 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 820 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 821 u8 timestamp_lo; 822 __le16 timestamp_hi; 823 __le32 event_data1; 824 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 825 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 826 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 827 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 828 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 829 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 830 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 831 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 832 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 833 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 834 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 835 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 836 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 837 }; 838 839 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 840 struct hwrm_async_event_cmpl_error_recovery { 841 __le16 type; 842 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 843 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 844 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 845 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 846 __le16 event_id; 847 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 848 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 849 __le32 event_data2; 850 u8 opaque_v; 851 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 852 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 853 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 854 u8 timestamp_lo; 855 __le16 timestamp_hi; 856 __le32 event_data1; 857 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 858 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 859 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 860 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 861 }; 862 863 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 864 struct hwrm_async_event_cmpl_ring_monitor_msg { 865 __le16 type; 866 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 867 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 868 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 869 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 870 __le16 event_id; 871 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 872 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 873 __le32 event_data2; 874 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 875 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 876 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 877 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 878 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 879 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 880 u8 opaque_v; 881 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 882 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 883 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 884 u8 timestamp_lo; 885 __le16 timestamp_hi; 886 __le32 event_data1; 887 }; 888 889 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 890 struct hwrm_async_event_cmpl_vf_cfg_change { 891 __le16 type; 892 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 893 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 894 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 895 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 896 __le16 event_id; 897 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 898 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 899 __le32 event_data2; 900 u8 opaque_v; 901 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 902 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 903 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 904 u8 timestamp_lo; 905 __le16 timestamp_hi; 906 __le32 event_data1; 907 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 908 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 909 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 910 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 911 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 912 }; 913 914 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 915 struct hwrm_async_event_cmpl_default_vnic_change { 916 __le16 type; 917 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 918 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 919 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 920 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 921 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 922 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 923 __le16 event_id; 924 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 925 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 926 __le32 event_data2; 927 u8 opaque_v; 928 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 929 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 930 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 931 u8 timestamp_lo; 932 __le16 timestamp_hi; 933 __le32 event_data1; 934 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 935 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 936 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 937 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 938 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 939 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 940 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 941 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 942 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 943 }; 944 945 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 946 struct hwrm_async_event_cmpl_hw_flow_aged { 947 __le16 type; 948 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 949 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 950 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 951 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 952 __le16 event_id; 953 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 954 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 955 __le32 event_data2; 956 u8 opaque_v; 957 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 958 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 959 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 960 u8 timestamp_lo; 961 __le16 timestamp_hi; 962 __le32 event_data1; 963 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 964 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 965 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 966 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 967 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 968 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 969 }; 970 971 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 972 struct hwrm_async_event_cmpl_eem_cache_flush_req { 973 __le16 type; 974 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 975 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 976 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 977 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 978 __le16 event_id; 979 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 980 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 981 __le32 event_data2; 982 u8 opaque_v; 983 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 984 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 985 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 986 u8 timestamp_lo; 987 __le16 timestamp_hi; 988 __le32 event_data1; 989 }; 990 991 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 992 struct hwrm_async_event_cmpl_eem_cache_flush_done { 993 __le16 type; 994 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 995 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 996 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 997 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 998 __le16 event_id; 999 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1000 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1001 __le32 event_data2; 1002 u8 opaque_v; 1003 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1004 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1005 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1006 u8 timestamp_lo; 1007 __le16 timestamp_hi; 1008 __le32 event_data1; 1009 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1010 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1011 }; 1012 1013 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1014 struct hwrm_async_event_cmpl_deferred_response { 1015 __le16 type; 1016 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1017 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1018 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1019 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1020 __le16 event_id; 1021 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1022 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1023 __le32 event_data2; 1024 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1025 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1026 u8 opaque_v; 1027 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1028 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1029 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1030 u8 timestamp_lo; 1031 __le16 timestamp_hi; 1032 __le32 event_data1; 1033 }; 1034 1035 /* hwrm_func_reset_input (size:192b/24B) */ 1036 struct hwrm_func_reset_input { 1037 __le16 req_type; 1038 __le16 cmpl_ring; 1039 __le16 seq_id; 1040 __le16 target_id; 1041 __le64 resp_addr; 1042 __le32 enables; 1043 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1044 __le16 vf_id; 1045 u8 func_reset_level; 1046 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1047 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1048 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1049 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1050 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1051 u8 unused_0; 1052 }; 1053 1054 /* hwrm_func_reset_output (size:128b/16B) */ 1055 struct hwrm_func_reset_output { 1056 __le16 error_code; 1057 __le16 req_type; 1058 __le16 seq_id; 1059 __le16 resp_len; 1060 u8 unused_0[7]; 1061 u8 valid; 1062 }; 1063 1064 /* hwrm_func_getfid_input (size:192b/24B) */ 1065 struct hwrm_func_getfid_input { 1066 __le16 req_type; 1067 __le16 cmpl_ring; 1068 __le16 seq_id; 1069 __le16 target_id; 1070 __le64 resp_addr; 1071 __le32 enables; 1072 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1073 __le16 pci_id; 1074 u8 unused_0[2]; 1075 }; 1076 1077 /* hwrm_func_getfid_output (size:128b/16B) */ 1078 struct hwrm_func_getfid_output { 1079 __le16 error_code; 1080 __le16 req_type; 1081 __le16 seq_id; 1082 __le16 resp_len; 1083 __le16 fid; 1084 u8 unused_0[5]; 1085 u8 valid; 1086 }; 1087 1088 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1089 struct hwrm_func_vf_alloc_input { 1090 __le16 req_type; 1091 __le16 cmpl_ring; 1092 __le16 seq_id; 1093 __le16 target_id; 1094 __le64 resp_addr; 1095 __le32 enables; 1096 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1097 __le16 first_vf_id; 1098 __le16 num_vfs; 1099 }; 1100 1101 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1102 struct hwrm_func_vf_alloc_output { 1103 __le16 error_code; 1104 __le16 req_type; 1105 __le16 seq_id; 1106 __le16 resp_len; 1107 __le16 first_vf_id; 1108 u8 unused_0[5]; 1109 u8 valid; 1110 }; 1111 1112 /* hwrm_func_vf_free_input (size:192b/24B) */ 1113 struct hwrm_func_vf_free_input { 1114 __le16 req_type; 1115 __le16 cmpl_ring; 1116 __le16 seq_id; 1117 __le16 target_id; 1118 __le64 resp_addr; 1119 __le32 enables; 1120 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1121 __le16 first_vf_id; 1122 __le16 num_vfs; 1123 }; 1124 1125 /* hwrm_func_vf_free_output (size:128b/16B) */ 1126 struct hwrm_func_vf_free_output { 1127 __le16 error_code; 1128 __le16 req_type; 1129 __le16 seq_id; 1130 __le16 resp_len; 1131 u8 unused_0[7]; 1132 u8 valid; 1133 }; 1134 1135 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1136 struct hwrm_func_vf_cfg_input { 1137 __le16 req_type; 1138 __le16 cmpl_ring; 1139 __le16 seq_id; 1140 __le16 target_id; 1141 __le64 resp_addr; 1142 __le32 enables; 1143 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1144 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1145 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1146 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1147 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1148 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1149 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1150 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1151 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1152 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1153 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1154 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1155 __le16 mtu; 1156 __le16 guest_vlan; 1157 __le16 async_event_cr; 1158 u8 dflt_mac_addr[6]; 1159 __le32 flags; 1160 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1161 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1162 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1163 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1164 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1165 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1166 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1167 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1168 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1169 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1170 __le16 num_rsscos_ctxs; 1171 __le16 num_cmpl_rings; 1172 __le16 num_tx_rings; 1173 __le16 num_rx_rings; 1174 __le16 num_l2_ctxs; 1175 __le16 num_vnics; 1176 __le16 num_stat_ctxs; 1177 __le16 num_hw_ring_grps; 1178 u8 unused_0[4]; 1179 }; 1180 1181 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1182 struct hwrm_func_vf_cfg_output { 1183 __le16 error_code; 1184 __le16 req_type; 1185 __le16 seq_id; 1186 __le16 resp_len; 1187 u8 unused_0[7]; 1188 u8 valid; 1189 }; 1190 1191 /* hwrm_func_qcaps_input (size:192b/24B) */ 1192 struct hwrm_func_qcaps_input { 1193 __le16 req_type; 1194 __le16 cmpl_ring; 1195 __le16 seq_id; 1196 __le16 target_id; 1197 __le64 resp_addr; 1198 __le16 fid; 1199 u8 unused_0[6]; 1200 }; 1201 1202 /* hwrm_func_qcaps_output (size:704b/88B) */ 1203 struct hwrm_func_qcaps_output { 1204 __le16 error_code; 1205 __le16 req_type; 1206 __le16 seq_id; 1207 __le16 resp_len; 1208 __le16 fid; 1209 __le16 port_id; 1210 __le32 flags; 1211 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1212 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1213 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1214 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1215 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1216 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1217 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1218 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1219 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1220 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1221 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1222 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1223 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1224 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1225 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1226 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1227 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1228 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1229 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1230 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1231 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1232 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1233 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1234 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1235 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1236 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1237 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1238 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1239 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1240 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1241 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1242 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1243 u8 mac_address[6]; 1244 __le16 max_rsscos_ctx; 1245 __le16 max_cmpl_rings; 1246 __le16 max_tx_rings; 1247 __le16 max_rx_rings; 1248 __le16 max_l2_ctxs; 1249 __le16 max_vnics; 1250 __le16 first_vf_id; 1251 __le16 max_vfs; 1252 __le16 max_stat_ctx; 1253 __le32 max_encap_records; 1254 __le32 max_decap_records; 1255 __le32 max_tx_em_flows; 1256 __le32 max_tx_wm_flows; 1257 __le32 max_rx_em_flows; 1258 __le32 max_rx_wm_flows; 1259 __le32 max_mcast_filters; 1260 __le32 max_flow_id; 1261 __le32 max_hw_ring_grps; 1262 __le16 max_sp_tx_rings; 1263 u8 unused_0[2]; 1264 __le32 flags_ext; 1265 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1266 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1267 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1268 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1269 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1270 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1271 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1272 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1273 u8 max_schqs; 1274 u8 mpc_chnls_cap; 1275 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1276 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1277 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1278 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1279 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1280 u8 unused_1; 1281 u8 valid; 1282 }; 1283 1284 /* hwrm_func_qcfg_input (size:192b/24B) */ 1285 struct hwrm_func_qcfg_input { 1286 __le16 req_type; 1287 __le16 cmpl_ring; 1288 __le16 seq_id; 1289 __le16 target_id; 1290 __le64 resp_addr; 1291 __le16 fid; 1292 u8 unused_0[6]; 1293 }; 1294 1295 /* hwrm_func_qcfg_output (size:768b/96B) */ 1296 struct hwrm_func_qcfg_output { 1297 __le16 error_code; 1298 __le16 req_type; 1299 __le16 seq_id; 1300 __le16 resp_len; 1301 __le16 fid; 1302 __le16 port_id; 1303 __le16 vlan; 1304 __le16 flags; 1305 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1306 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1307 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1308 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1309 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1310 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1311 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1312 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1313 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1314 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1315 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1316 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1317 u8 mac_address[6]; 1318 __le16 pci_id; 1319 __le16 alloc_rsscos_ctx; 1320 __le16 alloc_cmpl_rings; 1321 __le16 alloc_tx_rings; 1322 __le16 alloc_rx_rings; 1323 __le16 alloc_l2_ctx; 1324 __le16 alloc_vnics; 1325 __le16 mtu; 1326 __le16 mru; 1327 __le16 stat_ctx_id; 1328 u8 port_partition_type; 1329 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1330 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1331 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1332 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1333 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1334 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1335 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1336 u8 port_pf_cnt; 1337 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1338 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1339 __le16 dflt_vnic_id; 1340 __le16 max_mtu_configured; 1341 __le32 min_bw; 1342 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1343 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1344 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1345 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1346 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1347 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1348 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1349 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1350 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1351 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1352 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1353 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1354 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1355 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1356 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1357 __le32 max_bw; 1358 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1359 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1360 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1361 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1362 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1363 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1364 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1365 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1366 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1367 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1368 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1369 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1370 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1371 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1372 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1373 u8 evb_mode; 1374 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1375 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1376 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1377 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1378 u8 options; 1379 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1380 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1381 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1382 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1383 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1384 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1385 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1386 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1387 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1388 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1389 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1390 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1391 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1392 __le16 alloc_vfs; 1393 __le32 alloc_mcast_filters; 1394 __le32 alloc_hw_ring_grps; 1395 __le16 alloc_sp_tx_rings; 1396 __le16 alloc_stat_ctx; 1397 __le16 alloc_msix; 1398 __le16 registered_vfs; 1399 __le16 l2_doorbell_bar_size_kb; 1400 u8 unused_1; 1401 u8 always_1; 1402 __le32 reset_addr_poll; 1403 __le16 legacy_l2_db_size_kb; 1404 __le16 svif_info; 1405 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1406 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1407 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1408 u8 mpc_chnls; 1409 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1410 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1411 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1412 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1413 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1414 u8 unused_2[6]; 1415 u8 valid; 1416 }; 1417 1418 /* hwrm_func_cfg_input (size:768b/96B) */ 1419 struct hwrm_func_cfg_input { 1420 __le16 req_type; 1421 __le16 cmpl_ring; 1422 __le16 seq_id; 1423 __le16 target_id; 1424 __le64 resp_addr; 1425 __le16 fid; 1426 __le16 num_msix; 1427 __le32 flags; 1428 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1429 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1430 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1431 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1432 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1433 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1434 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1435 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1436 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1437 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1438 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1439 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1440 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1441 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1442 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1443 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1444 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1445 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1446 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1447 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1448 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1449 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1450 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1451 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1452 __le32 enables; 1453 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1454 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1455 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1456 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1457 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1458 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1459 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1460 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1461 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1462 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1463 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1464 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1465 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1466 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1467 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1468 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1469 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1470 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1471 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1472 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1473 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1474 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1475 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1476 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1477 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1478 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1479 __le16 mtu; 1480 __le16 mru; 1481 __le16 num_rsscos_ctxs; 1482 __le16 num_cmpl_rings; 1483 __le16 num_tx_rings; 1484 __le16 num_rx_rings; 1485 __le16 num_l2_ctxs; 1486 __le16 num_vnics; 1487 __le16 num_stat_ctxs; 1488 __le16 num_hw_ring_grps; 1489 u8 dflt_mac_addr[6]; 1490 __le16 dflt_vlan; 1491 __be32 dflt_ip_addr[4]; 1492 __le32 min_bw; 1493 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1494 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1495 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1496 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1497 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1498 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1499 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1500 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1501 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1502 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1503 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1504 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1505 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1506 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1507 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1508 __le32 max_bw; 1509 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1510 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1511 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1512 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1513 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1514 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1515 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1516 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1517 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1518 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1519 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1520 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1521 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1522 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1523 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1524 __le16 async_event_cr; 1525 u8 vlan_antispoof_mode; 1526 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1527 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1528 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1529 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1530 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1531 u8 allowed_vlan_pris; 1532 u8 evb_mode; 1533 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1534 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1535 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1536 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1537 u8 options; 1538 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1539 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1540 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1541 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1542 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1543 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1544 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1545 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1546 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1547 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1548 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1549 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1550 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1551 __le16 num_mcast_filters; 1552 __le16 schq_id; 1553 __le16 mpc_chnls; 1554 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1555 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1556 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1557 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1558 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1559 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1560 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1561 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1562 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1563 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1564 u8 unused_0[4]; 1565 }; 1566 1567 /* hwrm_func_cfg_output (size:128b/16B) */ 1568 struct hwrm_func_cfg_output { 1569 __le16 error_code; 1570 __le16 req_type; 1571 __le16 seq_id; 1572 __le16 resp_len; 1573 u8 unused_0[7]; 1574 u8 valid; 1575 }; 1576 1577 /* hwrm_func_qstats_input (size:192b/24B) */ 1578 struct hwrm_func_qstats_input { 1579 __le16 req_type; 1580 __le16 cmpl_ring; 1581 __le16 seq_id; 1582 __le16 target_id; 1583 __le64 resp_addr; 1584 __le16 fid; 1585 u8 flags; 1586 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1587 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1588 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1589 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1590 u8 unused_0[5]; 1591 }; 1592 1593 /* hwrm_func_qstats_output (size:1408b/176B) */ 1594 struct hwrm_func_qstats_output { 1595 __le16 error_code; 1596 __le16 req_type; 1597 __le16 seq_id; 1598 __le16 resp_len; 1599 __le64 tx_ucast_pkts; 1600 __le64 tx_mcast_pkts; 1601 __le64 tx_bcast_pkts; 1602 __le64 tx_discard_pkts; 1603 __le64 tx_drop_pkts; 1604 __le64 tx_ucast_bytes; 1605 __le64 tx_mcast_bytes; 1606 __le64 tx_bcast_bytes; 1607 __le64 rx_ucast_pkts; 1608 __le64 rx_mcast_pkts; 1609 __le64 rx_bcast_pkts; 1610 __le64 rx_discard_pkts; 1611 __le64 rx_drop_pkts; 1612 __le64 rx_ucast_bytes; 1613 __le64 rx_mcast_bytes; 1614 __le64 rx_bcast_bytes; 1615 __le64 rx_agg_pkts; 1616 __le64 rx_agg_bytes; 1617 __le64 rx_agg_events; 1618 __le64 rx_agg_aborts; 1619 u8 unused_0[7]; 1620 u8 valid; 1621 }; 1622 1623 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1624 struct hwrm_func_qstats_ext_input { 1625 __le16 req_type; 1626 __le16 cmpl_ring; 1627 __le16 seq_id; 1628 __le16 target_id; 1629 __le64 resp_addr; 1630 __le16 fid; 1631 u8 flags; 1632 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1633 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1634 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1635 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1636 u8 unused_0[1]; 1637 __le32 enables; 1638 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 1639 __le16 schq_id; 1640 __le16 traffic_class; 1641 u8 unused_1[4]; 1642 }; 1643 1644 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 1645 struct hwrm_func_qstats_ext_output { 1646 __le16 error_code; 1647 __le16 req_type; 1648 __le16 seq_id; 1649 __le16 resp_len; 1650 __le64 rx_ucast_pkts; 1651 __le64 rx_mcast_pkts; 1652 __le64 rx_bcast_pkts; 1653 __le64 rx_discard_pkts; 1654 __le64 rx_error_pkts; 1655 __le64 rx_ucast_bytes; 1656 __le64 rx_mcast_bytes; 1657 __le64 rx_bcast_bytes; 1658 __le64 tx_ucast_pkts; 1659 __le64 tx_mcast_pkts; 1660 __le64 tx_bcast_pkts; 1661 __le64 tx_error_pkts; 1662 __le64 tx_discard_pkts; 1663 __le64 tx_ucast_bytes; 1664 __le64 tx_mcast_bytes; 1665 __le64 tx_bcast_bytes; 1666 __le64 rx_tpa_eligible_pkt; 1667 __le64 rx_tpa_eligible_bytes; 1668 __le64 rx_tpa_pkt; 1669 __le64 rx_tpa_bytes; 1670 __le64 rx_tpa_errors; 1671 __le64 rx_tpa_events; 1672 u8 unused_0[7]; 1673 u8 valid; 1674 }; 1675 1676 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1677 struct hwrm_func_clr_stats_input { 1678 __le16 req_type; 1679 __le16 cmpl_ring; 1680 __le16 seq_id; 1681 __le16 target_id; 1682 __le64 resp_addr; 1683 __le16 fid; 1684 u8 unused_0[6]; 1685 }; 1686 1687 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1688 struct hwrm_func_clr_stats_output { 1689 __le16 error_code; 1690 __le16 req_type; 1691 __le16 seq_id; 1692 __le16 resp_len; 1693 u8 unused_0[7]; 1694 u8 valid; 1695 }; 1696 1697 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1698 struct hwrm_func_vf_resc_free_input { 1699 __le16 req_type; 1700 __le16 cmpl_ring; 1701 __le16 seq_id; 1702 __le16 target_id; 1703 __le64 resp_addr; 1704 __le16 vf_id; 1705 u8 unused_0[6]; 1706 }; 1707 1708 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1709 struct hwrm_func_vf_resc_free_output { 1710 __le16 error_code; 1711 __le16 req_type; 1712 __le16 seq_id; 1713 __le16 resp_len; 1714 u8 unused_0[7]; 1715 u8 valid; 1716 }; 1717 1718 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1719 struct hwrm_func_drv_rgtr_input { 1720 __le16 req_type; 1721 __le16 cmpl_ring; 1722 __le16 seq_id; 1723 __le16 target_id; 1724 __le64 resp_addr; 1725 __le32 flags; 1726 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1727 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1728 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1729 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1730 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1731 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1732 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1733 __le32 enables; 1734 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1735 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1736 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1737 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1738 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1739 __le16 os_type; 1740 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1741 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1742 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1743 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1744 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1745 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1746 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1747 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1748 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1749 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1750 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1751 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1752 u8 ver_maj_8b; 1753 u8 ver_min_8b; 1754 u8 ver_upd_8b; 1755 u8 unused_0[3]; 1756 __le32 timestamp; 1757 u8 unused_1[4]; 1758 __le32 vf_req_fwd[8]; 1759 __le32 async_event_fwd[8]; 1760 __le16 ver_maj; 1761 __le16 ver_min; 1762 __le16 ver_upd; 1763 __le16 ver_patch; 1764 }; 1765 1766 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1767 struct hwrm_func_drv_rgtr_output { 1768 __le16 error_code; 1769 __le16 req_type; 1770 __le16 seq_id; 1771 __le16 resp_len; 1772 __le32 flags; 1773 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1774 u8 unused_0[3]; 1775 u8 valid; 1776 }; 1777 1778 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1779 struct hwrm_func_drv_unrgtr_input { 1780 __le16 req_type; 1781 __le16 cmpl_ring; 1782 __le16 seq_id; 1783 __le16 target_id; 1784 __le64 resp_addr; 1785 __le32 flags; 1786 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1787 u8 unused_0[4]; 1788 }; 1789 1790 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1791 struct hwrm_func_drv_unrgtr_output { 1792 __le16 error_code; 1793 __le16 req_type; 1794 __le16 seq_id; 1795 __le16 resp_len; 1796 u8 unused_0[7]; 1797 u8 valid; 1798 }; 1799 1800 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1801 struct hwrm_func_buf_rgtr_input { 1802 __le16 req_type; 1803 __le16 cmpl_ring; 1804 __le16 seq_id; 1805 __le16 target_id; 1806 __le64 resp_addr; 1807 __le32 enables; 1808 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1809 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1810 __le16 vf_id; 1811 __le16 req_buf_num_pages; 1812 __le16 req_buf_page_size; 1813 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1814 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1815 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1816 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1817 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1818 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1819 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1820 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1821 __le16 req_buf_len; 1822 __le16 resp_buf_len; 1823 u8 unused_0[2]; 1824 __le64 req_buf_page_addr0; 1825 __le64 req_buf_page_addr1; 1826 __le64 req_buf_page_addr2; 1827 __le64 req_buf_page_addr3; 1828 __le64 req_buf_page_addr4; 1829 __le64 req_buf_page_addr5; 1830 __le64 req_buf_page_addr6; 1831 __le64 req_buf_page_addr7; 1832 __le64 req_buf_page_addr8; 1833 __le64 req_buf_page_addr9; 1834 __le64 error_buf_addr; 1835 __le64 resp_buf_addr; 1836 }; 1837 1838 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1839 struct hwrm_func_buf_rgtr_output { 1840 __le16 error_code; 1841 __le16 req_type; 1842 __le16 seq_id; 1843 __le16 resp_len; 1844 u8 unused_0[7]; 1845 u8 valid; 1846 }; 1847 1848 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1849 struct hwrm_func_drv_qver_input { 1850 __le16 req_type; 1851 __le16 cmpl_ring; 1852 __le16 seq_id; 1853 __le16 target_id; 1854 __le64 resp_addr; 1855 __le32 reserved; 1856 __le16 fid; 1857 u8 unused_0[2]; 1858 }; 1859 1860 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1861 struct hwrm_func_drv_qver_output { 1862 __le16 error_code; 1863 __le16 req_type; 1864 __le16 seq_id; 1865 __le16 resp_len; 1866 __le16 os_type; 1867 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1868 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1869 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1870 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1871 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1872 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1873 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1874 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1875 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1876 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1877 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1878 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1879 u8 ver_maj_8b; 1880 u8 ver_min_8b; 1881 u8 ver_upd_8b; 1882 u8 unused_0[3]; 1883 __le16 ver_maj; 1884 __le16 ver_min; 1885 __le16 ver_upd; 1886 __le16 ver_patch; 1887 u8 unused_1[7]; 1888 u8 valid; 1889 }; 1890 1891 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1892 struct hwrm_func_resource_qcaps_input { 1893 __le16 req_type; 1894 __le16 cmpl_ring; 1895 __le16 seq_id; 1896 __le16 target_id; 1897 __le64 resp_addr; 1898 __le16 fid; 1899 u8 unused_0[6]; 1900 }; 1901 1902 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1903 struct hwrm_func_resource_qcaps_output { 1904 __le16 error_code; 1905 __le16 req_type; 1906 __le16 seq_id; 1907 __le16 resp_len; 1908 __le16 max_vfs; 1909 __le16 max_msix; 1910 __le16 vf_reservation_strategy; 1911 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1912 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1913 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1914 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1915 __le16 min_rsscos_ctx; 1916 __le16 max_rsscos_ctx; 1917 __le16 min_cmpl_rings; 1918 __le16 max_cmpl_rings; 1919 __le16 min_tx_rings; 1920 __le16 max_tx_rings; 1921 __le16 min_rx_rings; 1922 __le16 max_rx_rings; 1923 __le16 min_l2_ctxs; 1924 __le16 max_l2_ctxs; 1925 __le16 min_vnics; 1926 __le16 max_vnics; 1927 __le16 min_stat_ctx; 1928 __le16 max_stat_ctx; 1929 __le16 min_hw_ring_grps; 1930 __le16 max_hw_ring_grps; 1931 __le16 max_tx_scheduler_inputs; 1932 __le16 flags; 1933 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1934 u8 unused_0[5]; 1935 u8 valid; 1936 }; 1937 1938 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1939 struct hwrm_func_vf_resource_cfg_input { 1940 __le16 req_type; 1941 __le16 cmpl_ring; 1942 __le16 seq_id; 1943 __le16 target_id; 1944 __le64 resp_addr; 1945 __le16 vf_id; 1946 __le16 max_msix; 1947 __le16 min_rsscos_ctx; 1948 __le16 max_rsscos_ctx; 1949 __le16 min_cmpl_rings; 1950 __le16 max_cmpl_rings; 1951 __le16 min_tx_rings; 1952 __le16 max_tx_rings; 1953 __le16 min_rx_rings; 1954 __le16 max_rx_rings; 1955 __le16 min_l2_ctxs; 1956 __le16 max_l2_ctxs; 1957 __le16 min_vnics; 1958 __le16 max_vnics; 1959 __le16 min_stat_ctx; 1960 __le16 max_stat_ctx; 1961 __le16 min_hw_ring_grps; 1962 __le16 max_hw_ring_grps; 1963 __le16 flags; 1964 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1965 u8 unused_0[2]; 1966 }; 1967 1968 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1969 struct hwrm_func_vf_resource_cfg_output { 1970 __le16 error_code; 1971 __le16 req_type; 1972 __le16 seq_id; 1973 __le16 resp_len; 1974 __le16 reserved_rsscos_ctx; 1975 __le16 reserved_cmpl_rings; 1976 __le16 reserved_tx_rings; 1977 __le16 reserved_rx_rings; 1978 __le16 reserved_l2_ctxs; 1979 __le16 reserved_vnics; 1980 __le16 reserved_stat_ctx; 1981 __le16 reserved_hw_ring_grps; 1982 u8 unused_0[7]; 1983 u8 valid; 1984 }; 1985 1986 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1987 struct hwrm_func_backing_store_qcaps_input { 1988 __le16 req_type; 1989 __le16 cmpl_ring; 1990 __le16 seq_id; 1991 __le16 target_id; 1992 __le64 resp_addr; 1993 }; 1994 1995 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ 1996 struct hwrm_func_backing_store_qcaps_output { 1997 __le16 error_code; 1998 __le16 req_type; 1999 __le16 seq_id; 2000 __le16 resp_len; 2001 __le32 qp_max_entries; 2002 __le16 qp_min_qp1_entries; 2003 __le16 qp_max_l2_entries; 2004 __le16 qp_entry_size; 2005 __le16 srq_max_l2_entries; 2006 __le32 srq_max_entries; 2007 __le16 srq_entry_size; 2008 __le16 cq_max_l2_entries; 2009 __le32 cq_max_entries; 2010 __le16 cq_entry_size; 2011 __le16 vnic_max_vnic_entries; 2012 __le16 vnic_max_ring_table_entries; 2013 __le16 vnic_entry_size; 2014 __le32 stat_max_entries; 2015 __le16 stat_entry_size; 2016 __le16 tqm_entry_size; 2017 __le32 tqm_min_entries_per_ring; 2018 __le32 tqm_max_entries_per_ring; 2019 __le32 mrav_max_entries; 2020 __le16 mrav_entry_size; 2021 __le16 tim_entry_size; 2022 __le32 tim_max_entries; 2023 __le16 mrav_num_entries_units; 2024 u8 tqm_entries_multiple; 2025 u8 ctx_kind_initializer; 2026 __le32 rsvd; 2027 __le16 rsvd1; 2028 u8 tqm_fp_rings_count; 2029 u8 valid; 2030 }; 2031 2032 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 2033 struct hwrm_func_backing_store_cfg_input { 2034 __le16 req_type; 2035 __le16 cmpl_ring; 2036 __le16 seq_id; 2037 __le16 target_id; 2038 __le64 resp_addr; 2039 __le32 flags; 2040 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2041 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2042 __le32 enables; 2043 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2044 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2045 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2046 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2047 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2048 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2049 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2050 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2051 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2052 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2053 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2054 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2055 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2056 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2057 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2058 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2059 u8 qpc_pg_size_qpc_lvl; 2060 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2061 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2062 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2063 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2064 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2065 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2066 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2067 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2068 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2069 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2070 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2071 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2072 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2073 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2074 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2075 u8 srq_pg_size_srq_lvl; 2076 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2077 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2078 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2079 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2080 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2081 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2082 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2083 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2084 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2085 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2086 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2087 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2088 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2089 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2090 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2091 u8 cq_pg_size_cq_lvl; 2092 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2093 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2094 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2095 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2096 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2097 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2098 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2099 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2100 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2101 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2102 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2103 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2104 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2105 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2106 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2107 u8 vnic_pg_size_vnic_lvl; 2108 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2109 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2110 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2111 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2112 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2113 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2114 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2115 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2116 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2117 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2118 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2119 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2120 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2121 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2122 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2123 u8 stat_pg_size_stat_lvl; 2124 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2125 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2126 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2127 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2128 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2129 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2130 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2131 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2132 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2133 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2134 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2135 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2136 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2137 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2138 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2139 u8 tqm_sp_pg_size_tqm_sp_lvl; 2140 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2144 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2148 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2151 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2152 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2155 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2156 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2157 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2158 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2159 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2160 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2161 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2162 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2163 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2164 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2165 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2166 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2167 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2168 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2169 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2170 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2171 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2172 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2173 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2174 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2175 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2176 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2177 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2178 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2179 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2180 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2181 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2182 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2183 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2184 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2185 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2186 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2187 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2188 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2189 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2190 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2191 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2192 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2193 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2194 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2195 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2196 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2197 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2198 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2199 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2200 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2201 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2202 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2203 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2204 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2205 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2206 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2207 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2208 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2209 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2210 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2211 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2212 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2213 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2214 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2215 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2216 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2217 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2218 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2219 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2220 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2221 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2222 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2223 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2224 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2225 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2226 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2227 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2228 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2229 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2230 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2231 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2232 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2233 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2234 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2235 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2236 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2237 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2238 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2239 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2240 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2241 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2242 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2243 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2244 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2245 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2246 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2247 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2248 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2249 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2250 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2251 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2252 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2253 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2254 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2255 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2256 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2257 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2258 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2259 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2260 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2261 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2262 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2263 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2264 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2265 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2266 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2267 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2268 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2269 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2270 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2271 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2272 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2273 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2274 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2275 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2276 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2277 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2278 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2279 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2280 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2281 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2282 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2283 u8 mrav_pg_size_mrav_lvl; 2284 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2285 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2286 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2287 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2288 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2289 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2290 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2291 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2292 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2293 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2294 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2295 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2296 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2297 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2298 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2299 u8 tim_pg_size_tim_lvl; 2300 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2301 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2302 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2303 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2304 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2305 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2306 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2307 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2308 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2309 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2310 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2311 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2312 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2313 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2314 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2315 __le64 qpc_page_dir; 2316 __le64 srq_page_dir; 2317 __le64 cq_page_dir; 2318 __le64 vnic_page_dir; 2319 __le64 stat_page_dir; 2320 __le64 tqm_sp_page_dir; 2321 __le64 tqm_ring0_page_dir; 2322 __le64 tqm_ring1_page_dir; 2323 __le64 tqm_ring2_page_dir; 2324 __le64 tqm_ring3_page_dir; 2325 __le64 tqm_ring4_page_dir; 2326 __le64 tqm_ring5_page_dir; 2327 __le64 tqm_ring6_page_dir; 2328 __le64 tqm_ring7_page_dir; 2329 __le64 mrav_page_dir; 2330 __le64 tim_page_dir; 2331 __le32 qp_num_entries; 2332 __le32 srq_num_entries; 2333 __le32 cq_num_entries; 2334 __le32 stat_num_entries; 2335 __le32 tqm_sp_num_entries; 2336 __le32 tqm_ring0_num_entries; 2337 __le32 tqm_ring1_num_entries; 2338 __le32 tqm_ring2_num_entries; 2339 __le32 tqm_ring3_num_entries; 2340 __le32 tqm_ring4_num_entries; 2341 __le32 tqm_ring5_num_entries; 2342 __le32 tqm_ring6_num_entries; 2343 __le32 tqm_ring7_num_entries; 2344 __le32 mrav_num_entries; 2345 __le32 tim_num_entries; 2346 __le16 qp_num_qp1_entries; 2347 __le16 qp_num_l2_entries; 2348 __le16 qp_entry_size; 2349 __le16 srq_num_l2_entries; 2350 __le16 srq_entry_size; 2351 __le16 cq_num_l2_entries; 2352 __le16 cq_entry_size; 2353 __le16 vnic_num_vnic_entries; 2354 __le16 vnic_num_ring_table_entries; 2355 __le16 vnic_entry_size; 2356 __le16 stat_entry_size; 2357 __le16 tqm_entry_size; 2358 __le16 mrav_entry_size; 2359 __le16 tim_entry_size; 2360 }; 2361 2362 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2363 struct hwrm_func_backing_store_cfg_output { 2364 __le16 error_code; 2365 __le16 req_type; 2366 __le16 seq_id; 2367 __le16 resp_len; 2368 u8 unused_0[7]; 2369 u8 valid; 2370 }; 2371 2372 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2373 struct hwrm_error_recovery_qcfg_input { 2374 __le16 req_type; 2375 __le16 cmpl_ring; 2376 __le16 seq_id; 2377 __le16 target_id; 2378 __le64 resp_addr; 2379 u8 unused_0[8]; 2380 }; 2381 2382 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2383 struct hwrm_error_recovery_qcfg_output { 2384 __le16 error_code; 2385 __le16 req_type; 2386 __le16 seq_id; 2387 __le16 resp_len; 2388 __le32 flags; 2389 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2390 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2391 __le32 driver_polling_freq; 2392 __le32 master_func_wait_period; 2393 __le32 normal_func_wait_period; 2394 __le32 master_func_wait_period_after_reset; 2395 __le32 max_bailout_time_after_reset; 2396 __le32 fw_health_status_reg; 2397 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2398 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2399 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2400 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2401 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2402 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2403 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2404 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2405 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2406 __le32 fw_heartbeat_reg; 2407 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2408 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2409 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2410 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2411 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2412 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2413 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2414 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2415 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2416 __le32 fw_reset_cnt_reg; 2417 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2418 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2419 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2420 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2421 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2422 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2423 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2424 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2425 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2426 __le32 reset_inprogress_reg; 2427 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2428 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2429 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2430 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2431 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2432 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2433 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2434 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2435 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2436 __le32 reset_inprogress_reg_mask; 2437 u8 unused_0[3]; 2438 u8 reg_array_cnt; 2439 __le32 reset_reg[16]; 2440 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2441 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2442 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2443 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2444 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2445 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2446 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2447 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2448 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2449 __le32 reset_reg_val[16]; 2450 u8 delay_after_reset[16]; 2451 __le32 err_recovery_cnt_reg; 2452 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2453 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2454 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2455 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2456 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2457 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2458 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2459 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2460 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2461 u8 unused_1[3]; 2462 u8 valid; 2463 }; 2464 2465 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2466 struct hwrm_func_drv_if_change_input { 2467 __le16 req_type; 2468 __le16 cmpl_ring; 2469 __le16 seq_id; 2470 __le16 target_id; 2471 __le64 resp_addr; 2472 __le32 flags; 2473 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2474 __le32 unused; 2475 }; 2476 2477 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2478 struct hwrm_func_drv_if_change_output { 2479 __le16 error_code; 2480 __le16 req_type; 2481 __le16 seq_id; 2482 __le16 resp_len; 2483 __le32 flags; 2484 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2485 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2486 u8 unused_0[3]; 2487 u8 valid; 2488 }; 2489 2490 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2491 struct hwrm_port_phy_cfg_input { 2492 __le16 req_type; 2493 __le16 cmpl_ring; 2494 __le16 seq_id; 2495 __le16 target_id; 2496 __le64 resp_addr; 2497 __le32 flags; 2498 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2499 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2500 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2501 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2502 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2503 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2504 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2505 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2506 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2507 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2508 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2509 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2510 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2511 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2512 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2513 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 2514 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 2515 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 2516 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 2517 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 2518 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 2519 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 2520 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 2521 __le32 enables; 2522 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2523 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2524 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2525 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2526 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2527 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2528 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2529 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2530 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2531 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2532 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2533 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 2534 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 2535 __le16 port_id; 2536 __le16 force_link_speed; 2537 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2538 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2539 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2540 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2541 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2542 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2543 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2544 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2545 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2546 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2547 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2548 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2549 u8 auto_mode; 2550 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2551 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2552 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2553 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2554 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2555 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2556 u8 auto_duplex; 2557 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2558 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2559 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2560 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2561 u8 auto_pause; 2562 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2563 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2564 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2565 u8 unused_0; 2566 __le16 auto_link_speed; 2567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2569 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2570 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2571 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2572 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2573 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2574 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2575 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2576 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2577 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2578 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2579 __le16 auto_link_speed_mask; 2580 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2581 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2582 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2583 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2584 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2585 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2586 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2587 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2588 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2589 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2590 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2591 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2592 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2593 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2594 u8 wirespeed; 2595 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2596 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2597 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2598 u8 lpbk; 2599 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2600 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2601 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2602 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2603 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2604 u8 force_pause; 2605 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2606 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2607 u8 unused_1; 2608 __le32 preemphasis; 2609 __le16 eee_link_speed_mask; 2610 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2611 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2612 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2613 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2614 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2615 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2616 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2617 __le16 force_pam4_link_speed; 2618 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2619 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2620 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2621 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 2622 __le32 tx_lpi_timer; 2623 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2624 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2625 __le16 auto_link_pam4_speed_mask; 2626 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 2627 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 2628 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 2629 u8 unused_2[2]; 2630 }; 2631 2632 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2633 struct hwrm_port_phy_cfg_output { 2634 __le16 error_code; 2635 __le16 req_type; 2636 __le16 seq_id; 2637 __le16 resp_len; 2638 u8 unused_0[7]; 2639 u8 valid; 2640 }; 2641 2642 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2643 struct hwrm_port_phy_cfg_cmd_err { 2644 u8 code; 2645 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2646 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2647 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2648 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2649 u8 unused_0[7]; 2650 }; 2651 2652 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2653 struct hwrm_port_phy_qcfg_input { 2654 __le16 req_type; 2655 __le16 cmpl_ring; 2656 __le16 seq_id; 2657 __le16 target_id; 2658 __le64 resp_addr; 2659 __le16 port_id; 2660 u8 unused_0[6]; 2661 }; 2662 2663 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2664 struct hwrm_port_phy_qcfg_output { 2665 __le16 error_code; 2666 __le16 req_type; 2667 __le16 seq_id; 2668 __le16 resp_len; 2669 u8 link; 2670 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2671 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2672 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2673 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2674 u8 active_fec_signal_mode; 2675 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 2676 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 2677 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 2678 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 2679 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 2680 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 2681 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 2682 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 2683 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 2684 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 2685 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 2686 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 2687 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 2688 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 2689 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 2690 __le16 link_speed; 2691 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2692 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2693 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2694 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2695 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2696 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2697 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2698 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2699 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2700 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2701 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2702 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2703 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2704 u8 duplex_cfg; 2705 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2706 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2707 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2708 u8 pause; 2709 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2710 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2711 __le16 support_speeds; 2712 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2713 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2714 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2715 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2716 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2717 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2718 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2719 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2720 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2721 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2722 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2723 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2724 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2725 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2726 __le16 force_link_speed; 2727 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2728 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2729 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2730 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2731 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2732 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2733 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2734 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2735 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2736 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2737 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2738 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2739 u8 auto_mode; 2740 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2741 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2742 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2743 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2744 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2745 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2746 u8 auto_pause; 2747 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2748 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2749 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2750 __le16 auto_link_speed; 2751 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2752 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2753 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2754 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2755 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2756 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2757 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2758 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2759 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2760 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2761 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2762 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2763 __le16 auto_link_speed_mask; 2764 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2765 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2766 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2767 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2768 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2769 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2770 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2771 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2772 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2773 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2774 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2775 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2776 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2777 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2778 u8 wirespeed; 2779 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2780 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2781 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2782 u8 lpbk; 2783 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2784 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2785 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2786 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2787 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2788 u8 force_pause; 2789 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2790 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2791 u8 module_status; 2792 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2793 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2794 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2795 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2796 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2797 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2798 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2799 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2800 __le32 preemphasis; 2801 u8 phy_maj; 2802 u8 phy_min; 2803 u8 phy_bld; 2804 u8 phy_type; 2805 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2806 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2807 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2808 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2809 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2810 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2811 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2812 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2813 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2814 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2815 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2816 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2817 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2818 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2819 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2820 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2821 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2822 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2823 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2824 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2825 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2826 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2827 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2828 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2829 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2830 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2831 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2832 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2833 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2834 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2835 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2836 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2837 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2838 u8 media_type; 2839 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2840 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2841 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2842 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2843 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2844 u8 xcvr_pkg_type; 2845 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2846 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2847 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2848 u8 eee_config_phy_addr; 2849 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2850 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2851 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2852 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2853 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2854 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2855 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2856 u8 parallel_detect; 2857 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2858 __le16 link_partner_adv_speeds; 2859 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2860 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2861 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2862 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2863 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2864 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2865 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2866 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2867 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2868 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2869 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2870 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2871 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2872 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2873 u8 link_partner_adv_auto_mode; 2874 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2875 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2876 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2877 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2878 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2879 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2880 u8 link_partner_adv_pause; 2881 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2882 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2883 __le16 adv_eee_link_speed_mask; 2884 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2885 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2886 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2887 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2888 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2889 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2890 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2891 __le16 link_partner_adv_eee_link_speed_mask; 2892 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2893 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2894 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2895 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2896 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2897 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2898 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2899 __le32 xcvr_identifier_type_tx_lpi_timer; 2900 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2901 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2902 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2903 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2904 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2905 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2906 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2907 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2908 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2909 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2910 __le16 fec_cfg; 2911 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2912 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2913 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2914 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2915 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2916 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2917 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2918 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 2919 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 2920 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 2921 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 2922 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 2923 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 2924 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 2925 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 2926 u8 duplex_state; 2927 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2928 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2929 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2930 u8 option_flags; 2931 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2932 char phy_vendor_name[16]; 2933 char phy_vendor_partnumber[16]; 2934 __le16 support_pam4_speeds; 2935 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 2936 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 2937 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 2938 __le16 force_pam4_link_speed; 2939 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2940 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2941 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2942 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 2943 __le16 auto_pam4_link_speed_mask; 2944 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 2945 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 2946 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 2947 u8 link_partner_pam4_adv_speeds; 2948 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 2949 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 2950 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 2951 u8 valid; 2952 }; 2953 2954 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 2955 struct hwrm_port_mac_cfg_input { 2956 __le16 req_type; 2957 __le16 cmpl_ring; 2958 __le16 seq_id; 2959 __le16 target_id; 2960 __le64 resp_addr; 2961 __le32 flags; 2962 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2963 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2964 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2965 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2966 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2967 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2968 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2969 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2970 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2971 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2972 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2973 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2974 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2975 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 2976 __le32 enables; 2977 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2978 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2979 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2980 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2981 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2982 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2983 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2984 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2985 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 2986 __le16 port_id; 2987 u8 ipg; 2988 u8 lpbk; 2989 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2990 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2991 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2992 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2993 u8 vlan_pri2cos_map_pri; 2994 u8 reserved1; 2995 u8 tunnel_pri2cos_map_pri; 2996 u8 dscp2pri_map_pri; 2997 __le16 rx_ts_capture_ptp_msg_type; 2998 __le16 tx_ts_capture_ptp_msg_type; 2999 u8 cos_field_cfg; 3000 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3001 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3002 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3003 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3004 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3005 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3006 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3007 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3008 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3009 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3010 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3011 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3012 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3013 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3014 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3015 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3016 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3017 u8 unused_0[3]; 3018 __s32 ptp_freq_adj_ppb; 3019 u8 unused_1[4]; 3020 }; 3021 3022 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3023 struct hwrm_port_mac_cfg_output { 3024 __le16 error_code; 3025 __le16 req_type; 3026 __le16 seq_id; 3027 __le16 resp_len; 3028 __le16 mru; 3029 __le16 mtu; 3030 u8 ipg; 3031 u8 lpbk; 3032 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3033 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3034 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3035 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3036 u8 unused_0; 3037 u8 valid; 3038 }; 3039 3040 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3041 struct hwrm_port_mac_ptp_qcfg_input { 3042 __le16 req_type; 3043 __le16 cmpl_ring; 3044 __le16 seq_id; 3045 __le16 target_id; 3046 __le64 resp_addr; 3047 __le16 port_id; 3048 u8 unused_0[6]; 3049 }; 3050 3051 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 3052 struct hwrm_port_mac_ptp_qcfg_output { 3053 __le16 error_code; 3054 __le16 req_type; 3055 __le16 seq_id; 3056 __le16 resp_len; 3057 u8 flags; 3058 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3059 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3060 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3061 u8 unused_0[3]; 3062 __le32 rx_ts_reg_off_lower; 3063 __le32 rx_ts_reg_off_upper; 3064 __le32 rx_ts_reg_off_seq_id; 3065 __le32 rx_ts_reg_off_src_id_0; 3066 __le32 rx_ts_reg_off_src_id_1; 3067 __le32 rx_ts_reg_off_src_id_2; 3068 __le32 rx_ts_reg_off_domain_id; 3069 __le32 rx_ts_reg_off_fifo; 3070 __le32 rx_ts_reg_off_fifo_adv; 3071 __le32 rx_ts_reg_off_granularity; 3072 __le32 tx_ts_reg_off_lower; 3073 __le32 tx_ts_reg_off_upper; 3074 __le32 tx_ts_reg_off_seq_id; 3075 __le32 tx_ts_reg_off_fifo; 3076 __le32 tx_ts_reg_off_granularity; 3077 u8 unused_1[7]; 3078 u8 valid; 3079 }; 3080 3081 /* tx_port_stats (size:3264b/408B) */ 3082 struct tx_port_stats { 3083 __le64 tx_64b_frames; 3084 __le64 tx_65b_127b_frames; 3085 __le64 tx_128b_255b_frames; 3086 __le64 tx_256b_511b_frames; 3087 __le64 tx_512b_1023b_frames; 3088 __le64 tx_1024b_1518b_frames; 3089 __le64 tx_good_vlan_frames; 3090 __le64 tx_1519b_2047b_frames; 3091 __le64 tx_2048b_4095b_frames; 3092 __le64 tx_4096b_9216b_frames; 3093 __le64 tx_9217b_16383b_frames; 3094 __le64 tx_good_frames; 3095 __le64 tx_total_frames; 3096 __le64 tx_ucast_frames; 3097 __le64 tx_mcast_frames; 3098 __le64 tx_bcast_frames; 3099 __le64 tx_pause_frames; 3100 __le64 tx_pfc_frames; 3101 __le64 tx_jabber_frames; 3102 __le64 tx_fcs_err_frames; 3103 __le64 tx_control_frames; 3104 __le64 tx_oversz_frames; 3105 __le64 tx_single_dfrl_frames; 3106 __le64 tx_multi_dfrl_frames; 3107 __le64 tx_single_coll_frames; 3108 __le64 tx_multi_coll_frames; 3109 __le64 tx_late_coll_frames; 3110 __le64 tx_excessive_coll_frames; 3111 __le64 tx_frag_frames; 3112 __le64 tx_err; 3113 __le64 tx_tagged_frames; 3114 __le64 tx_dbl_tagged_frames; 3115 __le64 tx_runt_frames; 3116 __le64 tx_fifo_underruns; 3117 __le64 tx_pfc_ena_frames_pri0; 3118 __le64 tx_pfc_ena_frames_pri1; 3119 __le64 tx_pfc_ena_frames_pri2; 3120 __le64 tx_pfc_ena_frames_pri3; 3121 __le64 tx_pfc_ena_frames_pri4; 3122 __le64 tx_pfc_ena_frames_pri5; 3123 __le64 tx_pfc_ena_frames_pri6; 3124 __le64 tx_pfc_ena_frames_pri7; 3125 __le64 tx_eee_lpi_events; 3126 __le64 tx_eee_lpi_duration; 3127 __le64 tx_llfc_logical_msgs; 3128 __le64 tx_hcfc_msgs; 3129 __le64 tx_total_collisions; 3130 __le64 tx_bytes; 3131 __le64 tx_xthol_frames; 3132 __le64 tx_stat_discard; 3133 __le64 tx_stat_error; 3134 }; 3135 3136 /* rx_port_stats (size:4224b/528B) */ 3137 struct rx_port_stats { 3138 __le64 rx_64b_frames; 3139 __le64 rx_65b_127b_frames; 3140 __le64 rx_128b_255b_frames; 3141 __le64 rx_256b_511b_frames; 3142 __le64 rx_512b_1023b_frames; 3143 __le64 rx_1024b_1518b_frames; 3144 __le64 rx_good_vlan_frames; 3145 __le64 rx_1519b_2047b_frames; 3146 __le64 rx_2048b_4095b_frames; 3147 __le64 rx_4096b_9216b_frames; 3148 __le64 rx_9217b_16383b_frames; 3149 __le64 rx_total_frames; 3150 __le64 rx_ucast_frames; 3151 __le64 rx_mcast_frames; 3152 __le64 rx_bcast_frames; 3153 __le64 rx_fcs_err_frames; 3154 __le64 rx_ctrl_frames; 3155 __le64 rx_pause_frames; 3156 __le64 rx_pfc_frames; 3157 __le64 rx_unsupported_opcode_frames; 3158 __le64 rx_unsupported_da_pausepfc_frames; 3159 __le64 rx_wrong_sa_frames; 3160 __le64 rx_align_err_frames; 3161 __le64 rx_oor_len_frames; 3162 __le64 rx_code_err_frames; 3163 __le64 rx_false_carrier_frames; 3164 __le64 rx_ovrsz_frames; 3165 __le64 rx_jbr_frames; 3166 __le64 rx_mtu_err_frames; 3167 __le64 rx_match_crc_frames; 3168 __le64 rx_promiscuous_frames; 3169 __le64 rx_tagged_frames; 3170 __le64 rx_double_tagged_frames; 3171 __le64 rx_trunc_frames; 3172 __le64 rx_good_frames; 3173 __le64 rx_pfc_xon2xoff_frames_pri0; 3174 __le64 rx_pfc_xon2xoff_frames_pri1; 3175 __le64 rx_pfc_xon2xoff_frames_pri2; 3176 __le64 rx_pfc_xon2xoff_frames_pri3; 3177 __le64 rx_pfc_xon2xoff_frames_pri4; 3178 __le64 rx_pfc_xon2xoff_frames_pri5; 3179 __le64 rx_pfc_xon2xoff_frames_pri6; 3180 __le64 rx_pfc_xon2xoff_frames_pri7; 3181 __le64 rx_pfc_ena_frames_pri0; 3182 __le64 rx_pfc_ena_frames_pri1; 3183 __le64 rx_pfc_ena_frames_pri2; 3184 __le64 rx_pfc_ena_frames_pri3; 3185 __le64 rx_pfc_ena_frames_pri4; 3186 __le64 rx_pfc_ena_frames_pri5; 3187 __le64 rx_pfc_ena_frames_pri6; 3188 __le64 rx_pfc_ena_frames_pri7; 3189 __le64 rx_sch_crc_err_frames; 3190 __le64 rx_undrsz_frames; 3191 __le64 rx_frag_frames; 3192 __le64 rx_eee_lpi_events; 3193 __le64 rx_eee_lpi_duration; 3194 __le64 rx_llfc_physical_msgs; 3195 __le64 rx_llfc_logical_msgs; 3196 __le64 rx_llfc_msgs_with_crc_err; 3197 __le64 rx_hcfc_msgs; 3198 __le64 rx_hcfc_msgs_with_crc_err; 3199 __le64 rx_bytes; 3200 __le64 rx_runt_bytes; 3201 __le64 rx_runt_frames; 3202 __le64 rx_stat_discard; 3203 __le64 rx_stat_err; 3204 }; 3205 3206 /* hwrm_port_qstats_input (size:320b/40B) */ 3207 struct hwrm_port_qstats_input { 3208 __le16 req_type; 3209 __le16 cmpl_ring; 3210 __le16 seq_id; 3211 __le16 target_id; 3212 __le64 resp_addr; 3213 __le16 port_id; 3214 u8 flags; 3215 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3216 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3217 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3218 u8 unused_0[5]; 3219 __le64 tx_stat_host_addr; 3220 __le64 rx_stat_host_addr; 3221 }; 3222 3223 /* hwrm_port_qstats_output (size:128b/16B) */ 3224 struct hwrm_port_qstats_output { 3225 __le16 error_code; 3226 __le16 req_type; 3227 __le16 seq_id; 3228 __le16 resp_len; 3229 __le16 tx_stat_size; 3230 __le16 rx_stat_size; 3231 u8 unused_0[3]; 3232 u8 valid; 3233 }; 3234 3235 /* tx_port_stats_ext (size:2048b/256B) */ 3236 struct tx_port_stats_ext { 3237 __le64 tx_bytes_cos0; 3238 __le64 tx_bytes_cos1; 3239 __le64 tx_bytes_cos2; 3240 __le64 tx_bytes_cos3; 3241 __le64 tx_bytes_cos4; 3242 __le64 tx_bytes_cos5; 3243 __le64 tx_bytes_cos6; 3244 __le64 tx_bytes_cos7; 3245 __le64 tx_packets_cos0; 3246 __le64 tx_packets_cos1; 3247 __le64 tx_packets_cos2; 3248 __le64 tx_packets_cos3; 3249 __le64 tx_packets_cos4; 3250 __le64 tx_packets_cos5; 3251 __le64 tx_packets_cos6; 3252 __le64 tx_packets_cos7; 3253 __le64 pfc_pri0_tx_duration_us; 3254 __le64 pfc_pri0_tx_transitions; 3255 __le64 pfc_pri1_tx_duration_us; 3256 __le64 pfc_pri1_tx_transitions; 3257 __le64 pfc_pri2_tx_duration_us; 3258 __le64 pfc_pri2_tx_transitions; 3259 __le64 pfc_pri3_tx_duration_us; 3260 __le64 pfc_pri3_tx_transitions; 3261 __le64 pfc_pri4_tx_duration_us; 3262 __le64 pfc_pri4_tx_transitions; 3263 __le64 pfc_pri5_tx_duration_us; 3264 __le64 pfc_pri5_tx_transitions; 3265 __le64 pfc_pri6_tx_duration_us; 3266 __le64 pfc_pri6_tx_transitions; 3267 __le64 pfc_pri7_tx_duration_us; 3268 __le64 pfc_pri7_tx_transitions; 3269 }; 3270 3271 /* rx_port_stats_ext (size:3648b/456B) */ 3272 struct rx_port_stats_ext { 3273 __le64 link_down_events; 3274 __le64 continuous_pause_events; 3275 __le64 resume_pause_events; 3276 __le64 continuous_roce_pause_events; 3277 __le64 resume_roce_pause_events; 3278 __le64 rx_bytes_cos0; 3279 __le64 rx_bytes_cos1; 3280 __le64 rx_bytes_cos2; 3281 __le64 rx_bytes_cos3; 3282 __le64 rx_bytes_cos4; 3283 __le64 rx_bytes_cos5; 3284 __le64 rx_bytes_cos6; 3285 __le64 rx_bytes_cos7; 3286 __le64 rx_packets_cos0; 3287 __le64 rx_packets_cos1; 3288 __le64 rx_packets_cos2; 3289 __le64 rx_packets_cos3; 3290 __le64 rx_packets_cos4; 3291 __le64 rx_packets_cos5; 3292 __le64 rx_packets_cos6; 3293 __le64 rx_packets_cos7; 3294 __le64 pfc_pri0_rx_duration_us; 3295 __le64 pfc_pri0_rx_transitions; 3296 __le64 pfc_pri1_rx_duration_us; 3297 __le64 pfc_pri1_rx_transitions; 3298 __le64 pfc_pri2_rx_duration_us; 3299 __le64 pfc_pri2_rx_transitions; 3300 __le64 pfc_pri3_rx_duration_us; 3301 __le64 pfc_pri3_rx_transitions; 3302 __le64 pfc_pri4_rx_duration_us; 3303 __le64 pfc_pri4_rx_transitions; 3304 __le64 pfc_pri5_rx_duration_us; 3305 __le64 pfc_pri5_rx_transitions; 3306 __le64 pfc_pri6_rx_duration_us; 3307 __le64 pfc_pri6_rx_transitions; 3308 __le64 pfc_pri7_rx_duration_us; 3309 __le64 pfc_pri7_rx_transitions; 3310 __le64 rx_bits; 3311 __le64 rx_buffer_passed_threshold; 3312 __le64 rx_pcs_symbol_err; 3313 __le64 rx_corrected_bits; 3314 __le64 rx_discard_bytes_cos0; 3315 __le64 rx_discard_bytes_cos1; 3316 __le64 rx_discard_bytes_cos2; 3317 __le64 rx_discard_bytes_cos3; 3318 __le64 rx_discard_bytes_cos4; 3319 __le64 rx_discard_bytes_cos5; 3320 __le64 rx_discard_bytes_cos6; 3321 __le64 rx_discard_bytes_cos7; 3322 __le64 rx_discard_packets_cos0; 3323 __le64 rx_discard_packets_cos1; 3324 __le64 rx_discard_packets_cos2; 3325 __le64 rx_discard_packets_cos3; 3326 __le64 rx_discard_packets_cos4; 3327 __le64 rx_discard_packets_cos5; 3328 __le64 rx_discard_packets_cos6; 3329 __le64 rx_discard_packets_cos7; 3330 }; 3331 3332 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3333 struct hwrm_port_qstats_ext_input { 3334 __le16 req_type; 3335 __le16 cmpl_ring; 3336 __le16 seq_id; 3337 __le16 target_id; 3338 __le64 resp_addr; 3339 __le16 port_id; 3340 __le16 tx_stat_size; 3341 __le16 rx_stat_size; 3342 u8 flags; 3343 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3344 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3345 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3346 u8 unused_0; 3347 __le64 tx_stat_host_addr; 3348 __le64 rx_stat_host_addr; 3349 }; 3350 3351 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3352 struct hwrm_port_qstats_ext_output { 3353 __le16 error_code; 3354 __le16 req_type; 3355 __le16 seq_id; 3356 __le16 resp_len; 3357 __le16 tx_stat_size; 3358 __le16 rx_stat_size; 3359 __le16 total_active_cos_queues; 3360 u8 flags; 3361 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3362 u8 valid; 3363 }; 3364 3365 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3366 struct hwrm_port_lpbk_qstats_input { 3367 __le16 req_type; 3368 __le16 cmpl_ring; 3369 __le16 seq_id; 3370 __le16 target_id; 3371 __le64 resp_addr; 3372 }; 3373 3374 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3375 struct hwrm_port_lpbk_qstats_output { 3376 __le16 error_code; 3377 __le16 req_type; 3378 __le16 seq_id; 3379 __le16 resp_len; 3380 __le64 lpbk_ucast_frames; 3381 __le64 lpbk_mcast_frames; 3382 __le64 lpbk_bcast_frames; 3383 __le64 lpbk_ucast_bytes; 3384 __le64 lpbk_mcast_bytes; 3385 __le64 lpbk_bcast_bytes; 3386 __le64 tx_stat_discard; 3387 __le64 tx_stat_error; 3388 __le64 rx_stat_discard; 3389 __le64 rx_stat_error; 3390 u8 unused_0[7]; 3391 u8 valid; 3392 }; 3393 3394 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 3395 struct hwrm_port_ecn_qstats_input { 3396 __le16 req_type; 3397 __le16 cmpl_ring; 3398 __le16 seq_id; 3399 __le16 target_id; 3400 __le64 resp_addr; 3401 __le16 port_id; 3402 __le16 ecn_stat_buf_size; 3403 u8 flags; 3404 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3405 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3406 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 3407 u8 unused_0[3]; 3408 __le64 ecn_stat_host_addr; 3409 }; 3410 3411 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 3412 struct hwrm_port_ecn_qstats_output { 3413 __le16 error_code; 3414 __le16 req_type; 3415 __le16 seq_id; 3416 __le16 resp_len; 3417 __le16 ecn_stat_buf_size; 3418 u8 mark_en; 3419 u8 unused_0[4]; 3420 u8 valid; 3421 }; 3422 3423 /* port_stats_ecn (size:512b/64B) */ 3424 struct port_stats_ecn { 3425 __le64 mark_cnt_cos0; 3426 __le64 mark_cnt_cos1; 3427 __le64 mark_cnt_cos2; 3428 __le64 mark_cnt_cos3; 3429 __le64 mark_cnt_cos4; 3430 __le64 mark_cnt_cos5; 3431 __le64 mark_cnt_cos6; 3432 __le64 mark_cnt_cos7; 3433 }; 3434 3435 /* hwrm_port_clr_stats_input (size:192b/24B) */ 3436 struct hwrm_port_clr_stats_input { 3437 __le16 req_type; 3438 __le16 cmpl_ring; 3439 __le16 seq_id; 3440 __le16 target_id; 3441 __le64 resp_addr; 3442 __le16 port_id; 3443 u8 flags; 3444 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3445 u8 unused_0[5]; 3446 }; 3447 3448 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3449 struct hwrm_port_clr_stats_output { 3450 __le16 error_code; 3451 __le16 req_type; 3452 __le16 seq_id; 3453 __le16 resp_len; 3454 u8 unused_0[7]; 3455 u8 valid; 3456 }; 3457 3458 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3459 struct hwrm_port_lpbk_clr_stats_input { 3460 __le16 req_type; 3461 __le16 cmpl_ring; 3462 __le16 seq_id; 3463 __le16 target_id; 3464 __le64 resp_addr; 3465 }; 3466 3467 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3468 struct hwrm_port_lpbk_clr_stats_output { 3469 __le16 error_code; 3470 __le16 req_type; 3471 __le16 seq_id; 3472 __le16 resp_len; 3473 u8 unused_0[7]; 3474 u8 valid; 3475 }; 3476 3477 /* hwrm_port_ts_query_input (size:192b/24B) */ 3478 struct hwrm_port_ts_query_input { 3479 __le16 req_type; 3480 __le16 cmpl_ring; 3481 __le16 seq_id; 3482 __le16 target_id; 3483 __le64 resp_addr; 3484 __le32 flags; 3485 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3486 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3487 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3488 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3489 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3490 __le16 port_id; 3491 u8 unused_0[2]; 3492 }; 3493 3494 /* hwrm_port_ts_query_output (size:192b/24B) */ 3495 struct hwrm_port_ts_query_output { 3496 __le16 error_code; 3497 __le16 req_type; 3498 __le16 seq_id; 3499 __le16 resp_len; 3500 __le64 ptp_msg_ts; 3501 __le16 ptp_msg_seqid; 3502 u8 unused_0[5]; 3503 u8 valid; 3504 }; 3505 3506 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3507 struct hwrm_port_phy_qcaps_input { 3508 __le16 req_type; 3509 __le16 cmpl_ring; 3510 __le16 seq_id; 3511 __le16 target_id; 3512 __le64 resp_addr; 3513 __le16 port_id; 3514 u8 unused_0[6]; 3515 }; 3516 3517 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 3518 struct hwrm_port_phy_qcaps_output { 3519 __le16 error_code; 3520 __le16 req_type; 3521 __le16 seq_id; 3522 __le16 resp_len; 3523 u8 flags; 3524 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3525 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3526 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 3527 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3528 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 3529 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 3530 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xc0UL 3531 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 6 3532 u8 port_cnt; 3533 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3534 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3535 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3536 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3537 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3538 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3539 __le16 supported_speeds_force_mode; 3540 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3541 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3542 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3543 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3544 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3545 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3546 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3547 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3548 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3549 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3550 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3551 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3552 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3553 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3554 __le16 supported_speeds_auto_mode; 3555 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3556 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3557 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3558 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3559 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3560 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3561 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3562 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3563 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3564 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3565 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3566 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3567 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3568 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3569 __le16 supported_speeds_eee_mode; 3570 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3571 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3572 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3573 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3574 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3575 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3576 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3577 __le32 tx_lpi_timer_low; 3578 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3579 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3580 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3581 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3582 __le32 valid_tx_lpi_timer_high; 3583 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3584 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3585 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 3586 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 3587 __le16 supported_pam4_speeds_auto_mode; 3588 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 3589 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 3590 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 3591 __le16 supported_pam4_speeds_force_mode; 3592 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 3593 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 3594 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 3595 u8 unused_0[3]; 3596 u8 valid; 3597 }; 3598 3599 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3600 struct hwrm_port_phy_i2c_read_input { 3601 __le16 req_type; 3602 __le16 cmpl_ring; 3603 __le16 seq_id; 3604 __le16 target_id; 3605 __le64 resp_addr; 3606 __le32 flags; 3607 __le32 enables; 3608 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3609 __le16 port_id; 3610 u8 i2c_slave_addr; 3611 u8 unused_0; 3612 __le16 page_number; 3613 __le16 page_offset; 3614 u8 data_length; 3615 u8 unused_1[7]; 3616 }; 3617 3618 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3619 struct hwrm_port_phy_i2c_read_output { 3620 __le16 error_code; 3621 __le16 req_type; 3622 __le16 seq_id; 3623 __le16 resp_len; 3624 __le32 data[16]; 3625 u8 unused_0[7]; 3626 u8 valid; 3627 }; 3628 3629 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3630 struct hwrm_port_phy_mdio_write_input { 3631 __le16 req_type; 3632 __le16 cmpl_ring; 3633 __le16 seq_id; 3634 __le16 target_id; 3635 __le64 resp_addr; 3636 __le32 unused_0[2]; 3637 __le16 port_id; 3638 u8 phy_addr; 3639 u8 dev_addr; 3640 __le16 reg_addr; 3641 __le16 reg_data; 3642 u8 cl45_mdio; 3643 u8 unused_1[7]; 3644 }; 3645 3646 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3647 struct hwrm_port_phy_mdio_write_output { 3648 __le16 error_code; 3649 __le16 req_type; 3650 __le16 seq_id; 3651 __le16 resp_len; 3652 u8 unused_0[7]; 3653 u8 valid; 3654 }; 3655 3656 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3657 struct hwrm_port_phy_mdio_read_input { 3658 __le16 req_type; 3659 __le16 cmpl_ring; 3660 __le16 seq_id; 3661 __le16 target_id; 3662 __le64 resp_addr; 3663 __le32 unused_0[2]; 3664 __le16 port_id; 3665 u8 phy_addr; 3666 u8 dev_addr; 3667 __le16 reg_addr; 3668 u8 cl45_mdio; 3669 u8 unused_1; 3670 }; 3671 3672 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3673 struct hwrm_port_phy_mdio_read_output { 3674 __le16 error_code; 3675 __le16 req_type; 3676 __le16 seq_id; 3677 __le16 resp_len; 3678 __le16 reg_data; 3679 u8 unused_0[5]; 3680 u8 valid; 3681 }; 3682 3683 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3684 struct hwrm_port_led_cfg_input { 3685 __le16 req_type; 3686 __le16 cmpl_ring; 3687 __le16 seq_id; 3688 __le16 target_id; 3689 __le64 resp_addr; 3690 __le32 enables; 3691 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3692 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3693 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3694 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3695 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3696 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3697 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3698 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3699 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3700 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3701 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3702 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3703 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3704 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3705 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3706 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3707 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3708 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3709 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3710 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3711 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3712 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3713 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3714 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3715 __le16 port_id; 3716 u8 num_leds; 3717 u8 rsvd; 3718 u8 led0_id; 3719 u8 led0_state; 3720 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3721 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3722 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3723 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3724 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3725 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3726 u8 led0_color; 3727 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3728 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3729 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3730 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3731 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3732 u8 unused_0; 3733 __le16 led0_blink_on; 3734 __le16 led0_blink_off; 3735 u8 led0_group_id; 3736 u8 rsvd0; 3737 u8 led1_id; 3738 u8 led1_state; 3739 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3740 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3741 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3742 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3743 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3744 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3745 u8 led1_color; 3746 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3747 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3748 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3749 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3750 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3751 u8 unused_1; 3752 __le16 led1_blink_on; 3753 __le16 led1_blink_off; 3754 u8 led1_group_id; 3755 u8 rsvd1; 3756 u8 led2_id; 3757 u8 led2_state; 3758 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3759 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3760 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3761 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3762 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3763 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3764 u8 led2_color; 3765 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3766 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3767 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3768 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3769 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3770 u8 unused_2; 3771 __le16 led2_blink_on; 3772 __le16 led2_blink_off; 3773 u8 led2_group_id; 3774 u8 rsvd2; 3775 u8 led3_id; 3776 u8 led3_state; 3777 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3778 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3779 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3780 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3781 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3782 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3783 u8 led3_color; 3784 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3785 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3786 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3787 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3788 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3789 u8 unused_3; 3790 __le16 led3_blink_on; 3791 __le16 led3_blink_off; 3792 u8 led3_group_id; 3793 u8 rsvd3; 3794 }; 3795 3796 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3797 struct hwrm_port_led_cfg_output { 3798 __le16 error_code; 3799 __le16 req_type; 3800 __le16 seq_id; 3801 __le16 resp_len; 3802 u8 unused_0[7]; 3803 u8 valid; 3804 }; 3805 3806 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3807 struct hwrm_port_led_qcfg_input { 3808 __le16 req_type; 3809 __le16 cmpl_ring; 3810 __le16 seq_id; 3811 __le16 target_id; 3812 __le64 resp_addr; 3813 __le16 port_id; 3814 u8 unused_0[6]; 3815 }; 3816 3817 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3818 struct hwrm_port_led_qcfg_output { 3819 __le16 error_code; 3820 __le16 req_type; 3821 __le16 seq_id; 3822 __le16 resp_len; 3823 u8 num_leds; 3824 u8 led0_id; 3825 u8 led0_type; 3826 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3827 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3828 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3829 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3830 u8 led0_state; 3831 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3832 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3833 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3834 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3835 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3836 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3837 u8 led0_color; 3838 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3839 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3840 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3841 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3842 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3843 u8 unused_0; 3844 __le16 led0_blink_on; 3845 __le16 led0_blink_off; 3846 u8 led0_group_id; 3847 u8 led1_id; 3848 u8 led1_type; 3849 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3850 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3851 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3852 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3853 u8 led1_state; 3854 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3855 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3856 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3857 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3858 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3859 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3860 u8 led1_color; 3861 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3862 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3863 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3864 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3865 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3866 u8 unused_1; 3867 __le16 led1_blink_on; 3868 __le16 led1_blink_off; 3869 u8 led1_group_id; 3870 u8 led2_id; 3871 u8 led2_type; 3872 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3873 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3874 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3875 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3876 u8 led2_state; 3877 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3878 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3879 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3880 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3881 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3882 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3883 u8 led2_color; 3884 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3885 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3886 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3887 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3888 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3889 u8 unused_2; 3890 __le16 led2_blink_on; 3891 __le16 led2_blink_off; 3892 u8 led2_group_id; 3893 u8 led3_id; 3894 u8 led3_type; 3895 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3896 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3897 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3898 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3899 u8 led3_state; 3900 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3901 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3902 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3903 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3904 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3905 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3906 u8 led3_color; 3907 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3908 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3909 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3910 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3911 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3912 u8 unused_3; 3913 __le16 led3_blink_on; 3914 __le16 led3_blink_off; 3915 u8 led3_group_id; 3916 u8 unused_4[6]; 3917 u8 valid; 3918 }; 3919 3920 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3921 struct hwrm_port_led_qcaps_input { 3922 __le16 req_type; 3923 __le16 cmpl_ring; 3924 __le16 seq_id; 3925 __le16 target_id; 3926 __le64 resp_addr; 3927 __le16 port_id; 3928 u8 unused_0[6]; 3929 }; 3930 3931 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3932 struct hwrm_port_led_qcaps_output { 3933 __le16 error_code; 3934 __le16 req_type; 3935 __le16 seq_id; 3936 __le16 resp_len; 3937 u8 num_leds; 3938 u8 unused[3]; 3939 u8 led0_id; 3940 u8 led0_type; 3941 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3942 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3943 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3944 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3945 u8 led0_group_id; 3946 u8 unused_0; 3947 __le16 led0_state_caps; 3948 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3949 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3950 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3951 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3952 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3953 __le16 led0_color_caps; 3954 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3955 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3956 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3957 u8 led1_id; 3958 u8 led1_type; 3959 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3960 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3961 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3962 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3963 u8 led1_group_id; 3964 u8 unused_1; 3965 __le16 led1_state_caps; 3966 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3967 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3968 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3969 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3970 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3971 __le16 led1_color_caps; 3972 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3973 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3974 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3975 u8 led2_id; 3976 u8 led2_type; 3977 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3978 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3979 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3980 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3981 u8 led2_group_id; 3982 u8 unused_2; 3983 __le16 led2_state_caps; 3984 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3985 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3986 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3987 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3988 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3989 __le16 led2_color_caps; 3990 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3991 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3992 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3993 u8 led3_id; 3994 u8 led3_type; 3995 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3996 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3997 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3998 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3999 u8 led3_group_id; 4000 u8 unused_3; 4001 __le16 led3_state_caps; 4002 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4003 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4004 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4005 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4006 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4007 __le16 led3_color_caps; 4008 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4009 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4010 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4011 u8 unused_4[3]; 4012 u8 valid; 4013 }; 4014 4015 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4016 struct hwrm_queue_qportcfg_input { 4017 __le16 req_type; 4018 __le16 cmpl_ring; 4019 __le16 seq_id; 4020 __le16 target_id; 4021 __le64 resp_addr; 4022 __le32 flags; 4023 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4024 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4025 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4026 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4027 __le16 port_id; 4028 u8 drv_qmap_cap; 4029 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4030 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4031 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4032 u8 unused_0; 4033 }; 4034 4035 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4036 struct hwrm_queue_qportcfg_output { 4037 __le16 error_code; 4038 __le16 req_type; 4039 __le16 seq_id; 4040 __le16 resp_len; 4041 u8 max_configurable_queues; 4042 u8 max_configurable_lossless_queues; 4043 u8 queue_cfg_allowed; 4044 u8 queue_cfg_info; 4045 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4046 u8 queue_pfcenable_cfg_allowed; 4047 u8 queue_pri2cos_cfg_allowed; 4048 u8 queue_cos2bw_cfg_allowed; 4049 u8 queue_id0; 4050 u8 queue_id0_service_profile; 4051 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4052 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4053 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4054 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4055 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4056 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4057 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4058 u8 queue_id1; 4059 u8 queue_id1_service_profile; 4060 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4061 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4062 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4063 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4064 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4065 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4066 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4067 u8 queue_id2; 4068 u8 queue_id2_service_profile; 4069 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4070 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4071 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4072 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4073 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4074 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4075 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4076 u8 queue_id3; 4077 u8 queue_id3_service_profile; 4078 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4079 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4080 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4081 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4082 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4083 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4084 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4085 u8 queue_id4; 4086 u8 queue_id4_service_profile; 4087 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4088 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4089 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4090 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4091 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4092 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4093 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4094 u8 queue_id5; 4095 u8 queue_id5_service_profile; 4096 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4097 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4098 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4099 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4100 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4101 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4102 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4103 u8 queue_id6; 4104 u8 queue_id6_service_profile; 4105 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4106 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4107 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4108 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4109 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4110 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4111 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4112 u8 queue_id7; 4113 u8 queue_id7_service_profile; 4114 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4115 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4116 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4117 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4118 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4119 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4120 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4121 u8 unused_0; 4122 char qid0_name[16]; 4123 char qid1_name[16]; 4124 char qid2_name[16]; 4125 char qid3_name[16]; 4126 char qid4_name[16]; 4127 char qid5_name[16]; 4128 char qid6_name[16]; 4129 char qid7_name[16]; 4130 u8 unused_1[7]; 4131 u8 valid; 4132 }; 4133 4134 /* hwrm_queue_qcfg_input (size:192b/24B) */ 4135 struct hwrm_queue_qcfg_input { 4136 __le16 req_type; 4137 __le16 cmpl_ring; 4138 __le16 seq_id; 4139 __le16 target_id; 4140 __le64 resp_addr; 4141 __le32 flags; 4142 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4143 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4144 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4145 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4146 __le32 queue_id; 4147 }; 4148 4149 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4150 struct hwrm_queue_qcfg_output { 4151 __le16 error_code; 4152 __le16 req_type; 4153 __le16 seq_id; 4154 __le16 resp_len; 4155 __le32 queue_len; 4156 u8 service_profile; 4157 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4158 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4159 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4160 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4161 u8 queue_cfg_info; 4162 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4163 u8 unused_0; 4164 u8 valid; 4165 }; 4166 4167 /* hwrm_queue_cfg_input (size:320b/40B) */ 4168 struct hwrm_queue_cfg_input { 4169 __le16 req_type; 4170 __le16 cmpl_ring; 4171 __le16 seq_id; 4172 __le16 target_id; 4173 __le64 resp_addr; 4174 __le32 flags; 4175 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4176 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4177 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4178 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4179 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4180 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4181 __le32 enables; 4182 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4183 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4184 __le32 queue_id; 4185 __le32 dflt_len; 4186 u8 service_profile; 4187 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4188 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4189 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4190 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4191 u8 unused_0[7]; 4192 }; 4193 4194 /* hwrm_queue_cfg_output (size:128b/16B) */ 4195 struct hwrm_queue_cfg_output { 4196 __le16 error_code; 4197 __le16 req_type; 4198 __le16 seq_id; 4199 __le16 resp_len; 4200 u8 unused_0[7]; 4201 u8 valid; 4202 }; 4203 4204 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 4205 struct hwrm_queue_pfcenable_qcfg_input { 4206 __le16 req_type; 4207 __le16 cmpl_ring; 4208 __le16 seq_id; 4209 __le16 target_id; 4210 __le64 resp_addr; 4211 __le16 port_id; 4212 u8 unused_0[6]; 4213 }; 4214 4215 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 4216 struct hwrm_queue_pfcenable_qcfg_output { 4217 __le16 error_code; 4218 __le16 req_type; 4219 __le16 seq_id; 4220 __le16 resp_len; 4221 __le32 flags; 4222 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 4223 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 4224 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 4225 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 4226 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 4227 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 4228 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 4229 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 4230 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4231 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4232 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4233 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4234 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4235 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4236 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4237 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4238 u8 unused_0[3]; 4239 u8 valid; 4240 }; 4241 4242 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 4243 struct hwrm_queue_pfcenable_cfg_input { 4244 __le16 req_type; 4245 __le16 cmpl_ring; 4246 __le16 seq_id; 4247 __le16 target_id; 4248 __le64 resp_addr; 4249 __le32 flags; 4250 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 4251 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 4252 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 4253 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 4254 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 4255 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 4256 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 4257 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 4258 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4259 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4260 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4261 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4262 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4263 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4264 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4265 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4266 __le16 port_id; 4267 u8 unused_0[2]; 4268 }; 4269 4270 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4271 struct hwrm_queue_pfcenable_cfg_output { 4272 __le16 error_code; 4273 __le16 req_type; 4274 __le16 seq_id; 4275 __le16 resp_len; 4276 u8 unused_0[7]; 4277 u8 valid; 4278 }; 4279 4280 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 4281 struct hwrm_queue_pri2cos_qcfg_input { 4282 __le16 req_type; 4283 __le16 cmpl_ring; 4284 __le16 seq_id; 4285 __le16 target_id; 4286 __le64 resp_addr; 4287 __le32 flags; 4288 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4289 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4290 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4291 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 4292 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 4293 u8 port_id; 4294 u8 unused_0[3]; 4295 }; 4296 4297 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 4298 struct hwrm_queue_pri2cos_qcfg_output { 4299 __le16 error_code; 4300 __le16 req_type; 4301 __le16 seq_id; 4302 __le16 resp_len; 4303 u8 pri0_cos_queue_id; 4304 u8 pri1_cos_queue_id; 4305 u8 pri2_cos_queue_id; 4306 u8 pri3_cos_queue_id; 4307 u8 pri4_cos_queue_id; 4308 u8 pri5_cos_queue_id; 4309 u8 pri6_cos_queue_id; 4310 u8 pri7_cos_queue_id; 4311 u8 queue_cfg_info; 4312 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4313 u8 unused_0[6]; 4314 u8 valid; 4315 }; 4316 4317 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4318 struct hwrm_queue_pri2cos_cfg_input { 4319 __le16 req_type; 4320 __le16 cmpl_ring; 4321 __le16 seq_id; 4322 __le16 target_id; 4323 __le64 resp_addr; 4324 __le32 flags; 4325 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4326 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4327 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4328 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4329 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4330 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4331 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4332 __le32 enables; 4333 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4334 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4335 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4336 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4337 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4338 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4339 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4340 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4341 u8 port_id; 4342 u8 pri0_cos_queue_id; 4343 u8 pri1_cos_queue_id; 4344 u8 pri2_cos_queue_id; 4345 u8 pri3_cos_queue_id; 4346 u8 pri4_cos_queue_id; 4347 u8 pri5_cos_queue_id; 4348 u8 pri6_cos_queue_id; 4349 u8 pri7_cos_queue_id; 4350 u8 unused_0[7]; 4351 }; 4352 4353 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4354 struct hwrm_queue_pri2cos_cfg_output { 4355 __le16 error_code; 4356 __le16 req_type; 4357 __le16 seq_id; 4358 __le16 resp_len; 4359 u8 unused_0[7]; 4360 u8 valid; 4361 }; 4362 4363 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 4364 struct hwrm_queue_cos2bw_qcfg_input { 4365 __le16 req_type; 4366 __le16 cmpl_ring; 4367 __le16 seq_id; 4368 __le16 target_id; 4369 __le64 resp_addr; 4370 __le16 port_id; 4371 u8 unused_0[6]; 4372 }; 4373 4374 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 4375 struct hwrm_queue_cos2bw_qcfg_output { 4376 __le16 error_code; 4377 __le16 req_type; 4378 __le16 seq_id; 4379 __le16 resp_len; 4380 u8 queue_id0; 4381 u8 unused_0; 4382 __le16 unused_1; 4383 __le32 queue_id0_min_bw; 4384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 4390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4397 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4399 __le32 queue_id0_max_bw; 4400 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4404 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 4406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4410 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4415 u8 queue_id0_tsa_assign; 4416 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4419 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4420 u8 queue_id0_pri_lvl; 4421 u8 queue_id0_bw_weight; 4422 u8 queue_id1; 4423 __le32 queue_id1_min_bw; 4424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 4430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4432 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4437 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4438 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4439 __le32 queue_id1_max_bw; 4440 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4441 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4442 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4443 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4444 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4445 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 4446 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4447 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4448 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4449 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4450 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4451 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4452 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4453 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4454 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4455 u8 queue_id1_tsa_assign; 4456 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4457 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4458 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4459 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4460 u8 queue_id1_pri_lvl; 4461 u8 queue_id1_bw_weight; 4462 u8 queue_id2; 4463 __le32 queue_id2_min_bw; 4464 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4465 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4466 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4467 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4468 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4469 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4479 __le32 queue_id2_max_bw; 4480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4495 u8 queue_id2_tsa_assign; 4496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4500 u8 queue_id2_pri_lvl; 4501 u8 queue_id2_bw_weight; 4502 u8 queue_id3; 4503 __le32 queue_id3_min_bw; 4504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4519 __le32 queue_id3_max_bw; 4520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4535 u8 queue_id3_tsa_assign; 4536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4540 u8 queue_id3_pri_lvl; 4541 u8 queue_id3_bw_weight; 4542 u8 queue_id4; 4543 __le32 queue_id4_min_bw; 4544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4547 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4548 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4549 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4550 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4559 __le32 queue_id4_max_bw; 4560 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4564 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4565 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4566 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4568 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4569 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4575 u8 queue_id4_tsa_assign; 4576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4580 u8 queue_id4_pri_lvl; 4581 u8 queue_id4_bw_weight; 4582 u8 queue_id5; 4583 __le32 queue_id5_min_bw; 4584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4589 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4599 __le32 queue_id5_max_bw; 4600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4615 u8 queue_id5_tsa_assign; 4616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4620 u8 queue_id5_pri_lvl; 4621 u8 queue_id5_bw_weight; 4622 u8 queue_id6; 4623 __le32 queue_id6_min_bw; 4624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4639 __le32 queue_id6_max_bw; 4640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4655 u8 queue_id6_tsa_assign; 4656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4660 u8 queue_id6_pri_lvl; 4661 u8 queue_id6_bw_weight; 4662 u8 queue_id7; 4663 __le32 queue_id7_min_bw; 4664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4679 __le32 queue_id7_max_bw; 4680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4695 u8 queue_id7_tsa_assign; 4696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4700 u8 queue_id7_pri_lvl; 4701 u8 queue_id7_bw_weight; 4702 u8 unused_2[4]; 4703 u8 valid; 4704 }; 4705 4706 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4707 struct hwrm_queue_cos2bw_cfg_input { 4708 __le16 req_type; 4709 __le16 cmpl_ring; 4710 __le16 seq_id; 4711 __le16 target_id; 4712 __le64 resp_addr; 4713 __le32 flags; 4714 __le32 enables; 4715 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4716 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4717 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4718 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4719 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4720 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4721 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4722 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4723 __le16 port_id; 4724 u8 queue_id0; 4725 u8 unused_0; 4726 __le32 queue_id0_min_bw; 4727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4735 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4740 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4742 __le32 queue_id0_max_bw; 4743 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4745 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4746 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4756 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4758 u8 queue_id0_tsa_assign; 4759 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4761 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4762 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4763 u8 queue_id0_pri_lvl; 4764 u8 queue_id0_bw_weight; 4765 u8 queue_id1; 4766 __le32 queue_id1_min_bw; 4767 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4769 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4774 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4775 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4776 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4777 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4778 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4780 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4781 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4782 __le32 queue_id1_max_bw; 4783 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4784 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4785 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4786 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4787 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4788 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4789 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4790 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4791 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4792 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4793 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4794 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4795 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4796 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4797 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4798 u8 queue_id1_tsa_assign; 4799 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4800 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4801 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4802 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4803 u8 queue_id1_pri_lvl; 4804 u8 queue_id1_bw_weight; 4805 u8 queue_id2; 4806 __le32 queue_id2_min_bw; 4807 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4808 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4809 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4810 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4811 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4812 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4813 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4814 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4815 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4816 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4820 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4822 __le32 queue_id2_max_bw; 4823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4836 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4838 u8 queue_id2_tsa_assign; 4839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4842 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4843 u8 queue_id2_pri_lvl; 4844 u8 queue_id2_bw_weight; 4845 u8 queue_id3; 4846 __le32 queue_id3_min_bw; 4847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4862 __le32 queue_id3_max_bw; 4863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4878 u8 queue_id3_tsa_assign; 4879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4883 u8 queue_id3_pri_lvl; 4884 u8 queue_id3_bw_weight; 4885 u8 queue_id4; 4886 __le32 queue_id4_min_bw; 4887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4892 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4893 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4894 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4902 __le32 queue_id4_max_bw; 4903 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4918 u8 queue_id4_tsa_assign; 4919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4923 u8 queue_id4_pri_lvl; 4924 u8 queue_id4_bw_weight; 4925 u8 queue_id5; 4926 __le32 queue_id5_min_bw; 4927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4942 __le32 queue_id5_max_bw; 4943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4958 u8 queue_id5_tsa_assign; 4959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4963 u8 queue_id5_pri_lvl; 4964 u8 queue_id5_bw_weight; 4965 u8 queue_id6; 4966 __le32 queue_id6_min_bw; 4967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4982 __le32 queue_id6_max_bw; 4983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4998 u8 queue_id6_tsa_assign; 4999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5003 u8 queue_id6_pri_lvl; 5004 u8 queue_id6_bw_weight; 5005 u8 queue_id7; 5006 __le32 queue_id7_min_bw; 5007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5022 __le32 queue_id7_max_bw; 5023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5038 u8 queue_id7_tsa_assign; 5039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5043 u8 queue_id7_pri_lvl; 5044 u8 queue_id7_bw_weight; 5045 u8 unused_1[5]; 5046 }; 5047 5048 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5049 struct hwrm_queue_cos2bw_cfg_output { 5050 __le16 error_code; 5051 __le16 req_type; 5052 __le16 seq_id; 5053 __le16 resp_len; 5054 u8 unused_0[7]; 5055 u8 valid; 5056 }; 5057 5058 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5059 struct hwrm_queue_dscp_qcaps_input { 5060 __le16 req_type; 5061 __le16 cmpl_ring; 5062 __le16 seq_id; 5063 __le16 target_id; 5064 __le64 resp_addr; 5065 u8 port_id; 5066 u8 unused_0[7]; 5067 }; 5068 5069 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5070 struct hwrm_queue_dscp_qcaps_output { 5071 __le16 error_code; 5072 __le16 req_type; 5073 __le16 seq_id; 5074 __le16 resp_len; 5075 u8 num_dscp_bits; 5076 u8 unused_0; 5077 __le16 max_entries; 5078 u8 unused_1[3]; 5079 u8 valid; 5080 }; 5081 5082 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5083 struct hwrm_queue_dscp2pri_qcfg_input { 5084 __le16 req_type; 5085 __le16 cmpl_ring; 5086 __le16 seq_id; 5087 __le16 target_id; 5088 __le64 resp_addr; 5089 __le64 dest_data_addr; 5090 u8 port_id; 5091 u8 unused_0; 5092 __le16 dest_data_buffer_size; 5093 u8 unused_1[4]; 5094 }; 5095 5096 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5097 struct hwrm_queue_dscp2pri_qcfg_output { 5098 __le16 error_code; 5099 __le16 req_type; 5100 __le16 seq_id; 5101 __le16 resp_len; 5102 __le16 entry_cnt; 5103 u8 default_pri; 5104 u8 unused_0[4]; 5105 u8 valid; 5106 }; 5107 5108 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5109 struct hwrm_queue_dscp2pri_cfg_input { 5110 __le16 req_type; 5111 __le16 cmpl_ring; 5112 __le16 seq_id; 5113 __le16 target_id; 5114 __le64 resp_addr; 5115 __le64 src_data_addr; 5116 __le32 flags; 5117 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5118 __le32 enables; 5119 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5120 u8 port_id; 5121 u8 default_pri; 5122 __le16 entry_cnt; 5123 u8 unused_0[4]; 5124 }; 5125 5126 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5127 struct hwrm_queue_dscp2pri_cfg_output { 5128 __le16 error_code; 5129 __le16 req_type; 5130 __le16 seq_id; 5131 __le16 resp_len; 5132 u8 unused_0[7]; 5133 u8 valid; 5134 }; 5135 5136 /* hwrm_vnic_alloc_input (size:192b/24B) */ 5137 struct hwrm_vnic_alloc_input { 5138 __le16 req_type; 5139 __le16 cmpl_ring; 5140 __le16 seq_id; 5141 __le16 target_id; 5142 __le64 resp_addr; 5143 __le32 flags; 5144 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5145 u8 unused_0[4]; 5146 }; 5147 5148 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5149 struct hwrm_vnic_alloc_output { 5150 __le16 error_code; 5151 __le16 req_type; 5152 __le16 seq_id; 5153 __le16 resp_len; 5154 __le32 vnic_id; 5155 u8 unused_0[3]; 5156 u8 valid; 5157 }; 5158 5159 /* hwrm_vnic_free_input (size:192b/24B) */ 5160 struct hwrm_vnic_free_input { 5161 __le16 req_type; 5162 __le16 cmpl_ring; 5163 __le16 seq_id; 5164 __le16 target_id; 5165 __le64 resp_addr; 5166 __le32 vnic_id; 5167 u8 unused_0[4]; 5168 }; 5169 5170 /* hwrm_vnic_free_output (size:128b/16B) */ 5171 struct hwrm_vnic_free_output { 5172 __le16 error_code; 5173 __le16 req_type; 5174 __le16 seq_id; 5175 __le16 resp_len; 5176 u8 unused_0[7]; 5177 u8 valid; 5178 }; 5179 5180 /* hwrm_vnic_cfg_input (size:384b/48B) */ 5181 struct hwrm_vnic_cfg_input { 5182 __le16 req_type; 5183 __le16 cmpl_ring; 5184 __le16 seq_id; 5185 __le16 target_id; 5186 __le64 resp_addr; 5187 __le32 flags; 5188 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5189 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5190 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 5191 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 5192 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5193 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 5194 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5195 __le32 enables; 5196 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5197 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5198 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5199 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5200 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 5201 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 5202 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 5203 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5204 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5205 __le16 vnic_id; 5206 __le16 dflt_ring_grp; 5207 __le16 rss_rule; 5208 __le16 cos_rule; 5209 __le16 lb_rule; 5210 __le16 mru; 5211 __le16 default_rx_ring_id; 5212 __le16 default_cmpl_ring_id; 5213 __le16 queue_id; 5214 u8 rx_csum_v2_mode; 5215 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 5216 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 5217 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 5218 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 5219 u8 unused0[5]; 5220 }; 5221 5222 /* hwrm_vnic_cfg_output (size:128b/16B) */ 5223 struct hwrm_vnic_cfg_output { 5224 __le16 error_code; 5225 __le16 req_type; 5226 __le16 seq_id; 5227 __le16 resp_len; 5228 u8 unused_0[7]; 5229 u8 valid; 5230 }; 5231 5232 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 5233 struct hwrm_vnic_qcaps_input { 5234 __le16 req_type; 5235 __le16 cmpl_ring; 5236 __le16 seq_id; 5237 __le16 target_id; 5238 __le64 resp_addr; 5239 __le32 enables; 5240 u8 unused_0[4]; 5241 }; 5242 5243 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 5244 struct hwrm_vnic_qcaps_output { 5245 __le16 error_code; 5246 __le16 req_type; 5247 __le16 seq_id; 5248 __le16 resp_len; 5249 __le16 mru; 5250 u8 unused_0[2]; 5251 __le32 flags; 5252 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 5253 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 5254 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 5255 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 5256 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 5257 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 5258 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 5259 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 5260 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5261 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5262 __le16 max_aggs_supported; 5263 u8 unused_1[5]; 5264 u8 valid; 5265 }; 5266 5267 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 5268 struct hwrm_vnic_tpa_cfg_input { 5269 __le16 req_type; 5270 __le16 cmpl_ring; 5271 __le16 seq_id; 5272 __le16 target_id; 5273 __le64 resp_addr; 5274 __le32 flags; 5275 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5276 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5277 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5278 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5279 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5280 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5281 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5282 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 5283 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5284 __le32 enables; 5285 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5286 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5287 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5288 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5289 __le16 vnic_id; 5290 __le16 max_agg_segs; 5291 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5292 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5293 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5294 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5295 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5296 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5297 __le16 max_aggs; 5298 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5299 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5300 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5301 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5302 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5303 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5304 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5305 u8 unused_0[2]; 5306 __le32 max_agg_timer; 5307 __le32 min_agg_len; 5308 }; 5309 5310 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5311 struct hwrm_vnic_tpa_cfg_output { 5312 __le16 error_code; 5313 __le16 req_type; 5314 __le16 seq_id; 5315 __le16 resp_len; 5316 u8 unused_0[7]; 5317 u8 valid; 5318 }; 5319 5320 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5321 struct hwrm_vnic_tpa_qcfg_input { 5322 __le16 req_type; 5323 __le16 cmpl_ring; 5324 __le16 seq_id; 5325 __le16 target_id; 5326 __le64 resp_addr; 5327 __le16 vnic_id; 5328 u8 unused_0[6]; 5329 }; 5330 5331 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5332 struct hwrm_vnic_tpa_qcfg_output { 5333 __le16 error_code; 5334 __le16 req_type; 5335 __le16 seq_id; 5336 __le16 resp_len; 5337 __le32 flags; 5338 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5339 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5340 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5341 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5342 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5343 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5344 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5345 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5346 __le16 max_agg_segs; 5347 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5348 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5349 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5350 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5351 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5352 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5353 __le16 max_aggs; 5354 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5355 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5356 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5357 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5358 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5359 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5360 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5361 __le32 max_agg_timer; 5362 __le32 min_agg_len; 5363 u8 unused_0[7]; 5364 u8 valid; 5365 }; 5366 5367 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5368 struct hwrm_vnic_rss_cfg_input { 5369 __le16 req_type; 5370 __le16 cmpl_ring; 5371 __le16 seq_id; 5372 __le16 target_id; 5373 __le64 resp_addr; 5374 __le32 hash_type; 5375 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5376 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5377 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5378 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5379 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5380 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 5381 __le16 vnic_id; 5382 u8 ring_table_pair_index; 5383 u8 hash_mode_flags; 5384 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 5385 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 5386 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 5387 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 5388 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5389 __le64 ring_grp_tbl_addr; 5390 __le64 hash_key_tbl_addr; 5391 __le16 rss_ctx_idx; 5392 u8 unused_1[6]; 5393 }; 5394 5395 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5396 struct hwrm_vnic_rss_cfg_output { 5397 __le16 error_code; 5398 __le16 req_type; 5399 __le16 seq_id; 5400 __le16 resp_len; 5401 u8 unused_0[7]; 5402 u8 valid; 5403 }; 5404 5405 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 5406 struct hwrm_vnic_rss_cfg_cmd_err { 5407 u8 code; 5408 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 5409 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 5410 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 5411 u8 unused_0[7]; 5412 }; 5413 5414 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5415 struct hwrm_vnic_plcmodes_cfg_input { 5416 __le16 req_type; 5417 __le16 cmpl_ring; 5418 __le16 seq_id; 5419 __le16 target_id; 5420 __le64 resp_addr; 5421 __le32 flags; 5422 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5423 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5424 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5425 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5426 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5427 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5428 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 5429 __le32 enables; 5430 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5431 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5432 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5433 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 5434 __le32 vnic_id; 5435 __le16 jumbo_thresh; 5436 __le16 hds_offset; 5437 __le16 hds_threshold; 5438 __le16 max_bds; 5439 u8 unused_0[4]; 5440 }; 5441 5442 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5443 struct hwrm_vnic_plcmodes_cfg_output { 5444 __le16 error_code; 5445 __le16 req_type; 5446 __le16 seq_id; 5447 __le16 resp_len; 5448 u8 unused_0[7]; 5449 u8 valid; 5450 }; 5451 5452 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5453 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5454 __le16 req_type; 5455 __le16 cmpl_ring; 5456 __le16 seq_id; 5457 __le16 target_id; 5458 __le64 resp_addr; 5459 }; 5460 5461 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5462 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5463 __le16 error_code; 5464 __le16 req_type; 5465 __le16 seq_id; 5466 __le16 resp_len; 5467 __le16 rss_cos_lb_ctx_id; 5468 u8 unused_0[5]; 5469 u8 valid; 5470 }; 5471 5472 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5473 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5474 __le16 req_type; 5475 __le16 cmpl_ring; 5476 __le16 seq_id; 5477 __le16 target_id; 5478 __le64 resp_addr; 5479 __le16 rss_cos_lb_ctx_id; 5480 u8 unused_0[6]; 5481 }; 5482 5483 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5484 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5485 __le16 error_code; 5486 __le16 req_type; 5487 __le16 seq_id; 5488 __le16 resp_len; 5489 u8 unused_0[7]; 5490 u8 valid; 5491 }; 5492 5493 /* hwrm_ring_alloc_input (size:704b/88B) */ 5494 struct hwrm_ring_alloc_input { 5495 __le16 req_type; 5496 __le16 cmpl_ring; 5497 __le16 seq_id; 5498 __le16 target_id; 5499 __le64 resp_addr; 5500 __le32 enables; 5501 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5502 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5503 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5504 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5505 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5506 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5507 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 5508 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 5509 u8 ring_type; 5510 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5511 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5512 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5513 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5514 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5515 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5516 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5517 u8 unused_0; 5518 __le16 flags; 5519 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5520 __le64 page_tbl_addr; 5521 __le32 fbo; 5522 u8 page_size; 5523 u8 page_tbl_depth; 5524 __le16 schq_id; 5525 __le32 length; 5526 __le16 logical_id; 5527 __le16 cmpl_ring_id; 5528 __le16 queue_id; 5529 __le16 rx_buf_size; 5530 __le16 rx_ring_id; 5531 __le16 nq_ring_id; 5532 __le16 ring_arb_cfg; 5533 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5534 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5535 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5536 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5537 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5538 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5539 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5540 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5541 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5542 __le16 unused_3; 5543 __le32 reserved3; 5544 __le32 stat_ctx_id; 5545 __le32 reserved4; 5546 __le32 max_bw; 5547 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5548 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5549 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5550 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5551 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5552 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5553 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5554 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5555 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5556 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5557 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5558 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5559 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5560 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5561 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5562 u8 int_mode; 5563 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5564 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5565 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5566 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5567 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5568 u8 mpc_chnls_type; 5569 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 5570 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 5571 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 5572 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 5573 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 5574 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 5575 u8 unused_4[2]; 5576 __le64 cq_handle; 5577 }; 5578 5579 /* hwrm_ring_alloc_output (size:128b/16B) */ 5580 struct hwrm_ring_alloc_output { 5581 __le16 error_code; 5582 __le16 req_type; 5583 __le16 seq_id; 5584 __le16 resp_len; 5585 __le16 ring_id; 5586 __le16 logical_ring_id; 5587 u8 unused_0[3]; 5588 u8 valid; 5589 }; 5590 5591 /* hwrm_ring_free_input (size:192b/24B) */ 5592 struct hwrm_ring_free_input { 5593 __le16 req_type; 5594 __le16 cmpl_ring; 5595 __le16 seq_id; 5596 __le16 target_id; 5597 __le64 resp_addr; 5598 u8 ring_type; 5599 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5600 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5601 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5602 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5603 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5604 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5605 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5606 u8 unused_0; 5607 __le16 ring_id; 5608 u8 unused_1[4]; 5609 }; 5610 5611 /* hwrm_ring_free_output (size:128b/16B) */ 5612 struct hwrm_ring_free_output { 5613 __le16 error_code; 5614 __le16 req_type; 5615 __le16 seq_id; 5616 __le16 resp_len; 5617 u8 unused_0[7]; 5618 u8 valid; 5619 }; 5620 5621 /* hwrm_ring_reset_input (size:192b/24B) */ 5622 struct hwrm_ring_reset_input { 5623 __le16 req_type; 5624 __le16 cmpl_ring; 5625 __le16 seq_id; 5626 __le16 target_id; 5627 __le64 resp_addr; 5628 u8 ring_type; 5629 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5630 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5631 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5632 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5633 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 5634 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 5635 u8 unused_0; 5636 __le16 ring_id; 5637 u8 unused_1[4]; 5638 }; 5639 5640 /* hwrm_ring_reset_output (size:128b/16B) */ 5641 struct hwrm_ring_reset_output { 5642 __le16 error_code; 5643 __le16 req_type; 5644 __le16 seq_id; 5645 __le16 resp_len; 5646 u8 unused_0[4]; 5647 u8 consumer_idx[3]; 5648 u8 valid; 5649 }; 5650 5651 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5652 struct hwrm_ring_aggint_qcaps_input { 5653 __le16 req_type; 5654 __le16 cmpl_ring; 5655 __le16 seq_id; 5656 __le16 target_id; 5657 __le64 resp_addr; 5658 }; 5659 5660 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5661 struct hwrm_ring_aggint_qcaps_output { 5662 __le16 error_code; 5663 __le16 req_type; 5664 __le16 seq_id; 5665 __le16 resp_len; 5666 __le32 cmpl_params; 5667 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5668 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5669 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5670 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5671 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5672 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5673 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5674 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5675 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5676 __le32 nq_params; 5677 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5678 __le16 num_cmpl_dma_aggr_min; 5679 __le16 num_cmpl_dma_aggr_max; 5680 __le16 num_cmpl_dma_aggr_during_int_min; 5681 __le16 num_cmpl_dma_aggr_during_int_max; 5682 __le16 cmpl_aggr_dma_tmr_min; 5683 __le16 cmpl_aggr_dma_tmr_max; 5684 __le16 cmpl_aggr_dma_tmr_during_int_min; 5685 __le16 cmpl_aggr_dma_tmr_during_int_max; 5686 __le16 int_lat_tmr_min_min; 5687 __le16 int_lat_tmr_min_max; 5688 __le16 int_lat_tmr_max_min; 5689 __le16 int_lat_tmr_max_max; 5690 __le16 num_cmpl_aggr_int_min; 5691 __le16 num_cmpl_aggr_int_max; 5692 __le16 timer_units; 5693 u8 unused_0[1]; 5694 u8 valid; 5695 }; 5696 5697 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5698 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5699 __le16 req_type; 5700 __le16 cmpl_ring; 5701 __le16 seq_id; 5702 __le16 target_id; 5703 __le64 resp_addr; 5704 __le16 ring_id; 5705 __le16 flags; 5706 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5707 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5708 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5709 u8 unused_0[4]; 5710 }; 5711 5712 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5713 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5714 __le16 error_code; 5715 __le16 req_type; 5716 __le16 seq_id; 5717 __le16 resp_len; 5718 __le16 flags; 5719 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5720 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5721 __le16 num_cmpl_dma_aggr; 5722 __le16 num_cmpl_dma_aggr_during_int; 5723 __le16 cmpl_aggr_dma_tmr; 5724 __le16 cmpl_aggr_dma_tmr_during_int; 5725 __le16 int_lat_tmr_min; 5726 __le16 int_lat_tmr_max; 5727 __le16 num_cmpl_aggr_int; 5728 u8 unused_0[7]; 5729 u8 valid; 5730 }; 5731 5732 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5733 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5734 __le16 req_type; 5735 __le16 cmpl_ring; 5736 __le16 seq_id; 5737 __le16 target_id; 5738 __le64 resp_addr; 5739 __le16 ring_id; 5740 __le16 flags; 5741 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5742 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5743 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5744 __le16 num_cmpl_dma_aggr; 5745 __le16 num_cmpl_dma_aggr_during_int; 5746 __le16 cmpl_aggr_dma_tmr; 5747 __le16 cmpl_aggr_dma_tmr_during_int; 5748 __le16 int_lat_tmr_min; 5749 __le16 int_lat_tmr_max; 5750 __le16 num_cmpl_aggr_int; 5751 __le16 enables; 5752 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5753 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5754 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5755 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5756 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5757 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5758 u8 unused_0[4]; 5759 }; 5760 5761 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5762 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5763 __le16 error_code; 5764 __le16 req_type; 5765 __le16 seq_id; 5766 __le16 resp_len; 5767 u8 unused_0[7]; 5768 u8 valid; 5769 }; 5770 5771 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5772 struct hwrm_ring_grp_alloc_input { 5773 __le16 req_type; 5774 __le16 cmpl_ring; 5775 __le16 seq_id; 5776 __le16 target_id; 5777 __le64 resp_addr; 5778 __le16 cr; 5779 __le16 rr; 5780 __le16 ar; 5781 __le16 sc; 5782 }; 5783 5784 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5785 struct hwrm_ring_grp_alloc_output { 5786 __le16 error_code; 5787 __le16 req_type; 5788 __le16 seq_id; 5789 __le16 resp_len; 5790 __le32 ring_group_id; 5791 u8 unused_0[3]; 5792 u8 valid; 5793 }; 5794 5795 /* hwrm_ring_grp_free_input (size:192b/24B) */ 5796 struct hwrm_ring_grp_free_input { 5797 __le16 req_type; 5798 __le16 cmpl_ring; 5799 __le16 seq_id; 5800 __le16 target_id; 5801 __le64 resp_addr; 5802 __le32 ring_group_id; 5803 u8 unused_0[4]; 5804 }; 5805 5806 /* hwrm_ring_grp_free_output (size:128b/16B) */ 5807 struct hwrm_ring_grp_free_output { 5808 __le16 error_code; 5809 __le16 req_type; 5810 __le16 seq_id; 5811 __le16 resp_len; 5812 u8 unused_0[7]; 5813 u8 valid; 5814 }; 5815 5816 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5817 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5818 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5819 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5820 5821 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5822 struct hwrm_cfa_l2_filter_alloc_input { 5823 __le16 req_type; 5824 __le16 cmpl_ring; 5825 __le16 seq_id; 5826 __le16 target_id; 5827 __le64 resp_addr; 5828 __le32 flags; 5829 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5830 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5831 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5832 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5833 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5834 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5835 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5836 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5837 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5838 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5839 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5840 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5841 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5842 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5843 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5844 __le32 enables; 5845 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5846 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5847 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5848 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5849 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5850 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5851 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5852 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5853 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5854 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5855 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5856 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5857 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5858 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5859 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5860 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5861 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5862 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 5863 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 5864 u8 l2_addr[6]; 5865 u8 num_vlans; 5866 u8 t_num_vlans; 5867 u8 l2_addr_mask[6]; 5868 __le16 l2_ovlan; 5869 __le16 l2_ovlan_mask; 5870 __le16 l2_ivlan; 5871 __le16 l2_ivlan_mask; 5872 u8 unused_1[2]; 5873 u8 t_l2_addr[6]; 5874 u8 unused_2[2]; 5875 u8 t_l2_addr_mask[6]; 5876 __le16 t_l2_ovlan; 5877 __le16 t_l2_ovlan_mask; 5878 __le16 t_l2_ivlan; 5879 __le16 t_l2_ivlan_mask; 5880 u8 src_type; 5881 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5882 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5883 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5884 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5885 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5886 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5887 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5888 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5889 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5890 u8 unused_3; 5891 __le32 src_id; 5892 u8 tunnel_type; 5893 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5894 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5895 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5896 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5897 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5898 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5899 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5900 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5901 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5902 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5903 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5904 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5905 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5906 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5907 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5908 u8 unused_4; 5909 __le16 dst_id; 5910 __le16 mirror_vnic_id; 5911 u8 pri_hint; 5912 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5913 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5914 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5915 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5916 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5917 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5918 u8 unused_5; 5919 __le32 unused_6; 5920 __le64 l2_filter_id_hint; 5921 }; 5922 5923 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5924 struct hwrm_cfa_l2_filter_alloc_output { 5925 __le16 error_code; 5926 __le16 req_type; 5927 __le16 seq_id; 5928 __le16 resp_len; 5929 __le64 l2_filter_id; 5930 __le32 flow_id; 5931 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5932 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5933 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5934 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5935 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5936 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5937 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5938 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5939 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5940 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5941 u8 unused_0[3]; 5942 u8 valid; 5943 }; 5944 5945 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5946 struct hwrm_cfa_l2_filter_free_input { 5947 __le16 req_type; 5948 __le16 cmpl_ring; 5949 __le16 seq_id; 5950 __le16 target_id; 5951 __le64 resp_addr; 5952 __le64 l2_filter_id; 5953 }; 5954 5955 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5956 struct hwrm_cfa_l2_filter_free_output { 5957 __le16 error_code; 5958 __le16 req_type; 5959 __le16 seq_id; 5960 __le16 resp_len; 5961 u8 unused_0[7]; 5962 u8 valid; 5963 }; 5964 5965 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5966 struct hwrm_cfa_l2_filter_cfg_input { 5967 __le16 req_type; 5968 __le16 cmpl_ring; 5969 __le16 seq_id; 5970 __le16 target_id; 5971 __le64 resp_addr; 5972 __le32 flags; 5973 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5974 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5975 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5976 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5977 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5978 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5979 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5980 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5981 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5982 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5983 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5984 __le32 enables; 5985 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5986 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5987 __le64 l2_filter_id; 5988 __le32 dst_id; 5989 __le32 new_mirror_vnic_id; 5990 }; 5991 5992 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5993 struct hwrm_cfa_l2_filter_cfg_output { 5994 __le16 error_code; 5995 __le16 req_type; 5996 __le16 seq_id; 5997 __le16 resp_len; 5998 u8 unused_0[7]; 5999 u8 valid; 6000 }; 6001 6002 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6003 struct hwrm_cfa_l2_set_rx_mask_input { 6004 __le16 req_type; 6005 __le16 cmpl_ring; 6006 __le16 seq_id; 6007 __le16 target_id; 6008 __le64 resp_addr; 6009 __le32 vnic_id; 6010 __le32 mask; 6011 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6012 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6013 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6014 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6015 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6016 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6017 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6018 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6019 __le64 mc_tbl_addr; 6020 __le32 num_mc_entries; 6021 u8 unused_0[4]; 6022 __le64 vlan_tag_tbl_addr; 6023 __le32 num_vlan_tags; 6024 u8 unused_1[4]; 6025 }; 6026 6027 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6028 struct hwrm_cfa_l2_set_rx_mask_output { 6029 __le16 error_code; 6030 __le16 req_type; 6031 __le16 seq_id; 6032 __le16 resp_len; 6033 u8 unused_0[7]; 6034 u8 valid; 6035 }; 6036 6037 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6038 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6039 u8 code; 6040 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6041 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6042 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6043 u8 unused_0[7]; 6044 }; 6045 6046 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6047 struct hwrm_cfa_tunnel_filter_alloc_input { 6048 __le16 req_type; 6049 __le16 cmpl_ring; 6050 __le16 seq_id; 6051 __le16 target_id; 6052 __le64 resp_addr; 6053 __le32 flags; 6054 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6055 __le32 enables; 6056 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6057 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6058 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6059 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6060 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6061 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6062 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6063 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6064 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6065 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6066 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6067 __le64 l2_filter_id; 6068 u8 l2_addr[6]; 6069 __le16 l2_ivlan; 6070 __le32 l3_addr[4]; 6071 __le32 t_l3_addr[4]; 6072 u8 l3_addr_type; 6073 u8 t_l3_addr_type; 6074 u8 tunnel_type; 6075 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6076 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6077 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6078 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6079 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6080 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6081 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6082 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6083 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6084 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6085 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6086 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6087 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6088 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6089 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6090 u8 tunnel_flags; 6091 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6092 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6093 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6094 __le32 vni; 6095 __le32 dst_vnic_id; 6096 __le32 mirror_vnic_id; 6097 }; 6098 6099 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6100 struct hwrm_cfa_tunnel_filter_alloc_output { 6101 __le16 error_code; 6102 __le16 req_type; 6103 __le16 seq_id; 6104 __le16 resp_len; 6105 __le64 tunnel_filter_id; 6106 __le32 flow_id; 6107 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6108 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6109 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6110 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6111 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6112 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6113 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6114 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6115 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6116 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6117 u8 unused_0[3]; 6118 u8 valid; 6119 }; 6120 6121 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6122 struct hwrm_cfa_tunnel_filter_free_input { 6123 __le16 req_type; 6124 __le16 cmpl_ring; 6125 __le16 seq_id; 6126 __le16 target_id; 6127 __le64 resp_addr; 6128 __le64 tunnel_filter_id; 6129 }; 6130 6131 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6132 struct hwrm_cfa_tunnel_filter_free_output { 6133 __le16 error_code; 6134 __le16 req_type; 6135 __le16 seq_id; 6136 __le16 resp_len; 6137 u8 unused_0[7]; 6138 u8 valid; 6139 }; 6140 6141 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6142 struct hwrm_vxlan_ipv4_hdr { 6143 u8 ver_hlen; 6144 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6145 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6146 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6147 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6148 u8 tos; 6149 __be16 ip_id; 6150 __be16 flags_frag_offset; 6151 u8 ttl; 6152 u8 protocol; 6153 __be32 src_ip_addr; 6154 __be32 dest_ip_addr; 6155 }; 6156 6157 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6158 struct hwrm_vxlan_ipv6_hdr { 6159 __be32 ver_tc_flow_label; 6160 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6161 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6162 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6163 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6164 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6165 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6166 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6167 __be16 payload_len; 6168 u8 next_hdr; 6169 u8 ttl; 6170 __be32 src_ip_addr[4]; 6171 __be32 dest_ip_addr[4]; 6172 }; 6173 6174 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6175 struct hwrm_cfa_encap_data_vxlan { 6176 u8 src_mac_addr[6]; 6177 __le16 unused_0; 6178 u8 dst_mac_addr[6]; 6179 u8 num_vlan_tags; 6180 u8 unused_1; 6181 __be16 ovlan_tpid; 6182 __be16 ovlan_tci; 6183 __be16 ivlan_tpid; 6184 __be16 ivlan_tci; 6185 __le32 l3[10]; 6186 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6187 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6188 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6189 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6190 __be16 src_port; 6191 __be16 dst_port; 6192 __be32 vni; 6193 u8 hdr_rsvd0[3]; 6194 u8 hdr_rsvd1; 6195 u8 hdr_flags; 6196 u8 unused[3]; 6197 }; 6198 6199 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 6200 struct hwrm_cfa_encap_record_alloc_input { 6201 __le16 req_type; 6202 __le16 cmpl_ring; 6203 __le16 seq_id; 6204 __le16 target_id; 6205 __le64 resp_addr; 6206 __le32 flags; 6207 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6208 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 6209 u8 encap_type; 6210 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 6211 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 6212 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 6213 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 6214 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 6215 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 6216 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 6217 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 6218 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 6219 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 6220 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 6221 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 6222 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 6223 u8 unused_0[3]; 6224 __le32 encap_data[20]; 6225 }; 6226 6227 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 6228 struct hwrm_cfa_encap_record_alloc_output { 6229 __le16 error_code; 6230 __le16 req_type; 6231 __le16 seq_id; 6232 __le16 resp_len; 6233 __le32 encap_record_id; 6234 u8 unused_0[3]; 6235 u8 valid; 6236 }; 6237 6238 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 6239 struct hwrm_cfa_encap_record_free_input { 6240 __le16 req_type; 6241 __le16 cmpl_ring; 6242 __le16 seq_id; 6243 __le16 target_id; 6244 __le64 resp_addr; 6245 __le32 encap_record_id; 6246 u8 unused_0[4]; 6247 }; 6248 6249 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 6250 struct hwrm_cfa_encap_record_free_output { 6251 __le16 error_code; 6252 __le16 req_type; 6253 __le16 seq_id; 6254 __le16 resp_len; 6255 u8 unused_0[7]; 6256 u8 valid; 6257 }; 6258 6259 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 6260 struct hwrm_cfa_ntuple_filter_alloc_input { 6261 __le16 req_type; 6262 __le16 cmpl_ring; 6263 __le16 seq_id; 6264 __le16 target_id; 6265 __le64 resp_addr; 6266 __le32 flags; 6267 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6268 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 6269 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 6270 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 6271 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 6272 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 6273 __le32 enables; 6274 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6275 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 6276 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 6277 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 6278 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 6279 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 6280 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 6281 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 6282 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 6283 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6284 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6285 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6286 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6287 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6288 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6289 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6290 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6291 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 6293 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6294 __le64 l2_filter_id; 6295 u8 src_macaddr[6]; 6296 __be16 ethertype; 6297 u8 ip_addr_type; 6298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6302 u8 ip_protocol; 6303 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6307 __le16 dst_id; 6308 __le16 mirror_vnic_id; 6309 u8 tunnel_type; 6310 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6315 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6316 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6317 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6322 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6325 u8 pri_hint; 6326 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6327 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6328 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6332 __be32 src_ipaddr[4]; 6333 __be32 src_ipaddr_mask[4]; 6334 __be32 dst_ipaddr[4]; 6335 __be32 dst_ipaddr_mask[4]; 6336 __be16 src_port; 6337 __be16 src_port_mask; 6338 __be16 dst_port; 6339 __be16 dst_port_mask; 6340 __le64 ntuple_filter_id_hint; 6341 }; 6342 6343 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6344 struct hwrm_cfa_ntuple_filter_alloc_output { 6345 __le16 error_code; 6346 __le16 req_type; 6347 __le16 seq_id; 6348 __le16 resp_len; 6349 __le64 ntuple_filter_id; 6350 __le32 flow_id; 6351 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6352 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6353 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6354 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6355 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6356 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6357 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6358 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6359 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6360 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6361 u8 unused_0[3]; 6362 u8 valid; 6363 }; 6364 6365 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 6366 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 6367 u8 code; 6368 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6369 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6370 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 6371 u8 unused_0[7]; 6372 }; 6373 6374 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6375 struct hwrm_cfa_ntuple_filter_free_input { 6376 __le16 req_type; 6377 __le16 cmpl_ring; 6378 __le16 seq_id; 6379 __le16 target_id; 6380 __le64 resp_addr; 6381 __le64 ntuple_filter_id; 6382 }; 6383 6384 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6385 struct hwrm_cfa_ntuple_filter_free_output { 6386 __le16 error_code; 6387 __le16 req_type; 6388 __le16 seq_id; 6389 __le16 resp_len; 6390 u8 unused_0[7]; 6391 u8 valid; 6392 }; 6393 6394 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6395 struct hwrm_cfa_ntuple_filter_cfg_input { 6396 __le16 req_type; 6397 __le16 cmpl_ring; 6398 __le16 seq_id; 6399 __le16 target_id; 6400 __le64 resp_addr; 6401 __le32 enables; 6402 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6403 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6404 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 6405 __le32 flags; 6406 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 6407 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6408 __le64 ntuple_filter_id; 6409 __le32 new_dst_id; 6410 __le32 new_mirror_vnic_id; 6411 __le16 new_meter_instance_id; 6412 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6413 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6414 u8 unused_1[6]; 6415 }; 6416 6417 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6418 struct hwrm_cfa_ntuple_filter_cfg_output { 6419 __le16 error_code; 6420 __le16 req_type; 6421 __le16 seq_id; 6422 __le16 resp_len; 6423 u8 unused_0[7]; 6424 u8 valid; 6425 }; 6426 6427 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 6428 struct hwrm_cfa_decap_filter_alloc_input { 6429 __le16 req_type; 6430 __le16 cmpl_ring; 6431 __le16 seq_id; 6432 __le16 target_id; 6433 __le64 resp_addr; 6434 __le32 flags; 6435 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 6436 __le32 enables; 6437 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 6438 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 6439 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 6440 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 6441 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 6442 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 6443 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 6444 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 6445 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 6446 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 6447 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 6448 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 6449 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 6450 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 6451 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 6452 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6453 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6454 __be32 tunnel_id; 6455 u8 tunnel_type; 6456 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6457 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6458 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6459 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6460 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6461 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6462 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6463 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6464 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6465 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6466 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6467 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6468 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6469 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6470 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6471 u8 unused_0; 6472 __le16 unused_1; 6473 u8 src_macaddr[6]; 6474 u8 unused_2[2]; 6475 u8 dst_macaddr[6]; 6476 __be16 ovlan_vid; 6477 __be16 ivlan_vid; 6478 __be16 t_ovlan_vid; 6479 __be16 t_ivlan_vid; 6480 __be16 ethertype; 6481 u8 ip_addr_type; 6482 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6483 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6484 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6485 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6486 u8 ip_protocol; 6487 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6488 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6489 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6490 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6491 __le16 unused_3; 6492 __le32 unused_4; 6493 __be32 src_ipaddr[4]; 6494 __be32 dst_ipaddr[4]; 6495 __be16 src_port; 6496 __be16 dst_port; 6497 __le16 dst_id; 6498 __le16 l2_ctxt_ref_id; 6499 }; 6500 6501 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6502 struct hwrm_cfa_decap_filter_alloc_output { 6503 __le16 error_code; 6504 __le16 req_type; 6505 __le16 seq_id; 6506 __le16 resp_len; 6507 __le32 decap_filter_id; 6508 u8 unused_0[3]; 6509 u8 valid; 6510 }; 6511 6512 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6513 struct hwrm_cfa_decap_filter_free_input { 6514 __le16 req_type; 6515 __le16 cmpl_ring; 6516 __le16 seq_id; 6517 __le16 target_id; 6518 __le64 resp_addr; 6519 __le32 decap_filter_id; 6520 u8 unused_0[4]; 6521 }; 6522 6523 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6524 struct hwrm_cfa_decap_filter_free_output { 6525 __le16 error_code; 6526 __le16 req_type; 6527 __le16 seq_id; 6528 __le16 resp_len; 6529 u8 unused_0[7]; 6530 u8 valid; 6531 }; 6532 6533 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6534 struct hwrm_cfa_flow_alloc_input { 6535 __le16 req_type; 6536 __le16 cmpl_ring; 6537 __le16 seq_id; 6538 __le16 target_id; 6539 __le64 resp_addr; 6540 __le16 flags; 6541 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6542 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6543 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6544 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6545 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6546 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6547 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6548 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6549 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6550 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6551 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6552 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6553 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6554 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6555 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6556 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6557 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6558 __le16 src_fid; 6559 __le32 tunnel_handle; 6560 __le16 action_flags; 6561 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6562 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6563 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6564 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6565 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6566 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6567 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6568 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6569 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6570 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6571 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6572 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6573 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6574 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6575 __le16 dst_fid; 6576 __be16 l2_rewrite_vlan_tpid; 6577 __be16 l2_rewrite_vlan_tci; 6578 __le16 act_meter_id; 6579 __le16 ref_flow_handle; 6580 __be16 ethertype; 6581 __be16 outer_vlan_tci; 6582 __be16 dmac[3]; 6583 __be16 inner_vlan_tci; 6584 __be16 smac[3]; 6585 u8 ip_dst_mask_len; 6586 u8 ip_src_mask_len; 6587 __be32 ip_dst[4]; 6588 __be32 ip_src[4]; 6589 __be16 l4_src_port; 6590 __be16 l4_src_port_mask; 6591 __be16 l4_dst_port; 6592 __be16 l4_dst_port_mask; 6593 __be32 nat_ip_address[4]; 6594 __be16 l2_rewrite_dmac[3]; 6595 __be16 nat_port; 6596 __be16 l2_rewrite_smac[3]; 6597 u8 ip_proto; 6598 u8 tunnel_type; 6599 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6600 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6601 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6602 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6603 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6604 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6605 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6606 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6607 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6608 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6609 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6610 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6611 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6612 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6613 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6614 }; 6615 6616 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6617 struct hwrm_cfa_flow_alloc_output { 6618 __le16 error_code; 6619 __le16 req_type; 6620 __le16 seq_id; 6621 __le16 resp_len; 6622 __le16 flow_handle; 6623 u8 unused_0[2]; 6624 __le32 flow_id; 6625 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6626 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6627 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6628 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6629 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6630 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6631 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6632 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6633 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6634 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6635 __le64 ext_flow_handle; 6636 __le32 flow_counter_id; 6637 u8 unused_1[3]; 6638 u8 valid; 6639 }; 6640 6641 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6642 struct hwrm_cfa_flow_alloc_cmd_err { 6643 u8 code; 6644 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6645 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6646 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6647 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6648 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6649 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6650 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6651 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6652 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6653 u8 unused_0[7]; 6654 }; 6655 6656 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6657 struct hwrm_cfa_flow_free_input { 6658 __le16 req_type; 6659 __le16 cmpl_ring; 6660 __le16 seq_id; 6661 __le16 target_id; 6662 __le64 resp_addr; 6663 __le16 flow_handle; 6664 __le16 unused_0; 6665 __le32 flow_counter_id; 6666 __le64 ext_flow_handle; 6667 }; 6668 6669 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6670 struct hwrm_cfa_flow_free_output { 6671 __le16 error_code; 6672 __le16 req_type; 6673 __le16 seq_id; 6674 __le16 resp_len; 6675 __le64 packet; 6676 __le64 byte; 6677 u8 unused_0[7]; 6678 u8 valid; 6679 }; 6680 6681 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6682 struct hwrm_cfa_flow_info_input { 6683 __le16 req_type; 6684 __le16 cmpl_ring; 6685 __le16 seq_id; 6686 __le16 target_id; 6687 __le64 resp_addr; 6688 __le16 flow_handle; 6689 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6690 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6691 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6692 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6693 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6694 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6695 u8 unused_0[6]; 6696 __le64 ext_flow_handle; 6697 }; 6698 6699 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6700 struct hwrm_cfa_flow_info_output { 6701 __le16 error_code; 6702 __le16 req_type; 6703 __le16 seq_id; 6704 __le16 resp_len; 6705 u8 flags; 6706 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6707 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6708 u8 profile; 6709 __le16 src_fid; 6710 __le16 dst_fid; 6711 __le16 l2_ctxt_id; 6712 __le64 em_info; 6713 __le64 tcam_info; 6714 __le64 vfp_tcam_info; 6715 __le16 ar_id; 6716 __le16 flow_handle; 6717 __le32 tunnel_handle; 6718 __le16 flow_timer; 6719 u8 unused_0[6]; 6720 __le32 flow_key_data[130]; 6721 __le32 flow_action_info[30]; 6722 u8 unused_1[7]; 6723 u8 valid; 6724 }; 6725 6726 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6727 struct hwrm_cfa_flow_stats_input { 6728 __le16 req_type; 6729 __le16 cmpl_ring; 6730 __le16 seq_id; 6731 __le16 target_id; 6732 __le64 resp_addr; 6733 __le16 num_flows; 6734 __le16 flow_handle_0; 6735 __le16 flow_handle_1; 6736 __le16 flow_handle_2; 6737 __le16 flow_handle_3; 6738 __le16 flow_handle_4; 6739 __le16 flow_handle_5; 6740 __le16 flow_handle_6; 6741 __le16 flow_handle_7; 6742 __le16 flow_handle_8; 6743 __le16 flow_handle_9; 6744 u8 unused_0[2]; 6745 __le32 flow_id_0; 6746 __le32 flow_id_1; 6747 __le32 flow_id_2; 6748 __le32 flow_id_3; 6749 __le32 flow_id_4; 6750 __le32 flow_id_5; 6751 __le32 flow_id_6; 6752 __le32 flow_id_7; 6753 __le32 flow_id_8; 6754 __le32 flow_id_9; 6755 }; 6756 6757 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6758 struct hwrm_cfa_flow_stats_output { 6759 __le16 error_code; 6760 __le16 req_type; 6761 __le16 seq_id; 6762 __le16 resp_len; 6763 __le64 packet_0; 6764 __le64 packet_1; 6765 __le64 packet_2; 6766 __le64 packet_3; 6767 __le64 packet_4; 6768 __le64 packet_5; 6769 __le64 packet_6; 6770 __le64 packet_7; 6771 __le64 packet_8; 6772 __le64 packet_9; 6773 __le64 byte_0; 6774 __le64 byte_1; 6775 __le64 byte_2; 6776 __le64 byte_3; 6777 __le64 byte_4; 6778 __le64 byte_5; 6779 __le64 byte_6; 6780 __le64 byte_7; 6781 __le64 byte_8; 6782 __le64 byte_9; 6783 u8 unused_0[7]; 6784 u8 valid; 6785 }; 6786 6787 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6788 struct hwrm_cfa_vfr_alloc_input { 6789 __le16 req_type; 6790 __le16 cmpl_ring; 6791 __le16 seq_id; 6792 __le16 target_id; 6793 __le64 resp_addr; 6794 __le16 vf_id; 6795 __le16 reserved; 6796 u8 unused_0[4]; 6797 char vfr_name[32]; 6798 }; 6799 6800 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6801 struct hwrm_cfa_vfr_alloc_output { 6802 __le16 error_code; 6803 __le16 req_type; 6804 __le16 seq_id; 6805 __le16 resp_len; 6806 __le16 rx_cfa_code; 6807 __le16 tx_cfa_action; 6808 u8 unused_0[3]; 6809 u8 valid; 6810 }; 6811 6812 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 6813 struct hwrm_cfa_vfr_free_input { 6814 __le16 req_type; 6815 __le16 cmpl_ring; 6816 __le16 seq_id; 6817 __le16 target_id; 6818 __le64 resp_addr; 6819 char vfr_name[32]; 6820 __le16 vf_id; 6821 __le16 reserved; 6822 u8 unused_0[4]; 6823 }; 6824 6825 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6826 struct hwrm_cfa_vfr_free_output { 6827 __le16 error_code; 6828 __le16 req_type; 6829 __le16 seq_id; 6830 __le16 resp_len; 6831 u8 unused_0[7]; 6832 u8 valid; 6833 }; 6834 6835 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6836 struct hwrm_cfa_eem_qcaps_input { 6837 __le16 req_type; 6838 __le16 cmpl_ring; 6839 __le16 seq_id; 6840 __le16 target_id; 6841 __le64 resp_addr; 6842 __le32 flags; 6843 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6844 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6845 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6846 __le32 unused_0; 6847 }; 6848 6849 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 6850 struct hwrm_cfa_eem_qcaps_output { 6851 __le16 error_code; 6852 __le16 req_type; 6853 __le16 seq_id; 6854 __le16 resp_len; 6855 __le32 flags; 6856 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6857 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6858 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 6859 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 6860 __le32 unused_0; 6861 __le32 supported; 6862 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6863 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6864 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6865 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6866 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 6867 __le32 max_entries_supported; 6868 __le16 key_entry_size; 6869 __le16 record_entry_size; 6870 __le16 efc_entry_size; 6871 __le16 fid_entry_size; 6872 u8 unused_1[7]; 6873 u8 valid; 6874 }; 6875 6876 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 6877 struct hwrm_cfa_eem_cfg_input { 6878 __le16 req_type; 6879 __le16 cmpl_ring; 6880 __le16 seq_id; 6881 __le16 target_id; 6882 __le64 resp_addr; 6883 __le32 flags; 6884 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6885 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6886 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6887 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 6888 __le16 group_id; 6889 __le16 unused_0; 6890 __le32 num_entries; 6891 __le32 unused_1; 6892 __le16 key0_ctx_id; 6893 __le16 key1_ctx_id; 6894 __le16 record_ctx_id; 6895 __le16 efc_ctx_id; 6896 __le16 fid_ctx_id; 6897 __le16 unused_2; 6898 __le32 unused_3; 6899 }; 6900 6901 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6902 struct hwrm_cfa_eem_cfg_output { 6903 __le16 error_code; 6904 __le16 req_type; 6905 __le16 seq_id; 6906 __le16 resp_len; 6907 u8 unused_0[7]; 6908 u8 valid; 6909 }; 6910 6911 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6912 struct hwrm_cfa_eem_qcfg_input { 6913 __le16 req_type; 6914 __le16 cmpl_ring; 6915 __le16 seq_id; 6916 __le16 target_id; 6917 __le64 resp_addr; 6918 __le32 flags; 6919 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6920 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6921 __le32 unused_0; 6922 }; 6923 6924 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 6925 struct hwrm_cfa_eem_qcfg_output { 6926 __le16 error_code; 6927 __le16 req_type; 6928 __le16 seq_id; 6929 __le16 resp_len; 6930 __le32 flags; 6931 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6932 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6933 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6934 __le32 num_entries; 6935 __le16 key0_ctx_id; 6936 __le16 key1_ctx_id; 6937 __le16 record_ctx_id; 6938 __le16 efc_ctx_id; 6939 __le16 fid_ctx_id; 6940 u8 unused_2[5]; 6941 u8 valid; 6942 }; 6943 6944 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 6945 struct hwrm_cfa_eem_op_input { 6946 __le16 req_type; 6947 __le16 cmpl_ring; 6948 __le16 seq_id; 6949 __le16 target_id; 6950 __le64 resp_addr; 6951 __le32 flags; 6952 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6953 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6954 __le16 unused_0; 6955 __le16 op; 6956 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6957 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6958 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6959 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6960 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6961 }; 6962 6963 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 6964 struct hwrm_cfa_eem_op_output { 6965 __le16 error_code; 6966 __le16 req_type; 6967 __le16 seq_id; 6968 __le16 resp_len; 6969 u8 unused_0[7]; 6970 u8 valid; 6971 }; 6972 6973 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 6974 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 6975 __le16 req_type; 6976 __le16 cmpl_ring; 6977 __le16 seq_id; 6978 __le16 target_id; 6979 __le64 resp_addr; 6980 __le32 unused_0[4]; 6981 }; 6982 6983 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 6984 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 6985 __le16 error_code; 6986 __le16 req_type; 6987 __le16 seq_id; 6988 __le16 resp_len; 6989 __le32 flags; 6990 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6991 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6992 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6993 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6994 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6995 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6996 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6997 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6998 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 6999 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7000 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7001 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7002 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7003 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7004 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7005 u8 unused_0[3]; 7006 u8 valid; 7007 }; 7008 7009 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7010 struct hwrm_tunnel_dst_port_query_input { 7011 __le16 req_type; 7012 __le16 cmpl_ring; 7013 __le16 seq_id; 7014 __le16 target_id; 7015 __le64 resp_addr; 7016 u8 tunnel_type; 7017 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7018 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7019 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7020 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7021 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7022 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7023 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7024 u8 unused_0[7]; 7025 }; 7026 7027 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7028 struct hwrm_tunnel_dst_port_query_output { 7029 __le16 error_code; 7030 __le16 req_type; 7031 __le16 seq_id; 7032 __le16 resp_len; 7033 __le16 tunnel_dst_port_id; 7034 __be16 tunnel_dst_port_val; 7035 u8 unused_0[3]; 7036 u8 valid; 7037 }; 7038 7039 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7040 struct hwrm_tunnel_dst_port_alloc_input { 7041 __le16 req_type; 7042 __le16 cmpl_ring; 7043 __le16 seq_id; 7044 __le16 target_id; 7045 __le64 resp_addr; 7046 u8 tunnel_type; 7047 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7048 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7049 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7050 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7051 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7052 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7053 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7054 u8 unused_0; 7055 __be16 tunnel_dst_port_val; 7056 u8 unused_1[4]; 7057 }; 7058 7059 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7060 struct hwrm_tunnel_dst_port_alloc_output { 7061 __le16 error_code; 7062 __le16 req_type; 7063 __le16 seq_id; 7064 __le16 resp_len; 7065 __le16 tunnel_dst_port_id; 7066 u8 unused_0[5]; 7067 u8 valid; 7068 }; 7069 7070 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7071 struct hwrm_tunnel_dst_port_free_input { 7072 __le16 req_type; 7073 __le16 cmpl_ring; 7074 __le16 seq_id; 7075 __le16 target_id; 7076 __le64 resp_addr; 7077 u8 tunnel_type; 7078 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7079 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7080 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7081 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7082 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7083 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7084 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7085 u8 unused_0; 7086 __le16 tunnel_dst_port_id; 7087 u8 unused_1[4]; 7088 }; 7089 7090 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7091 struct hwrm_tunnel_dst_port_free_output { 7092 __le16 error_code; 7093 __le16 req_type; 7094 __le16 seq_id; 7095 __le16 resp_len; 7096 u8 unused_1[7]; 7097 u8 valid; 7098 }; 7099 7100 /* ctx_hw_stats (size:1280b/160B) */ 7101 struct ctx_hw_stats { 7102 __le64 rx_ucast_pkts; 7103 __le64 rx_mcast_pkts; 7104 __le64 rx_bcast_pkts; 7105 __le64 rx_discard_pkts; 7106 __le64 rx_error_pkts; 7107 __le64 rx_ucast_bytes; 7108 __le64 rx_mcast_bytes; 7109 __le64 rx_bcast_bytes; 7110 __le64 tx_ucast_pkts; 7111 __le64 tx_mcast_pkts; 7112 __le64 tx_bcast_pkts; 7113 __le64 tx_error_pkts; 7114 __le64 tx_discard_pkts; 7115 __le64 tx_ucast_bytes; 7116 __le64 tx_mcast_bytes; 7117 __le64 tx_bcast_bytes; 7118 __le64 tpa_pkts; 7119 __le64 tpa_bytes; 7120 __le64 tpa_events; 7121 __le64 tpa_aborts; 7122 }; 7123 7124 /* ctx_hw_stats_ext (size:1408b/176B) */ 7125 struct ctx_hw_stats_ext { 7126 __le64 rx_ucast_pkts; 7127 __le64 rx_mcast_pkts; 7128 __le64 rx_bcast_pkts; 7129 __le64 rx_discard_pkts; 7130 __le64 rx_error_pkts; 7131 __le64 rx_ucast_bytes; 7132 __le64 rx_mcast_bytes; 7133 __le64 rx_bcast_bytes; 7134 __le64 tx_ucast_pkts; 7135 __le64 tx_mcast_pkts; 7136 __le64 tx_bcast_pkts; 7137 __le64 tx_error_pkts; 7138 __le64 tx_discard_pkts; 7139 __le64 tx_ucast_bytes; 7140 __le64 tx_mcast_bytes; 7141 __le64 tx_bcast_bytes; 7142 __le64 rx_tpa_eligible_pkt; 7143 __le64 rx_tpa_eligible_bytes; 7144 __le64 rx_tpa_pkt; 7145 __le64 rx_tpa_bytes; 7146 __le64 rx_tpa_errors; 7147 __le64 rx_tpa_events; 7148 }; 7149 7150 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7151 struct hwrm_stat_ctx_alloc_input { 7152 __le16 req_type; 7153 __le16 cmpl_ring; 7154 __le16 seq_id; 7155 __le16 target_id; 7156 __le64 resp_addr; 7157 __le64 stats_dma_addr; 7158 __le32 update_period_ms; 7159 u8 stat_ctx_flags; 7160 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7161 u8 unused_0; 7162 __le16 stats_dma_length; 7163 }; 7164 7165 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7166 struct hwrm_stat_ctx_alloc_output { 7167 __le16 error_code; 7168 __le16 req_type; 7169 __le16 seq_id; 7170 __le16 resp_len; 7171 __le32 stat_ctx_id; 7172 u8 unused_0[3]; 7173 u8 valid; 7174 }; 7175 7176 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7177 struct hwrm_stat_ctx_free_input { 7178 __le16 req_type; 7179 __le16 cmpl_ring; 7180 __le16 seq_id; 7181 __le16 target_id; 7182 __le64 resp_addr; 7183 __le32 stat_ctx_id; 7184 u8 unused_0[4]; 7185 }; 7186 7187 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7188 struct hwrm_stat_ctx_free_output { 7189 __le16 error_code; 7190 __le16 req_type; 7191 __le16 seq_id; 7192 __le16 resp_len; 7193 __le32 stat_ctx_id; 7194 u8 unused_0[3]; 7195 u8 valid; 7196 }; 7197 7198 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 7199 struct hwrm_stat_ctx_query_input { 7200 __le16 req_type; 7201 __le16 cmpl_ring; 7202 __le16 seq_id; 7203 __le16 target_id; 7204 __le64 resp_addr; 7205 __le32 stat_ctx_id; 7206 u8 flags; 7207 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7208 u8 unused_0[3]; 7209 }; 7210 7211 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 7212 struct hwrm_stat_ctx_query_output { 7213 __le16 error_code; 7214 __le16 req_type; 7215 __le16 seq_id; 7216 __le16 resp_len; 7217 __le64 tx_ucast_pkts; 7218 __le64 tx_mcast_pkts; 7219 __le64 tx_bcast_pkts; 7220 __le64 tx_discard_pkts; 7221 __le64 tx_error_pkts; 7222 __le64 tx_ucast_bytes; 7223 __le64 tx_mcast_bytes; 7224 __le64 tx_bcast_bytes; 7225 __le64 rx_ucast_pkts; 7226 __le64 rx_mcast_pkts; 7227 __le64 rx_bcast_pkts; 7228 __le64 rx_discard_pkts; 7229 __le64 rx_error_pkts; 7230 __le64 rx_ucast_bytes; 7231 __le64 rx_mcast_bytes; 7232 __le64 rx_bcast_bytes; 7233 __le64 rx_agg_pkts; 7234 __le64 rx_agg_bytes; 7235 __le64 rx_agg_events; 7236 __le64 rx_agg_aborts; 7237 u8 unused_0[7]; 7238 u8 valid; 7239 }; 7240 7241 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 7242 struct hwrm_stat_ext_ctx_query_input { 7243 __le16 req_type; 7244 __le16 cmpl_ring; 7245 __le16 seq_id; 7246 __le16 target_id; 7247 __le64 resp_addr; 7248 __le32 stat_ctx_id; 7249 u8 flags; 7250 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7251 u8 unused_0[3]; 7252 }; 7253 7254 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 7255 struct hwrm_stat_ext_ctx_query_output { 7256 __le16 error_code; 7257 __le16 req_type; 7258 __le16 seq_id; 7259 __le16 resp_len; 7260 __le64 rx_ucast_pkts; 7261 __le64 rx_mcast_pkts; 7262 __le64 rx_bcast_pkts; 7263 __le64 rx_discard_pkts; 7264 __le64 rx_error_pkts; 7265 __le64 rx_ucast_bytes; 7266 __le64 rx_mcast_bytes; 7267 __le64 rx_bcast_bytes; 7268 __le64 tx_ucast_pkts; 7269 __le64 tx_mcast_pkts; 7270 __le64 tx_bcast_pkts; 7271 __le64 tx_error_pkts; 7272 __le64 tx_discard_pkts; 7273 __le64 tx_ucast_bytes; 7274 __le64 tx_mcast_bytes; 7275 __le64 tx_bcast_bytes; 7276 __le64 rx_tpa_eligible_pkt; 7277 __le64 rx_tpa_eligible_bytes; 7278 __le64 rx_tpa_pkt; 7279 __le64 rx_tpa_bytes; 7280 __le64 rx_tpa_errors; 7281 __le64 rx_tpa_events; 7282 u8 unused_0[7]; 7283 u8 valid; 7284 }; 7285 7286 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 7287 struct hwrm_stat_ctx_clr_stats_input { 7288 __le16 req_type; 7289 __le16 cmpl_ring; 7290 __le16 seq_id; 7291 __le16 target_id; 7292 __le64 resp_addr; 7293 __le32 stat_ctx_id; 7294 u8 unused_0[4]; 7295 }; 7296 7297 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 7298 struct hwrm_stat_ctx_clr_stats_output { 7299 __le16 error_code; 7300 __le16 req_type; 7301 __le16 seq_id; 7302 __le16 resp_len; 7303 u8 unused_0[7]; 7304 u8 valid; 7305 }; 7306 7307 /* hwrm_pcie_qstats_input (size:256b/32B) */ 7308 struct hwrm_pcie_qstats_input { 7309 __le16 req_type; 7310 __le16 cmpl_ring; 7311 __le16 seq_id; 7312 __le16 target_id; 7313 __le64 resp_addr; 7314 __le16 pcie_stat_size; 7315 u8 unused_0[6]; 7316 __le64 pcie_stat_host_addr; 7317 }; 7318 7319 /* hwrm_pcie_qstats_output (size:128b/16B) */ 7320 struct hwrm_pcie_qstats_output { 7321 __le16 error_code; 7322 __le16 req_type; 7323 __le16 seq_id; 7324 __le16 resp_len; 7325 __le16 pcie_stat_size; 7326 u8 unused_0[5]; 7327 u8 valid; 7328 }; 7329 7330 /* pcie_ctx_hw_stats (size:768b/96B) */ 7331 struct pcie_ctx_hw_stats { 7332 __le64 pcie_pl_signal_integrity; 7333 __le64 pcie_dl_signal_integrity; 7334 __le64 pcie_tl_signal_integrity; 7335 __le64 pcie_link_integrity; 7336 __le64 pcie_tx_traffic_rate; 7337 __le64 pcie_rx_traffic_rate; 7338 __le64 pcie_tx_dllp_statistics; 7339 __le64 pcie_rx_dllp_statistics; 7340 __le64 pcie_equalization_time; 7341 __le32 pcie_ltssm_histogram[4]; 7342 __le64 pcie_recovery_histogram; 7343 }; 7344 7345 /* hwrm_fw_reset_input (size:192b/24B) */ 7346 struct hwrm_fw_reset_input { 7347 __le16 req_type; 7348 __le16 cmpl_ring; 7349 __le16 seq_id; 7350 __le16 target_id; 7351 __le64 resp_addr; 7352 u8 embedded_proc_type; 7353 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7354 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7355 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7356 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7357 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7358 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7359 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7360 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 7361 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 7362 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7363 u8 selfrst_status; 7364 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7365 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7366 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7367 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7368 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7369 u8 host_idx; 7370 u8 flags; 7371 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 7372 u8 unused_0[4]; 7373 }; 7374 7375 /* hwrm_fw_reset_output (size:128b/16B) */ 7376 struct hwrm_fw_reset_output { 7377 __le16 error_code; 7378 __le16 req_type; 7379 __le16 seq_id; 7380 __le16 resp_len; 7381 u8 selfrst_status; 7382 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7383 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7384 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7385 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7386 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7387 u8 unused_0[6]; 7388 u8 valid; 7389 }; 7390 7391 /* hwrm_fw_qstatus_input (size:192b/24B) */ 7392 struct hwrm_fw_qstatus_input { 7393 __le16 req_type; 7394 __le16 cmpl_ring; 7395 __le16 seq_id; 7396 __le16 target_id; 7397 __le64 resp_addr; 7398 u8 embedded_proc_type; 7399 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7400 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7401 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7402 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7403 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7404 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7405 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7406 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7407 u8 unused_0[7]; 7408 }; 7409 7410 /* hwrm_fw_qstatus_output (size:128b/16B) */ 7411 struct hwrm_fw_qstatus_output { 7412 __le16 error_code; 7413 __le16 req_type; 7414 __le16 seq_id; 7415 __le16 resp_len; 7416 u8 selfrst_status; 7417 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7418 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7419 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7420 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 7421 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7422 u8 unused_0[6]; 7423 u8 valid; 7424 }; 7425 7426 /* hwrm_fw_set_time_input (size:256b/32B) */ 7427 struct hwrm_fw_set_time_input { 7428 __le16 req_type; 7429 __le16 cmpl_ring; 7430 __le16 seq_id; 7431 __le16 target_id; 7432 __le64 resp_addr; 7433 __le16 year; 7434 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7435 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7436 u8 month; 7437 u8 day; 7438 u8 hour; 7439 u8 minute; 7440 u8 second; 7441 u8 unused_0; 7442 __le16 millisecond; 7443 __le16 zone; 7444 #define FW_SET_TIME_REQ_ZONE_UTC 0 7445 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7446 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7447 u8 unused_1[4]; 7448 }; 7449 7450 /* hwrm_fw_set_time_output (size:128b/16B) */ 7451 struct hwrm_fw_set_time_output { 7452 __le16 error_code; 7453 __le16 req_type; 7454 __le16 seq_id; 7455 __le16 resp_len; 7456 u8 unused_0[7]; 7457 u8 valid; 7458 }; 7459 7460 /* hwrm_struct_hdr (size:128b/16B) */ 7461 struct hwrm_struct_hdr { 7462 __le16 struct_id; 7463 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7464 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7465 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7466 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7467 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7468 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7469 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 7470 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 7471 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7472 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7473 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7474 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 7475 __le16 len; 7476 u8 version; 7477 u8 count; 7478 __le16 subtype; 7479 __le16 next_offset; 7480 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7481 u8 unused_0[6]; 7482 }; 7483 7484 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7485 struct hwrm_struct_data_dcbx_app { 7486 __be16 protocol_id; 7487 u8 protocol_selector; 7488 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7489 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7490 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7491 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7492 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 7493 u8 priority; 7494 u8 valid; 7495 u8 unused_0[3]; 7496 }; 7497 7498 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7499 struct hwrm_fw_set_structured_data_input { 7500 __le16 req_type; 7501 __le16 cmpl_ring; 7502 __le16 seq_id; 7503 __le16 target_id; 7504 __le64 resp_addr; 7505 __le64 src_data_addr; 7506 __le16 data_len; 7507 u8 hdr_cnt; 7508 u8 unused_0[5]; 7509 }; 7510 7511 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7512 struct hwrm_fw_set_structured_data_output { 7513 __le16 error_code; 7514 __le16 req_type; 7515 __le16 seq_id; 7516 __le16 resp_len; 7517 u8 unused_0[7]; 7518 u8 valid; 7519 }; 7520 7521 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7522 struct hwrm_fw_set_structured_data_cmd_err { 7523 u8 code; 7524 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7525 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7526 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7527 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7528 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7529 u8 unused_0[7]; 7530 }; 7531 7532 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7533 struct hwrm_fw_get_structured_data_input { 7534 __le16 req_type; 7535 __le16 cmpl_ring; 7536 __le16 seq_id; 7537 __le16 target_id; 7538 __le64 resp_addr; 7539 __le64 dest_data_addr; 7540 __le16 data_len; 7541 __le16 structure_id; 7542 __le16 subtype; 7543 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7544 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7545 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7546 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7547 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7548 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7549 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7550 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7551 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7552 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7553 u8 count; 7554 u8 unused_0; 7555 }; 7556 7557 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7558 struct hwrm_fw_get_structured_data_output { 7559 __le16 error_code; 7560 __le16 req_type; 7561 __le16 seq_id; 7562 __le16 resp_len; 7563 u8 hdr_cnt; 7564 u8 unused_0[6]; 7565 u8 valid; 7566 }; 7567 7568 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7569 struct hwrm_fw_get_structured_data_cmd_err { 7570 u8 code; 7571 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7572 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7573 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7574 u8 unused_0[7]; 7575 }; 7576 7577 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7578 struct hwrm_exec_fwd_resp_input { 7579 __le16 req_type; 7580 __le16 cmpl_ring; 7581 __le16 seq_id; 7582 __le16 target_id; 7583 __le64 resp_addr; 7584 __le32 encap_request[26]; 7585 __le16 encap_resp_target_id; 7586 u8 unused_0[6]; 7587 }; 7588 7589 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7590 struct hwrm_exec_fwd_resp_output { 7591 __le16 error_code; 7592 __le16 req_type; 7593 __le16 seq_id; 7594 __le16 resp_len; 7595 u8 unused_0[7]; 7596 u8 valid; 7597 }; 7598 7599 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7600 struct hwrm_reject_fwd_resp_input { 7601 __le16 req_type; 7602 __le16 cmpl_ring; 7603 __le16 seq_id; 7604 __le16 target_id; 7605 __le64 resp_addr; 7606 __le32 encap_request[26]; 7607 __le16 encap_resp_target_id; 7608 u8 unused_0[6]; 7609 }; 7610 7611 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7612 struct hwrm_reject_fwd_resp_output { 7613 __le16 error_code; 7614 __le16 req_type; 7615 __le16 seq_id; 7616 __le16 resp_len; 7617 u8 unused_0[7]; 7618 u8 valid; 7619 }; 7620 7621 /* hwrm_fwd_resp_input (size:1024b/128B) */ 7622 struct hwrm_fwd_resp_input { 7623 __le16 req_type; 7624 __le16 cmpl_ring; 7625 __le16 seq_id; 7626 __le16 target_id; 7627 __le64 resp_addr; 7628 __le16 encap_resp_target_id; 7629 __le16 encap_resp_cmpl_ring; 7630 __le16 encap_resp_len; 7631 u8 unused_0; 7632 u8 unused_1; 7633 __le64 encap_resp_addr; 7634 __le32 encap_resp[24]; 7635 }; 7636 7637 /* hwrm_fwd_resp_output (size:128b/16B) */ 7638 struct hwrm_fwd_resp_output { 7639 __le16 error_code; 7640 __le16 req_type; 7641 __le16 seq_id; 7642 __le16 resp_len; 7643 u8 unused_0[7]; 7644 u8 valid; 7645 }; 7646 7647 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7648 struct hwrm_fwd_async_event_cmpl_input { 7649 __le16 req_type; 7650 __le16 cmpl_ring; 7651 __le16 seq_id; 7652 __le16 target_id; 7653 __le64 resp_addr; 7654 __le16 encap_async_event_target_id; 7655 u8 unused_0[6]; 7656 __le32 encap_async_event_cmpl[4]; 7657 }; 7658 7659 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7660 struct hwrm_fwd_async_event_cmpl_output { 7661 __le16 error_code; 7662 __le16 req_type; 7663 __le16 seq_id; 7664 __le16 resp_len; 7665 u8 unused_0[7]; 7666 u8 valid; 7667 }; 7668 7669 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7670 struct hwrm_temp_monitor_query_input { 7671 __le16 req_type; 7672 __le16 cmpl_ring; 7673 __le16 seq_id; 7674 __le16 target_id; 7675 __le64 resp_addr; 7676 }; 7677 7678 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7679 struct hwrm_temp_monitor_query_output { 7680 __le16 error_code; 7681 __le16 req_type; 7682 __le16 seq_id; 7683 __le16 resp_len; 7684 u8 temp; 7685 u8 phy_temp; 7686 u8 om_temp; 7687 u8 flags; 7688 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 7689 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 7690 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 7691 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 7692 u8 unused_0[3]; 7693 u8 valid; 7694 }; 7695 7696 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7697 struct hwrm_wol_filter_alloc_input { 7698 __le16 req_type; 7699 __le16 cmpl_ring; 7700 __le16 seq_id; 7701 __le16 target_id; 7702 __le64 resp_addr; 7703 __le32 flags; 7704 __le32 enables; 7705 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7706 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7707 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7708 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7709 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7710 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7711 __le16 port_id; 7712 u8 wol_type; 7713 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7714 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7715 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7716 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7717 u8 unused_0[5]; 7718 u8 mac_address[6]; 7719 __le16 pattern_offset; 7720 __le16 pattern_buf_size; 7721 __le16 pattern_mask_size; 7722 u8 unused_1[4]; 7723 __le64 pattern_buf_addr; 7724 __le64 pattern_mask_addr; 7725 }; 7726 7727 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7728 struct hwrm_wol_filter_alloc_output { 7729 __le16 error_code; 7730 __le16 req_type; 7731 __le16 seq_id; 7732 __le16 resp_len; 7733 u8 wol_filter_id; 7734 u8 unused_0[6]; 7735 u8 valid; 7736 }; 7737 7738 /* hwrm_wol_filter_free_input (size:256b/32B) */ 7739 struct hwrm_wol_filter_free_input { 7740 __le16 req_type; 7741 __le16 cmpl_ring; 7742 __le16 seq_id; 7743 __le16 target_id; 7744 __le64 resp_addr; 7745 __le32 flags; 7746 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7747 __le32 enables; 7748 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7749 __le16 port_id; 7750 u8 wol_filter_id; 7751 u8 unused_0[5]; 7752 }; 7753 7754 /* hwrm_wol_filter_free_output (size:128b/16B) */ 7755 struct hwrm_wol_filter_free_output { 7756 __le16 error_code; 7757 __le16 req_type; 7758 __le16 seq_id; 7759 __le16 resp_len; 7760 u8 unused_0[7]; 7761 u8 valid; 7762 }; 7763 7764 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7765 struct hwrm_wol_filter_qcfg_input { 7766 __le16 req_type; 7767 __le16 cmpl_ring; 7768 __le16 seq_id; 7769 __le16 target_id; 7770 __le64 resp_addr; 7771 __le16 port_id; 7772 __le16 handle; 7773 u8 unused_0[4]; 7774 __le64 pattern_buf_addr; 7775 __le16 pattern_buf_size; 7776 u8 unused_1[6]; 7777 __le64 pattern_mask_addr; 7778 __le16 pattern_mask_size; 7779 u8 unused_2[6]; 7780 }; 7781 7782 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7783 struct hwrm_wol_filter_qcfg_output { 7784 __le16 error_code; 7785 __le16 req_type; 7786 __le16 seq_id; 7787 __le16 resp_len; 7788 __le16 next_handle; 7789 u8 wol_filter_id; 7790 u8 wol_type; 7791 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7792 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7793 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7794 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7795 __le32 unused_0; 7796 u8 mac_address[6]; 7797 __le16 pattern_offset; 7798 __le16 pattern_size; 7799 __le16 pattern_mask_size; 7800 u8 unused_1[3]; 7801 u8 valid; 7802 }; 7803 7804 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7805 struct hwrm_wol_reason_qcfg_input { 7806 __le16 req_type; 7807 __le16 cmpl_ring; 7808 __le16 seq_id; 7809 __le16 target_id; 7810 __le64 resp_addr; 7811 __le16 port_id; 7812 u8 unused_0[6]; 7813 __le64 wol_pkt_buf_addr; 7814 __le16 wol_pkt_buf_size; 7815 u8 unused_1[6]; 7816 }; 7817 7818 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7819 struct hwrm_wol_reason_qcfg_output { 7820 __le16 error_code; 7821 __le16 req_type; 7822 __le16 seq_id; 7823 __le16 resp_len; 7824 u8 wol_filter_id; 7825 u8 wol_reason; 7826 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7827 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7828 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7829 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7830 u8 wol_pkt_len; 7831 u8 unused_0[4]; 7832 u8 valid; 7833 }; 7834 7835 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 7836 struct hwrm_dbg_read_direct_input { 7837 __le16 req_type; 7838 __le16 cmpl_ring; 7839 __le16 seq_id; 7840 __le16 target_id; 7841 __le64 resp_addr; 7842 __le64 host_dest_addr; 7843 __le32 read_addr; 7844 __le32 read_len32; 7845 }; 7846 7847 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 7848 struct hwrm_dbg_read_direct_output { 7849 __le16 error_code; 7850 __le16 req_type; 7851 __le16 seq_id; 7852 __le16 resp_len; 7853 __le32 crc32; 7854 u8 unused_0[3]; 7855 u8 valid; 7856 }; 7857 7858 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 7859 struct hwrm_dbg_qcaps_input { 7860 __le16 req_type; 7861 __le16 cmpl_ring; 7862 __le16 seq_id; 7863 __le16 target_id; 7864 __le64 resp_addr; 7865 __le16 fid; 7866 u8 unused_0[6]; 7867 }; 7868 7869 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 7870 struct hwrm_dbg_qcaps_output { 7871 __le16 error_code; 7872 __le16 req_type; 7873 __le16 seq_id; 7874 __le16 resp_len; 7875 __le16 fid; 7876 u8 unused_0[2]; 7877 __le32 coredump_component_disable_caps; 7878 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 7879 __le32 flags; 7880 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 7881 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 7882 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 7883 u8 unused_1[3]; 7884 u8 valid; 7885 }; 7886 7887 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 7888 struct hwrm_dbg_qcfg_input { 7889 __le16 req_type; 7890 __le16 cmpl_ring; 7891 __le16 seq_id; 7892 __le16 target_id; 7893 __le64 resp_addr; 7894 __le16 fid; 7895 __le16 flags; 7896 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 7897 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 7898 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 7899 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 7900 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 7901 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 7902 __le32 coredump_component_disable_flags; 7903 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 7904 }; 7905 7906 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 7907 struct hwrm_dbg_qcfg_output { 7908 __le16 error_code; 7909 __le16 req_type; 7910 __le16 seq_id; 7911 __le16 resp_len; 7912 __le16 fid; 7913 u8 unused_0[2]; 7914 __le32 coredump_size; 7915 __le32 flags; 7916 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 7917 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 7918 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 7919 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 7920 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 7921 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 7922 __le16 async_cmpl_ring; 7923 u8 unused_2[2]; 7924 __le32 crashdump_size; 7925 u8 unused_3[3]; 7926 u8 valid; 7927 }; 7928 7929 /* coredump_segment_record (size:128b/16B) */ 7930 struct coredump_segment_record { 7931 __le16 component_id; 7932 __le16 segment_id; 7933 __le16 max_instances; 7934 u8 version_hi; 7935 u8 version_low; 7936 u8 seg_flags; 7937 u8 compress_flags; 7938 #define SFLAG_COMPRESSED_ZLIB 0x1UL 7939 u8 unused_0[2]; 7940 __le32 segment_len; 7941 }; 7942 7943 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7944 struct hwrm_dbg_coredump_list_input { 7945 __le16 req_type; 7946 __le16 cmpl_ring; 7947 __le16 seq_id; 7948 __le16 target_id; 7949 __le64 resp_addr; 7950 __le64 host_dest_addr; 7951 __le32 host_buf_len; 7952 __le16 seq_no; 7953 u8 flags; 7954 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 7955 u8 unused_0[1]; 7956 }; 7957 7958 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7959 struct hwrm_dbg_coredump_list_output { 7960 __le16 error_code; 7961 __le16 req_type; 7962 __le16 seq_id; 7963 __le16 resp_len; 7964 u8 flags; 7965 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7966 u8 unused_0; 7967 __le16 total_segments; 7968 __le16 data_len; 7969 u8 unused_1; 7970 u8 valid; 7971 }; 7972 7973 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7974 struct hwrm_dbg_coredump_initiate_input { 7975 __le16 req_type; 7976 __le16 cmpl_ring; 7977 __le16 seq_id; 7978 __le16 target_id; 7979 __le64 resp_addr; 7980 __le16 component_id; 7981 __le16 segment_id; 7982 __le16 instance; 7983 __le16 unused_0; 7984 u8 seg_flags; 7985 u8 unused_1[7]; 7986 }; 7987 7988 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7989 struct hwrm_dbg_coredump_initiate_output { 7990 __le16 error_code; 7991 __le16 req_type; 7992 __le16 seq_id; 7993 __le16 resp_len; 7994 u8 unused_0[7]; 7995 u8 valid; 7996 }; 7997 7998 /* coredump_data_hdr (size:128b/16B) */ 7999 struct coredump_data_hdr { 8000 __le32 address; 8001 __le32 flags_length; 8002 __le32 instance; 8003 __le32 next_offset; 8004 }; 8005 8006 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8007 struct hwrm_dbg_coredump_retrieve_input { 8008 __le16 req_type; 8009 __le16 cmpl_ring; 8010 __le16 seq_id; 8011 __le16 target_id; 8012 __le64 resp_addr; 8013 __le64 host_dest_addr; 8014 __le32 host_buf_len; 8015 __le32 unused_0; 8016 __le16 component_id; 8017 __le16 segment_id; 8018 __le16 instance; 8019 __le16 unused_1; 8020 u8 seg_flags; 8021 u8 unused_2; 8022 __le16 unused_3; 8023 __le32 unused_4; 8024 __le32 seq_no; 8025 __le32 unused_5; 8026 }; 8027 8028 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 8029 struct hwrm_dbg_coredump_retrieve_output { 8030 __le16 error_code; 8031 __le16 req_type; 8032 __le16 seq_id; 8033 __le16 resp_len; 8034 u8 flags; 8035 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 8036 u8 unused_0; 8037 __le16 data_len; 8038 u8 unused_1[3]; 8039 u8 valid; 8040 }; 8041 8042 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 8043 struct hwrm_dbg_ring_info_get_input { 8044 __le16 req_type; 8045 __le16 cmpl_ring; 8046 __le16 seq_id; 8047 __le16 target_id; 8048 __le64 resp_addr; 8049 u8 ring_type; 8050 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 8051 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 8052 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8053 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8054 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 8055 u8 unused_0[3]; 8056 __le32 fw_ring_id; 8057 }; 8058 8059 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 8060 struct hwrm_dbg_ring_info_get_output { 8061 __le16 error_code; 8062 __le16 req_type; 8063 __le16 seq_id; 8064 __le16 resp_len; 8065 __le32 producer_index; 8066 __le32 consumer_index; 8067 __le32 cag_vector_ctrl; 8068 u8 unused_0[3]; 8069 u8 valid; 8070 }; 8071 8072 /* hwrm_nvm_read_input (size:320b/40B) */ 8073 struct hwrm_nvm_read_input { 8074 __le16 req_type; 8075 __le16 cmpl_ring; 8076 __le16 seq_id; 8077 __le16 target_id; 8078 __le64 resp_addr; 8079 __le64 host_dest_addr; 8080 __le16 dir_idx; 8081 u8 unused_0[2]; 8082 __le32 offset; 8083 __le32 len; 8084 u8 unused_1[4]; 8085 }; 8086 8087 /* hwrm_nvm_read_output (size:128b/16B) */ 8088 struct hwrm_nvm_read_output { 8089 __le16 error_code; 8090 __le16 req_type; 8091 __le16 seq_id; 8092 __le16 resp_len; 8093 u8 unused_0[7]; 8094 u8 valid; 8095 }; 8096 8097 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8098 struct hwrm_nvm_get_dir_entries_input { 8099 __le16 req_type; 8100 __le16 cmpl_ring; 8101 __le16 seq_id; 8102 __le16 target_id; 8103 __le64 resp_addr; 8104 __le64 host_dest_addr; 8105 }; 8106 8107 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8108 struct hwrm_nvm_get_dir_entries_output { 8109 __le16 error_code; 8110 __le16 req_type; 8111 __le16 seq_id; 8112 __le16 resp_len; 8113 u8 unused_0[7]; 8114 u8 valid; 8115 }; 8116 8117 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8118 struct hwrm_nvm_get_dir_info_input { 8119 __le16 req_type; 8120 __le16 cmpl_ring; 8121 __le16 seq_id; 8122 __le16 target_id; 8123 __le64 resp_addr; 8124 }; 8125 8126 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8127 struct hwrm_nvm_get_dir_info_output { 8128 __le16 error_code; 8129 __le16 req_type; 8130 __le16 seq_id; 8131 __le16 resp_len; 8132 __le32 entries; 8133 __le32 entry_length; 8134 u8 unused_0[7]; 8135 u8 valid; 8136 }; 8137 8138 /* hwrm_nvm_write_input (size:384b/48B) */ 8139 struct hwrm_nvm_write_input { 8140 __le16 req_type; 8141 __le16 cmpl_ring; 8142 __le16 seq_id; 8143 __le16 target_id; 8144 __le64 resp_addr; 8145 __le64 host_src_addr; 8146 __le16 dir_type; 8147 __le16 dir_ordinal; 8148 __le16 dir_ext; 8149 __le16 dir_attr; 8150 __le32 dir_data_length; 8151 __le16 option; 8152 __le16 flags; 8153 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 8154 __le32 dir_item_length; 8155 __le32 unused_0; 8156 }; 8157 8158 /* hwrm_nvm_write_output (size:128b/16B) */ 8159 struct hwrm_nvm_write_output { 8160 __le16 error_code; 8161 __le16 req_type; 8162 __le16 seq_id; 8163 __le16 resp_len; 8164 __le32 dir_item_length; 8165 __le16 dir_idx; 8166 u8 unused_0; 8167 u8 valid; 8168 }; 8169 8170 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 8171 struct hwrm_nvm_write_cmd_err { 8172 u8 code; 8173 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 8174 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8175 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 8176 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 8177 u8 unused_0[7]; 8178 }; 8179 8180 /* hwrm_nvm_modify_input (size:320b/40B) */ 8181 struct hwrm_nvm_modify_input { 8182 __le16 req_type; 8183 __le16 cmpl_ring; 8184 __le16 seq_id; 8185 __le16 target_id; 8186 __le64 resp_addr; 8187 __le64 host_src_addr; 8188 __le16 dir_idx; 8189 __le16 flags; 8190 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 8191 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 8192 __le32 offset; 8193 __le32 len; 8194 u8 unused_1[4]; 8195 }; 8196 8197 /* hwrm_nvm_modify_output (size:128b/16B) */ 8198 struct hwrm_nvm_modify_output { 8199 __le16 error_code; 8200 __le16 req_type; 8201 __le16 seq_id; 8202 __le16 resp_len; 8203 u8 unused_0[7]; 8204 u8 valid; 8205 }; 8206 8207 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 8208 struct hwrm_nvm_find_dir_entry_input { 8209 __le16 req_type; 8210 __le16 cmpl_ring; 8211 __le16 seq_id; 8212 __le16 target_id; 8213 __le64 resp_addr; 8214 __le32 enables; 8215 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 8216 __le16 dir_idx; 8217 __le16 dir_type; 8218 __le16 dir_ordinal; 8219 __le16 dir_ext; 8220 u8 opt_ordinal; 8221 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 8222 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 8223 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 8224 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 8225 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 8226 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 8227 u8 unused_0[3]; 8228 }; 8229 8230 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 8231 struct hwrm_nvm_find_dir_entry_output { 8232 __le16 error_code; 8233 __le16 req_type; 8234 __le16 seq_id; 8235 __le16 resp_len; 8236 __le32 dir_item_length; 8237 __le32 dir_data_length; 8238 __le32 fw_ver; 8239 __le16 dir_ordinal; 8240 __le16 dir_idx; 8241 u8 unused_0[7]; 8242 u8 valid; 8243 }; 8244 8245 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 8246 struct hwrm_nvm_erase_dir_entry_input { 8247 __le16 req_type; 8248 __le16 cmpl_ring; 8249 __le16 seq_id; 8250 __le16 target_id; 8251 __le64 resp_addr; 8252 __le16 dir_idx; 8253 u8 unused_0[6]; 8254 }; 8255 8256 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 8257 struct hwrm_nvm_erase_dir_entry_output { 8258 __le16 error_code; 8259 __le16 req_type; 8260 __le16 seq_id; 8261 __le16 resp_len; 8262 u8 unused_0[7]; 8263 u8 valid; 8264 }; 8265 8266 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 8267 struct hwrm_nvm_get_dev_info_input { 8268 __le16 req_type; 8269 __le16 cmpl_ring; 8270 __le16 seq_id; 8271 __le16 target_id; 8272 __le64 resp_addr; 8273 }; 8274 8275 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 8276 struct hwrm_nvm_get_dev_info_output { 8277 __le16 error_code; 8278 __le16 req_type; 8279 __le16 seq_id; 8280 __le16 resp_len; 8281 __le16 manufacturer_id; 8282 __le16 device_id; 8283 __le32 sector_size; 8284 __le32 nvram_size; 8285 __le32 reserved_size; 8286 __le32 available_size; 8287 u8 nvm_cfg_ver_maj; 8288 u8 nvm_cfg_ver_min; 8289 u8 nvm_cfg_ver_upd; 8290 u8 valid; 8291 }; 8292 8293 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 8294 struct hwrm_nvm_mod_dir_entry_input { 8295 __le16 req_type; 8296 __le16 cmpl_ring; 8297 __le16 seq_id; 8298 __le16 target_id; 8299 __le64 resp_addr; 8300 __le32 enables; 8301 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 8302 __le16 dir_idx; 8303 __le16 dir_ordinal; 8304 __le16 dir_ext; 8305 __le16 dir_attr; 8306 __le32 checksum; 8307 }; 8308 8309 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 8310 struct hwrm_nvm_mod_dir_entry_output { 8311 __le16 error_code; 8312 __le16 req_type; 8313 __le16 seq_id; 8314 __le16 resp_len; 8315 u8 unused_0[7]; 8316 u8 valid; 8317 }; 8318 8319 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 8320 struct hwrm_nvm_verify_update_input { 8321 __le16 req_type; 8322 __le16 cmpl_ring; 8323 __le16 seq_id; 8324 __le16 target_id; 8325 __le64 resp_addr; 8326 __le16 dir_type; 8327 __le16 dir_ordinal; 8328 __le16 dir_ext; 8329 u8 unused_0[2]; 8330 }; 8331 8332 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 8333 struct hwrm_nvm_verify_update_output { 8334 __le16 error_code; 8335 __le16 req_type; 8336 __le16 seq_id; 8337 __le16 resp_len; 8338 u8 unused_0[7]; 8339 u8 valid; 8340 }; 8341 8342 /* hwrm_nvm_install_update_input (size:192b/24B) */ 8343 struct hwrm_nvm_install_update_input { 8344 __le16 req_type; 8345 __le16 cmpl_ring; 8346 __le16 seq_id; 8347 __le16 target_id; 8348 __le64 resp_addr; 8349 __le32 install_type; 8350 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 8351 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 8352 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 8353 __le16 flags; 8354 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 8355 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 8356 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 8357 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 8358 u8 unused_0[2]; 8359 }; 8360 8361 /* hwrm_nvm_install_update_output (size:192b/24B) */ 8362 struct hwrm_nvm_install_update_output { 8363 __le16 error_code; 8364 __le16 req_type; 8365 __le16 seq_id; 8366 __le16 resp_len; 8367 __le64 installed_items; 8368 u8 result; 8369 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 8370 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 8371 u8 problem_item; 8372 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 8373 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 8374 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 8375 u8 reset_required; 8376 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 8377 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 8378 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 8379 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 8380 u8 unused_0[4]; 8381 u8 valid; 8382 }; 8383 8384 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 8385 struct hwrm_nvm_install_update_cmd_err { 8386 u8 code; 8387 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 8388 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8389 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 8390 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 8391 u8 unused_0[7]; 8392 }; 8393 8394 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 8395 struct hwrm_nvm_get_variable_input { 8396 __le16 req_type; 8397 __le16 cmpl_ring; 8398 __le16 seq_id; 8399 __le16 target_id; 8400 __le64 resp_addr; 8401 __le64 dest_data_addr; 8402 __le16 data_len; 8403 __le16 option_num; 8404 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8405 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8406 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8407 __le16 dimensions; 8408 __le16 index_0; 8409 __le16 index_1; 8410 __le16 index_2; 8411 __le16 index_3; 8412 u8 flags; 8413 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 8414 u8 unused_0; 8415 }; 8416 8417 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 8418 struct hwrm_nvm_get_variable_output { 8419 __le16 error_code; 8420 __le16 req_type; 8421 __le16 seq_id; 8422 __le16 resp_len; 8423 __le16 data_len; 8424 __le16 option_num; 8425 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 8426 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 8427 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 8428 u8 unused_0[3]; 8429 u8 valid; 8430 }; 8431 8432 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8433 struct hwrm_nvm_get_variable_cmd_err { 8434 u8 code; 8435 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8436 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8437 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8438 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8439 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8440 u8 unused_0[7]; 8441 }; 8442 8443 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8444 struct hwrm_nvm_set_variable_input { 8445 __le16 req_type; 8446 __le16 cmpl_ring; 8447 __le16 seq_id; 8448 __le16 target_id; 8449 __le64 resp_addr; 8450 __le64 src_data_addr; 8451 __le16 data_len; 8452 __le16 option_num; 8453 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8454 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8455 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8456 __le16 dimensions; 8457 __le16 index_0; 8458 __le16 index_1; 8459 __le16 index_2; 8460 __le16 index_3; 8461 u8 flags; 8462 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8463 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8464 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8465 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8466 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 8467 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 8468 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 8469 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 8470 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 8471 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 8472 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8473 u8 unused_0; 8474 }; 8475 8476 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8477 struct hwrm_nvm_set_variable_output { 8478 __le16 error_code; 8479 __le16 req_type; 8480 __le16 seq_id; 8481 __le16 resp_len; 8482 u8 unused_0[7]; 8483 u8 valid; 8484 }; 8485 8486 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8487 struct hwrm_nvm_set_variable_cmd_err { 8488 u8 code; 8489 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8490 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8491 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8492 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8493 u8 unused_0[7]; 8494 }; 8495 8496 /* hwrm_selftest_qlist_input (size:128b/16B) */ 8497 struct hwrm_selftest_qlist_input { 8498 __le16 req_type; 8499 __le16 cmpl_ring; 8500 __le16 seq_id; 8501 __le16 target_id; 8502 __le64 resp_addr; 8503 }; 8504 8505 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8506 struct hwrm_selftest_qlist_output { 8507 __le16 error_code; 8508 __le16 req_type; 8509 __le16 seq_id; 8510 __le16 resp_len; 8511 u8 num_tests; 8512 u8 available_tests; 8513 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8514 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8515 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8516 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8517 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8518 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8519 u8 offline_tests; 8520 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8521 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8522 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8523 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8524 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8525 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8526 u8 unused_0; 8527 __le16 test_timeout; 8528 u8 unused_1[2]; 8529 char test0_name[32]; 8530 char test1_name[32]; 8531 char test2_name[32]; 8532 char test3_name[32]; 8533 char test4_name[32]; 8534 char test5_name[32]; 8535 char test6_name[32]; 8536 char test7_name[32]; 8537 u8 eyescope_target_BER_support; 8538 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 8539 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 8540 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 8541 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 8542 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 8543 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 8544 u8 unused_2[6]; 8545 u8 valid; 8546 }; 8547 8548 /* hwrm_selftest_exec_input (size:192b/24B) */ 8549 struct hwrm_selftest_exec_input { 8550 __le16 req_type; 8551 __le16 cmpl_ring; 8552 __le16 seq_id; 8553 __le16 target_id; 8554 __le64 resp_addr; 8555 u8 flags; 8556 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8557 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8558 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8559 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8560 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8561 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8562 u8 unused_0[7]; 8563 }; 8564 8565 /* hwrm_selftest_exec_output (size:128b/16B) */ 8566 struct hwrm_selftest_exec_output { 8567 __le16 error_code; 8568 __le16 req_type; 8569 __le16 seq_id; 8570 __le16 resp_len; 8571 u8 requested_tests; 8572 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8573 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8574 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8575 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8576 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8577 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8578 u8 test_success; 8579 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8580 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8581 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8582 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8583 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8584 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8585 u8 unused_0[5]; 8586 u8 valid; 8587 }; 8588 8589 /* hwrm_selftest_irq_input (size:128b/16B) */ 8590 struct hwrm_selftest_irq_input { 8591 __le16 req_type; 8592 __le16 cmpl_ring; 8593 __le16 seq_id; 8594 __le16 target_id; 8595 __le64 resp_addr; 8596 }; 8597 8598 /* hwrm_selftest_irq_output (size:128b/16B) */ 8599 struct hwrm_selftest_irq_output { 8600 __le16 error_code; 8601 __le16 req_type; 8602 __le16 seq_id; 8603 __le16 resp_len; 8604 u8 unused_0[7]; 8605 u8 valid; 8606 }; 8607 8608 /* db_push_info (size:64b/8B) */ 8609 struct db_push_info { 8610 u32 push_size_push_index; 8611 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 8612 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 8613 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 8614 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 8615 u32 reserved32; 8616 }; 8617 8618 /* fw_status_reg (size:32b/4B) */ 8619 struct fw_status_reg { 8620 u32 fw_status; 8621 #define FW_STATUS_REG_CODE_MASK 0xffffUL 8622 #define FW_STATUS_REG_CODE_SFT 0 8623 #define FW_STATUS_REG_CODE_READY 0x8000UL 8624 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8625 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8626 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8627 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8628 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8629 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8630 }; 8631 8632 /* hcomm_status (size:64b/8B) */ 8633 struct hcomm_status { 8634 u32 sig_ver; 8635 #define HCOMM_STATUS_VER_MASK 0xffUL 8636 #define HCOMM_STATUS_VER_SFT 0 8637 #define HCOMM_STATUS_VER_LATEST 0x1UL 8638 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 8639 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 8640 #define HCOMM_STATUS_SIGNATURE_SFT 8 8641 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 8642 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 8643 u32 fw_status_loc; 8644 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 8645 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 8646 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 8647 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 8648 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 8649 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 8650 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 8651 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 8652 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 8653 }; 8654 8655 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 8656 8657 #endif /* _BNXT_HSI_H_ */ 8658