1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_HSI_H 12 #define BNXT_HSI_H 13 14 /* HSI and HWRM Specification 1.6.0 */ 15 #define HWRM_VERSION_MAJOR 1 16 #define HWRM_VERSION_MINOR 6 17 #define HWRM_VERSION_UPDATE 0 18 19 #define HWRM_VERSION_STR "1.6.0" 20 /* 21 * Following is the signature for HWRM message field that indicates not 22 * applicable (All F's). Need to cast it the size of the field if needed. 23 */ 24 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 25 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 26 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 27 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 28 #define HW_HASH_KEY_SIZE 40 29 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 30 31 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 32 struct eject_cmpl { 33 __le16 type; 34 #define EJECT_CMPL_TYPE_MASK 0x3fUL 35 #define EJECT_CMPL_TYPE_SFT 0 36 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 37 __le16 len; 38 __le32 opaque; 39 __le32 v; 40 #define EJECT_CMPL_V 0x1UL 41 __le32 unused_2; 42 }; 43 44 /* HWRM Completion Record (16 bytes) */ 45 struct hwrm_cmpl { 46 __le16 type; 47 #define CMPL_TYPE_MASK 0x3fUL 48 #define CMPL_TYPE_SFT 0 49 #define CMPL_TYPE_HWRM_DONE 0x20UL 50 __le16 sequence_id; 51 __le32 unused_1; 52 __le32 v; 53 #define CMPL_V 0x1UL 54 __le32 unused_3; 55 }; 56 57 /* HWRM Forwarded Request (16 bytes) */ 58 struct hwrm_fwd_req_cmpl { 59 __le16 req_len_type; 60 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 61 #define FWD_REQ_CMPL_TYPE_SFT 0 62 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 63 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 64 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 65 __le16 source_id; 66 __le32 unused_0; 67 __le32 req_buf_addr_v[2]; 68 #define FWD_REQ_CMPL_V 0x1UL 69 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 70 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 71 }; 72 73 /* HWRM Forwarded Response (16 bytes) */ 74 struct hwrm_fwd_resp_cmpl { 75 __le16 type; 76 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 77 #define FWD_RESP_CMPL_TYPE_SFT 0 78 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 79 __le16 source_id; 80 __le16 resp_len; 81 __le16 unused_1; 82 __le32 resp_buf_addr_v[2]; 83 #define FWD_RESP_CMPL_V 0x1UL 84 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 85 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 86 }; 87 88 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 89 struct hwrm_async_event_cmpl { 90 __le16 type; 91 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 92 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 93 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 94 __le16 event_id; 95 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 96 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 97 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 98 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 99 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 100 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 101 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 102 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 103 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 104 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 105 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 106 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 107 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 108 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 109 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 110 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 111 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 112 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 113 __le32 event_data2; 114 u8 opaque_v; 115 #define ASYNC_EVENT_CMPL_V 0x1UL 116 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 117 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 118 u8 timestamp_lo; 119 __le16 timestamp_hi; 120 __le32 event_data1; 121 }; 122 123 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 124 struct hwrm_async_event_cmpl_link_status_change { 125 __le16 type; 126 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 127 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 128 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 129 __le16 event_id; 130 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 131 __le32 event_data2; 132 u8 opaque_v; 133 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 134 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 135 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 136 u8 timestamp_lo; 137 __le16 timestamp_hi; 138 __le32 event_data1; 139 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 140 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 141 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 142 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 143 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 144 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 145 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 146 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 147 }; 148 149 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 150 struct hwrm_async_event_cmpl_link_mtu_change { 151 __le16 type; 152 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 153 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 154 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 155 __le16 event_id; 156 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 157 __le32 event_data2; 158 u8 opaque_v; 159 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 160 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 161 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 162 u8 timestamp_lo; 163 __le16 timestamp_hi; 164 __le32 event_data1; 165 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 166 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 167 }; 168 169 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 170 struct hwrm_async_event_cmpl_link_speed_change { 171 __le16 type; 172 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 173 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 174 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 175 __le16 event_id; 176 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 177 __le32 event_data2; 178 u8 opaque_v; 179 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 180 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 181 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 182 u8 timestamp_lo; 183 __le16 timestamp_hi; 184 __le32 event_data1; 185 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 186 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 187 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 188 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 189 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 190 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 191 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 192 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 193 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 194 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 195 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 196 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 197 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 198 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 199 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 200 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 201 }; 202 203 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 204 struct hwrm_async_event_cmpl_dcb_config_change { 205 __le16 type; 206 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 207 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 208 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 209 __le16 event_id; 210 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 211 __le32 event_data2; 212 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 213 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 214 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 215 u8 opaque_v; 216 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 217 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 218 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 219 u8 timestamp_lo; 220 __le16 timestamp_hi; 221 __le32 event_data1; 222 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 223 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 224 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 225 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 226 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 227 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 228 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 229 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 230 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 231 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 232 }; 233 234 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 235 struct hwrm_async_event_cmpl_port_conn_not_allowed { 236 __le16 type; 237 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 238 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 239 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 240 __le16 event_id; 241 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 242 __le32 event_data2; 243 u8 opaque_v; 244 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 245 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 246 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 247 u8 timestamp_lo; 248 __le16 timestamp_hi; 249 __le32 event_data1; 250 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 251 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 252 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 253 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 254 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 255 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 256 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 257 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 258 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 259 }; 260 261 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 262 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 263 __le16 type; 264 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 265 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 266 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 267 __le16 event_id; 268 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 269 __le32 event_data2; 270 u8 opaque_v; 271 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 272 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 273 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 274 u8 timestamp_lo; 275 __le16 timestamp_hi; 276 __le32 event_data1; 277 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 278 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 279 }; 280 281 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 282 struct hwrm_async_event_cmpl_link_speed_cfg_change { 283 __le16 type; 284 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 285 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 286 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 287 __le16 event_id; 288 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 289 __le32 event_data2; 290 u8 opaque_v; 291 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 292 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 293 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 294 u8 timestamp_lo; 295 __le16 timestamp_hi; 296 __le32 event_data1; 297 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 298 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 299 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 300 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 301 }; 302 303 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 304 struct hwrm_async_event_cmpl_func_drvr_unload { 305 __le16 type; 306 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 307 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 308 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 309 __le16 event_id; 310 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 311 __le32 event_data2; 312 u8 opaque_v; 313 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 314 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 315 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 316 u8 timestamp_lo; 317 __le16 timestamp_hi; 318 __le32 event_data1; 319 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 320 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 321 }; 322 323 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 324 struct hwrm_async_event_cmpl_func_drvr_load { 325 __le16 type; 326 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 327 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 328 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 329 __le16 event_id; 330 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 331 __le32 event_data2; 332 u8 opaque_v; 333 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 334 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 335 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 336 u8 timestamp_lo; 337 __le16 timestamp_hi; 338 __le32 event_data1; 339 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 340 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 341 }; 342 343 /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ 344 struct hwrm_async_event_cmpl_func_flr_proc_cmplt { 345 __le16 type; 346 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL 347 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 348 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 349 __le16 event_id; 350 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 351 __le32 event_data2; 352 u8 opaque_v; 353 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL 354 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL 355 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 356 u8 timestamp_lo; 357 __le16 timestamp_hi; 358 __le32 event_data1; 359 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 360 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 361 }; 362 363 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 364 struct hwrm_async_event_cmpl_pf_drvr_unload { 365 __le16 type; 366 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 367 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 368 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 369 __le16 event_id; 370 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 371 __le32 event_data2; 372 u8 opaque_v; 373 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 374 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 375 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 376 u8 timestamp_lo; 377 __le16 timestamp_hi; 378 __le32 event_data1; 379 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 380 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 381 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 382 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 383 }; 384 385 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 386 struct hwrm_async_event_cmpl_pf_drvr_load { 387 __le16 type; 388 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 389 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 390 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 391 __le16 event_id; 392 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 393 __le32 event_data2; 394 u8 opaque_v; 395 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 396 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 397 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 398 u8 timestamp_lo; 399 __le16 timestamp_hi; 400 __le32 event_data1; 401 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 402 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 403 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 404 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 405 }; 406 407 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 408 struct hwrm_async_event_cmpl_vf_flr { 409 __le16 type; 410 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 411 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 412 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 413 __le16 event_id; 414 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 415 __le32 event_data2; 416 u8 opaque_v; 417 #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 418 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 419 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 420 u8 timestamp_lo; 421 __le16 timestamp_hi; 422 __le32 event_data1; 423 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 424 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 425 }; 426 427 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 428 struct hwrm_async_event_cmpl_vf_mac_addr_change { 429 __le16 type; 430 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 431 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 432 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 433 __le16 event_id; 434 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 435 __le32 event_data2; 436 u8 opaque_v; 437 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 438 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 439 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 440 u8 timestamp_lo; 441 __le16 timestamp_hi; 442 __le32 event_data1; 443 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 444 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 445 }; 446 447 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 448 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 449 __le16 type; 450 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 451 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 452 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 453 __le16 event_id; 454 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 455 __le32 event_data2; 456 u8 opaque_v; 457 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 458 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 459 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 460 u8 timestamp_lo; 461 __le16 timestamp_hi; 462 __le32 event_data1; 463 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 464 }; 465 466 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 467 struct hwrm_async_event_cmpl_vf_cfg_change { 468 __le16 type; 469 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 470 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 471 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 472 __le16 event_id; 473 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 474 __le32 event_data2; 475 u8 opaque_v; 476 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 477 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 478 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 479 u8 timestamp_lo; 480 __le16 timestamp_hi; 481 __le32 event_data1; 482 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 483 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 484 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 485 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 486 }; 487 488 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 489 struct hwrm_async_event_cmpl_hwrm_error { 490 __le16 type; 491 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 492 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 493 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 494 __le16 event_id; 495 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 496 __le32 event_data2; 497 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 498 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 499 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 500 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 501 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 502 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 503 u8 opaque_v; 504 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 505 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 506 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 507 u8 timestamp_lo; 508 __le16 timestamp_hi; 509 __le32 event_data1; 510 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 511 }; 512 513 /* hwrm_ver_get */ 514 /* Input (24 bytes) */ 515 struct hwrm_ver_get_input { 516 __le16 req_type; 517 __le16 cmpl_ring; 518 __le16 seq_id; 519 __le16 target_id; 520 __le64 resp_addr; 521 u8 hwrm_intf_maj; 522 u8 hwrm_intf_min; 523 u8 hwrm_intf_upd; 524 u8 unused_0[5]; 525 }; 526 527 /* Output (128 bytes) */ 528 struct hwrm_ver_get_output { 529 __le16 error_code; 530 __le16 req_type; 531 __le16 seq_id; 532 __le16 resp_len; 533 u8 hwrm_intf_maj; 534 u8 hwrm_intf_min; 535 u8 hwrm_intf_upd; 536 u8 hwrm_intf_rsvd; 537 u8 hwrm_fw_maj; 538 u8 hwrm_fw_min; 539 u8 hwrm_fw_bld; 540 u8 hwrm_fw_rsvd; 541 u8 mgmt_fw_maj; 542 u8 mgmt_fw_min; 543 u8 mgmt_fw_bld; 544 u8 mgmt_fw_rsvd; 545 u8 netctrl_fw_maj; 546 u8 netctrl_fw_min; 547 u8 netctrl_fw_bld; 548 u8 netctrl_fw_rsvd; 549 __le32 dev_caps_cfg; 550 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 551 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 552 u8 roce_fw_maj; 553 u8 roce_fw_min; 554 u8 roce_fw_bld; 555 u8 roce_fw_rsvd; 556 char hwrm_fw_name[16]; 557 char mgmt_fw_name[16]; 558 char netctrl_fw_name[16]; 559 __le32 reserved2[4]; 560 char roce_fw_name[16]; 561 __le16 chip_num; 562 u8 chip_rev; 563 u8 chip_metal; 564 u8 chip_bond_id; 565 u8 chip_platform_type; 566 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 567 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 568 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 569 __le16 max_req_win_len; 570 __le16 max_resp_len; 571 __le16 def_req_timeout; 572 u8 unused_0; 573 u8 unused_1; 574 u8 unused_2; 575 u8 valid; 576 }; 577 578 /* hwrm_func_reset */ 579 /* Input (24 bytes) */ 580 struct hwrm_func_reset_input { 581 __le16 req_type; 582 __le16 cmpl_ring; 583 __le16 seq_id; 584 __le16 target_id; 585 __le64 resp_addr; 586 __le32 enables; 587 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 588 __le16 vf_id; 589 u8 func_reset_level; 590 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 591 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 592 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 593 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 594 u8 unused_0; 595 }; 596 597 /* Output (16 bytes) */ 598 struct hwrm_func_reset_output { 599 __le16 error_code; 600 __le16 req_type; 601 __le16 seq_id; 602 __le16 resp_len; 603 __le32 unused_0; 604 u8 unused_1; 605 u8 unused_2; 606 u8 unused_3; 607 u8 valid; 608 }; 609 610 /* hwrm_func_getfid */ 611 /* Input (24 bytes) */ 612 struct hwrm_func_getfid_input { 613 __le16 req_type; 614 __le16 cmpl_ring; 615 __le16 seq_id; 616 __le16 target_id; 617 __le64 resp_addr; 618 __le32 enables; 619 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 620 __le16 pci_id; 621 __le16 unused_0; 622 }; 623 624 /* Output (16 bytes) */ 625 struct hwrm_func_getfid_output { 626 __le16 error_code; 627 __le16 req_type; 628 __le16 seq_id; 629 __le16 resp_len; 630 __le16 fid; 631 u8 unused_0; 632 u8 unused_1; 633 u8 unused_2; 634 u8 unused_3; 635 u8 unused_4; 636 u8 valid; 637 }; 638 639 /* hwrm_func_vf_alloc */ 640 /* Input (24 bytes) */ 641 struct hwrm_func_vf_alloc_input { 642 __le16 req_type; 643 __le16 cmpl_ring; 644 __le16 seq_id; 645 __le16 target_id; 646 __le64 resp_addr; 647 __le32 enables; 648 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 649 __le16 first_vf_id; 650 __le16 num_vfs; 651 }; 652 653 /* Output (16 bytes) */ 654 struct hwrm_func_vf_alloc_output { 655 __le16 error_code; 656 __le16 req_type; 657 __le16 seq_id; 658 __le16 resp_len; 659 __le16 first_vf_id; 660 u8 unused_0; 661 u8 unused_1; 662 u8 unused_2; 663 u8 unused_3; 664 u8 unused_4; 665 u8 valid; 666 }; 667 668 /* hwrm_func_vf_free */ 669 /* Input (24 bytes) */ 670 struct hwrm_func_vf_free_input { 671 __le16 req_type; 672 __le16 cmpl_ring; 673 __le16 seq_id; 674 __le16 target_id; 675 __le64 resp_addr; 676 __le32 enables; 677 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 678 __le16 first_vf_id; 679 __le16 num_vfs; 680 }; 681 682 /* Output (16 bytes) */ 683 struct hwrm_func_vf_free_output { 684 __le16 error_code; 685 __le16 req_type; 686 __le16 seq_id; 687 __le16 resp_len; 688 __le32 unused_0; 689 u8 unused_1; 690 u8 unused_2; 691 u8 unused_3; 692 u8 valid; 693 }; 694 695 /* hwrm_func_vf_cfg */ 696 /* Input (32 bytes) */ 697 struct hwrm_func_vf_cfg_input { 698 __le16 req_type; 699 __le16 cmpl_ring; 700 __le16 seq_id; 701 __le16 target_id; 702 __le64 resp_addr; 703 __le32 enables; 704 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 705 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 706 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 707 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 708 __le16 mtu; 709 __le16 guest_vlan; 710 __le16 async_event_cr; 711 u8 dflt_mac_addr[6]; 712 }; 713 714 /* Output (16 bytes) */ 715 struct hwrm_func_vf_cfg_output { 716 __le16 error_code; 717 __le16 req_type; 718 __le16 seq_id; 719 __le16 resp_len; 720 __le32 unused_0; 721 u8 unused_1; 722 u8 unused_2; 723 u8 unused_3; 724 u8 valid; 725 }; 726 727 /* hwrm_func_qcaps */ 728 /* Input (24 bytes) */ 729 struct hwrm_func_qcaps_input { 730 __le16 req_type; 731 __le16 cmpl_ring; 732 __le16 seq_id; 733 __le16 target_id; 734 __le64 resp_addr; 735 __le16 fid; 736 __le16 unused_0[3]; 737 }; 738 739 /* Output (80 bytes) */ 740 struct hwrm_func_qcaps_output { 741 __le16 error_code; 742 __le16 req_type; 743 __le16 seq_id; 744 __le16 resp_len; 745 __le16 fid; 746 __le16 port_id; 747 __le32 flags; 748 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 749 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 750 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 751 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 752 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 753 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 754 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 755 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 756 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 757 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 758 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 759 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 760 u8 mac_address[6]; 761 __le16 max_rsscos_ctx; 762 __le16 max_cmpl_rings; 763 __le16 max_tx_rings; 764 __le16 max_rx_rings; 765 __le16 max_l2_ctxs; 766 __le16 max_vnics; 767 __le16 first_vf_id; 768 __le16 max_vfs; 769 __le16 max_stat_ctx; 770 __le32 max_encap_records; 771 __le32 max_decap_records; 772 __le32 max_tx_em_flows; 773 __le32 max_tx_wm_flows; 774 __le32 max_rx_em_flows; 775 __le32 max_rx_wm_flows; 776 __le32 max_mcast_filters; 777 __le32 max_flow_id; 778 __le32 max_hw_ring_grps; 779 __le16 max_sp_tx_rings; 780 u8 unused_0; 781 u8 valid; 782 }; 783 784 /* hwrm_func_qcfg */ 785 /* Input (24 bytes) */ 786 struct hwrm_func_qcfg_input { 787 __le16 req_type; 788 __le16 cmpl_ring; 789 __le16 seq_id; 790 __le16 target_id; 791 __le64 resp_addr; 792 __le16 fid; 793 __le16 unused_0[3]; 794 }; 795 796 /* Output (72 bytes) */ 797 struct hwrm_func_qcfg_output { 798 __le16 error_code; 799 __le16 req_type; 800 __le16 seq_id; 801 __le16 resp_len; 802 __le16 fid; 803 __le16 port_id; 804 __le16 vlan; 805 __le16 flags; 806 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 807 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 808 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 809 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 810 u8 mac_address[6]; 811 __le16 pci_id; 812 __le16 alloc_rsscos_ctx; 813 __le16 alloc_cmpl_rings; 814 __le16 alloc_tx_rings; 815 __le16 alloc_rx_rings; 816 __le16 alloc_l2_ctx; 817 __le16 alloc_vnics; 818 __le16 mtu; 819 __le16 mru; 820 __le16 stat_ctx_id; 821 u8 port_partition_type; 822 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 823 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 824 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 825 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 826 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 827 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 828 u8 unused_0; 829 __le16 dflt_vnic_id; 830 u8 unused_1; 831 u8 unused_2; 832 __le32 min_bw; 833 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 834 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 835 #define FUNC_QCFG_RESP_MIN_BW_RSVD 0x10000000UL 836 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 837 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 838 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 839 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 840 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 841 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 842 __le32 max_bw; 843 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 844 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 845 #define FUNC_QCFG_RESP_MAX_BW_RSVD 0x10000000UL 846 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 847 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 848 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 849 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 850 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 851 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 852 u8 evb_mode; 853 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 854 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 855 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 856 u8 unused_3; 857 __le16 alloc_vfs; 858 __le32 alloc_mcast_filters; 859 __le32 alloc_hw_ring_grps; 860 __le16 alloc_sp_tx_rings; 861 u8 unused_4; 862 u8 valid; 863 }; 864 865 /* hwrm_func_cfg */ 866 /* Input (88 bytes) */ 867 struct hwrm_func_cfg_input { 868 __le16 req_type; 869 __le16 cmpl_ring; 870 __le16 seq_id; 871 __le16 target_id; 872 __le64 resp_addr; 873 __le16 fid; 874 u8 unused_0; 875 u8 unused_1; 876 __le32 flags; 877 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 878 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 879 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 880 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 881 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 882 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 883 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 884 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 885 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 886 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE 0x200UL 887 __le32 enables; 888 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 889 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 890 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 891 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 892 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 893 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 894 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 895 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 896 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 897 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 898 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 899 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 900 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 901 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 902 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 903 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 904 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 905 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 906 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 907 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 908 __le16 mtu; 909 __le16 mru; 910 __le16 num_rsscos_ctxs; 911 __le16 num_cmpl_rings; 912 __le16 num_tx_rings; 913 __le16 num_rx_rings; 914 __le16 num_l2_ctxs; 915 __le16 num_vnics; 916 __le16 num_stat_ctxs; 917 __le16 num_hw_ring_grps; 918 u8 dflt_mac_addr[6]; 919 __le16 dflt_vlan; 920 __be32 dflt_ip_addr[4]; 921 __le32 min_bw; 922 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 923 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 924 #define FUNC_CFG_REQ_MIN_BW_RSVD 0x10000000UL 925 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 926 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 927 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 928 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 929 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 930 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 931 __le32 max_bw; 932 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 933 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 934 #define FUNC_CFG_REQ_MAX_BW_RSVD 0x10000000UL 935 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 936 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 937 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 938 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 939 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 940 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 941 __le16 async_event_cr; 942 u8 vlan_antispoof_mode; 943 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 944 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 945 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 946 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 947 u8 allowed_vlan_pris; 948 u8 evb_mode; 949 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 950 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 951 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 952 u8 unused_2; 953 __le16 num_mcast_filters; 954 }; 955 956 /* Output (16 bytes) */ 957 struct hwrm_func_cfg_output { 958 __le16 error_code; 959 __le16 req_type; 960 __le16 seq_id; 961 __le16 resp_len; 962 __le32 unused_0; 963 u8 unused_1; 964 u8 unused_2; 965 u8 unused_3; 966 u8 valid; 967 }; 968 969 /* hwrm_func_qstats */ 970 /* Input (24 bytes) */ 971 struct hwrm_func_qstats_input { 972 __le16 req_type; 973 __le16 cmpl_ring; 974 __le16 seq_id; 975 __le16 target_id; 976 __le64 resp_addr; 977 __le16 fid; 978 __le16 unused_0[3]; 979 }; 980 981 /* Output (176 bytes) */ 982 struct hwrm_func_qstats_output { 983 __le16 error_code; 984 __le16 req_type; 985 __le16 seq_id; 986 __le16 resp_len; 987 __le64 tx_ucast_pkts; 988 __le64 tx_mcast_pkts; 989 __le64 tx_bcast_pkts; 990 __le64 tx_err_pkts; 991 __le64 tx_drop_pkts; 992 __le64 tx_ucast_bytes; 993 __le64 tx_mcast_bytes; 994 __le64 tx_bcast_bytes; 995 __le64 rx_ucast_pkts; 996 __le64 rx_mcast_pkts; 997 __le64 rx_bcast_pkts; 998 __le64 rx_err_pkts; 999 __le64 rx_drop_pkts; 1000 __le64 rx_ucast_bytes; 1001 __le64 rx_mcast_bytes; 1002 __le64 rx_bcast_bytes; 1003 __le64 rx_agg_pkts; 1004 __le64 rx_agg_bytes; 1005 __le64 rx_agg_events; 1006 __le64 rx_agg_aborts; 1007 __le32 unused_0; 1008 u8 unused_1; 1009 u8 unused_2; 1010 u8 unused_3; 1011 u8 valid; 1012 }; 1013 1014 /* hwrm_func_clr_stats */ 1015 /* Input (24 bytes) */ 1016 struct hwrm_func_clr_stats_input { 1017 __le16 req_type; 1018 __le16 cmpl_ring; 1019 __le16 seq_id; 1020 __le16 target_id; 1021 __le64 resp_addr; 1022 __le16 fid; 1023 __le16 unused_0[3]; 1024 }; 1025 1026 /* Output (16 bytes) */ 1027 struct hwrm_func_clr_stats_output { 1028 __le16 error_code; 1029 __le16 req_type; 1030 __le16 seq_id; 1031 __le16 resp_len; 1032 __le32 unused_0; 1033 u8 unused_1; 1034 u8 unused_2; 1035 u8 unused_3; 1036 u8 valid; 1037 }; 1038 1039 /* hwrm_func_vf_resc_free */ 1040 /* Input (24 bytes) */ 1041 struct hwrm_func_vf_resc_free_input { 1042 __le16 req_type; 1043 __le16 cmpl_ring; 1044 __le16 seq_id; 1045 __le16 target_id; 1046 __le64 resp_addr; 1047 __le16 vf_id; 1048 __le16 unused_0[3]; 1049 }; 1050 1051 /* Output (16 bytes) */ 1052 struct hwrm_func_vf_resc_free_output { 1053 __le16 error_code; 1054 __le16 req_type; 1055 __le16 seq_id; 1056 __le16 resp_len; 1057 __le32 unused_0; 1058 u8 unused_1; 1059 u8 unused_2; 1060 u8 unused_3; 1061 u8 valid; 1062 }; 1063 1064 /* hwrm_func_vf_vnic_ids_query */ 1065 /* Input (32 bytes) */ 1066 struct hwrm_func_vf_vnic_ids_query_input { 1067 __le16 req_type; 1068 __le16 cmpl_ring; 1069 __le16 seq_id; 1070 __le16 target_id; 1071 __le64 resp_addr; 1072 __le16 vf_id; 1073 u8 unused_0; 1074 u8 unused_1; 1075 __le32 max_vnic_id_cnt; 1076 __le64 vnic_id_tbl_addr; 1077 }; 1078 1079 /* Output (16 bytes) */ 1080 struct hwrm_func_vf_vnic_ids_query_output { 1081 __le16 error_code; 1082 __le16 req_type; 1083 __le16 seq_id; 1084 __le16 resp_len; 1085 __le32 vnic_id_cnt; 1086 u8 unused_0; 1087 u8 unused_1; 1088 u8 unused_2; 1089 u8 valid; 1090 }; 1091 1092 /* hwrm_func_drv_rgtr */ 1093 /* Input (80 bytes) */ 1094 struct hwrm_func_drv_rgtr_input { 1095 __le16 req_type; 1096 __le16 cmpl_ring; 1097 __le16 seq_id; 1098 __le16 target_id; 1099 __le64 resp_addr; 1100 __le32 flags; 1101 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1102 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1103 __le32 enables; 1104 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1105 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1106 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1107 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1108 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1109 __le16 os_type; 1110 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1111 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1112 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1113 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1114 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1115 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1116 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1117 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1118 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1119 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1120 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1121 u8 ver_maj; 1122 u8 ver_min; 1123 u8 ver_upd; 1124 u8 unused_0; 1125 __le16 unused_1; 1126 __le32 timestamp; 1127 __le32 unused_2; 1128 __le32 vf_req_fwd[8]; 1129 __le32 async_event_fwd[8]; 1130 }; 1131 1132 /* Output (16 bytes) */ 1133 struct hwrm_func_drv_rgtr_output { 1134 __le16 error_code; 1135 __le16 req_type; 1136 __le16 seq_id; 1137 __le16 resp_len; 1138 __le32 unused_0; 1139 u8 unused_1; 1140 u8 unused_2; 1141 u8 unused_3; 1142 u8 valid; 1143 }; 1144 1145 /* hwrm_func_drv_unrgtr */ 1146 /* Input (24 bytes) */ 1147 struct hwrm_func_drv_unrgtr_input { 1148 __le16 req_type; 1149 __le16 cmpl_ring; 1150 __le16 seq_id; 1151 __le16 target_id; 1152 __le64 resp_addr; 1153 __le32 flags; 1154 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1155 __le32 unused_0; 1156 }; 1157 1158 /* Output (16 bytes) */ 1159 struct hwrm_func_drv_unrgtr_output { 1160 __le16 error_code; 1161 __le16 req_type; 1162 __le16 seq_id; 1163 __le16 resp_len; 1164 __le32 unused_0; 1165 u8 unused_1; 1166 u8 unused_2; 1167 u8 unused_3; 1168 u8 valid; 1169 }; 1170 1171 /* hwrm_func_buf_rgtr */ 1172 /* Input (128 bytes) */ 1173 struct hwrm_func_buf_rgtr_input { 1174 __le16 req_type; 1175 __le16 cmpl_ring; 1176 __le16 seq_id; 1177 __le16 target_id; 1178 __le64 resp_addr; 1179 __le32 enables; 1180 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1181 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1182 __le16 vf_id; 1183 __le16 req_buf_num_pages; 1184 __le16 req_buf_page_size; 1185 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1186 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1187 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1188 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1189 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1190 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1191 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1192 __le16 req_buf_len; 1193 __le16 resp_buf_len; 1194 u8 unused_0; 1195 u8 unused_1; 1196 __le64 req_buf_page_addr0; 1197 __le64 req_buf_page_addr1; 1198 __le64 req_buf_page_addr2; 1199 __le64 req_buf_page_addr3; 1200 __le64 req_buf_page_addr4; 1201 __le64 req_buf_page_addr5; 1202 __le64 req_buf_page_addr6; 1203 __le64 req_buf_page_addr7; 1204 __le64 req_buf_page_addr8; 1205 __le64 req_buf_page_addr9; 1206 __le64 error_buf_addr; 1207 __le64 resp_buf_addr; 1208 }; 1209 1210 /* Output (16 bytes) */ 1211 struct hwrm_func_buf_rgtr_output { 1212 __le16 error_code; 1213 __le16 req_type; 1214 __le16 seq_id; 1215 __le16 resp_len; 1216 __le32 unused_0; 1217 u8 unused_1; 1218 u8 unused_2; 1219 u8 unused_3; 1220 u8 valid; 1221 }; 1222 1223 /* hwrm_func_drv_qver */ 1224 /* Input (24 bytes) */ 1225 struct hwrm_func_drv_qver_input { 1226 __le16 req_type; 1227 __le16 cmpl_ring; 1228 __le16 seq_id; 1229 __le16 target_id; 1230 __le64 resp_addr; 1231 __le32 reserved; 1232 __le16 fid; 1233 __le16 unused_0; 1234 }; 1235 1236 /* Output (16 bytes) */ 1237 struct hwrm_func_drv_qver_output { 1238 __le16 error_code; 1239 __le16 req_type; 1240 __le16 seq_id; 1241 __le16 resp_len; 1242 __le16 os_type; 1243 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1244 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1245 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1246 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1247 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1248 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1249 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1250 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1251 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1252 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1253 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1254 u8 ver_maj; 1255 u8 ver_min; 1256 u8 ver_upd; 1257 u8 unused_0; 1258 u8 unused_1; 1259 u8 valid; 1260 }; 1261 1262 /* hwrm_port_phy_cfg */ 1263 /* Input (56 bytes) */ 1264 struct hwrm_port_phy_cfg_input { 1265 __le16 req_type; 1266 __le16 cmpl_ring; 1267 __le16 seq_id; 1268 __le16 target_id; 1269 __le64 resp_addr; 1270 __le32 flags; 1271 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1272 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1273 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1274 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1275 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1276 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1277 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1278 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1279 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1280 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1281 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1282 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1283 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1284 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1285 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1286 __le32 enables; 1287 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1288 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1289 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1290 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1291 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1292 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1293 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1294 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1295 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1296 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1297 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1298 __le16 port_id; 1299 __le16 force_link_speed; 1300 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1301 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1302 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1303 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1304 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1305 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1306 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1307 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1308 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1309 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1310 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1311 u8 auto_mode; 1312 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1313 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1314 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1315 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1316 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1317 u8 auto_duplex; 1318 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1319 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1320 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1321 u8 auto_pause; 1322 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1323 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1324 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1325 u8 unused_0; 1326 __le16 auto_link_speed; 1327 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1328 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1329 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1330 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1331 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1332 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1333 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1334 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1335 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1336 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1337 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1338 __le16 auto_link_speed_mask; 1339 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1340 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1341 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1342 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1343 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1344 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1345 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1346 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1347 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1348 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1349 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1350 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1351 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1352 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1353 u8 wirespeed; 1354 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1355 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1356 u8 lpbk; 1357 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1358 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1359 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1360 u8 force_pause; 1361 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1362 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1363 u8 unused_1; 1364 __le32 preemphasis; 1365 __le16 eee_link_speed_mask; 1366 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1367 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1368 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1369 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1370 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1371 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1372 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1373 u8 unused_2; 1374 u8 unused_3; 1375 __le32 tx_lpi_timer; 1376 __le32 unused_4; 1377 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1378 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1379 }; 1380 1381 /* Output (16 bytes) */ 1382 struct hwrm_port_phy_cfg_output { 1383 __le16 error_code; 1384 __le16 req_type; 1385 __le16 seq_id; 1386 __le16 resp_len; 1387 __le32 unused_0; 1388 u8 unused_1; 1389 u8 unused_2; 1390 u8 unused_3; 1391 u8 valid; 1392 }; 1393 1394 /* hwrm_port_phy_qcfg */ 1395 /* Input (24 bytes) */ 1396 struct hwrm_port_phy_qcfg_input { 1397 __le16 req_type; 1398 __le16 cmpl_ring; 1399 __le16 seq_id; 1400 __le16 target_id; 1401 __le64 resp_addr; 1402 __le16 port_id; 1403 __le16 unused_0[3]; 1404 }; 1405 1406 /* Output (96 bytes) */ 1407 struct hwrm_port_phy_qcfg_output { 1408 __le16 error_code; 1409 __le16 req_type; 1410 __le16 seq_id; 1411 __le16 resp_len; 1412 u8 link; 1413 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1414 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1415 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1416 u8 unused_0; 1417 __le16 link_speed; 1418 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1419 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1420 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1421 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1422 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1423 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1424 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1425 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1426 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1427 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1428 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1429 u8 duplex; 1430 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF 0x0UL 1431 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL 0x1UL 1432 u8 pause; 1433 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1434 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1435 __le16 support_speeds; 1436 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1437 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1438 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1439 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1440 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1441 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1442 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1443 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1444 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1445 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1446 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1447 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1448 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1449 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1450 __le16 force_link_speed; 1451 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1452 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1453 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1454 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1455 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1456 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1457 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1458 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1459 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1460 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1461 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1462 u8 auto_mode; 1463 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1464 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1465 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1466 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1467 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1468 u8 auto_pause; 1469 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1470 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1471 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1472 __le16 auto_link_speed; 1473 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1474 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1475 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1476 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1477 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1478 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1479 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1480 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1481 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1482 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1483 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1484 __le16 auto_link_speed_mask; 1485 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1486 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1487 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1488 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1489 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1490 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1491 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1492 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1493 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1494 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1495 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1496 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1497 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1498 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1499 u8 wirespeed; 1500 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1501 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1502 u8 lpbk; 1503 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1504 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1505 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1506 u8 force_pause; 1507 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1508 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1509 u8 module_status; 1510 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1511 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1512 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1513 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1514 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1515 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1516 __le32 preemphasis; 1517 u8 phy_maj; 1518 u8 phy_min; 1519 u8 phy_bld; 1520 u8 phy_type; 1521 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1522 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1523 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1524 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1525 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1526 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1527 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1528 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1529 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1530 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1531 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1532 u8 media_type; 1533 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1534 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1535 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1536 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1537 u8 xcvr_pkg_type; 1538 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1539 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1540 u8 eee_config_phy_addr; 1541 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1542 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1543 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1544 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1545 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1546 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1547 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1548 u8 parallel_detect; 1549 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1550 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1551 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1552 __le16 link_partner_adv_speeds; 1553 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1554 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1555 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1556 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1557 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1558 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1559 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1560 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1561 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1562 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1563 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1564 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1565 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1566 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1567 u8 link_partner_adv_auto_mode; 1568 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1569 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1570 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1571 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1572 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1573 u8 link_partner_adv_pause; 1574 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1575 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1576 __le16 adv_eee_link_speed_mask; 1577 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1578 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1579 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1580 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1581 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1582 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1583 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1584 __le16 link_partner_adv_eee_link_speed_mask; 1585 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1586 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1587 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1588 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1589 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1590 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1591 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1592 __le32 xcvr_identifier_type_tx_lpi_timer; 1593 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1594 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1595 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1596 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1597 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1598 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1599 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1600 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1601 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1602 __le16 fec_cfg; 1603 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1604 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1605 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1606 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1607 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1608 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1609 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1610 u8 unused_1; 1611 u8 unused_2; 1612 char phy_vendor_name[16]; 1613 char phy_vendor_partnumber[16]; 1614 __le32 unused_3; 1615 u8 unused_4; 1616 u8 unused_5; 1617 u8 unused_6; 1618 u8 valid; 1619 }; 1620 1621 /* hwrm_port_mac_cfg */ 1622 /* Input (40 bytes) */ 1623 struct hwrm_port_mac_cfg_input { 1624 __le16 req_type; 1625 __le16 cmpl_ring; 1626 __le16 seq_id; 1627 __le16 target_id; 1628 __le64 resp_addr; 1629 __le32 flags; 1630 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1631 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1632 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1633 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1634 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1635 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1636 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1637 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1638 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1639 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1640 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1641 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1642 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1643 __le32 enables; 1644 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1645 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1646 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1647 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1648 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1649 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1650 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1651 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1652 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1653 __le16 port_id; 1654 u8 ipg; 1655 u8 lpbk; 1656 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1657 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1658 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1659 u8 vlan_pri2cos_map_pri; 1660 u8 reserved1; 1661 u8 tunnel_pri2cos_map_pri; 1662 u8 dscp2pri_map_pri; 1663 __le16 rx_ts_capture_ptp_msg_type; 1664 __le16 tx_ts_capture_ptp_msg_type; 1665 u8 cos_field_cfg; 1666 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1667 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1668 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1669 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1670 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1671 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1672 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1673 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1674 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1675 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1676 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1677 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1678 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1679 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1680 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1681 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1682 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1683 u8 unused_0[3]; 1684 }; 1685 1686 /* Output (16 bytes) */ 1687 struct hwrm_port_mac_cfg_output { 1688 __le16 error_code; 1689 __le16 req_type; 1690 __le16 seq_id; 1691 __le16 resp_len; 1692 __le16 mru; 1693 __le16 mtu; 1694 u8 ipg; 1695 u8 lpbk; 1696 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1697 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1698 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1699 u8 unused_0; 1700 u8 valid; 1701 }; 1702 1703 /* hwrm_port_qstats */ 1704 /* Input (40 bytes) */ 1705 struct hwrm_port_qstats_input { 1706 __le16 req_type; 1707 __le16 cmpl_ring; 1708 __le16 seq_id; 1709 __le16 target_id; 1710 __le64 resp_addr; 1711 __le16 port_id; 1712 u8 unused_0; 1713 u8 unused_1; 1714 u8 unused_2[3]; 1715 u8 unused_3; 1716 __le64 tx_stat_host_addr; 1717 __le64 rx_stat_host_addr; 1718 }; 1719 1720 /* Output (16 bytes) */ 1721 struct hwrm_port_qstats_output { 1722 __le16 error_code; 1723 __le16 req_type; 1724 __le16 seq_id; 1725 __le16 resp_len; 1726 __le16 tx_stat_size; 1727 __le16 rx_stat_size; 1728 u8 unused_0; 1729 u8 unused_1; 1730 u8 unused_2; 1731 u8 valid; 1732 }; 1733 1734 /* hwrm_port_lpbk_qstats */ 1735 /* Input (16 bytes) */ 1736 struct hwrm_port_lpbk_qstats_input { 1737 __le16 req_type; 1738 __le16 cmpl_ring; 1739 __le16 seq_id; 1740 __le16 target_id; 1741 __le64 resp_addr; 1742 }; 1743 1744 /* Output (96 bytes) */ 1745 struct hwrm_port_lpbk_qstats_output { 1746 __le16 error_code; 1747 __le16 req_type; 1748 __le16 seq_id; 1749 __le16 resp_len; 1750 __le64 lpbk_ucast_frames; 1751 __le64 lpbk_mcast_frames; 1752 __le64 lpbk_bcast_frames; 1753 __le64 lpbk_ucast_bytes; 1754 __le64 lpbk_mcast_bytes; 1755 __le64 lpbk_bcast_bytes; 1756 __le64 tx_stat_discard; 1757 __le64 tx_stat_error; 1758 __le64 rx_stat_discard; 1759 __le64 rx_stat_error; 1760 __le32 unused_0; 1761 u8 unused_1; 1762 u8 unused_2; 1763 u8 unused_3; 1764 u8 valid; 1765 }; 1766 1767 /* hwrm_port_clr_stats */ 1768 /* Input (24 bytes) */ 1769 struct hwrm_port_clr_stats_input { 1770 __le16 req_type; 1771 __le16 cmpl_ring; 1772 __le16 seq_id; 1773 __le16 target_id; 1774 __le64 resp_addr; 1775 __le16 port_id; 1776 __le16 unused_0[3]; 1777 }; 1778 1779 /* Output (16 bytes) */ 1780 struct hwrm_port_clr_stats_output { 1781 __le16 error_code; 1782 __le16 req_type; 1783 __le16 seq_id; 1784 __le16 resp_len; 1785 __le32 unused_0; 1786 u8 unused_1; 1787 u8 unused_2; 1788 u8 unused_3; 1789 u8 valid; 1790 }; 1791 1792 /* hwrm_port_lpbk_clr_stats */ 1793 /* Input (16 bytes) */ 1794 struct hwrm_port_lpbk_clr_stats_input { 1795 __le16 req_type; 1796 __le16 cmpl_ring; 1797 __le16 seq_id; 1798 __le16 target_id; 1799 __le64 resp_addr; 1800 }; 1801 1802 /* Output (16 bytes) */ 1803 struct hwrm_port_lpbk_clr_stats_output { 1804 __le16 error_code; 1805 __le16 req_type; 1806 __le16 seq_id; 1807 __le16 resp_len; 1808 __le32 unused_0; 1809 u8 unused_1; 1810 u8 unused_2; 1811 u8 unused_3; 1812 u8 valid; 1813 }; 1814 1815 /* hwrm_port_phy_qcaps */ 1816 /* Input (24 bytes) */ 1817 struct hwrm_port_phy_qcaps_input { 1818 __le16 req_type; 1819 __le16 cmpl_ring; 1820 __le16 seq_id; 1821 __le16 target_id; 1822 __le64 resp_addr; 1823 __le16 port_id; 1824 __le16 unused_0[3]; 1825 }; 1826 1827 /* Output (24 bytes) */ 1828 struct hwrm_port_phy_qcaps_output { 1829 __le16 error_code; 1830 __le16 req_type; 1831 __le16 seq_id; 1832 __le16 resp_len; 1833 u8 eee_supported; 1834 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 1835 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 1836 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 1837 u8 unused_0; 1838 __le16 supported_speeds_force_mode; 1839 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 1840 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 1841 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 1842 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 1843 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 1844 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 1845 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 1846 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 1847 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 1848 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 1849 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 1850 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 1851 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 1852 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 1853 __le16 supported_speeds_auto_mode; 1854 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 1855 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 1856 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 1857 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 1858 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 1859 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 1860 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 1861 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 1862 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 1863 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 1864 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 1865 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 1866 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 1867 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 1868 __le16 supported_speeds_eee_mode; 1869 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 1870 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 1871 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 1872 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 1873 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 1874 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 1875 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 1876 __le32 tx_lpi_timer_low; 1877 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 1878 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 1879 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 1880 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 1881 __le32 valid_tx_lpi_timer_high; 1882 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 1883 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 1884 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 1885 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 1886 }; 1887 1888 /* hwrm_port_phy_i2c_read */ 1889 /* Input (40 bytes) */ 1890 struct hwrm_port_phy_i2c_read_input { 1891 __le16 req_type; 1892 __le16 cmpl_ring; 1893 __le16 seq_id; 1894 __le16 target_id; 1895 __le64 resp_addr; 1896 __le32 flags; 1897 __le32 enables; 1898 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 1899 __le16 port_id; 1900 u8 i2c_slave_addr; 1901 u8 unused_0; 1902 __le16 page_number; 1903 __le16 page_offset; 1904 u8 data_length; 1905 u8 unused_1[7]; 1906 }; 1907 1908 /* Output (80 bytes) */ 1909 struct hwrm_port_phy_i2c_read_output { 1910 __le16 error_code; 1911 __le16 req_type; 1912 __le16 seq_id; 1913 __le16 resp_len; 1914 __le32 data[16]; 1915 __le32 unused_0; 1916 u8 unused_1; 1917 u8 unused_2; 1918 u8 unused_3; 1919 u8 valid; 1920 }; 1921 1922 /* hwrm_queue_qportcfg */ 1923 /* Input (24 bytes) */ 1924 struct hwrm_queue_qportcfg_input { 1925 __le16 req_type; 1926 __le16 cmpl_ring; 1927 __le16 seq_id; 1928 __le16 target_id; 1929 __le64 resp_addr; 1930 __le32 flags; 1931 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 1932 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 1933 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 1934 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 1935 __le16 port_id; 1936 __le16 unused_0; 1937 }; 1938 1939 /* Output (32 bytes) */ 1940 struct hwrm_queue_qportcfg_output { 1941 __le16 error_code; 1942 __le16 req_type; 1943 __le16 seq_id; 1944 __le16 resp_len; 1945 u8 max_configurable_queues; 1946 u8 max_configurable_lossless_queues; 1947 u8 queue_cfg_allowed; 1948 u8 queue_cfg_info; 1949 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 1950 u8 queue_pfcenable_cfg_allowed; 1951 u8 queue_pri2cos_cfg_allowed; 1952 u8 queue_cos2bw_cfg_allowed; 1953 u8 queue_id0; 1954 u8 queue_id0_service_profile; 1955 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 1956 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 1957 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 1958 u8 queue_id1; 1959 u8 queue_id1_service_profile; 1960 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 1961 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 1962 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 1963 u8 queue_id2; 1964 u8 queue_id2_service_profile; 1965 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 1966 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 1967 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 1968 u8 queue_id3; 1969 u8 queue_id3_service_profile; 1970 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 1971 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 1972 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 1973 u8 queue_id4; 1974 u8 queue_id4_service_profile; 1975 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 1976 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 1977 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 1978 u8 queue_id5; 1979 u8 queue_id5_service_profile; 1980 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 1981 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 1982 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 1983 u8 queue_id6; 1984 u8 queue_id6_service_profile; 1985 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 1986 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 1987 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 1988 u8 queue_id7; 1989 u8 queue_id7_service_profile; 1990 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 1991 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 1992 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 1993 u8 valid; 1994 }; 1995 1996 /* hwrm_queue_cfg */ 1997 /* Input (40 bytes) */ 1998 struct hwrm_queue_cfg_input { 1999 __le16 req_type; 2000 __le16 cmpl_ring; 2001 __le16 seq_id; 2002 __le16 target_id; 2003 __le64 resp_addr; 2004 __le32 flags; 2005 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2006 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2007 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2008 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2009 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2010 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2011 __le32 enables; 2012 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2013 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2014 __le32 queue_id; 2015 __le32 dflt_len; 2016 u8 service_profile; 2017 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2018 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2019 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2020 u8 unused_0[7]; 2021 }; 2022 2023 /* Output (16 bytes) */ 2024 struct hwrm_queue_cfg_output { 2025 __le16 error_code; 2026 __le16 req_type; 2027 __le16 seq_id; 2028 __le16 resp_len; 2029 __le32 unused_0; 2030 u8 unused_1; 2031 u8 unused_2; 2032 u8 unused_3; 2033 u8 valid; 2034 }; 2035 2036 /* hwrm_queue_pfcenable_qcfg */ 2037 /* Input (24 bytes) */ 2038 struct hwrm_queue_pfcenable_qcfg_input { 2039 __le16 req_type; 2040 __le16 cmpl_ring; 2041 __le16 seq_id; 2042 __le16 target_id; 2043 __le64 resp_addr; 2044 __le16 port_id; 2045 __le16 unused_0[3]; 2046 }; 2047 2048 /* Output (16 bytes) */ 2049 struct hwrm_queue_pfcenable_qcfg_output { 2050 __le16 error_code; 2051 __le16 req_type; 2052 __le16 seq_id; 2053 __le16 resp_len; 2054 __le32 flags; 2055 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2056 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2057 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2058 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2059 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2060 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2061 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2062 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2063 u8 unused_0; 2064 u8 unused_1; 2065 u8 unused_2; 2066 u8 valid; 2067 }; 2068 2069 /* hwrm_queue_pfcenable_cfg */ 2070 /* Input (24 bytes) */ 2071 struct hwrm_queue_pfcenable_cfg_input { 2072 __le16 req_type; 2073 __le16 cmpl_ring; 2074 __le16 seq_id; 2075 __le16 target_id; 2076 __le64 resp_addr; 2077 __le32 flags; 2078 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2079 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2080 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2081 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2082 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2083 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2084 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2085 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2086 __le16 port_id; 2087 __le16 unused_0; 2088 }; 2089 2090 /* Output (16 bytes) */ 2091 struct hwrm_queue_pfcenable_cfg_output { 2092 __le16 error_code; 2093 __le16 req_type; 2094 __le16 seq_id; 2095 __le16 resp_len; 2096 __le32 unused_0; 2097 u8 unused_1; 2098 u8 unused_2; 2099 u8 unused_3; 2100 u8 valid; 2101 }; 2102 2103 /* hwrm_queue_pri2cos_qcfg */ 2104 /* Input (24 bytes) */ 2105 struct hwrm_queue_pri2cos_qcfg_input { 2106 __le16 req_type; 2107 __le16 cmpl_ring; 2108 __le16 seq_id; 2109 __le16 target_id; 2110 __le64 resp_addr; 2111 __le32 flags; 2112 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2113 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2114 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2115 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2116 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2117 u8 port_id; 2118 u8 unused_0[3]; 2119 }; 2120 2121 /* Output (24 bytes) */ 2122 struct hwrm_queue_pri2cos_qcfg_output { 2123 __le16 error_code; 2124 __le16 req_type; 2125 __le16 seq_id; 2126 __le16 resp_len; 2127 u8 pri0_cos_queue_id; 2128 u8 pri1_cos_queue_id; 2129 u8 pri2_cos_queue_id; 2130 u8 pri3_cos_queue_id; 2131 u8 pri4_cos_queue_id; 2132 u8 pri5_cos_queue_id; 2133 u8 pri6_cos_queue_id; 2134 u8 pri7_cos_queue_id; 2135 u8 queue_cfg_info; 2136 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2137 u8 unused_0; 2138 __le16 unused_1; 2139 u8 unused_2; 2140 u8 unused_3; 2141 u8 unused_4; 2142 u8 valid; 2143 }; 2144 2145 /* hwrm_queue_pri2cos_cfg */ 2146 /* Input (40 bytes) */ 2147 struct hwrm_queue_pri2cos_cfg_input { 2148 __le16 req_type; 2149 __le16 cmpl_ring; 2150 __le16 seq_id; 2151 __le16 target_id; 2152 __le64 resp_addr; 2153 __le32 flags; 2154 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2155 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2156 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2157 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2158 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2159 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2160 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2161 __le32 enables; 2162 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2163 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2164 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2165 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2166 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2167 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2168 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2169 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2170 u8 port_id; 2171 u8 pri0_cos_queue_id; 2172 u8 pri1_cos_queue_id; 2173 u8 pri2_cos_queue_id; 2174 u8 pri3_cos_queue_id; 2175 u8 pri4_cos_queue_id; 2176 u8 pri5_cos_queue_id; 2177 u8 pri6_cos_queue_id; 2178 u8 pri7_cos_queue_id; 2179 u8 unused_0[7]; 2180 }; 2181 2182 /* Output (16 bytes) */ 2183 struct hwrm_queue_pri2cos_cfg_output { 2184 __le16 error_code; 2185 __le16 req_type; 2186 __le16 seq_id; 2187 __le16 resp_len; 2188 __le32 unused_0; 2189 u8 unused_1; 2190 u8 unused_2; 2191 u8 unused_3; 2192 u8 valid; 2193 }; 2194 2195 /* hwrm_queue_cos2bw_qcfg */ 2196 /* Input (24 bytes) */ 2197 struct hwrm_queue_cos2bw_qcfg_input { 2198 __le16 req_type; 2199 __le16 cmpl_ring; 2200 __le16 seq_id; 2201 __le16 target_id; 2202 __le64 resp_addr; 2203 __le16 port_id; 2204 __le16 unused_0[3]; 2205 }; 2206 2207 /* Output (112 bytes) */ 2208 struct hwrm_queue_cos2bw_qcfg_output { 2209 __le16 error_code; 2210 __le16 req_type; 2211 __le16 seq_id; 2212 __le16 resp_len; 2213 u8 queue_id0; 2214 u8 unused_0; 2215 __le16 unused_1; 2216 __le32 queue_id0_min_bw; 2217 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2218 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2219 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_RSVD 0x10000000UL 2220 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2221 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2226 __le32 queue_id0_max_bw; 2227 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_RSVD 0x10000000UL 2230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2232 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2236 u8 queue_id0_tsa_assign; 2237 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2241 u8 queue_id0_pri_lvl; 2242 u8 queue_id0_bw_weight; 2243 u8 queue_id1; 2244 __le32 queue_id1_min_bw; 2245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_RSVD 0x10000000UL 2248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2250 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2254 __le32 queue_id1_max_bw; 2255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_RSVD 0x10000000UL 2258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2259 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2260 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2261 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2264 u8 queue_id1_tsa_assign; 2265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2266 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2268 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2269 u8 queue_id1_pri_lvl; 2270 u8 queue_id1_bw_weight; 2271 u8 queue_id2; 2272 __le32 queue_id2_min_bw; 2273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_RSVD 0x10000000UL 2276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2277 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2280 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2282 __le32 queue_id2_max_bw; 2283 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2284 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_RSVD 0x10000000UL 2286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2290 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2292 u8 queue_id2_tsa_assign; 2293 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2296 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2297 u8 queue_id2_pri_lvl; 2298 u8 queue_id2_bw_weight; 2299 u8 queue_id3; 2300 __le32 queue_id3_min_bw; 2301 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_RSVD 0x10000000UL 2304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2305 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2306 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2307 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2308 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2309 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2310 __le32 queue_id3_max_bw; 2311 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2312 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2313 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_RSVD 0x10000000UL 2314 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2315 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2316 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2317 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2318 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2319 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2320 u8 queue_id3_tsa_assign; 2321 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2322 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2323 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2324 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2325 u8 queue_id3_pri_lvl; 2326 u8 queue_id3_bw_weight; 2327 u8 queue_id4; 2328 __le32 queue_id4_min_bw; 2329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2330 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_RSVD 0x10000000UL 2332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2333 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2336 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2338 __le32 queue_id4_max_bw; 2339 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2340 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2341 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_RSVD 0x10000000UL 2342 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2346 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2348 u8 queue_id4_tsa_assign; 2349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2351 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2352 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2353 u8 queue_id4_pri_lvl; 2354 u8 queue_id4_bw_weight; 2355 u8 queue_id5; 2356 __le32 queue_id5_min_bw; 2357 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2358 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2359 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_RSVD 0x10000000UL 2360 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2361 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2362 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2363 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2364 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2365 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2366 __le32 queue_id5_max_bw; 2367 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_RSVD 0x10000000UL 2370 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2373 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2376 u8 queue_id5_tsa_assign; 2377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2378 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2379 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2380 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2381 u8 queue_id5_pri_lvl; 2382 u8 queue_id5_bw_weight; 2383 u8 queue_id6; 2384 __le32 queue_id6_min_bw; 2385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_RSVD 0x10000000UL 2388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2394 __le32 queue_id6_max_bw; 2395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2397 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_RSVD 0x10000000UL 2398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2399 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2400 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2404 u8 queue_id6_tsa_assign; 2405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2409 u8 queue_id6_pri_lvl; 2410 u8 queue_id6_bw_weight; 2411 u8 queue_id7; 2412 __le32 queue_id7_min_bw; 2413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_RSVD 0x10000000UL 2416 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2419 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2420 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2421 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2422 __le32 queue_id7_max_bw; 2423 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_RSVD 0x10000000UL 2426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2432 u8 queue_id7_tsa_assign; 2433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2437 u8 queue_id7_pri_lvl; 2438 u8 queue_id7_bw_weight; 2439 u8 unused_2; 2440 u8 unused_3; 2441 u8 unused_4; 2442 u8 unused_5; 2443 u8 valid; 2444 }; 2445 2446 /* hwrm_queue_cos2bw_cfg */ 2447 /* Input (128 bytes) */ 2448 struct hwrm_queue_cos2bw_cfg_input { 2449 __le16 req_type; 2450 __le16 cmpl_ring; 2451 __le16 seq_id; 2452 __le16 target_id; 2453 __le64 resp_addr; 2454 __le32 flags; 2455 __le32 enables; 2456 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2457 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2458 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2459 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2460 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2461 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2462 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2463 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2464 __le16 port_id; 2465 u8 queue_id0; 2466 u8 unused_0; 2467 __le32 queue_id0_min_bw; 2468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_RSVD 0x10000000UL 2471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2477 __le32 queue_id0_max_bw; 2478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_RSVD 0x10000000UL 2481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2487 u8 queue_id0_tsa_assign; 2488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2492 u8 queue_id0_pri_lvl; 2493 u8 queue_id0_bw_weight; 2494 u8 queue_id1; 2495 __le32 queue_id1_min_bw; 2496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_RSVD 0x10000000UL 2499 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2500 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2501 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2502 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2505 __le32 queue_id1_max_bw; 2506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_RSVD 0x10000000UL 2509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2515 u8 queue_id1_tsa_assign; 2516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2518 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2519 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2520 u8 queue_id1_pri_lvl; 2521 u8 queue_id1_bw_weight; 2522 u8 queue_id2; 2523 __le32 queue_id2_min_bw; 2524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_RSVD 0x10000000UL 2527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2529 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2533 __le32 queue_id2_max_bw; 2534 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_RSVD 0x10000000UL 2537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2539 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2540 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2541 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2542 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2543 u8 queue_id2_tsa_assign; 2544 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2545 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2546 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2547 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2548 u8 queue_id2_pri_lvl; 2549 u8 queue_id2_bw_weight; 2550 u8 queue_id3; 2551 __le32 queue_id3_min_bw; 2552 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2553 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2554 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_RSVD 0x10000000UL 2555 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2556 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2557 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2558 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2559 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2560 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2561 __le32 queue_id3_max_bw; 2562 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2563 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2564 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_RSVD 0x10000000UL 2565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2571 u8 queue_id3_tsa_assign; 2572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2575 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2576 u8 queue_id3_pri_lvl; 2577 u8 queue_id3_bw_weight; 2578 u8 queue_id4; 2579 __le32 queue_id4_min_bw; 2580 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2582 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_RSVD 0x10000000UL 2583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2585 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2589 __le32 queue_id4_max_bw; 2590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_RSVD 0x10000000UL 2593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2599 u8 queue_id4_tsa_assign; 2600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2604 u8 queue_id4_pri_lvl; 2605 u8 queue_id4_bw_weight; 2606 u8 queue_id5; 2607 __le32 queue_id5_min_bw; 2608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_RSVD 0x10000000UL 2611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2617 __le32 queue_id5_max_bw; 2618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2620 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_RSVD 0x10000000UL 2621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2623 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2627 u8 queue_id5_tsa_assign; 2628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2632 u8 queue_id5_pri_lvl; 2633 u8 queue_id5_bw_weight; 2634 u8 queue_id6; 2635 __le32 queue_id6_min_bw; 2636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_RSVD 0x10000000UL 2639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2645 __le32 queue_id6_max_bw; 2646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_RSVD 0x10000000UL 2649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2655 u8 queue_id6_tsa_assign; 2656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2660 u8 queue_id6_pri_lvl; 2661 u8 queue_id6_bw_weight; 2662 u8 queue_id7; 2663 __le32 queue_id7_min_bw; 2664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2665 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2666 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_RSVD 0x10000000UL 2667 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2668 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2669 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2673 __le32 queue_id7_max_bw; 2674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2676 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_RSVD 0x10000000UL 2677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2679 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 2680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2682 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2683 u8 queue_id7_tsa_assign; 2684 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2688 u8 queue_id7_pri_lvl; 2689 u8 queue_id7_bw_weight; 2690 u8 unused_1[5]; 2691 }; 2692 2693 /* Output (16 bytes) */ 2694 struct hwrm_queue_cos2bw_cfg_output { 2695 __le16 error_code; 2696 __le16 req_type; 2697 __le16 seq_id; 2698 __le16 resp_len; 2699 __le32 unused_0; 2700 u8 unused_1; 2701 u8 unused_2; 2702 u8 unused_3; 2703 u8 valid; 2704 }; 2705 2706 /* hwrm_vnic_alloc */ 2707 /* Input (24 bytes) */ 2708 struct hwrm_vnic_alloc_input { 2709 __le16 req_type; 2710 __le16 cmpl_ring; 2711 __le16 seq_id; 2712 __le16 target_id; 2713 __le64 resp_addr; 2714 __le32 flags; 2715 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 2716 __le32 unused_0; 2717 }; 2718 2719 /* Output (16 bytes) */ 2720 struct hwrm_vnic_alloc_output { 2721 __le16 error_code; 2722 __le16 req_type; 2723 __le16 seq_id; 2724 __le16 resp_len; 2725 __le32 vnic_id; 2726 u8 unused_0; 2727 u8 unused_1; 2728 u8 unused_2; 2729 u8 valid; 2730 }; 2731 2732 /* hwrm_vnic_free */ 2733 /* Input (24 bytes) */ 2734 struct hwrm_vnic_free_input { 2735 __le16 req_type; 2736 __le16 cmpl_ring; 2737 __le16 seq_id; 2738 __le16 target_id; 2739 __le64 resp_addr; 2740 __le32 vnic_id; 2741 __le32 unused_0; 2742 }; 2743 2744 /* Output (16 bytes) */ 2745 struct hwrm_vnic_free_output { 2746 __le16 error_code; 2747 __le16 req_type; 2748 __le16 seq_id; 2749 __le16 resp_len; 2750 __le32 unused_0; 2751 u8 unused_1; 2752 u8 unused_2; 2753 u8 unused_3; 2754 u8 valid; 2755 }; 2756 2757 /* hwrm_vnic_cfg */ 2758 /* Input (40 bytes) */ 2759 struct hwrm_vnic_cfg_input { 2760 __le16 req_type; 2761 __le16 cmpl_ring; 2762 __le16 seq_id; 2763 __le16 target_id; 2764 __le64 resp_addr; 2765 __le32 flags; 2766 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 2767 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 2768 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 2769 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 2770 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 2771 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 2772 __le32 enables; 2773 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 2774 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 2775 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 2776 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 2777 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 2778 __le16 vnic_id; 2779 __le16 dflt_ring_grp; 2780 __le16 rss_rule; 2781 __le16 cos_rule; 2782 __le16 lb_rule; 2783 __le16 mru; 2784 __le32 unused_0; 2785 }; 2786 2787 /* Output (16 bytes) */ 2788 struct hwrm_vnic_cfg_output { 2789 __le16 error_code; 2790 __le16 req_type; 2791 __le16 seq_id; 2792 __le16 resp_len; 2793 __le32 unused_0; 2794 u8 unused_1; 2795 u8 unused_2; 2796 u8 unused_3; 2797 u8 valid; 2798 }; 2799 2800 /* hwrm_vnic_tpa_cfg */ 2801 /* Input (40 bytes) */ 2802 struct hwrm_vnic_tpa_cfg_input { 2803 __le16 req_type; 2804 __le16 cmpl_ring; 2805 __le16 seq_id; 2806 __le16 target_id; 2807 __le64 resp_addr; 2808 __le32 flags; 2809 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 2810 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 2811 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 2812 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 2813 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 2814 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 2815 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 2816 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 2817 __le32 enables; 2818 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 2819 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 2820 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 2821 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 2822 __le16 vnic_id; 2823 __le16 max_agg_segs; 2824 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 2825 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 2826 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 2827 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 2828 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 2829 __le16 max_aggs; 2830 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 2831 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 2832 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 2833 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 2834 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 2835 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 2836 u8 unused_0; 2837 u8 unused_1; 2838 __le32 max_agg_timer; 2839 __le32 min_agg_len; 2840 }; 2841 2842 /* Output (16 bytes) */ 2843 struct hwrm_vnic_tpa_cfg_output { 2844 __le16 error_code; 2845 __le16 req_type; 2846 __le16 seq_id; 2847 __le16 resp_len; 2848 __le32 unused_0; 2849 u8 unused_1; 2850 u8 unused_2; 2851 u8 unused_3; 2852 u8 valid; 2853 }; 2854 2855 /* hwrm_vnic_rss_cfg */ 2856 /* Input (48 bytes) */ 2857 struct hwrm_vnic_rss_cfg_input { 2858 __le16 req_type; 2859 __le16 cmpl_ring; 2860 __le16 seq_id; 2861 __le16 target_id; 2862 __le64 resp_addr; 2863 __le32 hash_type; 2864 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 2865 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 2866 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 2867 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 2868 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 2869 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 2870 __le32 unused_0; 2871 __le64 ring_grp_tbl_addr; 2872 __le64 hash_key_tbl_addr; 2873 __le16 rss_ctx_idx; 2874 __le16 unused_1[3]; 2875 }; 2876 2877 /* Output (16 bytes) */ 2878 struct hwrm_vnic_rss_cfg_output { 2879 __le16 error_code; 2880 __le16 req_type; 2881 __le16 seq_id; 2882 __le16 resp_len; 2883 __le32 unused_0; 2884 u8 unused_1; 2885 u8 unused_2; 2886 u8 unused_3; 2887 u8 valid; 2888 }; 2889 2890 /* hwrm_vnic_plcmodes_cfg */ 2891 /* Input (40 bytes) */ 2892 struct hwrm_vnic_plcmodes_cfg_input { 2893 __le16 req_type; 2894 __le16 cmpl_ring; 2895 __le16 seq_id; 2896 __le16 target_id; 2897 __le64 resp_addr; 2898 __le32 flags; 2899 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 2900 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 2901 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 2902 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 2903 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 2904 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 2905 __le32 enables; 2906 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 2907 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 2908 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 2909 __le32 vnic_id; 2910 __le16 jumbo_thresh; 2911 __le16 hds_offset; 2912 __le16 hds_threshold; 2913 __le16 unused_0[3]; 2914 }; 2915 2916 /* Output (16 bytes) */ 2917 struct hwrm_vnic_plcmodes_cfg_output { 2918 __le16 error_code; 2919 __le16 req_type; 2920 __le16 seq_id; 2921 __le16 resp_len; 2922 __le32 unused_0; 2923 u8 unused_1; 2924 u8 unused_2; 2925 u8 unused_3; 2926 u8 valid; 2927 }; 2928 2929 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 2930 /* Input (16 bytes) */ 2931 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 2932 __le16 req_type; 2933 __le16 cmpl_ring; 2934 __le16 seq_id; 2935 __le16 target_id; 2936 __le64 resp_addr; 2937 }; 2938 2939 /* Output (16 bytes) */ 2940 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 2941 __le16 error_code; 2942 __le16 req_type; 2943 __le16 seq_id; 2944 __le16 resp_len; 2945 __le16 rss_cos_lb_ctx_id; 2946 u8 unused_0; 2947 u8 unused_1; 2948 u8 unused_2; 2949 u8 unused_3; 2950 u8 unused_4; 2951 u8 valid; 2952 }; 2953 2954 /* hwrm_vnic_rss_cos_lb_ctx_free */ 2955 /* Input (24 bytes) */ 2956 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 2957 __le16 req_type; 2958 __le16 cmpl_ring; 2959 __le16 seq_id; 2960 __le16 target_id; 2961 __le64 resp_addr; 2962 __le16 rss_cos_lb_ctx_id; 2963 __le16 unused_0[3]; 2964 }; 2965 2966 /* Output (16 bytes) */ 2967 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 2968 __le16 error_code; 2969 __le16 req_type; 2970 __le16 seq_id; 2971 __le16 resp_len; 2972 __le32 unused_0; 2973 u8 unused_1; 2974 u8 unused_2; 2975 u8 unused_3; 2976 u8 valid; 2977 }; 2978 2979 /* hwrm_ring_alloc */ 2980 /* Input (80 bytes) */ 2981 struct hwrm_ring_alloc_input { 2982 __le16 req_type; 2983 __le16 cmpl_ring; 2984 __le16 seq_id; 2985 __le16 target_id; 2986 __le64 resp_addr; 2987 __le32 enables; 2988 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 2989 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 2990 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 2991 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 2992 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 2993 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 2994 u8 ring_type; 2995 #define RING_ALLOC_REQ_RING_TYPE_CMPL 0x0UL 2996 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 2997 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 2998 u8 unused_0; 2999 __le16 unused_1; 3000 __le64 page_tbl_addr; 3001 __le32 fbo; 3002 u8 page_size; 3003 u8 page_tbl_depth; 3004 u8 unused_2; 3005 u8 unused_3; 3006 __le32 length; 3007 __le16 logical_id; 3008 __le16 cmpl_ring_id; 3009 __le16 queue_id; 3010 u8 unused_4; 3011 u8 unused_5; 3012 __le32 reserved1; 3013 __le16 ring_arb_cfg; 3014 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3015 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3016 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3017 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3018 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3019 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3020 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3021 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3022 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3023 u8 unused_6; 3024 u8 unused_7; 3025 __le32 reserved3; 3026 __le32 stat_ctx_id; 3027 __le32 reserved4; 3028 __le32 max_bw; 3029 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3030 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3031 #define RING_ALLOC_REQ_MAX_BW_RSVD 0x10000000UL 3032 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3033 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3034 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MBPS (0x0UL << 29) 3035 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3036 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3037 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3038 u8 int_mode; 3039 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3040 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3041 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3042 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3043 u8 unused_8[3]; 3044 }; 3045 3046 /* Output (16 bytes) */ 3047 struct hwrm_ring_alloc_output { 3048 __le16 error_code; 3049 __le16 req_type; 3050 __le16 seq_id; 3051 __le16 resp_len; 3052 __le16 ring_id; 3053 __le16 logical_ring_id; 3054 u8 unused_0; 3055 u8 unused_1; 3056 u8 unused_2; 3057 u8 valid; 3058 }; 3059 3060 /* hwrm_ring_free */ 3061 /* Input (24 bytes) */ 3062 struct hwrm_ring_free_input { 3063 __le16 req_type; 3064 __le16 cmpl_ring; 3065 __le16 seq_id; 3066 __le16 target_id; 3067 __le64 resp_addr; 3068 u8 ring_type; 3069 #define RING_FREE_REQ_RING_TYPE_CMPL 0x0UL 3070 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3071 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3072 u8 unused_0; 3073 __le16 ring_id; 3074 __le32 unused_1; 3075 }; 3076 3077 /* Output (16 bytes) */ 3078 struct hwrm_ring_free_output { 3079 __le16 error_code; 3080 __le16 req_type; 3081 __le16 seq_id; 3082 __le16 resp_len; 3083 __le32 unused_0; 3084 u8 unused_1; 3085 u8 unused_2; 3086 u8 unused_3; 3087 u8 valid; 3088 }; 3089 3090 /* hwrm_ring_cmpl_ring_qaggint_params */ 3091 /* Input (24 bytes) */ 3092 struct hwrm_ring_cmpl_ring_qaggint_params_input { 3093 __le16 req_type; 3094 __le16 cmpl_ring; 3095 __le16 seq_id; 3096 __le16 target_id; 3097 __le64 resp_addr; 3098 __le16 ring_id; 3099 __le16 unused_0[3]; 3100 }; 3101 3102 /* Output (32 bytes) */ 3103 struct hwrm_ring_cmpl_ring_qaggint_params_output { 3104 __le16 error_code; 3105 __le16 req_type; 3106 __le16 seq_id; 3107 __le16 resp_len; 3108 __le16 flags; 3109 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3110 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3111 __le16 num_cmpl_dma_aggr; 3112 __le16 num_cmpl_dma_aggr_during_int; 3113 __le16 cmpl_aggr_dma_tmr; 3114 __le16 cmpl_aggr_dma_tmr_during_int; 3115 __le16 int_lat_tmr_min; 3116 __le16 int_lat_tmr_max; 3117 __le16 num_cmpl_aggr_int; 3118 __le32 unused_0; 3119 u8 unused_1; 3120 u8 unused_2; 3121 u8 unused_3; 3122 u8 valid; 3123 }; 3124 3125 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3126 /* Input (40 bytes) */ 3127 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3128 __le16 req_type; 3129 __le16 cmpl_ring; 3130 __le16 seq_id; 3131 __le16 target_id; 3132 __le64 resp_addr; 3133 __le16 ring_id; 3134 __le16 flags; 3135 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3136 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3137 __le16 num_cmpl_dma_aggr; 3138 __le16 num_cmpl_dma_aggr_during_int; 3139 __le16 cmpl_aggr_dma_tmr; 3140 __le16 cmpl_aggr_dma_tmr_during_int; 3141 __le16 int_lat_tmr_min; 3142 __le16 int_lat_tmr_max; 3143 __le16 num_cmpl_aggr_int; 3144 __le16 unused_0[3]; 3145 }; 3146 3147 /* Output (16 bytes) */ 3148 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3149 __le16 error_code; 3150 __le16 req_type; 3151 __le16 seq_id; 3152 __le16 resp_len; 3153 __le32 unused_0; 3154 u8 unused_1; 3155 u8 unused_2; 3156 u8 unused_3; 3157 u8 valid; 3158 }; 3159 3160 /* hwrm_ring_reset */ 3161 /* Input (24 bytes) */ 3162 struct hwrm_ring_reset_input { 3163 __le16 req_type; 3164 __le16 cmpl_ring; 3165 __le16 seq_id; 3166 __le16 target_id; 3167 __le64 resp_addr; 3168 u8 ring_type; 3169 #define RING_RESET_REQ_RING_TYPE_CMPL 0x0UL 3170 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3171 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3172 u8 unused_0; 3173 __le16 ring_id; 3174 __le32 unused_1; 3175 }; 3176 3177 /* Output (16 bytes) */ 3178 struct hwrm_ring_reset_output { 3179 __le16 error_code; 3180 __le16 req_type; 3181 __le16 seq_id; 3182 __le16 resp_len; 3183 __le32 unused_0; 3184 u8 unused_1; 3185 u8 unused_2; 3186 u8 unused_3; 3187 u8 valid; 3188 }; 3189 3190 /* hwrm_ring_grp_alloc */ 3191 /* Input (24 bytes) */ 3192 struct hwrm_ring_grp_alloc_input { 3193 __le16 req_type; 3194 __le16 cmpl_ring; 3195 __le16 seq_id; 3196 __le16 target_id; 3197 __le64 resp_addr; 3198 __le16 cr; 3199 __le16 rr; 3200 __le16 ar; 3201 __le16 sc; 3202 }; 3203 3204 /* Output (16 bytes) */ 3205 struct hwrm_ring_grp_alloc_output { 3206 __le16 error_code; 3207 __le16 req_type; 3208 __le16 seq_id; 3209 __le16 resp_len; 3210 __le32 ring_group_id; 3211 u8 unused_0; 3212 u8 unused_1; 3213 u8 unused_2; 3214 u8 valid; 3215 }; 3216 3217 /* hwrm_ring_grp_free */ 3218 /* Input (24 bytes) */ 3219 struct hwrm_ring_grp_free_input { 3220 __le16 req_type; 3221 __le16 cmpl_ring; 3222 __le16 seq_id; 3223 __le16 target_id; 3224 __le64 resp_addr; 3225 __le32 ring_group_id; 3226 __le32 unused_0; 3227 }; 3228 3229 /* Output (16 bytes) */ 3230 struct hwrm_ring_grp_free_output { 3231 __le16 error_code; 3232 __le16 req_type; 3233 __le16 seq_id; 3234 __le16 resp_len; 3235 __le32 unused_0; 3236 u8 unused_1; 3237 u8 unused_2; 3238 u8 unused_3; 3239 u8 valid; 3240 }; 3241 3242 /* hwrm_cfa_l2_filter_alloc */ 3243 /* Input (96 bytes) */ 3244 struct hwrm_cfa_l2_filter_alloc_input { 3245 __le16 req_type; 3246 __le16 cmpl_ring; 3247 __le16 seq_id; 3248 __le16 target_id; 3249 __le64 resp_addr; 3250 __le32 flags; 3251 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3252 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3253 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3254 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3255 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3256 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3257 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3258 __le32 enables; 3259 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3260 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3261 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3262 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3263 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3264 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3265 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3266 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3267 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3268 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3269 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3270 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3271 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3272 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3273 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3274 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3275 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3276 u8 l2_addr[6]; 3277 u8 unused_0; 3278 u8 unused_1; 3279 u8 l2_addr_mask[6]; 3280 __le16 l2_ovlan; 3281 __le16 l2_ovlan_mask; 3282 __le16 l2_ivlan; 3283 __le16 l2_ivlan_mask; 3284 u8 unused_2; 3285 u8 unused_3; 3286 u8 t_l2_addr[6]; 3287 u8 unused_4; 3288 u8 unused_5; 3289 u8 t_l2_addr_mask[6]; 3290 __le16 t_l2_ovlan; 3291 __le16 t_l2_ovlan_mask; 3292 __le16 t_l2_ivlan; 3293 __le16 t_l2_ivlan_mask; 3294 u8 src_type; 3295 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3296 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3297 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3298 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3299 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3300 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3301 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3302 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3303 u8 unused_6; 3304 __le32 src_id; 3305 u8 tunnel_type; 3306 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3307 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3308 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3309 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3310 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3311 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3312 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3313 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3314 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3315 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3316 u8 unused_7; 3317 __le16 dst_id; 3318 __le16 mirror_vnic_id; 3319 u8 pri_hint; 3320 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3321 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 3322 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 3323 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 3324 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 3325 u8 unused_8; 3326 __le32 unused_9; 3327 __le64 l2_filter_id_hint; 3328 }; 3329 3330 /* Output (24 bytes) */ 3331 struct hwrm_cfa_l2_filter_alloc_output { 3332 __le16 error_code; 3333 __le16 req_type; 3334 __le16 seq_id; 3335 __le16 resp_len; 3336 __le64 l2_filter_id; 3337 __le32 flow_id; 3338 u8 unused_0; 3339 u8 unused_1; 3340 u8 unused_2; 3341 u8 valid; 3342 }; 3343 3344 /* hwrm_cfa_l2_filter_free */ 3345 /* Input (24 bytes) */ 3346 struct hwrm_cfa_l2_filter_free_input { 3347 __le16 req_type; 3348 __le16 cmpl_ring; 3349 __le16 seq_id; 3350 __le16 target_id; 3351 __le64 resp_addr; 3352 __le64 l2_filter_id; 3353 }; 3354 3355 /* Output (16 bytes) */ 3356 struct hwrm_cfa_l2_filter_free_output { 3357 __le16 error_code; 3358 __le16 req_type; 3359 __le16 seq_id; 3360 __le16 resp_len; 3361 __le32 unused_0; 3362 u8 unused_1; 3363 u8 unused_2; 3364 u8 unused_3; 3365 u8 valid; 3366 }; 3367 3368 /* hwrm_cfa_l2_filter_cfg */ 3369 /* Input (40 bytes) */ 3370 struct hwrm_cfa_l2_filter_cfg_input { 3371 __le16 req_type; 3372 __le16 cmpl_ring; 3373 __le16 seq_id; 3374 __le16 target_id; 3375 __le64 resp_addr; 3376 __le32 flags; 3377 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3378 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3379 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 3380 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3381 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3382 __le32 enables; 3383 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3384 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3385 __le64 l2_filter_id; 3386 __le32 dst_id; 3387 __le32 new_mirror_vnic_id; 3388 }; 3389 3390 /* Output (16 bytes) */ 3391 struct hwrm_cfa_l2_filter_cfg_output { 3392 __le16 error_code; 3393 __le16 req_type; 3394 __le16 seq_id; 3395 __le16 resp_len; 3396 __le32 unused_0; 3397 u8 unused_1; 3398 u8 unused_2; 3399 u8 unused_3; 3400 u8 valid; 3401 }; 3402 3403 /* hwrm_cfa_l2_set_rx_mask */ 3404 /* Input (56 bytes) */ 3405 struct hwrm_cfa_l2_set_rx_mask_input { 3406 __le16 req_type; 3407 __le16 cmpl_ring; 3408 __le16 seq_id; 3409 __le16 target_id; 3410 __le64 resp_addr; 3411 __le32 vnic_id; 3412 __le32 mask; 3413 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3414 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3415 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3416 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3417 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3418 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3419 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 3420 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 3421 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 3422 __le64 mc_tbl_addr; 3423 __le32 num_mc_entries; 3424 __le32 unused_0; 3425 __le64 vlan_tag_tbl_addr; 3426 __le32 num_vlan_tags; 3427 __le32 unused_1; 3428 }; 3429 3430 /* Output (16 bytes) */ 3431 struct hwrm_cfa_l2_set_rx_mask_output { 3432 __le16 error_code; 3433 __le16 req_type; 3434 __le16 seq_id; 3435 __le16 resp_len; 3436 __le32 unused_0; 3437 u8 unused_1; 3438 u8 unused_2; 3439 u8 unused_3; 3440 u8 valid; 3441 }; 3442 3443 /* hwrm_cfa_tunnel_filter_alloc */ 3444 /* Input (88 bytes) */ 3445 struct hwrm_cfa_tunnel_filter_alloc_input { 3446 __le16 req_type; 3447 __le16 cmpl_ring; 3448 __le16 seq_id; 3449 __le16 target_id; 3450 __le64 resp_addr; 3451 __le32 flags; 3452 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3453 __le32 enables; 3454 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3455 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3456 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3457 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3458 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3459 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3460 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3461 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3462 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3463 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3464 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3465 __le64 l2_filter_id; 3466 u8 l2_addr[6]; 3467 __le16 l2_ivlan; 3468 __le32 l3_addr[4]; 3469 __le32 t_l3_addr[4]; 3470 u8 l3_addr_type; 3471 u8 t_l3_addr_type; 3472 u8 tunnel_type; 3473 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3474 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3475 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3476 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3477 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3478 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3479 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3480 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3481 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3482 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3483 u8 unused_0; 3484 __le32 vni; 3485 __le32 dst_vnic_id; 3486 __le32 mirror_vnic_id; 3487 }; 3488 3489 /* Output (24 bytes) */ 3490 struct hwrm_cfa_tunnel_filter_alloc_output { 3491 __le16 error_code; 3492 __le16 req_type; 3493 __le16 seq_id; 3494 __le16 resp_len; 3495 __le64 tunnel_filter_id; 3496 __le32 flow_id; 3497 u8 unused_0; 3498 u8 unused_1; 3499 u8 unused_2; 3500 u8 valid; 3501 }; 3502 3503 /* hwrm_cfa_tunnel_filter_free */ 3504 /* Input (24 bytes) */ 3505 struct hwrm_cfa_tunnel_filter_free_input { 3506 __le16 req_type; 3507 __le16 cmpl_ring; 3508 __le16 seq_id; 3509 __le16 target_id; 3510 __le64 resp_addr; 3511 __le64 tunnel_filter_id; 3512 }; 3513 3514 /* Output (16 bytes) */ 3515 struct hwrm_cfa_tunnel_filter_free_output { 3516 __le16 error_code; 3517 __le16 req_type; 3518 __le16 seq_id; 3519 __le16 resp_len; 3520 __le32 unused_0; 3521 u8 unused_1; 3522 u8 unused_2; 3523 u8 unused_3; 3524 u8 valid; 3525 }; 3526 3527 /* hwrm_cfa_encap_record_alloc */ 3528 /* Input (32 bytes) */ 3529 struct hwrm_cfa_encap_record_alloc_input { 3530 __le16 req_type; 3531 __le16 cmpl_ring; 3532 __le16 seq_id; 3533 __le16 target_id; 3534 __le64 resp_addr; 3535 __le32 flags; 3536 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3537 u8 encap_type; 3538 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 3539 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 3540 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 3541 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 3542 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 3543 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 3544 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 3545 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 3546 u8 unused_0; 3547 __le16 unused_1; 3548 __le32 encap_data[16]; 3549 }; 3550 3551 /* Output (16 bytes) */ 3552 struct hwrm_cfa_encap_record_alloc_output { 3553 __le16 error_code; 3554 __le16 req_type; 3555 __le16 seq_id; 3556 __le16 resp_len; 3557 __le32 encap_record_id; 3558 u8 unused_0; 3559 u8 unused_1; 3560 u8 unused_2; 3561 u8 valid; 3562 }; 3563 3564 /* hwrm_cfa_encap_record_free */ 3565 /* Input (24 bytes) */ 3566 struct hwrm_cfa_encap_record_free_input { 3567 __le16 req_type; 3568 __le16 cmpl_ring; 3569 __le16 seq_id; 3570 __le16 target_id; 3571 __le64 resp_addr; 3572 __le32 encap_record_id; 3573 __le32 unused_0; 3574 }; 3575 3576 /* Output (16 bytes) */ 3577 struct hwrm_cfa_encap_record_free_output { 3578 __le16 error_code; 3579 __le16 req_type; 3580 __le16 seq_id; 3581 __le16 resp_len; 3582 __le32 unused_0; 3583 u8 unused_1; 3584 u8 unused_2; 3585 u8 unused_3; 3586 u8 valid; 3587 }; 3588 3589 /* hwrm_cfa_ntuple_filter_alloc */ 3590 /* Input (128 bytes) */ 3591 struct hwrm_cfa_ntuple_filter_alloc_input { 3592 __le16 req_type; 3593 __le16 cmpl_ring; 3594 __le16 seq_id; 3595 __le16 target_id; 3596 __le64 resp_addr; 3597 __le32 flags; 3598 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3599 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 3600 __le32 enables; 3601 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3602 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 3603 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 3604 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 3605 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 3606 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 3607 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 3608 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 3609 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 3610 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 3611 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 3612 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 3613 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 3614 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 3615 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 3616 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 3617 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 3618 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 3619 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 3620 __le64 l2_filter_id; 3621 u8 src_macaddr[6]; 3622 __be16 ethertype; 3623 u8 ip_addr_type; 3624 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 3625 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 3626 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 3627 u8 ip_protocol; 3628 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 3629 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x6UL 3630 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x11UL 3631 __le16 dst_id; 3632 __le16 mirror_vnic_id; 3633 u8 tunnel_type; 3634 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3635 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3636 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3637 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3638 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3639 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3640 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3641 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3642 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3643 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3644 u8 pri_hint; 3645 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3646 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 3647 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 3648 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 3649 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 3650 __be32 src_ipaddr[4]; 3651 __be32 src_ipaddr_mask[4]; 3652 __be32 dst_ipaddr[4]; 3653 __be32 dst_ipaddr_mask[4]; 3654 __be16 src_port; 3655 __be16 src_port_mask; 3656 __be16 dst_port; 3657 __be16 dst_port_mask; 3658 __le64 ntuple_filter_id_hint; 3659 }; 3660 3661 /* Output (24 bytes) */ 3662 struct hwrm_cfa_ntuple_filter_alloc_output { 3663 __le16 error_code; 3664 __le16 req_type; 3665 __le16 seq_id; 3666 __le16 resp_len; 3667 __le64 ntuple_filter_id; 3668 __le32 flow_id; 3669 u8 unused_0; 3670 u8 unused_1; 3671 u8 unused_2; 3672 u8 valid; 3673 }; 3674 3675 /* hwrm_cfa_ntuple_filter_free */ 3676 /* Input (24 bytes) */ 3677 struct hwrm_cfa_ntuple_filter_free_input { 3678 __le16 req_type; 3679 __le16 cmpl_ring; 3680 __le16 seq_id; 3681 __le16 target_id; 3682 __le64 resp_addr; 3683 __le64 ntuple_filter_id; 3684 }; 3685 3686 /* Output (16 bytes) */ 3687 struct hwrm_cfa_ntuple_filter_free_output { 3688 __le16 error_code; 3689 __le16 req_type; 3690 __le16 seq_id; 3691 __le16 resp_len; 3692 __le32 unused_0; 3693 u8 unused_1; 3694 u8 unused_2; 3695 u8 unused_3; 3696 u8 valid; 3697 }; 3698 3699 /* hwrm_cfa_ntuple_filter_cfg */ 3700 /* Input (40 bytes) */ 3701 struct hwrm_cfa_ntuple_filter_cfg_input { 3702 __le16 req_type; 3703 __le16 cmpl_ring; 3704 __le16 seq_id; 3705 __le16 target_id; 3706 __le64 resp_addr; 3707 __le32 enables; 3708 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 3709 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3710 __le32 unused_0; 3711 __le64 ntuple_filter_id; 3712 __le32 new_dst_id; 3713 __le32 new_mirror_vnic_id; 3714 }; 3715 3716 /* Output (16 bytes) */ 3717 struct hwrm_cfa_ntuple_filter_cfg_output { 3718 __le16 error_code; 3719 __le16 req_type; 3720 __le16 seq_id; 3721 __le16 resp_len; 3722 __le32 unused_0; 3723 u8 unused_1; 3724 u8 unused_2; 3725 u8 unused_3; 3726 u8 valid; 3727 }; 3728 3729 /* hwrm_tunnel_dst_port_query */ 3730 /* Input (24 bytes) */ 3731 struct hwrm_tunnel_dst_port_query_input { 3732 __le16 req_type; 3733 __le16 cmpl_ring; 3734 __le16 seq_id; 3735 __le16 target_id; 3736 __le64 resp_addr; 3737 u8 tunnel_type; 3738 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3739 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3740 u8 unused_0[7]; 3741 }; 3742 3743 /* Output (16 bytes) */ 3744 struct hwrm_tunnel_dst_port_query_output { 3745 __le16 error_code; 3746 __le16 req_type; 3747 __le16 seq_id; 3748 __le16 resp_len; 3749 __le16 tunnel_dst_port_id; 3750 __be16 tunnel_dst_port_val; 3751 u8 unused_0; 3752 u8 unused_1; 3753 u8 unused_2; 3754 u8 valid; 3755 }; 3756 3757 /* hwrm_tunnel_dst_port_alloc */ 3758 /* Input (24 bytes) */ 3759 struct hwrm_tunnel_dst_port_alloc_input { 3760 __le16 req_type; 3761 __le16 cmpl_ring; 3762 __le16 seq_id; 3763 __le16 target_id; 3764 __le64 resp_addr; 3765 u8 tunnel_type; 3766 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3767 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3768 u8 unused_0; 3769 __be16 tunnel_dst_port_val; 3770 __le32 unused_1; 3771 }; 3772 3773 /* Output (16 bytes) */ 3774 struct hwrm_tunnel_dst_port_alloc_output { 3775 __le16 error_code; 3776 __le16 req_type; 3777 __le16 seq_id; 3778 __le16 resp_len; 3779 __le16 tunnel_dst_port_id; 3780 u8 unused_0; 3781 u8 unused_1; 3782 u8 unused_2; 3783 u8 unused_3; 3784 u8 unused_4; 3785 u8 valid; 3786 }; 3787 3788 /* hwrm_tunnel_dst_port_free */ 3789 /* Input (24 bytes) */ 3790 struct hwrm_tunnel_dst_port_free_input { 3791 __le16 req_type; 3792 __le16 cmpl_ring; 3793 __le16 seq_id; 3794 __le16 target_id; 3795 __le64 resp_addr; 3796 u8 tunnel_type; 3797 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3798 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3799 u8 unused_0; 3800 __le16 tunnel_dst_port_id; 3801 __le32 unused_1; 3802 }; 3803 3804 /* Output (16 bytes) */ 3805 struct hwrm_tunnel_dst_port_free_output { 3806 __le16 error_code; 3807 __le16 req_type; 3808 __le16 seq_id; 3809 __le16 resp_len; 3810 __le32 unused_0; 3811 u8 unused_1; 3812 u8 unused_2; 3813 u8 unused_3; 3814 u8 valid; 3815 }; 3816 3817 /* hwrm_stat_ctx_alloc */ 3818 /* Input (32 bytes) */ 3819 struct hwrm_stat_ctx_alloc_input { 3820 __le16 req_type; 3821 __le16 cmpl_ring; 3822 __le16 seq_id; 3823 __le16 target_id; 3824 __le64 resp_addr; 3825 __le64 stats_dma_addr; 3826 __le32 update_period_ms; 3827 u8 stat_ctx_flags; 3828 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 3829 u8 unused_0[3]; 3830 }; 3831 3832 /* Output (16 bytes) */ 3833 struct hwrm_stat_ctx_alloc_output { 3834 __le16 error_code; 3835 __le16 req_type; 3836 __le16 seq_id; 3837 __le16 resp_len; 3838 __le32 stat_ctx_id; 3839 u8 unused_0; 3840 u8 unused_1; 3841 u8 unused_2; 3842 u8 valid; 3843 }; 3844 3845 /* hwrm_stat_ctx_free */ 3846 /* Input (24 bytes) */ 3847 struct hwrm_stat_ctx_free_input { 3848 __le16 req_type; 3849 __le16 cmpl_ring; 3850 __le16 seq_id; 3851 __le16 target_id; 3852 __le64 resp_addr; 3853 __le32 stat_ctx_id; 3854 __le32 unused_0; 3855 }; 3856 3857 /* Output (16 bytes) */ 3858 struct hwrm_stat_ctx_free_output { 3859 __le16 error_code; 3860 __le16 req_type; 3861 __le16 seq_id; 3862 __le16 resp_len; 3863 __le32 stat_ctx_id; 3864 u8 unused_0; 3865 u8 unused_1; 3866 u8 unused_2; 3867 u8 valid; 3868 }; 3869 3870 /* hwrm_stat_ctx_query */ 3871 /* Input (24 bytes) */ 3872 struct hwrm_stat_ctx_query_input { 3873 __le16 req_type; 3874 __le16 cmpl_ring; 3875 __le16 seq_id; 3876 __le16 target_id; 3877 __le64 resp_addr; 3878 __le32 stat_ctx_id; 3879 __le32 unused_0; 3880 }; 3881 3882 /* Output (176 bytes) */ 3883 struct hwrm_stat_ctx_query_output { 3884 __le16 error_code; 3885 __le16 req_type; 3886 __le16 seq_id; 3887 __le16 resp_len; 3888 __le64 tx_ucast_pkts; 3889 __le64 tx_mcast_pkts; 3890 __le64 tx_bcast_pkts; 3891 __le64 tx_err_pkts; 3892 __le64 tx_drop_pkts; 3893 __le64 tx_ucast_bytes; 3894 __le64 tx_mcast_bytes; 3895 __le64 tx_bcast_bytes; 3896 __le64 rx_ucast_pkts; 3897 __le64 rx_mcast_pkts; 3898 __le64 rx_bcast_pkts; 3899 __le64 rx_err_pkts; 3900 __le64 rx_drop_pkts; 3901 __le64 rx_ucast_bytes; 3902 __le64 rx_mcast_bytes; 3903 __le64 rx_bcast_bytes; 3904 __le64 rx_agg_pkts; 3905 __le64 rx_agg_bytes; 3906 __le64 rx_agg_events; 3907 __le64 rx_agg_aborts; 3908 __le32 unused_0; 3909 u8 unused_1; 3910 u8 unused_2; 3911 u8 unused_3; 3912 u8 valid; 3913 }; 3914 3915 /* hwrm_stat_ctx_clr_stats */ 3916 /* Input (24 bytes) */ 3917 struct hwrm_stat_ctx_clr_stats_input { 3918 __le16 req_type; 3919 __le16 cmpl_ring; 3920 __le16 seq_id; 3921 __le16 target_id; 3922 __le64 resp_addr; 3923 __le32 stat_ctx_id; 3924 __le32 unused_0; 3925 }; 3926 3927 /* Output (16 bytes) */ 3928 struct hwrm_stat_ctx_clr_stats_output { 3929 __le16 error_code; 3930 __le16 req_type; 3931 __le16 seq_id; 3932 __le16 resp_len; 3933 __le32 unused_0; 3934 u8 unused_1; 3935 u8 unused_2; 3936 u8 unused_3; 3937 u8 valid; 3938 }; 3939 3940 /* hwrm_fw_reset */ 3941 /* Input (24 bytes) */ 3942 struct hwrm_fw_reset_input { 3943 __le16 req_type; 3944 __le16 cmpl_ring; 3945 __le16 seq_id; 3946 __le16 target_id; 3947 __le64 resp_addr; 3948 u8 embedded_proc_type; 3949 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 3950 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 3951 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 3952 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 3953 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 3954 u8 selfrst_status; 3955 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 3956 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 3957 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3958 __le16 unused_0[3]; 3959 }; 3960 3961 /* Output (16 bytes) */ 3962 struct hwrm_fw_reset_output { 3963 __le16 error_code; 3964 __le16 req_type; 3965 __le16 seq_id; 3966 __le16 resp_len; 3967 u8 selfrst_status; 3968 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 3969 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 3970 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 3971 u8 unused_0; 3972 __le16 unused_1; 3973 u8 unused_2; 3974 u8 unused_3; 3975 u8 unused_4; 3976 u8 valid; 3977 }; 3978 3979 /* hwrm_fw_qstatus */ 3980 /* Input (24 bytes) */ 3981 struct hwrm_fw_qstatus_input { 3982 __le16 req_type; 3983 __le16 cmpl_ring; 3984 __le16 seq_id; 3985 __le16 target_id; 3986 __le64 resp_addr; 3987 u8 embedded_proc_type; 3988 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 3989 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 3990 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 3991 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 3992 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 3993 u8 unused_0[7]; 3994 }; 3995 3996 /* Output (16 bytes) */ 3997 struct hwrm_fw_qstatus_output { 3998 __le16 error_code; 3999 __le16 req_type; 4000 __le16 seq_id; 4001 __le16 resp_len; 4002 u8 selfrst_status; 4003 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4004 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4005 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4006 u8 unused_0; 4007 __le16 unused_1; 4008 u8 unused_2; 4009 u8 unused_3; 4010 u8 unused_4; 4011 u8 valid; 4012 }; 4013 4014 /* hwrm_fw_set_time */ 4015 /* Input (32 bytes) */ 4016 struct hwrm_fw_set_time_input { 4017 __le16 req_type; 4018 __le16 cmpl_ring; 4019 __le16 seq_id; 4020 __le16 target_id; 4021 __le64 resp_addr; 4022 __le16 year; 4023 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4024 u8 month; 4025 u8 day; 4026 u8 hour; 4027 u8 minute; 4028 u8 second; 4029 u8 unused_0; 4030 __le16 millisecond; 4031 __le16 zone; 4032 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4033 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4034 __le32 unused_1; 4035 }; 4036 4037 /* Output (16 bytes) */ 4038 struct hwrm_fw_set_time_output { 4039 __le16 error_code; 4040 __le16 req_type; 4041 __le16 seq_id; 4042 __le16 resp_len; 4043 __le32 unused_0; 4044 u8 unused_1; 4045 u8 unused_2; 4046 u8 unused_3; 4047 u8 valid; 4048 }; 4049 4050 /* hwrm_fw_set_structured_data */ 4051 /* Input (32 bytes) */ 4052 struct hwrm_fw_set_structured_data_input { 4053 __le16 req_type; 4054 __le16 cmpl_ring; 4055 __le16 seq_id; 4056 __le16 target_id; 4057 __le64 resp_addr; 4058 __le64 src_data_addr; 4059 __le16 data_len; 4060 u8 hdr_cnt; 4061 u8 unused_0; 4062 __le16 port_id; 4063 __le16 unused_1; 4064 }; 4065 4066 /* Output (16 bytes) */ 4067 struct hwrm_fw_set_structured_data_output { 4068 __le16 error_code; 4069 __le16 req_type; 4070 __le16 seq_id; 4071 __le16 resp_len; 4072 __le32 unused_0; 4073 u8 unused_1; 4074 u8 unused_2; 4075 u8 unused_3; 4076 u8 valid; 4077 }; 4078 4079 /* hwrm_fw_get_structured_data */ 4080 /* Input (40 bytes) */ 4081 struct hwrm_fw_get_structured_data_input { 4082 __le16 req_type; 4083 __le16 cmpl_ring; 4084 __le16 seq_id; 4085 __le16 target_id; 4086 __le64 resp_addr; 4087 __le64 dest_data_addr; 4088 __le16 data_len; 4089 __le16 structure_id; 4090 __le16 subtype; 4091 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 4092 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 4093 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 4094 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 4095 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 4096 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 4097 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 4098 u8 count; 4099 u8 unused_0; 4100 __le16 port_id; 4101 __le16 unused_1[3]; 4102 }; 4103 4104 /* Output (16 bytes) */ 4105 struct hwrm_fw_get_structured_data_output { 4106 __le16 error_code; 4107 __le16 req_type; 4108 __le16 seq_id; 4109 __le16 resp_len; 4110 u8 hdr_cnt; 4111 u8 unused_0; 4112 __le16 unused_1; 4113 u8 unused_2; 4114 u8 unused_3; 4115 u8 unused_4; 4116 u8 valid; 4117 }; 4118 4119 /* hwrm_exec_fwd_resp */ 4120 /* Input (128 bytes) */ 4121 struct hwrm_exec_fwd_resp_input { 4122 __le16 req_type; 4123 __le16 cmpl_ring; 4124 __le16 seq_id; 4125 __le16 target_id; 4126 __le64 resp_addr; 4127 __le32 encap_request[26]; 4128 __le16 encap_resp_target_id; 4129 __le16 unused_0[3]; 4130 }; 4131 4132 /* Output (16 bytes) */ 4133 struct hwrm_exec_fwd_resp_output { 4134 __le16 error_code; 4135 __le16 req_type; 4136 __le16 seq_id; 4137 __le16 resp_len; 4138 __le32 unused_0; 4139 u8 unused_1; 4140 u8 unused_2; 4141 u8 unused_3; 4142 u8 valid; 4143 }; 4144 4145 /* hwrm_reject_fwd_resp */ 4146 /* Input (128 bytes) */ 4147 struct hwrm_reject_fwd_resp_input { 4148 __le16 req_type; 4149 __le16 cmpl_ring; 4150 __le16 seq_id; 4151 __le16 target_id; 4152 __le64 resp_addr; 4153 __le32 encap_request[26]; 4154 __le16 encap_resp_target_id; 4155 __le16 unused_0[3]; 4156 }; 4157 4158 /* Output (16 bytes) */ 4159 struct hwrm_reject_fwd_resp_output { 4160 __le16 error_code; 4161 __le16 req_type; 4162 __le16 seq_id; 4163 __le16 resp_len; 4164 __le32 unused_0; 4165 u8 unused_1; 4166 u8 unused_2; 4167 u8 unused_3; 4168 u8 valid; 4169 }; 4170 4171 /* hwrm_fwd_resp */ 4172 /* Input (40 bytes) */ 4173 struct hwrm_fwd_resp_input { 4174 __le16 req_type; 4175 __le16 cmpl_ring; 4176 __le16 seq_id; 4177 __le16 target_id; 4178 __le64 resp_addr; 4179 __le16 encap_resp_target_id; 4180 __le16 encap_resp_cmpl_ring; 4181 __le16 encap_resp_len; 4182 u8 unused_0; 4183 u8 unused_1; 4184 __le64 encap_resp_addr; 4185 __le32 encap_resp[24]; 4186 }; 4187 4188 /* Output (16 bytes) */ 4189 struct hwrm_fwd_resp_output { 4190 __le16 error_code; 4191 __le16 req_type; 4192 __le16 seq_id; 4193 __le16 resp_len; 4194 __le32 unused_0; 4195 u8 unused_1; 4196 u8 unused_2; 4197 u8 unused_3; 4198 u8 valid; 4199 }; 4200 4201 /* hwrm_fwd_async_event_cmpl */ 4202 /* Input (32 bytes) */ 4203 struct hwrm_fwd_async_event_cmpl_input { 4204 __le16 req_type; 4205 __le16 cmpl_ring; 4206 __le16 seq_id; 4207 __le16 target_id; 4208 __le64 resp_addr; 4209 __le16 encap_async_event_target_id; 4210 u8 unused_0; 4211 u8 unused_1; 4212 u8 unused_2[3]; 4213 u8 unused_3; 4214 __le32 encap_async_event_cmpl[4]; 4215 }; 4216 4217 /* Output (16 bytes) */ 4218 struct hwrm_fwd_async_event_cmpl_output { 4219 __le16 error_code; 4220 __le16 req_type; 4221 __le16 seq_id; 4222 __le16 resp_len; 4223 __le32 unused_0; 4224 u8 unused_1; 4225 u8 unused_2; 4226 u8 unused_3; 4227 u8 valid; 4228 }; 4229 4230 /* hwrm_temp_monitor_query */ 4231 /* Input (16 bytes) */ 4232 struct hwrm_temp_monitor_query_input { 4233 __le16 req_type; 4234 __le16 cmpl_ring; 4235 __le16 seq_id; 4236 __le16 target_id; 4237 __le64 resp_addr; 4238 }; 4239 4240 /* Output (16 bytes) */ 4241 struct hwrm_temp_monitor_query_output { 4242 __le16 error_code; 4243 __le16 req_type; 4244 __le16 seq_id; 4245 __le16 resp_len; 4246 u8 temp; 4247 u8 unused_0; 4248 __le16 unused_1; 4249 u8 unused_2; 4250 u8 unused_3; 4251 u8 unused_4; 4252 u8 valid; 4253 }; 4254 4255 /* hwrm_nvm_read */ 4256 /* Input (40 bytes) */ 4257 struct hwrm_nvm_read_input { 4258 __le16 req_type; 4259 __le16 cmpl_ring; 4260 __le16 seq_id; 4261 __le16 target_id; 4262 __le64 resp_addr; 4263 __le64 host_dest_addr; 4264 __le16 dir_idx; 4265 u8 unused_0; 4266 u8 unused_1; 4267 __le32 offset; 4268 __le32 len; 4269 __le32 unused_2; 4270 }; 4271 4272 /* Output (16 bytes) */ 4273 struct hwrm_nvm_read_output { 4274 __le16 error_code; 4275 __le16 req_type; 4276 __le16 seq_id; 4277 __le16 resp_len; 4278 __le32 unused_0; 4279 u8 unused_1; 4280 u8 unused_2; 4281 u8 unused_3; 4282 u8 valid; 4283 }; 4284 4285 /* hwrm_nvm_raw_dump */ 4286 /* Input (32 bytes) */ 4287 struct hwrm_nvm_raw_dump_input { 4288 __le16 req_type; 4289 __le16 cmpl_ring; 4290 __le16 seq_id; 4291 __le16 target_id; 4292 __le64 resp_addr; 4293 __le64 host_dest_addr; 4294 __le32 offset; 4295 __le32 len; 4296 }; 4297 4298 /* Output (16 bytes) */ 4299 struct hwrm_nvm_raw_dump_output { 4300 __le16 error_code; 4301 __le16 req_type; 4302 __le16 seq_id; 4303 __le16 resp_len; 4304 __le32 unused_0; 4305 u8 unused_1; 4306 u8 unused_2; 4307 u8 unused_3; 4308 u8 valid; 4309 }; 4310 4311 /* hwrm_nvm_get_dir_entries */ 4312 /* Input (24 bytes) */ 4313 struct hwrm_nvm_get_dir_entries_input { 4314 __le16 req_type; 4315 __le16 cmpl_ring; 4316 __le16 seq_id; 4317 __le16 target_id; 4318 __le64 resp_addr; 4319 __le64 host_dest_addr; 4320 }; 4321 4322 /* Output (16 bytes) */ 4323 struct hwrm_nvm_get_dir_entries_output { 4324 __le16 error_code; 4325 __le16 req_type; 4326 __le16 seq_id; 4327 __le16 resp_len; 4328 __le32 unused_0; 4329 u8 unused_1; 4330 u8 unused_2; 4331 u8 unused_3; 4332 u8 valid; 4333 }; 4334 4335 /* hwrm_nvm_get_dir_info */ 4336 /* Input (16 bytes) */ 4337 struct hwrm_nvm_get_dir_info_input { 4338 __le16 req_type; 4339 __le16 cmpl_ring; 4340 __le16 seq_id; 4341 __le16 target_id; 4342 __le64 resp_addr; 4343 }; 4344 4345 /* Output (24 bytes) */ 4346 struct hwrm_nvm_get_dir_info_output { 4347 __le16 error_code; 4348 __le16 req_type; 4349 __le16 seq_id; 4350 __le16 resp_len; 4351 __le32 entries; 4352 __le32 entry_length; 4353 __le32 unused_0; 4354 u8 unused_1; 4355 u8 unused_2; 4356 u8 unused_3; 4357 u8 valid; 4358 }; 4359 4360 /* hwrm_nvm_write */ 4361 /* Input (48 bytes) */ 4362 struct hwrm_nvm_write_input { 4363 __le16 req_type; 4364 __le16 cmpl_ring; 4365 __le16 seq_id; 4366 __le16 target_id; 4367 __le64 resp_addr; 4368 __le64 host_src_addr; 4369 __le16 dir_type; 4370 __le16 dir_ordinal; 4371 __le16 dir_ext; 4372 __le16 dir_attr; 4373 __le32 dir_data_length; 4374 __le16 option; 4375 __le16 flags; 4376 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 4377 __le32 dir_item_length; 4378 __le32 unused_0; 4379 }; 4380 4381 /* Output (16 bytes) */ 4382 struct hwrm_nvm_write_output { 4383 __le16 error_code; 4384 __le16 req_type; 4385 __le16 seq_id; 4386 __le16 resp_len; 4387 __le32 dir_item_length; 4388 __le16 dir_idx; 4389 u8 unused_0; 4390 u8 valid; 4391 }; 4392 4393 /* hwrm_nvm_modify */ 4394 /* Input (40 bytes) */ 4395 struct hwrm_nvm_modify_input { 4396 __le16 req_type; 4397 __le16 cmpl_ring; 4398 __le16 seq_id; 4399 __le16 target_id; 4400 __le64 resp_addr; 4401 __le64 host_src_addr; 4402 __le16 dir_idx; 4403 u8 unused_0; 4404 u8 unused_1; 4405 __le32 offset; 4406 __le32 len; 4407 __le32 unused_2; 4408 }; 4409 4410 /* Output (16 bytes) */ 4411 struct hwrm_nvm_modify_output { 4412 __le16 error_code; 4413 __le16 req_type; 4414 __le16 seq_id; 4415 __le16 resp_len; 4416 __le32 unused_0; 4417 u8 unused_1; 4418 u8 unused_2; 4419 u8 unused_3; 4420 u8 valid; 4421 }; 4422 4423 /* hwrm_nvm_find_dir_entry */ 4424 /* Input (32 bytes) */ 4425 struct hwrm_nvm_find_dir_entry_input { 4426 __le16 req_type; 4427 __le16 cmpl_ring; 4428 __le16 seq_id; 4429 __le16 target_id; 4430 __le64 resp_addr; 4431 __le32 enables; 4432 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 4433 __le16 dir_idx; 4434 __le16 dir_type; 4435 __le16 dir_ordinal; 4436 __le16 dir_ext; 4437 u8 opt_ordinal; 4438 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 4439 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 4440 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 4441 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 4442 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 4443 u8 unused_1[3]; 4444 }; 4445 4446 /* Output (32 bytes) */ 4447 struct hwrm_nvm_find_dir_entry_output { 4448 __le16 error_code; 4449 __le16 req_type; 4450 __le16 seq_id; 4451 __le16 resp_len; 4452 __le32 dir_item_length; 4453 __le32 dir_data_length; 4454 __le32 fw_ver; 4455 __le16 dir_ordinal; 4456 __le16 dir_idx; 4457 __le32 unused_0; 4458 u8 unused_1; 4459 u8 unused_2; 4460 u8 unused_3; 4461 u8 valid; 4462 }; 4463 4464 /* hwrm_nvm_erase_dir_entry */ 4465 /* Input (24 bytes) */ 4466 struct hwrm_nvm_erase_dir_entry_input { 4467 __le16 req_type; 4468 __le16 cmpl_ring; 4469 __le16 seq_id; 4470 __le16 target_id; 4471 __le64 resp_addr; 4472 __le16 dir_idx; 4473 __le16 unused_0[3]; 4474 }; 4475 4476 /* Output (16 bytes) */ 4477 struct hwrm_nvm_erase_dir_entry_output { 4478 __le16 error_code; 4479 __le16 req_type; 4480 __le16 seq_id; 4481 __le16 resp_len; 4482 __le32 unused_0; 4483 u8 unused_1; 4484 u8 unused_2; 4485 u8 unused_3; 4486 u8 valid; 4487 }; 4488 4489 /* hwrm_nvm_get_dev_info */ 4490 /* Input (16 bytes) */ 4491 struct hwrm_nvm_get_dev_info_input { 4492 __le16 req_type; 4493 __le16 cmpl_ring; 4494 __le16 seq_id; 4495 __le16 target_id; 4496 __le64 resp_addr; 4497 }; 4498 4499 /* Output (32 bytes) */ 4500 struct hwrm_nvm_get_dev_info_output { 4501 __le16 error_code; 4502 __le16 req_type; 4503 __le16 seq_id; 4504 __le16 resp_len; 4505 __le16 manufacturer_id; 4506 __le16 device_id; 4507 __le32 sector_size; 4508 __le32 nvram_size; 4509 __le32 reserved_size; 4510 __le32 available_size; 4511 u8 unused_0; 4512 u8 unused_1; 4513 u8 unused_2; 4514 u8 valid; 4515 }; 4516 4517 /* hwrm_nvm_mod_dir_entry */ 4518 /* Input (32 bytes) */ 4519 struct hwrm_nvm_mod_dir_entry_input { 4520 __le16 req_type; 4521 __le16 cmpl_ring; 4522 __le16 seq_id; 4523 __le16 target_id; 4524 __le64 resp_addr; 4525 __le32 enables; 4526 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 4527 __le16 dir_idx; 4528 __le16 dir_ordinal; 4529 __le16 dir_ext; 4530 __le16 dir_attr; 4531 __le32 checksum; 4532 }; 4533 4534 /* Output (16 bytes) */ 4535 struct hwrm_nvm_mod_dir_entry_output { 4536 __le16 error_code; 4537 __le16 req_type; 4538 __le16 seq_id; 4539 __le16 resp_len; 4540 __le32 unused_0; 4541 u8 unused_1; 4542 u8 unused_2; 4543 u8 unused_3; 4544 u8 valid; 4545 }; 4546 4547 /* hwrm_nvm_verify_update */ 4548 /* Input (24 bytes) */ 4549 struct hwrm_nvm_verify_update_input { 4550 __le16 req_type; 4551 __le16 cmpl_ring; 4552 __le16 seq_id; 4553 __le16 target_id; 4554 __le64 resp_addr; 4555 __le16 dir_type; 4556 __le16 dir_ordinal; 4557 __le16 dir_ext; 4558 __le16 unused_0; 4559 }; 4560 4561 /* Output (16 bytes) */ 4562 struct hwrm_nvm_verify_update_output { 4563 __le16 error_code; 4564 __le16 req_type; 4565 __le16 seq_id; 4566 __le16 resp_len; 4567 __le32 unused_0; 4568 u8 unused_1; 4569 u8 unused_2; 4570 u8 unused_3; 4571 u8 valid; 4572 }; 4573 4574 /* hwrm_nvm_install_update */ 4575 /* Input (24 bytes) */ 4576 struct hwrm_nvm_install_update_input { 4577 __le16 req_type; 4578 __le16 cmpl_ring; 4579 __le16 seq_id; 4580 __le16 target_id; 4581 __le64 resp_addr; 4582 __le32 install_type; 4583 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 4584 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 4585 __le32 unused_0; 4586 }; 4587 4588 /* Output (24 bytes) */ 4589 struct hwrm_nvm_install_update_output { 4590 __le16 error_code; 4591 __le16 req_type; 4592 __le16 seq_id; 4593 __le16 resp_len; 4594 __le64 installed_items; 4595 u8 result; 4596 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 4597 u8 problem_item; 4598 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 4599 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 4600 u8 reset_required; 4601 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 4602 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 4603 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 4604 u8 unused_0; 4605 u8 unused_1; 4606 u8 unused_2; 4607 u8 unused_3; 4608 u8 valid; 4609 }; 4610 4611 /* Hardware Resource Manager Specification */ 4612 /* Input (16 bytes) */ 4613 struct input { 4614 __le16 req_type; 4615 __le16 cmpl_ring; 4616 __le16 seq_id; 4617 __le16 target_id; 4618 __le64 resp_addr; 4619 }; 4620 4621 /* Output (8 bytes) */ 4622 struct output { 4623 __le16 error_code; 4624 __le16 req_type; 4625 __le16 seq_id; 4626 __le16 resp_len; 4627 }; 4628 4629 /* Command numbering (8 bytes) */ 4630 struct cmd_nums { 4631 __le16 req_type; 4632 #define HWRM_VER_GET (0x0UL) 4633 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 4634 #define HWRM_FUNC_VF_CFG (0xfUL) 4635 #define RESERVED1 (0x10UL) 4636 #define HWRM_FUNC_RESET (0x11UL) 4637 #define HWRM_FUNC_GETFID (0x12UL) 4638 #define HWRM_FUNC_VF_ALLOC (0x13UL) 4639 #define HWRM_FUNC_VF_FREE (0x14UL) 4640 #define HWRM_FUNC_QCAPS (0x15UL) 4641 #define HWRM_FUNC_QCFG (0x16UL) 4642 #define HWRM_FUNC_CFG (0x17UL) 4643 #define HWRM_FUNC_QSTATS (0x18UL) 4644 #define HWRM_FUNC_CLR_STATS (0x19UL) 4645 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 4646 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 4647 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 4648 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 4649 #define HWRM_FUNC_DRV_QVER (0x1eUL) 4650 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 4651 #define HWRM_PORT_PHY_CFG (0x20UL) 4652 #define HWRM_PORT_MAC_CFG (0x21UL) 4653 #define HWRM_PORT_TS_QUERY (0x22UL) 4654 #define HWRM_PORT_QSTATS (0x23UL) 4655 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 4656 #define HWRM_PORT_CLR_STATS (0x25UL) 4657 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 4658 #define HWRM_PORT_PHY_QCFG (0x27UL) 4659 #define HWRM_PORT_MAC_QCFG (0x28UL) 4660 #define RESERVED7 (0x29UL) 4661 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 4662 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 4663 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 4664 #define HWRM_PORT_LED_CFG (0x2dUL) 4665 #define HWRM_PORT_LED_QCFG (0x2eUL) 4666 #define HWRM_PORT_LED_QCAPS (0x2fUL) 4667 #define HWRM_QUEUE_QPORTCFG (0x30UL) 4668 #define HWRM_QUEUE_QCFG (0x31UL) 4669 #define HWRM_QUEUE_CFG (0x32UL) 4670 #define RESERVED2 (0x33UL) 4671 #define RESERVED3 (0x34UL) 4672 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 4673 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 4674 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 4675 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 4676 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 4677 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 4678 #define HWRM_VNIC_ALLOC (0x40UL) 4679 #define HWRM_VNIC_FREE (0x41UL) 4680 #define HWRM_VNIC_CFG (0x42UL) 4681 #define HWRM_VNIC_QCFG (0x43UL) 4682 #define HWRM_VNIC_TPA_CFG (0x44UL) 4683 #define HWRM_VNIC_TPA_QCFG (0x45UL) 4684 #define HWRM_VNIC_RSS_CFG (0x46UL) 4685 #define HWRM_VNIC_RSS_QCFG (0x47UL) 4686 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 4687 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 4688 #define HWRM_VNIC_QCAPS (0x4aUL) 4689 #define HWRM_RING_ALLOC (0x50UL) 4690 #define HWRM_RING_FREE (0x51UL) 4691 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 4692 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 4693 #define HWRM_RING_RESET (0x5eUL) 4694 #define HWRM_RING_GRP_ALLOC (0x60UL) 4695 #define HWRM_RING_GRP_FREE (0x61UL) 4696 #define RESERVED5 (0x64UL) 4697 #define RESERVED6 (0x65UL) 4698 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 4699 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 4700 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 4701 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 4702 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 4703 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 4704 #define RESERVED4 (0x94UL) 4705 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 4706 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 4707 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 4708 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 4709 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 4710 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 4711 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 4712 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 4713 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 4714 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 4715 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 4716 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 4717 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 4718 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 4719 #define HWRM_STAT_CTX_FREE (0xb1UL) 4720 #define HWRM_STAT_CTX_QUERY (0xb2UL) 4721 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 4722 #define HWRM_FW_RESET (0xc0UL) 4723 #define HWRM_FW_QSTATUS (0xc1UL) 4724 #define HWRM_FW_SET_TIME (0xc8UL) 4725 #define HWRM_FW_GET_TIME (0xc9UL) 4726 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 4727 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 4728 #define HWRM_FW_IPC_MAILBOX (0xccUL) 4729 #define HWRM_EXEC_FWD_RESP (0xd0UL) 4730 #define HWRM_REJECT_FWD_RESP (0xd1UL) 4731 #define HWRM_FWD_RESP (0xd2UL) 4732 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 4733 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 4734 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 4735 #define HWRM_WOL_FILTER_FREE (0xf1UL) 4736 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 4737 #define HWRM_WOL_REASON_QCFG (0xf3UL) 4738 #define HWRM_DBG_READ_DIRECT (0xff10UL) 4739 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 4740 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 4741 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 4742 #define HWRM_DBG_DUMP (0xff14UL) 4743 #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 4744 #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 4745 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 4746 #define HWRM_NVM_MODIFY (0xfff4UL) 4747 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 4748 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 4749 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 4750 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 4751 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 4752 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 4753 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 4754 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 4755 #define HWRM_NVM_READ (0xfffdUL) 4756 #define HWRM_NVM_WRITE (0xfffeUL) 4757 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 4758 __le16 unused_0[3]; 4759 }; 4760 4761 /* Return Codes (8 bytes) */ 4762 struct ret_codes { 4763 __le16 error_code; 4764 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 4765 #define HWRM_ERR_CODE_FAIL (0x1UL) 4766 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 4767 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 4768 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 4769 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 4770 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 4771 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 4772 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 4773 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 4774 __le16 unused_0[3]; 4775 }; 4776 4777 /* Output (16 bytes) */ 4778 struct hwrm_err_output { 4779 __le16 error_code; 4780 __le16 req_type; 4781 __le16 seq_id; 4782 __le16 resp_len; 4783 __le32 opaque_0; 4784 __le16 opaque_1; 4785 u8 cmd_err; 4786 u8 valid; 4787 }; 4788 4789 /* Port Tx Statistics Formats (408 bytes) */ 4790 struct tx_port_stats { 4791 __le64 tx_64b_frames; 4792 __le64 tx_65b_127b_frames; 4793 __le64 tx_128b_255b_frames; 4794 __le64 tx_256b_511b_frames; 4795 __le64 tx_512b_1023b_frames; 4796 __le64 tx_1024b_1518_frames; 4797 __le64 tx_good_vlan_frames; 4798 __le64 tx_1519b_2047_frames; 4799 __le64 tx_2048b_4095b_frames; 4800 __le64 tx_4096b_9216b_frames; 4801 __le64 tx_9217b_16383b_frames; 4802 __le64 tx_good_frames; 4803 __le64 tx_total_frames; 4804 __le64 tx_ucast_frames; 4805 __le64 tx_mcast_frames; 4806 __le64 tx_bcast_frames; 4807 __le64 tx_pause_frames; 4808 __le64 tx_pfc_frames; 4809 __le64 tx_jabber_frames; 4810 __le64 tx_fcs_err_frames; 4811 __le64 tx_control_frames; 4812 __le64 tx_oversz_frames; 4813 __le64 tx_single_dfrl_frames; 4814 __le64 tx_multi_dfrl_frames; 4815 __le64 tx_single_coll_frames; 4816 __le64 tx_multi_coll_frames; 4817 __le64 tx_late_coll_frames; 4818 __le64 tx_excessive_coll_frames; 4819 __le64 tx_frag_frames; 4820 __le64 tx_err; 4821 __le64 tx_tagged_frames; 4822 __le64 tx_dbl_tagged_frames; 4823 __le64 tx_runt_frames; 4824 __le64 tx_fifo_underruns; 4825 __le64 tx_pfc_ena_frames_pri0; 4826 __le64 tx_pfc_ena_frames_pri1; 4827 __le64 tx_pfc_ena_frames_pri2; 4828 __le64 tx_pfc_ena_frames_pri3; 4829 __le64 tx_pfc_ena_frames_pri4; 4830 __le64 tx_pfc_ena_frames_pri5; 4831 __le64 tx_pfc_ena_frames_pri6; 4832 __le64 tx_pfc_ena_frames_pri7; 4833 __le64 tx_eee_lpi_events; 4834 __le64 tx_eee_lpi_duration; 4835 __le64 tx_llfc_logical_msgs; 4836 __le64 tx_hcfc_msgs; 4837 __le64 tx_total_collisions; 4838 __le64 tx_bytes; 4839 __le64 tx_xthol_frames; 4840 __le64 tx_stat_discard; 4841 __le64 tx_stat_error; 4842 }; 4843 4844 /* Port Rx Statistics Formats (528 bytes) */ 4845 struct rx_port_stats { 4846 __le64 rx_64b_frames; 4847 __le64 rx_65b_127b_frames; 4848 __le64 rx_128b_255b_frames; 4849 __le64 rx_256b_511b_frames; 4850 __le64 rx_512b_1023b_frames; 4851 __le64 rx_1024b_1518_frames; 4852 __le64 rx_good_vlan_frames; 4853 __le64 rx_1519b_2047b_frames; 4854 __le64 rx_2048b_4095b_frames; 4855 __le64 rx_4096b_9216b_frames; 4856 __le64 rx_9217b_16383b_frames; 4857 __le64 rx_total_frames; 4858 __le64 rx_ucast_frames; 4859 __le64 rx_mcast_frames; 4860 __le64 rx_bcast_frames; 4861 __le64 rx_fcs_err_frames; 4862 __le64 rx_ctrl_frames; 4863 __le64 rx_pause_frames; 4864 __le64 rx_pfc_frames; 4865 __le64 rx_unsupported_opcode_frames; 4866 __le64 rx_unsupported_da_pausepfc_frames; 4867 __le64 rx_wrong_sa_frames; 4868 __le64 rx_align_err_frames; 4869 __le64 rx_oor_len_frames; 4870 __le64 rx_code_err_frames; 4871 __le64 rx_false_carrier_frames; 4872 __le64 rx_ovrsz_frames; 4873 __le64 rx_jbr_frames; 4874 __le64 rx_mtu_err_frames; 4875 __le64 rx_match_crc_frames; 4876 __le64 rx_promiscuous_frames; 4877 __le64 rx_tagged_frames; 4878 __le64 rx_double_tagged_frames; 4879 __le64 rx_trunc_frames; 4880 __le64 rx_good_frames; 4881 __le64 rx_pfc_xon2xoff_frames_pri0; 4882 __le64 rx_pfc_xon2xoff_frames_pri1; 4883 __le64 rx_pfc_xon2xoff_frames_pri2; 4884 __le64 rx_pfc_xon2xoff_frames_pri3; 4885 __le64 rx_pfc_xon2xoff_frames_pri4; 4886 __le64 rx_pfc_xon2xoff_frames_pri5; 4887 __le64 rx_pfc_xon2xoff_frames_pri6; 4888 __le64 rx_pfc_xon2xoff_frames_pri7; 4889 __le64 rx_pfc_ena_frames_pri0; 4890 __le64 rx_pfc_ena_frames_pri1; 4891 __le64 rx_pfc_ena_frames_pri2; 4892 __le64 rx_pfc_ena_frames_pri3; 4893 __le64 rx_pfc_ena_frames_pri4; 4894 __le64 rx_pfc_ena_frames_pri5; 4895 __le64 rx_pfc_ena_frames_pri6; 4896 __le64 rx_pfc_ena_frames_pri7; 4897 __le64 rx_sch_crc_err_frames; 4898 __le64 rx_undrsz_frames; 4899 __le64 rx_frag_frames; 4900 __le64 rx_eee_lpi_events; 4901 __le64 rx_eee_lpi_duration; 4902 __le64 rx_llfc_physical_msgs; 4903 __le64 rx_llfc_logical_msgs; 4904 __le64 rx_llfc_msgs_with_crc_err; 4905 __le64 rx_hcfc_msgs; 4906 __le64 rx_hcfc_msgs_with_crc_err; 4907 __le64 rx_bytes; 4908 __le64 rx_runt_bytes; 4909 __le64 rx_runt_frames; 4910 __le64 rx_stat_discard; 4911 __le64 rx_stat_err; 4912 }; 4913 4914 /* Periodic Statistics Context DMA to host (160 bytes) */ 4915 struct ctx_hw_stats { 4916 __le64 rx_ucast_pkts; 4917 __le64 rx_mcast_pkts; 4918 __le64 rx_bcast_pkts; 4919 __le64 rx_discard_pkts; 4920 __le64 rx_drop_pkts; 4921 __le64 rx_ucast_bytes; 4922 __le64 rx_mcast_bytes; 4923 __le64 rx_bcast_bytes; 4924 __le64 tx_ucast_pkts; 4925 __le64 tx_mcast_pkts; 4926 __le64 tx_bcast_pkts; 4927 __le64 tx_discard_pkts; 4928 __le64 tx_drop_pkts; 4929 __le64 tx_ucast_bytes; 4930 __le64 tx_mcast_bytes; 4931 __le64 tx_bcast_bytes; 4932 __le64 tpa_pkts; 4933 __le64 tpa_bytes; 4934 __le64 tpa_events; 4935 __le64 tpa_aborts; 4936 }; 4937 4938 /* Structure data header (16 bytes) */ 4939 struct hwrm_struct_hdr { 4940 __le16 struct_id; 4941 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 4942 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS_CFG 0x41dUL 4943 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC_CFG 0x41fUL 4944 #define STRUCT_HDR_STRUCT_ID_DCBX_APP_CFG 0x421UL 4945 #define STRUCT_HDR_STRUCT_ID_DCBX_STATE_CFG 0x422UL 4946 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC_CFG 0x424UL 4947 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE_CFG 0x426UL 4948 __le16 len; 4949 u8 version; 4950 u8 count; 4951 __le16 subtype; 4952 __le16 next_offset; 4953 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 4954 __le16 unused_0[3]; 4955 }; 4956 4957 /* DCBX Application configuration structure (8 bytes) */ 4958 struct hwrm_struct_data_dcbx_app_cfg { 4959 __le16 protocol_id; 4960 u8 protocol_selector; 4961 #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 4962 #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 4963 #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 4964 #define STRUCT_DATA_DCBX_APP_CFG_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 4965 u8 priority; 4966 u8 valid; 4967 u8 unused_0[3]; 4968 }; 4969 4970 #endif 4971