1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2021 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110 #define HWRM_FUNC_VF_CFG 0xfUL 111 #define HWRM_RESERVED1 0x10UL 112 #define HWRM_FUNC_RESET 0x11UL 113 #define HWRM_FUNC_GETFID 0x12UL 114 #define HWRM_FUNC_VF_ALLOC 0x13UL 115 #define HWRM_FUNC_VF_FREE 0x14UL 116 #define HWRM_FUNC_QCAPS 0x15UL 117 #define HWRM_FUNC_QCFG 0x16UL 118 #define HWRM_FUNC_CFG 0x17UL 119 #define HWRM_FUNC_QSTATS 0x18UL 120 #define HWRM_FUNC_CLR_STATS 0x19UL 121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124 #define HWRM_FUNC_DRV_RGTR 0x1dUL 125 #define HWRM_FUNC_DRV_QVER 0x1eUL 126 #define HWRM_FUNC_BUF_RGTR 0x1fUL 127 #define HWRM_PORT_PHY_CFG 0x20UL 128 #define HWRM_PORT_MAC_CFG 0x21UL 129 #define HWRM_PORT_TS_QUERY 0x22UL 130 #define HWRM_PORT_QSTATS 0x23UL 131 #define HWRM_PORT_LPBK_QSTATS 0x24UL 132 #define HWRM_PORT_CLR_STATS 0x25UL 133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134 #define HWRM_PORT_PHY_QCFG 0x27UL 135 #define HWRM_PORT_MAC_QCFG 0x28UL 136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137 #define HWRM_PORT_PHY_QCAPS 0x2aUL 138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140 #define HWRM_PORT_LED_CFG 0x2dUL 141 #define HWRM_PORT_LED_QCFG 0x2eUL 142 #define HWRM_PORT_LED_QCAPS 0x2fUL 143 #define HWRM_QUEUE_QPORTCFG 0x30UL 144 #define HWRM_QUEUE_QCFG 0x31UL 145 #define HWRM_QUEUE_CFG 0x32UL 146 #define HWRM_FUNC_VLAN_CFG 0x33UL 147 #define HWRM_FUNC_VLAN_QCFG 0x34UL 148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157 #define HWRM_VNIC_ALLOC 0x40UL 158 #define HWRM_VNIC_FREE 0x41UL 159 #define HWRM_VNIC_CFG 0x42UL 160 #define HWRM_VNIC_QCFG 0x43UL 161 #define HWRM_VNIC_TPA_CFG 0x44UL 162 #define HWRM_VNIC_TPA_QCFG 0x45UL 163 #define HWRM_VNIC_RSS_CFG 0x46UL 164 #define HWRM_VNIC_RSS_QCFG 0x47UL 165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167 #define HWRM_VNIC_QCAPS 0x4aUL 168 #define HWRM_VNIC_UPDATE 0x4bUL 169 #define HWRM_RING_ALLOC 0x50UL 170 #define HWRM_RING_FREE 0x51UL 171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 173 #define HWRM_RING_AGGINT_QCAPS 0x54UL 174 #define HWRM_RING_SCHQ_ALLOC 0x55UL 175 #define HWRM_RING_SCHQ_CFG 0x56UL 176 #define HWRM_RING_SCHQ_FREE 0x57UL 177 #define HWRM_RING_RESET 0x5eUL 178 #define HWRM_RING_GRP_ALLOC 0x60UL 179 #define HWRM_RING_GRP_FREE 0x61UL 180 #define HWRM_RING_CFG 0x62UL 181 #define HWRM_RING_QCFG 0x63UL 182 #define HWRM_RESERVED5 0x64UL 183 #define HWRM_RESERVED6 0x65UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 192 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 193 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 194 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 195 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 196 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 197 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 198 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 199 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 200 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 201 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 202 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 203 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 204 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 205 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 206 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 207 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 208 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 209 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 210 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 211 #define HWRM_STAT_CTX_ALLOC 0xb0UL 212 #define HWRM_STAT_CTX_FREE 0xb1UL 213 #define HWRM_STAT_CTX_QUERY 0xb2UL 214 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 215 #define HWRM_PORT_QSTATS_EXT 0xb4UL 216 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 217 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 218 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 219 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 220 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 221 #define HWRM_RESERVED7 0xbaUL 222 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 223 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 224 #define HWRM_PORT_ECN_QSTATS 0xbdUL 225 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 226 #define HWRM_FW_LIVEPATCH 0xbfUL 227 #define HWRM_FW_RESET 0xc0UL 228 #define HWRM_FW_QSTATUS 0xc1UL 229 #define HWRM_FW_HEALTH_CHECK 0xc2UL 230 #define HWRM_FW_SYNC 0xc3UL 231 #define HWRM_FW_STATE_QCAPS 0xc4UL 232 #define HWRM_FW_STATE_QUIESCE 0xc5UL 233 #define HWRM_FW_STATE_BACKUP 0xc6UL 234 #define HWRM_FW_STATE_RESTORE 0xc7UL 235 #define HWRM_FW_SET_TIME 0xc8UL 236 #define HWRM_FW_GET_TIME 0xc9UL 237 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 238 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 239 #define HWRM_FW_IPC_MAILBOX 0xccUL 240 #define HWRM_FW_ECN_CFG 0xcdUL 241 #define HWRM_FW_ECN_QCFG 0xceUL 242 #define HWRM_FW_SECURE_CFG 0xcfUL 243 #define HWRM_EXEC_FWD_RESP 0xd0UL 244 #define HWRM_REJECT_FWD_RESP 0xd1UL 245 #define HWRM_FWD_RESP 0xd2UL 246 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 247 #define HWRM_OEM_CMD 0xd4UL 248 #define HWRM_PORT_PRBS_TEST 0xd5UL 249 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 250 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 251 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 252 #define HWRM_PORT_DSC_DUMP 0xd9UL 253 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 254 #define HWRM_REG_POWER_QUERY 0xe1UL 255 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 256 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 257 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 258 #define HWRM_WOL_FILTER_FREE 0xf1UL 259 #define HWRM_WOL_FILTER_QCFG 0xf2UL 260 #define HWRM_WOL_REASON_QCFG 0xf3UL 261 #define HWRM_CFA_METER_QCAPS 0xf4UL 262 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 263 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 264 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 265 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 266 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 267 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 268 #define HWRM_CFA_VFR_ALLOC 0xfdUL 269 #define HWRM_CFA_VFR_FREE 0xfeUL 270 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 271 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 272 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 273 #define HWRM_CFA_FLOW_ALLOC 0x103UL 274 #define HWRM_CFA_FLOW_FREE 0x104UL 275 #define HWRM_CFA_FLOW_FLUSH 0x105UL 276 #define HWRM_CFA_FLOW_STATS 0x106UL 277 #define HWRM_CFA_FLOW_INFO 0x107UL 278 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 279 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 280 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 281 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 282 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 283 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 284 #define HWRM_CFA_PAIR_FREE 0x10eUL 285 #define HWRM_CFA_PAIR_INFO 0x10fUL 286 #define HWRM_FW_IPC_MSG 0x110UL 287 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 288 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 289 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 290 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 291 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 292 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 293 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 294 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 295 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 296 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 297 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 298 #define HWRM_CFA_COUNTER_CFG 0x11cUL 299 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 300 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 301 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 302 #define HWRM_CFA_EEM_QCAPS 0x120UL 303 #define HWRM_CFA_EEM_CFG 0x121UL 304 #define HWRM_CFA_EEM_QCFG 0x122UL 305 #define HWRM_CFA_EEM_OP 0x123UL 306 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 307 #define HWRM_CFA_TFLIB 0x125UL 308 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 309 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 310 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 311 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 312 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 313 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 314 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 315 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 316 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 317 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 318 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 319 #define HWRM_ENGINE_QG_QUERY 0x13dUL 320 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 321 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 322 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 323 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 324 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 325 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 326 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 327 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 328 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 329 #define HWRM_ENGINE_SG_QUERY 0x147UL 330 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 331 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 332 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 333 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 334 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 335 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 336 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 337 #define HWRM_ENGINE_STATS_QUERY 0x157UL 338 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 339 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 340 #define HWRM_ENGINE_RQ_FREE 0x15fUL 341 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 342 #define HWRM_ENGINE_CQ_FREE 0x161UL 343 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 344 #define HWRM_ENGINE_NQ_FREE 0x163UL 345 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 346 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 347 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 348 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 349 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 350 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 351 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 352 #define HWRM_FUNC_VF_BW_CFG 0x195UL 353 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 354 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 355 #define HWRM_FUNC_QSTATS_EXT 0x198UL 356 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 357 #define HWRM_FUNC_SPD_CFG 0x19aUL 358 #define HWRM_FUNC_SPD_QCFG 0x19bUL 359 #define HWRM_SELFTEST_QLIST 0x200UL 360 #define HWRM_SELFTEST_EXEC 0x201UL 361 #define HWRM_SELFTEST_IRQ 0x202UL 362 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 363 #define HWRM_PCIE_QSTATS 0x204UL 364 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 365 #define HWRM_MFG_TIMERS_QUERY 0x206UL 366 #define HWRM_MFG_OTP_CFG 0x207UL 367 #define HWRM_MFG_OTP_QCFG 0x208UL 368 #define HWRM_MFG_HDMA_TEST 0x209UL 369 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 370 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 371 #define HWRM_MFG_SOC_IMAGE 0x20cUL 372 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 373 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 374 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 375 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 376 #define HWRM_TF 0x2bcUL 377 #define HWRM_TF_VERSION_GET 0x2bdUL 378 #define HWRM_TF_SESSION_OPEN 0x2c6UL 379 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 380 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 381 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 382 #define HWRM_TF_SESSION_CLOSE 0x2caUL 383 #define HWRM_TF_SESSION_QCFG 0x2cbUL 384 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 385 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 386 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 387 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 388 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 389 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 390 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 391 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 392 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 393 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 394 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 395 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 396 #define HWRM_TF_EXT_EM_OP 0x2e7UL 397 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 398 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 399 #define HWRM_TF_EM_INSERT 0x2eaUL 400 #define HWRM_TF_EM_DELETE 0x2ebUL 401 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 402 #define HWRM_TF_TCAM_SET 0x2f8UL 403 #define HWRM_TF_TCAM_GET 0x2f9UL 404 #define HWRM_TF_TCAM_MOVE 0x2faUL 405 #define HWRM_TF_TCAM_FREE 0x2fbUL 406 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 407 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 408 #define HWRM_TF_IF_TBL_SET 0x2feUL 409 #define HWRM_TF_IF_TBL_GET 0x2ffUL 410 #define HWRM_SV 0x400UL 411 #define HWRM_DBG_READ_DIRECT 0xff10UL 412 #define HWRM_DBG_READ_INDIRECT 0xff11UL 413 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 414 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 415 #define HWRM_DBG_DUMP 0xff14UL 416 #define HWRM_DBG_ERASE_NVM 0xff15UL 417 #define HWRM_DBG_CFG 0xff16UL 418 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 419 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 420 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 421 #define HWRM_DBG_FW_CLI 0xff1aUL 422 #define HWRM_DBG_I2C_CMD 0xff1bUL 423 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 424 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 425 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 426 #define HWRM_DBG_DRV_TRACE 0xff1fUL 427 #define HWRM_DBG_QCAPS 0xff20UL 428 #define HWRM_DBG_QCFG 0xff21UL 429 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 430 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 431 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 432 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 433 #define HWRM_NVM_FLUSH 0xfff0UL 434 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 435 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 436 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 437 #define HWRM_NVM_MODIFY 0xfff4UL 438 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 439 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 440 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 441 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 442 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 443 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 444 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 445 #define HWRM_NVM_RAW_DUMP 0xfffcUL 446 #define HWRM_NVM_READ 0xfffdUL 447 #define HWRM_NVM_WRITE 0xfffeUL 448 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 449 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 450 __le16 unused_0[3]; 451 }; 452 453 /* ret_codes (size:64b/8B) */ 454 struct ret_codes { 455 __le16 error_code; 456 #define HWRM_ERR_CODE_SUCCESS 0x0UL 457 #define HWRM_ERR_CODE_FAIL 0x1UL 458 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 459 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 460 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 461 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 462 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 463 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 464 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 465 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 466 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 467 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 468 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 469 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 470 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 471 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 472 #define HWRM_ERR_CODE_BUSY 0x10UL 473 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 474 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 475 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 476 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 477 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 478 __le16 unused_0[3]; 479 }; 480 481 /* hwrm_err_output (size:128b/16B) */ 482 struct hwrm_err_output { 483 __le16 error_code; 484 __le16 req_type; 485 __le16 seq_id; 486 __le16 resp_len; 487 __le32 opaque_0; 488 __le16 opaque_1; 489 u8 cmd_err; 490 u8 valid; 491 }; 492 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 493 #define HWRM_MAX_REQ_LEN 128 494 #define HWRM_MAX_RESP_LEN 704 495 #define HW_HASH_INDEX_SIZE 0x80 496 #define HW_HASH_KEY_SIZE 40 497 #define HWRM_RESP_VALID_KEY 1 498 #define HWRM_TARGET_ID_BONO 0xFFF8 499 #define HWRM_TARGET_ID_KONG 0xFFF9 500 #define HWRM_TARGET_ID_APE 0xFFFA 501 #define HWRM_TARGET_ID_TOOLS 0xFFFD 502 #define HWRM_VERSION_MAJOR 1 503 #define HWRM_VERSION_MINOR 10 504 #define HWRM_VERSION_UPDATE 2 505 #define HWRM_VERSION_RSVD 16 506 #define HWRM_VERSION_STR "1.10.2.16" 507 508 /* hwrm_ver_get_input (size:192b/24B) */ 509 struct hwrm_ver_get_input { 510 __le16 req_type; 511 __le16 cmpl_ring; 512 __le16 seq_id; 513 __le16 target_id; 514 __le64 resp_addr; 515 u8 hwrm_intf_maj; 516 u8 hwrm_intf_min; 517 u8 hwrm_intf_upd; 518 u8 unused_0[5]; 519 }; 520 521 /* hwrm_ver_get_output (size:1408b/176B) */ 522 struct hwrm_ver_get_output { 523 __le16 error_code; 524 __le16 req_type; 525 __le16 seq_id; 526 __le16 resp_len; 527 u8 hwrm_intf_maj_8b; 528 u8 hwrm_intf_min_8b; 529 u8 hwrm_intf_upd_8b; 530 u8 hwrm_intf_rsvd_8b; 531 u8 hwrm_fw_maj_8b; 532 u8 hwrm_fw_min_8b; 533 u8 hwrm_fw_bld_8b; 534 u8 hwrm_fw_rsvd_8b; 535 u8 mgmt_fw_maj_8b; 536 u8 mgmt_fw_min_8b; 537 u8 mgmt_fw_bld_8b; 538 u8 mgmt_fw_rsvd_8b; 539 u8 netctrl_fw_maj_8b; 540 u8 netctrl_fw_min_8b; 541 u8 netctrl_fw_bld_8b; 542 u8 netctrl_fw_rsvd_8b; 543 __le32 dev_caps_cfg; 544 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 545 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 546 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 547 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 548 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 549 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 550 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 551 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 552 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 553 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 554 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 555 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 556 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 557 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 558 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 559 u8 roce_fw_maj_8b; 560 u8 roce_fw_min_8b; 561 u8 roce_fw_bld_8b; 562 u8 roce_fw_rsvd_8b; 563 char hwrm_fw_name[16]; 564 char mgmt_fw_name[16]; 565 char netctrl_fw_name[16]; 566 char active_pkg_name[16]; 567 char roce_fw_name[16]; 568 __le16 chip_num; 569 u8 chip_rev; 570 u8 chip_metal; 571 u8 chip_bond_id; 572 u8 chip_platform_type; 573 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 574 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 575 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 576 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 577 __le16 max_req_win_len; 578 __le16 max_resp_len; 579 __le16 def_req_timeout; 580 u8 flags; 581 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 582 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 583 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 584 u8 unused_0[2]; 585 u8 always_1; 586 __le16 hwrm_intf_major; 587 __le16 hwrm_intf_minor; 588 __le16 hwrm_intf_build; 589 __le16 hwrm_intf_patch; 590 __le16 hwrm_fw_major; 591 __le16 hwrm_fw_minor; 592 __le16 hwrm_fw_build; 593 __le16 hwrm_fw_patch; 594 __le16 mgmt_fw_major; 595 __le16 mgmt_fw_minor; 596 __le16 mgmt_fw_build; 597 __le16 mgmt_fw_patch; 598 __le16 netctrl_fw_major; 599 __le16 netctrl_fw_minor; 600 __le16 netctrl_fw_build; 601 __le16 netctrl_fw_patch; 602 __le16 roce_fw_major; 603 __le16 roce_fw_minor; 604 __le16 roce_fw_build; 605 __le16 roce_fw_patch; 606 __le16 max_ext_req_len; 607 u8 unused_1[5]; 608 u8 valid; 609 }; 610 611 /* eject_cmpl (size:128b/16B) */ 612 struct eject_cmpl { 613 __le16 type; 614 #define EJECT_CMPL_TYPE_MASK 0x3fUL 615 #define EJECT_CMPL_TYPE_SFT 0 616 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 617 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 618 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 619 #define EJECT_CMPL_FLAGS_SFT 6 620 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 621 __le16 len; 622 __le32 opaque; 623 __le16 v; 624 #define EJECT_CMPL_V 0x1UL 625 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 626 #define EJECT_CMPL_ERRORS_SFT 1 627 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 628 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 629 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 630 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 631 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 632 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 633 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 634 __le16 reserved16; 635 __le32 unused_2; 636 }; 637 638 /* hwrm_cmpl (size:128b/16B) */ 639 struct hwrm_cmpl { 640 __le16 type; 641 #define CMPL_TYPE_MASK 0x3fUL 642 #define CMPL_TYPE_SFT 0 643 #define CMPL_TYPE_HWRM_DONE 0x20UL 644 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 645 __le16 sequence_id; 646 __le32 unused_1; 647 __le32 v; 648 #define CMPL_V 0x1UL 649 __le32 unused_3; 650 }; 651 652 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 653 struct hwrm_fwd_req_cmpl { 654 __le16 req_len_type; 655 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 656 #define FWD_REQ_CMPL_TYPE_SFT 0 657 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 658 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 659 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 660 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 661 __le16 source_id; 662 __le32 unused0; 663 __le32 req_buf_addr_v[2]; 664 #define FWD_REQ_CMPL_V 0x1UL 665 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 666 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 667 }; 668 669 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 670 struct hwrm_fwd_resp_cmpl { 671 __le16 type; 672 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 673 #define FWD_RESP_CMPL_TYPE_SFT 0 674 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 675 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 676 __le16 source_id; 677 __le16 resp_len; 678 __le16 unused_1; 679 __le32 resp_buf_addr_v[2]; 680 #define FWD_RESP_CMPL_V 0x1UL 681 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 682 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 683 }; 684 685 /* hwrm_async_event_cmpl (size:128b/16B) */ 686 struct hwrm_async_event_cmpl { 687 __le16 type; 688 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 689 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 690 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 691 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 692 __le16 event_id; 693 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 694 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 695 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 696 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 697 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 698 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 699 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 700 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 701 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 702 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 703 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 704 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 705 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 706 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 707 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 708 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 709 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 710 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 711 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 712 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 713 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 714 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 715 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 716 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 717 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 718 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 719 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 720 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 721 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 722 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 723 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 724 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 725 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 726 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 727 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 728 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x43UL 729 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 730 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 731 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 732 __le32 event_data2; 733 u8 opaque_v; 734 #define ASYNC_EVENT_CMPL_V 0x1UL 735 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 736 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 737 u8 timestamp_lo; 738 __le16 timestamp_hi; 739 __le32 event_data1; 740 }; 741 742 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 743 struct hwrm_async_event_cmpl_link_status_change { 744 __le16 type; 745 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 746 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 747 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 748 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 749 __le16 event_id; 750 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 751 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 752 __le32 event_data2; 753 u8 opaque_v; 754 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 755 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 756 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 757 u8 timestamp_lo; 758 __le16 timestamp_hi; 759 __le32 event_data1; 760 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 761 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 762 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 763 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 764 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 765 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 766 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 767 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 768 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 769 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 770 }; 771 772 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 773 struct hwrm_async_event_cmpl_port_conn_not_allowed { 774 __le16 type; 775 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 776 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 777 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 778 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 779 __le16 event_id; 780 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 781 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 782 __le32 event_data2; 783 u8 opaque_v; 784 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 785 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 786 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 787 u8 timestamp_lo; 788 __le16 timestamp_hi; 789 __le32 event_data1; 790 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 791 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 792 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 793 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 794 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 795 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 796 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 797 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 798 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 799 }; 800 801 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 802 struct hwrm_async_event_cmpl_link_speed_cfg_change { 803 __le16 type; 804 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 805 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 806 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 807 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 808 __le16 event_id; 809 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 810 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 811 __le32 event_data2; 812 u8 opaque_v; 813 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 814 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 815 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 816 u8 timestamp_lo; 817 __le16 timestamp_hi; 818 __le32 event_data1; 819 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 820 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 821 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 822 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 823 }; 824 825 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 826 struct hwrm_async_event_cmpl_reset_notify { 827 __le16 type; 828 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 829 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 830 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 831 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 832 __le16 event_id; 833 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 834 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 835 __le32 event_data2; 836 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 837 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 838 u8 opaque_v; 839 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 840 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 841 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 842 u8 timestamp_lo; 843 __le16 timestamp_hi; 844 __le32 event_data1; 845 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 846 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 847 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 848 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 849 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 850 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 851 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 852 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 853 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 854 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 855 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 856 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET 857 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 858 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 859 }; 860 861 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 862 struct hwrm_async_event_cmpl_error_recovery { 863 __le16 type; 864 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 865 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 866 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 867 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 868 __le16 event_id; 869 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 870 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 871 __le32 event_data2; 872 u8 opaque_v; 873 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 874 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 875 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 876 u8 timestamp_lo; 877 __le16 timestamp_hi; 878 __le32 event_data1; 879 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 880 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 881 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 882 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 883 }; 884 885 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 886 struct hwrm_async_event_cmpl_ring_monitor_msg { 887 __le16 type; 888 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 889 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 890 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 891 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 892 __le16 event_id; 893 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 894 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 895 __le32 event_data2; 896 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 897 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 898 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 899 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 900 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 901 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 902 u8 opaque_v; 903 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 904 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 905 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 906 u8 timestamp_lo; 907 __le16 timestamp_hi; 908 __le32 event_data1; 909 }; 910 911 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 912 struct hwrm_async_event_cmpl_vf_cfg_change { 913 __le16 type; 914 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 915 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 916 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 917 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 918 __le16 event_id; 919 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 920 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 921 __le32 event_data2; 922 u8 opaque_v; 923 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 924 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 925 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 926 u8 timestamp_lo; 927 __le16 timestamp_hi; 928 __le32 event_data1; 929 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 930 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 931 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 932 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 933 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 934 }; 935 936 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 937 struct hwrm_async_event_cmpl_default_vnic_change { 938 __le16 type; 939 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 940 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 941 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 942 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 943 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 944 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 945 __le16 event_id; 946 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 947 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 948 __le32 event_data2; 949 u8 opaque_v; 950 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 951 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 952 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 953 u8 timestamp_lo; 954 __le16 timestamp_hi; 955 __le32 event_data1; 956 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 957 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 958 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 959 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 960 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 961 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 962 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 963 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 964 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 965 }; 966 967 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 968 struct hwrm_async_event_cmpl_hw_flow_aged { 969 __le16 type; 970 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 971 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 972 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 973 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 974 __le16 event_id; 975 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 976 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 977 __le32 event_data2; 978 u8 opaque_v; 979 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 980 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 981 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 982 u8 timestamp_lo; 983 __le16 timestamp_hi; 984 __le32 event_data1; 985 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 986 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 987 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 988 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 989 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 990 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 991 }; 992 993 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 994 struct hwrm_async_event_cmpl_eem_cache_flush_req { 995 __le16 type; 996 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 997 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 998 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 999 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1000 __le16 event_id; 1001 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1002 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1003 __le32 event_data2; 1004 u8 opaque_v; 1005 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1006 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1007 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1008 u8 timestamp_lo; 1009 __le16 timestamp_hi; 1010 __le32 event_data1; 1011 }; 1012 1013 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1014 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1015 __le16 type; 1016 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1017 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1018 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1019 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1020 __le16 event_id; 1021 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1022 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1023 __le32 event_data2; 1024 u8 opaque_v; 1025 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1026 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1027 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1028 u8 timestamp_lo; 1029 __le16 timestamp_hi; 1030 __le32 event_data1; 1031 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1032 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1033 }; 1034 1035 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1036 struct hwrm_async_event_cmpl_deferred_response { 1037 __le16 type; 1038 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1039 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1040 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1041 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1042 __le16 event_id; 1043 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1044 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1045 __le32 event_data2; 1046 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1047 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1048 u8 opaque_v; 1049 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1050 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1051 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1052 u8 timestamp_lo; 1053 __le16 timestamp_hi; 1054 __le32 event_data1; 1055 }; 1056 1057 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1058 struct hwrm_async_event_cmpl_echo_request { 1059 __le16 type; 1060 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1061 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1062 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1063 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1064 __le16 event_id; 1065 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1066 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1067 __le32 event_data2; 1068 u8 opaque_v; 1069 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1070 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1071 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1072 u8 timestamp_lo; 1073 __le16 timestamp_hi; 1074 __le32 event_data1; 1075 }; 1076 1077 /* hwrm_func_reset_input (size:192b/24B) */ 1078 struct hwrm_func_reset_input { 1079 __le16 req_type; 1080 __le16 cmpl_ring; 1081 __le16 seq_id; 1082 __le16 target_id; 1083 __le64 resp_addr; 1084 __le32 enables; 1085 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1086 __le16 vf_id; 1087 u8 func_reset_level; 1088 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1089 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1090 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1091 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1092 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1093 u8 unused_0; 1094 }; 1095 1096 /* hwrm_func_reset_output (size:128b/16B) */ 1097 struct hwrm_func_reset_output { 1098 __le16 error_code; 1099 __le16 req_type; 1100 __le16 seq_id; 1101 __le16 resp_len; 1102 u8 unused_0[7]; 1103 u8 valid; 1104 }; 1105 1106 /* hwrm_func_getfid_input (size:192b/24B) */ 1107 struct hwrm_func_getfid_input { 1108 __le16 req_type; 1109 __le16 cmpl_ring; 1110 __le16 seq_id; 1111 __le16 target_id; 1112 __le64 resp_addr; 1113 __le32 enables; 1114 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1115 __le16 pci_id; 1116 u8 unused_0[2]; 1117 }; 1118 1119 /* hwrm_func_getfid_output (size:128b/16B) */ 1120 struct hwrm_func_getfid_output { 1121 __le16 error_code; 1122 __le16 req_type; 1123 __le16 seq_id; 1124 __le16 resp_len; 1125 __le16 fid; 1126 u8 unused_0[5]; 1127 u8 valid; 1128 }; 1129 1130 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1131 struct hwrm_func_vf_alloc_input { 1132 __le16 req_type; 1133 __le16 cmpl_ring; 1134 __le16 seq_id; 1135 __le16 target_id; 1136 __le64 resp_addr; 1137 __le32 enables; 1138 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1139 __le16 first_vf_id; 1140 __le16 num_vfs; 1141 }; 1142 1143 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1144 struct hwrm_func_vf_alloc_output { 1145 __le16 error_code; 1146 __le16 req_type; 1147 __le16 seq_id; 1148 __le16 resp_len; 1149 __le16 first_vf_id; 1150 u8 unused_0[5]; 1151 u8 valid; 1152 }; 1153 1154 /* hwrm_func_vf_free_input (size:192b/24B) */ 1155 struct hwrm_func_vf_free_input { 1156 __le16 req_type; 1157 __le16 cmpl_ring; 1158 __le16 seq_id; 1159 __le16 target_id; 1160 __le64 resp_addr; 1161 __le32 enables; 1162 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1163 __le16 first_vf_id; 1164 __le16 num_vfs; 1165 }; 1166 1167 /* hwrm_func_vf_free_output (size:128b/16B) */ 1168 struct hwrm_func_vf_free_output { 1169 __le16 error_code; 1170 __le16 req_type; 1171 __le16 seq_id; 1172 __le16 resp_len; 1173 u8 unused_0[7]; 1174 u8 valid; 1175 }; 1176 1177 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1178 struct hwrm_func_vf_cfg_input { 1179 __le16 req_type; 1180 __le16 cmpl_ring; 1181 __le16 seq_id; 1182 __le16 target_id; 1183 __le64 resp_addr; 1184 __le32 enables; 1185 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1186 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1187 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1188 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1189 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1190 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1191 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1192 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1193 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1194 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1195 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1196 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1197 __le16 mtu; 1198 __le16 guest_vlan; 1199 __le16 async_event_cr; 1200 u8 dflt_mac_addr[6]; 1201 __le32 flags; 1202 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1203 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1204 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1205 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1206 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1207 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1208 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1209 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1210 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1211 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1212 __le16 num_rsscos_ctxs; 1213 __le16 num_cmpl_rings; 1214 __le16 num_tx_rings; 1215 __le16 num_rx_rings; 1216 __le16 num_l2_ctxs; 1217 __le16 num_vnics; 1218 __le16 num_stat_ctxs; 1219 __le16 num_hw_ring_grps; 1220 u8 unused_0[4]; 1221 }; 1222 1223 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1224 struct hwrm_func_vf_cfg_output { 1225 __le16 error_code; 1226 __le16 req_type; 1227 __le16 seq_id; 1228 __le16 resp_len; 1229 u8 unused_0[7]; 1230 u8 valid; 1231 }; 1232 1233 /* hwrm_func_qcaps_input (size:192b/24B) */ 1234 struct hwrm_func_qcaps_input { 1235 __le16 req_type; 1236 __le16 cmpl_ring; 1237 __le16 seq_id; 1238 __le16 target_id; 1239 __le64 resp_addr; 1240 __le16 fid; 1241 u8 unused_0[6]; 1242 }; 1243 1244 /* hwrm_func_qcaps_output (size:704b/88B) */ 1245 struct hwrm_func_qcaps_output { 1246 __le16 error_code; 1247 __le16 req_type; 1248 __le16 seq_id; 1249 __le16 resp_len; 1250 __le16 fid; 1251 __le16 port_id; 1252 __le32 flags; 1253 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1254 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1255 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1256 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1257 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1258 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1259 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1260 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1261 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1262 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1263 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1264 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1265 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1266 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1267 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1268 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1269 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1270 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1271 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1272 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1273 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1274 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1275 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1276 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1277 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1278 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1279 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1280 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1281 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1282 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1283 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1284 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1285 u8 mac_address[6]; 1286 __le16 max_rsscos_ctx; 1287 __le16 max_cmpl_rings; 1288 __le16 max_tx_rings; 1289 __le16 max_rx_rings; 1290 __le16 max_l2_ctxs; 1291 __le16 max_vnics; 1292 __le16 first_vf_id; 1293 __le16 max_vfs; 1294 __le16 max_stat_ctx; 1295 __le32 max_encap_records; 1296 __le32 max_decap_records; 1297 __le32 max_tx_em_flows; 1298 __le32 max_tx_wm_flows; 1299 __le32 max_rx_em_flows; 1300 __le32 max_rx_wm_flows; 1301 __le32 max_mcast_filters; 1302 __le32 max_flow_id; 1303 __le32 max_hw_ring_grps; 1304 __le16 max_sp_tx_rings; 1305 u8 unused_0[2]; 1306 __le32 flags_ext; 1307 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1308 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1309 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1310 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1311 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1312 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1313 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1314 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1315 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1316 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1317 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1318 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1319 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1320 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1321 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1322 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1323 u8 max_schqs; 1324 u8 mpc_chnls_cap; 1325 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1326 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1327 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1328 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1329 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1330 u8 unused_1; 1331 u8 valid; 1332 }; 1333 1334 /* hwrm_func_qcfg_input (size:192b/24B) */ 1335 struct hwrm_func_qcfg_input { 1336 __le16 req_type; 1337 __le16 cmpl_ring; 1338 __le16 seq_id; 1339 __le16 target_id; 1340 __le64 resp_addr; 1341 __le16 fid; 1342 u8 unused_0[6]; 1343 }; 1344 1345 /* hwrm_func_qcfg_output (size:768b/96B) */ 1346 struct hwrm_func_qcfg_output { 1347 __le16 error_code; 1348 __le16 req_type; 1349 __le16 seq_id; 1350 __le16 resp_len; 1351 __le16 fid; 1352 __le16 port_id; 1353 __le16 vlan; 1354 __le16 flags; 1355 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1356 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1357 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1358 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1359 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1360 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1361 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1362 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1363 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1364 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1365 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1366 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1367 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1368 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1369 u8 mac_address[6]; 1370 __le16 pci_id; 1371 __le16 alloc_rsscos_ctx; 1372 __le16 alloc_cmpl_rings; 1373 __le16 alloc_tx_rings; 1374 __le16 alloc_rx_rings; 1375 __le16 alloc_l2_ctx; 1376 __le16 alloc_vnics; 1377 __le16 mtu; 1378 __le16 mru; 1379 __le16 stat_ctx_id; 1380 u8 port_partition_type; 1381 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1382 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1383 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1384 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1385 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1386 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1387 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1388 u8 port_pf_cnt; 1389 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1390 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1391 __le16 dflt_vnic_id; 1392 __le16 max_mtu_configured; 1393 __le32 min_bw; 1394 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1395 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1396 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1397 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1398 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1399 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1400 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1401 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1402 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1403 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1404 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1405 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1406 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1407 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1408 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1409 __le32 max_bw; 1410 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1411 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1412 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1413 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1414 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1415 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1416 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1417 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1418 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1419 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1420 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1421 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1422 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1423 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1424 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1425 u8 evb_mode; 1426 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1427 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1428 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1429 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1430 u8 options; 1431 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1432 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1433 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1434 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1435 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1436 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1437 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1438 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1439 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1440 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1441 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1442 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1443 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1444 __le16 alloc_vfs; 1445 __le32 alloc_mcast_filters; 1446 __le32 alloc_hw_ring_grps; 1447 __le16 alloc_sp_tx_rings; 1448 __le16 alloc_stat_ctx; 1449 __le16 alloc_msix; 1450 __le16 registered_vfs; 1451 __le16 l2_doorbell_bar_size_kb; 1452 u8 unused_1; 1453 u8 always_1; 1454 __le32 reset_addr_poll; 1455 __le16 legacy_l2_db_size_kb; 1456 __le16 svif_info; 1457 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1458 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1459 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1460 u8 mpc_chnls; 1461 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1462 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1463 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1464 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1465 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1466 u8 unused_2[6]; 1467 u8 valid; 1468 }; 1469 1470 /* hwrm_func_cfg_input (size:768b/96B) */ 1471 struct hwrm_func_cfg_input { 1472 __le16 req_type; 1473 __le16 cmpl_ring; 1474 __le16 seq_id; 1475 __le16 target_id; 1476 __le64 resp_addr; 1477 __le16 fid; 1478 __le16 num_msix; 1479 __le32 flags; 1480 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1481 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1482 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1483 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1484 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1485 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1486 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1487 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1488 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1489 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1490 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1491 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1492 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1493 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1494 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1495 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1496 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1497 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1498 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1499 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1500 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1501 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1502 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1503 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1504 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1505 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1506 __le32 enables; 1507 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1508 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1509 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1510 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1511 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1512 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1513 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1514 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1515 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1516 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1517 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1518 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1519 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1520 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1521 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1522 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1523 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1524 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1525 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1526 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1527 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1528 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1529 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1530 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1531 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1532 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1533 __le16 mtu; 1534 __le16 mru; 1535 __le16 num_rsscos_ctxs; 1536 __le16 num_cmpl_rings; 1537 __le16 num_tx_rings; 1538 __le16 num_rx_rings; 1539 __le16 num_l2_ctxs; 1540 __le16 num_vnics; 1541 __le16 num_stat_ctxs; 1542 __le16 num_hw_ring_grps; 1543 u8 dflt_mac_addr[6]; 1544 __le16 dflt_vlan; 1545 __be32 dflt_ip_addr[4]; 1546 __le32 min_bw; 1547 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1548 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1549 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1550 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1551 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1552 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1553 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1554 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1555 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1556 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1557 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1558 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1559 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1560 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1561 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1562 __le32 max_bw; 1563 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1564 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1565 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1566 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1567 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1568 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1569 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1570 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1571 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1572 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1573 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1574 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1575 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1576 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1577 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1578 __le16 async_event_cr; 1579 u8 vlan_antispoof_mode; 1580 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1581 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1582 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1583 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1584 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1585 u8 allowed_vlan_pris; 1586 u8 evb_mode; 1587 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1588 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1589 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1590 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1591 u8 options; 1592 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1593 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1594 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1595 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1596 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1597 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1598 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1599 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1600 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1601 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1602 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1603 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1604 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1605 __le16 num_mcast_filters; 1606 __le16 schq_id; 1607 __le16 mpc_chnls; 1608 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1609 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1610 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1611 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1612 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1613 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1614 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1615 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1616 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1617 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1618 u8 unused_0[4]; 1619 }; 1620 1621 /* hwrm_func_cfg_output (size:128b/16B) */ 1622 struct hwrm_func_cfg_output { 1623 __le16 error_code; 1624 __le16 req_type; 1625 __le16 seq_id; 1626 __le16 resp_len; 1627 u8 unused_0[7]; 1628 u8 valid; 1629 }; 1630 1631 /* hwrm_func_qstats_input (size:192b/24B) */ 1632 struct hwrm_func_qstats_input { 1633 __le16 req_type; 1634 __le16 cmpl_ring; 1635 __le16 seq_id; 1636 __le16 target_id; 1637 __le64 resp_addr; 1638 __le16 fid; 1639 u8 flags; 1640 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1641 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1642 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1643 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1644 u8 unused_0[5]; 1645 }; 1646 1647 /* hwrm_func_qstats_output (size:1408b/176B) */ 1648 struct hwrm_func_qstats_output { 1649 __le16 error_code; 1650 __le16 req_type; 1651 __le16 seq_id; 1652 __le16 resp_len; 1653 __le64 tx_ucast_pkts; 1654 __le64 tx_mcast_pkts; 1655 __le64 tx_bcast_pkts; 1656 __le64 tx_discard_pkts; 1657 __le64 tx_drop_pkts; 1658 __le64 tx_ucast_bytes; 1659 __le64 tx_mcast_bytes; 1660 __le64 tx_bcast_bytes; 1661 __le64 rx_ucast_pkts; 1662 __le64 rx_mcast_pkts; 1663 __le64 rx_bcast_pkts; 1664 __le64 rx_discard_pkts; 1665 __le64 rx_drop_pkts; 1666 __le64 rx_ucast_bytes; 1667 __le64 rx_mcast_bytes; 1668 __le64 rx_bcast_bytes; 1669 __le64 rx_agg_pkts; 1670 __le64 rx_agg_bytes; 1671 __le64 rx_agg_events; 1672 __le64 rx_agg_aborts; 1673 u8 unused_0[7]; 1674 u8 valid; 1675 }; 1676 1677 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1678 struct hwrm_func_qstats_ext_input { 1679 __le16 req_type; 1680 __le16 cmpl_ring; 1681 __le16 seq_id; 1682 __le16 target_id; 1683 __le64 resp_addr; 1684 __le16 fid; 1685 u8 flags; 1686 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1687 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1688 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1689 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1690 u8 unused_0[1]; 1691 __le32 enables; 1692 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 1693 __le16 schq_id; 1694 __le16 traffic_class; 1695 u8 unused_1[4]; 1696 }; 1697 1698 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 1699 struct hwrm_func_qstats_ext_output { 1700 __le16 error_code; 1701 __le16 req_type; 1702 __le16 seq_id; 1703 __le16 resp_len; 1704 __le64 rx_ucast_pkts; 1705 __le64 rx_mcast_pkts; 1706 __le64 rx_bcast_pkts; 1707 __le64 rx_discard_pkts; 1708 __le64 rx_error_pkts; 1709 __le64 rx_ucast_bytes; 1710 __le64 rx_mcast_bytes; 1711 __le64 rx_bcast_bytes; 1712 __le64 tx_ucast_pkts; 1713 __le64 tx_mcast_pkts; 1714 __le64 tx_bcast_pkts; 1715 __le64 tx_error_pkts; 1716 __le64 tx_discard_pkts; 1717 __le64 tx_ucast_bytes; 1718 __le64 tx_mcast_bytes; 1719 __le64 tx_bcast_bytes; 1720 __le64 rx_tpa_eligible_pkt; 1721 __le64 rx_tpa_eligible_bytes; 1722 __le64 rx_tpa_pkt; 1723 __le64 rx_tpa_bytes; 1724 __le64 rx_tpa_errors; 1725 __le64 rx_tpa_events; 1726 u8 unused_0[7]; 1727 u8 valid; 1728 }; 1729 1730 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1731 struct hwrm_func_clr_stats_input { 1732 __le16 req_type; 1733 __le16 cmpl_ring; 1734 __le16 seq_id; 1735 __le16 target_id; 1736 __le64 resp_addr; 1737 __le16 fid; 1738 u8 unused_0[6]; 1739 }; 1740 1741 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1742 struct hwrm_func_clr_stats_output { 1743 __le16 error_code; 1744 __le16 req_type; 1745 __le16 seq_id; 1746 __le16 resp_len; 1747 u8 unused_0[7]; 1748 u8 valid; 1749 }; 1750 1751 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1752 struct hwrm_func_vf_resc_free_input { 1753 __le16 req_type; 1754 __le16 cmpl_ring; 1755 __le16 seq_id; 1756 __le16 target_id; 1757 __le64 resp_addr; 1758 __le16 vf_id; 1759 u8 unused_0[6]; 1760 }; 1761 1762 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1763 struct hwrm_func_vf_resc_free_output { 1764 __le16 error_code; 1765 __le16 req_type; 1766 __le16 seq_id; 1767 __le16 resp_len; 1768 u8 unused_0[7]; 1769 u8 valid; 1770 }; 1771 1772 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1773 struct hwrm_func_drv_rgtr_input { 1774 __le16 req_type; 1775 __le16 cmpl_ring; 1776 __le16 seq_id; 1777 __le16 target_id; 1778 __le64 resp_addr; 1779 __le32 flags; 1780 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1781 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1782 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1783 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1784 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1785 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1786 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1787 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 1788 __le32 enables; 1789 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1790 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1791 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1792 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1793 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1794 __le16 os_type; 1795 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1796 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1797 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1798 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1799 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1800 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1801 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1802 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1803 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1804 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1805 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1806 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1807 u8 ver_maj_8b; 1808 u8 ver_min_8b; 1809 u8 ver_upd_8b; 1810 u8 unused_0[3]; 1811 __le32 timestamp; 1812 u8 unused_1[4]; 1813 __le32 vf_req_fwd[8]; 1814 __le32 async_event_fwd[8]; 1815 __le16 ver_maj; 1816 __le16 ver_min; 1817 __le16 ver_upd; 1818 __le16 ver_patch; 1819 }; 1820 1821 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1822 struct hwrm_func_drv_rgtr_output { 1823 __le16 error_code; 1824 __le16 req_type; 1825 __le16 seq_id; 1826 __le16 resp_len; 1827 __le32 flags; 1828 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1829 u8 unused_0[3]; 1830 u8 valid; 1831 }; 1832 1833 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1834 struct hwrm_func_drv_unrgtr_input { 1835 __le16 req_type; 1836 __le16 cmpl_ring; 1837 __le16 seq_id; 1838 __le16 target_id; 1839 __le64 resp_addr; 1840 __le32 flags; 1841 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1842 u8 unused_0[4]; 1843 }; 1844 1845 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1846 struct hwrm_func_drv_unrgtr_output { 1847 __le16 error_code; 1848 __le16 req_type; 1849 __le16 seq_id; 1850 __le16 resp_len; 1851 u8 unused_0[7]; 1852 u8 valid; 1853 }; 1854 1855 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1856 struct hwrm_func_buf_rgtr_input { 1857 __le16 req_type; 1858 __le16 cmpl_ring; 1859 __le16 seq_id; 1860 __le16 target_id; 1861 __le64 resp_addr; 1862 __le32 enables; 1863 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1864 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1865 __le16 vf_id; 1866 __le16 req_buf_num_pages; 1867 __le16 req_buf_page_size; 1868 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1869 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1870 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1871 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1872 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1873 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1874 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1875 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1876 __le16 req_buf_len; 1877 __le16 resp_buf_len; 1878 u8 unused_0[2]; 1879 __le64 req_buf_page_addr0; 1880 __le64 req_buf_page_addr1; 1881 __le64 req_buf_page_addr2; 1882 __le64 req_buf_page_addr3; 1883 __le64 req_buf_page_addr4; 1884 __le64 req_buf_page_addr5; 1885 __le64 req_buf_page_addr6; 1886 __le64 req_buf_page_addr7; 1887 __le64 req_buf_page_addr8; 1888 __le64 req_buf_page_addr9; 1889 __le64 error_buf_addr; 1890 __le64 resp_buf_addr; 1891 }; 1892 1893 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1894 struct hwrm_func_buf_rgtr_output { 1895 __le16 error_code; 1896 __le16 req_type; 1897 __le16 seq_id; 1898 __le16 resp_len; 1899 u8 unused_0[7]; 1900 u8 valid; 1901 }; 1902 1903 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1904 struct hwrm_func_drv_qver_input { 1905 __le16 req_type; 1906 __le16 cmpl_ring; 1907 __le16 seq_id; 1908 __le16 target_id; 1909 __le64 resp_addr; 1910 __le32 reserved; 1911 __le16 fid; 1912 u8 unused_0[2]; 1913 }; 1914 1915 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1916 struct hwrm_func_drv_qver_output { 1917 __le16 error_code; 1918 __le16 req_type; 1919 __le16 seq_id; 1920 __le16 resp_len; 1921 __le16 os_type; 1922 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1923 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1924 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1925 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1926 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1927 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1928 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1929 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1930 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1931 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1932 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1933 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1934 u8 ver_maj_8b; 1935 u8 ver_min_8b; 1936 u8 ver_upd_8b; 1937 u8 unused_0[3]; 1938 __le16 ver_maj; 1939 __le16 ver_min; 1940 __le16 ver_upd; 1941 __le16 ver_patch; 1942 u8 unused_1[7]; 1943 u8 valid; 1944 }; 1945 1946 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1947 struct hwrm_func_resource_qcaps_input { 1948 __le16 req_type; 1949 __le16 cmpl_ring; 1950 __le16 seq_id; 1951 __le16 target_id; 1952 __le64 resp_addr; 1953 __le16 fid; 1954 u8 unused_0[6]; 1955 }; 1956 1957 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1958 struct hwrm_func_resource_qcaps_output { 1959 __le16 error_code; 1960 __le16 req_type; 1961 __le16 seq_id; 1962 __le16 resp_len; 1963 __le16 max_vfs; 1964 __le16 max_msix; 1965 __le16 vf_reservation_strategy; 1966 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1967 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1968 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1969 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1970 __le16 min_rsscos_ctx; 1971 __le16 max_rsscos_ctx; 1972 __le16 min_cmpl_rings; 1973 __le16 max_cmpl_rings; 1974 __le16 min_tx_rings; 1975 __le16 max_tx_rings; 1976 __le16 min_rx_rings; 1977 __le16 max_rx_rings; 1978 __le16 min_l2_ctxs; 1979 __le16 max_l2_ctxs; 1980 __le16 min_vnics; 1981 __le16 max_vnics; 1982 __le16 min_stat_ctx; 1983 __le16 max_stat_ctx; 1984 __le16 min_hw_ring_grps; 1985 __le16 max_hw_ring_grps; 1986 __le16 max_tx_scheduler_inputs; 1987 __le16 flags; 1988 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1989 u8 unused_0[5]; 1990 u8 valid; 1991 }; 1992 1993 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1994 struct hwrm_func_vf_resource_cfg_input { 1995 __le16 req_type; 1996 __le16 cmpl_ring; 1997 __le16 seq_id; 1998 __le16 target_id; 1999 __le64 resp_addr; 2000 __le16 vf_id; 2001 __le16 max_msix; 2002 __le16 min_rsscos_ctx; 2003 __le16 max_rsscos_ctx; 2004 __le16 min_cmpl_rings; 2005 __le16 max_cmpl_rings; 2006 __le16 min_tx_rings; 2007 __le16 max_tx_rings; 2008 __le16 min_rx_rings; 2009 __le16 max_rx_rings; 2010 __le16 min_l2_ctxs; 2011 __le16 max_l2_ctxs; 2012 __le16 min_vnics; 2013 __le16 max_vnics; 2014 __le16 min_stat_ctx; 2015 __le16 max_stat_ctx; 2016 __le16 min_hw_ring_grps; 2017 __le16 max_hw_ring_grps; 2018 __le16 flags; 2019 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2020 u8 unused_0[2]; 2021 }; 2022 2023 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2024 struct hwrm_func_vf_resource_cfg_output { 2025 __le16 error_code; 2026 __le16 req_type; 2027 __le16 seq_id; 2028 __le16 resp_len; 2029 __le16 reserved_rsscos_ctx; 2030 __le16 reserved_cmpl_rings; 2031 __le16 reserved_tx_rings; 2032 __le16 reserved_rx_rings; 2033 __le16 reserved_l2_ctxs; 2034 __le16 reserved_vnics; 2035 __le16 reserved_stat_ctx; 2036 __le16 reserved_hw_ring_grps; 2037 u8 unused_0[7]; 2038 u8 valid; 2039 }; 2040 2041 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2042 struct hwrm_func_backing_store_qcaps_input { 2043 __le16 req_type; 2044 __le16 cmpl_ring; 2045 __le16 seq_id; 2046 __le16 target_id; 2047 __le64 resp_addr; 2048 }; 2049 2050 /* hwrm_func_backing_store_qcaps_output (size:704b/88B) */ 2051 struct hwrm_func_backing_store_qcaps_output { 2052 __le16 error_code; 2053 __le16 req_type; 2054 __le16 seq_id; 2055 __le16 resp_len; 2056 __le32 qp_max_entries; 2057 __le16 qp_min_qp1_entries; 2058 __le16 qp_max_l2_entries; 2059 __le16 qp_entry_size; 2060 __le16 srq_max_l2_entries; 2061 __le32 srq_max_entries; 2062 __le16 srq_entry_size; 2063 __le16 cq_max_l2_entries; 2064 __le32 cq_max_entries; 2065 __le16 cq_entry_size; 2066 __le16 vnic_max_vnic_entries; 2067 __le16 vnic_max_ring_table_entries; 2068 __le16 vnic_entry_size; 2069 __le32 stat_max_entries; 2070 __le16 stat_entry_size; 2071 __le16 tqm_entry_size; 2072 __le32 tqm_min_entries_per_ring; 2073 __le32 tqm_max_entries_per_ring; 2074 __le32 mrav_max_entries; 2075 __le16 mrav_entry_size; 2076 __le16 tim_entry_size; 2077 __le32 tim_max_entries; 2078 __le16 mrav_num_entries_units; 2079 u8 tqm_entries_multiple; 2080 u8 ctx_kind_initializer; 2081 __le16 ctx_init_mask; 2082 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2083 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2084 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2085 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2086 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2087 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2088 u8 qp_init_offset; 2089 u8 srq_init_offset; 2090 u8 cq_init_offset; 2091 u8 vnic_init_offset; 2092 u8 tqm_fp_rings_count; 2093 u8 stat_init_offset; 2094 u8 mrav_init_offset; 2095 u8 tqm_fp_rings_count_ext; 2096 u8 rsvd[5]; 2097 u8 valid; 2098 }; 2099 2100 /* tqm_fp_ring_cfg (size:128b/16B) */ 2101 struct tqm_fp_ring_cfg { 2102 u8 tqm_ring_pg_size_tqm_ring_lvl; 2103 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2104 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2105 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2106 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2107 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2108 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2109 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2110 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2111 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2112 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2113 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2114 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2115 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2116 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2117 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2118 u8 unused[3]; 2119 __le32 tqm_ring_num_entries; 2120 __le64 tqm_ring_page_dir; 2121 }; 2122 2123 /* hwrm_func_backing_store_cfg_input (size:2432b/304B) */ 2124 struct hwrm_func_backing_store_cfg_input { 2125 __le16 req_type; 2126 __le16 cmpl_ring; 2127 __le16 seq_id; 2128 __le16 target_id; 2129 __le64 resp_addr; 2130 __le32 flags; 2131 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2132 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2133 __le32 enables; 2134 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2135 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2136 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2137 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2138 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2139 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2140 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2141 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2142 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2143 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2144 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2145 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2146 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2147 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2148 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2149 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2150 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2151 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2152 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2153 u8 qpc_pg_size_qpc_lvl; 2154 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2155 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2156 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2157 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2158 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2159 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2160 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2161 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2162 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2163 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2164 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2165 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2166 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2167 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2168 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2169 u8 srq_pg_size_srq_lvl; 2170 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2171 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2172 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2173 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2174 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2175 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2176 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2177 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2178 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2179 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2180 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2181 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2182 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2183 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2184 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2185 u8 cq_pg_size_cq_lvl; 2186 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2187 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2188 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2189 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2190 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2191 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2192 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2193 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2194 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2195 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2196 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2197 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2198 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2199 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2200 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2201 u8 vnic_pg_size_vnic_lvl; 2202 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2203 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2204 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2205 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2206 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2207 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2208 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2209 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2210 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2211 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2212 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2213 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2214 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2215 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2216 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2217 u8 stat_pg_size_stat_lvl; 2218 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2219 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2220 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2221 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2222 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2223 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2224 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2225 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2226 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2227 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2228 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2229 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2230 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2231 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2232 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2233 u8 tqm_sp_pg_size_tqm_sp_lvl; 2234 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2235 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2236 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2237 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2238 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2239 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2240 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2241 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2242 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2243 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2244 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2245 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2246 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2247 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2248 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2249 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2250 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2251 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2252 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2253 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2254 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2255 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2256 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2257 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2258 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2259 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2260 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2261 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2262 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2263 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2264 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2265 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2266 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2267 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2268 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2269 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2270 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2271 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2272 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2273 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2274 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2275 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2276 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2277 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2278 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2279 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2280 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2281 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2282 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2283 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2284 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2285 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2286 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2287 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2288 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2289 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2290 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2291 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2292 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2293 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2294 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2295 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2296 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2297 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2298 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2299 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2300 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2301 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2302 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2303 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2304 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2305 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2306 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2307 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2308 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2309 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2310 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2311 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2312 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2313 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2314 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2315 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2316 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2317 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2318 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2319 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2320 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2321 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2322 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2323 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2324 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2325 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2326 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2327 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2328 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2329 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2330 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2331 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2332 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2333 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2334 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2335 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2336 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2337 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2338 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2339 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2340 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2341 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2342 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2343 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2344 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2345 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2346 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2347 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2348 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2349 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2350 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2351 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2352 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2353 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2354 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2355 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2356 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2357 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2358 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2359 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2360 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2361 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2362 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2363 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2364 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2365 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2366 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2367 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2368 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2369 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2370 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2371 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2372 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2373 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2374 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2375 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2376 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2377 u8 mrav_pg_size_mrav_lvl; 2378 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2379 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2380 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2381 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2382 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2383 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2384 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2385 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2386 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2387 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2388 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2389 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2390 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2391 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2392 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2393 u8 tim_pg_size_tim_lvl; 2394 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2395 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2396 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2397 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2398 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2399 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2400 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2401 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2402 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2403 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2404 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2405 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2406 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2407 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2408 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2409 __le64 qpc_page_dir; 2410 __le64 srq_page_dir; 2411 __le64 cq_page_dir; 2412 __le64 vnic_page_dir; 2413 __le64 stat_page_dir; 2414 __le64 tqm_sp_page_dir; 2415 __le64 tqm_ring0_page_dir; 2416 __le64 tqm_ring1_page_dir; 2417 __le64 tqm_ring2_page_dir; 2418 __le64 tqm_ring3_page_dir; 2419 __le64 tqm_ring4_page_dir; 2420 __le64 tqm_ring5_page_dir; 2421 __le64 tqm_ring6_page_dir; 2422 __le64 tqm_ring7_page_dir; 2423 __le64 mrav_page_dir; 2424 __le64 tim_page_dir; 2425 __le32 qp_num_entries; 2426 __le32 srq_num_entries; 2427 __le32 cq_num_entries; 2428 __le32 stat_num_entries; 2429 __le32 tqm_sp_num_entries; 2430 __le32 tqm_ring0_num_entries; 2431 __le32 tqm_ring1_num_entries; 2432 __le32 tqm_ring2_num_entries; 2433 __le32 tqm_ring3_num_entries; 2434 __le32 tqm_ring4_num_entries; 2435 __le32 tqm_ring5_num_entries; 2436 __le32 tqm_ring6_num_entries; 2437 __le32 tqm_ring7_num_entries; 2438 __le32 mrav_num_entries; 2439 __le32 tim_num_entries; 2440 __le16 qp_num_qp1_entries; 2441 __le16 qp_num_l2_entries; 2442 __le16 qp_entry_size; 2443 __le16 srq_num_l2_entries; 2444 __le16 srq_entry_size; 2445 __le16 cq_num_l2_entries; 2446 __le16 cq_entry_size; 2447 __le16 vnic_num_vnic_entries; 2448 __le16 vnic_num_ring_table_entries; 2449 __le16 vnic_entry_size; 2450 __le16 stat_entry_size; 2451 __le16 tqm_entry_size; 2452 __le16 mrav_entry_size; 2453 __le16 tim_entry_size; 2454 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2455 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2456 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2457 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2458 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2459 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2460 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2461 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2462 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2463 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2464 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2465 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2466 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2467 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2468 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2469 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2470 u8 ring8_unused[3]; 2471 __le32 tqm_ring8_num_entries; 2472 __le64 tqm_ring8_page_dir; 2473 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2474 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2475 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2476 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2477 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2478 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2479 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2480 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2481 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2482 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2483 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2484 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2485 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2486 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2487 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2488 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2489 u8 ring9_unused[3]; 2490 __le32 tqm_ring9_num_entries; 2491 __le64 tqm_ring9_page_dir; 2492 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2493 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2494 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2495 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2496 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2497 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2498 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2499 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2500 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2501 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2502 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2503 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2504 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2505 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2506 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2507 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2508 u8 ring10_unused[3]; 2509 __le32 tqm_ring10_num_entries; 2510 __le64 tqm_ring10_page_dir; 2511 }; 2512 2513 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2514 struct hwrm_func_backing_store_cfg_output { 2515 __le16 error_code; 2516 __le16 req_type; 2517 __le16 seq_id; 2518 __le16 resp_len; 2519 u8 unused_0[7]; 2520 u8 valid; 2521 }; 2522 2523 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2524 struct hwrm_error_recovery_qcfg_input { 2525 __le16 req_type; 2526 __le16 cmpl_ring; 2527 __le16 seq_id; 2528 __le16 target_id; 2529 __le64 resp_addr; 2530 u8 unused_0[8]; 2531 }; 2532 2533 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2534 struct hwrm_error_recovery_qcfg_output { 2535 __le16 error_code; 2536 __le16 req_type; 2537 __le16 seq_id; 2538 __le16 resp_len; 2539 __le32 flags; 2540 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2541 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2542 __le32 driver_polling_freq; 2543 __le32 master_func_wait_period; 2544 __le32 normal_func_wait_period; 2545 __le32 master_func_wait_period_after_reset; 2546 __le32 max_bailout_time_after_reset; 2547 __le32 fw_health_status_reg; 2548 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2549 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2550 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2551 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2552 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2553 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2554 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2555 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2556 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2557 __le32 fw_heartbeat_reg; 2558 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2559 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2560 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2561 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2562 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2563 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2564 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2565 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2566 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2567 __le32 fw_reset_cnt_reg; 2568 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2569 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2570 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2571 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2572 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2573 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2574 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2575 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2576 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2577 __le32 reset_inprogress_reg; 2578 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2579 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2580 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2581 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2582 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2583 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2584 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2585 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2586 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2587 __le32 reset_inprogress_reg_mask; 2588 u8 unused_0[3]; 2589 u8 reg_array_cnt; 2590 __le32 reset_reg[16]; 2591 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2592 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2593 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2594 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2595 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2596 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2597 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2598 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2599 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2600 __le32 reset_reg_val[16]; 2601 u8 delay_after_reset[16]; 2602 __le32 err_recovery_cnt_reg; 2603 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2604 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2605 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2606 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2607 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2608 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2609 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2610 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2611 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2612 u8 unused_1[3]; 2613 u8 valid; 2614 }; 2615 2616 /* hwrm_func_echo_response_input (size:192b/24B) */ 2617 struct hwrm_func_echo_response_input { 2618 __le16 req_type; 2619 __le16 cmpl_ring; 2620 __le16 seq_id; 2621 __le16 target_id; 2622 __le64 resp_addr; 2623 __le32 event_data1; 2624 __le32 event_data2; 2625 }; 2626 2627 /* hwrm_func_echo_response_output (size:128b/16B) */ 2628 struct hwrm_func_echo_response_output { 2629 __le16 error_code; 2630 __le16 req_type; 2631 __le16 seq_id; 2632 __le16 resp_len; 2633 u8 unused_0[7]; 2634 u8 valid; 2635 }; 2636 2637 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2638 struct hwrm_func_drv_if_change_input { 2639 __le16 req_type; 2640 __le16 cmpl_ring; 2641 __le16 seq_id; 2642 __le16 target_id; 2643 __le64 resp_addr; 2644 __le32 flags; 2645 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2646 __le32 unused; 2647 }; 2648 2649 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2650 struct hwrm_func_drv_if_change_output { 2651 __le16 error_code; 2652 __le16 req_type; 2653 __le16 seq_id; 2654 __le16 resp_len; 2655 __le32 flags; 2656 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2657 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2658 u8 unused_0[3]; 2659 u8 valid; 2660 }; 2661 2662 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2663 struct hwrm_port_phy_cfg_input { 2664 __le16 req_type; 2665 __le16 cmpl_ring; 2666 __le16 seq_id; 2667 __le16 target_id; 2668 __le64 resp_addr; 2669 __le32 flags; 2670 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2671 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2672 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2673 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2674 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2675 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2676 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2677 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2678 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2679 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2680 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2681 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2682 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2683 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2684 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2685 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 2686 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 2687 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 2688 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 2689 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 2690 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 2691 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 2692 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 2693 __le32 enables; 2694 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2695 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2696 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2697 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2698 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2699 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2700 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2701 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2702 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2703 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2704 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2705 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 2706 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 2707 __le16 port_id; 2708 __le16 force_link_speed; 2709 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2710 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2711 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2712 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2713 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2714 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2715 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2716 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2717 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2718 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2719 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2720 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2721 u8 auto_mode; 2722 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2723 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2724 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2725 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2726 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2727 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2728 u8 auto_duplex; 2729 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2730 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2731 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2732 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2733 u8 auto_pause; 2734 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2735 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2736 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2737 u8 unused_0; 2738 __le16 auto_link_speed; 2739 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2740 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2741 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2742 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2743 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2744 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2745 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2746 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2747 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2748 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2749 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2750 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2751 __le16 auto_link_speed_mask; 2752 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2753 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2754 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2755 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2756 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2757 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2758 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2759 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2760 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2761 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2762 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2763 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2764 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2765 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2766 u8 wirespeed; 2767 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2768 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2769 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2770 u8 lpbk; 2771 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2772 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2773 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2774 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2775 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2776 u8 force_pause; 2777 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2778 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2779 u8 unused_1; 2780 __le32 preemphasis; 2781 __le16 eee_link_speed_mask; 2782 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2783 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2784 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2785 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2786 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2787 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2788 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2789 __le16 force_pam4_link_speed; 2790 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2791 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2792 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2793 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 2794 __le32 tx_lpi_timer; 2795 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2796 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2797 __le16 auto_link_pam4_speed_mask; 2798 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 2799 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 2800 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 2801 u8 unused_2[2]; 2802 }; 2803 2804 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2805 struct hwrm_port_phy_cfg_output { 2806 __le16 error_code; 2807 __le16 req_type; 2808 __le16 seq_id; 2809 __le16 resp_len; 2810 u8 unused_0[7]; 2811 u8 valid; 2812 }; 2813 2814 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2815 struct hwrm_port_phy_cfg_cmd_err { 2816 u8 code; 2817 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2818 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2819 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2820 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2821 u8 unused_0[7]; 2822 }; 2823 2824 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2825 struct hwrm_port_phy_qcfg_input { 2826 __le16 req_type; 2827 __le16 cmpl_ring; 2828 __le16 seq_id; 2829 __le16 target_id; 2830 __le64 resp_addr; 2831 __le16 port_id; 2832 u8 unused_0[6]; 2833 }; 2834 2835 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2836 struct hwrm_port_phy_qcfg_output { 2837 __le16 error_code; 2838 __le16 req_type; 2839 __le16 seq_id; 2840 __le16 resp_len; 2841 u8 link; 2842 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2843 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2844 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2845 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2846 u8 active_fec_signal_mode; 2847 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 2848 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 2849 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 2850 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 2851 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 2852 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 2853 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 2854 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 2855 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 2856 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 2857 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 2858 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 2859 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 2860 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 2861 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 2862 __le16 link_speed; 2863 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2864 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2865 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2866 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2867 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2868 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2869 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2870 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2871 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2872 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2873 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2874 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2875 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2876 u8 duplex_cfg; 2877 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2878 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2879 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2880 u8 pause; 2881 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2882 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2883 __le16 support_speeds; 2884 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2885 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2886 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2887 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2888 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2889 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2890 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2891 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2892 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2893 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2894 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2895 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2896 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2897 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2898 __le16 force_link_speed; 2899 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2900 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2901 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2902 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2903 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2904 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2905 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2906 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2907 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2908 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2909 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2910 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2911 u8 auto_mode; 2912 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2913 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2914 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2915 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2916 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2917 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2918 u8 auto_pause; 2919 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2920 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2921 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2922 __le16 auto_link_speed; 2923 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2924 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2925 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2926 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2927 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2928 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2929 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2930 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2931 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2932 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2933 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2934 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2935 __le16 auto_link_speed_mask; 2936 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2937 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2938 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2939 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2940 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2941 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2942 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2943 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2944 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2945 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2946 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2947 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2948 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2949 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2950 u8 wirespeed; 2951 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2952 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2953 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2954 u8 lpbk; 2955 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2956 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2957 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2958 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2959 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2960 u8 force_pause; 2961 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2962 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2963 u8 module_status; 2964 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2965 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2966 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2967 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2968 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2969 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2970 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2971 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2972 __le32 preemphasis; 2973 u8 phy_maj; 2974 u8 phy_min; 2975 u8 phy_bld; 2976 u8 phy_type; 2977 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2978 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2979 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2980 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2981 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2982 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2983 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2984 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2985 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2986 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2987 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2988 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2989 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2990 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2991 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2992 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2993 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2994 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2995 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2996 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2997 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2998 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2999 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 3000 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 3001 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 3002 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 3003 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 3004 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 3005 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 3006 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 3007 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 3008 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 3009 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 3010 u8 media_type; 3011 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 3012 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 3013 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 3014 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 3015 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 3016 u8 xcvr_pkg_type; 3017 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 3018 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 3019 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 3020 u8 eee_config_phy_addr; 3021 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 3022 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 3023 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 3024 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 3025 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 3026 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 3027 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 3028 u8 parallel_detect; 3029 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 3030 __le16 link_partner_adv_speeds; 3031 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 3032 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 3033 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 3034 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 3035 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 3036 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 3037 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 3038 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 3039 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 3040 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 3041 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 3042 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 3043 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 3044 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 3045 u8 link_partner_adv_auto_mode; 3046 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 3047 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 3048 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 3049 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 3050 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 3051 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 3052 u8 link_partner_adv_pause; 3053 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 3054 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 3055 __le16 adv_eee_link_speed_mask; 3056 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3057 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3058 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3059 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3060 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3061 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3062 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3063 __le16 link_partner_adv_eee_link_speed_mask; 3064 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3065 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3066 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3067 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3068 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3069 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3070 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3071 __le32 xcvr_identifier_type_tx_lpi_timer; 3072 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 3073 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 3074 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 3075 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 3076 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 3077 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 3078 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 3079 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 3080 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3081 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3082 __le16 fec_cfg; 3083 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3084 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3085 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3086 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3087 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3088 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3089 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3090 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3091 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 3092 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 3093 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 3094 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 3095 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 3096 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 3097 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3098 u8 duplex_state; 3099 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3100 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3101 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3102 u8 option_flags; 3103 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 3104 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 3105 char phy_vendor_name[16]; 3106 char phy_vendor_partnumber[16]; 3107 __le16 support_pam4_speeds; 3108 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3109 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3110 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3111 __le16 force_pam4_link_speed; 3112 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3113 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3114 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3115 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3116 __le16 auto_pam4_link_speed_mask; 3117 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3118 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3119 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 3120 u8 link_partner_pam4_adv_speeds; 3121 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3122 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3123 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3124 u8 valid; 3125 }; 3126 3127 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3128 struct hwrm_port_mac_cfg_input { 3129 __le16 req_type; 3130 __le16 cmpl_ring; 3131 __le16 seq_id; 3132 __le16 target_id; 3133 __le64 resp_addr; 3134 __le32 flags; 3135 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3136 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3137 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3138 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 3139 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 3140 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 3141 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 3142 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3143 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3144 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3145 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3146 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3147 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 3148 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3149 __le32 enables; 3150 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3151 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3152 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3153 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3154 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 3155 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 3156 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3157 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 3158 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 3159 __le16 port_id; 3160 u8 ipg; 3161 u8 lpbk; 3162 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3163 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3164 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3165 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3166 u8 vlan_pri2cos_map_pri; 3167 u8 reserved1; 3168 u8 tunnel_pri2cos_map_pri; 3169 u8 dscp2pri_map_pri; 3170 __le16 rx_ts_capture_ptp_msg_type; 3171 __le16 tx_ts_capture_ptp_msg_type; 3172 u8 cos_field_cfg; 3173 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3174 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3175 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3176 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3177 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3178 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3179 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3180 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3181 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3182 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3183 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3184 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3185 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3186 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3187 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3188 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3189 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3190 u8 unused_0[3]; 3191 __s32 ptp_freq_adj_ppb; 3192 u8 unused_1[4]; 3193 }; 3194 3195 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3196 struct hwrm_port_mac_cfg_output { 3197 __le16 error_code; 3198 __le16 req_type; 3199 __le16 seq_id; 3200 __le16 resp_len; 3201 __le16 mru; 3202 __le16 mtu; 3203 u8 ipg; 3204 u8 lpbk; 3205 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3206 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3207 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3208 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3209 u8 unused_0; 3210 u8 valid; 3211 }; 3212 3213 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3214 struct hwrm_port_mac_ptp_qcfg_input { 3215 __le16 req_type; 3216 __le16 cmpl_ring; 3217 __le16 seq_id; 3218 __le16 target_id; 3219 __le64 resp_addr; 3220 __le16 port_id; 3221 u8 unused_0[6]; 3222 }; 3223 3224 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 3225 struct hwrm_port_mac_ptp_qcfg_output { 3226 __le16 error_code; 3227 __le16 req_type; 3228 __le16 seq_id; 3229 __le16 resp_len; 3230 u8 flags; 3231 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3232 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3233 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3234 u8 unused_0[3]; 3235 __le32 rx_ts_reg_off_lower; 3236 __le32 rx_ts_reg_off_upper; 3237 __le32 rx_ts_reg_off_seq_id; 3238 __le32 rx_ts_reg_off_src_id_0; 3239 __le32 rx_ts_reg_off_src_id_1; 3240 __le32 rx_ts_reg_off_src_id_2; 3241 __le32 rx_ts_reg_off_domain_id; 3242 __le32 rx_ts_reg_off_fifo; 3243 __le32 rx_ts_reg_off_fifo_adv; 3244 __le32 rx_ts_reg_off_granularity; 3245 __le32 tx_ts_reg_off_lower; 3246 __le32 tx_ts_reg_off_upper; 3247 __le32 tx_ts_reg_off_seq_id; 3248 __le32 tx_ts_reg_off_fifo; 3249 __le32 tx_ts_reg_off_granularity; 3250 u8 unused_1[7]; 3251 u8 valid; 3252 }; 3253 3254 /* tx_port_stats (size:3264b/408B) */ 3255 struct tx_port_stats { 3256 __le64 tx_64b_frames; 3257 __le64 tx_65b_127b_frames; 3258 __le64 tx_128b_255b_frames; 3259 __le64 tx_256b_511b_frames; 3260 __le64 tx_512b_1023b_frames; 3261 __le64 tx_1024b_1518b_frames; 3262 __le64 tx_good_vlan_frames; 3263 __le64 tx_1519b_2047b_frames; 3264 __le64 tx_2048b_4095b_frames; 3265 __le64 tx_4096b_9216b_frames; 3266 __le64 tx_9217b_16383b_frames; 3267 __le64 tx_good_frames; 3268 __le64 tx_total_frames; 3269 __le64 tx_ucast_frames; 3270 __le64 tx_mcast_frames; 3271 __le64 tx_bcast_frames; 3272 __le64 tx_pause_frames; 3273 __le64 tx_pfc_frames; 3274 __le64 tx_jabber_frames; 3275 __le64 tx_fcs_err_frames; 3276 __le64 tx_control_frames; 3277 __le64 tx_oversz_frames; 3278 __le64 tx_single_dfrl_frames; 3279 __le64 tx_multi_dfrl_frames; 3280 __le64 tx_single_coll_frames; 3281 __le64 tx_multi_coll_frames; 3282 __le64 tx_late_coll_frames; 3283 __le64 tx_excessive_coll_frames; 3284 __le64 tx_frag_frames; 3285 __le64 tx_err; 3286 __le64 tx_tagged_frames; 3287 __le64 tx_dbl_tagged_frames; 3288 __le64 tx_runt_frames; 3289 __le64 tx_fifo_underruns; 3290 __le64 tx_pfc_ena_frames_pri0; 3291 __le64 tx_pfc_ena_frames_pri1; 3292 __le64 tx_pfc_ena_frames_pri2; 3293 __le64 tx_pfc_ena_frames_pri3; 3294 __le64 tx_pfc_ena_frames_pri4; 3295 __le64 tx_pfc_ena_frames_pri5; 3296 __le64 tx_pfc_ena_frames_pri6; 3297 __le64 tx_pfc_ena_frames_pri7; 3298 __le64 tx_eee_lpi_events; 3299 __le64 tx_eee_lpi_duration; 3300 __le64 tx_llfc_logical_msgs; 3301 __le64 tx_hcfc_msgs; 3302 __le64 tx_total_collisions; 3303 __le64 tx_bytes; 3304 __le64 tx_xthol_frames; 3305 __le64 tx_stat_discard; 3306 __le64 tx_stat_error; 3307 }; 3308 3309 /* rx_port_stats (size:4224b/528B) */ 3310 struct rx_port_stats { 3311 __le64 rx_64b_frames; 3312 __le64 rx_65b_127b_frames; 3313 __le64 rx_128b_255b_frames; 3314 __le64 rx_256b_511b_frames; 3315 __le64 rx_512b_1023b_frames; 3316 __le64 rx_1024b_1518b_frames; 3317 __le64 rx_good_vlan_frames; 3318 __le64 rx_1519b_2047b_frames; 3319 __le64 rx_2048b_4095b_frames; 3320 __le64 rx_4096b_9216b_frames; 3321 __le64 rx_9217b_16383b_frames; 3322 __le64 rx_total_frames; 3323 __le64 rx_ucast_frames; 3324 __le64 rx_mcast_frames; 3325 __le64 rx_bcast_frames; 3326 __le64 rx_fcs_err_frames; 3327 __le64 rx_ctrl_frames; 3328 __le64 rx_pause_frames; 3329 __le64 rx_pfc_frames; 3330 __le64 rx_unsupported_opcode_frames; 3331 __le64 rx_unsupported_da_pausepfc_frames; 3332 __le64 rx_wrong_sa_frames; 3333 __le64 rx_align_err_frames; 3334 __le64 rx_oor_len_frames; 3335 __le64 rx_code_err_frames; 3336 __le64 rx_false_carrier_frames; 3337 __le64 rx_ovrsz_frames; 3338 __le64 rx_jbr_frames; 3339 __le64 rx_mtu_err_frames; 3340 __le64 rx_match_crc_frames; 3341 __le64 rx_promiscuous_frames; 3342 __le64 rx_tagged_frames; 3343 __le64 rx_double_tagged_frames; 3344 __le64 rx_trunc_frames; 3345 __le64 rx_good_frames; 3346 __le64 rx_pfc_xon2xoff_frames_pri0; 3347 __le64 rx_pfc_xon2xoff_frames_pri1; 3348 __le64 rx_pfc_xon2xoff_frames_pri2; 3349 __le64 rx_pfc_xon2xoff_frames_pri3; 3350 __le64 rx_pfc_xon2xoff_frames_pri4; 3351 __le64 rx_pfc_xon2xoff_frames_pri5; 3352 __le64 rx_pfc_xon2xoff_frames_pri6; 3353 __le64 rx_pfc_xon2xoff_frames_pri7; 3354 __le64 rx_pfc_ena_frames_pri0; 3355 __le64 rx_pfc_ena_frames_pri1; 3356 __le64 rx_pfc_ena_frames_pri2; 3357 __le64 rx_pfc_ena_frames_pri3; 3358 __le64 rx_pfc_ena_frames_pri4; 3359 __le64 rx_pfc_ena_frames_pri5; 3360 __le64 rx_pfc_ena_frames_pri6; 3361 __le64 rx_pfc_ena_frames_pri7; 3362 __le64 rx_sch_crc_err_frames; 3363 __le64 rx_undrsz_frames; 3364 __le64 rx_frag_frames; 3365 __le64 rx_eee_lpi_events; 3366 __le64 rx_eee_lpi_duration; 3367 __le64 rx_llfc_physical_msgs; 3368 __le64 rx_llfc_logical_msgs; 3369 __le64 rx_llfc_msgs_with_crc_err; 3370 __le64 rx_hcfc_msgs; 3371 __le64 rx_hcfc_msgs_with_crc_err; 3372 __le64 rx_bytes; 3373 __le64 rx_runt_bytes; 3374 __le64 rx_runt_frames; 3375 __le64 rx_stat_discard; 3376 __le64 rx_stat_err; 3377 }; 3378 3379 /* hwrm_port_qstats_input (size:320b/40B) */ 3380 struct hwrm_port_qstats_input { 3381 __le16 req_type; 3382 __le16 cmpl_ring; 3383 __le16 seq_id; 3384 __le16 target_id; 3385 __le64 resp_addr; 3386 __le16 port_id; 3387 u8 flags; 3388 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3389 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3390 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3391 u8 unused_0[5]; 3392 __le64 tx_stat_host_addr; 3393 __le64 rx_stat_host_addr; 3394 }; 3395 3396 /* hwrm_port_qstats_output (size:128b/16B) */ 3397 struct hwrm_port_qstats_output { 3398 __le16 error_code; 3399 __le16 req_type; 3400 __le16 seq_id; 3401 __le16 resp_len; 3402 __le16 tx_stat_size; 3403 __le16 rx_stat_size; 3404 u8 unused_0[3]; 3405 u8 valid; 3406 }; 3407 3408 /* tx_port_stats_ext (size:2048b/256B) */ 3409 struct tx_port_stats_ext { 3410 __le64 tx_bytes_cos0; 3411 __le64 tx_bytes_cos1; 3412 __le64 tx_bytes_cos2; 3413 __le64 tx_bytes_cos3; 3414 __le64 tx_bytes_cos4; 3415 __le64 tx_bytes_cos5; 3416 __le64 tx_bytes_cos6; 3417 __le64 tx_bytes_cos7; 3418 __le64 tx_packets_cos0; 3419 __le64 tx_packets_cos1; 3420 __le64 tx_packets_cos2; 3421 __le64 tx_packets_cos3; 3422 __le64 tx_packets_cos4; 3423 __le64 tx_packets_cos5; 3424 __le64 tx_packets_cos6; 3425 __le64 tx_packets_cos7; 3426 __le64 pfc_pri0_tx_duration_us; 3427 __le64 pfc_pri0_tx_transitions; 3428 __le64 pfc_pri1_tx_duration_us; 3429 __le64 pfc_pri1_tx_transitions; 3430 __le64 pfc_pri2_tx_duration_us; 3431 __le64 pfc_pri2_tx_transitions; 3432 __le64 pfc_pri3_tx_duration_us; 3433 __le64 pfc_pri3_tx_transitions; 3434 __le64 pfc_pri4_tx_duration_us; 3435 __le64 pfc_pri4_tx_transitions; 3436 __le64 pfc_pri5_tx_duration_us; 3437 __le64 pfc_pri5_tx_transitions; 3438 __le64 pfc_pri6_tx_duration_us; 3439 __le64 pfc_pri6_tx_transitions; 3440 __le64 pfc_pri7_tx_duration_us; 3441 __le64 pfc_pri7_tx_transitions; 3442 }; 3443 3444 /* rx_port_stats_ext (size:3648b/456B) */ 3445 struct rx_port_stats_ext { 3446 __le64 link_down_events; 3447 __le64 continuous_pause_events; 3448 __le64 resume_pause_events; 3449 __le64 continuous_roce_pause_events; 3450 __le64 resume_roce_pause_events; 3451 __le64 rx_bytes_cos0; 3452 __le64 rx_bytes_cos1; 3453 __le64 rx_bytes_cos2; 3454 __le64 rx_bytes_cos3; 3455 __le64 rx_bytes_cos4; 3456 __le64 rx_bytes_cos5; 3457 __le64 rx_bytes_cos6; 3458 __le64 rx_bytes_cos7; 3459 __le64 rx_packets_cos0; 3460 __le64 rx_packets_cos1; 3461 __le64 rx_packets_cos2; 3462 __le64 rx_packets_cos3; 3463 __le64 rx_packets_cos4; 3464 __le64 rx_packets_cos5; 3465 __le64 rx_packets_cos6; 3466 __le64 rx_packets_cos7; 3467 __le64 pfc_pri0_rx_duration_us; 3468 __le64 pfc_pri0_rx_transitions; 3469 __le64 pfc_pri1_rx_duration_us; 3470 __le64 pfc_pri1_rx_transitions; 3471 __le64 pfc_pri2_rx_duration_us; 3472 __le64 pfc_pri2_rx_transitions; 3473 __le64 pfc_pri3_rx_duration_us; 3474 __le64 pfc_pri3_rx_transitions; 3475 __le64 pfc_pri4_rx_duration_us; 3476 __le64 pfc_pri4_rx_transitions; 3477 __le64 pfc_pri5_rx_duration_us; 3478 __le64 pfc_pri5_rx_transitions; 3479 __le64 pfc_pri6_rx_duration_us; 3480 __le64 pfc_pri6_rx_transitions; 3481 __le64 pfc_pri7_rx_duration_us; 3482 __le64 pfc_pri7_rx_transitions; 3483 __le64 rx_bits; 3484 __le64 rx_buffer_passed_threshold; 3485 __le64 rx_pcs_symbol_err; 3486 __le64 rx_corrected_bits; 3487 __le64 rx_discard_bytes_cos0; 3488 __le64 rx_discard_bytes_cos1; 3489 __le64 rx_discard_bytes_cos2; 3490 __le64 rx_discard_bytes_cos3; 3491 __le64 rx_discard_bytes_cos4; 3492 __le64 rx_discard_bytes_cos5; 3493 __le64 rx_discard_bytes_cos6; 3494 __le64 rx_discard_bytes_cos7; 3495 __le64 rx_discard_packets_cos0; 3496 __le64 rx_discard_packets_cos1; 3497 __le64 rx_discard_packets_cos2; 3498 __le64 rx_discard_packets_cos3; 3499 __le64 rx_discard_packets_cos4; 3500 __le64 rx_discard_packets_cos5; 3501 __le64 rx_discard_packets_cos6; 3502 __le64 rx_discard_packets_cos7; 3503 }; 3504 3505 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3506 struct hwrm_port_qstats_ext_input { 3507 __le16 req_type; 3508 __le16 cmpl_ring; 3509 __le16 seq_id; 3510 __le16 target_id; 3511 __le64 resp_addr; 3512 __le16 port_id; 3513 __le16 tx_stat_size; 3514 __le16 rx_stat_size; 3515 u8 flags; 3516 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3517 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3518 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3519 u8 unused_0; 3520 __le64 tx_stat_host_addr; 3521 __le64 rx_stat_host_addr; 3522 }; 3523 3524 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3525 struct hwrm_port_qstats_ext_output { 3526 __le16 error_code; 3527 __le16 req_type; 3528 __le16 seq_id; 3529 __le16 resp_len; 3530 __le16 tx_stat_size; 3531 __le16 rx_stat_size; 3532 __le16 total_active_cos_queues; 3533 u8 flags; 3534 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3535 u8 valid; 3536 }; 3537 3538 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3539 struct hwrm_port_lpbk_qstats_input { 3540 __le16 req_type; 3541 __le16 cmpl_ring; 3542 __le16 seq_id; 3543 __le16 target_id; 3544 __le64 resp_addr; 3545 }; 3546 3547 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3548 struct hwrm_port_lpbk_qstats_output { 3549 __le16 error_code; 3550 __le16 req_type; 3551 __le16 seq_id; 3552 __le16 resp_len; 3553 __le64 lpbk_ucast_frames; 3554 __le64 lpbk_mcast_frames; 3555 __le64 lpbk_bcast_frames; 3556 __le64 lpbk_ucast_bytes; 3557 __le64 lpbk_mcast_bytes; 3558 __le64 lpbk_bcast_bytes; 3559 __le64 tx_stat_discard; 3560 __le64 tx_stat_error; 3561 __le64 rx_stat_discard; 3562 __le64 rx_stat_error; 3563 u8 unused_0[7]; 3564 u8 valid; 3565 }; 3566 3567 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 3568 struct hwrm_port_ecn_qstats_input { 3569 __le16 req_type; 3570 __le16 cmpl_ring; 3571 __le16 seq_id; 3572 __le16 target_id; 3573 __le64 resp_addr; 3574 __le16 port_id; 3575 __le16 ecn_stat_buf_size; 3576 u8 flags; 3577 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3578 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3579 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 3580 u8 unused_0[3]; 3581 __le64 ecn_stat_host_addr; 3582 }; 3583 3584 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 3585 struct hwrm_port_ecn_qstats_output { 3586 __le16 error_code; 3587 __le16 req_type; 3588 __le16 seq_id; 3589 __le16 resp_len; 3590 __le16 ecn_stat_buf_size; 3591 u8 mark_en; 3592 u8 unused_0[4]; 3593 u8 valid; 3594 }; 3595 3596 /* port_stats_ecn (size:512b/64B) */ 3597 struct port_stats_ecn { 3598 __le64 mark_cnt_cos0; 3599 __le64 mark_cnt_cos1; 3600 __le64 mark_cnt_cos2; 3601 __le64 mark_cnt_cos3; 3602 __le64 mark_cnt_cos4; 3603 __le64 mark_cnt_cos5; 3604 __le64 mark_cnt_cos6; 3605 __le64 mark_cnt_cos7; 3606 }; 3607 3608 /* hwrm_port_clr_stats_input (size:192b/24B) */ 3609 struct hwrm_port_clr_stats_input { 3610 __le16 req_type; 3611 __le16 cmpl_ring; 3612 __le16 seq_id; 3613 __le16 target_id; 3614 __le64 resp_addr; 3615 __le16 port_id; 3616 u8 flags; 3617 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3618 u8 unused_0[5]; 3619 }; 3620 3621 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3622 struct hwrm_port_clr_stats_output { 3623 __le16 error_code; 3624 __le16 req_type; 3625 __le16 seq_id; 3626 __le16 resp_len; 3627 u8 unused_0[7]; 3628 u8 valid; 3629 }; 3630 3631 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3632 struct hwrm_port_lpbk_clr_stats_input { 3633 __le16 req_type; 3634 __le16 cmpl_ring; 3635 __le16 seq_id; 3636 __le16 target_id; 3637 __le64 resp_addr; 3638 }; 3639 3640 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3641 struct hwrm_port_lpbk_clr_stats_output { 3642 __le16 error_code; 3643 __le16 req_type; 3644 __le16 seq_id; 3645 __le16 resp_len; 3646 u8 unused_0[7]; 3647 u8 valid; 3648 }; 3649 3650 /* hwrm_port_ts_query_input (size:192b/24B) */ 3651 struct hwrm_port_ts_query_input { 3652 __le16 req_type; 3653 __le16 cmpl_ring; 3654 __le16 seq_id; 3655 __le16 target_id; 3656 __le64 resp_addr; 3657 __le32 flags; 3658 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3659 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3660 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3661 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3662 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3663 __le16 port_id; 3664 u8 unused_0[2]; 3665 }; 3666 3667 /* hwrm_port_ts_query_output (size:192b/24B) */ 3668 struct hwrm_port_ts_query_output { 3669 __le16 error_code; 3670 __le16 req_type; 3671 __le16 seq_id; 3672 __le16 resp_len; 3673 __le64 ptp_msg_ts; 3674 __le16 ptp_msg_seqid; 3675 u8 unused_0[5]; 3676 u8 valid; 3677 }; 3678 3679 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3680 struct hwrm_port_phy_qcaps_input { 3681 __le16 req_type; 3682 __le16 cmpl_ring; 3683 __le16 seq_id; 3684 __le16 target_id; 3685 __le64 resp_addr; 3686 __le16 port_id; 3687 u8 unused_0[6]; 3688 }; 3689 3690 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 3691 struct hwrm_port_phy_qcaps_output { 3692 __le16 error_code; 3693 __le16 req_type; 3694 __le16 seq_id; 3695 __le16 resp_len; 3696 u8 flags; 3697 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3698 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3699 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 3700 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3701 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 3702 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 3703 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 3704 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 3705 u8 port_cnt; 3706 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3707 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3708 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3709 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3710 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3711 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3712 __le16 supported_speeds_force_mode; 3713 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3714 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3715 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3716 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3717 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3718 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3719 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3720 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3721 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3722 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3723 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3724 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3725 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3726 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3727 __le16 supported_speeds_auto_mode; 3728 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3729 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3730 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3731 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3732 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3733 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3734 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3735 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3736 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3737 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3738 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3739 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3740 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3741 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3742 __le16 supported_speeds_eee_mode; 3743 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3744 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3745 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3746 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3747 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3748 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3749 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3750 __le32 tx_lpi_timer_low; 3751 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3752 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3753 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3754 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3755 __le32 valid_tx_lpi_timer_high; 3756 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3757 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3758 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 3759 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 3760 __le16 supported_pam4_speeds_auto_mode; 3761 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 3762 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 3763 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 3764 __le16 supported_pam4_speeds_force_mode; 3765 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 3766 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 3767 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 3768 u8 unused_0[3]; 3769 u8 valid; 3770 }; 3771 3772 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3773 struct hwrm_port_phy_i2c_read_input { 3774 __le16 req_type; 3775 __le16 cmpl_ring; 3776 __le16 seq_id; 3777 __le16 target_id; 3778 __le64 resp_addr; 3779 __le32 flags; 3780 __le32 enables; 3781 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3782 __le16 port_id; 3783 u8 i2c_slave_addr; 3784 u8 unused_0; 3785 __le16 page_number; 3786 __le16 page_offset; 3787 u8 data_length; 3788 u8 unused_1[7]; 3789 }; 3790 3791 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3792 struct hwrm_port_phy_i2c_read_output { 3793 __le16 error_code; 3794 __le16 req_type; 3795 __le16 seq_id; 3796 __le16 resp_len; 3797 __le32 data[16]; 3798 u8 unused_0[7]; 3799 u8 valid; 3800 }; 3801 3802 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3803 struct hwrm_port_phy_mdio_write_input { 3804 __le16 req_type; 3805 __le16 cmpl_ring; 3806 __le16 seq_id; 3807 __le16 target_id; 3808 __le64 resp_addr; 3809 __le32 unused_0[2]; 3810 __le16 port_id; 3811 u8 phy_addr; 3812 u8 dev_addr; 3813 __le16 reg_addr; 3814 __le16 reg_data; 3815 u8 cl45_mdio; 3816 u8 unused_1[7]; 3817 }; 3818 3819 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3820 struct hwrm_port_phy_mdio_write_output { 3821 __le16 error_code; 3822 __le16 req_type; 3823 __le16 seq_id; 3824 __le16 resp_len; 3825 u8 unused_0[7]; 3826 u8 valid; 3827 }; 3828 3829 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3830 struct hwrm_port_phy_mdio_read_input { 3831 __le16 req_type; 3832 __le16 cmpl_ring; 3833 __le16 seq_id; 3834 __le16 target_id; 3835 __le64 resp_addr; 3836 __le32 unused_0[2]; 3837 __le16 port_id; 3838 u8 phy_addr; 3839 u8 dev_addr; 3840 __le16 reg_addr; 3841 u8 cl45_mdio; 3842 u8 unused_1; 3843 }; 3844 3845 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3846 struct hwrm_port_phy_mdio_read_output { 3847 __le16 error_code; 3848 __le16 req_type; 3849 __le16 seq_id; 3850 __le16 resp_len; 3851 __le16 reg_data; 3852 u8 unused_0[5]; 3853 u8 valid; 3854 }; 3855 3856 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3857 struct hwrm_port_led_cfg_input { 3858 __le16 req_type; 3859 __le16 cmpl_ring; 3860 __le16 seq_id; 3861 __le16 target_id; 3862 __le64 resp_addr; 3863 __le32 enables; 3864 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3865 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3866 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3867 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3868 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3869 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3870 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3871 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3872 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3873 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3874 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3875 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3876 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3877 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3878 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3879 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3880 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3881 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3882 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3883 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3884 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3885 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3886 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3887 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3888 __le16 port_id; 3889 u8 num_leds; 3890 u8 rsvd; 3891 u8 led0_id; 3892 u8 led0_state; 3893 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3894 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3895 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3896 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3897 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3898 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3899 u8 led0_color; 3900 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3901 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3902 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3903 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3904 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3905 u8 unused_0; 3906 __le16 led0_blink_on; 3907 __le16 led0_blink_off; 3908 u8 led0_group_id; 3909 u8 rsvd0; 3910 u8 led1_id; 3911 u8 led1_state; 3912 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3913 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3914 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3915 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3916 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3917 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3918 u8 led1_color; 3919 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3920 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3921 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3922 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3923 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3924 u8 unused_1; 3925 __le16 led1_blink_on; 3926 __le16 led1_blink_off; 3927 u8 led1_group_id; 3928 u8 rsvd1; 3929 u8 led2_id; 3930 u8 led2_state; 3931 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3932 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3933 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3934 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3935 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3936 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3937 u8 led2_color; 3938 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3939 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3940 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3941 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3942 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3943 u8 unused_2; 3944 __le16 led2_blink_on; 3945 __le16 led2_blink_off; 3946 u8 led2_group_id; 3947 u8 rsvd2; 3948 u8 led3_id; 3949 u8 led3_state; 3950 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3951 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3952 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3953 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3954 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3955 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3956 u8 led3_color; 3957 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3958 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3959 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3960 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3961 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3962 u8 unused_3; 3963 __le16 led3_blink_on; 3964 __le16 led3_blink_off; 3965 u8 led3_group_id; 3966 u8 rsvd3; 3967 }; 3968 3969 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3970 struct hwrm_port_led_cfg_output { 3971 __le16 error_code; 3972 __le16 req_type; 3973 __le16 seq_id; 3974 __le16 resp_len; 3975 u8 unused_0[7]; 3976 u8 valid; 3977 }; 3978 3979 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3980 struct hwrm_port_led_qcfg_input { 3981 __le16 req_type; 3982 __le16 cmpl_ring; 3983 __le16 seq_id; 3984 __le16 target_id; 3985 __le64 resp_addr; 3986 __le16 port_id; 3987 u8 unused_0[6]; 3988 }; 3989 3990 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3991 struct hwrm_port_led_qcfg_output { 3992 __le16 error_code; 3993 __le16 req_type; 3994 __le16 seq_id; 3995 __le16 resp_len; 3996 u8 num_leds; 3997 u8 led0_id; 3998 u8 led0_type; 3999 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 4000 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 4001 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 4002 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 4003 u8 led0_state; 4004 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 4005 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 4006 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 4007 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 4008 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 4009 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 4010 u8 led0_color; 4011 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 4012 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 4013 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 4014 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 4015 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 4016 u8 unused_0; 4017 __le16 led0_blink_on; 4018 __le16 led0_blink_off; 4019 u8 led0_group_id; 4020 u8 led1_id; 4021 u8 led1_type; 4022 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 4023 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 4024 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 4025 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 4026 u8 led1_state; 4027 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 4028 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 4029 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 4030 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 4031 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 4032 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 4033 u8 led1_color; 4034 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 4035 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 4036 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 4037 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 4038 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 4039 u8 unused_1; 4040 __le16 led1_blink_on; 4041 __le16 led1_blink_off; 4042 u8 led1_group_id; 4043 u8 led2_id; 4044 u8 led2_type; 4045 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 4046 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 4047 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 4048 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 4049 u8 led2_state; 4050 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 4051 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 4052 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 4053 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 4054 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 4055 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 4056 u8 led2_color; 4057 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 4058 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 4059 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 4060 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 4061 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 4062 u8 unused_2; 4063 __le16 led2_blink_on; 4064 __le16 led2_blink_off; 4065 u8 led2_group_id; 4066 u8 led3_id; 4067 u8 led3_type; 4068 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 4069 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 4070 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 4071 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 4072 u8 led3_state; 4073 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4074 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4075 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4076 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4077 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4078 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4079 u8 led3_color; 4080 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4081 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4082 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4083 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4084 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4085 u8 unused_3; 4086 __le16 led3_blink_on; 4087 __le16 led3_blink_off; 4088 u8 led3_group_id; 4089 u8 unused_4[6]; 4090 u8 valid; 4091 }; 4092 4093 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4094 struct hwrm_port_led_qcaps_input { 4095 __le16 req_type; 4096 __le16 cmpl_ring; 4097 __le16 seq_id; 4098 __le16 target_id; 4099 __le64 resp_addr; 4100 __le16 port_id; 4101 u8 unused_0[6]; 4102 }; 4103 4104 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4105 struct hwrm_port_led_qcaps_output { 4106 __le16 error_code; 4107 __le16 req_type; 4108 __le16 seq_id; 4109 __le16 resp_len; 4110 u8 num_leds; 4111 u8 unused[3]; 4112 u8 led0_id; 4113 u8 led0_type; 4114 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4115 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4116 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4117 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4118 u8 led0_group_id; 4119 u8 unused_0; 4120 __le16 led0_state_caps; 4121 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4122 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4123 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4124 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4125 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4126 __le16 led0_color_caps; 4127 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4128 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4129 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4130 u8 led1_id; 4131 u8 led1_type; 4132 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4133 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4134 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4135 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4136 u8 led1_group_id; 4137 u8 unused_1; 4138 __le16 led1_state_caps; 4139 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4140 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4141 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4142 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4143 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4144 __le16 led1_color_caps; 4145 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4146 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4147 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4148 u8 led2_id; 4149 u8 led2_type; 4150 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4151 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4152 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4153 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4154 u8 led2_group_id; 4155 u8 unused_2; 4156 __le16 led2_state_caps; 4157 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4158 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4159 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4160 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4161 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4162 __le16 led2_color_caps; 4163 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4164 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4165 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4166 u8 led3_id; 4167 u8 led3_type; 4168 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4169 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4170 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4171 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4172 u8 led3_group_id; 4173 u8 unused_3; 4174 __le16 led3_state_caps; 4175 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4176 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4177 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4178 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4179 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4180 __le16 led3_color_caps; 4181 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4182 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4183 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4184 u8 unused_4[3]; 4185 u8 valid; 4186 }; 4187 4188 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4189 struct hwrm_queue_qportcfg_input { 4190 __le16 req_type; 4191 __le16 cmpl_ring; 4192 __le16 seq_id; 4193 __le16 target_id; 4194 __le64 resp_addr; 4195 __le32 flags; 4196 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4197 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4198 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4199 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4200 __le16 port_id; 4201 u8 drv_qmap_cap; 4202 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4203 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4204 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4205 u8 unused_0; 4206 }; 4207 4208 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4209 struct hwrm_queue_qportcfg_output { 4210 __le16 error_code; 4211 __le16 req_type; 4212 __le16 seq_id; 4213 __le16 resp_len; 4214 u8 max_configurable_queues; 4215 u8 max_configurable_lossless_queues; 4216 u8 queue_cfg_allowed; 4217 u8 queue_cfg_info; 4218 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4219 u8 queue_pfcenable_cfg_allowed; 4220 u8 queue_pri2cos_cfg_allowed; 4221 u8 queue_cos2bw_cfg_allowed; 4222 u8 queue_id0; 4223 u8 queue_id0_service_profile; 4224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4226 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4227 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4228 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4229 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4230 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4231 u8 queue_id1; 4232 u8 queue_id1_service_profile; 4233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4236 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4240 u8 queue_id2; 4241 u8 queue_id2_service_profile; 4242 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4246 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4248 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4249 u8 queue_id3; 4250 u8 queue_id3_service_profile; 4251 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4252 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4253 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4254 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4255 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4256 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4257 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4258 u8 queue_id4; 4259 u8 queue_id4_service_profile; 4260 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4261 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4262 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4263 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4264 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4265 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4266 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4267 u8 queue_id5; 4268 u8 queue_id5_service_profile; 4269 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4270 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4271 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4272 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4273 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4274 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4275 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4276 u8 queue_id6; 4277 u8 queue_id6_service_profile; 4278 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4279 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4280 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4281 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4282 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4283 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4284 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4285 u8 queue_id7; 4286 u8 queue_id7_service_profile; 4287 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4288 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4289 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4290 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4291 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4292 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4293 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4294 u8 queue_id0_service_profile_type; 4295 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4296 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4297 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4298 char qid0_name[16]; 4299 char qid1_name[16]; 4300 char qid2_name[16]; 4301 char qid3_name[16]; 4302 char qid4_name[16]; 4303 char qid5_name[16]; 4304 char qid6_name[16]; 4305 char qid7_name[16]; 4306 u8 queue_id1_service_profile_type; 4307 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4308 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4309 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4310 u8 queue_id2_service_profile_type; 4311 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4313 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4314 u8 queue_id3_service_profile_type; 4315 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4316 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4317 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4318 u8 queue_id4_service_profile_type; 4319 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4320 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4321 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4322 u8 queue_id5_service_profile_type; 4323 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4324 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4325 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4326 u8 queue_id6_service_profile_type; 4327 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4328 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4329 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4330 u8 queue_id7_service_profile_type; 4331 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4332 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4333 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4334 u8 valid; 4335 }; 4336 4337 /* hwrm_queue_qcfg_input (size:192b/24B) */ 4338 struct hwrm_queue_qcfg_input { 4339 __le16 req_type; 4340 __le16 cmpl_ring; 4341 __le16 seq_id; 4342 __le16 target_id; 4343 __le64 resp_addr; 4344 __le32 flags; 4345 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4346 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4347 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4348 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4349 __le32 queue_id; 4350 }; 4351 4352 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4353 struct hwrm_queue_qcfg_output { 4354 __le16 error_code; 4355 __le16 req_type; 4356 __le16 seq_id; 4357 __le16 resp_len; 4358 __le32 queue_len; 4359 u8 service_profile; 4360 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4361 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4362 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4363 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4364 u8 queue_cfg_info; 4365 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4366 u8 unused_0; 4367 u8 valid; 4368 }; 4369 4370 /* hwrm_queue_cfg_input (size:320b/40B) */ 4371 struct hwrm_queue_cfg_input { 4372 __le16 req_type; 4373 __le16 cmpl_ring; 4374 __le16 seq_id; 4375 __le16 target_id; 4376 __le64 resp_addr; 4377 __le32 flags; 4378 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4379 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4380 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4381 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4382 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4383 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4384 __le32 enables; 4385 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4386 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4387 __le32 queue_id; 4388 __le32 dflt_len; 4389 u8 service_profile; 4390 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4391 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4392 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4393 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4394 u8 unused_0[7]; 4395 }; 4396 4397 /* hwrm_queue_cfg_output (size:128b/16B) */ 4398 struct hwrm_queue_cfg_output { 4399 __le16 error_code; 4400 __le16 req_type; 4401 __le16 seq_id; 4402 __le16 resp_len; 4403 u8 unused_0[7]; 4404 u8 valid; 4405 }; 4406 4407 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 4408 struct hwrm_queue_pfcenable_qcfg_input { 4409 __le16 req_type; 4410 __le16 cmpl_ring; 4411 __le16 seq_id; 4412 __le16 target_id; 4413 __le64 resp_addr; 4414 __le16 port_id; 4415 u8 unused_0[6]; 4416 }; 4417 4418 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 4419 struct hwrm_queue_pfcenable_qcfg_output { 4420 __le16 error_code; 4421 __le16 req_type; 4422 __le16 seq_id; 4423 __le16 resp_len; 4424 __le32 flags; 4425 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 4426 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 4427 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 4428 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 4429 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 4430 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 4431 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 4432 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 4433 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4434 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4435 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4436 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4437 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4438 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4439 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4440 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4441 u8 unused_0[3]; 4442 u8 valid; 4443 }; 4444 4445 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 4446 struct hwrm_queue_pfcenable_cfg_input { 4447 __le16 req_type; 4448 __le16 cmpl_ring; 4449 __le16 seq_id; 4450 __le16 target_id; 4451 __le64 resp_addr; 4452 __le32 flags; 4453 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 4454 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 4455 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 4456 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 4457 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 4458 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 4459 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 4460 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 4461 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4462 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4463 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4464 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4465 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4466 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4467 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4468 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4469 __le16 port_id; 4470 u8 unused_0[2]; 4471 }; 4472 4473 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4474 struct hwrm_queue_pfcenable_cfg_output { 4475 __le16 error_code; 4476 __le16 req_type; 4477 __le16 seq_id; 4478 __le16 resp_len; 4479 u8 unused_0[7]; 4480 u8 valid; 4481 }; 4482 4483 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 4484 struct hwrm_queue_pri2cos_qcfg_input { 4485 __le16 req_type; 4486 __le16 cmpl_ring; 4487 __le16 seq_id; 4488 __le16 target_id; 4489 __le64 resp_addr; 4490 __le32 flags; 4491 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4492 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4493 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4494 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 4495 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 4496 u8 port_id; 4497 u8 unused_0[3]; 4498 }; 4499 4500 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 4501 struct hwrm_queue_pri2cos_qcfg_output { 4502 __le16 error_code; 4503 __le16 req_type; 4504 __le16 seq_id; 4505 __le16 resp_len; 4506 u8 pri0_cos_queue_id; 4507 u8 pri1_cos_queue_id; 4508 u8 pri2_cos_queue_id; 4509 u8 pri3_cos_queue_id; 4510 u8 pri4_cos_queue_id; 4511 u8 pri5_cos_queue_id; 4512 u8 pri6_cos_queue_id; 4513 u8 pri7_cos_queue_id; 4514 u8 queue_cfg_info; 4515 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4516 u8 unused_0[6]; 4517 u8 valid; 4518 }; 4519 4520 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4521 struct hwrm_queue_pri2cos_cfg_input { 4522 __le16 req_type; 4523 __le16 cmpl_ring; 4524 __le16 seq_id; 4525 __le16 target_id; 4526 __le64 resp_addr; 4527 __le32 flags; 4528 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4529 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4530 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4531 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4532 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4533 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4534 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4535 __le32 enables; 4536 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4537 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4538 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4539 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4540 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4541 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4542 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4543 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4544 u8 port_id; 4545 u8 pri0_cos_queue_id; 4546 u8 pri1_cos_queue_id; 4547 u8 pri2_cos_queue_id; 4548 u8 pri3_cos_queue_id; 4549 u8 pri4_cos_queue_id; 4550 u8 pri5_cos_queue_id; 4551 u8 pri6_cos_queue_id; 4552 u8 pri7_cos_queue_id; 4553 u8 unused_0[7]; 4554 }; 4555 4556 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4557 struct hwrm_queue_pri2cos_cfg_output { 4558 __le16 error_code; 4559 __le16 req_type; 4560 __le16 seq_id; 4561 __le16 resp_len; 4562 u8 unused_0[7]; 4563 u8 valid; 4564 }; 4565 4566 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 4567 struct hwrm_queue_cos2bw_qcfg_input { 4568 __le16 req_type; 4569 __le16 cmpl_ring; 4570 __le16 seq_id; 4571 __le16 target_id; 4572 __le64 resp_addr; 4573 __le16 port_id; 4574 u8 unused_0[6]; 4575 }; 4576 4577 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 4578 struct hwrm_queue_cos2bw_qcfg_output { 4579 __le16 error_code; 4580 __le16 req_type; 4581 __le16 seq_id; 4582 __le16 resp_len; 4583 u8 queue_id0; 4584 u8 unused_0; 4585 __le16 unused_1; 4586 __le32 queue_id0_min_bw; 4587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4589 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 4593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4602 __le32 queue_id0_max_bw; 4603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 4609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4618 u8 queue_id0_tsa_assign; 4619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4623 u8 queue_id0_pri_lvl; 4624 u8 queue_id0_bw_weight; 4625 u8 queue_id1; 4626 __le32 queue_id1_min_bw; 4627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 4633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4642 __le32 queue_id1_max_bw; 4643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 4649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4658 u8 queue_id1_tsa_assign; 4659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4663 u8 queue_id1_pri_lvl; 4664 u8 queue_id1_bw_weight; 4665 u8 queue_id2; 4666 __le32 queue_id2_min_bw; 4667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4682 __le32 queue_id2_max_bw; 4683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4698 u8 queue_id2_tsa_assign; 4699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4703 u8 queue_id2_pri_lvl; 4704 u8 queue_id2_bw_weight; 4705 u8 queue_id3; 4706 __le32 queue_id3_min_bw; 4707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4709 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4722 __le32 queue_id3_max_bw; 4723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4738 u8 queue_id3_tsa_assign; 4739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4743 u8 queue_id3_pri_lvl; 4744 u8 queue_id3_bw_weight; 4745 u8 queue_id4; 4746 __le32 queue_id4_min_bw; 4747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4749 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4762 __le32 queue_id4_max_bw; 4763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4778 u8 queue_id4_tsa_assign; 4779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4783 u8 queue_id4_pri_lvl; 4784 u8 queue_id4_bw_weight; 4785 u8 queue_id5; 4786 __le32 queue_id5_min_bw; 4787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4789 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4802 __le32 queue_id5_max_bw; 4803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4805 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4810 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4811 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4812 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4813 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4818 u8 queue_id5_tsa_assign; 4819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4823 u8 queue_id5_pri_lvl; 4824 u8 queue_id5_bw_weight; 4825 u8 queue_id6; 4826 __le32 queue_id6_min_bw; 4827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4829 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4842 __le32 queue_id6_max_bw; 4843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4858 u8 queue_id6_tsa_assign; 4859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4863 u8 queue_id6_pri_lvl; 4864 u8 queue_id6_bw_weight; 4865 u8 queue_id7; 4866 __le32 queue_id7_min_bw; 4867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4882 __le32 queue_id7_max_bw; 4883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4894 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4895 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4898 u8 queue_id7_tsa_assign; 4899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4903 u8 queue_id7_pri_lvl; 4904 u8 queue_id7_bw_weight; 4905 u8 unused_2[4]; 4906 u8 valid; 4907 }; 4908 4909 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4910 struct hwrm_queue_cos2bw_cfg_input { 4911 __le16 req_type; 4912 __le16 cmpl_ring; 4913 __le16 seq_id; 4914 __le16 target_id; 4915 __le64 resp_addr; 4916 __le32 flags; 4917 __le32 enables; 4918 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4919 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4920 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4921 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4922 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4923 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4924 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4925 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4926 __le16 port_id; 4927 u8 queue_id0; 4928 u8 unused_0; 4929 __le32 queue_id0_min_bw; 4930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4945 __le32 queue_id0_max_bw; 4946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4961 u8 queue_id0_tsa_assign; 4962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4966 u8 queue_id0_pri_lvl; 4967 u8 queue_id0_bw_weight; 4968 u8 queue_id1; 4969 __le32 queue_id1_min_bw; 4970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4985 __le32 queue_id1_max_bw; 4986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5001 u8 queue_id1_tsa_assign; 5002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5006 u8 queue_id1_pri_lvl; 5007 u8 queue_id1_bw_weight; 5008 u8 queue_id2; 5009 __le32 queue_id2_min_bw; 5010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 5016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5025 __le32 queue_id2_max_bw; 5026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 5032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5041 u8 queue_id2_tsa_assign; 5042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5046 u8 queue_id2_pri_lvl; 5047 u8 queue_id2_bw_weight; 5048 u8 queue_id3; 5049 __le32 queue_id3_min_bw; 5050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 5056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5065 __le32 queue_id3_max_bw; 5066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 5072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5081 u8 queue_id3_tsa_assign; 5082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5086 u8 queue_id3_pri_lvl; 5087 u8 queue_id3_bw_weight; 5088 u8 queue_id4; 5089 __le32 queue_id4_min_bw; 5090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5105 __le32 queue_id4_max_bw; 5106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5121 u8 queue_id4_tsa_assign; 5122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5126 u8 queue_id4_pri_lvl; 5127 u8 queue_id4_bw_weight; 5128 u8 queue_id5; 5129 __le32 queue_id5_min_bw; 5130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5145 __le32 queue_id5_max_bw; 5146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5152 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5157 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5158 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5159 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5160 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5161 u8 queue_id5_tsa_assign; 5162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5166 u8 queue_id5_pri_lvl; 5167 u8 queue_id5_bw_weight; 5168 u8 queue_id6; 5169 __le32 queue_id6_min_bw; 5170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5176 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5185 __le32 queue_id6_max_bw; 5186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5197 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5198 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5201 u8 queue_id6_tsa_assign; 5202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5206 u8 queue_id6_pri_lvl; 5207 u8 queue_id6_bw_weight; 5208 u8 queue_id7; 5209 __le32 queue_id7_min_bw; 5210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5225 __le32 queue_id7_max_bw; 5226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5237 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5238 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5241 u8 queue_id7_tsa_assign; 5242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5246 u8 queue_id7_pri_lvl; 5247 u8 queue_id7_bw_weight; 5248 u8 unused_1[5]; 5249 }; 5250 5251 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5252 struct hwrm_queue_cos2bw_cfg_output { 5253 __le16 error_code; 5254 __le16 req_type; 5255 __le16 seq_id; 5256 __le16 resp_len; 5257 u8 unused_0[7]; 5258 u8 valid; 5259 }; 5260 5261 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5262 struct hwrm_queue_dscp_qcaps_input { 5263 __le16 req_type; 5264 __le16 cmpl_ring; 5265 __le16 seq_id; 5266 __le16 target_id; 5267 __le64 resp_addr; 5268 u8 port_id; 5269 u8 unused_0[7]; 5270 }; 5271 5272 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5273 struct hwrm_queue_dscp_qcaps_output { 5274 __le16 error_code; 5275 __le16 req_type; 5276 __le16 seq_id; 5277 __le16 resp_len; 5278 u8 num_dscp_bits; 5279 u8 unused_0; 5280 __le16 max_entries; 5281 u8 unused_1[3]; 5282 u8 valid; 5283 }; 5284 5285 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5286 struct hwrm_queue_dscp2pri_qcfg_input { 5287 __le16 req_type; 5288 __le16 cmpl_ring; 5289 __le16 seq_id; 5290 __le16 target_id; 5291 __le64 resp_addr; 5292 __le64 dest_data_addr; 5293 u8 port_id; 5294 u8 unused_0; 5295 __le16 dest_data_buffer_size; 5296 u8 unused_1[4]; 5297 }; 5298 5299 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5300 struct hwrm_queue_dscp2pri_qcfg_output { 5301 __le16 error_code; 5302 __le16 req_type; 5303 __le16 seq_id; 5304 __le16 resp_len; 5305 __le16 entry_cnt; 5306 u8 default_pri; 5307 u8 unused_0[4]; 5308 u8 valid; 5309 }; 5310 5311 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5312 struct hwrm_queue_dscp2pri_cfg_input { 5313 __le16 req_type; 5314 __le16 cmpl_ring; 5315 __le16 seq_id; 5316 __le16 target_id; 5317 __le64 resp_addr; 5318 __le64 src_data_addr; 5319 __le32 flags; 5320 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5321 __le32 enables; 5322 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5323 u8 port_id; 5324 u8 default_pri; 5325 __le16 entry_cnt; 5326 u8 unused_0[4]; 5327 }; 5328 5329 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5330 struct hwrm_queue_dscp2pri_cfg_output { 5331 __le16 error_code; 5332 __le16 req_type; 5333 __le16 seq_id; 5334 __le16 resp_len; 5335 u8 unused_0[7]; 5336 u8 valid; 5337 }; 5338 5339 /* hwrm_vnic_alloc_input (size:192b/24B) */ 5340 struct hwrm_vnic_alloc_input { 5341 __le16 req_type; 5342 __le16 cmpl_ring; 5343 __le16 seq_id; 5344 __le16 target_id; 5345 __le64 resp_addr; 5346 __le32 flags; 5347 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5348 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5349 __le16 virtio_net_fid; 5350 u8 unused_0[2]; 5351 }; 5352 5353 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5354 struct hwrm_vnic_alloc_output { 5355 __le16 error_code; 5356 __le16 req_type; 5357 __le16 seq_id; 5358 __le16 resp_len; 5359 __le32 vnic_id; 5360 u8 unused_0[3]; 5361 u8 valid; 5362 }; 5363 5364 /* hwrm_vnic_free_input (size:192b/24B) */ 5365 struct hwrm_vnic_free_input { 5366 __le16 req_type; 5367 __le16 cmpl_ring; 5368 __le16 seq_id; 5369 __le16 target_id; 5370 __le64 resp_addr; 5371 __le32 vnic_id; 5372 u8 unused_0[4]; 5373 }; 5374 5375 /* hwrm_vnic_free_output (size:128b/16B) */ 5376 struct hwrm_vnic_free_output { 5377 __le16 error_code; 5378 __le16 req_type; 5379 __le16 seq_id; 5380 __le16 resp_len; 5381 u8 unused_0[7]; 5382 u8 valid; 5383 }; 5384 5385 /* hwrm_vnic_cfg_input (size:384b/48B) */ 5386 struct hwrm_vnic_cfg_input { 5387 __le16 req_type; 5388 __le16 cmpl_ring; 5389 __le16 seq_id; 5390 __le16 target_id; 5391 __le64 resp_addr; 5392 __le32 flags; 5393 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5394 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5395 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 5396 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 5397 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5398 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 5399 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5400 __le32 enables; 5401 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5402 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5403 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5404 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5405 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 5406 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 5407 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 5408 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5409 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5410 __le16 vnic_id; 5411 __le16 dflt_ring_grp; 5412 __le16 rss_rule; 5413 __le16 cos_rule; 5414 __le16 lb_rule; 5415 __le16 mru; 5416 __le16 default_rx_ring_id; 5417 __le16 default_cmpl_ring_id; 5418 __le16 queue_id; 5419 u8 rx_csum_v2_mode; 5420 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 5421 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 5422 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 5423 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 5424 u8 unused0[5]; 5425 }; 5426 5427 /* hwrm_vnic_cfg_output (size:128b/16B) */ 5428 struct hwrm_vnic_cfg_output { 5429 __le16 error_code; 5430 __le16 req_type; 5431 __le16 seq_id; 5432 __le16 resp_len; 5433 u8 unused_0[7]; 5434 u8 valid; 5435 }; 5436 5437 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 5438 struct hwrm_vnic_qcaps_input { 5439 __le16 req_type; 5440 __le16 cmpl_ring; 5441 __le16 seq_id; 5442 __le16 target_id; 5443 __le64 resp_addr; 5444 __le32 enables; 5445 u8 unused_0[4]; 5446 }; 5447 5448 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 5449 struct hwrm_vnic_qcaps_output { 5450 __le16 error_code; 5451 __le16 req_type; 5452 __le16 seq_id; 5453 __le16 resp_len; 5454 __le16 mru; 5455 u8 unused_0[2]; 5456 __le32 flags; 5457 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 5458 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 5459 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 5460 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 5461 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 5462 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 5463 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 5464 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 5465 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5466 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5467 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 5468 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 5469 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 5470 __le16 max_aggs_supported; 5471 u8 unused_1[5]; 5472 u8 valid; 5473 }; 5474 5475 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 5476 struct hwrm_vnic_tpa_cfg_input { 5477 __le16 req_type; 5478 __le16 cmpl_ring; 5479 __le16 seq_id; 5480 __le16 target_id; 5481 __le64 resp_addr; 5482 __le32 flags; 5483 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5484 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5485 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5486 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5487 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5488 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5489 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5490 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 5491 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5492 __le32 enables; 5493 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5494 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5495 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5496 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5497 __le16 vnic_id; 5498 __le16 max_agg_segs; 5499 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5500 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5501 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5502 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5503 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5504 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5505 __le16 max_aggs; 5506 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5507 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5508 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5509 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5510 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5511 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5512 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5513 u8 unused_0[2]; 5514 __le32 max_agg_timer; 5515 __le32 min_agg_len; 5516 }; 5517 5518 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5519 struct hwrm_vnic_tpa_cfg_output { 5520 __le16 error_code; 5521 __le16 req_type; 5522 __le16 seq_id; 5523 __le16 resp_len; 5524 u8 unused_0[7]; 5525 u8 valid; 5526 }; 5527 5528 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5529 struct hwrm_vnic_tpa_qcfg_input { 5530 __le16 req_type; 5531 __le16 cmpl_ring; 5532 __le16 seq_id; 5533 __le16 target_id; 5534 __le64 resp_addr; 5535 __le16 vnic_id; 5536 u8 unused_0[6]; 5537 }; 5538 5539 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5540 struct hwrm_vnic_tpa_qcfg_output { 5541 __le16 error_code; 5542 __le16 req_type; 5543 __le16 seq_id; 5544 __le16 resp_len; 5545 __le32 flags; 5546 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5547 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5548 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5549 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5550 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5551 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5552 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5553 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5554 __le16 max_agg_segs; 5555 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5556 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5557 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5558 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5559 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5560 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5561 __le16 max_aggs; 5562 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5563 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5564 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5565 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5566 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5567 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5568 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5569 __le32 max_agg_timer; 5570 __le32 min_agg_len; 5571 u8 unused_0[7]; 5572 u8 valid; 5573 }; 5574 5575 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5576 struct hwrm_vnic_rss_cfg_input { 5577 __le16 req_type; 5578 __le16 cmpl_ring; 5579 __le16 seq_id; 5580 __le16 target_id; 5581 __le64 resp_addr; 5582 __le32 hash_type; 5583 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5584 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5585 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5586 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5587 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5588 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 5589 __le16 vnic_id; 5590 u8 ring_table_pair_index; 5591 u8 hash_mode_flags; 5592 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 5593 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 5594 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 5595 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 5596 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5597 __le64 ring_grp_tbl_addr; 5598 __le64 hash_key_tbl_addr; 5599 __le16 rss_ctx_idx; 5600 u8 unused_1[6]; 5601 }; 5602 5603 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5604 struct hwrm_vnic_rss_cfg_output { 5605 __le16 error_code; 5606 __le16 req_type; 5607 __le16 seq_id; 5608 __le16 resp_len; 5609 u8 unused_0[7]; 5610 u8 valid; 5611 }; 5612 5613 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 5614 struct hwrm_vnic_rss_cfg_cmd_err { 5615 u8 code; 5616 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 5617 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 5618 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 5619 u8 unused_0[7]; 5620 }; 5621 5622 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5623 struct hwrm_vnic_plcmodes_cfg_input { 5624 __le16 req_type; 5625 __le16 cmpl_ring; 5626 __le16 seq_id; 5627 __le16 target_id; 5628 __le64 resp_addr; 5629 __le32 flags; 5630 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5631 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5632 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5633 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5634 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5635 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5636 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 5637 __le32 enables; 5638 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5639 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5640 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5641 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 5642 __le32 vnic_id; 5643 __le16 jumbo_thresh; 5644 __le16 hds_offset; 5645 __le16 hds_threshold; 5646 __le16 max_bds; 5647 u8 unused_0[4]; 5648 }; 5649 5650 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5651 struct hwrm_vnic_plcmodes_cfg_output { 5652 __le16 error_code; 5653 __le16 req_type; 5654 __le16 seq_id; 5655 __le16 resp_len; 5656 u8 unused_0[7]; 5657 u8 valid; 5658 }; 5659 5660 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5661 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5662 __le16 req_type; 5663 __le16 cmpl_ring; 5664 __le16 seq_id; 5665 __le16 target_id; 5666 __le64 resp_addr; 5667 }; 5668 5669 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5670 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5671 __le16 error_code; 5672 __le16 req_type; 5673 __le16 seq_id; 5674 __le16 resp_len; 5675 __le16 rss_cos_lb_ctx_id; 5676 u8 unused_0[5]; 5677 u8 valid; 5678 }; 5679 5680 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5681 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5682 __le16 req_type; 5683 __le16 cmpl_ring; 5684 __le16 seq_id; 5685 __le16 target_id; 5686 __le64 resp_addr; 5687 __le16 rss_cos_lb_ctx_id; 5688 u8 unused_0[6]; 5689 }; 5690 5691 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5692 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5693 __le16 error_code; 5694 __le16 req_type; 5695 __le16 seq_id; 5696 __le16 resp_len; 5697 u8 unused_0[7]; 5698 u8 valid; 5699 }; 5700 5701 /* hwrm_ring_alloc_input (size:704b/88B) */ 5702 struct hwrm_ring_alloc_input { 5703 __le16 req_type; 5704 __le16 cmpl_ring; 5705 __le16 seq_id; 5706 __le16 target_id; 5707 __le64 resp_addr; 5708 __le32 enables; 5709 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5710 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5711 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5712 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5713 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5714 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5715 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 5716 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 5717 u8 ring_type; 5718 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5719 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5720 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5721 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5722 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5723 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5724 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5725 u8 unused_0; 5726 __le16 flags; 5727 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5728 __le64 page_tbl_addr; 5729 __le32 fbo; 5730 u8 page_size; 5731 u8 page_tbl_depth; 5732 __le16 schq_id; 5733 __le32 length; 5734 __le16 logical_id; 5735 __le16 cmpl_ring_id; 5736 __le16 queue_id; 5737 __le16 rx_buf_size; 5738 __le16 rx_ring_id; 5739 __le16 nq_ring_id; 5740 __le16 ring_arb_cfg; 5741 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5742 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5743 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5744 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5745 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5746 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5747 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5748 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5749 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5750 __le16 unused_3; 5751 __le32 reserved3; 5752 __le32 stat_ctx_id; 5753 __le32 reserved4; 5754 __le32 max_bw; 5755 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5756 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5757 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5758 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5759 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5760 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5761 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5762 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5763 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5764 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5765 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5766 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5767 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5768 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5769 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5770 u8 int_mode; 5771 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5772 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5773 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5774 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5775 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5776 u8 mpc_chnls_type; 5777 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 5778 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 5779 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 5780 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 5781 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 5782 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 5783 u8 unused_4[2]; 5784 __le64 cq_handle; 5785 }; 5786 5787 /* hwrm_ring_alloc_output (size:128b/16B) */ 5788 struct hwrm_ring_alloc_output { 5789 __le16 error_code; 5790 __le16 req_type; 5791 __le16 seq_id; 5792 __le16 resp_len; 5793 __le16 ring_id; 5794 __le16 logical_ring_id; 5795 u8 push_buffer_index; 5796 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5797 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5798 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5799 u8 unused_0[2]; 5800 u8 valid; 5801 }; 5802 5803 /* hwrm_ring_free_input (size:256b/32B) */ 5804 struct hwrm_ring_free_input { 5805 __le16 req_type; 5806 __le16 cmpl_ring; 5807 __le16 seq_id; 5808 __le16 target_id; 5809 __le64 resp_addr; 5810 u8 ring_type; 5811 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5812 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5813 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5814 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5815 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5816 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5817 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5818 u8 flags; 5819 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 5820 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 5821 __le16 ring_id; 5822 __le32 prod_idx; 5823 __le32 opaque; 5824 __le32 unused_1; 5825 }; 5826 5827 /* hwrm_ring_free_output (size:128b/16B) */ 5828 struct hwrm_ring_free_output { 5829 __le16 error_code; 5830 __le16 req_type; 5831 __le16 seq_id; 5832 __le16 resp_len; 5833 u8 unused_0[7]; 5834 u8 valid; 5835 }; 5836 5837 /* hwrm_ring_reset_input (size:192b/24B) */ 5838 struct hwrm_ring_reset_input { 5839 __le16 req_type; 5840 __le16 cmpl_ring; 5841 __le16 seq_id; 5842 __le16 target_id; 5843 __le64 resp_addr; 5844 u8 ring_type; 5845 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5846 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5847 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5848 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5849 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 5850 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 5851 u8 unused_0; 5852 __le16 ring_id; 5853 u8 unused_1[4]; 5854 }; 5855 5856 /* hwrm_ring_reset_output (size:128b/16B) */ 5857 struct hwrm_ring_reset_output { 5858 __le16 error_code; 5859 __le16 req_type; 5860 __le16 seq_id; 5861 __le16 resp_len; 5862 u8 push_buffer_index; 5863 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5864 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5865 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5866 u8 unused_0[3]; 5867 u8 consumer_idx[3]; 5868 u8 valid; 5869 }; 5870 5871 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5872 struct hwrm_ring_aggint_qcaps_input { 5873 __le16 req_type; 5874 __le16 cmpl_ring; 5875 __le16 seq_id; 5876 __le16 target_id; 5877 __le64 resp_addr; 5878 }; 5879 5880 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5881 struct hwrm_ring_aggint_qcaps_output { 5882 __le16 error_code; 5883 __le16 req_type; 5884 __le16 seq_id; 5885 __le16 resp_len; 5886 __le32 cmpl_params; 5887 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5888 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5889 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5890 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5891 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5892 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5893 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5894 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5895 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5896 __le32 nq_params; 5897 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5898 __le16 num_cmpl_dma_aggr_min; 5899 __le16 num_cmpl_dma_aggr_max; 5900 __le16 num_cmpl_dma_aggr_during_int_min; 5901 __le16 num_cmpl_dma_aggr_during_int_max; 5902 __le16 cmpl_aggr_dma_tmr_min; 5903 __le16 cmpl_aggr_dma_tmr_max; 5904 __le16 cmpl_aggr_dma_tmr_during_int_min; 5905 __le16 cmpl_aggr_dma_tmr_during_int_max; 5906 __le16 int_lat_tmr_min_min; 5907 __le16 int_lat_tmr_min_max; 5908 __le16 int_lat_tmr_max_min; 5909 __le16 int_lat_tmr_max_max; 5910 __le16 num_cmpl_aggr_int_min; 5911 __le16 num_cmpl_aggr_int_max; 5912 __le16 timer_units; 5913 u8 unused_0[1]; 5914 u8 valid; 5915 }; 5916 5917 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5918 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5919 __le16 req_type; 5920 __le16 cmpl_ring; 5921 __le16 seq_id; 5922 __le16 target_id; 5923 __le64 resp_addr; 5924 __le16 ring_id; 5925 __le16 flags; 5926 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5927 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5928 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5929 u8 unused_0[4]; 5930 }; 5931 5932 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5933 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5934 __le16 error_code; 5935 __le16 req_type; 5936 __le16 seq_id; 5937 __le16 resp_len; 5938 __le16 flags; 5939 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5940 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5941 __le16 num_cmpl_dma_aggr; 5942 __le16 num_cmpl_dma_aggr_during_int; 5943 __le16 cmpl_aggr_dma_tmr; 5944 __le16 cmpl_aggr_dma_tmr_during_int; 5945 __le16 int_lat_tmr_min; 5946 __le16 int_lat_tmr_max; 5947 __le16 num_cmpl_aggr_int; 5948 u8 unused_0[7]; 5949 u8 valid; 5950 }; 5951 5952 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5953 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5954 __le16 req_type; 5955 __le16 cmpl_ring; 5956 __le16 seq_id; 5957 __le16 target_id; 5958 __le64 resp_addr; 5959 __le16 ring_id; 5960 __le16 flags; 5961 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5962 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5963 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5964 __le16 num_cmpl_dma_aggr; 5965 __le16 num_cmpl_dma_aggr_during_int; 5966 __le16 cmpl_aggr_dma_tmr; 5967 __le16 cmpl_aggr_dma_tmr_during_int; 5968 __le16 int_lat_tmr_min; 5969 __le16 int_lat_tmr_max; 5970 __le16 num_cmpl_aggr_int; 5971 __le16 enables; 5972 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5973 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5974 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5975 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5976 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5977 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5978 u8 unused_0[4]; 5979 }; 5980 5981 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5982 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5983 __le16 error_code; 5984 __le16 req_type; 5985 __le16 seq_id; 5986 __le16 resp_len; 5987 u8 unused_0[7]; 5988 u8 valid; 5989 }; 5990 5991 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5992 struct hwrm_ring_grp_alloc_input { 5993 __le16 req_type; 5994 __le16 cmpl_ring; 5995 __le16 seq_id; 5996 __le16 target_id; 5997 __le64 resp_addr; 5998 __le16 cr; 5999 __le16 rr; 6000 __le16 ar; 6001 __le16 sc; 6002 }; 6003 6004 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 6005 struct hwrm_ring_grp_alloc_output { 6006 __le16 error_code; 6007 __le16 req_type; 6008 __le16 seq_id; 6009 __le16 resp_len; 6010 __le32 ring_group_id; 6011 u8 unused_0[3]; 6012 u8 valid; 6013 }; 6014 6015 /* hwrm_ring_grp_free_input (size:192b/24B) */ 6016 struct hwrm_ring_grp_free_input { 6017 __le16 req_type; 6018 __le16 cmpl_ring; 6019 __le16 seq_id; 6020 __le16 target_id; 6021 __le64 resp_addr; 6022 __le32 ring_group_id; 6023 u8 unused_0[4]; 6024 }; 6025 6026 /* hwrm_ring_grp_free_output (size:128b/16B) */ 6027 struct hwrm_ring_grp_free_output { 6028 __le16 error_code; 6029 __le16 req_type; 6030 __le16 seq_id; 6031 __le16 resp_len; 6032 u8 unused_0[7]; 6033 u8 valid; 6034 }; 6035 6036 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 6037 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 6038 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 6039 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 6040 6041 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 6042 struct hwrm_cfa_l2_filter_alloc_input { 6043 __le16 req_type; 6044 __le16 cmpl_ring; 6045 __le16 seq_id; 6046 __le16 target_id; 6047 __le64 resp_addr; 6048 __le32 flags; 6049 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 6050 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 6051 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 6052 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 6053 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 6054 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 6055 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 6056 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 6057 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 6058 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 6059 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 6060 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 6061 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 6062 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 6063 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 6064 __le32 enables; 6065 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 6066 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 6067 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 6068 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 6069 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 6070 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 6071 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 6072 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 6073 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 6074 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 6075 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 6076 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 6077 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 6078 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6079 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6080 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6081 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6082 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 6083 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6084 u8 l2_addr[6]; 6085 u8 num_vlans; 6086 u8 t_num_vlans; 6087 u8 l2_addr_mask[6]; 6088 __le16 l2_ovlan; 6089 __le16 l2_ovlan_mask; 6090 __le16 l2_ivlan; 6091 __le16 l2_ivlan_mask; 6092 u8 unused_1[2]; 6093 u8 t_l2_addr[6]; 6094 u8 unused_2[2]; 6095 u8 t_l2_addr_mask[6]; 6096 __le16 t_l2_ovlan; 6097 __le16 t_l2_ovlan_mask; 6098 __le16 t_l2_ivlan; 6099 __le16 t_l2_ivlan_mask; 6100 u8 src_type; 6101 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6102 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6103 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6104 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6105 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6106 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6107 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6108 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6109 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6110 u8 unused_3; 6111 __le32 src_id; 6112 u8 tunnel_type; 6113 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6114 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6115 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6116 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6117 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6118 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6119 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6120 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6121 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6122 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6123 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6124 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6125 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6126 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6127 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6128 u8 unused_4; 6129 __le16 dst_id; 6130 __le16 mirror_vnic_id; 6131 u8 pri_hint; 6132 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6133 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6134 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6135 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6136 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6137 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6138 u8 unused_5; 6139 __le32 unused_6; 6140 __le64 l2_filter_id_hint; 6141 }; 6142 6143 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6144 struct hwrm_cfa_l2_filter_alloc_output { 6145 __le16 error_code; 6146 __le16 req_type; 6147 __le16 seq_id; 6148 __le16 resp_len; 6149 __le64 l2_filter_id; 6150 __le32 flow_id; 6151 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6152 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6153 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6154 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6155 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6156 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6157 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6158 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6159 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6160 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6161 u8 unused_0[3]; 6162 u8 valid; 6163 }; 6164 6165 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6166 struct hwrm_cfa_l2_filter_free_input { 6167 __le16 req_type; 6168 __le16 cmpl_ring; 6169 __le16 seq_id; 6170 __le16 target_id; 6171 __le64 resp_addr; 6172 __le64 l2_filter_id; 6173 }; 6174 6175 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6176 struct hwrm_cfa_l2_filter_free_output { 6177 __le16 error_code; 6178 __le16 req_type; 6179 __le16 seq_id; 6180 __le16 resp_len; 6181 u8 unused_0[7]; 6182 u8 valid; 6183 }; 6184 6185 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6186 struct hwrm_cfa_l2_filter_cfg_input { 6187 __le16 req_type; 6188 __le16 cmpl_ring; 6189 __le16 seq_id; 6190 __le16 target_id; 6191 __le64 resp_addr; 6192 __le32 flags; 6193 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6194 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6195 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 6196 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6197 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 6198 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 6199 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 6200 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 6201 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 6202 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 6203 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6204 __le32 enables; 6205 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6206 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6207 __le64 l2_filter_id; 6208 __le32 dst_id; 6209 __le32 new_mirror_vnic_id; 6210 }; 6211 6212 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6213 struct hwrm_cfa_l2_filter_cfg_output { 6214 __le16 error_code; 6215 __le16 req_type; 6216 __le16 seq_id; 6217 __le16 resp_len; 6218 u8 unused_0[7]; 6219 u8 valid; 6220 }; 6221 6222 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6223 struct hwrm_cfa_l2_set_rx_mask_input { 6224 __le16 req_type; 6225 __le16 cmpl_ring; 6226 __le16 seq_id; 6227 __le16 target_id; 6228 __le64 resp_addr; 6229 __le32 vnic_id; 6230 __le32 mask; 6231 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6232 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6233 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6234 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6235 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6236 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6237 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6238 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6239 __le64 mc_tbl_addr; 6240 __le32 num_mc_entries; 6241 u8 unused_0[4]; 6242 __le64 vlan_tag_tbl_addr; 6243 __le32 num_vlan_tags; 6244 u8 unused_1[4]; 6245 }; 6246 6247 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6248 struct hwrm_cfa_l2_set_rx_mask_output { 6249 __le16 error_code; 6250 __le16 req_type; 6251 __le16 seq_id; 6252 __le16 resp_len; 6253 u8 unused_0[7]; 6254 u8 valid; 6255 }; 6256 6257 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6258 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6259 u8 code; 6260 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6261 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6262 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6263 u8 unused_0[7]; 6264 }; 6265 6266 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6267 struct hwrm_cfa_tunnel_filter_alloc_input { 6268 __le16 req_type; 6269 __le16 cmpl_ring; 6270 __le16 seq_id; 6271 __le16 target_id; 6272 __le64 resp_addr; 6273 __le32 flags; 6274 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6275 __le32 enables; 6276 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6277 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6278 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6279 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6280 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6281 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6282 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6283 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6284 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6285 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6286 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6287 __le64 l2_filter_id; 6288 u8 l2_addr[6]; 6289 __le16 l2_ivlan; 6290 __le32 l3_addr[4]; 6291 __le32 t_l3_addr[4]; 6292 u8 l3_addr_type; 6293 u8 t_l3_addr_type; 6294 u8 tunnel_type; 6295 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6296 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6297 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6298 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6299 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6300 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6301 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6302 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6303 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6304 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6305 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6306 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6307 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6308 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6309 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6310 u8 tunnel_flags; 6311 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6312 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6313 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6314 __le32 vni; 6315 __le32 dst_vnic_id; 6316 __le32 mirror_vnic_id; 6317 }; 6318 6319 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6320 struct hwrm_cfa_tunnel_filter_alloc_output { 6321 __le16 error_code; 6322 __le16 req_type; 6323 __le16 seq_id; 6324 __le16 resp_len; 6325 __le64 tunnel_filter_id; 6326 __le32 flow_id; 6327 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6328 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6329 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6330 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6331 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6332 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6333 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6334 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6335 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6336 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6337 u8 unused_0[3]; 6338 u8 valid; 6339 }; 6340 6341 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6342 struct hwrm_cfa_tunnel_filter_free_input { 6343 __le16 req_type; 6344 __le16 cmpl_ring; 6345 __le16 seq_id; 6346 __le16 target_id; 6347 __le64 resp_addr; 6348 __le64 tunnel_filter_id; 6349 }; 6350 6351 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6352 struct hwrm_cfa_tunnel_filter_free_output { 6353 __le16 error_code; 6354 __le16 req_type; 6355 __le16 seq_id; 6356 __le16 resp_len; 6357 u8 unused_0[7]; 6358 u8 valid; 6359 }; 6360 6361 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6362 struct hwrm_vxlan_ipv4_hdr { 6363 u8 ver_hlen; 6364 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6365 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6366 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6367 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6368 u8 tos; 6369 __be16 ip_id; 6370 __be16 flags_frag_offset; 6371 u8 ttl; 6372 u8 protocol; 6373 __be32 src_ip_addr; 6374 __be32 dest_ip_addr; 6375 }; 6376 6377 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6378 struct hwrm_vxlan_ipv6_hdr { 6379 __be32 ver_tc_flow_label; 6380 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6381 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6382 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6383 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6384 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6385 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6386 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6387 __be16 payload_len; 6388 u8 next_hdr; 6389 u8 ttl; 6390 __be32 src_ip_addr[4]; 6391 __be32 dest_ip_addr[4]; 6392 }; 6393 6394 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6395 struct hwrm_cfa_encap_data_vxlan { 6396 u8 src_mac_addr[6]; 6397 __le16 unused_0; 6398 u8 dst_mac_addr[6]; 6399 u8 num_vlan_tags; 6400 u8 unused_1; 6401 __be16 ovlan_tpid; 6402 __be16 ovlan_tci; 6403 __be16 ivlan_tpid; 6404 __be16 ivlan_tci; 6405 __le32 l3[10]; 6406 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6407 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6408 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6409 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6410 __be16 src_port; 6411 __be16 dst_port; 6412 __be32 vni; 6413 u8 hdr_rsvd0[3]; 6414 u8 hdr_rsvd1; 6415 u8 hdr_flags; 6416 u8 unused[3]; 6417 }; 6418 6419 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 6420 struct hwrm_cfa_encap_record_alloc_input { 6421 __le16 req_type; 6422 __le16 cmpl_ring; 6423 __le16 seq_id; 6424 __le16 target_id; 6425 __le64 resp_addr; 6426 __le32 flags; 6427 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6428 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 6429 u8 encap_type; 6430 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 6431 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 6432 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 6433 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 6434 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 6435 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 6436 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 6437 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 6438 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 6439 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 6440 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 6441 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 6442 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 6443 u8 unused_0[3]; 6444 __le32 encap_data[20]; 6445 }; 6446 6447 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 6448 struct hwrm_cfa_encap_record_alloc_output { 6449 __le16 error_code; 6450 __le16 req_type; 6451 __le16 seq_id; 6452 __le16 resp_len; 6453 __le32 encap_record_id; 6454 u8 unused_0[3]; 6455 u8 valid; 6456 }; 6457 6458 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 6459 struct hwrm_cfa_encap_record_free_input { 6460 __le16 req_type; 6461 __le16 cmpl_ring; 6462 __le16 seq_id; 6463 __le16 target_id; 6464 __le64 resp_addr; 6465 __le32 encap_record_id; 6466 u8 unused_0[4]; 6467 }; 6468 6469 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 6470 struct hwrm_cfa_encap_record_free_output { 6471 __le16 error_code; 6472 __le16 req_type; 6473 __le16 seq_id; 6474 __le16 resp_len; 6475 u8 unused_0[7]; 6476 u8 valid; 6477 }; 6478 6479 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 6480 struct hwrm_cfa_ntuple_filter_alloc_input { 6481 __le16 req_type; 6482 __le16 cmpl_ring; 6483 __le16 seq_id; 6484 __le16 target_id; 6485 __le64 resp_addr; 6486 __le32 flags; 6487 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6488 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 6489 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 6490 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 6491 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 6492 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 6493 __le32 enables; 6494 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6495 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 6496 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 6497 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 6498 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 6499 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 6500 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 6501 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 6502 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 6503 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6504 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6505 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6506 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6507 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6508 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6509 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6510 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6511 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6512 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 6513 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6514 __le64 l2_filter_id; 6515 u8 src_macaddr[6]; 6516 __be16 ethertype; 6517 u8 ip_addr_type; 6518 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6519 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6520 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6521 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6522 u8 ip_protocol; 6523 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6524 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6525 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6526 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6527 __le16 dst_id; 6528 __le16 mirror_vnic_id; 6529 u8 tunnel_type; 6530 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6531 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6532 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6533 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6534 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6535 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6536 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6537 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6538 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6539 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6540 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6541 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6542 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6543 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6544 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6545 u8 pri_hint; 6546 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6547 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6548 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6549 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6550 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6551 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6552 __be32 src_ipaddr[4]; 6553 __be32 src_ipaddr_mask[4]; 6554 __be32 dst_ipaddr[4]; 6555 __be32 dst_ipaddr_mask[4]; 6556 __be16 src_port; 6557 __be16 src_port_mask; 6558 __be16 dst_port; 6559 __be16 dst_port_mask; 6560 __le64 ntuple_filter_id_hint; 6561 }; 6562 6563 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6564 struct hwrm_cfa_ntuple_filter_alloc_output { 6565 __le16 error_code; 6566 __le16 req_type; 6567 __le16 seq_id; 6568 __le16 resp_len; 6569 __le64 ntuple_filter_id; 6570 __le32 flow_id; 6571 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6572 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6573 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6574 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6575 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6576 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6577 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6578 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6579 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6580 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6581 u8 unused_0[3]; 6582 u8 valid; 6583 }; 6584 6585 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 6586 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 6587 u8 code; 6588 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6589 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6590 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 6591 u8 unused_0[7]; 6592 }; 6593 6594 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6595 struct hwrm_cfa_ntuple_filter_free_input { 6596 __le16 req_type; 6597 __le16 cmpl_ring; 6598 __le16 seq_id; 6599 __le16 target_id; 6600 __le64 resp_addr; 6601 __le64 ntuple_filter_id; 6602 }; 6603 6604 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6605 struct hwrm_cfa_ntuple_filter_free_output { 6606 __le16 error_code; 6607 __le16 req_type; 6608 __le16 seq_id; 6609 __le16 resp_len; 6610 u8 unused_0[7]; 6611 u8 valid; 6612 }; 6613 6614 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6615 struct hwrm_cfa_ntuple_filter_cfg_input { 6616 __le16 req_type; 6617 __le16 cmpl_ring; 6618 __le16 seq_id; 6619 __le16 target_id; 6620 __le64 resp_addr; 6621 __le32 enables; 6622 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6623 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6624 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 6625 __le32 flags; 6626 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 6627 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6628 __le64 ntuple_filter_id; 6629 __le32 new_dst_id; 6630 __le32 new_mirror_vnic_id; 6631 __le16 new_meter_instance_id; 6632 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6633 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6634 u8 unused_1[6]; 6635 }; 6636 6637 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6638 struct hwrm_cfa_ntuple_filter_cfg_output { 6639 __le16 error_code; 6640 __le16 req_type; 6641 __le16 seq_id; 6642 __le16 resp_len; 6643 u8 unused_0[7]; 6644 u8 valid; 6645 }; 6646 6647 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 6648 struct hwrm_cfa_decap_filter_alloc_input { 6649 __le16 req_type; 6650 __le16 cmpl_ring; 6651 __le16 seq_id; 6652 __le16 target_id; 6653 __le64 resp_addr; 6654 __le32 flags; 6655 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 6656 __le32 enables; 6657 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 6658 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 6659 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 6660 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 6661 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 6662 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 6663 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 6664 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 6665 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 6666 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 6667 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 6668 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 6669 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 6670 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 6671 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 6672 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6673 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6674 __be32 tunnel_id; 6675 u8 tunnel_type; 6676 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6677 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6678 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6679 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6680 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6681 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6682 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6683 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6684 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6685 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6686 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6687 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6688 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6689 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6690 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6691 u8 unused_0; 6692 __le16 unused_1; 6693 u8 src_macaddr[6]; 6694 u8 unused_2[2]; 6695 u8 dst_macaddr[6]; 6696 __be16 ovlan_vid; 6697 __be16 ivlan_vid; 6698 __be16 t_ovlan_vid; 6699 __be16 t_ivlan_vid; 6700 __be16 ethertype; 6701 u8 ip_addr_type; 6702 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6703 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6704 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6705 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6706 u8 ip_protocol; 6707 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6708 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6709 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6710 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6711 __le16 unused_3; 6712 __le32 unused_4; 6713 __be32 src_ipaddr[4]; 6714 __be32 dst_ipaddr[4]; 6715 __be16 src_port; 6716 __be16 dst_port; 6717 __le16 dst_id; 6718 __le16 l2_ctxt_ref_id; 6719 }; 6720 6721 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6722 struct hwrm_cfa_decap_filter_alloc_output { 6723 __le16 error_code; 6724 __le16 req_type; 6725 __le16 seq_id; 6726 __le16 resp_len; 6727 __le32 decap_filter_id; 6728 u8 unused_0[3]; 6729 u8 valid; 6730 }; 6731 6732 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6733 struct hwrm_cfa_decap_filter_free_input { 6734 __le16 req_type; 6735 __le16 cmpl_ring; 6736 __le16 seq_id; 6737 __le16 target_id; 6738 __le64 resp_addr; 6739 __le32 decap_filter_id; 6740 u8 unused_0[4]; 6741 }; 6742 6743 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6744 struct hwrm_cfa_decap_filter_free_output { 6745 __le16 error_code; 6746 __le16 req_type; 6747 __le16 seq_id; 6748 __le16 resp_len; 6749 u8 unused_0[7]; 6750 u8 valid; 6751 }; 6752 6753 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6754 struct hwrm_cfa_flow_alloc_input { 6755 __le16 req_type; 6756 __le16 cmpl_ring; 6757 __le16 seq_id; 6758 __le16 target_id; 6759 __le64 resp_addr; 6760 __le16 flags; 6761 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6762 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6763 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6764 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6765 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6766 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6767 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6768 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6769 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6770 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6771 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6772 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6773 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6774 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6775 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6776 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6777 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6778 __le16 src_fid; 6779 __le32 tunnel_handle; 6780 __le16 action_flags; 6781 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6782 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6783 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6784 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6785 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6786 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6787 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6788 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6789 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6790 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6791 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6792 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6793 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6794 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6795 __le16 dst_fid; 6796 __be16 l2_rewrite_vlan_tpid; 6797 __be16 l2_rewrite_vlan_tci; 6798 __le16 act_meter_id; 6799 __le16 ref_flow_handle; 6800 __be16 ethertype; 6801 __be16 outer_vlan_tci; 6802 __be16 dmac[3]; 6803 __be16 inner_vlan_tci; 6804 __be16 smac[3]; 6805 u8 ip_dst_mask_len; 6806 u8 ip_src_mask_len; 6807 __be32 ip_dst[4]; 6808 __be32 ip_src[4]; 6809 __be16 l4_src_port; 6810 __be16 l4_src_port_mask; 6811 __be16 l4_dst_port; 6812 __be16 l4_dst_port_mask; 6813 __be32 nat_ip_address[4]; 6814 __be16 l2_rewrite_dmac[3]; 6815 __be16 nat_port; 6816 __be16 l2_rewrite_smac[3]; 6817 u8 ip_proto; 6818 u8 tunnel_type; 6819 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6820 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6821 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6822 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6823 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6824 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6825 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6826 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6827 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6828 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6829 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6830 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6831 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6832 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6833 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6834 }; 6835 6836 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6837 struct hwrm_cfa_flow_alloc_output { 6838 __le16 error_code; 6839 __le16 req_type; 6840 __le16 seq_id; 6841 __le16 resp_len; 6842 __le16 flow_handle; 6843 u8 unused_0[2]; 6844 __le32 flow_id; 6845 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6846 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6847 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6848 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6849 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6850 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6851 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6852 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6853 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6854 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6855 __le64 ext_flow_handle; 6856 __le32 flow_counter_id; 6857 u8 unused_1[3]; 6858 u8 valid; 6859 }; 6860 6861 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6862 struct hwrm_cfa_flow_alloc_cmd_err { 6863 u8 code; 6864 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6865 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6866 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6867 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6868 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6869 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6870 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6871 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6872 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6873 u8 unused_0[7]; 6874 }; 6875 6876 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6877 struct hwrm_cfa_flow_free_input { 6878 __le16 req_type; 6879 __le16 cmpl_ring; 6880 __le16 seq_id; 6881 __le16 target_id; 6882 __le64 resp_addr; 6883 __le16 flow_handle; 6884 __le16 unused_0; 6885 __le32 flow_counter_id; 6886 __le64 ext_flow_handle; 6887 }; 6888 6889 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6890 struct hwrm_cfa_flow_free_output { 6891 __le16 error_code; 6892 __le16 req_type; 6893 __le16 seq_id; 6894 __le16 resp_len; 6895 __le64 packet; 6896 __le64 byte; 6897 u8 unused_0[7]; 6898 u8 valid; 6899 }; 6900 6901 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6902 struct hwrm_cfa_flow_info_input { 6903 __le16 req_type; 6904 __le16 cmpl_ring; 6905 __le16 seq_id; 6906 __le16 target_id; 6907 __le64 resp_addr; 6908 __le16 flow_handle; 6909 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6910 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6911 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6912 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6913 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6914 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6915 u8 unused_0[6]; 6916 __le64 ext_flow_handle; 6917 }; 6918 6919 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6920 struct hwrm_cfa_flow_info_output { 6921 __le16 error_code; 6922 __le16 req_type; 6923 __le16 seq_id; 6924 __le16 resp_len; 6925 u8 flags; 6926 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6927 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6928 u8 profile; 6929 __le16 src_fid; 6930 __le16 dst_fid; 6931 __le16 l2_ctxt_id; 6932 __le64 em_info; 6933 __le64 tcam_info; 6934 __le64 vfp_tcam_info; 6935 __le16 ar_id; 6936 __le16 flow_handle; 6937 __le32 tunnel_handle; 6938 __le16 flow_timer; 6939 u8 unused_0[6]; 6940 __le32 flow_key_data[130]; 6941 __le32 flow_action_info[30]; 6942 u8 unused_1[7]; 6943 u8 valid; 6944 }; 6945 6946 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6947 struct hwrm_cfa_flow_stats_input { 6948 __le16 req_type; 6949 __le16 cmpl_ring; 6950 __le16 seq_id; 6951 __le16 target_id; 6952 __le64 resp_addr; 6953 __le16 num_flows; 6954 __le16 flow_handle_0; 6955 __le16 flow_handle_1; 6956 __le16 flow_handle_2; 6957 __le16 flow_handle_3; 6958 __le16 flow_handle_4; 6959 __le16 flow_handle_5; 6960 __le16 flow_handle_6; 6961 __le16 flow_handle_7; 6962 __le16 flow_handle_8; 6963 __le16 flow_handle_9; 6964 u8 unused_0[2]; 6965 __le32 flow_id_0; 6966 __le32 flow_id_1; 6967 __le32 flow_id_2; 6968 __le32 flow_id_3; 6969 __le32 flow_id_4; 6970 __le32 flow_id_5; 6971 __le32 flow_id_6; 6972 __le32 flow_id_7; 6973 __le32 flow_id_8; 6974 __le32 flow_id_9; 6975 }; 6976 6977 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6978 struct hwrm_cfa_flow_stats_output { 6979 __le16 error_code; 6980 __le16 req_type; 6981 __le16 seq_id; 6982 __le16 resp_len; 6983 __le64 packet_0; 6984 __le64 packet_1; 6985 __le64 packet_2; 6986 __le64 packet_3; 6987 __le64 packet_4; 6988 __le64 packet_5; 6989 __le64 packet_6; 6990 __le64 packet_7; 6991 __le64 packet_8; 6992 __le64 packet_9; 6993 __le64 byte_0; 6994 __le64 byte_1; 6995 __le64 byte_2; 6996 __le64 byte_3; 6997 __le64 byte_4; 6998 __le64 byte_5; 6999 __le64 byte_6; 7000 __le64 byte_7; 7001 __le64 byte_8; 7002 __le64 byte_9; 7003 u8 unused_0[7]; 7004 u8 valid; 7005 }; 7006 7007 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 7008 struct hwrm_cfa_vfr_alloc_input { 7009 __le16 req_type; 7010 __le16 cmpl_ring; 7011 __le16 seq_id; 7012 __le16 target_id; 7013 __le64 resp_addr; 7014 __le16 vf_id; 7015 __le16 reserved; 7016 u8 unused_0[4]; 7017 char vfr_name[32]; 7018 }; 7019 7020 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 7021 struct hwrm_cfa_vfr_alloc_output { 7022 __le16 error_code; 7023 __le16 req_type; 7024 __le16 seq_id; 7025 __le16 resp_len; 7026 __le16 rx_cfa_code; 7027 __le16 tx_cfa_action; 7028 u8 unused_0[3]; 7029 u8 valid; 7030 }; 7031 7032 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 7033 struct hwrm_cfa_vfr_free_input { 7034 __le16 req_type; 7035 __le16 cmpl_ring; 7036 __le16 seq_id; 7037 __le16 target_id; 7038 __le64 resp_addr; 7039 char vfr_name[32]; 7040 __le16 vf_id; 7041 __le16 reserved; 7042 u8 unused_0[4]; 7043 }; 7044 7045 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 7046 struct hwrm_cfa_vfr_free_output { 7047 __le16 error_code; 7048 __le16 req_type; 7049 __le16 seq_id; 7050 __le16 resp_len; 7051 u8 unused_0[7]; 7052 u8 valid; 7053 }; 7054 7055 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 7056 struct hwrm_cfa_eem_qcaps_input { 7057 __le16 req_type; 7058 __le16 cmpl_ring; 7059 __le16 seq_id; 7060 __le16 target_id; 7061 __le64 resp_addr; 7062 __le32 flags; 7063 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 7064 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 7065 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7066 __le32 unused_0; 7067 }; 7068 7069 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 7070 struct hwrm_cfa_eem_qcaps_output { 7071 __le16 error_code; 7072 __le16 req_type; 7073 __le16 seq_id; 7074 __le16 resp_len; 7075 __le32 flags; 7076 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 7077 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 7078 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 7079 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 7080 __le32 unused_0; 7081 __le32 supported; 7082 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 7083 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 7084 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 7085 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 7086 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 7087 __le32 max_entries_supported; 7088 __le16 key_entry_size; 7089 __le16 record_entry_size; 7090 __le16 efc_entry_size; 7091 __le16 fid_entry_size; 7092 u8 unused_1[7]; 7093 u8 valid; 7094 }; 7095 7096 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 7097 struct hwrm_cfa_eem_cfg_input { 7098 __le16 req_type; 7099 __le16 cmpl_ring; 7100 __le16 seq_id; 7101 __le16 target_id; 7102 __le64 resp_addr; 7103 __le32 flags; 7104 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 7105 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 7106 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7107 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 7108 __le16 group_id; 7109 __le16 unused_0; 7110 __le32 num_entries; 7111 __le32 unused_1; 7112 __le16 key0_ctx_id; 7113 __le16 key1_ctx_id; 7114 __le16 record_ctx_id; 7115 __le16 efc_ctx_id; 7116 __le16 fid_ctx_id; 7117 __le16 unused_2; 7118 __le32 unused_3; 7119 }; 7120 7121 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 7122 struct hwrm_cfa_eem_cfg_output { 7123 __le16 error_code; 7124 __le16 req_type; 7125 __le16 seq_id; 7126 __le16 resp_len; 7127 u8 unused_0[7]; 7128 u8 valid; 7129 }; 7130 7131 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 7132 struct hwrm_cfa_eem_qcfg_input { 7133 __le16 req_type; 7134 __le16 cmpl_ring; 7135 __le16 seq_id; 7136 __le16 target_id; 7137 __le64 resp_addr; 7138 __le32 flags; 7139 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 7140 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 7141 __le32 unused_0; 7142 }; 7143 7144 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 7145 struct hwrm_cfa_eem_qcfg_output { 7146 __le16 error_code; 7147 __le16 req_type; 7148 __le16 seq_id; 7149 __le16 resp_len; 7150 __le32 flags; 7151 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 7152 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 7153 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 7154 __le32 num_entries; 7155 __le16 key0_ctx_id; 7156 __le16 key1_ctx_id; 7157 __le16 record_ctx_id; 7158 __le16 efc_ctx_id; 7159 __le16 fid_ctx_id; 7160 u8 unused_2[5]; 7161 u8 valid; 7162 }; 7163 7164 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 7165 struct hwrm_cfa_eem_op_input { 7166 __le16 req_type; 7167 __le16 cmpl_ring; 7168 __le16 seq_id; 7169 __le16 target_id; 7170 __le64 resp_addr; 7171 __le32 flags; 7172 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 7173 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 7174 __le16 unused_0; 7175 __le16 op; 7176 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 7177 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 7178 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 7179 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 7180 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 7181 }; 7182 7183 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 7184 struct hwrm_cfa_eem_op_output { 7185 __le16 error_code; 7186 __le16 req_type; 7187 __le16 seq_id; 7188 __le16 resp_len; 7189 u8 unused_0[7]; 7190 u8 valid; 7191 }; 7192 7193 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 7194 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 7195 __le16 req_type; 7196 __le16 cmpl_ring; 7197 __le16 seq_id; 7198 __le16 target_id; 7199 __le64 resp_addr; 7200 __le32 unused_0[4]; 7201 }; 7202 7203 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 7204 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 7205 __le16 error_code; 7206 __le16 req_type; 7207 __le16 seq_id; 7208 __le16 resp_len; 7209 __le32 flags; 7210 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 7211 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 7212 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 7213 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 7214 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 7215 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 7216 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 7217 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 7218 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7219 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7220 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7221 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7222 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7223 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7224 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7225 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7226 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 7227 u8 unused_0[3]; 7228 u8 valid; 7229 }; 7230 7231 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7232 struct hwrm_tunnel_dst_port_query_input { 7233 __le16 req_type; 7234 __le16 cmpl_ring; 7235 __le16 seq_id; 7236 __le16 target_id; 7237 __le64 resp_addr; 7238 u8 tunnel_type; 7239 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7240 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7241 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7242 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7243 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7244 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7245 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7246 u8 unused_0[7]; 7247 }; 7248 7249 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7250 struct hwrm_tunnel_dst_port_query_output { 7251 __le16 error_code; 7252 __le16 req_type; 7253 __le16 seq_id; 7254 __le16 resp_len; 7255 __le16 tunnel_dst_port_id; 7256 __be16 tunnel_dst_port_val; 7257 u8 unused_0[3]; 7258 u8 valid; 7259 }; 7260 7261 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7262 struct hwrm_tunnel_dst_port_alloc_input { 7263 __le16 req_type; 7264 __le16 cmpl_ring; 7265 __le16 seq_id; 7266 __le16 target_id; 7267 __le64 resp_addr; 7268 u8 tunnel_type; 7269 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7270 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7271 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7272 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7273 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7274 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7275 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7276 u8 unused_0; 7277 __be16 tunnel_dst_port_val; 7278 u8 unused_1[4]; 7279 }; 7280 7281 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7282 struct hwrm_tunnel_dst_port_alloc_output { 7283 __le16 error_code; 7284 __le16 req_type; 7285 __le16 seq_id; 7286 __le16 resp_len; 7287 __le16 tunnel_dst_port_id; 7288 u8 unused_0[5]; 7289 u8 valid; 7290 }; 7291 7292 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7293 struct hwrm_tunnel_dst_port_free_input { 7294 __le16 req_type; 7295 __le16 cmpl_ring; 7296 __le16 seq_id; 7297 __le16 target_id; 7298 __le64 resp_addr; 7299 u8 tunnel_type; 7300 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7301 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7302 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7303 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7304 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7305 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7306 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7307 u8 unused_0; 7308 __le16 tunnel_dst_port_id; 7309 u8 unused_1[4]; 7310 }; 7311 7312 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7313 struct hwrm_tunnel_dst_port_free_output { 7314 __le16 error_code; 7315 __le16 req_type; 7316 __le16 seq_id; 7317 __le16 resp_len; 7318 u8 unused_1[7]; 7319 u8 valid; 7320 }; 7321 7322 /* ctx_hw_stats (size:1280b/160B) */ 7323 struct ctx_hw_stats { 7324 __le64 rx_ucast_pkts; 7325 __le64 rx_mcast_pkts; 7326 __le64 rx_bcast_pkts; 7327 __le64 rx_discard_pkts; 7328 __le64 rx_error_pkts; 7329 __le64 rx_ucast_bytes; 7330 __le64 rx_mcast_bytes; 7331 __le64 rx_bcast_bytes; 7332 __le64 tx_ucast_pkts; 7333 __le64 tx_mcast_pkts; 7334 __le64 tx_bcast_pkts; 7335 __le64 tx_error_pkts; 7336 __le64 tx_discard_pkts; 7337 __le64 tx_ucast_bytes; 7338 __le64 tx_mcast_bytes; 7339 __le64 tx_bcast_bytes; 7340 __le64 tpa_pkts; 7341 __le64 tpa_bytes; 7342 __le64 tpa_events; 7343 __le64 tpa_aborts; 7344 }; 7345 7346 /* ctx_hw_stats_ext (size:1408b/176B) */ 7347 struct ctx_hw_stats_ext { 7348 __le64 rx_ucast_pkts; 7349 __le64 rx_mcast_pkts; 7350 __le64 rx_bcast_pkts; 7351 __le64 rx_discard_pkts; 7352 __le64 rx_error_pkts; 7353 __le64 rx_ucast_bytes; 7354 __le64 rx_mcast_bytes; 7355 __le64 rx_bcast_bytes; 7356 __le64 tx_ucast_pkts; 7357 __le64 tx_mcast_pkts; 7358 __le64 tx_bcast_pkts; 7359 __le64 tx_error_pkts; 7360 __le64 tx_discard_pkts; 7361 __le64 tx_ucast_bytes; 7362 __le64 tx_mcast_bytes; 7363 __le64 tx_bcast_bytes; 7364 __le64 rx_tpa_eligible_pkt; 7365 __le64 rx_tpa_eligible_bytes; 7366 __le64 rx_tpa_pkt; 7367 __le64 rx_tpa_bytes; 7368 __le64 rx_tpa_errors; 7369 __le64 rx_tpa_events; 7370 }; 7371 7372 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7373 struct hwrm_stat_ctx_alloc_input { 7374 __le16 req_type; 7375 __le16 cmpl_ring; 7376 __le16 seq_id; 7377 __le16 target_id; 7378 __le64 resp_addr; 7379 __le64 stats_dma_addr; 7380 __le32 update_period_ms; 7381 u8 stat_ctx_flags; 7382 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7383 u8 unused_0; 7384 __le16 stats_dma_length; 7385 }; 7386 7387 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7388 struct hwrm_stat_ctx_alloc_output { 7389 __le16 error_code; 7390 __le16 req_type; 7391 __le16 seq_id; 7392 __le16 resp_len; 7393 __le32 stat_ctx_id; 7394 u8 unused_0[3]; 7395 u8 valid; 7396 }; 7397 7398 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7399 struct hwrm_stat_ctx_free_input { 7400 __le16 req_type; 7401 __le16 cmpl_ring; 7402 __le16 seq_id; 7403 __le16 target_id; 7404 __le64 resp_addr; 7405 __le32 stat_ctx_id; 7406 u8 unused_0[4]; 7407 }; 7408 7409 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7410 struct hwrm_stat_ctx_free_output { 7411 __le16 error_code; 7412 __le16 req_type; 7413 __le16 seq_id; 7414 __le16 resp_len; 7415 __le32 stat_ctx_id; 7416 u8 unused_0[3]; 7417 u8 valid; 7418 }; 7419 7420 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 7421 struct hwrm_stat_ctx_query_input { 7422 __le16 req_type; 7423 __le16 cmpl_ring; 7424 __le16 seq_id; 7425 __le16 target_id; 7426 __le64 resp_addr; 7427 __le32 stat_ctx_id; 7428 u8 flags; 7429 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7430 u8 unused_0[3]; 7431 }; 7432 7433 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 7434 struct hwrm_stat_ctx_query_output { 7435 __le16 error_code; 7436 __le16 req_type; 7437 __le16 seq_id; 7438 __le16 resp_len; 7439 __le64 tx_ucast_pkts; 7440 __le64 tx_mcast_pkts; 7441 __le64 tx_bcast_pkts; 7442 __le64 tx_discard_pkts; 7443 __le64 tx_error_pkts; 7444 __le64 tx_ucast_bytes; 7445 __le64 tx_mcast_bytes; 7446 __le64 tx_bcast_bytes; 7447 __le64 rx_ucast_pkts; 7448 __le64 rx_mcast_pkts; 7449 __le64 rx_bcast_pkts; 7450 __le64 rx_discard_pkts; 7451 __le64 rx_error_pkts; 7452 __le64 rx_ucast_bytes; 7453 __le64 rx_mcast_bytes; 7454 __le64 rx_bcast_bytes; 7455 __le64 rx_agg_pkts; 7456 __le64 rx_agg_bytes; 7457 __le64 rx_agg_events; 7458 __le64 rx_agg_aborts; 7459 u8 unused_0[7]; 7460 u8 valid; 7461 }; 7462 7463 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 7464 struct hwrm_stat_ext_ctx_query_input { 7465 __le16 req_type; 7466 __le16 cmpl_ring; 7467 __le16 seq_id; 7468 __le16 target_id; 7469 __le64 resp_addr; 7470 __le32 stat_ctx_id; 7471 u8 flags; 7472 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7473 u8 unused_0[3]; 7474 }; 7475 7476 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 7477 struct hwrm_stat_ext_ctx_query_output { 7478 __le16 error_code; 7479 __le16 req_type; 7480 __le16 seq_id; 7481 __le16 resp_len; 7482 __le64 rx_ucast_pkts; 7483 __le64 rx_mcast_pkts; 7484 __le64 rx_bcast_pkts; 7485 __le64 rx_discard_pkts; 7486 __le64 rx_error_pkts; 7487 __le64 rx_ucast_bytes; 7488 __le64 rx_mcast_bytes; 7489 __le64 rx_bcast_bytes; 7490 __le64 tx_ucast_pkts; 7491 __le64 tx_mcast_pkts; 7492 __le64 tx_bcast_pkts; 7493 __le64 tx_error_pkts; 7494 __le64 tx_discard_pkts; 7495 __le64 tx_ucast_bytes; 7496 __le64 tx_mcast_bytes; 7497 __le64 tx_bcast_bytes; 7498 __le64 rx_tpa_eligible_pkt; 7499 __le64 rx_tpa_eligible_bytes; 7500 __le64 rx_tpa_pkt; 7501 __le64 rx_tpa_bytes; 7502 __le64 rx_tpa_errors; 7503 __le64 rx_tpa_events; 7504 u8 unused_0[7]; 7505 u8 valid; 7506 }; 7507 7508 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 7509 struct hwrm_stat_ctx_clr_stats_input { 7510 __le16 req_type; 7511 __le16 cmpl_ring; 7512 __le16 seq_id; 7513 __le16 target_id; 7514 __le64 resp_addr; 7515 __le32 stat_ctx_id; 7516 u8 unused_0[4]; 7517 }; 7518 7519 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 7520 struct hwrm_stat_ctx_clr_stats_output { 7521 __le16 error_code; 7522 __le16 req_type; 7523 __le16 seq_id; 7524 __le16 resp_len; 7525 u8 unused_0[7]; 7526 u8 valid; 7527 }; 7528 7529 /* hwrm_pcie_qstats_input (size:256b/32B) */ 7530 struct hwrm_pcie_qstats_input { 7531 __le16 req_type; 7532 __le16 cmpl_ring; 7533 __le16 seq_id; 7534 __le16 target_id; 7535 __le64 resp_addr; 7536 __le16 pcie_stat_size; 7537 u8 unused_0[6]; 7538 __le64 pcie_stat_host_addr; 7539 }; 7540 7541 /* hwrm_pcie_qstats_output (size:128b/16B) */ 7542 struct hwrm_pcie_qstats_output { 7543 __le16 error_code; 7544 __le16 req_type; 7545 __le16 seq_id; 7546 __le16 resp_len; 7547 __le16 pcie_stat_size; 7548 u8 unused_0[5]; 7549 u8 valid; 7550 }; 7551 7552 /* pcie_ctx_hw_stats (size:768b/96B) */ 7553 struct pcie_ctx_hw_stats { 7554 __le64 pcie_pl_signal_integrity; 7555 __le64 pcie_dl_signal_integrity; 7556 __le64 pcie_tl_signal_integrity; 7557 __le64 pcie_link_integrity; 7558 __le64 pcie_tx_traffic_rate; 7559 __le64 pcie_rx_traffic_rate; 7560 __le64 pcie_tx_dllp_statistics; 7561 __le64 pcie_rx_dllp_statistics; 7562 __le64 pcie_equalization_time; 7563 __le32 pcie_ltssm_histogram[4]; 7564 __le64 pcie_recovery_histogram; 7565 }; 7566 7567 /* hwrm_fw_reset_input (size:192b/24B) */ 7568 struct hwrm_fw_reset_input { 7569 __le16 req_type; 7570 __le16 cmpl_ring; 7571 __le16 seq_id; 7572 __le16 target_id; 7573 __le64 resp_addr; 7574 u8 embedded_proc_type; 7575 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7576 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7577 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7578 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7579 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7580 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7581 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7582 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 7583 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 7584 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7585 u8 selfrst_status; 7586 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7587 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7588 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7589 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7590 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7591 u8 host_idx; 7592 u8 flags; 7593 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 7594 u8 unused_0[4]; 7595 }; 7596 7597 /* hwrm_fw_reset_output (size:128b/16B) */ 7598 struct hwrm_fw_reset_output { 7599 __le16 error_code; 7600 __le16 req_type; 7601 __le16 seq_id; 7602 __le16 resp_len; 7603 u8 selfrst_status; 7604 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7605 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7606 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7607 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7608 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7609 u8 unused_0[6]; 7610 u8 valid; 7611 }; 7612 7613 /* hwrm_fw_qstatus_input (size:192b/24B) */ 7614 struct hwrm_fw_qstatus_input { 7615 __le16 req_type; 7616 __le16 cmpl_ring; 7617 __le16 seq_id; 7618 __le16 target_id; 7619 __le64 resp_addr; 7620 u8 embedded_proc_type; 7621 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7622 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7623 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7624 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7625 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7626 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7627 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7628 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7629 u8 unused_0[7]; 7630 }; 7631 7632 /* hwrm_fw_qstatus_output (size:128b/16B) */ 7633 struct hwrm_fw_qstatus_output { 7634 __le16 error_code; 7635 __le16 req_type; 7636 __le16 seq_id; 7637 __le16 resp_len; 7638 u8 selfrst_status; 7639 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7640 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7641 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7642 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 7643 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7644 u8 nvm_option_action_status; 7645 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 7646 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 7647 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 7648 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 7649 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 7650 u8 unused_0[5]; 7651 u8 valid; 7652 }; 7653 7654 /* hwrm_fw_set_time_input (size:256b/32B) */ 7655 struct hwrm_fw_set_time_input { 7656 __le16 req_type; 7657 __le16 cmpl_ring; 7658 __le16 seq_id; 7659 __le16 target_id; 7660 __le64 resp_addr; 7661 __le16 year; 7662 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7663 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7664 u8 month; 7665 u8 day; 7666 u8 hour; 7667 u8 minute; 7668 u8 second; 7669 u8 unused_0; 7670 __le16 millisecond; 7671 __le16 zone; 7672 #define FW_SET_TIME_REQ_ZONE_UTC 0 7673 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7674 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7675 u8 unused_1[4]; 7676 }; 7677 7678 /* hwrm_fw_set_time_output (size:128b/16B) */ 7679 struct hwrm_fw_set_time_output { 7680 __le16 error_code; 7681 __le16 req_type; 7682 __le16 seq_id; 7683 __le16 resp_len; 7684 u8 unused_0[7]; 7685 u8 valid; 7686 }; 7687 7688 /* hwrm_struct_hdr (size:128b/16B) */ 7689 struct hwrm_struct_hdr { 7690 __le16 struct_id; 7691 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7692 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7693 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7694 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7695 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7696 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7697 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 7698 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 7699 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7700 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7701 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7702 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 7703 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 7704 __le16 len; 7705 u8 version; 7706 u8 count; 7707 __le16 subtype; 7708 __le16 next_offset; 7709 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7710 u8 unused_0[6]; 7711 }; 7712 7713 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7714 struct hwrm_struct_data_dcbx_app { 7715 __be16 protocol_id; 7716 u8 protocol_selector; 7717 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7718 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7719 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7720 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7721 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 7722 u8 priority; 7723 u8 valid; 7724 u8 unused_0[3]; 7725 }; 7726 7727 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7728 struct hwrm_fw_set_structured_data_input { 7729 __le16 req_type; 7730 __le16 cmpl_ring; 7731 __le16 seq_id; 7732 __le16 target_id; 7733 __le64 resp_addr; 7734 __le64 src_data_addr; 7735 __le16 data_len; 7736 u8 hdr_cnt; 7737 u8 unused_0[5]; 7738 }; 7739 7740 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7741 struct hwrm_fw_set_structured_data_output { 7742 __le16 error_code; 7743 __le16 req_type; 7744 __le16 seq_id; 7745 __le16 resp_len; 7746 u8 unused_0[7]; 7747 u8 valid; 7748 }; 7749 7750 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7751 struct hwrm_fw_set_structured_data_cmd_err { 7752 u8 code; 7753 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7754 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7755 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7756 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7757 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7758 u8 unused_0[7]; 7759 }; 7760 7761 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7762 struct hwrm_fw_get_structured_data_input { 7763 __le16 req_type; 7764 __le16 cmpl_ring; 7765 __le16 seq_id; 7766 __le16 target_id; 7767 __le64 resp_addr; 7768 __le64 dest_data_addr; 7769 __le16 data_len; 7770 __le16 structure_id; 7771 __le16 subtype; 7772 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7773 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7774 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7775 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7776 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7777 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7778 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7779 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7780 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7781 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7782 u8 count; 7783 u8 unused_0; 7784 }; 7785 7786 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7787 struct hwrm_fw_get_structured_data_output { 7788 __le16 error_code; 7789 __le16 req_type; 7790 __le16 seq_id; 7791 __le16 resp_len; 7792 u8 hdr_cnt; 7793 u8 unused_0[6]; 7794 u8 valid; 7795 }; 7796 7797 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7798 struct hwrm_fw_get_structured_data_cmd_err { 7799 u8 code; 7800 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7801 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7802 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7803 u8 unused_0[7]; 7804 }; 7805 7806 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7807 struct hwrm_exec_fwd_resp_input { 7808 __le16 req_type; 7809 __le16 cmpl_ring; 7810 __le16 seq_id; 7811 __le16 target_id; 7812 __le64 resp_addr; 7813 __le32 encap_request[26]; 7814 __le16 encap_resp_target_id; 7815 u8 unused_0[6]; 7816 }; 7817 7818 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7819 struct hwrm_exec_fwd_resp_output { 7820 __le16 error_code; 7821 __le16 req_type; 7822 __le16 seq_id; 7823 __le16 resp_len; 7824 u8 unused_0[7]; 7825 u8 valid; 7826 }; 7827 7828 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7829 struct hwrm_reject_fwd_resp_input { 7830 __le16 req_type; 7831 __le16 cmpl_ring; 7832 __le16 seq_id; 7833 __le16 target_id; 7834 __le64 resp_addr; 7835 __le32 encap_request[26]; 7836 __le16 encap_resp_target_id; 7837 u8 unused_0[6]; 7838 }; 7839 7840 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7841 struct hwrm_reject_fwd_resp_output { 7842 __le16 error_code; 7843 __le16 req_type; 7844 __le16 seq_id; 7845 __le16 resp_len; 7846 u8 unused_0[7]; 7847 u8 valid; 7848 }; 7849 7850 /* hwrm_fwd_resp_input (size:1024b/128B) */ 7851 struct hwrm_fwd_resp_input { 7852 __le16 req_type; 7853 __le16 cmpl_ring; 7854 __le16 seq_id; 7855 __le16 target_id; 7856 __le64 resp_addr; 7857 __le16 encap_resp_target_id; 7858 __le16 encap_resp_cmpl_ring; 7859 __le16 encap_resp_len; 7860 u8 unused_0; 7861 u8 unused_1; 7862 __le64 encap_resp_addr; 7863 __le32 encap_resp[24]; 7864 }; 7865 7866 /* hwrm_fwd_resp_output (size:128b/16B) */ 7867 struct hwrm_fwd_resp_output { 7868 __le16 error_code; 7869 __le16 req_type; 7870 __le16 seq_id; 7871 __le16 resp_len; 7872 u8 unused_0[7]; 7873 u8 valid; 7874 }; 7875 7876 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7877 struct hwrm_fwd_async_event_cmpl_input { 7878 __le16 req_type; 7879 __le16 cmpl_ring; 7880 __le16 seq_id; 7881 __le16 target_id; 7882 __le64 resp_addr; 7883 __le16 encap_async_event_target_id; 7884 u8 unused_0[6]; 7885 __le32 encap_async_event_cmpl[4]; 7886 }; 7887 7888 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7889 struct hwrm_fwd_async_event_cmpl_output { 7890 __le16 error_code; 7891 __le16 req_type; 7892 __le16 seq_id; 7893 __le16 resp_len; 7894 u8 unused_0[7]; 7895 u8 valid; 7896 }; 7897 7898 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7899 struct hwrm_temp_monitor_query_input { 7900 __le16 req_type; 7901 __le16 cmpl_ring; 7902 __le16 seq_id; 7903 __le16 target_id; 7904 __le64 resp_addr; 7905 }; 7906 7907 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7908 struct hwrm_temp_monitor_query_output { 7909 __le16 error_code; 7910 __le16 req_type; 7911 __le16 seq_id; 7912 __le16 resp_len; 7913 u8 temp; 7914 u8 phy_temp; 7915 u8 om_temp; 7916 u8 flags; 7917 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 7918 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 7919 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 7920 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 7921 u8 unused_0[3]; 7922 u8 valid; 7923 }; 7924 7925 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7926 struct hwrm_wol_filter_alloc_input { 7927 __le16 req_type; 7928 __le16 cmpl_ring; 7929 __le16 seq_id; 7930 __le16 target_id; 7931 __le64 resp_addr; 7932 __le32 flags; 7933 __le32 enables; 7934 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7935 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7936 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7937 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7938 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7939 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7940 __le16 port_id; 7941 u8 wol_type; 7942 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7943 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7944 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7945 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7946 u8 unused_0[5]; 7947 u8 mac_address[6]; 7948 __le16 pattern_offset; 7949 __le16 pattern_buf_size; 7950 __le16 pattern_mask_size; 7951 u8 unused_1[4]; 7952 __le64 pattern_buf_addr; 7953 __le64 pattern_mask_addr; 7954 }; 7955 7956 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7957 struct hwrm_wol_filter_alloc_output { 7958 __le16 error_code; 7959 __le16 req_type; 7960 __le16 seq_id; 7961 __le16 resp_len; 7962 u8 wol_filter_id; 7963 u8 unused_0[6]; 7964 u8 valid; 7965 }; 7966 7967 /* hwrm_wol_filter_free_input (size:256b/32B) */ 7968 struct hwrm_wol_filter_free_input { 7969 __le16 req_type; 7970 __le16 cmpl_ring; 7971 __le16 seq_id; 7972 __le16 target_id; 7973 __le64 resp_addr; 7974 __le32 flags; 7975 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7976 __le32 enables; 7977 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7978 __le16 port_id; 7979 u8 wol_filter_id; 7980 u8 unused_0[5]; 7981 }; 7982 7983 /* hwrm_wol_filter_free_output (size:128b/16B) */ 7984 struct hwrm_wol_filter_free_output { 7985 __le16 error_code; 7986 __le16 req_type; 7987 __le16 seq_id; 7988 __le16 resp_len; 7989 u8 unused_0[7]; 7990 u8 valid; 7991 }; 7992 7993 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7994 struct hwrm_wol_filter_qcfg_input { 7995 __le16 req_type; 7996 __le16 cmpl_ring; 7997 __le16 seq_id; 7998 __le16 target_id; 7999 __le64 resp_addr; 8000 __le16 port_id; 8001 __le16 handle; 8002 u8 unused_0[4]; 8003 __le64 pattern_buf_addr; 8004 __le16 pattern_buf_size; 8005 u8 unused_1[6]; 8006 __le64 pattern_mask_addr; 8007 __le16 pattern_mask_size; 8008 u8 unused_2[6]; 8009 }; 8010 8011 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 8012 struct hwrm_wol_filter_qcfg_output { 8013 __le16 error_code; 8014 __le16 req_type; 8015 __le16 seq_id; 8016 __le16 resp_len; 8017 __le16 next_handle; 8018 u8 wol_filter_id; 8019 u8 wol_type; 8020 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 8021 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 8022 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 8023 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 8024 __le32 unused_0; 8025 u8 mac_address[6]; 8026 __le16 pattern_offset; 8027 __le16 pattern_size; 8028 __le16 pattern_mask_size; 8029 u8 unused_1[3]; 8030 u8 valid; 8031 }; 8032 8033 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 8034 struct hwrm_wol_reason_qcfg_input { 8035 __le16 req_type; 8036 __le16 cmpl_ring; 8037 __le16 seq_id; 8038 __le16 target_id; 8039 __le64 resp_addr; 8040 __le16 port_id; 8041 u8 unused_0[6]; 8042 __le64 wol_pkt_buf_addr; 8043 __le16 wol_pkt_buf_size; 8044 u8 unused_1[6]; 8045 }; 8046 8047 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 8048 struct hwrm_wol_reason_qcfg_output { 8049 __le16 error_code; 8050 __le16 req_type; 8051 __le16 seq_id; 8052 __le16 resp_len; 8053 u8 wol_filter_id; 8054 u8 wol_reason; 8055 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 8056 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 8057 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 8058 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 8059 u8 wol_pkt_len; 8060 u8 unused_0[4]; 8061 u8 valid; 8062 }; 8063 8064 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 8065 struct hwrm_dbg_read_direct_input { 8066 __le16 req_type; 8067 __le16 cmpl_ring; 8068 __le16 seq_id; 8069 __le16 target_id; 8070 __le64 resp_addr; 8071 __le64 host_dest_addr; 8072 __le32 read_addr; 8073 __le32 read_len32; 8074 }; 8075 8076 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 8077 struct hwrm_dbg_read_direct_output { 8078 __le16 error_code; 8079 __le16 req_type; 8080 __le16 seq_id; 8081 __le16 resp_len; 8082 __le32 crc32; 8083 u8 unused_0[3]; 8084 u8 valid; 8085 }; 8086 8087 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 8088 struct hwrm_dbg_qcaps_input { 8089 __le16 req_type; 8090 __le16 cmpl_ring; 8091 __le16 seq_id; 8092 __le16 target_id; 8093 __le64 resp_addr; 8094 __le16 fid; 8095 u8 unused_0[6]; 8096 }; 8097 8098 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 8099 struct hwrm_dbg_qcaps_output { 8100 __le16 error_code; 8101 __le16 req_type; 8102 __le16 seq_id; 8103 __le16 resp_len; 8104 __le16 fid; 8105 u8 unused_0[2]; 8106 __le32 coredump_component_disable_caps; 8107 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 8108 __le32 flags; 8109 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 8110 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 8111 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 8112 u8 unused_1[3]; 8113 u8 valid; 8114 }; 8115 8116 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 8117 struct hwrm_dbg_qcfg_input { 8118 __le16 req_type; 8119 __le16 cmpl_ring; 8120 __le16 seq_id; 8121 __le16 target_id; 8122 __le64 resp_addr; 8123 __le16 fid; 8124 __le16 flags; 8125 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 8126 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 8127 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 8128 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 8129 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 8130 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 8131 __le32 coredump_component_disable_flags; 8132 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 8133 }; 8134 8135 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 8136 struct hwrm_dbg_qcfg_output { 8137 __le16 error_code; 8138 __le16 req_type; 8139 __le16 seq_id; 8140 __le16 resp_len; 8141 __le16 fid; 8142 u8 unused_0[2]; 8143 __le32 coredump_size; 8144 __le32 flags; 8145 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 8146 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 8147 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 8148 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 8149 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 8150 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 8151 __le16 async_cmpl_ring; 8152 u8 unused_2[2]; 8153 __le32 crashdump_size; 8154 u8 unused_3[3]; 8155 u8 valid; 8156 }; 8157 8158 /* coredump_segment_record (size:128b/16B) */ 8159 struct coredump_segment_record { 8160 __le16 component_id; 8161 __le16 segment_id; 8162 __le16 max_instances; 8163 u8 version_hi; 8164 u8 version_low; 8165 u8 seg_flags; 8166 u8 compress_flags; 8167 #define SFLAG_COMPRESSED_ZLIB 0x1UL 8168 u8 unused_0[2]; 8169 __le32 segment_len; 8170 }; 8171 8172 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 8173 struct hwrm_dbg_coredump_list_input { 8174 __le16 req_type; 8175 __le16 cmpl_ring; 8176 __le16 seq_id; 8177 __le16 target_id; 8178 __le64 resp_addr; 8179 __le64 host_dest_addr; 8180 __le32 host_buf_len; 8181 __le16 seq_no; 8182 u8 flags; 8183 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 8184 u8 unused_0[1]; 8185 }; 8186 8187 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 8188 struct hwrm_dbg_coredump_list_output { 8189 __le16 error_code; 8190 __le16 req_type; 8191 __le16 seq_id; 8192 __le16 resp_len; 8193 u8 flags; 8194 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 8195 u8 unused_0; 8196 __le16 total_segments; 8197 __le16 data_len; 8198 u8 unused_1; 8199 u8 valid; 8200 }; 8201 8202 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 8203 struct hwrm_dbg_coredump_initiate_input { 8204 __le16 req_type; 8205 __le16 cmpl_ring; 8206 __le16 seq_id; 8207 __le16 target_id; 8208 __le64 resp_addr; 8209 __le16 component_id; 8210 __le16 segment_id; 8211 __le16 instance; 8212 __le16 unused_0; 8213 u8 seg_flags; 8214 u8 unused_1[7]; 8215 }; 8216 8217 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 8218 struct hwrm_dbg_coredump_initiate_output { 8219 __le16 error_code; 8220 __le16 req_type; 8221 __le16 seq_id; 8222 __le16 resp_len; 8223 u8 unused_0[7]; 8224 u8 valid; 8225 }; 8226 8227 /* coredump_data_hdr (size:128b/16B) */ 8228 struct coredump_data_hdr { 8229 __le32 address; 8230 __le32 flags_length; 8231 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8232 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8233 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 8234 __le32 instance; 8235 __le32 next_offset; 8236 }; 8237 8238 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8239 struct hwrm_dbg_coredump_retrieve_input { 8240 __le16 req_type; 8241 __le16 cmpl_ring; 8242 __le16 seq_id; 8243 __le16 target_id; 8244 __le64 resp_addr; 8245 __le64 host_dest_addr; 8246 __le32 host_buf_len; 8247 __le32 unused_0; 8248 __le16 component_id; 8249 __le16 segment_id; 8250 __le16 instance; 8251 __le16 unused_1; 8252 u8 seg_flags; 8253 u8 unused_2; 8254 __le16 unused_3; 8255 __le32 unused_4; 8256 __le32 seq_no; 8257 __le32 unused_5; 8258 }; 8259 8260 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 8261 struct hwrm_dbg_coredump_retrieve_output { 8262 __le16 error_code; 8263 __le16 req_type; 8264 __le16 seq_id; 8265 __le16 resp_len; 8266 u8 flags; 8267 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 8268 u8 unused_0; 8269 __le16 data_len; 8270 u8 unused_1[3]; 8271 u8 valid; 8272 }; 8273 8274 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 8275 struct hwrm_dbg_ring_info_get_input { 8276 __le16 req_type; 8277 __le16 cmpl_ring; 8278 __le16 seq_id; 8279 __le16 target_id; 8280 __le64 resp_addr; 8281 u8 ring_type; 8282 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 8283 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 8284 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8285 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8286 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 8287 u8 unused_0[3]; 8288 __le32 fw_ring_id; 8289 }; 8290 8291 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 8292 struct hwrm_dbg_ring_info_get_output { 8293 __le16 error_code; 8294 __le16 req_type; 8295 __le16 seq_id; 8296 __le16 resp_len; 8297 __le32 producer_index; 8298 __le32 consumer_index; 8299 __le32 cag_vector_ctrl; 8300 u8 unused_0[3]; 8301 u8 valid; 8302 }; 8303 8304 /* hwrm_nvm_read_input (size:320b/40B) */ 8305 struct hwrm_nvm_read_input { 8306 __le16 req_type; 8307 __le16 cmpl_ring; 8308 __le16 seq_id; 8309 __le16 target_id; 8310 __le64 resp_addr; 8311 __le64 host_dest_addr; 8312 __le16 dir_idx; 8313 u8 unused_0[2]; 8314 __le32 offset; 8315 __le32 len; 8316 u8 unused_1[4]; 8317 }; 8318 8319 /* hwrm_nvm_read_output (size:128b/16B) */ 8320 struct hwrm_nvm_read_output { 8321 __le16 error_code; 8322 __le16 req_type; 8323 __le16 seq_id; 8324 __le16 resp_len; 8325 u8 unused_0[7]; 8326 u8 valid; 8327 }; 8328 8329 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8330 struct hwrm_nvm_get_dir_entries_input { 8331 __le16 req_type; 8332 __le16 cmpl_ring; 8333 __le16 seq_id; 8334 __le16 target_id; 8335 __le64 resp_addr; 8336 __le64 host_dest_addr; 8337 }; 8338 8339 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8340 struct hwrm_nvm_get_dir_entries_output { 8341 __le16 error_code; 8342 __le16 req_type; 8343 __le16 seq_id; 8344 __le16 resp_len; 8345 u8 unused_0[7]; 8346 u8 valid; 8347 }; 8348 8349 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8350 struct hwrm_nvm_get_dir_info_input { 8351 __le16 req_type; 8352 __le16 cmpl_ring; 8353 __le16 seq_id; 8354 __le16 target_id; 8355 __le64 resp_addr; 8356 }; 8357 8358 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8359 struct hwrm_nvm_get_dir_info_output { 8360 __le16 error_code; 8361 __le16 req_type; 8362 __le16 seq_id; 8363 __le16 resp_len; 8364 __le32 entries; 8365 __le32 entry_length; 8366 u8 unused_0[7]; 8367 u8 valid; 8368 }; 8369 8370 /* hwrm_nvm_write_input (size:384b/48B) */ 8371 struct hwrm_nvm_write_input { 8372 __le16 req_type; 8373 __le16 cmpl_ring; 8374 __le16 seq_id; 8375 __le16 target_id; 8376 __le64 resp_addr; 8377 __le64 host_src_addr; 8378 __le16 dir_type; 8379 __le16 dir_ordinal; 8380 __le16 dir_ext; 8381 __le16 dir_attr; 8382 __le32 dir_data_length; 8383 __le16 option; 8384 __le16 flags; 8385 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 8386 __le32 dir_item_length; 8387 __le32 unused_0; 8388 }; 8389 8390 /* hwrm_nvm_write_output (size:128b/16B) */ 8391 struct hwrm_nvm_write_output { 8392 __le16 error_code; 8393 __le16 req_type; 8394 __le16 seq_id; 8395 __le16 resp_len; 8396 __le32 dir_item_length; 8397 __le16 dir_idx; 8398 u8 unused_0; 8399 u8 valid; 8400 }; 8401 8402 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 8403 struct hwrm_nvm_write_cmd_err { 8404 u8 code; 8405 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 8406 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8407 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 8408 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 8409 u8 unused_0[7]; 8410 }; 8411 8412 /* hwrm_nvm_modify_input (size:320b/40B) */ 8413 struct hwrm_nvm_modify_input { 8414 __le16 req_type; 8415 __le16 cmpl_ring; 8416 __le16 seq_id; 8417 __le16 target_id; 8418 __le64 resp_addr; 8419 __le64 host_src_addr; 8420 __le16 dir_idx; 8421 __le16 flags; 8422 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 8423 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 8424 __le32 offset; 8425 __le32 len; 8426 u8 unused_1[4]; 8427 }; 8428 8429 /* hwrm_nvm_modify_output (size:128b/16B) */ 8430 struct hwrm_nvm_modify_output { 8431 __le16 error_code; 8432 __le16 req_type; 8433 __le16 seq_id; 8434 __le16 resp_len; 8435 u8 unused_0[7]; 8436 u8 valid; 8437 }; 8438 8439 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 8440 struct hwrm_nvm_find_dir_entry_input { 8441 __le16 req_type; 8442 __le16 cmpl_ring; 8443 __le16 seq_id; 8444 __le16 target_id; 8445 __le64 resp_addr; 8446 __le32 enables; 8447 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 8448 __le16 dir_idx; 8449 __le16 dir_type; 8450 __le16 dir_ordinal; 8451 __le16 dir_ext; 8452 u8 opt_ordinal; 8453 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 8454 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 8455 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 8456 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 8457 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 8458 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 8459 u8 unused_0[3]; 8460 }; 8461 8462 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 8463 struct hwrm_nvm_find_dir_entry_output { 8464 __le16 error_code; 8465 __le16 req_type; 8466 __le16 seq_id; 8467 __le16 resp_len; 8468 __le32 dir_item_length; 8469 __le32 dir_data_length; 8470 __le32 fw_ver; 8471 __le16 dir_ordinal; 8472 __le16 dir_idx; 8473 u8 unused_0[7]; 8474 u8 valid; 8475 }; 8476 8477 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 8478 struct hwrm_nvm_erase_dir_entry_input { 8479 __le16 req_type; 8480 __le16 cmpl_ring; 8481 __le16 seq_id; 8482 __le16 target_id; 8483 __le64 resp_addr; 8484 __le16 dir_idx; 8485 u8 unused_0[6]; 8486 }; 8487 8488 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 8489 struct hwrm_nvm_erase_dir_entry_output { 8490 __le16 error_code; 8491 __le16 req_type; 8492 __le16 seq_id; 8493 __le16 resp_len; 8494 u8 unused_0[7]; 8495 u8 valid; 8496 }; 8497 8498 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 8499 struct hwrm_nvm_get_dev_info_input { 8500 __le16 req_type; 8501 __le16 cmpl_ring; 8502 __le16 seq_id; 8503 __le16 target_id; 8504 __le64 resp_addr; 8505 }; 8506 8507 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 8508 struct hwrm_nvm_get_dev_info_output { 8509 __le16 error_code; 8510 __le16 req_type; 8511 __le16 seq_id; 8512 __le16 resp_len; 8513 __le16 manufacturer_id; 8514 __le16 device_id; 8515 __le32 sector_size; 8516 __le32 nvram_size; 8517 __le32 reserved_size; 8518 __le32 available_size; 8519 u8 nvm_cfg_ver_maj; 8520 u8 nvm_cfg_ver_min; 8521 u8 nvm_cfg_ver_upd; 8522 u8 flags; 8523 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 8524 char pkg_name[16]; 8525 __le16 hwrm_fw_major; 8526 __le16 hwrm_fw_minor; 8527 __le16 hwrm_fw_build; 8528 __le16 hwrm_fw_patch; 8529 __le16 mgmt_fw_major; 8530 __le16 mgmt_fw_minor; 8531 __le16 mgmt_fw_build; 8532 __le16 mgmt_fw_patch; 8533 __le16 roce_fw_major; 8534 __le16 roce_fw_minor; 8535 __le16 roce_fw_build; 8536 __le16 roce_fw_patch; 8537 u8 unused_0[7]; 8538 u8 valid; 8539 }; 8540 8541 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 8542 struct hwrm_nvm_mod_dir_entry_input { 8543 __le16 req_type; 8544 __le16 cmpl_ring; 8545 __le16 seq_id; 8546 __le16 target_id; 8547 __le64 resp_addr; 8548 __le32 enables; 8549 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 8550 __le16 dir_idx; 8551 __le16 dir_ordinal; 8552 __le16 dir_ext; 8553 __le16 dir_attr; 8554 __le32 checksum; 8555 }; 8556 8557 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 8558 struct hwrm_nvm_mod_dir_entry_output { 8559 __le16 error_code; 8560 __le16 req_type; 8561 __le16 seq_id; 8562 __le16 resp_len; 8563 u8 unused_0[7]; 8564 u8 valid; 8565 }; 8566 8567 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 8568 struct hwrm_nvm_verify_update_input { 8569 __le16 req_type; 8570 __le16 cmpl_ring; 8571 __le16 seq_id; 8572 __le16 target_id; 8573 __le64 resp_addr; 8574 __le16 dir_type; 8575 __le16 dir_ordinal; 8576 __le16 dir_ext; 8577 u8 unused_0[2]; 8578 }; 8579 8580 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 8581 struct hwrm_nvm_verify_update_output { 8582 __le16 error_code; 8583 __le16 req_type; 8584 __le16 seq_id; 8585 __le16 resp_len; 8586 u8 unused_0[7]; 8587 u8 valid; 8588 }; 8589 8590 /* hwrm_nvm_install_update_input (size:192b/24B) */ 8591 struct hwrm_nvm_install_update_input { 8592 __le16 req_type; 8593 __le16 cmpl_ring; 8594 __le16 seq_id; 8595 __le16 target_id; 8596 __le64 resp_addr; 8597 __le32 install_type; 8598 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 8599 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 8600 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 8601 __le16 flags; 8602 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 8603 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 8604 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 8605 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 8606 u8 unused_0[2]; 8607 }; 8608 8609 /* hwrm_nvm_install_update_output (size:192b/24B) */ 8610 struct hwrm_nvm_install_update_output { 8611 __le16 error_code; 8612 __le16 req_type; 8613 __le16 seq_id; 8614 __le16 resp_len; 8615 __le64 installed_items; 8616 u8 result; 8617 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 8618 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 8619 u8 problem_item; 8620 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 8621 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 8622 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 8623 u8 reset_required; 8624 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 8625 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 8626 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 8627 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 8628 u8 unused_0[4]; 8629 u8 valid; 8630 }; 8631 8632 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 8633 struct hwrm_nvm_install_update_cmd_err { 8634 u8 code; 8635 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 8636 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8637 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 8638 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 8639 u8 unused_0[7]; 8640 }; 8641 8642 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 8643 struct hwrm_nvm_get_variable_input { 8644 __le16 req_type; 8645 __le16 cmpl_ring; 8646 __le16 seq_id; 8647 __le16 target_id; 8648 __le64 resp_addr; 8649 __le64 dest_data_addr; 8650 __le16 data_len; 8651 __le16 option_num; 8652 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8653 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8654 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8655 __le16 dimensions; 8656 __le16 index_0; 8657 __le16 index_1; 8658 __le16 index_2; 8659 __le16 index_3; 8660 u8 flags; 8661 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 8662 u8 unused_0; 8663 }; 8664 8665 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 8666 struct hwrm_nvm_get_variable_output { 8667 __le16 error_code; 8668 __le16 req_type; 8669 __le16 seq_id; 8670 __le16 resp_len; 8671 __le16 data_len; 8672 __le16 option_num; 8673 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 8674 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 8675 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 8676 u8 unused_0[3]; 8677 u8 valid; 8678 }; 8679 8680 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8681 struct hwrm_nvm_get_variable_cmd_err { 8682 u8 code; 8683 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8684 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8685 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8686 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8687 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8688 u8 unused_0[7]; 8689 }; 8690 8691 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8692 struct hwrm_nvm_set_variable_input { 8693 __le16 req_type; 8694 __le16 cmpl_ring; 8695 __le16 seq_id; 8696 __le16 target_id; 8697 __le64 resp_addr; 8698 __le64 src_data_addr; 8699 __le16 data_len; 8700 __le16 option_num; 8701 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8702 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8703 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8704 __le16 dimensions; 8705 __le16 index_0; 8706 __le16 index_1; 8707 __le16 index_2; 8708 __le16 index_3; 8709 u8 flags; 8710 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8711 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8712 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8713 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8714 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 8715 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 8716 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 8717 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 8718 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 8719 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 8720 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8721 u8 unused_0; 8722 }; 8723 8724 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8725 struct hwrm_nvm_set_variable_output { 8726 __le16 error_code; 8727 __le16 req_type; 8728 __le16 seq_id; 8729 __le16 resp_len; 8730 u8 unused_0[7]; 8731 u8 valid; 8732 }; 8733 8734 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8735 struct hwrm_nvm_set_variable_cmd_err { 8736 u8 code; 8737 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8738 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8739 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8740 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8741 u8 unused_0[7]; 8742 }; 8743 8744 /* hwrm_selftest_qlist_input (size:128b/16B) */ 8745 struct hwrm_selftest_qlist_input { 8746 __le16 req_type; 8747 __le16 cmpl_ring; 8748 __le16 seq_id; 8749 __le16 target_id; 8750 __le64 resp_addr; 8751 }; 8752 8753 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8754 struct hwrm_selftest_qlist_output { 8755 __le16 error_code; 8756 __le16 req_type; 8757 __le16 seq_id; 8758 __le16 resp_len; 8759 u8 num_tests; 8760 u8 available_tests; 8761 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8762 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8763 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8764 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8765 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8766 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8767 u8 offline_tests; 8768 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8769 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8770 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8771 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8772 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8773 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8774 u8 unused_0; 8775 __le16 test_timeout; 8776 u8 unused_1[2]; 8777 char test0_name[32]; 8778 char test1_name[32]; 8779 char test2_name[32]; 8780 char test3_name[32]; 8781 char test4_name[32]; 8782 char test5_name[32]; 8783 char test6_name[32]; 8784 char test7_name[32]; 8785 u8 eyescope_target_BER_support; 8786 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 8787 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 8788 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 8789 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 8790 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 8791 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 8792 u8 unused_2[6]; 8793 u8 valid; 8794 }; 8795 8796 /* hwrm_selftest_exec_input (size:192b/24B) */ 8797 struct hwrm_selftest_exec_input { 8798 __le16 req_type; 8799 __le16 cmpl_ring; 8800 __le16 seq_id; 8801 __le16 target_id; 8802 __le64 resp_addr; 8803 u8 flags; 8804 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8805 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8806 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8807 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8808 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8809 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8810 u8 unused_0[7]; 8811 }; 8812 8813 /* hwrm_selftest_exec_output (size:128b/16B) */ 8814 struct hwrm_selftest_exec_output { 8815 __le16 error_code; 8816 __le16 req_type; 8817 __le16 seq_id; 8818 __le16 resp_len; 8819 u8 requested_tests; 8820 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8821 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8822 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8823 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8824 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8825 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8826 u8 test_success; 8827 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8828 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8829 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8830 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8831 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8832 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8833 u8 unused_0[5]; 8834 u8 valid; 8835 }; 8836 8837 /* hwrm_selftest_irq_input (size:128b/16B) */ 8838 struct hwrm_selftest_irq_input { 8839 __le16 req_type; 8840 __le16 cmpl_ring; 8841 __le16 seq_id; 8842 __le16 target_id; 8843 __le64 resp_addr; 8844 }; 8845 8846 /* hwrm_selftest_irq_output (size:128b/16B) */ 8847 struct hwrm_selftest_irq_output { 8848 __le16 error_code; 8849 __le16 req_type; 8850 __le16 seq_id; 8851 __le16 resp_len; 8852 u8 unused_0[7]; 8853 u8 valid; 8854 }; 8855 8856 /* db_push_info (size:64b/8B) */ 8857 struct db_push_info { 8858 u32 push_size_push_index; 8859 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 8860 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 8861 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 8862 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 8863 u32 reserved32; 8864 }; 8865 8866 /* fw_status_reg (size:32b/4B) */ 8867 struct fw_status_reg { 8868 u32 fw_status; 8869 #define FW_STATUS_REG_CODE_MASK 0xffffUL 8870 #define FW_STATUS_REG_CODE_SFT 0 8871 #define FW_STATUS_REG_CODE_READY 0x8000UL 8872 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8873 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8874 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8875 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8876 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8877 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8878 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 8879 }; 8880 8881 /* hcomm_status (size:64b/8B) */ 8882 struct hcomm_status { 8883 u32 sig_ver; 8884 #define HCOMM_STATUS_VER_MASK 0xffUL 8885 #define HCOMM_STATUS_VER_SFT 0 8886 #define HCOMM_STATUS_VER_LATEST 0x1UL 8887 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 8888 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 8889 #define HCOMM_STATUS_SIGNATURE_SFT 8 8890 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 8891 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 8892 u32 fw_status_loc; 8893 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 8894 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 8895 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 8896 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 8897 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 8898 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 8899 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 8900 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 8901 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 8902 }; 8903 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 8904 8905 #endif /* _BNXT_HSI_H_ */ 8906