1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_HSI_H 12 #define BNXT_HSI_H 13 14 /* HSI and HWRM Specification 1.8.3 */ 15 #define HWRM_VERSION_MAJOR 1 16 #define HWRM_VERSION_MINOR 8 17 #define HWRM_VERSION_UPDATE 3 18 19 #define HWRM_VERSION_RSVD 1 /* non-zero means beta version */ 20 21 #define HWRM_VERSION_STR "1.8.3.1" 22 /* 23 * Following is the signature for HWRM message field that indicates not 24 * applicable (All F's). Need to cast it the size of the field if needed. 25 */ 26 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 27 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 28 #define HWRM_MAX_RESP_LEN (280) /* hwrm_selftest_qlist */ 29 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 30 #define HW_HASH_KEY_SIZE 40 31 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 32 33 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 34 struct eject_cmpl { 35 __le16 type; 36 #define EJECT_CMPL_TYPE_MASK 0x3fUL 37 #define EJECT_CMPL_TYPE_SFT 0 38 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 39 __le16 len; 40 __le32 opaque; 41 __le32 v; 42 #define EJECT_CMPL_V 0x1UL 43 __le32 unused_2; 44 }; 45 46 /* HWRM Completion Record (16 bytes) */ 47 struct hwrm_cmpl { 48 __le16 type; 49 #define CMPL_TYPE_MASK 0x3fUL 50 #define CMPL_TYPE_SFT 0 51 #define CMPL_TYPE_HWRM_DONE 0x20UL 52 __le16 sequence_id; 53 __le32 unused_1; 54 __le32 v; 55 #define CMPL_V 0x1UL 56 __le32 unused_3; 57 }; 58 59 /* HWRM Forwarded Request (16 bytes) */ 60 struct hwrm_fwd_req_cmpl { 61 __le16 req_len_type; 62 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 63 #define FWD_REQ_CMPL_TYPE_SFT 0 64 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 65 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 66 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 67 __le16 source_id; 68 __le32 unused_0; 69 __le32 req_buf_addr_v[2]; 70 #define FWD_REQ_CMPL_V 0x1UL 71 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 72 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 73 }; 74 75 /* HWRM Forwarded Response (16 bytes) */ 76 struct hwrm_fwd_resp_cmpl { 77 __le16 type; 78 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 79 #define FWD_RESP_CMPL_TYPE_SFT 0 80 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 81 __le16 source_id; 82 __le16 resp_len; 83 __le16 unused_1; 84 __le32 resp_buf_addr_v[2]; 85 #define FWD_RESP_CMPL_V 0x1UL 86 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 87 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 88 }; 89 90 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 91 struct hwrm_async_event_cmpl { 92 __le16 type; 93 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 94 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 95 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 96 __le16 event_id; 97 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 98 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 99 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 100 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 101 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 102 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 103 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 104 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 105 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 106 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 107 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 108 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 109 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 110 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 111 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 112 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 113 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 114 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 115 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 116 __le32 event_data2; 117 u8 opaque_v; 118 #define ASYNC_EVENT_CMPL_V 0x1UL 119 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 120 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 121 u8 timestamp_lo; 122 __le16 timestamp_hi; 123 __le32 event_data1; 124 }; 125 126 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 127 struct hwrm_async_event_cmpl_link_status_change { 128 __le16 type; 129 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 130 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 131 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 132 __le16 event_id; 133 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 134 __le32 event_data2; 135 u8 opaque_v; 136 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 137 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 138 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 139 u8 timestamp_lo; 140 __le16 timestamp_hi; 141 __le32 event_data1; 142 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 143 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 144 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 145 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 146 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 147 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 148 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 149 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 150 }; 151 152 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 153 struct hwrm_async_event_cmpl_link_mtu_change { 154 __le16 type; 155 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 156 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 157 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 158 __le16 event_id; 159 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 160 __le32 event_data2; 161 u8 opaque_v; 162 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 163 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 164 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 165 u8 timestamp_lo; 166 __le16 timestamp_hi; 167 __le32 event_data1; 168 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 169 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 170 }; 171 172 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 173 struct hwrm_async_event_cmpl_link_speed_change { 174 __le16 type; 175 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 176 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 177 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 178 __le16 event_id; 179 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 180 __le32 event_data2; 181 u8 opaque_v; 182 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 183 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 184 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 185 u8 timestamp_lo; 186 __le16 timestamp_hi; 187 __le32 event_data1; 188 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 189 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 190 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 191 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 192 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 193 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 194 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 195 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 196 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 197 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 198 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 199 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 200 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 201 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 202 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 203 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 204 }; 205 206 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 207 struct hwrm_async_event_cmpl_dcb_config_change { 208 __le16 type; 209 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 210 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 211 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 212 __le16 event_id; 213 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 214 __le32 event_data2; 215 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 216 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 217 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 218 u8 opaque_v; 219 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 220 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 221 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 222 u8 timestamp_lo; 223 __le16 timestamp_hi; 224 __le32 event_data1; 225 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 226 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 227 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 228 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 229 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 230 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 231 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 232 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 233 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 234 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 235 }; 236 237 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 238 struct hwrm_async_event_cmpl_port_conn_not_allowed { 239 __le16 type; 240 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 241 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 242 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 243 __le16 event_id; 244 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 245 __le32 event_data2; 246 u8 opaque_v; 247 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 248 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 249 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 250 u8 timestamp_lo; 251 __le16 timestamp_hi; 252 __le32 event_data1; 253 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 254 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 255 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 256 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 257 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 258 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 259 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 260 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 261 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 262 }; 263 264 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 265 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 266 __le16 type; 267 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 268 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 269 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 270 __le16 event_id; 271 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 272 __le32 event_data2; 273 u8 opaque_v; 274 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 275 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 276 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 277 u8 timestamp_lo; 278 __le16 timestamp_hi; 279 __le32 event_data1; 280 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 281 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 282 }; 283 284 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 285 struct hwrm_async_event_cmpl_link_speed_cfg_change { 286 __le16 type; 287 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 288 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 289 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 290 __le16 event_id; 291 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 292 __le32 event_data2; 293 u8 opaque_v; 294 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 295 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 296 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 297 u8 timestamp_lo; 298 __le16 timestamp_hi; 299 __le32 event_data1; 300 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 301 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 302 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 303 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 304 }; 305 306 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 307 struct hwrm_async_event_cmpl_func_drvr_unload { 308 __le16 type; 309 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 310 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 311 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 312 __le16 event_id; 313 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 314 __le32 event_data2; 315 u8 opaque_v; 316 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 317 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 318 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 319 u8 timestamp_lo; 320 __le16 timestamp_hi; 321 __le32 event_data1; 322 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 323 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 324 }; 325 326 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 327 struct hwrm_async_event_cmpl_func_drvr_load { 328 __le16 type; 329 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 330 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 331 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 332 __le16 event_id; 333 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 334 __le32 event_data2; 335 u8 opaque_v; 336 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 337 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 338 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 339 u8 timestamp_lo; 340 __le16 timestamp_hi; 341 __le32 event_data1; 342 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 343 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 344 }; 345 346 /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ 347 struct hwrm_async_event_cmpl_func_flr_proc_cmplt { 348 __le16 type; 349 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL 350 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 351 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 352 __le16 event_id; 353 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 354 __le32 event_data2; 355 u8 opaque_v; 356 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL 357 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL 358 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 359 u8 timestamp_lo; 360 __le16 timestamp_hi; 361 __le32 event_data1; 362 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 363 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 364 }; 365 366 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 367 struct hwrm_async_event_cmpl_pf_drvr_unload { 368 __le16 type; 369 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 370 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 371 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 372 __le16 event_id; 373 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 374 __le32 event_data2; 375 u8 opaque_v; 376 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 377 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 378 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 379 u8 timestamp_lo; 380 __le16 timestamp_hi; 381 __le32 event_data1; 382 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 383 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 384 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 385 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 386 }; 387 388 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 389 struct hwrm_async_event_cmpl_pf_drvr_load { 390 __le16 type; 391 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 392 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 393 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 394 __le16 event_id; 395 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 396 __le32 event_data2; 397 u8 opaque_v; 398 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 399 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 400 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 401 u8 timestamp_lo; 402 __le16 timestamp_hi; 403 __le32 event_data1; 404 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 405 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 406 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 407 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 408 }; 409 410 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 411 struct hwrm_async_event_cmpl_vf_flr { 412 __le16 type; 413 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 414 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 415 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 416 __le16 event_id; 417 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 418 __le32 event_data2; 419 u8 opaque_v; 420 #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 421 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 422 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 423 u8 timestamp_lo; 424 __le16 timestamp_hi; 425 __le32 event_data1; 426 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 427 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 428 }; 429 430 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 431 struct hwrm_async_event_cmpl_vf_mac_addr_change { 432 __le16 type; 433 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 434 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 435 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 436 __le16 event_id; 437 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 438 __le32 event_data2; 439 u8 opaque_v; 440 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 441 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 442 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 443 u8 timestamp_lo; 444 __le16 timestamp_hi; 445 __le32 event_data1; 446 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 447 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 448 }; 449 450 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 451 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 452 __le16 type; 453 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 454 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 455 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 456 __le16 event_id; 457 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 458 __le32 event_data2; 459 u8 opaque_v; 460 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 461 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 462 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 463 u8 timestamp_lo; 464 __le16 timestamp_hi; 465 __le32 event_data1; 466 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 467 }; 468 469 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 470 struct hwrm_async_event_cmpl_vf_cfg_change { 471 __le16 type; 472 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 473 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 474 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 475 __le16 event_id; 476 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 477 __le32 event_data2; 478 u8 opaque_v; 479 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 480 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 481 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 482 u8 timestamp_lo; 483 __le16 timestamp_hi; 484 __le32 event_data1; 485 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 486 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 487 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 488 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 489 }; 490 491 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 492 struct hwrm_async_event_cmpl_hwrm_error { 493 __le16 type; 494 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 495 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 496 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 497 __le16 event_id; 498 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 499 __le32 event_data2; 500 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 501 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 502 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 503 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 504 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 505 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 506 u8 opaque_v; 507 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 508 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 509 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 510 u8 timestamp_lo; 511 __le16 timestamp_hi; 512 __le32 event_data1; 513 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 514 }; 515 516 /* hwrm_ver_get */ 517 /* Input (24 bytes) */ 518 struct hwrm_ver_get_input { 519 __le16 req_type; 520 __le16 cmpl_ring; 521 __le16 seq_id; 522 __le16 target_id; 523 __le64 resp_addr; 524 u8 hwrm_intf_maj; 525 u8 hwrm_intf_min; 526 u8 hwrm_intf_upd; 527 u8 unused_0[5]; 528 }; 529 530 /* Output (128 bytes) */ 531 struct hwrm_ver_get_output { 532 __le16 error_code; 533 __le16 req_type; 534 __le16 seq_id; 535 __le16 resp_len; 536 u8 hwrm_intf_maj; 537 u8 hwrm_intf_min; 538 u8 hwrm_intf_upd; 539 u8 hwrm_intf_rsvd; 540 u8 hwrm_fw_maj; 541 u8 hwrm_fw_min; 542 u8 hwrm_fw_bld; 543 u8 hwrm_fw_rsvd; 544 u8 mgmt_fw_maj; 545 u8 mgmt_fw_min; 546 u8 mgmt_fw_bld; 547 u8 mgmt_fw_rsvd; 548 u8 netctrl_fw_maj; 549 u8 netctrl_fw_min; 550 u8 netctrl_fw_bld; 551 u8 netctrl_fw_rsvd; 552 __le32 dev_caps_cfg; 553 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 554 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 555 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 556 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 557 u8 roce_fw_maj; 558 u8 roce_fw_min; 559 u8 roce_fw_bld; 560 u8 roce_fw_rsvd; 561 char hwrm_fw_name[16]; 562 char mgmt_fw_name[16]; 563 char netctrl_fw_name[16]; 564 __le32 reserved2[4]; 565 char roce_fw_name[16]; 566 __le16 chip_num; 567 u8 chip_rev; 568 u8 chip_metal; 569 u8 chip_bond_id; 570 u8 chip_platform_type; 571 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 572 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 573 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 574 __le16 max_req_win_len; 575 __le16 max_resp_len; 576 __le16 def_req_timeout; 577 u8 init_pending; 578 #define VER_GET_RESP_INIT_PENDING_DEV_NOT_RDY 0x1UL 579 u8 unused_0; 580 u8 unused_1; 581 u8 valid; 582 }; 583 584 /* hwrm_func_reset */ 585 /* Input (24 bytes) */ 586 struct hwrm_func_reset_input { 587 __le16 req_type; 588 __le16 cmpl_ring; 589 __le16 seq_id; 590 __le16 target_id; 591 __le64 resp_addr; 592 __le32 enables; 593 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 594 __le16 vf_id; 595 u8 func_reset_level; 596 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 597 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 598 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 599 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 600 u8 unused_0; 601 }; 602 603 /* Output (16 bytes) */ 604 struct hwrm_func_reset_output { 605 __le16 error_code; 606 __le16 req_type; 607 __le16 seq_id; 608 __le16 resp_len; 609 __le32 unused_0; 610 u8 unused_1; 611 u8 unused_2; 612 u8 unused_3; 613 u8 valid; 614 }; 615 616 /* hwrm_func_getfid */ 617 /* Input (24 bytes) */ 618 struct hwrm_func_getfid_input { 619 __le16 req_type; 620 __le16 cmpl_ring; 621 __le16 seq_id; 622 __le16 target_id; 623 __le64 resp_addr; 624 __le32 enables; 625 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 626 __le16 pci_id; 627 __le16 unused_0; 628 }; 629 630 /* Output (16 bytes) */ 631 struct hwrm_func_getfid_output { 632 __le16 error_code; 633 __le16 req_type; 634 __le16 seq_id; 635 __le16 resp_len; 636 __le16 fid; 637 u8 unused_0; 638 u8 unused_1; 639 u8 unused_2; 640 u8 unused_3; 641 u8 unused_4; 642 u8 valid; 643 }; 644 645 /* hwrm_func_vf_alloc */ 646 /* Input (24 bytes) */ 647 struct hwrm_func_vf_alloc_input { 648 __le16 req_type; 649 __le16 cmpl_ring; 650 __le16 seq_id; 651 __le16 target_id; 652 __le64 resp_addr; 653 __le32 enables; 654 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 655 __le16 first_vf_id; 656 __le16 num_vfs; 657 }; 658 659 /* Output (16 bytes) */ 660 struct hwrm_func_vf_alloc_output { 661 __le16 error_code; 662 __le16 req_type; 663 __le16 seq_id; 664 __le16 resp_len; 665 __le16 first_vf_id; 666 u8 unused_0; 667 u8 unused_1; 668 u8 unused_2; 669 u8 unused_3; 670 u8 unused_4; 671 u8 valid; 672 }; 673 674 /* hwrm_func_vf_free */ 675 /* Input (24 bytes) */ 676 struct hwrm_func_vf_free_input { 677 __le16 req_type; 678 __le16 cmpl_ring; 679 __le16 seq_id; 680 __le16 target_id; 681 __le64 resp_addr; 682 __le32 enables; 683 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 684 __le16 first_vf_id; 685 __le16 num_vfs; 686 }; 687 688 /* Output (16 bytes) */ 689 struct hwrm_func_vf_free_output { 690 __le16 error_code; 691 __le16 req_type; 692 __le16 seq_id; 693 __le16 resp_len; 694 __le32 unused_0; 695 u8 unused_1; 696 u8 unused_2; 697 u8 unused_3; 698 u8 valid; 699 }; 700 701 /* hwrm_func_vf_cfg */ 702 /* Input (32 bytes) */ 703 struct hwrm_func_vf_cfg_input { 704 __le16 req_type; 705 __le16 cmpl_ring; 706 __le16 seq_id; 707 __le16 target_id; 708 __le64 resp_addr; 709 __le32 enables; 710 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 711 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 712 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 713 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 714 __le16 mtu; 715 __le16 guest_vlan; 716 __le16 async_event_cr; 717 u8 dflt_mac_addr[6]; 718 }; 719 720 /* Output (16 bytes) */ 721 struct hwrm_func_vf_cfg_output { 722 __le16 error_code; 723 __le16 req_type; 724 __le16 seq_id; 725 __le16 resp_len; 726 __le32 unused_0; 727 u8 unused_1; 728 u8 unused_2; 729 u8 unused_3; 730 u8 valid; 731 }; 732 733 /* hwrm_func_qcaps */ 734 /* Input (24 bytes) */ 735 struct hwrm_func_qcaps_input { 736 __le16 req_type; 737 __le16 cmpl_ring; 738 __le16 seq_id; 739 __le16 target_id; 740 __le64 resp_addr; 741 __le16 fid; 742 __le16 unused_0[3]; 743 }; 744 745 /* Output (80 bytes) */ 746 struct hwrm_func_qcaps_output { 747 __le16 error_code; 748 __le16 req_type; 749 __le16 seq_id; 750 __le16 resp_len; 751 __le16 fid; 752 __le16 port_id; 753 __le32 flags; 754 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 755 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 756 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 757 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 758 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 759 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 760 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 761 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 762 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 763 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 764 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 765 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 766 u8 mac_address[6]; 767 __le16 max_rsscos_ctx; 768 __le16 max_cmpl_rings; 769 __le16 max_tx_rings; 770 __le16 max_rx_rings; 771 __le16 max_l2_ctxs; 772 __le16 max_vnics; 773 __le16 first_vf_id; 774 __le16 max_vfs; 775 __le16 max_stat_ctx; 776 __le32 max_encap_records; 777 __le32 max_decap_records; 778 __le32 max_tx_em_flows; 779 __le32 max_tx_wm_flows; 780 __le32 max_rx_em_flows; 781 __le32 max_rx_wm_flows; 782 __le32 max_mcast_filters; 783 __le32 max_flow_id; 784 __le32 max_hw_ring_grps; 785 __le16 max_sp_tx_rings; 786 u8 unused_0; 787 u8 valid; 788 }; 789 790 /* hwrm_func_qcfg */ 791 /* Input (24 bytes) */ 792 struct hwrm_func_qcfg_input { 793 __le16 req_type; 794 __le16 cmpl_ring; 795 __le16 seq_id; 796 __le16 target_id; 797 __le64 resp_addr; 798 __le16 fid; 799 __le16 unused_0[3]; 800 }; 801 802 /* Output (72 bytes) */ 803 struct hwrm_func_qcfg_output { 804 __le16 error_code; 805 __le16 req_type; 806 __le16 seq_id; 807 __le16 resp_len; 808 __le16 fid; 809 __le16 port_id; 810 __le16 vlan; 811 __le16 flags; 812 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 813 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 814 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 815 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 816 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 817 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 818 u8 mac_address[6]; 819 __le16 pci_id; 820 __le16 alloc_rsscos_ctx; 821 __le16 alloc_cmpl_rings; 822 __le16 alloc_tx_rings; 823 __le16 alloc_rx_rings; 824 __le16 alloc_l2_ctx; 825 __le16 alloc_vnics; 826 __le16 mtu; 827 __le16 mru; 828 __le16 stat_ctx_id; 829 u8 port_partition_type; 830 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 831 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 832 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 833 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 834 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 835 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 836 u8 port_pf_cnt; 837 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 838 __le16 dflt_vnic_id; 839 __le16 max_mtu_configured; 840 __le32 min_bw; 841 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 842 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 843 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 844 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 845 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 846 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 847 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 848 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 849 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 850 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 851 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 852 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 853 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 854 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 855 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 856 __le32 max_bw; 857 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 858 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 859 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 860 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 861 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 862 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 863 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 864 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 865 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 866 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 867 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 868 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 869 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 870 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 871 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 872 u8 evb_mode; 873 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 874 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 875 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 876 u8 unused_0; 877 __le16 alloc_vfs; 878 __le32 alloc_mcast_filters; 879 __le32 alloc_hw_ring_grps; 880 __le16 alloc_sp_tx_rings; 881 u8 unused_1; 882 u8 valid; 883 }; 884 885 /* hwrm_func_vlan_cfg */ 886 /* Input (48 bytes) */ 887 struct hwrm_func_vlan_cfg_input { 888 __le16 req_type; 889 __le16 cmpl_ring; 890 __le16 seq_id; 891 __le16 target_id; 892 __le64 resp_addr; 893 __le16 fid; 894 u8 unused_0; 895 u8 unused_1; 896 __le32 enables; 897 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL 898 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL 899 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL 900 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL 901 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL 902 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL 903 __le16 stag_vid; 904 u8 stag_pcp; 905 u8 unused_2; 906 __be16 stag_tpid; 907 __le16 ctag_vid; 908 u8 ctag_pcp; 909 u8 unused_3; 910 __be16 ctag_tpid; 911 __le32 rsvd1; 912 __le32 rsvd2; 913 __le32 unused_4; 914 }; 915 916 /* Output (16 bytes) */ 917 struct hwrm_func_vlan_cfg_output { 918 __le16 error_code; 919 __le16 req_type; 920 __le16 seq_id; 921 __le16 resp_len; 922 __le32 unused_0; 923 u8 unused_1; 924 u8 unused_2; 925 u8 unused_3; 926 u8 valid; 927 }; 928 929 /* hwrm_func_cfg */ 930 /* Input (88 bytes) */ 931 struct hwrm_func_cfg_input { 932 __le16 req_type; 933 __le16 cmpl_ring; 934 __le16 seq_id; 935 __le16 target_id; 936 __le64 resp_addr; 937 __le16 fid; 938 u8 unused_0; 939 u8 unused_1; 940 __le32 flags; 941 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 942 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 943 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 944 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 945 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 946 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 947 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 948 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 949 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 950 __le32 enables; 951 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 952 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 953 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 954 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 955 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 956 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 957 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 958 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 959 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 960 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 961 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 962 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 963 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 964 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 965 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 966 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 967 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 968 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 969 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 970 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 971 __le16 mtu; 972 __le16 mru; 973 __le16 num_rsscos_ctxs; 974 __le16 num_cmpl_rings; 975 __le16 num_tx_rings; 976 __le16 num_rx_rings; 977 __le16 num_l2_ctxs; 978 __le16 num_vnics; 979 __le16 num_stat_ctxs; 980 __le16 num_hw_ring_grps; 981 u8 dflt_mac_addr[6]; 982 __le16 dflt_vlan; 983 __be32 dflt_ip_addr[4]; 984 __le32 min_bw; 985 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 986 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 987 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 988 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 989 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 990 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 991 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 992 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 993 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 994 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 995 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 996 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 997 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 998 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 999 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1000 __le32 max_bw; 1001 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1002 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1003 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1004 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1005 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1006 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1007 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1008 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1009 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1010 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1011 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1012 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1013 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1014 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1015 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1016 __le16 async_event_cr; 1017 u8 vlan_antispoof_mode; 1018 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1019 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1020 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1021 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1022 u8 allowed_vlan_pris; 1023 u8 evb_mode; 1024 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1025 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1026 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1027 u8 unused_2; 1028 __le16 num_mcast_filters; 1029 }; 1030 1031 /* Output (16 bytes) */ 1032 struct hwrm_func_cfg_output { 1033 __le16 error_code; 1034 __le16 req_type; 1035 __le16 seq_id; 1036 __le16 resp_len; 1037 __le32 unused_0; 1038 u8 unused_1; 1039 u8 unused_2; 1040 u8 unused_3; 1041 u8 valid; 1042 }; 1043 1044 /* hwrm_func_qstats */ 1045 /* Input (24 bytes) */ 1046 struct hwrm_func_qstats_input { 1047 __le16 req_type; 1048 __le16 cmpl_ring; 1049 __le16 seq_id; 1050 __le16 target_id; 1051 __le64 resp_addr; 1052 __le16 fid; 1053 __le16 unused_0[3]; 1054 }; 1055 1056 /* Output (176 bytes) */ 1057 struct hwrm_func_qstats_output { 1058 __le16 error_code; 1059 __le16 req_type; 1060 __le16 seq_id; 1061 __le16 resp_len; 1062 __le64 tx_ucast_pkts; 1063 __le64 tx_mcast_pkts; 1064 __le64 tx_bcast_pkts; 1065 __le64 tx_discard_pkts; 1066 __le64 tx_drop_pkts; 1067 __le64 tx_ucast_bytes; 1068 __le64 tx_mcast_bytes; 1069 __le64 tx_bcast_bytes; 1070 __le64 rx_ucast_pkts; 1071 __le64 rx_mcast_pkts; 1072 __le64 rx_bcast_pkts; 1073 __le64 rx_discard_pkts; 1074 __le64 rx_drop_pkts; 1075 __le64 rx_ucast_bytes; 1076 __le64 rx_mcast_bytes; 1077 __le64 rx_bcast_bytes; 1078 __le64 rx_agg_pkts; 1079 __le64 rx_agg_bytes; 1080 __le64 rx_agg_events; 1081 __le64 rx_agg_aborts; 1082 __le32 unused_0; 1083 u8 unused_1; 1084 u8 unused_2; 1085 u8 unused_3; 1086 u8 valid; 1087 }; 1088 1089 /* hwrm_func_clr_stats */ 1090 /* Input (24 bytes) */ 1091 struct hwrm_func_clr_stats_input { 1092 __le16 req_type; 1093 __le16 cmpl_ring; 1094 __le16 seq_id; 1095 __le16 target_id; 1096 __le64 resp_addr; 1097 __le16 fid; 1098 __le16 unused_0[3]; 1099 }; 1100 1101 /* Output (16 bytes) */ 1102 struct hwrm_func_clr_stats_output { 1103 __le16 error_code; 1104 __le16 req_type; 1105 __le16 seq_id; 1106 __le16 resp_len; 1107 __le32 unused_0; 1108 u8 unused_1; 1109 u8 unused_2; 1110 u8 unused_3; 1111 u8 valid; 1112 }; 1113 1114 /* hwrm_func_vf_resc_free */ 1115 /* Input (24 bytes) */ 1116 struct hwrm_func_vf_resc_free_input { 1117 __le16 req_type; 1118 __le16 cmpl_ring; 1119 __le16 seq_id; 1120 __le16 target_id; 1121 __le64 resp_addr; 1122 __le16 vf_id; 1123 __le16 unused_0[3]; 1124 }; 1125 1126 /* Output (16 bytes) */ 1127 struct hwrm_func_vf_resc_free_output { 1128 __le16 error_code; 1129 __le16 req_type; 1130 __le16 seq_id; 1131 __le16 resp_len; 1132 __le32 unused_0; 1133 u8 unused_1; 1134 u8 unused_2; 1135 u8 unused_3; 1136 u8 valid; 1137 }; 1138 1139 /* hwrm_func_vf_vnic_ids_query */ 1140 /* Input (32 bytes) */ 1141 struct hwrm_func_vf_vnic_ids_query_input { 1142 __le16 req_type; 1143 __le16 cmpl_ring; 1144 __le16 seq_id; 1145 __le16 target_id; 1146 __le64 resp_addr; 1147 __le16 vf_id; 1148 u8 unused_0; 1149 u8 unused_1; 1150 __le32 max_vnic_id_cnt; 1151 __le64 vnic_id_tbl_addr; 1152 }; 1153 1154 /* Output (16 bytes) */ 1155 struct hwrm_func_vf_vnic_ids_query_output { 1156 __le16 error_code; 1157 __le16 req_type; 1158 __le16 seq_id; 1159 __le16 resp_len; 1160 __le32 vnic_id_cnt; 1161 u8 unused_0; 1162 u8 unused_1; 1163 u8 unused_2; 1164 u8 valid; 1165 }; 1166 1167 /* hwrm_func_drv_rgtr */ 1168 /* Input (80 bytes) */ 1169 struct hwrm_func_drv_rgtr_input { 1170 __le16 req_type; 1171 __le16 cmpl_ring; 1172 __le16 seq_id; 1173 __le16 target_id; 1174 __le64 resp_addr; 1175 __le32 flags; 1176 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1177 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1178 __le32 enables; 1179 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1180 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1181 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1182 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1183 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1184 __le16 os_type; 1185 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1186 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1187 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1188 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1189 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1190 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1191 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1192 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1193 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1194 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1195 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1196 u8 ver_maj; 1197 u8 ver_min; 1198 u8 ver_upd; 1199 u8 unused_0; 1200 __le16 unused_1; 1201 __le32 timestamp; 1202 __le32 unused_2; 1203 __le32 vf_req_fwd[8]; 1204 __le32 async_event_fwd[8]; 1205 }; 1206 1207 /* Output (16 bytes) */ 1208 struct hwrm_func_drv_rgtr_output { 1209 __le16 error_code; 1210 __le16 req_type; 1211 __le16 seq_id; 1212 __le16 resp_len; 1213 __le32 unused_0; 1214 u8 unused_1; 1215 u8 unused_2; 1216 u8 unused_3; 1217 u8 valid; 1218 }; 1219 1220 /* hwrm_func_drv_unrgtr */ 1221 /* Input (24 bytes) */ 1222 struct hwrm_func_drv_unrgtr_input { 1223 __le16 req_type; 1224 __le16 cmpl_ring; 1225 __le16 seq_id; 1226 __le16 target_id; 1227 __le64 resp_addr; 1228 __le32 flags; 1229 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1230 __le32 unused_0; 1231 }; 1232 1233 /* Output (16 bytes) */ 1234 struct hwrm_func_drv_unrgtr_output { 1235 __le16 error_code; 1236 __le16 req_type; 1237 __le16 seq_id; 1238 __le16 resp_len; 1239 __le32 unused_0; 1240 u8 unused_1; 1241 u8 unused_2; 1242 u8 unused_3; 1243 u8 valid; 1244 }; 1245 1246 /* hwrm_func_buf_rgtr */ 1247 /* Input (128 bytes) */ 1248 struct hwrm_func_buf_rgtr_input { 1249 __le16 req_type; 1250 __le16 cmpl_ring; 1251 __le16 seq_id; 1252 __le16 target_id; 1253 __le64 resp_addr; 1254 __le32 enables; 1255 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1256 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1257 __le16 vf_id; 1258 __le16 req_buf_num_pages; 1259 __le16 req_buf_page_size; 1260 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1261 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1262 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1263 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1264 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1265 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1266 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1267 __le16 req_buf_len; 1268 __le16 resp_buf_len; 1269 u8 unused_0; 1270 u8 unused_1; 1271 __le64 req_buf_page_addr0; 1272 __le64 req_buf_page_addr1; 1273 __le64 req_buf_page_addr2; 1274 __le64 req_buf_page_addr3; 1275 __le64 req_buf_page_addr4; 1276 __le64 req_buf_page_addr5; 1277 __le64 req_buf_page_addr6; 1278 __le64 req_buf_page_addr7; 1279 __le64 req_buf_page_addr8; 1280 __le64 req_buf_page_addr9; 1281 __le64 error_buf_addr; 1282 __le64 resp_buf_addr; 1283 }; 1284 1285 /* Output (16 bytes) */ 1286 struct hwrm_func_buf_rgtr_output { 1287 __le16 error_code; 1288 __le16 req_type; 1289 __le16 seq_id; 1290 __le16 resp_len; 1291 __le32 unused_0; 1292 u8 unused_1; 1293 u8 unused_2; 1294 u8 unused_3; 1295 u8 valid; 1296 }; 1297 1298 /* hwrm_func_drv_qver */ 1299 /* Input (24 bytes) */ 1300 struct hwrm_func_drv_qver_input { 1301 __le16 req_type; 1302 __le16 cmpl_ring; 1303 __le16 seq_id; 1304 __le16 target_id; 1305 __le64 resp_addr; 1306 __le32 reserved; 1307 __le16 fid; 1308 __le16 unused_0; 1309 }; 1310 1311 /* Output (16 bytes) */ 1312 struct hwrm_func_drv_qver_output { 1313 __le16 error_code; 1314 __le16 req_type; 1315 __le16 seq_id; 1316 __le16 resp_len; 1317 __le16 os_type; 1318 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1319 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1320 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1321 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1322 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1323 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1324 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1325 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1326 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1327 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1328 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1329 u8 ver_maj; 1330 u8 ver_min; 1331 u8 ver_upd; 1332 u8 unused_0; 1333 u8 unused_1; 1334 u8 valid; 1335 }; 1336 1337 /* hwrm_port_phy_cfg */ 1338 /* Input (56 bytes) */ 1339 struct hwrm_port_phy_cfg_input { 1340 __le16 req_type; 1341 __le16 cmpl_ring; 1342 __le16 seq_id; 1343 __le16 target_id; 1344 __le64 resp_addr; 1345 __le32 flags; 1346 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1347 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1348 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1349 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1350 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1351 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1352 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1353 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1354 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1355 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1356 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1357 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1358 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1359 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1360 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1361 __le32 enables; 1362 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1363 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1364 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1365 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1366 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1367 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1368 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1369 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1370 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1371 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1372 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1373 __le16 port_id; 1374 __le16 force_link_speed; 1375 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1376 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1377 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1378 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1379 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1380 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1381 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1382 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1383 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1384 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1385 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1386 u8 auto_mode; 1387 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1388 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1389 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1390 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1391 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1392 u8 auto_duplex; 1393 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1394 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1395 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1396 u8 auto_pause; 1397 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1398 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1399 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1400 u8 unused_0; 1401 __le16 auto_link_speed; 1402 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1403 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1404 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1405 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1406 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1407 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1408 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1409 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1410 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1411 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1412 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1413 __le16 auto_link_speed_mask; 1414 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1415 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1416 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1417 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1418 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1419 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1420 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1421 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1422 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1423 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1424 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1425 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1426 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1427 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1428 u8 wirespeed; 1429 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1430 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1431 u8 lpbk; 1432 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1433 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1434 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1435 u8 force_pause; 1436 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1437 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1438 u8 unused_1; 1439 __le32 preemphasis; 1440 __le16 eee_link_speed_mask; 1441 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1442 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1443 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1444 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1445 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1446 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1447 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1448 u8 unused_2; 1449 u8 unused_3; 1450 __le32 tx_lpi_timer; 1451 __le32 unused_4; 1452 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1453 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1454 }; 1455 1456 /* Output (16 bytes) */ 1457 struct hwrm_port_phy_cfg_output { 1458 __le16 error_code; 1459 __le16 req_type; 1460 __le16 seq_id; 1461 __le16 resp_len; 1462 __le32 unused_0; 1463 u8 unused_1; 1464 u8 unused_2; 1465 u8 unused_3; 1466 u8 valid; 1467 }; 1468 1469 /* hwrm_port_phy_qcfg */ 1470 /* Input (24 bytes) */ 1471 struct hwrm_port_phy_qcfg_input { 1472 __le16 req_type; 1473 __le16 cmpl_ring; 1474 __le16 seq_id; 1475 __le16 target_id; 1476 __le64 resp_addr; 1477 __le16 port_id; 1478 __le16 unused_0[3]; 1479 }; 1480 1481 /* Output (96 bytes) */ 1482 struct hwrm_port_phy_qcfg_output { 1483 __le16 error_code; 1484 __le16 req_type; 1485 __le16 seq_id; 1486 __le16 resp_len; 1487 u8 link; 1488 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1489 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1490 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1491 u8 unused_0; 1492 __le16 link_speed; 1493 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1494 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1495 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1496 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1497 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1498 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1499 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1500 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1501 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1502 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1503 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1504 u8 duplex_cfg; 1505 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 1506 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 1507 u8 pause; 1508 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1509 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1510 __le16 support_speeds; 1511 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1512 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1513 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1514 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1515 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1516 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1517 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1518 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1519 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1520 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1521 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1522 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1523 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1524 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1525 __le16 force_link_speed; 1526 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1527 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1528 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1529 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1530 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1531 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1532 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1533 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1534 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1535 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1536 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1537 u8 auto_mode; 1538 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1539 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1540 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1541 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1542 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1543 u8 auto_pause; 1544 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1545 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1546 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1547 __le16 auto_link_speed; 1548 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1549 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1550 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1551 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1552 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1553 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1554 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1555 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1556 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1557 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1558 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1559 __le16 auto_link_speed_mask; 1560 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1561 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1562 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1563 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1564 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1565 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1566 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1567 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1568 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1569 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1570 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1571 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1572 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1573 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1574 u8 wirespeed; 1575 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1576 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1577 u8 lpbk; 1578 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1579 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1580 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1581 u8 force_pause; 1582 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1583 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1584 u8 module_status; 1585 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1586 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1587 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1588 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1589 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1590 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1591 __le32 preemphasis; 1592 u8 phy_maj; 1593 u8 phy_min; 1594 u8 phy_bld; 1595 u8 phy_type; 1596 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1597 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1598 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1599 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1600 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1601 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1602 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1603 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1604 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1605 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1606 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1607 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1608 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1609 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1610 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1611 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1612 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1613 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1614 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1615 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1616 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1617 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1618 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1619 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1620 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1621 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 1622 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 1623 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 1624 u8 media_type; 1625 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1626 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1627 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1628 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1629 u8 xcvr_pkg_type; 1630 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1631 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1632 u8 eee_config_phy_addr; 1633 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1634 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1635 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1636 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1637 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1638 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1639 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1640 u8 parallel_detect; 1641 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1642 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1643 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1644 __le16 link_partner_adv_speeds; 1645 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1646 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1647 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1648 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1649 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1650 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1651 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1652 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1653 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1654 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1655 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1656 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1657 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1658 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1659 u8 link_partner_adv_auto_mode; 1660 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1661 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1662 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1663 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1664 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1665 u8 link_partner_adv_pause; 1666 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1667 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1668 __le16 adv_eee_link_speed_mask; 1669 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1670 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1671 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1672 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1673 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1674 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1675 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1676 __le16 link_partner_adv_eee_link_speed_mask; 1677 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1678 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1679 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1680 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1681 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1682 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1683 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1684 __le32 xcvr_identifier_type_tx_lpi_timer; 1685 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1686 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1687 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1688 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1689 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1690 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1691 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1692 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1693 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1694 __le16 fec_cfg; 1695 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1696 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1697 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1698 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1699 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1700 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1701 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1702 u8 duplex_state; 1703 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 1704 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 1705 u8 unused_1; 1706 char phy_vendor_name[16]; 1707 char phy_vendor_partnumber[16]; 1708 __le32 unused_2; 1709 u8 unused_3; 1710 u8 unused_4; 1711 u8 unused_5; 1712 u8 valid; 1713 }; 1714 1715 /* hwrm_port_mac_cfg */ 1716 /* Input (40 bytes) */ 1717 struct hwrm_port_mac_cfg_input { 1718 __le16 req_type; 1719 __le16 cmpl_ring; 1720 __le16 seq_id; 1721 __le16 target_id; 1722 __le64 resp_addr; 1723 __le32 flags; 1724 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1725 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1726 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1727 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1728 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1729 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1730 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1731 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1732 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1733 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1734 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1735 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1736 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1737 __le32 enables; 1738 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1739 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1740 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1741 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1742 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1743 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1744 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1745 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1746 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1747 __le16 port_id; 1748 u8 ipg; 1749 u8 lpbk; 1750 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1751 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1752 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1753 u8 vlan_pri2cos_map_pri; 1754 u8 reserved1; 1755 u8 tunnel_pri2cos_map_pri; 1756 u8 dscp2pri_map_pri; 1757 __le16 rx_ts_capture_ptp_msg_type; 1758 __le16 tx_ts_capture_ptp_msg_type; 1759 u8 cos_field_cfg; 1760 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1761 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1762 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1763 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1764 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1765 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1766 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1767 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1768 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1769 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1770 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1771 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1772 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1773 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1774 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1775 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1776 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1777 u8 unused_0[3]; 1778 }; 1779 1780 /* Output (16 bytes) */ 1781 struct hwrm_port_mac_cfg_output { 1782 __le16 error_code; 1783 __le16 req_type; 1784 __le16 seq_id; 1785 __le16 resp_len; 1786 __le16 mru; 1787 __le16 mtu; 1788 u8 ipg; 1789 u8 lpbk; 1790 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1791 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1792 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1793 u8 unused_0; 1794 u8 valid; 1795 }; 1796 1797 /* hwrm_port_mac_ptp_qcfg */ 1798 /* Input (24 bytes) */ 1799 struct hwrm_port_mac_ptp_qcfg_input { 1800 __le16 req_type; 1801 __le16 cmpl_ring; 1802 __le16 seq_id; 1803 __le16 target_id; 1804 __le64 resp_addr; 1805 __le16 port_id; 1806 __le16 unused_0[3]; 1807 }; 1808 1809 /* Output (80 bytes) */ 1810 struct hwrm_port_mac_ptp_qcfg_output { 1811 __le16 error_code; 1812 __le16 req_type; 1813 __le16 seq_id; 1814 __le16 resp_len; 1815 u8 flags; 1816 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 1817 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 1818 u8 unused_0; 1819 __le16 unused_1; 1820 __le32 rx_ts_reg_off_lower; 1821 __le32 rx_ts_reg_off_upper; 1822 __le32 rx_ts_reg_off_seq_id; 1823 __le32 rx_ts_reg_off_src_id_0; 1824 __le32 rx_ts_reg_off_src_id_1; 1825 __le32 rx_ts_reg_off_src_id_2; 1826 __le32 rx_ts_reg_off_domain_id; 1827 __le32 rx_ts_reg_off_fifo; 1828 __le32 rx_ts_reg_off_fifo_adv; 1829 __le32 rx_ts_reg_off_granularity; 1830 __le32 tx_ts_reg_off_lower; 1831 __le32 tx_ts_reg_off_upper; 1832 __le32 tx_ts_reg_off_seq_id; 1833 __le32 tx_ts_reg_off_fifo; 1834 __le32 tx_ts_reg_off_granularity; 1835 __le32 unused_2; 1836 u8 unused_3; 1837 u8 unused_4; 1838 u8 unused_5; 1839 u8 valid; 1840 }; 1841 1842 /* hwrm_port_qstats */ 1843 /* Input (40 bytes) */ 1844 struct hwrm_port_qstats_input { 1845 __le16 req_type; 1846 __le16 cmpl_ring; 1847 __le16 seq_id; 1848 __le16 target_id; 1849 __le64 resp_addr; 1850 __le16 port_id; 1851 u8 unused_0; 1852 u8 unused_1; 1853 u8 unused_2[3]; 1854 u8 unused_3; 1855 __le64 tx_stat_host_addr; 1856 __le64 rx_stat_host_addr; 1857 }; 1858 1859 /* Output (16 bytes) */ 1860 struct hwrm_port_qstats_output { 1861 __le16 error_code; 1862 __le16 req_type; 1863 __le16 seq_id; 1864 __le16 resp_len; 1865 __le16 tx_stat_size; 1866 __le16 rx_stat_size; 1867 u8 unused_0; 1868 u8 unused_1; 1869 u8 unused_2; 1870 u8 valid; 1871 }; 1872 1873 /* hwrm_port_lpbk_qstats */ 1874 /* Input (16 bytes) */ 1875 struct hwrm_port_lpbk_qstats_input { 1876 __le16 req_type; 1877 __le16 cmpl_ring; 1878 __le16 seq_id; 1879 __le16 target_id; 1880 __le64 resp_addr; 1881 }; 1882 1883 /* Output (96 bytes) */ 1884 struct hwrm_port_lpbk_qstats_output { 1885 __le16 error_code; 1886 __le16 req_type; 1887 __le16 seq_id; 1888 __le16 resp_len; 1889 __le64 lpbk_ucast_frames; 1890 __le64 lpbk_mcast_frames; 1891 __le64 lpbk_bcast_frames; 1892 __le64 lpbk_ucast_bytes; 1893 __le64 lpbk_mcast_bytes; 1894 __le64 lpbk_bcast_bytes; 1895 __le64 tx_stat_discard; 1896 __le64 tx_stat_error; 1897 __le64 rx_stat_discard; 1898 __le64 rx_stat_error; 1899 __le32 unused_0; 1900 u8 unused_1; 1901 u8 unused_2; 1902 u8 unused_3; 1903 u8 valid; 1904 }; 1905 1906 /* hwrm_port_clr_stats */ 1907 /* Input (24 bytes) */ 1908 struct hwrm_port_clr_stats_input { 1909 __le16 req_type; 1910 __le16 cmpl_ring; 1911 __le16 seq_id; 1912 __le16 target_id; 1913 __le64 resp_addr; 1914 __le16 port_id; 1915 __le16 unused_0[3]; 1916 }; 1917 1918 /* Output (16 bytes) */ 1919 struct hwrm_port_clr_stats_output { 1920 __le16 error_code; 1921 __le16 req_type; 1922 __le16 seq_id; 1923 __le16 resp_len; 1924 __le32 unused_0; 1925 u8 unused_1; 1926 u8 unused_2; 1927 u8 unused_3; 1928 u8 valid; 1929 }; 1930 1931 /* hwrm_port_lpbk_clr_stats */ 1932 /* Input (16 bytes) */ 1933 struct hwrm_port_lpbk_clr_stats_input { 1934 __le16 req_type; 1935 __le16 cmpl_ring; 1936 __le16 seq_id; 1937 __le16 target_id; 1938 __le64 resp_addr; 1939 }; 1940 1941 /* Output (16 bytes) */ 1942 struct hwrm_port_lpbk_clr_stats_output { 1943 __le16 error_code; 1944 __le16 req_type; 1945 __le16 seq_id; 1946 __le16 resp_len; 1947 __le32 unused_0; 1948 u8 unused_1; 1949 u8 unused_2; 1950 u8 unused_3; 1951 u8 valid; 1952 }; 1953 1954 /* hwrm_port_phy_qcaps */ 1955 /* Input (24 bytes) */ 1956 struct hwrm_port_phy_qcaps_input { 1957 __le16 req_type; 1958 __le16 cmpl_ring; 1959 __le16 seq_id; 1960 __le16 target_id; 1961 __le64 resp_addr; 1962 __le16 port_id; 1963 __le16 unused_0[3]; 1964 }; 1965 1966 /* Output (24 bytes) */ 1967 struct hwrm_port_phy_qcaps_output { 1968 __le16 error_code; 1969 __le16 req_type; 1970 __le16 seq_id; 1971 __le16 resp_len; 1972 u8 flags; 1973 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 1974 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 1975 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 1976 u8 port_cnt; 1977 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 1978 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 1979 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 1980 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 1981 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 1982 __le16 supported_speeds_force_mode; 1983 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 1984 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 1985 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 1986 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 1987 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 1988 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 1989 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 1990 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 1991 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 1992 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 1993 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 1994 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 1995 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 1996 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 1997 __le16 supported_speeds_auto_mode; 1998 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 1999 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2000 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2001 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2002 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2003 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2004 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2005 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2006 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2007 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2008 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2009 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2010 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2011 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2012 __le16 supported_speeds_eee_mode; 2013 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2014 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2015 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2016 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2017 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2018 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2019 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2020 __le32 tx_lpi_timer_low; 2021 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2022 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2023 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2024 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2025 __le32 valid_tx_lpi_timer_high; 2026 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2027 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2028 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2029 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2030 }; 2031 2032 /* hwrm_port_phy_i2c_read */ 2033 /* Input (40 bytes) */ 2034 struct hwrm_port_phy_i2c_read_input { 2035 __le16 req_type; 2036 __le16 cmpl_ring; 2037 __le16 seq_id; 2038 __le16 target_id; 2039 __le64 resp_addr; 2040 __le32 flags; 2041 __le32 enables; 2042 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2043 __le16 port_id; 2044 u8 i2c_slave_addr; 2045 u8 unused_0; 2046 __le16 page_number; 2047 __le16 page_offset; 2048 u8 data_length; 2049 u8 unused_1[7]; 2050 }; 2051 2052 /* Output (80 bytes) */ 2053 struct hwrm_port_phy_i2c_read_output { 2054 __le16 error_code; 2055 __le16 req_type; 2056 __le16 seq_id; 2057 __le16 resp_len; 2058 __le32 data[16]; 2059 __le32 unused_0; 2060 u8 unused_1; 2061 u8 unused_2; 2062 u8 unused_3; 2063 u8 valid; 2064 }; 2065 2066 /* hwrm_port_led_cfg */ 2067 /* Input (64 bytes) */ 2068 struct hwrm_port_led_cfg_input { 2069 __le16 req_type; 2070 __le16 cmpl_ring; 2071 __le16 seq_id; 2072 __le16 target_id; 2073 __le64 resp_addr; 2074 __le32 enables; 2075 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2076 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2077 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2078 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2079 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2080 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2081 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2082 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2083 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2084 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2085 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2086 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2087 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2088 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2089 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2090 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2091 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2092 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2093 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2094 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2095 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2096 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2097 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2098 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2099 __le16 port_id; 2100 u8 num_leds; 2101 u8 rsvd; 2102 u8 led0_id; 2103 u8 led0_state; 2104 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2105 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2106 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2107 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2108 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2109 u8 led0_color; 2110 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2111 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2112 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2113 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2114 u8 unused_0; 2115 __le16 led0_blink_on; 2116 __le16 led0_blink_off; 2117 u8 led0_group_id; 2118 u8 rsvd0; 2119 u8 led1_id; 2120 u8 led1_state; 2121 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2122 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2123 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2124 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2125 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2126 u8 led1_color; 2127 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2128 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2129 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2130 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2131 u8 unused_1; 2132 __le16 led1_blink_on; 2133 __le16 led1_blink_off; 2134 u8 led1_group_id; 2135 u8 rsvd1; 2136 u8 led2_id; 2137 u8 led2_state; 2138 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2139 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2140 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2141 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2142 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2143 u8 led2_color; 2144 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2145 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2146 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2147 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2148 u8 unused_2; 2149 __le16 led2_blink_on; 2150 __le16 led2_blink_off; 2151 u8 led2_group_id; 2152 u8 rsvd2; 2153 u8 led3_id; 2154 u8 led3_state; 2155 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2156 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2157 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2158 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2159 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2160 u8 led3_color; 2161 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2162 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2163 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2164 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2165 u8 unused_3; 2166 __le16 led3_blink_on; 2167 __le16 led3_blink_off; 2168 u8 led3_group_id; 2169 u8 rsvd3; 2170 }; 2171 2172 /* Output (16 bytes) */ 2173 struct hwrm_port_led_cfg_output { 2174 __le16 error_code; 2175 __le16 req_type; 2176 __le16 seq_id; 2177 __le16 resp_len; 2178 __le32 unused_0; 2179 u8 unused_1; 2180 u8 unused_2; 2181 u8 unused_3; 2182 u8 valid; 2183 }; 2184 2185 /* hwrm_port_led_qcaps */ 2186 /* Input (24 bytes) */ 2187 struct hwrm_port_led_qcaps_input { 2188 __le16 req_type; 2189 __le16 cmpl_ring; 2190 __le16 seq_id; 2191 __le16 target_id; 2192 __le64 resp_addr; 2193 __le16 port_id; 2194 __le16 unused_0[3]; 2195 }; 2196 2197 /* Output (48 bytes) */ 2198 struct hwrm_port_led_qcaps_output { 2199 __le16 error_code; 2200 __le16 req_type; 2201 __le16 seq_id; 2202 __le16 resp_len; 2203 u8 num_leds; 2204 u8 unused_0[3]; 2205 u8 led0_id; 2206 u8 led0_type; 2207 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2208 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2209 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2210 u8 led0_group_id; 2211 u8 unused_1; 2212 __le16 led0_state_caps; 2213 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2214 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2215 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2216 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2217 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2218 __le16 led0_color_caps; 2219 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2220 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2221 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2222 u8 led1_id; 2223 u8 led1_type; 2224 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2225 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2226 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2227 u8 led1_group_id; 2228 u8 unused_2; 2229 __le16 led1_state_caps; 2230 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2231 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2232 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2233 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2234 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2235 __le16 led1_color_caps; 2236 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2237 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2238 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2239 u8 led2_id; 2240 u8 led2_type; 2241 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2242 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2243 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2244 u8 led2_group_id; 2245 u8 unused_3; 2246 __le16 led2_state_caps; 2247 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2248 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2249 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2250 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2251 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2252 __le16 led2_color_caps; 2253 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2254 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2255 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2256 u8 led3_id; 2257 u8 led3_type; 2258 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2259 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2260 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2261 u8 led3_group_id; 2262 u8 unused_4; 2263 __le16 led3_state_caps; 2264 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2265 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2266 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2267 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2268 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2269 __le16 led3_color_caps; 2270 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2271 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2272 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2273 u8 unused_5; 2274 u8 unused_6; 2275 u8 unused_7; 2276 u8 valid; 2277 }; 2278 2279 /* hwrm_queue_qportcfg */ 2280 /* Input (24 bytes) */ 2281 struct hwrm_queue_qportcfg_input { 2282 __le16 req_type; 2283 __le16 cmpl_ring; 2284 __le16 seq_id; 2285 __le16 target_id; 2286 __le64 resp_addr; 2287 __le32 flags; 2288 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2289 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2290 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2291 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2292 __le16 port_id; 2293 __le16 unused_0; 2294 }; 2295 2296 /* Output (32 bytes) */ 2297 struct hwrm_queue_qportcfg_output { 2298 __le16 error_code; 2299 __le16 req_type; 2300 __le16 seq_id; 2301 __le16 resp_len; 2302 u8 max_configurable_queues; 2303 u8 max_configurable_lossless_queues; 2304 u8 queue_cfg_allowed; 2305 u8 queue_cfg_info; 2306 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2307 u8 queue_pfcenable_cfg_allowed; 2308 u8 queue_pri2cos_cfg_allowed; 2309 u8 queue_cos2bw_cfg_allowed; 2310 u8 queue_id0; 2311 u8 queue_id0_service_profile; 2312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2313 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2315 u8 queue_id1; 2316 u8 queue_id1_service_profile; 2317 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2318 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2319 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2320 u8 queue_id2; 2321 u8 queue_id2_service_profile; 2322 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2323 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2324 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2325 u8 queue_id3; 2326 u8 queue_id3_service_profile; 2327 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2328 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2329 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2330 u8 queue_id4; 2331 u8 queue_id4_service_profile; 2332 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2333 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2334 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2335 u8 queue_id5; 2336 u8 queue_id5_service_profile; 2337 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2338 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2339 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2340 u8 queue_id6; 2341 u8 queue_id6_service_profile; 2342 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2343 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2344 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2345 u8 queue_id7; 2346 u8 queue_id7_service_profile; 2347 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2348 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2349 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2350 u8 valid; 2351 }; 2352 2353 /* hwrm_queue_cfg */ 2354 /* Input (40 bytes) */ 2355 struct hwrm_queue_cfg_input { 2356 __le16 req_type; 2357 __le16 cmpl_ring; 2358 __le16 seq_id; 2359 __le16 target_id; 2360 __le64 resp_addr; 2361 __le32 flags; 2362 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2363 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2364 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2365 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2366 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2367 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2368 __le32 enables; 2369 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2370 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2371 __le32 queue_id; 2372 __le32 dflt_len; 2373 u8 service_profile; 2374 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2375 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2376 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2377 u8 unused_0[7]; 2378 }; 2379 2380 /* Output (16 bytes) */ 2381 struct hwrm_queue_cfg_output { 2382 __le16 error_code; 2383 __le16 req_type; 2384 __le16 seq_id; 2385 __le16 resp_len; 2386 __le32 unused_0; 2387 u8 unused_1; 2388 u8 unused_2; 2389 u8 unused_3; 2390 u8 valid; 2391 }; 2392 2393 /* hwrm_queue_pfcenable_qcfg */ 2394 /* Input (24 bytes) */ 2395 struct hwrm_queue_pfcenable_qcfg_input { 2396 __le16 req_type; 2397 __le16 cmpl_ring; 2398 __le16 seq_id; 2399 __le16 target_id; 2400 __le64 resp_addr; 2401 __le16 port_id; 2402 __le16 unused_0[3]; 2403 }; 2404 2405 /* Output (16 bytes) */ 2406 struct hwrm_queue_pfcenable_qcfg_output { 2407 __le16 error_code; 2408 __le16 req_type; 2409 __le16 seq_id; 2410 __le16 resp_len; 2411 __le32 flags; 2412 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2413 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2414 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2415 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2416 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2417 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2418 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2419 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2420 u8 unused_0; 2421 u8 unused_1; 2422 u8 unused_2; 2423 u8 valid; 2424 }; 2425 2426 /* hwrm_queue_pfcenable_cfg */ 2427 /* Input (24 bytes) */ 2428 struct hwrm_queue_pfcenable_cfg_input { 2429 __le16 req_type; 2430 __le16 cmpl_ring; 2431 __le16 seq_id; 2432 __le16 target_id; 2433 __le64 resp_addr; 2434 __le32 flags; 2435 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2436 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2437 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2438 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2439 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2440 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2441 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2442 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2443 __le16 port_id; 2444 __le16 unused_0; 2445 }; 2446 2447 /* Output (16 bytes) */ 2448 struct hwrm_queue_pfcenable_cfg_output { 2449 __le16 error_code; 2450 __le16 req_type; 2451 __le16 seq_id; 2452 __le16 resp_len; 2453 __le32 unused_0; 2454 u8 unused_1; 2455 u8 unused_2; 2456 u8 unused_3; 2457 u8 valid; 2458 }; 2459 2460 /* hwrm_queue_pri2cos_qcfg */ 2461 /* Input (24 bytes) */ 2462 struct hwrm_queue_pri2cos_qcfg_input { 2463 __le16 req_type; 2464 __le16 cmpl_ring; 2465 __le16 seq_id; 2466 __le16 target_id; 2467 __le64 resp_addr; 2468 __le32 flags; 2469 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2470 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2471 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2472 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2473 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2474 u8 port_id; 2475 u8 unused_0[3]; 2476 }; 2477 2478 /* Output (24 bytes) */ 2479 struct hwrm_queue_pri2cos_qcfg_output { 2480 __le16 error_code; 2481 __le16 req_type; 2482 __le16 seq_id; 2483 __le16 resp_len; 2484 u8 pri0_cos_queue_id; 2485 u8 pri1_cos_queue_id; 2486 u8 pri2_cos_queue_id; 2487 u8 pri3_cos_queue_id; 2488 u8 pri4_cos_queue_id; 2489 u8 pri5_cos_queue_id; 2490 u8 pri6_cos_queue_id; 2491 u8 pri7_cos_queue_id; 2492 u8 queue_cfg_info; 2493 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2494 u8 unused_0; 2495 __le16 unused_1; 2496 u8 unused_2; 2497 u8 unused_3; 2498 u8 unused_4; 2499 u8 valid; 2500 }; 2501 2502 /* hwrm_queue_pri2cos_cfg */ 2503 /* Input (40 bytes) */ 2504 struct hwrm_queue_pri2cos_cfg_input { 2505 __le16 req_type; 2506 __le16 cmpl_ring; 2507 __le16 seq_id; 2508 __le16 target_id; 2509 __le64 resp_addr; 2510 __le32 flags; 2511 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2512 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2513 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2514 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2515 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2516 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2517 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2518 __le32 enables; 2519 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2520 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2521 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2522 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2523 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2524 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2525 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2526 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2527 u8 port_id; 2528 u8 pri0_cos_queue_id; 2529 u8 pri1_cos_queue_id; 2530 u8 pri2_cos_queue_id; 2531 u8 pri3_cos_queue_id; 2532 u8 pri4_cos_queue_id; 2533 u8 pri5_cos_queue_id; 2534 u8 pri6_cos_queue_id; 2535 u8 pri7_cos_queue_id; 2536 u8 unused_0[7]; 2537 }; 2538 2539 /* Output (16 bytes) */ 2540 struct hwrm_queue_pri2cos_cfg_output { 2541 __le16 error_code; 2542 __le16 req_type; 2543 __le16 seq_id; 2544 __le16 resp_len; 2545 __le32 unused_0; 2546 u8 unused_1; 2547 u8 unused_2; 2548 u8 unused_3; 2549 u8 valid; 2550 }; 2551 2552 /* hwrm_queue_cos2bw_qcfg */ 2553 /* Input (24 bytes) */ 2554 struct hwrm_queue_cos2bw_qcfg_input { 2555 __le16 req_type; 2556 __le16 cmpl_ring; 2557 __le16 seq_id; 2558 __le16 target_id; 2559 __le64 resp_addr; 2560 __le16 port_id; 2561 __le16 unused_0[3]; 2562 }; 2563 2564 /* Output (112 bytes) */ 2565 struct hwrm_queue_cos2bw_qcfg_output { 2566 __le16 error_code; 2567 __le16 req_type; 2568 __le16 seq_id; 2569 __le16 resp_len; 2570 u8 queue_id0; 2571 u8 unused_0; 2572 __le16 unused_1; 2573 __le32 queue_id0_min_bw; 2574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2589 __le32 queue_id0_max_bw; 2590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2605 u8 queue_id0_tsa_assign; 2606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2610 u8 queue_id0_pri_lvl; 2611 u8 queue_id0_bw_weight; 2612 u8 queue_id1; 2613 __le32 queue_id1_min_bw; 2614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2629 __le32 queue_id1_max_bw; 2630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2645 u8 queue_id1_tsa_assign; 2646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2650 u8 queue_id1_pri_lvl; 2651 u8 queue_id1_bw_weight; 2652 u8 queue_id2; 2653 __le32 queue_id2_min_bw; 2654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2669 __le32 queue_id2_max_bw; 2670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2685 u8 queue_id2_tsa_assign; 2686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2690 u8 queue_id2_pri_lvl; 2691 u8 queue_id2_bw_weight; 2692 u8 queue_id3; 2693 __le32 queue_id3_min_bw; 2694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 2700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2709 __le32 queue_id3_max_bw; 2710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 2716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2725 u8 queue_id3_tsa_assign; 2726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2730 u8 queue_id3_pri_lvl; 2731 u8 queue_id3_bw_weight; 2732 u8 queue_id4; 2733 __le32 queue_id4_min_bw; 2734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 2740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2749 __le32 queue_id4_max_bw; 2750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 2753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 2754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 2755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 2756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2765 u8 queue_id4_tsa_assign; 2766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2770 u8 queue_id4_pri_lvl; 2771 u8 queue_id4_bw_weight; 2772 u8 queue_id5; 2773 __le32 queue_id5_min_bw; 2774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 2777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 2778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 2779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 2780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2789 __le32 queue_id5_max_bw; 2790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 2793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 2794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 2795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 2796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2805 u8 queue_id5_tsa_assign; 2806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2810 u8 queue_id5_pri_lvl; 2811 u8 queue_id5_bw_weight; 2812 u8 queue_id6; 2813 __le32 queue_id6_min_bw; 2814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 2817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 2818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 2819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 2820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2829 __le32 queue_id6_max_bw; 2830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 2833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 2834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 2835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 2836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2845 u8 queue_id6_tsa_assign; 2846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2850 u8 queue_id6_pri_lvl; 2851 u8 queue_id6_bw_weight; 2852 u8 queue_id7; 2853 __le32 queue_id7_min_bw; 2854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 2857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 2858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 2859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 2860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2869 __le32 queue_id7_max_bw; 2870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 2873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 2874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 2875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 2876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2885 u8 queue_id7_tsa_assign; 2886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2890 u8 queue_id7_pri_lvl; 2891 u8 queue_id7_bw_weight; 2892 u8 unused_2; 2893 u8 unused_3; 2894 u8 unused_4; 2895 u8 unused_5; 2896 u8 valid; 2897 }; 2898 2899 /* hwrm_queue_cos2bw_cfg */ 2900 /* Input (128 bytes) */ 2901 struct hwrm_queue_cos2bw_cfg_input { 2902 __le16 req_type; 2903 __le16 cmpl_ring; 2904 __le16 seq_id; 2905 __le16 target_id; 2906 __le64 resp_addr; 2907 __le32 flags; 2908 __le32 enables; 2909 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2910 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2911 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2912 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2913 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2914 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2915 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2916 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2917 __le16 port_id; 2918 u8 queue_id0; 2919 u8 unused_0; 2920 __le32 queue_id0_min_bw; 2921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 2927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2936 __le32 queue_id0_max_bw; 2937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 2943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2952 u8 queue_id0_tsa_assign; 2953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2957 u8 queue_id0_pri_lvl; 2958 u8 queue_id0_bw_weight; 2959 u8 queue_id1; 2960 __le32 queue_id1_min_bw; 2961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 2967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2976 __le32 queue_id1_max_bw; 2977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 2983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2992 u8 queue_id1_tsa_assign; 2993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2997 u8 queue_id1_pri_lvl; 2998 u8 queue_id1_bw_weight; 2999 u8 queue_id2; 3000 __le32 queue_id2_min_bw; 3001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3016 __le32 queue_id2_max_bw; 3017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3032 u8 queue_id2_tsa_assign; 3033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3037 u8 queue_id2_pri_lvl; 3038 u8 queue_id2_bw_weight; 3039 u8 queue_id3; 3040 __le32 queue_id3_min_bw; 3041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3056 __le32 queue_id3_max_bw; 3057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3072 u8 queue_id3_tsa_assign; 3073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3077 u8 queue_id3_pri_lvl; 3078 u8 queue_id3_bw_weight; 3079 u8 queue_id4; 3080 __le32 queue_id4_min_bw; 3081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 3087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3096 __le32 queue_id4_max_bw; 3097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3112 u8 queue_id4_tsa_assign; 3113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3117 u8 queue_id4_pri_lvl; 3118 u8 queue_id4_bw_weight; 3119 u8 queue_id5; 3120 __le32 queue_id5_min_bw; 3121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3136 __le32 queue_id5_max_bw; 3137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3152 u8 queue_id5_tsa_assign; 3153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3157 u8 queue_id5_pri_lvl; 3158 u8 queue_id5_bw_weight; 3159 u8 queue_id6; 3160 __le32 queue_id6_min_bw; 3161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3176 __le32 queue_id6_max_bw; 3177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3192 u8 queue_id6_tsa_assign; 3193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3197 u8 queue_id6_pri_lvl; 3198 u8 queue_id6_bw_weight; 3199 u8 queue_id7; 3200 __le32 queue_id7_min_bw; 3201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3216 __le32 queue_id7_max_bw; 3217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3232 u8 queue_id7_tsa_assign; 3233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3237 u8 queue_id7_pri_lvl; 3238 u8 queue_id7_bw_weight; 3239 u8 unused_1[5]; 3240 }; 3241 3242 /* Output (16 bytes) */ 3243 struct hwrm_queue_cos2bw_cfg_output { 3244 __le16 error_code; 3245 __le16 req_type; 3246 __le16 seq_id; 3247 __le16 resp_len; 3248 __le32 unused_0; 3249 u8 unused_1; 3250 u8 unused_2; 3251 u8 unused_3; 3252 u8 valid; 3253 }; 3254 3255 /* hwrm_queue_dscp_qcaps */ 3256 /* Input (24 bytes) */ 3257 struct hwrm_queue_dscp_qcaps_input { 3258 __le16 req_type; 3259 __le16 cmpl_ring; 3260 __le16 seq_id; 3261 __le16 target_id; 3262 __le64 resp_addr; 3263 u8 port_id; 3264 u8 unused_0[7]; 3265 }; 3266 3267 /* Output (16 bytes) */ 3268 struct hwrm_queue_dscp_qcaps_output { 3269 __le16 error_code; 3270 __le16 req_type; 3271 __le16 seq_id; 3272 __le16 resp_len; 3273 u8 num_dscp_bits; 3274 u8 unused_0; 3275 __le16 max_entries; 3276 u8 unused_1; 3277 u8 unused_2; 3278 u8 unused_3; 3279 u8 valid; 3280 }; 3281 3282 /* hwrm_queue_dscp2pri_qcfg */ 3283 /* Input (32 bytes) */ 3284 struct hwrm_queue_dscp2pri_qcfg_input { 3285 __le16 req_type; 3286 __le16 cmpl_ring; 3287 __le16 seq_id; 3288 __le16 target_id; 3289 __le64 resp_addr; 3290 __le64 dest_data_addr; 3291 u8 port_id; 3292 u8 unused_0; 3293 __le16 dest_data_buffer_size; 3294 __le32 unused_1; 3295 }; 3296 3297 /* Output (16 bytes) */ 3298 struct hwrm_queue_dscp2pri_qcfg_output { 3299 __le16 error_code; 3300 __le16 req_type; 3301 __le16 seq_id; 3302 __le16 resp_len; 3303 __le16 entry_cnt; 3304 u8 default_pri; 3305 u8 unused_0; 3306 u8 unused_1; 3307 u8 unused_2; 3308 u8 unused_3; 3309 u8 valid; 3310 }; 3311 3312 /* hwrm_queue_dscp2pri_cfg */ 3313 /* Input (40 bytes) */ 3314 struct hwrm_queue_dscp2pri_cfg_input { 3315 __le16 req_type; 3316 __le16 cmpl_ring; 3317 __le16 seq_id; 3318 __le16 target_id; 3319 __le64 resp_addr; 3320 __le64 src_data_addr; 3321 __le32 flags; 3322 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 3323 __le32 enables; 3324 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 3325 u8 port_id; 3326 u8 default_pri; 3327 __le16 entry_cnt; 3328 __le32 unused_0; 3329 }; 3330 3331 /* Output (16 bytes) */ 3332 struct hwrm_queue_dscp2pri_cfg_output { 3333 __le16 error_code; 3334 __le16 req_type; 3335 __le16 seq_id; 3336 __le16 resp_len; 3337 __le32 unused_0; 3338 u8 unused_1; 3339 u8 unused_2; 3340 u8 unused_3; 3341 u8 valid; 3342 }; 3343 3344 /* hwrm_vnic_alloc */ 3345 /* Input (24 bytes) */ 3346 struct hwrm_vnic_alloc_input { 3347 __le16 req_type; 3348 __le16 cmpl_ring; 3349 __le16 seq_id; 3350 __le16 target_id; 3351 __le64 resp_addr; 3352 __le32 flags; 3353 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3354 __le32 unused_0; 3355 }; 3356 3357 /* Output (16 bytes) */ 3358 struct hwrm_vnic_alloc_output { 3359 __le16 error_code; 3360 __le16 req_type; 3361 __le16 seq_id; 3362 __le16 resp_len; 3363 __le32 vnic_id; 3364 u8 unused_0; 3365 u8 unused_1; 3366 u8 unused_2; 3367 u8 valid; 3368 }; 3369 3370 /* hwrm_vnic_free */ 3371 /* Input (24 bytes) */ 3372 struct hwrm_vnic_free_input { 3373 __le16 req_type; 3374 __le16 cmpl_ring; 3375 __le16 seq_id; 3376 __le16 target_id; 3377 __le64 resp_addr; 3378 __le32 vnic_id; 3379 __le32 unused_0; 3380 }; 3381 3382 /* Output (16 bytes) */ 3383 struct hwrm_vnic_free_output { 3384 __le16 error_code; 3385 __le16 req_type; 3386 __le16 seq_id; 3387 __le16 resp_len; 3388 __le32 unused_0; 3389 u8 unused_1; 3390 u8 unused_2; 3391 u8 unused_3; 3392 u8 valid; 3393 }; 3394 3395 /* hwrm_vnic_cfg */ 3396 /* Input (40 bytes) */ 3397 struct hwrm_vnic_cfg_input { 3398 __le16 req_type; 3399 __le16 cmpl_ring; 3400 __le16 seq_id; 3401 __le16 target_id; 3402 __le64 resp_addr; 3403 __le32 flags; 3404 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3405 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3406 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3407 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3408 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3409 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3410 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 3411 __le32 enables; 3412 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3413 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3414 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3415 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3416 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3417 __le16 vnic_id; 3418 __le16 dflt_ring_grp; 3419 __le16 rss_rule; 3420 __le16 cos_rule; 3421 __le16 lb_rule; 3422 __le16 mru; 3423 __le32 unused_0; 3424 }; 3425 3426 /* Output (16 bytes) */ 3427 struct hwrm_vnic_cfg_output { 3428 __le16 error_code; 3429 __le16 req_type; 3430 __le16 seq_id; 3431 __le16 resp_len; 3432 __le32 unused_0; 3433 u8 unused_1; 3434 u8 unused_2; 3435 u8 unused_3; 3436 u8 valid; 3437 }; 3438 3439 /* hwrm_vnic_qcaps */ 3440 /* Input (24 bytes) */ 3441 struct hwrm_vnic_qcaps_input { 3442 __le16 req_type; 3443 __le16 cmpl_ring; 3444 __le16 seq_id; 3445 __le16 target_id; 3446 __le64 resp_addr; 3447 __le32 enables; 3448 __le32 unused_0; 3449 }; 3450 3451 /* Output (24 bytes) */ 3452 struct hwrm_vnic_qcaps_output { 3453 __le16 error_code; 3454 __le16 req_type; 3455 __le16 seq_id; 3456 __le16 resp_len; 3457 __le16 mru; 3458 u8 unused_0; 3459 u8 unused_1; 3460 __le32 flags; 3461 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3462 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3463 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3464 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3465 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3466 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3467 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRROING_CAPABLE_VNIC_CAP 0x40UL 3468 __le32 unused_2; 3469 u8 unused_3; 3470 u8 unused_4; 3471 u8 unused_5; 3472 u8 valid; 3473 }; 3474 3475 /* hwrm_vnic_tpa_cfg */ 3476 /* Input (40 bytes) */ 3477 struct hwrm_vnic_tpa_cfg_input { 3478 __le16 req_type; 3479 __le16 cmpl_ring; 3480 __le16 seq_id; 3481 __le16 target_id; 3482 __le64 resp_addr; 3483 __le32 flags; 3484 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3485 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3486 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3487 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3488 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3489 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3490 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3491 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3492 __le32 enables; 3493 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3494 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3495 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3496 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3497 __le16 vnic_id; 3498 __le16 max_agg_segs; 3499 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3500 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3501 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3502 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3503 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3504 __le16 max_aggs; 3505 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3506 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3507 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3508 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3509 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3510 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3511 u8 unused_0; 3512 u8 unused_1; 3513 __le32 max_agg_timer; 3514 __le32 min_agg_len; 3515 }; 3516 3517 /* Output (16 bytes) */ 3518 struct hwrm_vnic_tpa_cfg_output { 3519 __le16 error_code; 3520 __le16 req_type; 3521 __le16 seq_id; 3522 __le16 resp_len; 3523 __le32 unused_0; 3524 u8 unused_1; 3525 u8 unused_2; 3526 u8 unused_3; 3527 u8 valid; 3528 }; 3529 3530 /* hwrm_vnic_rss_cfg */ 3531 /* Input (48 bytes) */ 3532 struct hwrm_vnic_rss_cfg_input { 3533 __le16 req_type; 3534 __le16 cmpl_ring; 3535 __le16 seq_id; 3536 __le16 target_id; 3537 __le64 resp_addr; 3538 __le32 hash_type; 3539 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3540 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3541 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3542 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3543 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3544 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3545 __le32 unused_0; 3546 __le64 ring_grp_tbl_addr; 3547 __le64 hash_key_tbl_addr; 3548 __le16 rss_ctx_idx; 3549 __le16 unused_1[3]; 3550 }; 3551 3552 /* Output (16 bytes) */ 3553 struct hwrm_vnic_rss_cfg_output { 3554 __le16 error_code; 3555 __le16 req_type; 3556 __le16 seq_id; 3557 __le16 resp_len; 3558 __le32 unused_0; 3559 u8 unused_1; 3560 u8 unused_2; 3561 u8 unused_3; 3562 u8 valid; 3563 }; 3564 3565 /* hwrm_vnic_plcmodes_cfg */ 3566 /* Input (40 bytes) */ 3567 struct hwrm_vnic_plcmodes_cfg_input { 3568 __le16 req_type; 3569 __le16 cmpl_ring; 3570 __le16 seq_id; 3571 __le16 target_id; 3572 __le64 resp_addr; 3573 __le32 flags; 3574 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3575 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3576 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3577 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3578 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3579 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3580 __le32 enables; 3581 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3582 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3583 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3584 __le32 vnic_id; 3585 __le16 jumbo_thresh; 3586 __le16 hds_offset; 3587 __le16 hds_threshold; 3588 __le16 unused_0[3]; 3589 }; 3590 3591 /* Output (16 bytes) */ 3592 struct hwrm_vnic_plcmodes_cfg_output { 3593 __le16 error_code; 3594 __le16 req_type; 3595 __le16 seq_id; 3596 __le16 resp_len; 3597 __le32 unused_0; 3598 u8 unused_1; 3599 u8 unused_2; 3600 u8 unused_3; 3601 u8 valid; 3602 }; 3603 3604 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 3605 /* Input (16 bytes) */ 3606 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3607 __le16 req_type; 3608 __le16 cmpl_ring; 3609 __le16 seq_id; 3610 __le16 target_id; 3611 __le64 resp_addr; 3612 }; 3613 3614 /* Output (16 bytes) */ 3615 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3616 __le16 error_code; 3617 __le16 req_type; 3618 __le16 seq_id; 3619 __le16 resp_len; 3620 __le16 rss_cos_lb_ctx_id; 3621 u8 unused_0; 3622 u8 unused_1; 3623 u8 unused_2; 3624 u8 unused_3; 3625 u8 unused_4; 3626 u8 valid; 3627 }; 3628 3629 /* hwrm_vnic_rss_cos_lb_ctx_free */ 3630 /* Input (24 bytes) */ 3631 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3632 __le16 req_type; 3633 __le16 cmpl_ring; 3634 __le16 seq_id; 3635 __le16 target_id; 3636 __le64 resp_addr; 3637 __le16 rss_cos_lb_ctx_id; 3638 __le16 unused_0[3]; 3639 }; 3640 3641 /* Output (16 bytes) */ 3642 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3643 __le16 error_code; 3644 __le16 req_type; 3645 __le16 seq_id; 3646 __le16 resp_len; 3647 __le32 unused_0; 3648 u8 unused_1; 3649 u8 unused_2; 3650 u8 unused_3; 3651 u8 valid; 3652 }; 3653 3654 /* hwrm_ring_alloc */ 3655 /* Input (80 bytes) */ 3656 struct hwrm_ring_alloc_input { 3657 __le16 req_type; 3658 __le16 cmpl_ring; 3659 __le16 seq_id; 3660 __le16 target_id; 3661 __le64 resp_addr; 3662 __le32 enables; 3663 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 3664 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3665 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 3666 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3667 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 3668 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3669 u8 ring_type; 3670 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3671 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3672 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3673 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3674 u8 unused_0; 3675 __le16 unused_1; 3676 __le64 page_tbl_addr; 3677 __le32 fbo; 3678 u8 page_size; 3679 u8 page_tbl_depth; 3680 u8 unused_2; 3681 u8 unused_3; 3682 __le32 length; 3683 __le16 logical_id; 3684 __le16 cmpl_ring_id; 3685 __le16 queue_id; 3686 u8 unused_4; 3687 u8 unused_5; 3688 __le32 reserved1; 3689 __le16 ring_arb_cfg; 3690 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3691 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3692 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3693 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3694 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3695 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3696 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3697 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3698 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3699 u8 unused_6; 3700 u8 unused_7; 3701 __le32 reserved3; 3702 __le32 stat_ctx_id; 3703 __le32 reserved4; 3704 __le32 max_bw; 3705 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3706 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3707 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3708 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3709 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3710 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3711 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3712 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3713 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3714 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3715 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3716 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3717 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3718 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3719 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3720 u8 int_mode; 3721 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3722 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3723 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3724 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3725 u8 unused_8[3]; 3726 }; 3727 3728 /* Output (16 bytes) */ 3729 struct hwrm_ring_alloc_output { 3730 __le16 error_code; 3731 __le16 req_type; 3732 __le16 seq_id; 3733 __le16 resp_len; 3734 __le16 ring_id; 3735 __le16 logical_ring_id; 3736 u8 unused_0; 3737 u8 unused_1; 3738 u8 unused_2; 3739 u8 valid; 3740 }; 3741 3742 /* hwrm_ring_free */ 3743 /* Input (24 bytes) */ 3744 struct hwrm_ring_free_input { 3745 __le16 req_type; 3746 __le16 cmpl_ring; 3747 __le16 seq_id; 3748 __le16 target_id; 3749 __le64 resp_addr; 3750 u8 ring_type; 3751 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3752 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3753 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3754 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3755 u8 unused_0; 3756 __le16 ring_id; 3757 __le32 unused_1; 3758 }; 3759 3760 /* Output (16 bytes) */ 3761 struct hwrm_ring_free_output { 3762 __le16 error_code; 3763 __le16 req_type; 3764 __le16 seq_id; 3765 __le16 resp_len; 3766 __le32 unused_0; 3767 u8 unused_1; 3768 u8 unused_2; 3769 u8 unused_3; 3770 u8 valid; 3771 }; 3772 3773 /* hwrm_ring_cmpl_ring_qaggint_params */ 3774 /* Input (24 bytes) */ 3775 struct hwrm_ring_cmpl_ring_qaggint_params_input { 3776 __le16 req_type; 3777 __le16 cmpl_ring; 3778 __le16 seq_id; 3779 __le16 target_id; 3780 __le64 resp_addr; 3781 __le16 ring_id; 3782 __le16 unused_0[3]; 3783 }; 3784 3785 /* Output (32 bytes) */ 3786 struct hwrm_ring_cmpl_ring_qaggint_params_output { 3787 __le16 error_code; 3788 __le16 req_type; 3789 __le16 seq_id; 3790 __le16 resp_len; 3791 __le16 flags; 3792 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3793 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3794 __le16 num_cmpl_dma_aggr; 3795 __le16 num_cmpl_dma_aggr_during_int; 3796 __le16 cmpl_aggr_dma_tmr; 3797 __le16 cmpl_aggr_dma_tmr_during_int; 3798 __le16 int_lat_tmr_min; 3799 __le16 int_lat_tmr_max; 3800 __le16 num_cmpl_aggr_int; 3801 __le32 unused_0; 3802 u8 unused_1; 3803 u8 unused_2; 3804 u8 unused_3; 3805 u8 valid; 3806 }; 3807 3808 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3809 /* Input (40 bytes) */ 3810 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3811 __le16 req_type; 3812 __le16 cmpl_ring; 3813 __le16 seq_id; 3814 __le16 target_id; 3815 __le64 resp_addr; 3816 __le16 ring_id; 3817 __le16 flags; 3818 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3819 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3820 __le16 num_cmpl_dma_aggr; 3821 __le16 num_cmpl_dma_aggr_during_int; 3822 __le16 cmpl_aggr_dma_tmr; 3823 __le16 cmpl_aggr_dma_tmr_during_int; 3824 __le16 int_lat_tmr_min; 3825 __le16 int_lat_tmr_max; 3826 __le16 num_cmpl_aggr_int; 3827 __le16 unused_0[3]; 3828 }; 3829 3830 /* Output (16 bytes) */ 3831 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3832 __le16 error_code; 3833 __le16 req_type; 3834 __le16 seq_id; 3835 __le16 resp_len; 3836 __le32 unused_0; 3837 u8 unused_1; 3838 u8 unused_2; 3839 u8 unused_3; 3840 u8 valid; 3841 }; 3842 3843 /* hwrm_ring_reset */ 3844 /* Input (24 bytes) */ 3845 struct hwrm_ring_reset_input { 3846 __le16 req_type; 3847 __le16 cmpl_ring; 3848 __le16 seq_id; 3849 __le16 target_id; 3850 __le64 resp_addr; 3851 u8 ring_type; 3852 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 3853 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3854 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3855 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3856 u8 unused_0; 3857 __le16 ring_id; 3858 __le32 unused_1; 3859 }; 3860 3861 /* Output (16 bytes) */ 3862 struct hwrm_ring_reset_output { 3863 __le16 error_code; 3864 __le16 req_type; 3865 __le16 seq_id; 3866 __le16 resp_len; 3867 __le32 unused_0; 3868 u8 unused_1; 3869 u8 unused_2; 3870 u8 unused_3; 3871 u8 valid; 3872 }; 3873 3874 /* hwrm_ring_grp_alloc */ 3875 /* Input (24 bytes) */ 3876 struct hwrm_ring_grp_alloc_input { 3877 __le16 req_type; 3878 __le16 cmpl_ring; 3879 __le16 seq_id; 3880 __le16 target_id; 3881 __le64 resp_addr; 3882 __le16 cr; 3883 __le16 rr; 3884 __le16 ar; 3885 __le16 sc; 3886 }; 3887 3888 /* Output (16 bytes) */ 3889 struct hwrm_ring_grp_alloc_output { 3890 __le16 error_code; 3891 __le16 req_type; 3892 __le16 seq_id; 3893 __le16 resp_len; 3894 __le32 ring_group_id; 3895 u8 unused_0; 3896 u8 unused_1; 3897 u8 unused_2; 3898 u8 valid; 3899 }; 3900 3901 /* hwrm_ring_grp_free */ 3902 /* Input (24 bytes) */ 3903 struct hwrm_ring_grp_free_input { 3904 __le16 req_type; 3905 __le16 cmpl_ring; 3906 __le16 seq_id; 3907 __le16 target_id; 3908 __le64 resp_addr; 3909 __le32 ring_group_id; 3910 __le32 unused_0; 3911 }; 3912 3913 /* Output (16 bytes) */ 3914 struct hwrm_ring_grp_free_output { 3915 __le16 error_code; 3916 __le16 req_type; 3917 __le16 seq_id; 3918 __le16 resp_len; 3919 __le32 unused_0; 3920 u8 unused_1; 3921 u8 unused_2; 3922 u8 unused_3; 3923 u8 valid; 3924 }; 3925 3926 /* hwrm_cfa_l2_filter_alloc */ 3927 /* Input (96 bytes) */ 3928 struct hwrm_cfa_l2_filter_alloc_input { 3929 __le16 req_type; 3930 __le16 cmpl_ring; 3931 __le16 seq_id; 3932 __le16 target_id; 3933 __le64 resp_addr; 3934 __le32 flags; 3935 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3936 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3937 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3938 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3939 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3940 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3941 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3942 __le32 enables; 3943 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3944 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3945 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3946 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3947 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3948 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3949 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3950 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3951 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3952 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3953 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3954 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3955 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3956 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3957 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3958 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3959 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3960 u8 l2_addr[6]; 3961 u8 unused_0; 3962 u8 unused_1; 3963 u8 l2_addr_mask[6]; 3964 __le16 l2_ovlan; 3965 __le16 l2_ovlan_mask; 3966 __le16 l2_ivlan; 3967 __le16 l2_ivlan_mask; 3968 u8 unused_2; 3969 u8 unused_3; 3970 u8 t_l2_addr[6]; 3971 u8 unused_4; 3972 u8 unused_5; 3973 u8 t_l2_addr_mask[6]; 3974 __le16 t_l2_ovlan; 3975 __le16 t_l2_ovlan_mask; 3976 __le16 t_l2_ivlan; 3977 __le16 t_l2_ivlan_mask; 3978 u8 src_type; 3979 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3980 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3981 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3982 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3983 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3984 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3985 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3986 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3987 u8 unused_6; 3988 __le32 src_id; 3989 u8 tunnel_type; 3990 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3991 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3992 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3993 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3994 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3995 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3996 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3997 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3998 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3999 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4000 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4001 u8 unused_7; 4002 __le16 dst_id; 4003 __le16 mirror_vnic_id; 4004 u8 pri_hint; 4005 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4006 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 4007 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 4008 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4009 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4010 u8 unused_8; 4011 __le32 unused_9; 4012 __le64 l2_filter_id_hint; 4013 }; 4014 4015 /* Output (24 bytes) */ 4016 struct hwrm_cfa_l2_filter_alloc_output { 4017 __le16 error_code; 4018 __le16 req_type; 4019 __le16 seq_id; 4020 __le16 resp_len; 4021 __le64 l2_filter_id; 4022 __le32 flow_id; 4023 u8 unused_0; 4024 u8 unused_1; 4025 u8 unused_2; 4026 u8 valid; 4027 }; 4028 4029 /* hwrm_cfa_l2_filter_free */ 4030 /* Input (24 bytes) */ 4031 struct hwrm_cfa_l2_filter_free_input { 4032 __le16 req_type; 4033 __le16 cmpl_ring; 4034 __le16 seq_id; 4035 __le16 target_id; 4036 __le64 resp_addr; 4037 __le64 l2_filter_id; 4038 }; 4039 4040 /* Output (16 bytes) */ 4041 struct hwrm_cfa_l2_filter_free_output { 4042 __le16 error_code; 4043 __le16 req_type; 4044 __le16 seq_id; 4045 __le16 resp_len; 4046 __le32 unused_0; 4047 u8 unused_1; 4048 u8 unused_2; 4049 u8 unused_3; 4050 u8 valid; 4051 }; 4052 4053 /* hwrm_cfa_l2_filter_cfg */ 4054 /* Input (40 bytes) */ 4055 struct hwrm_cfa_l2_filter_cfg_input { 4056 __le16 req_type; 4057 __le16 cmpl_ring; 4058 __le16 seq_id; 4059 __le16 target_id; 4060 __le64 resp_addr; 4061 __le32 flags; 4062 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 4063 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 4064 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 4065 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 4066 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 4067 __le32 enables; 4068 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 4069 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4070 __le64 l2_filter_id; 4071 __le32 dst_id; 4072 __le32 new_mirror_vnic_id; 4073 }; 4074 4075 /* Output (16 bytes) */ 4076 struct hwrm_cfa_l2_filter_cfg_output { 4077 __le16 error_code; 4078 __le16 req_type; 4079 __le16 seq_id; 4080 __le16 resp_len; 4081 __le32 unused_0; 4082 u8 unused_1; 4083 u8 unused_2; 4084 u8 unused_3; 4085 u8 valid; 4086 }; 4087 4088 /* hwrm_cfa_l2_set_rx_mask */ 4089 /* Input (56 bytes) */ 4090 struct hwrm_cfa_l2_set_rx_mask_input { 4091 __le16 req_type; 4092 __le16 cmpl_ring; 4093 __le16 seq_id; 4094 __le16 target_id; 4095 __le64 resp_addr; 4096 __le32 vnic_id; 4097 __le32 mask; 4098 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 4099 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 4100 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 4101 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 4102 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 4103 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 4104 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 4105 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 4106 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 4107 __le64 mc_tbl_addr; 4108 __le32 num_mc_entries; 4109 __le32 unused_0; 4110 __le64 vlan_tag_tbl_addr; 4111 __le32 num_vlan_tags; 4112 __le32 unused_1; 4113 }; 4114 4115 /* Output (16 bytes) */ 4116 struct hwrm_cfa_l2_set_rx_mask_output { 4117 __le16 error_code; 4118 __le16 req_type; 4119 __le16 seq_id; 4120 __le16 resp_len; 4121 __le32 unused_0; 4122 u8 unused_1; 4123 u8 unused_2; 4124 u8 unused_3; 4125 u8 valid; 4126 }; 4127 4128 /* Command specific Error Codes (8 bytes) */ 4129 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 4130 u8 code; 4131 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 4132 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 4133 u8 unused_0[7]; 4134 }; 4135 4136 /* hwrm_cfa_tunnel_filter_alloc */ 4137 /* Input (88 bytes) */ 4138 struct hwrm_cfa_tunnel_filter_alloc_input { 4139 __le16 req_type; 4140 __le16 cmpl_ring; 4141 __le16 seq_id; 4142 __le16 target_id; 4143 __le64 resp_addr; 4144 __le32 flags; 4145 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4146 __le32 enables; 4147 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4148 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 4149 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 4150 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 4151 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 4152 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 4153 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 4154 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 4155 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 4156 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 4157 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 4158 __le64 l2_filter_id; 4159 u8 l2_addr[6]; 4160 __le16 l2_ivlan; 4161 __le32 l3_addr[4]; 4162 __le32 t_l3_addr[4]; 4163 u8 l3_addr_type; 4164 u8 t_l3_addr_type; 4165 u8 tunnel_type; 4166 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4167 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4168 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4169 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4170 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4171 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4172 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4173 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4174 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4175 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4176 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4177 u8 unused_0; 4178 __le32 vni; 4179 __le32 dst_vnic_id; 4180 __le32 mirror_vnic_id; 4181 }; 4182 4183 /* Output (24 bytes) */ 4184 struct hwrm_cfa_tunnel_filter_alloc_output { 4185 __le16 error_code; 4186 __le16 req_type; 4187 __le16 seq_id; 4188 __le16 resp_len; 4189 __le64 tunnel_filter_id; 4190 __le32 flow_id; 4191 u8 unused_0; 4192 u8 unused_1; 4193 u8 unused_2; 4194 u8 valid; 4195 }; 4196 4197 /* hwrm_cfa_tunnel_filter_free */ 4198 /* Input (24 bytes) */ 4199 struct hwrm_cfa_tunnel_filter_free_input { 4200 __le16 req_type; 4201 __le16 cmpl_ring; 4202 __le16 seq_id; 4203 __le16 target_id; 4204 __le64 resp_addr; 4205 __le64 tunnel_filter_id; 4206 }; 4207 4208 /* Output (16 bytes) */ 4209 struct hwrm_cfa_tunnel_filter_free_output { 4210 __le16 error_code; 4211 __le16 req_type; 4212 __le16 seq_id; 4213 __le16 resp_len; 4214 __le32 unused_0; 4215 u8 unused_1; 4216 u8 unused_2; 4217 u8 unused_3; 4218 u8 valid; 4219 }; 4220 4221 /* hwrm_cfa_encap_record_alloc */ 4222 /* Input (32 bytes) */ 4223 struct hwrm_cfa_encap_record_alloc_input { 4224 __le16 req_type; 4225 __le16 cmpl_ring; 4226 __le16 seq_id; 4227 __le16 target_id; 4228 __le64 resp_addr; 4229 __le32 flags; 4230 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4231 u8 encap_type; 4232 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4233 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4234 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4235 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4236 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4237 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4238 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4239 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4240 u8 unused_0; 4241 __le16 unused_1; 4242 __le32 encap_data[20]; 4243 }; 4244 4245 /* Output (16 bytes) */ 4246 struct hwrm_cfa_encap_record_alloc_output { 4247 __le16 error_code; 4248 __le16 req_type; 4249 __le16 seq_id; 4250 __le16 resp_len; 4251 __le32 encap_record_id; 4252 u8 unused_0; 4253 u8 unused_1; 4254 u8 unused_2; 4255 u8 valid; 4256 }; 4257 4258 /* hwrm_cfa_encap_record_free */ 4259 /* Input (24 bytes) */ 4260 struct hwrm_cfa_encap_record_free_input { 4261 __le16 req_type; 4262 __le16 cmpl_ring; 4263 __le16 seq_id; 4264 __le16 target_id; 4265 __le64 resp_addr; 4266 __le32 encap_record_id; 4267 __le32 unused_0; 4268 }; 4269 4270 /* Output (16 bytes) */ 4271 struct hwrm_cfa_encap_record_free_output { 4272 __le16 error_code; 4273 __le16 req_type; 4274 __le16 seq_id; 4275 __le16 resp_len; 4276 __le32 unused_0; 4277 u8 unused_1; 4278 u8 unused_2; 4279 u8 unused_3; 4280 u8 valid; 4281 }; 4282 4283 /* hwrm_cfa_ntuple_filter_alloc */ 4284 /* Input (128 bytes) */ 4285 struct hwrm_cfa_ntuple_filter_alloc_input { 4286 __le16 req_type; 4287 __le16 cmpl_ring; 4288 __le16 seq_id; 4289 __le16 target_id; 4290 __le64 resp_addr; 4291 __le32 flags; 4292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4293 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4295 __le32 enables; 4296 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4297 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4303 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4304 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4305 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4306 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4309 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4310 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4314 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4315 __le64 l2_filter_id; 4316 u8 src_macaddr[6]; 4317 __be16 ethertype; 4318 u8 ip_addr_type; 4319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4322 u8 ip_protocol; 4323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4325 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4326 __le16 dst_id; 4327 __le16 mirror_vnic_id; 4328 u8 tunnel_type; 4329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4333 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4334 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4335 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4336 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4337 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4338 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4339 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4340 u8 pri_hint; 4341 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4342 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4343 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4344 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4345 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4346 __be32 src_ipaddr[4]; 4347 __be32 src_ipaddr_mask[4]; 4348 __be32 dst_ipaddr[4]; 4349 __be32 dst_ipaddr_mask[4]; 4350 __be16 src_port; 4351 __be16 src_port_mask; 4352 __be16 dst_port; 4353 __be16 dst_port_mask; 4354 __le64 ntuple_filter_id_hint; 4355 }; 4356 4357 /* Output (24 bytes) */ 4358 struct hwrm_cfa_ntuple_filter_alloc_output { 4359 __le16 error_code; 4360 __le16 req_type; 4361 __le16 seq_id; 4362 __le16 resp_len; 4363 __le64 ntuple_filter_id; 4364 __le32 flow_id; 4365 u8 unused_0; 4366 u8 unused_1; 4367 u8 unused_2; 4368 u8 valid; 4369 }; 4370 4371 /* Command specific Error Codes (8 bytes) */ 4372 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 4373 u8 code; 4374 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 4375 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 4376 u8 unused_0[7]; 4377 }; 4378 4379 /* hwrm_cfa_ntuple_filter_free */ 4380 /* Input (24 bytes) */ 4381 struct hwrm_cfa_ntuple_filter_free_input { 4382 __le16 req_type; 4383 __le16 cmpl_ring; 4384 __le16 seq_id; 4385 __le16 target_id; 4386 __le64 resp_addr; 4387 __le64 ntuple_filter_id; 4388 }; 4389 4390 /* Output (16 bytes) */ 4391 struct hwrm_cfa_ntuple_filter_free_output { 4392 __le16 error_code; 4393 __le16 req_type; 4394 __le16 seq_id; 4395 __le16 resp_len; 4396 __le32 unused_0; 4397 u8 unused_1; 4398 u8 unused_2; 4399 u8 unused_3; 4400 u8 valid; 4401 }; 4402 4403 /* hwrm_cfa_ntuple_filter_cfg */ 4404 /* Input (48 bytes) */ 4405 struct hwrm_cfa_ntuple_filter_cfg_input { 4406 __le16 req_type; 4407 __le16 cmpl_ring; 4408 __le16 seq_id; 4409 __le16 target_id; 4410 __le64 resp_addr; 4411 __le32 enables; 4412 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4413 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4414 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4415 __le32 unused_0; 4416 __le64 ntuple_filter_id; 4417 __le32 new_dst_id; 4418 __le32 new_mirror_vnic_id; 4419 __le16 new_meter_instance_id; 4420 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4421 __le16 unused_1[3]; 4422 }; 4423 4424 /* Output (16 bytes) */ 4425 struct hwrm_cfa_ntuple_filter_cfg_output { 4426 __le16 error_code; 4427 __le16 req_type; 4428 __le16 seq_id; 4429 __le16 resp_len; 4430 __le32 unused_0; 4431 u8 unused_1; 4432 u8 unused_2; 4433 u8 unused_3; 4434 u8 valid; 4435 }; 4436 4437 /* hwrm_cfa_decap_filter_alloc */ 4438 /* Input (104 bytes) */ 4439 struct hwrm_cfa_decap_filter_alloc_input { 4440 __le16 req_type; 4441 __le16 cmpl_ring; 4442 __le16 seq_id; 4443 __le16 target_id; 4444 __le64 resp_addr; 4445 __le32 flags; 4446 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 4447 __le32 enables; 4448 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 4449 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 4450 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 4451 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 4452 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 4453 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 4454 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 4455 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 4456 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 4457 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 4458 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 4459 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 4460 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 4461 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 4462 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 4463 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4464 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4465 __be32 tunnel_id; 4466 u8 tunnel_type; 4467 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4468 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4469 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4470 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4471 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4472 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4473 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4474 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4475 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4476 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4477 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4478 u8 unused_0; 4479 __le16 unused_1; 4480 u8 src_macaddr[6]; 4481 u8 unused_2; 4482 u8 unused_3; 4483 u8 dst_macaddr[6]; 4484 __be16 ovlan_vid; 4485 __be16 ivlan_vid; 4486 __be16 t_ovlan_vid; 4487 __be16 t_ivlan_vid; 4488 __be16 ethertype; 4489 u8 ip_addr_type; 4490 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4491 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4492 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4493 u8 ip_protocol; 4494 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4495 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4496 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4497 u8 unused_4; 4498 u8 unused_5; 4499 u8 unused_6[3]; 4500 u8 unused_7; 4501 __be32 src_ipaddr[4]; 4502 __be32 dst_ipaddr[4]; 4503 __be16 src_port; 4504 __be16 dst_port; 4505 __le16 dst_id; 4506 __le16 l2_ctxt_ref_id; 4507 }; 4508 4509 /* Output (16 bytes) */ 4510 struct hwrm_cfa_decap_filter_alloc_output { 4511 __le16 error_code; 4512 __le16 req_type; 4513 __le16 seq_id; 4514 __le16 resp_len; 4515 __le32 decap_filter_id; 4516 u8 unused_0; 4517 u8 unused_1; 4518 u8 unused_2; 4519 u8 valid; 4520 }; 4521 4522 /* hwrm_cfa_decap_filter_free */ 4523 /* Input (24 bytes) */ 4524 struct hwrm_cfa_decap_filter_free_input { 4525 __le16 req_type; 4526 __le16 cmpl_ring; 4527 __le16 seq_id; 4528 __le16 target_id; 4529 __le64 resp_addr; 4530 __le32 decap_filter_id; 4531 __le32 unused_0; 4532 }; 4533 4534 /* Output (16 bytes) */ 4535 struct hwrm_cfa_decap_filter_free_output { 4536 __le16 error_code; 4537 __le16 req_type; 4538 __le16 seq_id; 4539 __le16 resp_len; 4540 __le32 unused_0; 4541 u8 unused_1; 4542 u8 unused_2; 4543 u8 unused_3; 4544 u8 valid; 4545 }; 4546 4547 /* hwrm_cfa_flow_alloc */ 4548 /* Input (128 bytes) */ 4549 struct hwrm_cfa_flow_alloc_input { 4550 __le16 req_type; 4551 __le16 cmpl_ring; 4552 __le16 seq_id; 4553 __le16 target_id; 4554 __le64 resp_addr; 4555 __le16 flags; 4556 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 4557 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 4558 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 4559 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 4560 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 4561 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 4562 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 4563 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 4564 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 4565 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 4566 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 4567 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 4568 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 4569 __le16 src_fid; 4570 __le32 tunnel_handle; 4571 __le16 action_flags; 4572 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 4573 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 4574 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 4575 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 4576 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 4577 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 4578 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 4579 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 4580 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 4581 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 4582 __le16 dst_fid; 4583 __be16 l2_rewrite_vlan_tpid; 4584 __be16 l2_rewrite_vlan_tci; 4585 __le16 act_meter_id; 4586 __le16 ref_flow_handle; 4587 __be16 ethertype; 4588 __be16 outer_vlan_tci; 4589 __be16 dmac[3]; 4590 __be16 inner_vlan_tci; 4591 __be16 smac[3]; 4592 u8 ip_dst_mask_len; 4593 u8 ip_src_mask_len; 4594 __be32 ip_dst[4]; 4595 __be32 ip_src[4]; 4596 __be16 l4_src_port; 4597 __be16 l4_src_port_mask; 4598 __be16 l4_dst_port; 4599 __be16 l4_dst_port_mask; 4600 __be32 nat_ip_address[4]; 4601 __be16 l2_rewrite_dmac[3]; 4602 __be16 nat_port; 4603 __be16 l2_rewrite_smac[3]; 4604 u8 ip_proto; 4605 u8 unused_0; 4606 }; 4607 4608 /* Output (16 bytes) */ 4609 struct hwrm_cfa_flow_alloc_output { 4610 __le16 error_code; 4611 __le16 req_type; 4612 __le16 seq_id; 4613 __le16 resp_len; 4614 __le16 flow_handle; 4615 u8 unused_0; 4616 u8 unused_1; 4617 u8 unused_2; 4618 u8 unused_3; 4619 u8 unused_4; 4620 u8 valid; 4621 }; 4622 4623 /* hwrm_cfa_flow_free */ 4624 /* Input (24 bytes) */ 4625 struct hwrm_cfa_flow_free_input { 4626 __le16 req_type; 4627 __le16 cmpl_ring; 4628 __le16 seq_id; 4629 __le16 target_id; 4630 __le64 resp_addr; 4631 __le16 flow_handle; 4632 __le16 unused_0[3]; 4633 }; 4634 4635 /* Output (32 bytes) */ 4636 struct hwrm_cfa_flow_free_output { 4637 __le16 error_code; 4638 __le16 req_type; 4639 __le16 seq_id; 4640 __le16 resp_len; 4641 __le64 packet; 4642 __le64 byte; 4643 __le32 unused_0; 4644 u8 unused_1; 4645 u8 unused_2; 4646 u8 unused_3; 4647 u8 valid; 4648 }; 4649 4650 /* hwrm_cfa_flow_stats */ 4651 /* Input (40 bytes) */ 4652 struct hwrm_cfa_flow_stats_input { 4653 __le16 req_type; 4654 __le16 cmpl_ring; 4655 __le16 seq_id; 4656 __le16 target_id; 4657 __le64 resp_addr; 4658 __le16 num_flows; 4659 __le16 flow_handle_0; 4660 __le16 flow_handle_1; 4661 __le16 flow_handle_2; 4662 __le16 flow_handle_3; 4663 __le16 flow_handle_4; 4664 __le16 flow_handle_5; 4665 __le16 flow_handle_6; 4666 __le16 flow_handle_7; 4667 __le16 flow_handle_8; 4668 __le16 flow_handle_9; 4669 __le16 unused_0; 4670 }; 4671 4672 /* Output (176 bytes) */ 4673 struct hwrm_cfa_flow_stats_output { 4674 __le16 error_code; 4675 __le16 req_type; 4676 __le16 seq_id; 4677 __le16 resp_len; 4678 __le64 packet_0; 4679 __le64 packet_1; 4680 __le64 packet_2; 4681 __le64 packet_3; 4682 __le64 packet_4; 4683 __le64 packet_5; 4684 __le64 packet_6; 4685 __le64 packet_7; 4686 __le64 packet_8; 4687 __le64 packet_9; 4688 __le64 byte_0; 4689 __le64 byte_1; 4690 __le64 byte_2; 4691 __le64 byte_3; 4692 __le64 byte_4; 4693 __le64 byte_5; 4694 __le64 byte_6; 4695 __le64 byte_7; 4696 __le64 byte_8; 4697 __le64 byte_9; 4698 __le32 unused_0; 4699 u8 unused_1; 4700 u8 unused_2; 4701 u8 unused_3; 4702 u8 valid; 4703 }; 4704 4705 /* hwrm_cfa_vfr_alloc */ 4706 /* Input (32 bytes) */ 4707 struct hwrm_cfa_vfr_alloc_input { 4708 __le16 req_type; 4709 __le16 cmpl_ring; 4710 __le16 seq_id; 4711 __le16 target_id; 4712 __le64 resp_addr; 4713 __le16 vf_id; 4714 __le16 reserved; 4715 __le32 unused_0; 4716 char vfr_name[32]; 4717 }; 4718 4719 /* Output (16 bytes) */ 4720 struct hwrm_cfa_vfr_alloc_output { 4721 __le16 error_code; 4722 __le16 req_type; 4723 __le16 seq_id; 4724 __le16 resp_len; 4725 __le16 rx_cfa_code; 4726 __le16 tx_cfa_action; 4727 u8 unused_0; 4728 u8 unused_1; 4729 u8 unused_2; 4730 u8 valid; 4731 }; 4732 4733 /* hwrm_cfa_vfr_free */ 4734 /* Input (24 bytes) */ 4735 struct hwrm_cfa_vfr_free_input { 4736 __le16 req_type; 4737 __le16 cmpl_ring; 4738 __le16 seq_id; 4739 __le16 target_id; 4740 __le64 resp_addr; 4741 char vfr_name[32]; 4742 }; 4743 4744 /* Output (16 bytes) */ 4745 struct hwrm_cfa_vfr_free_output { 4746 __le16 error_code; 4747 __le16 req_type; 4748 __le16 seq_id; 4749 __le16 resp_len; 4750 __le32 unused_0; 4751 u8 unused_1; 4752 u8 unused_2; 4753 u8 unused_3; 4754 u8 valid; 4755 }; 4756 4757 /* hwrm_tunnel_dst_port_query */ 4758 /* Input (24 bytes) */ 4759 struct hwrm_tunnel_dst_port_query_input { 4760 __le16 req_type; 4761 __le16 cmpl_ring; 4762 __le16 seq_id; 4763 __le16 target_id; 4764 __le64 resp_addr; 4765 u8 tunnel_type; 4766 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4767 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4768 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4769 u8 unused_0[7]; 4770 }; 4771 4772 /* Output (16 bytes) */ 4773 struct hwrm_tunnel_dst_port_query_output { 4774 __le16 error_code; 4775 __le16 req_type; 4776 __le16 seq_id; 4777 __le16 resp_len; 4778 __le16 tunnel_dst_port_id; 4779 __be16 tunnel_dst_port_val; 4780 u8 unused_0; 4781 u8 unused_1; 4782 u8 unused_2; 4783 u8 valid; 4784 }; 4785 4786 /* hwrm_tunnel_dst_port_alloc */ 4787 /* Input (24 bytes) */ 4788 struct hwrm_tunnel_dst_port_alloc_input { 4789 __le16 req_type; 4790 __le16 cmpl_ring; 4791 __le16 seq_id; 4792 __le16 target_id; 4793 __le64 resp_addr; 4794 u8 tunnel_type; 4795 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4796 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4797 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4798 u8 unused_0; 4799 __be16 tunnel_dst_port_val; 4800 __be32 unused_1; 4801 }; 4802 4803 /* Output (16 bytes) */ 4804 struct hwrm_tunnel_dst_port_alloc_output { 4805 __le16 error_code; 4806 __le16 req_type; 4807 __le16 seq_id; 4808 __le16 resp_len; 4809 __le16 tunnel_dst_port_id; 4810 u8 unused_0; 4811 u8 unused_1; 4812 u8 unused_2; 4813 u8 unused_3; 4814 u8 unused_4; 4815 u8 valid; 4816 }; 4817 4818 /* hwrm_tunnel_dst_port_free */ 4819 /* Input (24 bytes) */ 4820 struct hwrm_tunnel_dst_port_free_input { 4821 __le16 req_type; 4822 __le16 cmpl_ring; 4823 __le16 seq_id; 4824 __le16 target_id; 4825 __le64 resp_addr; 4826 u8 tunnel_type; 4827 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4828 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4829 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4830 u8 unused_0; 4831 __le16 tunnel_dst_port_id; 4832 __le32 unused_1; 4833 }; 4834 4835 /* Output (16 bytes) */ 4836 struct hwrm_tunnel_dst_port_free_output { 4837 __le16 error_code; 4838 __le16 req_type; 4839 __le16 seq_id; 4840 __le16 resp_len; 4841 __le32 unused_0; 4842 u8 unused_1; 4843 u8 unused_2; 4844 u8 unused_3; 4845 u8 valid; 4846 }; 4847 4848 /* hwrm_stat_ctx_alloc */ 4849 /* Input (32 bytes) */ 4850 struct hwrm_stat_ctx_alloc_input { 4851 __le16 req_type; 4852 __le16 cmpl_ring; 4853 __le16 seq_id; 4854 __le16 target_id; 4855 __le64 resp_addr; 4856 __le64 stats_dma_addr; 4857 __le32 update_period_ms; 4858 u8 stat_ctx_flags; 4859 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 4860 u8 unused_0[3]; 4861 }; 4862 4863 /* Output (16 bytes) */ 4864 struct hwrm_stat_ctx_alloc_output { 4865 __le16 error_code; 4866 __le16 req_type; 4867 __le16 seq_id; 4868 __le16 resp_len; 4869 __le32 stat_ctx_id; 4870 u8 unused_0; 4871 u8 unused_1; 4872 u8 unused_2; 4873 u8 valid; 4874 }; 4875 4876 /* hwrm_stat_ctx_free */ 4877 /* Input (24 bytes) */ 4878 struct hwrm_stat_ctx_free_input { 4879 __le16 req_type; 4880 __le16 cmpl_ring; 4881 __le16 seq_id; 4882 __le16 target_id; 4883 __le64 resp_addr; 4884 __le32 stat_ctx_id; 4885 __le32 unused_0; 4886 }; 4887 4888 /* Output (16 bytes) */ 4889 struct hwrm_stat_ctx_free_output { 4890 __le16 error_code; 4891 __le16 req_type; 4892 __le16 seq_id; 4893 __le16 resp_len; 4894 __le32 stat_ctx_id; 4895 u8 unused_0; 4896 u8 unused_1; 4897 u8 unused_2; 4898 u8 valid; 4899 }; 4900 4901 /* hwrm_stat_ctx_query */ 4902 /* Input (24 bytes) */ 4903 struct hwrm_stat_ctx_query_input { 4904 __le16 req_type; 4905 __le16 cmpl_ring; 4906 __le16 seq_id; 4907 __le16 target_id; 4908 __le64 resp_addr; 4909 __le32 stat_ctx_id; 4910 __le32 unused_0; 4911 }; 4912 4913 /* Output (176 bytes) */ 4914 struct hwrm_stat_ctx_query_output { 4915 __le16 error_code; 4916 __le16 req_type; 4917 __le16 seq_id; 4918 __le16 resp_len; 4919 __le64 tx_ucast_pkts; 4920 __le64 tx_mcast_pkts; 4921 __le64 tx_bcast_pkts; 4922 __le64 tx_err_pkts; 4923 __le64 tx_drop_pkts; 4924 __le64 tx_ucast_bytes; 4925 __le64 tx_mcast_bytes; 4926 __le64 tx_bcast_bytes; 4927 __le64 rx_ucast_pkts; 4928 __le64 rx_mcast_pkts; 4929 __le64 rx_bcast_pkts; 4930 __le64 rx_err_pkts; 4931 __le64 rx_drop_pkts; 4932 __le64 rx_ucast_bytes; 4933 __le64 rx_mcast_bytes; 4934 __le64 rx_bcast_bytes; 4935 __le64 rx_agg_pkts; 4936 __le64 rx_agg_bytes; 4937 __le64 rx_agg_events; 4938 __le64 rx_agg_aborts; 4939 __le32 unused_0; 4940 u8 unused_1; 4941 u8 unused_2; 4942 u8 unused_3; 4943 u8 valid; 4944 }; 4945 4946 /* hwrm_stat_ctx_clr_stats */ 4947 /* Input (24 bytes) */ 4948 struct hwrm_stat_ctx_clr_stats_input { 4949 __le16 req_type; 4950 __le16 cmpl_ring; 4951 __le16 seq_id; 4952 __le16 target_id; 4953 __le64 resp_addr; 4954 __le32 stat_ctx_id; 4955 __le32 unused_0; 4956 }; 4957 4958 /* Output (16 bytes) */ 4959 struct hwrm_stat_ctx_clr_stats_output { 4960 __le16 error_code; 4961 __le16 req_type; 4962 __le16 seq_id; 4963 __le16 resp_len; 4964 __le32 unused_0; 4965 u8 unused_1; 4966 u8 unused_2; 4967 u8 unused_3; 4968 u8 valid; 4969 }; 4970 4971 /* hwrm_fw_reset */ 4972 /* Input (24 bytes) */ 4973 struct hwrm_fw_reset_input { 4974 __le16 req_type; 4975 __le16 cmpl_ring; 4976 __le16 seq_id; 4977 __le16 target_id; 4978 __le64 resp_addr; 4979 u8 embedded_proc_type; 4980 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4981 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4982 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4983 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4984 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 4985 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 4986 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 4987 u8 selfrst_status; 4988 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 4989 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 4990 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4991 u8 host_idx; 4992 u8 unused_0[5]; 4993 }; 4994 4995 /* Output (16 bytes) */ 4996 struct hwrm_fw_reset_output { 4997 __le16 error_code; 4998 __le16 req_type; 4999 __le16 seq_id; 5000 __le16 resp_len; 5001 u8 selfrst_status; 5002 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5003 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5004 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5005 u8 unused_0; 5006 __le16 unused_1; 5007 u8 unused_2; 5008 u8 unused_3; 5009 u8 unused_4; 5010 u8 valid; 5011 }; 5012 5013 /* hwrm_fw_qstatus */ 5014 /* Input (24 bytes) */ 5015 struct hwrm_fw_qstatus_input { 5016 __le16 req_type; 5017 __le16 cmpl_ring; 5018 __le16 seq_id; 5019 __le16 target_id; 5020 __le64 resp_addr; 5021 u8 embedded_proc_type; 5022 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5023 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5024 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5025 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5026 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5027 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5028 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5029 u8 unused_0[7]; 5030 }; 5031 5032 /* Output (16 bytes) */ 5033 struct hwrm_fw_qstatus_output { 5034 __le16 error_code; 5035 __le16 req_type; 5036 __le16 seq_id; 5037 __le16 resp_len; 5038 u8 selfrst_status; 5039 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5040 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5041 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5042 u8 unused_0; 5043 __le16 unused_1; 5044 u8 unused_2; 5045 u8 unused_3; 5046 u8 unused_4; 5047 u8 valid; 5048 }; 5049 5050 /* hwrm_fw_set_time */ 5051 /* Input (32 bytes) */ 5052 struct hwrm_fw_set_time_input { 5053 __le16 req_type; 5054 __le16 cmpl_ring; 5055 __le16 seq_id; 5056 __le16 target_id; 5057 __le64 resp_addr; 5058 __le16 year; 5059 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 5060 u8 month; 5061 u8 day; 5062 u8 hour; 5063 u8 minute; 5064 u8 second; 5065 u8 unused_0; 5066 __le16 millisecond; 5067 __le16 zone; 5068 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 5069 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 5070 __le32 unused_1; 5071 }; 5072 5073 /* Output (16 bytes) */ 5074 struct hwrm_fw_set_time_output { 5075 __le16 error_code; 5076 __le16 req_type; 5077 __le16 seq_id; 5078 __le16 resp_len; 5079 __le32 unused_0; 5080 u8 unused_1; 5081 u8 unused_2; 5082 u8 unused_3; 5083 u8 valid; 5084 }; 5085 5086 /* hwrm_fw_set_structured_data */ 5087 /* Input (32 bytes) */ 5088 struct hwrm_fw_set_structured_data_input { 5089 __le16 req_type; 5090 __le16 cmpl_ring; 5091 __le16 seq_id; 5092 __le16 target_id; 5093 __le64 resp_addr; 5094 __le64 src_data_addr; 5095 __le16 data_len; 5096 u8 hdr_cnt; 5097 u8 unused_0[5]; 5098 }; 5099 5100 /* Output (16 bytes) */ 5101 struct hwrm_fw_set_structured_data_output { 5102 __le16 error_code; 5103 __le16 req_type; 5104 __le16 seq_id; 5105 __le16 resp_len; 5106 __le32 unused_0; 5107 u8 unused_1; 5108 u8 unused_2; 5109 u8 unused_3; 5110 u8 valid; 5111 }; 5112 5113 /* Command specific Error Codes (8 bytes) */ 5114 struct hwrm_fw_set_structured_data_cmd_err { 5115 u8 code; 5116 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5117 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 5118 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 5119 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5120 u8 unused_0[7]; 5121 }; 5122 5123 /* hwrm_fw_get_structured_data */ 5124 /* Input (32 bytes) */ 5125 struct hwrm_fw_get_structured_data_input { 5126 __le16 req_type; 5127 __le16 cmpl_ring; 5128 __le16 seq_id; 5129 __le16 target_id; 5130 __le64 resp_addr; 5131 __le64 dest_data_addr; 5132 __le16 data_len; 5133 __le16 structure_id; 5134 __le16 subtype; 5135 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 5136 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 5137 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 5138 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 5139 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 5140 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 5141 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 5142 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 5143 u8 count; 5144 u8 unused_0; 5145 }; 5146 5147 /* Output (16 bytes) */ 5148 struct hwrm_fw_get_structured_data_output { 5149 __le16 error_code; 5150 __le16 req_type; 5151 __le16 seq_id; 5152 __le16 resp_len; 5153 u8 hdr_cnt; 5154 u8 unused_0; 5155 __le16 unused_1; 5156 u8 unused_2; 5157 u8 unused_3; 5158 u8 unused_4; 5159 u8 valid; 5160 }; 5161 5162 /* Command specific Error Codes (8 bytes) */ 5163 struct hwrm_fw_get_structured_data_cmd_err { 5164 u8 code; 5165 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5166 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5167 u8 unused_0[7]; 5168 }; 5169 5170 /* hwrm_exec_fwd_resp */ 5171 /* Input (128 bytes) */ 5172 struct hwrm_exec_fwd_resp_input { 5173 __le16 req_type; 5174 __le16 cmpl_ring; 5175 __le16 seq_id; 5176 __le16 target_id; 5177 __le64 resp_addr; 5178 __le32 encap_request[26]; 5179 __le16 encap_resp_target_id; 5180 __le16 unused_0[3]; 5181 }; 5182 5183 /* Output (16 bytes) */ 5184 struct hwrm_exec_fwd_resp_output { 5185 __le16 error_code; 5186 __le16 req_type; 5187 __le16 seq_id; 5188 __le16 resp_len; 5189 __le32 unused_0; 5190 u8 unused_1; 5191 u8 unused_2; 5192 u8 unused_3; 5193 u8 valid; 5194 }; 5195 5196 /* hwrm_reject_fwd_resp */ 5197 /* Input (128 bytes) */ 5198 struct hwrm_reject_fwd_resp_input { 5199 __le16 req_type; 5200 __le16 cmpl_ring; 5201 __le16 seq_id; 5202 __le16 target_id; 5203 __le64 resp_addr; 5204 __le32 encap_request[26]; 5205 __le16 encap_resp_target_id; 5206 __le16 unused_0[3]; 5207 }; 5208 5209 /* Output (16 bytes) */ 5210 struct hwrm_reject_fwd_resp_output { 5211 __le16 error_code; 5212 __le16 req_type; 5213 __le16 seq_id; 5214 __le16 resp_len; 5215 __le32 unused_0; 5216 u8 unused_1; 5217 u8 unused_2; 5218 u8 unused_3; 5219 u8 valid; 5220 }; 5221 5222 /* hwrm_fwd_resp */ 5223 /* Input (40 bytes) */ 5224 struct hwrm_fwd_resp_input { 5225 __le16 req_type; 5226 __le16 cmpl_ring; 5227 __le16 seq_id; 5228 __le16 target_id; 5229 __le64 resp_addr; 5230 __le16 encap_resp_target_id; 5231 __le16 encap_resp_cmpl_ring; 5232 __le16 encap_resp_len; 5233 u8 unused_0; 5234 u8 unused_1; 5235 __le64 encap_resp_addr; 5236 __le32 encap_resp[24]; 5237 }; 5238 5239 /* Output (16 bytes) */ 5240 struct hwrm_fwd_resp_output { 5241 __le16 error_code; 5242 __le16 req_type; 5243 __le16 seq_id; 5244 __le16 resp_len; 5245 __le32 unused_0; 5246 u8 unused_1; 5247 u8 unused_2; 5248 u8 unused_3; 5249 u8 valid; 5250 }; 5251 5252 /* hwrm_fwd_async_event_cmpl */ 5253 /* Input (32 bytes) */ 5254 struct hwrm_fwd_async_event_cmpl_input { 5255 __le16 req_type; 5256 __le16 cmpl_ring; 5257 __le16 seq_id; 5258 __le16 target_id; 5259 __le64 resp_addr; 5260 __le16 encap_async_event_target_id; 5261 u8 unused_0; 5262 u8 unused_1; 5263 u8 unused_2[3]; 5264 u8 unused_3; 5265 __le32 encap_async_event_cmpl[4]; 5266 }; 5267 5268 /* Output (16 bytes) */ 5269 struct hwrm_fwd_async_event_cmpl_output { 5270 __le16 error_code; 5271 __le16 req_type; 5272 __le16 seq_id; 5273 __le16 resp_len; 5274 __le32 unused_0; 5275 u8 unused_1; 5276 u8 unused_2; 5277 u8 unused_3; 5278 u8 valid; 5279 }; 5280 5281 /* hwrm_temp_monitor_query */ 5282 /* Input (16 bytes) */ 5283 struct hwrm_temp_monitor_query_input { 5284 __le16 req_type; 5285 __le16 cmpl_ring; 5286 __le16 seq_id; 5287 __le16 target_id; 5288 __le64 resp_addr; 5289 }; 5290 5291 /* Output (16 bytes) */ 5292 struct hwrm_temp_monitor_query_output { 5293 __le16 error_code; 5294 __le16 req_type; 5295 __le16 seq_id; 5296 __le16 resp_len; 5297 u8 temp; 5298 u8 unused_0; 5299 __le16 unused_1; 5300 u8 unused_2; 5301 u8 unused_3; 5302 u8 unused_4; 5303 u8 valid; 5304 }; 5305 5306 /* hwrm_wol_filter_alloc */ 5307 /* Input (64 bytes) */ 5308 struct hwrm_wol_filter_alloc_input { 5309 __le16 req_type; 5310 __le16 cmpl_ring; 5311 __le16 seq_id; 5312 __le16 target_id; 5313 __le64 resp_addr; 5314 __le32 flags; 5315 __le32 enables; 5316 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 5317 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 5318 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 5319 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 5320 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 5321 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 5322 __le16 port_id; 5323 u8 wol_type; 5324 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 5325 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 5326 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 5327 u8 unused_0; 5328 __le32 unused_1; 5329 u8 mac_address[6]; 5330 __le16 pattern_offset; 5331 __le16 pattern_buf_size; 5332 __le16 pattern_mask_size; 5333 __le32 unused_2; 5334 __le64 pattern_buf_addr; 5335 __le64 pattern_mask_addr; 5336 }; 5337 5338 /* Output (16 bytes) */ 5339 struct hwrm_wol_filter_alloc_output { 5340 __le16 error_code; 5341 __le16 req_type; 5342 __le16 seq_id; 5343 __le16 resp_len; 5344 u8 wol_filter_id; 5345 u8 unused_0; 5346 __le16 unused_1; 5347 u8 unused_2; 5348 u8 unused_3; 5349 u8 unused_4; 5350 u8 valid; 5351 }; 5352 5353 /* hwrm_wol_filter_free */ 5354 /* Input (32 bytes) */ 5355 struct hwrm_wol_filter_free_input { 5356 __le16 req_type; 5357 __le16 cmpl_ring; 5358 __le16 seq_id; 5359 __le16 target_id; 5360 __le64 resp_addr; 5361 __le32 flags; 5362 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 5363 __le32 enables; 5364 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 5365 __le16 port_id; 5366 u8 wol_filter_id; 5367 u8 unused_0[5]; 5368 }; 5369 5370 /* Output (16 bytes) */ 5371 struct hwrm_wol_filter_free_output { 5372 __le16 error_code; 5373 __le16 req_type; 5374 __le16 seq_id; 5375 __le16 resp_len; 5376 __le32 unused_0; 5377 u8 unused_1; 5378 u8 unused_2; 5379 u8 unused_3; 5380 u8 valid; 5381 }; 5382 5383 /* hwrm_wol_filter_qcfg */ 5384 /* Input (56 bytes) */ 5385 struct hwrm_wol_filter_qcfg_input { 5386 __le16 req_type; 5387 __le16 cmpl_ring; 5388 __le16 seq_id; 5389 __le16 target_id; 5390 __le64 resp_addr; 5391 __le16 port_id; 5392 __le16 handle; 5393 __le32 unused_0; 5394 __le64 pattern_buf_addr; 5395 __le16 pattern_buf_size; 5396 u8 unused_1; 5397 u8 unused_2; 5398 u8 unused_3[3]; 5399 u8 unused_4; 5400 __le64 pattern_mask_addr; 5401 __le16 pattern_mask_size; 5402 __le16 unused_5[3]; 5403 }; 5404 5405 /* Output (32 bytes) */ 5406 struct hwrm_wol_filter_qcfg_output { 5407 __le16 error_code; 5408 __le16 req_type; 5409 __le16 seq_id; 5410 __le16 resp_len; 5411 __le16 next_handle; 5412 u8 wol_filter_id; 5413 u8 wol_type; 5414 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 5415 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 5416 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 5417 __le32 unused_0; 5418 u8 mac_address[6]; 5419 __le16 pattern_offset; 5420 __le16 pattern_size; 5421 __le16 pattern_mask_size; 5422 u8 unused_1; 5423 u8 unused_2; 5424 u8 unused_3; 5425 u8 valid; 5426 }; 5427 5428 /* hwrm_wol_reason_qcfg */ 5429 /* Input (40 bytes) */ 5430 struct hwrm_wol_reason_qcfg_input { 5431 __le16 req_type; 5432 __le16 cmpl_ring; 5433 __le16 seq_id; 5434 __le16 target_id; 5435 __le64 resp_addr; 5436 __le16 port_id; 5437 u8 unused_0; 5438 u8 unused_1; 5439 u8 unused_2[3]; 5440 u8 unused_3; 5441 __le64 wol_pkt_buf_addr; 5442 __le16 wol_pkt_buf_size; 5443 __le16 unused_4[3]; 5444 }; 5445 5446 /* Output (16 bytes) */ 5447 struct hwrm_wol_reason_qcfg_output { 5448 __le16 error_code; 5449 __le16 req_type; 5450 __le16 seq_id; 5451 __le16 resp_len; 5452 u8 wol_filter_id; 5453 u8 wol_reason; 5454 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 5455 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 5456 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 5457 u8 wol_pkt_len; 5458 u8 unused_0; 5459 u8 unused_1; 5460 u8 unused_2; 5461 u8 unused_3; 5462 u8 valid; 5463 }; 5464 5465 /* hwrm_dbg_read_direct */ 5466 /* Input (32 bytes) */ 5467 struct hwrm_dbg_read_direct_input { 5468 __le16 req_type; 5469 __le16 cmpl_ring; 5470 __le16 seq_id; 5471 __le16 target_id; 5472 __le64 resp_addr; 5473 __le64 host_dest_addr; 5474 __le32 read_addr; 5475 __le32 read_len32; 5476 }; 5477 5478 /* Output (16 bytes) */ 5479 struct hwrm_dbg_read_direct_output { 5480 __le16 error_code; 5481 __le16 req_type; 5482 __le16 seq_id; 5483 __le16 resp_len; 5484 __le32 unused_0; 5485 u8 unused_1; 5486 u8 unused_2; 5487 u8 unused_3; 5488 u8 valid; 5489 }; 5490 5491 /* hwrm_nvm_read */ 5492 /* Input (40 bytes) */ 5493 struct hwrm_nvm_read_input { 5494 __le16 req_type; 5495 __le16 cmpl_ring; 5496 __le16 seq_id; 5497 __le16 target_id; 5498 __le64 resp_addr; 5499 __le64 host_dest_addr; 5500 __le16 dir_idx; 5501 u8 unused_0; 5502 u8 unused_1; 5503 __le32 offset; 5504 __le32 len; 5505 __le32 unused_2; 5506 }; 5507 5508 /* Output (16 bytes) */ 5509 struct hwrm_nvm_read_output { 5510 __le16 error_code; 5511 __le16 req_type; 5512 __le16 seq_id; 5513 __le16 resp_len; 5514 __le32 unused_0; 5515 u8 unused_1; 5516 u8 unused_2; 5517 u8 unused_3; 5518 u8 valid; 5519 }; 5520 5521 /* hwrm_nvm_get_dir_entries */ 5522 /* Input (24 bytes) */ 5523 struct hwrm_nvm_get_dir_entries_input { 5524 __le16 req_type; 5525 __le16 cmpl_ring; 5526 __le16 seq_id; 5527 __le16 target_id; 5528 __le64 resp_addr; 5529 __le64 host_dest_addr; 5530 }; 5531 5532 /* Output (16 bytes) */ 5533 struct hwrm_nvm_get_dir_entries_output { 5534 __le16 error_code; 5535 __le16 req_type; 5536 __le16 seq_id; 5537 __le16 resp_len; 5538 __le32 unused_0; 5539 u8 unused_1; 5540 u8 unused_2; 5541 u8 unused_3; 5542 u8 valid; 5543 }; 5544 5545 /* hwrm_nvm_get_dir_info */ 5546 /* Input (16 bytes) */ 5547 struct hwrm_nvm_get_dir_info_input { 5548 __le16 req_type; 5549 __le16 cmpl_ring; 5550 __le16 seq_id; 5551 __le16 target_id; 5552 __le64 resp_addr; 5553 }; 5554 5555 /* Output (24 bytes) */ 5556 struct hwrm_nvm_get_dir_info_output { 5557 __le16 error_code; 5558 __le16 req_type; 5559 __le16 seq_id; 5560 __le16 resp_len; 5561 __le32 entries; 5562 __le32 entry_length; 5563 __le32 unused_0; 5564 u8 unused_1; 5565 u8 unused_2; 5566 u8 unused_3; 5567 u8 valid; 5568 }; 5569 5570 /* hwrm_nvm_write */ 5571 /* Input (48 bytes) */ 5572 struct hwrm_nvm_write_input { 5573 __le16 req_type; 5574 __le16 cmpl_ring; 5575 __le16 seq_id; 5576 __le16 target_id; 5577 __le64 resp_addr; 5578 __le64 host_src_addr; 5579 __le16 dir_type; 5580 __le16 dir_ordinal; 5581 __le16 dir_ext; 5582 __le16 dir_attr; 5583 __le32 dir_data_length; 5584 __le16 option; 5585 __le16 flags; 5586 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5587 __le32 dir_item_length; 5588 __le32 unused_0; 5589 }; 5590 5591 /* Output (16 bytes) */ 5592 struct hwrm_nvm_write_output { 5593 __le16 error_code; 5594 __le16 req_type; 5595 __le16 seq_id; 5596 __le16 resp_len; 5597 __le32 dir_item_length; 5598 __le16 dir_idx; 5599 u8 unused_0; 5600 u8 valid; 5601 }; 5602 5603 /* Command specific Error Codes (8 bytes) */ 5604 struct hwrm_nvm_write_cmd_err { 5605 u8 code; 5606 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 5607 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5608 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 5609 u8 unused_0[7]; 5610 }; 5611 5612 /* hwrm_nvm_modify */ 5613 /* Input (40 bytes) */ 5614 struct hwrm_nvm_modify_input { 5615 __le16 req_type; 5616 __le16 cmpl_ring; 5617 __le16 seq_id; 5618 __le16 target_id; 5619 __le64 resp_addr; 5620 __le64 host_src_addr; 5621 __le16 dir_idx; 5622 u8 unused_0; 5623 u8 unused_1; 5624 __le32 offset; 5625 __le32 len; 5626 __le32 unused_2; 5627 }; 5628 5629 /* Output (16 bytes) */ 5630 struct hwrm_nvm_modify_output { 5631 __le16 error_code; 5632 __le16 req_type; 5633 __le16 seq_id; 5634 __le16 resp_len; 5635 __le32 unused_0; 5636 u8 unused_1; 5637 u8 unused_2; 5638 u8 unused_3; 5639 u8 valid; 5640 }; 5641 5642 /* hwrm_nvm_find_dir_entry */ 5643 /* Input (32 bytes) */ 5644 struct hwrm_nvm_find_dir_entry_input { 5645 __le16 req_type; 5646 __le16 cmpl_ring; 5647 __le16 seq_id; 5648 __le16 target_id; 5649 __le64 resp_addr; 5650 __le32 enables; 5651 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 5652 __le16 dir_idx; 5653 __le16 dir_type; 5654 __le16 dir_ordinal; 5655 __le16 dir_ext; 5656 u8 opt_ordinal; 5657 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 5658 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 5659 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 5660 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 5661 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 5662 u8 unused_1[3]; 5663 }; 5664 5665 /* Output (32 bytes) */ 5666 struct hwrm_nvm_find_dir_entry_output { 5667 __le16 error_code; 5668 __le16 req_type; 5669 __le16 seq_id; 5670 __le16 resp_len; 5671 __le32 dir_item_length; 5672 __le32 dir_data_length; 5673 __le32 fw_ver; 5674 __le16 dir_ordinal; 5675 __le16 dir_idx; 5676 __le32 unused_0; 5677 u8 unused_1; 5678 u8 unused_2; 5679 u8 unused_3; 5680 u8 valid; 5681 }; 5682 5683 /* hwrm_nvm_erase_dir_entry */ 5684 /* Input (24 bytes) */ 5685 struct hwrm_nvm_erase_dir_entry_input { 5686 __le16 req_type; 5687 __le16 cmpl_ring; 5688 __le16 seq_id; 5689 __le16 target_id; 5690 __le64 resp_addr; 5691 __le16 dir_idx; 5692 __le16 unused_0[3]; 5693 }; 5694 5695 /* Output (16 bytes) */ 5696 struct hwrm_nvm_erase_dir_entry_output { 5697 __le16 error_code; 5698 __le16 req_type; 5699 __le16 seq_id; 5700 __le16 resp_len; 5701 __le32 unused_0; 5702 u8 unused_1; 5703 u8 unused_2; 5704 u8 unused_3; 5705 u8 valid; 5706 }; 5707 5708 /* hwrm_nvm_get_dev_info */ 5709 /* Input (16 bytes) */ 5710 struct hwrm_nvm_get_dev_info_input { 5711 __le16 req_type; 5712 __le16 cmpl_ring; 5713 __le16 seq_id; 5714 __le16 target_id; 5715 __le64 resp_addr; 5716 }; 5717 5718 /* Output (32 bytes) */ 5719 struct hwrm_nvm_get_dev_info_output { 5720 __le16 error_code; 5721 __le16 req_type; 5722 __le16 seq_id; 5723 __le16 resp_len; 5724 __le16 manufacturer_id; 5725 __le16 device_id; 5726 __le32 sector_size; 5727 __le32 nvram_size; 5728 __le32 reserved_size; 5729 __le32 available_size; 5730 u8 unused_0; 5731 u8 unused_1; 5732 u8 unused_2; 5733 u8 valid; 5734 }; 5735 5736 /* hwrm_nvm_mod_dir_entry */ 5737 /* Input (32 bytes) */ 5738 struct hwrm_nvm_mod_dir_entry_input { 5739 __le16 req_type; 5740 __le16 cmpl_ring; 5741 __le16 seq_id; 5742 __le16 target_id; 5743 __le64 resp_addr; 5744 __le32 enables; 5745 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 5746 __le16 dir_idx; 5747 __le16 dir_ordinal; 5748 __le16 dir_ext; 5749 __le16 dir_attr; 5750 __le32 checksum; 5751 }; 5752 5753 /* Output (16 bytes) */ 5754 struct hwrm_nvm_mod_dir_entry_output { 5755 __le16 error_code; 5756 __le16 req_type; 5757 __le16 seq_id; 5758 __le16 resp_len; 5759 __le32 unused_0; 5760 u8 unused_1; 5761 u8 unused_2; 5762 u8 unused_3; 5763 u8 valid; 5764 }; 5765 5766 /* hwrm_nvm_verify_update */ 5767 /* Input (24 bytes) */ 5768 struct hwrm_nvm_verify_update_input { 5769 __le16 req_type; 5770 __le16 cmpl_ring; 5771 __le16 seq_id; 5772 __le16 target_id; 5773 __le64 resp_addr; 5774 __le16 dir_type; 5775 __le16 dir_ordinal; 5776 __le16 dir_ext; 5777 __le16 unused_0; 5778 }; 5779 5780 /* Output (16 bytes) */ 5781 struct hwrm_nvm_verify_update_output { 5782 __le16 error_code; 5783 __le16 req_type; 5784 __le16 seq_id; 5785 __le16 resp_len; 5786 __le32 unused_0; 5787 u8 unused_1; 5788 u8 unused_2; 5789 u8 unused_3; 5790 u8 valid; 5791 }; 5792 5793 /* hwrm_nvm_install_update */ 5794 /* Input (24 bytes) */ 5795 struct hwrm_nvm_install_update_input { 5796 __le16 req_type; 5797 __le16 cmpl_ring; 5798 __le16 seq_id; 5799 __le16 target_id; 5800 __le64 resp_addr; 5801 __le32 install_type; 5802 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 5803 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 5804 __le16 flags; 5805 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 5806 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 5807 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 5808 __le16 unused_0; 5809 }; 5810 5811 /* Output (24 bytes) */ 5812 struct hwrm_nvm_install_update_output { 5813 __le16 error_code; 5814 __le16 req_type; 5815 __le16 seq_id; 5816 __le16 resp_len; 5817 __le64 installed_items; 5818 u8 result; 5819 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 5820 u8 problem_item; 5821 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 5822 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 5823 u8 reset_required; 5824 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 5825 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 5826 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 5827 u8 unused_0; 5828 u8 unused_1; 5829 u8 unused_2; 5830 u8 unused_3; 5831 u8 valid; 5832 }; 5833 5834 /* Command specific Error Codes (8 bytes) */ 5835 struct hwrm_nvm_install_update_cmd_err { 5836 u8 code; 5837 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 5838 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5839 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 5840 u8 unused_0[7]; 5841 }; 5842 5843 /* hwrm_nvm_get_variable */ 5844 /* Input (40 bytes) */ 5845 struct hwrm_nvm_get_variable_input { 5846 __le16 req_type; 5847 __le16 cmpl_ring; 5848 __le16 seq_id; 5849 __le16 target_id; 5850 __le64 resp_addr; 5851 __le64 dest_data_addr; 5852 __le16 data_len; 5853 __le16 option_num; 5854 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 5855 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 5856 __le16 dimensions; 5857 __le16 index_0; 5858 __le16 index_1; 5859 __le16 index_2; 5860 __le16 index_3; 5861 u8 flags; 5862 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 5863 u8 unused_0; 5864 }; 5865 5866 /* Output (16 bytes) */ 5867 struct hwrm_nvm_get_variable_output { 5868 __le16 error_code; 5869 __le16 req_type; 5870 __le16 seq_id; 5871 __le16 resp_len; 5872 __le16 data_len; 5873 __le16 option_num; 5874 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 5875 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 5876 u8 unused_0; 5877 u8 unused_1; 5878 u8 unused_2; 5879 u8 valid; 5880 }; 5881 5882 /* Command specific Error Codes (8 bytes) */ 5883 struct hwrm_nvm_get_variable_cmd_err { 5884 u8 code; 5885 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 5886 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 5887 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 5888 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 5889 u8 unused_0[7]; 5890 }; 5891 5892 /* hwrm_nvm_set_variable */ 5893 /* Input (40 bytes) */ 5894 struct hwrm_nvm_set_variable_input { 5895 __le16 req_type; 5896 __le16 cmpl_ring; 5897 __le16 seq_id; 5898 __le16 target_id; 5899 __le64 resp_addr; 5900 __le64 src_data_addr; 5901 __le16 data_len; 5902 __le16 option_num; 5903 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 5904 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 5905 __le16 dimensions; 5906 __le16 index_0; 5907 __le16 index_1; 5908 __le16 index_2; 5909 __le16 index_3; 5910 u8 flags; 5911 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 5912 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 5913 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 5914 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 5915 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 5916 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 5917 u8 unused_0; 5918 }; 5919 5920 /* Output (16 bytes) */ 5921 struct hwrm_nvm_set_variable_output { 5922 __le16 error_code; 5923 __le16 req_type; 5924 __le16 seq_id; 5925 __le16 resp_len; 5926 __le32 unused_0; 5927 u8 unused_1; 5928 u8 unused_2; 5929 u8 unused_3; 5930 u8 valid; 5931 }; 5932 5933 /* Command specific Error Codes (8 bytes) */ 5934 struct hwrm_nvm_set_variable_cmd_err { 5935 u8 code; 5936 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 5937 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 5938 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 5939 u8 unused_0[7]; 5940 }; 5941 5942 /* hwrm_selftest_qlist */ 5943 /* Input (16 bytes) */ 5944 struct hwrm_selftest_qlist_input { 5945 __le16 req_type; 5946 __le16 cmpl_ring; 5947 __le16 seq_id; 5948 __le16 target_id; 5949 __le64 resp_addr; 5950 }; 5951 5952 /* Output (280 bytes) */ 5953 struct hwrm_selftest_qlist_output { 5954 __le16 error_code; 5955 __le16 req_type; 5956 __le16 seq_id; 5957 __le16 resp_len; 5958 u8 num_tests; 5959 u8 available_tests; 5960 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 5961 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 5962 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 5963 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 5964 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 5965 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 5966 u8 offline_tests; 5967 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 5968 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 5969 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 5970 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 5971 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 5972 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 5973 u8 unused_0; 5974 __le16 test_timeout; 5975 u8 unused_1; 5976 u8 unused_2; 5977 char test0_name[32]; 5978 char test1_name[32]; 5979 char test2_name[32]; 5980 char test3_name[32]; 5981 char test4_name[32]; 5982 char test5_name[32]; 5983 char test6_name[32]; 5984 char test7_name[32]; 5985 __le32 unused_3; 5986 u8 unused_4; 5987 u8 unused_5; 5988 u8 unused_6; 5989 u8 valid; 5990 }; 5991 5992 /* hwrm_selftest_exec */ 5993 /* Input (24 bytes) */ 5994 struct hwrm_selftest_exec_input { 5995 __le16 req_type; 5996 __le16 cmpl_ring; 5997 __le16 seq_id; 5998 __le16 target_id; 5999 __le64 resp_addr; 6000 u8 flags; 6001 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 6002 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 6003 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 6004 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 6005 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 6006 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 6007 u8 unused_0[7]; 6008 }; 6009 6010 /* Output (16 bytes) */ 6011 struct hwrm_selftest_exec_output { 6012 __le16 error_code; 6013 __le16 req_type; 6014 __le16 seq_id; 6015 __le16 resp_len; 6016 u8 requested_tests; 6017 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 6018 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 6019 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 6020 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 6021 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 6022 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 6023 u8 test_success; 6024 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 6025 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 6026 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 6027 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 6028 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 6029 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 6030 u8 unused_0; 6031 u8 unused_1; 6032 u8 unused_2; 6033 u8 unused_3; 6034 u8 unused_4; 6035 u8 valid; 6036 }; 6037 6038 /* hwrm_selftest_irq */ 6039 /* Input (16 bytes) */ 6040 struct hwrm_selftest_irq_input { 6041 __le16 req_type; 6042 __le16 cmpl_ring; 6043 __le16 seq_id; 6044 __le16 target_id; 6045 __le64 resp_addr; 6046 }; 6047 6048 /* Output (16 bytes) */ 6049 struct hwrm_selftest_irq_output { 6050 __le16 error_code; 6051 __le16 req_type; 6052 __le16 seq_id; 6053 __le16 resp_len; 6054 __le32 unused_0; 6055 u8 unused_1; 6056 u8 unused_2; 6057 u8 unused_3; 6058 u8 valid; 6059 }; 6060 6061 /* hwrm_selftest_retrieve_serdes_data */ 6062 /* Input (32 bytes) */ 6063 struct hwrm_selftest_retrieve_serdes_data_input { 6064 __le16 req_type; 6065 __le16 cmpl_ring; 6066 __le16 seq_id; 6067 __le16 target_id; 6068 __le64 resp_addr; 6069 __le64 resp_data_addr; 6070 __le32 resp_data_offset; 6071 __le16 data_len; 6072 u8 flags; 6073 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_MASK 0xfUL 6074 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_UNUSED_TEST_SFT 0 6075 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 6076 #define SELFTEST_RETRIEVE_SERDES_DATA_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 6077 u8 unused_0; 6078 }; 6079 6080 /* Output (16 bytes) */ 6081 struct hwrm_selftest_retrieve_serdes_data_output { 6082 __le16 error_code; 6083 __le16 req_type; 6084 __le16 seq_id; 6085 __le16 resp_len; 6086 __le16 total_data_len; 6087 __le16 copied_data_len; 6088 u8 unused_0; 6089 u8 unused_1; 6090 u8 unused_2; 6091 u8 valid; 6092 }; 6093 6094 /* Hardware Resource Manager Specification */ 6095 /* Input (16 bytes) */ 6096 struct input { 6097 __le16 req_type; 6098 __le16 cmpl_ring; 6099 __le16 seq_id; 6100 __le16 target_id; 6101 __le64 resp_addr; 6102 }; 6103 6104 /* Output (8 bytes) */ 6105 struct output { 6106 __le16 error_code; 6107 __le16 req_type; 6108 __le16 seq_id; 6109 __le16 resp_len; 6110 }; 6111 6112 /* Short Command Structure (16 bytes) */ 6113 struct hwrm_short_input { 6114 __le16 req_type; 6115 __le16 signature; 6116 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 6117 __le16 unused_0; 6118 __le16 size; 6119 __le64 req_addr; 6120 }; 6121 6122 /* Command numbering (8 bytes) */ 6123 struct cmd_nums { 6124 __le16 req_type; 6125 #define HWRM_VER_GET (0x0UL) 6126 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 6127 #define HWRM_FUNC_VF_CFG (0xfUL) 6128 #define RESERVED1 (0x10UL) 6129 #define HWRM_FUNC_RESET (0x11UL) 6130 #define HWRM_FUNC_GETFID (0x12UL) 6131 #define HWRM_FUNC_VF_ALLOC (0x13UL) 6132 #define HWRM_FUNC_VF_FREE (0x14UL) 6133 #define HWRM_FUNC_QCAPS (0x15UL) 6134 #define HWRM_FUNC_QCFG (0x16UL) 6135 #define HWRM_FUNC_CFG (0x17UL) 6136 #define HWRM_FUNC_QSTATS (0x18UL) 6137 #define HWRM_FUNC_CLR_STATS (0x19UL) 6138 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 6139 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 6140 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 6141 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 6142 #define HWRM_FUNC_DRV_QVER (0x1eUL) 6143 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 6144 #define HWRM_PORT_PHY_CFG (0x20UL) 6145 #define HWRM_PORT_MAC_CFG (0x21UL) 6146 #define HWRM_PORT_TS_QUERY (0x22UL) 6147 #define HWRM_PORT_QSTATS (0x23UL) 6148 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 6149 #define HWRM_PORT_CLR_STATS (0x25UL) 6150 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 6151 #define HWRM_PORT_PHY_QCFG (0x27UL) 6152 #define HWRM_PORT_MAC_QCFG (0x28UL) 6153 #define HWRM_PORT_MAC_PTP_QCFG (0x29UL) 6154 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 6155 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 6156 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 6157 #define HWRM_PORT_LED_CFG (0x2dUL) 6158 #define HWRM_PORT_LED_QCFG (0x2eUL) 6159 #define HWRM_PORT_LED_QCAPS (0x2fUL) 6160 #define HWRM_QUEUE_QPORTCFG (0x30UL) 6161 #define HWRM_QUEUE_QCFG (0x31UL) 6162 #define HWRM_QUEUE_CFG (0x32UL) 6163 #define HWRM_FUNC_VLAN_CFG (0x33UL) 6164 #define HWRM_FUNC_VLAN_QCFG (0x34UL) 6165 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 6166 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 6167 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 6168 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 6169 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 6170 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 6171 #define HWRM_QUEUE_DSCP_QCAPS (0x3bUL) 6172 #define HWRM_QUEUE_DSCP2PRI_QCFG (0x3cUL) 6173 #define HWRM_QUEUE_DSCP2PRI_CFG (0x3dUL) 6174 #define HWRM_VNIC_ALLOC (0x40UL) 6175 #define HWRM_VNIC_FREE (0x41UL) 6176 #define HWRM_VNIC_CFG (0x42UL) 6177 #define HWRM_VNIC_QCFG (0x43UL) 6178 #define HWRM_VNIC_TPA_CFG (0x44UL) 6179 #define HWRM_VNIC_TPA_QCFG (0x45UL) 6180 #define HWRM_VNIC_RSS_CFG (0x46UL) 6181 #define HWRM_VNIC_RSS_QCFG (0x47UL) 6182 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 6183 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 6184 #define HWRM_VNIC_QCAPS (0x4aUL) 6185 #define HWRM_RING_ALLOC (0x50UL) 6186 #define HWRM_RING_FREE (0x51UL) 6187 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 6188 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 6189 #define HWRM_RING_RESET (0x5eUL) 6190 #define HWRM_RING_GRP_ALLOC (0x60UL) 6191 #define HWRM_RING_GRP_FREE (0x61UL) 6192 #define RESERVED5 (0x64UL) 6193 #define RESERVED6 (0x65UL) 6194 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 6195 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 6196 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 6197 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 6198 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 6199 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 6200 #define HWRM_CFA_VLAN_ANTISPOOF_CFG (0x94UL) 6201 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 6202 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 6203 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 6204 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 6205 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 6206 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 6207 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 6208 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 6209 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 6210 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 6211 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 6212 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 6213 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 6214 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 6215 #define HWRM_STAT_CTX_FREE (0xb1UL) 6216 #define HWRM_STAT_CTX_QUERY (0xb2UL) 6217 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 6218 #define HWRM_FW_RESET (0xc0UL) 6219 #define HWRM_FW_QSTATUS (0xc1UL) 6220 #define HWRM_FW_SET_TIME (0xc8UL) 6221 #define HWRM_FW_GET_TIME (0xc9UL) 6222 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 6223 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 6224 #define HWRM_FW_IPC_MAILBOX (0xccUL) 6225 #define HWRM_EXEC_FWD_RESP (0xd0UL) 6226 #define HWRM_REJECT_FWD_RESP (0xd1UL) 6227 #define HWRM_FWD_RESP (0xd2UL) 6228 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 6229 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 6230 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 6231 #define HWRM_WOL_FILTER_FREE (0xf1UL) 6232 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 6233 #define HWRM_WOL_REASON_QCFG (0xf3UL) 6234 #define HWRM_CFA_METER_PROFILE_ALLOC (0xf5UL) 6235 #define HWRM_CFA_METER_PROFILE_FREE (0xf6UL) 6236 #define HWRM_CFA_METER_PROFILE_CFG (0xf7UL) 6237 #define HWRM_CFA_METER_INSTANCE_ALLOC (0xf8UL) 6238 #define HWRM_CFA_METER_INSTANCE_FREE (0xf9UL) 6239 #define HWRM_CFA_VFR_ALLOC (0xfdUL) 6240 #define HWRM_CFA_VFR_FREE (0xfeUL) 6241 #define HWRM_CFA_VF_PAIR_ALLOC (0x100UL) 6242 #define HWRM_CFA_VF_PAIR_FREE (0x101UL) 6243 #define HWRM_CFA_VF_PAIR_INFO (0x102UL) 6244 #define HWRM_CFA_FLOW_ALLOC (0x103UL) 6245 #define HWRM_CFA_FLOW_FREE (0x104UL) 6246 #define HWRM_CFA_FLOW_FLUSH (0x105UL) 6247 #define HWRM_CFA_FLOW_STATS (0x106UL) 6248 #define HWRM_CFA_FLOW_INFO (0x107UL) 6249 #define HWRM_CFA_DECAP_FILTER_ALLOC (0x108UL) 6250 #define HWRM_CFA_DECAP_FILTER_FREE (0x109UL) 6251 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG (0x10aUL) 6252 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC (0x10bUL) 6253 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE (0x10cUL) 6254 #define HWRM_CFA_PAIR_ALLOC (0x10dUL) 6255 #define HWRM_CFA_PAIR_FREE (0x10eUL) 6256 #define HWRM_CFA_PAIR_INFO (0x10fUL) 6257 #define HWRM_FW_IPC_MSG (0x110UL) 6258 #define HWRM_SELFTEST_QLIST (0x200UL) 6259 #define HWRM_SELFTEST_EXEC (0x201UL) 6260 #define HWRM_SELFTEST_IRQ (0x202UL) 6261 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA (0x203UL) 6262 #define HWRM_DBG_READ_DIRECT (0xff10UL) 6263 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 6264 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 6265 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 6266 #define HWRM_DBG_DUMP (0xff14UL) 6267 #define HWRM_DBG_ERASE_NVM (0xff15UL) 6268 #define HWRM_DBG_CFG (0xff16UL) 6269 #define HWRM_DBG_COREDUMP_LIST (0xff17UL) 6270 #define HWRM_DBG_COREDUMP_INITIATE (0xff18UL) 6271 #define HWRM_DBG_COREDUMP_RETRIEVE (0xff19UL) 6272 #define HWRM_NVM_FACTORY_DEFAULTS (0xffeeUL) 6273 #define HWRM_NVM_VALIDATE_OPTION (0xffefUL) 6274 #define HWRM_NVM_FLUSH (0xfff0UL) 6275 #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 6276 #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 6277 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 6278 #define HWRM_NVM_MODIFY (0xfff4UL) 6279 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 6280 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 6281 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 6282 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 6283 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 6284 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 6285 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 6286 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 6287 #define HWRM_NVM_READ (0xfffdUL) 6288 #define HWRM_NVM_WRITE (0xfffeUL) 6289 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 6290 __le16 unused_0[3]; 6291 }; 6292 6293 /* Return Codes (8 bytes) */ 6294 struct ret_codes { 6295 __le16 error_code; 6296 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 6297 #define HWRM_ERR_CODE_FAIL (0x1UL) 6298 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 6299 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 6300 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 6301 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 6302 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 6303 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 6304 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 6305 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 6306 __le16 unused_0[3]; 6307 }; 6308 6309 /* Output (16 bytes) */ 6310 struct hwrm_err_output { 6311 __le16 error_code; 6312 __le16 req_type; 6313 __le16 seq_id; 6314 __le16 resp_len; 6315 __le32 opaque_0; 6316 __le16 opaque_1; 6317 u8 cmd_err; 6318 u8 valid; 6319 }; 6320 6321 /* Port Tx Statistics Formats (408 bytes) */ 6322 struct tx_port_stats { 6323 __le64 tx_64b_frames; 6324 __le64 tx_65b_127b_frames; 6325 __le64 tx_128b_255b_frames; 6326 __le64 tx_256b_511b_frames; 6327 __le64 tx_512b_1023b_frames; 6328 __le64 tx_1024b_1518_frames; 6329 __le64 tx_good_vlan_frames; 6330 __le64 tx_1519b_2047_frames; 6331 __le64 tx_2048b_4095b_frames; 6332 __le64 tx_4096b_9216b_frames; 6333 __le64 tx_9217b_16383b_frames; 6334 __le64 tx_good_frames; 6335 __le64 tx_total_frames; 6336 __le64 tx_ucast_frames; 6337 __le64 tx_mcast_frames; 6338 __le64 tx_bcast_frames; 6339 __le64 tx_pause_frames; 6340 __le64 tx_pfc_frames; 6341 __le64 tx_jabber_frames; 6342 __le64 tx_fcs_err_frames; 6343 __le64 tx_control_frames; 6344 __le64 tx_oversz_frames; 6345 __le64 tx_single_dfrl_frames; 6346 __le64 tx_multi_dfrl_frames; 6347 __le64 tx_single_coll_frames; 6348 __le64 tx_multi_coll_frames; 6349 __le64 tx_late_coll_frames; 6350 __le64 tx_excessive_coll_frames; 6351 __le64 tx_frag_frames; 6352 __le64 tx_err; 6353 __le64 tx_tagged_frames; 6354 __le64 tx_dbl_tagged_frames; 6355 __le64 tx_runt_frames; 6356 __le64 tx_fifo_underruns; 6357 __le64 tx_pfc_ena_frames_pri0; 6358 __le64 tx_pfc_ena_frames_pri1; 6359 __le64 tx_pfc_ena_frames_pri2; 6360 __le64 tx_pfc_ena_frames_pri3; 6361 __le64 tx_pfc_ena_frames_pri4; 6362 __le64 tx_pfc_ena_frames_pri5; 6363 __le64 tx_pfc_ena_frames_pri6; 6364 __le64 tx_pfc_ena_frames_pri7; 6365 __le64 tx_eee_lpi_events; 6366 __le64 tx_eee_lpi_duration; 6367 __le64 tx_llfc_logical_msgs; 6368 __le64 tx_hcfc_msgs; 6369 __le64 tx_total_collisions; 6370 __le64 tx_bytes; 6371 __le64 tx_xthol_frames; 6372 __le64 tx_stat_discard; 6373 __le64 tx_stat_error; 6374 }; 6375 6376 /* Port Rx Statistics Formats (528 bytes) */ 6377 struct rx_port_stats { 6378 __le64 rx_64b_frames; 6379 __le64 rx_65b_127b_frames; 6380 __le64 rx_128b_255b_frames; 6381 __le64 rx_256b_511b_frames; 6382 __le64 rx_512b_1023b_frames; 6383 __le64 rx_1024b_1518_frames; 6384 __le64 rx_good_vlan_frames; 6385 __le64 rx_1519b_2047b_frames; 6386 __le64 rx_2048b_4095b_frames; 6387 __le64 rx_4096b_9216b_frames; 6388 __le64 rx_9217b_16383b_frames; 6389 __le64 rx_total_frames; 6390 __le64 rx_ucast_frames; 6391 __le64 rx_mcast_frames; 6392 __le64 rx_bcast_frames; 6393 __le64 rx_fcs_err_frames; 6394 __le64 rx_ctrl_frames; 6395 __le64 rx_pause_frames; 6396 __le64 rx_pfc_frames; 6397 __le64 rx_unsupported_opcode_frames; 6398 __le64 rx_unsupported_da_pausepfc_frames; 6399 __le64 rx_wrong_sa_frames; 6400 __le64 rx_align_err_frames; 6401 __le64 rx_oor_len_frames; 6402 __le64 rx_code_err_frames; 6403 __le64 rx_false_carrier_frames; 6404 __le64 rx_ovrsz_frames; 6405 __le64 rx_jbr_frames; 6406 __le64 rx_mtu_err_frames; 6407 __le64 rx_match_crc_frames; 6408 __le64 rx_promiscuous_frames; 6409 __le64 rx_tagged_frames; 6410 __le64 rx_double_tagged_frames; 6411 __le64 rx_trunc_frames; 6412 __le64 rx_good_frames; 6413 __le64 rx_pfc_xon2xoff_frames_pri0; 6414 __le64 rx_pfc_xon2xoff_frames_pri1; 6415 __le64 rx_pfc_xon2xoff_frames_pri2; 6416 __le64 rx_pfc_xon2xoff_frames_pri3; 6417 __le64 rx_pfc_xon2xoff_frames_pri4; 6418 __le64 rx_pfc_xon2xoff_frames_pri5; 6419 __le64 rx_pfc_xon2xoff_frames_pri6; 6420 __le64 rx_pfc_xon2xoff_frames_pri7; 6421 __le64 rx_pfc_ena_frames_pri0; 6422 __le64 rx_pfc_ena_frames_pri1; 6423 __le64 rx_pfc_ena_frames_pri2; 6424 __le64 rx_pfc_ena_frames_pri3; 6425 __le64 rx_pfc_ena_frames_pri4; 6426 __le64 rx_pfc_ena_frames_pri5; 6427 __le64 rx_pfc_ena_frames_pri6; 6428 __le64 rx_pfc_ena_frames_pri7; 6429 __le64 rx_sch_crc_err_frames; 6430 __le64 rx_undrsz_frames; 6431 __le64 rx_frag_frames; 6432 __le64 rx_eee_lpi_events; 6433 __le64 rx_eee_lpi_duration; 6434 __le64 rx_llfc_physical_msgs; 6435 __le64 rx_llfc_logical_msgs; 6436 __le64 rx_llfc_msgs_with_crc_err; 6437 __le64 rx_hcfc_msgs; 6438 __le64 rx_hcfc_msgs_with_crc_err; 6439 __le64 rx_bytes; 6440 __le64 rx_runt_bytes; 6441 __le64 rx_runt_frames; 6442 __le64 rx_stat_discard; 6443 __le64 rx_stat_err; 6444 }; 6445 6446 /* VXLAN IPv4 encapsulation structure (16 bytes) */ 6447 struct hwrm_vxlan_ipv4_hdr { 6448 u8 ver_hlen; 6449 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6450 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6451 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6452 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6453 u8 tos; 6454 __be16 ip_id; 6455 __be16 flags_frag_offset; 6456 u8 ttl; 6457 u8 protocol; 6458 __be32 src_ip_addr; 6459 __be32 dest_ip_addr; 6460 }; 6461 6462 /* VXLAN IPv6 encapsulation structure (32 bytes) */ 6463 struct hwrm_vxlan_ipv6_hdr { 6464 __be32 ver_tc_flow_label; 6465 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6466 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6467 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6468 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6469 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6470 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6471 __be16 payload_len; 6472 u8 next_hdr; 6473 u8 ttl; 6474 __be32 src_ip_addr[4]; 6475 __be32 dest_ip_addr[4]; 6476 }; 6477 6478 /* VXLAN encapsulation structure (72 bytes) */ 6479 struct hwrm_cfa_encap_data_vxlan { 6480 u8 src_mac_addr[6]; 6481 __le16 unused_0; 6482 u8 dst_mac_addr[6]; 6483 u8 num_vlan_tags; 6484 u8 unused_1; 6485 __be16 ovlan_tpid; 6486 __be16 ovlan_tci; 6487 __be16 ivlan_tpid; 6488 __be16 ivlan_tci; 6489 __le32 l3[10]; 6490 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6491 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6492 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6493 __be16 src_port; 6494 __be16 dst_port; 6495 __be32 vni; 6496 }; 6497 6498 /* Periodic Statistics Context DMA to host (160 bytes) */ 6499 struct ctx_hw_stats { 6500 __le64 rx_ucast_pkts; 6501 __le64 rx_mcast_pkts; 6502 __le64 rx_bcast_pkts; 6503 __le64 rx_discard_pkts; 6504 __le64 rx_drop_pkts; 6505 __le64 rx_ucast_bytes; 6506 __le64 rx_mcast_bytes; 6507 __le64 rx_bcast_bytes; 6508 __le64 tx_ucast_pkts; 6509 __le64 tx_mcast_pkts; 6510 __le64 tx_bcast_pkts; 6511 __le64 tx_discard_pkts; 6512 __le64 tx_drop_pkts; 6513 __le64 tx_ucast_bytes; 6514 __le64 tx_mcast_bytes; 6515 __le64 tx_bcast_bytes; 6516 __le64 tpa_pkts; 6517 __le64 tpa_bytes; 6518 __le64 tpa_events; 6519 __le64 tpa_aborts; 6520 }; 6521 6522 /* Structure data header (16 bytes) */ 6523 struct hwrm_struct_hdr { 6524 __le16 struct_id; 6525 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6526 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6527 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6528 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6529 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6530 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6531 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6532 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6533 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6534 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6535 __le16 len; 6536 u8 version; 6537 u8 count; 6538 __le16 subtype; 6539 __le16 next_offset; 6540 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6541 __le16 unused_0[3]; 6542 }; 6543 6544 /* DCBX Application configuration structure (1057) (8 bytes) */ 6545 struct hwrm_struct_data_dcbx_app { 6546 __be16 protocol_id; 6547 u8 protocol_selector; 6548 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6549 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6550 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6551 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6552 u8 priority; 6553 u8 valid; 6554 u8 unused_0[3]; 6555 }; 6556 6557 #endif 6558