1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2021 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 107 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 108 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110 #define HWRM_FUNC_VF_CFG 0xfUL 111 #define HWRM_RESERVED1 0x10UL 112 #define HWRM_FUNC_RESET 0x11UL 113 #define HWRM_FUNC_GETFID 0x12UL 114 #define HWRM_FUNC_VF_ALLOC 0x13UL 115 #define HWRM_FUNC_VF_FREE 0x14UL 116 #define HWRM_FUNC_QCAPS 0x15UL 117 #define HWRM_FUNC_QCFG 0x16UL 118 #define HWRM_FUNC_CFG 0x17UL 119 #define HWRM_FUNC_QSTATS 0x18UL 120 #define HWRM_FUNC_CLR_STATS 0x19UL 121 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124 #define HWRM_FUNC_DRV_RGTR 0x1dUL 125 #define HWRM_FUNC_DRV_QVER 0x1eUL 126 #define HWRM_FUNC_BUF_RGTR 0x1fUL 127 #define HWRM_PORT_PHY_CFG 0x20UL 128 #define HWRM_PORT_MAC_CFG 0x21UL 129 #define HWRM_PORT_TS_QUERY 0x22UL 130 #define HWRM_PORT_QSTATS 0x23UL 131 #define HWRM_PORT_LPBK_QSTATS 0x24UL 132 #define HWRM_PORT_CLR_STATS 0x25UL 133 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134 #define HWRM_PORT_PHY_QCFG 0x27UL 135 #define HWRM_PORT_MAC_QCFG 0x28UL 136 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137 #define HWRM_PORT_PHY_QCAPS 0x2aUL 138 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140 #define HWRM_PORT_LED_CFG 0x2dUL 141 #define HWRM_PORT_LED_QCFG 0x2eUL 142 #define HWRM_PORT_LED_QCAPS 0x2fUL 143 #define HWRM_QUEUE_QPORTCFG 0x30UL 144 #define HWRM_QUEUE_QCFG 0x31UL 145 #define HWRM_QUEUE_CFG 0x32UL 146 #define HWRM_FUNC_VLAN_CFG 0x33UL 147 #define HWRM_FUNC_VLAN_QCFG 0x34UL 148 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157 #define HWRM_VNIC_ALLOC 0x40UL 158 #define HWRM_VNIC_FREE 0x41UL 159 #define HWRM_VNIC_CFG 0x42UL 160 #define HWRM_VNIC_QCFG 0x43UL 161 #define HWRM_VNIC_TPA_CFG 0x44UL 162 #define HWRM_VNIC_TPA_QCFG 0x45UL 163 #define HWRM_VNIC_RSS_CFG 0x46UL 164 #define HWRM_VNIC_RSS_QCFG 0x47UL 165 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167 #define HWRM_VNIC_QCAPS 0x4aUL 168 #define HWRM_VNIC_UPDATE 0x4bUL 169 #define HWRM_RING_ALLOC 0x50UL 170 #define HWRM_RING_FREE 0x51UL 171 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 173 #define HWRM_RING_AGGINT_QCAPS 0x54UL 174 #define HWRM_RING_SCHQ_ALLOC 0x55UL 175 #define HWRM_RING_SCHQ_CFG 0x56UL 176 #define HWRM_RING_SCHQ_FREE 0x57UL 177 #define HWRM_RING_RESET 0x5eUL 178 #define HWRM_RING_GRP_ALLOC 0x60UL 179 #define HWRM_RING_GRP_FREE 0x61UL 180 #define HWRM_RING_CFG 0x62UL 181 #define HWRM_RING_QCFG 0x63UL 182 #define HWRM_RESERVED5 0x64UL 183 #define HWRM_RESERVED6 0x65UL 184 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 186 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 187 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 188 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 189 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 190 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 191 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 192 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 193 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 212 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213 #define HWRM_STAT_CTX_ALLOC 0xb0UL 214 #define HWRM_STAT_CTX_FREE 0xb1UL 215 #define HWRM_STAT_CTX_QUERY 0xb2UL 216 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217 #define HWRM_PORT_QSTATS_EXT 0xb4UL 218 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 219 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 220 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 221 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 223 #define HWRM_RESERVED7 0xbaUL 224 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 225 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 226 #define HWRM_PORT_ECN_QSTATS 0xbdUL 227 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 228 #define HWRM_FW_LIVEPATCH 0xbfUL 229 #define HWRM_FW_RESET 0xc0UL 230 #define HWRM_FW_QSTATUS 0xc1UL 231 #define HWRM_FW_HEALTH_CHECK 0xc2UL 232 #define HWRM_FW_SYNC 0xc3UL 233 #define HWRM_FW_STATE_QCAPS 0xc4UL 234 #define HWRM_FW_STATE_QUIESCE 0xc5UL 235 #define HWRM_FW_STATE_BACKUP 0xc6UL 236 #define HWRM_FW_STATE_RESTORE 0xc7UL 237 #define HWRM_FW_SET_TIME 0xc8UL 238 #define HWRM_FW_GET_TIME 0xc9UL 239 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241 #define HWRM_FW_IPC_MAILBOX 0xccUL 242 #define HWRM_FW_ECN_CFG 0xcdUL 243 #define HWRM_FW_ECN_QCFG 0xceUL 244 #define HWRM_FW_SECURE_CFG 0xcfUL 245 #define HWRM_EXEC_FWD_RESP 0xd0UL 246 #define HWRM_REJECT_FWD_RESP 0xd1UL 247 #define HWRM_FWD_RESP 0xd2UL 248 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249 #define HWRM_OEM_CMD 0xd4UL 250 #define HWRM_PORT_PRBS_TEST 0xd5UL 251 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 252 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 253 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 254 #define HWRM_PORT_DSC_DUMP 0xd9UL 255 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 256 #define HWRM_PORT_EP_TX_CFG 0xdbUL 257 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 258 #define HWRM_REG_POWER_QUERY 0xe1UL 259 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 260 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 261 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 262 #define HWRM_WOL_FILTER_FREE 0xf1UL 263 #define HWRM_WOL_FILTER_QCFG 0xf2UL 264 #define HWRM_WOL_REASON_QCFG 0xf3UL 265 #define HWRM_CFA_METER_QCAPS 0xf4UL 266 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 267 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 268 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 269 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 270 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 271 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 272 #define HWRM_CFA_VFR_ALLOC 0xfdUL 273 #define HWRM_CFA_VFR_FREE 0xfeUL 274 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 275 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 276 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 277 #define HWRM_CFA_FLOW_ALLOC 0x103UL 278 #define HWRM_CFA_FLOW_FREE 0x104UL 279 #define HWRM_CFA_FLOW_FLUSH 0x105UL 280 #define HWRM_CFA_FLOW_STATS 0x106UL 281 #define HWRM_CFA_FLOW_INFO 0x107UL 282 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 283 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 284 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 285 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 286 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 287 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 288 #define HWRM_CFA_PAIR_FREE 0x10eUL 289 #define HWRM_CFA_PAIR_INFO 0x10fUL 290 #define HWRM_FW_IPC_MSG 0x110UL 291 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 292 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 293 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 294 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 295 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 296 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 297 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 298 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 299 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 300 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 301 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 302 #define HWRM_CFA_COUNTER_CFG 0x11cUL 303 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 304 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 305 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 306 #define HWRM_CFA_EEM_QCAPS 0x120UL 307 #define HWRM_CFA_EEM_CFG 0x121UL 308 #define HWRM_CFA_EEM_QCFG 0x122UL 309 #define HWRM_CFA_EEM_OP 0x123UL 310 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 311 #define HWRM_CFA_TFLIB 0x125UL 312 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 313 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 314 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 315 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 316 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 317 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 318 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 319 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 320 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 321 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 322 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 323 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 324 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 325 #define HWRM_ENGINE_QG_QUERY 0x13dUL 326 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 327 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 328 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 329 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 330 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 331 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 332 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 333 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 334 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 335 #define HWRM_ENGINE_SG_QUERY 0x147UL 336 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 337 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 338 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 339 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 340 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 341 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 342 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 343 #define HWRM_ENGINE_STATS_QUERY 0x157UL 344 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 345 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 346 #define HWRM_ENGINE_RQ_FREE 0x15fUL 347 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 348 #define HWRM_ENGINE_CQ_FREE 0x161UL 349 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 350 #define HWRM_ENGINE_NQ_FREE 0x163UL 351 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 352 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 353 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 354 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 355 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 356 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 357 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 358 #define HWRM_FUNC_VF_BW_CFG 0x195UL 359 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 360 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 361 #define HWRM_FUNC_QSTATS_EXT 0x198UL 362 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 363 #define HWRM_FUNC_SPD_CFG 0x19aUL 364 #define HWRM_FUNC_SPD_QCFG 0x19bUL 365 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 366 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 367 #define HWRM_FUNC_PTP_CFG 0x19eUL 368 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 369 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 370 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 371 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 372 #define HWRM_SELFTEST_QLIST 0x200UL 373 #define HWRM_SELFTEST_EXEC 0x201UL 374 #define HWRM_SELFTEST_IRQ 0x202UL 375 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 376 #define HWRM_PCIE_QSTATS 0x204UL 377 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 378 #define HWRM_MFG_TIMERS_QUERY 0x206UL 379 #define HWRM_MFG_OTP_CFG 0x207UL 380 #define HWRM_MFG_OTP_QCFG 0x208UL 381 #define HWRM_MFG_HDMA_TEST 0x209UL 382 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 383 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 384 #define HWRM_MFG_SOC_IMAGE 0x20cUL 385 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 386 #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 387 #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 388 #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 389 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 390 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 391 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 392 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 393 #define HWRM_TF 0x2bcUL 394 #define HWRM_TF_VERSION_GET 0x2bdUL 395 #define HWRM_TF_SESSION_OPEN 0x2c6UL 396 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 397 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 398 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 399 #define HWRM_TF_SESSION_CLOSE 0x2caUL 400 #define HWRM_TF_SESSION_QCFG 0x2cbUL 401 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 402 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 403 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 404 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 405 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 406 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 407 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 408 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 409 #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 410 #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 411 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 412 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 413 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 414 #define HWRM_TF_EXT_EM_OP 0x2e7UL 415 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 416 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 417 #define HWRM_TF_EM_INSERT 0x2eaUL 418 #define HWRM_TF_EM_DELETE 0x2ebUL 419 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 420 #define HWRM_TF_EM_MOVE 0x2edUL 421 #define HWRM_TF_TCAM_SET 0x2f8UL 422 #define HWRM_TF_TCAM_GET 0x2f9UL 423 #define HWRM_TF_TCAM_MOVE 0x2faUL 424 #define HWRM_TF_TCAM_FREE 0x2fbUL 425 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 426 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 427 #define HWRM_TF_IF_TBL_SET 0x2feUL 428 #define HWRM_TF_IF_TBL_GET 0x2ffUL 429 #define HWRM_SV 0x400UL 430 #define HWRM_DBG_READ_DIRECT 0xff10UL 431 #define HWRM_DBG_READ_INDIRECT 0xff11UL 432 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 433 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 434 #define HWRM_DBG_DUMP 0xff14UL 435 #define HWRM_DBG_ERASE_NVM 0xff15UL 436 #define HWRM_DBG_CFG 0xff16UL 437 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 438 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 439 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 440 #define HWRM_DBG_FW_CLI 0xff1aUL 441 #define HWRM_DBG_I2C_CMD 0xff1bUL 442 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 443 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 444 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 445 #define HWRM_DBG_DRV_TRACE 0xff1fUL 446 #define HWRM_DBG_QCAPS 0xff20UL 447 #define HWRM_DBG_QCFG 0xff21UL 448 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 449 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 450 #define HWRM_DBG_USEQ_FREE 0xff24UL 451 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 452 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 453 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 454 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 455 #define HWRM_DBG_USEQ_RUN 0xff29UL 456 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 457 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 458 #define HWRM_NVM_DEFRAG 0xffecUL 459 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 460 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 461 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 462 #define HWRM_NVM_FLUSH 0xfff0UL 463 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 464 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 465 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 466 #define HWRM_NVM_MODIFY 0xfff4UL 467 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 468 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 469 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 470 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 471 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 472 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 473 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 474 #define HWRM_NVM_RAW_DUMP 0xfffcUL 475 #define HWRM_NVM_READ 0xfffdUL 476 #define HWRM_NVM_WRITE 0xfffeUL 477 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 478 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 479 __le16 unused_0[3]; 480 }; 481 482 /* ret_codes (size:64b/8B) */ 483 struct ret_codes { 484 __le16 error_code; 485 #define HWRM_ERR_CODE_SUCCESS 0x0UL 486 #define HWRM_ERR_CODE_FAIL 0x1UL 487 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 488 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 489 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 490 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 491 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 492 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 493 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 494 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 495 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 496 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 497 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 498 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 499 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 500 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 501 #define HWRM_ERR_CODE_BUSY 0x10UL 502 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 503 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 504 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 505 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 506 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 507 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 508 __le16 unused_0[3]; 509 }; 510 511 /* hwrm_err_output (size:128b/16B) */ 512 struct hwrm_err_output { 513 __le16 error_code; 514 __le16 req_type; 515 __le16 seq_id; 516 __le16 resp_len; 517 __le32 opaque_0; 518 __le16 opaque_1; 519 u8 cmd_err; 520 u8 valid; 521 }; 522 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 523 #define HWRM_MAX_REQ_LEN 128 524 #define HWRM_MAX_RESP_LEN 704 525 #define HW_HASH_INDEX_SIZE 0x80 526 #define HW_HASH_KEY_SIZE 40 527 #define HWRM_RESP_VALID_KEY 1 528 #define HWRM_TARGET_ID_BONO 0xFFF8 529 #define HWRM_TARGET_ID_KONG 0xFFF9 530 #define HWRM_TARGET_ID_APE 0xFFFA 531 #define HWRM_TARGET_ID_TOOLS 0xFFFD 532 #define HWRM_VERSION_MAJOR 1 533 #define HWRM_VERSION_MINOR 10 534 #define HWRM_VERSION_UPDATE 2 535 #define HWRM_VERSION_RSVD 63 536 #define HWRM_VERSION_STR "1.10.2.63" 537 538 /* hwrm_ver_get_input (size:192b/24B) */ 539 struct hwrm_ver_get_input { 540 __le16 req_type; 541 __le16 cmpl_ring; 542 __le16 seq_id; 543 __le16 target_id; 544 __le64 resp_addr; 545 u8 hwrm_intf_maj; 546 u8 hwrm_intf_min; 547 u8 hwrm_intf_upd; 548 u8 unused_0[5]; 549 }; 550 551 /* hwrm_ver_get_output (size:1408b/176B) */ 552 struct hwrm_ver_get_output { 553 __le16 error_code; 554 __le16 req_type; 555 __le16 seq_id; 556 __le16 resp_len; 557 u8 hwrm_intf_maj_8b; 558 u8 hwrm_intf_min_8b; 559 u8 hwrm_intf_upd_8b; 560 u8 hwrm_intf_rsvd_8b; 561 u8 hwrm_fw_maj_8b; 562 u8 hwrm_fw_min_8b; 563 u8 hwrm_fw_bld_8b; 564 u8 hwrm_fw_rsvd_8b; 565 u8 mgmt_fw_maj_8b; 566 u8 mgmt_fw_min_8b; 567 u8 mgmt_fw_bld_8b; 568 u8 mgmt_fw_rsvd_8b; 569 u8 netctrl_fw_maj_8b; 570 u8 netctrl_fw_min_8b; 571 u8 netctrl_fw_bld_8b; 572 u8 netctrl_fw_rsvd_8b; 573 __le32 dev_caps_cfg; 574 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 575 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 576 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 577 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 578 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 579 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 580 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 581 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 582 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 583 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 584 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 585 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 586 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 587 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 588 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 589 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 590 u8 roce_fw_maj_8b; 591 u8 roce_fw_min_8b; 592 u8 roce_fw_bld_8b; 593 u8 roce_fw_rsvd_8b; 594 char hwrm_fw_name[16]; 595 char mgmt_fw_name[16]; 596 char netctrl_fw_name[16]; 597 char active_pkg_name[16]; 598 char roce_fw_name[16]; 599 __le16 chip_num; 600 u8 chip_rev; 601 u8 chip_metal; 602 u8 chip_bond_id; 603 u8 chip_platform_type; 604 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 605 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 606 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 607 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 608 __le16 max_req_win_len; 609 __le16 max_resp_len; 610 __le16 def_req_timeout; 611 u8 flags; 612 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 613 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 614 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 615 u8 unused_0[2]; 616 u8 always_1; 617 __le16 hwrm_intf_major; 618 __le16 hwrm_intf_minor; 619 __le16 hwrm_intf_build; 620 __le16 hwrm_intf_patch; 621 __le16 hwrm_fw_major; 622 __le16 hwrm_fw_minor; 623 __le16 hwrm_fw_build; 624 __le16 hwrm_fw_patch; 625 __le16 mgmt_fw_major; 626 __le16 mgmt_fw_minor; 627 __le16 mgmt_fw_build; 628 __le16 mgmt_fw_patch; 629 __le16 netctrl_fw_major; 630 __le16 netctrl_fw_minor; 631 __le16 netctrl_fw_build; 632 __le16 netctrl_fw_patch; 633 __le16 roce_fw_major; 634 __le16 roce_fw_minor; 635 __le16 roce_fw_build; 636 __le16 roce_fw_patch; 637 __le16 max_ext_req_len; 638 __le16 max_req_timeout; 639 u8 unused_1[3]; 640 u8 valid; 641 }; 642 643 /* eject_cmpl (size:128b/16B) */ 644 struct eject_cmpl { 645 __le16 type; 646 #define EJECT_CMPL_TYPE_MASK 0x3fUL 647 #define EJECT_CMPL_TYPE_SFT 0 648 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 649 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 650 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 651 #define EJECT_CMPL_FLAGS_SFT 6 652 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 653 __le16 len; 654 __le32 opaque; 655 __le16 v; 656 #define EJECT_CMPL_V 0x1UL 657 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 658 #define EJECT_CMPL_ERRORS_SFT 1 659 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 660 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 661 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 662 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 663 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 664 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 665 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 666 __le16 reserved16; 667 __le32 unused_2; 668 }; 669 670 /* hwrm_cmpl (size:128b/16B) */ 671 struct hwrm_cmpl { 672 __le16 type; 673 #define CMPL_TYPE_MASK 0x3fUL 674 #define CMPL_TYPE_SFT 0 675 #define CMPL_TYPE_HWRM_DONE 0x20UL 676 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 677 __le16 sequence_id; 678 __le32 unused_1; 679 __le32 v; 680 #define CMPL_V 0x1UL 681 __le32 unused_3; 682 }; 683 684 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 685 struct hwrm_fwd_req_cmpl { 686 __le16 req_len_type; 687 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 688 #define FWD_REQ_CMPL_TYPE_SFT 0 689 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 690 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 691 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 692 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 693 __le16 source_id; 694 __le32 unused0; 695 __le32 req_buf_addr_v[2]; 696 #define FWD_REQ_CMPL_V 0x1UL 697 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 698 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 699 }; 700 701 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 702 struct hwrm_fwd_resp_cmpl { 703 __le16 type; 704 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 705 #define FWD_RESP_CMPL_TYPE_SFT 0 706 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 707 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 708 __le16 source_id; 709 __le16 resp_len; 710 __le16 unused_1; 711 __le32 resp_buf_addr_v[2]; 712 #define FWD_RESP_CMPL_V 0x1UL 713 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 714 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 715 }; 716 717 /* hwrm_async_event_cmpl (size:128b/16B) */ 718 struct hwrm_async_event_cmpl { 719 __le16 type; 720 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 721 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 722 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 723 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 724 __le16 event_id; 725 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 726 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 727 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 728 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 729 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 730 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 731 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 732 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 733 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 734 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 735 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 736 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 737 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 738 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 739 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 740 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 741 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 742 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 743 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 744 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 745 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 746 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 747 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 748 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 749 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 750 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 751 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 752 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 753 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 754 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 755 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 756 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 757 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 758 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 759 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 760 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER 0x43UL 761 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 762 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 763 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x46UL 764 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 765 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 766 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 767 __le32 event_data2; 768 u8 opaque_v; 769 #define ASYNC_EVENT_CMPL_V 0x1UL 770 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 771 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 772 u8 timestamp_lo; 773 __le16 timestamp_hi; 774 __le32 event_data1; 775 }; 776 777 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 778 struct hwrm_async_event_cmpl_link_status_change { 779 __le16 type; 780 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 781 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 782 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 783 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 784 __le16 event_id; 785 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 786 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 787 __le32 event_data2; 788 u8 opaque_v; 789 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 790 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 791 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 792 u8 timestamp_lo; 793 __le16 timestamp_hi; 794 __le32 event_data1; 795 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 796 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 797 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 798 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 799 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 800 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 801 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 802 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 803 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 804 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 805 }; 806 807 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 808 struct hwrm_async_event_cmpl_port_conn_not_allowed { 809 __le16 type; 810 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 811 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 812 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 813 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 814 __le16 event_id; 815 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 816 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 817 __le32 event_data2; 818 u8 opaque_v; 819 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 820 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 821 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 822 u8 timestamp_lo; 823 __le16 timestamp_hi; 824 __le32 event_data1; 825 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 826 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 827 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 828 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 829 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 830 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 831 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 832 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 833 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 834 }; 835 836 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 837 struct hwrm_async_event_cmpl_link_speed_cfg_change { 838 __le16 type; 839 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 840 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 841 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 842 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 843 __le16 event_id; 844 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 845 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 846 __le32 event_data2; 847 u8 opaque_v; 848 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 849 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 850 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 851 u8 timestamp_lo; 852 __le16 timestamp_hi; 853 __le32 event_data1; 854 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 855 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 856 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 857 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 858 }; 859 860 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 861 struct hwrm_async_event_cmpl_reset_notify { 862 __le16 type; 863 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 864 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 865 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 866 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 867 __le16 event_id; 868 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 869 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 870 __le32 event_data2; 871 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 872 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 873 u8 opaque_v; 874 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 875 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 876 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 877 u8 timestamp_lo; 878 __le16 timestamp_hi; 879 __le32 event_data1; 880 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 881 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 882 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 883 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 884 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 885 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 886 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 887 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 888 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 889 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 890 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 891 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 892 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 893 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 894 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 895 }; 896 897 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 898 struct hwrm_async_event_cmpl_error_recovery { 899 __le16 type; 900 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 901 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 902 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 903 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 904 __le16 event_id; 905 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 906 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 907 __le32 event_data2; 908 u8 opaque_v; 909 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 910 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 911 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 912 u8 timestamp_lo; 913 __le16 timestamp_hi; 914 __le32 event_data1; 915 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 916 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 917 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 918 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 919 }; 920 921 /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 922 struct hwrm_async_event_cmpl_ring_monitor_msg { 923 __le16 type; 924 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 925 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 926 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 927 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 928 __le16 event_id; 929 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 930 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 931 __le32 event_data2; 932 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 933 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 934 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 935 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 936 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 937 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 938 u8 opaque_v; 939 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 940 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 941 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 942 u8 timestamp_lo; 943 __le16 timestamp_hi; 944 __le32 event_data1; 945 }; 946 947 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 948 struct hwrm_async_event_cmpl_vf_cfg_change { 949 __le16 type; 950 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 951 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 952 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 953 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 954 __le16 event_id; 955 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 956 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 957 __le32 event_data2; 958 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 959 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 960 u8 opaque_v; 961 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 962 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 963 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 964 u8 timestamp_lo; 965 __le16 timestamp_hi; 966 __le32 event_data1; 967 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 968 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 969 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 970 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 971 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 972 }; 973 974 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 975 struct hwrm_async_event_cmpl_default_vnic_change { 976 __le16 type; 977 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 978 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 979 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 980 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 981 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 982 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 983 __le16 event_id; 984 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 985 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 986 __le32 event_data2; 987 u8 opaque_v; 988 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 989 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 990 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 991 u8 timestamp_lo; 992 __le16 timestamp_hi; 993 __le32 event_data1; 994 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 995 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 996 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 997 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 998 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 999 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1000 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1001 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1002 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1003 }; 1004 1005 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1006 struct hwrm_async_event_cmpl_hw_flow_aged { 1007 __le16 type; 1008 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1009 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1010 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1011 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1012 __le16 event_id; 1013 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1014 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1015 __le32 event_data2; 1016 u8 opaque_v; 1017 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1018 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1019 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1020 u8 timestamp_lo; 1021 __le16 timestamp_hi; 1022 __le32 event_data1; 1023 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1024 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1025 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1026 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1027 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1028 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1029 }; 1030 1031 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1032 struct hwrm_async_event_cmpl_eem_cache_flush_req { 1033 __le16 type; 1034 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1035 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1036 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1037 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1038 __le16 event_id; 1039 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1040 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1041 __le32 event_data2; 1042 u8 opaque_v; 1043 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1044 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1045 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1046 u8 timestamp_lo; 1047 __le16 timestamp_hi; 1048 __le32 event_data1; 1049 }; 1050 1051 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1052 struct hwrm_async_event_cmpl_eem_cache_flush_done { 1053 __le16 type; 1054 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1055 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1056 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1057 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1058 __le16 event_id; 1059 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1060 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1061 __le32 event_data2; 1062 u8 opaque_v; 1063 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1064 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1065 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1066 u8 timestamp_lo; 1067 __le16 timestamp_hi; 1068 __le32 event_data1; 1069 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1070 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1071 }; 1072 1073 /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1074 struct hwrm_async_event_cmpl_deferred_response { 1075 __le16 type; 1076 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1077 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1078 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1079 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1080 __le16 event_id; 1081 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1082 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1083 __le32 event_data2; 1084 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1085 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1086 u8 opaque_v; 1087 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1088 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1089 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1090 u8 timestamp_lo; 1091 __le16 timestamp_hi; 1092 __le32 event_data1; 1093 }; 1094 1095 /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1096 struct hwrm_async_event_cmpl_echo_request { 1097 __le16 type; 1098 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1099 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1100 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1101 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1102 __le16 event_id; 1103 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1104 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1105 __le32 event_data2; 1106 u8 opaque_v; 1107 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1108 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1109 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1110 u8 timestamp_lo; 1111 __le16 timestamp_hi; 1112 __le32 event_data1; 1113 }; 1114 1115 /* hwrm_async_event_cmpl_phc_master (size:128b/16B) */ 1116 struct hwrm_async_event_cmpl_phc_master { 1117 __le16 type; 1118 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK 0x3fUL 1119 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0 1120 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1121 #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 1122 __le16 event_id; 1123 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL 1124 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 1125 __le32 event_data2; 1126 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1127 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1128 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1129 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT 16 1130 u8 opaque_v; 1131 #define ASYNC_EVENT_CMPL_PHC_MASTER_V 0x1UL 1132 #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL 1133 #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1 1134 u8 timestamp_lo; 1135 __le16 timestamp_hi; 1136 __le32 event_data1; 1137 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK 0xfUL 1138 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT 0 1139 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1140 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1141 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1142 #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 1143 }; 1144 1145 /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1146 struct hwrm_async_event_cmpl_pps_timestamp { 1147 __le16 type; 1148 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1149 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1150 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1151 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1152 __le16 event_id; 1153 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1154 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1155 __le32 event_data2; 1156 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1157 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1158 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1159 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1160 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1161 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1162 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1163 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1164 u8 opaque_v; 1165 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1166 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1167 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1168 u8 timestamp_lo; 1169 __le16 timestamp_hi; 1170 __le32 event_data1; 1171 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1172 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1173 }; 1174 1175 /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1176 struct hwrm_async_event_cmpl_error_report { 1177 __le16 type; 1178 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1179 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1180 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1181 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1182 __le16 event_id; 1183 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1184 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1185 __le32 event_data2; 1186 u8 opaque_v; 1187 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1188 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1189 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1190 u8 timestamp_lo; 1191 __le16 timestamp_hi; 1192 __le32 event_data1; 1193 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1194 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1195 }; 1196 1197 /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1198 struct hwrm_async_event_cmpl_hwrm_error { 1199 __le16 type; 1200 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1201 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1202 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1203 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1204 __le16 event_id; 1205 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1206 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1207 __le32 event_data2; 1208 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1209 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1210 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1211 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1212 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1213 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1214 u8 opaque_v; 1215 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1216 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1217 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1218 u8 timestamp_lo; 1219 __le16 timestamp_hi; 1220 __le32 event_data1; 1221 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1222 }; 1223 1224 /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1225 struct hwrm_async_event_cmpl_error_report_base { 1226 __le16 type; 1227 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1228 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1229 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1230 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1231 __le16 event_id; 1232 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1233 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1234 __le32 event_data2; 1235 u8 opaque_v; 1236 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1237 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1238 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1239 u8 timestamp_lo; 1240 __le16 timestamp_hi; 1241 __le32 event_data1; 1242 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1243 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1244 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1245 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1246 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1247 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1248 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1249 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1250 }; 1251 1252 /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1253 struct hwrm_async_event_cmpl_error_report_pause_storm { 1254 __le16 type; 1255 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1256 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1257 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1258 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1259 __le16 event_id; 1260 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1261 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1262 __le32 event_data2; 1263 u8 opaque_v; 1264 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1265 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1266 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1267 u8 timestamp_lo; 1268 __le16 timestamp_hi; 1269 __le32 event_data1; 1270 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1271 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1272 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1273 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1274 }; 1275 1276 /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1277 struct hwrm_async_event_cmpl_error_report_invalid_signal { 1278 __le16 type; 1279 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1280 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1281 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1282 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1283 __le16 event_id; 1284 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1285 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1286 __le32 event_data2; 1287 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1288 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1289 u8 opaque_v; 1290 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1291 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1292 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1293 u8 timestamp_lo; 1294 __le16 timestamp_hi; 1295 __le32 event_data1; 1296 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1297 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1298 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1299 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1300 }; 1301 1302 /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1303 struct hwrm_async_event_cmpl_error_report_nvm { 1304 __le16 type; 1305 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1307 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1308 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1309 __le16 event_id; 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1311 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1312 __le32 event_data2; 1313 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1315 u8 opaque_v; 1316 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1317 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1318 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1319 u8 timestamp_lo; 1320 __le16 timestamp_hi; 1321 __le32 event_data1; 1322 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1323 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1324 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1325 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1326 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1327 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1328 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1329 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1330 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1331 }; 1332 1333 /* hwrm_func_reset_input (size:192b/24B) */ 1334 struct hwrm_func_reset_input { 1335 __le16 req_type; 1336 __le16 cmpl_ring; 1337 __le16 seq_id; 1338 __le16 target_id; 1339 __le64 resp_addr; 1340 __le32 enables; 1341 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1342 __le16 vf_id; 1343 u8 func_reset_level; 1344 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1345 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1346 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1347 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1348 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1349 u8 unused_0; 1350 }; 1351 1352 /* hwrm_func_reset_output (size:128b/16B) */ 1353 struct hwrm_func_reset_output { 1354 __le16 error_code; 1355 __le16 req_type; 1356 __le16 seq_id; 1357 __le16 resp_len; 1358 u8 unused_0[7]; 1359 u8 valid; 1360 }; 1361 1362 /* hwrm_func_getfid_input (size:192b/24B) */ 1363 struct hwrm_func_getfid_input { 1364 __le16 req_type; 1365 __le16 cmpl_ring; 1366 __le16 seq_id; 1367 __le16 target_id; 1368 __le64 resp_addr; 1369 __le32 enables; 1370 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1371 __le16 pci_id; 1372 u8 unused_0[2]; 1373 }; 1374 1375 /* hwrm_func_getfid_output (size:128b/16B) */ 1376 struct hwrm_func_getfid_output { 1377 __le16 error_code; 1378 __le16 req_type; 1379 __le16 seq_id; 1380 __le16 resp_len; 1381 __le16 fid; 1382 u8 unused_0[5]; 1383 u8 valid; 1384 }; 1385 1386 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1387 struct hwrm_func_vf_alloc_input { 1388 __le16 req_type; 1389 __le16 cmpl_ring; 1390 __le16 seq_id; 1391 __le16 target_id; 1392 __le64 resp_addr; 1393 __le32 enables; 1394 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1395 __le16 first_vf_id; 1396 __le16 num_vfs; 1397 }; 1398 1399 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1400 struct hwrm_func_vf_alloc_output { 1401 __le16 error_code; 1402 __le16 req_type; 1403 __le16 seq_id; 1404 __le16 resp_len; 1405 __le16 first_vf_id; 1406 u8 unused_0[5]; 1407 u8 valid; 1408 }; 1409 1410 /* hwrm_func_vf_free_input (size:192b/24B) */ 1411 struct hwrm_func_vf_free_input { 1412 __le16 req_type; 1413 __le16 cmpl_ring; 1414 __le16 seq_id; 1415 __le16 target_id; 1416 __le64 resp_addr; 1417 __le32 enables; 1418 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1419 __le16 first_vf_id; 1420 __le16 num_vfs; 1421 }; 1422 1423 /* hwrm_func_vf_free_output (size:128b/16B) */ 1424 struct hwrm_func_vf_free_output { 1425 __le16 error_code; 1426 __le16 req_type; 1427 __le16 seq_id; 1428 __le16 resp_len; 1429 u8 unused_0[7]; 1430 u8 valid; 1431 }; 1432 1433 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1434 struct hwrm_func_vf_cfg_input { 1435 __le16 req_type; 1436 __le16 cmpl_ring; 1437 __le16 seq_id; 1438 __le16 target_id; 1439 __le64 resp_addr; 1440 __le32 enables; 1441 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1442 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1443 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1444 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1445 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1446 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1447 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1448 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1449 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1450 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1451 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1452 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1453 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL 1454 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL 1455 __le16 mtu; 1456 __le16 guest_vlan; 1457 __le16 async_event_cr; 1458 u8 dflt_mac_addr[6]; 1459 __le32 flags; 1460 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1461 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1462 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1463 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1464 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1465 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1466 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1467 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1468 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1469 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1470 __le16 num_rsscos_ctxs; 1471 __le16 num_cmpl_rings; 1472 __le16 num_tx_rings; 1473 __le16 num_rx_rings; 1474 __le16 num_l2_ctxs; 1475 __le16 num_vnics; 1476 __le16 num_stat_ctxs; 1477 __le16 num_hw_ring_grps; 1478 __le16 num_tx_key_ctxs; 1479 __le16 num_rx_key_ctxs; 1480 }; 1481 1482 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1483 struct hwrm_func_vf_cfg_output { 1484 __le16 error_code; 1485 __le16 req_type; 1486 __le16 seq_id; 1487 __le16 resp_len; 1488 u8 unused_0[7]; 1489 u8 valid; 1490 }; 1491 1492 /* hwrm_func_qcaps_input (size:192b/24B) */ 1493 struct hwrm_func_qcaps_input { 1494 __le16 req_type; 1495 __le16 cmpl_ring; 1496 __le16 seq_id; 1497 __le16 target_id; 1498 __le64 resp_addr; 1499 __le16 fid; 1500 u8 unused_0[6]; 1501 }; 1502 1503 /* hwrm_func_qcaps_output (size:768b/96B) */ 1504 struct hwrm_func_qcaps_output { 1505 __le16 error_code; 1506 __le16 req_type; 1507 __le16 seq_id; 1508 __le16 resp_len; 1509 __le16 fid; 1510 __le16 port_id; 1511 __le32 flags; 1512 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1513 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1514 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1515 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1516 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1517 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1518 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1519 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1520 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1521 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1522 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1523 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1524 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1525 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1526 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1527 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1528 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1529 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1530 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1531 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1532 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1533 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1534 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1535 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1536 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1537 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1538 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1539 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1540 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1541 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1542 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1543 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1544 u8 mac_address[6]; 1545 __le16 max_rsscos_ctx; 1546 __le16 max_cmpl_rings; 1547 __le16 max_tx_rings; 1548 __le16 max_rx_rings; 1549 __le16 max_l2_ctxs; 1550 __le16 max_vnics; 1551 __le16 first_vf_id; 1552 __le16 max_vfs; 1553 __le16 max_stat_ctx; 1554 __le32 max_encap_records; 1555 __le32 max_decap_records; 1556 __le32 max_tx_em_flows; 1557 __le32 max_tx_wm_flows; 1558 __le32 max_rx_em_flows; 1559 __le32 max_rx_wm_flows; 1560 __le32 max_mcast_filters; 1561 __le32 max_flow_id; 1562 __le32 max_hw_ring_grps; 1563 __le16 max_sp_tx_rings; 1564 __le16 max_msix_vfs; 1565 __le32 flags_ext; 1566 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1567 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1568 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1569 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1570 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1571 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1572 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1573 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1574 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1575 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1576 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1577 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1578 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1579 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1580 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1581 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1582 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1583 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1584 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1585 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1586 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1587 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1588 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1589 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1590 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1591 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1592 u8 max_schqs; 1593 u8 mpc_chnls_cap; 1594 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1595 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1596 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1597 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1598 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1599 __le16 max_key_ctxs_alloc; 1600 u8 unused_1[7]; 1601 u8 valid; 1602 }; 1603 1604 /* hwrm_func_qcfg_input (size:192b/24B) */ 1605 struct hwrm_func_qcfg_input { 1606 __le16 req_type; 1607 __le16 cmpl_ring; 1608 __le16 seq_id; 1609 __le16 target_id; 1610 __le64 resp_addr; 1611 __le16 fid; 1612 u8 unused_0[6]; 1613 }; 1614 1615 /* hwrm_func_qcfg_output (size:896b/112B) */ 1616 struct hwrm_func_qcfg_output { 1617 __le16 error_code; 1618 __le16 req_type; 1619 __le16 seq_id; 1620 __le16 resp_len; 1621 __le16 fid; 1622 __le16 port_id; 1623 __le16 vlan; 1624 __le16 flags; 1625 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1626 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1627 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1628 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1629 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1630 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1631 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1632 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1633 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1634 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1635 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1636 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1637 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1638 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1639 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1640 u8 mac_address[6]; 1641 __le16 pci_id; 1642 __le16 alloc_rsscos_ctx; 1643 __le16 alloc_cmpl_rings; 1644 __le16 alloc_tx_rings; 1645 __le16 alloc_rx_rings; 1646 __le16 alloc_l2_ctx; 1647 __le16 alloc_vnics; 1648 __le16 admin_mtu; 1649 __le16 mru; 1650 __le16 stat_ctx_id; 1651 u8 port_partition_type; 1652 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1653 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1654 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1655 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1656 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1657 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1658 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1659 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1660 u8 port_pf_cnt; 1661 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1662 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1663 __le16 dflt_vnic_id; 1664 __le16 max_mtu_configured; 1665 __le32 min_bw; 1666 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1667 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1668 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1669 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1670 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1671 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1672 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1673 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1674 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1675 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1676 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1677 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1678 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1679 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1680 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1681 __le32 max_bw; 1682 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1683 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1684 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1685 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1686 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1687 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1688 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1689 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1690 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1691 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1692 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1693 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1694 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1695 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1696 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1697 u8 evb_mode; 1698 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1699 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1700 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1701 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1702 u8 options; 1703 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1704 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1705 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1706 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1707 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1708 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1709 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1710 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1711 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1712 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1713 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1714 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1715 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1716 __le16 alloc_vfs; 1717 __le32 alloc_mcast_filters; 1718 __le32 alloc_hw_ring_grps; 1719 __le16 alloc_sp_tx_rings; 1720 __le16 alloc_stat_ctx; 1721 __le16 alloc_msix; 1722 __le16 registered_vfs; 1723 __le16 l2_doorbell_bar_size_kb; 1724 u8 unused_1; 1725 u8 always_1; 1726 __le32 reset_addr_poll; 1727 __le16 legacy_l2_db_size_kb; 1728 __le16 svif_info; 1729 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1730 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1731 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1732 u8 mpc_chnls; 1733 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 1734 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 1735 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 1736 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 1737 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 1738 u8 unused_2[3]; 1739 __le32 partition_min_bw; 1740 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1741 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 1742 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 1743 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1744 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1745 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 1746 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1747 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1748 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1749 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1750 __le32 partition_max_bw; 1751 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1752 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 1753 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 1754 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1755 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1756 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 1757 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1758 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1759 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1760 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1761 __le16 host_mtu; 1762 __le16 alloc_tx_key_ctxs; 1763 __le16 alloc_rx_key_ctxs; 1764 u8 unused_3[5]; 1765 u8 valid; 1766 }; 1767 1768 /* hwrm_func_cfg_input (size:896b/112B) */ 1769 struct hwrm_func_cfg_input { 1770 __le16 req_type; 1771 __le16 cmpl_ring; 1772 __le16 seq_id; 1773 __le16 target_id; 1774 __le64 resp_addr; 1775 __le16 fid; 1776 __le16 num_msix; 1777 __le32 flags; 1778 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1779 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1780 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1781 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1782 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1783 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1784 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1785 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1786 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1787 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1788 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1789 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1790 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1791 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1792 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1793 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1794 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1795 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1796 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1797 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1798 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1799 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1800 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1801 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1802 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 1803 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1804 __le32 enables; 1805 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1806 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1807 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1808 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1809 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1810 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1811 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1812 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1813 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1814 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1815 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1816 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1817 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1818 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1819 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1820 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1821 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1822 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1823 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1824 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1825 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1826 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1827 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1828 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1829 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1830 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1831 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 1832 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 1833 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 1834 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1835 #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL 1836 #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL 1837 __le16 admin_mtu; 1838 __le16 mru; 1839 __le16 num_rsscos_ctxs; 1840 __le16 num_cmpl_rings; 1841 __le16 num_tx_rings; 1842 __le16 num_rx_rings; 1843 __le16 num_l2_ctxs; 1844 __le16 num_vnics; 1845 __le16 num_stat_ctxs; 1846 __le16 num_hw_ring_grps; 1847 u8 dflt_mac_addr[6]; 1848 __le16 dflt_vlan; 1849 __be32 dflt_ip_addr[4]; 1850 __le32 min_bw; 1851 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1852 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1853 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1854 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1855 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1856 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1857 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1858 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1859 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1860 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1861 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1862 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1863 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1864 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1865 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1866 __le32 max_bw; 1867 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1868 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1869 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1870 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1871 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1872 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1873 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1874 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1875 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1876 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1877 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1878 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1879 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1880 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1881 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1882 __le16 async_event_cr; 1883 u8 vlan_antispoof_mode; 1884 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1885 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1886 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1887 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1888 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1889 u8 allowed_vlan_pris; 1890 u8 evb_mode; 1891 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1892 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1893 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1894 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1895 u8 options; 1896 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1897 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1898 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1899 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1900 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1901 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1902 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1903 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1904 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1905 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1906 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1907 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1908 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1909 __le16 num_mcast_filters; 1910 __le16 schq_id; 1911 __le16 mpc_chnls; 1912 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 1913 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 1914 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 1915 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 1916 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 1917 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 1918 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 1919 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 1920 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 1921 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 1922 __le32 partition_min_bw; 1923 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1924 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 1925 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 1926 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 1927 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 1928 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 1929 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1930 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 1931 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1932 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 1933 __le32 partition_max_bw; 1934 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1935 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 1936 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 1937 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 1938 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 1939 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 1940 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1941 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 1942 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1943 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 1944 __be16 tpid; 1945 __le16 host_mtu; 1946 __le16 num_tx_key_ctxs; 1947 __le16 num_rx_key_ctxs; 1948 u8 unused_0[4]; 1949 }; 1950 1951 /* hwrm_func_cfg_output (size:128b/16B) */ 1952 struct hwrm_func_cfg_output { 1953 __le16 error_code; 1954 __le16 req_type; 1955 __le16 seq_id; 1956 __le16 resp_len; 1957 u8 unused_0[7]; 1958 u8 valid; 1959 }; 1960 1961 /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 1962 struct hwrm_func_cfg_cmd_err { 1963 u8 code; 1964 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 1965 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 1966 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 1967 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 1968 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 1969 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 1970 u8 unused_0[7]; 1971 }; 1972 1973 /* hwrm_func_qstats_input (size:192b/24B) */ 1974 struct hwrm_func_qstats_input { 1975 __le16 req_type; 1976 __le16 cmpl_ring; 1977 __le16 seq_id; 1978 __le16 target_id; 1979 __le64 resp_addr; 1980 __le16 fid; 1981 u8 flags; 1982 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1983 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1984 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1985 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1986 u8 unused_0[5]; 1987 }; 1988 1989 /* hwrm_func_qstats_output (size:1408b/176B) */ 1990 struct hwrm_func_qstats_output { 1991 __le16 error_code; 1992 __le16 req_type; 1993 __le16 seq_id; 1994 __le16 resp_len; 1995 __le64 tx_ucast_pkts; 1996 __le64 tx_mcast_pkts; 1997 __le64 tx_bcast_pkts; 1998 __le64 tx_discard_pkts; 1999 __le64 tx_drop_pkts; 2000 __le64 tx_ucast_bytes; 2001 __le64 tx_mcast_bytes; 2002 __le64 tx_bcast_bytes; 2003 __le64 rx_ucast_pkts; 2004 __le64 rx_mcast_pkts; 2005 __le64 rx_bcast_pkts; 2006 __le64 rx_discard_pkts; 2007 __le64 rx_drop_pkts; 2008 __le64 rx_ucast_bytes; 2009 __le64 rx_mcast_bytes; 2010 __le64 rx_bcast_bytes; 2011 __le64 rx_agg_pkts; 2012 __le64 rx_agg_bytes; 2013 __le64 rx_agg_events; 2014 __le64 rx_agg_aborts; 2015 u8 unused_0[7]; 2016 u8 valid; 2017 }; 2018 2019 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2020 struct hwrm_func_qstats_ext_input { 2021 __le16 req_type; 2022 __le16 cmpl_ring; 2023 __le16 seq_id; 2024 __le16 target_id; 2025 __le64 resp_addr; 2026 __le16 fid; 2027 u8 flags; 2028 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2029 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2030 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2031 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2032 u8 unused_0[1]; 2033 __le32 enables; 2034 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2035 __le16 schq_id; 2036 __le16 traffic_class; 2037 u8 unused_1[4]; 2038 }; 2039 2040 /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2041 struct hwrm_func_qstats_ext_output { 2042 __le16 error_code; 2043 __le16 req_type; 2044 __le16 seq_id; 2045 __le16 resp_len; 2046 __le64 rx_ucast_pkts; 2047 __le64 rx_mcast_pkts; 2048 __le64 rx_bcast_pkts; 2049 __le64 rx_discard_pkts; 2050 __le64 rx_error_pkts; 2051 __le64 rx_ucast_bytes; 2052 __le64 rx_mcast_bytes; 2053 __le64 rx_bcast_bytes; 2054 __le64 tx_ucast_pkts; 2055 __le64 tx_mcast_pkts; 2056 __le64 tx_bcast_pkts; 2057 __le64 tx_error_pkts; 2058 __le64 tx_discard_pkts; 2059 __le64 tx_ucast_bytes; 2060 __le64 tx_mcast_bytes; 2061 __le64 tx_bcast_bytes; 2062 __le64 rx_tpa_eligible_pkt; 2063 __le64 rx_tpa_eligible_bytes; 2064 __le64 rx_tpa_pkt; 2065 __le64 rx_tpa_bytes; 2066 __le64 rx_tpa_errors; 2067 __le64 rx_tpa_events; 2068 u8 unused_0[7]; 2069 u8 valid; 2070 }; 2071 2072 /* hwrm_func_clr_stats_input (size:192b/24B) */ 2073 struct hwrm_func_clr_stats_input { 2074 __le16 req_type; 2075 __le16 cmpl_ring; 2076 __le16 seq_id; 2077 __le16 target_id; 2078 __le64 resp_addr; 2079 __le16 fid; 2080 u8 unused_0[6]; 2081 }; 2082 2083 /* hwrm_func_clr_stats_output (size:128b/16B) */ 2084 struct hwrm_func_clr_stats_output { 2085 __le16 error_code; 2086 __le16 req_type; 2087 __le16 seq_id; 2088 __le16 resp_len; 2089 u8 unused_0[7]; 2090 u8 valid; 2091 }; 2092 2093 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2094 struct hwrm_func_vf_resc_free_input { 2095 __le16 req_type; 2096 __le16 cmpl_ring; 2097 __le16 seq_id; 2098 __le16 target_id; 2099 __le64 resp_addr; 2100 __le16 vf_id; 2101 u8 unused_0[6]; 2102 }; 2103 2104 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2105 struct hwrm_func_vf_resc_free_output { 2106 __le16 error_code; 2107 __le16 req_type; 2108 __le16 seq_id; 2109 __le16 resp_len; 2110 u8 unused_0[7]; 2111 u8 valid; 2112 }; 2113 2114 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2115 struct hwrm_func_drv_rgtr_input { 2116 __le16 req_type; 2117 __le16 cmpl_ring; 2118 __le16 seq_id; 2119 __le16 target_id; 2120 __le64 resp_addr; 2121 __le32 flags; 2122 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2123 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2124 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2125 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2126 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2127 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2128 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2129 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2130 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2131 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2132 __le32 enables; 2133 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2134 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2135 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2136 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2137 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2138 __le16 os_type; 2139 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2140 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2141 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2142 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2143 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2144 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2145 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2146 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2147 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2148 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2149 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2150 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2151 u8 ver_maj_8b; 2152 u8 ver_min_8b; 2153 u8 ver_upd_8b; 2154 u8 unused_0[3]; 2155 __le32 timestamp; 2156 u8 unused_1[4]; 2157 __le32 vf_req_fwd[8]; 2158 __le32 async_event_fwd[8]; 2159 __le16 ver_maj; 2160 __le16 ver_min; 2161 __le16 ver_upd; 2162 __le16 ver_patch; 2163 }; 2164 2165 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2166 struct hwrm_func_drv_rgtr_output { 2167 __le16 error_code; 2168 __le16 req_type; 2169 __le16 seq_id; 2170 __le16 resp_len; 2171 __le32 flags; 2172 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2173 u8 unused_0[3]; 2174 u8 valid; 2175 }; 2176 2177 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2178 struct hwrm_func_drv_unrgtr_input { 2179 __le16 req_type; 2180 __le16 cmpl_ring; 2181 __le16 seq_id; 2182 __le16 target_id; 2183 __le64 resp_addr; 2184 __le32 flags; 2185 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2186 u8 unused_0[4]; 2187 }; 2188 2189 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2190 struct hwrm_func_drv_unrgtr_output { 2191 __le16 error_code; 2192 __le16 req_type; 2193 __le16 seq_id; 2194 __le16 resp_len; 2195 u8 unused_0[7]; 2196 u8 valid; 2197 }; 2198 2199 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2200 struct hwrm_func_buf_rgtr_input { 2201 __le16 req_type; 2202 __le16 cmpl_ring; 2203 __le16 seq_id; 2204 __le16 target_id; 2205 __le64 resp_addr; 2206 __le32 enables; 2207 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2208 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2209 __le16 vf_id; 2210 __le16 req_buf_num_pages; 2211 __le16 req_buf_page_size; 2212 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2213 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2214 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2215 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2216 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2217 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2218 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2219 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2220 __le16 req_buf_len; 2221 __le16 resp_buf_len; 2222 u8 unused_0[2]; 2223 __le64 req_buf_page_addr0; 2224 __le64 req_buf_page_addr1; 2225 __le64 req_buf_page_addr2; 2226 __le64 req_buf_page_addr3; 2227 __le64 req_buf_page_addr4; 2228 __le64 req_buf_page_addr5; 2229 __le64 req_buf_page_addr6; 2230 __le64 req_buf_page_addr7; 2231 __le64 req_buf_page_addr8; 2232 __le64 req_buf_page_addr9; 2233 __le64 error_buf_addr; 2234 __le64 resp_buf_addr; 2235 }; 2236 2237 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2238 struct hwrm_func_buf_rgtr_output { 2239 __le16 error_code; 2240 __le16 req_type; 2241 __le16 seq_id; 2242 __le16 resp_len; 2243 u8 unused_0[7]; 2244 u8 valid; 2245 }; 2246 2247 /* hwrm_func_drv_qver_input (size:192b/24B) */ 2248 struct hwrm_func_drv_qver_input { 2249 __le16 req_type; 2250 __le16 cmpl_ring; 2251 __le16 seq_id; 2252 __le16 target_id; 2253 __le64 resp_addr; 2254 __le32 reserved; 2255 __le16 fid; 2256 u8 unused_0[2]; 2257 }; 2258 2259 /* hwrm_func_drv_qver_output (size:256b/32B) */ 2260 struct hwrm_func_drv_qver_output { 2261 __le16 error_code; 2262 __le16 req_type; 2263 __le16 seq_id; 2264 __le16 resp_len; 2265 __le16 os_type; 2266 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2267 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2268 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2269 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2270 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2271 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2272 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2273 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2274 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2275 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2276 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2277 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2278 u8 ver_maj_8b; 2279 u8 ver_min_8b; 2280 u8 ver_upd_8b; 2281 u8 unused_0[3]; 2282 __le16 ver_maj; 2283 __le16 ver_min; 2284 __le16 ver_upd; 2285 __le16 ver_patch; 2286 u8 unused_1[7]; 2287 u8 valid; 2288 }; 2289 2290 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2291 struct hwrm_func_resource_qcaps_input { 2292 __le16 req_type; 2293 __le16 cmpl_ring; 2294 __le16 seq_id; 2295 __le16 target_id; 2296 __le64 resp_addr; 2297 __le16 fid; 2298 u8 unused_0[6]; 2299 }; 2300 2301 /* hwrm_func_resource_qcaps_output (size:512b/64B) */ 2302 struct hwrm_func_resource_qcaps_output { 2303 __le16 error_code; 2304 __le16 req_type; 2305 __le16 seq_id; 2306 __le16 resp_len; 2307 __le16 max_vfs; 2308 __le16 max_msix; 2309 __le16 vf_reservation_strategy; 2310 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2311 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2312 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2313 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2314 __le16 min_rsscos_ctx; 2315 __le16 max_rsscos_ctx; 2316 __le16 min_cmpl_rings; 2317 __le16 max_cmpl_rings; 2318 __le16 min_tx_rings; 2319 __le16 max_tx_rings; 2320 __le16 min_rx_rings; 2321 __le16 max_rx_rings; 2322 __le16 min_l2_ctxs; 2323 __le16 max_l2_ctxs; 2324 __le16 min_vnics; 2325 __le16 max_vnics; 2326 __le16 min_stat_ctx; 2327 __le16 max_stat_ctx; 2328 __le16 min_hw_ring_grps; 2329 __le16 max_hw_ring_grps; 2330 __le16 max_tx_scheduler_inputs; 2331 __le16 flags; 2332 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2333 __le16 min_tx_key_ctxs; 2334 __le16 max_tx_key_ctxs; 2335 __le16 min_rx_key_ctxs; 2336 __le16 max_rx_key_ctxs; 2337 u8 unused_0[5]; 2338 u8 valid; 2339 }; 2340 2341 /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ 2342 struct hwrm_func_vf_resource_cfg_input { 2343 __le16 req_type; 2344 __le16 cmpl_ring; 2345 __le16 seq_id; 2346 __le16 target_id; 2347 __le64 resp_addr; 2348 __le16 vf_id; 2349 __le16 max_msix; 2350 __le16 min_rsscos_ctx; 2351 __le16 max_rsscos_ctx; 2352 __le16 min_cmpl_rings; 2353 __le16 max_cmpl_rings; 2354 __le16 min_tx_rings; 2355 __le16 max_tx_rings; 2356 __le16 min_rx_rings; 2357 __le16 max_rx_rings; 2358 __le16 min_l2_ctxs; 2359 __le16 max_l2_ctxs; 2360 __le16 min_vnics; 2361 __le16 max_vnics; 2362 __le16 min_stat_ctx; 2363 __le16 max_stat_ctx; 2364 __le16 min_hw_ring_grps; 2365 __le16 max_hw_ring_grps; 2366 __le16 flags; 2367 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2368 __le16 min_tx_key_ctxs; 2369 __le16 max_tx_key_ctxs; 2370 __le16 min_rx_key_ctxs; 2371 __le16 max_rx_key_ctxs; 2372 u8 unused_0[2]; 2373 }; 2374 2375 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2376 struct hwrm_func_vf_resource_cfg_output { 2377 __le16 error_code; 2378 __le16 req_type; 2379 __le16 seq_id; 2380 __le16 resp_len; 2381 __le16 reserved_rsscos_ctx; 2382 __le16 reserved_cmpl_rings; 2383 __le16 reserved_tx_rings; 2384 __le16 reserved_rx_rings; 2385 __le16 reserved_l2_ctxs; 2386 __le16 reserved_vnics; 2387 __le16 reserved_stat_ctx; 2388 __le16 reserved_hw_ring_grps; 2389 __le16 reserved_tx_key_ctxs; 2390 __le16 reserved_rx_key_ctxs; 2391 u8 unused_0[3]; 2392 u8 valid; 2393 }; 2394 2395 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2396 struct hwrm_func_backing_store_qcaps_input { 2397 __le16 req_type; 2398 __le16 cmpl_ring; 2399 __le16 seq_id; 2400 __le16 target_id; 2401 __le64 resp_addr; 2402 }; 2403 2404 /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2405 struct hwrm_func_backing_store_qcaps_output { 2406 __le16 error_code; 2407 __le16 req_type; 2408 __le16 seq_id; 2409 __le16 resp_len; 2410 __le32 qp_max_entries; 2411 __le16 qp_min_qp1_entries; 2412 __le16 qp_max_l2_entries; 2413 __le16 qp_entry_size; 2414 __le16 srq_max_l2_entries; 2415 __le32 srq_max_entries; 2416 __le16 srq_entry_size; 2417 __le16 cq_max_l2_entries; 2418 __le32 cq_max_entries; 2419 __le16 cq_entry_size; 2420 __le16 vnic_max_vnic_entries; 2421 __le16 vnic_max_ring_table_entries; 2422 __le16 vnic_entry_size; 2423 __le32 stat_max_entries; 2424 __le16 stat_entry_size; 2425 __le16 tqm_entry_size; 2426 __le32 tqm_min_entries_per_ring; 2427 __le32 tqm_max_entries_per_ring; 2428 __le32 mrav_max_entries; 2429 __le16 mrav_entry_size; 2430 __le16 tim_entry_size; 2431 __le32 tim_max_entries; 2432 __le16 mrav_num_entries_units; 2433 u8 tqm_entries_multiple; 2434 u8 ctx_kind_initializer; 2435 __le16 ctx_init_mask; 2436 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2437 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2438 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2439 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2440 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2441 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2442 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2443 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2444 u8 qp_init_offset; 2445 u8 srq_init_offset; 2446 u8 cq_init_offset; 2447 u8 vnic_init_offset; 2448 u8 tqm_fp_rings_count; 2449 u8 stat_init_offset; 2450 u8 mrav_init_offset; 2451 u8 tqm_fp_rings_count_ext; 2452 u8 tkc_init_offset; 2453 u8 rkc_init_offset; 2454 __le16 tkc_entry_size; 2455 __le16 rkc_entry_size; 2456 __le32 tkc_max_entries; 2457 __le32 rkc_max_entries; 2458 u8 rsvd[7]; 2459 u8 valid; 2460 }; 2461 2462 /* tqm_fp_ring_cfg (size:128b/16B) */ 2463 struct tqm_fp_ring_cfg { 2464 u8 tqm_ring_pg_size_tqm_ring_lvl; 2465 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2466 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2467 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2468 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2469 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2470 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2471 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2472 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2473 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2474 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2475 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2476 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2477 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2478 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2479 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2480 u8 unused[3]; 2481 __le32 tqm_ring_num_entries; 2482 __le64 tqm_ring_page_dir; 2483 }; 2484 2485 /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 2486 struct hwrm_func_backing_store_cfg_input { 2487 __le16 req_type; 2488 __le16 cmpl_ring; 2489 __le16 seq_id; 2490 __le16 target_id; 2491 __le64 resp_addr; 2492 __le32 flags; 2493 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2494 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2495 __le32 enables; 2496 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2497 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2498 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2499 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2500 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2501 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2502 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2503 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2504 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2505 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2506 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2507 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2508 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2509 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2510 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2511 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2512 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2513 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2514 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2515 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 2516 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 2517 u8 qpc_pg_size_qpc_lvl; 2518 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2519 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 2520 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 2521 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 2522 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 2523 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 2524 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 2525 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 2526 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 2527 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 2528 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 2529 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 2530 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 2531 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 2532 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 2533 u8 srq_pg_size_srq_lvl; 2534 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 2535 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 2536 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 2537 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 2538 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 2539 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 2540 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2541 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2542 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2543 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2544 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2545 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2546 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2547 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2548 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2549 u8 cq_pg_size_cq_lvl; 2550 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2551 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2552 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2553 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2554 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2555 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2556 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2557 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2558 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2559 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2560 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2561 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2562 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2563 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2564 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2565 u8 vnic_pg_size_vnic_lvl; 2566 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2567 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2568 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2569 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2570 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2571 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2572 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2573 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2574 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2575 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2576 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2577 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2578 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2579 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2580 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2581 u8 stat_pg_size_stat_lvl; 2582 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2583 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2584 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2585 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2586 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2587 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2588 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2589 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2590 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2591 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2592 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2593 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2594 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2595 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2596 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2597 u8 tqm_sp_pg_size_tqm_sp_lvl; 2598 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2599 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2600 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2601 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2602 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2603 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2604 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2605 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2606 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2607 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2608 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2609 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2610 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2611 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2612 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2613 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2614 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2615 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2616 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2617 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2618 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2619 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2620 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2621 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2622 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2623 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2624 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2625 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2626 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2627 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2628 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2629 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2630 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2631 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2632 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2633 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2634 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2635 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2636 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2637 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2638 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2639 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2640 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2641 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2642 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2643 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2644 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2645 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2646 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2647 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2648 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2649 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2650 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2651 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2652 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2653 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2654 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2655 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2656 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2657 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2658 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2659 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2660 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2661 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2662 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2663 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2664 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2665 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2666 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2667 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2668 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2669 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2670 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2671 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2672 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2673 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2674 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2675 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2676 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2677 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2678 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2679 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2680 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2681 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2682 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2683 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2684 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2685 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2686 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2687 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2688 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2689 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2690 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2691 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2692 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2693 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2694 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2695 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2696 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2697 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2698 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2699 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2700 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2701 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2702 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2703 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2704 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2705 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2706 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2707 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2708 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2709 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2710 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2711 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2712 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2713 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2714 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2715 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2716 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2717 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2718 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2719 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2720 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2721 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2722 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2723 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2724 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2725 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2726 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2727 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2728 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2729 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2730 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2731 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2732 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2733 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2734 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2735 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2736 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2737 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2738 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2739 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2740 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2741 u8 mrav_pg_size_mrav_lvl; 2742 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2743 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2744 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2745 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2746 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2747 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2748 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2749 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2750 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2751 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2752 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2753 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2754 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2755 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2756 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2757 u8 tim_pg_size_tim_lvl; 2758 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2759 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2760 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2761 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2762 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2763 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2764 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2765 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2766 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2767 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2768 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2769 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2770 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2771 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2772 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2773 __le64 qpc_page_dir; 2774 __le64 srq_page_dir; 2775 __le64 cq_page_dir; 2776 __le64 vnic_page_dir; 2777 __le64 stat_page_dir; 2778 __le64 tqm_sp_page_dir; 2779 __le64 tqm_ring0_page_dir; 2780 __le64 tqm_ring1_page_dir; 2781 __le64 tqm_ring2_page_dir; 2782 __le64 tqm_ring3_page_dir; 2783 __le64 tqm_ring4_page_dir; 2784 __le64 tqm_ring5_page_dir; 2785 __le64 tqm_ring6_page_dir; 2786 __le64 tqm_ring7_page_dir; 2787 __le64 mrav_page_dir; 2788 __le64 tim_page_dir; 2789 __le32 qp_num_entries; 2790 __le32 srq_num_entries; 2791 __le32 cq_num_entries; 2792 __le32 stat_num_entries; 2793 __le32 tqm_sp_num_entries; 2794 __le32 tqm_ring0_num_entries; 2795 __le32 tqm_ring1_num_entries; 2796 __le32 tqm_ring2_num_entries; 2797 __le32 tqm_ring3_num_entries; 2798 __le32 tqm_ring4_num_entries; 2799 __le32 tqm_ring5_num_entries; 2800 __le32 tqm_ring6_num_entries; 2801 __le32 tqm_ring7_num_entries; 2802 __le32 mrav_num_entries; 2803 __le32 tim_num_entries; 2804 __le16 qp_num_qp1_entries; 2805 __le16 qp_num_l2_entries; 2806 __le16 qp_entry_size; 2807 __le16 srq_num_l2_entries; 2808 __le16 srq_entry_size; 2809 __le16 cq_num_l2_entries; 2810 __le16 cq_entry_size; 2811 __le16 vnic_num_vnic_entries; 2812 __le16 vnic_num_ring_table_entries; 2813 __le16 vnic_entry_size; 2814 __le16 stat_entry_size; 2815 __le16 tqm_entry_size; 2816 __le16 mrav_entry_size; 2817 __le16 tim_entry_size; 2818 u8 tqm_ring8_pg_size_tqm_ring_lvl; 2819 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2820 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2821 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2822 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2823 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2824 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2825 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2826 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2827 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2828 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2829 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2830 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2831 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2832 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2833 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2834 u8 ring8_unused[3]; 2835 __le32 tqm_ring8_num_entries; 2836 __le64 tqm_ring8_page_dir; 2837 u8 tqm_ring9_pg_size_tqm_ring_lvl; 2838 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2839 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2840 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2841 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2842 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2843 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2844 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2845 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2846 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2847 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2848 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2849 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2850 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2851 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2852 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2853 u8 ring9_unused[3]; 2854 __le32 tqm_ring9_num_entries; 2855 __le64 tqm_ring9_page_dir; 2856 u8 tqm_ring10_pg_size_tqm_ring_lvl; 2857 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2858 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2859 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2860 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2861 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2862 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2863 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2864 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2865 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2866 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2867 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2868 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2869 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2870 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2871 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2872 u8 ring10_unused[3]; 2873 __le32 tqm_ring10_num_entries; 2874 __le64 tqm_ring10_page_dir; 2875 __le32 tkc_num_entries; 2876 __le32 rkc_num_entries; 2877 __le64 tkc_page_dir; 2878 __le64 rkc_page_dir; 2879 __le16 tkc_entry_size; 2880 __le16 rkc_entry_size; 2881 u8 tkc_pg_size_tkc_lvl; 2882 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 2883 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 2884 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 2885 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 2886 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 2887 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 2888 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 2889 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 2890 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 2891 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 2892 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 2893 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 2894 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 2895 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 2896 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 2897 u8 rkc_pg_size_rkc_lvl; 2898 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 2899 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 2900 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 2901 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 2902 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 2903 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 2904 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 2905 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 2906 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 2907 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 2908 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 2909 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 2910 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 2911 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 2912 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 2913 u8 rsvd[2]; 2914 }; 2915 2916 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2917 struct hwrm_func_backing_store_cfg_output { 2918 __le16 error_code; 2919 __le16 req_type; 2920 __le16 seq_id; 2921 __le16 resp_len; 2922 u8 unused_0[7]; 2923 u8 valid; 2924 }; 2925 2926 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2927 struct hwrm_error_recovery_qcfg_input { 2928 __le16 req_type; 2929 __le16 cmpl_ring; 2930 __le16 seq_id; 2931 __le16 target_id; 2932 __le64 resp_addr; 2933 u8 unused_0[8]; 2934 }; 2935 2936 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2937 struct hwrm_error_recovery_qcfg_output { 2938 __le16 error_code; 2939 __le16 req_type; 2940 __le16 seq_id; 2941 __le16 resp_len; 2942 __le32 flags; 2943 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2944 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2945 __le32 driver_polling_freq; 2946 __le32 master_func_wait_period; 2947 __le32 normal_func_wait_period; 2948 __le32 master_func_wait_period_after_reset; 2949 __le32 max_bailout_time_after_reset; 2950 __le32 fw_health_status_reg; 2951 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2952 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2953 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2954 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2955 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2956 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2957 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2958 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2959 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2960 __le32 fw_heartbeat_reg; 2961 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2962 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2963 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2964 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2965 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2966 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2967 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2968 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2969 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2970 __le32 fw_reset_cnt_reg; 2971 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2972 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2973 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2974 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2975 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2976 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2977 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2978 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2979 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2980 __le32 reset_inprogress_reg; 2981 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2982 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2983 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2984 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2985 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2986 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2987 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2988 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2989 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2990 __le32 reset_inprogress_reg_mask; 2991 u8 unused_0[3]; 2992 u8 reg_array_cnt; 2993 __le32 reset_reg[16]; 2994 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2995 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2996 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2997 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2998 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2999 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3000 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3001 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3002 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3003 __le32 reset_reg_val[16]; 3004 u8 delay_after_reset[16]; 3005 __le32 err_recovery_cnt_reg; 3006 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3007 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3008 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3009 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3010 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3011 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3012 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3013 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3014 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3015 u8 unused_1[3]; 3016 u8 valid; 3017 }; 3018 3019 /* hwrm_func_echo_response_input (size:192b/24B) */ 3020 struct hwrm_func_echo_response_input { 3021 __le16 req_type; 3022 __le16 cmpl_ring; 3023 __le16 seq_id; 3024 __le16 target_id; 3025 __le64 resp_addr; 3026 __le32 event_data1; 3027 __le32 event_data2; 3028 }; 3029 3030 /* hwrm_func_echo_response_output (size:128b/16B) */ 3031 struct hwrm_func_echo_response_output { 3032 __le16 error_code; 3033 __le16 req_type; 3034 __le16 seq_id; 3035 __le16 resp_len; 3036 u8 unused_0[7]; 3037 u8 valid; 3038 }; 3039 3040 /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3041 struct hwrm_func_ptp_pin_qcfg_input { 3042 __le16 req_type; 3043 __le16 cmpl_ring; 3044 __le16 seq_id; 3045 __le16 target_id; 3046 __le64 resp_addr; 3047 u8 unused_0[8]; 3048 }; 3049 3050 /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3051 struct hwrm_func_ptp_pin_qcfg_output { 3052 __le16 error_code; 3053 __le16 req_type; 3054 __le16 seq_id; 3055 __le16 resp_len; 3056 u8 num_pins; 3057 u8 state; 3058 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3059 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3060 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3061 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3062 u8 pin0_usage; 3063 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3064 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3065 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3066 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3067 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3068 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3069 u8 pin1_usage; 3070 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3071 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3072 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3073 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3074 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3075 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3076 u8 pin2_usage; 3077 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3078 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3079 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3080 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3081 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3082 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 3083 u8 pin3_usage; 3084 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3085 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3086 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3087 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3088 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3089 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 3090 u8 unused_0; 3091 u8 valid; 3092 }; 3093 3094 /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3095 struct hwrm_func_ptp_pin_cfg_input { 3096 __le16 req_type; 3097 __le16 cmpl_ring; 3098 __le16 seq_id; 3099 __le16 target_id; 3100 __le64 resp_addr; 3101 __le32 enables; 3102 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3103 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3104 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3105 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3106 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3107 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3108 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3109 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3110 u8 pin0_state; 3111 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3112 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3113 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3114 u8 pin0_usage; 3115 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3116 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3117 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3118 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3119 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3120 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3121 u8 pin1_state; 3122 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3123 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3124 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3125 u8 pin1_usage; 3126 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3127 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3128 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3129 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3130 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3131 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3132 u8 pin2_state; 3133 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3134 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3135 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3136 u8 pin2_usage; 3137 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3138 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3139 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3140 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3141 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3142 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 3143 u8 pin3_state; 3144 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3145 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3146 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3147 u8 pin3_usage; 3148 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3149 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3150 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3151 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3152 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3153 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 3154 u8 unused_0[4]; 3155 }; 3156 3157 /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3158 struct hwrm_func_ptp_pin_cfg_output { 3159 __le16 error_code; 3160 __le16 req_type; 3161 __le16 seq_id; 3162 __le16 resp_len; 3163 u8 unused_0[7]; 3164 u8 valid; 3165 }; 3166 3167 /* hwrm_func_ptp_cfg_input (size:320b/40B) */ 3168 struct hwrm_func_ptp_cfg_input { 3169 __le16 req_type; 3170 __le16 cmpl_ring; 3171 __le16 seq_id; 3172 __le16 target_id; 3173 __le64 resp_addr; 3174 __le16 enables; 3175 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3176 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3177 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3178 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3179 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3180 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3181 u8 ptp_pps_event; 3182 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3183 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3184 u8 ptp_freq_adj_dll_source; 3185 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3186 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3187 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3188 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3189 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3190 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3191 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3192 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3193 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3194 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3195 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3196 u8 ptp_freq_adj_dll_phase; 3197 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3198 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3199 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3200 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3201 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 3202 u8 unused_0[3]; 3203 __le32 ptp_freq_adj_ext_period; 3204 __le32 ptp_freq_adj_ext_up; 3205 __le32 ptp_freq_adj_ext_phase_lower; 3206 __le32 ptp_freq_adj_ext_phase_upper; 3207 }; 3208 3209 /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3210 struct hwrm_func_ptp_cfg_output { 3211 __le16 error_code; 3212 __le16 req_type; 3213 __le16 seq_id; 3214 __le16 resp_len; 3215 u8 unused_0[7]; 3216 u8 valid; 3217 }; 3218 3219 /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3220 struct hwrm_func_ptp_ts_query_input { 3221 __le16 req_type; 3222 __le16 cmpl_ring; 3223 __le16 seq_id; 3224 __le16 target_id; 3225 __le64 resp_addr; 3226 __le32 flags; 3227 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3228 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3229 u8 unused_0[4]; 3230 }; 3231 3232 /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3233 struct hwrm_func_ptp_ts_query_output { 3234 __le16 error_code; 3235 __le16 req_type; 3236 __le16 seq_id; 3237 __le16 resp_len; 3238 __le64 pps_event_ts; 3239 __le64 ptm_res_local_ts; 3240 __le64 ptm_pmstr_ts; 3241 __le32 ptm_mstr_prop_dly; 3242 u8 unused_0[3]; 3243 u8 valid; 3244 }; 3245 3246 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 3247 struct hwrm_func_drv_if_change_input { 3248 __le16 req_type; 3249 __le16 cmpl_ring; 3250 __le16 seq_id; 3251 __le16 target_id; 3252 __le64 resp_addr; 3253 __le32 flags; 3254 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 3255 __le32 unused; 3256 }; 3257 3258 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 3259 struct hwrm_func_drv_if_change_output { 3260 __le16 error_code; 3261 __le16 req_type; 3262 __le16 seq_id; 3263 __le16 resp_len; 3264 __le32 flags; 3265 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 3266 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 3267 u8 unused_0[3]; 3268 u8 valid; 3269 }; 3270 3271 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3272 struct hwrm_port_phy_cfg_input { 3273 __le16 req_type; 3274 __le16 cmpl_ring; 3275 __le16 seq_id; 3276 __le16 target_id; 3277 __le64 resp_addr; 3278 __le32 flags; 3279 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 3280 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3281 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3282 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 3283 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 3284 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 3285 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 3286 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3287 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3288 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3289 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3290 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3291 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3292 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 3293 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3294 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3295 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 3296 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 3297 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 3298 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 3299 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 3300 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 3301 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3302 __le32 enables; 3303 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3304 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3305 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3306 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3307 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3308 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3309 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3310 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3311 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 3312 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 3313 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3314 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3315 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3316 __le16 port_id; 3317 __le16 force_link_speed; 3318 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3319 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3320 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3321 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3322 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3323 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3324 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3325 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3326 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3327 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3328 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3329 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3330 u8 auto_mode; 3331 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3332 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3333 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3334 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3335 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3336 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3337 u8 auto_duplex; 3338 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3339 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3340 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3341 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3342 u8 auto_pause; 3343 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3344 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 3345 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3346 u8 unused_0; 3347 __le16 auto_link_speed; 3348 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3349 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3350 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3351 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3352 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3353 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3354 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3355 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3356 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3359 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3360 __le16 auto_link_speed_mask; 3361 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3362 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3363 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3364 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3365 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3366 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3367 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3368 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3371 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3372 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3373 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3374 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3375 u8 wirespeed; 3376 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3377 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3378 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3379 u8 lpbk; 3380 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3381 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3382 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 3383 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 3384 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3385 u8 force_pause; 3386 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3387 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3388 u8 unused_1; 3389 __le32 preemphasis; 3390 __le16 eee_link_speed_mask; 3391 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3392 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 3393 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3394 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 3395 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3396 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3397 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3398 __le16 force_pam4_link_speed; 3399 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3400 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3401 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3402 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 3403 __le32 tx_lpi_timer; 3404 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 3405 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3406 __le16 auto_link_pam4_speed_mask; 3407 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3408 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3409 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3410 u8 unused_2[2]; 3411 }; 3412 3413 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3414 struct hwrm_port_phy_cfg_output { 3415 __le16 error_code; 3416 __le16 req_type; 3417 __le16 seq_id; 3418 __le16 resp_len; 3419 u8 unused_0[7]; 3420 u8 valid; 3421 }; 3422 3423 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3424 struct hwrm_port_phy_cfg_cmd_err { 3425 u8 code; 3426 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3427 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3428 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3429 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3430 u8 unused_0[7]; 3431 }; 3432 3433 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3434 struct hwrm_port_phy_qcfg_input { 3435 __le16 req_type; 3436 __le16 cmpl_ring; 3437 __le16 seq_id; 3438 __le16 target_id; 3439 __le64 resp_addr; 3440 __le16 port_id; 3441 u8 unused_0[6]; 3442 }; 3443 3444 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3445 struct hwrm_port_phy_qcfg_output { 3446 __le16 error_code; 3447 __le16 req_type; 3448 __le16 seq_id; 3449 __le16 resp_len; 3450 u8 link; 3451 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3452 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3453 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3454 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 3455 u8 active_fec_signal_mode; 3456 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 3457 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 3458 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 3459 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 3460 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 3461 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 3462 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 3463 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 3464 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 3465 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 3466 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 3467 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 3468 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 3469 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 3470 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3471 __le16 link_speed; 3472 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3473 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3474 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3475 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3476 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3477 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3478 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3479 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3480 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3481 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 3482 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3483 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3484 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3485 u8 duplex_cfg; 3486 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3487 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3488 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3489 u8 pause; 3490 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3491 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3492 __le16 support_speeds; 3493 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3494 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3495 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3496 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3497 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3498 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3499 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3500 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3501 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3502 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3503 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 3504 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 3505 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 3506 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3507 __le16 force_link_speed; 3508 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3509 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3510 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3511 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3512 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3513 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3514 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3515 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3516 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3517 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3518 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3519 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3520 u8 auto_mode; 3521 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 3522 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 3523 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 3524 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 3525 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 3526 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 3527 u8 auto_pause; 3528 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 3529 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 3530 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3531 __le16 auto_link_speed; 3532 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 3533 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 3534 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 3535 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 3536 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 3537 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 3538 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 3539 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 3540 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 3541 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 3542 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 3543 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 3544 __le16 auto_link_speed_mask; 3545 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3546 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3547 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3548 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3549 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3550 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3551 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3552 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3553 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3554 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3555 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 3556 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 3557 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 3558 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3559 u8 wirespeed; 3560 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 3561 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 3562 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 3563 u8 lpbk; 3564 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 3565 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 3566 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 3567 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 3568 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 3569 u8 force_pause; 3570 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 3571 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 3572 u8 module_status; 3573 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 3574 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 3575 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 3576 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 3577 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 3578 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 3579 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 3580 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 3581 __le32 preemphasis; 3582 u8 phy_maj; 3583 u8 phy_min; 3584 u8 phy_bld; 3585 u8 phy_type; 3586 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 3587 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 3588 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 3589 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 3590 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 3591 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 3592 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 3593 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 3594 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 3595 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 3596 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 3597 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 3598 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 3599 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 3600 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 3601 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 3602 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 3603 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 3604 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 3605 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 3606 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 3607 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 3608 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 3609 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 3610 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 3611 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 3612 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 3613 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 3614 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 3615 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 3616 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 3617 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 3618 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 3619 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 3620 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 3621 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 3622 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 3623 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 3624 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 3625 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 3626 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 3627 u8 media_type; 3628 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 3629 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 3630 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 3631 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 3632 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 3633 u8 xcvr_pkg_type; 3634 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 3635 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 3636 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 3637 u8 eee_config_phy_addr; 3638 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 3639 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 3640 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 3641 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 3642 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 3643 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 3644 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 3645 u8 parallel_detect; 3646 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 3647 __le16 link_partner_adv_speeds; 3648 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 3649 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 3650 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 3651 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 3652 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 3653 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 3654 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 3655 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 3656 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 3657 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 3658 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 3659 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 3660 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 3661 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 3662 u8 link_partner_adv_auto_mode; 3663 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 3664 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 3665 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 3666 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 3667 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 3668 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 3669 u8 link_partner_adv_pause; 3670 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 3671 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 3672 __le16 adv_eee_link_speed_mask; 3673 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3674 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3675 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3676 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3677 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3678 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3679 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3680 __le16 link_partner_adv_eee_link_speed_mask; 3681 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 3682 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 3683 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 3684 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 3685 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 3686 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 3687 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 3688 __le32 xcvr_identifier_type_tx_lpi_timer; 3689 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 3690 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 3691 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 3692 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 3693 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 3694 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 3695 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 3696 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 3697 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3698 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3699 __le16 fec_cfg; 3700 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3701 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3702 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3703 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3704 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3705 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3706 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3707 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3708 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 3709 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 3710 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 3711 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 3712 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 3713 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 3714 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3715 u8 duplex_state; 3716 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3717 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3718 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3719 u8 option_flags; 3720 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 3721 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 3722 char phy_vendor_name[16]; 3723 char phy_vendor_partnumber[16]; 3724 __le16 support_pam4_speeds; 3725 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3726 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3727 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3728 __le16 force_pam4_link_speed; 3729 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3730 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3731 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3732 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3733 __le16 auto_pam4_link_speed_mask; 3734 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3735 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3736 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 3737 u8 link_partner_pam4_adv_speeds; 3738 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3739 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3740 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3741 u8 valid; 3742 }; 3743 3744 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3745 struct hwrm_port_mac_cfg_input { 3746 __le16 req_type; 3747 __le16 cmpl_ring; 3748 __le16 seq_id; 3749 __le16 target_id; 3750 __le64 resp_addr; 3751 __le32 flags; 3752 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3753 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3754 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3755 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 3756 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 3757 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 3758 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 3759 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3760 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3761 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3762 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3763 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3764 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 3765 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3766 __le32 enables; 3767 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3768 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3769 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3770 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3771 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 3772 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 3773 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3774 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 3775 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 3776 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 3777 __le16 port_id; 3778 u8 ipg; 3779 u8 lpbk; 3780 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3781 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3782 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3783 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3784 u8 vlan_pri2cos_map_pri; 3785 u8 reserved1; 3786 u8 tunnel_pri2cos_map_pri; 3787 u8 dscp2pri_map_pri; 3788 __le16 rx_ts_capture_ptp_msg_type; 3789 __le16 tx_ts_capture_ptp_msg_type; 3790 u8 cos_field_cfg; 3791 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3792 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3793 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3794 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3795 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3796 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3797 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3798 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3799 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3800 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3801 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3802 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3803 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3804 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3805 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3806 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3807 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3808 u8 unused_0[3]; 3809 __le32 ptp_freq_adj_ppb; 3810 __le32 ptp_adj_phase; 3811 }; 3812 3813 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3814 struct hwrm_port_mac_cfg_output { 3815 __le16 error_code; 3816 __le16 req_type; 3817 __le16 seq_id; 3818 __le16 resp_len; 3819 __le16 mru; 3820 __le16 mtu; 3821 u8 ipg; 3822 u8 lpbk; 3823 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3824 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3825 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3826 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3827 u8 unused_0; 3828 u8 valid; 3829 }; 3830 3831 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3832 struct hwrm_port_mac_ptp_qcfg_input { 3833 __le16 req_type; 3834 __le16 cmpl_ring; 3835 __le16 seq_id; 3836 __le16 target_id; 3837 __le64 resp_addr; 3838 __le16 port_id; 3839 u8 unused_0[6]; 3840 }; 3841 3842 /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 3843 struct hwrm_port_mac_ptp_qcfg_output { 3844 __le16 error_code; 3845 __le16 req_type; 3846 __le16 seq_id; 3847 __le16 resp_len; 3848 u8 flags; 3849 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 3850 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 3851 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3852 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 3853 u8 unused_0[3]; 3854 __le32 rx_ts_reg_off_lower; 3855 __le32 rx_ts_reg_off_upper; 3856 __le32 rx_ts_reg_off_seq_id; 3857 __le32 rx_ts_reg_off_src_id_0; 3858 __le32 rx_ts_reg_off_src_id_1; 3859 __le32 rx_ts_reg_off_src_id_2; 3860 __le32 rx_ts_reg_off_domain_id; 3861 __le32 rx_ts_reg_off_fifo; 3862 __le32 rx_ts_reg_off_fifo_adv; 3863 __le32 rx_ts_reg_off_granularity; 3864 __le32 tx_ts_reg_off_lower; 3865 __le32 tx_ts_reg_off_upper; 3866 __le32 tx_ts_reg_off_seq_id; 3867 __le32 tx_ts_reg_off_fifo; 3868 __le32 tx_ts_reg_off_granularity; 3869 __le32 ts_ref_clock_reg_lower; 3870 __le32 ts_ref_clock_reg_upper; 3871 u8 unused_1[7]; 3872 u8 valid; 3873 }; 3874 3875 /* tx_port_stats (size:3264b/408B) */ 3876 struct tx_port_stats { 3877 __le64 tx_64b_frames; 3878 __le64 tx_65b_127b_frames; 3879 __le64 tx_128b_255b_frames; 3880 __le64 tx_256b_511b_frames; 3881 __le64 tx_512b_1023b_frames; 3882 __le64 tx_1024b_1518b_frames; 3883 __le64 tx_good_vlan_frames; 3884 __le64 tx_1519b_2047b_frames; 3885 __le64 tx_2048b_4095b_frames; 3886 __le64 tx_4096b_9216b_frames; 3887 __le64 tx_9217b_16383b_frames; 3888 __le64 tx_good_frames; 3889 __le64 tx_total_frames; 3890 __le64 tx_ucast_frames; 3891 __le64 tx_mcast_frames; 3892 __le64 tx_bcast_frames; 3893 __le64 tx_pause_frames; 3894 __le64 tx_pfc_frames; 3895 __le64 tx_jabber_frames; 3896 __le64 tx_fcs_err_frames; 3897 __le64 tx_control_frames; 3898 __le64 tx_oversz_frames; 3899 __le64 tx_single_dfrl_frames; 3900 __le64 tx_multi_dfrl_frames; 3901 __le64 tx_single_coll_frames; 3902 __le64 tx_multi_coll_frames; 3903 __le64 tx_late_coll_frames; 3904 __le64 tx_excessive_coll_frames; 3905 __le64 tx_frag_frames; 3906 __le64 tx_err; 3907 __le64 tx_tagged_frames; 3908 __le64 tx_dbl_tagged_frames; 3909 __le64 tx_runt_frames; 3910 __le64 tx_fifo_underruns; 3911 __le64 tx_pfc_ena_frames_pri0; 3912 __le64 tx_pfc_ena_frames_pri1; 3913 __le64 tx_pfc_ena_frames_pri2; 3914 __le64 tx_pfc_ena_frames_pri3; 3915 __le64 tx_pfc_ena_frames_pri4; 3916 __le64 tx_pfc_ena_frames_pri5; 3917 __le64 tx_pfc_ena_frames_pri6; 3918 __le64 tx_pfc_ena_frames_pri7; 3919 __le64 tx_eee_lpi_events; 3920 __le64 tx_eee_lpi_duration; 3921 __le64 tx_llfc_logical_msgs; 3922 __le64 tx_hcfc_msgs; 3923 __le64 tx_total_collisions; 3924 __le64 tx_bytes; 3925 __le64 tx_xthol_frames; 3926 __le64 tx_stat_discard; 3927 __le64 tx_stat_error; 3928 }; 3929 3930 /* rx_port_stats (size:4224b/528B) */ 3931 struct rx_port_stats { 3932 __le64 rx_64b_frames; 3933 __le64 rx_65b_127b_frames; 3934 __le64 rx_128b_255b_frames; 3935 __le64 rx_256b_511b_frames; 3936 __le64 rx_512b_1023b_frames; 3937 __le64 rx_1024b_1518b_frames; 3938 __le64 rx_good_vlan_frames; 3939 __le64 rx_1519b_2047b_frames; 3940 __le64 rx_2048b_4095b_frames; 3941 __le64 rx_4096b_9216b_frames; 3942 __le64 rx_9217b_16383b_frames; 3943 __le64 rx_total_frames; 3944 __le64 rx_ucast_frames; 3945 __le64 rx_mcast_frames; 3946 __le64 rx_bcast_frames; 3947 __le64 rx_fcs_err_frames; 3948 __le64 rx_ctrl_frames; 3949 __le64 rx_pause_frames; 3950 __le64 rx_pfc_frames; 3951 __le64 rx_unsupported_opcode_frames; 3952 __le64 rx_unsupported_da_pausepfc_frames; 3953 __le64 rx_wrong_sa_frames; 3954 __le64 rx_align_err_frames; 3955 __le64 rx_oor_len_frames; 3956 __le64 rx_code_err_frames; 3957 __le64 rx_false_carrier_frames; 3958 __le64 rx_ovrsz_frames; 3959 __le64 rx_jbr_frames; 3960 __le64 rx_mtu_err_frames; 3961 __le64 rx_match_crc_frames; 3962 __le64 rx_promiscuous_frames; 3963 __le64 rx_tagged_frames; 3964 __le64 rx_double_tagged_frames; 3965 __le64 rx_trunc_frames; 3966 __le64 rx_good_frames; 3967 __le64 rx_pfc_xon2xoff_frames_pri0; 3968 __le64 rx_pfc_xon2xoff_frames_pri1; 3969 __le64 rx_pfc_xon2xoff_frames_pri2; 3970 __le64 rx_pfc_xon2xoff_frames_pri3; 3971 __le64 rx_pfc_xon2xoff_frames_pri4; 3972 __le64 rx_pfc_xon2xoff_frames_pri5; 3973 __le64 rx_pfc_xon2xoff_frames_pri6; 3974 __le64 rx_pfc_xon2xoff_frames_pri7; 3975 __le64 rx_pfc_ena_frames_pri0; 3976 __le64 rx_pfc_ena_frames_pri1; 3977 __le64 rx_pfc_ena_frames_pri2; 3978 __le64 rx_pfc_ena_frames_pri3; 3979 __le64 rx_pfc_ena_frames_pri4; 3980 __le64 rx_pfc_ena_frames_pri5; 3981 __le64 rx_pfc_ena_frames_pri6; 3982 __le64 rx_pfc_ena_frames_pri7; 3983 __le64 rx_sch_crc_err_frames; 3984 __le64 rx_undrsz_frames; 3985 __le64 rx_frag_frames; 3986 __le64 rx_eee_lpi_events; 3987 __le64 rx_eee_lpi_duration; 3988 __le64 rx_llfc_physical_msgs; 3989 __le64 rx_llfc_logical_msgs; 3990 __le64 rx_llfc_msgs_with_crc_err; 3991 __le64 rx_hcfc_msgs; 3992 __le64 rx_hcfc_msgs_with_crc_err; 3993 __le64 rx_bytes; 3994 __le64 rx_runt_bytes; 3995 __le64 rx_runt_frames; 3996 __le64 rx_stat_discard; 3997 __le64 rx_stat_err; 3998 }; 3999 4000 /* hwrm_port_qstats_input (size:320b/40B) */ 4001 struct hwrm_port_qstats_input { 4002 __le16 req_type; 4003 __le16 cmpl_ring; 4004 __le16 seq_id; 4005 __le16 target_id; 4006 __le64 resp_addr; 4007 __le16 port_id; 4008 u8 flags; 4009 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4010 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4011 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 4012 u8 unused_0[5]; 4013 __le64 tx_stat_host_addr; 4014 __le64 rx_stat_host_addr; 4015 }; 4016 4017 /* hwrm_port_qstats_output (size:128b/16B) */ 4018 struct hwrm_port_qstats_output { 4019 __le16 error_code; 4020 __le16 req_type; 4021 __le16 seq_id; 4022 __le16 resp_len; 4023 __le16 tx_stat_size; 4024 __le16 rx_stat_size; 4025 u8 unused_0[3]; 4026 u8 valid; 4027 }; 4028 4029 /* tx_port_stats_ext (size:2048b/256B) */ 4030 struct tx_port_stats_ext { 4031 __le64 tx_bytes_cos0; 4032 __le64 tx_bytes_cos1; 4033 __le64 tx_bytes_cos2; 4034 __le64 tx_bytes_cos3; 4035 __le64 tx_bytes_cos4; 4036 __le64 tx_bytes_cos5; 4037 __le64 tx_bytes_cos6; 4038 __le64 tx_bytes_cos7; 4039 __le64 tx_packets_cos0; 4040 __le64 tx_packets_cos1; 4041 __le64 tx_packets_cos2; 4042 __le64 tx_packets_cos3; 4043 __le64 tx_packets_cos4; 4044 __le64 tx_packets_cos5; 4045 __le64 tx_packets_cos6; 4046 __le64 tx_packets_cos7; 4047 __le64 pfc_pri0_tx_duration_us; 4048 __le64 pfc_pri0_tx_transitions; 4049 __le64 pfc_pri1_tx_duration_us; 4050 __le64 pfc_pri1_tx_transitions; 4051 __le64 pfc_pri2_tx_duration_us; 4052 __le64 pfc_pri2_tx_transitions; 4053 __le64 pfc_pri3_tx_duration_us; 4054 __le64 pfc_pri3_tx_transitions; 4055 __le64 pfc_pri4_tx_duration_us; 4056 __le64 pfc_pri4_tx_transitions; 4057 __le64 pfc_pri5_tx_duration_us; 4058 __le64 pfc_pri5_tx_transitions; 4059 __le64 pfc_pri6_tx_duration_us; 4060 __le64 pfc_pri6_tx_transitions; 4061 __le64 pfc_pri7_tx_duration_us; 4062 __le64 pfc_pri7_tx_transitions; 4063 }; 4064 4065 /* rx_port_stats_ext (size:3776b/472B) */ 4066 struct rx_port_stats_ext { 4067 __le64 link_down_events; 4068 __le64 continuous_pause_events; 4069 __le64 resume_pause_events; 4070 __le64 continuous_roce_pause_events; 4071 __le64 resume_roce_pause_events; 4072 __le64 rx_bytes_cos0; 4073 __le64 rx_bytes_cos1; 4074 __le64 rx_bytes_cos2; 4075 __le64 rx_bytes_cos3; 4076 __le64 rx_bytes_cos4; 4077 __le64 rx_bytes_cos5; 4078 __le64 rx_bytes_cos6; 4079 __le64 rx_bytes_cos7; 4080 __le64 rx_packets_cos0; 4081 __le64 rx_packets_cos1; 4082 __le64 rx_packets_cos2; 4083 __le64 rx_packets_cos3; 4084 __le64 rx_packets_cos4; 4085 __le64 rx_packets_cos5; 4086 __le64 rx_packets_cos6; 4087 __le64 rx_packets_cos7; 4088 __le64 pfc_pri0_rx_duration_us; 4089 __le64 pfc_pri0_rx_transitions; 4090 __le64 pfc_pri1_rx_duration_us; 4091 __le64 pfc_pri1_rx_transitions; 4092 __le64 pfc_pri2_rx_duration_us; 4093 __le64 pfc_pri2_rx_transitions; 4094 __le64 pfc_pri3_rx_duration_us; 4095 __le64 pfc_pri3_rx_transitions; 4096 __le64 pfc_pri4_rx_duration_us; 4097 __le64 pfc_pri4_rx_transitions; 4098 __le64 pfc_pri5_rx_duration_us; 4099 __le64 pfc_pri5_rx_transitions; 4100 __le64 pfc_pri6_rx_duration_us; 4101 __le64 pfc_pri6_rx_transitions; 4102 __le64 pfc_pri7_rx_duration_us; 4103 __le64 pfc_pri7_rx_transitions; 4104 __le64 rx_bits; 4105 __le64 rx_buffer_passed_threshold; 4106 __le64 rx_pcs_symbol_err; 4107 __le64 rx_corrected_bits; 4108 __le64 rx_discard_bytes_cos0; 4109 __le64 rx_discard_bytes_cos1; 4110 __le64 rx_discard_bytes_cos2; 4111 __le64 rx_discard_bytes_cos3; 4112 __le64 rx_discard_bytes_cos4; 4113 __le64 rx_discard_bytes_cos5; 4114 __le64 rx_discard_bytes_cos6; 4115 __le64 rx_discard_bytes_cos7; 4116 __le64 rx_discard_packets_cos0; 4117 __le64 rx_discard_packets_cos1; 4118 __le64 rx_discard_packets_cos2; 4119 __le64 rx_discard_packets_cos3; 4120 __le64 rx_discard_packets_cos4; 4121 __le64 rx_discard_packets_cos5; 4122 __le64 rx_discard_packets_cos6; 4123 __le64 rx_discard_packets_cos7; 4124 __le64 rx_fec_corrected_blocks; 4125 __le64 rx_fec_uncorrectable_blocks; 4126 }; 4127 4128 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4129 struct hwrm_port_qstats_ext_input { 4130 __le16 req_type; 4131 __le16 cmpl_ring; 4132 __le16 seq_id; 4133 __le16 target_id; 4134 __le64 resp_addr; 4135 __le16 port_id; 4136 __le16 tx_stat_size; 4137 __le16 rx_stat_size; 4138 u8 flags; 4139 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4140 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4141 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4142 u8 unused_0; 4143 __le64 tx_stat_host_addr; 4144 __le64 rx_stat_host_addr; 4145 }; 4146 4147 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4148 struct hwrm_port_qstats_ext_output { 4149 __le16 error_code; 4150 __le16 req_type; 4151 __le16 seq_id; 4152 __le16 resp_len; 4153 __le16 tx_stat_size; 4154 __le16 rx_stat_size; 4155 __le16 total_active_cos_queues; 4156 u8 flags; 4157 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4158 u8 valid; 4159 }; 4160 4161 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4162 struct hwrm_port_lpbk_qstats_input { 4163 __le16 req_type; 4164 __le16 cmpl_ring; 4165 __le16 seq_id; 4166 __le16 target_id; 4167 __le64 resp_addr; 4168 }; 4169 4170 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4171 struct hwrm_port_lpbk_qstats_output { 4172 __le16 error_code; 4173 __le16 req_type; 4174 __le16 seq_id; 4175 __le16 resp_len; 4176 __le64 lpbk_ucast_frames; 4177 __le64 lpbk_mcast_frames; 4178 __le64 lpbk_bcast_frames; 4179 __le64 lpbk_ucast_bytes; 4180 __le64 lpbk_mcast_bytes; 4181 __le64 lpbk_bcast_bytes; 4182 __le64 tx_stat_discard; 4183 __le64 tx_stat_error; 4184 __le64 rx_stat_discard; 4185 __le64 rx_stat_error; 4186 u8 unused_0[7]; 4187 u8 valid; 4188 }; 4189 4190 /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 4191 struct hwrm_port_ecn_qstats_input { 4192 __le16 req_type; 4193 __le16 cmpl_ring; 4194 __le16 seq_id; 4195 __le16 target_id; 4196 __le64 resp_addr; 4197 __le16 port_id; 4198 __le16 ecn_stat_buf_size; 4199 u8 flags; 4200 #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4201 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4202 #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 4203 u8 unused_0[3]; 4204 __le64 ecn_stat_host_addr; 4205 }; 4206 4207 /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 4208 struct hwrm_port_ecn_qstats_output { 4209 __le16 error_code; 4210 __le16 req_type; 4211 __le16 seq_id; 4212 __le16 resp_len; 4213 __le16 ecn_stat_buf_size; 4214 u8 mark_en; 4215 u8 unused_0[4]; 4216 u8 valid; 4217 }; 4218 4219 /* port_stats_ecn (size:512b/64B) */ 4220 struct port_stats_ecn { 4221 __le64 mark_cnt_cos0; 4222 __le64 mark_cnt_cos1; 4223 __le64 mark_cnt_cos2; 4224 __le64 mark_cnt_cos3; 4225 __le64 mark_cnt_cos4; 4226 __le64 mark_cnt_cos5; 4227 __le64 mark_cnt_cos6; 4228 __le64 mark_cnt_cos7; 4229 }; 4230 4231 /* hwrm_port_clr_stats_input (size:192b/24B) */ 4232 struct hwrm_port_clr_stats_input { 4233 __le16 req_type; 4234 __le16 cmpl_ring; 4235 __le16 seq_id; 4236 __le16 target_id; 4237 __le64 resp_addr; 4238 __le16 port_id; 4239 u8 flags; 4240 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 4241 u8 unused_0[5]; 4242 }; 4243 4244 /* hwrm_port_clr_stats_output (size:128b/16B) */ 4245 struct hwrm_port_clr_stats_output { 4246 __le16 error_code; 4247 __le16 req_type; 4248 __le16 seq_id; 4249 __le16 resp_len; 4250 u8 unused_0[7]; 4251 u8 valid; 4252 }; 4253 4254 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4255 struct hwrm_port_lpbk_clr_stats_input { 4256 __le16 req_type; 4257 __le16 cmpl_ring; 4258 __le16 seq_id; 4259 __le16 target_id; 4260 __le64 resp_addr; 4261 }; 4262 4263 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4264 struct hwrm_port_lpbk_clr_stats_output { 4265 __le16 error_code; 4266 __le16 req_type; 4267 __le16 seq_id; 4268 __le16 resp_len; 4269 u8 unused_0[7]; 4270 u8 valid; 4271 }; 4272 4273 /* hwrm_port_ts_query_input (size:320b/40B) */ 4274 struct hwrm_port_ts_query_input { 4275 __le16 req_type; 4276 __le16 cmpl_ring; 4277 __le16 seq_id; 4278 __le16 target_id; 4279 __le64 resp_addr; 4280 __le32 flags; 4281 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 4282 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 4283 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 4284 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 4285 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 4286 __le16 port_id; 4287 u8 unused_0[2]; 4288 __le16 enables; 4289 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 4290 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4291 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 4292 __le16 ts_req_timeout; 4293 __le32 ptp_seq_id; 4294 __le16 ptp_hdr_offset; 4295 u8 unused_1[6]; 4296 }; 4297 4298 /* hwrm_port_ts_query_output (size:192b/24B) */ 4299 struct hwrm_port_ts_query_output { 4300 __le16 error_code; 4301 __le16 req_type; 4302 __le16 seq_id; 4303 __le16 resp_len; 4304 __le64 ptp_msg_ts; 4305 __le16 ptp_msg_seqid; 4306 u8 unused_0[5]; 4307 u8 valid; 4308 }; 4309 4310 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 4311 struct hwrm_port_phy_qcaps_input { 4312 __le16 req_type; 4313 __le16 cmpl_ring; 4314 __le16 seq_id; 4315 __le16 target_id; 4316 __le64 resp_addr; 4317 __le16 port_id; 4318 u8 unused_0[6]; 4319 }; 4320 4321 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 4322 struct hwrm_port_phy_qcaps_output { 4323 __le16 error_code; 4324 __le16 req_type; 4325 __le16 seq_id; 4326 __le16 resp_len; 4327 u8 flags; 4328 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 4329 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 4330 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 4331 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4332 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 4333 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 4334 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 4335 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 4336 u8 port_cnt; 4337 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 4338 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 4339 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 4340 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 4341 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 4342 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 4343 __le16 supported_speeds_force_mode; 4344 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 4345 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 4346 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 4347 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 4348 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 4349 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 4350 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 4351 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 4352 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 4353 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 4354 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 4355 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 4356 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 4357 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 4358 __le16 supported_speeds_auto_mode; 4359 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 4360 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 4361 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 4362 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 4363 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 4364 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 4365 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 4366 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 4367 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 4368 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 4369 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 4370 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 4371 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 4372 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 4373 __le16 supported_speeds_eee_mode; 4374 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 4375 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 4376 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 4377 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 4378 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 4379 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 4380 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 4381 __le32 tx_lpi_timer_low; 4382 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 4383 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 4384 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 4385 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 4386 __le32 valid_tx_lpi_timer_high; 4387 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 4388 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4389 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4390 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4391 __le16 supported_pam4_speeds_auto_mode; 4392 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4393 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4394 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4395 __le16 supported_pam4_speeds_force_mode; 4396 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4397 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4398 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4399 __le16 flags2; 4400 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 4401 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 4402 u8 unused_0[1]; 4403 u8 valid; 4404 }; 4405 4406 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 4407 struct hwrm_port_phy_i2c_read_input { 4408 __le16 req_type; 4409 __le16 cmpl_ring; 4410 __le16 seq_id; 4411 __le16 target_id; 4412 __le64 resp_addr; 4413 __le32 flags; 4414 __le32 enables; 4415 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 4416 __le16 port_id; 4417 u8 i2c_slave_addr; 4418 u8 unused_0; 4419 __le16 page_number; 4420 __le16 page_offset; 4421 u8 data_length; 4422 u8 unused_1[7]; 4423 }; 4424 4425 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 4426 struct hwrm_port_phy_i2c_read_output { 4427 __le16 error_code; 4428 __le16 req_type; 4429 __le16 seq_id; 4430 __le16 resp_len; 4431 __le32 data[16]; 4432 u8 unused_0[7]; 4433 u8 valid; 4434 }; 4435 4436 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 4437 struct hwrm_port_phy_mdio_write_input { 4438 __le16 req_type; 4439 __le16 cmpl_ring; 4440 __le16 seq_id; 4441 __le16 target_id; 4442 __le64 resp_addr; 4443 __le32 unused_0[2]; 4444 __le16 port_id; 4445 u8 phy_addr; 4446 u8 dev_addr; 4447 __le16 reg_addr; 4448 __le16 reg_data; 4449 u8 cl45_mdio; 4450 u8 unused_1[7]; 4451 }; 4452 4453 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 4454 struct hwrm_port_phy_mdio_write_output { 4455 __le16 error_code; 4456 __le16 req_type; 4457 __le16 seq_id; 4458 __le16 resp_len; 4459 u8 unused_0[7]; 4460 u8 valid; 4461 }; 4462 4463 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 4464 struct hwrm_port_phy_mdio_read_input { 4465 __le16 req_type; 4466 __le16 cmpl_ring; 4467 __le16 seq_id; 4468 __le16 target_id; 4469 __le64 resp_addr; 4470 __le32 unused_0[2]; 4471 __le16 port_id; 4472 u8 phy_addr; 4473 u8 dev_addr; 4474 __le16 reg_addr; 4475 u8 cl45_mdio; 4476 u8 unused_1; 4477 }; 4478 4479 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 4480 struct hwrm_port_phy_mdio_read_output { 4481 __le16 error_code; 4482 __le16 req_type; 4483 __le16 seq_id; 4484 __le16 resp_len; 4485 __le16 reg_data; 4486 u8 unused_0[5]; 4487 u8 valid; 4488 }; 4489 4490 /* hwrm_port_led_cfg_input (size:512b/64B) */ 4491 struct hwrm_port_led_cfg_input { 4492 __le16 req_type; 4493 __le16 cmpl_ring; 4494 __le16 seq_id; 4495 __le16 target_id; 4496 __le64 resp_addr; 4497 __le32 enables; 4498 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4499 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4500 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4501 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4502 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4503 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4504 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4505 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4506 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4507 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4508 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4509 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4510 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4511 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4512 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4513 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4514 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4515 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4516 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4517 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 4518 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 4519 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 4520 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 4521 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 4522 __le16 port_id; 4523 u8 num_leds; 4524 u8 rsvd; 4525 u8 led0_id; 4526 u8 led0_state; 4527 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 4528 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 4529 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 4530 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 4531 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 4532 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 4533 u8 led0_color; 4534 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 4535 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 4536 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 4537 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 4538 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 4539 u8 unused_0; 4540 __le16 led0_blink_on; 4541 __le16 led0_blink_off; 4542 u8 led0_group_id; 4543 u8 rsvd0; 4544 u8 led1_id; 4545 u8 led1_state; 4546 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 4547 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 4548 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 4549 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 4550 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 4551 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 4552 u8 led1_color; 4553 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 4554 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 4555 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 4556 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 4557 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 4558 u8 unused_1; 4559 __le16 led1_blink_on; 4560 __le16 led1_blink_off; 4561 u8 led1_group_id; 4562 u8 rsvd1; 4563 u8 led2_id; 4564 u8 led2_state; 4565 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 4566 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 4567 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 4568 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 4569 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 4570 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 4571 u8 led2_color; 4572 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 4573 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 4574 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 4575 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 4576 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 4577 u8 unused_2; 4578 __le16 led2_blink_on; 4579 __le16 led2_blink_off; 4580 u8 led2_group_id; 4581 u8 rsvd2; 4582 u8 led3_id; 4583 u8 led3_state; 4584 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 4585 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 4586 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 4587 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 4588 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 4589 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 4590 u8 led3_color; 4591 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 4592 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 4593 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 4594 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 4595 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 4596 u8 unused_3; 4597 __le16 led3_blink_on; 4598 __le16 led3_blink_off; 4599 u8 led3_group_id; 4600 u8 rsvd3; 4601 }; 4602 4603 /* hwrm_port_led_cfg_output (size:128b/16B) */ 4604 struct hwrm_port_led_cfg_output { 4605 __le16 error_code; 4606 __le16 req_type; 4607 __le16 seq_id; 4608 __le16 resp_len; 4609 u8 unused_0[7]; 4610 u8 valid; 4611 }; 4612 4613 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 4614 struct hwrm_port_led_qcfg_input { 4615 __le16 req_type; 4616 __le16 cmpl_ring; 4617 __le16 seq_id; 4618 __le16 target_id; 4619 __le64 resp_addr; 4620 __le16 port_id; 4621 u8 unused_0[6]; 4622 }; 4623 4624 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 4625 struct hwrm_port_led_qcfg_output { 4626 __le16 error_code; 4627 __le16 req_type; 4628 __le16 seq_id; 4629 __le16 resp_len; 4630 u8 num_leds; 4631 u8 led0_id; 4632 u8 led0_type; 4633 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 4634 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 4635 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 4636 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 4637 u8 led0_state; 4638 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 4639 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 4640 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 4641 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 4642 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 4643 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 4644 u8 led0_color; 4645 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 4646 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 4647 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 4648 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 4649 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 4650 u8 unused_0; 4651 __le16 led0_blink_on; 4652 __le16 led0_blink_off; 4653 u8 led0_group_id; 4654 u8 led1_id; 4655 u8 led1_type; 4656 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 4657 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 4658 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 4659 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 4660 u8 led1_state; 4661 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 4662 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 4663 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 4664 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 4665 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 4666 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 4667 u8 led1_color; 4668 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 4669 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 4670 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 4671 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 4672 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 4673 u8 unused_1; 4674 __le16 led1_blink_on; 4675 __le16 led1_blink_off; 4676 u8 led1_group_id; 4677 u8 led2_id; 4678 u8 led2_type; 4679 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 4680 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 4681 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 4682 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 4683 u8 led2_state; 4684 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 4685 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 4686 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 4687 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 4688 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 4689 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 4690 u8 led2_color; 4691 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 4692 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 4693 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 4694 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 4695 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 4696 u8 unused_2; 4697 __le16 led2_blink_on; 4698 __le16 led2_blink_off; 4699 u8 led2_group_id; 4700 u8 led3_id; 4701 u8 led3_type; 4702 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 4703 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 4704 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 4705 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 4706 u8 led3_state; 4707 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4708 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4709 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4710 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4711 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4712 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4713 u8 led3_color; 4714 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4715 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4716 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4717 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4718 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4719 u8 unused_3; 4720 __le16 led3_blink_on; 4721 __le16 led3_blink_off; 4722 u8 led3_group_id; 4723 u8 unused_4[6]; 4724 u8 valid; 4725 }; 4726 4727 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4728 struct hwrm_port_led_qcaps_input { 4729 __le16 req_type; 4730 __le16 cmpl_ring; 4731 __le16 seq_id; 4732 __le16 target_id; 4733 __le64 resp_addr; 4734 __le16 port_id; 4735 u8 unused_0[6]; 4736 }; 4737 4738 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4739 struct hwrm_port_led_qcaps_output { 4740 __le16 error_code; 4741 __le16 req_type; 4742 __le16 seq_id; 4743 __le16 resp_len; 4744 u8 num_leds; 4745 u8 unused[3]; 4746 u8 led0_id; 4747 u8 led0_type; 4748 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4749 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4750 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4751 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4752 u8 led0_group_id; 4753 u8 unused_0; 4754 __le16 led0_state_caps; 4755 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4756 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4757 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4758 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4759 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4760 __le16 led0_color_caps; 4761 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4762 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4763 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4764 u8 led1_id; 4765 u8 led1_type; 4766 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4767 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4768 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4769 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4770 u8 led1_group_id; 4771 u8 unused_1; 4772 __le16 led1_state_caps; 4773 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4774 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4775 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4776 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4777 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4778 __le16 led1_color_caps; 4779 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4780 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4781 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4782 u8 led2_id; 4783 u8 led2_type; 4784 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4785 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4786 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4787 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4788 u8 led2_group_id; 4789 u8 unused_2; 4790 __le16 led2_state_caps; 4791 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4792 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4793 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4794 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4795 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4796 __le16 led2_color_caps; 4797 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4798 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4799 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4800 u8 led3_id; 4801 u8 led3_type; 4802 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4803 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4804 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4805 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4806 u8 led3_group_id; 4807 u8 unused_3; 4808 __le16 led3_state_caps; 4809 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4810 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4811 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4812 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4813 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4814 __le16 led3_color_caps; 4815 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4816 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4817 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4818 u8 unused_4[3]; 4819 u8 valid; 4820 }; 4821 4822 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4823 struct hwrm_queue_qportcfg_input { 4824 __le16 req_type; 4825 __le16 cmpl_ring; 4826 __le16 seq_id; 4827 __le16 target_id; 4828 __le64 resp_addr; 4829 __le32 flags; 4830 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4831 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4832 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 4833 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4834 __le16 port_id; 4835 u8 drv_qmap_cap; 4836 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4837 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4838 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4839 u8 unused_0; 4840 }; 4841 4842 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4843 struct hwrm_queue_qportcfg_output { 4844 __le16 error_code; 4845 __le16 req_type; 4846 __le16 seq_id; 4847 __le16 resp_len; 4848 u8 max_configurable_queues; 4849 u8 max_configurable_lossless_queues; 4850 u8 queue_cfg_allowed; 4851 u8 queue_cfg_info; 4852 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4853 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 4854 u8 queue_pfcenable_cfg_allowed; 4855 u8 queue_pri2cos_cfg_allowed; 4856 u8 queue_cos2bw_cfg_allowed; 4857 u8 queue_id0; 4858 u8 queue_id0_service_profile; 4859 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 4860 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4861 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4862 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4863 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4864 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4865 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4866 u8 queue_id1; 4867 u8 queue_id1_service_profile; 4868 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 4869 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4870 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4871 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4872 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4873 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4874 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4875 u8 queue_id2; 4876 u8 queue_id2_service_profile; 4877 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 4878 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4879 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4880 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4881 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4882 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4883 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4884 u8 queue_id3; 4885 u8 queue_id3_service_profile; 4886 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 4887 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4888 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4889 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4890 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4891 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4892 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4893 u8 queue_id4; 4894 u8 queue_id4_service_profile; 4895 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 4896 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4897 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4898 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4899 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4900 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4901 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4902 u8 queue_id5; 4903 u8 queue_id5_service_profile; 4904 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 4905 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4906 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4907 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4908 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4909 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4910 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4911 u8 queue_id6; 4912 u8 queue_id6_service_profile; 4913 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 4914 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4915 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4916 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4917 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4918 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4919 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4920 u8 queue_id7; 4921 u8 queue_id7_service_profile; 4922 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 4923 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4924 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4925 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4926 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4927 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4928 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4929 u8 queue_id0_service_profile_type; 4930 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4931 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4932 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4933 char qid0_name[16]; 4934 char qid1_name[16]; 4935 char qid2_name[16]; 4936 char qid3_name[16]; 4937 char qid4_name[16]; 4938 char qid5_name[16]; 4939 char qid6_name[16]; 4940 char qid7_name[16]; 4941 u8 queue_id1_service_profile_type; 4942 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4943 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4944 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4945 u8 queue_id2_service_profile_type; 4946 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4947 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4948 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4949 u8 queue_id3_service_profile_type; 4950 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4951 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4952 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4953 u8 queue_id4_service_profile_type; 4954 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4955 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4956 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4957 u8 queue_id5_service_profile_type; 4958 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4959 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4960 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4961 u8 queue_id6_service_profile_type; 4962 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4963 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4964 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4965 u8 queue_id7_service_profile_type; 4966 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4967 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4968 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4969 u8 valid; 4970 }; 4971 4972 /* hwrm_queue_qcfg_input (size:192b/24B) */ 4973 struct hwrm_queue_qcfg_input { 4974 __le16 req_type; 4975 __le16 cmpl_ring; 4976 __le16 seq_id; 4977 __le16 target_id; 4978 __le64 resp_addr; 4979 __le32 flags; 4980 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4981 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4982 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4983 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4984 __le32 queue_id; 4985 }; 4986 4987 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4988 struct hwrm_queue_qcfg_output { 4989 __le16 error_code; 4990 __le16 req_type; 4991 __le16 seq_id; 4992 __le16 resp_len; 4993 __le32 queue_len; 4994 u8 service_profile; 4995 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4996 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4997 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4998 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4999 u8 queue_cfg_info; 5000 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5001 u8 unused_0; 5002 u8 valid; 5003 }; 5004 5005 /* hwrm_queue_cfg_input (size:320b/40B) */ 5006 struct hwrm_queue_cfg_input { 5007 __le16 req_type; 5008 __le16 cmpl_ring; 5009 __le16 seq_id; 5010 __le16 target_id; 5011 __le64 resp_addr; 5012 __le32 flags; 5013 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5014 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5015 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5016 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5017 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5018 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5019 __le32 enables; 5020 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5021 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5022 __le32 queue_id; 5023 __le32 dflt_len; 5024 u8 service_profile; 5025 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5026 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5027 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5028 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5029 u8 unused_0[7]; 5030 }; 5031 5032 /* hwrm_queue_cfg_output (size:128b/16B) */ 5033 struct hwrm_queue_cfg_output { 5034 __le16 error_code; 5035 __le16 req_type; 5036 __le16 seq_id; 5037 __le16 resp_len; 5038 u8 unused_0[7]; 5039 u8 valid; 5040 }; 5041 5042 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 5043 struct hwrm_queue_pfcenable_qcfg_input { 5044 __le16 req_type; 5045 __le16 cmpl_ring; 5046 __le16 seq_id; 5047 __le16 target_id; 5048 __le64 resp_addr; 5049 __le16 port_id; 5050 u8 unused_0[6]; 5051 }; 5052 5053 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 5054 struct hwrm_queue_pfcenable_qcfg_output { 5055 __le16 error_code; 5056 __le16 req_type; 5057 __le16 seq_id; 5058 __le16 resp_len; 5059 __le32 flags; 5060 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 5061 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 5062 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 5063 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 5064 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 5065 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 5066 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 5067 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5068 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5069 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5070 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5071 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5072 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5073 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5074 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5075 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5076 u8 unused_0[3]; 5077 u8 valid; 5078 }; 5079 5080 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5081 struct hwrm_queue_pfcenable_cfg_input { 5082 __le16 req_type; 5083 __le16 cmpl_ring; 5084 __le16 seq_id; 5085 __le16 target_id; 5086 __le64 resp_addr; 5087 __le32 flags; 5088 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5089 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5090 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5091 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5092 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5093 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5094 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5095 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5096 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5097 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5098 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5099 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5100 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5101 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5102 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5103 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5104 __le16 port_id; 5105 u8 unused_0[2]; 5106 }; 5107 5108 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5109 struct hwrm_queue_pfcenable_cfg_output { 5110 __le16 error_code; 5111 __le16 req_type; 5112 __le16 seq_id; 5113 __le16 resp_len; 5114 u8 unused_0[7]; 5115 u8 valid; 5116 }; 5117 5118 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 5119 struct hwrm_queue_pri2cos_qcfg_input { 5120 __le16 req_type; 5121 __le16 cmpl_ring; 5122 __le16 seq_id; 5123 __le16 target_id; 5124 __le64 resp_addr; 5125 __le32 flags; 5126 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5127 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5128 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5129 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 5130 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 5131 u8 port_id; 5132 u8 unused_0[3]; 5133 }; 5134 5135 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 5136 struct hwrm_queue_pri2cos_qcfg_output { 5137 __le16 error_code; 5138 __le16 req_type; 5139 __le16 seq_id; 5140 __le16 resp_len; 5141 u8 pri0_cos_queue_id; 5142 u8 pri1_cos_queue_id; 5143 u8 pri2_cos_queue_id; 5144 u8 pri3_cos_queue_id; 5145 u8 pri4_cos_queue_id; 5146 u8 pri5_cos_queue_id; 5147 u8 pri6_cos_queue_id; 5148 u8 pri7_cos_queue_id; 5149 u8 queue_cfg_info; 5150 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5151 u8 unused_0[6]; 5152 u8 valid; 5153 }; 5154 5155 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5156 struct hwrm_queue_pri2cos_cfg_input { 5157 __le16 req_type; 5158 __le16 cmpl_ring; 5159 __le16 seq_id; 5160 __le16 target_id; 5161 __le64 resp_addr; 5162 __le32 flags; 5163 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5164 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5165 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5166 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5167 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5168 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5169 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5170 __le32 enables; 5171 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5172 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5173 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5174 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5175 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5176 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5177 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5178 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5179 u8 port_id; 5180 u8 pri0_cos_queue_id; 5181 u8 pri1_cos_queue_id; 5182 u8 pri2_cos_queue_id; 5183 u8 pri3_cos_queue_id; 5184 u8 pri4_cos_queue_id; 5185 u8 pri5_cos_queue_id; 5186 u8 pri6_cos_queue_id; 5187 u8 pri7_cos_queue_id; 5188 u8 unused_0[7]; 5189 }; 5190 5191 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5192 struct hwrm_queue_pri2cos_cfg_output { 5193 __le16 error_code; 5194 __le16 req_type; 5195 __le16 seq_id; 5196 __le16 resp_len; 5197 u8 unused_0[7]; 5198 u8 valid; 5199 }; 5200 5201 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 5202 struct hwrm_queue_cos2bw_qcfg_input { 5203 __le16 req_type; 5204 __le16 cmpl_ring; 5205 __le16 seq_id; 5206 __le16 target_id; 5207 __le64 resp_addr; 5208 __le16 port_id; 5209 u8 unused_0[6]; 5210 }; 5211 5212 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 5213 struct hwrm_queue_cos2bw_qcfg_output { 5214 __le16 error_code; 5215 __le16 req_type; 5216 __le16 seq_id; 5217 __le16 resp_len; 5218 u8 queue_id0; 5219 u8 unused_0; 5220 __le16 unused_1; 5221 __le32 queue_id0_min_bw; 5222 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5223 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5224 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5225 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5226 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5227 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 5228 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5229 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5230 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5231 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5232 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5233 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5234 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5235 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5236 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5237 __le32 queue_id0_max_bw; 5238 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5239 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5240 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5241 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5242 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5243 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 5244 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5250 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5253 u8 queue_id0_tsa_assign; 5254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5258 u8 queue_id0_pri_lvl; 5259 u8 queue_id0_bw_weight; 5260 u8 queue_id1; 5261 __le32 queue_id1_min_bw; 5262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5266 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 5268 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5271 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5272 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5275 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5277 __le32 queue_id1_max_bw; 5278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5280 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5281 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5282 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5283 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 5284 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5290 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5292 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5293 u8 queue_id1_tsa_assign; 5294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5296 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5297 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5298 u8 queue_id1_pri_lvl; 5299 u8 queue_id1_bw_weight; 5300 u8 queue_id2; 5301 __le32 queue_id2_min_bw; 5302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5305 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5306 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5307 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 5308 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5309 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5310 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5311 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5312 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5313 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5314 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5315 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5316 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5317 __le32 queue_id2_max_bw; 5318 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5319 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5320 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5321 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5322 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5323 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 5324 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5325 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5326 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5327 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5328 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5330 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5333 u8 queue_id2_tsa_assign; 5334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5336 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5338 u8 queue_id2_pri_lvl; 5339 u8 queue_id2_bw_weight; 5340 u8 queue_id3; 5341 __le32 queue_id3_min_bw; 5342 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5346 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 5348 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5351 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5352 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5353 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5354 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5355 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5356 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5357 __le32 queue_id3_max_bw; 5358 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5359 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5360 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5361 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5362 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5363 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 5364 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5365 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5366 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5367 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5370 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5373 u8 queue_id3_tsa_assign; 5374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5376 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5378 u8 queue_id3_pri_lvl; 5379 u8 queue_id3_bw_weight; 5380 u8 queue_id4; 5381 __le32 queue_id4_min_bw; 5382 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5383 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 5388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5395 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5397 __le32 queue_id4_max_bw; 5398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5399 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5400 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5401 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5402 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5403 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 5404 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5410 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5413 u8 queue_id4_tsa_assign; 5414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5416 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5418 u8 queue_id4_pri_lvl; 5419 u8 queue_id4_bw_weight; 5420 u8 queue_id5; 5421 __le32 queue_id5_min_bw; 5422 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5423 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 5428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5432 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5435 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5437 __le32 queue_id5_max_bw; 5438 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5439 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5440 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5441 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5442 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5443 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 5444 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5445 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5446 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5447 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5448 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5449 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5450 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5451 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5452 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5453 u8 queue_id5_tsa_assign; 5454 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5455 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5456 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5457 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5458 u8 queue_id5_pri_lvl; 5459 u8 queue_id5_bw_weight; 5460 u8 queue_id6; 5461 __le32 queue_id6_min_bw; 5462 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5463 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5464 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5465 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5466 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5467 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 5468 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5469 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5477 __le32 queue_id6_max_bw; 5478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 5484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5493 u8 queue_id6_tsa_assign; 5494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5498 u8 queue_id6_pri_lvl; 5499 u8 queue_id6_bw_weight; 5500 u8 queue_id7; 5501 __le32 queue_id7_min_bw; 5502 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 5508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5517 __le32 queue_id7_max_bw; 5518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 5524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5533 u8 queue_id7_tsa_assign; 5534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5538 u8 queue_id7_pri_lvl; 5539 u8 queue_id7_bw_weight; 5540 u8 unused_2[4]; 5541 u8 valid; 5542 }; 5543 5544 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 5545 struct hwrm_queue_cos2bw_cfg_input { 5546 __le16 req_type; 5547 __le16 cmpl_ring; 5548 __le16 seq_id; 5549 __le16 target_id; 5550 __le64 resp_addr; 5551 __le32 flags; 5552 __le32 enables; 5553 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 5554 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 5555 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 5556 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 5557 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 5558 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 5559 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 5560 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 5561 __le16 port_id; 5562 u8 queue_id0; 5563 u8 unused_0; 5564 __le32 queue_id0_min_bw; 5565 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5566 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5567 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5568 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5569 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5570 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 5571 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5572 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5573 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5574 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5575 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5576 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5577 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5578 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5579 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5580 __le32 queue_id0_max_bw; 5581 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5582 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5585 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 5587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5596 u8 queue_id0_tsa_assign; 5597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5601 u8 queue_id0_pri_lvl; 5602 u8 queue_id0_bw_weight; 5603 u8 queue_id1; 5604 __le32 queue_id1_min_bw; 5605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 5611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5620 __le32 queue_id1_max_bw; 5621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5623 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 5627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5636 u8 queue_id1_tsa_assign; 5637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5641 u8 queue_id1_pri_lvl; 5642 u8 queue_id1_bw_weight; 5643 u8 queue_id2; 5644 __le32 queue_id2_min_bw; 5645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 5651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5655 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5660 __le32 queue_id2_max_bw; 5661 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5662 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5663 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5664 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5665 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5666 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 5667 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5668 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5669 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5673 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5676 u8 queue_id2_tsa_assign; 5677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5679 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5681 u8 queue_id2_pri_lvl; 5682 u8 queue_id2_bw_weight; 5683 u8 queue_id3; 5684 __le32 queue_id3_min_bw; 5685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5688 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5689 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5690 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 5691 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5692 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5693 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5694 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5695 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5696 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5697 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5698 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5699 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5700 __le32 queue_id3_max_bw; 5701 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5702 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5703 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5704 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5705 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5706 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 5707 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5708 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5709 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5710 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5711 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5712 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5713 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5714 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5715 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5716 u8 queue_id3_tsa_assign; 5717 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5718 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5719 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5720 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5721 u8 queue_id3_pri_lvl; 5722 u8 queue_id3_bw_weight; 5723 u8 queue_id4; 5724 __le32 queue_id4_min_bw; 5725 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5726 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5735 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5738 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5740 __le32 queue_id4_max_bw; 5741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5742 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5743 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5744 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5745 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5746 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5756 u8 queue_id4_tsa_assign; 5757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5758 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5759 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5761 u8 queue_id4_pri_lvl; 5762 u8 queue_id4_bw_weight; 5763 u8 queue_id5; 5764 __le32 queue_id5_min_bw; 5765 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5766 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5767 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5769 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5774 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5775 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5776 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5777 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5778 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5780 __le32 queue_id5_max_bw; 5781 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5782 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5783 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5784 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5785 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5786 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5787 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5788 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5789 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5790 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5791 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5792 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5793 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5794 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5795 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5796 u8 queue_id5_tsa_assign; 5797 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5798 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5799 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5800 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5801 u8 queue_id5_pri_lvl; 5802 u8 queue_id5_bw_weight; 5803 u8 queue_id6; 5804 __le32 queue_id6_min_bw; 5805 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5806 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5807 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5808 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5809 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5810 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5811 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5812 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5813 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5814 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5815 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5816 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5820 __le32 queue_id6_max_bw; 5821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5836 u8 queue_id6_tsa_assign; 5837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5841 u8 queue_id6_pri_lvl; 5842 u8 queue_id6_bw_weight; 5843 u8 queue_id7; 5844 __le32 queue_id7_min_bw; 5845 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5846 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5860 __le32 queue_id7_max_bw; 5861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5876 u8 queue_id7_tsa_assign; 5877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5881 u8 queue_id7_pri_lvl; 5882 u8 queue_id7_bw_weight; 5883 u8 unused_1[5]; 5884 }; 5885 5886 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5887 struct hwrm_queue_cos2bw_cfg_output { 5888 __le16 error_code; 5889 __le16 req_type; 5890 __le16 seq_id; 5891 __le16 resp_len; 5892 u8 unused_0[7]; 5893 u8 valid; 5894 }; 5895 5896 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5897 struct hwrm_queue_dscp_qcaps_input { 5898 __le16 req_type; 5899 __le16 cmpl_ring; 5900 __le16 seq_id; 5901 __le16 target_id; 5902 __le64 resp_addr; 5903 u8 port_id; 5904 u8 unused_0[7]; 5905 }; 5906 5907 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5908 struct hwrm_queue_dscp_qcaps_output { 5909 __le16 error_code; 5910 __le16 req_type; 5911 __le16 seq_id; 5912 __le16 resp_len; 5913 u8 num_dscp_bits; 5914 u8 unused_0; 5915 __le16 max_entries; 5916 u8 unused_1[3]; 5917 u8 valid; 5918 }; 5919 5920 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5921 struct hwrm_queue_dscp2pri_qcfg_input { 5922 __le16 req_type; 5923 __le16 cmpl_ring; 5924 __le16 seq_id; 5925 __le16 target_id; 5926 __le64 resp_addr; 5927 __le64 dest_data_addr; 5928 u8 port_id; 5929 u8 unused_0; 5930 __le16 dest_data_buffer_size; 5931 u8 unused_1[4]; 5932 }; 5933 5934 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5935 struct hwrm_queue_dscp2pri_qcfg_output { 5936 __le16 error_code; 5937 __le16 req_type; 5938 __le16 seq_id; 5939 __le16 resp_len; 5940 __le16 entry_cnt; 5941 u8 default_pri; 5942 u8 unused_0[4]; 5943 u8 valid; 5944 }; 5945 5946 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5947 struct hwrm_queue_dscp2pri_cfg_input { 5948 __le16 req_type; 5949 __le16 cmpl_ring; 5950 __le16 seq_id; 5951 __le16 target_id; 5952 __le64 resp_addr; 5953 __le64 src_data_addr; 5954 __le32 flags; 5955 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5956 __le32 enables; 5957 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5958 u8 port_id; 5959 u8 default_pri; 5960 __le16 entry_cnt; 5961 u8 unused_0[4]; 5962 }; 5963 5964 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5965 struct hwrm_queue_dscp2pri_cfg_output { 5966 __le16 error_code; 5967 __le16 req_type; 5968 __le16 seq_id; 5969 __le16 resp_len; 5970 u8 unused_0[7]; 5971 u8 valid; 5972 }; 5973 5974 /* hwrm_vnic_alloc_input (size:192b/24B) */ 5975 struct hwrm_vnic_alloc_input { 5976 __le16 req_type; 5977 __le16 cmpl_ring; 5978 __le16 seq_id; 5979 __le16 target_id; 5980 __le64 resp_addr; 5981 __le32 flags; 5982 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5983 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5984 __le16 virtio_net_fid; 5985 u8 unused_0[2]; 5986 }; 5987 5988 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5989 struct hwrm_vnic_alloc_output { 5990 __le16 error_code; 5991 __le16 req_type; 5992 __le16 seq_id; 5993 __le16 resp_len; 5994 __le32 vnic_id; 5995 u8 unused_0[3]; 5996 u8 valid; 5997 }; 5998 5999 /* hwrm_vnic_free_input (size:192b/24B) */ 6000 struct hwrm_vnic_free_input { 6001 __le16 req_type; 6002 __le16 cmpl_ring; 6003 __le16 seq_id; 6004 __le16 target_id; 6005 __le64 resp_addr; 6006 __le32 vnic_id; 6007 u8 unused_0[4]; 6008 }; 6009 6010 /* hwrm_vnic_free_output (size:128b/16B) */ 6011 struct hwrm_vnic_free_output { 6012 __le16 error_code; 6013 __le16 req_type; 6014 __le16 seq_id; 6015 __le16 resp_len; 6016 u8 unused_0[7]; 6017 u8 valid; 6018 }; 6019 6020 /* hwrm_vnic_cfg_input (size:384b/48B) */ 6021 struct hwrm_vnic_cfg_input { 6022 __le16 req_type; 6023 __le16 cmpl_ring; 6024 __le16 seq_id; 6025 __le16 target_id; 6026 __le64 resp_addr; 6027 __le32 flags; 6028 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6029 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6030 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6031 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6032 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6033 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6034 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6035 __le32 enables; 6036 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6037 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6038 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6039 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6040 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6041 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6042 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6043 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6044 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6045 __le16 vnic_id; 6046 __le16 dflt_ring_grp; 6047 __le16 rss_rule; 6048 __le16 cos_rule; 6049 __le16 lb_rule; 6050 __le16 mru; 6051 __le16 default_rx_ring_id; 6052 __le16 default_cmpl_ring_id; 6053 __le16 queue_id; 6054 u8 rx_csum_v2_mode; 6055 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6056 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6057 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6058 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6059 u8 unused0[5]; 6060 }; 6061 6062 /* hwrm_vnic_cfg_output (size:128b/16B) */ 6063 struct hwrm_vnic_cfg_output { 6064 __le16 error_code; 6065 __le16 req_type; 6066 __le16 seq_id; 6067 __le16 resp_len; 6068 u8 unused_0[7]; 6069 u8 valid; 6070 }; 6071 6072 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 6073 struct hwrm_vnic_qcaps_input { 6074 __le16 req_type; 6075 __le16 cmpl_ring; 6076 __le16 seq_id; 6077 __le16 target_id; 6078 __le64 resp_addr; 6079 __le32 enables; 6080 u8 unused_0[4]; 6081 }; 6082 6083 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 6084 struct hwrm_vnic_qcaps_output { 6085 __le16 error_code; 6086 __le16 req_type; 6087 __le16 seq_id; 6088 __le16 resp_len; 6089 __le16 mru; 6090 u8 unused_0[2]; 6091 __le32 flags; 6092 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6093 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6094 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6095 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6096 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6097 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6098 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6099 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6100 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6101 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6102 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6103 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6104 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6105 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6106 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6107 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP 0x8000UL 6108 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_XOR_CAP 0x10000UL 6109 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP 0x20000UL 6110 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6111 __le16 max_aggs_supported; 6112 u8 unused_1[5]; 6113 u8 valid; 6114 }; 6115 6116 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6117 struct hwrm_vnic_tpa_cfg_input { 6118 __le16 req_type; 6119 __le16 cmpl_ring; 6120 __le16 seq_id; 6121 __le16 target_id; 6122 __le64 resp_addr; 6123 __le32 flags; 6124 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6125 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6126 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6127 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6128 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6129 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6130 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6131 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 6132 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6133 __le32 enables; 6134 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6135 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6136 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6137 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6138 __le16 vnic_id; 6139 __le16 max_agg_segs; 6140 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6141 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6142 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6143 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6144 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6145 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6146 __le16 max_aggs; 6147 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6148 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6149 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6150 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6151 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6152 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6153 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6154 u8 unused_0[2]; 6155 __le32 max_agg_timer; 6156 __le32 min_agg_len; 6157 }; 6158 6159 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6160 struct hwrm_vnic_tpa_cfg_output { 6161 __le16 error_code; 6162 __le16 req_type; 6163 __le16 seq_id; 6164 __le16 resp_len; 6165 u8 unused_0[7]; 6166 u8 valid; 6167 }; 6168 6169 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6170 struct hwrm_vnic_tpa_qcfg_input { 6171 __le16 req_type; 6172 __le16 cmpl_ring; 6173 __le16 seq_id; 6174 __le16 target_id; 6175 __le64 resp_addr; 6176 __le16 vnic_id; 6177 u8 unused_0[6]; 6178 }; 6179 6180 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6181 struct hwrm_vnic_tpa_qcfg_output { 6182 __le16 error_code; 6183 __le16 req_type; 6184 __le16 seq_id; 6185 __le16 resp_len; 6186 __le32 flags; 6187 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6188 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6189 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6190 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6191 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6192 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6193 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6194 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6195 __le16 max_agg_segs; 6196 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6197 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6198 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6199 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6200 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6201 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6202 __le16 max_aggs; 6203 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6204 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6205 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6206 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6207 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6208 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6209 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6210 __le32 max_agg_timer; 6211 __le32 min_agg_len; 6212 u8 unused_0[7]; 6213 u8 valid; 6214 }; 6215 6216 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6217 struct hwrm_vnic_rss_cfg_input { 6218 __le16 req_type; 6219 __le16 cmpl_ring; 6220 __le16 seq_id; 6221 __le16 target_id; 6222 __le64 resp_addr; 6223 __le32 hash_type; 6224 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6225 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6226 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6227 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6228 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6229 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 6230 __le16 vnic_id; 6231 u8 ring_table_pair_index; 6232 u8 hash_mode_flags; 6233 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 6234 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 6235 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 6236 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 6237 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6238 __le64 ring_grp_tbl_addr; 6239 __le64 hash_key_tbl_addr; 6240 __le16 rss_ctx_idx; 6241 u8 flags; 6242 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6243 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6244 u8 rss_hash_function; 6245 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_TOEPLITZ 0x0UL 6246 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_XOR 0x1UL 6247 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 0x2UL 6248 #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_LAST VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 6249 u8 unused_1[4]; 6250 }; 6251 6252 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6253 struct hwrm_vnic_rss_cfg_output { 6254 __le16 error_code; 6255 __le16 req_type; 6256 __le16 seq_id; 6257 __le16 resp_len; 6258 u8 unused_0[7]; 6259 u8 valid; 6260 }; 6261 6262 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 6263 struct hwrm_vnic_rss_cfg_cmd_err { 6264 u8 code; 6265 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 6266 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 6267 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 6268 u8 unused_0[7]; 6269 }; 6270 6271 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6272 struct hwrm_vnic_plcmodes_cfg_input { 6273 __le16 req_type; 6274 __le16 cmpl_ring; 6275 __le16 seq_id; 6276 __le16 target_id; 6277 __le64 resp_addr; 6278 __le32 flags; 6279 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6280 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6281 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6282 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6283 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6284 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6285 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6286 __le32 enables; 6287 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6288 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6289 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6290 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6291 __le32 vnic_id; 6292 __le16 jumbo_thresh; 6293 __le16 hds_offset; 6294 __le16 hds_threshold; 6295 __le16 max_bds; 6296 u8 unused_0[4]; 6297 }; 6298 6299 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6300 struct hwrm_vnic_plcmodes_cfg_output { 6301 __le16 error_code; 6302 __le16 req_type; 6303 __le16 seq_id; 6304 __le16 resp_len; 6305 u8 unused_0[7]; 6306 u8 valid; 6307 }; 6308 6309 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6310 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6311 __le16 req_type; 6312 __le16 cmpl_ring; 6313 __le16 seq_id; 6314 __le16 target_id; 6315 __le64 resp_addr; 6316 }; 6317 6318 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6319 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6320 __le16 error_code; 6321 __le16 req_type; 6322 __le16 seq_id; 6323 __le16 resp_len; 6324 __le16 rss_cos_lb_ctx_id; 6325 u8 unused_0[5]; 6326 u8 valid; 6327 }; 6328 6329 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6330 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6331 __le16 req_type; 6332 __le16 cmpl_ring; 6333 __le16 seq_id; 6334 __le16 target_id; 6335 __le64 resp_addr; 6336 __le16 rss_cos_lb_ctx_id; 6337 u8 unused_0[6]; 6338 }; 6339 6340 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6341 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6342 __le16 error_code; 6343 __le16 req_type; 6344 __le16 seq_id; 6345 __le16 resp_len; 6346 u8 unused_0[7]; 6347 u8 valid; 6348 }; 6349 6350 /* hwrm_ring_alloc_input (size:704b/88B) */ 6351 struct hwrm_ring_alloc_input { 6352 __le16 req_type; 6353 __le16 cmpl_ring; 6354 __le16 seq_id; 6355 __le16 target_id; 6356 __le64 resp_addr; 6357 __le32 enables; 6358 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6359 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6360 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 6361 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 6362 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 6363 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6364 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 6365 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6366 u8 ring_type; 6367 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6368 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6369 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6370 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6371 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 6372 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 6373 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6374 u8 cmpl_coal_cnt; 6375 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 6376 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 6377 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 6378 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 6379 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 6380 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 6381 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 6382 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 6383 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 6384 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 6385 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 6386 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 6387 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 6388 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 6389 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 6390 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 6391 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 6392 __le16 flags; 6393 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6394 __le64 page_tbl_addr; 6395 __le32 fbo; 6396 u8 page_size; 6397 u8 page_tbl_depth; 6398 __le16 schq_id; 6399 __le32 length; 6400 __le16 logical_id; 6401 __le16 cmpl_ring_id; 6402 __le16 queue_id; 6403 __le16 rx_buf_size; 6404 __le16 rx_ring_id; 6405 __le16 nq_ring_id; 6406 __le16 ring_arb_cfg; 6407 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6408 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6409 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6410 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6411 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6412 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6413 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6414 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6415 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6416 __le16 unused_3; 6417 __le32 reserved3; 6418 __le32 stat_ctx_id; 6419 __le32 reserved4; 6420 __le32 max_bw; 6421 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6422 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6423 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6424 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6425 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6426 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6427 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6428 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6429 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6430 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6431 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6432 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6433 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6434 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6435 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6436 u8 int_mode; 6437 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6438 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6439 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6440 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6441 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 6442 u8 mpc_chnls_type; 6443 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 6444 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 6445 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 6446 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 6447 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 6448 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 6449 u8 unused_4[2]; 6450 __le64 cq_handle; 6451 }; 6452 6453 /* hwrm_ring_alloc_output (size:128b/16B) */ 6454 struct hwrm_ring_alloc_output { 6455 __le16 error_code; 6456 __le16 req_type; 6457 __le16 seq_id; 6458 __le16 resp_len; 6459 __le16 ring_id; 6460 __le16 logical_ring_id; 6461 u8 push_buffer_index; 6462 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6463 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6464 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6465 u8 unused_0[2]; 6466 u8 valid; 6467 }; 6468 6469 /* hwrm_ring_free_input (size:256b/32B) */ 6470 struct hwrm_ring_free_input { 6471 __le16 req_type; 6472 __le16 cmpl_ring; 6473 __le16 seq_id; 6474 __le16 target_id; 6475 __le64 resp_addr; 6476 u8 ring_type; 6477 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 6478 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 6479 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 6480 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6481 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 6482 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 6483 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 6484 u8 flags; 6485 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 6486 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 6487 __le16 ring_id; 6488 __le32 prod_idx; 6489 __le32 opaque; 6490 __le32 unused_1; 6491 }; 6492 6493 /* hwrm_ring_free_output (size:128b/16B) */ 6494 struct hwrm_ring_free_output { 6495 __le16 error_code; 6496 __le16 req_type; 6497 __le16 seq_id; 6498 __le16 resp_len; 6499 u8 unused_0[7]; 6500 u8 valid; 6501 }; 6502 6503 /* hwrm_ring_reset_input (size:192b/24B) */ 6504 struct hwrm_ring_reset_input { 6505 __le16 req_type; 6506 __le16 cmpl_ring; 6507 __le16 seq_id; 6508 __le16 target_id; 6509 __le64 resp_addr; 6510 u8 ring_type; 6511 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 6512 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 6513 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 6514 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6515 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 6516 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 6517 u8 unused_0; 6518 __le16 ring_id; 6519 u8 unused_1[4]; 6520 }; 6521 6522 /* hwrm_ring_reset_output (size:128b/16B) */ 6523 struct hwrm_ring_reset_output { 6524 __le16 error_code; 6525 __le16 req_type; 6526 __le16 seq_id; 6527 __le16 resp_len; 6528 u8 push_buffer_index; 6529 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 6530 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 6531 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 6532 u8 unused_0[3]; 6533 u8 consumer_idx[3]; 6534 u8 valid; 6535 }; 6536 6537 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 6538 struct hwrm_ring_aggint_qcaps_input { 6539 __le16 req_type; 6540 __le16 cmpl_ring; 6541 __le16 seq_id; 6542 __le16 target_id; 6543 __le64 resp_addr; 6544 }; 6545 6546 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 6547 struct hwrm_ring_aggint_qcaps_output { 6548 __le16 error_code; 6549 __le16 req_type; 6550 __le16 seq_id; 6551 __le16 resp_len; 6552 __le32 cmpl_params; 6553 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 6554 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 6555 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 6556 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 6557 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 6558 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 6559 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 6560 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 6561 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 6562 __le32 nq_params; 6563 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 6564 __le16 num_cmpl_dma_aggr_min; 6565 __le16 num_cmpl_dma_aggr_max; 6566 __le16 num_cmpl_dma_aggr_during_int_min; 6567 __le16 num_cmpl_dma_aggr_during_int_max; 6568 __le16 cmpl_aggr_dma_tmr_min; 6569 __le16 cmpl_aggr_dma_tmr_max; 6570 __le16 cmpl_aggr_dma_tmr_during_int_min; 6571 __le16 cmpl_aggr_dma_tmr_during_int_max; 6572 __le16 int_lat_tmr_min_min; 6573 __le16 int_lat_tmr_min_max; 6574 __le16 int_lat_tmr_max_min; 6575 __le16 int_lat_tmr_max_max; 6576 __le16 num_cmpl_aggr_int_min; 6577 __le16 num_cmpl_aggr_int_max; 6578 __le16 timer_units; 6579 u8 unused_0[1]; 6580 u8 valid; 6581 }; 6582 6583 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 6584 struct hwrm_ring_cmpl_ring_qaggint_params_input { 6585 __le16 req_type; 6586 __le16 cmpl_ring; 6587 __le16 seq_id; 6588 __le16 target_id; 6589 __le64 resp_addr; 6590 __le16 ring_id; 6591 __le16 flags; 6592 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 6593 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 6594 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6595 u8 unused_0[4]; 6596 }; 6597 6598 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 6599 struct hwrm_ring_cmpl_ring_qaggint_params_output { 6600 __le16 error_code; 6601 __le16 req_type; 6602 __le16 seq_id; 6603 __le16 resp_len; 6604 __le16 flags; 6605 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 6606 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 6607 __le16 num_cmpl_dma_aggr; 6608 __le16 num_cmpl_dma_aggr_during_int; 6609 __le16 cmpl_aggr_dma_tmr; 6610 __le16 cmpl_aggr_dma_tmr_during_int; 6611 __le16 int_lat_tmr_min; 6612 __le16 int_lat_tmr_max; 6613 __le16 num_cmpl_aggr_int; 6614 u8 unused_0[7]; 6615 u8 valid; 6616 }; 6617 6618 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 6619 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 6620 __le16 req_type; 6621 __le16 cmpl_ring; 6622 __le16 seq_id; 6623 __le16 target_id; 6624 __le64 resp_addr; 6625 __le16 ring_id; 6626 __le16 flags; 6627 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 6628 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 6629 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6630 __le16 num_cmpl_dma_aggr; 6631 __le16 num_cmpl_dma_aggr_during_int; 6632 __le16 cmpl_aggr_dma_tmr; 6633 __le16 cmpl_aggr_dma_tmr_during_int; 6634 __le16 int_lat_tmr_min; 6635 __le16 int_lat_tmr_max; 6636 __le16 num_cmpl_aggr_int; 6637 __le16 enables; 6638 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 6639 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 6640 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 6641 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 6642 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 6643 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 6644 u8 unused_0[4]; 6645 }; 6646 6647 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 6648 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 6649 __le16 error_code; 6650 __le16 req_type; 6651 __le16 seq_id; 6652 __le16 resp_len; 6653 u8 unused_0[7]; 6654 u8 valid; 6655 }; 6656 6657 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 6658 struct hwrm_ring_grp_alloc_input { 6659 __le16 req_type; 6660 __le16 cmpl_ring; 6661 __le16 seq_id; 6662 __le16 target_id; 6663 __le64 resp_addr; 6664 __le16 cr; 6665 __le16 rr; 6666 __le16 ar; 6667 __le16 sc; 6668 }; 6669 6670 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 6671 struct hwrm_ring_grp_alloc_output { 6672 __le16 error_code; 6673 __le16 req_type; 6674 __le16 seq_id; 6675 __le16 resp_len; 6676 __le32 ring_group_id; 6677 u8 unused_0[3]; 6678 u8 valid; 6679 }; 6680 6681 /* hwrm_ring_grp_free_input (size:192b/24B) */ 6682 struct hwrm_ring_grp_free_input { 6683 __le16 req_type; 6684 __le16 cmpl_ring; 6685 __le16 seq_id; 6686 __le16 target_id; 6687 __le64 resp_addr; 6688 __le32 ring_group_id; 6689 u8 unused_0[4]; 6690 }; 6691 6692 /* hwrm_ring_grp_free_output (size:128b/16B) */ 6693 struct hwrm_ring_grp_free_output { 6694 __le16 error_code; 6695 __le16 req_type; 6696 __le16 seq_id; 6697 __le16 resp_len; 6698 u8 unused_0[7]; 6699 u8 valid; 6700 }; 6701 6702 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 6703 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 6704 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 6705 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 6706 6707 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 6708 struct hwrm_cfa_l2_filter_alloc_input { 6709 __le16 req_type; 6710 __le16 cmpl_ring; 6711 __le16 seq_id; 6712 __le16 target_id; 6713 __le64 resp_addr; 6714 __le32 flags; 6715 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 6716 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 6717 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 6718 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 6719 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 6720 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 6721 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 6722 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 6723 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 6724 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 6725 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 6726 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 6727 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 6728 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 6729 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 6730 __le32 enables; 6731 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 6732 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 6733 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 6734 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 6735 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 6736 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 6737 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 6738 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 6739 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 6740 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 6741 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 6742 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 6743 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 6744 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6745 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6746 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6747 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6748 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 6749 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6750 u8 l2_addr[6]; 6751 u8 num_vlans; 6752 u8 t_num_vlans; 6753 u8 l2_addr_mask[6]; 6754 __le16 l2_ovlan; 6755 __le16 l2_ovlan_mask; 6756 __le16 l2_ivlan; 6757 __le16 l2_ivlan_mask; 6758 u8 unused_1[2]; 6759 u8 t_l2_addr[6]; 6760 u8 unused_2[2]; 6761 u8 t_l2_addr_mask[6]; 6762 __le16 t_l2_ovlan; 6763 __le16 t_l2_ovlan_mask; 6764 __le16 t_l2_ivlan; 6765 __le16 t_l2_ivlan_mask; 6766 u8 src_type; 6767 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6768 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6769 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6770 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6771 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6772 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6773 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6774 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6775 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6776 u8 unused_3; 6777 __le32 src_id; 6778 u8 tunnel_type; 6779 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6780 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6781 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6782 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6783 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6784 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6785 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6786 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6787 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6788 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6789 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6790 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6791 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6792 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6793 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6794 u8 unused_4; 6795 __le16 dst_id; 6796 __le16 mirror_vnic_id; 6797 u8 pri_hint; 6798 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6799 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6800 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6801 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6802 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6803 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6804 u8 unused_5; 6805 __le32 unused_6; 6806 __le64 l2_filter_id_hint; 6807 }; 6808 6809 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6810 struct hwrm_cfa_l2_filter_alloc_output { 6811 __le16 error_code; 6812 __le16 req_type; 6813 __le16 seq_id; 6814 __le16 resp_len; 6815 __le64 l2_filter_id; 6816 __le32 flow_id; 6817 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6818 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6819 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6820 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6821 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6822 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6823 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6824 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6825 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6826 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6827 u8 unused_0[3]; 6828 u8 valid; 6829 }; 6830 6831 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6832 struct hwrm_cfa_l2_filter_free_input { 6833 __le16 req_type; 6834 __le16 cmpl_ring; 6835 __le16 seq_id; 6836 __le16 target_id; 6837 __le64 resp_addr; 6838 __le64 l2_filter_id; 6839 }; 6840 6841 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6842 struct hwrm_cfa_l2_filter_free_output { 6843 __le16 error_code; 6844 __le16 req_type; 6845 __le16 seq_id; 6846 __le16 resp_len; 6847 u8 unused_0[7]; 6848 u8 valid; 6849 }; 6850 6851 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6852 struct hwrm_cfa_l2_filter_cfg_input { 6853 __le16 req_type; 6854 __le16 cmpl_ring; 6855 __le16 seq_id; 6856 __le16 target_id; 6857 __le64 resp_addr; 6858 __le32 flags; 6859 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6860 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6861 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 6862 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6863 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 6864 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 6865 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 6866 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 6867 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 6868 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 6869 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6870 __le32 enables; 6871 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6872 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6873 __le64 l2_filter_id; 6874 __le32 dst_id; 6875 __le32 new_mirror_vnic_id; 6876 }; 6877 6878 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6879 struct hwrm_cfa_l2_filter_cfg_output { 6880 __le16 error_code; 6881 __le16 req_type; 6882 __le16 seq_id; 6883 __le16 resp_len; 6884 u8 unused_0[7]; 6885 u8 valid; 6886 }; 6887 6888 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6889 struct hwrm_cfa_l2_set_rx_mask_input { 6890 __le16 req_type; 6891 __le16 cmpl_ring; 6892 __le16 seq_id; 6893 __le16 target_id; 6894 __le64 resp_addr; 6895 __le32 vnic_id; 6896 __le32 mask; 6897 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6898 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6899 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6900 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6901 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6902 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6903 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6904 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6905 __le64 mc_tbl_addr; 6906 __le32 num_mc_entries; 6907 u8 unused_0[4]; 6908 __le64 vlan_tag_tbl_addr; 6909 __le32 num_vlan_tags; 6910 u8 unused_1[4]; 6911 }; 6912 6913 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6914 struct hwrm_cfa_l2_set_rx_mask_output { 6915 __le16 error_code; 6916 __le16 req_type; 6917 __le16 seq_id; 6918 __le16 resp_len; 6919 u8 unused_0[7]; 6920 u8 valid; 6921 }; 6922 6923 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 6924 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 6925 u8 code; 6926 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 6927 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6928 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 6929 u8 unused_0[7]; 6930 }; 6931 6932 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6933 struct hwrm_cfa_tunnel_filter_alloc_input { 6934 __le16 req_type; 6935 __le16 cmpl_ring; 6936 __le16 seq_id; 6937 __le16 target_id; 6938 __le64 resp_addr; 6939 __le32 flags; 6940 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6941 __le32 enables; 6942 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6943 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6944 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6945 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6946 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6947 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6948 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6949 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6950 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6951 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6952 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6953 __le64 l2_filter_id; 6954 u8 l2_addr[6]; 6955 __le16 l2_ivlan; 6956 __le32 l3_addr[4]; 6957 __le32 t_l3_addr[4]; 6958 u8 l3_addr_type; 6959 u8 t_l3_addr_type; 6960 u8 tunnel_type; 6961 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6962 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6963 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6964 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6965 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6966 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6967 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6968 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6969 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6970 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6971 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6972 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6973 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6974 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6975 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6976 u8 tunnel_flags; 6977 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6978 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6979 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6980 __le32 vni; 6981 __le32 dst_vnic_id; 6982 __le32 mirror_vnic_id; 6983 }; 6984 6985 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6986 struct hwrm_cfa_tunnel_filter_alloc_output { 6987 __le16 error_code; 6988 __le16 req_type; 6989 __le16 seq_id; 6990 __le16 resp_len; 6991 __le64 tunnel_filter_id; 6992 __le32 flow_id; 6993 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6994 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6995 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6996 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6997 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6998 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6999 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7000 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7001 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7002 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7003 u8 unused_0[3]; 7004 u8 valid; 7005 }; 7006 7007 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7008 struct hwrm_cfa_tunnel_filter_free_input { 7009 __le16 req_type; 7010 __le16 cmpl_ring; 7011 __le16 seq_id; 7012 __le16 target_id; 7013 __le64 resp_addr; 7014 __le64 tunnel_filter_id; 7015 }; 7016 7017 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7018 struct hwrm_cfa_tunnel_filter_free_output { 7019 __le16 error_code; 7020 __le16 req_type; 7021 __le16 seq_id; 7022 __le16 resp_len; 7023 u8 unused_0[7]; 7024 u8 valid; 7025 }; 7026 7027 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7028 struct hwrm_vxlan_ipv4_hdr { 7029 u8 ver_hlen; 7030 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7031 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7032 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7033 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7034 u8 tos; 7035 __be16 ip_id; 7036 __be16 flags_frag_offset; 7037 u8 ttl; 7038 u8 protocol; 7039 __be32 src_ip_addr; 7040 __be32 dest_ip_addr; 7041 }; 7042 7043 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7044 struct hwrm_vxlan_ipv6_hdr { 7045 __be32 ver_tc_flow_label; 7046 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7047 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7048 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7049 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7050 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7051 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7052 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7053 __be16 payload_len; 7054 u8 next_hdr; 7055 u8 ttl; 7056 __be32 src_ip_addr[4]; 7057 __be32 dest_ip_addr[4]; 7058 }; 7059 7060 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7061 struct hwrm_cfa_encap_data_vxlan { 7062 u8 src_mac_addr[6]; 7063 __le16 unused_0; 7064 u8 dst_mac_addr[6]; 7065 u8 num_vlan_tags; 7066 u8 unused_1; 7067 __be16 ovlan_tpid; 7068 __be16 ovlan_tci; 7069 __be16 ivlan_tpid; 7070 __be16 ivlan_tci; 7071 __le32 l3[10]; 7072 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7073 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7074 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7075 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7076 __be16 src_port; 7077 __be16 dst_port; 7078 __be32 vni; 7079 u8 hdr_rsvd0[3]; 7080 u8 hdr_rsvd1; 7081 u8 hdr_flags; 7082 u8 unused[3]; 7083 }; 7084 7085 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7086 struct hwrm_cfa_encap_record_alloc_input { 7087 __le16 req_type; 7088 __le16 cmpl_ring; 7089 __le16 seq_id; 7090 __le16 target_id; 7091 __le64 resp_addr; 7092 __le32 flags; 7093 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7094 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7095 u8 encap_type; 7096 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7097 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7098 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7099 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7100 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7101 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7102 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7103 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 7104 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 7105 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 7106 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 7107 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 7108 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7109 u8 unused_0[3]; 7110 __le32 encap_data[20]; 7111 }; 7112 7113 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7114 struct hwrm_cfa_encap_record_alloc_output { 7115 __le16 error_code; 7116 __le16 req_type; 7117 __le16 seq_id; 7118 __le16 resp_len; 7119 __le32 encap_record_id; 7120 u8 unused_0[3]; 7121 u8 valid; 7122 }; 7123 7124 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7125 struct hwrm_cfa_encap_record_free_input { 7126 __le16 req_type; 7127 __le16 cmpl_ring; 7128 __le16 seq_id; 7129 __le16 target_id; 7130 __le64 resp_addr; 7131 __le32 encap_record_id; 7132 u8 unused_0[4]; 7133 }; 7134 7135 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7136 struct hwrm_cfa_encap_record_free_output { 7137 __le16 error_code; 7138 __le16 req_type; 7139 __le16 seq_id; 7140 __le16 resp_len; 7141 u8 unused_0[7]; 7142 u8 valid; 7143 }; 7144 7145 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7146 struct hwrm_cfa_ntuple_filter_alloc_input { 7147 __le16 req_type; 7148 __le16 cmpl_ring; 7149 __le16 seq_id; 7150 __le16 target_id; 7151 __le64 resp_addr; 7152 __le32 flags; 7153 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7154 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7155 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 7156 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 7157 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 7158 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7159 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7160 __le32 enables; 7161 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7162 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7163 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7164 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7165 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7166 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7167 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7168 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7169 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7170 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7171 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7172 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7173 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7174 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7175 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7176 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7177 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7178 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7179 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 7180 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7181 __le64 l2_filter_id; 7182 u8 src_macaddr[6]; 7183 __be16 ethertype; 7184 u8 ip_addr_type; 7185 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7186 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7187 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7188 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7189 u8 ip_protocol; 7190 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7191 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7192 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7193 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7194 __le16 dst_id; 7195 __le16 mirror_vnic_id; 7196 u8 tunnel_type; 7197 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7198 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7199 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7200 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7201 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7202 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7203 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7204 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7205 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7206 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7207 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7208 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7209 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7210 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7211 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7212 u8 pri_hint; 7213 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7214 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7215 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7216 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7217 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7218 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7219 __be32 src_ipaddr[4]; 7220 __be32 src_ipaddr_mask[4]; 7221 __be32 dst_ipaddr[4]; 7222 __be32 dst_ipaddr_mask[4]; 7223 __be16 src_port; 7224 __be16 src_port_mask; 7225 __be16 dst_port; 7226 __be16 dst_port_mask; 7227 __le64 ntuple_filter_id_hint; 7228 }; 7229 7230 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7231 struct hwrm_cfa_ntuple_filter_alloc_output { 7232 __le16 error_code; 7233 __le16 req_type; 7234 __le16 seq_id; 7235 __le16 resp_len; 7236 __le64 ntuple_filter_id; 7237 __le32 flow_id; 7238 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7239 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7240 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7241 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7242 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7243 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7244 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7245 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7246 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7247 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7248 u8 unused_0[3]; 7249 u8 valid; 7250 }; 7251 7252 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 7253 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 7254 u8 code; 7255 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7256 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7257 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 7258 u8 unused_0[7]; 7259 }; 7260 7261 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7262 struct hwrm_cfa_ntuple_filter_free_input { 7263 __le16 req_type; 7264 __le16 cmpl_ring; 7265 __le16 seq_id; 7266 __le16 target_id; 7267 __le64 resp_addr; 7268 __le64 ntuple_filter_id; 7269 }; 7270 7271 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7272 struct hwrm_cfa_ntuple_filter_free_output { 7273 __le16 error_code; 7274 __le16 req_type; 7275 __le16 seq_id; 7276 __le16 resp_len; 7277 u8 unused_0[7]; 7278 u8 valid; 7279 }; 7280 7281 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7282 struct hwrm_cfa_ntuple_filter_cfg_input { 7283 __le16 req_type; 7284 __le16 cmpl_ring; 7285 __le16 seq_id; 7286 __le16 target_id; 7287 __le64 resp_addr; 7288 __le32 enables; 7289 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7290 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7291 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 7292 __le32 flags; 7293 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 7294 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7295 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7296 __le64 ntuple_filter_id; 7297 __le32 new_dst_id; 7298 __le32 new_mirror_vnic_id; 7299 __le16 new_meter_instance_id; 7300 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7301 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7302 u8 unused_1[6]; 7303 }; 7304 7305 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7306 struct hwrm_cfa_ntuple_filter_cfg_output { 7307 __le16 error_code; 7308 __le16 req_type; 7309 __le16 seq_id; 7310 __le16 resp_len; 7311 u8 unused_0[7]; 7312 u8 valid; 7313 }; 7314 7315 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 7316 struct hwrm_cfa_decap_filter_alloc_input { 7317 __le16 req_type; 7318 __le16 cmpl_ring; 7319 __le16 seq_id; 7320 __le16 target_id; 7321 __le64 resp_addr; 7322 __le32 flags; 7323 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 7324 __le32 enables; 7325 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 7326 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 7327 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 7328 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 7329 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 7330 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 7331 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 7332 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 7333 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 7334 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 7335 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 7336 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 7337 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 7338 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 7339 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 7340 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7341 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7342 __be32 tunnel_id; 7343 u8 tunnel_type; 7344 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7345 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7346 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7347 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7348 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7349 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7350 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7351 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7352 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7353 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7354 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7355 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7356 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7357 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7358 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7359 u8 unused_0; 7360 __le16 unused_1; 7361 u8 src_macaddr[6]; 7362 u8 unused_2[2]; 7363 u8 dst_macaddr[6]; 7364 __be16 ovlan_vid; 7365 __be16 ivlan_vid; 7366 __be16 t_ovlan_vid; 7367 __be16 t_ivlan_vid; 7368 __be16 ethertype; 7369 u8 ip_addr_type; 7370 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7371 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7372 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7373 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7374 u8 ip_protocol; 7375 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7376 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7377 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7378 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7379 __le16 unused_3; 7380 __le32 unused_4; 7381 __be32 src_ipaddr[4]; 7382 __be32 dst_ipaddr[4]; 7383 __be16 src_port; 7384 __be16 dst_port; 7385 __le16 dst_id; 7386 __le16 l2_ctxt_ref_id; 7387 }; 7388 7389 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 7390 struct hwrm_cfa_decap_filter_alloc_output { 7391 __le16 error_code; 7392 __le16 req_type; 7393 __le16 seq_id; 7394 __le16 resp_len; 7395 __le32 decap_filter_id; 7396 u8 unused_0[3]; 7397 u8 valid; 7398 }; 7399 7400 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 7401 struct hwrm_cfa_decap_filter_free_input { 7402 __le16 req_type; 7403 __le16 cmpl_ring; 7404 __le16 seq_id; 7405 __le16 target_id; 7406 __le64 resp_addr; 7407 __le32 decap_filter_id; 7408 u8 unused_0[4]; 7409 }; 7410 7411 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 7412 struct hwrm_cfa_decap_filter_free_output { 7413 __le16 error_code; 7414 __le16 req_type; 7415 __le16 seq_id; 7416 __le16 resp_len; 7417 u8 unused_0[7]; 7418 u8 valid; 7419 }; 7420 7421 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 7422 struct hwrm_cfa_flow_alloc_input { 7423 __le16 req_type; 7424 __le16 cmpl_ring; 7425 __le16 seq_id; 7426 __le16 target_id; 7427 __le64 resp_addr; 7428 __le16 flags; 7429 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 7430 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 7431 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 7432 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 7433 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 7434 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 7435 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 7436 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 7437 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 7438 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 7439 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 7440 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 7441 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 7442 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 7443 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 7444 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 7445 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 7446 __le16 src_fid; 7447 __le32 tunnel_handle; 7448 __le16 action_flags; 7449 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 7450 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 7451 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 7452 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 7453 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 7454 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 7455 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 7456 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 7457 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 7458 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 7459 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 7460 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 7461 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 7462 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 7463 __le16 dst_fid; 7464 __be16 l2_rewrite_vlan_tpid; 7465 __be16 l2_rewrite_vlan_tci; 7466 __le16 act_meter_id; 7467 __le16 ref_flow_handle; 7468 __be16 ethertype; 7469 __be16 outer_vlan_tci; 7470 __be16 dmac[3]; 7471 __be16 inner_vlan_tci; 7472 __be16 smac[3]; 7473 u8 ip_dst_mask_len; 7474 u8 ip_src_mask_len; 7475 __be32 ip_dst[4]; 7476 __be32 ip_src[4]; 7477 __be16 l4_src_port; 7478 __be16 l4_src_port_mask; 7479 __be16 l4_dst_port; 7480 __be16 l4_dst_port_mask; 7481 __be32 nat_ip_address[4]; 7482 __be16 l2_rewrite_dmac[3]; 7483 __be16 nat_port; 7484 __be16 l2_rewrite_smac[3]; 7485 u8 ip_proto; 7486 u8 tunnel_type; 7487 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7488 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7489 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7490 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7491 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7492 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7493 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7494 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7495 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7496 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7497 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7498 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7499 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7500 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7501 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7502 }; 7503 7504 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 7505 struct hwrm_cfa_flow_alloc_output { 7506 __le16 error_code; 7507 __le16 req_type; 7508 __le16 seq_id; 7509 __le16 resp_len; 7510 __le16 flow_handle; 7511 u8 unused_0[2]; 7512 __le32 flow_id; 7513 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7514 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7515 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7516 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7517 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7518 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 7519 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7520 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7521 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7522 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 7523 __le64 ext_flow_handle; 7524 __le32 flow_counter_id; 7525 u8 unused_1[3]; 7526 u8 valid; 7527 }; 7528 7529 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 7530 struct hwrm_cfa_flow_alloc_cmd_err { 7531 u8 code; 7532 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 7533 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 7534 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 7535 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 7536 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 7537 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 7538 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 7539 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 7540 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 7541 u8 unused_0[7]; 7542 }; 7543 7544 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 7545 struct hwrm_cfa_flow_free_input { 7546 __le16 req_type; 7547 __le16 cmpl_ring; 7548 __le16 seq_id; 7549 __le16 target_id; 7550 __le64 resp_addr; 7551 __le16 flow_handle; 7552 __le16 unused_0; 7553 __le32 flow_counter_id; 7554 __le64 ext_flow_handle; 7555 }; 7556 7557 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 7558 struct hwrm_cfa_flow_free_output { 7559 __le16 error_code; 7560 __le16 req_type; 7561 __le16 seq_id; 7562 __le16 resp_len; 7563 __le64 packet; 7564 __le64 byte; 7565 u8 unused_0[7]; 7566 u8 valid; 7567 }; 7568 7569 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 7570 struct hwrm_cfa_flow_info_input { 7571 __le16 req_type; 7572 __le16 cmpl_ring; 7573 __le16 seq_id; 7574 __le16 target_id; 7575 __le64 resp_addr; 7576 __le16 flow_handle; 7577 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 7578 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 7579 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 7580 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 7581 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 7582 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 7583 u8 unused_0[6]; 7584 __le64 ext_flow_handle; 7585 }; 7586 7587 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 7588 struct hwrm_cfa_flow_info_output { 7589 __le16 error_code; 7590 __le16 req_type; 7591 __le16 seq_id; 7592 __le16 resp_len; 7593 u8 flags; 7594 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 7595 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 7596 u8 profile; 7597 __le16 src_fid; 7598 __le16 dst_fid; 7599 __le16 l2_ctxt_id; 7600 __le64 em_info; 7601 __le64 tcam_info; 7602 __le64 vfp_tcam_info; 7603 __le16 ar_id; 7604 __le16 flow_handle; 7605 __le32 tunnel_handle; 7606 __le16 flow_timer; 7607 u8 unused_0[6]; 7608 __le32 flow_key_data[130]; 7609 __le32 flow_action_info[30]; 7610 u8 unused_1[7]; 7611 u8 valid; 7612 }; 7613 7614 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 7615 struct hwrm_cfa_flow_stats_input { 7616 __le16 req_type; 7617 __le16 cmpl_ring; 7618 __le16 seq_id; 7619 __le16 target_id; 7620 __le64 resp_addr; 7621 __le16 num_flows; 7622 __le16 flow_handle_0; 7623 __le16 flow_handle_1; 7624 __le16 flow_handle_2; 7625 __le16 flow_handle_3; 7626 __le16 flow_handle_4; 7627 __le16 flow_handle_5; 7628 __le16 flow_handle_6; 7629 __le16 flow_handle_7; 7630 __le16 flow_handle_8; 7631 __le16 flow_handle_9; 7632 u8 unused_0[2]; 7633 __le32 flow_id_0; 7634 __le32 flow_id_1; 7635 __le32 flow_id_2; 7636 __le32 flow_id_3; 7637 __le32 flow_id_4; 7638 __le32 flow_id_5; 7639 __le32 flow_id_6; 7640 __le32 flow_id_7; 7641 __le32 flow_id_8; 7642 __le32 flow_id_9; 7643 }; 7644 7645 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 7646 struct hwrm_cfa_flow_stats_output { 7647 __le16 error_code; 7648 __le16 req_type; 7649 __le16 seq_id; 7650 __le16 resp_len; 7651 __le64 packet_0; 7652 __le64 packet_1; 7653 __le64 packet_2; 7654 __le64 packet_3; 7655 __le64 packet_4; 7656 __le64 packet_5; 7657 __le64 packet_6; 7658 __le64 packet_7; 7659 __le64 packet_8; 7660 __le64 packet_9; 7661 __le64 byte_0; 7662 __le64 byte_1; 7663 __le64 byte_2; 7664 __le64 byte_3; 7665 __le64 byte_4; 7666 __le64 byte_5; 7667 __le64 byte_6; 7668 __le64 byte_7; 7669 __le64 byte_8; 7670 __le64 byte_9; 7671 u8 unused_0[7]; 7672 u8 valid; 7673 }; 7674 7675 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 7676 struct hwrm_cfa_vfr_alloc_input { 7677 __le16 req_type; 7678 __le16 cmpl_ring; 7679 __le16 seq_id; 7680 __le16 target_id; 7681 __le64 resp_addr; 7682 __le16 vf_id; 7683 __le16 reserved; 7684 u8 unused_0[4]; 7685 char vfr_name[32]; 7686 }; 7687 7688 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 7689 struct hwrm_cfa_vfr_alloc_output { 7690 __le16 error_code; 7691 __le16 req_type; 7692 __le16 seq_id; 7693 __le16 resp_len; 7694 __le16 rx_cfa_code; 7695 __le16 tx_cfa_action; 7696 u8 unused_0[3]; 7697 u8 valid; 7698 }; 7699 7700 /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 7701 struct hwrm_cfa_vfr_free_input { 7702 __le16 req_type; 7703 __le16 cmpl_ring; 7704 __le16 seq_id; 7705 __le16 target_id; 7706 __le64 resp_addr; 7707 char vfr_name[32]; 7708 __le16 vf_id; 7709 __le16 reserved; 7710 u8 unused_0[4]; 7711 }; 7712 7713 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 7714 struct hwrm_cfa_vfr_free_output { 7715 __le16 error_code; 7716 __le16 req_type; 7717 __le16 seq_id; 7718 __le16 resp_len; 7719 u8 unused_0[7]; 7720 u8 valid; 7721 }; 7722 7723 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 7724 struct hwrm_cfa_eem_qcaps_input { 7725 __le16 req_type; 7726 __le16 cmpl_ring; 7727 __le16 seq_id; 7728 __le16 target_id; 7729 __le64 resp_addr; 7730 __le32 flags; 7731 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 7732 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 7733 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7734 __le32 unused_0; 7735 }; 7736 7737 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 7738 struct hwrm_cfa_eem_qcaps_output { 7739 __le16 error_code; 7740 __le16 req_type; 7741 __le16 seq_id; 7742 __le16 resp_len; 7743 __le32 flags; 7744 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 7745 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 7746 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 7747 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 7748 __le32 unused_0; 7749 __le32 supported; 7750 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 7751 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 7752 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 7753 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 7754 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 7755 __le32 max_entries_supported; 7756 __le16 key_entry_size; 7757 __le16 record_entry_size; 7758 __le16 efc_entry_size; 7759 __le16 fid_entry_size; 7760 u8 unused_1[7]; 7761 u8 valid; 7762 }; 7763 7764 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 7765 struct hwrm_cfa_eem_cfg_input { 7766 __le16 req_type; 7767 __le16 cmpl_ring; 7768 __le16 seq_id; 7769 __le16 target_id; 7770 __le64 resp_addr; 7771 __le32 flags; 7772 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 7773 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 7774 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 7775 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 7776 __le16 group_id; 7777 __le16 unused_0; 7778 __le32 num_entries; 7779 __le32 unused_1; 7780 __le16 key0_ctx_id; 7781 __le16 key1_ctx_id; 7782 __le16 record_ctx_id; 7783 __le16 efc_ctx_id; 7784 __le16 fid_ctx_id; 7785 __le16 unused_2; 7786 __le32 unused_3; 7787 }; 7788 7789 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 7790 struct hwrm_cfa_eem_cfg_output { 7791 __le16 error_code; 7792 __le16 req_type; 7793 __le16 seq_id; 7794 __le16 resp_len; 7795 u8 unused_0[7]; 7796 u8 valid; 7797 }; 7798 7799 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 7800 struct hwrm_cfa_eem_qcfg_input { 7801 __le16 req_type; 7802 __le16 cmpl_ring; 7803 __le16 seq_id; 7804 __le16 target_id; 7805 __le64 resp_addr; 7806 __le32 flags; 7807 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 7808 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 7809 __le32 unused_0; 7810 }; 7811 7812 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 7813 struct hwrm_cfa_eem_qcfg_output { 7814 __le16 error_code; 7815 __le16 req_type; 7816 __le16 seq_id; 7817 __le16 resp_len; 7818 __le32 flags; 7819 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 7820 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 7821 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 7822 __le32 num_entries; 7823 __le16 key0_ctx_id; 7824 __le16 key1_ctx_id; 7825 __le16 record_ctx_id; 7826 __le16 efc_ctx_id; 7827 __le16 fid_ctx_id; 7828 u8 unused_2[5]; 7829 u8 valid; 7830 }; 7831 7832 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 7833 struct hwrm_cfa_eem_op_input { 7834 __le16 req_type; 7835 __le16 cmpl_ring; 7836 __le16 seq_id; 7837 __le16 target_id; 7838 __le64 resp_addr; 7839 __le32 flags; 7840 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 7841 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 7842 __le16 unused_0; 7843 __le16 op; 7844 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 7845 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 7846 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 7847 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 7848 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 7849 }; 7850 7851 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 7852 struct hwrm_cfa_eem_op_output { 7853 __le16 error_code; 7854 __le16 req_type; 7855 __le16 seq_id; 7856 __le16 resp_len; 7857 u8 unused_0[7]; 7858 u8 valid; 7859 }; 7860 7861 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 7862 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 7863 __le16 req_type; 7864 __le16 cmpl_ring; 7865 __le16 seq_id; 7866 __le16 target_id; 7867 __le64 resp_addr; 7868 __le32 unused_0[4]; 7869 }; 7870 7871 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 7872 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 7873 __le16 error_code; 7874 __le16 req_type; 7875 __le16 seq_id; 7876 __le16 resp_len; 7877 __le32 flags; 7878 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 7879 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 7880 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 7881 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 7882 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 7883 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 7884 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 7885 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 7886 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7887 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7888 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7889 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7890 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7891 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7892 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7893 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7894 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 7895 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 7896 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 7897 u8 unused_0[3]; 7898 u8 valid; 7899 }; 7900 7901 struct hwrm_tunnel_dst_port_query_input { 7902 __le16 req_type; 7903 __le16 cmpl_ring; 7904 __le16 seq_id; 7905 __le16 target_id; 7906 __le64 resp_addr; 7907 u8 tunnel_type; 7908 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7909 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7910 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7911 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7912 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7913 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7914 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7915 u8 unused_0[7]; 7916 }; 7917 7918 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7919 struct hwrm_tunnel_dst_port_query_output { 7920 __le16 error_code; 7921 __le16 req_type; 7922 __le16 seq_id; 7923 __le16 resp_len; 7924 __le16 tunnel_dst_port_id; 7925 __be16 tunnel_dst_port_val; 7926 u8 unused_0[3]; 7927 u8 valid; 7928 }; 7929 7930 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7931 struct hwrm_tunnel_dst_port_alloc_input { 7932 __le16 req_type; 7933 __le16 cmpl_ring; 7934 __le16 seq_id; 7935 __le16 target_id; 7936 __le64 resp_addr; 7937 u8 tunnel_type; 7938 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7939 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7940 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7941 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7942 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7943 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7944 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7945 u8 unused_0; 7946 __be16 tunnel_dst_port_val; 7947 u8 unused_1[4]; 7948 }; 7949 7950 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7951 struct hwrm_tunnel_dst_port_alloc_output { 7952 __le16 error_code; 7953 __le16 req_type; 7954 __le16 seq_id; 7955 __le16 resp_len; 7956 __le16 tunnel_dst_port_id; 7957 u8 unused_0[5]; 7958 u8 valid; 7959 }; 7960 7961 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7962 struct hwrm_tunnel_dst_port_free_input { 7963 __le16 req_type; 7964 __le16 cmpl_ring; 7965 __le16 seq_id; 7966 __le16 target_id; 7967 __le64 resp_addr; 7968 u8 tunnel_type; 7969 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7970 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7971 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7972 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7973 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7974 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7975 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7976 u8 unused_0; 7977 __le16 tunnel_dst_port_id; 7978 u8 unused_1[4]; 7979 }; 7980 7981 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7982 struct hwrm_tunnel_dst_port_free_output { 7983 __le16 error_code; 7984 __le16 req_type; 7985 __le16 seq_id; 7986 __le16 resp_len; 7987 u8 unused_1[7]; 7988 u8 valid; 7989 }; 7990 7991 /* ctx_hw_stats (size:1280b/160B) */ 7992 struct ctx_hw_stats { 7993 __le64 rx_ucast_pkts; 7994 __le64 rx_mcast_pkts; 7995 __le64 rx_bcast_pkts; 7996 __le64 rx_discard_pkts; 7997 __le64 rx_error_pkts; 7998 __le64 rx_ucast_bytes; 7999 __le64 rx_mcast_bytes; 8000 __le64 rx_bcast_bytes; 8001 __le64 tx_ucast_pkts; 8002 __le64 tx_mcast_pkts; 8003 __le64 tx_bcast_pkts; 8004 __le64 tx_error_pkts; 8005 __le64 tx_discard_pkts; 8006 __le64 tx_ucast_bytes; 8007 __le64 tx_mcast_bytes; 8008 __le64 tx_bcast_bytes; 8009 __le64 tpa_pkts; 8010 __le64 tpa_bytes; 8011 __le64 tpa_events; 8012 __le64 tpa_aborts; 8013 }; 8014 8015 /* ctx_hw_stats_ext (size:1408b/176B) */ 8016 struct ctx_hw_stats_ext { 8017 __le64 rx_ucast_pkts; 8018 __le64 rx_mcast_pkts; 8019 __le64 rx_bcast_pkts; 8020 __le64 rx_discard_pkts; 8021 __le64 rx_error_pkts; 8022 __le64 rx_ucast_bytes; 8023 __le64 rx_mcast_bytes; 8024 __le64 rx_bcast_bytes; 8025 __le64 tx_ucast_pkts; 8026 __le64 tx_mcast_pkts; 8027 __le64 tx_bcast_pkts; 8028 __le64 tx_error_pkts; 8029 __le64 tx_discard_pkts; 8030 __le64 tx_ucast_bytes; 8031 __le64 tx_mcast_bytes; 8032 __le64 tx_bcast_bytes; 8033 __le64 rx_tpa_eligible_pkt; 8034 __le64 rx_tpa_eligible_bytes; 8035 __le64 rx_tpa_pkt; 8036 __le64 rx_tpa_bytes; 8037 __le64 rx_tpa_errors; 8038 __le64 rx_tpa_events; 8039 }; 8040 8041 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 8042 struct hwrm_stat_ctx_alloc_input { 8043 __le16 req_type; 8044 __le16 cmpl_ring; 8045 __le16 seq_id; 8046 __le16 target_id; 8047 __le64 resp_addr; 8048 __le64 stats_dma_addr; 8049 __le32 update_period_ms; 8050 u8 stat_ctx_flags; 8051 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 8052 u8 unused_0; 8053 __le16 stats_dma_length; 8054 }; 8055 8056 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8057 struct hwrm_stat_ctx_alloc_output { 8058 __le16 error_code; 8059 __le16 req_type; 8060 __le16 seq_id; 8061 __le16 resp_len; 8062 __le32 stat_ctx_id; 8063 u8 unused_0[3]; 8064 u8 valid; 8065 }; 8066 8067 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8068 struct hwrm_stat_ctx_free_input { 8069 __le16 req_type; 8070 __le16 cmpl_ring; 8071 __le16 seq_id; 8072 __le16 target_id; 8073 __le64 resp_addr; 8074 __le32 stat_ctx_id; 8075 u8 unused_0[4]; 8076 }; 8077 8078 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8079 struct hwrm_stat_ctx_free_output { 8080 __le16 error_code; 8081 __le16 req_type; 8082 __le16 seq_id; 8083 __le16 resp_len; 8084 __le32 stat_ctx_id; 8085 u8 unused_0[3]; 8086 u8 valid; 8087 }; 8088 8089 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8090 struct hwrm_stat_ctx_query_input { 8091 __le16 req_type; 8092 __le16 cmpl_ring; 8093 __le16 seq_id; 8094 __le16 target_id; 8095 __le64 resp_addr; 8096 __le32 stat_ctx_id; 8097 u8 flags; 8098 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8099 u8 unused_0[3]; 8100 }; 8101 8102 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8103 struct hwrm_stat_ctx_query_output { 8104 __le16 error_code; 8105 __le16 req_type; 8106 __le16 seq_id; 8107 __le16 resp_len; 8108 __le64 tx_ucast_pkts; 8109 __le64 tx_mcast_pkts; 8110 __le64 tx_bcast_pkts; 8111 __le64 tx_discard_pkts; 8112 __le64 tx_error_pkts; 8113 __le64 tx_ucast_bytes; 8114 __le64 tx_mcast_bytes; 8115 __le64 tx_bcast_bytes; 8116 __le64 rx_ucast_pkts; 8117 __le64 rx_mcast_pkts; 8118 __le64 rx_bcast_pkts; 8119 __le64 rx_discard_pkts; 8120 __le64 rx_error_pkts; 8121 __le64 rx_ucast_bytes; 8122 __le64 rx_mcast_bytes; 8123 __le64 rx_bcast_bytes; 8124 __le64 rx_agg_pkts; 8125 __le64 rx_agg_bytes; 8126 __le64 rx_agg_events; 8127 __le64 rx_agg_aborts; 8128 u8 unused_0[7]; 8129 u8 valid; 8130 }; 8131 8132 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8133 struct hwrm_stat_ext_ctx_query_input { 8134 __le16 req_type; 8135 __le16 cmpl_ring; 8136 __le16 seq_id; 8137 __le16 target_id; 8138 __le64 resp_addr; 8139 __le32 stat_ctx_id; 8140 u8 flags; 8141 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8142 u8 unused_0[3]; 8143 }; 8144 8145 /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8146 struct hwrm_stat_ext_ctx_query_output { 8147 __le16 error_code; 8148 __le16 req_type; 8149 __le16 seq_id; 8150 __le16 resp_len; 8151 __le64 rx_ucast_pkts; 8152 __le64 rx_mcast_pkts; 8153 __le64 rx_bcast_pkts; 8154 __le64 rx_discard_pkts; 8155 __le64 rx_error_pkts; 8156 __le64 rx_ucast_bytes; 8157 __le64 rx_mcast_bytes; 8158 __le64 rx_bcast_bytes; 8159 __le64 tx_ucast_pkts; 8160 __le64 tx_mcast_pkts; 8161 __le64 tx_bcast_pkts; 8162 __le64 tx_error_pkts; 8163 __le64 tx_discard_pkts; 8164 __le64 tx_ucast_bytes; 8165 __le64 tx_mcast_bytes; 8166 __le64 tx_bcast_bytes; 8167 __le64 rx_tpa_eligible_pkt; 8168 __le64 rx_tpa_eligible_bytes; 8169 __le64 rx_tpa_pkt; 8170 __le64 rx_tpa_bytes; 8171 __le64 rx_tpa_errors; 8172 __le64 rx_tpa_events; 8173 u8 unused_0[7]; 8174 u8 valid; 8175 }; 8176 8177 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8178 struct hwrm_stat_ctx_clr_stats_input { 8179 __le16 req_type; 8180 __le16 cmpl_ring; 8181 __le16 seq_id; 8182 __le16 target_id; 8183 __le64 resp_addr; 8184 __le32 stat_ctx_id; 8185 u8 unused_0[4]; 8186 }; 8187 8188 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8189 struct hwrm_stat_ctx_clr_stats_output { 8190 __le16 error_code; 8191 __le16 req_type; 8192 __le16 seq_id; 8193 __le16 resp_len; 8194 u8 unused_0[7]; 8195 u8 valid; 8196 }; 8197 8198 /* hwrm_pcie_qstats_input (size:256b/32B) */ 8199 struct hwrm_pcie_qstats_input { 8200 __le16 req_type; 8201 __le16 cmpl_ring; 8202 __le16 seq_id; 8203 __le16 target_id; 8204 __le64 resp_addr; 8205 __le16 pcie_stat_size; 8206 u8 unused_0[6]; 8207 __le64 pcie_stat_host_addr; 8208 }; 8209 8210 /* hwrm_pcie_qstats_output (size:128b/16B) */ 8211 struct hwrm_pcie_qstats_output { 8212 __le16 error_code; 8213 __le16 req_type; 8214 __le16 seq_id; 8215 __le16 resp_len; 8216 __le16 pcie_stat_size; 8217 u8 unused_0[5]; 8218 u8 valid; 8219 }; 8220 8221 /* pcie_ctx_hw_stats (size:768b/96B) */ 8222 struct pcie_ctx_hw_stats { 8223 __le64 pcie_pl_signal_integrity; 8224 __le64 pcie_dl_signal_integrity; 8225 __le64 pcie_tl_signal_integrity; 8226 __le64 pcie_link_integrity; 8227 __le64 pcie_tx_traffic_rate; 8228 __le64 pcie_rx_traffic_rate; 8229 __le64 pcie_tx_dllp_statistics; 8230 __le64 pcie_rx_dllp_statistics; 8231 __le64 pcie_equalization_time; 8232 __le32 pcie_ltssm_histogram[4]; 8233 __le64 pcie_recovery_histogram; 8234 }; 8235 8236 /* hwrm_fw_reset_input (size:192b/24B) */ 8237 struct hwrm_fw_reset_input { 8238 __le16 req_type; 8239 __le16 cmpl_ring; 8240 __le16 seq_id; 8241 __le16 target_id; 8242 __le64 resp_addr; 8243 u8 embedded_proc_type; 8244 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8245 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8246 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8247 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8248 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8249 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8250 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8251 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 8252 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 8253 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8254 u8 selfrst_status; 8255 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8256 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8257 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8258 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8259 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8260 u8 host_idx; 8261 u8 flags; 8262 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8263 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 8264 u8 unused_0[4]; 8265 }; 8266 8267 /* hwrm_fw_reset_output (size:128b/16B) */ 8268 struct hwrm_fw_reset_output { 8269 __le16 error_code; 8270 __le16 req_type; 8271 __le16 seq_id; 8272 __le16 resp_len; 8273 u8 selfrst_status; 8274 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8275 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8276 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8277 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 8278 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8279 u8 unused_0[6]; 8280 u8 valid; 8281 }; 8282 8283 /* hwrm_fw_qstatus_input (size:192b/24B) */ 8284 struct hwrm_fw_qstatus_input { 8285 __le16 req_type; 8286 __le16 cmpl_ring; 8287 __le16 seq_id; 8288 __le16 target_id; 8289 __le64 resp_addr; 8290 u8 embedded_proc_type; 8291 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8292 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8293 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8294 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8295 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8296 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8297 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8298 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8299 u8 unused_0[7]; 8300 }; 8301 8302 /* hwrm_fw_qstatus_output (size:128b/16B) */ 8303 struct hwrm_fw_qstatus_output { 8304 __le16 error_code; 8305 __le16 req_type; 8306 __le16 seq_id; 8307 __le16 resp_len; 8308 u8 selfrst_status; 8309 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8310 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8311 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 8312 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 8313 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 8314 u8 nvm_option_action_status; 8315 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 8316 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 8317 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 8318 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 8319 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 8320 u8 unused_0[5]; 8321 u8 valid; 8322 }; 8323 8324 /* hwrm_fw_set_time_input (size:256b/32B) */ 8325 struct hwrm_fw_set_time_input { 8326 __le16 req_type; 8327 __le16 cmpl_ring; 8328 __le16 seq_id; 8329 __le16 target_id; 8330 __le64 resp_addr; 8331 __le16 year; 8332 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8333 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8334 u8 month; 8335 u8 day; 8336 u8 hour; 8337 u8 minute; 8338 u8 second; 8339 u8 unused_0; 8340 __le16 millisecond; 8341 __le16 zone; 8342 #define FW_SET_TIME_REQ_ZONE_UTC 0 8343 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8344 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8345 u8 unused_1[4]; 8346 }; 8347 8348 /* hwrm_fw_set_time_output (size:128b/16B) */ 8349 struct hwrm_fw_set_time_output { 8350 __le16 error_code; 8351 __le16 req_type; 8352 __le16 seq_id; 8353 __le16 resp_len; 8354 u8 unused_0[7]; 8355 u8 valid; 8356 }; 8357 8358 /* hwrm_struct_hdr (size:128b/16B) */ 8359 struct hwrm_struct_hdr { 8360 __le16 struct_id; 8361 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 8362 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 8363 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 8364 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 8365 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 8366 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 8367 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 8368 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 8369 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 8370 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 8371 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 8372 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 8373 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 8374 __le16 len; 8375 u8 version; 8376 u8 count; 8377 __le16 subtype; 8378 __le16 next_offset; 8379 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 8380 u8 unused_0[6]; 8381 }; 8382 8383 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 8384 struct hwrm_struct_data_dcbx_app { 8385 __be16 protocol_id; 8386 u8 protocol_selector; 8387 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 8388 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 8389 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 8390 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 8391 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 8392 u8 priority; 8393 u8 valid; 8394 u8 unused_0[3]; 8395 }; 8396 8397 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 8398 struct hwrm_fw_set_structured_data_input { 8399 __le16 req_type; 8400 __le16 cmpl_ring; 8401 __le16 seq_id; 8402 __le16 target_id; 8403 __le64 resp_addr; 8404 __le64 src_data_addr; 8405 __le16 data_len; 8406 u8 hdr_cnt; 8407 u8 unused_0[5]; 8408 }; 8409 8410 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 8411 struct hwrm_fw_set_structured_data_output { 8412 __le16 error_code; 8413 __le16 req_type; 8414 __le16 seq_id; 8415 __le16 resp_len; 8416 u8 unused_0[7]; 8417 u8 valid; 8418 }; 8419 8420 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 8421 struct hwrm_fw_set_structured_data_cmd_err { 8422 u8 code; 8423 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8424 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 8425 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 8426 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8427 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8428 u8 unused_0[7]; 8429 }; 8430 8431 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 8432 struct hwrm_fw_get_structured_data_input { 8433 __le16 req_type; 8434 __le16 cmpl_ring; 8435 __le16 seq_id; 8436 __le16 target_id; 8437 __le64 resp_addr; 8438 __le64 dest_data_addr; 8439 __le16 data_len; 8440 __le16 structure_id; 8441 __le16 subtype; 8442 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 8443 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 8444 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 8445 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 8446 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 8447 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 8448 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 8449 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 8450 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 8451 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 8452 u8 count; 8453 u8 unused_0; 8454 }; 8455 8456 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 8457 struct hwrm_fw_get_structured_data_output { 8458 __le16 error_code; 8459 __le16 req_type; 8460 __le16 seq_id; 8461 __le16 resp_len; 8462 u8 hdr_cnt; 8463 u8 unused_0[6]; 8464 u8 valid; 8465 }; 8466 8467 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 8468 struct hwrm_fw_get_structured_data_cmd_err { 8469 u8 code; 8470 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8471 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8472 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8473 u8 unused_0[7]; 8474 }; 8475 8476 /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 8477 struct hwrm_fw_livepatch_query_input { 8478 __le16 req_type; 8479 __le16 cmpl_ring; 8480 __le16 seq_id; 8481 __le16 target_id; 8482 __le64 resp_addr; 8483 u8 fw_target; 8484 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 8485 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 8486 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 8487 u8 unused_0[7]; 8488 }; 8489 8490 /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 8491 struct hwrm_fw_livepatch_query_output { 8492 __le16 error_code; 8493 __le16 req_type; 8494 __le16 seq_id; 8495 __le16 resp_len; 8496 char install_ver[32]; 8497 char active_ver[32]; 8498 __le16 status_flags; 8499 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 8500 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 8501 u8 unused_0[5]; 8502 u8 valid; 8503 }; 8504 8505 /* hwrm_fw_livepatch_input (size:256b/32B) */ 8506 struct hwrm_fw_livepatch_input { 8507 __le16 req_type; 8508 __le16 cmpl_ring; 8509 __le16 seq_id; 8510 __le16 target_id; 8511 __le64 resp_addr; 8512 u8 opcode; 8513 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 8514 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 8515 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 8516 u8 fw_target; 8517 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 8518 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 8519 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 8520 u8 loadtype; 8521 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 8522 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 8523 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 8524 u8 flags; 8525 __le32 patch_len; 8526 __le64 host_addr; 8527 }; 8528 8529 /* hwrm_fw_livepatch_output (size:128b/16B) */ 8530 struct hwrm_fw_livepatch_output { 8531 __le16 error_code; 8532 __le16 req_type; 8533 __le16 seq_id; 8534 __le16 resp_len; 8535 u8 unused_0[7]; 8536 u8 valid; 8537 }; 8538 8539 /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 8540 struct hwrm_fw_livepatch_cmd_err { 8541 u8 code; 8542 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 8543 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 8544 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 8545 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 8546 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 8547 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 8548 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 8549 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 8550 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 8551 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 8552 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 8553 u8 unused_0[7]; 8554 }; 8555 8556 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 8557 struct hwrm_exec_fwd_resp_input { 8558 __le16 req_type; 8559 __le16 cmpl_ring; 8560 __le16 seq_id; 8561 __le16 target_id; 8562 __le64 resp_addr; 8563 __le32 encap_request[26]; 8564 __le16 encap_resp_target_id; 8565 u8 unused_0[6]; 8566 }; 8567 8568 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 8569 struct hwrm_exec_fwd_resp_output { 8570 __le16 error_code; 8571 __le16 req_type; 8572 __le16 seq_id; 8573 __le16 resp_len; 8574 u8 unused_0[7]; 8575 u8 valid; 8576 }; 8577 8578 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 8579 struct hwrm_reject_fwd_resp_input { 8580 __le16 req_type; 8581 __le16 cmpl_ring; 8582 __le16 seq_id; 8583 __le16 target_id; 8584 __le64 resp_addr; 8585 __le32 encap_request[26]; 8586 __le16 encap_resp_target_id; 8587 u8 unused_0[6]; 8588 }; 8589 8590 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 8591 struct hwrm_reject_fwd_resp_output { 8592 __le16 error_code; 8593 __le16 req_type; 8594 __le16 seq_id; 8595 __le16 resp_len; 8596 u8 unused_0[7]; 8597 u8 valid; 8598 }; 8599 8600 /* hwrm_fwd_resp_input (size:1024b/128B) */ 8601 struct hwrm_fwd_resp_input { 8602 __le16 req_type; 8603 __le16 cmpl_ring; 8604 __le16 seq_id; 8605 __le16 target_id; 8606 __le64 resp_addr; 8607 __le16 encap_resp_target_id; 8608 __le16 encap_resp_cmpl_ring; 8609 __le16 encap_resp_len; 8610 u8 unused_0; 8611 u8 unused_1; 8612 __le64 encap_resp_addr; 8613 __le32 encap_resp[24]; 8614 }; 8615 8616 /* hwrm_fwd_resp_output (size:128b/16B) */ 8617 struct hwrm_fwd_resp_output { 8618 __le16 error_code; 8619 __le16 req_type; 8620 __le16 seq_id; 8621 __le16 resp_len; 8622 u8 unused_0[7]; 8623 u8 valid; 8624 }; 8625 8626 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 8627 struct hwrm_fwd_async_event_cmpl_input { 8628 __le16 req_type; 8629 __le16 cmpl_ring; 8630 __le16 seq_id; 8631 __le16 target_id; 8632 __le64 resp_addr; 8633 __le16 encap_async_event_target_id; 8634 u8 unused_0[6]; 8635 __le32 encap_async_event_cmpl[4]; 8636 }; 8637 8638 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 8639 struct hwrm_fwd_async_event_cmpl_output { 8640 __le16 error_code; 8641 __le16 req_type; 8642 __le16 seq_id; 8643 __le16 resp_len; 8644 u8 unused_0[7]; 8645 u8 valid; 8646 }; 8647 8648 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 8649 struct hwrm_temp_monitor_query_input { 8650 __le16 req_type; 8651 __le16 cmpl_ring; 8652 __le16 seq_id; 8653 __le16 target_id; 8654 __le64 resp_addr; 8655 }; 8656 8657 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 8658 struct hwrm_temp_monitor_query_output { 8659 __le16 error_code; 8660 __le16 req_type; 8661 __le16 seq_id; 8662 __le16 resp_len; 8663 u8 temp; 8664 u8 phy_temp; 8665 u8 om_temp; 8666 u8 flags; 8667 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 8668 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 8669 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 8670 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 8671 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 8672 u8 temp2; 8673 u8 phy_temp2; 8674 u8 om_temp2; 8675 u8 valid; 8676 }; 8677 8678 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 8679 struct hwrm_wol_filter_alloc_input { 8680 __le16 req_type; 8681 __le16 cmpl_ring; 8682 __le16 seq_id; 8683 __le16 target_id; 8684 __le64 resp_addr; 8685 __le32 flags; 8686 __le32 enables; 8687 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 8688 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 8689 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 8690 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 8691 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 8692 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 8693 __le16 port_id; 8694 u8 wol_type; 8695 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 8696 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 8697 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 8698 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 8699 u8 unused_0[5]; 8700 u8 mac_address[6]; 8701 __le16 pattern_offset; 8702 __le16 pattern_buf_size; 8703 __le16 pattern_mask_size; 8704 u8 unused_1[4]; 8705 __le64 pattern_buf_addr; 8706 __le64 pattern_mask_addr; 8707 }; 8708 8709 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 8710 struct hwrm_wol_filter_alloc_output { 8711 __le16 error_code; 8712 __le16 req_type; 8713 __le16 seq_id; 8714 __le16 resp_len; 8715 u8 wol_filter_id; 8716 u8 unused_0[6]; 8717 u8 valid; 8718 }; 8719 8720 /* hwrm_wol_filter_free_input (size:256b/32B) */ 8721 struct hwrm_wol_filter_free_input { 8722 __le16 req_type; 8723 __le16 cmpl_ring; 8724 __le16 seq_id; 8725 __le16 target_id; 8726 __le64 resp_addr; 8727 __le32 flags; 8728 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 8729 __le32 enables; 8730 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 8731 __le16 port_id; 8732 u8 wol_filter_id; 8733 u8 unused_0[5]; 8734 }; 8735 8736 /* hwrm_wol_filter_free_output (size:128b/16B) */ 8737 struct hwrm_wol_filter_free_output { 8738 __le16 error_code; 8739 __le16 req_type; 8740 __le16 seq_id; 8741 __le16 resp_len; 8742 u8 unused_0[7]; 8743 u8 valid; 8744 }; 8745 8746 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 8747 struct hwrm_wol_filter_qcfg_input { 8748 __le16 req_type; 8749 __le16 cmpl_ring; 8750 __le16 seq_id; 8751 __le16 target_id; 8752 __le64 resp_addr; 8753 __le16 port_id; 8754 __le16 handle; 8755 u8 unused_0[4]; 8756 __le64 pattern_buf_addr; 8757 __le16 pattern_buf_size; 8758 u8 unused_1[6]; 8759 __le64 pattern_mask_addr; 8760 __le16 pattern_mask_size; 8761 u8 unused_2[6]; 8762 }; 8763 8764 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 8765 struct hwrm_wol_filter_qcfg_output { 8766 __le16 error_code; 8767 __le16 req_type; 8768 __le16 seq_id; 8769 __le16 resp_len; 8770 __le16 next_handle; 8771 u8 wol_filter_id; 8772 u8 wol_type; 8773 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 8774 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 8775 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 8776 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 8777 __le32 unused_0; 8778 u8 mac_address[6]; 8779 __le16 pattern_offset; 8780 __le16 pattern_size; 8781 __le16 pattern_mask_size; 8782 u8 unused_1[3]; 8783 u8 valid; 8784 }; 8785 8786 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 8787 struct hwrm_wol_reason_qcfg_input { 8788 __le16 req_type; 8789 __le16 cmpl_ring; 8790 __le16 seq_id; 8791 __le16 target_id; 8792 __le64 resp_addr; 8793 __le16 port_id; 8794 u8 unused_0[6]; 8795 __le64 wol_pkt_buf_addr; 8796 __le16 wol_pkt_buf_size; 8797 u8 unused_1[6]; 8798 }; 8799 8800 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 8801 struct hwrm_wol_reason_qcfg_output { 8802 __le16 error_code; 8803 __le16 req_type; 8804 __le16 seq_id; 8805 __le16 resp_len; 8806 u8 wol_filter_id; 8807 u8 wol_reason; 8808 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 8809 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 8810 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 8811 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 8812 u8 wol_pkt_len; 8813 u8 unused_0[4]; 8814 u8 valid; 8815 }; 8816 8817 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 8818 struct hwrm_dbg_read_direct_input { 8819 __le16 req_type; 8820 __le16 cmpl_ring; 8821 __le16 seq_id; 8822 __le16 target_id; 8823 __le64 resp_addr; 8824 __le64 host_dest_addr; 8825 __le32 read_addr; 8826 __le32 read_len32; 8827 }; 8828 8829 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 8830 struct hwrm_dbg_read_direct_output { 8831 __le16 error_code; 8832 __le16 req_type; 8833 __le16 seq_id; 8834 __le16 resp_len; 8835 __le32 crc32; 8836 u8 unused_0[3]; 8837 u8 valid; 8838 }; 8839 8840 /* hwrm_dbg_qcaps_input (size:192b/24B) */ 8841 struct hwrm_dbg_qcaps_input { 8842 __le16 req_type; 8843 __le16 cmpl_ring; 8844 __le16 seq_id; 8845 __le16 target_id; 8846 __le64 resp_addr; 8847 __le16 fid; 8848 u8 unused_0[6]; 8849 }; 8850 8851 /* hwrm_dbg_qcaps_output (size:192b/24B) */ 8852 struct hwrm_dbg_qcaps_output { 8853 __le16 error_code; 8854 __le16 req_type; 8855 __le16 seq_id; 8856 __le16 resp_len; 8857 __le16 fid; 8858 u8 unused_0[2]; 8859 __le32 coredump_component_disable_caps; 8860 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 8861 __le32 flags; 8862 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 8863 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 8864 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 8865 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 8866 u8 unused_1[3]; 8867 u8 valid; 8868 }; 8869 8870 /* hwrm_dbg_qcfg_input (size:192b/24B) */ 8871 struct hwrm_dbg_qcfg_input { 8872 __le16 req_type; 8873 __le16 cmpl_ring; 8874 __le16 seq_id; 8875 __le16 target_id; 8876 __le64 resp_addr; 8877 __le16 fid; 8878 __le16 flags; 8879 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 8880 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 8881 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 8882 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 8883 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 8884 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 8885 __le32 coredump_component_disable_flags; 8886 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 8887 }; 8888 8889 /* hwrm_dbg_qcfg_output (size:256b/32B) */ 8890 struct hwrm_dbg_qcfg_output { 8891 __le16 error_code; 8892 __le16 req_type; 8893 __le16 seq_id; 8894 __le16 resp_len; 8895 __le16 fid; 8896 u8 unused_0[2]; 8897 __le32 coredump_size; 8898 __le32 flags; 8899 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 8900 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 8901 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 8902 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 8903 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 8904 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 8905 __le16 async_cmpl_ring; 8906 u8 unused_2[2]; 8907 __le32 crashdump_size; 8908 u8 unused_3[3]; 8909 u8 valid; 8910 }; 8911 8912 /* coredump_segment_record (size:128b/16B) */ 8913 struct coredump_segment_record { 8914 __le16 component_id; 8915 __le16 segment_id; 8916 __le16 max_instances; 8917 u8 version_hi; 8918 u8 version_low; 8919 u8 seg_flags; 8920 u8 compress_flags; 8921 #define SFLAG_COMPRESSED_ZLIB 0x1UL 8922 u8 unused_0[2]; 8923 __le32 segment_len; 8924 }; 8925 8926 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 8927 struct hwrm_dbg_coredump_list_input { 8928 __le16 req_type; 8929 __le16 cmpl_ring; 8930 __le16 seq_id; 8931 __le16 target_id; 8932 __le64 resp_addr; 8933 __le64 host_dest_addr; 8934 __le32 host_buf_len; 8935 __le16 seq_no; 8936 u8 flags; 8937 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 8938 u8 unused_0[1]; 8939 }; 8940 8941 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 8942 struct hwrm_dbg_coredump_list_output { 8943 __le16 error_code; 8944 __le16 req_type; 8945 __le16 seq_id; 8946 __le16 resp_len; 8947 u8 flags; 8948 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 8949 u8 unused_0; 8950 __le16 total_segments; 8951 __le16 data_len; 8952 u8 unused_1; 8953 u8 valid; 8954 }; 8955 8956 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 8957 struct hwrm_dbg_coredump_initiate_input { 8958 __le16 req_type; 8959 __le16 cmpl_ring; 8960 __le16 seq_id; 8961 __le16 target_id; 8962 __le64 resp_addr; 8963 __le16 component_id; 8964 __le16 segment_id; 8965 __le16 instance; 8966 __le16 unused_0; 8967 u8 seg_flags; 8968 u8 unused_1[7]; 8969 }; 8970 8971 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 8972 struct hwrm_dbg_coredump_initiate_output { 8973 __le16 error_code; 8974 __le16 req_type; 8975 __le16 seq_id; 8976 __le16 resp_len; 8977 u8 unused_0[7]; 8978 u8 valid; 8979 }; 8980 8981 /* coredump_data_hdr (size:128b/16B) */ 8982 struct coredump_data_hdr { 8983 __le32 address; 8984 __le32 flags_length; 8985 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8986 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8987 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 8988 __le32 instance; 8989 __le32 next_offset; 8990 }; 8991 8992 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 8993 struct hwrm_dbg_coredump_retrieve_input { 8994 __le16 req_type; 8995 __le16 cmpl_ring; 8996 __le16 seq_id; 8997 __le16 target_id; 8998 __le64 resp_addr; 8999 __le64 host_dest_addr; 9000 __le32 host_buf_len; 9001 __le32 unused_0; 9002 __le16 component_id; 9003 __le16 segment_id; 9004 __le16 instance; 9005 __le16 unused_1; 9006 u8 seg_flags; 9007 u8 unused_2; 9008 __le16 unused_3; 9009 __le32 unused_4; 9010 __le32 seq_no; 9011 __le32 unused_5; 9012 }; 9013 9014 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 9015 struct hwrm_dbg_coredump_retrieve_output { 9016 __le16 error_code; 9017 __le16 req_type; 9018 __le16 seq_id; 9019 __le16 resp_len; 9020 u8 flags; 9021 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 9022 u8 unused_0; 9023 __le16 data_len; 9024 u8 unused_1[3]; 9025 u8 valid; 9026 }; 9027 9028 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 9029 struct hwrm_dbg_ring_info_get_input { 9030 __le16 req_type; 9031 __le16 cmpl_ring; 9032 __le16 seq_id; 9033 __le16 target_id; 9034 __le64 resp_addr; 9035 u8 ring_type; 9036 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 9037 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 9038 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9039 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9040 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 9041 u8 unused_0[3]; 9042 __le32 fw_ring_id; 9043 }; 9044 9045 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 9046 struct hwrm_dbg_ring_info_get_output { 9047 __le16 error_code; 9048 __le16 req_type; 9049 __le16 seq_id; 9050 __le16 resp_len; 9051 __le32 producer_index; 9052 __le32 consumer_index; 9053 __le32 cag_vector_ctrl; 9054 u8 unused_0[3]; 9055 u8 valid; 9056 }; 9057 9058 /* hwrm_nvm_read_input (size:320b/40B) */ 9059 struct hwrm_nvm_read_input { 9060 __le16 req_type; 9061 __le16 cmpl_ring; 9062 __le16 seq_id; 9063 __le16 target_id; 9064 __le64 resp_addr; 9065 __le64 host_dest_addr; 9066 __le16 dir_idx; 9067 u8 unused_0[2]; 9068 __le32 offset; 9069 __le32 len; 9070 u8 unused_1[4]; 9071 }; 9072 9073 /* hwrm_nvm_read_output (size:128b/16B) */ 9074 struct hwrm_nvm_read_output { 9075 __le16 error_code; 9076 __le16 req_type; 9077 __le16 seq_id; 9078 __le16 resp_len; 9079 u8 unused_0[7]; 9080 u8 valid; 9081 }; 9082 9083 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9084 struct hwrm_nvm_get_dir_entries_input { 9085 __le16 req_type; 9086 __le16 cmpl_ring; 9087 __le16 seq_id; 9088 __le16 target_id; 9089 __le64 resp_addr; 9090 __le64 host_dest_addr; 9091 }; 9092 9093 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9094 struct hwrm_nvm_get_dir_entries_output { 9095 __le16 error_code; 9096 __le16 req_type; 9097 __le16 seq_id; 9098 __le16 resp_len; 9099 u8 unused_0[7]; 9100 u8 valid; 9101 }; 9102 9103 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9104 struct hwrm_nvm_get_dir_info_input { 9105 __le16 req_type; 9106 __le16 cmpl_ring; 9107 __le16 seq_id; 9108 __le16 target_id; 9109 __le64 resp_addr; 9110 }; 9111 9112 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9113 struct hwrm_nvm_get_dir_info_output { 9114 __le16 error_code; 9115 __le16 req_type; 9116 __le16 seq_id; 9117 __le16 resp_len; 9118 __le32 entries; 9119 __le32 entry_length; 9120 u8 unused_0[7]; 9121 u8 valid; 9122 }; 9123 9124 /* hwrm_nvm_write_input (size:448b/56B) */ 9125 struct hwrm_nvm_write_input { 9126 __le16 req_type; 9127 __le16 cmpl_ring; 9128 __le16 seq_id; 9129 __le16 target_id; 9130 __le64 resp_addr; 9131 __le64 host_src_addr; 9132 __le16 dir_type; 9133 __le16 dir_ordinal; 9134 __le16 dir_ext; 9135 __le16 dir_attr; 9136 __le32 dir_data_length; 9137 __le16 option; 9138 __le16 flags; 9139 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9140 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9141 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9142 __le32 dir_item_length; 9143 __le32 offset; 9144 __le32 len; 9145 __le32 unused_0; 9146 }; 9147 9148 /* hwrm_nvm_write_output (size:128b/16B) */ 9149 struct hwrm_nvm_write_output { 9150 __le16 error_code; 9151 __le16 req_type; 9152 __le16 seq_id; 9153 __le16 resp_len; 9154 __le32 dir_item_length; 9155 __le16 dir_idx; 9156 u8 unused_0; 9157 u8 valid; 9158 }; 9159 9160 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9161 struct hwrm_nvm_write_cmd_err { 9162 u8 code; 9163 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9164 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9165 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9166 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9167 u8 unused_0[7]; 9168 }; 9169 9170 /* hwrm_nvm_modify_input (size:320b/40B) */ 9171 struct hwrm_nvm_modify_input { 9172 __le16 req_type; 9173 __le16 cmpl_ring; 9174 __le16 seq_id; 9175 __le16 target_id; 9176 __le64 resp_addr; 9177 __le64 host_src_addr; 9178 __le16 dir_idx; 9179 __le16 flags; 9180 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9181 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9182 __le32 offset; 9183 __le32 len; 9184 u8 unused_1[4]; 9185 }; 9186 9187 /* hwrm_nvm_modify_output (size:128b/16B) */ 9188 struct hwrm_nvm_modify_output { 9189 __le16 error_code; 9190 __le16 req_type; 9191 __le16 seq_id; 9192 __le16 resp_len; 9193 u8 unused_0[7]; 9194 u8 valid; 9195 }; 9196 9197 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9198 struct hwrm_nvm_find_dir_entry_input { 9199 __le16 req_type; 9200 __le16 cmpl_ring; 9201 __le16 seq_id; 9202 __le16 target_id; 9203 __le64 resp_addr; 9204 __le32 enables; 9205 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9206 __le16 dir_idx; 9207 __le16 dir_type; 9208 __le16 dir_ordinal; 9209 __le16 dir_ext; 9210 u8 opt_ordinal; 9211 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9212 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9213 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9214 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9215 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9216 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9217 u8 unused_0[3]; 9218 }; 9219 9220 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9221 struct hwrm_nvm_find_dir_entry_output { 9222 __le16 error_code; 9223 __le16 req_type; 9224 __le16 seq_id; 9225 __le16 resp_len; 9226 __le32 dir_item_length; 9227 __le32 dir_data_length; 9228 __le32 fw_ver; 9229 __le16 dir_ordinal; 9230 __le16 dir_idx; 9231 u8 unused_0[7]; 9232 u8 valid; 9233 }; 9234 9235 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9236 struct hwrm_nvm_erase_dir_entry_input { 9237 __le16 req_type; 9238 __le16 cmpl_ring; 9239 __le16 seq_id; 9240 __le16 target_id; 9241 __le64 resp_addr; 9242 __le16 dir_idx; 9243 u8 unused_0[6]; 9244 }; 9245 9246 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9247 struct hwrm_nvm_erase_dir_entry_output { 9248 __le16 error_code; 9249 __le16 req_type; 9250 __le16 seq_id; 9251 __le16 resp_len; 9252 u8 unused_0[7]; 9253 u8 valid; 9254 }; 9255 9256 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9257 struct hwrm_nvm_get_dev_info_input { 9258 __le16 req_type; 9259 __le16 cmpl_ring; 9260 __le16 seq_id; 9261 __le16 target_id; 9262 __le64 resp_addr; 9263 }; 9264 9265 /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9266 struct hwrm_nvm_get_dev_info_output { 9267 __le16 error_code; 9268 __le16 req_type; 9269 __le16 seq_id; 9270 __le16 resp_len; 9271 __le16 manufacturer_id; 9272 __le16 device_id; 9273 __le32 sector_size; 9274 __le32 nvram_size; 9275 __le32 reserved_size; 9276 __le32 available_size; 9277 u8 nvm_cfg_ver_maj; 9278 u8 nvm_cfg_ver_min; 9279 u8 nvm_cfg_ver_upd; 9280 u8 flags; 9281 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9282 char pkg_name[16]; 9283 __le16 hwrm_fw_major; 9284 __le16 hwrm_fw_minor; 9285 __le16 hwrm_fw_build; 9286 __le16 hwrm_fw_patch; 9287 __le16 mgmt_fw_major; 9288 __le16 mgmt_fw_minor; 9289 __le16 mgmt_fw_build; 9290 __le16 mgmt_fw_patch; 9291 __le16 roce_fw_major; 9292 __le16 roce_fw_minor; 9293 __le16 roce_fw_build; 9294 __le16 roce_fw_patch; 9295 u8 unused_0[7]; 9296 u8 valid; 9297 }; 9298 9299 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9300 struct hwrm_nvm_mod_dir_entry_input { 9301 __le16 req_type; 9302 __le16 cmpl_ring; 9303 __le16 seq_id; 9304 __le16 target_id; 9305 __le64 resp_addr; 9306 __le32 enables; 9307 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9308 __le16 dir_idx; 9309 __le16 dir_ordinal; 9310 __le16 dir_ext; 9311 __le16 dir_attr; 9312 __le32 checksum; 9313 }; 9314 9315 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 9316 struct hwrm_nvm_mod_dir_entry_output { 9317 __le16 error_code; 9318 __le16 req_type; 9319 __le16 seq_id; 9320 __le16 resp_len; 9321 u8 unused_0[7]; 9322 u8 valid; 9323 }; 9324 9325 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 9326 struct hwrm_nvm_verify_update_input { 9327 __le16 req_type; 9328 __le16 cmpl_ring; 9329 __le16 seq_id; 9330 __le16 target_id; 9331 __le64 resp_addr; 9332 __le16 dir_type; 9333 __le16 dir_ordinal; 9334 __le16 dir_ext; 9335 u8 unused_0[2]; 9336 }; 9337 9338 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 9339 struct hwrm_nvm_verify_update_output { 9340 __le16 error_code; 9341 __le16 req_type; 9342 __le16 seq_id; 9343 __le16 resp_len; 9344 u8 unused_0[7]; 9345 u8 valid; 9346 }; 9347 9348 /* hwrm_nvm_install_update_input (size:192b/24B) */ 9349 struct hwrm_nvm_install_update_input { 9350 __le16 req_type; 9351 __le16 cmpl_ring; 9352 __le16 seq_id; 9353 __le16 target_id; 9354 __le64 resp_addr; 9355 __le32 install_type; 9356 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 9357 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 9358 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 9359 __le16 flags; 9360 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 9361 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 9362 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 9363 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 9364 u8 unused_0[2]; 9365 }; 9366 9367 /* hwrm_nvm_install_update_output (size:192b/24B) */ 9368 struct hwrm_nvm_install_update_output { 9369 __le16 error_code; 9370 __le16 req_type; 9371 __le16 seq_id; 9372 __le16 resp_len; 9373 __le64 installed_items; 9374 u8 result; 9375 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 9376 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 9377 u8 problem_item; 9378 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 9379 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 9380 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 9381 u8 reset_required; 9382 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 9383 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 9384 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 9385 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 9386 u8 unused_0[4]; 9387 u8 valid; 9388 }; 9389 9390 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 9391 struct hwrm_nvm_install_update_cmd_err { 9392 u8 code; 9393 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 9394 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9395 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 9396 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 9397 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 9398 u8 unused_0[7]; 9399 }; 9400 9401 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 9402 struct hwrm_nvm_get_variable_input { 9403 __le16 req_type; 9404 __le16 cmpl_ring; 9405 __le16 seq_id; 9406 __le16 target_id; 9407 __le64 resp_addr; 9408 __le64 dest_data_addr; 9409 __le16 data_len; 9410 __le16 option_num; 9411 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9412 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9413 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9414 __le16 dimensions; 9415 __le16 index_0; 9416 __le16 index_1; 9417 __le16 index_2; 9418 __le16 index_3; 9419 u8 flags; 9420 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 9421 u8 unused_0; 9422 }; 9423 9424 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 9425 struct hwrm_nvm_get_variable_output { 9426 __le16 error_code; 9427 __le16 req_type; 9428 __le16 seq_id; 9429 __le16 resp_len; 9430 __le16 data_len; 9431 __le16 option_num; 9432 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 9433 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 9434 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 9435 u8 unused_0[3]; 9436 u8 valid; 9437 }; 9438 9439 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 9440 struct hwrm_nvm_get_variable_cmd_err { 9441 u8 code; 9442 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9443 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9444 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9445 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 9446 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 9447 u8 unused_0[7]; 9448 }; 9449 9450 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 9451 struct hwrm_nvm_set_variable_input { 9452 __le16 req_type; 9453 __le16 cmpl_ring; 9454 __le16 seq_id; 9455 __le16 target_id; 9456 __le64 resp_addr; 9457 __le64 src_data_addr; 9458 __le16 data_len; 9459 __le16 option_num; 9460 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9461 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9462 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9463 __le16 dimensions; 9464 __le16 index_0; 9465 __le16 index_1; 9466 __le16 index_2; 9467 __le16 index_3; 9468 u8 flags; 9469 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 9470 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 9471 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 9472 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 9473 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 9474 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 9475 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 9476 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 9477 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 9478 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 9479 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 9480 u8 unused_0; 9481 }; 9482 9483 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 9484 struct hwrm_nvm_set_variable_output { 9485 __le16 error_code; 9486 __le16 req_type; 9487 __le16 seq_id; 9488 __le16 resp_len; 9489 u8 unused_0[7]; 9490 u8 valid; 9491 }; 9492 9493 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 9494 struct hwrm_nvm_set_variable_cmd_err { 9495 u8 code; 9496 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9497 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9498 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9499 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 9500 u8 unused_0[7]; 9501 }; 9502 9503 /* hwrm_selftest_qlist_input (size:128b/16B) */ 9504 struct hwrm_selftest_qlist_input { 9505 __le16 req_type; 9506 __le16 cmpl_ring; 9507 __le16 seq_id; 9508 __le16 target_id; 9509 __le64 resp_addr; 9510 }; 9511 9512 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 9513 struct hwrm_selftest_qlist_output { 9514 __le16 error_code; 9515 __le16 req_type; 9516 __le16 seq_id; 9517 __le16 resp_len; 9518 u8 num_tests; 9519 u8 available_tests; 9520 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 9521 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 9522 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 9523 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 9524 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 9525 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9526 u8 offline_tests; 9527 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 9528 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 9529 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 9530 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 9531 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 9532 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9533 u8 unused_0; 9534 __le16 test_timeout; 9535 u8 unused_1[2]; 9536 char test0_name[32]; 9537 char test1_name[32]; 9538 char test2_name[32]; 9539 char test3_name[32]; 9540 char test4_name[32]; 9541 char test5_name[32]; 9542 char test6_name[32]; 9543 char test7_name[32]; 9544 u8 eyescope_target_BER_support; 9545 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 9546 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 9547 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 9548 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 9549 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 9550 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 9551 u8 unused_2[6]; 9552 u8 valid; 9553 }; 9554 9555 /* hwrm_selftest_exec_input (size:192b/24B) */ 9556 struct hwrm_selftest_exec_input { 9557 __le16 req_type; 9558 __le16 cmpl_ring; 9559 __le16 seq_id; 9560 __le16 target_id; 9561 __le64 resp_addr; 9562 u8 flags; 9563 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 9564 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 9565 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 9566 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 9567 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 9568 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 9569 u8 unused_0[7]; 9570 }; 9571 9572 /* hwrm_selftest_exec_output (size:128b/16B) */ 9573 struct hwrm_selftest_exec_output { 9574 __le16 error_code; 9575 __le16 req_type; 9576 __le16 seq_id; 9577 __le16 resp_len; 9578 u8 requested_tests; 9579 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 9580 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 9581 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 9582 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 9583 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 9584 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 9585 u8 test_success; 9586 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 9587 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 9588 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 9589 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 9590 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 9591 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 9592 u8 unused_0[5]; 9593 u8 valid; 9594 }; 9595 9596 /* hwrm_selftest_irq_input (size:128b/16B) */ 9597 struct hwrm_selftest_irq_input { 9598 __le16 req_type; 9599 __le16 cmpl_ring; 9600 __le16 seq_id; 9601 __le16 target_id; 9602 __le64 resp_addr; 9603 }; 9604 9605 /* hwrm_selftest_irq_output (size:128b/16B) */ 9606 struct hwrm_selftest_irq_output { 9607 __le16 error_code; 9608 __le16 req_type; 9609 __le16 seq_id; 9610 __le16 resp_len; 9611 u8 unused_0[7]; 9612 u8 valid; 9613 }; 9614 9615 /* db_push_info (size:64b/8B) */ 9616 struct db_push_info { 9617 u32 push_size_push_index; 9618 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 9619 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 9620 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 9621 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 9622 u32 reserved32; 9623 }; 9624 9625 /* fw_status_reg (size:32b/4B) */ 9626 struct fw_status_reg { 9627 u32 fw_status; 9628 #define FW_STATUS_REG_CODE_MASK 0xffffUL 9629 #define FW_STATUS_REG_CODE_SFT 0 9630 #define FW_STATUS_REG_CODE_READY 0x8000UL 9631 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 9632 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 9633 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 9634 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 9635 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 9636 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 9637 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 9638 #define FW_STATUS_REG_RECOVERING 0x400000UL 9639 }; 9640 9641 /* hcomm_status (size:64b/8B) */ 9642 struct hcomm_status { 9643 u32 sig_ver; 9644 #define HCOMM_STATUS_VER_MASK 0xffUL 9645 #define HCOMM_STATUS_VER_SFT 0 9646 #define HCOMM_STATUS_VER_LATEST 0x1UL 9647 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 9648 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 9649 #define HCOMM_STATUS_SIGNATURE_SFT 8 9650 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 9651 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 9652 u32 fw_status_loc; 9653 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 9654 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 9655 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 9656 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 9657 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 9658 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 9659 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 9660 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 9661 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 9662 }; 9663 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 9664 9665 #endif /* _BNXT_HSI_H_ */ 9666