1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_HSI_H 12 #define BNXT_HSI_H 13 14 /* HSI and HWRM Specification 1.8.1 */ 15 #define HWRM_VERSION_MAJOR 1 16 #define HWRM_VERSION_MINOR 8 17 #define HWRM_VERSION_UPDATE 1 18 19 #define HWRM_VERSION_RSVD 4 /* non-zero means beta version */ 20 21 #define HWRM_VERSION_STR "1.8.1.4" 22 /* 23 * Following is the signature for HWRM message field that indicates not 24 * applicable (All F's). Need to cast it the size of the field if needed. 25 */ 26 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 27 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 28 #define HWRM_MAX_RESP_LEN (248) /* hwrm_selftest_qlist */ 29 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 30 #define HW_HASH_KEY_SIZE 40 31 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 32 33 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 34 struct eject_cmpl { 35 __le16 type; 36 #define EJECT_CMPL_TYPE_MASK 0x3fUL 37 #define EJECT_CMPL_TYPE_SFT 0 38 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 39 __le16 len; 40 __le32 opaque; 41 __le32 v; 42 #define EJECT_CMPL_V 0x1UL 43 __le32 unused_2; 44 }; 45 46 /* HWRM Completion Record (16 bytes) */ 47 struct hwrm_cmpl { 48 __le16 type; 49 #define CMPL_TYPE_MASK 0x3fUL 50 #define CMPL_TYPE_SFT 0 51 #define CMPL_TYPE_HWRM_DONE 0x20UL 52 __le16 sequence_id; 53 __le32 unused_1; 54 __le32 v; 55 #define CMPL_V 0x1UL 56 __le32 unused_3; 57 }; 58 59 /* HWRM Forwarded Request (16 bytes) */ 60 struct hwrm_fwd_req_cmpl { 61 __le16 req_len_type; 62 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 63 #define FWD_REQ_CMPL_TYPE_SFT 0 64 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 65 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 66 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 67 __le16 source_id; 68 __le32 unused_0; 69 __le32 req_buf_addr_v[2]; 70 #define FWD_REQ_CMPL_V 0x1UL 71 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 72 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 73 }; 74 75 /* HWRM Forwarded Response (16 bytes) */ 76 struct hwrm_fwd_resp_cmpl { 77 __le16 type; 78 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 79 #define FWD_RESP_CMPL_TYPE_SFT 0 80 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 81 __le16 source_id; 82 __le16 resp_len; 83 __le16 unused_1; 84 __le32 resp_buf_addr_v[2]; 85 #define FWD_RESP_CMPL_V 0x1UL 86 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 87 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 88 }; 89 90 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 91 struct hwrm_async_event_cmpl { 92 __le16 type; 93 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 94 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 95 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 96 __le16 event_id; 97 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 98 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 99 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 100 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 101 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 102 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 103 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 104 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 105 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 106 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 107 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 108 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 109 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 110 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 111 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 112 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 113 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 114 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 115 __le32 event_data2; 116 u8 opaque_v; 117 #define ASYNC_EVENT_CMPL_V 0x1UL 118 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 119 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 120 u8 timestamp_lo; 121 __le16 timestamp_hi; 122 __le32 event_data1; 123 }; 124 125 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 126 struct hwrm_async_event_cmpl_link_status_change { 127 __le16 type; 128 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 129 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 130 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 131 __le16 event_id; 132 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 133 __le32 event_data2; 134 u8 opaque_v; 135 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 136 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 137 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 138 u8 timestamp_lo; 139 __le16 timestamp_hi; 140 __le32 event_data1; 141 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 142 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 143 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 144 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 145 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 146 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 147 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 148 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 149 }; 150 151 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 152 struct hwrm_async_event_cmpl_link_mtu_change { 153 __le16 type; 154 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 155 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 156 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 157 __le16 event_id; 158 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 159 __le32 event_data2; 160 u8 opaque_v; 161 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 162 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 163 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 164 u8 timestamp_lo; 165 __le16 timestamp_hi; 166 __le32 event_data1; 167 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 168 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 169 }; 170 171 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 172 struct hwrm_async_event_cmpl_link_speed_change { 173 __le16 type; 174 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 175 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 176 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 177 __le16 event_id; 178 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 179 __le32 event_data2; 180 u8 opaque_v; 181 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 182 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 183 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 184 u8 timestamp_lo; 185 __le16 timestamp_hi; 186 __le32 event_data1; 187 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 188 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 189 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 190 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 191 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 192 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 193 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 194 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 195 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 196 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 197 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 198 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 199 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 200 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 201 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 202 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 203 }; 204 205 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 206 struct hwrm_async_event_cmpl_dcb_config_change { 207 __le16 type; 208 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 209 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 210 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 211 __le16 event_id; 212 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 213 __le32 event_data2; 214 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 215 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 216 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 217 u8 opaque_v; 218 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 219 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 220 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 221 u8 timestamp_lo; 222 __le16 timestamp_hi; 223 __le32 event_data1; 224 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 225 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 226 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 227 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 228 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 229 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 230 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 231 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 232 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 233 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 234 }; 235 236 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 237 struct hwrm_async_event_cmpl_port_conn_not_allowed { 238 __le16 type; 239 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 240 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 241 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 242 __le16 event_id; 243 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 244 __le32 event_data2; 245 u8 opaque_v; 246 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 247 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 248 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 249 u8 timestamp_lo; 250 __le16 timestamp_hi; 251 __le32 event_data1; 252 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 253 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 254 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 255 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 256 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 257 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 258 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 259 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 260 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 261 }; 262 263 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 264 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 265 __le16 type; 266 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 267 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 268 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 269 __le16 event_id; 270 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 271 __le32 event_data2; 272 u8 opaque_v; 273 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 274 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 275 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 276 u8 timestamp_lo; 277 __le16 timestamp_hi; 278 __le32 event_data1; 279 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 280 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 281 }; 282 283 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 284 struct hwrm_async_event_cmpl_link_speed_cfg_change { 285 __le16 type; 286 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 287 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 288 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 289 __le16 event_id; 290 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 291 __le32 event_data2; 292 u8 opaque_v; 293 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 294 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 295 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 296 u8 timestamp_lo; 297 __le16 timestamp_hi; 298 __le32 event_data1; 299 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 300 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 301 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 302 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 303 }; 304 305 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 306 struct hwrm_async_event_cmpl_func_drvr_unload { 307 __le16 type; 308 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 309 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 310 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 311 __le16 event_id; 312 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 313 __le32 event_data2; 314 u8 opaque_v; 315 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 316 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 317 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 318 u8 timestamp_lo; 319 __le16 timestamp_hi; 320 __le32 event_data1; 321 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 322 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 323 }; 324 325 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 326 struct hwrm_async_event_cmpl_func_drvr_load { 327 __le16 type; 328 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 329 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 330 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 331 __le16 event_id; 332 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 333 __le32 event_data2; 334 u8 opaque_v; 335 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 336 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 337 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 338 u8 timestamp_lo; 339 __le16 timestamp_hi; 340 __le32 event_data1; 341 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 342 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 343 }; 344 345 /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ 346 struct hwrm_async_event_cmpl_func_flr_proc_cmplt { 347 __le16 type; 348 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL 349 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 350 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 351 __le16 event_id; 352 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 353 __le32 event_data2; 354 u8 opaque_v; 355 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL 356 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL 357 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 358 u8 timestamp_lo; 359 __le16 timestamp_hi; 360 __le32 event_data1; 361 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 362 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 363 }; 364 365 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 366 struct hwrm_async_event_cmpl_pf_drvr_unload { 367 __le16 type; 368 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 369 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 370 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 371 __le16 event_id; 372 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 373 __le32 event_data2; 374 u8 opaque_v; 375 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 376 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 377 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 378 u8 timestamp_lo; 379 __le16 timestamp_hi; 380 __le32 event_data1; 381 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 382 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 383 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 384 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 385 }; 386 387 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 388 struct hwrm_async_event_cmpl_pf_drvr_load { 389 __le16 type; 390 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 391 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 392 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 393 __le16 event_id; 394 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 395 __le32 event_data2; 396 u8 opaque_v; 397 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 398 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 399 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 400 u8 timestamp_lo; 401 __le16 timestamp_hi; 402 __le32 event_data1; 403 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 404 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 405 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 406 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 407 }; 408 409 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 410 struct hwrm_async_event_cmpl_vf_flr { 411 __le16 type; 412 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 413 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 414 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 415 __le16 event_id; 416 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 417 __le32 event_data2; 418 u8 opaque_v; 419 #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 420 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 421 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 422 u8 timestamp_lo; 423 __le16 timestamp_hi; 424 __le32 event_data1; 425 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 426 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 427 }; 428 429 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 430 struct hwrm_async_event_cmpl_vf_mac_addr_change { 431 __le16 type; 432 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 433 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 434 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 435 __le16 event_id; 436 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 437 __le32 event_data2; 438 u8 opaque_v; 439 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 440 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 441 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 442 u8 timestamp_lo; 443 __le16 timestamp_hi; 444 __le32 event_data1; 445 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 446 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 447 }; 448 449 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 450 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 451 __le16 type; 452 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 453 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 454 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 455 __le16 event_id; 456 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 457 __le32 event_data2; 458 u8 opaque_v; 459 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 460 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 461 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 462 u8 timestamp_lo; 463 __le16 timestamp_hi; 464 __le32 event_data1; 465 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 466 }; 467 468 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 469 struct hwrm_async_event_cmpl_vf_cfg_change { 470 __le16 type; 471 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 472 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 473 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 474 __le16 event_id; 475 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 476 __le32 event_data2; 477 u8 opaque_v; 478 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 479 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 480 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 481 u8 timestamp_lo; 482 __le16 timestamp_hi; 483 __le32 event_data1; 484 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 485 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 486 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 487 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 488 }; 489 490 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 491 struct hwrm_async_event_cmpl_hwrm_error { 492 __le16 type; 493 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 494 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 495 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 496 __le16 event_id; 497 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 498 __le32 event_data2; 499 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 500 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 501 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 502 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 503 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 504 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 505 u8 opaque_v; 506 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 507 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 508 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 509 u8 timestamp_lo; 510 __le16 timestamp_hi; 511 __le32 event_data1; 512 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 513 }; 514 515 /* hwrm_ver_get */ 516 /* Input (24 bytes) */ 517 struct hwrm_ver_get_input { 518 __le16 req_type; 519 __le16 cmpl_ring; 520 __le16 seq_id; 521 __le16 target_id; 522 __le64 resp_addr; 523 u8 hwrm_intf_maj; 524 u8 hwrm_intf_min; 525 u8 hwrm_intf_upd; 526 u8 unused_0[5]; 527 }; 528 529 /* Output (128 bytes) */ 530 struct hwrm_ver_get_output { 531 __le16 error_code; 532 __le16 req_type; 533 __le16 seq_id; 534 __le16 resp_len; 535 u8 hwrm_intf_maj; 536 u8 hwrm_intf_min; 537 u8 hwrm_intf_upd; 538 u8 hwrm_intf_rsvd; 539 u8 hwrm_fw_maj; 540 u8 hwrm_fw_min; 541 u8 hwrm_fw_bld; 542 u8 hwrm_fw_rsvd; 543 u8 mgmt_fw_maj; 544 u8 mgmt_fw_min; 545 u8 mgmt_fw_bld; 546 u8 mgmt_fw_rsvd; 547 u8 netctrl_fw_maj; 548 u8 netctrl_fw_min; 549 u8 netctrl_fw_bld; 550 u8 netctrl_fw_rsvd; 551 __le32 dev_caps_cfg; 552 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 553 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 554 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 555 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 556 u8 roce_fw_maj; 557 u8 roce_fw_min; 558 u8 roce_fw_bld; 559 u8 roce_fw_rsvd; 560 char hwrm_fw_name[16]; 561 char mgmt_fw_name[16]; 562 char netctrl_fw_name[16]; 563 __le32 reserved2[4]; 564 char roce_fw_name[16]; 565 __le16 chip_num; 566 u8 chip_rev; 567 u8 chip_metal; 568 u8 chip_bond_id; 569 u8 chip_platform_type; 570 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 571 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 572 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 573 __le16 max_req_win_len; 574 __le16 max_resp_len; 575 __le16 def_req_timeout; 576 u8 init_pending; 577 #define VER_GET_RESP_INIT_PENDING_DEV_NOT_RDY 0x1UL 578 u8 unused_0; 579 u8 unused_1; 580 u8 valid; 581 }; 582 583 /* hwrm_func_reset */ 584 /* Input (24 bytes) */ 585 struct hwrm_func_reset_input { 586 __le16 req_type; 587 __le16 cmpl_ring; 588 __le16 seq_id; 589 __le16 target_id; 590 __le64 resp_addr; 591 __le32 enables; 592 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 593 __le16 vf_id; 594 u8 func_reset_level; 595 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 596 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 597 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 598 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 599 u8 unused_0; 600 }; 601 602 /* Output (16 bytes) */ 603 struct hwrm_func_reset_output { 604 __le16 error_code; 605 __le16 req_type; 606 __le16 seq_id; 607 __le16 resp_len; 608 __le32 unused_0; 609 u8 unused_1; 610 u8 unused_2; 611 u8 unused_3; 612 u8 valid; 613 }; 614 615 /* hwrm_func_getfid */ 616 /* Input (24 bytes) */ 617 struct hwrm_func_getfid_input { 618 __le16 req_type; 619 __le16 cmpl_ring; 620 __le16 seq_id; 621 __le16 target_id; 622 __le64 resp_addr; 623 __le32 enables; 624 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 625 __le16 pci_id; 626 __le16 unused_0; 627 }; 628 629 /* Output (16 bytes) */ 630 struct hwrm_func_getfid_output { 631 __le16 error_code; 632 __le16 req_type; 633 __le16 seq_id; 634 __le16 resp_len; 635 __le16 fid; 636 u8 unused_0; 637 u8 unused_1; 638 u8 unused_2; 639 u8 unused_3; 640 u8 unused_4; 641 u8 valid; 642 }; 643 644 /* hwrm_func_vf_alloc */ 645 /* Input (24 bytes) */ 646 struct hwrm_func_vf_alloc_input { 647 __le16 req_type; 648 __le16 cmpl_ring; 649 __le16 seq_id; 650 __le16 target_id; 651 __le64 resp_addr; 652 __le32 enables; 653 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 654 __le16 first_vf_id; 655 __le16 num_vfs; 656 }; 657 658 /* Output (16 bytes) */ 659 struct hwrm_func_vf_alloc_output { 660 __le16 error_code; 661 __le16 req_type; 662 __le16 seq_id; 663 __le16 resp_len; 664 __le16 first_vf_id; 665 u8 unused_0; 666 u8 unused_1; 667 u8 unused_2; 668 u8 unused_3; 669 u8 unused_4; 670 u8 valid; 671 }; 672 673 /* hwrm_func_vf_free */ 674 /* Input (24 bytes) */ 675 struct hwrm_func_vf_free_input { 676 __le16 req_type; 677 __le16 cmpl_ring; 678 __le16 seq_id; 679 __le16 target_id; 680 __le64 resp_addr; 681 __le32 enables; 682 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 683 __le16 first_vf_id; 684 __le16 num_vfs; 685 }; 686 687 /* Output (16 bytes) */ 688 struct hwrm_func_vf_free_output { 689 __le16 error_code; 690 __le16 req_type; 691 __le16 seq_id; 692 __le16 resp_len; 693 __le32 unused_0; 694 u8 unused_1; 695 u8 unused_2; 696 u8 unused_3; 697 u8 valid; 698 }; 699 700 /* hwrm_func_vf_cfg */ 701 /* Input (32 bytes) */ 702 struct hwrm_func_vf_cfg_input { 703 __le16 req_type; 704 __le16 cmpl_ring; 705 __le16 seq_id; 706 __le16 target_id; 707 __le64 resp_addr; 708 __le32 enables; 709 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 710 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 711 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 712 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 713 __le16 mtu; 714 __le16 guest_vlan; 715 __le16 async_event_cr; 716 u8 dflt_mac_addr[6]; 717 }; 718 719 /* Output (16 bytes) */ 720 struct hwrm_func_vf_cfg_output { 721 __le16 error_code; 722 __le16 req_type; 723 __le16 seq_id; 724 __le16 resp_len; 725 __le32 unused_0; 726 u8 unused_1; 727 u8 unused_2; 728 u8 unused_3; 729 u8 valid; 730 }; 731 732 /* hwrm_func_qcaps */ 733 /* Input (24 bytes) */ 734 struct hwrm_func_qcaps_input { 735 __le16 req_type; 736 __le16 cmpl_ring; 737 __le16 seq_id; 738 __le16 target_id; 739 __le64 resp_addr; 740 __le16 fid; 741 __le16 unused_0[3]; 742 }; 743 744 /* Output (80 bytes) */ 745 struct hwrm_func_qcaps_output { 746 __le16 error_code; 747 __le16 req_type; 748 __le16 seq_id; 749 __le16 resp_len; 750 __le16 fid; 751 __le16 port_id; 752 __le32 flags; 753 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 754 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 755 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 756 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 757 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 758 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 759 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 760 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 761 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 762 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 763 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 764 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 765 u8 mac_address[6]; 766 __le16 max_rsscos_ctx; 767 __le16 max_cmpl_rings; 768 __le16 max_tx_rings; 769 __le16 max_rx_rings; 770 __le16 max_l2_ctxs; 771 __le16 max_vnics; 772 __le16 first_vf_id; 773 __le16 max_vfs; 774 __le16 max_stat_ctx; 775 __le32 max_encap_records; 776 __le32 max_decap_records; 777 __le32 max_tx_em_flows; 778 __le32 max_tx_wm_flows; 779 __le32 max_rx_em_flows; 780 __le32 max_rx_wm_flows; 781 __le32 max_mcast_filters; 782 __le32 max_flow_id; 783 __le32 max_hw_ring_grps; 784 __le16 max_sp_tx_rings; 785 u8 unused_0; 786 u8 valid; 787 }; 788 789 /* hwrm_func_qcfg */ 790 /* Input (24 bytes) */ 791 struct hwrm_func_qcfg_input { 792 __le16 req_type; 793 __le16 cmpl_ring; 794 __le16 seq_id; 795 __le16 target_id; 796 __le64 resp_addr; 797 __le16 fid; 798 __le16 unused_0[3]; 799 }; 800 801 /* Output (72 bytes) */ 802 struct hwrm_func_qcfg_output { 803 __le16 error_code; 804 __le16 req_type; 805 __le16 seq_id; 806 __le16 resp_len; 807 __le16 fid; 808 __le16 port_id; 809 __le16 vlan; 810 __le16 flags; 811 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 812 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 813 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 814 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 815 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 816 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 817 u8 mac_address[6]; 818 __le16 pci_id; 819 __le16 alloc_rsscos_ctx; 820 __le16 alloc_cmpl_rings; 821 __le16 alloc_tx_rings; 822 __le16 alloc_rx_rings; 823 __le16 alloc_l2_ctx; 824 __le16 alloc_vnics; 825 __le16 mtu; 826 __le16 mru; 827 __le16 stat_ctx_id; 828 u8 port_partition_type; 829 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 830 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 831 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 832 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 833 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 834 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 835 u8 port_pf_cnt; 836 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 837 __le16 dflt_vnic_id; 838 u8 unused_0; 839 u8 unused_1; 840 __le32 min_bw; 841 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 842 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 843 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 844 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 845 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 846 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 847 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 848 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 849 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 850 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 851 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 852 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 853 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 854 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 855 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 856 __le32 max_bw; 857 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 858 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 859 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 860 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 861 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 862 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 863 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 864 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 865 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 866 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 867 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 868 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 869 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 870 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 871 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 872 u8 evb_mode; 873 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 874 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 875 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 876 u8 unused_2; 877 __le16 alloc_vfs; 878 __le32 alloc_mcast_filters; 879 __le32 alloc_hw_ring_grps; 880 __le16 alloc_sp_tx_rings; 881 u8 unused_3; 882 u8 valid; 883 }; 884 885 /* hwrm_func_vlan_cfg */ 886 /* Input (48 bytes) */ 887 struct hwrm_func_vlan_cfg_input { 888 __le16 req_type; 889 __le16 cmpl_ring; 890 __le16 seq_id; 891 __le16 target_id; 892 __le64 resp_addr; 893 __le16 fid; 894 u8 unused_0; 895 u8 unused_1; 896 __le32 enables; 897 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL 898 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL 899 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL 900 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL 901 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL 902 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL 903 __le16 stag_vid; 904 u8 stag_pcp; 905 u8 unused_2; 906 __be16 stag_tpid; 907 __le16 ctag_vid; 908 u8 ctag_pcp; 909 u8 unused_3; 910 __be16 ctag_tpid; 911 __le32 rsvd1; 912 __le32 rsvd2; 913 __le32 unused_4; 914 }; 915 916 /* Output (16 bytes) */ 917 struct hwrm_func_vlan_cfg_output { 918 __le16 error_code; 919 __le16 req_type; 920 __le16 seq_id; 921 __le16 resp_len; 922 __le32 unused_0; 923 u8 unused_1; 924 u8 unused_2; 925 u8 unused_3; 926 u8 valid; 927 }; 928 929 /* hwrm_func_cfg */ 930 /* Input (88 bytes) */ 931 struct hwrm_func_cfg_input { 932 __le16 req_type; 933 __le16 cmpl_ring; 934 __le16 seq_id; 935 __le16 target_id; 936 __le64 resp_addr; 937 __le16 fid; 938 u8 unused_0; 939 u8 unused_1; 940 __le32 flags; 941 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 942 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 943 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 944 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 945 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 946 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 947 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 948 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 949 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 950 __le32 enables; 951 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 952 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 953 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 954 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 955 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 956 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 957 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 958 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 959 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 960 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 961 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 962 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 963 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 964 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 965 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 966 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 967 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 968 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 969 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 970 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 971 __le16 mtu; 972 __le16 mru; 973 __le16 num_rsscos_ctxs; 974 __le16 num_cmpl_rings; 975 __le16 num_tx_rings; 976 __le16 num_rx_rings; 977 __le16 num_l2_ctxs; 978 __le16 num_vnics; 979 __le16 num_stat_ctxs; 980 __le16 num_hw_ring_grps; 981 u8 dflt_mac_addr[6]; 982 __le16 dflt_vlan; 983 __be32 dflt_ip_addr[4]; 984 __le32 min_bw; 985 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 986 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 987 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 988 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 989 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 990 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 991 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 992 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 993 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 994 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 995 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 996 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 997 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 998 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 999 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1000 __le32 max_bw; 1001 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1002 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1003 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1004 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1005 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1006 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1007 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1008 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1009 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1010 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1011 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1012 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1013 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1014 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1015 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1016 __le16 async_event_cr; 1017 u8 vlan_antispoof_mode; 1018 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1019 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1020 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1021 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1022 u8 allowed_vlan_pris; 1023 u8 evb_mode; 1024 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1025 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1026 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1027 u8 unused_2; 1028 __le16 num_mcast_filters; 1029 }; 1030 1031 /* Output (16 bytes) */ 1032 struct hwrm_func_cfg_output { 1033 __le16 error_code; 1034 __le16 req_type; 1035 __le16 seq_id; 1036 __le16 resp_len; 1037 __le32 unused_0; 1038 u8 unused_1; 1039 u8 unused_2; 1040 u8 unused_3; 1041 u8 valid; 1042 }; 1043 1044 /* hwrm_func_qstats */ 1045 /* Input (24 bytes) */ 1046 struct hwrm_func_qstats_input { 1047 __le16 req_type; 1048 __le16 cmpl_ring; 1049 __le16 seq_id; 1050 __le16 target_id; 1051 __le64 resp_addr; 1052 __le16 fid; 1053 __le16 unused_0[3]; 1054 }; 1055 1056 /* Output (176 bytes) */ 1057 struct hwrm_func_qstats_output { 1058 __le16 error_code; 1059 __le16 req_type; 1060 __le16 seq_id; 1061 __le16 resp_len; 1062 __le64 tx_ucast_pkts; 1063 __le64 tx_mcast_pkts; 1064 __le64 tx_bcast_pkts; 1065 __le64 tx_discard_pkts; 1066 __le64 tx_drop_pkts; 1067 __le64 tx_ucast_bytes; 1068 __le64 tx_mcast_bytes; 1069 __le64 tx_bcast_bytes; 1070 __le64 rx_ucast_pkts; 1071 __le64 rx_mcast_pkts; 1072 __le64 rx_bcast_pkts; 1073 __le64 rx_discard_pkts; 1074 __le64 rx_drop_pkts; 1075 __le64 rx_ucast_bytes; 1076 __le64 rx_mcast_bytes; 1077 __le64 rx_bcast_bytes; 1078 __le64 rx_agg_pkts; 1079 __le64 rx_agg_bytes; 1080 __le64 rx_agg_events; 1081 __le64 rx_agg_aborts; 1082 __le32 unused_0; 1083 u8 unused_1; 1084 u8 unused_2; 1085 u8 unused_3; 1086 u8 valid; 1087 }; 1088 1089 /* hwrm_func_clr_stats */ 1090 /* Input (24 bytes) */ 1091 struct hwrm_func_clr_stats_input { 1092 __le16 req_type; 1093 __le16 cmpl_ring; 1094 __le16 seq_id; 1095 __le16 target_id; 1096 __le64 resp_addr; 1097 __le16 fid; 1098 __le16 unused_0[3]; 1099 }; 1100 1101 /* Output (16 bytes) */ 1102 struct hwrm_func_clr_stats_output { 1103 __le16 error_code; 1104 __le16 req_type; 1105 __le16 seq_id; 1106 __le16 resp_len; 1107 __le32 unused_0; 1108 u8 unused_1; 1109 u8 unused_2; 1110 u8 unused_3; 1111 u8 valid; 1112 }; 1113 1114 /* hwrm_func_vf_resc_free */ 1115 /* Input (24 bytes) */ 1116 struct hwrm_func_vf_resc_free_input { 1117 __le16 req_type; 1118 __le16 cmpl_ring; 1119 __le16 seq_id; 1120 __le16 target_id; 1121 __le64 resp_addr; 1122 __le16 vf_id; 1123 __le16 unused_0[3]; 1124 }; 1125 1126 /* Output (16 bytes) */ 1127 struct hwrm_func_vf_resc_free_output { 1128 __le16 error_code; 1129 __le16 req_type; 1130 __le16 seq_id; 1131 __le16 resp_len; 1132 __le32 unused_0; 1133 u8 unused_1; 1134 u8 unused_2; 1135 u8 unused_3; 1136 u8 valid; 1137 }; 1138 1139 /* hwrm_func_vf_vnic_ids_query */ 1140 /* Input (32 bytes) */ 1141 struct hwrm_func_vf_vnic_ids_query_input { 1142 __le16 req_type; 1143 __le16 cmpl_ring; 1144 __le16 seq_id; 1145 __le16 target_id; 1146 __le64 resp_addr; 1147 __le16 vf_id; 1148 u8 unused_0; 1149 u8 unused_1; 1150 __le32 max_vnic_id_cnt; 1151 __le64 vnic_id_tbl_addr; 1152 }; 1153 1154 /* Output (16 bytes) */ 1155 struct hwrm_func_vf_vnic_ids_query_output { 1156 __le16 error_code; 1157 __le16 req_type; 1158 __le16 seq_id; 1159 __le16 resp_len; 1160 __le32 vnic_id_cnt; 1161 u8 unused_0; 1162 u8 unused_1; 1163 u8 unused_2; 1164 u8 valid; 1165 }; 1166 1167 /* hwrm_func_drv_rgtr */ 1168 /* Input (80 bytes) */ 1169 struct hwrm_func_drv_rgtr_input { 1170 __le16 req_type; 1171 __le16 cmpl_ring; 1172 __le16 seq_id; 1173 __le16 target_id; 1174 __le64 resp_addr; 1175 __le32 flags; 1176 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1177 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1178 __le32 enables; 1179 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1180 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1181 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1182 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1183 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1184 __le16 os_type; 1185 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1186 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1187 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1188 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1189 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1190 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1191 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1192 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1193 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1194 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1195 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1196 u8 ver_maj; 1197 u8 ver_min; 1198 u8 ver_upd; 1199 u8 unused_0; 1200 __le16 unused_1; 1201 __le32 timestamp; 1202 __le32 unused_2; 1203 __le32 vf_req_fwd[8]; 1204 __le32 async_event_fwd[8]; 1205 }; 1206 1207 /* Output (16 bytes) */ 1208 struct hwrm_func_drv_rgtr_output { 1209 __le16 error_code; 1210 __le16 req_type; 1211 __le16 seq_id; 1212 __le16 resp_len; 1213 __le32 unused_0; 1214 u8 unused_1; 1215 u8 unused_2; 1216 u8 unused_3; 1217 u8 valid; 1218 }; 1219 1220 /* hwrm_func_drv_unrgtr */ 1221 /* Input (24 bytes) */ 1222 struct hwrm_func_drv_unrgtr_input { 1223 __le16 req_type; 1224 __le16 cmpl_ring; 1225 __le16 seq_id; 1226 __le16 target_id; 1227 __le64 resp_addr; 1228 __le32 flags; 1229 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1230 __le32 unused_0; 1231 }; 1232 1233 /* Output (16 bytes) */ 1234 struct hwrm_func_drv_unrgtr_output { 1235 __le16 error_code; 1236 __le16 req_type; 1237 __le16 seq_id; 1238 __le16 resp_len; 1239 __le32 unused_0; 1240 u8 unused_1; 1241 u8 unused_2; 1242 u8 unused_3; 1243 u8 valid; 1244 }; 1245 1246 /* hwrm_func_buf_rgtr */ 1247 /* Input (128 bytes) */ 1248 struct hwrm_func_buf_rgtr_input { 1249 __le16 req_type; 1250 __le16 cmpl_ring; 1251 __le16 seq_id; 1252 __le16 target_id; 1253 __le64 resp_addr; 1254 __le32 enables; 1255 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1256 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1257 __le16 vf_id; 1258 __le16 req_buf_num_pages; 1259 __le16 req_buf_page_size; 1260 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1261 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1262 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1263 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1264 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1265 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1266 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1267 __le16 req_buf_len; 1268 __le16 resp_buf_len; 1269 u8 unused_0; 1270 u8 unused_1; 1271 __le64 req_buf_page_addr0; 1272 __le64 req_buf_page_addr1; 1273 __le64 req_buf_page_addr2; 1274 __le64 req_buf_page_addr3; 1275 __le64 req_buf_page_addr4; 1276 __le64 req_buf_page_addr5; 1277 __le64 req_buf_page_addr6; 1278 __le64 req_buf_page_addr7; 1279 __le64 req_buf_page_addr8; 1280 __le64 req_buf_page_addr9; 1281 __le64 error_buf_addr; 1282 __le64 resp_buf_addr; 1283 }; 1284 1285 /* Output (16 bytes) */ 1286 struct hwrm_func_buf_rgtr_output { 1287 __le16 error_code; 1288 __le16 req_type; 1289 __le16 seq_id; 1290 __le16 resp_len; 1291 __le32 unused_0; 1292 u8 unused_1; 1293 u8 unused_2; 1294 u8 unused_3; 1295 u8 valid; 1296 }; 1297 1298 /* hwrm_func_drv_qver */ 1299 /* Input (24 bytes) */ 1300 struct hwrm_func_drv_qver_input { 1301 __le16 req_type; 1302 __le16 cmpl_ring; 1303 __le16 seq_id; 1304 __le16 target_id; 1305 __le64 resp_addr; 1306 __le32 reserved; 1307 __le16 fid; 1308 __le16 unused_0; 1309 }; 1310 1311 /* Output (16 bytes) */ 1312 struct hwrm_func_drv_qver_output { 1313 __le16 error_code; 1314 __le16 req_type; 1315 __le16 seq_id; 1316 __le16 resp_len; 1317 __le16 os_type; 1318 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1319 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1320 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1321 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1322 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1323 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1324 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1325 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1326 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1327 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1328 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1329 u8 ver_maj; 1330 u8 ver_min; 1331 u8 ver_upd; 1332 u8 unused_0; 1333 u8 unused_1; 1334 u8 valid; 1335 }; 1336 1337 /* hwrm_port_phy_cfg */ 1338 /* Input (56 bytes) */ 1339 struct hwrm_port_phy_cfg_input { 1340 __le16 req_type; 1341 __le16 cmpl_ring; 1342 __le16 seq_id; 1343 __le16 target_id; 1344 __le64 resp_addr; 1345 __le32 flags; 1346 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1347 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1348 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1349 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1350 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1351 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1352 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1353 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1354 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1355 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1356 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1357 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1358 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1359 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1360 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1361 __le32 enables; 1362 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1363 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1364 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1365 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1366 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1367 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1368 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1369 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1370 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1371 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1372 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1373 __le16 port_id; 1374 __le16 force_link_speed; 1375 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1376 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1377 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1378 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1379 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1380 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1381 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1382 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1383 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1384 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1385 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1386 u8 auto_mode; 1387 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1388 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1389 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1390 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1391 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1392 u8 auto_duplex; 1393 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1394 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1395 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1396 u8 auto_pause; 1397 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1398 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1399 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1400 u8 unused_0; 1401 __le16 auto_link_speed; 1402 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1403 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1404 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1405 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1406 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1407 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1408 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1409 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1410 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1411 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1412 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1413 __le16 auto_link_speed_mask; 1414 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1415 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1416 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1417 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1418 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1419 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1420 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1421 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1422 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1423 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1424 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1425 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1426 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1427 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1428 u8 wirespeed; 1429 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1430 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1431 u8 lpbk; 1432 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1433 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1434 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1435 u8 force_pause; 1436 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1437 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1438 u8 unused_1; 1439 __le32 preemphasis; 1440 __le16 eee_link_speed_mask; 1441 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1442 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1443 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1444 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1445 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1446 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1447 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1448 u8 unused_2; 1449 u8 unused_3; 1450 __le32 tx_lpi_timer; 1451 __le32 unused_4; 1452 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1453 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1454 }; 1455 1456 /* Output (16 bytes) */ 1457 struct hwrm_port_phy_cfg_output { 1458 __le16 error_code; 1459 __le16 req_type; 1460 __le16 seq_id; 1461 __le16 resp_len; 1462 __le32 unused_0; 1463 u8 unused_1; 1464 u8 unused_2; 1465 u8 unused_3; 1466 u8 valid; 1467 }; 1468 1469 /* hwrm_port_phy_qcfg */ 1470 /* Input (24 bytes) */ 1471 struct hwrm_port_phy_qcfg_input { 1472 __le16 req_type; 1473 __le16 cmpl_ring; 1474 __le16 seq_id; 1475 __le16 target_id; 1476 __le64 resp_addr; 1477 __le16 port_id; 1478 __le16 unused_0[3]; 1479 }; 1480 1481 /* Output (96 bytes) */ 1482 struct hwrm_port_phy_qcfg_output { 1483 __le16 error_code; 1484 __le16 req_type; 1485 __le16 seq_id; 1486 __le16 resp_len; 1487 u8 link; 1488 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1489 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1490 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1491 u8 unused_0; 1492 __le16 link_speed; 1493 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1494 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1495 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1496 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1497 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1498 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1499 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1500 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1501 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1502 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1503 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1504 u8 duplex_cfg; 1505 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 1506 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 1507 u8 pause; 1508 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1509 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1510 __le16 support_speeds; 1511 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1512 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1513 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1514 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1515 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1516 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1517 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1518 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1519 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1520 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1521 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1522 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1523 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1524 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1525 __le16 force_link_speed; 1526 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1527 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1528 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1529 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1530 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1531 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1532 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1533 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1534 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1535 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1536 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1537 u8 auto_mode; 1538 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1539 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1540 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1541 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1542 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1543 u8 auto_pause; 1544 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1545 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1546 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1547 __le16 auto_link_speed; 1548 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1549 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1550 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1551 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1552 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1553 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1554 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1555 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1556 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1557 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1558 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1559 __le16 auto_link_speed_mask; 1560 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1561 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1562 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1563 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1564 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1565 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1566 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1567 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1568 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1569 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1570 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1571 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1572 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1573 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1574 u8 wirespeed; 1575 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1576 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1577 u8 lpbk; 1578 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1579 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1580 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1581 u8 force_pause; 1582 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1583 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1584 u8 module_status; 1585 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1586 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1587 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1588 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1589 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1590 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1591 __le32 preemphasis; 1592 u8 phy_maj; 1593 u8 phy_min; 1594 u8 phy_bld; 1595 u8 phy_type; 1596 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1597 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1598 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1599 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1600 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1601 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1602 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1603 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1604 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1605 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1606 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1607 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1608 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1609 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1610 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1611 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1612 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1613 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1614 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1615 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1616 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1617 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1618 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1619 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1620 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1621 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 1622 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 1623 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 1624 u8 media_type; 1625 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1626 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1627 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1628 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1629 u8 xcvr_pkg_type; 1630 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1631 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1632 u8 eee_config_phy_addr; 1633 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1634 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1635 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1636 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1637 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1638 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1639 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1640 u8 parallel_detect; 1641 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1642 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1643 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1644 __le16 link_partner_adv_speeds; 1645 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1646 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1647 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1648 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1649 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1650 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1651 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1652 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1653 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1654 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1655 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1656 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1657 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1658 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1659 u8 link_partner_adv_auto_mode; 1660 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1661 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1662 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1663 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1664 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1665 u8 link_partner_adv_pause; 1666 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1667 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1668 __le16 adv_eee_link_speed_mask; 1669 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1670 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1671 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1672 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1673 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1674 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1675 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1676 __le16 link_partner_adv_eee_link_speed_mask; 1677 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1678 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1679 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1680 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1681 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1682 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1683 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1684 __le32 xcvr_identifier_type_tx_lpi_timer; 1685 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1686 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1687 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1688 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1689 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1690 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1691 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1692 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1693 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1694 __le16 fec_cfg; 1695 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1696 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1697 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1698 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1699 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1700 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1701 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1702 u8 duplex_state; 1703 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 1704 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 1705 u8 unused_1; 1706 char phy_vendor_name[16]; 1707 char phy_vendor_partnumber[16]; 1708 __le32 unused_2; 1709 u8 unused_3; 1710 u8 unused_4; 1711 u8 unused_5; 1712 u8 valid; 1713 }; 1714 1715 /* hwrm_port_mac_cfg */ 1716 /* Input (40 bytes) */ 1717 struct hwrm_port_mac_cfg_input { 1718 __le16 req_type; 1719 __le16 cmpl_ring; 1720 __le16 seq_id; 1721 __le16 target_id; 1722 __le64 resp_addr; 1723 __le32 flags; 1724 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1725 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1726 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1727 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1728 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1729 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1730 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1731 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1732 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1733 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1734 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1735 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1736 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1737 __le32 enables; 1738 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1739 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1740 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1741 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1742 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1743 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1744 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1745 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1746 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1747 __le16 port_id; 1748 u8 ipg; 1749 u8 lpbk; 1750 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1751 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1752 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1753 u8 vlan_pri2cos_map_pri; 1754 u8 reserved1; 1755 u8 tunnel_pri2cos_map_pri; 1756 u8 dscp2pri_map_pri; 1757 __le16 rx_ts_capture_ptp_msg_type; 1758 __le16 tx_ts_capture_ptp_msg_type; 1759 u8 cos_field_cfg; 1760 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1761 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1762 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1763 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1764 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1765 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1766 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1767 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1768 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1769 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1770 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1771 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1772 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1773 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1774 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1775 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1776 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1777 u8 unused_0[3]; 1778 }; 1779 1780 /* Output (16 bytes) */ 1781 struct hwrm_port_mac_cfg_output { 1782 __le16 error_code; 1783 __le16 req_type; 1784 __le16 seq_id; 1785 __le16 resp_len; 1786 __le16 mru; 1787 __le16 mtu; 1788 u8 ipg; 1789 u8 lpbk; 1790 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1791 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1792 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1793 u8 unused_0; 1794 u8 valid; 1795 }; 1796 1797 /* hwrm_port_mac_ptp_qcfg */ 1798 /* Input (24 bytes) */ 1799 struct hwrm_port_mac_ptp_qcfg_input { 1800 __le16 req_type; 1801 __le16 cmpl_ring; 1802 __le16 seq_id; 1803 __le16 target_id; 1804 __le64 resp_addr; 1805 __le16 port_id; 1806 __le16 unused_0[3]; 1807 }; 1808 1809 /* Output (80 bytes) */ 1810 struct hwrm_port_mac_ptp_qcfg_output { 1811 __le16 error_code; 1812 __le16 req_type; 1813 __le16 seq_id; 1814 __le16 resp_len; 1815 u8 flags; 1816 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 1817 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 1818 u8 unused_0; 1819 __le16 unused_1; 1820 __le32 rx_ts_reg_off_lower; 1821 __le32 rx_ts_reg_off_upper; 1822 __le32 rx_ts_reg_off_seq_id; 1823 __le32 rx_ts_reg_off_src_id_0; 1824 __le32 rx_ts_reg_off_src_id_1; 1825 __le32 rx_ts_reg_off_src_id_2; 1826 __le32 rx_ts_reg_off_domain_id; 1827 __le32 rx_ts_reg_off_fifo; 1828 __le32 rx_ts_reg_off_fifo_adv; 1829 __le32 rx_ts_reg_off_granularity; 1830 __le32 tx_ts_reg_off_lower; 1831 __le32 tx_ts_reg_off_upper; 1832 __le32 tx_ts_reg_off_seq_id; 1833 __le32 tx_ts_reg_off_fifo; 1834 __le32 tx_ts_reg_off_granularity; 1835 __le32 unused_2; 1836 u8 unused_3; 1837 u8 unused_4; 1838 u8 unused_5; 1839 u8 valid; 1840 }; 1841 1842 /* hwrm_port_qstats */ 1843 /* Input (40 bytes) */ 1844 struct hwrm_port_qstats_input { 1845 __le16 req_type; 1846 __le16 cmpl_ring; 1847 __le16 seq_id; 1848 __le16 target_id; 1849 __le64 resp_addr; 1850 __le16 port_id; 1851 u8 unused_0; 1852 u8 unused_1; 1853 u8 unused_2[3]; 1854 u8 unused_3; 1855 __le64 tx_stat_host_addr; 1856 __le64 rx_stat_host_addr; 1857 }; 1858 1859 /* Output (16 bytes) */ 1860 struct hwrm_port_qstats_output { 1861 __le16 error_code; 1862 __le16 req_type; 1863 __le16 seq_id; 1864 __le16 resp_len; 1865 __le16 tx_stat_size; 1866 __le16 rx_stat_size; 1867 u8 unused_0; 1868 u8 unused_1; 1869 u8 unused_2; 1870 u8 valid; 1871 }; 1872 1873 /* hwrm_port_lpbk_qstats */ 1874 /* Input (16 bytes) */ 1875 struct hwrm_port_lpbk_qstats_input { 1876 __le16 req_type; 1877 __le16 cmpl_ring; 1878 __le16 seq_id; 1879 __le16 target_id; 1880 __le64 resp_addr; 1881 }; 1882 1883 /* Output (96 bytes) */ 1884 struct hwrm_port_lpbk_qstats_output { 1885 __le16 error_code; 1886 __le16 req_type; 1887 __le16 seq_id; 1888 __le16 resp_len; 1889 __le64 lpbk_ucast_frames; 1890 __le64 lpbk_mcast_frames; 1891 __le64 lpbk_bcast_frames; 1892 __le64 lpbk_ucast_bytes; 1893 __le64 lpbk_mcast_bytes; 1894 __le64 lpbk_bcast_bytes; 1895 __le64 tx_stat_discard; 1896 __le64 tx_stat_error; 1897 __le64 rx_stat_discard; 1898 __le64 rx_stat_error; 1899 __le32 unused_0; 1900 u8 unused_1; 1901 u8 unused_2; 1902 u8 unused_3; 1903 u8 valid; 1904 }; 1905 1906 /* hwrm_port_clr_stats */ 1907 /* Input (24 bytes) */ 1908 struct hwrm_port_clr_stats_input { 1909 __le16 req_type; 1910 __le16 cmpl_ring; 1911 __le16 seq_id; 1912 __le16 target_id; 1913 __le64 resp_addr; 1914 __le16 port_id; 1915 __le16 unused_0[3]; 1916 }; 1917 1918 /* Output (16 bytes) */ 1919 struct hwrm_port_clr_stats_output { 1920 __le16 error_code; 1921 __le16 req_type; 1922 __le16 seq_id; 1923 __le16 resp_len; 1924 __le32 unused_0; 1925 u8 unused_1; 1926 u8 unused_2; 1927 u8 unused_3; 1928 u8 valid; 1929 }; 1930 1931 /* hwrm_port_lpbk_clr_stats */ 1932 /* Input (16 bytes) */ 1933 struct hwrm_port_lpbk_clr_stats_input { 1934 __le16 req_type; 1935 __le16 cmpl_ring; 1936 __le16 seq_id; 1937 __le16 target_id; 1938 __le64 resp_addr; 1939 }; 1940 1941 /* Output (16 bytes) */ 1942 struct hwrm_port_lpbk_clr_stats_output { 1943 __le16 error_code; 1944 __le16 req_type; 1945 __le16 seq_id; 1946 __le16 resp_len; 1947 __le32 unused_0; 1948 u8 unused_1; 1949 u8 unused_2; 1950 u8 unused_3; 1951 u8 valid; 1952 }; 1953 1954 /* hwrm_port_phy_qcaps */ 1955 /* Input (24 bytes) */ 1956 struct hwrm_port_phy_qcaps_input { 1957 __le16 req_type; 1958 __le16 cmpl_ring; 1959 __le16 seq_id; 1960 __le16 target_id; 1961 __le64 resp_addr; 1962 __le16 port_id; 1963 __le16 unused_0[3]; 1964 }; 1965 1966 /* Output (24 bytes) */ 1967 struct hwrm_port_phy_qcaps_output { 1968 __le16 error_code; 1969 __le16 req_type; 1970 __le16 seq_id; 1971 __le16 resp_len; 1972 u8 flags; 1973 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 1974 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 1975 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 1976 u8 port_cnt; 1977 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 1978 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 1979 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 1980 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 1981 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 1982 __le16 supported_speeds_force_mode; 1983 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 1984 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 1985 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 1986 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 1987 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 1988 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 1989 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 1990 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 1991 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 1992 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 1993 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 1994 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 1995 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 1996 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 1997 __le16 supported_speeds_auto_mode; 1998 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 1999 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2000 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2001 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2002 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2003 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2004 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2005 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2006 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2007 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2008 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2009 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2010 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2011 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2012 __le16 supported_speeds_eee_mode; 2013 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2014 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2015 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2016 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2017 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2018 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2019 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2020 __le32 tx_lpi_timer_low; 2021 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2022 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2023 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2024 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2025 __le32 valid_tx_lpi_timer_high; 2026 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2027 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2028 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2029 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2030 }; 2031 2032 /* hwrm_port_phy_i2c_read */ 2033 /* Input (40 bytes) */ 2034 struct hwrm_port_phy_i2c_read_input { 2035 __le16 req_type; 2036 __le16 cmpl_ring; 2037 __le16 seq_id; 2038 __le16 target_id; 2039 __le64 resp_addr; 2040 __le32 flags; 2041 __le32 enables; 2042 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2043 __le16 port_id; 2044 u8 i2c_slave_addr; 2045 u8 unused_0; 2046 __le16 page_number; 2047 __le16 page_offset; 2048 u8 data_length; 2049 u8 unused_1[7]; 2050 }; 2051 2052 /* Output (80 bytes) */ 2053 struct hwrm_port_phy_i2c_read_output { 2054 __le16 error_code; 2055 __le16 req_type; 2056 __le16 seq_id; 2057 __le16 resp_len; 2058 __le32 data[16]; 2059 __le32 unused_0; 2060 u8 unused_1; 2061 u8 unused_2; 2062 u8 unused_3; 2063 u8 valid; 2064 }; 2065 2066 /* hwrm_port_led_cfg */ 2067 /* Input (64 bytes) */ 2068 struct hwrm_port_led_cfg_input { 2069 __le16 req_type; 2070 __le16 cmpl_ring; 2071 __le16 seq_id; 2072 __le16 target_id; 2073 __le64 resp_addr; 2074 __le32 enables; 2075 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2076 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2077 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2078 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2079 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2080 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2081 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2082 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2083 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2084 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2085 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2086 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2087 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2088 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2089 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2090 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2091 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2092 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2093 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2094 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2095 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2096 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2097 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2098 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2099 __le16 port_id; 2100 u8 num_leds; 2101 u8 rsvd; 2102 u8 led0_id; 2103 u8 led0_state; 2104 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2105 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2106 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2107 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2108 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2109 u8 led0_color; 2110 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2111 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2112 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2113 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2114 u8 unused_0; 2115 __le16 led0_blink_on; 2116 __le16 led0_blink_off; 2117 u8 led0_group_id; 2118 u8 rsvd0; 2119 u8 led1_id; 2120 u8 led1_state; 2121 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2122 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2123 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2124 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2125 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2126 u8 led1_color; 2127 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2128 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2129 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2130 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2131 u8 unused_1; 2132 __le16 led1_blink_on; 2133 __le16 led1_blink_off; 2134 u8 led1_group_id; 2135 u8 rsvd1; 2136 u8 led2_id; 2137 u8 led2_state; 2138 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2139 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2140 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2141 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2142 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2143 u8 led2_color; 2144 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2145 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2146 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2147 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2148 u8 unused_2; 2149 __le16 led2_blink_on; 2150 __le16 led2_blink_off; 2151 u8 led2_group_id; 2152 u8 rsvd2; 2153 u8 led3_id; 2154 u8 led3_state; 2155 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2156 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2157 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2158 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2159 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2160 u8 led3_color; 2161 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2162 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2163 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2164 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2165 u8 unused_3; 2166 __le16 led3_blink_on; 2167 __le16 led3_blink_off; 2168 u8 led3_group_id; 2169 u8 rsvd3; 2170 }; 2171 2172 /* Output (16 bytes) */ 2173 struct hwrm_port_led_cfg_output { 2174 __le16 error_code; 2175 __le16 req_type; 2176 __le16 seq_id; 2177 __le16 resp_len; 2178 __le32 unused_0; 2179 u8 unused_1; 2180 u8 unused_2; 2181 u8 unused_3; 2182 u8 valid; 2183 }; 2184 2185 /* hwrm_port_led_qcaps */ 2186 /* Input (24 bytes) */ 2187 struct hwrm_port_led_qcaps_input { 2188 __le16 req_type; 2189 __le16 cmpl_ring; 2190 __le16 seq_id; 2191 __le16 target_id; 2192 __le64 resp_addr; 2193 __le16 port_id; 2194 __le16 unused_0[3]; 2195 }; 2196 2197 /* Output (48 bytes) */ 2198 struct hwrm_port_led_qcaps_output { 2199 __le16 error_code; 2200 __le16 req_type; 2201 __le16 seq_id; 2202 __le16 resp_len; 2203 u8 num_leds; 2204 u8 unused_0[3]; 2205 u8 led0_id; 2206 u8 led0_type; 2207 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2208 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2209 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2210 u8 led0_group_id; 2211 u8 unused_1; 2212 __le16 led0_state_caps; 2213 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2214 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2215 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2216 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2217 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2218 __le16 led0_color_caps; 2219 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2220 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2221 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2222 u8 led1_id; 2223 u8 led1_type; 2224 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2225 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2226 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2227 u8 led1_group_id; 2228 u8 unused_2; 2229 __le16 led1_state_caps; 2230 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2231 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2232 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2233 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2234 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2235 __le16 led1_color_caps; 2236 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2237 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2238 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2239 u8 led2_id; 2240 u8 led2_type; 2241 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2242 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2243 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2244 u8 led2_group_id; 2245 u8 unused_3; 2246 __le16 led2_state_caps; 2247 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2248 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2249 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2250 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2251 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2252 __le16 led2_color_caps; 2253 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2254 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2255 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2256 u8 led3_id; 2257 u8 led3_type; 2258 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2259 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2260 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2261 u8 led3_group_id; 2262 u8 unused_4; 2263 __le16 led3_state_caps; 2264 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2265 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2266 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2267 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2268 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2269 __le16 led3_color_caps; 2270 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2271 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2272 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2273 u8 unused_5; 2274 u8 unused_6; 2275 u8 unused_7; 2276 u8 valid; 2277 }; 2278 2279 /* hwrm_queue_qportcfg */ 2280 /* Input (24 bytes) */ 2281 struct hwrm_queue_qportcfg_input { 2282 __le16 req_type; 2283 __le16 cmpl_ring; 2284 __le16 seq_id; 2285 __le16 target_id; 2286 __le64 resp_addr; 2287 __le32 flags; 2288 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2289 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2290 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2291 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2292 __le16 port_id; 2293 __le16 unused_0; 2294 }; 2295 2296 /* Output (32 bytes) */ 2297 struct hwrm_queue_qportcfg_output { 2298 __le16 error_code; 2299 __le16 req_type; 2300 __le16 seq_id; 2301 __le16 resp_len; 2302 u8 max_configurable_queues; 2303 u8 max_configurable_lossless_queues; 2304 u8 queue_cfg_allowed; 2305 u8 queue_cfg_info; 2306 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2307 u8 queue_pfcenable_cfg_allowed; 2308 u8 queue_pri2cos_cfg_allowed; 2309 u8 queue_cos2bw_cfg_allowed; 2310 u8 queue_id0; 2311 u8 queue_id0_service_profile; 2312 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2313 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2314 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2315 u8 queue_id1; 2316 u8 queue_id1_service_profile; 2317 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2318 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2319 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2320 u8 queue_id2; 2321 u8 queue_id2_service_profile; 2322 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2323 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2324 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2325 u8 queue_id3; 2326 u8 queue_id3_service_profile; 2327 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2328 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2329 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2330 u8 queue_id4; 2331 u8 queue_id4_service_profile; 2332 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2333 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2334 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2335 u8 queue_id5; 2336 u8 queue_id5_service_profile; 2337 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2338 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2339 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2340 u8 queue_id6; 2341 u8 queue_id6_service_profile; 2342 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2343 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2344 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2345 u8 queue_id7; 2346 u8 queue_id7_service_profile; 2347 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2348 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2349 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2350 u8 valid; 2351 }; 2352 2353 /* hwrm_queue_cfg */ 2354 /* Input (40 bytes) */ 2355 struct hwrm_queue_cfg_input { 2356 __le16 req_type; 2357 __le16 cmpl_ring; 2358 __le16 seq_id; 2359 __le16 target_id; 2360 __le64 resp_addr; 2361 __le32 flags; 2362 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2363 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2364 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2365 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2366 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2367 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2368 __le32 enables; 2369 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2370 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2371 __le32 queue_id; 2372 __le32 dflt_len; 2373 u8 service_profile; 2374 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2375 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2376 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2377 u8 unused_0[7]; 2378 }; 2379 2380 /* Output (16 bytes) */ 2381 struct hwrm_queue_cfg_output { 2382 __le16 error_code; 2383 __le16 req_type; 2384 __le16 seq_id; 2385 __le16 resp_len; 2386 __le32 unused_0; 2387 u8 unused_1; 2388 u8 unused_2; 2389 u8 unused_3; 2390 u8 valid; 2391 }; 2392 2393 /* hwrm_queue_pfcenable_qcfg */ 2394 /* Input (24 bytes) */ 2395 struct hwrm_queue_pfcenable_qcfg_input { 2396 __le16 req_type; 2397 __le16 cmpl_ring; 2398 __le16 seq_id; 2399 __le16 target_id; 2400 __le64 resp_addr; 2401 __le16 port_id; 2402 __le16 unused_0[3]; 2403 }; 2404 2405 /* Output (16 bytes) */ 2406 struct hwrm_queue_pfcenable_qcfg_output { 2407 __le16 error_code; 2408 __le16 req_type; 2409 __le16 seq_id; 2410 __le16 resp_len; 2411 __le32 flags; 2412 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2413 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2414 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2415 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2416 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2417 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2418 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2419 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2420 u8 unused_0; 2421 u8 unused_1; 2422 u8 unused_2; 2423 u8 valid; 2424 }; 2425 2426 /* hwrm_queue_pfcenable_cfg */ 2427 /* Input (24 bytes) */ 2428 struct hwrm_queue_pfcenable_cfg_input { 2429 __le16 req_type; 2430 __le16 cmpl_ring; 2431 __le16 seq_id; 2432 __le16 target_id; 2433 __le64 resp_addr; 2434 __le32 flags; 2435 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2436 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2437 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2438 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2439 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2440 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2441 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2442 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2443 __le16 port_id; 2444 __le16 unused_0; 2445 }; 2446 2447 /* Output (16 bytes) */ 2448 struct hwrm_queue_pfcenable_cfg_output { 2449 __le16 error_code; 2450 __le16 req_type; 2451 __le16 seq_id; 2452 __le16 resp_len; 2453 __le32 unused_0; 2454 u8 unused_1; 2455 u8 unused_2; 2456 u8 unused_3; 2457 u8 valid; 2458 }; 2459 2460 /* hwrm_queue_pri2cos_qcfg */ 2461 /* Input (24 bytes) */ 2462 struct hwrm_queue_pri2cos_qcfg_input { 2463 __le16 req_type; 2464 __le16 cmpl_ring; 2465 __le16 seq_id; 2466 __le16 target_id; 2467 __le64 resp_addr; 2468 __le32 flags; 2469 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2470 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2471 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2472 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2473 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2474 u8 port_id; 2475 u8 unused_0[3]; 2476 }; 2477 2478 /* Output (24 bytes) */ 2479 struct hwrm_queue_pri2cos_qcfg_output { 2480 __le16 error_code; 2481 __le16 req_type; 2482 __le16 seq_id; 2483 __le16 resp_len; 2484 u8 pri0_cos_queue_id; 2485 u8 pri1_cos_queue_id; 2486 u8 pri2_cos_queue_id; 2487 u8 pri3_cos_queue_id; 2488 u8 pri4_cos_queue_id; 2489 u8 pri5_cos_queue_id; 2490 u8 pri6_cos_queue_id; 2491 u8 pri7_cos_queue_id; 2492 u8 queue_cfg_info; 2493 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2494 u8 unused_0; 2495 __le16 unused_1; 2496 u8 unused_2; 2497 u8 unused_3; 2498 u8 unused_4; 2499 u8 valid; 2500 }; 2501 2502 /* hwrm_queue_pri2cos_cfg */ 2503 /* Input (40 bytes) */ 2504 struct hwrm_queue_pri2cos_cfg_input { 2505 __le16 req_type; 2506 __le16 cmpl_ring; 2507 __le16 seq_id; 2508 __le16 target_id; 2509 __le64 resp_addr; 2510 __le32 flags; 2511 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2512 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2513 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2514 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2515 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2516 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2517 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2518 __le32 enables; 2519 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2520 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2521 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2522 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2523 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2524 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2525 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2526 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2527 u8 port_id; 2528 u8 pri0_cos_queue_id; 2529 u8 pri1_cos_queue_id; 2530 u8 pri2_cos_queue_id; 2531 u8 pri3_cos_queue_id; 2532 u8 pri4_cos_queue_id; 2533 u8 pri5_cos_queue_id; 2534 u8 pri6_cos_queue_id; 2535 u8 pri7_cos_queue_id; 2536 u8 unused_0[7]; 2537 }; 2538 2539 /* Output (16 bytes) */ 2540 struct hwrm_queue_pri2cos_cfg_output { 2541 __le16 error_code; 2542 __le16 req_type; 2543 __le16 seq_id; 2544 __le16 resp_len; 2545 __le32 unused_0; 2546 u8 unused_1; 2547 u8 unused_2; 2548 u8 unused_3; 2549 u8 valid; 2550 }; 2551 2552 /* hwrm_queue_cos2bw_qcfg */ 2553 /* Input (24 bytes) */ 2554 struct hwrm_queue_cos2bw_qcfg_input { 2555 __le16 req_type; 2556 __le16 cmpl_ring; 2557 __le16 seq_id; 2558 __le16 target_id; 2559 __le64 resp_addr; 2560 __le16 port_id; 2561 __le16 unused_0[3]; 2562 }; 2563 2564 /* Output (112 bytes) */ 2565 struct hwrm_queue_cos2bw_qcfg_output { 2566 __le16 error_code; 2567 __le16 req_type; 2568 __le16 seq_id; 2569 __le16 resp_len; 2570 u8 queue_id0; 2571 u8 unused_0; 2572 __le16 unused_1; 2573 __le32 queue_id0_min_bw; 2574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2589 __le32 queue_id0_max_bw; 2590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2605 u8 queue_id0_tsa_assign; 2606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2610 u8 queue_id0_pri_lvl; 2611 u8 queue_id0_bw_weight; 2612 u8 queue_id1; 2613 __le32 queue_id1_min_bw; 2614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2629 __le32 queue_id1_max_bw; 2630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2645 u8 queue_id1_tsa_assign; 2646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2650 u8 queue_id1_pri_lvl; 2651 u8 queue_id1_bw_weight; 2652 u8 queue_id2; 2653 __le32 queue_id2_min_bw; 2654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2669 __le32 queue_id2_max_bw; 2670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2685 u8 queue_id2_tsa_assign; 2686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2690 u8 queue_id2_pri_lvl; 2691 u8 queue_id2_bw_weight; 2692 u8 queue_id3; 2693 __le32 queue_id3_min_bw; 2694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 2700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2709 __le32 queue_id3_max_bw; 2710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 2716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2725 u8 queue_id3_tsa_assign; 2726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2730 u8 queue_id3_pri_lvl; 2731 u8 queue_id3_bw_weight; 2732 u8 queue_id4; 2733 __le32 queue_id4_min_bw; 2734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 2740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2749 __le32 queue_id4_max_bw; 2750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 2753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 2754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 2755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 2756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2765 u8 queue_id4_tsa_assign; 2766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2770 u8 queue_id4_pri_lvl; 2771 u8 queue_id4_bw_weight; 2772 u8 queue_id5; 2773 __le32 queue_id5_min_bw; 2774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 2777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 2778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 2779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 2780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2789 __le32 queue_id5_max_bw; 2790 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2791 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2792 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 2793 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 2794 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 2795 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 2796 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2797 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2798 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2799 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2800 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2801 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2802 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2803 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2804 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2805 u8 queue_id5_tsa_assign; 2806 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2807 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2808 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2809 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2810 u8 queue_id5_pri_lvl; 2811 u8 queue_id5_bw_weight; 2812 u8 queue_id6; 2813 __le32 queue_id6_min_bw; 2814 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2815 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2816 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 2817 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 2818 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 2819 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 2820 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2821 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2822 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2823 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2824 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2825 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2826 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2827 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2828 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2829 __le32 queue_id6_max_bw; 2830 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2831 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2832 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 2833 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 2834 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 2835 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 2836 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2837 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2838 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2845 u8 queue_id6_tsa_assign; 2846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2850 u8 queue_id6_pri_lvl; 2851 u8 queue_id6_bw_weight; 2852 u8 queue_id7; 2853 __le32 queue_id7_min_bw; 2854 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 2857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 2858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 2859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 2860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2869 __le32 queue_id7_max_bw; 2870 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 2873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 2874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 2875 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 2876 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2877 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2878 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2885 u8 queue_id7_tsa_assign; 2886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2890 u8 queue_id7_pri_lvl; 2891 u8 queue_id7_bw_weight; 2892 u8 unused_2; 2893 u8 unused_3; 2894 u8 unused_4; 2895 u8 unused_5; 2896 u8 valid; 2897 }; 2898 2899 /* hwrm_queue_cos2bw_cfg */ 2900 /* Input (128 bytes) */ 2901 struct hwrm_queue_cos2bw_cfg_input { 2902 __le16 req_type; 2903 __le16 cmpl_ring; 2904 __le16 seq_id; 2905 __le16 target_id; 2906 __le64 resp_addr; 2907 __le32 flags; 2908 __le32 enables; 2909 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2910 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2911 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2912 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2913 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2914 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2915 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2916 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2917 __le16 port_id; 2918 u8 queue_id0; 2919 u8 unused_0; 2920 __le32 queue_id0_min_bw; 2921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 2927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2936 __le32 queue_id0_max_bw; 2937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 2943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2952 u8 queue_id0_tsa_assign; 2953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2957 u8 queue_id0_pri_lvl; 2958 u8 queue_id0_bw_weight; 2959 u8 queue_id1; 2960 __le32 queue_id1_min_bw; 2961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 2967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2976 __le32 queue_id1_max_bw; 2977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 2983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2992 u8 queue_id1_tsa_assign; 2993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2997 u8 queue_id1_pri_lvl; 2998 u8 queue_id1_bw_weight; 2999 u8 queue_id2; 3000 __le32 queue_id2_min_bw; 3001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3016 __le32 queue_id2_max_bw; 3017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3032 u8 queue_id2_tsa_assign; 3033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3037 u8 queue_id2_pri_lvl; 3038 u8 queue_id2_bw_weight; 3039 u8 queue_id3; 3040 __le32 queue_id3_min_bw; 3041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3056 __le32 queue_id3_max_bw; 3057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3072 u8 queue_id3_tsa_assign; 3073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3077 u8 queue_id3_pri_lvl; 3078 u8 queue_id3_bw_weight; 3079 u8 queue_id4; 3080 __le32 queue_id4_min_bw; 3081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 3087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3096 __le32 queue_id4_max_bw; 3097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3112 u8 queue_id4_tsa_assign; 3113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3117 u8 queue_id4_pri_lvl; 3118 u8 queue_id4_bw_weight; 3119 u8 queue_id5; 3120 __le32 queue_id5_min_bw; 3121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3136 __le32 queue_id5_max_bw; 3137 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3138 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3139 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3140 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3141 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3142 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3143 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3144 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3145 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3146 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3147 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3148 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3149 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3150 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3151 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3152 u8 queue_id5_tsa_assign; 3153 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3154 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3155 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3156 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3157 u8 queue_id5_pri_lvl; 3158 u8 queue_id5_bw_weight; 3159 u8 queue_id6; 3160 __le32 queue_id6_min_bw; 3161 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3162 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3163 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3164 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3165 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3166 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3167 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3168 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3169 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3170 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3171 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3172 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3173 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3174 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3175 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3176 __le32 queue_id6_max_bw; 3177 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3178 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3179 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3180 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3181 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3192 u8 queue_id6_tsa_assign; 3193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3197 u8 queue_id6_pri_lvl; 3198 u8 queue_id6_bw_weight; 3199 u8 queue_id7; 3200 __le32 queue_id7_min_bw; 3201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3213 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3216 __le32 queue_id7_max_bw; 3217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3218 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3219 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3220 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3221 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3232 u8 queue_id7_tsa_assign; 3233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3237 u8 queue_id7_pri_lvl; 3238 u8 queue_id7_bw_weight; 3239 u8 unused_1[5]; 3240 }; 3241 3242 /* Output (16 bytes) */ 3243 struct hwrm_queue_cos2bw_cfg_output { 3244 __le16 error_code; 3245 __le16 req_type; 3246 __le16 seq_id; 3247 __le16 resp_len; 3248 __le32 unused_0; 3249 u8 unused_1; 3250 u8 unused_2; 3251 u8 unused_3; 3252 u8 valid; 3253 }; 3254 3255 /* hwrm_queue_dscp_qcaps */ 3256 /* Input (24 bytes) */ 3257 struct hwrm_queue_dscp_qcaps_input { 3258 __le16 req_type; 3259 __le16 cmpl_ring; 3260 __le16 seq_id; 3261 __le16 target_id; 3262 __le64 resp_addr; 3263 u8 port_id; 3264 u8 unused_0[7]; 3265 }; 3266 3267 /* Output (16 bytes) */ 3268 struct hwrm_queue_dscp_qcaps_output { 3269 __le16 error_code; 3270 __le16 req_type; 3271 __le16 seq_id; 3272 __le16 resp_len; 3273 u8 num_dscp_bits; 3274 u8 unused_0; 3275 __le16 max_entries; 3276 u8 unused_1; 3277 u8 unused_2; 3278 u8 unused_3; 3279 u8 valid; 3280 }; 3281 3282 /* hwrm_queue_dscp2pri_qcfg */ 3283 /* Input (32 bytes) */ 3284 struct hwrm_queue_dscp2pri_qcfg_input { 3285 __le16 req_type; 3286 __le16 cmpl_ring; 3287 __le16 seq_id; 3288 __le16 target_id; 3289 __le64 resp_addr; 3290 __le64 dest_data_addr; 3291 u8 port_id; 3292 u8 unused_0; 3293 __le16 dest_data_buffer_size; 3294 __le32 unused_1; 3295 }; 3296 3297 /* Output (16 bytes) */ 3298 struct hwrm_queue_dscp2pri_qcfg_output { 3299 __le16 error_code; 3300 __le16 req_type; 3301 __le16 seq_id; 3302 __le16 resp_len; 3303 __le16 entry_cnt; 3304 u8 default_pri; 3305 u8 unused_0; 3306 u8 unused_1; 3307 u8 unused_2; 3308 u8 unused_3; 3309 u8 valid; 3310 }; 3311 3312 /* hwrm_queue_dscp2pri_cfg */ 3313 /* Input (40 bytes) */ 3314 struct hwrm_queue_dscp2pri_cfg_input { 3315 __le16 req_type; 3316 __le16 cmpl_ring; 3317 __le16 seq_id; 3318 __le16 target_id; 3319 __le64 resp_addr; 3320 __le64 src_data_addr; 3321 __le32 flags; 3322 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 3323 __le32 enables; 3324 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 3325 u8 port_id; 3326 u8 default_pri; 3327 __le16 entry_cnt; 3328 __le32 unused_0; 3329 }; 3330 3331 /* Output (16 bytes) */ 3332 struct hwrm_queue_dscp2pri_cfg_output { 3333 __le16 error_code; 3334 __le16 req_type; 3335 __le16 seq_id; 3336 __le16 resp_len; 3337 __le32 unused_0; 3338 u8 unused_1; 3339 u8 unused_2; 3340 u8 unused_3; 3341 u8 valid; 3342 }; 3343 3344 /* hwrm_vnic_alloc */ 3345 /* Input (24 bytes) */ 3346 struct hwrm_vnic_alloc_input { 3347 __le16 req_type; 3348 __le16 cmpl_ring; 3349 __le16 seq_id; 3350 __le16 target_id; 3351 __le64 resp_addr; 3352 __le32 flags; 3353 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3354 __le32 unused_0; 3355 }; 3356 3357 /* Output (16 bytes) */ 3358 struct hwrm_vnic_alloc_output { 3359 __le16 error_code; 3360 __le16 req_type; 3361 __le16 seq_id; 3362 __le16 resp_len; 3363 __le32 vnic_id; 3364 u8 unused_0; 3365 u8 unused_1; 3366 u8 unused_2; 3367 u8 valid; 3368 }; 3369 3370 /* hwrm_vnic_free */ 3371 /* Input (24 bytes) */ 3372 struct hwrm_vnic_free_input { 3373 __le16 req_type; 3374 __le16 cmpl_ring; 3375 __le16 seq_id; 3376 __le16 target_id; 3377 __le64 resp_addr; 3378 __le32 vnic_id; 3379 __le32 unused_0; 3380 }; 3381 3382 /* Output (16 bytes) */ 3383 struct hwrm_vnic_free_output { 3384 __le16 error_code; 3385 __le16 req_type; 3386 __le16 seq_id; 3387 __le16 resp_len; 3388 __le32 unused_0; 3389 u8 unused_1; 3390 u8 unused_2; 3391 u8 unused_3; 3392 u8 valid; 3393 }; 3394 3395 /* hwrm_vnic_cfg */ 3396 /* Input (40 bytes) */ 3397 struct hwrm_vnic_cfg_input { 3398 __le16 req_type; 3399 __le16 cmpl_ring; 3400 __le16 seq_id; 3401 __le16 target_id; 3402 __le64 resp_addr; 3403 __le32 flags; 3404 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3405 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3406 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3407 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3408 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3409 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3410 __le32 enables; 3411 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3412 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3413 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3414 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3415 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3416 __le16 vnic_id; 3417 __le16 dflt_ring_grp; 3418 __le16 rss_rule; 3419 __le16 cos_rule; 3420 __le16 lb_rule; 3421 __le16 mru; 3422 __le32 unused_0; 3423 }; 3424 3425 /* Output (16 bytes) */ 3426 struct hwrm_vnic_cfg_output { 3427 __le16 error_code; 3428 __le16 req_type; 3429 __le16 seq_id; 3430 __le16 resp_len; 3431 __le32 unused_0; 3432 u8 unused_1; 3433 u8 unused_2; 3434 u8 unused_3; 3435 u8 valid; 3436 }; 3437 3438 /* hwrm_vnic_qcaps */ 3439 /* Input (24 bytes) */ 3440 struct hwrm_vnic_qcaps_input { 3441 __le16 req_type; 3442 __le16 cmpl_ring; 3443 __le16 seq_id; 3444 __le16 target_id; 3445 __le64 resp_addr; 3446 __le32 enables; 3447 __le32 unused_0; 3448 }; 3449 3450 /* Output (24 bytes) */ 3451 struct hwrm_vnic_qcaps_output { 3452 __le16 error_code; 3453 __le16 req_type; 3454 __le16 seq_id; 3455 __le16 resp_len; 3456 __le16 mru; 3457 u8 unused_0; 3458 u8 unused_1; 3459 __le32 flags; 3460 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3461 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3462 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3463 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3464 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3465 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3466 __le32 unused_2; 3467 u8 unused_3; 3468 u8 unused_4; 3469 u8 unused_5; 3470 u8 valid; 3471 }; 3472 3473 /* hwrm_vnic_tpa_cfg */ 3474 /* Input (40 bytes) */ 3475 struct hwrm_vnic_tpa_cfg_input { 3476 __le16 req_type; 3477 __le16 cmpl_ring; 3478 __le16 seq_id; 3479 __le16 target_id; 3480 __le64 resp_addr; 3481 __le32 flags; 3482 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3483 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3484 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3485 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3486 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3487 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3488 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3489 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3490 __le32 enables; 3491 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3492 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3493 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3494 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3495 __le16 vnic_id; 3496 __le16 max_agg_segs; 3497 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3498 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3499 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3500 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3501 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3502 __le16 max_aggs; 3503 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3504 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3505 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3506 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3507 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3508 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3509 u8 unused_0; 3510 u8 unused_1; 3511 __le32 max_agg_timer; 3512 __le32 min_agg_len; 3513 }; 3514 3515 /* Output (16 bytes) */ 3516 struct hwrm_vnic_tpa_cfg_output { 3517 __le16 error_code; 3518 __le16 req_type; 3519 __le16 seq_id; 3520 __le16 resp_len; 3521 __le32 unused_0; 3522 u8 unused_1; 3523 u8 unused_2; 3524 u8 unused_3; 3525 u8 valid; 3526 }; 3527 3528 /* hwrm_vnic_rss_cfg */ 3529 /* Input (48 bytes) */ 3530 struct hwrm_vnic_rss_cfg_input { 3531 __le16 req_type; 3532 __le16 cmpl_ring; 3533 __le16 seq_id; 3534 __le16 target_id; 3535 __le64 resp_addr; 3536 __le32 hash_type; 3537 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3538 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3539 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3540 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3541 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3542 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3543 __le32 unused_0; 3544 __le64 ring_grp_tbl_addr; 3545 __le64 hash_key_tbl_addr; 3546 __le16 rss_ctx_idx; 3547 __le16 unused_1[3]; 3548 }; 3549 3550 /* Output (16 bytes) */ 3551 struct hwrm_vnic_rss_cfg_output { 3552 __le16 error_code; 3553 __le16 req_type; 3554 __le16 seq_id; 3555 __le16 resp_len; 3556 __le32 unused_0; 3557 u8 unused_1; 3558 u8 unused_2; 3559 u8 unused_3; 3560 u8 valid; 3561 }; 3562 3563 /* hwrm_vnic_plcmodes_cfg */ 3564 /* Input (40 bytes) */ 3565 struct hwrm_vnic_plcmodes_cfg_input { 3566 __le16 req_type; 3567 __le16 cmpl_ring; 3568 __le16 seq_id; 3569 __le16 target_id; 3570 __le64 resp_addr; 3571 __le32 flags; 3572 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3573 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3574 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3575 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3576 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3577 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3578 __le32 enables; 3579 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3580 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3581 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3582 __le32 vnic_id; 3583 __le16 jumbo_thresh; 3584 __le16 hds_offset; 3585 __le16 hds_threshold; 3586 __le16 unused_0[3]; 3587 }; 3588 3589 /* Output (16 bytes) */ 3590 struct hwrm_vnic_plcmodes_cfg_output { 3591 __le16 error_code; 3592 __le16 req_type; 3593 __le16 seq_id; 3594 __le16 resp_len; 3595 __le32 unused_0; 3596 u8 unused_1; 3597 u8 unused_2; 3598 u8 unused_3; 3599 u8 valid; 3600 }; 3601 3602 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 3603 /* Input (16 bytes) */ 3604 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3605 __le16 req_type; 3606 __le16 cmpl_ring; 3607 __le16 seq_id; 3608 __le16 target_id; 3609 __le64 resp_addr; 3610 }; 3611 3612 /* Output (16 bytes) */ 3613 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3614 __le16 error_code; 3615 __le16 req_type; 3616 __le16 seq_id; 3617 __le16 resp_len; 3618 __le16 rss_cos_lb_ctx_id; 3619 u8 unused_0; 3620 u8 unused_1; 3621 u8 unused_2; 3622 u8 unused_3; 3623 u8 unused_4; 3624 u8 valid; 3625 }; 3626 3627 /* hwrm_vnic_rss_cos_lb_ctx_free */ 3628 /* Input (24 bytes) */ 3629 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3630 __le16 req_type; 3631 __le16 cmpl_ring; 3632 __le16 seq_id; 3633 __le16 target_id; 3634 __le64 resp_addr; 3635 __le16 rss_cos_lb_ctx_id; 3636 __le16 unused_0[3]; 3637 }; 3638 3639 /* Output (16 bytes) */ 3640 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3641 __le16 error_code; 3642 __le16 req_type; 3643 __le16 seq_id; 3644 __le16 resp_len; 3645 __le32 unused_0; 3646 u8 unused_1; 3647 u8 unused_2; 3648 u8 unused_3; 3649 u8 valid; 3650 }; 3651 3652 /* hwrm_ring_alloc */ 3653 /* Input (80 bytes) */ 3654 struct hwrm_ring_alloc_input { 3655 __le16 req_type; 3656 __le16 cmpl_ring; 3657 __le16 seq_id; 3658 __le16 target_id; 3659 __le64 resp_addr; 3660 __le32 enables; 3661 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 3662 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3663 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 3664 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3665 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 3666 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3667 u8 ring_type; 3668 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3669 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3670 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3671 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3672 u8 unused_0; 3673 __le16 unused_1; 3674 __le64 page_tbl_addr; 3675 __le32 fbo; 3676 u8 page_size; 3677 u8 page_tbl_depth; 3678 u8 unused_2; 3679 u8 unused_3; 3680 __le32 length; 3681 __le16 logical_id; 3682 __le16 cmpl_ring_id; 3683 __le16 queue_id; 3684 u8 unused_4; 3685 u8 unused_5; 3686 __le32 reserved1; 3687 __le16 ring_arb_cfg; 3688 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3689 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3690 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3691 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3692 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3693 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3694 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3695 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3696 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3697 u8 unused_6; 3698 u8 unused_7; 3699 __le32 reserved3; 3700 __le32 stat_ctx_id; 3701 __le32 reserved4; 3702 __le32 max_bw; 3703 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3704 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3705 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3706 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3707 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3708 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3709 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3710 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3711 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3712 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3713 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3714 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3715 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3716 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3717 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3718 u8 int_mode; 3719 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3720 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3721 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3722 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3723 u8 unused_8[3]; 3724 }; 3725 3726 /* Output (16 bytes) */ 3727 struct hwrm_ring_alloc_output { 3728 __le16 error_code; 3729 __le16 req_type; 3730 __le16 seq_id; 3731 __le16 resp_len; 3732 __le16 ring_id; 3733 __le16 logical_ring_id; 3734 u8 unused_0; 3735 u8 unused_1; 3736 u8 unused_2; 3737 u8 valid; 3738 }; 3739 3740 /* hwrm_ring_free */ 3741 /* Input (24 bytes) */ 3742 struct hwrm_ring_free_input { 3743 __le16 req_type; 3744 __le16 cmpl_ring; 3745 __le16 seq_id; 3746 __le16 target_id; 3747 __le64 resp_addr; 3748 u8 ring_type; 3749 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3750 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3751 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3752 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3753 u8 unused_0; 3754 __le16 ring_id; 3755 __le32 unused_1; 3756 }; 3757 3758 /* Output (16 bytes) */ 3759 struct hwrm_ring_free_output { 3760 __le16 error_code; 3761 __le16 req_type; 3762 __le16 seq_id; 3763 __le16 resp_len; 3764 __le32 unused_0; 3765 u8 unused_1; 3766 u8 unused_2; 3767 u8 unused_3; 3768 u8 valid; 3769 }; 3770 3771 /* hwrm_ring_cmpl_ring_qaggint_params */ 3772 /* Input (24 bytes) */ 3773 struct hwrm_ring_cmpl_ring_qaggint_params_input { 3774 __le16 req_type; 3775 __le16 cmpl_ring; 3776 __le16 seq_id; 3777 __le16 target_id; 3778 __le64 resp_addr; 3779 __le16 ring_id; 3780 __le16 unused_0[3]; 3781 }; 3782 3783 /* Output (32 bytes) */ 3784 struct hwrm_ring_cmpl_ring_qaggint_params_output { 3785 __le16 error_code; 3786 __le16 req_type; 3787 __le16 seq_id; 3788 __le16 resp_len; 3789 __le16 flags; 3790 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3791 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3792 __le16 num_cmpl_dma_aggr; 3793 __le16 num_cmpl_dma_aggr_during_int; 3794 __le16 cmpl_aggr_dma_tmr; 3795 __le16 cmpl_aggr_dma_tmr_during_int; 3796 __le16 int_lat_tmr_min; 3797 __le16 int_lat_tmr_max; 3798 __le16 num_cmpl_aggr_int; 3799 __le32 unused_0; 3800 u8 unused_1; 3801 u8 unused_2; 3802 u8 unused_3; 3803 u8 valid; 3804 }; 3805 3806 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3807 /* Input (40 bytes) */ 3808 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3809 __le16 req_type; 3810 __le16 cmpl_ring; 3811 __le16 seq_id; 3812 __le16 target_id; 3813 __le64 resp_addr; 3814 __le16 ring_id; 3815 __le16 flags; 3816 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3817 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3818 __le16 num_cmpl_dma_aggr; 3819 __le16 num_cmpl_dma_aggr_during_int; 3820 __le16 cmpl_aggr_dma_tmr; 3821 __le16 cmpl_aggr_dma_tmr_during_int; 3822 __le16 int_lat_tmr_min; 3823 __le16 int_lat_tmr_max; 3824 __le16 num_cmpl_aggr_int; 3825 __le16 unused_0[3]; 3826 }; 3827 3828 /* Output (16 bytes) */ 3829 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3830 __le16 error_code; 3831 __le16 req_type; 3832 __le16 seq_id; 3833 __le16 resp_len; 3834 __le32 unused_0; 3835 u8 unused_1; 3836 u8 unused_2; 3837 u8 unused_3; 3838 u8 valid; 3839 }; 3840 3841 /* hwrm_ring_reset */ 3842 /* Input (24 bytes) */ 3843 struct hwrm_ring_reset_input { 3844 __le16 req_type; 3845 __le16 cmpl_ring; 3846 __le16 seq_id; 3847 __le16 target_id; 3848 __le64 resp_addr; 3849 u8 ring_type; 3850 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 3851 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3852 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3853 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3854 u8 unused_0; 3855 __le16 ring_id; 3856 __le32 unused_1; 3857 }; 3858 3859 /* Output (16 bytes) */ 3860 struct hwrm_ring_reset_output { 3861 __le16 error_code; 3862 __le16 req_type; 3863 __le16 seq_id; 3864 __le16 resp_len; 3865 __le32 unused_0; 3866 u8 unused_1; 3867 u8 unused_2; 3868 u8 unused_3; 3869 u8 valid; 3870 }; 3871 3872 /* hwrm_ring_grp_alloc */ 3873 /* Input (24 bytes) */ 3874 struct hwrm_ring_grp_alloc_input { 3875 __le16 req_type; 3876 __le16 cmpl_ring; 3877 __le16 seq_id; 3878 __le16 target_id; 3879 __le64 resp_addr; 3880 __le16 cr; 3881 __le16 rr; 3882 __le16 ar; 3883 __le16 sc; 3884 }; 3885 3886 /* Output (16 bytes) */ 3887 struct hwrm_ring_grp_alloc_output { 3888 __le16 error_code; 3889 __le16 req_type; 3890 __le16 seq_id; 3891 __le16 resp_len; 3892 __le32 ring_group_id; 3893 u8 unused_0; 3894 u8 unused_1; 3895 u8 unused_2; 3896 u8 valid; 3897 }; 3898 3899 /* hwrm_ring_grp_free */ 3900 /* Input (24 bytes) */ 3901 struct hwrm_ring_grp_free_input { 3902 __le16 req_type; 3903 __le16 cmpl_ring; 3904 __le16 seq_id; 3905 __le16 target_id; 3906 __le64 resp_addr; 3907 __le32 ring_group_id; 3908 __le32 unused_0; 3909 }; 3910 3911 /* Output (16 bytes) */ 3912 struct hwrm_ring_grp_free_output { 3913 __le16 error_code; 3914 __le16 req_type; 3915 __le16 seq_id; 3916 __le16 resp_len; 3917 __le32 unused_0; 3918 u8 unused_1; 3919 u8 unused_2; 3920 u8 unused_3; 3921 u8 valid; 3922 }; 3923 3924 /* hwrm_cfa_l2_filter_alloc */ 3925 /* Input (96 bytes) */ 3926 struct hwrm_cfa_l2_filter_alloc_input { 3927 __le16 req_type; 3928 __le16 cmpl_ring; 3929 __le16 seq_id; 3930 __le16 target_id; 3931 __le64 resp_addr; 3932 __le32 flags; 3933 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3934 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3935 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3936 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3937 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3938 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3939 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3940 __le32 enables; 3941 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3942 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3943 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3944 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3945 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3946 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3947 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3948 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3949 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3950 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3951 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3952 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3953 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3954 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3955 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3956 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3957 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3958 u8 l2_addr[6]; 3959 u8 unused_0; 3960 u8 unused_1; 3961 u8 l2_addr_mask[6]; 3962 __le16 l2_ovlan; 3963 __le16 l2_ovlan_mask; 3964 __le16 l2_ivlan; 3965 __le16 l2_ivlan_mask; 3966 u8 unused_2; 3967 u8 unused_3; 3968 u8 t_l2_addr[6]; 3969 u8 unused_4; 3970 u8 unused_5; 3971 u8 t_l2_addr_mask[6]; 3972 __le16 t_l2_ovlan; 3973 __le16 t_l2_ovlan_mask; 3974 __le16 t_l2_ivlan; 3975 __le16 t_l2_ivlan_mask; 3976 u8 src_type; 3977 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3978 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3979 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3980 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3981 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3982 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3983 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3984 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3985 u8 unused_6; 3986 __le32 src_id; 3987 u8 tunnel_type; 3988 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3989 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3990 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3991 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3992 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3993 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3994 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3995 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3996 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3997 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3998 u8 unused_7; 3999 __le16 dst_id; 4000 __le16 mirror_vnic_id; 4001 u8 pri_hint; 4002 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4003 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 4004 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 4005 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4006 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4007 u8 unused_8; 4008 __le32 unused_9; 4009 __le64 l2_filter_id_hint; 4010 }; 4011 4012 /* Output (24 bytes) */ 4013 struct hwrm_cfa_l2_filter_alloc_output { 4014 __le16 error_code; 4015 __le16 req_type; 4016 __le16 seq_id; 4017 __le16 resp_len; 4018 __le64 l2_filter_id; 4019 __le32 flow_id; 4020 u8 unused_0; 4021 u8 unused_1; 4022 u8 unused_2; 4023 u8 valid; 4024 }; 4025 4026 /* hwrm_cfa_l2_filter_free */ 4027 /* Input (24 bytes) */ 4028 struct hwrm_cfa_l2_filter_free_input { 4029 __le16 req_type; 4030 __le16 cmpl_ring; 4031 __le16 seq_id; 4032 __le16 target_id; 4033 __le64 resp_addr; 4034 __le64 l2_filter_id; 4035 }; 4036 4037 /* Output (16 bytes) */ 4038 struct hwrm_cfa_l2_filter_free_output { 4039 __le16 error_code; 4040 __le16 req_type; 4041 __le16 seq_id; 4042 __le16 resp_len; 4043 __le32 unused_0; 4044 u8 unused_1; 4045 u8 unused_2; 4046 u8 unused_3; 4047 u8 valid; 4048 }; 4049 4050 /* hwrm_cfa_l2_filter_cfg */ 4051 /* Input (40 bytes) */ 4052 struct hwrm_cfa_l2_filter_cfg_input { 4053 __le16 req_type; 4054 __le16 cmpl_ring; 4055 __le16 seq_id; 4056 __le16 target_id; 4057 __le64 resp_addr; 4058 __le32 flags; 4059 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 4060 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 4061 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 4062 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 4063 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 4064 __le32 enables; 4065 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 4066 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4067 __le64 l2_filter_id; 4068 __le32 dst_id; 4069 __le32 new_mirror_vnic_id; 4070 }; 4071 4072 /* Output (16 bytes) */ 4073 struct hwrm_cfa_l2_filter_cfg_output { 4074 __le16 error_code; 4075 __le16 req_type; 4076 __le16 seq_id; 4077 __le16 resp_len; 4078 __le32 unused_0; 4079 u8 unused_1; 4080 u8 unused_2; 4081 u8 unused_3; 4082 u8 valid; 4083 }; 4084 4085 /* hwrm_cfa_l2_set_rx_mask */ 4086 /* Input (56 bytes) */ 4087 struct hwrm_cfa_l2_set_rx_mask_input { 4088 __le16 req_type; 4089 __le16 cmpl_ring; 4090 __le16 seq_id; 4091 __le16 target_id; 4092 __le64 resp_addr; 4093 __le32 vnic_id; 4094 __le32 mask; 4095 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 4096 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 4097 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 4098 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 4099 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 4100 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 4101 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 4102 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 4103 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 4104 __le64 mc_tbl_addr; 4105 __le32 num_mc_entries; 4106 __le32 unused_0; 4107 __le64 vlan_tag_tbl_addr; 4108 __le32 num_vlan_tags; 4109 __le32 unused_1; 4110 }; 4111 4112 /* Output (16 bytes) */ 4113 struct hwrm_cfa_l2_set_rx_mask_output { 4114 __le16 error_code; 4115 __le16 req_type; 4116 __le16 seq_id; 4117 __le16 resp_len; 4118 __le32 unused_0; 4119 u8 unused_1; 4120 u8 unused_2; 4121 u8 unused_3; 4122 u8 valid; 4123 }; 4124 4125 /* hwrm_cfa_tunnel_filter_alloc */ 4126 /* Input (88 bytes) */ 4127 struct hwrm_cfa_tunnel_filter_alloc_input { 4128 __le16 req_type; 4129 __le16 cmpl_ring; 4130 __le16 seq_id; 4131 __le16 target_id; 4132 __le64 resp_addr; 4133 __le32 flags; 4134 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4135 __le32 enables; 4136 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4137 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 4138 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 4139 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 4140 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 4141 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 4142 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 4143 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 4144 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 4145 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 4146 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 4147 __le64 l2_filter_id; 4148 u8 l2_addr[6]; 4149 __le16 l2_ivlan; 4150 __le32 l3_addr[4]; 4151 __le32 t_l3_addr[4]; 4152 u8 l3_addr_type; 4153 u8 t_l3_addr_type; 4154 u8 tunnel_type; 4155 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4156 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4157 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4158 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4159 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4160 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4161 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4162 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4163 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4164 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4165 u8 unused_0; 4166 __le32 vni; 4167 __le32 dst_vnic_id; 4168 __le32 mirror_vnic_id; 4169 }; 4170 4171 /* Output (24 bytes) */ 4172 struct hwrm_cfa_tunnel_filter_alloc_output { 4173 __le16 error_code; 4174 __le16 req_type; 4175 __le16 seq_id; 4176 __le16 resp_len; 4177 __le64 tunnel_filter_id; 4178 __le32 flow_id; 4179 u8 unused_0; 4180 u8 unused_1; 4181 u8 unused_2; 4182 u8 valid; 4183 }; 4184 4185 /* hwrm_cfa_tunnel_filter_free */ 4186 /* Input (24 bytes) */ 4187 struct hwrm_cfa_tunnel_filter_free_input { 4188 __le16 req_type; 4189 __le16 cmpl_ring; 4190 __le16 seq_id; 4191 __le16 target_id; 4192 __le64 resp_addr; 4193 __le64 tunnel_filter_id; 4194 }; 4195 4196 /* Output (16 bytes) */ 4197 struct hwrm_cfa_tunnel_filter_free_output { 4198 __le16 error_code; 4199 __le16 req_type; 4200 __le16 seq_id; 4201 __le16 resp_len; 4202 __le32 unused_0; 4203 u8 unused_1; 4204 u8 unused_2; 4205 u8 unused_3; 4206 u8 valid; 4207 }; 4208 4209 /* hwrm_cfa_encap_record_alloc */ 4210 /* Input (32 bytes) */ 4211 struct hwrm_cfa_encap_record_alloc_input { 4212 __le16 req_type; 4213 __le16 cmpl_ring; 4214 __le16 seq_id; 4215 __le16 target_id; 4216 __le64 resp_addr; 4217 __le32 flags; 4218 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4219 u8 encap_type; 4220 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4221 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4222 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4223 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4224 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4225 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4226 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4227 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4228 u8 unused_0; 4229 __le16 unused_1; 4230 __le32 encap_data[20]; 4231 }; 4232 4233 /* Output (16 bytes) */ 4234 struct hwrm_cfa_encap_record_alloc_output { 4235 __le16 error_code; 4236 __le16 req_type; 4237 __le16 seq_id; 4238 __le16 resp_len; 4239 __le32 encap_record_id; 4240 u8 unused_0; 4241 u8 unused_1; 4242 u8 unused_2; 4243 u8 valid; 4244 }; 4245 4246 /* hwrm_cfa_encap_record_free */ 4247 /* Input (24 bytes) */ 4248 struct hwrm_cfa_encap_record_free_input { 4249 __le16 req_type; 4250 __le16 cmpl_ring; 4251 __le16 seq_id; 4252 __le16 target_id; 4253 __le64 resp_addr; 4254 __le32 encap_record_id; 4255 __le32 unused_0; 4256 }; 4257 4258 /* Output (16 bytes) */ 4259 struct hwrm_cfa_encap_record_free_output { 4260 __le16 error_code; 4261 __le16 req_type; 4262 __le16 seq_id; 4263 __le16 resp_len; 4264 __le32 unused_0; 4265 u8 unused_1; 4266 u8 unused_2; 4267 u8 unused_3; 4268 u8 valid; 4269 }; 4270 4271 /* hwrm_cfa_ntuple_filter_alloc */ 4272 /* Input (128 bytes) */ 4273 struct hwrm_cfa_ntuple_filter_alloc_input { 4274 __le16 req_type; 4275 __le16 cmpl_ring; 4276 __le16 seq_id; 4277 __le16 target_id; 4278 __le64 resp_addr; 4279 __le32 flags; 4280 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4281 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4282 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4283 __le32 enables; 4284 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4285 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4286 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4287 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4288 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4289 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4290 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4291 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4292 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4293 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4294 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4295 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4296 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4297 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4298 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4299 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4300 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4301 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4302 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4303 __le64 l2_filter_id; 4304 u8 src_macaddr[6]; 4305 __be16 ethertype; 4306 u8 ip_addr_type; 4307 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4308 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4309 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4310 u8 ip_protocol; 4311 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4312 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4313 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4314 __le16 dst_id; 4315 __le16 mirror_vnic_id; 4316 u8 tunnel_type; 4317 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4318 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4319 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4320 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4321 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4322 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4323 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4324 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4325 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4326 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4327 u8 pri_hint; 4328 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4329 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4330 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4331 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4332 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4333 __be32 src_ipaddr[4]; 4334 __be32 src_ipaddr_mask[4]; 4335 __be32 dst_ipaddr[4]; 4336 __be32 dst_ipaddr_mask[4]; 4337 __be16 src_port; 4338 __be16 src_port_mask; 4339 __be16 dst_port; 4340 __be16 dst_port_mask; 4341 __le64 ntuple_filter_id_hint; 4342 }; 4343 4344 /* Output (24 bytes) */ 4345 struct hwrm_cfa_ntuple_filter_alloc_output { 4346 __le16 error_code; 4347 __le16 req_type; 4348 __le16 seq_id; 4349 __le16 resp_len; 4350 __le64 ntuple_filter_id; 4351 __le32 flow_id; 4352 u8 unused_0; 4353 u8 unused_1; 4354 u8 unused_2; 4355 u8 valid; 4356 }; 4357 4358 /* hwrm_cfa_ntuple_filter_free */ 4359 /* Input (24 bytes) */ 4360 struct hwrm_cfa_ntuple_filter_free_input { 4361 __le16 req_type; 4362 __le16 cmpl_ring; 4363 __le16 seq_id; 4364 __le16 target_id; 4365 __le64 resp_addr; 4366 __le64 ntuple_filter_id; 4367 }; 4368 4369 /* Output (16 bytes) */ 4370 struct hwrm_cfa_ntuple_filter_free_output { 4371 __le16 error_code; 4372 __le16 req_type; 4373 __le16 seq_id; 4374 __le16 resp_len; 4375 __le32 unused_0; 4376 u8 unused_1; 4377 u8 unused_2; 4378 u8 unused_3; 4379 u8 valid; 4380 }; 4381 4382 /* hwrm_cfa_ntuple_filter_cfg */ 4383 /* Input (48 bytes) */ 4384 struct hwrm_cfa_ntuple_filter_cfg_input { 4385 __le16 req_type; 4386 __le16 cmpl_ring; 4387 __le16 seq_id; 4388 __le16 target_id; 4389 __le64 resp_addr; 4390 __le32 enables; 4391 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4392 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4393 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4394 __le32 unused_0; 4395 __le64 ntuple_filter_id; 4396 __le32 new_dst_id; 4397 __le32 new_mirror_vnic_id; 4398 __le16 new_meter_instance_id; 4399 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4400 __le16 unused_1[3]; 4401 }; 4402 4403 /* Output (16 bytes) */ 4404 struct hwrm_cfa_ntuple_filter_cfg_output { 4405 __le16 error_code; 4406 __le16 req_type; 4407 __le16 seq_id; 4408 __le16 resp_len; 4409 __le32 unused_0; 4410 u8 unused_1; 4411 u8 unused_2; 4412 u8 unused_3; 4413 u8 valid; 4414 }; 4415 4416 /* hwrm_cfa_flow_alloc */ 4417 /* Input (128 bytes) */ 4418 struct hwrm_cfa_flow_alloc_input { 4419 __le16 req_type; 4420 __le16 cmpl_ring; 4421 __le16 seq_id; 4422 __le16 target_id; 4423 __le64 resp_addr; 4424 __le16 flags; 4425 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 4426 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 4427 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 4428 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 4429 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 4430 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 4431 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 4432 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 4433 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 4434 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 4435 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 4436 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 4437 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 4438 __le16 src_fid; 4439 __le32 tunnel_handle; 4440 __le16 action_flags; 4441 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 4442 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 4443 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 4444 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 4445 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 4446 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 4447 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 4448 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 4449 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 4450 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 4451 __le16 dst_fid; 4452 __be16 l2_rewrite_vlan_tpid; 4453 __be16 l2_rewrite_vlan_tci; 4454 __le16 act_meter_id; 4455 __le16 ref_flow_handle; 4456 __be16 ethertype; 4457 __be16 outer_vlan_tci; 4458 __be16 dmac[3]; 4459 __be16 inner_vlan_tci; 4460 __be16 smac[3]; 4461 u8 ip_dst_mask_len; 4462 u8 ip_src_mask_len; 4463 __be32 ip_dst[4]; 4464 __be32 ip_src[4]; 4465 __be16 l4_src_port; 4466 __be16 l4_src_port_mask; 4467 __be16 l4_dst_port; 4468 __be16 l4_dst_port_mask; 4469 __be32 nat_ip_address[4]; 4470 __be16 l2_rewrite_dmac[3]; 4471 __be16 nat_port; 4472 __be16 l2_rewrite_smac[3]; 4473 u8 ip_proto; 4474 u8 unused_0; 4475 }; 4476 4477 /* Output (16 bytes) */ 4478 struct hwrm_cfa_flow_alloc_output { 4479 __le16 error_code; 4480 __le16 req_type; 4481 __le16 seq_id; 4482 __le16 resp_len; 4483 __le16 flow_handle; 4484 u8 unused_0; 4485 u8 unused_1; 4486 u8 unused_2; 4487 u8 unused_3; 4488 u8 unused_4; 4489 u8 valid; 4490 }; 4491 4492 /* hwrm_cfa_flow_free */ 4493 /* Input (24 bytes) */ 4494 struct hwrm_cfa_flow_free_input { 4495 __le16 req_type; 4496 __le16 cmpl_ring; 4497 __le16 seq_id; 4498 __le16 target_id; 4499 __le64 resp_addr; 4500 __le16 flow_handle; 4501 __le16 unused_0[3]; 4502 }; 4503 4504 /* Output (32 bytes) */ 4505 struct hwrm_cfa_flow_free_output { 4506 __le16 error_code; 4507 __le16 req_type; 4508 __le16 seq_id; 4509 __le16 resp_len; 4510 __le64 packet; 4511 __le64 byte; 4512 __le32 unused_0; 4513 u8 unused_1; 4514 u8 unused_2; 4515 u8 unused_3; 4516 u8 valid; 4517 }; 4518 4519 /* hwrm_cfa_flow_stats */ 4520 /* Input (40 bytes) */ 4521 struct hwrm_cfa_flow_stats_input { 4522 __le16 req_type; 4523 __le16 cmpl_ring; 4524 __le16 seq_id; 4525 __le16 target_id; 4526 __le64 resp_addr; 4527 __le16 num_flows; 4528 __le16 flow_handle_0; 4529 __le16 flow_handle_1; 4530 __le16 flow_handle_2; 4531 __le16 flow_handle_3; 4532 __le16 flow_handle_4; 4533 __le16 flow_handle_5; 4534 __le16 flow_handle_6; 4535 __le16 flow_handle_7; 4536 __le16 flow_handle_8; 4537 __le16 flow_handle_9; 4538 __le16 unused_0; 4539 }; 4540 4541 /* Output (176 bytes) */ 4542 struct hwrm_cfa_flow_stats_output { 4543 __le16 error_code; 4544 __le16 req_type; 4545 __le16 seq_id; 4546 __le16 resp_len; 4547 __le64 packet_0; 4548 __le64 packet_1; 4549 __le64 packet_2; 4550 __le64 packet_3; 4551 __le64 packet_4; 4552 __le64 packet_5; 4553 __le64 packet_6; 4554 __le64 packet_7; 4555 __le64 packet_8; 4556 __le64 packet_9; 4557 __le64 byte_0; 4558 __le64 byte_1; 4559 __le64 byte_2; 4560 __le64 byte_3; 4561 __le64 byte_4; 4562 __le64 byte_5; 4563 __le64 byte_6; 4564 __le64 byte_7; 4565 __le64 byte_8; 4566 __le64 byte_9; 4567 __le32 unused_0; 4568 u8 unused_1; 4569 u8 unused_2; 4570 u8 unused_3; 4571 u8 valid; 4572 }; 4573 4574 /* hwrm_cfa_vfr_alloc */ 4575 /* Input (32 bytes) */ 4576 struct hwrm_cfa_vfr_alloc_input { 4577 __le16 req_type; 4578 __le16 cmpl_ring; 4579 __le16 seq_id; 4580 __le16 target_id; 4581 __le64 resp_addr; 4582 __le16 vf_id; 4583 __le16 reserved; 4584 __le32 unused_0; 4585 char vfr_name[32]; 4586 }; 4587 4588 /* Output (16 bytes) */ 4589 struct hwrm_cfa_vfr_alloc_output { 4590 __le16 error_code; 4591 __le16 req_type; 4592 __le16 seq_id; 4593 __le16 resp_len; 4594 __le16 rx_cfa_code; 4595 __le16 tx_cfa_action; 4596 u8 unused_0; 4597 u8 unused_1; 4598 u8 unused_2; 4599 u8 valid; 4600 }; 4601 4602 /* hwrm_cfa_vfr_free */ 4603 /* Input (24 bytes) */ 4604 struct hwrm_cfa_vfr_free_input { 4605 __le16 req_type; 4606 __le16 cmpl_ring; 4607 __le16 seq_id; 4608 __le16 target_id; 4609 __le64 resp_addr; 4610 char vfr_name[32]; 4611 }; 4612 4613 /* Output (16 bytes) */ 4614 struct hwrm_cfa_vfr_free_output { 4615 __le16 error_code; 4616 __le16 req_type; 4617 __le16 seq_id; 4618 __le16 resp_len; 4619 __le32 unused_0; 4620 u8 unused_1; 4621 u8 unused_2; 4622 u8 unused_3; 4623 u8 valid; 4624 }; 4625 4626 /* hwrm_tunnel_dst_port_query */ 4627 /* Input (24 bytes) */ 4628 struct hwrm_tunnel_dst_port_query_input { 4629 __le16 req_type; 4630 __le16 cmpl_ring; 4631 __le16 seq_id; 4632 __le16 target_id; 4633 __le64 resp_addr; 4634 u8 tunnel_type; 4635 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4636 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4637 u8 unused_0[7]; 4638 }; 4639 4640 /* Output (16 bytes) */ 4641 struct hwrm_tunnel_dst_port_query_output { 4642 __le16 error_code; 4643 __le16 req_type; 4644 __le16 seq_id; 4645 __le16 resp_len; 4646 __le16 tunnel_dst_port_id; 4647 __be16 tunnel_dst_port_val; 4648 u8 unused_0; 4649 u8 unused_1; 4650 u8 unused_2; 4651 u8 valid; 4652 }; 4653 4654 /* hwrm_tunnel_dst_port_alloc */ 4655 /* Input (24 bytes) */ 4656 struct hwrm_tunnel_dst_port_alloc_input { 4657 __le16 req_type; 4658 __le16 cmpl_ring; 4659 __le16 seq_id; 4660 __le16 target_id; 4661 __le64 resp_addr; 4662 u8 tunnel_type; 4663 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4664 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4665 u8 unused_0; 4666 __be16 tunnel_dst_port_val; 4667 __le32 unused_1; 4668 }; 4669 4670 /* Output (16 bytes) */ 4671 struct hwrm_tunnel_dst_port_alloc_output { 4672 __le16 error_code; 4673 __le16 req_type; 4674 __le16 seq_id; 4675 __le16 resp_len; 4676 __le16 tunnel_dst_port_id; 4677 u8 unused_0; 4678 u8 unused_1; 4679 u8 unused_2; 4680 u8 unused_3; 4681 u8 unused_4; 4682 u8 valid; 4683 }; 4684 4685 /* hwrm_tunnel_dst_port_free */ 4686 /* Input (24 bytes) */ 4687 struct hwrm_tunnel_dst_port_free_input { 4688 __le16 req_type; 4689 __le16 cmpl_ring; 4690 __le16 seq_id; 4691 __le16 target_id; 4692 __le64 resp_addr; 4693 u8 tunnel_type; 4694 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4695 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4696 u8 unused_0; 4697 __le16 tunnel_dst_port_id; 4698 __le32 unused_1; 4699 }; 4700 4701 /* Output (16 bytes) */ 4702 struct hwrm_tunnel_dst_port_free_output { 4703 __le16 error_code; 4704 __le16 req_type; 4705 __le16 seq_id; 4706 __le16 resp_len; 4707 __le32 unused_0; 4708 u8 unused_1; 4709 u8 unused_2; 4710 u8 unused_3; 4711 u8 valid; 4712 }; 4713 4714 /* hwrm_stat_ctx_alloc */ 4715 /* Input (32 bytes) */ 4716 struct hwrm_stat_ctx_alloc_input { 4717 __le16 req_type; 4718 __le16 cmpl_ring; 4719 __le16 seq_id; 4720 __le16 target_id; 4721 __le64 resp_addr; 4722 __le64 stats_dma_addr; 4723 __le32 update_period_ms; 4724 u8 stat_ctx_flags; 4725 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 4726 u8 unused_0[3]; 4727 }; 4728 4729 /* Output (16 bytes) */ 4730 struct hwrm_stat_ctx_alloc_output { 4731 __le16 error_code; 4732 __le16 req_type; 4733 __le16 seq_id; 4734 __le16 resp_len; 4735 __le32 stat_ctx_id; 4736 u8 unused_0; 4737 u8 unused_1; 4738 u8 unused_2; 4739 u8 valid; 4740 }; 4741 4742 /* hwrm_stat_ctx_free */ 4743 /* Input (24 bytes) */ 4744 struct hwrm_stat_ctx_free_input { 4745 __le16 req_type; 4746 __le16 cmpl_ring; 4747 __le16 seq_id; 4748 __le16 target_id; 4749 __le64 resp_addr; 4750 __le32 stat_ctx_id; 4751 __le32 unused_0; 4752 }; 4753 4754 /* Output (16 bytes) */ 4755 struct hwrm_stat_ctx_free_output { 4756 __le16 error_code; 4757 __le16 req_type; 4758 __le16 seq_id; 4759 __le16 resp_len; 4760 __le32 stat_ctx_id; 4761 u8 unused_0; 4762 u8 unused_1; 4763 u8 unused_2; 4764 u8 valid; 4765 }; 4766 4767 /* hwrm_stat_ctx_query */ 4768 /* Input (24 bytes) */ 4769 struct hwrm_stat_ctx_query_input { 4770 __le16 req_type; 4771 __le16 cmpl_ring; 4772 __le16 seq_id; 4773 __le16 target_id; 4774 __le64 resp_addr; 4775 __le32 stat_ctx_id; 4776 __le32 unused_0; 4777 }; 4778 4779 /* Output (176 bytes) */ 4780 struct hwrm_stat_ctx_query_output { 4781 __le16 error_code; 4782 __le16 req_type; 4783 __le16 seq_id; 4784 __le16 resp_len; 4785 __le64 tx_ucast_pkts; 4786 __le64 tx_mcast_pkts; 4787 __le64 tx_bcast_pkts; 4788 __le64 tx_err_pkts; 4789 __le64 tx_drop_pkts; 4790 __le64 tx_ucast_bytes; 4791 __le64 tx_mcast_bytes; 4792 __le64 tx_bcast_bytes; 4793 __le64 rx_ucast_pkts; 4794 __le64 rx_mcast_pkts; 4795 __le64 rx_bcast_pkts; 4796 __le64 rx_err_pkts; 4797 __le64 rx_drop_pkts; 4798 __le64 rx_ucast_bytes; 4799 __le64 rx_mcast_bytes; 4800 __le64 rx_bcast_bytes; 4801 __le64 rx_agg_pkts; 4802 __le64 rx_agg_bytes; 4803 __le64 rx_agg_events; 4804 __le64 rx_agg_aborts; 4805 __le32 unused_0; 4806 u8 unused_1; 4807 u8 unused_2; 4808 u8 unused_3; 4809 u8 valid; 4810 }; 4811 4812 /* hwrm_stat_ctx_clr_stats */ 4813 /* Input (24 bytes) */ 4814 struct hwrm_stat_ctx_clr_stats_input { 4815 __le16 req_type; 4816 __le16 cmpl_ring; 4817 __le16 seq_id; 4818 __le16 target_id; 4819 __le64 resp_addr; 4820 __le32 stat_ctx_id; 4821 __le32 unused_0; 4822 }; 4823 4824 /* Output (16 bytes) */ 4825 struct hwrm_stat_ctx_clr_stats_output { 4826 __le16 error_code; 4827 __le16 req_type; 4828 __le16 seq_id; 4829 __le16 resp_len; 4830 __le32 unused_0; 4831 u8 unused_1; 4832 u8 unused_2; 4833 u8 unused_3; 4834 u8 valid; 4835 }; 4836 4837 /* hwrm_fw_reset */ 4838 /* Input (24 bytes) */ 4839 struct hwrm_fw_reset_input { 4840 __le16 req_type; 4841 __le16 cmpl_ring; 4842 __le16 seq_id; 4843 __le16 target_id; 4844 __le64 resp_addr; 4845 u8 embedded_proc_type; 4846 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4847 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4848 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4849 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4850 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 4851 u8 selfrst_status; 4852 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 4853 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 4854 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4855 u8 host_idx; 4856 u8 unused_0[5]; 4857 }; 4858 4859 /* Output (16 bytes) */ 4860 struct hwrm_fw_reset_output { 4861 __le16 error_code; 4862 __le16 req_type; 4863 __le16 seq_id; 4864 __le16 resp_len; 4865 u8 selfrst_status; 4866 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4867 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4868 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4869 u8 unused_0; 4870 __le16 unused_1; 4871 u8 unused_2; 4872 u8 unused_3; 4873 u8 unused_4; 4874 u8 valid; 4875 }; 4876 4877 /* hwrm_fw_qstatus */ 4878 /* Input (24 bytes) */ 4879 struct hwrm_fw_qstatus_input { 4880 __le16 req_type; 4881 __le16 cmpl_ring; 4882 __le16 seq_id; 4883 __le16 target_id; 4884 __le64 resp_addr; 4885 u8 embedded_proc_type; 4886 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4887 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4888 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4889 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4890 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 4891 u8 unused_0[7]; 4892 }; 4893 4894 /* Output (16 bytes) */ 4895 struct hwrm_fw_qstatus_output { 4896 __le16 error_code; 4897 __le16 req_type; 4898 __le16 seq_id; 4899 __le16 resp_len; 4900 u8 selfrst_status; 4901 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4902 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4903 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4904 u8 unused_0; 4905 __le16 unused_1; 4906 u8 unused_2; 4907 u8 unused_3; 4908 u8 unused_4; 4909 u8 valid; 4910 }; 4911 4912 /* hwrm_fw_set_time */ 4913 /* Input (32 bytes) */ 4914 struct hwrm_fw_set_time_input { 4915 __le16 req_type; 4916 __le16 cmpl_ring; 4917 __le16 seq_id; 4918 __le16 target_id; 4919 __le64 resp_addr; 4920 __le16 year; 4921 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4922 u8 month; 4923 u8 day; 4924 u8 hour; 4925 u8 minute; 4926 u8 second; 4927 u8 unused_0; 4928 __le16 millisecond; 4929 __le16 zone; 4930 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4931 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4932 __le32 unused_1; 4933 }; 4934 4935 /* Output (16 bytes) */ 4936 struct hwrm_fw_set_time_output { 4937 __le16 error_code; 4938 __le16 req_type; 4939 __le16 seq_id; 4940 __le16 resp_len; 4941 __le32 unused_0; 4942 u8 unused_1; 4943 u8 unused_2; 4944 u8 unused_3; 4945 u8 valid; 4946 }; 4947 4948 /* hwrm_fw_set_structured_data */ 4949 /* Input (32 bytes) */ 4950 struct hwrm_fw_set_structured_data_input { 4951 __le16 req_type; 4952 __le16 cmpl_ring; 4953 __le16 seq_id; 4954 __le16 target_id; 4955 __le64 resp_addr; 4956 __le64 src_data_addr; 4957 __le16 data_len; 4958 u8 hdr_cnt; 4959 u8 unused_0[5]; 4960 }; 4961 4962 /* Output (16 bytes) */ 4963 struct hwrm_fw_set_structured_data_output { 4964 __le16 error_code; 4965 __le16 req_type; 4966 __le16 seq_id; 4967 __le16 resp_len; 4968 __le32 unused_0; 4969 u8 unused_1; 4970 u8 unused_2; 4971 u8 unused_3; 4972 u8 valid; 4973 }; 4974 4975 /* Command specific Error Codes (8 bytes) */ 4976 struct hwrm_fw_set_structured_data_cmd_err { 4977 u8 code; 4978 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 4979 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 4980 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 4981 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 4982 u8 unused_0[7]; 4983 }; 4984 4985 /* hwrm_fw_get_structured_data */ 4986 /* Input (32 bytes) */ 4987 struct hwrm_fw_get_structured_data_input { 4988 __le16 req_type; 4989 __le16 cmpl_ring; 4990 __le16 seq_id; 4991 __le16 target_id; 4992 __le64 resp_addr; 4993 __le64 dest_data_addr; 4994 __le16 data_len; 4995 __le16 structure_id; 4996 __le16 subtype; 4997 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 4998 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 4999 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 5000 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 5001 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 5002 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 5003 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 5004 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 5005 u8 count; 5006 u8 unused_0; 5007 }; 5008 5009 /* Output (16 bytes) */ 5010 struct hwrm_fw_get_structured_data_output { 5011 __le16 error_code; 5012 __le16 req_type; 5013 __le16 seq_id; 5014 __le16 resp_len; 5015 u8 hdr_cnt; 5016 u8 unused_0; 5017 __le16 unused_1; 5018 u8 unused_2; 5019 u8 unused_3; 5020 u8 unused_4; 5021 u8 valid; 5022 }; 5023 5024 /* Command specific Error Codes (8 bytes) */ 5025 struct hwrm_fw_get_structured_data_cmd_err { 5026 u8 code; 5027 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5028 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5029 u8 unused_0[7]; 5030 }; 5031 5032 /* hwrm_exec_fwd_resp */ 5033 /* Input (128 bytes) */ 5034 struct hwrm_exec_fwd_resp_input { 5035 __le16 req_type; 5036 __le16 cmpl_ring; 5037 __le16 seq_id; 5038 __le16 target_id; 5039 __le64 resp_addr; 5040 __le32 encap_request[26]; 5041 __le16 encap_resp_target_id; 5042 __le16 unused_0[3]; 5043 }; 5044 5045 /* Output (16 bytes) */ 5046 struct hwrm_exec_fwd_resp_output { 5047 __le16 error_code; 5048 __le16 req_type; 5049 __le16 seq_id; 5050 __le16 resp_len; 5051 __le32 unused_0; 5052 u8 unused_1; 5053 u8 unused_2; 5054 u8 unused_3; 5055 u8 valid; 5056 }; 5057 5058 /* hwrm_reject_fwd_resp */ 5059 /* Input (128 bytes) */ 5060 struct hwrm_reject_fwd_resp_input { 5061 __le16 req_type; 5062 __le16 cmpl_ring; 5063 __le16 seq_id; 5064 __le16 target_id; 5065 __le64 resp_addr; 5066 __le32 encap_request[26]; 5067 __le16 encap_resp_target_id; 5068 __le16 unused_0[3]; 5069 }; 5070 5071 /* Output (16 bytes) */ 5072 struct hwrm_reject_fwd_resp_output { 5073 __le16 error_code; 5074 __le16 req_type; 5075 __le16 seq_id; 5076 __le16 resp_len; 5077 __le32 unused_0; 5078 u8 unused_1; 5079 u8 unused_2; 5080 u8 unused_3; 5081 u8 valid; 5082 }; 5083 5084 /* hwrm_fwd_resp */ 5085 /* Input (40 bytes) */ 5086 struct hwrm_fwd_resp_input { 5087 __le16 req_type; 5088 __le16 cmpl_ring; 5089 __le16 seq_id; 5090 __le16 target_id; 5091 __le64 resp_addr; 5092 __le16 encap_resp_target_id; 5093 __le16 encap_resp_cmpl_ring; 5094 __le16 encap_resp_len; 5095 u8 unused_0; 5096 u8 unused_1; 5097 __le64 encap_resp_addr; 5098 __le32 encap_resp[24]; 5099 }; 5100 5101 /* Output (16 bytes) */ 5102 struct hwrm_fwd_resp_output { 5103 __le16 error_code; 5104 __le16 req_type; 5105 __le16 seq_id; 5106 __le16 resp_len; 5107 __le32 unused_0; 5108 u8 unused_1; 5109 u8 unused_2; 5110 u8 unused_3; 5111 u8 valid; 5112 }; 5113 5114 /* hwrm_fwd_async_event_cmpl */ 5115 /* Input (32 bytes) */ 5116 struct hwrm_fwd_async_event_cmpl_input { 5117 __le16 req_type; 5118 __le16 cmpl_ring; 5119 __le16 seq_id; 5120 __le16 target_id; 5121 __le64 resp_addr; 5122 __le16 encap_async_event_target_id; 5123 u8 unused_0; 5124 u8 unused_1; 5125 u8 unused_2[3]; 5126 u8 unused_3; 5127 __le32 encap_async_event_cmpl[4]; 5128 }; 5129 5130 /* Output (16 bytes) */ 5131 struct hwrm_fwd_async_event_cmpl_output { 5132 __le16 error_code; 5133 __le16 req_type; 5134 __le16 seq_id; 5135 __le16 resp_len; 5136 __le32 unused_0; 5137 u8 unused_1; 5138 u8 unused_2; 5139 u8 unused_3; 5140 u8 valid; 5141 }; 5142 5143 /* hwrm_temp_monitor_query */ 5144 /* Input (16 bytes) */ 5145 struct hwrm_temp_monitor_query_input { 5146 __le16 req_type; 5147 __le16 cmpl_ring; 5148 __le16 seq_id; 5149 __le16 target_id; 5150 __le64 resp_addr; 5151 }; 5152 5153 /* Output (16 bytes) */ 5154 struct hwrm_temp_monitor_query_output { 5155 __le16 error_code; 5156 __le16 req_type; 5157 __le16 seq_id; 5158 __le16 resp_len; 5159 u8 temp; 5160 u8 unused_0; 5161 __le16 unused_1; 5162 u8 unused_2; 5163 u8 unused_3; 5164 u8 unused_4; 5165 u8 valid; 5166 }; 5167 5168 /* hwrm_wol_filter_alloc */ 5169 /* Input (64 bytes) */ 5170 struct hwrm_wol_filter_alloc_input { 5171 __le16 req_type; 5172 __le16 cmpl_ring; 5173 __le16 seq_id; 5174 __le16 target_id; 5175 __le64 resp_addr; 5176 __le32 flags; 5177 __le32 enables; 5178 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 5179 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 5180 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 5181 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 5182 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 5183 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 5184 __le16 port_id; 5185 u8 wol_type; 5186 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 5187 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 5188 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 5189 u8 unused_0; 5190 __le32 unused_1; 5191 u8 mac_address[6]; 5192 __le16 pattern_offset; 5193 __le16 pattern_buf_size; 5194 __le16 pattern_mask_size; 5195 __le32 unused_2; 5196 __le64 pattern_buf_addr; 5197 __le64 pattern_mask_addr; 5198 }; 5199 5200 /* Output (16 bytes) */ 5201 struct hwrm_wol_filter_alloc_output { 5202 __le16 error_code; 5203 __le16 req_type; 5204 __le16 seq_id; 5205 __le16 resp_len; 5206 u8 wol_filter_id; 5207 u8 unused_0; 5208 __le16 unused_1; 5209 u8 unused_2; 5210 u8 unused_3; 5211 u8 unused_4; 5212 u8 valid; 5213 }; 5214 5215 /* hwrm_wol_filter_free */ 5216 /* Input (32 bytes) */ 5217 struct hwrm_wol_filter_free_input { 5218 __le16 req_type; 5219 __le16 cmpl_ring; 5220 __le16 seq_id; 5221 __le16 target_id; 5222 __le64 resp_addr; 5223 __le32 flags; 5224 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 5225 __le32 enables; 5226 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 5227 __le16 port_id; 5228 u8 wol_filter_id; 5229 u8 unused_0[5]; 5230 }; 5231 5232 /* Output (16 bytes) */ 5233 struct hwrm_wol_filter_free_output { 5234 __le16 error_code; 5235 __le16 req_type; 5236 __le16 seq_id; 5237 __le16 resp_len; 5238 __le32 unused_0; 5239 u8 unused_1; 5240 u8 unused_2; 5241 u8 unused_3; 5242 u8 valid; 5243 }; 5244 5245 /* hwrm_wol_filter_qcfg */ 5246 /* Input (56 bytes) */ 5247 struct hwrm_wol_filter_qcfg_input { 5248 __le16 req_type; 5249 __le16 cmpl_ring; 5250 __le16 seq_id; 5251 __le16 target_id; 5252 __le64 resp_addr; 5253 __le16 port_id; 5254 __le16 handle; 5255 __le32 unused_0; 5256 __le64 pattern_buf_addr; 5257 __le16 pattern_buf_size; 5258 u8 unused_1; 5259 u8 unused_2; 5260 u8 unused_3[3]; 5261 u8 unused_4; 5262 __le64 pattern_mask_addr; 5263 __le16 pattern_mask_size; 5264 __le16 unused_5[3]; 5265 }; 5266 5267 /* Output (32 bytes) */ 5268 struct hwrm_wol_filter_qcfg_output { 5269 __le16 error_code; 5270 __le16 req_type; 5271 __le16 seq_id; 5272 __le16 resp_len; 5273 __le16 next_handle; 5274 u8 wol_filter_id; 5275 u8 wol_type; 5276 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 5277 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 5278 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 5279 __le32 unused_0; 5280 u8 mac_address[6]; 5281 __le16 pattern_offset; 5282 __le16 pattern_size; 5283 __le16 pattern_mask_size; 5284 u8 unused_1; 5285 u8 unused_2; 5286 u8 unused_3; 5287 u8 valid; 5288 }; 5289 5290 /* hwrm_wol_reason_qcfg */ 5291 /* Input (40 bytes) */ 5292 struct hwrm_wol_reason_qcfg_input { 5293 __le16 req_type; 5294 __le16 cmpl_ring; 5295 __le16 seq_id; 5296 __le16 target_id; 5297 __le64 resp_addr; 5298 __le16 port_id; 5299 u8 unused_0; 5300 u8 unused_1; 5301 u8 unused_2[3]; 5302 u8 unused_3; 5303 __le64 wol_pkt_buf_addr; 5304 __le16 wol_pkt_buf_size; 5305 __le16 unused_4[3]; 5306 }; 5307 5308 /* Output (16 bytes) */ 5309 struct hwrm_wol_reason_qcfg_output { 5310 __le16 error_code; 5311 __le16 req_type; 5312 __le16 seq_id; 5313 __le16 resp_len; 5314 u8 wol_filter_id; 5315 u8 wol_reason; 5316 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 5317 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 5318 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 5319 u8 wol_pkt_len; 5320 u8 unused_0; 5321 u8 unused_1; 5322 u8 unused_2; 5323 u8 unused_3; 5324 u8 valid; 5325 }; 5326 5327 /* hwrm_nvm_read */ 5328 /* Input (40 bytes) */ 5329 struct hwrm_nvm_read_input { 5330 __le16 req_type; 5331 __le16 cmpl_ring; 5332 __le16 seq_id; 5333 __le16 target_id; 5334 __le64 resp_addr; 5335 __le64 host_dest_addr; 5336 __le16 dir_idx; 5337 u8 unused_0; 5338 u8 unused_1; 5339 __le32 offset; 5340 __le32 len; 5341 __le32 unused_2; 5342 }; 5343 5344 /* Output (16 bytes) */ 5345 struct hwrm_nvm_read_output { 5346 __le16 error_code; 5347 __le16 req_type; 5348 __le16 seq_id; 5349 __le16 resp_len; 5350 __le32 unused_0; 5351 u8 unused_1; 5352 u8 unused_2; 5353 u8 unused_3; 5354 u8 valid; 5355 }; 5356 5357 /* hwrm_nvm_get_dir_entries */ 5358 /* Input (24 bytes) */ 5359 struct hwrm_nvm_get_dir_entries_input { 5360 __le16 req_type; 5361 __le16 cmpl_ring; 5362 __le16 seq_id; 5363 __le16 target_id; 5364 __le64 resp_addr; 5365 __le64 host_dest_addr; 5366 }; 5367 5368 /* Output (16 bytes) */ 5369 struct hwrm_nvm_get_dir_entries_output { 5370 __le16 error_code; 5371 __le16 req_type; 5372 __le16 seq_id; 5373 __le16 resp_len; 5374 __le32 unused_0; 5375 u8 unused_1; 5376 u8 unused_2; 5377 u8 unused_3; 5378 u8 valid; 5379 }; 5380 5381 /* hwrm_nvm_get_dir_info */ 5382 /* Input (16 bytes) */ 5383 struct hwrm_nvm_get_dir_info_input { 5384 __le16 req_type; 5385 __le16 cmpl_ring; 5386 __le16 seq_id; 5387 __le16 target_id; 5388 __le64 resp_addr; 5389 }; 5390 5391 /* Output (24 bytes) */ 5392 struct hwrm_nvm_get_dir_info_output { 5393 __le16 error_code; 5394 __le16 req_type; 5395 __le16 seq_id; 5396 __le16 resp_len; 5397 __le32 entries; 5398 __le32 entry_length; 5399 __le32 unused_0; 5400 u8 unused_1; 5401 u8 unused_2; 5402 u8 unused_3; 5403 u8 valid; 5404 }; 5405 5406 /* hwrm_nvm_write */ 5407 /* Input (48 bytes) */ 5408 struct hwrm_nvm_write_input { 5409 __le16 req_type; 5410 __le16 cmpl_ring; 5411 __le16 seq_id; 5412 __le16 target_id; 5413 __le64 resp_addr; 5414 __le64 host_src_addr; 5415 __le16 dir_type; 5416 __le16 dir_ordinal; 5417 __le16 dir_ext; 5418 __le16 dir_attr; 5419 __le32 dir_data_length; 5420 __le16 option; 5421 __le16 flags; 5422 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5423 __le32 dir_item_length; 5424 __le32 unused_0; 5425 }; 5426 5427 /* Output (16 bytes) */ 5428 struct hwrm_nvm_write_output { 5429 __le16 error_code; 5430 __le16 req_type; 5431 __le16 seq_id; 5432 __le16 resp_len; 5433 __le32 dir_item_length; 5434 __le16 dir_idx; 5435 u8 unused_0; 5436 u8 valid; 5437 }; 5438 5439 /* Command specific Error Codes (8 bytes) */ 5440 struct hwrm_nvm_write_cmd_err { 5441 u8 code; 5442 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 5443 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5444 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 5445 u8 unused_0[7]; 5446 }; 5447 5448 /* hwrm_nvm_modify */ 5449 /* Input (40 bytes) */ 5450 struct hwrm_nvm_modify_input { 5451 __le16 req_type; 5452 __le16 cmpl_ring; 5453 __le16 seq_id; 5454 __le16 target_id; 5455 __le64 resp_addr; 5456 __le64 host_src_addr; 5457 __le16 dir_idx; 5458 u8 unused_0; 5459 u8 unused_1; 5460 __le32 offset; 5461 __le32 len; 5462 __le32 unused_2; 5463 }; 5464 5465 /* Output (16 bytes) */ 5466 struct hwrm_nvm_modify_output { 5467 __le16 error_code; 5468 __le16 req_type; 5469 __le16 seq_id; 5470 __le16 resp_len; 5471 __le32 unused_0; 5472 u8 unused_1; 5473 u8 unused_2; 5474 u8 unused_3; 5475 u8 valid; 5476 }; 5477 5478 /* hwrm_nvm_find_dir_entry */ 5479 /* Input (32 bytes) */ 5480 struct hwrm_nvm_find_dir_entry_input { 5481 __le16 req_type; 5482 __le16 cmpl_ring; 5483 __le16 seq_id; 5484 __le16 target_id; 5485 __le64 resp_addr; 5486 __le32 enables; 5487 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 5488 __le16 dir_idx; 5489 __le16 dir_type; 5490 __le16 dir_ordinal; 5491 __le16 dir_ext; 5492 u8 opt_ordinal; 5493 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 5494 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 5495 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 5496 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 5497 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 5498 u8 unused_1[3]; 5499 }; 5500 5501 /* Output (32 bytes) */ 5502 struct hwrm_nvm_find_dir_entry_output { 5503 __le16 error_code; 5504 __le16 req_type; 5505 __le16 seq_id; 5506 __le16 resp_len; 5507 __le32 dir_item_length; 5508 __le32 dir_data_length; 5509 __le32 fw_ver; 5510 __le16 dir_ordinal; 5511 __le16 dir_idx; 5512 __le32 unused_0; 5513 u8 unused_1; 5514 u8 unused_2; 5515 u8 unused_3; 5516 u8 valid; 5517 }; 5518 5519 /* hwrm_nvm_erase_dir_entry */ 5520 /* Input (24 bytes) */ 5521 struct hwrm_nvm_erase_dir_entry_input { 5522 __le16 req_type; 5523 __le16 cmpl_ring; 5524 __le16 seq_id; 5525 __le16 target_id; 5526 __le64 resp_addr; 5527 __le16 dir_idx; 5528 __le16 unused_0[3]; 5529 }; 5530 5531 /* Output (16 bytes) */ 5532 struct hwrm_nvm_erase_dir_entry_output { 5533 __le16 error_code; 5534 __le16 req_type; 5535 __le16 seq_id; 5536 __le16 resp_len; 5537 __le32 unused_0; 5538 u8 unused_1; 5539 u8 unused_2; 5540 u8 unused_3; 5541 u8 valid; 5542 }; 5543 5544 /* hwrm_nvm_get_dev_info */ 5545 /* Input (16 bytes) */ 5546 struct hwrm_nvm_get_dev_info_input { 5547 __le16 req_type; 5548 __le16 cmpl_ring; 5549 __le16 seq_id; 5550 __le16 target_id; 5551 __le64 resp_addr; 5552 }; 5553 5554 /* Output (32 bytes) */ 5555 struct hwrm_nvm_get_dev_info_output { 5556 __le16 error_code; 5557 __le16 req_type; 5558 __le16 seq_id; 5559 __le16 resp_len; 5560 __le16 manufacturer_id; 5561 __le16 device_id; 5562 __le32 sector_size; 5563 __le32 nvram_size; 5564 __le32 reserved_size; 5565 __le32 available_size; 5566 u8 unused_0; 5567 u8 unused_1; 5568 u8 unused_2; 5569 u8 valid; 5570 }; 5571 5572 /* hwrm_nvm_mod_dir_entry */ 5573 /* Input (32 bytes) */ 5574 struct hwrm_nvm_mod_dir_entry_input { 5575 __le16 req_type; 5576 __le16 cmpl_ring; 5577 __le16 seq_id; 5578 __le16 target_id; 5579 __le64 resp_addr; 5580 __le32 enables; 5581 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 5582 __le16 dir_idx; 5583 __le16 dir_ordinal; 5584 __le16 dir_ext; 5585 __le16 dir_attr; 5586 __le32 checksum; 5587 }; 5588 5589 /* Output (16 bytes) */ 5590 struct hwrm_nvm_mod_dir_entry_output { 5591 __le16 error_code; 5592 __le16 req_type; 5593 __le16 seq_id; 5594 __le16 resp_len; 5595 __le32 unused_0; 5596 u8 unused_1; 5597 u8 unused_2; 5598 u8 unused_3; 5599 u8 valid; 5600 }; 5601 5602 /* hwrm_nvm_verify_update */ 5603 /* Input (24 bytes) */ 5604 struct hwrm_nvm_verify_update_input { 5605 __le16 req_type; 5606 __le16 cmpl_ring; 5607 __le16 seq_id; 5608 __le16 target_id; 5609 __le64 resp_addr; 5610 __le16 dir_type; 5611 __le16 dir_ordinal; 5612 __le16 dir_ext; 5613 __le16 unused_0; 5614 }; 5615 5616 /* Output (16 bytes) */ 5617 struct hwrm_nvm_verify_update_output { 5618 __le16 error_code; 5619 __le16 req_type; 5620 __le16 seq_id; 5621 __le16 resp_len; 5622 __le32 unused_0; 5623 u8 unused_1; 5624 u8 unused_2; 5625 u8 unused_3; 5626 u8 valid; 5627 }; 5628 5629 /* hwrm_nvm_install_update */ 5630 /* Input (24 bytes) */ 5631 struct hwrm_nvm_install_update_input { 5632 __le16 req_type; 5633 __le16 cmpl_ring; 5634 __le16 seq_id; 5635 __le16 target_id; 5636 __le64 resp_addr; 5637 __le32 install_type; 5638 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 5639 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 5640 __le16 flags; 5641 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 5642 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 5643 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 5644 __le16 unused_0; 5645 }; 5646 5647 /* Output (24 bytes) */ 5648 struct hwrm_nvm_install_update_output { 5649 __le16 error_code; 5650 __le16 req_type; 5651 __le16 seq_id; 5652 __le16 resp_len; 5653 __le64 installed_items; 5654 u8 result; 5655 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 5656 u8 problem_item; 5657 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 5658 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 5659 u8 reset_required; 5660 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 5661 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 5662 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 5663 u8 unused_0; 5664 u8 unused_1; 5665 u8 unused_2; 5666 u8 unused_3; 5667 u8 valid; 5668 }; 5669 5670 /* Command specific Error Codes (8 bytes) */ 5671 struct hwrm_nvm_install_update_cmd_err { 5672 u8 code; 5673 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 5674 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5675 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 5676 u8 unused_0[7]; 5677 }; 5678 5679 /* hwrm_selftest_qlist */ 5680 /* Input (16 bytes) */ 5681 struct hwrm_selftest_qlist_input { 5682 __le16 req_type; 5683 __le16 cmpl_ring; 5684 __le16 seq_id; 5685 __le16 target_id; 5686 __le64 resp_addr; 5687 }; 5688 5689 /* Output (248 bytes) */ 5690 struct hwrm_selftest_qlist_output { 5691 __le16 error_code; 5692 __le16 req_type; 5693 __le16 seq_id; 5694 __le16 resp_len; 5695 u8 num_tests; 5696 u8 available_tests; 5697 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 5698 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 5699 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 5700 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 5701 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_EYE_TEST 0x10UL 5702 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_EYE_TEST 0x20UL 5703 u8 offline_tests; 5704 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 5705 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 5706 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 5707 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 5708 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_EYE_TEST 0x10UL 5709 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_EYE_TEST 0x20UL 5710 u8 unused_0; 5711 __le16 test_timeout; 5712 u8 unused_1; 5713 u8 unused_2; 5714 char test0_name[32]; 5715 char test1_name[32]; 5716 char test2_name[32]; 5717 char test3_name[32]; 5718 char test4_name[32]; 5719 char test5_name[32]; 5720 char test6_name[32]; 5721 char test7_name[32]; 5722 }; 5723 5724 /* hwrm_selftest_exec */ 5725 /* Input (24 bytes) */ 5726 struct hwrm_selftest_exec_input { 5727 __le16 req_type; 5728 __le16 cmpl_ring; 5729 __le16 seq_id; 5730 __le16 target_id; 5731 __le64 resp_addr; 5732 u8 flags; 5733 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 5734 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 5735 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 5736 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 5737 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_EYE_TEST 0x10UL 5738 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_EYE_TEST 0x20UL 5739 u8 unused_0[7]; 5740 }; 5741 5742 /* Output (16 bytes) */ 5743 struct hwrm_selftest_exec_output { 5744 __le16 error_code; 5745 __le16 req_type; 5746 __le16 seq_id; 5747 __le16 resp_len; 5748 u8 requested_tests; 5749 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 5750 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 5751 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 5752 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 5753 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_EYE_TEST 0x10UL 5754 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_EYE_TEST 0x20UL 5755 u8 test_success; 5756 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 5757 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 5758 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 5759 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 5760 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_EYE_TEST 0x10UL 5761 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_EYE_TEST 0x20UL 5762 __le16 unused_0[3]; 5763 }; 5764 5765 /* hwrm_selftest_irq */ 5766 /* Input (16 bytes) */ 5767 struct hwrm_selftest_irq_input { 5768 __le16 req_type; 5769 __le16 cmpl_ring; 5770 __le16 seq_id; 5771 __le16 target_id; 5772 __le64 resp_addr; 5773 }; 5774 5775 /* Output (8 bytes) */ 5776 struct hwrm_selftest_irq_output { 5777 __le16 error_code; 5778 __le16 req_type; 5779 __le16 seq_id; 5780 __le16 resp_len; 5781 }; 5782 5783 /* Hardware Resource Manager Specification */ 5784 /* Input (16 bytes) */ 5785 struct input { 5786 __le16 req_type; 5787 __le16 cmpl_ring; 5788 __le16 seq_id; 5789 __le16 target_id; 5790 __le64 resp_addr; 5791 }; 5792 5793 /* Output (8 bytes) */ 5794 struct output { 5795 __le16 error_code; 5796 __le16 req_type; 5797 __le16 seq_id; 5798 __le16 resp_len; 5799 }; 5800 5801 /* Short Command Structure (16 bytes) */ 5802 struct hwrm_short_input { 5803 __le16 req_type; 5804 __le16 signature; 5805 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 5806 __le16 unused_0; 5807 __le16 size; 5808 __le64 req_addr; 5809 }; 5810 5811 /* Command numbering (8 bytes) */ 5812 struct cmd_nums { 5813 __le16 req_type; 5814 #define HWRM_VER_GET (0x0UL) 5815 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 5816 #define HWRM_FUNC_VF_CFG (0xfUL) 5817 #define RESERVED1 (0x10UL) 5818 #define HWRM_FUNC_RESET (0x11UL) 5819 #define HWRM_FUNC_GETFID (0x12UL) 5820 #define HWRM_FUNC_VF_ALLOC (0x13UL) 5821 #define HWRM_FUNC_VF_FREE (0x14UL) 5822 #define HWRM_FUNC_QCAPS (0x15UL) 5823 #define HWRM_FUNC_QCFG (0x16UL) 5824 #define HWRM_FUNC_CFG (0x17UL) 5825 #define HWRM_FUNC_QSTATS (0x18UL) 5826 #define HWRM_FUNC_CLR_STATS (0x19UL) 5827 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 5828 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 5829 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 5830 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 5831 #define HWRM_FUNC_DRV_QVER (0x1eUL) 5832 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 5833 #define HWRM_PORT_PHY_CFG (0x20UL) 5834 #define HWRM_PORT_MAC_CFG (0x21UL) 5835 #define HWRM_PORT_TS_QUERY (0x22UL) 5836 #define HWRM_PORT_QSTATS (0x23UL) 5837 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 5838 #define HWRM_PORT_CLR_STATS (0x25UL) 5839 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 5840 #define HWRM_PORT_PHY_QCFG (0x27UL) 5841 #define HWRM_PORT_MAC_QCFG (0x28UL) 5842 #define HWRM_PORT_MAC_PTP_QCFG (0x29UL) 5843 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 5844 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 5845 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 5846 #define HWRM_PORT_LED_CFG (0x2dUL) 5847 #define HWRM_PORT_LED_QCFG (0x2eUL) 5848 #define HWRM_PORT_LED_QCAPS (0x2fUL) 5849 #define HWRM_QUEUE_QPORTCFG (0x30UL) 5850 #define HWRM_QUEUE_QCFG (0x31UL) 5851 #define HWRM_QUEUE_CFG (0x32UL) 5852 #define HWRM_FUNC_VLAN_CFG (0x33UL) 5853 #define HWRM_FUNC_VLAN_QCFG (0x34UL) 5854 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 5855 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 5856 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 5857 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 5858 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 5859 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 5860 #define HWRM_QUEUE_DSCP_QCAPS (0x3bUL) 5861 #define HWRM_QUEUE_DSCP2PRI_QCFG (0x3cUL) 5862 #define HWRM_QUEUE_DSCP2PRI_CFG (0x3dUL) 5863 #define HWRM_VNIC_ALLOC (0x40UL) 5864 #define HWRM_VNIC_FREE (0x41UL) 5865 #define HWRM_VNIC_CFG (0x42UL) 5866 #define HWRM_VNIC_QCFG (0x43UL) 5867 #define HWRM_VNIC_TPA_CFG (0x44UL) 5868 #define HWRM_VNIC_TPA_QCFG (0x45UL) 5869 #define HWRM_VNIC_RSS_CFG (0x46UL) 5870 #define HWRM_VNIC_RSS_QCFG (0x47UL) 5871 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 5872 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 5873 #define HWRM_VNIC_QCAPS (0x4aUL) 5874 #define HWRM_RING_ALLOC (0x50UL) 5875 #define HWRM_RING_FREE (0x51UL) 5876 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 5877 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 5878 #define HWRM_RING_RESET (0x5eUL) 5879 #define HWRM_RING_GRP_ALLOC (0x60UL) 5880 #define HWRM_RING_GRP_FREE (0x61UL) 5881 #define RESERVED5 (0x64UL) 5882 #define RESERVED6 (0x65UL) 5883 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 5884 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 5885 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 5886 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 5887 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 5888 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 5889 #define HWRM_CFA_VLAN_ANTISPOOF_CFG (0x94UL) 5890 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 5891 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 5892 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 5893 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 5894 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 5895 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 5896 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 5897 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 5898 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 5899 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 5900 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 5901 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 5902 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 5903 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 5904 #define HWRM_STAT_CTX_FREE (0xb1UL) 5905 #define HWRM_STAT_CTX_QUERY (0xb2UL) 5906 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 5907 #define HWRM_FW_RESET (0xc0UL) 5908 #define HWRM_FW_QSTATUS (0xc1UL) 5909 #define HWRM_FW_SET_TIME (0xc8UL) 5910 #define HWRM_FW_GET_TIME (0xc9UL) 5911 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 5912 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 5913 #define HWRM_FW_IPC_MAILBOX (0xccUL) 5914 #define HWRM_EXEC_FWD_RESP (0xd0UL) 5915 #define HWRM_REJECT_FWD_RESP (0xd1UL) 5916 #define HWRM_FWD_RESP (0xd2UL) 5917 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 5918 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 5919 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 5920 #define HWRM_WOL_FILTER_FREE (0xf1UL) 5921 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 5922 #define HWRM_WOL_REASON_QCFG (0xf3UL) 5923 #define HWRM_CFA_METER_PROFILE_ALLOC (0xf5UL) 5924 #define HWRM_CFA_METER_PROFILE_FREE (0xf6UL) 5925 #define HWRM_CFA_METER_PROFILE_CFG (0xf7UL) 5926 #define HWRM_CFA_METER_INSTANCE_ALLOC (0xf8UL) 5927 #define HWRM_CFA_METER_INSTANCE_FREE (0xf9UL) 5928 #define HWRM_CFA_VFR_ALLOC (0xfdUL) 5929 #define HWRM_CFA_VFR_FREE (0xfeUL) 5930 #define HWRM_CFA_VF_PAIR_ALLOC (0x100UL) 5931 #define HWRM_CFA_VF_PAIR_FREE (0x101UL) 5932 #define HWRM_CFA_VF_PAIR_INFO (0x102UL) 5933 #define HWRM_CFA_FLOW_ALLOC (0x103UL) 5934 #define HWRM_CFA_FLOW_FREE (0x104UL) 5935 #define HWRM_CFA_FLOW_FLUSH (0x105UL) 5936 #define HWRM_CFA_FLOW_STATS (0x106UL) 5937 #define HWRM_CFA_FLOW_INFO (0x107UL) 5938 #define HWRM_CFA_DECAP_FILTER_ALLOC (0x108UL) 5939 #define HWRM_CFA_DECAP_FILTER_FREE (0x109UL) 5940 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG (0x10aUL) 5941 #define HWRM_SELFTEST_QLIST (0x200UL) 5942 #define HWRM_SELFTEST_EXEC (0x201UL) 5943 #define HWRM_SELFTEST_IRQ (0x202UL) 5944 #define HWRM_SELFTEST_RETREIVE_EYE_DATA (0x203UL) 5945 #define HWRM_DBG_READ_DIRECT (0xff10UL) 5946 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 5947 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 5948 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 5949 #define HWRM_DBG_DUMP (0xff14UL) 5950 #define HWRM_DBG_ERASE_NVM (0xff15UL) 5951 #define HWRM_DBG_CFG (0xff16UL) 5952 #define HWRM_NVM_FACTORY_DEFAULTS (0xffeeUL) 5953 #define HWRM_NVM_VALIDATE_OPTION (0xffefUL) 5954 #define HWRM_NVM_FLUSH (0xfff0UL) 5955 #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 5956 #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 5957 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 5958 #define HWRM_NVM_MODIFY (0xfff4UL) 5959 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 5960 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 5961 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 5962 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 5963 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 5964 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 5965 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 5966 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 5967 #define HWRM_NVM_READ (0xfffdUL) 5968 #define HWRM_NVM_WRITE (0xfffeUL) 5969 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 5970 __le16 unused_0[3]; 5971 }; 5972 5973 /* Return Codes (8 bytes) */ 5974 struct ret_codes { 5975 __le16 error_code; 5976 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 5977 #define HWRM_ERR_CODE_FAIL (0x1UL) 5978 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 5979 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 5980 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 5981 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 5982 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 5983 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 5984 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 5985 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 5986 __le16 unused_0[3]; 5987 }; 5988 5989 /* Output (16 bytes) */ 5990 struct hwrm_err_output { 5991 __le16 error_code; 5992 __le16 req_type; 5993 __le16 seq_id; 5994 __le16 resp_len; 5995 __le32 opaque_0; 5996 __le16 opaque_1; 5997 u8 cmd_err; 5998 u8 valid; 5999 }; 6000 6001 /* Port Tx Statistics Formats (408 bytes) */ 6002 struct tx_port_stats { 6003 __le64 tx_64b_frames; 6004 __le64 tx_65b_127b_frames; 6005 __le64 tx_128b_255b_frames; 6006 __le64 tx_256b_511b_frames; 6007 __le64 tx_512b_1023b_frames; 6008 __le64 tx_1024b_1518_frames; 6009 __le64 tx_good_vlan_frames; 6010 __le64 tx_1519b_2047_frames; 6011 __le64 tx_2048b_4095b_frames; 6012 __le64 tx_4096b_9216b_frames; 6013 __le64 tx_9217b_16383b_frames; 6014 __le64 tx_good_frames; 6015 __le64 tx_total_frames; 6016 __le64 tx_ucast_frames; 6017 __le64 tx_mcast_frames; 6018 __le64 tx_bcast_frames; 6019 __le64 tx_pause_frames; 6020 __le64 tx_pfc_frames; 6021 __le64 tx_jabber_frames; 6022 __le64 tx_fcs_err_frames; 6023 __le64 tx_control_frames; 6024 __le64 tx_oversz_frames; 6025 __le64 tx_single_dfrl_frames; 6026 __le64 tx_multi_dfrl_frames; 6027 __le64 tx_single_coll_frames; 6028 __le64 tx_multi_coll_frames; 6029 __le64 tx_late_coll_frames; 6030 __le64 tx_excessive_coll_frames; 6031 __le64 tx_frag_frames; 6032 __le64 tx_err; 6033 __le64 tx_tagged_frames; 6034 __le64 tx_dbl_tagged_frames; 6035 __le64 tx_runt_frames; 6036 __le64 tx_fifo_underruns; 6037 __le64 tx_pfc_ena_frames_pri0; 6038 __le64 tx_pfc_ena_frames_pri1; 6039 __le64 tx_pfc_ena_frames_pri2; 6040 __le64 tx_pfc_ena_frames_pri3; 6041 __le64 tx_pfc_ena_frames_pri4; 6042 __le64 tx_pfc_ena_frames_pri5; 6043 __le64 tx_pfc_ena_frames_pri6; 6044 __le64 tx_pfc_ena_frames_pri7; 6045 __le64 tx_eee_lpi_events; 6046 __le64 tx_eee_lpi_duration; 6047 __le64 tx_llfc_logical_msgs; 6048 __le64 tx_hcfc_msgs; 6049 __le64 tx_total_collisions; 6050 __le64 tx_bytes; 6051 __le64 tx_xthol_frames; 6052 __le64 tx_stat_discard; 6053 __le64 tx_stat_error; 6054 }; 6055 6056 /* Port Rx Statistics Formats (528 bytes) */ 6057 struct rx_port_stats { 6058 __le64 rx_64b_frames; 6059 __le64 rx_65b_127b_frames; 6060 __le64 rx_128b_255b_frames; 6061 __le64 rx_256b_511b_frames; 6062 __le64 rx_512b_1023b_frames; 6063 __le64 rx_1024b_1518_frames; 6064 __le64 rx_good_vlan_frames; 6065 __le64 rx_1519b_2047b_frames; 6066 __le64 rx_2048b_4095b_frames; 6067 __le64 rx_4096b_9216b_frames; 6068 __le64 rx_9217b_16383b_frames; 6069 __le64 rx_total_frames; 6070 __le64 rx_ucast_frames; 6071 __le64 rx_mcast_frames; 6072 __le64 rx_bcast_frames; 6073 __le64 rx_fcs_err_frames; 6074 __le64 rx_ctrl_frames; 6075 __le64 rx_pause_frames; 6076 __le64 rx_pfc_frames; 6077 __le64 rx_unsupported_opcode_frames; 6078 __le64 rx_unsupported_da_pausepfc_frames; 6079 __le64 rx_wrong_sa_frames; 6080 __le64 rx_align_err_frames; 6081 __le64 rx_oor_len_frames; 6082 __le64 rx_code_err_frames; 6083 __le64 rx_false_carrier_frames; 6084 __le64 rx_ovrsz_frames; 6085 __le64 rx_jbr_frames; 6086 __le64 rx_mtu_err_frames; 6087 __le64 rx_match_crc_frames; 6088 __le64 rx_promiscuous_frames; 6089 __le64 rx_tagged_frames; 6090 __le64 rx_double_tagged_frames; 6091 __le64 rx_trunc_frames; 6092 __le64 rx_good_frames; 6093 __le64 rx_pfc_xon2xoff_frames_pri0; 6094 __le64 rx_pfc_xon2xoff_frames_pri1; 6095 __le64 rx_pfc_xon2xoff_frames_pri2; 6096 __le64 rx_pfc_xon2xoff_frames_pri3; 6097 __le64 rx_pfc_xon2xoff_frames_pri4; 6098 __le64 rx_pfc_xon2xoff_frames_pri5; 6099 __le64 rx_pfc_xon2xoff_frames_pri6; 6100 __le64 rx_pfc_xon2xoff_frames_pri7; 6101 __le64 rx_pfc_ena_frames_pri0; 6102 __le64 rx_pfc_ena_frames_pri1; 6103 __le64 rx_pfc_ena_frames_pri2; 6104 __le64 rx_pfc_ena_frames_pri3; 6105 __le64 rx_pfc_ena_frames_pri4; 6106 __le64 rx_pfc_ena_frames_pri5; 6107 __le64 rx_pfc_ena_frames_pri6; 6108 __le64 rx_pfc_ena_frames_pri7; 6109 __le64 rx_sch_crc_err_frames; 6110 __le64 rx_undrsz_frames; 6111 __le64 rx_frag_frames; 6112 __le64 rx_eee_lpi_events; 6113 __le64 rx_eee_lpi_duration; 6114 __le64 rx_llfc_physical_msgs; 6115 __le64 rx_llfc_logical_msgs; 6116 __le64 rx_llfc_msgs_with_crc_err; 6117 __le64 rx_hcfc_msgs; 6118 __le64 rx_hcfc_msgs_with_crc_err; 6119 __le64 rx_bytes; 6120 __le64 rx_runt_bytes; 6121 __le64 rx_runt_frames; 6122 __le64 rx_stat_discard; 6123 __le64 rx_stat_err; 6124 }; 6125 6126 /* Periodic Statistics Context DMA to host (160 bytes) */ 6127 struct ctx_hw_stats { 6128 __le64 rx_ucast_pkts; 6129 __le64 rx_mcast_pkts; 6130 __le64 rx_bcast_pkts; 6131 __le64 rx_discard_pkts; 6132 __le64 rx_drop_pkts; 6133 __le64 rx_ucast_bytes; 6134 __le64 rx_mcast_bytes; 6135 __le64 rx_bcast_bytes; 6136 __le64 tx_ucast_pkts; 6137 __le64 tx_mcast_pkts; 6138 __le64 tx_bcast_pkts; 6139 __le64 tx_discard_pkts; 6140 __le64 tx_drop_pkts; 6141 __le64 tx_ucast_bytes; 6142 __le64 tx_mcast_bytes; 6143 __le64 tx_bcast_bytes; 6144 __le64 tpa_pkts; 6145 __le64 tpa_bytes; 6146 __le64 tpa_events; 6147 __le64 tpa_aborts; 6148 }; 6149 6150 /* Structure data header (16 bytes) */ 6151 struct hwrm_struct_hdr { 6152 __le16 struct_id; 6153 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6154 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6155 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6156 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6157 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6158 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6159 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6160 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6161 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6162 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6163 __le16 len; 6164 u8 version; 6165 u8 count; 6166 __le16 subtype; 6167 __le16 next_offset; 6168 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6169 __le16 unused_0[3]; 6170 }; 6171 6172 /* DCBX Application configuration structure (1057) (8 bytes) */ 6173 struct hwrm_struct_data_dcbx_app { 6174 __be16 protocol_id; 6175 u8 protocol_selector; 6176 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6177 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6178 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6179 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6180 u8 priority; 6181 u8 valid; 6182 u8 unused_0[3]; 6183 }; 6184 6185 #endif 6186