1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2020 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14 #ifndef _BNXT_HSI_H_ 15 #define _BNXT_HSI_H_ 16 17 /* hwrm_cmd_hdr (size:128b/16B) */ 18 struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24 }; 25 26 /* hwrm_resp_hdr (size:64b/8B) */ 27 struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32 }; 33 34 #define CMD_DISCR_TLV_ENCAP 0x8000UL 35 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38 #define TLV_TYPE_HWRM_REQUEST 0x1UL 39 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43 #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 51 #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 52 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53 54 55 /* tlv (size:64b/8B) */ 56 struct tlv { 57 __le16 cmd_discr; 58 u8 reserved_8b; 59 u8 flags; 60 #define TLV_FLAGS_MORE 0x1UL 61 #define TLV_FLAGS_MORE_LAST 0x0UL 62 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63 #define TLV_FLAGS_REQUIRED 0x2UL 64 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67 __le16 tlv_type; 68 __le16 length; 69 }; 70 71 /* input (size:128b/16B) */ 72 struct input { 73 __le16 req_type; 74 __le16 cmpl_ring; 75 __le16 seq_id; 76 __le16 target_id; 77 __le64 resp_addr; 78 }; 79 80 /* output (size:64b/8B) */ 81 struct output { 82 __le16 error_code; 83 __le16 req_type; 84 __le16 seq_id; 85 __le16 resp_len; 86 }; 87 88 /* hwrm_short_input (size:128b/16B) */ 89 struct hwrm_short_input { 90 __le16 req_type; 91 __le16 signature; 92 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 94 __le16 target_id; 95 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 96 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 97 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98 __le16 size; 99 __le64 req_addr; 100 }; 101 102 /* cmd_nums (size:64b/8B) */ 103 struct cmd_nums { 104 __le16 req_type; 105 #define HWRM_VER_GET 0x0UL 106 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 107 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 108 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 109 #define HWRM_FUNC_VF_CFG 0xfUL 110 #define HWRM_RESERVED1 0x10UL 111 #define HWRM_FUNC_RESET 0x11UL 112 #define HWRM_FUNC_GETFID 0x12UL 113 #define HWRM_FUNC_VF_ALLOC 0x13UL 114 #define HWRM_FUNC_VF_FREE 0x14UL 115 #define HWRM_FUNC_QCAPS 0x15UL 116 #define HWRM_FUNC_QCFG 0x16UL 117 #define HWRM_FUNC_CFG 0x17UL 118 #define HWRM_FUNC_QSTATS 0x18UL 119 #define HWRM_FUNC_CLR_STATS 0x19UL 120 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 121 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 122 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 123 #define HWRM_FUNC_DRV_RGTR 0x1dUL 124 #define HWRM_FUNC_DRV_QVER 0x1eUL 125 #define HWRM_FUNC_BUF_RGTR 0x1fUL 126 #define HWRM_PORT_PHY_CFG 0x20UL 127 #define HWRM_PORT_MAC_CFG 0x21UL 128 #define HWRM_PORT_TS_QUERY 0x22UL 129 #define HWRM_PORT_QSTATS 0x23UL 130 #define HWRM_PORT_LPBK_QSTATS 0x24UL 131 #define HWRM_PORT_CLR_STATS 0x25UL 132 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 133 #define HWRM_PORT_PHY_QCFG 0x27UL 134 #define HWRM_PORT_MAC_QCFG 0x28UL 135 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 136 #define HWRM_PORT_PHY_QCAPS 0x2aUL 137 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 138 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 139 #define HWRM_PORT_LED_CFG 0x2dUL 140 #define HWRM_PORT_LED_QCFG 0x2eUL 141 #define HWRM_PORT_LED_QCAPS 0x2fUL 142 #define HWRM_QUEUE_QPORTCFG 0x30UL 143 #define HWRM_QUEUE_QCFG 0x31UL 144 #define HWRM_QUEUE_CFG 0x32UL 145 #define HWRM_FUNC_VLAN_CFG 0x33UL 146 #define HWRM_FUNC_VLAN_QCFG 0x34UL 147 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 148 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 149 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 150 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 151 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 152 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 153 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 154 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 155 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 156 #define HWRM_VNIC_ALLOC 0x40UL 157 #define HWRM_VNIC_FREE 0x41UL 158 #define HWRM_VNIC_CFG 0x42UL 159 #define HWRM_VNIC_QCFG 0x43UL 160 #define HWRM_VNIC_TPA_CFG 0x44UL 161 #define HWRM_VNIC_TPA_QCFG 0x45UL 162 #define HWRM_VNIC_RSS_CFG 0x46UL 163 #define HWRM_VNIC_RSS_QCFG 0x47UL 164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166 #define HWRM_VNIC_QCAPS 0x4aUL 167 #define HWRM_RING_ALLOC 0x50UL 168 #define HWRM_RING_FREE 0x51UL 169 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 170 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 171 #define HWRM_RING_AGGINT_QCAPS 0x54UL 172 #define HWRM_RING_SCHQ_ALLOC 0x55UL 173 #define HWRM_RING_SCHQ_CFG 0x56UL 174 #define HWRM_RING_SCHQ_FREE 0x57UL 175 #define HWRM_RING_RESET 0x5eUL 176 #define HWRM_RING_GRP_ALLOC 0x60UL 177 #define HWRM_RING_GRP_FREE 0x61UL 178 #define HWRM_RING_CFG 0x62UL 179 #define HWRM_RING_QCFG 0x63UL 180 #define HWRM_RESERVED5 0x64UL 181 #define HWRM_RESERVED6 0x65UL 182 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 183 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 184 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 185 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 186 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 187 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 188 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 189 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 190 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 191 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 192 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 193 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 194 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 195 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 196 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 197 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 198 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 199 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 200 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 201 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 202 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 203 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 204 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 205 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 206 #define HWRM_STAT_CTX_ALLOC 0xb0UL 207 #define HWRM_STAT_CTX_FREE 0xb1UL 208 #define HWRM_STAT_CTX_QUERY 0xb2UL 209 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 210 #define HWRM_PORT_QSTATS_EXT 0xb4UL 211 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 212 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 213 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 214 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 215 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 216 #define HWRM_PORT_ECN_QSTATS 0xbaUL 217 #define HWRM_FW_RESET 0xc0UL 218 #define HWRM_FW_QSTATUS 0xc1UL 219 #define HWRM_FW_HEALTH_CHECK 0xc2UL 220 #define HWRM_FW_SYNC 0xc3UL 221 #define HWRM_FW_STATE_QCAPS 0xc4UL 222 #define HWRM_FW_STATE_QUIESCE 0xc5UL 223 #define HWRM_FW_STATE_BACKUP 0xc6UL 224 #define HWRM_FW_STATE_RESTORE 0xc7UL 225 #define HWRM_FW_SET_TIME 0xc8UL 226 #define HWRM_FW_GET_TIME 0xc9UL 227 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 228 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 229 #define HWRM_FW_IPC_MAILBOX 0xccUL 230 #define HWRM_FW_ECN_CFG 0xcdUL 231 #define HWRM_FW_ECN_QCFG 0xceUL 232 #define HWRM_FW_SECURE_CFG 0xcfUL 233 #define HWRM_EXEC_FWD_RESP 0xd0UL 234 #define HWRM_REJECT_FWD_RESP 0xd1UL 235 #define HWRM_FWD_RESP 0xd2UL 236 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 237 #define HWRM_OEM_CMD 0xd4UL 238 #define HWRM_PORT_PRBS_TEST 0xd5UL 239 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 240 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 241 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 242 #define HWRM_PORT_DSC_DUMP 0xd9UL 243 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 244 #define HWRM_REG_POWER_QUERY 0xe1UL 245 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 246 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 247 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 248 #define HWRM_WOL_FILTER_FREE 0xf1UL 249 #define HWRM_WOL_FILTER_QCFG 0xf2UL 250 #define HWRM_WOL_REASON_QCFG 0xf3UL 251 #define HWRM_CFA_METER_QCAPS 0xf4UL 252 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 253 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 254 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 255 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 256 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 257 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 258 #define HWRM_CFA_VFR_ALLOC 0xfdUL 259 #define HWRM_CFA_VFR_FREE 0xfeUL 260 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 261 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 262 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 263 #define HWRM_CFA_FLOW_ALLOC 0x103UL 264 #define HWRM_CFA_FLOW_FREE 0x104UL 265 #define HWRM_CFA_FLOW_FLUSH 0x105UL 266 #define HWRM_CFA_FLOW_STATS 0x106UL 267 #define HWRM_CFA_FLOW_INFO 0x107UL 268 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 269 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 270 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 271 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 272 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 273 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 274 #define HWRM_CFA_PAIR_FREE 0x10eUL 275 #define HWRM_CFA_PAIR_INFO 0x10fUL 276 #define HWRM_FW_IPC_MSG 0x110UL 277 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 278 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 279 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 280 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 281 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 282 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 283 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 284 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 285 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 286 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 287 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 288 #define HWRM_CFA_COUNTER_CFG 0x11cUL 289 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 290 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 291 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 292 #define HWRM_CFA_EEM_QCAPS 0x120UL 293 #define HWRM_CFA_EEM_CFG 0x121UL 294 #define HWRM_CFA_EEM_QCFG 0x122UL 295 #define HWRM_CFA_EEM_OP 0x123UL 296 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 297 #define HWRM_CFA_TFLIB 0x125UL 298 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 299 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 300 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 301 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 302 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 303 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 304 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 305 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 306 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 307 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 308 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 309 #define HWRM_ENGINE_QG_QUERY 0x13dUL 310 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 311 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 312 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 313 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 314 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 315 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 316 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 317 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 318 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 319 #define HWRM_ENGINE_SG_QUERY 0x147UL 320 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 321 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 322 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 323 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 324 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 325 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 326 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 327 #define HWRM_ENGINE_STATS_QUERY 0x157UL 328 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 329 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 330 #define HWRM_ENGINE_RQ_FREE 0x15fUL 331 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 332 #define HWRM_ENGINE_CQ_FREE 0x161UL 333 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 334 #define HWRM_ENGINE_NQ_FREE 0x163UL 335 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 336 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 337 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 338 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 339 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 340 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 341 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 342 #define HWRM_FUNC_VF_BW_CFG 0x195UL 343 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 344 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 345 #define HWRM_FUNC_QSTATS_EXT 0x198UL 346 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 347 #define HWRM_SELFTEST_QLIST 0x200UL 348 #define HWRM_SELFTEST_EXEC 0x201UL 349 #define HWRM_SELFTEST_IRQ 0x202UL 350 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 351 #define HWRM_PCIE_QSTATS 0x204UL 352 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 353 #define HWRM_MFG_TIMERS_QUERY 0x206UL 354 #define HWRM_MFG_OTP_CFG 0x207UL 355 #define HWRM_MFG_OTP_QCFG 0x208UL 356 #define HWRM_MFG_HDMA_TEST 0x209UL 357 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 358 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 359 #define HWRM_TF 0x2bcUL 360 #define HWRM_TF_VERSION_GET 0x2bdUL 361 #define HWRM_TF_SESSION_OPEN 0x2c6UL 362 #define HWRM_TF_SESSION_ATTACH 0x2c7UL 363 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 364 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 365 #define HWRM_TF_SESSION_CLOSE 0x2caUL 366 #define HWRM_TF_SESSION_QCFG 0x2cbUL 367 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 368 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 369 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 370 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 371 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 372 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 373 #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 374 #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 375 #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 376 #define HWRM_TF_EXT_EM_OP 0x2e7UL 377 #define HWRM_TF_EXT_EM_CFG 0x2e8UL 378 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 379 #define HWRM_TF_EM_INSERT 0x2eaUL 380 #define HWRM_TF_EM_DELETE 0x2ebUL 381 #define HWRM_TF_TCAM_SET 0x2f8UL 382 #define HWRM_TF_TCAM_GET 0x2f9UL 383 #define HWRM_TF_TCAM_MOVE 0x2faUL 384 #define HWRM_TF_TCAM_FREE 0x2fbUL 385 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 386 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 387 #define HWRM_SV 0x400UL 388 #define HWRM_DBG_READ_DIRECT 0xff10UL 389 #define HWRM_DBG_READ_INDIRECT 0xff11UL 390 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 391 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 392 #define HWRM_DBG_DUMP 0xff14UL 393 #define HWRM_DBG_ERASE_NVM 0xff15UL 394 #define HWRM_DBG_CFG 0xff16UL 395 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 396 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 397 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 398 #define HWRM_DBG_FW_CLI 0xff1aUL 399 #define HWRM_DBG_I2C_CMD 0xff1bUL 400 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 401 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 402 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 403 #define HWRM_DBG_DRV_TRACE 0xff1fUL 404 #define HWRM_DBG_QCAPS 0xff20UL 405 #define HWRM_DBG_QCFG 0xff21UL 406 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 407 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 408 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 409 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 410 #define HWRM_NVM_FLUSH 0xfff0UL 411 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 412 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 413 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 414 #define HWRM_NVM_MODIFY 0xfff4UL 415 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 416 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 417 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 418 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 419 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 420 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 421 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 422 #define HWRM_NVM_RAW_DUMP 0xfffcUL 423 #define HWRM_NVM_READ 0xfffdUL 424 #define HWRM_NVM_WRITE 0xfffeUL 425 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 426 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 427 __le16 unused_0[3]; 428 }; 429 430 /* ret_codes (size:64b/8B) */ 431 struct ret_codes { 432 __le16 error_code; 433 #define HWRM_ERR_CODE_SUCCESS 0x0UL 434 #define HWRM_ERR_CODE_FAIL 0x1UL 435 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 436 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 437 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 438 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 439 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 440 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 441 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 442 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 443 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 444 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 445 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 446 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 447 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 448 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 449 #define HWRM_ERR_CODE_BUSY 0x10UL 450 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 451 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 452 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 453 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 454 __le16 unused_0[3]; 455 }; 456 457 /* hwrm_err_output (size:128b/16B) */ 458 struct hwrm_err_output { 459 __le16 error_code; 460 __le16 req_type; 461 __le16 seq_id; 462 __le16 resp_len; 463 __le32 opaque_0; 464 __le16 opaque_1; 465 u8 cmd_err; 466 u8 valid; 467 }; 468 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 469 #define HWRM_MAX_REQ_LEN 128 470 #define HWRM_MAX_RESP_LEN 704 471 #define HW_HASH_INDEX_SIZE 0x80 472 #define HW_HASH_KEY_SIZE 40 473 #define HWRM_RESP_VALID_KEY 1 474 #define HWRM_TARGET_ID_BONO 0xFFF8 475 #define HWRM_TARGET_ID_KONG 0xFFF9 476 #define HWRM_TARGET_ID_APE 0xFFFA 477 #define HWRM_TARGET_ID_TOOLS 0xFFFD 478 #define HWRM_VERSION_MAJOR 1 479 #define HWRM_VERSION_MINOR 10 480 #define HWRM_VERSION_UPDATE 1 481 #define HWRM_VERSION_RSVD 54 482 #define HWRM_VERSION_STR "1.10.1.54" 483 484 /* hwrm_ver_get_input (size:192b/24B) */ 485 struct hwrm_ver_get_input { 486 __le16 req_type; 487 __le16 cmpl_ring; 488 __le16 seq_id; 489 __le16 target_id; 490 __le64 resp_addr; 491 u8 hwrm_intf_maj; 492 u8 hwrm_intf_min; 493 u8 hwrm_intf_upd; 494 u8 unused_0[5]; 495 }; 496 497 /* hwrm_ver_get_output (size:1408b/176B) */ 498 struct hwrm_ver_get_output { 499 __le16 error_code; 500 __le16 req_type; 501 __le16 seq_id; 502 __le16 resp_len; 503 u8 hwrm_intf_maj_8b; 504 u8 hwrm_intf_min_8b; 505 u8 hwrm_intf_upd_8b; 506 u8 hwrm_intf_rsvd_8b; 507 u8 hwrm_fw_maj_8b; 508 u8 hwrm_fw_min_8b; 509 u8 hwrm_fw_bld_8b; 510 u8 hwrm_fw_rsvd_8b; 511 u8 mgmt_fw_maj_8b; 512 u8 mgmt_fw_min_8b; 513 u8 mgmt_fw_bld_8b; 514 u8 mgmt_fw_rsvd_8b; 515 u8 netctrl_fw_maj_8b; 516 u8 netctrl_fw_min_8b; 517 u8 netctrl_fw_bld_8b; 518 u8 netctrl_fw_rsvd_8b; 519 __le32 dev_caps_cfg; 520 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 521 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 522 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 523 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 524 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 525 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 526 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 527 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 528 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 529 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 530 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 531 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 532 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 533 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 534 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 535 u8 roce_fw_maj_8b; 536 u8 roce_fw_min_8b; 537 u8 roce_fw_bld_8b; 538 u8 roce_fw_rsvd_8b; 539 char hwrm_fw_name[16]; 540 char mgmt_fw_name[16]; 541 char netctrl_fw_name[16]; 542 char active_pkg_name[16]; 543 char roce_fw_name[16]; 544 __le16 chip_num; 545 u8 chip_rev; 546 u8 chip_metal; 547 u8 chip_bond_id; 548 u8 chip_platform_type; 549 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 550 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 551 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 552 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 553 __le16 max_req_win_len; 554 __le16 max_resp_len; 555 __le16 def_req_timeout; 556 u8 flags; 557 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 558 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 559 u8 unused_0[2]; 560 u8 always_1; 561 __le16 hwrm_intf_major; 562 __le16 hwrm_intf_minor; 563 __le16 hwrm_intf_build; 564 __le16 hwrm_intf_patch; 565 __le16 hwrm_fw_major; 566 __le16 hwrm_fw_minor; 567 __le16 hwrm_fw_build; 568 __le16 hwrm_fw_patch; 569 __le16 mgmt_fw_major; 570 __le16 mgmt_fw_minor; 571 __le16 mgmt_fw_build; 572 __le16 mgmt_fw_patch; 573 __le16 netctrl_fw_major; 574 __le16 netctrl_fw_minor; 575 __le16 netctrl_fw_build; 576 __le16 netctrl_fw_patch; 577 __le16 roce_fw_major; 578 __le16 roce_fw_minor; 579 __le16 roce_fw_build; 580 __le16 roce_fw_patch; 581 __le16 max_ext_req_len; 582 u8 unused_1[5]; 583 u8 valid; 584 }; 585 586 /* eject_cmpl (size:128b/16B) */ 587 struct eject_cmpl { 588 __le16 type; 589 #define EJECT_CMPL_TYPE_MASK 0x3fUL 590 #define EJECT_CMPL_TYPE_SFT 0 591 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 592 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 593 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 594 #define EJECT_CMPL_FLAGS_SFT 6 595 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 596 __le16 len; 597 __le32 opaque; 598 __le16 v; 599 #define EJECT_CMPL_V 0x1UL 600 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 601 #define EJECT_CMPL_ERRORS_SFT 1 602 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 603 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 604 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 605 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 606 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 607 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 608 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 609 __le16 reserved16; 610 __le32 unused_2; 611 }; 612 613 /* hwrm_cmpl (size:128b/16B) */ 614 struct hwrm_cmpl { 615 __le16 type; 616 #define CMPL_TYPE_MASK 0x3fUL 617 #define CMPL_TYPE_SFT 0 618 #define CMPL_TYPE_HWRM_DONE 0x20UL 619 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 620 __le16 sequence_id; 621 __le32 unused_1; 622 __le32 v; 623 #define CMPL_V 0x1UL 624 __le32 unused_3; 625 }; 626 627 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 628 struct hwrm_fwd_req_cmpl { 629 __le16 req_len_type; 630 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 631 #define FWD_REQ_CMPL_TYPE_SFT 0 632 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 633 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 634 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 635 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 636 __le16 source_id; 637 __le32 unused0; 638 __le32 req_buf_addr_v[2]; 639 #define FWD_REQ_CMPL_V 0x1UL 640 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 641 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 642 }; 643 644 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 645 struct hwrm_fwd_resp_cmpl { 646 __le16 type; 647 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 648 #define FWD_RESP_CMPL_TYPE_SFT 0 649 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 650 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 651 __le16 source_id; 652 __le16 resp_len; 653 __le16 unused_1; 654 __le32 resp_buf_addr_v[2]; 655 #define FWD_RESP_CMPL_V 0x1UL 656 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 657 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 658 }; 659 660 /* hwrm_async_event_cmpl (size:128b/16B) */ 661 struct hwrm_async_event_cmpl { 662 __le16 type; 663 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 664 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 665 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 666 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 667 __le16 event_id; 668 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 669 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 670 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 671 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 672 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 673 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 674 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 675 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 676 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 677 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 678 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 679 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 680 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 681 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 682 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 683 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 684 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 685 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 686 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 687 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 688 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 689 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 690 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 691 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 692 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 693 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 694 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 695 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 696 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 697 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 698 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 699 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 700 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 701 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 702 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 703 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 704 __le32 event_data2; 705 u8 opaque_v; 706 #define ASYNC_EVENT_CMPL_V 0x1UL 707 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 708 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 709 u8 timestamp_lo; 710 __le16 timestamp_hi; 711 __le32 event_data1; 712 }; 713 714 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 715 struct hwrm_async_event_cmpl_link_status_change { 716 __le16 type; 717 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 718 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 719 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 720 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 721 __le16 event_id; 722 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 723 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 724 __le32 event_data2; 725 u8 opaque_v; 726 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 727 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 728 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 729 u8 timestamp_lo; 730 __le16 timestamp_hi; 731 __le32 event_data1; 732 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 733 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 734 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 735 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 736 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 737 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 738 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 739 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 740 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 741 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 742 }; 743 744 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 745 struct hwrm_async_event_cmpl_port_conn_not_allowed { 746 __le16 type; 747 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 748 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 749 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 750 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 751 __le16 event_id; 752 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 753 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 754 __le32 event_data2; 755 u8 opaque_v; 756 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 757 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 758 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 759 u8 timestamp_lo; 760 __le16 timestamp_hi; 761 __le32 event_data1; 762 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 763 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 764 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 765 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 766 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 767 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 768 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 769 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 770 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 771 }; 772 773 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 774 struct hwrm_async_event_cmpl_link_speed_cfg_change { 775 __le16 type; 776 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 777 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 778 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 779 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 780 __le16 event_id; 781 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 782 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 783 __le32 event_data2; 784 u8 opaque_v; 785 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 786 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 787 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 788 u8 timestamp_lo; 789 __le16 timestamp_hi; 790 __le32 event_data1; 791 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 792 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 793 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 794 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 795 }; 796 797 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 798 struct hwrm_async_event_cmpl_reset_notify { 799 __le16 type; 800 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 801 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 802 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 803 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 804 __le16 event_id; 805 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 806 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 807 __le32 event_data2; 808 u8 opaque_v; 809 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 810 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 811 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 812 u8 timestamp_lo; 813 __le16 timestamp_hi; 814 __le32 event_data1; 815 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 816 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 817 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 818 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 819 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 820 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 821 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 822 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 823 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 824 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 825 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 826 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 827 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 828 }; 829 830 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 831 struct hwrm_async_event_cmpl_error_recovery { 832 __le16 type; 833 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 834 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 835 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 836 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 837 __le16 event_id; 838 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 839 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 840 __le32 event_data2; 841 u8 opaque_v; 842 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 843 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 844 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 845 u8 timestamp_lo; 846 __le16 timestamp_hi; 847 __le32 event_data1; 848 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 849 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 850 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 851 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 852 }; 853 854 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 855 struct hwrm_async_event_cmpl_vf_cfg_change { 856 __le16 type; 857 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 858 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 859 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 860 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 861 __le16 event_id; 862 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 863 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 864 __le32 event_data2; 865 u8 opaque_v; 866 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 867 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 868 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 869 u8 timestamp_lo; 870 __le16 timestamp_hi; 871 __le32 event_data1; 872 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 873 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 874 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 875 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 876 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 877 }; 878 879 /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 880 struct hwrm_async_event_cmpl_default_vnic_change { 881 __le16 type; 882 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 883 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 884 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 885 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 886 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 887 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 888 __le16 event_id; 889 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 890 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 891 __le32 event_data2; 892 u8 opaque_v; 893 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 894 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 895 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 896 u8 timestamp_lo; 897 __le16 timestamp_hi; 898 __le32 event_data1; 899 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 900 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 901 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 902 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 903 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 904 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 905 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 906 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 907 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 908 }; 909 910 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 911 struct hwrm_async_event_cmpl_hw_flow_aged { 912 __le16 type; 913 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 914 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 915 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 916 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 917 __le16 event_id; 918 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 919 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 920 __le32 event_data2; 921 u8 opaque_v; 922 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 923 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 924 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 925 u8 timestamp_lo; 926 __le16 timestamp_hi; 927 __le32 event_data1; 928 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 929 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 930 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 931 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 932 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 933 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 934 }; 935 936 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 937 struct hwrm_async_event_cmpl_eem_cache_flush_req { 938 __le16 type; 939 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 940 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 941 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 942 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 943 __le16 event_id; 944 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 945 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 946 __le32 event_data2; 947 u8 opaque_v; 948 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 949 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 950 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 951 u8 timestamp_lo; 952 __le16 timestamp_hi; 953 __le32 event_data1; 954 }; 955 956 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 957 struct hwrm_async_event_cmpl_eem_cache_flush_done { 958 __le16 type; 959 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 960 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 961 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 962 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 963 __le16 event_id; 964 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 965 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 966 __le32 event_data2; 967 u8 opaque_v; 968 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 969 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 970 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 971 u8 timestamp_lo; 972 __le16 timestamp_hi; 973 __le32 event_data1; 974 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 975 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 976 }; 977 978 /* hwrm_func_reset_input (size:192b/24B) */ 979 struct hwrm_func_reset_input { 980 __le16 req_type; 981 __le16 cmpl_ring; 982 __le16 seq_id; 983 __le16 target_id; 984 __le64 resp_addr; 985 __le32 enables; 986 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 987 __le16 vf_id; 988 u8 func_reset_level; 989 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 990 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 991 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 992 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 993 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 994 u8 unused_0; 995 }; 996 997 /* hwrm_func_reset_output (size:128b/16B) */ 998 struct hwrm_func_reset_output { 999 __le16 error_code; 1000 __le16 req_type; 1001 __le16 seq_id; 1002 __le16 resp_len; 1003 u8 unused_0[7]; 1004 u8 valid; 1005 }; 1006 1007 /* hwrm_func_getfid_input (size:192b/24B) */ 1008 struct hwrm_func_getfid_input { 1009 __le16 req_type; 1010 __le16 cmpl_ring; 1011 __le16 seq_id; 1012 __le16 target_id; 1013 __le64 resp_addr; 1014 __le32 enables; 1015 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1016 __le16 pci_id; 1017 u8 unused_0[2]; 1018 }; 1019 1020 /* hwrm_func_getfid_output (size:128b/16B) */ 1021 struct hwrm_func_getfid_output { 1022 __le16 error_code; 1023 __le16 req_type; 1024 __le16 seq_id; 1025 __le16 resp_len; 1026 __le16 fid; 1027 u8 unused_0[5]; 1028 u8 valid; 1029 }; 1030 1031 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1032 struct hwrm_func_vf_alloc_input { 1033 __le16 req_type; 1034 __le16 cmpl_ring; 1035 __le16 seq_id; 1036 __le16 target_id; 1037 __le64 resp_addr; 1038 __le32 enables; 1039 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1040 __le16 first_vf_id; 1041 __le16 num_vfs; 1042 }; 1043 1044 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1045 struct hwrm_func_vf_alloc_output { 1046 __le16 error_code; 1047 __le16 req_type; 1048 __le16 seq_id; 1049 __le16 resp_len; 1050 __le16 first_vf_id; 1051 u8 unused_0[5]; 1052 u8 valid; 1053 }; 1054 1055 /* hwrm_func_vf_free_input (size:192b/24B) */ 1056 struct hwrm_func_vf_free_input { 1057 __le16 req_type; 1058 __le16 cmpl_ring; 1059 __le16 seq_id; 1060 __le16 target_id; 1061 __le64 resp_addr; 1062 __le32 enables; 1063 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1064 __le16 first_vf_id; 1065 __le16 num_vfs; 1066 }; 1067 1068 /* hwrm_func_vf_free_output (size:128b/16B) */ 1069 struct hwrm_func_vf_free_output { 1070 __le16 error_code; 1071 __le16 req_type; 1072 __le16 seq_id; 1073 __le16 resp_len; 1074 u8 unused_0[7]; 1075 u8 valid; 1076 }; 1077 1078 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1079 struct hwrm_func_vf_cfg_input { 1080 __le16 req_type; 1081 __le16 cmpl_ring; 1082 __le16 seq_id; 1083 __le16 target_id; 1084 __le64 resp_addr; 1085 __le32 enables; 1086 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1087 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1088 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1089 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1090 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1091 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1092 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1093 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1094 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1095 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1096 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1097 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1098 __le16 mtu; 1099 __le16 guest_vlan; 1100 __le16 async_event_cr; 1101 u8 dflt_mac_addr[6]; 1102 __le32 flags; 1103 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1104 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1105 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1106 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1107 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1108 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1109 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1110 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1111 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1112 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1113 __le16 num_rsscos_ctxs; 1114 __le16 num_cmpl_rings; 1115 __le16 num_tx_rings; 1116 __le16 num_rx_rings; 1117 __le16 num_l2_ctxs; 1118 __le16 num_vnics; 1119 __le16 num_stat_ctxs; 1120 __le16 num_hw_ring_grps; 1121 u8 unused_0[4]; 1122 }; 1123 1124 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1125 struct hwrm_func_vf_cfg_output { 1126 __le16 error_code; 1127 __le16 req_type; 1128 __le16 seq_id; 1129 __le16 resp_len; 1130 u8 unused_0[7]; 1131 u8 valid; 1132 }; 1133 1134 /* hwrm_func_qcaps_input (size:192b/24B) */ 1135 struct hwrm_func_qcaps_input { 1136 __le16 req_type; 1137 __le16 cmpl_ring; 1138 __le16 seq_id; 1139 __le16 target_id; 1140 __le64 resp_addr; 1141 __le16 fid; 1142 u8 unused_0[6]; 1143 }; 1144 1145 /* hwrm_func_qcaps_output (size:704b/88B) */ 1146 struct hwrm_func_qcaps_output { 1147 __le16 error_code; 1148 __le16 req_type; 1149 __le16 seq_id; 1150 __le16 resp_len; 1151 __le16 fid; 1152 __le16 port_id; 1153 __le32 flags; 1154 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1155 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1156 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1157 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1158 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1159 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1160 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1161 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1162 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1163 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1164 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1165 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1166 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1167 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1168 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1169 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1170 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1171 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1172 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1173 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1174 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1175 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1176 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1177 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1178 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1179 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1180 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1181 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1182 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1183 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1184 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1185 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1186 u8 mac_address[6]; 1187 __le16 max_rsscos_ctx; 1188 __le16 max_cmpl_rings; 1189 __le16 max_tx_rings; 1190 __le16 max_rx_rings; 1191 __le16 max_l2_ctxs; 1192 __le16 max_vnics; 1193 __le16 first_vf_id; 1194 __le16 max_vfs; 1195 __le16 max_stat_ctx; 1196 __le32 max_encap_records; 1197 __le32 max_decap_records; 1198 __le32 max_tx_em_flows; 1199 __le32 max_tx_wm_flows; 1200 __le32 max_rx_em_flows; 1201 __le32 max_rx_wm_flows; 1202 __le32 max_mcast_filters; 1203 __le32 max_flow_id; 1204 __le32 max_hw_ring_grps; 1205 __le16 max_sp_tx_rings; 1206 u8 unused_0[2]; 1207 __le32 flags_ext; 1208 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1209 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1210 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1211 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1212 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1213 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1214 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1215 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1216 u8 max_schqs; 1217 u8 unused_1[2]; 1218 u8 valid; 1219 }; 1220 1221 /* hwrm_func_qcfg_input (size:192b/24B) */ 1222 struct hwrm_func_qcfg_input { 1223 __le16 req_type; 1224 __le16 cmpl_ring; 1225 __le16 seq_id; 1226 __le16 target_id; 1227 __le64 resp_addr; 1228 __le16 fid; 1229 u8 unused_0[6]; 1230 }; 1231 1232 /* hwrm_func_qcfg_output (size:768b/96B) */ 1233 struct hwrm_func_qcfg_output { 1234 __le16 error_code; 1235 __le16 req_type; 1236 __le16 seq_id; 1237 __le16 resp_len; 1238 __le16 fid; 1239 __le16 port_id; 1240 __le16 vlan; 1241 __le16 flags; 1242 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1243 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1244 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1245 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1246 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1247 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1248 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1249 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1250 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1251 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1252 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1253 u8 mac_address[6]; 1254 __le16 pci_id; 1255 __le16 alloc_rsscos_ctx; 1256 __le16 alloc_cmpl_rings; 1257 __le16 alloc_tx_rings; 1258 __le16 alloc_rx_rings; 1259 __le16 alloc_l2_ctx; 1260 __le16 alloc_vnics; 1261 __le16 mtu; 1262 __le16 mru; 1263 __le16 stat_ctx_id; 1264 u8 port_partition_type; 1265 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1266 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1267 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1268 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1269 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1270 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1271 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1272 u8 port_pf_cnt; 1273 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1274 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1275 __le16 dflt_vnic_id; 1276 __le16 max_mtu_configured; 1277 __le32 min_bw; 1278 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1279 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1280 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1281 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1282 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1283 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1284 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1285 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1286 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1287 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1288 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1289 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1290 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1291 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1292 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1293 __le32 max_bw; 1294 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1295 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1296 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1297 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1298 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1299 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1300 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1301 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1302 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1303 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1304 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1305 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1306 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1307 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1308 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1309 u8 evb_mode; 1310 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1311 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1312 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1313 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1314 u8 options; 1315 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1316 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1317 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1318 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1319 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1320 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1321 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1322 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1323 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1324 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1325 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1326 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1327 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1328 __le16 alloc_vfs; 1329 __le32 alloc_mcast_filters; 1330 __le32 alloc_hw_ring_grps; 1331 __le16 alloc_sp_tx_rings; 1332 __le16 alloc_stat_ctx; 1333 __le16 alloc_msix; 1334 __le16 registered_vfs; 1335 __le16 l2_doorbell_bar_size_kb; 1336 u8 unused_1; 1337 u8 always_1; 1338 __le32 reset_addr_poll; 1339 __le16 legacy_l2_db_size_kb; 1340 __le16 svif_info; 1341 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1342 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1343 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 1344 u8 unused_2[7]; 1345 u8 valid; 1346 }; 1347 1348 /* hwrm_func_cfg_input (size:768b/96B) */ 1349 struct hwrm_func_cfg_input { 1350 __le16 req_type; 1351 __le16 cmpl_ring; 1352 __le16 seq_id; 1353 __le16 target_id; 1354 __le64 resp_addr; 1355 __le16 fid; 1356 __le16 num_msix; 1357 __le32 flags; 1358 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1359 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1360 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1361 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1362 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1363 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1364 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1365 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1366 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1367 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1368 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1369 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1370 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1371 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1372 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1373 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1374 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1375 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1376 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1377 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1378 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1379 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1380 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1381 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1382 __le32 enables; 1383 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1384 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1385 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1386 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1387 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1388 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1389 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1390 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1391 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1392 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1393 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1394 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1395 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1396 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1397 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1398 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1399 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1400 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1401 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1402 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1403 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1404 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1405 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1406 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1407 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 1408 __le16 mtu; 1409 __le16 mru; 1410 __le16 num_rsscos_ctxs; 1411 __le16 num_cmpl_rings; 1412 __le16 num_tx_rings; 1413 __le16 num_rx_rings; 1414 __le16 num_l2_ctxs; 1415 __le16 num_vnics; 1416 __le16 num_stat_ctxs; 1417 __le16 num_hw_ring_grps; 1418 u8 dflt_mac_addr[6]; 1419 __le16 dflt_vlan; 1420 __be32 dflt_ip_addr[4]; 1421 __le32 min_bw; 1422 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1423 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1424 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1425 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1426 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1427 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1428 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1429 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1430 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1431 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1432 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1433 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1434 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1435 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1436 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1437 __le32 max_bw; 1438 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1439 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1440 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1441 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1442 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1443 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1444 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1445 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1446 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1447 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1448 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1449 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1450 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1451 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1452 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1453 __le16 async_event_cr; 1454 u8 vlan_antispoof_mode; 1455 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1456 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1457 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1458 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1459 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1460 u8 allowed_vlan_pris; 1461 u8 evb_mode; 1462 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1463 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1464 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1465 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1466 u8 options; 1467 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1468 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1469 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1470 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1471 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1472 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1473 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1474 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1475 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1476 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1477 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1478 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1479 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1480 __le16 num_mcast_filters; 1481 __le16 schq_id; 1482 u8 unused_0[6]; 1483 }; 1484 1485 /* hwrm_func_cfg_output (size:128b/16B) */ 1486 struct hwrm_func_cfg_output { 1487 __le16 error_code; 1488 __le16 req_type; 1489 __le16 seq_id; 1490 __le16 resp_len; 1491 u8 unused_0[7]; 1492 u8 valid; 1493 }; 1494 1495 /* hwrm_func_qstats_input (size:192b/24B) */ 1496 struct hwrm_func_qstats_input { 1497 __le16 req_type; 1498 __le16 cmpl_ring; 1499 __le16 seq_id; 1500 __le16 target_id; 1501 __le64 resp_addr; 1502 __le16 fid; 1503 u8 flags; 1504 #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 1505 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1506 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1507 #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 1508 u8 unused_0[5]; 1509 }; 1510 1511 /* hwrm_func_qstats_output (size:1408b/176B) */ 1512 struct hwrm_func_qstats_output { 1513 __le16 error_code; 1514 __le16 req_type; 1515 __le16 seq_id; 1516 __le16 resp_len; 1517 __le64 tx_ucast_pkts; 1518 __le64 tx_mcast_pkts; 1519 __le64 tx_bcast_pkts; 1520 __le64 tx_discard_pkts; 1521 __le64 tx_drop_pkts; 1522 __le64 tx_ucast_bytes; 1523 __le64 tx_mcast_bytes; 1524 __le64 tx_bcast_bytes; 1525 __le64 rx_ucast_pkts; 1526 __le64 rx_mcast_pkts; 1527 __le64 rx_bcast_pkts; 1528 __le64 rx_discard_pkts; 1529 __le64 rx_drop_pkts; 1530 __le64 rx_ucast_bytes; 1531 __le64 rx_mcast_bytes; 1532 __le64 rx_bcast_bytes; 1533 __le64 rx_agg_pkts; 1534 __le64 rx_agg_bytes; 1535 __le64 rx_agg_events; 1536 __le64 rx_agg_aborts; 1537 u8 unused_0[7]; 1538 u8 valid; 1539 }; 1540 1541 /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1542 struct hwrm_func_qstats_ext_input { 1543 __le16 req_type; 1544 __le16 cmpl_ring; 1545 __le16 seq_id; 1546 __le16 target_id; 1547 __le64 resp_addr; 1548 __le16 fid; 1549 u8 flags; 1550 #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1551 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1552 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1553 #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1554 u8 unused_0[1]; 1555 __le32 enables; 1556 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 1557 __le16 schq_id; 1558 __le16 traffic_class; 1559 u8 unused_1[4]; 1560 }; 1561 1562 /* hwrm_func_qstats_ext_output (size:1472b/184B) */ 1563 struct hwrm_func_qstats_ext_output { 1564 __le16 error_code; 1565 __le16 req_type; 1566 __le16 seq_id; 1567 __le16 resp_len; 1568 __le64 rx_ucast_pkts; 1569 __le64 rx_mcast_pkts; 1570 __le64 rx_bcast_pkts; 1571 __le64 rx_discard_pkts; 1572 __le64 rx_error_pkts; 1573 __le64 rx_ucast_bytes; 1574 __le64 rx_mcast_bytes; 1575 __le64 rx_bcast_bytes; 1576 __le64 tx_ucast_pkts; 1577 __le64 tx_mcast_pkts; 1578 __le64 tx_bcast_pkts; 1579 __le64 tx_error_pkts; 1580 __le64 tx_discard_pkts; 1581 __le64 tx_ucast_bytes; 1582 __le64 tx_mcast_bytes; 1583 __le64 tx_bcast_bytes; 1584 __le64 rx_tpa_eligible_pkt; 1585 __le64 rx_tpa_eligible_bytes; 1586 __le64 rx_tpa_pkt; 1587 __le64 rx_tpa_bytes; 1588 __le64 rx_tpa_errors; 1589 u8 unused_0[7]; 1590 u8 valid; 1591 }; 1592 1593 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1594 struct hwrm_func_clr_stats_input { 1595 __le16 req_type; 1596 __le16 cmpl_ring; 1597 __le16 seq_id; 1598 __le16 target_id; 1599 __le64 resp_addr; 1600 __le16 fid; 1601 u8 unused_0[6]; 1602 }; 1603 1604 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1605 struct hwrm_func_clr_stats_output { 1606 __le16 error_code; 1607 __le16 req_type; 1608 __le16 seq_id; 1609 __le16 resp_len; 1610 u8 unused_0[7]; 1611 u8 valid; 1612 }; 1613 1614 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1615 struct hwrm_func_vf_resc_free_input { 1616 __le16 req_type; 1617 __le16 cmpl_ring; 1618 __le16 seq_id; 1619 __le16 target_id; 1620 __le64 resp_addr; 1621 __le16 vf_id; 1622 u8 unused_0[6]; 1623 }; 1624 1625 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1626 struct hwrm_func_vf_resc_free_output { 1627 __le16 error_code; 1628 __le16 req_type; 1629 __le16 seq_id; 1630 __le16 resp_len; 1631 u8 unused_0[7]; 1632 u8 valid; 1633 }; 1634 1635 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1636 struct hwrm_func_drv_rgtr_input { 1637 __le16 req_type; 1638 __le16 cmpl_ring; 1639 __le16 seq_id; 1640 __le16 target_id; 1641 __le64 resp_addr; 1642 __le32 flags; 1643 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1644 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1645 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1646 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1647 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1648 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1649 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1650 __le32 enables; 1651 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1652 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1653 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1654 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1655 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1656 __le16 os_type; 1657 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1658 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1659 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1660 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1661 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1662 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1663 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1664 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1665 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1666 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1667 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1668 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1669 u8 ver_maj_8b; 1670 u8 ver_min_8b; 1671 u8 ver_upd_8b; 1672 u8 unused_0[3]; 1673 __le32 timestamp; 1674 u8 unused_1[4]; 1675 __le32 vf_req_fwd[8]; 1676 __le32 async_event_fwd[8]; 1677 __le16 ver_maj; 1678 __le16 ver_min; 1679 __le16 ver_upd; 1680 __le16 ver_patch; 1681 }; 1682 1683 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1684 struct hwrm_func_drv_rgtr_output { 1685 __le16 error_code; 1686 __le16 req_type; 1687 __le16 seq_id; 1688 __le16 resp_len; 1689 __le32 flags; 1690 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1691 u8 unused_0[3]; 1692 u8 valid; 1693 }; 1694 1695 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1696 struct hwrm_func_drv_unrgtr_input { 1697 __le16 req_type; 1698 __le16 cmpl_ring; 1699 __le16 seq_id; 1700 __le16 target_id; 1701 __le64 resp_addr; 1702 __le32 flags; 1703 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1704 u8 unused_0[4]; 1705 }; 1706 1707 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1708 struct hwrm_func_drv_unrgtr_output { 1709 __le16 error_code; 1710 __le16 req_type; 1711 __le16 seq_id; 1712 __le16 resp_len; 1713 u8 unused_0[7]; 1714 u8 valid; 1715 }; 1716 1717 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1718 struct hwrm_func_buf_rgtr_input { 1719 __le16 req_type; 1720 __le16 cmpl_ring; 1721 __le16 seq_id; 1722 __le16 target_id; 1723 __le64 resp_addr; 1724 __le32 enables; 1725 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1726 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1727 __le16 vf_id; 1728 __le16 req_buf_num_pages; 1729 __le16 req_buf_page_size; 1730 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1731 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1732 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1733 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1734 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1735 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1736 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1737 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1738 __le16 req_buf_len; 1739 __le16 resp_buf_len; 1740 u8 unused_0[2]; 1741 __le64 req_buf_page_addr0; 1742 __le64 req_buf_page_addr1; 1743 __le64 req_buf_page_addr2; 1744 __le64 req_buf_page_addr3; 1745 __le64 req_buf_page_addr4; 1746 __le64 req_buf_page_addr5; 1747 __le64 req_buf_page_addr6; 1748 __le64 req_buf_page_addr7; 1749 __le64 req_buf_page_addr8; 1750 __le64 req_buf_page_addr9; 1751 __le64 error_buf_addr; 1752 __le64 resp_buf_addr; 1753 }; 1754 1755 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1756 struct hwrm_func_buf_rgtr_output { 1757 __le16 error_code; 1758 __le16 req_type; 1759 __le16 seq_id; 1760 __le16 resp_len; 1761 u8 unused_0[7]; 1762 u8 valid; 1763 }; 1764 1765 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1766 struct hwrm_func_drv_qver_input { 1767 __le16 req_type; 1768 __le16 cmpl_ring; 1769 __le16 seq_id; 1770 __le16 target_id; 1771 __le64 resp_addr; 1772 __le32 reserved; 1773 __le16 fid; 1774 u8 unused_0[2]; 1775 }; 1776 1777 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1778 struct hwrm_func_drv_qver_output { 1779 __le16 error_code; 1780 __le16 req_type; 1781 __le16 seq_id; 1782 __le16 resp_len; 1783 __le16 os_type; 1784 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1785 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1786 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1787 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1788 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1789 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1790 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1791 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1792 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1793 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1794 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1795 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1796 u8 ver_maj_8b; 1797 u8 ver_min_8b; 1798 u8 ver_upd_8b; 1799 u8 unused_0[3]; 1800 __le16 ver_maj; 1801 __le16 ver_min; 1802 __le16 ver_upd; 1803 __le16 ver_patch; 1804 u8 unused_1[7]; 1805 u8 valid; 1806 }; 1807 1808 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1809 struct hwrm_func_resource_qcaps_input { 1810 __le16 req_type; 1811 __le16 cmpl_ring; 1812 __le16 seq_id; 1813 __le16 target_id; 1814 __le64 resp_addr; 1815 __le16 fid; 1816 u8 unused_0[6]; 1817 }; 1818 1819 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1820 struct hwrm_func_resource_qcaps_output { 1821 __le16 error_code; 1822 __le16 req_type; 1823 __le16 seq_id; 1824 __le16 resp_len; 1825 __le16 max_vfs; 1826 __le16 max_msix; 1827 __le16 vf_reservation_strategy; 1828 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1829 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1830 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1831 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1832 __le16 min_rsscos_ctx; 1833 __le16 max_rsscos_ctx; 1834 __le16 min_cmpl_rings; 1835 __le16 max_cmpl_rings; 1836 __le16 min_tx_rings; 1837 __le16 max_tx_rings; 1838 __le16 min_rx_rings; 1839 __le16 max_rx_rings; 1840 __le16 min_l2_ctxs; 1841 __le16 max_l2_ctxs; 1842 __le16 min_vnics; 1843 __le16 max_vnics; 1844 __le16 min_stat_ctx; 1845 __le16 max_stat_ctx; 1846 __le16 min_hw_ring_grps; 1847 __le16 max_hw_ring_grps; 1848 __le16 max_tx_scheduler_inputs; 1849 __le16 flags; 1850 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1851 u8 unused_0[5]; 1852 u8 valid; 1853 }; 1854 1855 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1856 struct hwrm_func_vf_resource_cfg_input { 1857 __le16 req_type; 1858 __le16 cmpl_ring; 1859 __le16 seq_id; 1860 __le16 target_id; 1861 __le64 resp_addr; 1862 __le16 vf_id; 1863 __le16 max_msix; 1864 __le16 min_rsscos_ctx; 1865 __le16 max_rsscos_ctx; 1866 __le16 min_cmpl_rings; 1867 __le16 max_cmpl_rings; 1868 __le16 min_tx_rings; 1869 __le16 max_tx_rings; 1870 __le16 min_rx_rings; 1871 __le16 max_rx_rings; 1872 __le16 min_l2_ctxs; 1873 __le16 max_l2_ctxs; 1874 __le16 min_vnics; 1875 __le16 max_vnics; 1876 __le16 min_stat_ctx; 1877 __le16 max_stat_ctx; 1878 __le16 min_hw_ring_grps; 1879 __le16 max_hw_ring_grps; 1880 __le16 flags; 1881 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1882 u8 unused_0[2]; 1883 }; 1884 1885 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1886 struct hwrm_func_vf_resource_cfg_output { 1887 __le16 error_code; 1888 __le16 req_type; 1889 __le16 seq_id; 1890 __le16 resp_len; 1891 __le16 reserved_rsscos_ctx; 1892 __le16 reserved_cmpl_rings; 1893 __le16 reserved_tx_rings; 1894 __le16 reserved_rx_rings; 1895 __le16 reserved_l2_ctxs; 1896 __le16 reserved_vnics; 1897 __le16 reserved_stat_ctx; 1898 __le16 reserved_hw_ring_grps; 1899 u8 unused_0[7]; 1900 u8 valid; 1901 }; 1902 1903 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1904 struct hwrm_func_backing_store_qcaps_input { 1905 __le16 req_type; 1906 __le16 cmpl_ring; 1907 __le16 seq_id; 1908 __le16 target_id; 1909 __le64 resp_addr; 1910 }; 1911 1912 /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ 1913 struct hwrm_func_backing_store_qcaps_output { 1914 __le16 error_code; 1915 __le16 req_type; 1916 __le16 seq_id; 1917 __le16 resp_len; 1918 __le32 qp_max_entries; 1919 __le16 qp_min_qp1_entries; 1920 __le16 qp_max_l2_entries; 1921 __le16 qp_entry_size; 1922 __le16 srq_max_l2_entries; 1923 __le32 srq_max_entries; 1924 __le16 srq_entry_size; 1925 __le16 cq_max_l2_entries; 1926 __le32 cq_max_entries; 1927 __le16 cq_entry_size; 1928 __le16 vnic_max_vnic_entries; 1929 __le16 vnic_max_ring_table_entries; 1930 __le16 vnic_entry_size; 1931 __le32 stat_max_entries; 1932 __le16 stat_entry_size; 1933 __le16 tqm_entry_size; 1934 __le32 tqm_min_entries_per_ring; 1935 __le32 tqm_max_entries_per_ring; 1936 __le32 mrav_max_entries; 1937 __le16 mrav_entry_size; 1938 __le16 tim_entry_size; 1939 __le32 tim_max_entries; 1940 __le16 mrav_num_entries_units; 1941 u8 tqm_entries_multiple; 1942 u8 ctx_kind_initializer; 1943 __le32 rsvd; 1944 __le16 rsvd1; 1945 u8 tqm_fp_rings_count; 1946 u8 valid; 1947 }; 1948 1949 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1950 struct hwrm_func_backing_store_cfg_input { 1951 __le16 req_type; 1952 __le16 cmpl_ring; 1953 __le16 seq_id; 1954 __le16 target_id; 1955 __le64 resp_addr; 1956 __le32 flags; 1957 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1958 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 1959 __le32 enables; 1960 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1961 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1962 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1963 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1964 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1965 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1966 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1967 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1968 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1969 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1970 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1971 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1972 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1973 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1974 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1975 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1976 u8 qpc_pg_size_qpc_lvl; 1977 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1978 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1979 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1980 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1981 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1982 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1983 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1984 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1985 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1986 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1987 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1988 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1989 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1990 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1991 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1992 u8 srq_pg_size_srq_lvl; 1993 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1994 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1995 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1996 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1997 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1998 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1999 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 2000 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 2001 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 2002 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 2003 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 2004 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 2005 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 2006 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 2007 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 2008 u8 cq_pg_size_cq_lvl; 2009 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 2010 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 2011 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 2012 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 2013 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 2014 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 2015 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 2016 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 2017 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 2018 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 2019 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 2020 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 2021 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 2022 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 2023 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 2024 u8 vnic_pg_size_vnic_lvl; 2025 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 2026 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 2027 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 2028 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 2029 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 2030 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 2031 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 2032 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 2033 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 2034 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 2035 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 2036 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 2037 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 2038 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 2039 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 2040 u8 stat_pg_size_stat_lvl; 2041 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 2042 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 2043 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 2044 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 2045 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 2046 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 2047 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 2048 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 2049 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 2050 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 2051 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 2052 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 2053 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 2054 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 2055 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 2056 u8 tqm_sp_pg_size_tqm_sp_lvl; 2057 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 2058 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 2059 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 2060 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 2061 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 2062 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 2063 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 2064 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 2065 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 2066 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 2067 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 2068 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 2069 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 2070 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 2071 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 2072 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 2073 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 2074 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 2075 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 2076 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 2077 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 2078 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 2079 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 2080 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 2081 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 2082 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 2083 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 2084 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 2085 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 2086 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 2087 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 2088 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 2089 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 2090 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 2091 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 2092 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 2093 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 2094 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 2095 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 2096 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 2097 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 2098 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 2099 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 2100 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 2101 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 2102 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 2103 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 2104 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 2105 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 2106 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 2107 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 2108 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 2109 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 2110 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 2111 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 2112 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 2113 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 2114 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 2115 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 2116 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 2117 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 2118 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 2119 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 2120 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 2121 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 2122 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 2123 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 2124 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 2125 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 2126 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 2127 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 2128 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 2129 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 2130 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 2131 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 2132 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 2133 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 2134 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 2135 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 2136 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 2137 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 2138 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 2139 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 2140 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 2141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 2142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 2143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 2144 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 2145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 2146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 2147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 2148 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 2149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 2150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 2151 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 2152 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 2153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 2154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 2155 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 2156 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 2157 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 2158 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 2159 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 2160 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 2161 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 2162 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 2163 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 2164 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 2165 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 2166 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 2167 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 2168 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 2169 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 2170 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 2171 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 2172 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 2173 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 2174 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 2175 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 2176 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 2177 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 2178 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 2179 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 2180 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 2181 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 2182 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 2183 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 2184 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 2185 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 2186 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 2187 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 2188 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 2189 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 2190 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 2191 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 2192 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 2193 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 2194 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 2195 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 2196 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 2197 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 2198 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 2199 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 2200 u8 mrav_pg_size_mrav_lvl; 2201 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 2202 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 2203 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 2204 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 2205 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 2206 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 2207 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 2208 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 2209 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 2210 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 2211 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 2212 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 2213 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 2214 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 2215 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 2216 u8 tim_pg_size_tim_lvl; 2217 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 2218 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 2219 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 2220 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 2221 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 2222 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 2223 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 2224 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 2225 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 2226 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2227 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2228 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2229 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2230 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2231 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2232 __le64 qpc_page_dir; 2233 __le64 srq_page_dir; 2234 __le64 cq_page_dir; 2235 __le64 vnic_page_dir; 2236 __le64 stat_page_dir; 2237 __le64 tqm_sp_page_dir; 2238 __le64 tqm_ring0_page_dir; 2239 __le64 tqm_ring1_page_dir; 2240 __le64 tqm_ring2_page_dir; 2241 __le64 tqm_ring3_page_dir; 2242 __le64 tqm_ring4_page_dir; 2243 __le64 tqm_ring5_page_dir; 2244 __le64 tqm_ring6_page_dir; 2245 __le64 tqm_ring7_page_dir; 2246 __le64 mrav_page_dir; 2247 __le64 tim_page_dir; 2248 __le32 qp_num_entries; 2249 __le32 srq_num_entries; 2250 __le32 cq_num_entries; 2251 __le32 stat_num_entries; 2252 __le32 tqm_sp_num_entries; 2253 __le32 tqm_ring0_num_entries; 2254 __le32 tqm_ring1_num_entries; 2255 __le32 tqm_ring2_num_entries; 2256 __le32 tqm_ring3_num_entries; 2257 __le32 tqm_ring4_num_entries; 2258 __le32 tqm_ring5_num_entries; 2259 __le32 tqm_ring6_num_entries; 2260 __le32 tqm_ring7_num_entries; 2261 __le32 mrav_num_entries; 2262 __le32 tim_num_entries; 2263 __le16 qp_num_qp1_entries; 2264 __le16 qp_num_l2_entries; 2265 __le16 qp_entry_size; 2266 __le16 srq_num_l2_entries; 2267 __le16 srq_entry_size; 2268 __le16 cq_num_l2_entries; 2269 __le16 cq_entry_size; 2270 __le16 vnic_num_vnic_entries; 2271 __le16 vnic_num_ring_table_entries; 2272 __le16 vnic_entry_size; 2273 __le16 stat_entry_size; 2274 __le16 tqm_entry_size; 2275 __le16 mrav_entry_size; 2276 __le16 tim_entry_size; 2277 }; 2278 2279 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2280 struct hwrm_func_backing_store_cfg_output { 2281 __le16 error_code; 2282 __le16 req_type; 2283 __le16 seq_id; 2284 __le16 resp_len; 2285 u8 unused_0[7]; 2286 u8 valid; 2287 }; 2288 2289 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2290 struct hwrm_error_recovery_qcfg_input { 2291 __le16 req_type; 2292 __le16 cmpl_ring; 2293 __le16 seq_id; 2294 __le16 target_id; 2295 __le64 resp_addr; 2296 u8 unused_0[8]; 2297 }; 2298 2299 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2300 struct hwrm_error_recovery_qcfg_output { 2301 __le16 error_code; 2302 __le16 req_type; 2303 __le16 seq_id; 2304 __le16 resp_len; 2305 __le32 flags; 2306 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2307 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2308 __le32 driver_polling_freq; 2309 __le32 master_func_wait_period; 2310 __le32 normal_func_wait_period; 2311 __le32 master_func_wait_period_after_reset; 2312 __le32 max_bailout_time_after_reset; 2313 __le32 fw_health_status_reg; 2314 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2315 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2316 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2317 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2318 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2319 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2320 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2321 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2322 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2323 __le32 fw_heartbeat_reg; 2324 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2325 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2326 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2327 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2328 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2329 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2330 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2331 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2332 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2333 __le32 fw_reset_cnt_reg; 2334 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2335 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2336 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2337 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2338 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2339 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2340 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2341 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2342 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2343 __le32 reset_inprogress_reg; 2344 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2345 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2346 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2347 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2348 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2349 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2350 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2351 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2352 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2353 __le32 reset_inprogress_reg_mask; 2354 u8 unused_0[3]; 2355 u8 reg_array_cnt; 2356 __le32 reset_reg[16]; 2357 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2358 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2359 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2360 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2361 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2362 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2363 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2364 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2365 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2366 __le32 reset_reg_val[16]; 2367 u8 delay_after_reset[16]; 2368 __le32 err_recovery_cnt_reg; 2369 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2370 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2371 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2372 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2373 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2374 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2375 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2376 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2377 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2378 u8 unused_1[3]; 2379 u8 valid; 2380 }; 2381 2382 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2383 struct hwrm_func_drv_if_change_input { 2384 __le16 req_type; 2385 __le16 cmpl_ring; 2386 __le16 seq_id; 2387 __le16 target_id; 2388 __le64 resp_addr; 2389 __le32 flags; 2390 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2391 __le32 unused; 2392 }; 2393 2394 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2395 struct hwrm_func_drv_if_change_output { 2396 __le16 error_code; 2397 __le16 req_type; 2398 __le16 seq_id; 2399 __le16 resp_len; 2400 __le32 flags; 2401 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2402 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2403 u8 unused_0[3]; 2404 u8 valid; 2405 }; 2406 2407 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2408 struct hwrm_port_phy_cfg_input { 2409 __le16 req_type; 2410 __le16 cmpl_ring; 2411 __le16 seq_id; 2412 __le16 target_id; 2413 __le64 resp_addr; 2414 __le32 flags; 2415 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2416 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2417 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2418 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2419 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2420 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2421 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2422 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2423 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2424 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2425 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2426 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2427 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2428 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2429 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2430 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 2431 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 2432 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_2XN_ENABLE 0x20000UL 2433 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_2XN_DISABLE 0x40000UL 2434 __le32 enables; 2435 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2436 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2437 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2438 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2439 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2440 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2441 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2442 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2443 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2444 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2445 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2446 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 2447 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 2448 __le16 port_id; 2449 __le16 force_link_speed; 2450 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2451 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2452 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2453 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2454 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2455 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2456 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2457 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2458 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2459 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2460 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2461 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2462 u8 auto_mode; 2463 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2464 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2465 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2466 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2467 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2468 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2469 u8 auto_duplex; 2470 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2471 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2472 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2473 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2474 u8 auto_pause; 2475 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2476 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2477 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2478 u8 unused_0; 2479 __le16 auto_link_speed; 2480 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2481 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2482 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2483 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2484 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2485 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2486 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2487 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2488 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2489 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2490 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2491 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2492 __le16 auto_link_speed_mask; 2493 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2494 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2495 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2496 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2497 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2498 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2499 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2500 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2501 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2502 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2503 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2504 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2505 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2506 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2507 u8 wirespeed; 2508 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2509 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2510 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2511 u8 lpbk; 2512 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2513 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2514 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2515 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2516 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2517 u8 force_pause; 2518 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2519 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2520 u8 unused_1; 2521 __le32 preemphasis; 2522 __le16 eee_link_speed_mask; 2523 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2524 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2525 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2526 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2527 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2528 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2529 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2530 __le16 force_pam4_link_speed; 2531 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2532 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2533 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2534 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 2535 __le32 tx_lpi_timer; 2536 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2537 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2538 __le16 auto_link_pam4_speed_mask; 2539 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 2540 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 2541 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 2542 u8 unused_2[2]; 2543 }; 2544 2545 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2546 struct hwrm_port_phy_cfg_output { 2547 __le16 error_code; 2548 __le16 req_type; 2549 __le16 seq_id; 2550 __le16 resp_len; 2551 u8 unused_0[7]; 2552 u8 valid; 2553 }; 2554 2555 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2556 struct hwrm_port_phy_cfg_cmd_err { 2557 u8 code; 2558 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2559 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2560 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2561 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2562 u8 unused_0[7]; 2563 }; 2564 2565 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2566 struct hwrm_port_phy_qcfg_input { 2567 __le16 req_type; 2568 __le16 cmpl_ring; 2569 __le16 seq_id; 2570 __le16 target_id; 2571 __le64 resp_addr; 2572 __le16 port_id; 2573 u8 unused_0[6]; 2574 }; 2575 2576 /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 2577 struct hwrm_port_phy_qcfg_output { 2578 __le16 error_code; 2579 __le16 req_type; 2580 __le16 seq_id; 2581 __le16 resp_len; 2582 u8 link; 2583 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2584 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2585 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2586 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2587 u8 link_signal_mode; 2588 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL_MODE_NRZ 0x0UL 2589 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL_MODE_PAM4 0x1UL 2590 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_LINK_SIGNAL_MODE_PAM4 2591 __le16 link_speed; 2592 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2593 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2594 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2595 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2596 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2597 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2598 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2599 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2600 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2601 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2602 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2603 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2604 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2605 u8 duplex_cfg; 2606 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2607 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2608 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2609 u8 pause; 2610 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2611 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2612 __le16 support_speeds; 2613 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2614 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2615 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2616 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2617 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2618 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2619 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2620 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2621 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2622 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2623 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2624 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2625 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2626 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2627 __le16 force_link_speed; 2628 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2629 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2630 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2631 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2632 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2633 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2634 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2635 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2636 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2637 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2638 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2639 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2640 u8 auto_mode; 2641 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2642 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2643 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2644 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2645 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2646 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2647 u8 auto_pause; 2648 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2649 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2650 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2651 __le16 auto_link_speed; 2652 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2653 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2654 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2655 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2656 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2657 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2658 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2659 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2660 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2661 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2662 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2663 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2664 __le16 auto_link_speed_mask; 2665 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2666 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2667 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2668 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2669 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2670 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2671 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2672 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2673 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2674 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2675 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2676 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2677 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2678 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2679 u8 wirespeed; 2680 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2681 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2682 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2683 u8 lpbk; 2684 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2685 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2686 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2687 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2688 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2689 u8 force_pause; 2690 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2691 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2692 u8 module_status; 2693 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2694 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2695 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2696 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2697 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2698 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2699 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2700 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2701 __le32 preemphasis; 2702 u8 phy_maj; 2703 u8 phy_min; 2704 u8 phy_bld; 2705 u8 phy_type; 2706 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2707 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2708 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2709 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2710 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2711 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2712 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2713 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2714 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2715 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2716 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2717 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2718 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2719 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2720 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2721 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2722 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2723 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2724 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2725 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2726 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2727 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2728 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2729 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2730 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2731 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2732 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2733 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2734 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2735 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2736 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2737 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2738 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2739 u8 media_type; 2740 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2741 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2742 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2743 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2744 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2745 u8 xcvr_pkg_type; 2746 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2747 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2748 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2749 u8 eee_config_phy_addr; 2750 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2751 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2752 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2753 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2754 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2755 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2756 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2757 u8 parallel_detect; 2758 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2759 __le16 link_partner_adv_speeds; 2760 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2761 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2762 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2763 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2764 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2765 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2766 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2767 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2768 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2769 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2770 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2771 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2772 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2773 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2774 u8 link_partner_adv_auto_mode; 2775 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2776 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2777 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2778 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2779 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2780 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2781 u8 link_partner_adv_pause; 2782 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2783 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2784 __le16 adv_eee_link_speed_mask; 2785 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2786 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2787 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2788 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2789 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2790 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2791 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2792 __le16 link_partner_adv_eee_link_speed_mask; 2793 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2794 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2795 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2796 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2797 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2798 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2799 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2800 __le32 xcvr_identifier_type_tx_lpi_timer; 2801 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2802 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2803 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2804 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2805 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2806 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2807 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2808 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2809 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2810 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2811 __le16 fec_cfg; 2812 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2813 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2814 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2815 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2816 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2817 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2818 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2819 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 2820 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 2821 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_2XN_SUPPORTED 0x200UL 2822 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_2XN_ENABLED 0x400UL 2823 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ACTIVE 0x800UL 2824 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ACTIVE 0x1000UL 2825 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ACTIVE 0x2000UL 2826 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_2XN_ACTIVE 0x4000UL 2827 u8 duplex_state; 2828 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2829 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2830 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2831 u8 option_flags; 2832 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2833 char phy_vendor_name[16]; 2834 char phy_vendor_partnumber[16]; 2835 __le16 support_pam4_speeds; 2836 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 2837 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 2838 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 2839 __le16 force_pam4_link_speed; 2840 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2841 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2842 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2843 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 2844 __le16 auto_pam4_link_speed_mask; 2845 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 2846 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 2847 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 2848 __le16 link_partner_pam4_adv_speeds; 2849 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 2850 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 2851 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 2852 u8 unused_0[7]; 2853 u8 valid; 2854 }; 2855 2856 /* hwrm_port_mac_cfg_input (size:384b/48B) */ 2857 struct hwrm_port_mac_cfg_input { 2858 __le16 req_type; 2859 __le16 cmpl_ring; 2860 __le16 seq_id; 2861 __le16 target_id; 2862 __le64 resp_addr; 2863 __le32 flags; 2864 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2865 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2866 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2867 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2868 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2869 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2870 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2871 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2872 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2873 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2874 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2875 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2876 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2877 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 2878 __le32 enables; 2879 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2880 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2881 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2882 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2883 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2884 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2885 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2886 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2887 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 2888 __le16 port_id; 2889 u8 ipg; 2890 u8 lpbk; 2891 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2892 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2893 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2894 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2895 u8 vlan_pri2cos_map_pri; 2896 u8 reserved1; 2897 u8 tunnel_pri2cos_map_pri; 2898 u8 dscp2pri_map_pri; 2899 __le16 rx_ts_capture_ptp_msg_type; 2900 __le16 tx_ts_capture_ptp_msg_type; 2901 u8 cos_field_cfg; 2902 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2903 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2904 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2905 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2906 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2907 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2908 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2909 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2910 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2911 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2912 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2913 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2914 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2915 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2916 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2917 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2918 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2919 u8 unused_0[3]; 2920 __s32 ptp_freq_adj_ppb; 2921 u8 unused_1[4]; 2922 }; 2923 2924 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 2925 struct hwrm_port_mac_cfg_output { 2926 __le16 error_code; 2927 __le16 req_type; 2928 __le16 seq_id; 2929 __le16 resp_len; 2930 __le16 mru; 2931 __le16 mtu; 2932 u8 ipg; 2933 u8 lpbk; 2934 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2935 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2936 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2937 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2938 u8 unused_0; 2939 u8 valid; 2940 }; 2941 2942 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2943 struct hwrm_port_mac_ptp_qcfg_input { 2944 __le16 req_type; 2945 __le16 cmpl_ring; 2946 __le16 seq_id; 2947 __le16 target_id; 2948 __le64 resp_addr; 2949 __le16 port_id; 2950 u8 unused_0[6]; 2951 }; 2952 2953 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2954 struct hwrm_port_mac_ptp_qcfg_output { 2955 __le16 error_code; 2956 __le16 req_type; 2957 __le16 seq_id; 2958 __le16 resp_len; 2959 u8 flags; 2960 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2961 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 2962 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 2963 u8 unused_0[3]; 2964 __le32 rx_ts_reg_off_lower; 2965 __le32 rx_ts_reg_off_upper; 2966 __le32 rx_ts_reg_off_seq_id; 2967 __le32 rx_ts_reg_off_src_id_0; 2968 __le32 rx_ts_reg_off_src_id_1; 2969 __le32 rx_ts_reg_off_src_id_2; 2970 __le32 rx_ts_reg_off_domain_id; 2971 __le32 rx_ts_reg_off_fifo; 2972 __le32 rx_ts_reg_off_fifo_adv; 2973 __le32 rx_ts_reg_off_granularity; 2974 __le32 tx_ts_reg_off_lower; 2975 __le32 tx_ts_reg_off_upper; 2976 __le32 tx_ts_reg_off_seq_id; 2977 __le32 tx_ts_reg_off_fifo; 2978 __le32 tx_ts_reg_off_granularity; 2979 u8 unused_1[7]; 2980 u8 valid; 2981 }; 2982 2983 /* tx_port_stats (size:3264b/408B) */ 2984 struct tx_port_stats { 2985 __le64 tx_64b_frames; 2986 __le64 tx_65b_127b_frames; 2987 __le64 tx_128b_255b_frames; 2988 __le64 tx_256b_511b_frames; 2989 __le64 tx_512b_1023b_frames; 2990 __le64 tx_1024b_1518b_frames; 2991 __le64 tx_good_vlan_frames; 2992 __le64 tx_1519b_2047b_frames; 2993 __le64 tx_2048b_4095b_frames; 2994 __le64 tx_4096b_9216b_frames; 2995 __le64 tx_9217b_16383b_frames; 2996 __le64 tx_good_frames; 2997 __le64 tx_total_frames; 2998 __le64 tx_ucast_frames; 2999 __le64 tx_mcast_frames; 3000 __le64 tx_bcast_frames; 3001 __le64 tx_pause_frames; 3002 __le64 tx_pfc_frames; 3003 __le64 tx_jabber_frames; 3004 __le64 tx_fcs_err_frames; 3005 __le64 tx_control_frames; 3006 __le64 tx_oversz_frames; 3007 __le64 tx_single_dfrl_frames; 3008 __le64 tx_multi_dfrl_frames; 3009 __le64 tx_single_coll_frames; 3010 __le64 tx_multi_coll_frames; 3011 __le64 tx_late_coll_frames; 3012 __le64 tx_excessive_coll_frames; 3013 __le64 tx_frag_frames; 3014 __le64 tx_err; 3015 __le64 tx_tagged_frames; 3016 __le64 tx_dbl_tagged_frames; 3017 __le64 tx_runt_frames; 3018 __le64 tx_fifo_underruns; 3019 __le64 tx_pfc_ena_frames_pri0; 3020 __le64 tx_pfc_ena_frames_pri1; 3021 __le64 tx_pfc_ena_frames_pri2; 3022 __le64 tx_pfc_ena_frames_pri3; 3023 __le64 tx_pfc_ena_frames_pri4; 3024 __le64 tx_pfc_ena_frames_pri5; 3025 __le64 tx_pfc_ena_frames_pri6; 3026 __le64 tx_pfc_ena_frames_pri7; 3027 __le64 tx_eee_lpi_events; 3028 __le64 tx_eee_lpi_duration; 3029 __le64 tx_llfc_logical_msgs; 3030 __le64 tx_hcfc_msgs; 3031 __le64 tx_total_collisions; 3032 __le64 tx_bytes; 3033 __le64 tx_xthol_frames; 3034 __le64 tx_stat_discard; 3035 __le64 tx_stat_error; 3036 }; 3037 3038 /* rx_port_stats (size:4224b/528B) */ 3039 struct rx_port_stats { 3040 __le64 rx_64b_frames; 3041 __le64 rx_65b_127b_frames; 3042 __le64 rx_128b_255b_frames; 3043 __le64 rx_256b_511b_frames; 3044 __le64 rx_512b_1023b_frames; 3045 __le64 rx_1024b_1518b_frames; 3046 __le64 rx_good_vlan_frames; 3047 __le64 rx_1519b_2047b_frames; 3048 __le64 rx_2048b_4095b_frames; 3049 __le64 rx_4096b_9216b_frames; 3050 __le64 rx_9217b_16383b_frames; 3051 __le64 rx_total_frames; 3052 __le64 rx_ucast_frames; 3053 __le64 rx_mcast_frames; 3054 __le64 rx_bcast_frames; 3055 __le64 rx_fcs_err_frames; 3056 __le64 rx_ctrl_frames; 3057 __le64 rx_pause_frames; 3058 __le64 rx_pfc_frames; 3059 __le64 rx_unsupported_opcode_frames; 3060 __le64 rx_unsupported_da_pausepfc_frames; 3061 __le64 rx_wrong_sa_frames; 3062 __le64 rx_align_err_frames; 3063 __le64 rx_oor_len_frames; 3064 __le64 rx_code_err_frames; 3065 __le64 rx_false_carrier_frames; 3066 __le64 rx_ovrsz_frames; 3067 __le64 rx_jbr_frames; 3068 __le64 rx_mtu_err_frames; 3069 __le64 rx_match_crc_frames; 3070 __le64 rx_promiscuous_frames; 3071 __le64 rx_tagged_frames; 3072 __le64 rx_double_tagged_frames; 3073 __le64 rx_trunc_frames; 3074 __le64 rx_good_frames; 3075 __le64 rx_pfc_xon2xoff_frames_pri0; 3076 __le64 rx_pfc_xon2xoff_frames_pri1; 3077 __le64 rx_pfc_xon2xoff_frames_pri2; 3078 __le64 rx_pfc_xon2xoff_frames_pri3; 3079 __le64 rx_pfc_xon2xoff_frames_pri4; 3080 __le64 rx_pfc_xon2xoff_frames_pri5; 3081 __le64 rx_pfc_xon2xoff_frames_pri6; 3082 __le64 rx_pfc_xon2xoff_frames_pri7; 3083 __le64 rx_pfc_ena_frames_pri0; 3084 __le64 rx_pfc_ena_frames_pri1; 3085 __le64 rx_pfc_ena_frames_pri2; 3086 __le64 rx_pfc_ena_frames_pri3; 3087 __le64 rx_pfc_ena_frames_pri4; 3088 __le64 rx_pfc_ena_frames_pri5; 3089 __le64 rx_pfc_ena_frames_pri6; 3090 __le64 rx_pfc_ena_frames_pri7; 3091 __le64 rx_sch_crc_err_frames; 3092 __le64 rx_undrsz_frames; 3093 __le64 rx_frag_frames; 3094 __le64 rx_eee_lpi_events; 3095 __le64 rx_eee_lpi_duration; 3096 __le64 rx_llfc_physical_msgs; 3097 __le64 rx_llfc_logical_msgs; 3098 __le64 rx_llfc_msgs_with_crc_err; 3099 __le64 rx_hcfc_msgs; 3100 __le64 rx_hcfc_msgs_with_crc_err; 3101 __le64 rx_bytes; 3102 __le64 rx_runt_bytes; 3103 __le64 rx_runt_frames; 3104 __le64 rx_stat_discard; 3105 __le64 rx_stat_err; 3106 }; 3107 3108 /* hwrm_port_qstats_input (size:320b/40B) */ 3109 struct hwrm_port_qstats_input { 3110 __le16 req_type; 3111 __le16 cmpl_ring; 3112 __le16 seq_id; 3113 __le16 target_id; 3114 __le64 resp_addr; 3115 __le16 port_id; 3116 u8 flags; 3117 #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3118 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3119 #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3120 u8 unused_0[5]; 3121 __le64 tx_stat_host_addr; 3122 __le64 rx_stat_host_addr; 3123 }; 3124 3125 /* hwrm_port_qstats_output (size:128b/16B) */ 3126 struct hwrm_port_qstats_output { 3127 __le16 error_code; 3128 __le16 req_type; 3129 __le16 seq_id; 3130 __le16 resp_len; 3131 __le16 tx_stat_size; 3132 __le16 rx_stat_size; 3133 u8 unused_0[3]; 3134 u8 valid; 3135 }; 3136 3137 /* tx_port_stats_ext (size:2048b/256B) */ 3138 struct tx_port_stats_ext { 3139 __le64 tx_bytes_cos0; 3140 __le64 tx_bytes_cos1; 3141 __le64 tx_bytes_cos2; 3142 __le64 tx_bytes_cos3; 3143 __le64 tx_bytes_cos4; 3144 __le64 tx_bytes_cos5; 3145 __le64 tx_bytes_cos6; 3146 __le64 tx_bytes_cos7; 3147 __le64 tx_packets_cos0; 3148 __le64 tx_packets_cos1; 3149 __le64 tx_packets_cos2; 3150 __le64 tx_packets_cos3; 3151 __le64 tx_packets_cos4; 3152 __le64 tx_packets_cos5; 3153 __le64 tx_packets_cos6; 3154 __le64 tx_packets_cos7; 3155 __le64 pfc_pri0_tx_duration_us; 3156 __le64 pfc_pri0_tx_transitions; 3157 __le64 pfc_pri1_tx_duration_us; 3158 __le64 pfc_pri1_tx_transitions; 3159 __le64 pfc_pri2_tx_duration_us; 3160 __le64 pfc_pri2_tx_transitions; 3161 __le64 pfc_pri3_tx_duration_us; 3162 __le64 pfc_pri3_tx_transitions; 3163 __le64 pfc_pri4_tx_duration_us; 3164 __le64 pfc_pri4_tx_transitions; 3165 __le64 pfc_pri5_tx_duration_us; 3166 __le64 pfc_pri5_tx_transitions; 3167 __le64 pfc_pri6_tx_duration_us; 3168 __le64 pfc_pri6_tx_transitions; 3169 __le64 pfc_pri7_tx_duration_us; 3170 __le64 pfc_pri7_tx_transitions; 3171 }; 3172 3173 /* rx_port_stats_ext (size:3648b/456B) */ 3174 struct rx_port_stats_ext { 3175 __le64 link_down_events; 3176 __le64 continuous_pause_events; 3177 __le64 resume_pause_events; 3178 __le64 continuous_roce_pause_events; 3179 __le64 resume_roce_pause_events; 3180 __le64 rx_bytes_cos0; 3181 __le64 rx_bytes_cos1; 3182 __le64 rx_bytes_cos2; 3183 __le64 rx_bytes_cos3; 3184 __le64 rx_bytes_cos4; 3185 __le64 rx_bytes_cos5; 3186 __le64 rx_bytes_cos6; 3187 __le64 rx_bytes_cos7; 3188 __le64 rx_packets_cos0; 3189 __le64 rx_packets_cos1; 3190 __le64 rx_packets_cos2; 3191 __le64 rx_packets_cos3; 3192 __le64 rx_packets_cos4; 3193 __le64 rx_packets_cos5; 3194 __le64 rx_packets_cos6; 3195 __le64 rx_packets_cos7; 3196 __le64 pfc_pri0_rx_duration_us; 3197 __le64 pfc_pri0_rx_transitions; 3198 __le64 pfc_pri1_rx_duration_us; 3199 __le64 pfc_pri1_rx_transitions; 3200 __le64 pfc_pri2_rx_duration_us; 3201 __le64 pfc_pri2_rx_transitions; 3202 __le64 pfc_pri3_rx_duration_us; 3203 __le64 pfc_pri3_rx_transitions; 3204 __le64 pfc_pri4_rx_duration_us; 3205 __le64 pfc_pri4_rx_transitions; 3206 __le64 pfc_pri5_rx_duration_us; 3207 __le64 pfc_pri5_rx_transitions; 3208 __le64 pfc_pri6_rx_duration_us; 3209 __le64 pfc_pri6_rx_transitions; 3210 __le64 pfc_pri7_rx_duration_us; 3211 __le64 pfc_pri7_rx_transitions; 3212 __le64 rx_bits; 3213 __le64 rx_buffer_passed_threshold; 3214 __le64 rx_pcs_symbol_err; 3215 __le64 rx_corrected_bits; 3216 __le64 rx_discard_bytes_cos0; 3217 __le64 rx_discard_bytes_cos1; 3218 __le64 rx_discard_bytes_cos2; 3219 __le64 rx_discard_bytes_cos3; 3220 __le64 rx_discard_bytes_cos4; 3221 __le64 rx_discard_bytes_cos5; 3222 __le64 rx_discard_bytes_cos6; 3223 __le64 rx_discard_bytes_cos7; 3224 __le64 rx_discard_packets_cos0; 3225 __le64 rx_discard_packets_cos1; 3226 __le64 rx_discard_packets_cos2; 3227 __le64 rx_discard_packets_cos3; 3228 __le64 rx_discard_packets_cos4; 3229 __le64 rx_discard_packets_cos5; 3230 __le64 rx_discard_packets_cos6; 3231 __le64 rx_discard_packets_cos7; 3232 }; 3233 3234 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3235 struct hwrm_port_qstats_ext_input { 3236 __le16 req_type; 3237 __le16 cmpl_ring; 3238 __le16 seq_id; 3239 __le16 target_id; 3240 __le64 resp_addr; 3241 __le16 port_id; 3242 __le16 tx_stat_size; 3243 __le16 rx_stat_size; 3244 u8 flags; 3245 #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3246 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3247 #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3248 u8 unused_0; 3249 __le64 tx_stat_host_addr; 3250 __le64 rx_stat_host_addr; 3251 }; 3252 3253 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3254 struct hwrm_port_qstats_ext_output { 3255 __le16 error_code; 3256 __le16 req_type; 3257 __le16 seq_id; 3258 __le16 resp_len; 3259 __le16 tx_stat_size; 3260 __le16 rx_stat_size; 3261 __le16 total_active_cos_queues; 3262 u8 flags; 3263 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3264 u8 valid; 3265 }; 3266 3267 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3268 struct hwrm_port_lpbk_qstats_input { 3269 __le16 req_type; 3270 __le16 cmpl_ring; 3271 __le16 seq_id; 3272 __le16 target_id; 3273 __le64 resp_addr; 3274 }; 3275 3276 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3277 struct hwrm_port_lpbk_qstats_output { 3278 __le16 error_code; 3279 __le16 req_type; 3280 __le16 seq_id; 3281 __le16 resp_len; 3282 __le64 lpbk_ucast_frames; 3283 __le64 lpbk_mcast_frames; 3284 __le64 lpbk_bcast_frames; 3285 __le64 lpbk_ucast_bytes; 3286 __le64 lpbk_mcast_bytes; 3287 __le64 lpbk_bcast_bytes; 3288 __le64 tx_stat_discard; 3289 __le64 tx_stat_error; 3290 __le64 rx_stat_discard; 3291 __le64 rx_stat_error; 3292 u8 unused_0[7]; 3293 u8 valid; 3294 }; 3295 3296 /* hwrm_port_clr_stats_input (size:192b/24B) */ 3297 struct hwrm_port_clr_stats_input { 3298 __le16 req_type; 3299 __le16 cmpl_ring; 3300 __le16 seq_id; 3301 __le16 target_id; 3302 __le64 resp_addr; 3303 __le16 port_id; 3304 u8 flags; 3305 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3306 u8 unused_0[5]; 3307 }; 3308 3309 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3310 struct hwrm_port_clr_stats_output { 3311 __le16 error_code; 3312 __le16 req_type; 3313 __le16 seq_id; 3314 __le16 resp_len; 3315 u8 unused_0[7]; 3316 u8 valid; 3317 }; 3318 3319 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3320 struct hwrm_port_lpbk_clr_stats_input { 3321 __le16 req_type; 3322 __le16 cmpl_ring; 3323 __le16 seq_id; 3324 __le16 target_id; 3325 __le64 resp_addr; 3326 }; 3327 3328 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3329 struct hwrm_port_lpbk_clr_stats_output { 3330 __le16 error_code; 3331 __le16 req_type; 3332 __le16 seq_id; 3333 __le16 resp_len; 3334 u8 unused_0[7]; 3335 u8 valid; 3336 }; 3337 3338 /* hwrm_port_ts_query_input (size:192b/24B) */ 3339 struct hwrm_port_ts_query_input { 3340 __le16 req_type; 3341 __le16 cmpl_ring; 3342 __le16 seq_id; 3343 __le16 target_id; 3344 __le64 resp_addr; 3345 __le32 flags; 3346 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 3347 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 3348 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 3349 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 3350 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 3351 __le16 port_id; 3352 u8 unused_0[2]; 3353 }; 3354 3355 /* hwrm_port_ts_query_output (size:192b/24B) */ 3356 struct hwrm_port_ts_query_output { 3357 __le16 error_code; 3358 __le16 req_type; 3359 __le16 seq_id; 3360 __le16 resp_len; 3361 __le64 ptp_msg_ts; 3362 __le16 ptp_msg_seqid; 3363 u8 unused_0[5]; 3364 u8 valid; 3365 }; 3366 3367 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3368 struct hwrm_port_phy_qcaps_input { 3369 __le16 req_type; 3370 __le16 cmpl_ring; 3371 __le16 seq_id; 3372 __le16 target_id; 3373 __le64 resp_addr; 3374 __le16 port_id; 3375 u8 unused_0[6]; 3376 }; 3377 3378 /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 3379 struct hwrm_port_phy_qcaps_output { 3380 __le16 error_code; 3381 __le16 req_type; 3382 __le16 seq_id; 3383 __le16 resp_len; 3384 u8 flags; 3385 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3386 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3387 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 3388 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3389 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 3390 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xe0UL 3391 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 5 3392 u8 port_cnt; 3393 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3394 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3395 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3396 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3397 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3398 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3399 __le16 supported_speeds_force_mode; 3400 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3401 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3402 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3403 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3404 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3405 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3406 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3407 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3408 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3409 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3410 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3411 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3412 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3413 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3414 __le16 supported_speeds_auto_mode; 3415 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3416 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3417 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3418 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3419 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3420 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3421 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3422 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3423 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3424 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3425 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3426 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3427 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3428 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3429 __le16 supported_speeds_eee_mode; 3430 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3431 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3432 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3433 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3434 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3435 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3436 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3437 __le32 tx_lpi_timer_low; 3438 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3439 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3440 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3441 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3442 __le32 valid_tx_lpi_timer_high; 3443 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3444 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3445 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 3446 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 3447 __le16 supported_pam4_speeds_auto_mode; 3448 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 3449 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 3450 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 3451 __le16 supported_pam4_speeds_force_mode; 3452 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 3453 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 3454 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 3455 u8 unused_0[3]; 3456 u8 valid; 3457 }; 3458 3459 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3460 struct hwrm_port_phy_i2c_read_input { 3461 __le16 req_type; 3462 __le16 cmpl_ring; 3463 __le16 seq_id; 3464 __le16 target_id; 3465 __le64 resp_addr; 3466 __le32 flags; 3467 __le32 enables; 3468 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3469 __le16 port_id; 3470 u8 i2c_slave_addr; 3471 u8 unused_0; 3472 __le16 page_number; 3473 __le16 page_offset; 3474 u8 data_length; 3475 u8 unused_1[7]; 3476 }; 3477 3478 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3479 struct hwrm_port_phy_i2c_read_output { 3480 __le16 error_code; 3481 __le16 req_type; 3482 __le16 seq_id; 3483 __le16 resp_len; 3484 __le32 data[16]; 3485 u8 unused_0[7]; 3486 u8 valid; 3487 }; 3488 3489 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3490 struct hwrm_port_phy_mdio_write_input { 3491 __le16 req_type; 3492 __le16 cmpl_ring; 3493 __le16 seq_id; 3494 __le16 target_id; 3495 __le64 resp_addr; 3496 __le32 unused_0[2]; 3497 __le16 port_id; 3498 u8 phy_addr; 3499 u8 dev_addr; 3500 __le16 reg_addr; 3501 __le16 reg_data; 3502 u8 cl45_mdio; 3503 u8 unused_1[7]; 3504 }; 3505 3506 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3507 struct hwrm_port_phy_mdio_write_output { 3508 __le16 error_code; 3509 __le16 req_type; 3510 __le16 seq_id; 3511 __le16 resp_len; 3512 u8 unused_0[7]; 3513 u8 valid; 3514 }; 3515 3516 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3517 struct hwrm_port_phy_mdio_read_input { 3518 __le16 req_type; 3519 __le16 cmpl_ring; 3520 __le16 seq_id; 3521 __le16 target_id; 3522 __le64 resp_addr; 3523 __le32 unused_0[2]; 3524 __le16 port_id; 3525 u8 phy_addr; 3526 u8 dev_addr; 3527 __le16 reg_addr; 3528 u8 cl45_mdio; 3529 u8 unused_1; 3530 }; 3531 3532 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3533 struct hwrm_port_phy_mdio_read_output { 3534 __le16 error_code; 3535 __le16 req_type; 3536 __le16 seq_id; 3537 __le16 resp_len; 3538 __le16 reg_data; 3539 u8 unused_0[5]; 3540 u8 valid; 3541 }; 3542 3543 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3544 struct hwrm_port_led_cfg_input { 3545 __le16 req_type; 3546 __le16 cmpl_ring; 3547 __le16 seq_id; 3548 __le16 target_id; 3549 __le64 resp_addr; 3550 __le32 enables; 3551 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3552 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3553 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3554 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3555 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3556 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3557 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3558 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3559 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3560 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3561 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3562 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3563 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3564 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3565 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3566 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3567 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3568 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3569 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3570 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3571 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3572 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3573 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3574 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3575 __le16 port_id; 3576 u8 num_leds; 3577 u8 rsvd; 3578 u8 led0_id; 3579 u8 led0_state; 3580 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3581 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3582 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3583 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3584 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3585 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3586 u8 led0_color; 3587 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3588 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3589 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3590 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3591 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3592 u8 unused_0; 3593 __le16 led0_blink_on; 3594 __le16 led0_blink_off; 3595 u8 led0_group_id; 3596 u8 rsvd0; 3597 u8 led1_id; 3598 u8 led1_state; 3599 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3600 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3601 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3602 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3603 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3604 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3605 u8 led1_color; 3606 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3607 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3608 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3609 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3610 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3611 u8 unused_1; 3612 __le16 led1_blink_on; 3613 __le16 led1_blink_off; 3614 u8 led1_group_id; 3615 u8 rsvd1; 3616 u8 led2_id; 3617 u8 led2_state; 3618 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3619 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3620 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3621 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3622 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3623 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3624 u8 led2_color; 3625 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3626 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3627 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3628 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3629 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3630 u8 unused_2; 3631 __le16 led2_blink_on; 3632 __le16 led2_blink_off; 3633 u8 led2_group_id; 3634 u8 rsvd2; 3635 u8 led3_id; 3636 u8 led3_state; 3637 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3638 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3639 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3640 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3641 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3642 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3643 u8 led3_color; 3644 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3645 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3646 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3647 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3648 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3649 u8 unused_3; 3650 __le16 led3_blink_on; 3651 __le16 led3_blink_off; 3652 u8 led3_group_id; 3653 u8 rsvd3; 3654 }; 3655 3656 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3657 struct hwrm_port_led_cfg_output { 3658 __le16 error_code; 3659 __le16 req_type; 3660 __le16 seq_id; 3661 __le16 resp_len; 3662 u8 unused_0[7]; 3663 u8 valid; 3664 }; 3665 3666 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3667 struct hwrm_port_led_qcfg_input { 3668 __le16 req_type; 3669 __le16 cmpl_ring; 3670 __le16 seq_id; 3671 __le16 target_id; 3672 __le64 resp_addr; 3673 __le16 port_id; 3674 u8 unused_0[6]; 3675 }; 3676 3677 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3678 struct hwrm_port_led_qcfg_output { 3679 __le16 error_code; 3680 __le16 req_type; 3681 __le16 seq_id; 3682 __le16 resp_len; 3683 u8 num_leds; 3684 u8 led0_id; 3685 u8 led0_type; 3686 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3687 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3688 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3689 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3690 u8 led0_state; 3691 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3692 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3693 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3694 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3695 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3696 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3697 u8 led0_color; 3698 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3699 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3700 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3701 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3702 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3703 u8 unused_0; 3704 __le16 led0_blink_on; 3705 __le16 led0_blink_off; 3706 u8 led0_group_id; 3707 u8 led1_id; 3708 u8 led1_type; 3709 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3710 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3711 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3712 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3713 u8 led1_state; 3714 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3715 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3716 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3717 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3718 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3719 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3720 u8 led1_color; 3721 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3722 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3723 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3724 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3725 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3726 u8 unused_1; 3727 __le16 led1_blink_on; 3728 __le16 led1_blink_off; 3729 u8 led1_group_id; 3730 u8 led2_id; 3731 u8 led2_type; 3732 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3733 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3734 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3735 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3736 u8 led2_state; 3737 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3738 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3739 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3740 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3741 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3742 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3743 u8 led2_color; 3744 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3745 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3746 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3747 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3748 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3749 u8 unused_2; 3750 __le16 led2_blink_on; 3751 __le16 led2_blink_off; 3752 u8 led2_group_id; 3753 u8 led3_id; 3754 u8 led3_type; 3755 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3756 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3757 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3758 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3759 u8 led3_state; 3760 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3761 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3762 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3763 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3764 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3765 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3766 u8 led3_color; 3767 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3768 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3769 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3770 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3771 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3772 u8 unused_3; 3773 __le16 led3_blink_on; 3774 __le16 led3_blink_off; 3775 u8 led3_group_id; 3776 u8 unused_4[6]; 3777 u8 valid; 3778 }; 3779 3780 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3781 struct hwrm_port_led_qcaps_input { 3782 __le16 req_type; 3783 __le16 cmpl_ring; 3784 __le16 seq_id; 3785 __le16 target_id; 3786 __le64 resp_addr; 3787 __le16 port_id; 3788 u8 unused_0[6]; 3789 }; 3790 3791 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3792 struct hwrm_port_led_qcaps_output { 3793 __le16 error_code; 3794 __le16 req_type; 3795 __le16 seq_id; 3796 __le16 resp_len; 3797 u8 num_leds; 3798 u8 unused[3]; 3799 u8 led0_id; 3800 u8 led0_type; 3801 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3802 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3803 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3804 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3805 u8 led0_group_id; 3806 u8 unused_0; 3807 __le16 led0_state_caps; 3808 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3809 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3810 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3811 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3812 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3813 __le16 led0_color_caps; 3814 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3815 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3816 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3817 u8 led1_id; 3818 u8 led1_type; 3819 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3820 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3821 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3822 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3823 u8 led1_group_id; 3824 u8 unused_1; 3825 __le16 led1_state_caps; 3826 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3827 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3828 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3829 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3830 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3831 __le16 led1_color_caps; 3832 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3833 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3834 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3835 u8 led2_id; 3836 u8 led2_type; 3837 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3838 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3839 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3840 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3841 u8 led2_group_id; 3842 u8 unused_2; 3843 __le16 led2_state_caps; 3844 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3845 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3846 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3847 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3848 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3849 __le16 led2_color_caps; 3850 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3851 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3852 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3853 u8 led3_id; 3854 u8 led3_type; 3855 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3856 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3857 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3858 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3859 u8 led3_group_id; 3860 u8 unused_3; 3861 __le16 led3_state_caps; 3862 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3863 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3864 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3865 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3866 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3867 __le16 led3_color_caps; 3868 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3869 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3870 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3871 u8 unused_4[3]; 3872 u8 valid; 3873 }; 3874 3875 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 3876 struct hwrm_queue_qportcfg_input { 3877 __le16 req_type; 3878 __le16 cmpl_ring; 3879 __le16 seq_id; 3880 __le16 target_id; 3881 __le64 resp_addr; 3882 __le32 flags; 3883 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3884 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3885 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3886 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3887 __le16 port_id; 3888 u8 drv_qmap_cap; 3889 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3890 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3891 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3892 u8 unused_0; 3893 }; 3894 3895 /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 3896 struct hwrm_queue_qportcfg_output { 3897 __le16 error_code; 3898 __le16 req_type; 3899 __le16 seq_id; 3900 __le16 resp_len; 3901 u8 max_configurable_queues; 3902 u8 max_configurable_lossless_queues; 3903 u8 queue_cfg_allowed; 3904 u8 queue_cfg_info; 3905 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3906 u8 queue_pfcenable_cfg_allowed; 3907 u8 queue_pri2cos_cfg_allowed; 3908 u8 queue_cos2bw_cfg_allowed; 3909 u8 queue_id0; 3910 u8 queue_id0_service_profile; 3911 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3912 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3913 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3914 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3915 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3916 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3917 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3918 u8 queue_id1; 3919 u8 queue_id1_service_profile; 3920 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3921 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3922 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3923 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3924 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3925 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3926 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3927 u8 queue_id2; 3928 u8 queue_id2_service_profile; 3929 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3930 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3931 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3932 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3933 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3934 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3935 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3936 u8 queue_id3; 3937 u8 queue_id3_service_profile; 3938 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3939 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3940 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3941 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3942 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3943 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3944 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3945 u8 queue_id4; 3946 u8 queue_id4_service_profile; 3947 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3948 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3949 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3950 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3951 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3952 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3953 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3954 u8 queue_id5; 3955 u8 queue_id5_service_profile; 3956 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3957 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3958 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3959 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3960 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3961 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3962 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3963 u8 queue_id6; 3964 u8 queue_id6_service_profile; 3965 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3966 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3967 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3968 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3969 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3970 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3971 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3972 u8 queue_id7; 3973 u8 queue_id7_service_profile; 3974 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3975 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3976 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3977 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3978 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3979 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3980 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3981 u8 unused_0; 3982 char qid0_name[16]; 3983 char qid1_name[16]; 3984 char qid2_name[16]; 3985 char qid3_name[16]; 3986 char qid4_name[16]; 3987 char qid5_name[16]; 3988 char qid6_name[16]; 3989 char qid7_name[16]; 3990 u8 unused_1[7]; 3991 u8 valid; 3992 }; 3993 3994 /* hwrm_queue_qcfg_input (size:192b/24B) */ 3995 struct hwrm_queue_qcfg_input { 3996 __le16 req_type; 3997 __le16 cmpl_ring; 3998 __le16 seq_id; 3999 __le16 target_id; 4000 __le64 resp_addr; 4001 __le32 flags; 4002 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4003 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4004 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4005 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4006 __le32 queue_id; 4007 }; 4008 4009 /* hwrm_queue_qcfg_output (size:128b/16B) */ 4010 struct hwrm_queue_qcfg_output { 4011 __le16 error_code; 4012 __le16 req_type; 4013 __le16 seq_id; 4014 __le16 resp_len; 4015 __le32 queue_len; 4016 u8 service_profile; 4017 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4018 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4019 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4020 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4021 u8 queue_cfg_info; 4022 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4023 u8 unused_0; 4024 u8 valid; 4025 }; 4026 4027 /* hwrm_queue_cfg_input (size:320b/40B) */ 4028 struct hwrm_queue_cfg_input { 4029 __le16 req_type; 4030 __le16 cmpl_ring; 4031 __le16 seq_id; 4032 __le16 target_id; 4033 __le64 resp_addr; 4034 __le32 flags; 4035 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4036 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4037 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4038 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4039 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4040 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4041 __le32 enables; 4042 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4043 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4044 __le32 queue_id; 4045 __le32 dflt_len; 4046 u8 service_profile; 4047 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4048 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4049 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4050 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4051 u8 unused_0[7]; 4052 }; 4053 4054 /* hwrm_queue_cfg_output (size:128b/16B) */ 4055 struct hwrm_queue_cfg_output { 4056 __le16 error_code; 4057 __le16 req_type; 4058 __le16 seq_id; 4059 __le16 resp_len; 4060 u8 unused_0[7]; 4061 u8 valid; 4062 }; 4063 4064 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 4065 struct hwrm_queue_pfcenable_qcfg_input { 4066 __le16 req_type; 4067 __le16 cmpl_ring; 4068 __le16 seq_id; 4069 __le16 target_id; 4070 __le64 resp_addr; 4071 __le16 port_id; 4072 u8 unused_0[6]; 4073 }; 4074 4075 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 4076 struct hwrm_queue_pfcenable_qcfg_output { 4077 __le16 error_code; 4078 __le16 req_type; 4079 __le16 seq_id; 4080 __le16 resp_len; 4081 __le32 flags; 4082 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 4083 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 4084 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 4085 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 4086 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 4087 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 4088 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 4089 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 4090 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4091 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4092 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4093 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4094 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4095 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4096 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4097 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4098 u8 unused_0[3]; 4099 u8 valid; 4100 }; 4101 4102 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 4103 struct hwrm_queue_pfcenable_cfg_input { 4104 __le16 req_type; 4105 __le16 cmpl_ring; 4106 __le16 seq_id; 4107 __le16 target_id; 4108 __le64 resp_addr; 4109 __le32 flags; 4110 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 4111 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 4112 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 4113 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 4114 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 4115 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 4116 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 4117 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 4118 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4119 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4120 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4121 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4122 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4123 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4124 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4125 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4126 __le16 port_id; 4127 u8 unused_0[2]; 4128 }; 4129 4130 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4131 struct hwrm_queue_pfcenable_cfg_output { 4132 __le16 error_code; 4133 __le16 req_type; 4134 __le16 seq_id; 4135 __le16 resp_len; 4136 u8 unused_0[7]; 4137 u8 valid; 4138 }; 4139 4140 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 4141 struct hwrm_queue_pri2cos_qcfg_input { 4142 __le16 req_type; 4143 __le16 cmpl_ring; 4144 __le16 seq_id; 4145 __le16 target_id; 4146 __le64 resp_addr; 4147 __le32 flags; 4148 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4149 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4150 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4151 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 4152 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 4153 u8 port_id; 4154 u8 unused_0[3]; 4155 }; 4156 4157 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 4158 struct hwrm_queue_pri2cos_qcfg_output { 4159 __le16 error_code; 4160 __le16 req_type; 4161 __le16 seq_id; 4162 __le16 resp_len; 4163 u8 pri0_cos_queue_id; 4164 u8 pri1_cos_queue_id; 4165 u8 pri2_cos_queue_id; 4166 u8 pri3_cos_queue_id; 4167 u8 pri4_cos_queue_id; 4168 u8 pri5_cos_queue_id; 4169 u8 pri6_cos_queue_id; 4170 u8 pri7_cos_queue_id; 4171 u8 queue_cfg_info; 4172 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4173 u8 unused_0[6]; 4174 u8 valid; 4175 }; 4176 4177 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4178 struct hwrm_queue_pri2cos_cfg_input { 4179 __le16 req_type; 4180 __le16 cmpl_ring; 4181 __le16 seq_id; 4182 __le16 target_id; 4183 __le64 resp_addr; 4184 __le32 flags; 4185 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4186 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4187 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4188 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4189 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4190 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4191 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4192 __le32 enables; 4193 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4194 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4195 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4196 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4197 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4198 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4199 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4200 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4201 u8 port_id; 4202 u8 pri0_cos_queue_id; 4203 u8 pri1_cos_queue_id; 4204 u8 pri2_cos_queue_id; 4205 u8 pri3_cos_queue_id; 4206 u8 pri4_cos_queue_id; 4207 u8 pri5_cos_queue_id; 4208 u8 pri6_cos_queue_id; 4209 u8 pri7_cos_queue_id; 4210 u8 unused_0[7]; 4211 }; 4212 4213 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4214 struct hwrm_queue_pri2cos_cfg_output { 4215 __le16 error_code; 4216 __le16 req_type; 4217 __le16 seq_id; 4218 __le16 resp_len; 4219 u8 unused_0[7]; 4220 u8 valid; 4221 }; 4222 4223 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 4224 struct hwrm_queue_cos2bw_qcfg_input { 4225 __le16 req_type; 4226 __le16 cmpl_ring; 4227 __le16 seq_id; 4228 __le16 target_id; 4229 __le64 resp_addr; 4230 __le16 port_id; 4231 u8 unused_0[6]; 4232 }; 4233 4234 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 4235 struct hwrm_queue_cos2bw_qcfg_output { 4236 __le16 error_code; 4237 __le16 req_type; 4238 __le16 seq_id; 4239 __le16 resp_len; 4240 u8 queue_id0; 4241 u8 unused_0; 4242 __le16 unused_1; 4243 __le32 queue_id0_min_bw; 4244 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4245 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4246 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4247 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4248 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4249 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 4250 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4251 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4252 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4253 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4254 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4255 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4256 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4257 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4258 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4259 __le32 queue_id0_max_bw; 4260 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4261 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4262 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4263 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4264 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4265 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 4266 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4267 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4268 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4269 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4270 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4271 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4272 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4273 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4274 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4275 u8 queue_id0_tsa_assign; 4276 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4277 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4278 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4279 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4280 u8 queue_id0_pri_lvl; 4281 u8 queue_id0_bw_weight; 4282 u8 queue_id1; 4283 __le32 queue_id1_min_bw; 4284 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4285 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4286 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4287 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4288 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4289 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 4290 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4291 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4292 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4293 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4294 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4295 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4296 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4297 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4298 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4299 __le32 queue_id1_max_bw; 4300 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4301 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4302 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4303 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4304 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4305 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 4306 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4307 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4308 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4309 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4310 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4311 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4312 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4313 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4314 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4315 u8 queue_id1_tsa_assign; 4316 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4317 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4318 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4319 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4320 u8 queue_id1_pri_lvl; 4321 u8 queue_id1_bw_weight; 4322 u8 queue_id2; 4323 __le32 queue_id2_min_bw; 4324 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4325 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4326 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4327 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4328 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4329 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 4330 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4331 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4332 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4333 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4334 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4335 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4336 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4337 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4338 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4339 __le32 queue_id2_max_bw; 4340 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4341 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4342 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4343 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4344 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4345 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 4346 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4347 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4348 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4349 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4350 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4351 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4352 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4353 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4354 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4355 u8 queue_id2_tsa_assign; 4356 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4357 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4358 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4359 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4360 u8 queue_id2_pri_lvl; 4361 u8 queue_id2_bw_weight; 4362 u8 queue_id3; 4363 __le32 queue_id3_min_bw; 4364 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4365 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4366 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4367 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4368 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4369 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 4370 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4371 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4372 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4373 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4374 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4375 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4376 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4377 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4378 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4379 __le32 queue_id3_max_bw; 4380 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4381 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4382 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4383 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4384 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4385 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 4386 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4387 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4388 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4389 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4390 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4391 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4392 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4393 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4394 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4395 u8 queue_id3_tsa_assign; 4396 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4397 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4398 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4399 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4400 u8 queue_id3_pri_lvl; 4401 u8 queue_id3_bw_weight; 4402 u8 queue_id4; 4403 __le32 queue_id4_min_bw; 4404 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4405 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4406 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4407 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4408 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4409 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4410 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4411 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4412 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4413 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4414 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4415 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4416 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4417 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4418 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4419 __le32 queue_id4_max_bw; 4420 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4421 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4422 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4423 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4424 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4425 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4426 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4427 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4428 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4429 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4430 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4431 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4432 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4433 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4434 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4435 u8 queue_id4_tsa_assign; 4436 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4437 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4438 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4439 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4440 u8 queue_id4_pri_lvl; 4441 u8 queue_id4_bw_weight; 4442 u8 queue_id5; 4443 __le32 queue_id5_min_bw; 4444 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4445 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4446 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4447 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4448 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4449 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4450 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4451 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4452 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4453 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4454 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4455 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4456 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4457 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4458 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4459 __le32 queue_id5_max_bw; 4460 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4461 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4462 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4463 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4464 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4465 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4466 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4467 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4468 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4469 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4475 u8 queue_id5_tsa_assign; 4476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4480 u8 queue_id5_pri_lvl; 4481 u8 queue_id5_bw_weight; 4482 u8 queue_id6; 4483 __le32 queue_id6_min_bw; 4484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4499 __le32 queue_id6_max_bw; 4500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4501 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4502 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4515 u8 queue_id6_tsa_assign; 4516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4520 u8 queue_id6_pri_lvl; 4521 u8 queue_id6_bw_weight; 4522 u8 queue_id7; 4523 __le32 queue_id7_min_bw; 4524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4539 __le32 queue_id7_max_bw; 4540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4541 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4542 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4547 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4548 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4549 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4550 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4555 u8 queue_id7_tsa_assign; 4556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4560 u8 queue_id7_pri_lvl; 4561 u8 queue_id7_bw_weight; 4562 u8 unused_2[4]; 4563 u8 valid; 4564 }; 4565 4566 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4567 struct hwrm_queue_cos2bw_cfg_input { 4568 __le16 req_type; 4569 __le16 cmpl_ring; 4570 __le16 seq_id; 4571 __le16 target_id; 4572 __le64 resp_addr; 4573 __le32 flags; 4574 __le32 enables; 4575 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4576 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4577 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4578 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4579 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4580 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4581 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4582 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4583 __le16 port_id; 4584 u8 queue_id0; 4585 u8 unused_0; 4586 __le32 queue_id0_min_bw; 4587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4598 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4602 __le32 queue_id0_max_bw; 4603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4614 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4618 u8 queue_id0_tsa_assign; 4619 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4620 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4621 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4622 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4623 u8 queue_id0_pri_lvl; 4624 u8 queue_id0_bw_weight; 4625 u8 queue_id1; 4626 __le32 queue_id1_min_bw; 4627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4639 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4642 __le32 queue_id1_max_bw; 4643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4655 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4658 u8 queue_id1_tsa_assign; 4659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4660 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4661 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4662 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4663 u8 queue_id1_pri_lvl; 4664 u8 queue_id1_bw_weight; 4665 u8 queue_id2; 4666 __le32 queue_id2_min_bw; 4667 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4668 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4669 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4670 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4671 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4672 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4673 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4674 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4675 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4676 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4677 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4678 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4679 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4680 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4681 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4682 __le32 queue_id2_max_bw; 4683 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4684 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4685 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4686 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4687 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4688 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4689 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4690 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4691 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4692 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4693 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4694 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4695 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4696 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4697 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4698 u8 queue_id2_tsa_assign; 4699 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4700 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4701 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4702 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4703 u8 queue_id2_pri_lvl; 4704 u8 queue_id2_bw_weight; 4705 u8 queue_id3; 4706 __le32 queue_id3_min_bw; 4707 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4708 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4709 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4710 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4711 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4712 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4713 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4714 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4715 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4716 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4717 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4718 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4719 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4720 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4721 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4722 __le32 queue_id3_max_bw; 4723 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4724 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4725 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4726 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4727 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4728 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4729 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4730 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4731 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4732 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4733 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4734 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4735 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4736 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4737 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4738 u8 queue_id3_tsa_assign; 4739 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4740 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4741 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4742 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4743 u8 queue_id3_pri_lvl; 4744 u8 queue_id3_bw_weight; 4745 u8 queue_id4; 4746 __le32 queue_id4_min_bw; 4747 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4748 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4749 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4750 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4751 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4752 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4753 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4754 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4755 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4756 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4757 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4758 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4759 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4760 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4761 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4762 __le32 queue_id4_max_bw; 4763 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4764 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4765 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4766 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4767 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4768 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4769 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4770 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4771 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4772 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4773 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4774 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4775 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4776 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4777 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4778 u8 queue_id4_tsa_assign; 4779 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4780 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4781 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4782 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4783 u8 queue_id4_pri_lvl; 4784 u8 queue_id4_bw_weight; 4785 u8 queue_id5; 4786 __le32 queue_id5_min_bw; 4787 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4788 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4789 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4790 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4791 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4792 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4793 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4794 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4795 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4796 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4797 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4798 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4799 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4800 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4801 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4802 __le32 queue_id5_max_bw; 4803 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4804 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4805 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4806 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4807 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4808 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4809 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4810 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4811 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4812 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4813 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4814 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4815 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4816 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4818 u8 queue_id5_tsa_assign; 4819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4820 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4823 u8 queue_id5_pri_lvl; 4824 u8 queue_id5_bw_weight; 4825 u8 queue_id6; 4826 __le32 queue_id6_min_bw; 4827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4836 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4842 __le32 queue_id6_max_bw; 4843 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4844 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4845 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4846 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4858 u8 queue_id6_tsa_assign; 4859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4863 u8 queue_id6_pri_lvl; 4864 u8 queue_id6_bw_weight; 4865 u8 queue_id7; 4866 __le32 queue_id7_min_bw; 4867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4882 __le32 queue_id7_max_bw; 4883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4885 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4892 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4893 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4894 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4898 u8 queue_id7_tsa_assign; 4899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4903 u8 queue_id7_pri_lvl; 4904 u8 queue_id7_bw_weight; 4905 u8 unused_1[5]; 4906 }; 4907 4908 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4909 struct hwrm_queue_cos2bw_cfg_output { 4910 __le16 error_code; 4911 __le16 req_type; 4912 __le16 seq_id; 4913 __le16 resp_len; 4914 u8 unused_0[7]; 4915 u8 valid; 4916 }; 4917 4918 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4919 struct hwrm_queue_dscp_qcaps_input { 4920 __le16 req_type; 4921 __le16 cmpl_ring; 4922 __le16 seq_id; 4923 __le16 target_id; 4924 __le64 resp_addr; 4925 u8 port_id; 4926 u8 unused_0[7]; 4927 }; 4928 4929 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4930 struct hwrm_queue_dscp_qcaps_output { 4931 __le16 error_code; 4932 __le16 req_type; 4933 __le16 seq_id; 4934 __le16 resp_len; 4935 u8 num_dscp_bits; 4936 u8 unused_0; 4937 __le16 max_entries; 4938 u8 unused_1[3]; 4939 u8 valid; 4940 }; 4941 4942 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4943 struct hwrm_queue_dscp2pri_qcfg_input { 4944 __le16 req_type; 4945 __le16 cmpl_ring; 4946 __le16 seq_id; 4947 __le16 target_id; 4948 __le64 resp_addr; 4949 __le64 dest_data_addr; 4950 u8 port_id; 4951 u8 unused_0; 4952 __le16 dest_data_buffer_size; 4953 u8 unused_1[4]; 4954 }; 4955 4956 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4957 struct hwrm_queue_dscp2pri_qcfg_output { 4958 __le16 error_code; 4959 __le16 req_type; 4960 __le16 seq_id; 4961 __le16 resp_len; 4962 __le16 entry_cnt; 4963 u8 default_pri; 4964 u8 unused_0[4]; 4965 u8 valid; 4966 }; 4967 4968 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4969 struct hwrm_queue_dscp2pri_cfg_input { 4970 __le16 req_type; 4971 __le16 cmpl_ring; 4972 __le16 seq_id; 4973 __le16 target_id; 4974 __le64 resp_addr; 4975 __le64 src_data_addr; 4976 __le32 flags; 4977 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4978 __le32 enables; 4979 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4980 u8 port_id; 4981 u8 default_pri; 4982 __le16 entry_cnt; 4983 u8 unused_0[4]; 4984 }; 4985 4986 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4987 struct hwrm_queue_dscp2pri_cfg_output { 4988 __le16 error_code; 4989 __le16 req_type; 4990 __le16 seq_id; 4991 __le16 resp_len; 4992 u8 unused_0[7]; 4993 u8 valid; 4994 }; 4995 4996 /* hwrm_vnic_alloc_input (size:192b/24B) */ 4997 struct hwrm_vnic_alloc_input { 4998 __le16 req_type; 4999 __le16 cmpl_ring; 5000 __le16 seq_id; 5001 __le16 target_id; 5002 __le64 resp_addr; 5003 __le32 flags; 5004 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5005 u8 unused_0[4]; 5006 }; 5007 5008 /* hwrm_vnic_alloc_output (size:128b/16B) */ 5009 struct hwrm_vnic_alloc_output { 5010 __le16 error_code; 5011 __le16 req_type; 5012 __le16 seq_id; 5013 __le16 resp_len; 5014 __le32 vnic_id; 5015 u8 unused_0[3]; 5016 u8 valid; 5017 }; 5018 5019 /* hwrm_vnic_free_input (size:192b/24B) */ 5020 struct hwrm_vnic_free_input { 5021 __le16 req_type; 5022 __le16 cmpl_ring; 5023 __le16 seq_id; 5024 __le16 target_id; 5025 __le64 resp_addr; 5026 __le32 vnic_id; 5027 u8 unused_0[4]; 5028 }; 5029 5030 /* hwrm_vnic_free_output (size:128b/16B) */ 5031 struct hwrm_vnic_free_output { 5032 __le16 error_code; 5033 __le16 req_type; 5034 __le16 seq_id; 5035 __le16 resp_len; 5036 u8 unused_0[7]; 5037 u8 valid; 5038 }; 5039 5040 /* hwrm_vnic_cfg_input (size:384b/48B) */ 5041 struct hwrm_vnic_cfg_input { 5042 __le16 req_type; 5043 __le16 cmpl_ring; 5044 __le16 seq_id; 5045 __le16 target_id; 5046 __le64 resp_addr; 5047 __le32 flags; 5048 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5049 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5050 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 5051 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 5052 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5053 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 5054 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5055 __le32 enables; 5056 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5057 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5058 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5059 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5060 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 5061 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 5062 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 5063 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5064 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5065 __le16 vnic_id; 5066 __le16 dflt_ring_grp; 5067 __le16 rss_rule; 5068 __le16 cos_rule; 5069 __le16 lb_rule; 5070 __le16 mru; 5071 __le16 default_rx_ring_id; 5072 __le16 default_cmpl_ring_id; 5073 __le16 queue_id; 5074 u8 rx_csum_v2_mode; 5075 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 5076 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 5077 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 5078 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 5079 u8 unused0[5]; 5080 }; 5081 5082 /* hwrm_vnic_cfg_output (size:128b/16B) */ 5083 struct hwrm_vnic_cfg_output { 5084 __le16 error_code; 5085 __le16 req_type; 5086 __le16 seq_id; 5087 __le16 resp_len; 5088 u8 unused_0[7]; 5089 u8 valid; 5090 }; 5091 5092 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 5093 struct hwrm_vnic_qcaps_input { 5094 __le16 req_type; 5095 __le16 cmpl_ring; 5096 __le16 seq_id; 5097 __le16 target_id; 5098 __le64 resp_addr; 5099 __le32 enables; 5100 u8 unused_0[4]; 5101 }; 5102 5103 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 5104 struct hwrm_vnic_qcaps_output { 5105 __le16 error_code; 5106 __le16 req_type; 5107 __le16 seq_id; 5108 __le16 resp_len; 5109 __le16 mru; 5110 u8 unused_0[2]; 5111 __le32 flags; 5112 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 5113 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 5114 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 5115 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 5116 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 5117 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 5118 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 5119 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 5120 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5121 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5122 __le16 max_aggs_supported; 5123 u8 unused_1[5]; 5124 u8 valid; 5125 }; 5126 5127 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 5128 struct hwrm_vnic_tpa_cfg_input { 5129 __le16 req_type; 5130 __le16 cmpl_ring; 5131 __le16 seq_id; 5132 __le16 target_id; 5133 __le64 resp_addr; 5134 __le32 flags; 5135 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5136 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5137 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5138 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5139 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5140 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5141 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5142 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 5143 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5144 __le32 enables; 5145 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5146 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5147 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5148 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5149 __le16 vnic_id; 5150 __le16 max_agg_segs; 5151 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5152 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5153 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5154 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5155 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5156 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5157 __le16 max_aggs; 5158 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5159 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5160 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5161 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5162 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5163 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5164 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5165 u8 unused_0[2]; 5166 __le32 max_agg_timer; 5167 __le32 min_agg_len; 5168 }; 5169 5170 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5171 struct hwrm_vnic_tpa_cfg_output { 5172 __le16 error_code; 5173 __le16 req_type; 5174 __le16 seq_id; 5175 __le16 resp_len; 5176 u8 unused_0[7]; 5177 u8 valid; 5178 }; 5179 5180 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5181 struct hwrm_vnic_tpa_qcfg_input { 5182 __le16 req_type; 5183 __le16 cmpl_ring; 5184 __le16 seq_id; 5185 __le16 target_id; 5186 __le64 resp_addr; 5187 __le16 vnic_id; 5188 u8 unused_0[6]; 5189 }; 5190 5191 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5192 struct hwrm_vnic_tpa_qcfg_output { 5193 __le16 error_code; 5194 __le16 req_type; 5195 __le16 seq_id; 5196 __le16 resp_len; 5197 __le32 flags; 5198 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5199 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5200 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5201 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5202 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5203 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5204 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5205 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5206 __le16 max_agg_segs; 5207 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5208 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5209 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5210 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5211 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5212 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5213 __le16 max_aggs; 5214 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5215 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5216 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5217 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5218 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5219 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5220 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5221 __le32 max_agg_timer; 5222 __le32 min_agg_len; 5223 u8 unused_0[7]; 5224 u8 valid; 5225 }; 5226 5227 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5228 struct hwrm_vnic_rss_cfg_input { 5229 __le16 req_type; 5230 __le16 cmpl_ring; 5231 __le16 seq_id; 5232 __le16 target_id; 5233 __le64 resp_addr; 5234 __le32 hash_type; 5235 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5236 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5237 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5238 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5239 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5240 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 5241 __le16 vnic_id; 5242 u8 ring_table_pair_index; 5243 u8 hash_mode_flags; 5244 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 5245 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 5246 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 5247 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 5248 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5249 __le64 ring_grp_tbl_addr; 5250 __le64 hash_key_tbl_addr; 5251 __le16 rss_ctx_idx; 5252 u8 unused_1[6]; 5253 }; 5254 5255 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5256 struct hwrm_vnic_rss_cfg_output { 5257 __le16 error_code; 5258 __le16 req_type; 5259 __le16 seq_id; 5260 __le16 resp_len; 5261 u8 unused_0[7]; 5262 u8 valid; 5263 }; 5264 5265 /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 5266 struct hwrm_vnic_rss_cfg_cmd_err { 5267 u8 code; 5268 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 5269 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 5270 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 5271 u8 unused_0[7]; 5272 }; 5273 5274 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5275 struct hwrm_vnic_plcmodes_cfg_input { 5276 __le16 req_type; 5277 __le16 cmpl_ring; 5278 __le16 seq_id; 5279 __le16 target_id; 5280 __le64 resp_addr; 5281 __le32 flags; 5282 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5283 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5284 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5285 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5286 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5287 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5288 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 5289 __le32 enables; 5290 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5291 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5292 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5293 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 5294 __le32 vnic_id; 5295 __le16 jumbo_thresh; 5296 __le16 hds_offset; 5297 __le16 hds_threshold; 5298 __le16 max_bds; 5299 u8 unused_0[4]; 5300 }; 5301 5302 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5303 struct hwrm_vnic_plcmodes_cfg_output { 5304 __le16 error_code; 5305 __le16 req_type; 5306 __le16 seq_id; 5307 __le16 resp_len; 5308 u8 unused_0[7]; 5309 u8 valid; 5310 }; 5311 5312 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5313 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5314 __le16 req_type; 5315 __le16 cmpl_ring; 5316 __le16 seq_id; 5317 __le16 target_id; 5318 __le64 resp_addr; 5319 }; 5320 5321 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5322 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5323 __le16 error_code; 5324 __le16 req_type; 5325 __le16 seq_id; 5326 __le16 resp_len; 5327 __le16 rss_cos_lb_ctx_id; 5328 u8 unused_0[5]; 5329 u8 valid; 5330 }; 5331 5332 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5333 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5334 __le16 req_type; 5335 __le16 cmpl_ring; 5336 __le16 seq_id; 5337 __le16 target_id; 5338 __le64 resp_addr; 5339 __le16 rss_cos_lb_ctx_id; 5340 u8 unused_0[6]; 5341 }; 5342 5343 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5344 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5345 __le16 error_code; 5346 __le16 req_type; 5347 __le16 seq_id; 5348 __le16 resp_len; 5349 u8 unused_0[7]; 5350 u8 valid; 5351 }; 5352 5353 /* hwrm_ring_alloc_input (size:704b/88B) */ 5354 struct hwrm_ring_alloc_input { 5355 __le16 req_type; 5356 __le16 cmpl_ring; 5357 __le16 seq_id; 5358 __le16 target_id; 5359 __le64 resp_addr; 5360 __le32 enables; 5361 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5362 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5363 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 5364 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 5365 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 5366 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5367 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 5368 u8 ring_type; 5369 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5370 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5371 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5372 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5373 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 5374 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 5375 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 5376 u8 unused_0; 5377 __le16 flags; 5378 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5379 __le64 page_tbl_addr; 5380 __le32 fbo; 5381 u8 page_size; 5382 u8 page_tbl_depth; 5383 __le16 schq_id; 5384 __le32 length; 5385 __le16 logical_id; 5386 __le16 cmpl_ring_id; 5387 __le16 queue_id; 5388 __le16 rx_buf_size; 5389 __le16 rx_ring_id; 5390 __le16 nq_ring_id; 5391 __le16 ring_arb_cfg; 5392 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5393 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5394 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5395 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5396 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5397 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5398 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5399 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5400 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5401 __le16 unused_3; 5402 __le32 reserved3; 5403 __le32 stat_ctx_id; 5404 __le32 reserved4; 5405 __le32 max_bw; 5406 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5407 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5408 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5409 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5410 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5411 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5412 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5413 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5414 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5415 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5416 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5417 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5418 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5419 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5420 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5421 u8 int_mode; 5422 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5423 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5424 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5425 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5426 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 5427 u8 unused_4[3]; 5428 __le64 cq_handle; 5429 }; 5430 5431 /* hwrm_ring_alloc_output (size:128b/16B) */ 5432 struct hwrm_ring_alloc_output { 5433 __le16 error_code; 5434 __le16 req_type; 5435 __le16 seq_id; 5436 __le16 resp_len; 5437 __le16 ring_id; 5438 __le16 logical_ring_id; 5439 u8 unused_0[3]; 5440 u8 valid; 5441 }; 5442 5443 /* hwrm_ring_free_input (size:192b/24B) */ 5444 struct hwrm_ring_free_input { 5445 __le16 req_type; 5446 __le16 cmpl_ring; 5447 __le16 seq_id; 5448 __le16 target_id; 5449 __le64 resp_addr; 5450 u8 ring_type; 5451 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5452 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5453 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5454 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5455 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5456 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5457 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5458 u8 unused_0; 5459 __le16 ring_id; 5460 u8 unused_1[4]; 5461 }; 5462 5463 /* hwrm_ring_free_output (size:128b/16B) */ 5464 struct hwrm_ring_free_output { 5465 __le16 error_code; 5466 __le16 req_type; 5467 __le16 seq_id; 5468 __le16 resp_len; 5469 u8 unused_0[7]; 5470 u8 valid; 5471 }; 5472 5473 /* hwrm_ring_reset_input (size:192b/24B) */ 5474 struct hwrm_ring_reset_input { 5475 __le16 req_type; 5476 __le16 cmpl_ring; 5477 __le16 seq_id; 5478 __le16 target_id; 5479 __le64 resp_addr; 5480 u8 ring_type; 5481 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5482 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5483 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5484 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5485 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 5486 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 5487 u8 unused_0; 5488 __le16 ring_id; 5489 u8 unused_1[4]; 5490 }; 5491 5492 /* hwrm_ring_reset_output (size:128b/16B) */ 5493 struct hwrm_ring_reset_output { 5494 __le16 error_code; 5495 __le16 req_type; 5496 __le16 seq_id; 5497 __le16 resp_len; 5498 u8 unused_0[4]; 5499 u8 consumer_idx[3]; 5500 u8 valid; 5501 }; 5502 5503 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5504 struct hwrm_ring_aggint_qcaps_input { 5505 __le16 req_type; 5506 __le16 cmpl_ring; 5507 __le16 seq_id; 5508 __le16 target_id; 5509 __le64 resp_addr; 5510 }; 5511 5512 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5513 struct hwrm_ring_aggint_qcaps_output { 5514 __le16 error_code; 5515 __le16 req_type; 5516 __le16 seq_id; 5517 __le16 resp_len; 5518 __le32 cmpl_params; 5519 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5520 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5521 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5522 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5523 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5524 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5525 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5526 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5527 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5528 __le32 nq_params; 5529 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5530 __le16 num_cmpl_dma_aggr_min; 5531 __le16 num_cmpl_dma_aggr_max; 5532 __le16 num_cmpl_dma_aggr_during_int_min; 5533 __le16 num_cmpl_dma_aggr_during_int_max; 5534 __le16 cmpl_aggr_dma_tmr_min; 5535 __le16 cmpl_aggr_dma_tmr_max; 5536 __le16 cmpl_aggr_dma_tmr_during_int_min; 5537 __le16 cmpl_aggr_dma_tmr_during_int_max; 5538 __le16 int_lat_tmr_min_min; 5539 __le16 int_lat_tmr_min_max; 5540 __le16 int_lat_tmr_max_min; 5541 __le16 int_lat_tmr_max_max; 5542 __le16 num_cmpl_aggr_int_min; 5543 __le16 num_cmpl_aggr_int_max; 5544 __le16 timer_units; 5545 u8 unused_0[1]; 5546 u8 valid; 5547 }; 5548 5549 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5550 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5551 __le16 req_type; 5552 __le16 cmpl_ring; 5553 __le16 seq_id; 5554 __le16 target_id; 5555 __le64 resp_addr; 5556 __le16 ring_id; 5557 __le16 flags; 5558 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5559 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5560 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5561 u8 unused_0[4]; 5562 }; 5563 5564 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5565 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5566 __le16 error_code; 5567 __le16 req_type; 5568 __le16 seq_id; 5569 __le16 resp_len; 5570 __le16 flags; 5571 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5572 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5573 __le16 num_cmpl_dma_aggr; 5574 __le16 num_cmpl_dma_aggr_during_int; 5575 __le16 cmpl_aggr_dma_tmr; 5576 __le16 cmpl_aggr_dma_tmr_during_int; 5577 __le16 int_lat_tmr_min; 5578 __le16 int_lat_tmr_max; 5579 __le16 num_cmpl_aggr_int; 5580 u8 unused_0[7]; 5581 u8 valid; 5582 }; 5583 5584 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5585 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5586 __le16 req_type; 5587 __le16 cmpl_ring; 5588 __le16 seq_id; 5589 __le16 target_id; 5590 __le64 resp_addr; 5591 __le16 ring_id; 5592 __le16 flags; 5593 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5594 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5595 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5596 __le16 num_cmpl_dma_aggr; 5597 __le16 num_cmpl_dma_aggr_during_int; 5598 __le16 cmpl_aggr_dma_tmr; 5599 __le16 cmpl_aggr_dma_tmr_during_int; 5600 __le16 int_lat_tmr_min; 5601 __le16 int_lat_tmr_max; 5602 __le16 num_cmpl_aggr_int; 5603 __le16 enables; 5604 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5605 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5606 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5607 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5608 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5609 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5610 u8 unused_0[4]; 5611 }; 5612 5613 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5614 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5615 __le16 error_code; 5616 __le16 req_type; 5617 __le16 seq_id; 5618 __le16 resp_len; 5619 u8 unused_0[7]; 5620 u8 valid; 5621 }; 5622 5623 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5624 struct hwrm_ring_grp_alloc_input { 5625 __le16 req_type; 5626 __le16 cmpl_ring; 5627 __le16 seq_id; 5628 __le16 target_id; 5629 __le64 resp_addr; 5630 __le16 cr; 5631 __le16 rr; 5632 __le16 ar; 5633 __le16 sc; 5634 }; 5635 5636 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5637 struct hwrm_ring_grp_alloc_output { 5638 __le16 error_code; 5639 __le16 req_type; 5640 __le16 seq_id; 5641 __le16 resp_len; 5642 __le32 ring_group_id; 5643 u8 unused_0[3]; 5644 u8 valid; 5645 }; 5646 5647 /* hwrm_ring_grp_free_input (size:192b/24B) */ 5648 struct hwrm_ring_grp_free_input { 5649 __le16 req_type; 5650 __le16 cmpl_ring; 5651 __le16 seq_id; 5652 __le16 target_id; 5653 __le64 resp_addr; 5654 __le32 ring_group_id; 5655 u8 unused_0[4]; 5656 }; 5657 5658 /* hwrm_ring_grp_free_output (size:128b/16B) */ 5659 struct hwrm_ring_grp_free_output { 5660 __le16 error_code; 5661 __le16 req_type; 5662 __le16 seq_id; 5663 __le16 resp_len; 5664 u8 unused_0[7]; 5665 u8 valid; 5666 }; 5667 5668 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5669 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5670 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5671 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5672 5673 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5674 struct hwrm_cfa_l2_filter_alloc_input { 5675 __le16 req_type; 5676 __le16 cmpl_ring; 5677 __le16 seq_id; 5678 __le16 target_id; 5679 __le64 resp_addr; 5680 __le32 flags; 5681 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5682 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5683 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5684 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5685 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5686 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5687 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5688 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5689 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5690 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5691 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5692 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5693 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5694 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 5695 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5696 __le32 enables; 5697 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5698 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5699 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5700 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5701 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5702 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5703 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5704 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5705 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5706 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5707 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5708 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5709 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5710 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5711 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5712 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5713 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5714 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 5715 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 5716 u8 l2_addr[6]; 5717 u8 num_vlans; 5718 u8 t_num_vlans; 5719 u8 l2_addr_mask[6]; 5720 __le16 l2_ovlan; 5721 __le16 l2_ovlan_mask; 5722 __le16 l2_ivlan; 5723 __le16 l2_ivlan_mask; 5724 u8 unused_1[2]; 5725 u8 t_l2_addr[6]; 5726 u8 unused_2[2]; 5727 u8 t_l2_addr_mask[6]; 5728 __le16 t_l2_ovlan; 5729 __le16 t_l2_ovlan_mask; 5730 __le16 t_l2_ivlan; 5731 __le16 t_l2_ivlan_mask; 5732 u8 src_type; 5733 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5734 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5735 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5736 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5737 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5738 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5739 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5740 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5741 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5742 u8 unused_3; 5743 __le32 src_id; 5744 u8 tunnel_type; 5745 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5746 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5747 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5748 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5749 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5750 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5751 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5752 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5753 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5754 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5755 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5756 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5757 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5758 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5759 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5760 u8 unused_4; 5761 __le16 dst_id; 5762 __le16 mirror_vnic_id; 5763 u8 pri_hint; 5764 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5765 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5766 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5767 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5768 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5769 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5770 u8 unused_5; 5771 __le32 unused_6; 5772 __le64 l2_filter_id_hint; 5773 }; 5774 5775 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5776 struct hwrm_cfa_l2_filter_alloc_output { 5777 __le16 error_code; 5778 __le16 req_type; 5779 __le16 seq_id; 5780 __le16 resp_len; 5781 __le64 l2_filter_id; 5782 __le32 flow_id; 5783 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5784 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5785 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5786 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5787 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5788 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5789 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5790 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5791 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5792 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5793 u8 unused_0[3]; 5794 u8 valid; 5795 }; 5796 5797 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5798 struct hwrm_cfa_l2_filter_free_input { 5799 __le16 req_type; 5800 __le16 cmpl_ring; 5801 __le16 seq_id; 5802 __le16 target_id; 5803 __le64 resp_addr; 5804 __le64 l2_filter_id; 5805 }; 5806 5807 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5808 struct hwrm_cfa_l2_filter_free_output { 5809 __le16 error_code; 5810 __le16 req_type; 5811 __le16 seq_id; 5812 __le16 resp_len; 5813 u8 unused_0[7]; 5814 u8 valid; 5815 }; 5816 5817 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5818 struct hwrm_cfa_l2_filter_cfg_input { 5819 __le16 req_type; 5820 __le16 cmpl_ring; 5821 __le16 seq_id; 5822 __le16 target_id; 5823 __le64 resp_addr; 5824 __le32 flags; 5825 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5826 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5827 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5828 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5829 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5830 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5831 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5832 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5833 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5834 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5835 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5836 __le32 enables; 5837 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5838 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5839 __le64 l2_filter_id; 5840 __le32 dst_id; 5841 __le32 new_mirror_vnic_id; 5842 }; 5843 5844 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5845 struct hwrm_cfa_l2_filter_cfg_output { 5846 __le16 error_code; 5847 __le16 req_type; 5848 __le16 seq_id; 5849 __le16 resp_len; 5850 u8 unused_0[7]; 5851 u8 valid; 5852 }; 5853 5854 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5855 struct hwrm_cfa_l2_set_rx_mask_input { 5856 __le16 req_type; 5857 __le16 cmpl_ring; 5858 __le16 seq_id; 5859 __le16 target_id; 5860 __le64 resp_addr; 5861 __le32 vnic_id; 5862 __le32 mask; 5863 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5864 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5865 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5866 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5867 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5868 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5869 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5870 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5871 __le64 mc_tbl_addr; 5872 __le32 num_mc_entries; 5873 u8 unused_0[4]; 5874 __le64 vlan_tag_tbl_addr; 5875 __le32 num_vlan_tags; 5876 u8 unused_1[4]; 5877 }; 5878 5879 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5880 struct hwrm_cfa_l2_set_rx_mask_output { 5881 __le16 error_code; 5882 __le16 req_type; 5883 __le16 seq_id; 5884 __le16 resp_len; 5885 u8 unused_0[7]; 5886 u8 valid; 5887 }; 5888 5889 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5890 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5891 u8 code; 5892 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5893 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5894 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5895 u8 unused_0[7]; 5896 }; 5897 5898 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5899 struct hwrm_cfa_tunnel_filter_alloc_input { 5900 __le16 req_type; 5901 __le16 cmpl_ring; 5902 __le16 seq_id; 5903 __le16 target_id; 5904 __le64 resp_addr; 5905 __le32 flags; 5906 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5907 __le32 enables; 5908 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5909 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5910 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5911 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5912 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5913 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5914 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5915 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5916 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5917 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5918 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5919 __le64 l2_filter_id; 5920 u8 l2_addr[6]; 5921 __le16 l2_ivlan; 5922 __le32 l3_addr[4]; 5923 __le32 t_l3_addr[4]; 5924 u8 l3_addr_type; 5925 u8 t_l3_addr_type; 5926 u8 tunnel_type; 5927 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5928 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5929 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5930 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5931 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5932 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5933 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5934 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5935 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5936 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5937 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5938 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5939 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5940 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5941 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5942 u8 tunnel_flags; 5943 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5944 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5945 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5946 __le32 vni; 5947 __le32 dst_vnic_id; 5948 __le32 mirror_vnic_id; 5949 }; 5950 5951 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5952 struct hwrm_cfa_tunnel_filter_alloc_output { 5953 __le16 error_code; 5954 __le16 req_type; 5955 __le16 seq_id; 5956 __le16 resp_len; 5957 __le64 tunnel_filter_id; 5958 __le32 flow_id; 5959 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 5960 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 5961 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 5962 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 5963 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 5964 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 5965 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 5966 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 5967 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 5968 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 5969 u8 unused_0[3]; 5970 u8 valid; 5971 }; 5972 5973 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5974 struct hwrm_cfa_tunnel_filter_free_input { 5975 __le16 req_type; 5976 __le16 cmpl_ring; 5977 __le16 seq_id; 5978 __le16 target_id; 5979 __le64 resp_addr; 5980 __le64 tunnel_filter_id; 5981 }; 5982 5983 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5984 struct hwrm_cfa_tunnel_filter_free_output { 5985 __le16 error_code; 5986 __le16 req_type; 5987 __le16 seq_id; 5988 __le16 resp_len; 5989 u8 unused_0[7]; 5990 u8 valid; 5991 }; 5992 5993 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5994 struct hwrm_vxlan_ipv4_hdr { 5995 u8 ver_hlen; 5996 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5997 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5998 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5999 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6000 u8 tos; 6001 __be16 ip_id; 6002 __be16 flags_frag_offset; 6003 u8 ttl; 6004 u8 protocol; 6005 __be32 src_ip_addr; 6006 __be32 dest_ip_addr; 6007 }; 6008 6009 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6010 struct hwrm_vxlan_ipv6_hdr { 6011 __be32 ver_tc_flow_label; 6012 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6013 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6014 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6015 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6016 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6017 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6018 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6019 __be16 payload_len; 6020 u8 next_hdr; 6021 u8 ttl; 6022 __be32 src_ip_addr[4]; 6023 __be32 dest_ip_addr[4]; 6024 }; 6025 6026 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6027 struct hwrm_cfa_encap_data_vxlan { 6028 u8 src_mac_addr[6]; 6029 __le16 unused_0; 6030 u8 dst_mac_addr[6]; 6031 u8 num_vlan_tags; 6032 u8 unused_1; 6033 __be16 ovlan_tpid; 6034 __be16 ovlan_tci; 6035 __be16 ivlan_tpid; 6036 __be16 ivlan_tci; 6037 __le32 l3[10]; 6038 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6039 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6040 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6041 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6042 __be16 src_port; 6043 __be16 dst_port; 6044 __be32 vni; 6045 u8 hdr_rsvd0[3]; 6046 u8 hdr_rsvd1; 6047 u8 hdr_flags; 6048 u8 unused[3]; 6049 }; 6050 6051 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 6052 struct hwrm_cfa_encap_record_alloc_input { 6053 __le16 req_type; 6054 __le16 cmpl_ring; 6055 __le16 seq_id; 6056 __le16 target_id; 6057 __le64 resp_addr; 6058 __le32 flags; 6059 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6060 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 6061 u8 encap_type; 6062 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 6063 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 6064 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 6065 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 6066 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 6067 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 6068 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 6069 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 6070 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 6071 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 6072 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 6073 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 6074 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 6075 u8 unused_0[3]; 6076 __le32 encap_data[20]; 6077 }; 6078 6079 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 6080 struct hwrm_cfa_encap_record_alloc_output { 6081 __le16 error_code; 6082 __le16 req_type; 6083 __le16 seq_id; 6084 __le16 resp_len; 6085 __le32 encap_record_id; 6086 u8 unused_0[3]; 6087 u8 valid; 6088 }; 6089 6090 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 6091 struct hwrm_cfa_encap_record_free_input { 6092 __le16 req_type; 6093 __le16 cmpl_ring; 6094 __le16 seq_id; 6095 __le16 target_id; 6096 __le64 resp_addr; 6097 __le32 encap_record_id; 6098 u8 unused_0[4]; 6099 }; 6100 6101 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 6102 struct hwrm_cfa_encap_record_free_output { 6103 __le16 error_code; 6104 __le16 req_type; 6105 __le16 seq_id; 6106 __le16 resp_len; 6107 u8 unused_0[7]; 6108 u8 valid; 6109 }; 6110 6111 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 6112 struct hwrm_cfa_ntuple_filter_alloc_input { 6113 __le16 req_type; 6114 __le16 cmpl_ring; 6115 __le16 seq_id; 6116 __le16 target_id; 6117 __le64 resp_addr; 6118 __le32 flags; 6119 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6120 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 6121 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 6122 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 6123 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 6124 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 6125 __le32 enables; 6126 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6127 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 6128 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 6129 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 6130 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 6131 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 6132 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 6133 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 6134 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 6135 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6136 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6137 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6138 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6139 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6140 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6141 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6142 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6143 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6144 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 6145 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6146 __le64 l2_filter_id; 6147 u8 src_macaddr[6]; 6148 __be16 ethertype; 6149 u8 ip_addr_type; 6150 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6151 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6152 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6153 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6154 u8 ip_protocol; 6155 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6156 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6157 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6158 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6159 __le16 dst_id; 6160 __le16 mirror_vnic_id; 6161 u8 tunnel_type; 6162 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6163 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6164 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6165 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6166 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6167 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6168 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6169 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6170 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6171 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6172 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6173 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6174 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6175 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6176 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6177 u8 pri_hint; 6178 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6179 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6180 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6181 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6182 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6183 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6184 __be32 src_ipaddr[4]; 6185 __be32 src_ipaddr_mask[4]; 6186 __be32 dst_ipaddr[4]; 6187 __be32 dst_ipaddr_mask[4]; 6188 __be16 src_port; 6189 __be16 src_port_mask; 6190 __be16 dst_port; 6191 __be16 dst_port_mask; 6192 __le64 ntuple_filter_id_hint; 6193 }; 6194 6195 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6196 struct hwrm_cfa_ntuple_filter_alloc_output { 6197 __le16 error_code; 6198 __le16 req_type; 6199 __le16 seq_id; 6200 __le16 resp_len; 6201 __le64 ntuple_filter_id; 6202 __le32 flow_id; 6203 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6204 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6205 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6206 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6207 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6208 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 6209 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6210 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6211 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6212 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6213 u8 unused_0[3]; 6214 u8 valid; 6215 }; 6216 6217 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 6218 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 6219 u8 code; 6220 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6221 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6222 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 6223 u8 unused_0[7]; 6224 }; 6225 6226 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6227 struct hwrm_cfa_ntuple_filter_free_input { 6228 __le16 req_type; 6229 __le16 cmpl_ring; 6230 __le16 seq_id; 6231 __le16 target_id; 6232 __le64 resp_addr; 6233 __le64 ntuple_filter_id; 6234 }; 6235 6236 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6237 struct hwrm_cfa_ntuple_filter_free_output { 6238 __le16 error_code; 6239 __le16 req_type; 6240 __le16 seq_id; 6241 __le16 resp_len; 6242 u8 unused_0[7]; 6243 u8 valid; 6244 }; 6245 6246 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6247 struct hwrm_cfa_ntuple_filter_cfg_input { 6248 __le16 req_type; 6249 __le16 cmpl_ring; 6250 __le16 seq_id; 6251 __le16 target_id; 6252 __le64 resp_addr; 6253 __le32 enables; 6254 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6255 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6256 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 6257 __le32 flags; 6258 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 6259 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6260 __le64 ntuple_filter_id; 6261 __le32 new_dst_id; 6262 __le32 new_mirror_vnic_id; 6263 __le16 new_meter_instance_id; 6264 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6265 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6266 u8 unused_1[6]; 6267 }; 6268 6269 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6270 struct hwrm_cfa_ntuple_filter_cfg_output { 6271 __le16 error_code; 6272 __le16 req_type; 6273 __le16 seq_id; 6274 __le16 resp_len; 6275 u8 unused_0[7]; 6276 u8 valid; 6277 }; 6278 6279 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 6280 struct hwrm_cfa_decap_filter_alloc_input { 6281 __le16 req_type; 6282 __le16 cmpl_ring; 6283 __le16 seq_id; 6284 __le16 target_id; 6285 __le64 resp_addr; 6286 __le32 flags; 6287 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 6288 __le32 enables; 6289 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 6290 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 6291 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 6292 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 6293 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 6294 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 6295 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 6296 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 6297 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 6298 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 6299 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 6300 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 6301 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 6302 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 6303 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 6304 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6305 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 6306 __be32 tunnel_id; 6307 u8 tunnel_type; 6308 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6309 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6310 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6311 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6312 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6313 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6314 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6315 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6316 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6317 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6318 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6319 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6320 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6321 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6322 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6323 u8 unused_0; 6324 __le16 unused_1; 6325 u8 src_macaddr[6]; 6326 u8 unused_2[2]; 6327 u8 dst_macaddr[6]; 6328 __be16 ovlan_vid; 6329 __be16 ivlan_vid; 6330 __be16 t_ovlan_vid; 6331 __be16 t_ivlan_vid; 6332 __be16 ethertype; 6333 u8 ip_addr_type; 6334 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6335 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6336 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6337 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6338 u8 ip_protocol; 6339 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6340 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6341 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6342 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6343 __le16 unused_3; 6344 __le32 unused_4; 6345 __be32 src_ipaddr[4]; 6346 __be32 dst_ipaddr[4]; 6347 __be16 src_port; 6348 __be16 dst_port; 6349 __le16 dst_id; 6350 __le16 l2_ctxt_ref_id; 6351 }; 6352 6353 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 6354 struct hwrm_cfa_decap_filter_alloc_output { 6355 __le16 error_code; 6356 __le16 req_type; 6357 __le16 seq_id; 6358 __le16 resp_len; 6359 __le32 decap_filter_id; 6360 u8 unused_0[3]; 6361 u8 valid; 6362 }; 6363 6364 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 6365 struct hwrm_cfa_decap_filter_free_input { 6366 __le16 req_type; 6367 __le16 cmpl_ring; 6368 __le16 seq_id; 6369 __le16 target_id; 6370 __le64 resp_addr; 6371 __le32 decap_filter_id; 6372 u8 unused_0[4]; 6373 }; 6374 6375 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 6376 struct hwrm_cfa_decap_filter_free_output { 6377 __le16 error_code; 6378 __le16 req_type; 6379 __le16 seq_id; 6380 __le16 resp_len; 6381 u8 unused_0[7]; 6382 u8 valid; 6383 }; 6384 6385 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 6386 struct hwrm_cfa_flow_alloc_input { 6387 __le16 req_type; 6388 __le16 cmpl_ring; 6389 __le16 seq_id; 6390 __le16 target_id; 6391 __le64 resp_addr; 6392 __le16 flags; 6393 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 6394 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 6395 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 6396 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 6397 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 6398 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 6399 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 6400 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 6401 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 6402 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 6403 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 6404 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 6405 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 6406 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 6407 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 6408 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 6409 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 6410 __le16 src_fid; 6411 __le32 tunnel_handle; 6412 __le16 action_flags; 6413 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 6414 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 6415 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 6416 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 6417 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 6418 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 6419 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 6420 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 6421 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 6422 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 6423 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 6424 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 6425 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 6426 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 6427 __le16 dst_fid; 6428 __be16 l2_rewrite_vlan_tpid; 6429 __be16 l2_rewrite_vlan_tci; 6430 __le16 act_meter_id; 6431 __le16 ref_flow_handle; 6432 __be16 ethertype; 6433 __be16 outer_vlan_tci; 6434 __be16 dmac[3]; 6435 __be16 inner_vlan_tci; 6436 __be16 smac[3]; 6437 u8 ip_dst_mask_len; 6438 u8 ip_src_mask_len; 6439 __be32 ip_dst[4]; 6440 __be32 ip_src[4]; 6441 __be16 l4_src_port; 6442 __be16 l4_src_port_mask; 6443 __be16 l4_dst_port; 6444 __be16 l4_dst_port_mask; 6445 __be32 nat_ip_address[4]; 6446 __be16 l2_rewrite_dmac[3]; 6447 __be16 nat_port; 6448 __be16 l2_rewrite_smac[3]; 6449 u8 ip_proto; 6450 u8 tunnel_type; 6451 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6452 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6453 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6454 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6455 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6456 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6457 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6458 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6459 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 6460 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6461 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6462 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6463 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6464 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6465 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6466 }; 6467 6468 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 6469 struct hwrm_cfa_flow_alloc_output { 6470 __le16 error_code; 6471 __le16 req_type; 6472 __le16 seq_id; 6473 __le16 resp_len; 6474 __le16 flow_handle; 6475 u8 unused_0[2]; 6476 __le32 flow_id; 6477 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 6478 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 6479 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 6480 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 6481 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 6482 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 6483 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 6484 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 6485 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 6486 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 6487 __le64 ext_flow_handle; 6488 __le32 flow_counter_id; 6489 u8 unused_1[3]; 6490 u8 valid; 6491 }; 6492 6493 /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 6494 struct hwrm_cfa_flow_alloc_cmd_err { 6495 u8 code; 6496 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 6497 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 6498 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 6499 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 6500 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 6501 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 6502 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 6503 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 6504 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 6505 u8 unused_0[7]; 6506 }; 6507 6508 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6509 struct hwrm_cfa_flow_free_input { 6510 __le16 req_type; 6511 __le16 cmpl_ring; 6512 __le16 seq_id; 6513 __le16 target_id; 6514 __le64 resp_addr; 6515 __le16 flow_handle; 6516 __le16 unused_0; 6517 __le32 flow_counter_id; 6518 __le64 ext_flow_handle; 6519 }; 6520 6521 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6522 struct hwrm_cfa_flow_free_output { 6523 __le16 error_code; 6524 __le16 req_type; 6525 __le16 seq_id; 6526 __le16 resp_len; 6527 __le64 packet; 6528 __le64 byte; 6529 u8 unused_0[7]; 6530 u8 valid; 6531 }; 6532 6533 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6534 struct hwrm_cfa_flow_info_input { 6535 __le16 req_type; 6536 __le16 cmpl_ring; 6537 __le16 seq_id; 6538 __le16 target_id; 6539 __le64 resp_addr; 6540 __le16 flow_handle; 6541 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6542 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6543 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6544 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6545 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6546 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6547 u8 unused_0[6]; 6548 __le64 ext_flow_handle; 6549 }; 6550 6551 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6552 struct hwrm_cfa_flow_info_output { 6553 __le16 error_code; 6554 __le16 req_type; 6555 __le16 seq_id; 6556 __le16 resp_len; 6557 u8 flags; 6558 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6559 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6560 u8 profile; 6561 __le16 src_fid; 6562 __le16 dst_fid; 6563 __le16 l2_ctxt_id; 6564 __le64 em_info; 6565 __le64 tcam_info; 6566 __le64 vfp_tcam_info; 6567 __le16 ar_id; 6568 __le16 flow_handle; 6569 __le32 tunnel_handle; 6570 __le16 flow_timer; 6571 u8 unused_0[6]; 6572 __le32 flow_key_data[130]; 6573 __le32 flow_action_info[30]; 6574 u8 unused_1[7]; 6575 u8 valid; 6576 }; 6577 6578 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6579 struct hwrm_cfa_flow_stats_input { 6580 __le16 req_type; 6581 __le16 cmpl_ring; 6582 __le16 seq_id; 6583 __le16 target_id; 6584 __le64 resp_addr; 6585 __le16 num_flows; 6586 __le16 flow_handle_0; 6587 __le16 flow_handle_1; 6588 __le16 flow_handle_2; 6589 __le16 flow_handle_3; 6590 __le16 flow_handle_4; 6591 __le16 flow_handle_5; 6592 __le16 flow_handle_6; 6593 __le16 flow_handle_7; 6594 __le16 flow_handle_8; 6595 __le16 flow_handle_9; 6596 u8 unused_0[2]; 6597 __le32 flow_id_0; 6598 __le32 flow_id_1; 6599 __le32 flow_id_2; 6600 __le32 flow_id_3; 6601 __le32 flow_id_4; 6602 __le32 flow_id_5; 6603 __le32 flow_id_6; 6604 __le32 flow_id_7; 6605 __le32 flow_id_8; 6606 __le32 flow_id_9; 6607 }; 6608 6609 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6610 struct hwrm_cfa_flow_stats_output { 6611 __le16 error_code; 6612 __le16 req_type; 6613 __le16 seq_id; 6614 __le16 resp_len; 6615 __le64 packet_0; 6616 __le64 packet_1; 6617 __le64 packet_2; 6618 __le64 packet_3; 6619 __le64 packet_4; 6620 __le64 packet_5; 6621 __le64 packet_6; 6622 __le64 packet_7; 6623 __le64 packet_8; 6624 __le64 packet_9; 6625 __le64 byte_0; 6626 __le64 byte_1; 6627 __le64 byte_2; 6628 __le64 byte_3; 6629 __le64 byte_4; 6630 __le64 byte_5; 6631 __le64 byte_6; 6632 __le64 byte_7; 6633 __le64 byte_8; 6634 __le64 byte_9; 6635 u8 unused_0[7]; 6636 u8 valid; 6637 }; 6638 6639 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6640 struct hwrm_cfa_vfr_alloc_input { 6641 __le16 req_type; 6642 __le16 cmpl_ring; 6643 __le16 seq_id; 6644 __le16 target_id; 6645 __le64 resp_addr; 6646 __le16 vf_id; 6647 __le16 reserved; 6648 u8 unused_0[4]; 6649 char vfr_name[32]; 6650 }; 6651 6652 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6653 struct hwrm_cfa_vfr_alloc_output { 6654 __le16 error_code; 6655 __le16 req_type; 6656 __le16 seq_id; 6657 __le16 resp_len; 6658 __le16 rx_cfa_code; 6659 __le16 tx_cfa_action; 6660 u8 unused_0[3]; 6661 u8 valid; 6662 }; 6663 6664 /* hwrm_cfa_vfr_free_input (size:384b/48B) */ 6665 struct hwrm_cfa_vfr_free_input { 6666 __le16 req_type; 6667 __le16 cmpl_ring; 6668 __le16 seq_id; 6669 __le16 target_id; 6670 __le64 resp_addr; 6671 char vfr_name[32]; 6672 }; 6673 6674 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6675 struct hwrm_cfa_vfr_free_output { 6676 __le16 error_code; 6677 __le16 req_type; 6678 __le16 seq_id; 6679 __le16 resp_len; 6680 u8 unused_0[7]; 6681 u8 valid; 6682 }; 6683 6684 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6685 struct hwrm_cfa_eem_qcaps_input { 6686 __le16 req_type; 6687 __le16 cmpl_ring; 6688 __le16 seq_id; 6689 __le16 target_id; 6690 __le64 resp_addr; 6691 __le32 flags; 6692 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6693 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6694 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6695 __le32 unused_0; 6696 }; 6697 6698 /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 6699 struct hwrm_cfa_eem_qcaps_output { 6700 __le16 error_code; 6701 __le16 req_type; 6702 __le16 seq_id; 6703 __le16 resp_len; 6704 __le32 flags; 6705 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6706 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6707 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 6708 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 6709 __le32 unused_0; 6710 __le32 supported; 6711 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6712 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6713 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6714 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6715 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 6716 __le32 max_entries_supported; 6717 __le16 key_entry_size; 6718 __le16 record_entry_size; 6719 __le16 efc_entry_size; 6720 __le16 fid_entry_size; 6721 u8 unused_1[7]; 6722 u8 valid; 6723 }; 6724 6725 /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 6726 struct hwrm_cfa_eem_cfg_input { 6727 __le16 req_type; 6728 __le16 cmpl_ring; 6729 __le16 seq_id; 6730 __le16 target_id; 6731 __le64 resp_addr; 6732 __le32 flags; 6733 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6734 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6735 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6736 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 6737 __le16 group_id; 6738 __le16 unused_0; 6739 __le32 num_entries; 6740 __le32 unused_1; 6741 __le16 key0_ctx_id; 6742 __le16 key1_ctx_id; 6743 __le16 record_ctx_id; 6744 __le16 efc_ctx_id; 6745 __le16 fid_ctx_id; 6746 __le16 unused_2; 6747 __le32 unused_3; 6748 }; 6749 6750 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6751 struct hwrm_cfa_eem_cfg_output { 6752 __le16 error_code; 6753 __le16 req_type; 6754 __le16 seq_id; 6755 __le16 resp_len; 6756 u8 unused_0[7]; 6757 u8 valid; 6758 }; 6759 6760 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6761 struct hwrm_cfa_eem_qcfg_input { 6762 __le16 req_type; 6763 __le16 cmpl_ring; 6764 __le16 seq_id; 6765 __le16 target_id; 6766 __le64 resp_addr; 6767 __le32 flags; 6768 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6769 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6770 __le32 unused_0; 6771 }; 6772 6773 /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 6774 struct hwrm_cfa_eem_qcfg_output { 6775 __le16 error_code; 6776 __le16 req_type; 6777 __le16 seq_id; 6778 __le16 resp_len; 6779 __le32 flags; 6780 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6781 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6782 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6783 __le32 num_entries; 6784 __le16 key0_ctx_id; 6785 __le16 key1_ctx_id; 6786 __le16 record_ctx_id; 6787 __le16 efc_ctx_id; 6788 __le16 fid_ctx_id; 6789 u8 unused_2[5]; 6790 u8 valid; 6791 }; 6792 6793 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 6794 struct hwrm_cfa_eem_op_input { 6795 __le16 req_type; 6796 __le16 cmpl_ring; 6797 __le16 seq_id; 6798 __le16 target_id; 6799 __le64 resp_addr; 6800 __le32 flags; 6801 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6802 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6803 __le16 unused_0; 6804 __le16 op; 6805 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6806 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6807 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6808 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6809 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6810 }; 6811 6812 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 6813 struct hwrm_cfa_eem_op_output { 6814 __le16 error_code; 6815 __le16 req_type; 6816 __le16 seq_id; 6817 __le16 resp_len; 6818 u8 unused_0[7]; 6819 u8 valid; 6820 }; 6821 6822 /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 6823 struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 6824 __le16 req_type; 6825 __le16 cmpl_ring; 6826 __le16 seq_id; 6827 __le16 target_id; 6828 __le64 resp_addr; 6829 __le32 unused_0[4]; 6830 }; 6831 6832 /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 6833 struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 6834 __le16 error_code; 6835 __le16 req_type; 6836 __le16 seq_id; 6837 __le16 resp_len; 6838 __le32 flags; 6839 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6840 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6841 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6842 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6843 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6844 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6845 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6846 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6847 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 6848 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 6849 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 6850 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 6851 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 6852 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 6853 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 6854 u8 unused_0[3]; 6855 u8 valid; 6856 }; 6857 6858 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6859 struct hwrm_tunnel_dst_port_query_input { 6860 __le16 req_type; 6861 __le16 cmpl_ring; 6862 __le16 seq_id; 6863 __le16 target_id; 6864 __le64 resp_addr; 6865 u8 tunnel_type; 6866 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6867 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6868 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6869 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6870 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6871 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6872 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6873 u8 unused_0[7]; 6874 }; 6875 6876 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 6877 struct hwrm_tunnel_dst_port_query_output { 6878 __le16 error_code; 6879 __le16 req_type; 6880 __le16 seq_id; 6881 __le16 resp_len; 6882 __le16 tunnel_dst_port_id; 6883 __be16 tunnel_dst_port_val; 6884 u8 unused_0[3]; 6885 u8 valid; 6886 }; 6887 6888 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 6889 struct hwrm_tunnel_dst_port_alloc_input { 6890 __le16 req_type; 6891 __le16 cmpl_ring; 6892 __le16 seq_id; 6893 __le16 target_id; 6894 __le64 resp_addr; 6895 u8 tunnel_type; 6896 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6897 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6898 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6899 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6900 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6901 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6902 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6903 u8 unused_0; 6904 __be16 tunnel_dst_port_val; 6905 u8 unused_1[4]; 6906 }; 6907 6908 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 6909 struct hwrm_tunnel_dst_port_alloc_output { 6910 __le16 error_code; 6911 __le16 req_type; 6912 __le16 seq_id; 6913 __le16 resp_len; 6914 __le16 tunnel_dst_port_id; 6915 u8 unused_0[5]; 6916 u8 valid; 6917 }; 6918 6919 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 6920 struct hwrm_tunnel_dst_port_free_input { 6921 __le16 req_type; 6922 __le16 cmpl_ring; 6923 __le16 seq_id; 6924 __le16 target_id; 6925 __le64 resp_addr; 6926 u8 tunnel_type; 6927 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6928 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6929 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6930 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6931 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6932 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6933 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6934 u8 unused_0; 6935 __le16 tunnel_dst_port_id; 6936 u8 unused_1[4]; 6937 }; 6938 6939 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 6940 struct hwrm_tunnel_dst_port_free_output { 6941 __le16 error_code; 6942 __le16 req_type; 6943 __le16 seq_id; 6944 __le16 resp_len; 6945 u8 unused_1[7]; 6946 u8 valid; 6947 }; 6948 6949 /* ctx_hw_stats (size:1280b/160B) */ 6950 struct ctx_hw_stats { 6951 __le64 rx_ucast_pkts; 6952 __le64 rx_mcast_pkts; 6953 __le64 rx_bcast_pkts; 6954 __le64 rx_discard_pkts; 6955 __le64 rx_error_pkts; 6956 __le64 rx_ucast_bytes; 6957 __le64 rx_mcast_bytes; 6958 __le64 rx_bcast_bytes; 6959 __le64 tx_ucast_pkts; 6960 __le64 tx_mcast_pkts; 6961 __le64 tx_bcast_pkts; 6962 __le64 tx_error_pkts; 6963 __le64 tx_discard_pkts; 6964 __le64 tx_ucast_bytes; 6965 __le64 tx_mcast_bytes; 6966 __le64 tx_bcast_bytes; 6967 __le64 tpa_pkts; 6968 __le64 tpa_bytes; 6969 __le64 tpa_events; 6970 __le64 tpa_aborts; 6971 }; 6972 6973 /* ctx_hw_stats_ext (size:1344b/168B) */ 6974 struct ctx_hw_stats_ext { 6975 __le64 rx_ucast_pkts; 6976 __le64 rx_mcast_pkts; 6977 __le64 rx_bcast_pkts; 6978 __le64 rx_discard_pkts; 6979 __le64 rx_error_pkts; 6980 __le64 rx_ucast_bytes; 6981 __le64 rx_mcast_bytes; 6982 __le64 rx_bcast_bytes; 6983 __le64 tx_ucast_pkts; 6984 __le64 tx_mcast_pkts; 6985 __le64 tx_bcast_pkts; 6986 __le64 tx_error_pkts; 6987 __le64 tx_discard_pkts; 6988 __le64 tx_ucast_bytes; 6989 __le64 tx_mcast_bytes; 6990 __le64 tx_bcast_bytes; 6991 __le64 rx_tpa_eligible_pkt; 6992 __le64 rx_tpa_eligible_bytes; 6993 __le64 rx_tpa_pkt; 6994 __le64 rx_tpa_bytes; 6995 __le64 rx_tpa_errors; 6996 }; 6997 6998 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 6999 struct hwrm_stat_ctx_alloc_input { 7000 __le16 req_type; 7001 __le16 cmpl_ring; 7002 __le16 seq_id; 7003 __le16 target_id; 7004 __le64 resp_addr; 7005 __le64 stats_dma_addr; 7006 __le32 update_period_ms; 7007 u8 stat_ctx_flags; 7008 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 7009 u8 unused_0; 7010 __le16 stats_dma_length; 7011 }; 7012 7013 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7014 struct hwrm_stat_ctx_alloc_output { 7015 __le16 error_code; 7016 __le16 req_type; 7017 __le16 seq_id; 7018 __le16 resp_len; 7019 __le32 stat_ctx_id; 7020 u8 unused_0[3]; 7021 u8 valid; 7022 }; 7023 7024 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7025 struct hwrm_stat_ctx_free_input { 7026 __le16 req_type; 7027 __le16 cmpl_ring; 7028 __le16 seq_id; 7029 __le16 target_id; 7030 __le64 resp_addr; 7031 __le32 stat_ctx_id; 7032 u8 unused_0[4]; 7033 }; 7034 7035 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7036 struct hwrm_stat_ctx_free_output { 7037 __le16 error_code; 7038 __le16 req_type; 7039 __le16 seq_id; 7040 __le16 resp_len; 7041 __le32 stat_ctx_id; 7042 u8 unused_0[3]; 7043 u8 valid; 7044 }; 7045 7046 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 7047 struct hwrm_stat_ctx_query_input { 7048 __le16 req_type; 7049 __le16 cmpl_ring; 7050 __le16 seq_id; 7051 __le16 target_id; 7052 __le64 resp_addr; 7053 __le32 stat_ctx_id; 7054 u8 flags; 7055 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7056 u8 unused_0[3]; 7057 }; 7058 7059 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 7060 struct hwrm_stat_ctx_query_output { 7061 __le16 error_code; 7062 __le16 req_type; 7063 __le16 seq_id; 7064 __le16 resp_len; 7065 __le64 tx_ucast_pkts; 7066 __le64 tx_mcast_pkts; 7067 __le64 tx_bcast_pkts; 7068 __le64 tx_err_pkts; 7069 __le64 tx_drop_pkts; 7070 __le64 tx_ucast_bytes; 7071 __le64 tx_mcast_bytes; 7072 __le64 tx_bcast_bytes; 7073 __le64 rx_ucast_pkts; 7074 __le64 rx_mcast_pkts; 7075 __le64 rx_bcast_pkts; 7076 __le64 rx_err_pkts; 7077 __le64 rx_drop_pkts; 7078 __le64 rx_ucast_bytes; 7079 __le64 rx_mcast_bytes; 7080 __le64 rx_bcast_bytes; 7081 __le64 rx_agg_pkts; 7082 __le64 rx_agg_bytes; 7083 __le64 rx_agg_events; 7084 __le64 rx_agg_aborts; 7085 u8 unused_0[7]; 7086 u8 valid; 7087 }; 7088 7089 /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 7090 struct hwrm_stat_ext_ctx_query_input { 7091 __le16 req_type; 7092 __le16 cmpl_ring; 7093 __le16 seq_id; 7094 __le16 target_id; 7095 __le64 resp_addr; 7096 __le32 stat_ctx_id; 7097 u8 flags; 7098 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7099 u8 unused_0[3]; 7100 }; 7101 7102 /* hwrm_stat_ext_ctx_query_output (size:1472b/184B) */ 7103 struct hwrm_stat_ext_ctx_query_output { 7104 __le16 error_code; 7105 __le16 req_type; 7106 __le16 seq_id; 7107 __le16 resp_len; 7108 __le64 rx_ucast_pkts; 7109 __le64 rx_mcast_pkts; 7110 __le64 rx_bcast_pkts; 7111 __le64 rx_discard_pkts; 7112 __le64 rx_error_pkts; 7113 __le64 rx_ucast_bytes; 7114 __le64 rx_mcast_bytes; 7115 __le64 rx_bcast_bytes; 7116 __le64 tx_ucast_pkts; 7117 __le64 tx_mcast_pkts; 7118 __le64 tx_bcast_pkts; 7119 __le64 tx_error_pkts; 7120 __le64 tx_discard_pkts; 7121 __le64 tx_ucast_bytes; 7122 __le64 tx_mcast_bytes; 7123 __le64 tx_bcast_bytes; 7124 __le64 rx_tpa_eligible_pkt; 7125 __le64 rx_tpa_eligible_bytes; 7126 __le64 rx_tpa_pkt; 7127 __le64 rx_tpa_bytes; 7128 __le64 rx_tpa_errors; 7129 u8 unused_0[7]; 7130 u8 valid; 7131 }; 7132 7133 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 7134 struct hwrm_stat_ctx_clr_stats_input { 7135 __le16 req_type; 7136 __le16 cmpl_ring; 7137 __le16 seq_id; 7138 __le16 target_id; 7139 __le64 resp_addr; 7140 __le32 stat_ctx_id; 7141 u8 unused_0[4]; 7142 }; 7143 7144 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 7145 struct hwrm_stat_ctx_clr_stats_output { 7146 __le16 error_code; 7147 __le16 req_type; 7148 __le16 seq_id; 7149 __le16 resp_len; 7150 u8 unused_0[7]; 7151 u8 valid; 7152 }; 7153 7154 /* hwrm_pcie_qstats_input (size:256b/32B) */ 7155 struct hwrm_pcie_qstats_input { 7156 __le16 req_type; 7157 __le16 cmpl_ring; 7158 __le16 seq_id; 7159 __le16 target_id; 7160 __le64 resp_addr; 7161 __le16 pcie_stat_size; 7162 u8 unused_0[6]; 7163 __le64 pcie_stat_host_addr; 7164 }; 7165 7166 /* hwrm_pcie_qstats_output (size:128b/16B) */ 7167 struct hwrm_pcie_qstats_output { 7168 __le16 error_code; 7169 __le16 req_type; 7170 __le16 seq_id; 7171 __le16 resp_len; 7172 __le16 pcie_stat_size; 7173 u8 unused_0[5]; 7174 u8 valid; 7175 }; 7176 7177 /* pcie_ctx_hw_stats (size:768b/96B) */ 7178 struct pcie_ctx_hw_stats { 7179 __le64 pcie_pl_signal_integrity; 7180 __le64 pcie_dl_signal_integrity; 7181 __le64 pcie_tl_signal_integrity; 7182 __le64 pcie_link_integrity; 7183 __le64 pcie_tx_traffic_rate; 7184 __le64 pcie_rx_traffic_rate; 7185 __le64 pcie_tx_dllp_statistics; 7186 __le64 pcie_rx_dllp_statistics; 7187 __le64 pcie_equalization_time; 7188 __le32 pcie_ltssm_histogram[4]; 7189 __le64 pcie_recovery_histogram; 7190 }; 7191 7192 /* hwrm_fw_reset_input (size:192b/24B) */ 7193 struct hwrm_fw_reset_input { 7194 __le16 req_type; 7195 __le16 cmpl_ring; 7196 __le16 seq_id; 7197 __le16 target_id; 7198 __le64 resp_addr; 7199 u8 embedded_proc_type; 7200 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7201 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7202 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7203 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7204 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7205 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7206 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7207 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 7208 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 7209 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7210 u8 selfrst_status; 7211 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7212 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7213 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7214 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7215 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7216 u8 host_idx; 7217 u8 flags; 7218 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 7219 u8 unused_0[4]; 7220 }; 7221 7222 /* hwrm_fw_reset_output (size:128b/16B) */ 7223 struct hwrm_fw_reset_output { 7224 __le16 error_code; 7225 __le16 req_type; 7226 __le16 seq_id; 7227 __le16 resp_len; 7228 u8 selfrst_status; 7229 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7230 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7231 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7232 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 7233 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7234 u8 unused_0[6]; 7235 u8 valid; 7236 }; 7237 7238 /* hwrm_fw_qstatus_input (size:192b/24B) */ 7239 struct hwrm_fw_qstatus_input { 7240 __le16 req_type; 7241 __le16 cmpl_ring; 7242 __le16 seq_id; 7243 __le16 target_id; 7244 __le64 resp_addr; 7245 u8 embedded_proc_type; 7246 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7247 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7248 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7249 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7250 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7251 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7252 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7253 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7254 u8 unused_0[7]; 7255 }; 7256 7257 /* hwrm_fw_qstatus_output (size:128b/16B) */ 7258 struct hwrm_fw_qstatus_output { 7259 __le16 error_code; 7260 __le16 req_type; 7261 __le16 seq_id; 7262 __le16 resp_len; 7263 u8 selfrst_status; 7264 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7265 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7266 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 7267 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 7268 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7269 u8 unused_0[6]; 7270 u8 valid; 7271 }; 7272 7273 /* hwrm_fw_set_time_input (size:256b/32B) */ 7274 struct hwrm_fw_set_time_input { 7275 __le16 req_type; 7276 __le16 cmpl_ring; 7277 __le16 seq_id; 7278 __le16 target_id; 7279 __le64 resp_addr; 7280 __le16 year; 7281 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7282 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7283 u8 month; 7284 u8 day; 7285 u8 hour; 7286 u8 minute; 7287 u8 second; 7288 u8 unused_0; 7289 __le16 millisecond; 7290 __le16 zone; 7291 #define FW_SET_TIME_REQ_ZONE_UTC 0 7292 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7293 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7294 u8 unused_1[4]; 7295 }; 7296 7297 /* hwrm_fw_set_time_output (size:128b/16B) */ 7298 struct hwrm_fw_set_time_output { 7299 __le16 error_code; 7300 __le16 req_type; 7301 __le16 seq_id; 7302 __le16 resp_len; 7303 u8 unused_0[7]; 7304 u8 valid; 7305 }; 7306 7307 /* hwrm_struct_hdr (size:128b/16B) */ 7308 struct hwrm_struct_hdr { 7309 __le16 struct_id; 7310 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7311 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7312 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7313 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7314 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7315 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7316 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 7317 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 7318 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7319 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7320 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7321 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 7322 __le16 len; 7323 u8 version; 7324 u8 count; 7325 __le16 subtype; 7326 __le16 next_offset; 7327 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7328 u8 unused_0[6]; 7329 }; 7330 7331 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7332 struct hwrm_struct_data_dcbx_app { 7333 __be16 protocol_id; 7334 u8 protocol_selector; 7335 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7336 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7337 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7338 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7339 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 7340 u8 priority; 7341 u8 valid; 7342 u8 unused_0[3]; 7343 }; 7344 7345 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7346 struct hwrm_fw_set_structured_data_input { 7347 __le16 req_type; 7348 __le16 cmpl_ring; 7349 __le16 seq_id; 7350 __le16 target_id; 7351 __le64 resp_addr; 7352 __le64 src_data_addr; 7353 __le16 data_len; 7354 u8 hdr_cnt; 7355 u8 unused_0[5]; 7356 }; 7357 7358 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7359 struct hwrm_fw_set_structured_data_output { 7360 __le16 error_code; 7361 __le16 req_type; 7362 __le16 seq_id; 7363 __le16 resp_len; 7364 u8 unused_0[7]; 7365 u8 valid; 7366 }; 7367 7368 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7369 struct hwrm_fw_set_structured_data_cmd_err { 7370 u8 code; 7371 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7372 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7373 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7374 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7375 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7376 u8 unused_0[7]; 7377 }; 7378 7379 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7380 struct hwrm_fw_get_structured_data_input { 7381 __le16 req_type; 7382 __le16 cmpl_ring; 7383 __le16 seq_id; 7384 __le16 target_id; 7385 __le64 resp_addr; 7386 __le64 dest_data_addr; 7387 __le16 data_len; 7388 __le16 structure_id; 7389 __le16 subtype; 7390 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7391 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7392 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7393 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7394 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7395 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7396 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7397 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7398 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7399 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7400 u8 count; 7401 u8 unused_0; 7402 }; 7403 7404 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7405 struct hwrm_fw_get_structured_data_output { 7406 __le16 error_code; 7407 __le16 req_type; 7408 __le16 seq_id; 7409 __le16 resp_len; 7410 u8 hdr_cnt; 7411 u8 unused_0[6]; 7412 u8 valid; 7413 }; 7414 7415 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7416 struct hwrm_fw_get_structured_data_cmd_err { 7417 u8 code; 7418 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7419 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7420 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7421 u8 unused_0[7]; 7422 }; 7423 7424 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7425 struct hwrm_exec_fwd_resp_input { 7426 __le16 req_type; 7427 __le16 cmpl_ring; 7428 __le16 seq_id; 7429 __le16 target_id; 7430 __le64 resp_addr; 7431 __le32 encap_request[26]; 7432 __le16 encap_resp_target_id; 7433 u8 unused_0[6]; 7434 }; 7435 7436 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7437 struct hwrm_exec_fwd_resp_output { 7438 __le16 error_code; 7439 __le16 req_type; 7440 __le16 seq_id; 7441 __le16 resp_len; 7442 u8 unused_0[7]; 7443 u8 valid; 7444 }; 7445 7446 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7447 struct hwrm_reject_fwd_resp_input { 7448 __le16 req_type; 7449 __le16 cmpl_ring; 7450 __le16 seq_id; 7451 __le16 target_id; 7452 __le64 resp_addr; 7453 __le32 encap_request[26]; 7454 __le16 encap_resp_target_id; 7455 u8 unused_0[6]; 7456 }; 7457 7458 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7459 struct hwrm_reject_fwd_resp_output { 7460 __le16 error_code; 7461 __le16 req_type; 7462 __le16 seq_id; 7463 __le16 resp_len; 7464 u8 unused_0[7]; 7465 u8 valid; 7466 }; 7467 7468 /* hwrm_fwd_resp_input (size:1024b/128B) */ 7469 struct hwrm_fwd_resp_input { 7470 __le16 req_type; 7471 __le16 cmpl_ring; 7472 __le16 seq_id; 7473 __le16 target_id; 7474 __le64 resp_addr; 7475 __le16 encap_resp_target_id; 7476 __le16 encap_resp_cmpl_ring; 7477 __le16 encap_resp_len; 7478 u8 unused_0; 7479 u8 unused_1; 7480 __le64 encap_resp_addr; 7481 __le32 encap_resp[24]; 7482 }; 7483 7484 /* hwrm_fwd_resp_output (size:128b/16B) */ 7485 struct hwrm_fwd_resp_output { 7486 __le16 error_code; 7487 __le16 req_type; 7488 __le16 seq_id; 7489 __le16 resp_len; 7490 u8 unused_0[7]; 7491 u8 valid; 7492 }; 7493 7494 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7495 struct hwrm_fwd_async_event_cmpl_input { 7496 __le16 req_type; 7497 __le16 cmpl_ring; 7498 __le16 seq_id; 7499 __le16 target_id; 7500 __le64 resp_addr; 7501 __le16 encap_async_event_target_id; 7502 u8 unused_0[6]; 7503 __le32 encap_async_event_cmpl[4]; 7504 }; 7505 7506 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7507 struct hwrm_fwd_async_event_cmpl_output { 7508 __le16 error_code; 7509 __le16 req_type; 7510 __le16 seq_id; 7511 __le16 resp_len; 7512 u8 unused_0[7]; 7513 u8 valid; 7514 }; 7515 7516 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7517 struct hwrm_temp_monitor_query_input { 7518 __le16 req_type; 7519 __le16 cmpl_ring; 7520 __le16 seq_id; 7521 __le16 target_id; 7522 __le64 resp_addr; 7523 }; 7524 7525 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7526 struct hwrm_temp_monitor_query_output { 7527 __le16 error_code; 7528 __le16 req_type; 7529 __le16 seq_id; 7530 __le16 resp_len; 7531 u8 temp; 7532 u8 phy_temp; 7533 u8 om_temp; 7534 u8 flags; 7535 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 7536 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 7537 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 7538 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 7539 u8 unused_0[3]; 7540 u8 valid; 7541 }; 7542 7543 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7544 struct hwrm_wol_filter_alloc_input { 7545 __le16 req_type; 7546 __le16 cmpl_ring; 7547 __le16 seq_id; 7548 __le16 target_id; 7549 __le64 resp_addr; 7550 __le32 flags; 7551 __le32 enables; 7552 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7553 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7554 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7555 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7556 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7557 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7558 __le16 port_id; 7559 u8 wol_type; 7560 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7561 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7562 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7563 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7564 u8 unused_0[5]; 7565 u8 mac_address[6]; 7566 __le16 pattern_offset; 7567 __le16 pattern_buf_size; 7568 __le16 pattern_mask_size; 7569 u8 unused_1[4]; 7570 __le64 pattern_buf_addr; 7571 __le64 pattern_mask_addr; 7572 }; 7573 7574 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7575 struct hwrm_wol_filter_alloc_output { 7576 __le16 error_code; 7577 __le16 req_type; 7578 __le16 seq_id; 7579 __le16 resp_len; 7580 u8 wol_filter_id; 7581 u8 unused_0[6]; 7582 u8 valid; 7583 }; 7584 7585 /* hwrm_wol_filter_free_input (size:256b/32B) */ 7586 struct hwrm_wol_filter_free_input { 7587 __le16 req_type; 7588 __le16 cmpl_ring; 7589 __le16 seq_id; 7590 __le16 target_id; 7591 __le64 resp_addr; 7592 __le32 flags; 7593 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7594 __le32 enables; 7595 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7596 __le16 port_id; 7597 u8 wol_filter_id; 7598 u8 unused_0[5]; 7599 }; 7600 7601 /* hwrm_wol_filter_free_output (size:128b/16B) */ 7602 struct hwrm_wol_filter_free_output { 7603 __le16 error_code; 7604 __le16 req_type; 7605 __le16 seq_id; 7606 __le16 resp_len; 7607 u8 unused_0[7]; 7608 u8 valid; 7609 }; 7610 7611 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7612 struct hwrm_wol_filter_qcfg_input { 7613 __le16 req_type; 7614 __le16 cmpl_ring; 7615 __le16 seq_id; 7616 __le16 target_id; 7617 __le64 resp_addr; 7618 __le16 port_id; 7619 __le16 handle; 7620 u8 unused_0[4]; 7621 __le64 pattern_buf_addr; 7622 __le16 pattern_buf_size; 7623 u8 unused_1[6]; 7624 __le64 pattern_mask_addr; 7625 __le16 pattern_mask_size; 7626 u8 unused_2[6]; 7627 }; 7628 7629 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7630 struct hwrm_wol_filter_qcfg_output { 7631 __le16 error_code; 7632 __le16 req_type; 7633 __le16 seq_id; 7634 __le16 resp_len; 7635 __le16 next_handle; 7636 u8 wol_filter_id; 7637 u8 wol_type; 7638 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7639 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7640 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7641 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7642 __le32 unused_0; 7643 u8 mac_address[6]; 7644 __le16 pattern_offset; 7645 __le16 pattern_size; 7646 __le16 pattern_mask_size; 7647 u8 unused_1[3]; 7648 u8 valid; 7649 }; 7650 7651 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7652 struct hwrm_wol_reason_qcfg_input { 7653 __le16 req_type; 7654 __le16 cmpl_ring; 7655 __le16 seq_id; 7656 __le16 target_id; 7657 __le64 resp_addr; 7658 __le16 port_id; 7659 u8 unused_0[6]; 7660 __le64 wol_pkt_buf_addr; 7661 __le16 wol_pkt_buf_size; 7662 u8 unused_1[6]; 7663 }; 7664 7665 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7666 struct hwrm_wol_reason_qcfg_output { 7667 __le16 error_code; 7668 __le16 req_type; 7669 __le16 seq_id; 7670 __le16 resp_len; 7671 u8 wol_filter_id; 7672 u8 wol_reason; 7673 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7674 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7675 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7676 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7677 u8 wol_pkt_len; 7678 u8 unused_0[4]; 7679 u8 valid; 7680 }; 7681 7682 /* hwrm_dbg_read_direct_input (size:256b/32B) */ 7683 struct hwrm_dbg_read_direct_input { 7684 __le16 req_type; 7685 __le16 cmpl_ring; 7686 __le16 seq_id; 7687 __le16 target_id; 7688 __le64 resp_addr; 7689 __le64 host_dest_addr; 7690 __le32 read_addr; 7691 __le32 read_len32; 7692 }; 7693 7694 /* hwrm_dbg_read_direct_output (size:128b/16B) */ 7695 struct hwrm_dbg_read_direct_output { 7696 __le16 error_code; 7697 __le16 req_type; 7698 __le16 seq_id; 7699 __le16 resp_len; 7700 __le32 crc32; 7701 u8 unused_0[3]; 7702 u8 valid; 7703 }; 7704 7705 /* coredump_segment_record (size:128b/16B) */ 7706 struct coredump_segment_record { 7707 __le16 component_id; 7708 __le16 segment_id; 7709 __le16 max_instances; 7710 u8 version_hi; 7711 u8 version_low; 7712 u8 seg_flags; 7713 u8 compress_flags; 7714 #define SFLAG_COMPRESSED_ZLIB 0x1UL 7715 u8 unused_0[2]; 7716 __le32 segment_len; 7717 }; 7718 7719 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7720 struct hwrm_dbg_coredump_list_input { 7721 __le16 req_type; 7722 __le16 cmpl_ring; 7723 __le16 seq_id; 7724 __le16 target_id; 7725 __le64 resp_addr; 7726 __le64 host_dest_addr; 7727 __le32 host_buf_len; 7728 __le16 seq_no; 7729 u8 flags; 7730 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 7731 u8 unused_0[1]; 7732 }; 7733 7734 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7735 struct hwrm_dbg_coredump_list_output { 7736 __le16 error_code; 7737 __le16 req_type; 7738 __le16 seq_id; 7739 __le16 resp_len; 7740 u8 flags; 7741 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7742 u8 unused_0; 7743 __le16 total_segments; 7744 __le16 data_len; 7745 u8 unused_1; 7746 u8 valid; 7747 }; 7748 7749 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7750 struct hwrm_dbg_coredump_initiate_input { 7751 __le16 req_type; 7752 __le16 cmpl_ring; 7753 __le16 seq_id; 7754 __le16 target_id; 7755 __le64 resp_addr; 7756 __le16 component_id; 7757 __le16 segment_id; 7758 __le16 instance; 7759 __le16 unused_0; 7760 u8 seg_flags; 7761 u8 unused_1[7]; 7762 }; 7763 7764 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7765 struct hwrm_dbg_coredump_initiate_output { 7766 __le16 error_code; 7767 __le16 req_type; 7768 __le16 seq_id; 7769 __le16 resp_len; 7770 u8 unused_0[7]; 7771 u8 valid; 7772 }; 7773 7774 /* coredump_data_hdr (size:128b/16B) */ 7775 struct coredump_data_hdr { 7776 __le32 address; 7777 __le32 flags_length; 7778 __le32 instance; 7779 __le32 next_offset; 7780 }; 7781 7782 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 7783 struct hwrm_dbg_coredump_retrieve_input { 7784 __le16 req_type; 7785 __le16 cmpl_ring; 7786 __le16 seq_id; 7787 __le16 target_id; 7788 __le64 resp_addr; 7789 __le64 host_dest_addr; 7790 __le32 host_buf_len; 7791 __le32 unused_0; 7792 __le16 component_id; 7793 __le16 segment_id; 7794 __le16 instance; 7795 __le16 unused_1; 7796 u8 seg_flags; 7797 u8 unused_2; 7798 __le16 unused_3; 7799 __le32 unused_4; 7800 __le32 seq_no; 7801 __le32 unused_5; 7802 }; 7803 7804 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 7805 struct hwrm_dbg_coredump_retrieve_output { 7806 __le16 error_code; 7807 __le16 req_type; 7808 __le16 seq_id; 7809 __le16 resp_len; 7810 u8 flags; 7811 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 7812 u8 unused_0; 7813 __le16 data_len; 7814 u8 unused_1[3]; 7815 u8 valid; 7816 }; 7817 7818 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 7819 struct hwrm_dbg_ring_info_get_input { 7820 __le16 req_type; 7821 __le16 cmpl_ring; 7822 __le16 seq_id; 7823 __le16 target_id; 7824 __le64 resp_addr; 7825 u8 ring_type; 7826 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 7827 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 7828 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 7829 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 7830 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 7831 u8 unused_0[3]; 7832 __le32 fw_ring_id; 7833 }; 7834 7835 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 7836 struct hwrm_dbg_ring_info_get_output { 7837 __le16 error_code; 7838 __le16 req_type; 7839 __le16 seq_id; 7840 __le16 resp_len; 7841 __le32 producer_index; 7842 __le32 consumer_index; 7843 __le32 cag_vector_ctrl; 7844 u8 unused_0[3]; 7845 u8 valid; 7846 }; 7847 7848 /* hwrm_nvm_read_input (size:320b/40B) */ 7849 struct hwrm_nvm_read_input { 7850 __le16 req_type; 7851 __le16 cmpl_ring; 7852 __le16 seq_id; 7853 __le16 target_id; 7854 __le64 resp_addr; 7855 __le64 host_dest_addr; 7856 __le16 dir_idx; 7857 u8 unused_0[2]; 7858 __le32 offset; 7859 __le32 len; 7860 u8 unused_1[4]; 7861 }; 7862 7863 /* hwrm_nvm_read_output (size:128b/16B) */ 7864 struct hwrm_nvm_read_output { 7865 __le16 error_code; 7866 __le16 req_type; 7867 __le16 seq_id; 7868 __le16 resp_len; 7869 u8 unused_0[7]; 7870 u8 valid; 7871 }; 7872 7873 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 7874 struct hwrm_nvm_get_dir_entries_input { 7875 __le16 req_type; 7876 __le16 cmpl_ring; 7877 __le16 seq_id; 7878 __le16 target_id; 7879 __le64 resp_addr; 7880 __le64 host_dest_addr; 7881 }; 7882 7883 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 7884 struct hwrm_nvm_get_dir_entries_output { 7885 __le16 error_code; 7886 __le16 req_type; 7887 __le16 seq_id; 7888 __le16 resp_len; 7889 u8 unused_0[7]; 7890 u8 valid; 7891 }; 7892 7893 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 7894 struct hwrm_nvm_get_dir_info_input { 7895 __le16 req_type; 7896 __le16 cmpl_ring; 7897 __le16 seq_id; 7898 __le16 target_id; 7899 __le64 resp_addr; 7900 }; 7901 7902 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 7903 struct hwrm_nvm_get_dir_info_output { 7904 __le16 error_code; 7905 __le16 req_type; 7906 __le16 seq_id; 7907 __le16 resp_len; 7908 __le32 entries; 7909 __le32 entry_length; 7910 u8 unused_0[7]; 7911 u8 valid; 7912 }; 7913 7914 /* hwrm_nvm_write_input (size:384b/48B) */ 7915 struct hwrm_nvm_write_input { 7916 __le16 req_type; 7917 __le16 cmpl_ring; 7918 __le16 seq_id; 7919 __le16 target_id; 7920 __le64 resp_addr; 7921 __le64 host_src_addr; 7922 __le16 dir_type; 7923 __le16 dir_ordinal; 7924 __le16 dir_ext; 7925 __le16 dir_attr; 7926 __le32 dir_data_length; 7927 __le16 option; 7928 __le16 flags; 7929 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 7930 __le32 dir_item_length; 7931 __le32 unused_0; 7932 }; 7933 7934 /* hwrm_nvm_write_output (size:128b/16B) */ 7935 struct hwrm_nvm_write_output { 7936 __le16 error_code; 7937 __le16 req_type; 7938 __le16 seq_id; 7939 __le16 resp_len; 7940 __le32 dir_item_length; 7941 __le16 dir_idx; 7942 u8 unused_0; 7943 u8 valid; 7944 }; 7945 7946 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 7947 struct hwrm_nvm_write_cmd_err { 7948 u8 code; 7949 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 7950 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7951 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 7952 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 7953 u8 unused_0[7]; 7954 }; 7955 7956 /* hwrm_nvm_modify_input (size:320b/40B) */ 7957 struct hwrm_nvm_modify_input { 7958 __le16 req_type; 7959 __le16 cmpl_ring; 7960 __le16 seq_id; 7961 __le16 target_id; 7962 __le64 resp_addr; 7963 __le64 host_src_addr; 7964 __le16 dir_idx; 7965 __le16 flags; 7966 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 7967 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 7968 __le32 offset; 7969 __le32 len; 7970 u8 unused_1[4]; 7971 }; 7972 7973 /* hwrm_nvm_modify_output (size:128b/16B) */ 7974 struct hwrm_nvm_modify_output { 7975 __le16 error_code; 7976 __le16 req_type; 7977 __le16 seq_id; 7978 __le16 resp_len; 7979 u8 unused_0[7]; 7980 u8 valid; 7981 }; 7982 7983 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 7984 struct hwrm_nvm_find_dir_entry_input { 7985 __le16 req_type; 7986 __le16 cmpl_ring; 7987 __le16 seq_id; 7988 __le16 target_id; 7989 __le64 resp_addr; 7990 __le32 enables; 7991 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 7992 __le16 dir_idx; 7993 __le16 dir_type; 7994 __le16 dir_ordinal; 7995 __le16 dir_ext; 7996 u8 opt_ordinal; 7997 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 7998 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 7999 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 8000 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 8001 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 8002 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 8003 u8 unused_0[3]; 8004 }; 8005 8006 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 8007 struct hwrm_nvm_find_dir_entry_output { 8008 __le16 error_code; 8009 __le16 req_type; 8010 __le16 seq_id; 8011 __le16 resp_len; 8012 __le32 dir_item_length; 8013 __le32 dir_data_length; 8014 __le32 fw_ver; 8015 __le16 dir_ordinal; 8016 __le16 dir_idx; 8017 u8 unused_0[7]; 8018 u8 valid; 8019 }; 8020 8021 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 8022 struct hwrm_nvm_erase_dir_entry_input { 8023 __le16 req_type; 8024 __le16 cmpl_ring; 8025 __le16 seq_id; 8026 __le16 target_id; 8027 __le64 resp_addr; 8028 __le16 dir_idx; 8029 u8 unused_0[6]; 8030 }; 8031 8032 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 8033 struct hwrm_nvm_erase_dir_entry_output { 8034 __le16 error_code; 8035 __le16 req_type; 8036 __le16 seq_id; 8037 __le16 resp_len; 8038 u8 unused_0[7]; 8039 u8 valid; 8040 }; 8041 8042 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 8043 struct hwrm_nvm_get_dev_info_input { 8044 __le16 req_type; 8045 __le16 cmpl_ring; 8046 __le16 seq_id; 8047 __le16 target_id; 8048 __le64 resp_addr; 8049 }; 8050 8051 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 8052 struct hwrm_nvm_get_dev_info_output { 8053 __le16 error_code; 8054 __le16 req_type; 8055 __le16 seq_id; 8056 __le16 resp_len; 8057 __le16 manufacturer_id; 8058 __le16 device_id; 8059 __le32 sector_size; 8060 __le32 nvram_size; 8061 __le32 reserved_size; 8062 __le32 available_size; 8063 u8 nvm_cfg_ver_maj; 8064 u8 nvm_cfg_ver_min; 8065 u8 nvm_cfg_ver_upd; 8066 u8 valid; 8067 }; 8068 8069 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 8070 struct hwrm_nvm_mod_dir_entry_input { 8071 __le16 req_type; 8072 __le16 cmpl_ring; 8073 __le16 seq_id; 8074 __le16 target_id; 8075 __le64 resp_addr; 8076 __le32 enables; 8077 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 8078 __le16 dir_idx; 8079 __le16 dir_ordinal; 8080 __le16 dir_ext; 8081 __le16 dir_attr; 8082 __le32 checksum; 8083 }; 8084 8085 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 8086 struct hwrm_nvm_mod_dir_entry_output { 8087 __le16 error_code; 8088 __le16 req_type; 8089 __le16 seq_id; 8090 __le16 resp_len; 8091 u8 unused_0[7]; 8092 u8 valid; 8093 }; 8094 8095 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 8096 struct hwrm_nvm_verify_update_input { 8097 __le16 req_type; 8098 __le16 cmpl_ring; 8099 __le16 seq_id; 8100 __le16 target_id; 8101 __le64 resp_addr; 8102 __le16 dir_type; 8103 __le16 dir_ordinal; 8104 __le16 dir_ext; 8105 u8 unused_0[2]; 8106 }; 8107 8108 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 8109 struct hwrm_nvm_verify_update_output { 8110 __le16 error_code; 8111 __le16 req_type; 8112 __le16 seq_id; 8113 __le16 resp_len; 8114 u8 unused_0[7]; 8115 u8 valid; 8116 }; 8117 8118 /* hwrm_nvm_install_update_input (size:192b/24B) */ 8119 struct hwrm_nvm_install_update_input { 8120 __le16 req_type; 8121 __le16 cmpl_ring; 8122 __le16 seq_id; 8123 __le16 target_id; 8124 __le64 resp_addr; 8125 __le32 install_type; 8126 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 8127 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 8128 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 8129 __le16 flags; 8130 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 8131 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 8132 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 8133 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 8134 u8 unused_0[2]; 8135 }; 8136 8137 /* hwrm_nvm_install_update_output (size:192b/24B) */ 8138 struct hwrm_nvm_install_update_output { 8139 __le16 error_code; 8140 __le16 req_type; 8141 __le16 seq_id; 8142 __le16 resp_len; 8143 __le64 installed_items; 8144 u8 result; 8145 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 8146 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 8147 u8 problem_item; 8148 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 8149 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 8150 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 8151 u8 reset_required; 8152 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 8153 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 8154 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 8155 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 8156 u8 unused_0[4]; 8157 u8 valid; 8158 }; 8159 8160 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 8161 struct hwrm_nvm_install_update_cmd_err { 8162 u8 code; 8163 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 8164 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8165 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 8166 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 8167 u8 unused_0[7]; 8168 }; 8169 8170 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 8171 struct hwrm_nvm_get_variable_input { 8172 __le16 req_type; 8173 __le16 cmpl_ring; 8174 __le16 seq_id; 8175 __le16 target_id; 8176 __le64 resp_addr; 8177 __le64 dest_data_addr; 8178 __le16 data_len; 8179 __le16 option_num; 8180 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8181 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8182 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8183 __le16 dimensions; 8184 __le16 index_0; 8185 __le16 index_1; 8186 __le16 index_2; 8187 __le16 index_3; 8188 u8 flags; 8189 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 8190 u8 unused_0; 8191 }; 8192 8193 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 8194 struct hwrm_nvm_get_variable_output { 8195 __le16 error_code; 8196 __le16 req_type; 8197 __le16 seq_id; 8198 __le16 resp_len; 8199 __le16 data_len; 8200 __le16 option_num; 8201 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 8202 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 8203 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 8204 u8 unused_0[3]; 8205 u8 valid; 8206 }; 8207 8208 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8209 struct hwrm_nvm_get_variable_cmd_err { 8210 u8 code; 8211 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8212 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8213 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8214 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8215 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8216 u8 unused_0[7]; 8217 }; 8218 8219 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8220 struct hwrm_nvm_set_variable_input { 8221 __le16 req_type; 8222 __le16 cmpl_ring; 8223 __le16 seq_id; 8224 __le16 target_id; 8225 __le64 resp_addr; 8226 __le64 src_data_addr; 8227 __le16 data_len; 8228 __le16 option_num; 8229 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8230 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8231 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8232 __le16 dimensions; 8233 __le16 index_0; 8234 __le16 index_1; 8235 __le16 index_2; 8236 __le16 index_3; 8237 u8 flags; 8238 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8239 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8240 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8241 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8242 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 8243 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 8244 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 8245 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 8246 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 8247 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 8248 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8249 u8 unused_0; 8250 }; 8251 8252 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8253 struct hwrm_nvm_set_variable_output { 8254 __le16 error_code; 8255 __le16 req_type; 8256 __le16 seq_id; 8257 __le16 resp_len; 8258 u8 unused_0[7]; 8259 u8 valid; 8260 }; 8261 8262 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8263 struct hwrm_nvm_set_variable_cmd_err { 8264 u8 code; 8265 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8266 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8267 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8268 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8269 u8 unused_0[7]; 8270 }; 8271 8272 /* hwrm_selftest_qlist_input (size:128b/16B) */ 8273 struct hwrm_selftest_qlist_input { 8274 __le16 req_type; 8275 __le16 cmpl_ring; 8276 __le16 seq_id; 8277 __le16 target_id; 8278 __le64 resp_addr; 8279 }; 8280 8281 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8282 struct hwrm_selftest_qlist_output { 8283 __le16 error_code; 8284 __le16 req_type; 8285 __le16 seq_id; 8286 __le16 resp_len; 8287 u8 num_tests; 8288 u8 available_tests; 8289 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8290 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8291 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8292 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8293 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8294 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8295 u8 offline_tests; 8296 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8297 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8298 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8299 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8300 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8301 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8302 u8 unused_0; 8303 __le16 test_timeout; 8304 u8 unused_1[2]; 8305 char test0_name[32]; 8306 char test1_name[32]; 8307 char test2_name[32]; 8308 char test3_name[32]; 8309 char test4_name[32]; 8310 char test5_name[32]; 8311 char test6_name[32]; 8312 char test7_name[32]; 8313 u8 eyescope_target_BER_support; 8314 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 8315 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 8316 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 8317 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 8318 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 8319 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 8320 u8 unused_2[6]; 8321 u8 valid; 8322 }; 8323 8324 /* hwrm_selftest_exec_input (size:192b/24B) */ 8325 struct hwrm_selftest_exec_input { 8326 __le16 req_type; 8327 __le16 cmpl_ring; 8328 __le16 seq_id; 8329 __le16 target_id; 8330 __le64 resp_addr; 8331 u8 flags; 8332 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8333 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8334 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8335 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8336 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8337 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8338 u8 unused_0[7]; 8339 }; 8340 8341 /* hwrm_selftest_exec_output (size:128b/16B) */ 8342 struct hwrm_selftest_exec_output { 8343 __le16 error_code; 8344 __le16 req_type; 8345 __le16 seq_id; 8346 __le16 resp_len; 8347 u8 requested_tests; 8348 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8349 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8350 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8351 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8352 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8353 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8354 u8 test_success; 8355 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8356 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8357 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8358 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8359 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8360 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8361 u8 unused_0[5]; 8362 u8 valid; 8363 }; 8364 8365 /* hwrm_selftest_irq_input (size:128b/16B) */ 8366 struct hwrm_selftest_irq_input { 8367 __le16 req_type; 8368 __le16 cmpl_ring; 8369 __le16 seq_id; 8370 __le16 target_id; 8371 __le64 resp_addr; 8372 }; 8373 8374 /* hwrm_selftest_irq_output (size:128b/16B) */ 8375 struct hwrm_selftest_irq_output { 8376 __le16 error_code; 8377 __le16 req_type; 8378 __le16 seq_id; 8379 __le16 resp_len; 8380 u8 unused_0[7]; 8381 u8 valid; 8382 }; 8383 8384 /* fw_status_reg (size:32b/4B) */ 8385 struct fw_status_reg { 8386 u32 fw_status; 8387 #define FW_STATUS_REG_CODE_MASK 0xffffUL 8388 #define FW_STATUS_REG_CODE_SFT 0 8389 #define FW_STATUS_REG_CODE_READY 0x8000UL 8390 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8391 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8392 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8393 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8394 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8395 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8396 }; 8397 8398 #endif /* _BNXT_HSI_H_ */ 8399