1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_HSI_H 12 #define BNXT_HSI_H 13 14 /* HSI and HWRM Specification 1.7.6 */ 15 #define HWRM_VERSION_MAJOR 1 16 #define HWRM_VERSION_MINOR 7 17 #define HWRM_VERSION_UPDATE 6 18 19 #define HWRM_VERSION_RSVD 2 /* non-zero means beta version */ 20 21 #define HWRM_VERSION_STR "1.7.6.2" 22 /* 23 * Following is the signature for HWRM message field that indicates not 24 * applicable (All F's). Need to cast it the size of the field if needed. 25 */ 26 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 27 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 28 #define HWRM_MAX_RESP_LEN (248) /* hwrm_selftest_qlist */ 29 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 30 #define HW_HASH_KEY_SIZE 40 31 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 32 33 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 34 struct eject_cmpl { 35 __le16 type; 36 #define EJECT_CMPL_TYPE_MASK 0x3fUL 37 #define EJECT_CMPL_TYPE_SFT 0 38 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 39 __le16 len; 40 __le32 opaque; 41 __le32 v; 42 #define EJECT_CMPL_V 0x1UL 43 __le32 unused_2; 44 }; 45 46 /* HWRM Completion Record (16 bytes) */ 47 struct hwrm_cmpl { 48 __le16 type; 49 #define CMPL_TYPE_MASK 0x3fUL 50 #define CMPL_TYPE_SFT 0 51 #define CMPL_TYPE_HWRM_DONE 0x20UL 52 __le16 sequence_id; 53 __le32 unused_1; 54 __le32 v; 55 #define CMPL_V 0x1UL 56 __le32 unused_3; 57 }; 58 59 /* HWRM Forwarded Request (16 bytes) */ 60 struct hwrm_fwd_req_cmpl { 61 __le16 req_len_type; 62 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 63 #define FWD_REQ_CMPL_TYPE_SFT 0 64 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 65 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 66 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 67 __le16 source_id; 68 __le32 unused_0; 69 __le32 req_buf_addr_v[2]; 70 #define FWD_REQ_CMPL_V 0x1UL 71 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 72 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 73 }; 74 75 /* HWRM Forwarded Response (16 bytes) */ 76 struct hwrm_fwd_resp_cmpl { 77 __le16 type; 78 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 79 #define FWD_RESP_CMPL_TYPE_SFT 0 80 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 81 __le16 source_id; 82 __le16 resp_len; 83 __le16 unused_1; 84 __le32 resp_buf_addr_v[2]; 85 #define FWD_RESP_CMPL_V 0x1UL 86 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 87 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 88 }; 89 90 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 91 struct hwrm_async_event_cmpl { 92 __le16 type; 93 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 94 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 95 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 96 __le16 event_id; 97 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 98 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 99 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 100 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 101 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 102 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 103 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 104 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 105 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 106 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 107 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 108 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 109 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 110 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 111 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 112 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 113 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 114 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 115 __le32 event_data2; 116 u8 opaque_v; 117 #define ASYNC_EVENT_CMPL_V 0x1UL 118 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 119 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 120 u8 timestamp_lo; 121 __le16 timestamp_hi; 122 __le32 event_data1; 123 }; 124 125 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 126 struct hwrm_async_event_cmpl_link_status_change { 127 __le16 type; 128 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 129 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 130 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 131 __le16 event_id; 132 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 133 __le32 event_data2; 134 u8 opaque_v; 135 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 136 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 137 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 138 u8 timestamp_lo; 139 __le16 timestamp_hi; 140 __le32 event_data1; 141 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 142 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 143 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 144 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 145 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 146 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 147 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 148 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 149 }; 150 151 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 152 struct hwrm_async_event_cmpl_link_mtu_change { 153 __le16 type; 154 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 155 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 156 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 157 __le16 event_id; 158 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 159 __le32 event_data2; 160 u8 opaque_v; 161 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 162 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 163 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 164 u8 timestamp_lo; 165 __le16 timestamp_hi; 166 __le32 event_data1; 167 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 168 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 169 }; 170 171 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 172 struct hwrm_async_event_cmpl_link_speed_change { 173 __le16 type; 174 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 175 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 176 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 177 __le16 event_id; 178 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 179 __le32 event_data2; 180 u8 opaque_v; 181 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 182 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 183 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 184 u8 timestamp_lo; 185 __le16 timestamp_hi; 186 __le32 event_data1; 187 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 188 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 189 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 190 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 191 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 192 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 193 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 194 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 195 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 196 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 197 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 198 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 199 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 200 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 201 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 202 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 203 }; 204 205 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 206 struct hwrm_async_event_cmpl_dcb_config_change { 207 __le16 type; 208 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 209 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 210 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 211 __le16 event_id; 212 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 213 __le32 event_data2; 214 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 215 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 216 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 217 u8 opaque_v; 218 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 219 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 220 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 221 u8 timestamp_lo; 222 __le16 timestamp_hi; 223 __le32 event_data1; 224 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 225 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 226 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 227 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 228 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 229 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 230 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 231 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 232 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 233 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 234 }; 235 236 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 237 struct hwrm_async_event_cmpl_port_conn_not_allowed { 238 __le16 type; 239 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 240 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 241 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 242 __le16 event_id; 243 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 244 __le32 event_data2; 245 u8 opaque_v; 246 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 247 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 248 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 249 u8 timestamp_lo; 250 __le16 timestamp_hi; 251 __le32 event_data1; 252 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 253 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 254 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 255 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 256 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 257 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 258 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 259 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 260 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 261 }; 262 263 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 264 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 265 __le16 type; 266 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 267 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 268 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 269 __le16 event_id; 270 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 271 __le32 event_data2; 272 u8 opaque_v; 273 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 274 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 275 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 276 u8 timestamp_lo; 277 __le16 timestamp_hi; 278 __le32 event_data1; 279 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 280 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 281 }; 282 283 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 284 struct hwrm_async_event_cmpl_link_speed_cfg_change { 285 __le16 type; 286 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 287 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 288 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 289 __le16 event_id; 290 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 291 __le32 event_data2; 292 u8 opaque_v; 293 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 294 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 295 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 296 u8 timestamp_lo; 297 __le16 timestamp_hi; 298 __le32 event_data1; 299 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 300 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 301 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 302 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 303 }; 304 305 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 306 struct hwrm_async_event_cmpl_func_drvr_unload { 307 __le16 type; 308 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 309 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 310 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 311 __le16 event_id; 312 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 313 __le32 event_data2; 314 u8 opaque_v; 315 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 316 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 317 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 318 u8 timestamp_lo; 319 __le16 timestamp_hi; 320 __le32 event_data1; 321 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 322 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 323 }; 324 325 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 326 struct hwrm_async_event_cmpl_func_drvr_load { 327 __le16 type; 328 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 329 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 330 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 331 __le16 event_id; 332 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 333 __le32 event_data2; 334 u8 opaque_v; 335 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 336 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 337 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 338 u8 timestamp_lo; 339 __le16 timestamp_hi; 340 __le32 event_data1; 341 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 342 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 343 }; 344 345 /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ 346 struct hwrm_async_event_cmpl_func_flr_proc_cmplt { 347 __le16 type; 348 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL 349 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 350 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 351 __le16 event_id; 352 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 353 __le32 event_data2; 354 u8 opaque_v; 355 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL 356 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL 357 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 358 u8 timestamp_lo; 359 __le16 timestamp_hi; 360 __le32 event_data1; 361 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 362 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 363 }; 364 365 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 366 struct hwrm_async_event_cmpl_pf_drvr_unload { 367 __le16 type; 368 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 369 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 370 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 371 __le16 event_id; 372 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 373 __le32 event_data2; 374 u8 opaque_v; 375 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 376 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 377 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 378 u8 timestamp_lo; 379 __le16 timestamp_hi; 380 __le32 event_data1; 381 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 382 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 383 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 384 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 385 }; 386 387 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 388 struct hwrm_async_event_cmpl_pf_drvr_load { 389 __le16 type; 390 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 391 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 392 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 393 __le16 event_id; 394 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 395 __le32 event_data2; 396 u8 opaque_v; 397 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 398 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 399 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 400 u8 timestamp_lo; 401 __le16 timestamp_hi; 402 __le32 event_data1; 403 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 404 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 405 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 406 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 407 }; 408 409 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 410 struct hwrm_async_event_cmpl_vf_flr { 411 __le16 type; 412 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 413 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 414 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 415 __le16 event_id; 416 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 417 __le32 event_data2; 418 u8 opaque_v; 419 #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 420 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 421 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 422 u8 timestamp_lo; 423 __le16 timestamp_hi; 424 __le32 event_data1; 425 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 426 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 427 }; 428 429 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 430 struct hwrm_async_event_cmpl_vf_mac_addr_change { 431 __le16 type; 432 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 433 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 434 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 435 __le16 event_id; 436 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 437 __le32 event_data2; 438 u8 opaque_v; 439 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 440 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 441 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 442 u8 timestamp_lo; 443 __le16 timestamp_hi; 444 __le32 event_data1; 445 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 446 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 447 }; 448 449 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 450 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 451 __le16 type; 452 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 453 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 454 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 455 __le16 event_id; 456 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 457 __le32 event_data2; 458 u8 opaque_v; 459 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 460 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 461 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 462 u8 timestamp_lo; 463 __le16 timestamp_hi; 464 __le32 event_data1; 465 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 466 }; 467 468 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 469 struct hwrm_async_event_cmpl_vf_cfg_change { 470 __le16 type; 471 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 472 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 473 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 474 __le16 event_id; 475 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 476 __le32 event_data2; 477 u8 opaque_v; 478 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 479 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 480 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 481 u8 timestamp_lo; 482 __le16 timestamp_hi; 483 __le32 event_data1; 484 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 485 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 486 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 487 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 488 }; 489 490 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 491 struct hwrm_async_event_cmpl_hwrm_error { 492 __le16 type; 493 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 494 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 495 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 496 __le16 event_id; 497 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 498 __le32 event_data2; 499 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 500 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 501 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 502 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 503 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 504 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 505 u8 opaque_v; 506 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 507 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 508 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 509 u8 timestamp_lo; 510 __le16 timestamp_hi; 511 __le32 event_data1; 512 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 513 }; 514 515 /* hwrm_ver_get */ 516 /* Input (24 bytes) */ 517 struct hwrm_ver_get_input { 518 __le16 req_type; 519 __le16 cmpl_ring; 520 __le16 seq_id; 521 __le16 target_id; 522 __le64 resp_addr; 523 u8 hwrm_intf_maj; 524 u8 hwrm_intf_min; 525 u8 hwrm_intf_upd; 526 u8 unused_0[5]; 527 }; 528 529 /* Output (128 bytes) */ 530 struct hwrm_ver_get_output { 531 __le16 error_code; 532 __le16 req_type; 533 __le16 seq_id; 534 __le16 resp_len; 535 u8 hwrm_intf_maj; 536 u8 hwrm_intf_min; 537 u8 hwrm_intf_upd; 538 u8 hwrm_intf_rsvd; 539 u8 hwrm_fw_maj; 540 u8 hwrm_fw_min; 541 u8 hwrm_fw_bld; 542 u8 hwrm_fw_rsvd; 543 u8 mgmt_fw_maj; 544 u8 mgmt_fw_min; 545 u8 mgmt_fw_bld; 546 u8 mgmt_fw_rsvd; 547 u8 netctrl_fw_maj; 548 u8 netctrl_fw_min; 549 u8 netctrl_fw_bld; 550 u8 netctrl_fw_rsvd; 551 __le32 dev_caps_cfg; 552 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 553 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 554 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 555 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 556 u8 roce_fw_maj; 557 u8 roce_fw_min; 558 u8 roce_fw_bld; 559 u8 roce_fw_rsvd; 560 char hwrm_fw_name[16]; 561 char mgmt_fw_name[16]; 562 char netctrl_fw_name[16]; 563 __le32 reserved2[4]; 564 char roce_fw_name[16]; 565 __le16 chip_num; 566 u8 chip_rev; 567 u8 chip_metal; 568 u8 chip_bond_id; 569 u8 chip_platform_type; 570 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 571 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 572 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 573 __le16 max_req_win_len; 574 __le16 max_resp_len; 575 __le16 def_req_timeout; 576 u8 init_pending; 577 #define VER_GET_RESP_INIT_PENDING_DEV_NOT_RDY 0x1UL 578 u8 unused_0; 579 u8 unused_1; 580 u8 valid; 581 }; 582 583 /* hwrm_func_reset */ 584 /* Input (24 bytes) */ 585 struct hwrm_func_reset_input { 586 __le16 req_type; 587 __le16 cmpl_ring; 588 __le16 seq_id; 589 __le16 target_id; 590 __le64 resp_addr; 591 __le32 enables; 592 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 593 __le16 vf_id; 594 u8 func_reset_level; 595 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 596 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 597 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 598 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 599 u8 unused_0; 600 }; 601 602 /* Output (16 bytes) */ 603 struct hwrm_func_reset_output { 604 __le16 error_code; 605 __le16 req_type; 606 __le16 seq_id; 607 __le16 resp_len; 608 __le32 unused_0; 609 u8 unused_1; 610 u8 unused_2; 611 u8 unused_3; 612 u8 valid; 613 }; 614 615 /* hwrm_func_getfid */ 616 /* Input (24 bytes) */ 617 struct hwrm_func_getfid_input { 618 __le16 req_type; 619 __le16 cmpl_ring; 620 __le16 seq_id; 621 __le16 target_id; 622 __le64 resp_addr; 623 __le32 enables; 624 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 625 __le16 pci_id; 626 __le16 unused_0; 627 }; 628 629 /* Output (16 bytes) */ 630 struct hwrm_func_getfid_output { 631 __le16 error_code; 632 __le16 req_type; 633 __le16 seq_id; 634 __le16 resp_len; 635 __le16 fid; 636 u8 unused_0; 637 u8 unused_1; 638 u8 unused_2; 639 u8 unused_3; 640 u8 unused_4; 641 u8 valid; 642 }; 643 644 /* hwrm_func_vf_alloc */ 645 /* Input (24 bytes) */ 646 struct hwrm_func_vf_alloc_input { 647 __le16 req_type; 648 __le16 cmpl_ring; 649 __le16 seq_id; 650 __le16 target_id; 651 __le64 resp_addr; 652 __le32 enables; 653 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 654 __le16 first_vf_id; 655 __le16 num_vfs; 656 }; 657 658 /* Output (16 bytes) */ 659 struct hwrm_func_vf_alloc_output { 660 __le16 error_code; 661 __le16 req_type; 662 __le16 seq_id; 663 __le16 resp_len; 664 __le16 first_vf_id; 665 u8 unused_0; 666 u8 unused_1; 667 u8 unused_2; 668 u8 unused_3; 669 u8 unused_4; 670 u8 valid; 671 }; 672 673 /* hwrm_func_vf_free */ 674 /* Input (24 bytes) */ 675 struct hwrm_func_vf_free_input { 676 __le16 req_type; 677 __le16 cmpl_ring; 678 __le16 seq_id; 679 __le16 target_id; 680 __le64 resp_addr; 681 __le32 enables; 682 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 683 __le16 first_vf_id; 684 __le16 num_vfs; 685 }; 686 687 /* Output (16 bytes) */ 688 struct hwrm_func_vf_free_output { 689 __le16 error_code; 690 __le16 req_type; 691 __le16 seq_id; 692 __le16 resp_len; 693 __le32 unused_0; 694 u8 unused_1; 695 u8 unused_2; 696 u8 unused_3; 697 u8 valid; 698 }; 699 700 /* hwrm_func_vf_cfg */ 701 /* Input (32 bytes) */ 702 struct hwrm_func_vf_cfg_input { 703 __le16 req_type; 704 __le16 cmpl_ring; 705 __le16 seq_id; 706 __le16 target_id; 707 __le64 resp_addr; 708 __le32 enables; 709 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 710 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 711 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 712 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 713 __le16 mtu; 714 __le16 guest_vlan; 715 __le16 async_event_cr; 716 u8 dflt_mac_addr[6]; 717 }; 718 719 /* Output (16 bytes) */ 720 struct hwrm_func_vf_cfg_output { 721 __le16 error_code; 722 __le16 req_type; 723 __le16 seq_id; 724 __le16 resp_len; 725 __le32 unused_0; 726 u8 unused_1; 727 u8 unused_2; 728 u8 unused_3; 729 u8 valid; 730 }; 731 732 /* hwrm_func_qcaps */ 733 /* Input (24 bytes) */ 734 struct hwrm_func_qcaps_input { 735 __le16 req_type; 736 __le16 cmpl_ring; 737 __le16 seq_id; 738 __le16 target_id; 739 __le64 resp_addr; 740 __le16 fid; 741 __le16 unused_0[3]; 742 }; 743 744 /* Output (80 bytes) */ 745 struct hwrm_func_qcaps_output { 746 __le16 error_code; 747 __le16 req_type; 748 __le16 seq_id; 749 __le16 resp_len; 750 __le16 fid; 751 __le16 port_id; 752 __le32 flags; 753 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 754 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 755 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 756 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 757 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 758 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 759 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 760 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 761 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 762 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 763 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 764 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 765 u8 mac_address[6]; 766 __le16 max_rsscos_ctx; 767 __le16 max_cmpl_rings; 768 __le16 max_tx_rings; 769 __le16 max_rx_rings; 770 __le16 max_l2_ctxs; 771 __le16 max_vnics; 772 __le16 first_vf_id; 773 __le16 max_vfs; 774 __le16 max_stat_ctx; 775 __le32 max_encap_records; 776 __le32 max_decap_records; 777 __le32 max_tx_em_flows; 778 __le32 max_tx_wm_flows; 779 __le32 max_rx_em_flows; 780 __le32 max_rx_wm_flows; 781 __le32 max_mcast_filters; 782 __le32 max_flow_id; 783 __le32 max_hw_ring_grps; 784 __le16 max_sp_tx_rings; 785 u8 unused_0; 786 u8 valid; 787 }; 788 789 /* hwrm_func_qcfg */ 790 /* Input (24 bytes) */ 791 struct hwrm_func_qcfg_input { 792 __le16 req_type; 793 __le16 cmpl_ring; 794 __le16 seq_id; 795 __le16 target_id; 796 __le64 resp_addr; 797 __le16 fid; 798 __le16 unused_0[3]; 799 }; 800 801 /* Output (72 bytes) */ 802 struct hwrm_func_qcfg_output { 803 __le16 error_code; 804 __le16 req_type; 805 __le16 seq_id; 806 __le16 resp_len; 807 __le16 fid; 808 __le16 port_id; 809 __le16 vlan; 810 __le16 flags; 811 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 812 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 813 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 814 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 815 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 816 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 817 u8 mac_address[6]; 818 __le16 pci_id; 819 __le16 alloc_rsscos_ctx; 820 __le16 alloc_cmpl_rings; 821 __le16 alloc_tx_rings; 822 __le16 alloc_rx_rings; 823 __le16 alloc_l2_ctx; 824 __le16 alloc_vnics; 825 __le16 mtu; 826 __le16 mru; 827 __le16 stat_ctx_id; 828 u8 port_partition_type; 829 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 830 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 831 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 832 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 833 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 834 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 835 u8 port_pf_cnt; 836 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 837 __le16 dflt_vnic_id; 838 u8 host_cnt; 839 #define FUNC_QCFG_RESP_HOST_CNT_UNAVAIL 0x0UL 840 u8 unused_0; 841 __le32 min_bw; 842 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 843 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 844 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 845 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 846 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 847 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 848 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 849 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 850 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 851 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 852 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 853 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 854 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 855 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 856 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 857 __le32 max_bw; 858 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 859 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 860 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 861 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 862 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 863 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 864 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 865 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 866 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 867 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 868 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 869 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 870 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 871 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 872 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 873 u8 evb_mode; 874 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 875 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 876 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 877 u8 unused_1; 878 __le16 alloc_vfs; 879 __le32 alloc_mcast_filters; 880 __le32 alloc_hw_ring_grps; 881 __le16 alloc_sp_tx_rings; 882 u8 unused_2; 883 u8 valid; 884 }; 885 886 /* hwrm_func_cfg */ 887 /* Input (88 bytes) */ 888 struct hwrm_func_cfg_input { 889 __le16 req_type; 890 __le16 cmpl_ring; 891 __le16 seq_id; 892 __le16 target_id; 893 __le64 resp_addr; 894 __le16 fid; 895 u8 unused_0; 896 u8 unused_1; 897 __le32 flags; 898 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 899 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 900 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 901 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 902 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 903 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 904 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 905 __le32 enables; 906 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 907 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 908 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 909 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 910 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 911 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 912 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 913 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 914 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 915 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 916 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 917 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 918 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 919 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 920 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 921 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 922 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 923 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 924 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 925 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 926 __le16 mtu; 927 __le16 mru; 928 __le16 num_rsscos_ctxs; 929 __le16 num_cmpl_rings; 930 __le16 num_tx_rings; 931 __le16 num_rx_rings; 932 __le16 num_l2_ctxs; 933 __le16 num_vnics; 934 __le16 num_stat_ctxs; 935 __le16 num_hw_ring_grps; 936 u8 dflt_mac_addr[6]; 937 __le16 dflt_vlan; 938 __be32 dflt_ip_addr[4]; 939 __le32 min_bw; 940 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 941 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 942 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 943 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 944 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 945 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 946 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 947 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 948 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 949 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 950 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 951 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 952 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 953 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 954 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 955 __le32 max_bw; 956 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 957 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 958 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 959 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 960 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 961 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 962 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 963 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 964 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 965 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 966 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 967 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 968 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 969 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 970 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 971 __le16 async_event_cr; 972 u8 vlan_antispoof_mode; 973 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 974 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 975 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 976 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 977 u8 allowed_vlan_pris; 978 u8 evb_mode; 979 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 980 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 981 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 982 u8 unused_2; 983 __le16 num_mcast_filters; 984 }; 985 986 /* Output (16 bytes) */ 987 struct hwrm_func_cfg_output { 988 __le16 error_code; 989 __le16 req_type; 990 __le16 seq_id; 991 __le16 resp_len; 992 __le32 unused_0; 993 u8 unused_1; 994 u8 unused_2; 995 u8 unused_3; 996 u8 valid; 997 }; 998 999 /* hwrm_func_qstats */ 1000 /* Input (24 bytes) */ 1001 struct hwrm_func_qstats_input { 1002 __le16 req_type; 1003 __le16 cmpl_ring; 1004 __le16 seq_id; 1005 __le16 target_id; 1006 __le64 resp_addr; 1007 __le16 fid; 1008 __le16 unused_0[3]; 1009 }; 1010 1011 /* Output (176 bytes) */ 1012 struct hwrm_func_qstats_output { 1013 __le16 error_code; 1014 __le16 req_type; 1015 __le16 seq_id; 1016 __le16 resp_len; 1017 __le64 tx_ucast_pkts; 1018 __le64 tx_mcast_pkts; 1019 __le64 tx_bcast_pkts; 1020 __le64 tx_discard_pkts; 1021 __le64 tx_drop_pkts; 1022 __le64 tx_ucast_bytes; 1023 __le64 tx_mcast_bytes; 1024 __le64 tx_bcast_bytes; 1025 __le64 rx_ucast_pkts; 1026 __le64 rx_mcast_pkts; 1027 __le64 rx_bcast_pkts; 1028 __le64 rx_discard_pkts; 1029 __le64 rx_drop_pkts; 1030 __le64 rx_ucast_bytes; 1031 __le64 rx_mcast_bytes; 1032 __le64 rx_bcast_bytes; 1033 __le64 rx_agg_pkts; 1034 __le64 rx_agg_bytes; 1035 __le64 rx_agg_events; 1036 __le64 rx_agg_aborts; 1037 __le32 unused_0; 1038 u8 unused_1; 1039 u8 unused_2; 1040 u8 unused_3; 1041 u8 valid; 1042 }; 1043 1044 /* hwrm_func_clr_stats */ 1045 /* Input (24 bytes) */ 1046 struct hwrm_func_clr_stats_input { 1047 __le16 req_type; 1048 __le16 cmpl_ring; 1049 __le16 seq_id; 1050 __le16 target_id; 1051 __le64 resp_addr; 1052 __le16 fid; 1053 __le16 unused_0[3]; 1054 }; 1055 1056 /* Output (16 bytes) */ 1057 struct hwrm_func_clr_stats_output { 1058 __le16 error_code; 1059 __le16 req_type; 1060 __le16 seq_id; 1061 __le16 resp_len; 1062 __le32 unused_0; 1063 u8 unused_1; 1064 u8 unused_2; 1065 u8 unused_3; 1066 u8 valid; 1067 }; 1068 1069 /* hwrm_func_vf_resc_free */ 1070 /* Input (24 bytes) */ 1071 struct hwrm_func_vf_resc_free_input { 1072 __le16 req_type; 1073 __le16 cmpl_ring; 1074 __le16 seq_id; 1075 __le16 target_id; 1076 __le64 resp_addr; 1077 __le16 vf_id; 1078 __le16 unused_0[3]; 1079 }; 1080 1081 /* Output (16 bytes) */ 1082 struct hwrm_func_vf_resc_free_output { 1083 __le16 error_code; 1084 __le16 req_type; 1085 __le16 seq_id; 1086 __le16 resp_len; 1087 __le32 unused_0; 1088 u8 unused_1; 1089 u8 unused_2; 1090 u8 unused_3; 1091 u8 valid; 1092 }; 1093 1094 /* hwrm_func_vf_vnic_ids_query */ 1095 /* Input (32 bytes) */ 1096 struct hwrm_func_vf_vnic_ids_query_input { 1097 __le16 req_type; 1098 __le16 cmpl_ring; 1099 __le16 seq_id; 1100 __le16 target_id; 1101 __le64 resp_addr; 1102 __le16 vf_id; 1103 u8 unused_0; 1104 u8 unused_1; 1105 __le32 max_vnic_id_cnt; 1106 __le64 vnic_id_tbl_addr; 1107 }; 1108 1109 /* Output (16 bytes) */ 1110 struct hwrm_func_vf_vnic_ids_query_output { 1111 __le16 error_code; 1112 __le16 req_type; 1113 __le16 seq_id; 1114 __le16 resp_len; 1115 __le32 vnic_id_cnt; 1116 u8 unused_0; 1117 u8 unused_1; 1118 u8 unused_2; 1119 u8 valid; 1120 }; 1121 1122 /* hwrm_func_drv_rgtr */ 1123 /* Input (80 bytes) */ 1124 struct hwrm_func_drv_rgtr_input { 1125 __le16 req_type; 1126 __le16 cmpl_ring; 1127 __le16 seq_id; 1128 __le16 target_id; 1129 __le64 resp_addr; 1130 __le32 flags; 1131 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1132 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1133 __le32 enables; 1134 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1135 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1136 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1137 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1138 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1139 __le16 os_type; 1140 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1141 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1142 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1143 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1144 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1145 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1146 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1147 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1148 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1149 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1150 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1151 u8 ver_maj; 1152 u8 ver_min; 1153 u8 ver_upd; 1154 u8 unused_0; 1155 __le16 unused_1; 1156 __le32 timestamp; 1157 __le32 unused_2; 1158 __le32 vf_req_fwd[8]; 1159 __le32 async_event_fwd[8]; 1160 }; 1161 1162 /* Output (16 bytes) */ 1163 struct hwrm_func_drv_rgtr_output { 1164 __le16 error_code; 1165 __le16 req_type; 1166 __le16 seq_id; 1167 __le16 resp_len; 1168 __le32 unused_0; 1169 u8 unused_1; 1170 u8 unused_2; 1171 u8 unused_3; 1172 u8 valid; 1173 }; 1174 1175 /* hwrm_func_drv_unrgtr */ 1176 /* Input (24 bytes) */ 1177 struct hwrm_func_drv_unrgtr_input { 1178 __le16 req_type; 1179 __le16 cmpl_ring; 1180 __le16 seq_id; 1181 __le16 target_id; 1182 __le64 resp_addr; 1183 __le32 flags; 1184 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1185 __le32 unused_0; 1186 }; 1187 1188 /* Output (16 bytes) */ 1189 struct hwrm_func_drv_unrgtr_output { 1190 __le16 error_code; 1191 __le16 req_type; 1192 __le16 seq_id; 1193 __le16 resp_len; 1194 __le32 unused_0; 1195 u8 unused_1; 1196 u8 unused_2; 1197 u8 unused_3; 1198 u8 valid; 1199 }; 1200 1201 /* hwrm_func_buf_rgtr */ 1202 /* Input (128 bytes) */ 1203 struct hwrm_func_buf_rgtr_input { 1204 __le16 req_type; 1205 __le16 cmpl_ring; 1206 __le16 seq_id; 1207 __le16 target_id; 1208 __le64 resp_addr; 1209 __le32 enables; 1210 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1211 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1212 __le16 vf_id; 1213 __le16 req_buf_num_pages; 1214 __le16 req_buf_page_size; 1215 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1216 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1217 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1218 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1219 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1220 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1221 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1222 __le16 req_buf_len; 1223 __le16 resp_buf_len; 1224 u8 unused_0; 1225 u8 unused_1; 1226 __le64 req_buf_page_addr0; 1227 __le64 req_buf_page_addr1; 1228 __le64 req_buf_page_addr2; 1229 __le64 req_buf_page_addr3; 1230 __le64 req_buf_page_addr4; 1231 __le64 req_buf_page_addr5; 1232 __le64 req_buf_page_addr6; 1233 __le64 req_buf_page_addr7; 1234 __le64 req_buf_page_addr8; 1235 __le64 req_buf_page_addr9; 1236 __le64 error_buf_addr; 1237 __le64 resp_buf_addr; 1238 }; 1239 1240 /* Output (16 bytes) */ 1241 struct hwrm_func_buf_rgtr_output { 1242 __le16 error_code; 1243 __le16 req_type; 1244 __le16 seq_id; 1245 __le16 resp_len; 1246 __le32 unused_0; 1247 u8 unused_1; 1248 u8 unused_2; 1249 u8 unused_3; 1250 u8 valid; 1251 }; 1252 1253 /* hwrm_func_drv_qver */ 1254 /* Input (24 bytes) */ 1255 struct hwrm_func_drv_qver_input { 1256 __le16 req_type; 1257 __le16 cmpl_ring; 1258 __le16 seq_id; 1259 __le16 target_id; 1260 __le64 resp_addr; 1261 __le32 reserved; 1262 __le16 fid; 1263 __le16 unused_0; 1264 }; 1265 1266 /* Output (16 bytes) */ 1267 struct hwrm_func_drv_qver_output { 1268 __le16 error_code; 1269 __le16 req_type; 1270 __le16 seq_id; 1271 __le16 resp_len; 1272 __le16 os_type; 1273 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1274 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1275 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1276 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1277 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1278 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1279 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1280 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1281 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1282 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1283 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1284 u8 ver_maj; 1285 u8 ver_min; 1286 u8 ver_upd; 1287 u8 unused_0; 1288 u8 unused_1; 1289 u8 valid; 1290 }; 1291 1292 /* hwrm_port_phy_cfg */ 1293 /* Input (56 bytes) */ 1294 struct hwrm_port_phy_cfg_input { 1295 __le16 req_type; 1296 __le16 cmpl_ring; 1297 __le16 seq_id; 1298 __le16 target_id; 1299 __le64 resp_addr; 1300 __le32 flags; 1301 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1302 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1303 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1304 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1305 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1306 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1307 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1308 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1309 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1310 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1311 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1312 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1313 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1314 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1315 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1316 __le32 enables; 1317 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1318 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1319 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1320 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1321 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1322 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1323 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1324 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1325 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1326 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1327 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1328 __le16 port_id; 1329 __le16 force_link_speed; 1330 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1331 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1332 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1333 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1334 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1335 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1336 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1337 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1338 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1339 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1340 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1341 u8 auto_mode; 1342 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1343 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1344 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1345 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1346 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1347 u8 auto_duplex; 1348 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1349 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1350 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1351 u8 auto_pause; 1352 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1353 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1354 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1355 u8 unused_0; 1356 __le16 auto_link_speed; 1357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1359 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1360 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1361 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1362 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1363 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1364 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1365 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1366 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1367 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1368 __le16 auto_link_speed_mask; 1369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1371 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1372 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1373 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1374 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1375 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1376 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1377 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1378 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1379 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1380 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1381 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1382 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1383 u8 wirespeed; 1384 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1385 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1386 u8 lpbk; 1387 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1388 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1389 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1390 u8 force_pause; 1391 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1392 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1393 u8 unused_1; 1394 __le32 preemphasis; 1395 __le16 eee_link_speed_mask; 1396 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1397 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1398 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1399 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1400 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1401 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1402 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1403 u8 unused_2; 1404 u8 unused_3; 1405 __le32 tx_lpi_timer; 1406 __le32 unused_4; 1407 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1408 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1409 }; 1410 1411 /* Output (16 bytes) */ 1412 struct hwrm_port_phy_cfg_output { 1413 __le16 error_code; 1414 __le16 req_type; 1415 __le16 seq_id; 1416 __le16 resp_len; 1417 __le32 unused_0; 1418 u8 unused_1; 1419 u8 unused_2; 1420 u8 unused_3; 1421 u8 valid; 1422 }; 1423 1424 /* hwrm_port_phy_qcfg */ 1425 /* Input (24 bytes) */ 1426 struct hwrm_port_phy_qcfg_input { 1427 __le16 req_type; 1428 __le16 cmpl_ring; 1429 __le16 seq_id; 1430 __le16 target_id; 1431 __le64 resp_addr; 1432 __le16 port_id; 1433 __le16 unused_0[3]; 1434 }; 1435 1436 /* Output (96 bytes) */ 1437 struct hwrm_port_phy_qcfg_output { 1438 __le16 error_code; 1439 __le16 req_type; 1440 __le16 seq_id; 1441 __le16 resp_len; 1442 u8 link; 1443 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1444 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1445 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1446 u8 unused_0; 1447 __le16 link_speed; 1448 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1449 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1450 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1451 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1452 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1453 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1454 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1455 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1456 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1457 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1458 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1459 u8 duplex; 1460 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF 0x0UL 1461 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL 0x1UL 1462 u8 pause; 1463 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1464 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1465 __le16 support_speeds; 1466 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1467 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1468 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1469 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1470 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1471 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1472 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1473 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1474 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1475 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1476 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1477 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1478 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1479 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1480 __le16 force_link_speed; 1481 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1482 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1483 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1484 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1485 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1486 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1487 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1488 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1489 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1490 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1491 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1492 u8 auto_mode; 1493 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1494 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1495 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1496 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1497 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1498 u8 auto_pause; 1499 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1500 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1501 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1502 __le16 auto_link_speed; 1503 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1504 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1505 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1506 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1507 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1508 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1509 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1510 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1511 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1512 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1513 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1514 __le16 auto_link_speed_mask; 1515 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1516 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1517 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1518 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1519 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1520 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1521 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1522 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1523 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1524 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1525 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1526 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1527 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1528 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1529 u8 wirespeed; 1530 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1531 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1532 u8 lpbk; 1533 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1534 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1535 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1536 u8 force_pause; 1537 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1538 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1539 u8 module_status; 1540 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1541 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1542 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1543 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1544 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1545 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1546 __le32 preemphasis; 1547 u8 phy_maj; 1548 u8 phy_min; 1549 u8 phy_bld; 1550 u8 phy_type; 1551 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1552 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1553 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1554 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1555 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1556 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1557 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1558 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1559 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1560 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1561 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1562 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1563 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1564 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1565 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1566 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1567 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1568 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1569 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1570 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1571 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1572 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1573 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1574 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1575 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1576 u8 media_type; 1577 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1578 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1579 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1580 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1581 u8 xcvr_pkg_type; 1582 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1583 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1584 u8 eee_config_phy_addr; 1585 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1586 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1587 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1588 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1589 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1590 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1591 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1592 u8 parallel_detect; 1593 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1594 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1595 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1596 __le16 link_partner_adv_speeds; 1597 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1598 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1599 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1600 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1601 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1602 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1603 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1604 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1605 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1606 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1607 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1608 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1609 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1610 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1611 u8 link_partner_adv_auto_mode; 1612 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1613 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1614 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1615 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1616 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1617 u8 link_partner_adv_pause; 1618 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1619 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1620 __le16 adv_eee_link_speed_mask; 1621 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1622 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1623 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1624 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1625 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1626 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1627 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1628 __le16 link_partner_adv_eee_link_speed_mask; 1629 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1630 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1631 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1632 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1633 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1634 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1635 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1636 __le32 xcvr_identifier_type_tx_lpi_timer; 1637 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1638 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1639 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1640 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1641 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1642 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1643 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1644 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1645 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1646 __le16 fec_cfg; 1647 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1648 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1649 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1650 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1651 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1652 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1653 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1654 u8 unused_1; 1655 u8 unused_2; 1656 char phy_vendor_name[16]; 1657 char phy_vendor_partnumber[16]; 1658 __le32 unused_3; 1659 u8 unused_4; 1660 u8 unused_5; 1661 u8 unused_6; 1662 u8 valid; 1663 }; 1664 1665 /* hwrm_port_mac_cfg */ 1666 /* Input (40 bytes) */ 1667 struct hwrm_port_mac_cfg_input { 1668 __le16 req_type; 1669 __le16 cmpl_ring; 1670 __le16 seq_id; 1671 __le16 target_id; 1672 __le64 resp_addr; 1673 __le32 flags; 1674 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1675 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1676 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1677 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1678 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1679 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1680 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1681 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1682 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1683 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1684 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1685 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1686 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1687 __le32 enables; 1688 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1689 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1690 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1691 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1692 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1693 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1694 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1695 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1696 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1697 __le16 port_id; 1698 u8 ipg; 1699 u8 lpbk; 1700 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1701 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1702 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1703 u8 vlan_pri2cos_map_pri; 1704 u8 reserved1; 1705 u8 tunnel_pri2cos_map_pri; 1706 u8 dscp2pri_map_pri; 1707 __le16 rx_ts_capture_ptp_msg_type; 1708 __le16 tx_ts_capture_ptp_msg_type; 1709 u8 cos_field_cfg; 1710 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1711 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1712 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1713 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1714 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1715 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1716 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1717 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1718 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1719 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1720 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1721 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1722 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1723 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1724 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1725 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1726 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1727 u8 unused_0[3]; 1728 }; 1729 1730 /* Output (16 bytes) */ 1731 struct hwrm_port_mac_cfg_output { 1732 __le16 error_code; 1733 __le16 req_type; 1734 __le16 seq_id; 1735 __le16 resp_len; 1736 __le16 mru; 1737 __le16 mtu; 1738 u8 ipg; 1739 u8 lpbk; 1740 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1741 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1742 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1743 u8 unused_0; 1744 u8 valid; 1745 }; 1746 1747 /* hwrm_port_qstats */ 1748 /* Input (40 bytes) */ 1749 struct hwrm_port_qstats_input { 1750 __le16 req_type; 1751 __le16 cmpl_ring; 1752 __le16 seq_id; 1753 __le16 target_id; 1754 __le64 resp_addr; 1755 __le16 port_id; 1756 u8 unused_0; 1757 u8 unused_1; 1758 u8 unused_2[3]; 1759 u8 unused_3; 1760 __le64 tx_stat_host_addr; 1761 __le64 rx_stat_host_addr; 1762 }; 1763 1764 /* Output (16 bytes) */ 1765 struct hwrm_port_qstats_output { 1766 __le16 error_code; 1767 __le16 req_type; 1768 __le16 seq_id; 1769 __le16 resp_len; 1770 __le16 tx_stat_size; 1771 __le16 rx_stat_size; 1772 u8 unused_0; 1773 u8 unused_1; 1774 u8 unused_2; 1775 u8 valid; 1776 }; 1777 1778 /* hwrm_port_lpbk_qstats */ 1779 /* Input (16 bytes) */ 1780 struct hwrm_port_lpbk_qstats_input { 1781 __le16 req_type; 1782 __le16 cmpl_ring; 1783 __le16 seq_id; 1784 __le16 target_id; 1785 __le64 resp_addr; 1786 }; 1787 1788 /* Output (96 bytes) */ 1789 struct hwrm_port_lpbk_qstats_output { 1790 __le16 error_code; 1791 __le16 req_type; 1792 __le16 seq_id; 1793 __le16 resp_len; 1794 __le64 lpbk_ucast_frames; 1795 __le64 lpbk_mcast_frames; 1796 __le64 lpbk_bcast_frames; 1797 __le64 lpbk_ucast_bytes; 1798 __le64 lpbk_mcast_bytes; 1799 __le64 lpbk_bcast_bytes; 1800 __le64 tx_stat_discard; 1801 __le64 tx_stat_error; 1802 __le64 rx_stat_discard; 1803 __le64 rx_stat_error; 1804 __le32 unused_0; 1805 u8 unused_1; 1806 u8 unused_2; 1807 u8 unused_3; 1808 u8 valid; 1809 }; 1810 1811 /* hwrm_port_clr_stats */ 1812 /* Input (24 bytes) */ 1813 struct hwrm_port_clr_stats_input { 1814 __le16 req_type; 1815 __le16 cmpl_ring; 1816 __le16 seq_id; 1817 __le16 target_id; 1818 __le64 resp_addr; 1819 __le16 port_id; 1820 __le16 unused_0[3]; 1821 }; 1822 1823 /* Output (16 bytes) */ 1824 struct hwrm_port_clr_stats_output { 1825 __le16 error_code; 1826 __le16 req_type; 1827 __le16 seq_id; 1828 __le16 resp_len; 1829 __le32 unused_0; 1830 u8 unused_1; 1831 u8 unused_2; 1832 u8 unused_3; 1833 u8 valid; 1834 }; 1835 1836 /* hwrm_port_lpbk_clr_stats */ 1837 /* Input (16 bytes) */ 1838 struct hwrm_port_lpbk_clr_stats_input { 1839 __le16 req_type; 1840 __le16 cmpl_ring; 1841 __le16 seq_id; 1842 __le16 target_id; 1843 __le64 resp_addr; 1844 }; 1845 1846 /* Output (16 bytes) */ 1847 struct hwrm_port_lpbk_clr_stats_output { 1848 __le16 error_code; 1849 __le16 req_type; 1850 __le16 seq_id; 1851 __le16 resp_len; 1852 __le32 unused_0; 1853 u8 unused_1; 1854 u8 unused_2; 1855 u8 unused_3; 1856 u8 valid; 1857 }; 1858 1859 /* hwrm_port_phy_qcaps */ 1860 /* Input (24 bytes) */ 1861 struct hwrm_port_phy_qcaps_input { 1862 __le16 req_type; 1863 __le16 cmpl_ring; 1864 __le16 seq_id; 1865 __le16 target_id; 1866 __le64 resp_addr; 1867 __le16 port_id; 1868 __le16 unused_0[3]; 1869 }; 1870 1871 /* Output (24 bytes) */ 1872 struct hwrm_port_phy_qcaps_output { 1873 __le16 error_code; 1874 __le16 req_type; 1875 __le16 seq_id; 1876 __le16 resp_len; 1877 u8 eee_supported; 1878 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 1879 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 1880 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 1881 u8 unused_0; 1882 __le16 supported_speeds_force_mode; 1883 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 1884 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 1885 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 1886 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 1887 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 1888 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 1889 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 1890 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 1891 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 1892 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 1893 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 1894 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 1895 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 1896 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 1897 __le16 supported_speeds_auto_mode; 1898 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 1899 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 1900 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 1901 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 1902 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 1903 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 1904 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 1905 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 1906 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 1907 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 1908 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 1909 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 1910 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 1911 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 1912 __le16 supported_speeds_eee_mode; 1913 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 1914 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 1915 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 1916 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 1917 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 1918 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 1919 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 1920 __le32 tx_lpi_timer_low; 1921 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 1922 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 1923 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 1924 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 1925 __le32 valid_tx_lpi_timer_high; 1926 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 1927 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 1928 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 1929 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 1930 }; 1931 1932 /* hwrm_port_phy_i2c_read */ 1933 /* Input (40 bytes) */ 1934 struct hwrm_port_phy_i2c_read_input { 1935 __le16 req_type; 1936 __le16 cmpl_ring; 1937 __le16 seq_id; 1938 __le16 target_id; 1939 __le64 resp_addr; 1940 __le32 flags; 1941 __le32 enables; 1942 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 1943 __le16 port_id; 1944 u8 i2c_slave_addr; 1945 u8 unused_0; 1946 __le16 page_number; 1947 __le16 page_offset; 1948 u8 data_length; 1949 u8 unused_1[7]; 1950 }; 1951 1952 /* Output (80 bytes) */ 1953 struct hwrm_port_phy_i2c_read_output { 1954 __le16 error_code; 1955 __le16 req_type; 1956 __le16 seq_id; 1957 __le16 resp_len; 1958 __le32 data[16]; 1959 __le32 unused_0; 1960 u8 unused_1; 1961 u8 unused_2; 1962 u8 unused_3; 1963 u8 valid; 1964 }; 1965 1966 /* hwrm_port_led_cfg */ 1967 /* Input (64 bytes) */ 1968 struct hwrm_port_led_cfg_input { 1969 __le16 req_type; 1970 __le16 cmpl_ring; 1971 __le16 seq_id; 1972 __le16 target_id; 1973 __le64 resp_addr; 1974 __le32 enables; 1975 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 1976 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 1977 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 1978 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 1979 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 1980 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 1981 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 1982 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 1983 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 1984 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 1985 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 1986 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 1987 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 1988 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 1989 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 1990 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 1991 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 1992 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 1993 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 1994 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 1995 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 1996 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 1997 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 1998 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 1999 __le16 port_id; 2000 u8 num_leds; 2001 u8 rsvd; 2002 u8 led0_id; 2003 u8 led0_state; 2004 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2005 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2006 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2007 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2008 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2009 u8 led0_color; 2010 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2011 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2012 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2013 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2014 u8 unused_0; 2015 __le16 led0_blink_on; 2016 __le16 led0_blink_off; 2017 u8 led0_group_id; 2018 u8 rsvd0; 2019 u8 led1_id; 2020 u8 led1_state; 2021 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2022 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2023 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2024 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2025 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2026 u8 led1_color; 2027 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2028 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2029 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2030 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2031 u8 unused_1; 2032 __le16 led1_blink_on; 2033 __le16 led1_blink_off; 2034 u8 led1_group_id; 2035 u8 rsvd1; 2036 u8 led2_id; 2037 u8 led2_state; 2038 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2039 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2040 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2041 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2042 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2043 u8 led2_color; 2044 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2045 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2046 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2047 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2048 u8 unused_2; 2049 __le16 led2_blink_on; 2050 __le16 led2_blink_off; 2051 u8 led2_group_id; 2052 u8 rsvd2; 2053 u8 led3_id; 2054 u8 led3_state; 2055 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2056 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2057 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2058 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2059 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2060 u8 led3_color; 2061 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2062 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2063 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2064 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2065 u8 unused_3; 2066 __le16 led3_blink_on; 2067 __le16 led3_blink_off; 2068 u8 led3_group_id; 2069 u8 rsvd3; 2070 }; 2071 2072 /* Output (16 bytes) */ 2073 struct hwrm_port_led_cfg_output { 2074 __le16 error_code; 2075 __le16 req_type; 2076 __le16 seq_id; 2077 __le16 resp_len; 2078 __le32 unused_0; 2079 u8 unused_1; 2080 u8 unused_2; 2081 u8 unused_3; 2082 u8 valid; 2083 }; 2084 2085 /* hwrm_port_led_qcaps */ 2086 /* Input (24 bytes) */ 2087 struct hwrm_port_led_qcaps_input { 2088 __le16 req_type; 2089 __le16 cmpl_ring; 2090 __le16 seq_id; 2091 __le16 target_id; 2092 __le64 resp_addr; 2093 __le16 port_id; 2094 __le16 unused_0[3]; 2095 }; 2096 2097 /* Output (48 bytes) */ 2098 struct hwrm_port_led_qcaps_output { 2099 __le16 error_code; 2100 __le16 req_type; 2101 __le16 seq_id; 2102 __le16 resp_len; 2103 u8 num_leds; 2104 u8 unused_0[3]; 2105 u8 led0_id; 2106 u8 led0_type; 2107 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2108 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2109 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2110 u8 led0_group_id; 2111 u8 unused_1; 2112 __le16 led0_state_caps; 2113 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2114 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2115 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2116 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2117 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2118 __le16 led0_color_caps; 2119 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2120 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2121 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2122 u8 led1_id; 2123 u8 led1_type; 2124 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2125 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2126 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2127 u8 led1_group_id; 2128 u8 unused_2; 2129 __le16 led1_state_caps; 2130 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2131 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2132 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2133 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2134 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2135 __le16 led1_color_caps; 2136 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2137 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2138 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2139 u8 led2_id; 2140 u8 led2_type; 2141 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2142 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2143 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2144 u8 led2_group_id; 2145 u8 unused_3; 2146 __le16 led2_state_caps; 2147 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2148 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2149 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2150 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2151 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2152 __le16 led2_color_caps; 2153 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2154 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2155 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2156 u8 led3_id; 2157 u8 led3_type; 2158 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2159 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2160 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2161 u8 led3_group_id; 2162 u8 unused_4; 2163 __le16 led3_state_caps; 2164 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2165 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2166 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2167 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2168 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2169 __le16 led3_color_caps; 2170 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2171 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2172 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2173 u8 unused_5; 2174 u8 unused_6; 2175 u8 unused_7; 2176 u8 valid; 2177 }; 2178 2179 /* hwrm_queue_qportcfg */ 2180 /* Input (24 bytes) */ 2181 struct hwrm_queue_qportcfg_input { 2182 __le16 req_type; 2183 __le16 cmpl_ring; 2184 __le16 seq_id; 2185 __le16 target_id; 2186 __le64 resp_addr; 2187 __le32 flags; 2188 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2189 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2190 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2191 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2192 __le16 port_id; 2193 __le16 unused_0; 2194 }; 2195 2196 /* Output (32 bytes) */ 2197 struct hwrm_queue_qportcfg_output { 2198 __le16 error_code; 2199 __le16 req_type; 2200 __le16 seq_id; 2201 __le16 resp_len; 2202 u8 max_configurable_queues; 2203 u8 max_configurable_lossless_queues; 2204 u8 queue_cfg_allowed; 2205 u8 queue_cfg_info; 2206 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2207 u8 queue_pfcenable_cfg_allowed; 2208 u8 queue_pri2cos_cfg_allowed; 2209 u8 queue_cos2bw_cfg_allowed; 2210 u8 queue_id0; 2211 u8 queue_id0_service_profile; 2212 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2213 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2214 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2215 u8 queue_id1; 2216 u8 queue_id1_service_profile; 2217 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2220 u8 queue_id2; 2221 u8 queue_id2_service_profile; 2222 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2223 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2225 u8 queue_id3; 2226 u8 queue_id3_service_profile; 2227 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2228 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2229 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2230 u8 queue_id4; 2231 u8 queue_id4_service_profile; 2232 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2235 u8 queue_id5; 2236 u8 queue_id5_service_profile; 2237 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2240 u8 queue_id6; 2241 u8 queue_id6_service_profile; 2242 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2245 u8 queue_id7; 2246 u8 queue_id7_service_profile; 2247 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2248 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2249 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2250 u8 valid; 2251 }; 2252 2253 /* hwrm_queue_cfg */ 2254 /* Input (40 bytes) */ 2255 struct hwrm_queue_cfg_input { 2256 __le16 req_type; 2257 __le16 cmpl_ring; 2258 __le16 seq_id; 2259 __le16 target_id; 2260 __le64 resp_addr; 2261 __le32 flags; 2262 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2263 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2264 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2265 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2266 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2267 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2268 __le32 enables; 2269 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2270 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2271 __le32 queue_id; 2272 __le32 dflt_len; 2273 u8 service_profile; 2274 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2275 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2276 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2277 u8 unused_0[7]; 2278 }; 2279 2280 /* Output (16 bytes) */ 2281 struct hwrm_queue_cfg_output { 2282 __le16 error_code; 2283 __le16 req_type; 2284 __le16 seq_id; 2285 __le16 resp_len; 2286 __le32 unused_0; 2287 u8 unused_1; 2288 u8 unused_2; 2289 u8 unused_3; 2290 u8 valid; 2291 }; 2292 2293 /* hwrm_queue_pfcenable_qcfg */ 2294 /* Input (24 bytes) */ 2295 struct hwrm_queue_pfcenable_qcfg_input { 2296 __le16 req_type; 2297 __le16 cmpl_ring; 2298 __le16 seq_id; 2299 __le16 target_id; 2300 __le64 resp_addr; 2301 __le16 port_id; 2302 __le16 unused_0[3]; 2303 }; 2304 2305 /* Output (16 bytes) */ 2306 struct hwrm_queue_pfcenable_qcfg_output { 2307 __le16 error_code; 2308 __le16 req_type; 2309 __le16 seq_id; 2310 __le16 resp_len; 2311 __le32 flags; 2312 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2313 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2314 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2315 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2316 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2317 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2318 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2319 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2320 u8 unused_0; 2321 u8 unused_1; 2322 u8 unused_2; 2323 u8 valid; 2324 }; 2325 2326 /* hwrm_queue_pfcenable_cfg */ 2327 /* Input (24 bytes) */ 2328 struct hwrm_queue_pfcenable_cfg_input { 2329 __le16 req_type; 2330 __le16 cmpl_ring; 2331 __le16 seq_id; 2332 __le16 target_id; 2333 __le64 resp_addr; 2334 __le32 flags; 2335 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2336 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2337 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2338 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2339 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2340 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2341 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2342 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2343 __le16 port_id; 2344 __le16 unused_0; 2345 }; 2346 2347 /* Output (16 bytes) */ 2348 struct hwrm_queue_pfcenable_cfg_output { 2349 __le16 error_code; 2350 __le16 req_type; 2351 __le16 seq_id; 2352 __le16 resp_len; 2353 __le32 unused_0; 2354 u8 unused_1; 2355 u8 unused_2; 2356 u8 unused_3; 2357 u8 valid; 2358 }; 2359 2360 /* hwrm_queue_pri2cos_qcfg */ 2361 /* Input (24 bytes) */ 2362 struct hwrm_queue_pri2cos_qcfg_input { 2363 __le16 req_type; 2364 __le16 cmpl_ring; 2365 __le16 seq_id; 2366 __le16 target_id; 2367 __le64 resp_addr; 2368 __le32 flags; 2369 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2370 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2371 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2372 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2373 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2374 u8 port_id; 2375 u8 unused_0[3]; 2376 }; 2377 2378 /* Output (24 bytes) */ 2379 struct hwrm_queue_pri2cos_qcfg_output { 2380 __le16 error_code; 2381 __le16 req_type; 2382 __le16 seq_id; 2383 __le16 resp_len; 2384 u8 pri0_cos_queue_id; 2385 u8 pri1_cos_queue_id; 2386 u8 pri2_cos_queue_id; 2387 u8 pri3_cos_queue_id; 2388 u8 pri4_cos_queue_id; 2389 u8 pri5_cos_queue_id; 2390 u8 pri6_cos_queue_id; 2391 u8 pri7_cos_queue_id; 2392 u8 queue_cfg_info; 2393 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2394 u8 unused_0; 2395 __le16 unused_1; 2396 u8 unused_2; 2397 u8 unused_3; 2398 u8 unused_4; 2399 u8 valid; 2400 }; 2401 2402 /* hwrm_queue_pri2cos_cfg */ 2403 /* Input (40 bytes) */ 2404 struct hwrm_queue_pri2cos_cfg_input { 2405 __le16 req_type; 2406 __le16 cmpl_ring; 2407 __le16 seq_id; 2408 __le16 target_id; 2409 __le64 resp_addr; 2410 __le32 flags; 2411 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2412 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2413 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2414 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2415 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2416 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2417 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2418 __le32 enables; 2419 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2420 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2421 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2422 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2423 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2424 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2425 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2426 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2427 u8 port_id; 2428 u8 pri0_cos_queue_id; 2429 u8 pri1_cos_queue_id; 2430 u8 pri2_cos_queue_id; 2431 u8 pri3_cos_queue_id; 2432 u8 pri4_cos_queue_id; 2433 u8 pri5_cos_queue_id; 2434 u8 pri6_cos_queue_id; 2435 u8 pri7_cos_queue_id; 2436 u8 unused_0[7]; 2437 }; 2438 2439 /* Output (16 bytes) */ 2440 struct hwrm_queue_pri2cos_cfg_output { 2441 __le16 error_code; 2442 __le16 req_type; 2443 __le16 seq_id; 2444 __le16 resp_len; 2445 __le32 unused_0; 2446 u8 unused_1; 2447 u8 unused_2; 2448 u8 unused_3; 2449 u8 valid; 2450 }; 2451 2452 /* hwrm_queue_cos2bw_qcfg */ 2453 /* Input (24 bytes) */ 2454 struct hwrm_queue_cos2bw_qcfg_input { 2455 __le16 req_type; 2456 __le16 cmpl_ring; 2457 __le16 seq_id; 2458 __le16 target_id; 2459 __le64 resp_addr; 2460 __le16 port_id; 2461 __le16 unused_0[3]; 2462 }; 2463 2464 /* Output (112 bytes) */ 2465 struct hwrm_queue_cos2bw_qcfg_output { 2466 __le16 error_code; 2467 __le16 req_type; 2468 __le16 seq_id; 2469 __le16 resp_len; 2470 u8 queue_id0; 2471 u8 unused_0; 2472 __le16 unused_1; 2473 __le32 queue_id0_min_bw; 2474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2489 __le32 queue_id0_max_bw; 2490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2501 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2502 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2505 u8 queue_id0_tsa_assign; 2506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2509 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2510 u8 queue_id0_pri_lvl; 2511 u8 queue_id0_bw_weight; 2512 u8 queue_id1; 2513 __le32 queue_id1_min_bw; 2514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2529 __le32 queue_id1_max_bw; 2530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2541 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2542 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2545 u8 queue_id1_tsa_assign; 2546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2547 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2548 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2549 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2550 u8 queue_id1_pri_lvl; 2551 u8 queue_id1_bw_weight; 2552 u8 queue_id2; 2553 __le32 queue_id2_min_bw; 2554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2560 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2564 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2565 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2566 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2568 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2569 __le32 queue_id2_max_bw; 2570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2581 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2585 u8 queue_id2_tsa_assign; 2586 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2587 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2588 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2589 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2590 u8 queue_id2_pri_lvl; 2591 u8 queue_id2_bw_weight; 2592 u8 queue_id3; 2593 __le32 queue_id3_min_bw; 2594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 2600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2605 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2609 __le32 queue_id3_max_bw; 2610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 2616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2621 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2625 u8 queue_id3_tsa_assign; 2626 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2627 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2628 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2629 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2630 u8 queue_id3_pri_lvl; 2631 u8 queue_id3_bw_weight; 2632 u8 queue_id4; 2633 __le32 queue_id4_min_bw; 2634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 2640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2645 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2649 __le32 queue_id4_max_bw; 2650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 2653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 2654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 2655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 2656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2661 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2665 u8 queue_id4_tsa_assign; 2666 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2667 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2668 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2669 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2670 u8 queue_id4_pri_lvl; 2671 u8 queue_id4_bw_weight; 2672 u8 queue_id5; 2673 __le32 queue_id5_min_bw; 2674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 2677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 2678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 2679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 2680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2685 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2689 __le32 queue_id5_max_bw; 2690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 2693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 2694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 2695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 2696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2701 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2705 u8 queue_id5_tsa_assign; 2706 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2707 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2708 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2709 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2710 u8 queue_id5_pri_lvl; 2711 u8 queue_id5_bw_weight; 2712 u8 queue_id6; 2713 __le32 queue_id6_min_bw; 2714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 2717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 2718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 2719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 2720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2725 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2729 __le32 queue_id6_max_bw; 2730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 2733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 2734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 2735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 2736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2741 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2745 u8 queue_id6_tsa_assign; 2746 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2747 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2748 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2749 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2750 u8 queue_id6_pri_lvl; 2751 u8 queue_id6_bw_weight; 2752 u8 queue_id7; 2753 __le32 queue_id7_min_bw; 2754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 2757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 2758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 2759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 2760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2765 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2769 __le32 queue_id7_max_bw; 2770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 2773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 2774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 2775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 2776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2781 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2785 u8 queue_id7_tsa_assign; 2786 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2787 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2788 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2789 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2790 u8 queue_id7_pri_lvl; 2791 u8 queue_id7_bw_weight; 2792 u8 unused_2; 2793 u8 unused_3; 2794 u8 unused_4; 2795 u8 unused_5; 2796 u8 valid; 2797 }; 2798 2799 /* hwrm_queue_cos2bw_cfg */ 2800 /* Input (128 bytes) */ 2801 struct hwrm_queue_cos2bw_cfg_input { 2802 __le16 req_type; 2803 __le16 cmpl_ring; 2804 __le16 seq_id; 2805 __le16 target_id; 2806 __le64 resp_addr; 2807 __le32 flags; 2808 __le32 enables; 2809 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2810 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2811 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2812 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2813 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2814 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2815 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2816 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2817 __le16 port_id; 2818 u8 queue_id0; 2819 u8 unused_0; 2820 __le32 queue_id0_min_bw; 2821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 2827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2832 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2836 __le32 queue_id0_max_bw; 2837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2842 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 2843 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2844 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2845 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2846 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2848 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2852 u8 queue_id0_tsa_assign; 2853 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2854 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2855 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2856 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2857 u8 queue_id0_pri_lvl; 2858 u8 queue_id0_bw_weight; 2859 u8 queue_id1; 2860 __le32 queue_id1_min_bw; 2861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 2867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2872 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2876 __le32 queue_id1_max_bw; 2877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 2883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2885 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2888 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2892 u8 queue_id1_tsa_assign; 2893 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2894 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2895 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2896 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2897 u8 queue_id1_pri_lvl; 2898 u8 queue_id1_bw_weight; 2899 u8 queue_id2; 2900 __le32 queue_id2_min_bw; 2901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2903 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 2907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2912 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2916 __le32 queue_id2_max_bw; 2917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 2923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2928 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2932 u8 queue_id2_tsa_assign; 2933 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2934 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2935 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2936 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2937 u8 queue_id2_pri_lvl; 2938 u8 queue_id2_bw_weight; 2939 u8 queue_id3; 2940 __le32 queue_id3_min_bw; 2941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 2947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2952 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2956 __le32 queue_id3_max_bw; 2957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 2963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2968 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2972 u8 queue_id3_tsa_assign; 2973 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2974 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2975 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2976 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2977 u8 queue_id3_pri_lvl; 2978 u8 queue_id3_bw_weight; 2979 u8 queue_id4; 2980 __le32 queue_id4_min_bw; 2981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 2987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2992 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2996 __le32 queue_id4_max_bw; 2997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3008 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3012 u8 queue_id4_tsa_assign; 3013 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3014 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3015 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3016 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3017 u8 queue_id4_pri_lvl; 3018 u8 queue_id4_bw_weight; 3019 u8 queue_id5; 3020 __le32 queue_id5_min_bw; 3021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3032 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3036 __le32 queue_id5_max_bw; 3037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3048 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3052 u8 queue_id5_tsa_assign; 3053 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3054 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3055 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3056 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3057 u8 queue_id5_pri_lvl; 3058 u8 queue_id5_bw_weight; 3059 u8 queue_id6; 3060 __le32 queue_id6_min_bw; 3061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3072 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3076 __le32 queue_id6_max_bw; 3077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3088 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3092 u8 queue_id6_tsa_assign; 3093 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3094 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3095 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3096 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3097 u8 queue_id6_pri_lvl; 3098 u8 queue_id6_bw_weight; 3099 u8 queue_id7; 3100 __le32 queue_id7_min_bw; 3101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3112 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3116 __le32 queue_id7_max_bw; 3117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3128 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3132 u8 queue_id7_tsa_assign; 3133 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3134 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3135 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3136 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3137 u8 queue_id7_pri_lvl; 3138 u8 queue_id7_bw_weight; 3139 u8 unused_1[5]; 3140 }; 3141 3142 /* Output (16 bytes) */ 3143 struct hwrm_queue_cos2bw_cfg_output { 3144 __le16 error_code; 3145 __le16 req_type; 3146 __le16 seq_id; 3147 __le16 resp_len; 3148 __le32 unused_0; 3149 u8 unused_1; 3150 u8 unused_2; 3151 u8 unused_3; 3152 u8 valid; 3153 }; 3154 3155 /* hwrm_vnic_alloc */ 3156 /* Input (24 bytes) */ 3157 struct hwrm_vnic_alloc_input { 3158 __le16 req_type; 3159 __le16 cmpl_ring; 3160 __le16 seq_id; 3161 __le16 target_id; 3162 __le64 resp_addr; 3163 __le32 flags; 3164 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3165 __le32 unused_0; 3166 }; 3167 3168 /* Output (16 bytes) */ 3169 struct hwrm_vnic_alloc_output { 3170 __le16 error_code; 3171 __le16 req_type; 3172 __le16 seq_id; 3173 __le16 resp_len; 3174 __le32 vnic_id; 3175 u8 unused_0; 3176 u8 unused_1; 3177 u8 unused_2; 3178 u8 valid; 3179 }; 3180 3181 /* hwrm_vnic_free */ 3182 /* Input (24 bytes) */ 3183 struct hwrm_vnic_free_input { 3184 __le16 req_type; 3185 __le16 cmpl_ring; 3186 __le16 seq_id; 3187 __le16 target_id; 3188 __le64 resp_addr; 3189 __le32 vnic_id; 3190 __le32 unused_0; 3191 }; 3192 3193 /* Output (16 bytes) */ 3194 struct hwrm_vnic_free_output { 3195 __le16 error_code; 3196 __le16 req_type; 3197 __le16 seq_id; 3198 __le16 resp_len; 3199 __le32 unused_0; 3200 u8 unused_1; 3201 u8 unused_2; 3202 u8 unused_3; 3203 u8 valid; 3204 }; 3205 3206 /* hwrm_vnic_cfg */ 3207 /* Input (40 bytes) */ 3208 struct hwrm_vnic_cfg_input { 3209 __le16 req_type; 3210 __le16 cmpl_ring; 3211 __le16 seq_id; 3212 __le16 target_id; 3213 __le64 resp_addr; 3214 __le32 flags; 3215 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3216 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3217 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3218 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3219 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3220 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3221 __le32 enables; 3222 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3223 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3224 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3225 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3226 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3227 __le16 vnic_id; 3228 __le16 dflt_ring_grp; 3229 __le16 rss_rule; 3230 __le16 cos_rule; 3231 __le16 lb_rule; 3232 __le16 mru; 3233 __le32 unused_0; 3234 }; 3235 3236 /* Output (16 bytes) */ 3237 struct hwrm_vnic_cfg_output { 3238 __le16 error_code; 3239 __le16 req_type; 3240 __le16 seq_id; 3241 __le16 resp_len; 3242 __le32 unused_0; 3243 u8 unused_1; 3244 u8 unused_2; 3245 u8 unused_3; 3246 u8 valid; 3247 }; 3248 3249 /* hwrm_vnic_qcaps */ 3250 /* Input (24 bytes) */ 3251 struct hwrm_vnic_qcaps_input { 3252 __le16 req_type; 3253 __le16 cmpl_ring; 3254 __le16 seq_id; 3255 __le16 target_id; 3256 __le64 resp_addr; 3257 __le32 enables; 3258 __le32 unused_0; 3259 }; 3260 3261 /* Output (24 bytes) */ 3262 struct hwrm_vnic_qcaps_output { 3263 __le16 error_code; 3264 __le16 req_type; 3265 __le16 seq_id; 3266 __le16 resp_len; 3267 __le16 mru; 3268 u8 unused_0; 3269 u8 unused_1; 3270 __le32 flags; 3271 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3272 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3273 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3274 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3275 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3276 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3277 __le32 unused_2; 3278 u8 unused_3; 3279 u8 unused_4; 3280 u8 unused_5; 3281 u8 valid; 3282 }; 3283 3284 /* hwrm_vnic_tpa_cfg */ 3285 /* Input (40 bytes) */ 3286 struct hwrm_vnic_tpa_cfg_input { 3287 __le16 req_type; 3288 __le16 cmpl_ring; 3289 __le16 seq_id; 3290 __le16 target_id; 3291 __le64 resp_addr; 3292 __le32 flags; 3293 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3294 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3295 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3296 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3297 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3298 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3299 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3300 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3301 __le32 enables; 3302 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3303 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3304 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3305 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3306 __le16 vnic_id; 3307 __le16 max_agg_segs; 3308 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3309 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3310 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3311 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3312 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3313 __le16 max_aggs; 3314 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3315 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3316 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3317 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3318 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3319 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3320 u8 unused_0; 3321 u8 unused_1; 3322 __le32 max_agg_timer; 3323 __le32 min_agg_len; 3324 }; 3325 3326 /* Output (16 bytes) */ 3327 struct hwrm_vnic_tpa_cfg_output { 3328 __le16 error_code; 3329 __le16 req_type; 3330 __le16 seq_id; 3331 __le16 resp_len; 3332 __le32 unused_0; 3333 u8 unused_1; 3334 u8 unused_2; 3335 u8 unused_3; 3336 u8 valid; 3337 }; 3338 3339 /* hwrm_vnic_rss_cfg */ 3340 /* Input (48 bytes) */ 3341 struct hwrm_vnic_rss_cfg_input { 3342 __le16 req_type; 3343 __le16 cmpl_ring; 3344 __le16 seq_id; 3345 __le16 target_id; 3346 __le64 resp_addr; 3347 __le32 hash_type; 3348 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3349 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3350 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3351 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3352 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3353 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3354 __le32 unused_0; 3355 __le64 ring_grp_tbl_addr; 3356 __le64 hash_key_tbl_addr; 3357 __le16 rss_ctx_idx; 3358 __le16 unused_1[3]; 3359 }; 3360 3361 /* Output (16 bytes) */ 3362 struct hwrm_vnic_rss_cfg_output { 3363 __le16 error_code; 3364 __le16 req_type; 3365 __le16 seq_id; 3366 __le16 resp_len; 3367 __le32 unused_0; 3368 u8 unused_1; 3369 u8 unused_2; 3370 u8 unused_3; 3371 u8 valid; 3372 }; 3373 3374 /* hwrm_vnic_plcmodes_cfg */ 3375 /* Input (40 bytes) */ 3376 struct hwrm_vnic_plcmodes_cfg_input { 3377 __le16 req_type; 3378 __le16 cmpl_ring; 3379 __le16 seq_id; 3380 __le16 target_id; 3381 __le64 resp_addr; 3382 __le32 flags; 3383 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3384 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3385 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3386 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3387 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3388 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3389 __le32 enables; 3390 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3391 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3392 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3393 __le32 vnic_id; 3394 __le16 jumbo_thresh; 3395 __le16 hds_offset; 3396 __le16 hds_threshold; 3397 __le16 unused_0[3]; 3398 }; 3399 3400 /* Output (16 bytes) */ 3401 struct hwrm_vnic_plcmodes_cfg_output { 3402 __le16 error_code; 3403 __le16 req_type; 3404 __le16 seq_id; 3405 __le16 resp_len; 3406 __le32 unused_0; 3407 u8 unused_1; 3408 u8 unused_2; 3409 u8 unused_3; 3410 u8 valid; 3411 }; 3412 3413 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 3414 /* Input (16 bytes) */ 3415 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3416 __le16 req_type; 3417 __le16 cmpl_ring; 3418 __le16 seq_id; 3419 __le16 target_id; 3420 __le64 resp_addr; 3421 }; 3422 3423 /* Output (16 bytes) */ 3424 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3425 __le16 error_code; 3426 __le16 req_type; 3427 __le16 seq_id; 3428 __le16 resp_len; 3429 __le16 rss_cos_lb_ctx_id; 3430 u8 unused_0; 3431 u8 unused_1; 3432 u8 unused_2; 3433 u8 unused_3; 3434 u8 unused_4; 3435 u8 valid; 3436 }; 3437 3438 /* hwrm_vnic_rss_cos_lb_ctx_free */ 3439 /* Input (24 bytes) */ 3440 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3441 __le16 req_type; 3442 __le16 cmpl_ring; 3443 __le16 seq_id; 3444 __le16 target_id; 3445 __le64 resp_addr; 3446 __le16 rss_cos_lb_ctx_id; 3447 __le16 unused_0[3]; 3448 }; 3449 3450 /* Output (16 bytes) */ 3451 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3452 __le16 error_code; 3453 __le16 req_type; 3454 __le16 seq_id; 3455 __le16 resp_len; 3456 __le32 unused_0; 3457 u8 unused_1; 3458 u8 unused_2; 3459 u8 unused_3; 3460 u8 valid; 3461 }; 3462 3463 /* hwrm_ring_alloc */ 3464 /* Input (80 bytes) */ 3465 struct hwrm_ring_alloc_input { 3466 __le16 req_type; 3467 __le16 cmpl_ring; 3468 __le16 seq_id; 3469 __le16 target_id; 3470 __le64 resp_addr; 3471 __le32 enables; 3472 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 3473 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3474 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 3475 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3476 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 3477 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3478 u8 ring_type; 3479 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3480 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3481 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3482 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3483 u8 unused_0; 3484 __le16 unused_1; 3485 __le64 page_tbl_addr; 3486 __le32 fbo; 3487 u8 page_size; 3488 u8 page_tbl_depth; 3489 u8 unused_2; 3490 u8 unused_3; 3491 __le32 length; 3492 __le16 logical_id; 3493 __le16 cmpl_ring_id; 3494 __le16 queue_id; 3495 u8 unused_4; 3496 u8 unused_5; 3497 __le32 reserved1; 3498 __le16 ring_arb_cfg; 3499 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3500 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3501 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3502 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3503 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3504 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3505 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3506 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3507 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3508 u8 unused_6; 3509 u8 unused_7; 3510 __le32 reserved3; 3511 __le32 stat_ctx_id; 3512 __le32 reserved4; 3513 __le32 max_bw; 3514 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3515 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3516 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3517 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3518 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3519 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3520 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3521 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3522 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3523 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3524 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3525 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3526 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3527 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3528 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3529 u8 int_mode; 3530 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3531 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3532 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3533 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3534 u8 unused_8[3]; 3535 }; 3536 3537 /* Output (16 bytes) */ 3538 struct hwrm_ring_alloc_output { 3539 __le16 error_code; 3540 __le16 req_type; 3541 __le16 seq_id; 3542 __le16 resp_len; 3543 __le16 ring_id; 3544 __le16 logical_ring_id; 3545 u8 unused_0; 3546 u8 unused_1; 3547 u8 unused_2; 3548 u8 valid; 3549 }; 3550 3551 /* hwrm_ring_free */ 3552 /* Input (24 bytes) */ 3553 struct hwrm_ring_free_input { 3554 __le16 req_type; 3555 __le16 cmpl_ring; 3556 __le16 seq_id; 3557 __le16 target_id; 3558 __le64 resp_addr; 3559 u8 ring_type; 3560 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3561 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3562 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3563 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3564 u8 unused_0; 3565 __le16 ring_id; 3566 __le32 unused_1; 3567 }; 3568 3569 /* Output (16 bytes) */ 3570 struct hwrm_ring_free_output { 3571 __le16 error_code; 3572 __le16 req_type; 3573 __le16 seq_id; 3574 __le16 resp_len; 3575 __le32 unused_0; 3576 u8 unused_1; 3577 u8 unused_2; 3578 u8 unused_3; 3579 u8 valid; 3580 }; 3581 3582 /* hwrm_ring_cmpl_ring_qaggint_params */ 3583 /* Input (24 bytes) */ 3584 struct hwrm_ring_cmpl_ring_qaggint_params_input { 3585 __le16 req_type; 3586 __le16 cmpl_ring; 3587 __le16 seq_id; 3588 __le16 target_id; 3589 __le64 resp_addr; 3590 __le16 ring_id; 3591 __le16 unused_0[3]; 3592 }; 3593 3594 /* Output (32 bytes) */ 3595 struct hwrm_ring_cmpl_ring_qaggint_params_output { 3596 __le16 error_code; 3597 __le16 req_type; 3598 __le16 seq_id; 3599 __le16 resp_len; 3600 __le16 flags; 3601 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3602 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3603 __le16 num_cmpl_dma_aggr; 3604 __le16 num_cmpl_dma_aggr_during_int; 3605 __le16 cmpl_aggr_dma_tmr; 3606 __le16 cmpl_aggr_dma_tmr_during_int; 3607 __le16 int_lat_tmr_min; 3608 __le16 int_lat_tmr_max; 3609 __le16 num_cmpl_aggr_int; 3610 __le32 unused_0; 3611 u8 unused_1; 3612 u8 unused_2; 3613 u8 unused_3; 3614 u8 valid; 3615 }; 3616 3617 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3618 /* Input (40 bytes) */ 3619 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3620 __le16 req_type; 3621 __le16 cmpl_ring; 3622 __le16 seq_id; 3623 __le16 target_id; 3624 __le64 resp_addr; 3625 __le16 ring_id; 3626 __le16 flags; 3627 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3628 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3629 __le16 num_cmpl_dma_aggr; 3630 __le16 num_cmpl_dma_aggr_during_int; 3631 __le16 cmpl_aggr_dma_tmr; 3632 __le16 cmpl_aggr_dma_tmr_during_int; 3633 __le16 int_lat_tmr_min; 3634 __le16 int_lat_tmr_max; 3635 __le16 num_cmpl_aggr_int; 3636 __le16 unused_0[3]; 3637 }; 3638 3639 /* Output (16 bytes) */ 3640 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3641 __le16 error_code; 3642 __le16 req_type; 3643 __le16 seq_id; 3644 __le16 resp_len; 3645 __le32 unused_0; 3646 u8 unused_1; 3647 u8 unused_2; 3648 u8 unused_3; 3649 u8 valid; 3650 }; 3651 3652 /* hwrm_ring_reset */ 3653 /* Input (24 bytes) */ 3654 struct hwrm_ring_reset_input { 3655 __le16 req_type; 3656 __le16 cmpl_ring; 3657 __le16 seq_id; 3658 __le16 target_id; 3659 __le64 resp_addr; 3660 u8 ring_type; 3661 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 3662 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3663 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3664 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3665 u8 unused_0; 3666 __le16 ring_id; 3667 __le32 unused_1; 3668 }; 3669 3670 /* Output (16 bytes) */ 3671 struct hwrm_ring_reset_output { 3672 __le16 error_code; 3673 __le16 req_type; 3674 __le16 seq_id; 3675 __le16 resp_len; 3676 __le32 unused_0; 3677 u8 unused_1; 3678 u8 unused_2; 3679 u8 unused_3; 3680 u8 valid; 3681 }; 3682 3683 /* hwrm_ring_grp_alloc */ 3684 /* Input (24 bytes) */ 3685 struct hwrm_ring_grp_alloc_input { 3686 __le16 req_type; 3687 __le16 cmpl_ring; 3688 __le16 seq_id; 3689 __le16 target_id; 3690 __le64 resp_addr; 3691 __le16 cr; 3692 __le16 rr; 3693 __le16 ar; 3694 __le16 sc; 3695 }; 3696 3697 /* Output (16 bytes) */ 3698 struct hwrm_ring_grp_alloc_output { 3699 __le16 error_code; 3700 __le16 req_type; 3701 __le16 seq_id; 3702 __le16 resp_len; 3703 __le32 ring_group_id; 3704 u8 unused_0; 3705 u8 unused_1; 3706 u8 unused_2; 3707 u8 valid; 3708 }; 3709 3710 /* hwrm_ring_grp_free */ 3711 /* Input (24 bytes) */ 3712 struct hwrm_ring_grp_free_input { 3713 __le16 req_type; 3714 __le16 cmpl_ring; 3715 __le16 seq_id; 3716 __le16 target_id; 3717 __le64 resp_addr; 3718 __le32 ring_group_id; 3719 __le32 unused_0; 3720 }; 3721 3722 /* Output (16 bytes) */ 3723 struct hwrm_ring_grp_free_output { 3724 __le16 error_code; 3725 __le16 req_type; 3726 __le16 seq_id; 3727 __le16 resp_len; 3728 __le32 unused_0; 3729 u8 unused_1; 3730 u8 unused_2; 3731 u8 unused_3; 3732 u8 valid; 3733 }; 3734 3735 /* hwrm_cfa_l2_filter_alloc */ 3736 /* Input (96 bytes) */ 3737 struct hwrm_cfa_l2_filter_alloc_input { 3738 __le16 req_type; 3739 __le16 cmpl_ring; 3740 __le16 seq_id; 3741 __le16 target_id; 3742 __le64 resp_addr; 3743 __le32 flags; 3744 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3745 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3746 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3747 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3748 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3749 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3750 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3751 __le32 enables; 3752 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3753 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3754 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3755 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3756 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3757 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3758 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3759 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3760 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3761 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3762 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3763 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3764 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3765 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3766 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3767 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3768 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3769 u8 l2_addr[6]; 3770 u8 unused_0; 3771 u8 unused_1; 3772 u8 l2_addr_mask[6]; 3773 __le16 l2_ovlan; 3774 __le16 l2_ovlan_mask; 3775 __le16 l2_ivlan; 3776 __le16 l2_ivlan_mask; 3777 u8 unused_2; 3778 u8 unused_3; 3779 u8 t_l2_addr[6]; 3780 u8 unused_4; 3781 u8 unused_5; 3782 u8 t_l2_addr_mask[6]; 3783 __le16 t_l2_ovlan; 3784 __le16 t_l2_ovlan_mask; 3785 __le16 t_l2_ivlan; 3786 __le16 t_l2_ivlan_mask; 3787 u8 src_type; 3788 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3789 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3790 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3791 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3792 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3793 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3794 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3795 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3796 u8 unused_6; 3797 __le32 src_id; 3798 u8 tunnel_type; 3799 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3800 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3801 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3802 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3803 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3804 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3805 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3806 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3807 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3808 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3809 u8 unused_7; 3810 __le16 dst_id; 3811 __le16 mirror_vnic_id; 3812 u8 pri_hint; 3813 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3814 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 3815 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 3816 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 3817 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 3818 u8 unused_8; 3819 __le32 unused_9; 3820 __le64 l2_filter_id_hint; 3821 }; 3822 3823 /* Output (24 bytes) */ 3824 struct hwrm_cfa_l2_filter_alloc_output { 3825 __le16 error_code; 3826 __le16 req_type; 3827 __le16 seq_id; 3828 __le16 resp_len; 3829 __le64 l2_filter_id; 3830 __le32 flow_id; 3831 u8 unused_0; 3832 u8 unused_1; 3833 u8 unused_2; 3834 u8 valid; 3835 }; 3836 3837 /* hwrm_cfa_l2_filter_free */ 3838 /* Input (24 bytes) */ 3839 struct hwrm_cfa_l2_filter_free_input { 3840 __le16 req_type; 3841 __le16 cmpl_ring; 3842 __le16 seq_id; 3843 __le16 target_id; 3844 __le64 resp_addr; 3845 __le64 l2_filter_id; 3846 }; 3847 3848 /* Output (16 bytes) */ 3849 struct hwrm_cfa_l2_filter_free_output { 3850 __le16 error_code; 3851 __le16 req_type; 3852 __le16 seq_id; 3853 __le16 resp_len; 3854 __le32 unused_0; 3855 u8 unused_1; 3856 u8 unused_2; 3857 u8 unused_3; 3858 u8 valid; 3859 }; 3860 3861 /* hwrm_cfa_l2_filter_cfg */ 3862 /* Input (40 bytes) */ 3863 struct hwrm_cfa_l2_filter_cfg_input { 3864 __le16 req_type; 3865 __le16 cmpl_ring; 3866 __le16 seq_id; 3867 __le16 target_id; 3868 __le64 resp_addr; 3869 __le32 flags; 3870 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3871 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3872 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 3873 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3874 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3875 __le32 enables; 3876 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3877 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3878 __le64 l2_filter_id; 3879 __le32 dst_id; 3880 __le32 new_mirror_vnic_id; 3881 }; 3882 3883 /* Output (16 bytes) */ 3884 struct hwrm_cfa_l2_filter_cfg_output { 3885 __le16 error_code; 3886 __le16 req_type; 3887 __le16 seq_id; 3888 __le16 resp_len; 3889 __le32 unused_0; 3890 u8 unused_1; 3891 u8 unused_2; 3892 u8 unused_3; 3893 u8 valid; 3894 }; 3895 3896 /* hwrm_cfa_l2_set_rx_mask */ 3897 /* Input (56 bytes) */ 3898 struct hwrm_cfa_l2_set_rx_mask_input { 3899 __le16 req_type; 3900 __le16 cmpl_ring; 3901 __le16 seq_id; 3902 __le16 target_id; 3903 __le64 resp_addr; 3904 __le32 vnic_id; 3905 __le32 mask; 3906 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3907 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3908 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3909 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3910 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3911 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3912 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 3913 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 3914 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 3915 __le64 mc_tbl_addr; 3916 __le32 num_mc_entries; 3917 __le32 unused_0; 3918 __le64 vlan_tag_tbl_addr; 3919 __le32 num_vlan_tags; 3920 __le32 unused_1; 3921 }; 3922 3923 /* Output (16 bytes) */ 3924 struct hwrm_cfa_l2_set_rx_mask_output { 3925 __le16 error_code; 3926 __le16 req_type; 3927 __le16 seq_id; 3928 __le16 resp_len; 3929 __le32 unused_0; 3930 u8 unused_1; 3931 u8 unused_2; 3932 u8 unused_3; 3933 u8 valid; 3934 }; 3935 3936 /* hwrm_cfa_tunnel_filter_alloc */ 3937 /* Input (88 bytes) */ 3938 struct hwrm_cfa_tunnel_filter_alloc_input { 3939 __le16 req_type; 3940 __le16 cmpl_ring; 3941 __le16 seq_id; 3942 __le16 target_id; 3943 __le64 resp_addr; 3944 __le32 flags; 3945 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3946 __le32 enables; 3947 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3948 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3949 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3950 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3951 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3952 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3953 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3954 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3955 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3956 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3957 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3958 __le64 l2_filter_id; 3959 u8 l2_addr[6]; 3960 __le16 l2_ivlan; 3961 __le32 l3_addr[4]; 3962 __le32 t_l3_addr[4]; 3963 u8 l3_addr_type; 3964 u8 t_l3_addr_type; 3965 u8 tunnel_type; 3966 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3967 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3968 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3969 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3970 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3971 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3972 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3973 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3974 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3975 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3976 u8 unused_0; 3977 __le32 vni; 3978 __le32 dst_vnic_id; 3979 __le32 mirror_vnic_id; 3980 }; 3981 3982 /* Output (24 bytes) */ 3983 struct hwrm_cfa_tunnel_filter_alloc_output { 3984 __le16 error_code; 3985 __le16 req_type; 3986 __le16 seq_id; 3987 __le16 resp_len; 3988 __le64 tunnel_filter_id; 3989 __le32 flow_id; 3990 u8 unused_0; 3991 u8 unused_1; 3992 u8 unused_2; 3993 u8 valid; 3994 }; 3995 3996 /* hwrm_cfa_tunnel_filter_free */ 3997 /* Input (24 bytes) */ 3998 struct hwrm_cfa_tunnel_filter_free_input { 3999 __le16 req_type; 4000 __le16 cmpl_ring; 4001 __le16 seq_id; 4002 __le16 target_id; 4003 __le64 resp_addr; 4004 __le64 tunnel_filter_id; 4005 }; 4006 4007 /* Output (16 bytes) */ 4008 struct hwrm_cfa_tunnel_filter_free_output { 4009 __le16 error_code; 4010 __le16 req_type; 4011 __le16 seq_id; 4012 __le16 resp_len; 4013 __le32 unused_0; 4014 u8 unused_1; 4015 u8 unused_2; 4016 u8 unused_3; 4017 u8 valid; 4018 }; 4019 4020 /* hwrm_cfa_encap_record_alloc */ 4021 /* Input (32 bytes) */ 4022 struct hwrm_cfa_encap_record_alloc_input { 4023 __le16 req_type; 4024 __le16 cmpl_ring; 4025 __le16 seq_id; 4026 __le16 target_id; 4027 __le64 resp_addr; 4028 __le32 flags; 4029 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4030 u8 encap_type; 4031 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4032 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4033 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4034 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4035 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4036 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4037 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4038 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4039 u8 unused_0; 4040 __le16 unused_1; 4041 __le32 encap_data[16]; 4042 }; 4043 4044 /* Output (16 bytes) */ 4045 struct hwrm_cfa_encap_record_alloc_output { 4046 __le16 error_code; 4047 __le16 req_type; 4048 __le16 seq_id; 4049 __le16 resp_len; 4050 __le32 encap_record_id; 4051 u8 unused_0; 4052 u8 unused_1; 4053 u8 unused_2; 4054 u8 valid; 4055 }; 4056 4057 /* hwrm_cfa_encap_record_free */ 4058 /* Input (24 bytes) */ 4059 struct hwrm_cfa_encap_record_free_input { 4060 __le16 req_type; 4061 __le16 cmpl_ring; 4062 __le16 seq_id; 4063 __le16 target_id; 4064 __le64 resp_addr; 4065 __le32 encap_record_id; 4066 __le32 unused_0; 4067 }; 4068 4069 /* Output (16 bytes) */ 4070 struct hwrm_cfa_encap_record_free_output { 4071 __le16 error_code; 4072 __le16 req_type; 4073 __le16 seq_id; 4074 __le16 resp_len; 4075 __le32 unused_0; 4076 u8 unused_1; 4077 u8 unused_2; 4078 u8 unused_3; 4079 u8 valid; 4080 }; 4081 4082 /* hwrm_cfa_ntuple_filter_alloc */ 4083 /* Input (128 bytes) */ 4084 struct hwrm_cfa_ntuple_filter_alloc_input { 4085 __le16 req_type; 4086 __le16 cmpl_ring; 4087 __le16 seq_id; 4088 __le16 target_id; 4089 __le64 resp_addr; 4090 __le32 flags; 4091 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4092 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4093 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4094 __le32 enables; 4095 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4096 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4097 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4098 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4099 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4100 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4101 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4102 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4103 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4104 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4105 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4106 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4107 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4108 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4109 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4110 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4111 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4112 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4113 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4114 __le64 l2_filter_id; 4115 u8 src_macaddr[6]; 4116 __be16 ethertype; 4117 u8 ip_addr_type; 4118 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4119 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4120 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4121 u8 ip_protocol; 4122 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4123 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x6UL 4124 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x11UL 4125 __le16 dst_id; 4126 __le16 mirror_vnic_id; 4127 u8 tunnel_type; 4128 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4129 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4130 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4131 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4132 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4133 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4134 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4135 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4136 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4137 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4138 u8 pri_hint; 4139 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4140 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4141 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4142 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4143 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4144 __be32 src_ipaddr[4]; 4145 __be32 src_ipaddr_mask[4]; 4146 __be32 dst_ipaddr[4]; 4147 __be32 dst_ipaddr_mask[4]; 4148 __be16 src_port; 4149 __be16 src_port_mask; 4150 __be16 dst_port; 4151 __be16 dst_port_mask; 4152 __le64 ntuple_filter_id_hint; 4153 }; 4154 4155 /* Output (24 bytes) */ 4156 struct hwrm_cfa_ntuple_filter_alloc_output { 4157 __le16 error_code; 4158 __le16 req_type; 4159 __le16 seq_id; 4160 __le16 resp_len; 4161 __le64 ntuple_filter_id; 4162 __le32 flow_id; 4163 u8 unused_0; 4164 u8 unused_1; 4165 u8 unused_2; 4166 u8 valid; 4167 }; 4168 4169 /* hwrm_cfa_ntuple_filter_free */ 4170 /* Input (24 bytes) */ 4171 struct hwrm_cfa_ntuple_filter_free_input { 4172 __le16 req_type; 4173 __le16 cmpl_ring; 4174 __le16 seq_id; 4175 __le16 target_id; 4176 __le64 resp_addr; 4177 __le64 ntuple_filter_id; 4178 }; 4179 4180 /* Output (16 bytes) */ 4181 struct hwrm_cfa_ntuple_filter_free_output { 4182 __le16 error_code; 4183 __le16 req_type; 4184 __le16 seq_id; 4185 __le16 resp_len; 4186 __le32 unused_0; 4187 u8 unused_1; 4188 u8 unused_2; 4189 u8 unused_3; 4190 u8 valid; 4191 }; 4192 4193 /* hwrm_cfa_ntuple_filter_cfg */ 4194 /* Input (48 bytes) */ 4195 struct hwrm_cfa_ntuple_filter_cfg_input { 4196 __le16 req_type; 4197 __le16 cmpl_ring; 4198 __le16 seq_id; 4199 __le16 target_id; 4200 __le64 resp_addr; 4201 __le32 enables; 4202 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4203 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4204 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4205 __le32 unused_0; 4206 __le64 ntuple_filter_id; 4207 __le32 new_dst_id; 4208 __le32 new_mirror_vnic_id; 4209 __le16 new_meter_instance_id; 4210 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4211 __le16 unused_1[3]; 4212 }; 4213 4214 /* Output (16 bytes) */ 4215 struct hwrm_cfa_ntuple_filter_cfg_output { 4216 __le16 error_code; 4217 __le16 req_type; 4218 __le16 seq_id; 4219 __le16 resp_len; 4220 __le32 unused_0; 4221 u8 unused_1; 4222 u8 unused_2; 4223 u8 unused_3; 4224 u8 valid; 4225 }; 4226 4227 /* hwrm_tunnel_dst_port_query */ 4228 /* Input (24 bytes) */ 4229 struct hwrm_tunnel_dst_port_query_input { 4230 __le16 req_type; 4231 __le16 cmpl_ring; 4232 __le16 seq_id; 4233 __le16 target_id; 4234 __le64 resp_addr; 4235 u8 tunnel_type; 4236 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4237 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4238 u8 unused_0[7]; 4239 }; 4240 4241 /* Output (16 bytes) */ 4242 struct hwrm_tunnel_dst_port_query_output { 4243 __le16 error_code; 4244 __le16 req_type; 4245 __le16 seq_id; 4246 __le16 resp_len; 4247 __le16 tunnel_dst_port_id; 4248 __be16 tunnel_dst_port_val; 4249 u8 unused_0; 4250 u8 unused_1; 4251 u8 unused_2; 4252 u8 valid; 4253 }; 4254 4255 /* hwrm_tunnel_dst_port_alloc */ 4256 /* Input (24 bytes) */ 4257 struct hwrm_tunnel_dst_port_alloc_input { 4258 __le16 req_type; 4259 __le16 cmpl_ring; 4260 __le16 seq_id; 4261 __le16 target_id; 4262 __le64 resp_addr; 4263 u8 tunnel_type; 4264 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4265 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4266 u8 unused_0; 4267 __be16 tunnel_dst_port_val; 4268 __le32 unused_1; 4269 }; 4270 4271 /* Output (16 bytes) */ 4272 struct hwrm_tunnel_dst_port_alloc_output { 4273 __le16 error_code; 4274 __le16 req_type; 4275 __le16 seq_id; 4276 __le16 resp_len; 4277 __le16 tunnel_dst_port_id; 4278 u8 unused_0; 4279 u8 unused_1; 4280 u8 unused_2; 4281 u8 unused_3; 4282 u8 unused_4; 4283 u8 valid; 4284 }; 4285 4286 /* hwrm_tunnel_dst_port_free */ 4287 /* Input (24 bytes) */ 4288 struct hwrm_tunnel_dst_port_free_input { 4289 __le16 req_type; 4290 __le16 cmpl_ring; 4291 __le16 seq_id; 4292 __le16 target_id; 4293 __le64 resp_addr; 4294 u8 tunnel_type; 4295 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4296 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4297 u8 unused_0; 4298 __le16 tunnel_dst_port_id; 4299 __le32 unused_1; 4300 }; 4301 4302 /* Output (16 bytes) */ 4303 struct hwrm_tunnel_dst_port_free_output { 4304 __le16 error_code; 4305 __le16 req_type; 4306 __le16 seq_id; 4307 __le16 resp_len; 4308 __le32 unused_0; 4309 u8 unused_1; 4310 u8 unused_2; 4311 u8 unused_3; 4312 u8 valid; 4313 }; 4314 4315 /* hwrm_stat_ctx_alloc */ 4316 /* Input (32 bytes) */ 4317 struct hwrm_stat_ctx_alloc_input { 4318 __le16 req_type; 4319 __le16 cmpl_ring; 4320 __le16 seq_id; 4321 __le16 target_id; 4322 __le64 resp_addr; 4323 __le64 stats_dma_addr; 4324 __le32 update_period_ms; 4325 u8 stat_ctx_flags; 4326 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 4327 u8 unused_0[3]; 4328 }; 4329 4330 /* Output (16 bytes) */ 4331 struct hwrm_stat_ctx_alloc_output { 4332 __le16 error_code; 4333 __le16 req_type; 4334 __le16 seq_id; 4335 __le16 resp_len; 4336 __le32 stat_ctx_id; 4337 u8 unused_0; 4338 u8 unused_1; 4339 u8 unused_2; 4340 u8 valid; 4341 }; 4342 4343 /* hwrm_stat_ctx_free */ 4344 /* Input (24 bytes) */ 4345 struct hwrm_stat_ctx_free_input { 4346 __le16 req_type; 4347 __le16 cmpl_ring; 4348 __le16 seq_id; 4349 __le16 target_id; 4350 __le64 resp_addr; 4351 __le32 stat_ctx_id; 4352 __le32 unused_0; 4353 }; 4354 4355 /* Output (16 bytes) */ 4356 struct hwrm_stat_ctx_free_output { 4357 __le16 error_code; 4358 __le16 req_type; 4359 __le16 seq_id; 4360 __le16 resp_len; 4361 __le32 stat_ctx_id; 4362 u8 unused_0; 4363 u8 unused_1; 4364 u8 unused_2; 4365 u8 valid; 4366 }; 4367 4368 /* hwrm_stat_ctx_query */ 4369 /* Input (24 bytes) */ 4370 struct hwrm_stat_ctx_query_input { 4371 __le16 req_type; 4372 __le16 cmpl_ring; 4373 __le16 seq_id; 4374 __le16 target_id; 4375 __le64 resp_addr; 4376 __le32 stat_ctx_id; 4377 __le32 unused_0; 4378 }; 4379 4380 /* Output (176 bytes) */ 4381 struct hwrm_stat_ctx_query_output { 4382 __le16 error_code; 4383 __le16 req_type; 4384 __le16 seq_id; 4385 __le16 resp_len; 4386 __le64 tx_ucast_pkts; 4387 __le64 tx_mcast_pkts; 4388 __le64 tx_bcast_pkts; 4389 __le64 tx_err_pkts; 4390 __le64 tx_drop_pkts; 4391 __le64 tx_ucast_bytes; 4392 __le64 tx_mcast_bytes; 4393 __le64 tx_bcast_bytes; 4394 __le64 rx_ucast_pkts; 4395 __le64 rx_mcast_pkts; 4396 __le64 rx_bcast_pkts; 4397 __le64 rx_err_pkts; 4398 __le64 rx_drop_pkts; 4399 __le64 rx_ucast_bytes; 4400 __le64 rx_mcast_bytes; 4401 __le64 rx_bcast_bytes; 4402 __le64 rx_agg_pkts; 4403 __le64 rx_agg_bytes; 4404 __le64 rx_agg_events; 4405 __le64 rx_agg_aborts; 4406 __le32 unused_0; 4407 u8 unused_1; 4408 u8 unused_2; 4409 u8 unused_3; 4410 u8 valid; 4411 }; 4412 4413 /* hwrm_stat_ctx_clr_stats */ 4414 /* Input (24 bytes) */ 4415 struct hwrm_stat_ctx_clr_stats_input { 4416 __le16 req_type; 4417 __le16 cmpl_ring; 4418 __le16 seq_id; 4419 __le16 target_id; 4420 __le64 resp_addr; 4421 __le32 stat_ctx_id; 4422 __le32 unused_0; 4423 }; 4424 4425 /* Output (16 bytes) */ 4426 struct hwrm_stat_ctx_clr_stats_output { 4427 __le16 error_code; 4428 __le16 req_type; 4429 __le16 seq_id; 4430 __le16 resp_len; 4431 __le32 unused_0; 4432 u8 unused_1; 4433 u8 unused_2; 4434 u8 unused_3; 4435 u8 valid; 4436 }; 4437 4438 /* hwrm_fw_reset */ 4439 /* Input (24 bytes) */ 4440 struct hwrm_fw_reset_input { 4441 __le16 req_type; 4442 __le16 cmpl_ring; 4443 __le16 seq_id; 4444 __le16 target_id; 4445 __le64 resp_addr; 4446 u8 embedded_proc_type; 4447 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4448 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4449 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4450 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4451 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 4452 u8 selfrst_status; 4453 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 4454 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 4455 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4456 __le16 unused_0[3]; 4457 }; 4458 4459 /* Output (16 bytes) */ 4460 struct hwrm_fw_reset_output { 4461 __le16 error_code; 4462 __le16 req_type; 4463 __le16 seq_id; 4464 __le16 resp_len; 4465 u8 selfrst_status; 4466 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4467 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4468 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4469 u8 unused_0; 4470 __le16 unused_1; 4471 u8 unused_2; 4472 u8 unused_3; 4473 u8 unused_4; 4474 u8 valid; 4475 }; 4476 4477 /* hwrm_fw_qstatus */ 4478 /* Input (24 bytes) */ 4479 struct hwrm_fw_qstatus_input { 4480 __le16 req_type; 4481 __le16 cmpl_ring; 4482 __le16 seq_id; 4483 __le16 target_id; 4484 __le64 resp_addr; 4485 u8 embedded_proc_type; 4486 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4487 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4488 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4489 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4490 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 4491 u8 unused_0[7]; 4492 }; 4493 4494 /* Output (16 bytes) */ 4495 struct hwrm_fw_qstatus_output { 4496 __le16 error_code; 4497 __le16 req_type; 4498 __le16 seq_id; 4499 __le16 resp_len; 4500 u8 selfrst_status; 4501 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4502 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4503 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4504 u8 unused_0; 4505 __le16 unused_1; 4506 u8 unused_2; 4507 u8 unused_3; 4508 u8 unused_4; 4509 u8 valid; 4510 }; 4511 4512 /* hwrm_fw_set_time */ 4513 /* Input (32 bytes) */ 4514 struct hwrm_fw_set_time_input { 4515 __le16 req_type; 4516 __le16 cmpl_ring; 4517 __le16 seq_id; 4518 __le16 target_id; 4519 __le64 resp_addr; 4520 __le16 year; 4521 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4522 u8 month; 4523 u8 day; 4524 u8 hour; 4525 u8 minute; 4526 u8 second; 4527 u8 unused_0; 4528 __le16 millisecond; 4529 __le16 zone; 4530 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4531 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4532 __le32 unused_1; 4533 }; 4534 4535 /* Output (16 bytes) */ 4536 struct hwrm_fw_set_time_output { 4537 __le16 error_code; 4538 __le16 req_type; 4539 __le16 seq_id; 4540 __le16 resp_len; 4541 __le32 unused_0; 4542 u8 unused_1; 4543 u8 unused_2; 4544 u8 unused_3; 4545 u8 valid; 4546 }; 4547 4548 /* hwrm_fw_set_structured_data */ 4549 /* Input (32 bytes) */ 4550 struct hwrm_fw_set_structured_data_input { 4551 __le16 req_type; 4552 __le16 cmpl_ring; 4553 __le16 seq_id; 4554 __le16 target_id; 4555 __le64 resp_addr; 4556 __le64 src_data_addr; 4557 __le16 data_len; 4558 u8 hdr_cnt; 4559 u8 unused_0[5]; 4560 }; 4561 4562 /* Output (16 bytes) */ 4563 struct hwrm_fw_set_structured_data_output { 4564 __le16 error_code; 4565 __le16 req_type; 4566 __le16 seq_id; 4567 __le16 resp_len; 4568 __le32 unused_0; 4569 u8 unused_1; 4570 u8 unused_2; 4571 u8 unused_3; 4572 u8 valid; 4573 }; 4574 4575 /* hwrm_fw_get_structured_data */ 4576 /* Input (32 bytes) */ 4577 struct hwrm_fw_get_structured_data_input { 4578 __le16 req_type; 4579 __le16 cmpl_ring; 4580 __le16 seq_id; 4581 __le16 target_id; 4582 __le64 resp_addr; 4583 __le64 dest_data_addr; 4584 __le16 data_len; 4585 __le16 structure_id; 4586 __le16 subtype; 4587 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 4588 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 4589 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 4590 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 4591 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 4592 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 4593 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 4594 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 4595 u8 count; 4596 u8 unused_0; 4597 }; 4598 4599 /* Output (16 bytes) */ 4600 struct hwrm_fw_get_structured_data_output { 4601 __le16 error_code; 4602 __le16 req_type; 4603 __le16 seq_id; 4604 __le16 resp_len; 4605 u8 hdr_cnt; 4606 u8 unused_0; 4607 __le16 unused_1; 4608 u8 unused_2; 4609 u8 unused_3; 4610 u8 unused_4; 4611 u8 valid; 4612 }; 4613 4614 /* hwrm_exec_fwd_resp */ 4615 /* Input (128 bytes) */ 4616 struct hwrm_exec_fwd_resp_input { 4617 __le16 req_type; 4618 __le16 cmpl_ring; 4619 __le16 seq_id; 4620 __le16 target_id; 4621 __le64 resp_addr; 4622 __le32 encap_request[26]; 4623 __le16 encap_resp_target_id; 4624 __le16 unused_0[3]; 4625 }; 4626 4627 /* Output (16 bytes) */ 4628 struct hwrm_exec_fwd_resp_output { 4629 __le16 error_code; 4630 __le16 req_type; 4631 __le16 seq_id; 4632 __le16 resp_len; 4633 __le32 unused_0; 4634 u8 unused_1; 4635 u8 unused_2; 4636 u8 unused_3; 4637 u8 valid; 4638 }; 4639 4640 /* hwrm_reject_fwd_resp */ 4641 /* Input (128 bytes) */ 4642 struct hwrm_reject_fwd_resp_input { 4643 __le16 req_type; 4644 __le16 cmpl_ring; 4645 __le16 seq_id; 4646 __le16 target_id; 4647 __le64 resp_addr; 4648 __le32 encap_request[26]; 4649 __le16 encap_resp_target_id; 4650 __le16 unused_0[3]; 4651 }; 4652 4653 /* Output (16 bytes) */ 4654 struct hwrm_reject_fwd_resp_output { 4655 __le16 error_code; 4656 __le16 req_type; 4657 __le16 seq_id; 4658 __le16 resp_len; 4659 __le32 unused_0; 4660 u8 unused_1; 4661 u8 unused_2; 4662 u8 unused_3; 4663 u8 valid; 4664 }; 4665 4666 /* hwrm_fwd_resp */ 4667 /* Input (40 bytes) */ 4668 struct hwrm_fwd_resp_input { 4669 __le16 req_type; 4670 __le16 cmpl_ring; 4671 __le16 seq_id; 4672 __le16 target_id; 4673 __le64 resp_addr; 4674 __le16 encap_resp_target_id; 4675 __le16 encap_resp_cmpl_ring; 4676 __le16 encap_resp_len; 4677 u8 unused_0; 4678 u8 unused_1; 4679 __le64 encap_resp_addr; 4680 __le32 encap_resp[24]; 4681 }; 4682 4683 /* Output (16 bytes) */ 4684 struct hwrm_fwd_resp_output { 4685 __le16 error_code; 4686 __le16 req_type; 4687 __le16 seq_id; 4688 __le16 resp_len; 4689 __le32 unused_0; 4690 u8 unused_1; 4691 u8 unused_2; 4692 u8 unused_3; 4693 u8 valid; 4694 }; 4695 4696 /* hwrm_fwd_async_event_cmpl */ 4697 /* Input (32 bytes) */ 4698 struct hwrm_fwd_async_event_cmpl_input { 4699 __le16 req_type; 4700 __le16 cmpl_ring; 4701 __le16 seq_id; 4702 __le16 target_id; 4703 __le64 resp_addr; 4704 __le16 encap_async_event_target_id; 4705 u8 unused_0; 4706 u8 unused_1; 4707 u8 unused_2[3]; 4708 u8 unused_3; 4709 __le32 encap_async_event_cmpl[4]; 4710 }; 4711 4712 /* Output (16 bytes) */ 4713 struct hwrm_fwd_async_event_cmpl_output { 4714 __le16 error_code; 4715 __le16 req_type; 4716 __le16 seq_id; 4717 __le16 resp_len; 4718 __le32 unused_0; 4719 u8 unused_1; 4720 u8 unused_2; 4721 u8 unused_3; 4722 u8 valid; 4723 }; 4724 4725 /* hwrm_temp_monitor_query */ 4726 /* Input (16 bytes) */ 4727 struct hwrm_temp_monitor_query_input { 4728 __le16 req_type; 4729 __le16 cmpl_ring; 4730 __le16 seq_id; 4731 __le16 target_id; 4732 __le64 resp_addr; 4733 }; 4734 4735 /* Output (16 bytes) */ 4736 struct hwrm_temp_monitor_query_output { 4737 __le16 error_code; 4738 __le16 req_type; 4739 __le16 seq_id; 4740 __le16 resp_len; 4741 u8 temp; 4742 u8 unused_0; 4743 __le16 unused_1; 4744 u8 unused_2; 4745 u8 unused_3; 4746 u8 unused_4; 4747 u8 valid; 4748 }; 4749 4750 /* hwrm_wol_filter_alloc */ 4751 /* Input (64 bytes) */ 4752 struct hwrm_wol_filter_alloc_input { 4753 __le16 req_type; 4754 __le16 cmpl_ring; 4755 __le16 seq_id; 4756 __le16 target_id; 4757 __le64 resp_addr; 4758 __le32 flags; 4759 __le32 enables; 4760 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 4761 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 4762 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 4763 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 4764 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 4765 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 4766 __le16 port_id; 4767 u8 wol_type; 4768 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 4769 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 4770 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 4771 u8 unused_0; 4772 __le32 unused_1; 4773 u8 mac_address[6]; 4774 __le16 pattern_offset; 4775 __le16 pattern_buf_size; 4776 __le16 pattern_mask_size; 4777 __le32 unused_2; 4778 __le64 pattern_buf_addr; 4779 __le64 pattern_mask_addr; 4780 }; 4781 4782 /* Output (16 bytes) */ 4783 struct hwrm_wol_filter_alloc_output { 4784 __le16 error_code; 4785 __le16 req_type; 4786 __le16 seq_id; 4787 __le16 resp_len; 4788 u8 wol_filter_id; 4789 u8 unused_0; 4790 __le16 unused_1; 4791 u8 unused_2; 4792 u8 unused_3; 4793 u8 unused_4; 4794 u8 valid; 4795 }; 4796 4797 /* hwrm_wol_filter_free */ 4798 /* Input (32 bytes) */ 4799 struct hwrm_wol_filter_free_input { 4800 __le16 req_type; 4801 __le16 cmpl_ring; 4802 __le16 seq_id; 4803 __le16 target_id; 4804 __le64 resp_addr; 4805 __le32 flags; 4806 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 4807 __le32 enables; 4808 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 4809 __le16 port_id; 4810 u8 wol_filter_id; 4811 u8 unused_0[5]; 4812 }; 4813 4814 /* Output (16 bytes) */ 4815 struct hwrm_wol_filter_free_output { 4816 __le16 error_code; 4817 __le16 req_type; 4818 __le16 seq_id; 4819 __le16 resp_len; 4820 __le32 unused_0; 4821 u8 unused_1; 4822 u8 unused_2; 4823 u8 unused_3; 4824 u8 valid; 4825 }; 4826 4827 /* hwrm_wol_filter_qcfg */ 4828 /* Input (56 bytes) */ 4829 struct hwrm_wol_filter_qcfg_input { 4830 __le16 req_type; 4831 __le16 cmpl_ring; 4832 __le16 seq_id; 4833 __le16 target_id; 4834 __le64 resp_addr; 4835 __le16 port_id; 4836 __le16 handle; 4837 __le32 unused_0; 4838 __le64 pattern_buf_addr; 4839 __le16 pattern_buf_size; 4840 u8 unused_1; 4841 u8 unused_2; 4842 u8 unused_3[3]; 4843 u8 unused_4; 4844 __le64 pattern_mask_addr; 4845 __le16 pattern_mask_size; 4846 __le16 unused_5[3]; 4847 }; 4848 4849 /* Output (32 bytes) */ 4850 struct hwrm_wol_filter_qcfg_output { 4851 __le16 error_code; 4852 __le16 req_type; 4853 __le16 seq_id; 4854 __le16 resp_len; 4855 __le16 next_handle; 4856 u8 wol_filter_id; 4857 u8 wol_type; 4858 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 4859 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 4860 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 4861 __le32 unused_0; 4862 u8 mac_address[6]; 4863 __le16 pattern_offset; 4864 __le16 pattern_size; 4865 __le16 pattern_mask_size; 4866 u8 unused_1; 4867 u8 unused_2; 4868 u8 unused_3; 4869 u8 valid; 4870 }; 4871 4872 /* hwrm_wol_reason_qcfg */ 4873 /* Input (40 bytes) */ 4874 struct hwrm_wol_reason_qcfg_input { 4875 __le16 req_type; 4876 __le16 cmpl_ring; 4877 __le16 seq_id; 4878 __le16 target_id; 4879 __le64 resp_addr; 4880 __le16 port_id; 4881 u8 unused_0; 4882 u8 unused_1; 4883 u8 unused_2[3]; 4884 u8 unused_3; 4885 __le64 wol_pkt_buf_addr; 4886 __le16 wol_pkt_buf_size; 4887 __le16 unused_4[3]; 4888 }; 4889 4890 /* Output (16 bytes) */ 4891 struct hwrm_wol_reason_qcfg_output { 4892 __le16 error_code; 4893 __le16 req_type; 4894 __le16 seq_id; 4895 __le16 resp_len; 4896 u8 wol_filter_id; 4897 u8 wol_reason; 4898 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 4899 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 4900 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 4901 u8 wol_pkt_len; 4902 u8 unused_0; 4903 u8 unused_1; 4904 u8 unused_2; 4905 u8 unused_3; 4906 u8 valid; 4907 }; 4908 4909 /* hwrm_nvm_read */ 4910 /* Input (40 bytes) */ 4911 struct hwrm_nvm_read_input { 4912 __le16 req_type; 4913 __le16 cmpl_ring; 4914 __le16 seq_id; 4915 __le16 target_id; 4916 __le64 resp_addr; 4917 __le64 host_dest_addr; 4918 __le16 dir_idx; 4919 u8 unused_0; 4920 u8 unused_1; 4921 __le32 offset; 4922 __le32 len; 4923 __le32 unused_2; 4924 }; 4925 4926 /* Output (16 bytes) */ 4927 struct hwrm_nvm_read_output { 4928 __le16 error_code; 4929 __le16 req_type; 4930 __le16 seq_id; 4931 __le16 resp_len; 4932 __le32 unused_0; 4933 u8 unused_1; 4934 u8 unused_2; 4935 u8 unused_3; 4936 u8 valid; 4937 }; 4938 4939 /* hwrm_nvm_get_dir_entries */ 4940 /* Input (24 bytes) */ 4941 struct hwrm_nvm_get_dir_entries_input { 4942 __le16 req_type; 4943 __le16 cmpl_ring; 4944 __le16 seq_id; 4945 __le16 target_id; 4946 __le64 resp_addr; 4947 __le64 host_dest_addr; 4948 }; 4949 4950 /* Output (16 bytes) */ 4951 struct hwrm_nvm_get_dir_entries_output { 4952 __le16 error_code; 4953 __le16 req_type; 4954 __le16 seq_id; 4955 __le16 resp_len; 4956 __le32 unused_0; 4957 u8 unused_1; 4958 u8 unused_2; 4959 u8 unused_3; 4960 u8 valid; 4961 }; 4962 4963 /* hwrm_nvm_get_dir_info */ 4964 /* Input (16 bytes) */ 4965 struct hwrm_nvm_get_dir_info_input { 4966 __le16 req_type; 4967 __le16 cmpl_ring; 4968 __le16 seq_id; 4969 __le16 target_id; 4970 __le64 resp_addr; 4971 }; 4972 4973 /* Output (24 bytes) */ 4974 struct hwrm_nvm_get_dir_info_output { 4975 __le16 error_code; 4976 __le16 req_type; 4977 __le16 seq_id; 4978 __le16 resp_len; 4979 __le32 entries; 4980 __le32 entry_length; 4981 __le32 unused_0; 4982 u8 unused_1; 4983 u8 unused_2; 4984 u8 unused_3; 4985 u8 valid; 4986 }; 4987 4988 /* hwrm_nvm_write */ 4989 /* Input (48 bytes) */ 4990 struct hwrm_nvm_write_input { 4991 __le16 req_type; 4992 __le16 cmpl_ring; 4993 __le16 seq_id; 4994 __le16 target_id; 4995 __le64 resp_addr; 4996 __le64 host_src_addr; 4997 __le16 dir_type; 4998 __le16 dir_ordinal; 4999 __le16 dir_ext; 5000 __le16 dir_attr; 5001 __le32 dir_data_length; 5002 __le16 option; 5003 __le16 flags; 5004 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5005 __le32 dir_item_length; 5006 __le32 unused_0; 5007 }; 5008 5009 /* Output (16 bytes) */ 5010 struct hwrm_nvm_write_output { 5011 __le16 error_code; 5012 __le16 req_type; 5013 __le16 seq_id; 5014 __le16 resp_len; 5015 __le32 dir_item_length; 5016 __le16 dir_idx; 5017 u8 unused_0; 5018 u8 valid; 5019 }; 5020 5021 /* Command specific Error Codes (8 bytes) */ 5022 struct hwrm_nvm_write_cmd_err { 5023 u8 code; 5024 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 5025 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5026 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 5027 u8 unused_0[7]; 5028 }; 5029 5030 /* hwrm_nvm_modify */ 5031 /* Input (40 bytes) */ 5032 struct hwrm_nvm_modify_input { 5033 __le16 req_type; 5034 __le16 cmpl_ring; 5035 __le16 seq_id; 5036 __le16 target_id; 5037 __le64 resp_addr; 5038 __le64 host_src_addr; 5039 __le16 dir_idx; 5040 u8 unused_0; 5041 u8 unused_1; 5042 __le32 offset; 5043 __le32 len; 5044 __le32 unused_2; 5045 }; 5046 5047 /* Output (16 bytes) */ 5048 struct hwrm_nvm_modify_output { 5049 __le16 error_code; 5050 __le16 req_type; 5051 __le16 seq_id; 5052 __le16 resp_len; 5053 __le32 unused_0; 5054 u8 unused_1; 5055 u8 unused_2; 5056 u8 unused_3; 5057 u8 valid; 5058 }; 5059 5060 /* hwrm_nvm_find_dir_entry */ 5061 /* Input (32 bytes) */ 5062 struct hwrm_nvm_find_dir_entry_input { 5063 __le16 req_type; 5064 __le16 cmpl_ring; 5065 __le16 seq_id; 5066 __le16 target_id; 5067 __le64 resp_addr; 5068 __le32 enables; 5069 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 5070 __le16 dir_idx; 5071 __le16 dir_type; 5072 __le16 dir_ordinal; 5073 __le16 dir_ext; 5074 u8 opt_ordinal; 5075 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 5076 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 5077 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 5078 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 5079 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 5080 u8 unused_1[3]; 5081 }; 5082 5083 /* Output (32 bytes) */ 5084 struct hwrm_nvm_find_dir_entry_output { 5085 __le16 error_code; 5086 __le16 req_type; 5087 __le16 seq_id; 5088 __le16 resp_len; 5089 __le32 dir_item_length; 5090 __le32 dir_data_length; 5091 __le32 fw_ver; 5092 __le16 dir_ordinal; 5093 __le16 dir_idx; 5094 __le32 unused_0; 5095 u8 unused_1; 5096 u8 unused_2; 5097 u8 unused_3; 5098 u8 valid; 5099 }; 5100 5101 /* hwrm_nvm_erase_dir_entry */ 5102 /* Input (24 bytes) */ 5103 struct hwrm_nvm_erase_dir_entry_input { 5104 __le16 req_type; 5105 __le16 cmpl_ring; 5106 __le16 seq_id; 5107 __le16 target_id; 5108 __le64 resp_addr; 5109 __le16 dir_idx; 5110 __le16 unused_0[3]; 5111 }; 5112 5113 /* Output (16 bytes) */ 5114 struct hwrm_nvm_erase_dir_entry_output { 5115 __le16 error_code; 5116 __le16 req_type; 5117 __le16 seq_id; 5118 __le16 resp_len; 5119 __le32 unused_0; 5120 u8 unused_1; 5121 u8 unused_2; 5122 u8 unused_3; 5123 u8 valid; 5124 }; 5125 5126 /* hwrm_nvm_get_dev_info */ 5127 /* Input (16 bytes) */ 5128 struct hwrm_nvm_get_dev_info_input { 5129 __le16 req_type; 5130 __le16 cmpl_ring; 5131 __le16 seq_id; 5132 __le16 target_id; 5133 __le64 resp_addr; 5134 }; 5135 5136 /* Output (32 bytes) */ 5137 struct hwrm_nvm_get_dev_info_output { 5138 __le16 error_code; 5139 __le16 req_type; 5140 __le16 seq_id; 5141 __le16 resp_len; 5142 __le16 manufacturer_id; 5143 __le16 device_id; 5144 __le32 sector_size; 5145 __le32 nvram_size; 5146 __le32 reserved_size; 5147 __le32 available_size; 5148 u8 unused_0; 5149 u8 unused_1; 5150 u8 unused_2; 5151 u8 valid; 5152 }; 5153 5154 /* hwrm_nvm_mod_dir_entry */ 5155 /* Input (32 bytes) */ 5156 struct hwrm_nvm_mod_dir_entry_input { 5157 __le16 req_type; 5158 __le16 cmpl_ring; 5159 __le16 seq_id; 5160 __le16 target_id; 5161 __le64 resp_addr; 5162 __le32 enables; 5163 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 5164 __le16 dir_idx; 5165 __le16 dir_ordinal; 5166 __le16 dir_ext; 5167 __le16 dir_attr; 5168 __le32 checksum; 5169 }; 5170 5171 /* Output (16 bytes) */ 5172 struct hwrm_nvm_mod_dir_entry_output { 5173 __le16 error_code; 5174 __le16 req_type; 5175 __le16 seq_id; 5176 __le16 resp_len; 5177 __le32 unused_0; 5178 u8 unused_1; 5179 u8 unused_2; 5180 u8 unused_3; 5181 u8 valid; 5182 }; 5183 5184 /* hwrm_nvm_verify_update */ 5185 /* Input (24 bytes) */ 5186 struct hwrm_nvm_verify_update_input { 5187 __le16 req_type; 5188 __le16 cmpl_ring; 5189 __le16 seq_id; 5190 __le16 target_id; 5191 __le64 resp_addr; 5192 __le16 dir_type; 5193 __le16 dir_ordinal; 5194 __le16 dir_ext; 5195 __le16 unused_0; 5196 }; 5197 5198 /* Output (16 bytes) */ 5199 struct hwrm_nvm_verify_update_output { 5200 __le16 error_code; 5201 __le16 req_type; 5202 __le16 seq_id; 5203 __le16 resp_len; 5204 __le32 unused_0; 5205 u8 unused_1; 5206 u8 unused_2; 5207 u8 unused_3; 5208 u8 valid; 5209 }; 5210 5211 /* hwrm_nvm_install_update */ 5212 /* Input (24 bytes) */ 5213 struct hwrm_nvm_install_update_input { 5214 __le16 req_type; 5215 __le16 cmpl_ring; 5216 __le16 seq_id; 5217 __le16 target_id; 5218 __le64 resp_addr; 5219 __le32 install_type; 5220 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 5221 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 5222 __le16 flags; 5223 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 5224 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 5225 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 5226 __le16 unused_0; 5227 }; 5228 5229 /* Output (24 bytes) */ 5230 struct hwrm_nvm_install_update_output { 5231 __le16 error_code; 5232 __le16 req_type; 5233 __le16 seq_id; 5234 __le16 resp_len; 5235 __le64 installed_items; 5236 u8 result; 5237 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 5238 u8 problem_item; 5239 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 5240 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 5241 u8 reset_required; 5242 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 5243 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 5244 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 5245 u8 unused_0; 5246 u8 unused_1; 5247 u8 unused_2; 5248 u8 unused_3; 5249 u8 valid; 5250 }; 5251 5252 /* Command specific Error Codes (8 bytes) */ 5253 struct hwrm_nvm_install_update_cmd_err { 5254 u8 code; 5255 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 5256 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5257 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 5258 u8 unused_0[7]; 5259 }; 5260 5261 /* hwrm_selftest_qlist */ 5262 /* Input (16 bytes) */ 5263 struct hwrm_selftest_qlist_input { 5264 __le16 req_type; 5265 __le16 cmpl_ring; 5266 __le16 seq_id; 5267 __le16 target_id; 5268 __le64 resp_addr; 5269 }; 5270 5271 /* Output (248 bytes) */ 5272 struct hwrm_selftest_qlist_output { 5273 __le16 error_code; 5274 __le16 req_type; 5275 __le16 seq_id; 5276 __le16 resp_len; 5277 u8 num_tests; 5278 u8 available_tests; 5279 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 5280 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 5281 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 5282 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 5283 u8 offline_tests; 5284 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 5285 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 5286 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 5287 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 5288 u8 unused_0; 5289 __le16 test_timeout; 5290 u8 unused_1; 5291 u8 unused_2; 5292 char test0_name[32]; 5293 char test1_name[32]; 5294 char test2_name[32]; 5295 char test3_name[32]; 5296 char test4_name[32]; 5297 char test5_name[32]; 5298 char test6_name[32]; 5299 char test7_name[32]; 5300 }; 5301 5302 /* hwrm_selftest_exec */ 5303 /* Input (24 bytes) */ 5304 struct hwrm_selftest_exec_input { 5305 __le16 req_type; 5306 __le16 cmpl_ring; 5307 __le16 seq_id; 5308 __le16 target_id; 5309 __le64 resp_addr; 5310 u8 flags; 5311 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 5312 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 5313 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 5314 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 5315 u8 unused_0[7]; 5316 }; 5317 5318 /* Output (16 bytes) */ 5319 struct hwrm_selftest_exec_output { 5320 __le16 error_code; 5321 __le16 req_type; 5322 __le16 seq_id; 5323 __le16 resp_len; 5324 u8 requested_tests; 5325 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 5326 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 5327 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 5328 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 5329 u8 test_success; 5330 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 5331 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 5332 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 5333 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 5334 __le16 unused_0[3]; 5335 }; 5336 5337 /* hwrm_selftest_irq */ 5338 /* Input (16 bytes) */ 5339 struct hwrm_selftest_irq_input { 5340 __le16 req_type; 5341 __le16 cmpl_ring; 5342 __le16 seq_id; 5343 __le16 target_id; 5344 __le64 resp_addr; 5345 }; 5346 5347 /* Output (8 bytes) */ 5348 struct hwrm_selftest_irq_output { 5349 __le16 error_code; 5350 __le16 req_type; 5351 __le16 seq_id; 5352 __le16 resp_len; 5353 }; 5354 5355 /* Hardware Resource Manager Specification */ 5356 /* Input (16 bytes) */ 5357 struct input { 5358 __le16 req_type; 5359 __le16 cmpl_ring; 5360 __le16 seq_id; 5361 __le16 target_id; 5362 __le64 resp_addr; 5363 }; 5364 5365 /* Output (8 bytes) */ 5366 struct output { 5367 __le16 error_code; 5368 __le16 req_type; 5369 __le16 seq_id; 5370 __le16 resp_len; 5371 }; 5372 5373 /* Short Command Structure (16 bytes) */ 5374 struct hwrm_short_input { 5375 __le16 req_type; 5376 __le16 signature; 5377 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 5378 __le16 unused_0; 5379 __le16 size; 5380 __le64 req_addr; 5381 }; 5382 5383 /* Command numbering (8 bytes) */ 5384 struct cmd_nums { 5385 __le16 req_type; 5386 #define HWRM_VER_GET (0x0UL) 5387 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 5388 #define HWRM_FUNC_VF_CFG (0xfUL) 5389 #define RESERVED1 (0x10UL) 5390 #define HWRM_FUNC_RESET (0x11UL) 5391 #define HWRM_FUNC_GETFID (0x12UL) 5392 #define HWRM_FUNC_VF_ALLOC (0x13UL) 5393 #define HWRM_FUNC_VF_FREE (0x14UL) 5394 #define HWRM_FUNC_QCAPS (0x15UL) 5395 #define HWRM_FUNC_QCFG (0x16UL) 5396 #define HWRM_FUNC_CFG (0x17UL) 5397 #define HWRM_FUNC_QSTATS (0x18UL) 5398 #define HWRM_FUNC_CLR_STATS (0x19UL) 5399 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 5400 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 5401 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 5402 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 5403 #define HWRM_FUNC_DRV_QVER (0x1eUL) 5404 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 5405 #define HWRM_PORT_PHY_CFG (0x20UL) 5406 #define HWRM_PORT_MAC_CFG (0x21UL) 5407 #define HWRM_PORT_TS_QUERY (0x22UL) 5408 #define HWRM_PORT_QSTATS (0x23UL) 5409 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 5410 #define HWRM_PORT_CLR_STATS (0x25UL) 5411 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 5412 #define HWRM_PORT_PHY_QCFG (0x27UL) 5413 #define HWRM_PORT_MAC_QCFG (0x28UL) 5414 #define RESERVED7 (0x29UL) 5415 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 5416 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 5417 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 5418 #define HWRM_PORT_LED_CFG (0x2dUL) 5419 #define HWRM_PORT_LED_QCFG (0x2eUL) 5420 #define HWRM_PORT_LED_QCAPS (0x2fUL) 5421 #define HWRM_QUEUE_QPORTCFG (0x30UL) 5422 #define HWRM_QUEUE_QCFG (0x31UL) 5423 #define HWRM_QUEUE_CFG (0x32UL) 5424 #define RESERVED2 (0x33UL) 5425 #define RESERVED3 (0x34UL) 5426 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 5427 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 5428 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 5429 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 5430 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 5431 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 5432 #define HWRM_VNIC_ALLOC (0x40UL) 5433 #define HWRM_VNIC_FREE (0x41UL) 5434 #define HWRM_VNIC_CFG (0x42UL) 5435 #define HWRM_VNIC_QCFG (0x43UL) 5436 #define HWRM_VNIC_TPA_CFG (0x44UL) 5437 #define HWRM_VNIC_TPA_QCFG (0x45UL) 5438 #define HWRM_VNIC_RSS_CFG (0x46UL) 5439 #define HWRM_VNIC_RSS_QCFG (0x47UL) 5440 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 5441 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 5442 #define HWRM_VNIC_QCAPS (0x4aUL) 5443 #define HWRM_RING_ALLOC (0x50UL) 5444 #define HWRM_RING_FREE (0x51UL) 5445 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 5446 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 5447 #define HWRM_RING_RESET (0x5eUL) 5448 #define HWRM_RING_GRP_ALLOC (0x60UL) 5449 #define HWRM_RING_GRP_FREE (0x61UL) 5450 #define RESERVED5 (0x64UL) 5451 #define RESERVED6 (0x65UL) 5452 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 5453 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 5454 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 5455 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 5456 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 5457 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 5458 #define RESERVED4 (0x94UL) 5459 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 5460 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 5461 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 5462 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 5463 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 5464 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 5465 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 5466 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 5467 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 5468 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 5469 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 5470 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 5471 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 5472 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 5473 #define HWRM_STAT_CTX_FREE (0xb1UL) 5474 #define HWRM_STAT_CTX_QUERY (0xb2UL) 5475 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 5476 #define HWRM_FW_RESET (0xc0UL) 5477 #define HWRM_FW_QSTATUS (0xc1UL) 5478 #define HWRM_FW_SET_TIME (0xc8UL) 5479 #define HWRM_FW_GET_TIME (0xc9UL) 5480 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 5481 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 5482 #define HWRM_FW_IPC_MAILBOX (0xccUL) 5483 #define HWRM_EXEC_FWD_RESP (0xd0UL) 5484 #define HWRM_REJECT_FWD_RESP (0xd1UL) 5485 #define HWRM_FWD_RESP (0xd2UL) 5486 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 5487 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 5488 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 5489 #define HWRM_WOL_FILTER_FREE (0xf1UL) 5490 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 5491 #define HWRM_WOL_REASON_QCFG (0xf3UL) 5492 #define HWRM_CFA_METER_PROFILE_ALLOC (0xf5UL) 5493 #define HWRM_CFA_METER_PROFILE_FREE (0xf6UL) 5494 #define HWRM_CFA_METER_PROFILE_CFG (0xf7UL) 5495 #define HWRM_CFA_METER_INSTANCE_ALLOC (0xf8UL) 5496 #define HWRM_CFA_METER_INSTANCE_FREE (0xf9UL) 5497 #define HWRM_CFA_VF_PAIR_ALLOC (0x100UL) 5498 #define HWRM_CFA_VF_PAIR_FREE (0x101UL) 5499 #define HWRM_CFA_VF_PAIR_INFO (0x102UL) 5500 #define HWRM_CFA_FLOW_ALLOC (0x103UL) 5501 #define HWRM_CFA_FLOW_FREE (0x104UL) 5502 #define HWRM_CFA_FLOW_FLUSH (0x105UL) 5503 #define HWRM_CFA_FLOW_STATS (0x106UL) 5504 #define HWRM_CFA_FLOW_INFO (0x107UL) 5505 #define HWRM_SELFTEST_QLIST (0x200UL) 5506 #define HWRM_SELFTEST_EXEC (0x201UL) 5507 #define HWRM_SELFTEST_IRQ (0x202UL) 5508 #define HWRM_DBG_READ_DIRECT (0xff10UL) 5509 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 5510 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 5511 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 5512 #define HWRM_DBG_DUMP (0xff14UL) 5513 #define HWRM_NVM_FACTORY_DEFAULTS (0xffeeUL) 5514 #define HWRM_NVM_VALIDATE_OPTION (0xffefUL) 5515 #define HWRM_NVM_FLUSH (0xfff0UL) 5516 #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 5517 #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 5518 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 5519 #define HWRM_NVM_MODIFY (0xfff4UL) 5520 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 5521 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 5522 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 5523 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 5524 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 5525 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 5526 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 5527 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 5528 #define HWRM_NVM_READ (0xfffdUL) 5529 #define HWRM_NVM_WRITE (0xfffeUL) 5530 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 5531 __le16 unused_0[3]; 5532 }; 5533 5534 /* Return Codes (8 bytes) */ 5535 struct ret_codes { 5536 __le16 error_code; 5537 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 5538 #define HWRM_ERR_CODE_FAIL (0x1UL) 5539 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 5540 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 5541 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 5542 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 5543 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 5544 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 5545 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 5546 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 5547 __le16 unused_0[3]; 5548 }; 5549 5550 /* Output (16 bytes) */ 5551 struct hwrm_err_output { 5552 __le16 error_code; 5553 __le16 req_type; 5554 __le16 seq_id; 5555 __le16 resp_len; 5556 __le32 opaque_0; 5557 __le16 opaque_1; 5558 u8 cmd_err; 5559 u8 valid; 5560 }; 5561 5562 /* Port Tx Statistics Formats (408 bytes) */ 5563 struct tx_port_stats { 5564 __le64 tx_64b_frames; 5565 __le64 tx_65b_127b_frames; 5566 __le64 tx_128b_255b_frames; 5567 __le64 tx_256b_511b_frames; 5568 __le64 tx_512b_1023b_frames; 5569 __le64 tx_1024b_1518_frames; 5570 __le64 tx_good_vlan_frames; 5571 __le64 tx_1519b_2047_frames; 5572 __le64 tx_2048b_4095b_frames; 5573 __le64 tx_4096b_9216b_frames; 5574 __le64 tx_9217b_16383b_frames; 5575 __le64 tx_good_frames; 5576 __le64 tx_total_frames; 5577 __le64 tx_ucast_frames; 5578 __le64 tx_mcast_frames; 5579 __le64 tx_bcast_frames; 5580 __le64 tx_pause_frames; 5581 __le64 tx_pfc_frames; 5582 __le64 tx_jabber_frames; 5583 __le64 tx_fcs_err_frames; 5584 __le64 tx_control_frames; 5585 __le64 tx_oversz_frames; 5586 __le64 tx_single_dfrl_frames; 5587 __le64 tx_multi_dfrl_frames; 5588 __le64 tx_single_coll_frames; 5589 __le64 tx_multi_coll_frames; 5590 __le64 tx_late_coll_frames; 5591 __le64 tx_excessive_coll_frames; 5592 __le64 tx_frag_frames; 5593 __le64 tx_err; 5594 __le64 tx_tagged_frames; 5595 __le64 tx_dbl_tagged_frames; 5596 __le64 tx_runt_frames; 5597 __le64 tx_fifo_underruns; 5598 __le64 tx_pfc_ena_frames_pri0; 5599 __le64 tx_pfc_ena_frames_pri1; 5600 __le64 tx_pfc_ena_frames_pri2; 5601 __le64 tx_pfc_ena_frames_pri3; 5602 __le64 tx_pfc_ena_frames_pri4; 5603 __le64 tx_pfc_ena_frames_pri5; 5604 __le64 tx_pfc_ena_frames_pri6; 5605 __le64 tx_pfc_ena_frames_pri7; 5606 __le64 tx_eee_lpi_events; 5607 __le64 tx_eee_lpi_duration; 5608 __le64 tx_llfc_logical_msgs; 5609 __le64 tx_hcfc_msgs; 5610 __le64 tx_total_collisions; 5611 __le64 tx_bytes; 5612 __le64 tx_xthol_frames; 5613 __le64 tx_stat_discard; 5614 __le64 tx_stat_error; 5615 }; 5616 5617 /* Port Rx Statistics Formats (528 bytes) */ 5618 struct rx_port_stats { 5619 __le64 rx_64b_frames; 5620 __le64 rx_65b_127b_frames; 5621 __le64 rx_128b_255b_frames; 5622 __le64 rx_256b_511b_frames; 5623 __le64 rx_512b_1023b_frames; 5624 __le64 rx_1024b_1518_frames; 5625 __le64 rx_good_vlan_frames; 5626 __le64 rx_1519b_2047b_frames; 5627 __le64 rx_2048b_4095b_frames; 5628 __le64 rx_4096b_9216b_frames; 5629 __le64 rx_9217b_16383b_frames; 5630 __le64 rx_total_frames; 5631 __le64 rx_ucast_frames; 5632 __le64 rx_mcast_frames; 5633 __le64 rx_bcast_frames; 5634 __le64 rx_fcs_err_frames; 5635 __le64 rx_ctrl_frames; 5636 __le64 rx_pause_frames; 5637 __le64 rx_pfc_frames; 5638 __le64 rx_unsupported_opcode_frames; 5639 __le64 rx_unsupported_da_pausepfc_frames; 5640 __le64 rx_wrong_sa_frames; 5641 __le64 rx_align_err_frames; 5642 __le64 rx_oor_len_frames; 5643 __le64 rx_code_err_frames; 5644 __le64 rx_false_carrier_frames; 5645 __le64 rx_ovrsz_frames; 5646 __le64 rx_jbr_frames; 5647 __le64 rx_mtu_err_frames; 5648 __le64 rx_match_crc_frames; 5649 __le64 rx_promiscuous_frames; 5650 __le64 rx_tagged_frames; 5651 __le64 rx_double_tagged_frames; 5652 __le64 rx_trunc_frames; 5653 __le64 rx_good_frames; 5654 __le64 rx_pfc_xon2xoff_frames_pri0; 5655 __le64 rx_pfc_xon2xoff_frames_pri1; 5656 __le64 rx_pfc_xon2xoff_frames_pri2; 5657 __le64 rx_pfc_xon2xoff_frames_pri3; 5658 __le64 rx_pfc_xon2xoff_frames_pri4; 5659 __le64 rx_pfc_xon2xoff_frames_pri5; 5660 __le64 rx_pfc_xon2xoff_frames_pri6; 5661 __le64 rx_pfc_xon2xoff_frames_pri7; 5662 __le64 rx_pfc_ena_frames_pri0; 5663 __le64 rx_pfc_ena_frames_pri1; 5664 __le64 rx_pfc_ena_frames_pri2; 5665 __le64 rx_pfc_ena_frames_pri3; 5666 __le64 rx_pfc_ena_frames_pri4; 5667 __le64 rx_pfc_ena_frames_pri5; 5668 __le64 rx_pfc_ena_frames_pri6; 5669 __le64 rx_pfc_ena_frames_pri7; 5670 __le64 rx_sch_crc_err_frames; 5671 __le64 rx_undrsz_frames; 5672 __le64 rx_frag_frames; 5673 __le64 rx_eee_lpi_events; 5674 __le64 rx_eee_lpi_duration; 5675 __le64 rx_llfc_physical_msgs; 5676 __le64 rx_llfc_logical_msgs; 5677 __le64 rx_llfc_msgs_with_crc_err; 5678 __le64 rx_hcfc_msgs; 5679 __le64 rx_hcfc_msgs_with_crc_err; 5680 __le64 rx_bytes; 5681 __le64 rx_runt_bytes; 5682 __le64 rx_runt_frames; 5683 __le64 rx_stat_discard; 5684 __le64 rx_stat_err; 5685 }; 5686 5687 /* Periodic Statistics Context DMA to host (160 bytes) */ 5688 struct ctx_hw_stats { 5689 __le64 rx_ucast_pkts; 5690 __le64 rx_mcast_pkts; 5691 __le64 rx_bcast_pkts; 5692 __le64 rx_discard_pkts; 5693 __le64 rx_drop_pkts; 5694 __le64 rx_ucast_bytes; 5695 __le64 rx_mcast_bytes; 5696 __le64 rx_bcast_bytes; 5697 __le64 tx_ucast_pkts; 5698 __le64 tx_mcast_pkts; 5699 __le64 tx_bcast_pkts; 5700 __le64 tx_discard_pkts; 5701 __le64 tx_drop_pkts; 5702 __le64 tx_ucast_bytes; 5703 __le64 tx_mcast_bytes; 5704 __le64 tx_bcast_bytes; 5705 __le64 tpa_pkts; 5706 __le64 tpa_bytes; 5707 __le64 tpa_events; 5708 __le64 tpa_aborts; 5709 }; 5710 5711 /* Structure data header (16 bytes) */ 5712 struct hwrm_struct_hdr { 5713 __le16 struct_id; 5714 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 5715 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 5716 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 5717 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 5718 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 5719 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 5720 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 5721 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 5722 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 5723 __le16 len; 5724 u8 version; 5725 u8 count; 5726 __le16 subtype; 5727 __le16 next_offset; 5728 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 5729 __le16 unused_0[3]; 5730 }; 5731 5732 /* DCBX Application configuration structure (1057) (8 bytes) */ 5733 struct hwrm_struct_data_dcbx_app { 5734 __be16 protocol_id; 5735 u8 protocol_selector; 5736 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 5737 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 5738 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 5739 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 5740 u8 priority; 5741 u8 valid; 5742 u8 unused_0[3]; 5743 }; 5744 5745 #endif 5746