1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2017 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_HSI_H 12 #define BNXT_HSI_H 13 14 /* HSI and HWRM Specification 1.7.0 */ 15 #define HWRM_VERSION_MAJOR 1 16 #define HWRM_VERSION_MINOR 7 17 #define HWRM_VERSION_UPDATE 0 18 19 #define HWRM_VERSION_STR "1.7.0" 20 /* 21 * Following is the signature for HWRM message field that indicates not 22 * applicable (All F's). Need to cast it the size of the field if needed. 23 */ 24 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 25 #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 26 #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 27 #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 28 #define HW_HASH_KEY_SIZE 40 29 #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 30 31 /* Statistics Ejection Buffer Completion Record (16 bytes) */ 32 struct eject_cmpl { 33 __le16 type; 34 #define EJECT_CMPL_TYPE_MASK 0x3fUL 35 #define EJECT_CMPL_TYPE_SFT 0 36 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 37 __le16 len; 38 __le32 opaque; 39 __le32 v; 40 #define EJECT_CMPL_V 0x1UL 41 __le32 unused_2; 42 }; 43 44 /* HWRM Completion Record (16 bytes) */ 45 struct hwrm_cmpl { 46 __le16 type; 47 #define CMPL_TYPE_MASK 0x3fUL 48 #define CMPL_TYPE_SFT 0 49 #define CMPL_TYPE_HWRM_DONE 0x20UL 50 __le16 sequence_id; 51 __le32 unused_1; 52 __le32 v; 53 #define CMPL_V 0x1UL 54 __le32 unused_3; 55 }; 56 57 /* HWRM Forwarded Request (16 bytes) */ 58 struct hwrm_fwd_req_cmpl { 59 __le16 req_len_type; 60 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 61 #define FWD_REQ_CMPL_TYPE_SFT 0 62 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 63 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 64 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 65 __le16 source_id; 66 __le32 unused_0; 67 __le32 req_buf_addr_v[2]; 68 #define FWD_REQ_CMPL_V 0x1UL 69 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 70 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 71 }; 72 73 /* HWRM Forwarded Response (16 bytes) */ 74 struct hwrm_fwd_resp_cmpl { 75 __le16 type; 76 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 77 #define FWD_RESP_CMPL_TYPE_SFT 0 78 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 79 __le16 source_id; 80 __le16 resp_len; 81 __le16 unused_1; 82 __le32 resp_buf_addr_v[2]; 83 #define FWD_RESP_CMPL_V 0x1UL 84 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 85 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 86 }; 87 88 /* HWRM Asynchronous Event Completion Record (16 bytes) */ 89 struct hwrm_async_event_cmpl { 90 __le16 type; 91 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 92 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 93 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 94 __le16 event_id; 95 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 96 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 97 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 98 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 99 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 100 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 101 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 102 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 103 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 104 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 105 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 106 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 107 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 108 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 109 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 110 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 111 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 112 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 113 __le32 event_data2; 114 u8 opaque_v; 115 #define ASYNC_EVENT_CMPL_V 0x1UL 116 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 117 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 118 u8 timestamp_lo; 119 __le16 timestamp_hi; 120 __le32 event_data1; 121 }; 122 123 /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 124 struct hwrm_async_event_cmpl_link_status_change { 125 __le16 type; 126 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 127 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 128 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 129 __le16 event_id; 130 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 131 __le32 event_data2; 132 u8 opaque_v; 133 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 134 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 135 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 136 u8 timestamp_lo; 137 __le16 timestamp_hi; 138 __le32 event_data1; 139 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 140 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 141 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 142 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 143 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 144 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 145 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 146 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 147 }; 148 149 /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 150 struct hwrm_async_event_cmpl_link_mtu_change { 151 __le16 type; 152 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 153 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 154 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 155 __le16 event_id; 156 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 157 __le32 event_data2; 158 u8 opaque_v; 159 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 160 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 161 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 162 u8 timestamp_lo; 163 __le16 timestamp_hi; 164 __le32 event_data1; 165 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 166 #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 167 }; 168 169 /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 170 struct hwrm_async_event_cmpl_link_speed_change { 171 __le16 type; 172 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 173 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 174 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 175 __le16 event_id; 176 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 177 __le32 event_data2; 178 u8 opaque_v; 179 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 180 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 181 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 182 u8 timestamp_lo; 183 __le16 timestamp_hi; 184 __le32 event_data1; 185 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 186 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 187 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 188 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 189 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 190 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 191 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 192 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 193 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 194 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 195 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 196 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 197 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 198 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 199 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 200 #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 201 }; 202 203 /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 204 struct hwrm_async_event_cmpl_dcb_config_change { 205 __le16 type; 206 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 207 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 208 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 209 __le16 event_id; 210 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 211 __le32 event_data2; 212 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 213 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 214 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 215 u8 opaque_v; 216 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 217 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 218 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 219 u8 timestamp_lo; 220 __le16 timestamp_hi; 221 __le32 event_data1; 222 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 223 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 224 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 225 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 226 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 227 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 228 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 229 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 230 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 231 #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 232 }; 233 234 /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 235 struct hwrm_async_event_cmpl_port_conn_not_allowed { 236 __le16 type; 237 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 238 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 239 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 240 __le16 event_id; 241 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 242 __le32 event_data2; 243 u8 opaque_v; 244 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 245 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 246 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 247 u8 timestamp_lo; 248 __le16 timestamp_hi; 249 __le32 event_data1; 250 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 251 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 252 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 253 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 254 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 255 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 256 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 257 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 258 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 259 }; 260 261 /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 262 struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 263 __le16 type; 264 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 265 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 266 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 267 __le16 event_id; 268 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 269 __le32 event_data2; 270 u8 opaque_v; 271 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 272 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 273 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 274 u8 timestamp_lo; 275 __le16 timestamp_hi; 276 __le32 event_data1; 277 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 278 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 279 }; 280 281 /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 282 struct hwrm_async_event_cmpl_link_speed_cfg_change { 283 __le16 type; 284 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 285 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 286 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 287 __le16 event_id; 288 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 289 __le32 event_data2; 290 u8 opaque_v; 291 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 292 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 293 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 294 u8 timestamp_lo; 295 __le16 timestamp_hi; 296 __le32 event_data1; 297 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 298 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 299 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 300 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 301 }; 302 303 /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 304 struct hwrm_async_event_cmpl_func_drvr_unload { 305 __le16 type; 306 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 307 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 308 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 309 __le16 event_id; 310 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 311 __le32 event_data2; 312 u8 opaque_v; 313 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 314 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 315 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 316 u8 timestamp_lo; 317 __le16 timestamp_hi; 318 __le32 event_data1; 319 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 320 #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 321 }; 322 323 /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 324 struct hwrm_async_event_cmpl_func_drvr_load { 325 __le16 type; 326 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 327 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 328 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 329 __le16 event_id; 330 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 331 __le32 event_data2; 332 u8 opaque_v; 333 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 334 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 335 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 336 u8 timestamp_lo; 337 __le16 timestamp_hi; 338 __le32 event_data1; 339 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 340 #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 341 }; 342 343 /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ 344 struct hwrm_async_event_cmpl_func_flr_proc_cmplt { 345 __le16 type; 346 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL 347 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 348 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 349 __le16 event_id; 350 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 351 __le32 event_data2; 352 u8 opaque_v; 353 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL 354 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL 355 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 356 u8 timestamp_lo; 357 __le16 timestamp_hi; 358 __le32 event_data1; 359 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 360 #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 361 }; 362 363 /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 364 struct hwrm_async_event_cmpl_pf_drvr_unload { 365 __le16 type; 366 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 367 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 368 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 369 __le16 event_id; 370 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 371 __le32 event_data2; 372 u8 opaque_v; 373 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 374 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 375 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 376 u8 timestamp_lo; 377 __le16 timestamp_hi; 378 __le32 event_data1; 379 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 380 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 381 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 382 #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 383 }; 384 385 /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 386 struct hwrm_async_event_cmpl_pf_drvr_load { 387 __le16 type; 388 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 389 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 390 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 391 __le16 event_id; 392 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 393 __le32 event_data2; 394 u8 opaque_v; 395 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 396 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 397 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 398 u8 timestamp_lo; 399 __le16 timestamp_hi; 400 __le32 event_data1; 401 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 402 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 403 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 404 #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 405 }; 406 407 /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 408 struct hwrm_async_event_cmpl_vf_flr { 409 __le16 type; 410 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 411 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 412 #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 413 __le16 event_id; 414 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 415 __le32 event_data2; 416 u8 opaque_v; 417 #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 418 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 419 #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 420 u8 timestamp_lo; 421 __le16 timestamp_hi; 422 __le32 event_data1; 423 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 424 #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 425 }; 426 427 /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 428 struct hwrm_async_event_cmpl_vf_mac_addr_change { 429 __le16 type; 430 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 431 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 432 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 433 __le16 event_id; 434 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 435 __le32 event_data2; 436 u8 opaque_v; 437 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 438 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 439 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 440 u8 timestamp_lo; 441 __le16 timestamp_hi; 442 __le32 event_data1; 443 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 444 #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 445 }; 446 447 /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 448 struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 449 __le16 type; 450 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 451 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 452 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 453 __le16 event_id; 454 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 455 __le32 event_data2; 456 u8 opaque_v; 457 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 458 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 459 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 460 u8 timestamp_lo; 461 __le16 timestamp_hi; 462 __le32 event_data1; 463 #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 464 }; 465 466 /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 467 struct hwrm_async_event_cmpl_vf_cfg_change { 468 __le16 type; 469 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 470 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 471 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 472 __le16 event_id; 473 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 474 __le32 event_data2; 475 u8 opaque_v; 476 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 477 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 478 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 479 u8 timestamp_lo; 480 __le16 timestamp_hi; 481 __le32 event_data1; 482 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 483 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 484 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 485 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 486 }; 487 488 /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 489 struct hwrm_async_event_cmpl_hwrm_error { 490 __le16 type; 491 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 492 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 493 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 494 __le16 event_id; 495 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 496 __le32 event_data2; 497 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 498 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 499 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 500 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 501 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 502 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 503 u8 opaque_v; 504 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 505 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 506 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 507 u8 timestamp_lo; 508 __le16 timestamp_hi; 509 __le32 event_data1; 510 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 511 }; 512 513 /* hwrm_ver_get */ 514 /* Input (24 bytes) */ 515 struct hwrm_ver_get_input { 516 __le16 req_type; 517 __le16 cmpl_ring; 518 __le16 seq_id; 519 __le16 target_id; 520 __le64 resp_addr; 521 u8 hwrm_intf_maj; 522 u8 hwrm_intf_min; 523 u8 hwrm_intf_upd; 524 u8 unused_0[5]; 525 }; 526 527 /* Output (128 bytes) */ 528 struct hwrm_ver_get_output { 529 __le16 error_code; 530 __le16 req_type; 531 __le16 seq_id; 532 __le16 resp_len; 533 u8 hwrm_intf_maj; 534 u8 hwrm_intf_min; 535 u8 hwrm_intf_upd; 536 u8 hwrm_intf_rsvd; 537 u8 hwrm_fw_maj; 538 u8 hwrm_fw_min; 539 u8 hwrm_fw_bld; 540 u8 hwrm_fw_rsvd; 541 u8 mgmt_fw_maj; 542 u8 mgmt_fw_min; 543 u8 mgmt_fw_bld; 544 u8 mgmt_fw_rsvd; 545 u8 netctrl_fw_maj; 546 u8 netctrl_fw_min; 547 u8 netctrl_fw_bld; 548 u8 netctrl_fw_rsvd; 549 __le32 dev_caps_cfg; 550 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 551 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 552 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 553 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 554 u8 roce_fw_maj; 555 u8 roce_fw_min; 556 u8 roce_fw_bld; 557 u8 roce_fw_rsvd; 558 char hwrm_fw_name[16]; 559 char mgmt_fw_name[16]; 560 char netctrl_fw_name[16]; 561 __le32 reserved2[4]; 562 char roce_fw_name[16]; 563 __le16 chip_num; 564 u8 chip_rev; 565 u8 chip_metal; 566 u8 chip_bond_id; 567 u8 chip_platform_type; 568 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 569 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 570 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 571 __le16 max_req_win_len; 572 __le16 max_resp_len; 573 __le16 def_req_timeout; 574 u8 unused_0; 575 u8 unused_1; 576 u8 unused_2; 577 u8 valid; 578 }; 579 580 /* hwrm_func_reset */ 581 /* Input (24 bytes) */ 582 struct hwrm_func_reset_input { 583 __le16 req_type; 584 __le16 cmpl_ring; 585 __le16 seq_id; 586 __le16 target_id; 587 __le64 resp_addr; 588 __le32 enables; 589 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 590 __le16 vf_id; 591 u8 func_reset_level; 592 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 593 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 594 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 595 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 596 u8 unused_0; 597 }; 598 599 /* Output (16 bytes) */ 600 struct hwrm_func_reset_output { 601 __le16 error_code; 602 __le16 req_type; 603 __le16 seq_id; 604 __le16 resp_len; 605 __le32 unused_0; 606 u8 unused_1; 607 u8 unused_2; 608 u8 unused_3; 609 u8 valid; 610 }; 611 612 /* hwrm_func_getfid */ 613 /* Input (24 bytes) */ 614 struct hwrm_func_getfid_input { 615 __le16 req_type; 616 __le16 cmpl_ring; 617 __le16 seq_id; 618 __le16 target_id; 619 __le64 resp_addr; 620 __le32 enables; 621 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 622 __le16 pci_id; 623 __le16 unused_0; 624 }; 625 626 /* Output (16 bytes) */ 627 struct hwrm_func_getfid_output { 628 __le16 error_code; 629 __le16 req_type; 630 __le16 seq_id; 631 __le16 resp_len; 632 __le16 fid; 633 u8 unused_0; 634 u8 unused_1; 635 u8 unused_2; 636 u8 unused_3; 637 u8 unused_4; 638 u8 valid; 639 }; 640 641 /* hwrm_func_vf_alloc */ 642 /* Input (24 bytes) */ 643 struct hwrm_func_vf_alloc_input { 644 __le16 req_type; 645 __le16 cmpl_ring; 646 __le16 seq_id; 647 __le16 target_id; 648 __le64 resp_addr; 649 __le32 enables; 650 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 651 __le16 first_vf_id; 652 __le16 num_vfs; 653 }; 654 655 /* Output (16 bytes) */ 656 struct hwrm_func_vf_alloc_output { 657 __le16 error_code; 658 __le16 req_type; 659 __le16 seq_id; 660 __le16 resp_len; 661 __le16 first_vf_id; 662 u8 unused_0; 663 u8 unused_1; 664 u8 unused_2; 665 u8 unused_3; 666 u8 unused_4; 667 u8 valid; 668 }; 669 670 /* hwrm_func_vf_free */ 671 /* Input (24 bytes) */ 672 struct hwrm_func_vf_free_input { 673 __le16 req_type; 674 __le16 cmpl_ring; 675 __le16 seq_id; 676 __le16 target_id; 677 __le64 resp_addr; 678 __le32 enables; 679 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 680 __le16 first_vf_id; 681 __le16 num_vfs; 682 }; 683 684 /* Output (16 bytes) */ 685 struct hwrm_func_vf_free_output { 686 __le16 error_code; 687 __le16 req_type; 688 __le16 seq_id; 689 __le16 resp_len; 690 __le32 unused_0; 691 u8 unused_1; 692 u8 unused_2; 693 u8 unused_3; 694 u8 valid; 695 }; 696 697 /* hwrm_func_vf_cfg */ 698 /* Input (32 bytes) */ 699 struct hwrm_func_vf_cfg_input { 700 __le16 req_type; 701 __le16 cmpl_ring; 702 __le16 seq_id; 703 __le16 target_id; 704 __le64 resp_addr; 705 __le32 enables; 706 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 707 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 708 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 709 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 710 __le16 mtu; 711 __le16 guest_vlan; 712 __le16 async_event_cr; 713 u8 dflt_mac_addr[6]; 714 }; 715 716 /* Output (16 bytes) */ 717 struct hwrm_func_vf_cfg_output { 718 __le16 error_code; 719 __le16 req_type; 720 __le16 seq_id; 721 __le16 resp_len; 722 __le32 unused_0; 723 u8 unused_1; 724 u8 unused_2; 725 u8 unused_3; 726 u8 valid; 727 }; 728 729 /* hwrm_func_qcaps */ 730 /* Input (24 bytes) */ 731 struct hwrm_func_qcaps_input { 732 __le16 req_type; 733 __le16 cmpl_ring; 734 __le16 seq_id; 735 __le16 target_id; 736 __le64 resp_addr; 737 __le16 fid; 738 __le16 unused_0[3]; 739 }; 740 741 /* Output (80 bytes) */ 742 struct hwrm_func_qcaps_output { 743 __le16 error_code; 744 __le16 req_type; 745 __le16 seq_id; 746 __le16 resp_len; 747 __le16 fid; 748 __le16 port_id; 749 __le32 flags; 750 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 751 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 752 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 753 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 754 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 755 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 756 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 757 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 758 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 759 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 760 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 761 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 762 u8 mac_address[6]; 763 __le16 max_rsscos_ctx; 764 __le16 max_cmpl_rings; 765 __le16 max_tx_rings; 766 __le16 max_rx_rings; 767 __le16 max_l2_ctxs; 768 __le16 max_vnics; 769 __le16 first_vf_id; 770 __le16 max_vfs; 771 __le16 max_stat_ctx; 772 __le32 max_encap_records; 773 __le32 max_decap_records; 774 __le32 max_tx_em_flows; 775 __le32 max_tx_wm_flows; 776 __le32 max_rx_em_flows; 777 __le32 max_rx_wm_flows; 778 __le32 max_mcast_filters; 779 __le32 max_flow_id; 780 __le32 max_hw_ring_grps; 781 __le16 max_sp_tx_rings; 782 u8 unused_0; 783 u8 valid; 784 }; 785 786 /* hwrm_func_qcfg */ 787 /* Input (24 bytes) */ 788 struct hwrm_func_qcfg_input { 789 __le16 req_type; 790 __le16 cmpl_ring; 791 __le16 seq_id; 792 __le16 target_id; 793 __le64 resp_addr; 794 __le16 fid; 795 __le16 unused_0[3]; 796 }; 797 798 /* Output (72 bytes) */ 799 struct hwrm_func_qcfg_output { 800 __le16 error_code; 801 __le16 req_type; 802 __le16 seq_id; 803 __le16 resp_len; 804 __le16 fid; 805 __le16 port_id; 806 __le16 vlan; 807 __le16 flags; 808 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 809 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 810 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 811 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 812 u8 mac_address[6]; 813 __le16 pci_id; 814 __le16 alloc_rsscos_ctx; 815 __le16 alloc_cmpl_rings; 816 __le16 alloc_tx_rings; 817 __le16 alloc_rx_rings; 818 __le16 alloc_l2_ctx; 819 __le16 alloc_vnics; 820 __le16 mtu; 821 __le16 mru; 822 __le16 stat_ctx_id; 823 u8 port_partition_type; 824 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 825 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 826 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 827 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 828 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 829 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 830 u8 unused_0; 831 __le16 dflt_vnic_id; 832 u8 unused_1; 833 u8 unused_2; 834 __le32 min_bw; 835 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 836 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 837 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 838 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 839 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 840 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 841 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 842 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 843 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 844 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 845 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 846 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 847 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 848 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 849 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 850 __le32 max_bw; 851 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 852 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 853 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 854 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 855 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 856 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 857 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 858 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 859 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 860 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 861 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 862 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 863 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 864 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 865 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 866 u8 evb_mode; 867 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 868 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 869 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 870 u8 unused_3; 871 __le16 alloc_vfs; 872 __le32 alloc_mcast_filters; 873 __le32 alloc_hw_ring_grps; 874 __le16 alloc_sp_tx_rings; 875 u8 unused_4; 876 u8 valid; 877 }; 878 879 /* hwrm_func_cfg */ 880 /* Input (88 bytes) */ 881 struct hwrm_func_cfg_input { 882 __le16 req_type; 883 __le16 cmpl_ring; 884 __le16 seq_id; 885 __le16 target_id; 886 __le64 resp_addr; 887 __le16 fid; 888 u8 unused_0; 889 u8 unused_1; 890 __le32 flags; 891 #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 892 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 893 #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 894 #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 895 #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 896 #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 897 #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 898 #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 899 #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 900 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE 0x200UL 901 __le32 enables; 902 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 903 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 904 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 905 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 906 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 907 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 908 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 909 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 910 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 911 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 912 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 913 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 914 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 915 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 916 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 917 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 918 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 919 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 920 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 921 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 922 __le16 mtu; 923 __le16 mru; 924 __le16 num_rsscos_ctxs; 925 __le16 num_cmpl_rings; 926 __le16 num_tx_rings; 927 __le16 num_rx_rings; 928 __le16 num_l2_ctxs; 929 __le16 num_vnics; 930 __le16 num_stat_ctxs; 931 __le16 num_hw_ring_grps; 932 u8 dflt_mac_addr[6]; 933 __le16 dflt_vlan; 934 __be32 dflt_ip_addr[4]; 935 __le32 min_bw; 936 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 937 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 938 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 939 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 940 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 941 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 942 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 943 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 944 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 945 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 946 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 947 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 948 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 949 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 950 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 951 __le32 max_bw; 952 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 953 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 954 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 955 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 956 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 957 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 958 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 959 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 960 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 961 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 962 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 963 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 964 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 965 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 966 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 967 __le16 async_event_cr; 968 u8 vlan_antispoof_mode; 969 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 970 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 971 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 972 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 973 u8 allowed_vlan_pris; 974 u8 evb_mode; 975 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 976 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 977 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 978 u8 unused_2; 979 __le16 num_mcast_filters; 980 }; 981 982 /* Output (16 bytes) */ 983 struct hwrm_func_cfg_output { 984 __le16 error_code; 985 __le16 req_type; 986 __le16 seq_id; 987 __le16 resp_len; 988 __le32 unused_0; 989 u8 unused_1; 990 u8 unused_2; 991 u8 unused_3; 992 u8 valid; 993 }; 994 995 /* hwrm_func_qstats */ 996 /* Input (24 bytes) */ 997 struct hwrm_func_qstats_input { 998 __le16 req_type; 999 __le16 cmpl_ring; 1000 __le16 seq_id; 1001 __le16 target_id; 1002 __le64 resp_addr; 1003 __le16 fid; 1004 __le16 unused_0[3]; 1005 }; 1006 1007 /* Output (176 bytes) */ 1008 struct hwrm_func_qstats_output { 1009 __le16 error_code; 1010 __le16 req_type; 1011 __le16 seq_id; 1012 __le16 resp_len; 1013 __le64 tx_ucast_pkts; 1014 __le64 tx_mcast_pkts; 1015 __le64 tx_bcast_pkts; 1016 __le64 tx_err_pkts; 1017 __le64 tx_drop_pkts; 1018 __le64 tx_ucast_bytes; 1019 __le64 tx_mcast_bytes; 1020 __le64 tx_bcast_bytes; 1021 __le64 rx_ucast_pkts; 1022 __le64 rx_mcast_pkts; 1023 __le64 rx_bcast_pkts; 1024 __le64 rx_err_pkts; 1025 __le64 rx_drop_pkts; 1026 __le64 rx_ucast_bytes; 1027 __le64 rx_mcast_bytes; 1028 __le64 rx_bcast_bytes; 1029 __le64 rx_agg_pkts; 1030 __le64 rx_agg_bytes; 1031 __le64 rx_agg_events; 1032 __le64 rx_agg_aborts; 1033 __le32 unused_0; 1034 u8 unused_1; 1035 u8 unused_2; 1036 u8 unused_3; 1037 u8 valid; 1038 }; 1039 1040 /* hwrm_func_clr_stats */ 1041 /* Input (24 bytes) */ 1042 struct hwrm_func_clr_stats_input { 1043 __le16 req_type; 1044 __le16 cmpl_ring; 1045 __le16 seq_id; 1046 __le16 target_id; 1047 __le64 resp_addr; 1048 __le16 fid; 1049 __le16 unused_0[3]; 1050 }; 1051 1052 /* Output (16 bytes) */ 1053 struct hwrm_func_clr_stats_output { 1054 __le16 error_code; 1055 __le16 req_type; 1056 __le16 seq_id; 1057 __le16 resp_len; 1058 __le32 unused_0; 1059 u8 unused_1; 1060 u8 unused_2; 1061 u8 unused_3; 1062 u8 valid; 1063 }; 1064 1065 /* hwrm_func_vf_resc_free */ 1066 /* Input (24 bytes) */ 1067 struct hwrm_func_vf_resc_free_input { 1068 __le16 req_type; 1069 __le16 cmpl_ring; 1070 __le16 seq_id; 1071 __le16 target_id; 1072 __le64 resp_addr; 1073 __le16 vf_id; 1074 __le16 unused_0[3]; 1075 }; 1076 1077 /* Output (16 bytes) */ 1078 struct hwrm_func_vf_resc_free_output { 1079 __le16 error_code; 1080 __le16 req_type; 1081 __le16 seq_id; 1082 __le16 resp_len; 1083 __le32 unused_0; 1084 u8 unused_1; 1085 u8 unused_2; 1086 u8 unused_3; 1087 u8 valid; 1088 }; 1089 1090 /* hwrm_func_vf_vnic_ids_query */ 1091 /* Input (32 bytes) */ 1092 struct hwrm_func_vf_vnic_ids_query_input { 1093 __le16 req_type; 1094 __le16 cmpl_ring; 1095 __le16 seq_id; 1096 __le16 target_id; 1097 __le64 resp_addr; 1098 __le16 vf_id; 1099 u8 unused_0; 1100 u8 unused_1; 1101 __le32 max_vnic_id_cnt; 1102 __le64 vnic_id_tbl_addr; 1103 }; 1104 1105 /* Output (16 bytes) */ 1106 struct hwrm_func_vf_vnic_ids_query_output { 1107 __le16 error_code; 1108 __le16 req_type; 1109 __le16 seq_id; 1110 __le16 resp_len; 1111 __le32 vnic_id_cnt; 1112 u8 unused_0; 1113 u8 unused_1; 1114 u8 unused_2; 1115 u8 valid; 1116 }; 1117 1118 /* hwrm_func_drv_rgtr */ 1119 /* Input (80 bytes) */ 1120 struct hwrm_func_drv_rgtr_input { 1121 __le16 req_type; 1122 __le16 cmpl_ring; 1123 __le16 seq_id; 1124 __le16 target_id; 1125 __le64 resp_addr; 1126 __le32 flags; 1127 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1128 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1129 __le32 enables; 1130 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1131 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1132 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1133 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1134 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1135 __le16 os_type; 1136 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1137 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1138 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1139 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1140 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1141 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1142 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1143 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1144 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1145 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1146 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1147 u8 ver_maj; 1148 u8 ver_min; 1149 u8 ver_upd; 1150 u8 unused_0; 1151 __le16 unused_1; 1152 __le32 timestamp; 1153 __le32 unused_2; 1154 __le32 vf_req_fwd[8]; 1155 __le32 async_event_fwd[8]; 1156 }; 1157 1158 /* Output (16 bytes) */ 1159 struct hwrm_func_drv_rgtr_output { 1160 __le16 error_code; 1161 __le16 req_type; 1162 __le16 seq_id; 1163 __le16 resp_len; 1164 __le32 unused_0; 1165 u8 unused_1; 1166 u8 unused_2; 1167 u8 unused_3; 1168 u8 valid; 1169 }; 1170 1171 /* hwrm_func_drv_unrgtr */ 1172 /* Input (24 bytes) */ 1173 struct hwrm_func_drv_unrgtr_input { 1174 __le16 req_type; 1175 __le16 cmpl_ring; 1176 __le16 seq_id; 1177 __le16 target_id; 1178 __le64 resp_addr; 1179 __le32 flags; 1180 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1181 __le32 unused_0; 1182 }; 1183 1184 /* Output (16 bytes) */ 1185 struct hwrm_func_drv_unrgtr_output { 1186 __le16 error_code; 1187 __le16 req_type; 1188 __le16 seq_id; 1189 __le16 resp_len; 1190 __le32 unused_0; 1191 u8 unused_1; 1192 u8 unused_2; 1193 u8 unused_3; 1194 u8 valid; 1195 }; 1196 1197 /* hwrm_func_buf_rgtr */ 1198 /* Input (128 bytes) */ 1199 struct hwrm_func_buf_rgtr_input { 1200 __le16 req_type; 1201 __le16 cmpl_ring; 1202 __le16 seq_id; 1203 __le16 target_id; 1204 __le64 resp_addr; 1205 __le32 enables; 1206 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1207 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1208 __le16 vf_id; 1209 __le16 req_buf_num_pages; 1210 __le16 req_buf_page_size; 1211 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1212 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1213 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1214 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1215 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1216 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1217 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1218 __le16 req_buf_len; 1219 __le16 resp_buf_len; 1220 u8 unused_0; 1221 u8 unused_1; 1222 __le64 req_buf_page_addr0; 1223 __le64 req_buf_page_addr1; 1224 __le64 req_buf_page_addr2; 1225 __le64 req_buf_page_addr3; 1226 __le64 req_buf_page_addr4; 1227 __le64 req_buf_page_addr5; 1228 __le64 req_buf_page_addr6; 1229 __le64 req_buf_page_addr7; 1230 __le64 req_buf_page_addr8; 1231 __le64 req_buf_page_addr9; 1232 __le64 error_buf_addr; 1233 __le64 resp_buf_addr; 1234 }; 1235 1236 /* Output (16 bytes) */ 1237 struct hwrm_func_buf_rgtr_output { 1238 __le16 error_code; 1239 __le16 req_type; 1240 __le16 seq_id; 1241 __le16 resp_len; 1242 __le32 unused_0; 1243 u8 unused_1; 1244 u8 unused_2; 1245 u8 unused_3; 1246 u8 valid; 1247 }; 1248 1249 /* hwrm_func_drv_qver */ 1250 /* Input (24 bytes) */ 1251 struct hwrm_func_drv_qver_input { 1252 __le16 req_type; 1253 __le16 cmpl_ring; 1254 __le16 seq_id; 1255 __le16 target_id; 1256 __le64 resp_addr; 1257 __le32 reserved; 1258 __le16 fid; 1259 __le16 unused_0; 1260 }; 1261 1262 /* Output (16 bytes) */ 1263 struct hwrm_func_drv_qver_output { 1264 __le16 error_code; 1265 __le16 req_type; 1266 __le16 seq_id; 1267 __le16 resp_len; 1268 __le16 os_type; 1269 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1270 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1271 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1272 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1273 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1274 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1275 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1276 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1277 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1278 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1279 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1280 u8 ver_maj; 1281 u8 ver_min; 1282 u8 ver_upd; 1283 u8 unused_0; 1284 u8 unused_1; 1285 u8 valid; 1286 }; 1287 1288 /* hwrm_port_phy_cfg */ 1289 /* Input (56 bytes) */ 1290 struct hwrm_port_phy_cfg_input { 1291 __le16 req_type; 1292 __le16 cmpl_ring; 1293 __le16 seq_id; 1294 __le16 target_id; 1295 __le64 resp_addr; 1296 __le32 flags; 1297 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1298 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1299 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1300 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1301 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1302 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1303 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1304 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1305 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1306 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1307 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1308 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1309 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1310 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1311 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1312 __le32 enables; 1313 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1314 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1315 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1316 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1317 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1318 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1319 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1320 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1321 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1322 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1323 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1324 __le16 port_id; 1325 __le16 force_link_speed; 1326 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1327 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1328 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1329 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1330 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1331 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1332 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1333 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1334 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1335 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1336 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1337 u8 auto_mode; 1338 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1339 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1340 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1341 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1342 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1343 u8 auto_duplex; 1344 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1345 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1346 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1347 u8 auto_pause; 1348 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1349 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1350 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1351 u8 unused_0; 1352 __le16 auto_link_speed; 1353 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1354 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1355 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1356 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1357 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1358 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1359 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1360 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1361 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1362 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1363 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1364 __le16 auto_link_speed_mask; 1365 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1366 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1367 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1368 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1371 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1372 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1373 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1374 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1375 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1376 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1377 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1378 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1379 u8 wirespeed; 1380 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1381 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1382 u8 lpbk; 1383 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1384 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1385 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1386 u8 force_pause; 1387 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1388 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1389 u8 unused_1; 1390 __le32 preemphasis; 1391 __le16 eee_link_speed_mask; 1392 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1393 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1394 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1395 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1396 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1397 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1398 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1399 u8 unused_2; 1400 u8 unused_3; 1401 __le32 tx_lpi_timer; 1402 __le32 unused_4; 1403 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1404 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1405 }; 1406 1407 /* Output (16 bytes) */ 1408 struct hwrm_port_phy_cfg_output { 1409 __le16 error_code; 1410 __le16 req_type; 1411 __le16 seq_id; 1412 __le16 resp_len; 1413 __le32 unused_0; 1414 u8 unused_1; 1415 u8 unused_2; 1416 u8 unused_3; 1417 u8 valid; 1418 }; 1419 1420 /* hwrm_port_phy_qcfg */ 1421 /* Input (24 bytes) */ 1422 struct hwrm_port_phy_qcfg_input { 1423 __le16 req_type; 1424 __le16 cmpl_ring; 1425 __le16 seq_id; 1426 __le16 target_id; 1427 __le64 resp_addr; 1428 __le16 port_id; 1429 __le16 unused_0[3]; 1430 }; 1431 1432 /* Output (96 bytes) */ 1433 struct hwrm_port_phy_qcfg_output { 1434 __le16 error_code; 1435 __le16 req_type; 1436 __le16 seq_id; 1437 __le16 resp_len; 1438 u8 link; 1439 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1440 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1441 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1442 u8 unused_0; 1443 __le16 link_speed; 1444 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1445 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1446 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1447 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1448 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1449 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1450 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1451 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1452 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1453 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1454 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1455 u8 duplex; 1456 #define PORT_PHY_QCFG_RESP_DUPLEX_HALF 0x0UL 1457 #define PORT_PHY_QCFG_RESP_DUPLEX_FULL 0x1UL 1458 u8 pause; 1459 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1460 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1461 __le16 support_speeds; 1462 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1463 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1464 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1465 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1466 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1467 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1468 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1469 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1470 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1471 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1472 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1473 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1474 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1475 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1476 __le16 force_link_speed; 1477 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1478 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1479 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1480 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1481 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1482 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1483 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1484 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1485 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1486 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1487 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1488 u8 auto_mode; 1489 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1490 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1491 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1492 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1493 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1494 u8 auto_pause; 1495 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1496 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1497 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1498 __le16 auto_link_speed; 1499 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1500 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1501 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1502 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1503 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1504 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1505 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1506 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1507 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1508 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1509 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1510 __le16 auto_link_speed_mask; 1511 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1512 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1513 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1514 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1515 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1516 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1517 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1518 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1519 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1520 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1521 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1522 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1523 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1524 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1525 u8 wirespeed; 1526 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1527 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1528 u8 lpbk; 1529 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1530 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1531 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1532 u8 force_pause; 1533 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1534 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1535 u8 module_status; 1536 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1537 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1538 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1539 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1540 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1541 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1542 __le32 preemphasis; 1543 u8 phy_maj; 1544 u8 phy_min; 1545 u8 phy_bld; 1546 u8 phy_type; 1547 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1548 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1549 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1550 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1551 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1552 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1553 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1554 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1555 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1556 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1557 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1558 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1559 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1560 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1561 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1562 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1563 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1564 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1565 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1566 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1567 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1568 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1569 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1570 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1571 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1572 u8 media_type; 1573 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1574 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1575 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1576 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1577 u8 xcvr_pkg_type; 1578 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1579 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1580 u8 eee_config_phy_addr; 1581 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1582 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1583 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1584 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1585 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1586 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1587 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1588 u8 parallel_detect; 1589 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1590 #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 1591 #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1592 __le16 link_partner_adv_speeds; 1593 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1594 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1595 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1596 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1597 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1598 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1599 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1600 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1601 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1602 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1603 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1604 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1605 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1606 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1607 u8 link_partner_adv_auto_mode; 1608 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1609 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1610 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1611 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1612 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1613 u8 link_partner_adv_pause; 1614 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1615 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1616 __le16 adv_eee_link_speed_mask; 1617 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1618 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1619 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1620 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1621 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1622 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1623 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1624 __le16 link_partner_adv_eee_link_speed_mask; 1625 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1626 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1627 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1628 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1629 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1630 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1631 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1632 __le32 xcvr_identifier_type_tx_lpi_timer; 1633 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1634 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1635 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1636 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1637 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1638 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1639 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1640 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1641 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1642 __le16 fec_cfg; 1643 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1644 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1645 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1646 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1647 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1648 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1649 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1650 u8 unused_1; 1651 u8 unused_2; 1652 char phy_vendor_name[16]; 1653 char phy_vendor_partnumber[16]; 1654 __le32 unused_3; 1655 u8 unused_4; 1656 u8 unused_5; 1657 u8 unused_6; 1658 u8 valid; 1659 }; 1660 1661 /* hwrm_port_mac_cfg */ 1662 /* Input (40 bytes) */ 1663 struct hwrm_port_mac_cfg_input { 1664 __le16 req_type; 1665 __le16 cmpl_ring; 1666 __le16 seq_id; 1667 __le16 target_id; 1668 __le64 resp_addr; 1669 __le32 flags; 1670 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1671 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1672 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1673 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1674 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1675 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1676 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1677 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1678 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1679 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1680 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1681 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1682 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1683 __le32 enables; 1684 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1685 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1686 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1687 #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1688 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1689 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1690 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1691 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1692 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1693 __le16 port_id; 1694 u8 ipg; 1695 u8 lpbk; 1696 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1697 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1698 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1699 u8 vlan_pri2cos_map_pri; 1700 u8 reserved1; 1701 u8 tunnel_pri2cos_map_pri; 1702 u8 dscp2pri_map_pri; 1703 __le16 rx_ts_capture_ptp_msg_type; 1704 __le16 tx_ts_capture_ptp_msg_type; 1705 u8 cos_field_cfg; 1706 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1707 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1708 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1709 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1710 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1711 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1712 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1713 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1714 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1715 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1716 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1717 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1718 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1719 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1720 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1721 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1722 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1723 u8 unused_0[3]; 1724 }; 1725 1726 /* Output (16 bytes) */ 1727 struct hwrm_port_mac_cfg_output { 1728 __le16 error_code; 1729 __le16 req_type; 1730 __le16 seq_id; 1731 __le16 resp_len; 1732 __le16 mru; 1733 __le16 mtu; 1734 u8 ipg; 1735 u8 lpbk; 1736 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1737 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1738 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1739 u8 unused_0; 1740 u8 valid; 1741 }; 1742 1743 /* hwrm_port_qstats */ 1744 /* Input (40 bytes) */ 1745 struct hwrm_port_qstats_input { 1746 __le16 req_type; 1747 __le16 cmpl_ring; 1748 __le16 seq_id; 1749 __le16 target_id; 1750 __le64 resp_addr; 1751 __le16 port_id; 1752 u8 unused_0; 1753 u8 unused_1; 1754 u8 unused_2[3]; 1755 u8 unused_3; 1756 __le64 tx_stat_host_addr; 1757 __le64 rx_stat_host_addr; 1758 }; 1759 1760 /* Output (16 bytes) */ 1761 struct hwrm_port_qstats_output { 1762 __le16 error_code; 1763 __le16 req_type; 1764 __le16 seq_id; 1765 __le16 resp_len; 1766 __le16 tx_stat_size; 1767 __le16 rx_stat_size; 1768 u8 unused_0; 1769 u8 unused_1; 1770 u8 unused_2; 1771 u8 valid; 1772 }; 1773 1774 /* hwrm_port_lpbk_qstats */ 1775 /* Input (16 bytes) */ 1776 struct hwrm_port_lpbk_qstats_input { 1777 __le16 req_type; 1778 __le16 cmpl_ring; 1779 __le16 seq_id; 1780 __le16 target_id; 1781 __le64 resp_addr; 1782 }; 1783 1784 /* Output (96 bytes) */ 1785 struct hwrm_port_lpbk_qstats_output { 1786 __le16 error_code; 1787 __le16 req_type; 1788 __le16 seq_id; 1789 __le16 resp_len; 1790 __le64 lpbk_ucast_frames; 1791 __le64 lpbk_mcast_frames; 1792 __le64 lpbk_bcast_frames; 1793 __le64 lpbk_ucast_bytes; 1794 __le64 lpbk_mcast_bytes; 1795 __le64 lpbk_bcast_bytes; 1796 __le64 tx_stat_discard; 1797 __le64 tx_stat_error; 1798 __le64 rx_stat_discard; 1799 __le64 rx_stat_error; 1800 __le32 unused_0; 1801 u8 unused_1; 1802 u8 unused_2; 1803 u8 unused_3; 1804 u8 valid; 1805 }; 1806 1807 /* hwrm_port_clr_stats */ 1808 /* Input (24 bytes) */ 1809 struct hwrm_port_clr_stats_input { 1810 __le16 req_type; 1811 __le16 cmpl_ring; 1812 __le16 seq_id; 1813 __le16 target_id; 1814 __le64 resp_addr; 1815 __le16 port_id; 1816 __le16 unused_0[3]; 1817 }; 1818 1819 /* Output (16 bytes) */ 1820 struct hwrm_port_clr_stats_output { 1821 __le16 error_code; 1822 __le16 req_type; 1823 __le16 seq_id; 1824 __le16 resp_len; 1825 __le32 unused_0; 1826 u8 unused_1; 1827 u8 unused_2; 1828 u8 unused_3; 1829 u8 valid; 1830 }; 1831 1832 /* hwrm_port_lpbk_clr_stats */ 1833 /* Input (16 bytes) */ 1834 struct hwrm_port_lpbk_clr_stats_input { 1835 __le16 req_type; 1836 __le16 cmpl_ring; 1837 __le16 seq_id; 1838 __le16 target_id; 1839 __le64 resp_addr; 1840 }; 1841 1842 /* Output (16 bytes) */ 1843 struct hwrm_port_lpbk_clr_stats_output { 1844 __le16 error_code; 1845 __le16 req_type; 1846 __le16 seq_id; 1847 __le16 resp_len; 1848 __le32 unused_0; 1849 u8 unused_1; 1850 u8 unused_2; 1851 u8 unused_3; 1852 u8 valid; 1853 }; 1854 1855 /* hwrm_port_phy_qcaps */ 1856 /* Input (24 bytes) */ 1857 struct hwrm_port_phy_qcaps_input { 1858 __le16 req_type; 1859 __le16 cmpl_ring; 1860 __le16 seq_id; 1861 __le16 target_id; 1862 __le64 resp_addr; 1863 __le16 port_id; 1864 __le16 unused_0[3]; 1865 }; 1866 1867 /* Output (24 bytes) */ 1868 struct hwrm_port_phy_qcaps_output { 1869 __le16 error_code; 1870 __le16 req_type; 1871 __le16 seq_id; 1872 __le16 resp_len; 1873 u8 eee_supported; 1874 #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 1875 #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 1876 #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 1877 u8 unused_0; 1878 __le16 supported_speeds_force_mode; 1879 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 1880 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 1881 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 1882 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 1883 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 1884 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 1885 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 1886 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 1887 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 1888 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 1889 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 1890 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 1891 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 1892 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 1893 __le16 supported_speeds_auto_mode; 1894 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 1895 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 1896 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 1897 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 1898 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 1899 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 1900 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 1901 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 1902 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 1903 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 1904 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 1905 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 1906 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 1907 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 1908 __le16 supported_speeds_eee_mode; 1909 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 1910 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 1911 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 1912 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 1913 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 1914 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 1915 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 1916 __le32 tx_lpi_timer_low; 1917 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 1918 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 1919 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 1920 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 1921 __le32 valid_tx_lpi_timer_high; 1922 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 1923 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 1924 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 1925 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 1926 }; 1927 1928 /* hwrm_port_phy_i2c_read */ 1929 /* Input (40 bytes) */ 1930 struct hwrm_port_phy_i2c_read_input { 1931 __le16 req_type; 1932 __le16 cmpl_ring; 1933 __le16 seq_id; 1934 __le16 target_id; 1935 __le64 resp_addr; 1936 __le32 flags; 1937 __le32 enables; 1938 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 1939 __le16 port_id; 1940 u8 i2c_slave_addr; 1941 u8 unused_0; 1942 __le16 page_number; 1943 __le16 page_offset; 1944 u8 data_length; 1945 u8 unused_1[7]; 1946 }; 1947 1948 /* Output (80 bytes) */ 1949 struct hwrm_port_phy_i2c_read_output { 1950 __le16 error_code; 1951 __le16 req_type; 1952 __le16 seq_id; 1953 __le16 resp_len; 1954 __le32 data[16]; 1955 __le32 unused_0; 1956 u8 unused_1; 1957 u8 unused_2; 1958 u8 unused_3; 1959 u8 valid; 1960 }; 1961 1962 /* hwrm_port_led_cfg */ 1963 /* Input (64 bytes) */ 1964 struct hwrm_port_led_cfg_input { 1965 __le16 req_type; 1966 __le16 cmpl_ring; 1967 __le16 seq_id; 1968 __le16 target_id; 1969 __le64 resp_addr; 1970 __le32 enables; 1971 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 1972 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 1973 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 1974 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 1975 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 1976 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 1977 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 1978 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 1979 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 1980 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 1981 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 1982 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 1983 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 1984 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 1985 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 1986 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 1987 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 1988 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 1989 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 1990 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 1991 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 1992 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 1993 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 1994 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 1995 __le16 port_id; 1996 u8 num_leds; 1997 u8 rsvd; 1998 u8 led0_id; 1999 u8 led0_state; 2000 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2001 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2002 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2003 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2004 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2005 u8 led0_color; 2006 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2007 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2008 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2009 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2010 u8 unused_0; 2011 __le16 led0_blink_on; 2012 __le16 led0_blink_off; 2013 u8 led0_group_id; 2014 u8 rsvd0; 2015 u8 led1_id; 2016 u8 led1_state; 2017 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2018 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2019 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2020 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2021 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2022 u8 led1_color; 2023 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2024 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2025 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2026 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2027 u8 unused_1; 2028 __le16 led1_blink_on; 2029 __le16 led1_blink_off; 2030 u8 led1_group_id; 2031 u8 rsvd1; 2032 u8 led2_id; 2033 u8 led2_state; 2034 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2035 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2036 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2037 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2038 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2039 u8 led2_color; 2040 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2041 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2042 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2043 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2044 u8 unused_2; 2045 __le16 led2_blink_on; 2046 __le16 led2_blink_off; 2047 u8 led2_group_id; 2048 u8 rsvd2; 2049 u8 led3_id; 2050 u8 led3_state; 2051 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2052 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2053 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2054 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2055 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2056 u8 led3_color; 2057 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2058 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2059 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2060 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2061 u8 unused_3; 2062 __le16 led3_blink_on; 2063 __le16 led3_blink_off; 2064 u8 led3_group_id; 2065 u8 rsvd3; 2066 }; 2067 2068 /* Output (16 bytes) */ 2069 struct hwrm_port_led_cfg_output { 2070 __le16 error_code; 2071 __le16 req_type; 2072 __le16 seq_id; 2073 __le16 resp_len; 2074 __le32 unused_0; 2075 u8 unused_1; 2076 u8 unused_2; 2077 u8 unused_3; 2078 u8 valid; 2079 }; 2080 2081 /* hwrm_port_led_qcaps */ 2082 /* Input (24 bytes) */ 2083 struct hwrm_port_led_qcaps_input { 2084 __le16 req_type; 2085 __le16 cmpl_ring; 2086 __le16 seq_id; 2087 __le16 target_id; 2088 __le64 resp_addr; 2089 __le16 port_id; 2090 __le16 unused_0[3]; 2091 }; 2092 2093 /* Output (48 bytes) */ 2094 struct hwrm_port_led_qcaps_output { 2095 __le16 error_code; 2096 __le16 req_type; 2097 __le16 seq_id; 2098 __le16 resp_len; 2099 u8 num_leds; 2100 u8 unused_0[3]; 2101 u8 led0_id; 2102 u8 led0_type; 2103 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2104 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2105 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2106 u8 led0_group_id; 2107 u8 unused_1; 2108 __le16 led0_state_caps; 2109 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2110 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2111 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2112 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2113 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2114 __le16 led0_color_caps; 2115 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2116 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2117 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2118 u8 led1_id; 2119 u8 led1_type; 2120 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2121 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2122 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2123 u8 led1_group_id; 2124 u8 unused_2; 2125 __le16 led1_state_caps; 2126 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2127 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2128 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2129 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2130 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2131 __le16 led1_color_caps; 2132 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2133 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2134 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2135 u8 led2_id; 2136 u8 led2_type; 2137 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2138 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2139 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2140 u8 led2_group_id; 2141 u8 unused_3; 2142 __le16 led2_state_caps; 2143 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2144 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2145 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2146 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2147 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2148 __le16 led2_color_caps; 2149 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2150 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2151 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2152 u8 led3_id; 2153 u8 led3_type; 2154 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2155 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2156 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2157 u8 led3_group_id; 2158 u8 unused_4; 2159 __le16 led3_state_caps; 2160 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2161 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2162 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2163 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2164 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2165 __le16 led3_color_caps; 2166 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2167 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2168 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2169 u8 unused_5; 2170 u8 unused_6; 2171 u8 unused_7; 2172 u8 valid; 2173 }; 2174 2175 /* hwrm_queue_qportcfg */ 2176 /* Input (24 bytes) */ 2177 struct hwrm_queue_qportcfg_input { 2178 __le16 req_type; 2179 __le16 cmpl_ring; 2180 __le16 seq_id; 2181 __le16 target_id; 2182 __le64 resp_addr; 2183 __le32 flags; 2184 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2185 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2186 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2187 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2188 __le16 port_id; 2189 __le16 unused_0; 2190 }; 2191 2192 /* Output (32 bytes) */ 2193 struct hwrm_queue_qportcfg_output { 2194 __le16 error_code; 2195 __le16 req_type; 2196 __le16 seq_id; 2197 __le16 resp_len; 2198 u8 max_configurable_queues; 2199 u8 max_configurable_lossless_queues; 2200 u8 queue_cfg_allowed; 2201 u8 queue_cfg_info; 2202 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2203 u8 queue_pfcenable_cfg_allowed; 2204 u8 queue_pri2cos_cfg_allowed; 2205 u8 queue_cos2bw_cfg_allowed; 2206 u8 queue_id0; 2207 u8 queue_id0_service_profile; 2208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2209 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2211 u8 queue_id1; 2212 u8 queue_id1_service_profile; 2213 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2214 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2216 u8 queue_id2; 2217 u8 queue_id2_service_profile; 2218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2220 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2221 u8 queue_id3; 2222 u8 queue_id3_service_profile; 2223 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2225 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2226 u8 queue_id4; 2227 u8 queue_id4_service_profile; 2228 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2229 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2230 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2231 u8 queue_id5; 2232 u8 queue_id5_service_profile; 2233 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2234 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2235 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2236 u8 queue_id6; 2237 u8 queue_id6_service_profile; 2238 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2239 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2240 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2241 u8 queue_id7; 2242 u8 queue_id7_service_profile; 2243 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2244 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2245 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2246 u8 valid; 2247 }; 2248 2249 /* hwrm_queue_cfg */ 2250 /* Input (40 bytes) */ 2251 struct hwrm_queue_cfg_input { 2252 __le16 req_type; 2253 __le16 cmpl_ring; 2254 __le16 seq_id; 2255 __le16 target_id; 2256 __le64 resp_addr; 2257 __le32 flags; 2258 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2259 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2260 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2261 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2262 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2263 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2264 __le32 enables; 2265 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2266 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2267 __le32 queue_id; 2268 __le32 dflt_len; 2269 u8 service_profile; 2270 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2271 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2272 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2273 u8 unused_0[7]; 2274 }; 2275 2276 /* Output (16 bytes) */ 2277 struct hwrm_queue_cfg_output { 2278 __le16 error_code; 2279 __le16 req_type; 2280 __le16 seq_id; 2281 __le16 resp_len; 2282 __le32 unused_0; 2283 u8 unused_1; 2284 u8 unused_2; 2285 u8 unused_3; 2286 u8 valid; 2287 }; 2288 2289 /* hwrm_queue_pfcenable_qcfg */ 2290 /* Input (24 bytes) */ 2291 struct hwrm_queue_pfcenable_qcfg_input { 2292 __le16 req_type; 2293 __le16 cmpl_ring; 2294 __le16 seq_id; 2295 __le16 target_id; 2296 __le64 resp_addr; 2297 __le16 port_id; 2298 __le16 unused_0[3]; 2299 }; 2300 2301 /* Output (16 bytes) */ 2302 struct hwrm_queue_pfcenable_qcfg_output { 2303 __le16 error_code; 2304 __le16 req_type; 2305 __le16 seq_id; 2306 __le16 resp_len; 2307 __le32 flags; 2308 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2309 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2310 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2311 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2312 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2313 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2314 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2315 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2316 u8 unused_0; 2317 u8 unused_1; 2318 u8 unused_2; 2319 u8 valid; 2320 }; 2321 2322 /* hwrm_queue_pfcenable_cfg */ 2323 /* Input (24 bytes) */ 2324 struct hwrm_queue_pfcenable_cfg_input { 2325 __le16 req_type; 2326 __le16 cmpl_ring; 2327 __le16 seq_id; 2328 __le16 target_id; 2329 __le64 resp_addr; 2330 __le32 flags; 2331 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2332 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2333 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2334 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2335 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2336 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2337 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2338 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2339 __le16 port_id; 2340 __le16 unused_0; 2341 }; 2342 2343 /* Output (16 bytes) */ 2344 struct hwrm_queue_pfcenable_cfg_output { 2345 __le16 error_code; 2346 __le16 req_type; 2347 __le16 seq_id; 2348 __le16 resp_len; 2349 __le32 unused_0; 2350 u8 unused_1; 2351 u8 unused_2; 2352 u8 unused_3; 2353 u8 valid; 2354 }; 2355 2356 /* hwrm_queue_pri2cos_qcfg */ 2357 /* Input (24 bytes) */ 2358 struct hwrm_queue_pri2cos_qcfg_input { 2359 __le16 req_type; 2360 __le16 cmpl_ring; 2361 __le16 seq_id; 2362 __le16 target_id; 2363 __le64 resp_addr; 2364 __le32 flags; 2365 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2366 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2367 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2368 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2369 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2370 u8 port_id; 2371 u8 unused_0[3]; 2372 }; 2373 2374 /* Output (24 bytes) */ 2375 struct hwrm_queue_pri2cos_qcfg_output { 2376 __le16 error_code; 2377 __le16 req_type; 2378 __le16 seq_id; 2379 __le16 resp_len; 2380 u8 pri0_cos_queue_id; 2381 u8 pri1_cos_queue_id; 2382 u8 pri2_cos_queue_id; 2383 u8 pri3_cos_queue_id; 2384 u8 pri4_cos_queue_id; 2385 u8 pri5_cos_queue_id; 2386 u8 pri6_cos_queue_id; 2387 u8 pri7_cos_queue_id; 2388 u8 queue_cfg_info; 2389 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2390 u8 unused_0; 2391 __le16 unused_1; 2392 u8 unused_2; 2393 u8 unused_3; 2394 u8 unused_4; 2395 u8 valid; 2396 }; 2397 2398 /* hwrm_queue_pri2cos_cfg */ 2399 /* Input (40 bytes) */ 2400 struct hwrm_queue_pri2cos_cfg_input { 2401 __le16 req_type; 2402 __le16 cmpl_ring; 2403 __le16 seq_id; 2404 __le16 target_id; 2405 __le64 resp_addr; 2406 __le32 flags; 2407 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2408 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2409 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2410 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2411 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2412 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2413 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2414 __le32 enables; 2415 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2416 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2417 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2418 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2419 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2420 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2421 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2422 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2423 u8 port_id; 2424 u8 pri0_cos_queue_id; 2425 u8 pri1_cos_queue_id; 2426 u8 pri2_cos_queue_id; 2427 u8 pri3_cos_queue_id; 2428 u8 pri4_cos_queue_id; 2429 u8 pri5_cos_queue_id; 2430 u8 pri6_cos_queue_id; 2431 u8 pri7_cos_queue_id; 2432 u8 unused_0[7]; 2433 }; 2434 2435 /* Output (16 bytes) */ 2436 struct hwrm_queue_pri2cos_cfg_output { 2437 __le16 error_code; 2438 __le16 req_type; 2439 __le16 seq_id; 2440 __le16 resp_len; 2441 __le32 unused_0; 2442 u8 unused_1; 2443 u8 unused_2; 2444 u8 unused_3; 2445 u8 valid; 2446 }; 2447 2448 /* hwrm_queue_cos2bw_qcfg */ 2449 /* Input (24 bytes) */ 2450 struct hwrm_queue_cos2bw_qcfg_input { 2451 __le16 req_type; 2452 __le16 cmpl_ring; 2453 __le16 seq_id; 2454 __le16 target_id; 2455 __le64 resp_addr; 2456 __le16 port_id; 2457 __le16 unused_0[3]; 2458 }; 2459 2460 /* Output (112 bytes) */ 2461 struct hwrm_queue_cos2bw_qcfg_output { 2462 __le16 error_code; 2463 __le16 req_type; 2464 __le16 seq_id; 2465 __le16 resp_len; 2466 u8 queue_id0; 2467 u8 unused_0; 2468 __le16 unused_1; 2469 __le32 queue_id0_min_bw; 2470 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2471 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2472 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2473 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2474 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2475 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2476 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2477 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2485 __le32 queue_id0_max_bw; 2486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2493 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2501 u8 queue_id0_tsa_assign; 2502 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2506 u8 queue_id0_pri_lvl; 2507 u8 queue_id0_bw_weight; 2508 u8 queue_id1; 2509 __le32 queue_id1_min_bw; 2510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2514 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2515 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2516 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2517 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2518 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2525 __le32 queue_id1_max_bw; 2526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2534 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2541 u8 queue_id1_tsa_assign; 2542 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2546 u8 queue_id1_pri_lvl; 2547 u8 queue_id1_bw_weight; 2548 u8 queue_id2; 2549 __le32 queue_id2_min_bw; 2550 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2555 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2556 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2557 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2558 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2559 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2560 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2561 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2562 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2563 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2564 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2565 __le32 queue_id2_max_bw; 2566 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2567 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2568 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2569 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2570 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2571 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2572 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2573 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2574 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2575 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2576 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2577 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2578 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2579 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2580 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2581 u8 queue_id2_tsa_assign; 2582 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2583 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2584 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2585 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2586 u8 queue_id2_pri_lvl; 2587 u8 queue_id2_bw_weight; 2588 u8 queue_id3; 2589 __le32 queue_id3_min_bw; 2590 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2591 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2592 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2593 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2594 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2595 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 2596 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2597 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2598 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2599 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2600 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2601 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2602 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2603 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2604 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2605 __le32 queue_id3_max_bw; 2606 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2607 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2608 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2609 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2610 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2611 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 2612 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2613 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2614 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2615 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2616 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2617 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2618 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2619 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2620 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2621 u8 queue_id3_tsa_assign; 2622 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2623 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2624 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2625 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2626 u8 queue_id3_pri_lvl; 2627 u8 queue_id3_bw_weight; 2628 u8 queue_id4; 2629 __le32 queue_id4_min_bw; 2630 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2631 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2632 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2633 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2634 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2635 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 2636 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2637 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2638 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2639 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2640 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2641 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2642 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2643 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2644 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2645 __le32 queue_id4_max_bw; 2646 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2647 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2648 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 2649 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 2650 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 2651 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 2652 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2653 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2654 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2655 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2656 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2657 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2658 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2659 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2660 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 2661 u8 queue_id4_tsa_assign; 2662 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 2663 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 2664 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2665 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 2666 u8 queue_id4_pri_lvl; 2667 u8 queue_id4_bw_weight; 2668 u8 queue_id5; 2669 __le32 queue_id5_min_bw; 2670 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2671 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2672 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 2673 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 2674 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 2675 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 2676 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2677 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2678 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2679 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2680 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2681 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2682 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2683 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2684 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 2685 __le32 queue_id5_max_bw; 2686 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2687 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2688 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 2689 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 2690 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 2691 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 2692 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2693 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2694 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2695 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2696 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2697 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2698 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2699 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2700 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 2701 u8 queue_id5_tsa_assign; 2702 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 2703 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 2704 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2705 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 2706 u8 queue_id5_pri_lvl; 2707 u8 queue_id5_bw_weight; 2708 u8 queue_id6; 2709 __le32 queue_id6_min_bw; 2710 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2711 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2712 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 2713 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 2714 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 2715 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 2716 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2717 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2718 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2719 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2720 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2721 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2722 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2723 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2724 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 2725 __le32 queue_id6_max_bw; 2726 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2727 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2728 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 2729 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 2730 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 2731 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 2732 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2733 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2734 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2735 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2736 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2737 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2738 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2739 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2740 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 2741 u8 queue_id6_tsa_assign; 2742 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 2743 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 2744 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2745 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 2746 u8 queue_id6_pri_lvl; 2747 u8 queue_id6_bw_weight; 2748 u8 queue_id7; 2749 __le32 queue_id7_min_bw; 2750 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2751 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2752 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 2753 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 2754 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 2755 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 2756 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2757 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2758 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2759 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2760 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2761 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2762 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2763 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2764 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 2765 __le32 queue_id7_max_bw; 2766 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2767 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2768 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 2769 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 2770 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 2771 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 2772 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2773 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2774 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2775 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2776 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2777 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2778 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2779 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2780 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 2781 u8 queue_id7_tsa_assign; 2782 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 2783 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 2784 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2785 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 2786 u8 queue_id7_pri_lvl; 2787 u8 queue_id7_bw_weight; 2788 u8 unused_2; 2789 u8 unused_3; 2790 u8 unused_4; 2791 u8 unused_5; 2792 u8 valid; 2793 }; 2794 2795 /* hwrm_queue_cos2bw_cfg */ 2796 /* Input (128 bytes) */ 2797 struct hwrm_queue_cos2bw_cfg_input { 2798 __le16 req_type; 2799 __le16 cmpl_ring; 2800 __le16 seq_id; 2801 __le16 target_id; 2802 __le64 resp_addr; 2803 __le32 flags; 2804 __le32 enables; 2805 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2806 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2807 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2808 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2809 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2810 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2811 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2812 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2813 __le16 port_id; 2814 u8 queue_id0; 2815 u8 unused_0; 2816 __le32 queue_id0_min_bw; 2817 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2818 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2819 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2820 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2821 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2822 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 2823 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2824 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2825 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2826 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2827 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2828 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2829 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2830 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2831 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2832 __le32 queue_id0_max_bw; 2833 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2834 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2835 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2836 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2837 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2838 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 2839 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2840 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2841 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2842 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2843 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2844 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2845 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2846 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2847 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2848 u8 queue_id0_tsa_assign; 2849 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2850 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2851 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2852 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2853 u8 queue_id0_pri_lvl; 2854 u8 queue_id0_bw_weight; 2855 u8 queue_id1; 2856 __le32 queue_id1_min_bw; 2857 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2858 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2859 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2860 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2861 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2862 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 2863 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2864 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2865 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2866 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2867 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2868 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2869 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2870 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2871 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2872 __le32 queue_id1_max_bw; 2873 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2874 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2875 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2876 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2877 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2878 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 2879 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2880 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2881 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2882 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2883 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2884 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2885 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2886 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2887 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2888 u8 queue_id1_tsa_assign; 2889 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2890 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2891 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2892 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2893 u8 queue_id1_pri_lvl; 2894 u8 queue_id1_bw_weight; 2895 u8 queue_id2; 2896 __le32 queue_id2_min_bw; 2897 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2898 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2899 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2900 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2901 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2902 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 2903 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2904 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2905 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2906 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2907 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2908 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2909 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2910 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2911 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2912 __le32 queue_id2_max_bw; 2913 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2914 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2915 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2916 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2917 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2918 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 2919 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2920 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2921 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2922 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2923 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2924 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2925 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2926 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2927 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2928 u8 queue_id2_tsa_assign; 2929 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2930 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2931 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2932 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2933 u8 queue_id2_pri_lvl; 2934 u8 queue_id2_bw_weight; 2935 u8 queue_id3; 2936 __le32 queue_id3_min_bw; 2937 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2938 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2939 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2940 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2941 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2942 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 2943 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2944 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2945 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2946 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2947 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2948 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2949 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2950 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2951 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 2952 __le32 queue_id3_max_bw; 2953 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2954 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2955 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2956 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2957 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2958 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 2959 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2960 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2961 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2962 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2963 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2964 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2965 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2966 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2967 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 2968 u8 queue_id3_tsa_assign; 2969 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 2970 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 2971 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2972 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 2973 u8 queue_id3_pri_lvl; 2974 u8 queue_id3_bw_weight; 2975 u8 queue_id4; 2976 __le32 queue_id4_min_bw; 2977 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2978 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2979 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2980 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2981 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2982 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 2983 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2984 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2985 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2986 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2987 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2988 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2989 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2990 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2991 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 2992 __le32 queue_id4_max_bw; 2993 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2994 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2995 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 2996 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 2997 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 2998 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 2999 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3000 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3001 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3002 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3003 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3004 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3005 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3006 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3007 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3008 u8 queue_id4_tsa_assign; 3009 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3010 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3011 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3012 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3013 u8 queue_id4_pri_lvl; 3014 u8 queue_id4_bw_weight; 3015 u8 queue_id5; 3016 __le32 queue_id5_min_bw; 3017 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3018 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3019 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3020 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3021 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3022 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3023 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3024 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3025 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3026 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3027 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3028 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3029 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3030 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3031 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3032 __le32 queue_id5_max_bw; 3033 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3034 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3035 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3036 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3037 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3038 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3039 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3040 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3041 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3042 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3043 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3044 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3045 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3046 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3047 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3048 u8 queue_id5_tsa_assign; 3049 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3050 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3051 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3052 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3053 u8 queue_id5_pri_lvl; 3054 u8 queue_id5_bw_weight; 3055 u8 queue_id6; 3056 __le32 queue_id6_min_bw; 3057 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3058 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3059 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3060 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3061 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3062 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3063 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3064 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3065 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3066 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3067 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3068 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3069 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3070 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3071 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3072 __le32 queue_id6_max_bw; 3073 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3074 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3075 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3076 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3077 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3078 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3079 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3080 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3081 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3082 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3083 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3084 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3085 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3086 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3087 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3088 u8 queue_id6_tsa_assign; 3089 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3090 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3091 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3092 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3093 u8 queue_id6_pri_lvl; 3094 u8 queue_id6_bw_weight; 3095 u8 queue_id7; 3096 __le32 queue_id7_min_bw; 3097 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3098 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3099 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3100 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3101 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3102 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3103 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3104 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3105 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3106 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3107 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3108 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3109 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3110 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3111 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3112 __le32 queue_id7_max_bw; 3113 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3114 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3115 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3116 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3117 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3118 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3119 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3120 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3121 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3122 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3123 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3124 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3125 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3126 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3127 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3128 u8 queue_id7_tsa_assign; 3129 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3130 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3131 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3132 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3133 u8 queue_id7_pri_lvl; 3134 u8 queue_id7_bw_weight; 3135 u8 unused_1[5]; 3136 }; 3137 3138 /* Output (16 bytes) */ 3139 struct hwrm_queue_cos2bw_cfg_output { 3140 __le16 error_code; 3141 __le16 req_type; 3142 __le16 seq_id; 3143 __le16 resp_len; 3144 __le32 unused_0; 3145 u8 unused_1; 3146 u8 unused_2; 3147 u8 unused_3; 3148 u8 valid; 3149 }; 3150 3151 /* hwrm_vnic_alloc */ 3152 /* Input (24 bytes) */ 3153 struct hwrm_vnic_alloc_input { 3154 __le16 req_type; 3155 __le16 cmpl_ring; 3156 __le16 seq_id; 3157 __le16 target_id; 3158 __le64 resp_addr; 3159 __le32 flags; 3160 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3161 __le32 unused_0; 3162 }; 3163 3164 /* Output (16 bytes) */ 3165 struct hwrm_vnic_alloc_output { 3166 __le16 error_code; 3167 __le16 req_type; 3168 __le16 seq_id; 3169 __le16 resp_len; 3170 __le32 vnic_id; 3171 u8 unused_0; 3172 u8 unused_1; 3173 u8 unused_2; 3174 u8 valid; 3175 }; 3176 3177 /* hwrm_vnic_free */ 3178 /* Input (24 bytes) */ 3179 struct hwrm_vnic_free_input { 3180 __le16 req_type; 3181 __le16 cmpl_ring; 3182 __le16 seq_id; 3183 __le16 target_id; 3184 __le64 resp_addr; 3185 __le32 vnic_id; 3186 __le32 unused_0; 3187 }; 3188 3189 /* Output (16 bytes) */ 3190 struct hwrm_vnic_free_output { 3191 __le16 error_code; 3192 __le16 req_type; 3193 __le16 seq_id; 3194 __le16 resp_len; 3195 __le32 unused_0; 3196 u8 unused_1; 3197 u8 unused_2; 3198 u8 unused_3; 3199 u8 valid; 3200 }; 3201 3202 /* hwrm_vnic_cfg */ 3203 /* Input (40 bytes) */ 3204 struct hwrm_vnic_cfg_input { 3205 __le16 req_type; 3206 __le16 cmpl_ring; 3207 __le16 seq_id; 3208 __le16 target_id; 3209 __le64 resp_addr; 3210 __le32 flags; 3211 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3212 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3213 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3214 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3215 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3216 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3217 __le32 enables; 3218 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3219 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3220 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3221 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3222 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3223 __le16 vnic_id; 3224 __le16 dflt_ring_grp; 3225 __le16 rss_rule; 3226 __le16 cos_rule; 3227 __le16 lb_rule; 3228 __le16 mru; 3229 __le32 unused_0; 3230 }; 3231 3232 /* Output (16 bytes) */ 3233 struct hwrm_vnic_cfg_output { 3234 __le16 error_code; 3235 __le16 req_type; 3236 __le16 seq_id; 3237 __le16 resp_len; 3238 __le32 unused_0; 3239 u8 unused_1; 3240 u8 unused_2; 3241 u8 unused_3; 3242 u8 valid; 3243 }; 3244 3245 /* hwrm_vnic_qcaps */ 3246 /* Input (24 bytes) */ 3247 struct hwrm_vnic_qcaps_input { 3248 __le16 req_type; 3249 __le16 cmpl_ring; 3250 __le16 seq_id; 3251 __le16 target_id; 3252 __le64 resp_addr; 3253 __le32 enables; 3254 __le32 unused_0; 3255 }; 3256 3257 /* Output (24 bytes) */ 3258 struct hwrm_vnic_qcaps_output { 3259 __le16 error_code; 3260 __le16 req_type; 3261 __le16 seq_id; 3262 __le16 resp_len; 3263 __le16 mru; 3264 u8 unused_0; 3265 u8 unused_1; 3266 __le32 flags; 3267 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3268 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3269 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3270 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3271 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3272 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3273 __le32 unused_2; 3274 u8 unused_3; 3275 u8 unused_4; 3276 u8 unused_5; 3277 u8 valid; 3278 }; 3279 3280 /* hwrm_vnic_tpa_cfg */ 3281 /* Input (40 bytes) */ 3282 struct hwrm_vnic_tpa_cfg_input { 3283 __le16 req_type; 3284 __le16 cmpl_ring; 3285 __le16 seq_id; 3286 __le16 target_id; 3287 __le64 resp_addr; 3288 __le32 flags; 3289 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3290 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3291 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3292 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3293 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3294 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3295 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3296 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3297 __le32 enables; 3298 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3299 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3300 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3301 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3302 __le16 vnic_id; 3303 __le16 max_agg_segs; 3304 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3305 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3306 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3307 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3308 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3309 __le16 max_aggs; 3310 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3311 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3312 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3313 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3314 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3315 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3316 u8 unused_0; 3317 u8 unused_1; 3318 __le32 max_agg_timer; 3319 __le32 min_agg_len; 3320 }; 3321 3322 /* Output (16 bytes) */ 3323 struct hwrm_vnic_tpa_cfg_output { 3324 __le16 error_code; 3325 __le16 req_type; 3326 __le16 seq_id; 3327 __le16 resp_len; 3328 __le32 unused_0; 3329 u8 unused_1; 3330 u8 unused_2; 3331 u8 unused_3; 3332 u8 valid; 3333 }; 3334 3335 /* hwrm_vnic_rss_cfg */ 3336 /* Input (48 bytes) */ 3337 struct hwrm_vnic_rss_cfg_input { 3338 __le16 req_type; 3339 __le16 cmpl_ring; 3340 __le16 seq_id; 3341 __le16 target_id; 3342 __le64 resp_addr; 3343 __le32 hash_type; 3344 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3345 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3346 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3347 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3348 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3349 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3350 __le32 unused_0; 3351 __le64 ring_grp_tbl_addr; 3352 __le64 hash_key_tbl_addr; 3353 __le16 rss_ctx_idx; 3354 __le16 unused_1[3]; 3355 }; 3356 3357 /* Output (16 bytes) */ 3358 struct hwrm_vnic_rss_cfg_output { 3359 __le16 error_code; 3360 __le16 req_type; 3361 __le16 seq_id; 3362 __le16 resp_len; 3363 __le32 unused_0; 3364 u8 unused_1; 3365 u8 unused_2; 3366 u8 unused_3; 3367 u8 valid; 3368 }; 3369 3370 /* hwrm_vnic_plcmodes_cfg */ 3371 /* Input (40 bytes) */ 3372 struct hwrm_vnic_plcmodes_cfg_input { 3373 __le16 req_type; 3374 __le16 cmpl_ring; 3375 __le16 seq_id; 3376 __le16 target_id; 3377 __le64 resp_addr; 3378 __le32 flags; 3379 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3380 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3381 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3382 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3383 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3384 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3385 __le32 enables; 3386 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3387 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3388 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3389 __le32 vnic_id; 3390 __le16 jumbo_thresh; 3391 __le16 hds_offset; 3392 __le16 hds_threshold; 3393 __le16 unused_0[3]; 3394 }; 3395 3396 /* Output (16 bytes) */ 3397 struct hwrm_vnic_plcmodes_cfg_output { 3398 __le16 error_code; 3399 __le16 req_type; 3400 __le16 seq_id; 3401 __le16 resp_len; 3402 __le32 unused_0; 3403 u8 unused_1; 3404 u8 unused_2; 3405 u8 unused_3; 3406 u8 valid; 3407 }; 3408 3409 /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 3410 /* Input (16 bytes) */ 3411 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3412 __le16 req_type; 3413 __le16 cmpl_ring; 3414 __le16 seq_id; 3415 __le16 target_id; 3416 __le64 resp_addr; 3417 }; 3418 3419 /* Output (16 bytes) */ 3420 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3421 __le16 error_code; 3422 __le16 req_type; 3423 __le16 seq_id; 3424 __le16 resp_len; 3425 __le16 rss_cos_lb_ctx_id; 3426 u8 unused_0; 3427 u8 unused_1; 3428 u8 unused_2; 3429 u8 unused_3; 3430 u8 unused_4; 3431 u8 valid; 3432 }; 3433 3434 /* hwrm_vnic_rss_cos_lb_ctx_free */ 3435 /* Input (24 bytes) */ 3436 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3437 __le16 req_type; 3438 __le16 cmpl_ring; 3439 __le16 seq_id; 3440 __le16 target_id; 3441 __le64 resp_addr; 3442 __le16 rss_cos_lb_ctx_id; 3443 __le16 unused_0[3]; 3444 }; 3445 3446 /* Output (16 bytes) */ 3447 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3448 __le16 error_code; 3449 __le16 req_type; 3450 __le16 seq_id; 3451 __le16 resp_len; 3452 __le32 unused_0; 3453 u8 unused_1; 3454 u8 unused_2; 3455 u8 unused_3; 3456 u8 valid; 3457 }; 3458 3459 /* hwrm_ring_alloc */ 3460 /* Input (80 bytes) */ 3461 struct hwrm_ring_alloc_input { 3462 __le16 req_type; 3463 __le16 cmpl_ring; 3464 __le16 seq_id; 3465 __le16 target_id; 3466 __le64 resp_addr; 3467 __le32 enables; 3468 #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 3469 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3470 #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 3471 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3472 #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 3473 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3474 u8 ring_type; 3475 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3476 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3477 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3478 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3479 u8 unused_0; 3480 __le16 unused_1; 3481 __le64 page_tbl_addr; 3482 __le32 fbo; 3483 u8 page_size; 3484 u8 page_tbl_depth; 3485 u8 unused_2; 3486 u8 unused_3; 3487 __le32 length; 3488 __le16 logical_id; 3489 __le16 cmpl_ring_id; 3490 __le16 queue_id; 3491 u8 unused_4; 3492 u8 unused_5; 3493 __le32 reserved1; 3494 __le16 ring_arb_cfg; 3495 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3496 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3497 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3498 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3499 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3500 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3501 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3502 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3503 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3504 u8 unused_6; 3505 u8 unused_7; 3506 __le32 reserved3; 3507 __le32 stat_ctx_id; 3508 __le32 reserved4; 3509 __le32 max_bw; 3510 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3511 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3512 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3513 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3514 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3515 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3516 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3517 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3518 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3519 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3520 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3521 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3522 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3523 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3524 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3525 u8 int_mode; 3526 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3527 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3528 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3529 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3530 u8 unused_8[3]; 3531 }; 3532 3533 /* Output (16 bytes) */ 3534 struct hwrm_ring_alloc_output { 3535 __le16 error_code; 3536 __le16 req_type; 3537 __le16 seq_id; 3538 __le16 resp_len; 3539 __le16 ring_id; 3540 __le16 logical_ring_id; 3541 u8 unused_0; 3542 u8 unused_1; 3543 u8 unused_2; 3544 u8 valid; 3545 }; 3546 3547 /* hwrm_ring_free */ 3548 /* Input (24 bytes) */ 3549 struct hwrm_ring_free_input { 3550 __le16 req_type; 3551 __le16 cmpl_ring; 3552 __le16 seq_id; 3553 __le16 target_id; 3554 __le64 resp_addr; 3555 u8 ring_type; 3556 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3557 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3558 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3559 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3560 u8 unused_0; 3561 __le16 ring_id; 3562 __le32 unused_1; 3563 }; 3564 3565 /* Output (16 bytes) */ 3566 struct hwrm_ring_free_output { 3567 __le16 error_code; 3568 __le16 req_type; 3569 __le16 seq_id; 3570 __le16 resp_len; 3571 __le32 unused_0; 3572 u8 unused_1; 3573 u8 unused_2; 3574 u8 unused_3; 3575 u8 valid; 3576 }; 3577 3578 /* hwrm_ring_cmpl_ring_qaggint_params */ 3579 /* Input (24 bytes) */ 3580 struct hwrm_ring_cmpl_ring_qaggint_params_input { 3581 __le16 req_type; 3582 __le16 cmpl_ring; 3583 __le16 seq_id; 3584 __le16 target_id; 3585 __le64 resp_addr; 3586 __le16 ring_id; 3587 __le16 unused_0[3]; 3588 }; 3589 3590 /* Output (32 bytes) */ 3591 struct hwrm_ring_cmpl_ring_qaggint_params_output { 3592 __le16 error_code; 3593 __le16 req_type; 3594 __le16 seq_id; 3595 __le16 resp_len; 3596 __le16 flags; 3597 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3598 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3599 __le16 num_cmpl_dma_aggr; 3600 __le16 num_cmpl_dma_aggr_during_int; 3601 __le16 cmpl_aggr_dma_tmr; 3602 __le16 cmpl_aggr_dma_tmr_during_int; 3603 __le16 int_lat_tmr_min; 3604 __le16 int_lat_tmr_max; 3605 __le16 num_cmpl_aggr_int; 3606 __le32 unused_0; 3607 u8 unused_1; 3608 u8 unused_2; 3609 u8 unused_3; 3610 u8 valid; 3611 }; 3612 3613 /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3614 /* Input (40 bytes) */ 3615 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3616 __le16 req_type; 3617 __le16 cmpl_ring; 3618 __le16 seq_id; 3619 __le16 target_id; 3620 __le64 resp_addr; 3621 __le16 ring_id; 3622 __le16 flags; 3623 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3624 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3625 __le16 num_cmpl_dma_aggr; 3626 __le16 num_cmpl_dma_aggr_during_int; 3627 __le16 cmpl_aggr_dma_tmr; 3628 __le16 cmpl_aggr_dma_tmr_during_int; 3629 __le16 int_lat_tmr_min; 3630 __le16 int_lat_tmr_max; 3631 __le16 num_cmpl_aggr_int; 3632 __le16 unused_0[3]; 3633 }; 3634 3635 /* Output (16 bytes) */ 3636 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3637 __le16 error_code; 3638 __le16 req_type; 3639 __le16 seq_id; 3640 __le16 resp_len; 3641 __le32 unused_0; 3642 u8 unused_1; 3643 u8 unused_2; 3644 u8 unused_3; 3645 u8 valid; 3646 }; 3647 3648 /* hwrm_ring_reset */ 3649 /* Input (24 bytes) */ 3650 struct hwrm_ring_reset_input { 3651 __le16 req_type; 3652 __le16 cmpl_ring; 3653 __le16 seq_id; 3654 __le16 target_id; 3655 __le64 resp_addr; 3656 u8 ring_type; 3657 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 3658 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3659 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3660 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3661 u8 unused_0; 3662 __le16 ring_id; 3663 __le32 unused_1; 3664 }; 3665 3666 /* Output (16 bytes) */ 3667 struct hwrm_ring_reset_output { 3668 __le16 error_code; 3669 __le16 req_type; 3670 __le16 seq_id; 3671 __le16 resp_len; 3672 __le32 unused_0; 3673 u8 unused_1; 3674 u8 unused_2; 3675 u8 unused_3; 3676 u8 valid; 3677 }; 3678 3679 /* hwrm_ring_grp_alloc */ 3680 /* Input (24 bytes) */ 3681 struct hwrm_ring_grp_alloc_input { 3682 __le16 req_type; 3683 __le16 cmpl_ring; 3684 __le16 seq_id; 3685 __le16 target_id; 3686 __le64 resp_addr; 3687 __le16 cr; 3688 __le16 rr; 3689 __le16 ar; 3690 __le16 sc; 3691 }; 3692 3693 /* Output (16 bytes) */ 3694 struct hwrm_ring_grp_alloc_output { 3695 __le16 error_code; 3696 __le16 req_type; 3697 __le16 seq_id; 3698 __le16 resp_len; 3699 __le32 ring_group_id; 3700 u8 unused_0; 3701 u8 unused_1; 3702 u8 unused_2; 3703 u8 valid; 3704 }; 3705 3706 /* hwrm_ring_grp_free */ 3707 /* Input (24 bytes) */ 3708 struct hwrm_ring_grp_free_input { 3709 __le16 req_type; 3710 __le16 cmpl_ring; 3711 __le16 seq_id; 3712 __le16 target_id; 3713 __le64 resp_addr; 3714 __le32 ring_group_id; 3715 __le32 unused_0; 3716 }; 3717 3718 /* Output (16 bytes) */ 3719 struct hwrm_ring_grp_free_output { 3720 __le16 error_code; 3721 __le16 req_type; 3722 __le16 seq_id; 3723 __le16 resp_len; 3724 __le32 unused_0; 3725 u8 unused_1; 3726 u8 unused_2; 3727 u8 unused_3; 3728 u8 valid; 3729 }; 3730 3731 /* hwrm_cfa_l2_filter_alloc */ 3732 /* Input (96 bytes) */ 3733 struct hwrm_cfa_l2_filter_alloc_input { 3734 __le16 req_type; 3735 __le16 cmpl_ring; 3736 __le16 seq_id; 3737 __le16 target_id; 3738 __le64 resp_addr; 3739 __le32 flags; 3740 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3741 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3742 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 3743 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3744 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3745 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3746 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3747 __le32 enables; 3748 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3749 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3750 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3751 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3752 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3753 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3754 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3755 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3756 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3757 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3758 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3759 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3760 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3761 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3762 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3763 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3764 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3765 u8 l2_addr[6]; 3766 u8 unused_0; 3767 u8 unused_1; 3768 u8 l2_addr_mask[6]; 3769 __le16 l2_ovlan; 3770 __le16 l2_ovlan_mask; 3771 __le16 l2_ivlan; 3772 __le16 l2_ivlan_mask; 3773 u8 unused_2; 3774 u8 unused_3; 3775 u8 t_l2_addr[6]; 3776 u8 unused_4; 3777 u8 unused_5; 3778 u8 t_l2_addr_mask[6]; 3779 __le16 t_l2_ovlan; 3780 __le16 t_l2_ovlan_mask; 3781 __le16 t_l2_ivlan; 3782 __le16 t_l2_ivlan_mask; 3783 u8 src_type; 3784 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3785 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3786 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3787 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3788 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3789 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3790 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3791 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3792 u8 unused_6; 3793 __le32 src_id; 3794 u8 tunnel_type; 3795 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3796 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3797 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3798 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3799 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3800 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3801 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3802 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3803 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3804 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3805 u8 unused_7; 3806 __le16 dst_id; 3807 __le16 mirror_vnic_id; 3808 u8 pri_hint; 3809 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3810 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 3811 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 3812 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 3813 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 3814 u8 unused_8; 3815 __le32 unused_9; 3816 __le64 l2_filter_id_hint; 3817 }; 3818 3819 /* Output (24 bytes) */ 3820 struct hwrm_cfa_l2_filter_alloc_output { 3821 __le16 error_code; 3822 __le16 req_type; 3823 __le16 seq_id; 3824 __le16 resp_len; 3825 __le64 l2_filter_id; 3826 __le32 flow_id; 3827 u8 unused_0; 3828 u8 unused_1; 3829 u8 unused_2; 3830 u8 valid; 3831 }; 3832 3833 /* hwrm_cfa_l2_filter_free */ 3834 /* Input (24 bytes) */ 3835 struct hwrm_cfa_l2_filter_free_input { 3836 __le16 req_type; 3837 __le16 cmpl_ring; 3838 __le16 seq_id; 3839 __le16 target_id; 3840 __le64 resp_addr; 3841 __le64 l2_filter_id; 3842 }; 3843 3844 /* Output (16 bytes) */ 3845 struct hwrm_cfa_l2_filter_free_output { 3846 __le16 error_code; 3847 __le16 req_type; 3848 __le16 seq_id; 3849 __le16 resp_len; 3850 __le32 unused_0; 3851 u8 unused_1; 3852 u8 unused_2; 3853 u8 unused_3; 3854 u8 valid; 3855 }; 3856 3857 /* hwrm_cfa_l2_filter_cfg */ 3858 /* Input (40 bytes) */ 3859 struct hwrm_cfa_l2_filter_cfg_input { 3860 __le16 req_type; 3861 __le16 cmpl_ring; 3862 __le16 seq_id; 3863 __le16 target_id; 3864 __le64 resp_addr; 3865 __le32 flags; 3866 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3867 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3868 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 3869 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3870 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3871 __le32 enables; 3872 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3873 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3874 __le64 l2_filter_id; 3875 __le32 dst_id; 3876 __le32 new_mirror_vnic_id; 3877 }; 3878 3879 /* Output (16 bytes) */ 3880 struct hwrm_cfa_l2_filter_cfg_output { 3881 __le16 error_code; 3882 __le16 req_type; 3883 __le16 seq_id; 3884 __le16 resp_len; 3885 __le32 unused_0; 3886 u8 unused_1; 3887 u8 unused_2; 3888 u8 unused_3; 3889 u8 valid; 3890 }; 3891 3892 /* hwrm_cfa_l2_set_rx_mask */ 3893 /* Input (56 bytes) */ 3894 struct hwrm_cfa_l2_set_rx_mask_input { 3895 __le16 req_type; 3896 __le16 cmpl_ring; 3897 __le16 seq_id; 3898 __le16 target_id; 3899 __le64 resp_addr; 3900 __le32 vnic_id; 3901 __le32 mask; 3902 #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3903 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3904 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3905 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3906 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3907 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3908 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 3909 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 3910 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 3911 __le64 mc_tbl_addr; 3912 __le32 num_mc_entries; 3913 __le32 unused_0; 3914 __le64 vlan_tag_tbl_addr; 3915 __le32 num_vlan_tags; 3916 __le32 unused_1; 3917 }; 3918 3919 /* Output (16 bytes) */ 3920 struct hwrm_cfa_l2_set_rx_mask_output { 3921 __le16 error_code; 3922 __le16 req_type; 3923 __le16 seq_id; 3924 __le16 resp_len; 3925 __le32 unused_0; 3926 u8 unused_1; 3927 u8 unused_2; 3928 u8 unused_3; 3929 u8 valid; 3930 }; 3931 3932 /* hwrm_cfa_tunnel_filter_alloc */ 3933 /* Input (88 bytes) */ 3934 struct hwrm_cfa_tunnel_filter_alloc_input { 3935 __le16 req_type; 3936 __le16 cmpl_ring; 3937 __le16 seq_id; 3938 __le16 target_id; 3939 __le64 resp_addr; 3940 __le32 flags; 3941 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3942 __le32 enables; 3943 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3944 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3945 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3946 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3947 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3948 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3949 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3950 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3951 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3952 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3953 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3954 __le64 l2_filter_id; 3955 u8 l2_addr[6]; 3956 __le16 l2_ivlan; 3957 __le32 l3_addr[4]; 3958 __le32 t_l3_addr[4]; 3959 u8 l3_addr_type; 3960 u8 t_l3_addr_type; 3961 u8 tunnel_type; 3962 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3963 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3964 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3965 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3966 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3967 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3968 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3969 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3970 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3971 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3972 u8 unused_0; 3973 __le32 vni; 3974 __le32 dst_vnic_id; 3975 __le32 mirror_vnic_id; 3976 }; 3977 3978 /* Output (24 bytes) */ 3979 struct hwrm_cfa_tunnel_filter_alloc_output { 3980 __le16 error_code; 3981 __le16 req_type; 3982 __le16 seq_id; 3983 __le16 resp_len; 3984 __le64 tunnel_filter_id; 3985 __le32 flow_id; 3986 u8 unused_0; 3987 u8 unused_1; 3988 u8 unused_2; 3989 u8 valid; 3990 }; 3991 3992 /* hwrm_cfa_tunnel_filter_free */ 3993 /* Input (24 bytes) */ 3994 struct hwrm_cfa_tunnel_filter_free_input { 3995 __le16 req_type; 3996 __le16 cmpl_ring; 3997 __le16 seq_id; 3998 __le16 target_id; 3999 __le64 resp_addr; 4000 __le64 tunnel_filter_id; 4001 }; 4002 4003 /* Output (16 bytes) */ 4004 struct hwrm_cfa_tunnel_filter_free_output { 4005 __le16 error_code; 4006 __le16 req_type; 4007 __le16 seq_id; 4008 __le16 resp_len; 4009 __le32 unused_0; 4010 u8 unused_1; 4011 u8 unused_2; 4012 u8 unused_3; 4013 u8 valid; 4014 }; 4015 4016 /* hwrm_cfa_encap_record_alloc */ 4017 /* Input (32 bytes) */ 4018 struct hwrm_cfa_encap_record_alloc_input { 4019 __le16 req_type; 4020 __le16 cmpl_ring; 4021 __le16 seq_id; 4022 __le16 target_id; 4023 __le64 resp_addr; 4024 __le32 flags; 4025 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4026 u8 encap_type; 4027 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4028 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4029 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4030 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4031 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4032 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4033 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4034 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4035 u8 unused_0; 4036 __le16 unused_1; 4037 __le32 encap_data[16]; 4038 }; 4039 4040 /* Output (16 bytes) */ 4041 struct hwrm_cfa_encap_record_alloc_output { 4042 __le16 error_code; 4043 __le16 req_type; 4044 __le16 seq_id; 4045 __le16 resp_len; 4046 __le32 encap_record_id; 4047 u8 unused_0; 4048 u8 unused_1; 4049 u8 unused_2; 4050 u8 valid; 4051 }; 4052 4053 /* hwrm_cfa_encap_record_free */ 4054 /* Input (24 bytes) */ 4055 struct hwrm_cfa_encap_record_free_input { 4056 __le16 req_type; 4057 __le16 cmpl_ring; 4058 __le16 seq_id; 4059 __le16 target_id; 4060 __le64 resp_addr; 4061 __le32 encap_record_id; 4062 __le32 unused_0; 4063 }; 4064 4065 /* Output (16 bytes) */ 4066 struct hwrm_cfa_encap_record_free_output { 4067 __le16 error_code; 4068 __le16 req_type; 4069 __le16 seq_id; 4070 __le16 resp_len; 4071 __le32 unused_0; 4072 u8 unused_1; 4073 u8 unused_2; 4074 u8 unused_3; 4075 u8 valid; 4076 }; 4077 4078 /* hwrm_cfa_ntuple_filter_alloc */ 4079 /* Input (128 bytes) */ 4080 struct hwrm_cfa_ntuple_filter_alloc_input { 4081 __le16 req_type; 4082 __le16 cmpl_ring; 4083 __le16 seq_id; 4084 __le16 target_id; 4085 __le64 resp_addr; 4086 __le32 flags; 4087 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4088 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4089 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4090 __le32 enables; 4091 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4092 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4093 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4094 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4095 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4096 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4097 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4098 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4099 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4100 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4101 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4102 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4103 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4104 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4105 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4106 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4107 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4108 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4109 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4110 __le64 l2_filter_id; 4111 u8 src_macaddr[6]; 4112 __be16 ethertype; 4113 u8 ip_addr_type; 4114 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4115 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4116 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4117 u8 ip_protocol; 4118 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4119 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x6UL 4120 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x11UL 4121 __le16 dst_id; 4122 __le16 mirror_vnic_id; 4123 u8 tunnel_type; 4124 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4125 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4126 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4127 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4128 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4129 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4130 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4131 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4132 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4133 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4134 u8 pri_hint; 4135 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4136 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4137 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4138 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4139 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4140 __be32 src_ipaddr[4]; 4141 __be32 src_ipaddr_mask[4]; 4142 __be32 dst_ipaddr[4]; 4143 __be32 dst_ipaddr_mask[4]; 4144 __be16 src_port; 4145 __be16 src_port_mask; 4146 __be16 dst_port; 4147 __be16 dst_port_mask; 4148 __le64 ntuple_filter_id_hint; 4149 }; 4150 4151 /* Output (24 bytes) */ 4152 struct hwrm_cfa_ntuple_filter_alloc_output { 4153 __le16 error_code; 4154 __le16 req_type; 4155 __le16 seq_id; 4156 __le16 resp_len; 4157 __le64 ntuple_filter_id; 4158 __le32 flow_id; 4159 u8 unused_0; 4160 u8 unused_1; 4161 u8 unused_2; 4162 u8 valid; 4163 }; 4164 4165 /* hwrm_cfa_ntuple_filter_free */ 4166 /* Input (24 bytes) */ 4167 struct hwrm_cfa_ntuple_filter_free_input { 4168 __le16 req_type; 4169 __le16 cmpl_ring; 4170 __le16 seq_id; 4171 __le16 target_id; 4172 __le64 resp_addr; 4173 __le64 ntuple_filter_id; 4174 }; 4175 4176 /* Output (16 bytes) */ 4177 struct hwrm_cfa_ntuple_filter_free_output { 4178 __le16 error_code; 4179 __le16 req_type; 4180 __le16 seq_id; 4181 __le16 resp_len; 4182 __le32 unused_0; 4183 u8 unused_1; 4184 u8 unused_2; 4185 u8 unused_3; 4186 u8 valid; 4187 }; 4188 4189 /* hwrm_cfa_ntuple_filter_cfg */ 4190 /* Input (48 bytes) */ 4191 struct hwrm_cfa_ntuple_filter_cfg_input { 4192 __le16 req_type; 4193 __le16 cmpl_ring; 4194 __le16 seq_id; 4195 __le16 target_id; 4196 __le64 resp_addr; 4197 __le32 enables; 4198 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4199 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4200 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4201 __le32 unused_0; 4202 __le64 ntuple_filter_id; 4203 __le32 new_dst_id; 4204 __le32 new_mirror_vnic_id; 4205 __le16 new_meter_instance_id; 4206 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4207 __le16 unused_1[3]; 4208 }; 4209 4210 /* Output (16 bytes) */ 4211 struct hwrm_cfa_ntuple_filter_cfg_output { 4212 __le16 error_code; 4213 __le16 req_type; 4214 __le16 seq_id; 4215 __le16 resp_len; 4216 __le32 unused_0; 4217 u8 unused_1; 4218 u8 unused_2; 4219 u8 unused_3; 4220 u8 valid; 4221 }; 4222 4223 /* hwrm_tunnel_dst_port_query */ 4224 /* Input (24 bytes) */ 4225 struct hwrm_tunnel_dst_port_query_input { 4226 __le16 req_type; 4227 __le16 cmpl_ring; 4228 __le16 seq_id; 4229 __le16 target_id; 4230 __le64 resp_addr; 4231 u8 tunnel_type; 4232 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4233 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4234 u8 unused_0[7]; 4235 }; 4236 4237 /* Output (16 bytes) */ 4238 struct hwrm_tunnel_dst_port_query_output { 4239 __le16 error_code; 4240 __le16 req_type; 4241 __le16 seq_id; 4242 __le16 resp_len; 4243 __le16 tunnel_dst_port_id; 4244 __be16 tunnel_dst_port_val; 4245 u8 unused_0; 4246 u8 unused_1; 4247 u8 unused_2; 4248 u8 valid; 4249 }; 4250 4251 /* hwrm_tunnel_dst_port_alloc */ 4252 /* Input (24 bytes) */ 4253 struct hwrm_tunnel_dst_port_alloc_input { 4254 __le16 req_type; 4255 __le16 cmpl_ring; 4256 __le16 seq_id; 4257 __le16 target_id; 4258 __le64 resp_addr; 4259 u8 tunnel_type; 4260 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4261 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4262 u8 unused_0; 4263 __be16 tunnel_dst_port_val; 4264 __le32 unused_1; 4265 }; 4266 4267 /* Output (16 bytes) */ 4268 struct hwrm_tunnel_dst_port_alloc_output { 4269 __le16 error_code; 4270 __le16 req_type; 4271 __le16 seq_id; 4272 __le16 resp_len; 4273 __le16 tunnel_dst_port_id; 4274 u8 unused_0; 4275 u8 unused_1; 4276 u8 unused_2; 4277 u8 unused_3; 4278 u8 unused_4; 4279 u8 valid; 4280 }; 4281 4282 /* hwrm_tunnel_dst_port_free */ 4283 /* Input (24 bytes) */ 4284 struct hwrm_tunnel_dst_port_free_input { 4285 __le16 req_type; 4286 __le16 cmpl_ring; 4287 __le16 seq_id; 4288 __le16 target_id; 4289 __le64 resp_addr; 4290 u8 tunnel_type; 4291 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4292 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4293 u8 unused_0; 4294 __le16 tunnel_dst_port_id; 4295 __le32 unused_1; 4296 }; 4297 4298 /* Output (16 bytes) */ 4299 struct hwrm_tunnel_dst_port_free_output { 4300 __le16 error_code; 4301 __le16 req_type; 4302 __le16 seq_id; 4303 __le16 resp_len; 4304 __le32 unused_0; 4305 u8 unused_1; 4306 u8 unused_2; 4307 u8 unused_3; 4308 u8 valid; 4309 }; 4310 4311 /* hwrm_stat_ctx_alloc */ 4312 /* Input (32 bytes) */ 4313 struct hwrm_stat_ctx_alloc_input { 4314 __le16 req_type; 4315 __le16 cmpl_ring; 4316 __le16 seq_id; 4317 __le16 target_id; 4318 __le64 resp_addr; 4319 __le64 stats_dma_addr; 4320 __le32 update_period_ms; 4321 u8 stat_ctx_flags; 4322 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 4323 u8 unused_0[3]; 4324 }; 4325 4326 /* Output (16 bytes) */ 4327 struct hwrm_stat_ctx_alloc_output { 4328 __le16 error_code; 4329 __le16 req_type; 4330 __le16 seq_id; 4331 __le16 resp_len; 4332 __le32 stat_ctx_id; 4333 u8 unused_0; 4334 u8 unused_1; 4335 u8 unused_2; 4336 u8 valid; 4337 }; 4338 4339 /* hwrm_stat_ctx_free */ 4340 /* Input (24 bytes) */ 4341 struct hwrm_stat_ctx_free_input { 4342 __le16 req_type; 4343 __le16 cmpl_ring; 4344 __le16 seq_id; 4345 __le16 target_id; 4346 __le64 resp_addr; 4347 __le32 stat_ctx_id; 4348 __le32 unused_0; 4349 }; 4350 4351 /* Output (16 bytes) */ 4352 struct hwrm_stat_ctx_free_output { 4353 __le16 error_code; 4354 __le16 req_type; 4355 __le16 seq_id; 4356 __le16 resp_len; 4357 __le32 stat_ctx_id; 4358 u8 unused_0; 4359 u8 unused_1; 4360 u8 unused_2; 4361 u8 valid; 4362 }; 4363 4364 /* hwrm_stat_ctx_query */ 4365 /* Input (24 bytes) */ 4366 struct hwrm_stat_ctx_query_input { 4367 __le16 req_type; 4368 __le16 cmpl_ring; 4369 __le16 seq_id; 4370 __le16 target_id; 4371 __le64 resp_addr; 4372 __le32 stat_ctx_id; 4373 __le32 unused_0; 4374 }; 4375 4376 /* Output (176 bytes) */ 4377 struct hwrm_stat_ctx_query_output { 4378 __le16 error_code; 4379 __le16 req_type; 4380 __le16 seq_id; 4381 __le16 resp_len; 4382 __le64 tx_ucast_pkts; 4383 __le64 tx_mcast_pkts; 4384 __le64 tx_bcast_pkts; 4385 __le64 tx_err_pkts; 4386 __le64 tx_drop_pkts; 4387 __le64 tx_ucast_bytes; 4388 __le64 tx_mcast_bytes; 4389 __le64 tx_bcast_bytes; 4390 __le64 rx_ucast_pkts; 4391 __le64 rx_mcast_pkts; 4392 __le64 rx_bcast_pkts; 4393 __le64 rx_err_pkts; 4394 __le64 rx_drop_pkts; 4395 __le64 rx_ucast_bytes; 4396 __le64 rx_mcast_bytes; 4397 __le64 rx_bcast_bytes; 4398 __le64 rx_agg_pkts; 4399 __le64 rx_agg_bytes; 4400 __le64 rx_agg_events; 4401 __le64 rx_agg_aborts; 4402 __le32 unused_0; 4403 u8 unused_1; 4404 u8 unused_2; 4405 u8 unused_3; 4406 u8 valid; 4407 }; 4408 4409 /* hwrm_stat_ctx_clr_stats */ 4410 /* Input (24 bytes) */ 4411 struct hwrm_stat_ctx_clr_stats_input { 4412 __le16 req_type; 4413 __le16 cmpl_ring; 4414 __le16 seq_id; 4415 __le16 target_id; 4416 __le64 resp_addr; 4417 __le32 stat_ctx_id; 4418 __le32 unused_0; 4419 }; 4420 4421 /* Output (16 bytes) */ 4422 struct hwrm_stat_ctx_clr_stats_output { 4423 __le16 error_code; 4424 __le16 req_type; 4425 __le16 seq_id; 4426 __le16 resp_len; 4427 __le32 unused_0; 4428 u8 unused_1; 4429 u8 unused_2; 4430 u8 unused_3; 4431 u8 valid; 4432 }; 4433 4434 /* hwrm_fw_reset */ 4435 /* Input (24 bytes) */ 4436 struct hwrm_fw_reset_input { 4437 __le16 req_type; 4438 __le16 cmpl_ring; 4439 __le16 seq_id; 4440 __le16 target_id; 4441 __le64 resp_addr; 4442 u8 embedded_proc_type; 4443 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4444 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4445 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4446 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4447 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 4448 u8 selfrst_status; 4449 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 4450 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 4451 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4452 __le16 unused_0[3]; 4453 }; 4454 4455 /* Output (16 bytes) */ 4456 struct hwrm_fw_reset_output { 4457 __le16 error_code; 4458 __le16 req_type; 4459 __le16 seq_id; 4460 __le16 resp_len; 4461 u8 selfrst_status; 4462 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4463 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4464 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4465 u8 unused_0; 4466 __le16 unused_1; 4467 u8 unused_2; 4468 u8 unused_3; 4469 u8 unused_4; 4470 u8 valid; 4471 }; 4472 4473 /* hwrm_fw_qstatus */ 4474 /* Input (24 bytes) */ 4475 struct hwrm_fw_qstatus_input { 4476 __le16 req_type; 4477 __le16 cmpl_ring; 4478 __le16 seq_id; 4479 __le16 target_id; 4480 __le64 resp_addr; 4481 u8 embedded_proc_type; 4482 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4483 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4484 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4485 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4486 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD 0x4UL 4487 u8 unused_0[7]; 4488 }; 4489 4490 /* Output (16 bytes) */ 4491 struct hwrm_fw_qstatus_output { 4492 __le16 error_code; 4493 __le16 req_type; 4494 __le16 seq_id; 4495 __le16 resp_len; 4496 u8 selfrst_status; 4497 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4498 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4499 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4500 u8 unused_0; 4501 __le16 unused_1; 4502 u8 unused_2; 4503 u8 unused_3; 4504 u8 unused_4; 4505 u8 valid; 4506 }; 4507 4508 /* hwrm_fw_set_time */ 4509 /* Input (32 bytes) */ 4510 struct hwrm_fw_set_time_input { 4511 __le16 req_type; 4512 __le16 cmpl_ring; 4513 __le16 seq_id; 4514 __le16 target_id; 4515 __le64 resp_addr; 4516 __le16 year; 4517 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4518 u8 month; 4519 u8 day; 4520 u8 hour; 4521 u8 minute; 4522 u8 second; 4523 u8 unused_0; 4524 __le16 millisecond; 4525 __le16 zone; 4526 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4527 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4528 __le32 unused_1; 4529 }; 4530 4531 /* Output (16 bytes) */ 4532 struct hwrm_fw_set_time_output { 4533 __le16 error_code; 4534 __le16 req_type; 4535 __le16 seq_id; 4536 __le16 resp_len; 4537 __le32 unused_0; 4538 u8 unused_1; 4539 u8 unused_2; 4540 u8 unused_3; 4541 u8 valid; 4542 }; 4543 4544 /* hwrm_fw_set_structured_data */ 4545 /* Input (32 bytes) */ 4546 struct hwrm_fw_set_structured_data_input { 4547 __le16 req_type; 4548 __le16 cmpl_ring; 4549 __le16 seq_id; 4550 __le16 target_id; 4551 __le64 resp_addr; 4552 __le64 src_data_addr; 4553 __le16 data_len; 4554 u8 hdr_cnt; 4555 u8 unused_0[5]; 4556 }; 4557 4558 /* Output (16 bytes) */ 4559 struct hwrm_fw_set_structured_data_output { 4560 __le16 error_code; 4561 __le16 req_type; 4562 __le16 seq_id; 4563 __le16 resp_len; 4564 __le32 unused_0; 4565 u8 unused_1; 4566 u8 unused_2; 4567 u8 unused_3; 4568 u8 valid; 4569 }; 4570 4571 /* hwrm_fw_get_structured_data */ 4572 /* Input (32 bytes) */ 4573 struct hwrm_fw_get_structured_data_input { 4574 __le16 req_type; 4575 __le16 cmpl_ring; 4576 __le16 seq_id; 4577 __le16 target_id; 4578 __le64 resp_addr; 4579 __le64 dest_data_addr; 4580 __le16 data_len; 4581 __le16 structure_id; 4582 __le16 subtype; 4583 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 4584 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 4585 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 4586 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 4587 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 4588 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 4589 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 4590 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 4591 u8 count; 4592 u8 unused_0; 4593 }; 4594 4595 /* Output (16 bytes) */ 4596 struct hwrm_fw_get_structured_data_output { 4597 __le16 error_code; 4598 __le16 req_type; 4599 __le16 seq_id; 4600 __le16 resp_len; 4601 u8 hdr_cnt; 4602 u8 unused_0; 4603 __le16 unused_1; 4604 u8 unused_2; 4605 u8 unused_3; 4606 u8 unused_4; 4607 u8 valid; 4608 }; 4609 4610 /* hwrm_exec_fwd_resp */ 4611 /* Input (128 bytes) */ 4612 struct hwrm_exec_fwd_resp_input { 4613 __le16 req_type; 4614 __le16 cmpl_ring; 4615 __le16 seq_id; 4616 __le16 target_id; 4617 __le64 resp_addr; 4618 __le32 encap_request[26]; 4619 __le16 encap_resp_target_id; 4620 __le16 unused_0[3]; 4621 }; 4622 4623 /* Output (16 bytes) */ 4624 struct hwrm_exec_fwd_resp_output { 4625 __le16 error_code; 4626 __le16 req_type; 4627 __le16 seq_id; 4628 __le16 resp_len; 4629 __le32 unused_0; 4630 u8 unused_1; 4631 u8 unused_2; 4632 u8 unused_3; 4633 u8 valid; 4634 }; 4635 4636 /* hwrm_reject_fwd_resp */ 4637 /* Input (128 bytes) */ 4638 struct hwrm_reject_fwd_resp_input { 4639 __le16 req_type; 4640 __le16 cmpl_ring; 4641 __le16 seq_id; 4642 __le16 target_id; 4643 __le64 resp_addr; 4644 __le32 encap_request[26]; 4645 __le16 encap_resp_target_id; 4646 __le16 unused_0[3]; 4647 }; 4648 4649 /* Output (16 bytes) */ 4650 struct hwrm_reject_fwd_resp_output { 4651 __le16 error_code; 4652 __le16 req_type; 4653 __le16 seq_id; 4654 __le16 resp_len; 4655 __le32 unused_0; 4656 u8 unused_1; 4657 u8 unused_2; 4658 u8 unused_3; 4659 u8 valid; 4660 }; 4661 4662 /* hwrm_fwd_resp */ 4663 /* Input (40 bytes) */ 4664 struct hwrm_fwd_resp_input { 4665 __le16 req_type; 4666 __le16 cmpl_ring; 4667 __le16 seq_id; 4668 __le16 target_id; 4669 __le64 resp_addr; 4670 __le16 encap_resp_target_id; 4671 __le16 encap_resp_cmpl_ring; 4672 __le16 encap_resp_len; 4673 u8 unused_0; 4674 u8 unused_1; 4675 __le64 encap_resp_addr; 4676 __le32 encap_resp[24]; 4677 }; 4678 4679 /* Output (16 bytes) */ 4680 struct hwrm_fwd_resp_output { 4681 __le16 error_code; 4682 __le16 req_type; 4683 __le16 seq_id; 4684 __le16 resp_len; 4685 __le32 unused_0; 4686 u8 unused_1; 4687 u8 unused_2; 4688 u8 unused_3; 4689 u8 valid; 4690 }; 4691 4692 /* hwrm_fwd_async_event_cmpl */ 4693 /* Input (32 bytes) */ 4694 struct hwrm_fwd_async_event_cmpl_input { 4695 __le16 req_type; 4696 __le16 cmpl_ring; 4697 __le16 seq_id; 4698 __le16 target_id; 4699 __le64 resp_addr; 4700 __le16 encap_async_event_target_id; 4701 u8 unused_0; 4702 u8 unused_1; 4703 u8 unused_2[3]; 4704 u8 unused_3; 4705 __le32 encap_async_event_cmpl[4]; 4706 }; 4707 4708 /* Output (16 bytes) */ 4709 struct hwrm_fwd_async_event_cmpl_output { 4710 __le16 error_code; 4711 __le16 req_type; 4712 __le16 seq_id; 4713 __le16 resp_len; 4714 __le32 unused_0; 4715 u8 unused_1; 4716 u8 unused_2; 4717 u8 unused_3; 4718 u8 valid; 4719 }; 4720 4721 /* hwrm_temp_monitor_query */ 4722 /* Input (16 bytes) */ 4723 struct hwrm_temp_monitor_query_input { 4724 __le16 req_type; 4725 __le16 cmpl_ring; 4726 __le16 seq_id; 4727 __le16 target_id; 4728 __le64 resp_addr; 4729 }; 4730 4731 /* Output (16 bytes) */ 4732 struct hwrm_temp_monitor_query_output { 4733 __le16 error_code; 4734 __le16 req_type; 4735 __le16 seq_id; 4736 __le16 resp_len; 4737 u8 temp; 4738 u8 unused_0; 4739 __le16 unused_1; 4740 u8 unused_2; 4741 u8 unused_3; 4742 u8 unused_4; 4743 u8 valid; 4744 }; 4745 4746 /* hwrm_nvm_read */ 4747 /* Input (40 bytes) */ 4748 struct hwrm_nvm_read_input { 4749 __le16 req_type; 4750 __le16 cmpl_ring; 4751 __le16 seq_id; 4752 __le16 target_id; 4753 __le64 resp_addr; 4754 __le64 host_dest_addr; 4755 __le16 dir_idx; 4756 u8 unused_0; 4757 u8 unused_1; 4758 __le32 offset; 4759 __le32 len; 4760 __le32 unused_2; 4761 }; 4762 4763 /* Output (16 bytes) */ 4764 struct hwrm_nvm_read_output { 4765 __le16 error_code; 4766 __le16 req_type; 4767 __le16 seq_id; 4768 __le16 resp_len; 4769 __le32 unused_0; 4770 u8 unused_1; 4771 u8 unused_2; 4772 u8 unused_3; 4773 u8 valid; 4774 }; 4775 4776 /* hwrm_nvm_raw_dump */ 4777 /* Input (32 bytes) */ 4778 struct hwrm_nvm_raw_dump_input { 4779 __le16 req_type; 4780 __le16 cmpl_ring; 4781 __le16 seq_id; 4782 __le16 target_id; 4783 __le64 resp_addr; 4784 __le64 host_dest_addr; 4785 __le32 offset; 4786 __le32 len; 4787 }; 4788 4789 /* Output (16 bytes) */ 4790 struct hwrm_nvm_raw_dump_output { 4791 __le16 error_code; 4792 __le16 req_type; 4793 __le16 seq_id; 4794 __le16 resp_len; 4795 __le32 unused_0; 4796 u8 unused_1; 4797 u8 unused_2; 4798 u8 unused_3; 4799 u8 valid; 4800 }; 4801 4802 /* hwrm_nvm_get_dir_entries */ 4803 /* Input (24 bytes) */ 4804 struct hwrm_nvm_get_dir_entries_input { 4805 __le16 req_type; 4806 __le16 cmpl_ring; 4807 __le16 seq_id; 4808 __le16 target_id; 4809 __le64 resp_addr; 4810 __le64 host_dest_addr; 4811 }; 4812 4813 /* Output (16 bytes) */ 4814 struct hwrm_nvm_get_dir_entries_output { 4815 __le16 error_code; 4816 __le16 req_type; 4817 __le16 seq_id; 4818 __le16 resp_len; 4819 __le32 unused_0; 4820 u8 unused_1; 4821 u8 unused_2; 4822 u8 unused_3; 4823 u8 valid; 4824 }; 4825 4826 /* hwrm_nvm_get_dir_info */ 4827 /* Input (16 bytes) */ 4828 struct hwrm_nvm_get_dir_info_input { 4829 __le16 req_type; 4830 __le16 cmpl_ring; 4831 __le16 seq_id; 4832 __le16 target_id; 4833 __le64 resp_addr; 4834 }; 4835 4836 /* Output (24 bytes) */ 4837 struct hwrm_nvm_get_dir_info_output { 4838 __le16 error_code; 4839 __le16 req_type; 4840 __le16 seq_id; 4841 __le16 resp_len; 4842 __le32 entries; 4843 __le32 entry_length; 4844 __le32 unused_0; 4845 u8 unused_1; 4846 u8 unused_2; 4847 u8 unused_3; 4848 u8 valid; 4849 }; 4850 4851 /* hwrm_nvm_write */ 4852 /* Input (48 bytes) */ 4853 struct hwrm_nvm_write_input { 4854 __le16 req_type; 4855 __le16 cmpl_ring; 4856 __le16 seq_id; 4857 __le16 target_id; 4858 __le64 resp_addr; 4859 __le64 host_src_addr; 4860 __le16 dir_type; 4861 __le16 dir_ordinal; 4862 __le16 dir_ext; 4863 __le16 dir_attr; 4864 __le32 dir_data_length; 4865 __le16 option; 4866 __le16 flags; 4867 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 4868 __le32 dir_item_length; 4869 __le32 unused_0; 4870 }; 4871 4872 /* Output (16 bytes) */ 4873 struct hwrm_nvm_write_output { 4874 __le16 error_code; 4875 __le16 req_type; 4876 __le16 seq_id; 4877 __le16 resp_len; 4878 __le32 dir_item_length; 4879 __le16 dir_idx; 4880 u8 unused_0; 4881 u8 valid; 4882 }; 4883 4884 /* hwrm_nvm_modify */ 4885 /* Input (40 bytes) */ 4886 struct hwrm_nvm_modify_input { 4887 __le16 req_type; 4888 __le16 cmpl_ring; 4889 __le16 seq_id; 4890 __le16 target_id; 4891 __le64 resp_addr; 4892 __le64 host_src_addr; 4893 __le16 dir_idx; 4894 u8 unused_0; 4895 u8 unused_1; 4896 __le32 offset; 4897 __le32 len; 4898 __le32 unused_2; 4899 }; 4900 4901 /* Output (16 bytes) */ 4902 struct hwrm_nvm_modify_output { 4903 __le16 error_code; 4904 __le16 req_type; 4905 __le16 seq_id; 4906 __le16 resp_len; 4907 __le32 unused_0; 4908 u8 unused_1; 4909 u8 unused_2; 4910 u8 unused_3; 4911 u8 valid; 4912 }; 4913 4914 /* hwrm_nvm_find_dir_entry */ 4915 /* Input (32 bytes) */ 4916 struct hwrm_nvm_find_dir_entry_input { 4917 __le16 req_type; 4918 __le16 cmpl_ring; 4919 __le16 seq_id; 4920 __le16 target_id; 4921 __le64 resp_addr; 4922 __le32 enables; 4923 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 4924 __le16 dir_idx; 4925 __le16 dir_type; 4926 __le16 dir_ordinal; 4927 __le16 dir_ext; 4928 u8 opt_ordinal; 4929 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 4930 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 4931 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 4932 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 4933 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 4934 u8 unused_1[3]; 4935 }; 4936 4937 /* Output (32 bytes) */ 4938 struct hwrm_nvm_find_dir_entry_output { 4939 __le16 error_code; 4940 __le16 req_type; 4941 __le16 seq_id; 4942 __le16 resp_len; 4943 __le32 dir_item_length; 4944 __le32 dir_data_length; 4945 __le32 fw_ver; 4946 __le16 dir_ordinal; 4947 __le16 dir_idx; 4948 __le32 unused_0; 4949 u8 unused_1; 4950 u8 unused_2; 4951 u8 unused_3; 4952 u8 valid; 4953 }; 4954 4955 /* hwrm_nvm_erase_dir_entry */ 4956 /* Input (24 bytes) */ 4957 struct hwrm_nvm_erase_dir_entry_input { 4958 __le16 req_type; 4959 __le16 cmpl_ring; 4960 __le16 seq_id; 4961 __le16 target_id; 4962 __le64 resp_addr; 4963 __le16 dir_idx; 4964 __le16 unused_0[3]; 4965 }; 4966 4967 /* Output (16 bytes) */ 4968 struct hwrm_nvm_erase_dir_entry_output { 4969 __le16 error_code; 4970 __le16 req_type; 4971 __le16 seq_id; 4972 __le16 resp_len; 4973 __le32 unused_0; 4974 u8 unused_1; 4975 u8 unused_2; 4976 u8 unused_3; 4977 u8 valid; 4978 }; 4979 4980 /* hwrm_nvm_get_dev_info */ 4981 /* Input (16 bytes) */ 4982 struct hwrm_nvm_get_dev_info_input { 4983 __le16 req_type; 4984 __le16 cmpl_ring; 4985 __le16 seq_id; 4986 __le16 target_id; 4987 __le64 resp_addr; 4988 }; 4989 4990 /* Output (32 bytes) */ 4991 struct hwrm_nvm_get_dev_info_output { 4992 __le16 error_code; 4993 __le16 req_type; 4994 __le16 seq_id; 4995 __le16 resp_len; 4996 __le16 manufacturer_id; 4997 __le16 device_id; 4998 __le32 sector_size; 4999 __le32 nvram_size; 5000 __le32 reserved_size; 5001 __le32 available_size; 5002 u8 unused_0; 5003 u8 unused_1; 5004 u8 unused_2; 5005 u8 valid; 5006 }; 5007 5008 /* hwrm_nvm_mod_dir_entry */ 5009 /* Input (32 bytes) */ 5010 struct hwrm_nvm_mod_dir_entry_input { 5011 __le16 req_type; 5012 __le16 cmpl_ring; 5013 __le16 seq_id; 5014 __le16 target_id; 5015 __le64 resp_addr; 5016 __le32 enables; 5017 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 5018 __le16 dir_idx; 5019 __le16 dir_ordinal; 5020 __le16 dir_ext; 5021 __le16 dir_attr; 5022 __le32 checksum; 5023 }; 5024 5025 /* Output (16 bytes) */ 5026 struct hwrm_nvm_mod_dir_entry_output { 5027 __le16 error_code; 5028 __le16 req_type; 5029 __le16 seq_id; 5030 __le16 resp_len; 5031 __le32 unused_0; 5032 u8 unused_1; 5033 u8 unused_2; 5034 u8 unused_3; 5035 u8 valid; 5036 }; 5037 5038 /* hwrm_nvm_verify_update */ 5039 /* Input (24 bytes) */ 5040 struct hwrm_nvm_verify_update_input { 5041 __le16 req_type; 5042 __le16 cmpl_ring; 5043 __le16 seq_id; 5044 __le16 target_id; 5045 __le64 resp_addr; 5046 __le16 dir_type; 5047 __le16 dir_ordinal; 5048 __le16 dir_ext; 5049 __le16 unused_0; 5050 }; 5051 5052 /* Output (16 bytes) */ 5053 struct hwrm_nvm_verify_update_output { 5054 __le16 error_code; 5055 __le16 req_type; 5056 __le16 seq_id; 5057 __le16 resp_len; 5058 __le32 unused_0; 5059 u8 unused_1; 5060 u8 unused_2; 5061 u8 unused_3; 5062 u8 valid; 5063 }; 5064 5065 /* hwrm_nvm_install_update */ 5066 /* Input (24 bytes) */ 5067 struct hwrm_nvm_install_update_input { 5068 __le16 req_type; 5069 __le16 cmpl_ring; 5070 __le16 seq_id; 5071 __le16 target_id; 5072 __le64 resp_addr; 5073 __le32 install_type; 5074 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 5075 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 5076 __le16 flags; 5077 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 5078 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 5079 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 5080 __le16 unused_0; 5081 }; 5082 5083 /* Output (24 bytes) */ 5084 struct hwrm_nvm_install_update_output { 5085 __le16 error_code; 5086 __le16 req_type; 5087 __le16 seq_id; 5088 __le16 resp_len; 5089 __le64 installed_items; 5090 u8 result; 5091 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 5092 u8 problem_item; 5093 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 5094 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 5095 u8 reset_required; 5096 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 5097 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 5098 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 5099 u8 unused_0; 5100 u8 unused_1; 5101 u8 unused_2; 5102 u8 unused_3; 5103 u8 valid; 5104 }; 5105 5106 /* Command specific Error Codes (8 bytes) */ 5107 struct hwrm_nvm_install_update_cmd_err { 5108 u8 code; 5109 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 5110 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5111 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 5112 u8 unused_0[7]; 5113 }; 5114 5115 /* Hardware Resource Manager Specification */ 5116 /* Input (16 bytes) */ 5117 struct input { 5118 __le16 req_type; 5119 __le16 cmpl_ring; 5120 __le16 seq_id; 5121 __le16 target_id; 5122 __le64 resp_addr; 5123 }; 5124 5125 /* Output (8 bytes) */ 5126 struct output { 5127 __le16 error_code; 5128 __le16 req_type; 5129 __le16 seq_id; 5130 __le16 resp_len; 5131 }; 5132 5133 /* Command numbering (8 bytes) */ 5134 struct cmd_nums { 5135 __le16 req_type; 5136 #define HWRM_VER_GET (0x0UL) 5137 #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 5138 #define HWRM_FUNC_VF_CFG (0xfUL) 5139 #define RESERVED1 (0x10UL) 5140 #define HWRM_FUNC_RESET (0x11UL) 5141 #define HWRM_FUNC_GETFID (0x12UL) 5142 #define HWRM_FUNC_VF_ALLOC (0x13UL) 5143 #define HWRM_FUNC_VF_FREE (0x14UL) 5144 #define HWRM_FUNC_QCAPS (0x15UL) 5145 #define HWRM_FUNC_QCFG (0x16UL) 5146 #define HWRM_FUNC_CFG (0x17UL) 5147 #define HWRM_FUNC_QSTATS (0x18UL) 5148 #define HWRM_FUNC_CLR_STATS (0x19UL) 5149 #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 5150 #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 5151 #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 5152 #define HWRM_FUNC_DRV_RGTR (0x1dUL) 5153 #define HWRM_FUNC_DRV_QVER (0x1eUL) 5154 #define HWRM_FUNC_BUF_RGTR (0x1fUL) 5155 #define HWRM_PORT_PHY_CFG (0x20UL) 5156 #define HWRM_PORT_MAC_CFG (0x21UL) 5157 #define HWRM_PORT_TS_QUERY (0x22UL) 5158 #define HWRM_PORT_QSTATS (0x23UL) 5159 #define HWRM_PORT_LPBK_QSTATS (0x24UL) 5160 #define HWRM_PORT_CLR_STATS (0x25UL) 5161 #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 5162 #define HWRM_PORT_PHY_QCFG (0x27UL) 5163 #define HWRM_PORT_MAC_QCFG (0x28UL) 5164 #define RESERVED7 (0x29UL) 5165 #define HWRM_PORT_PHY_QCAPS (0x2aUL) 5166 #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 5167 #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 5168 #define HWRM_PORT_LED_CFG (0x2dUL) 5169 #define HWRM_PORT_LED_QCFG (0x2eUL) 5170 #define HWRM_PORT_LED_QCAPS (0x2fUL) 5171 #define HWRM_QUEUE_QPORTCFG (0x30UL) 5172 #define HWRM_QUEUE_QCFG (0x31UL) 5173 #define HWRM_QUEUE_CFG (0x32UL) 5174 #define RESERVED2 (0x33UL) 5175 #define RESERVED3 (0x34UL) 5176 #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 5177 #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 5178 #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 5179 #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 5180 #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 5181 #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 5182 #define HWRM_VNIC_ALLOC (0x40UL) 5183 #define HWRM_VNIC_FREE (0x41UL) 5184 #define HWRM_VNIC_CFG (0x42UL) 5185 #define HWRM_VNIC_QCFG (0x43UL) 5186 #define HWRM_VNIC_TPA_CFG (0x44UL) 5187 #define HWRM_VNIC_TPA_QCFG (0x45UL) 5188 #define HWRM_VNIC_RSS_CFG (0x46UL) 5189 #define HWRM_VNIC_RSS_QCFG (0x47UL) 5190 #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 5191 #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 5192 #define HWRM_VNIC_QCAPS (0x4aUL) 5193 #define HWRM_RING_ALLOC (0x50UL) 5194 #define HWRM_RING_FREE (0x51UL) 5195 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 5196 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 5197 #define HWRM_RING_RESET (0x5eUL) 5198 #define HWRM_RING_GRP_ALLOC (0x60UL) 5199 #define HWRM_RING_GRP_FREE (0x61UL) 5200 #define RESERVED5 (0x64UL) 5201 #define RESERVED6 (0x65UL) 5202 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 5203 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 5204 #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 5205 #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 5206 #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 5207 #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 5208 #define RESERVED4 (0x94UL) 5209 #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 5210 #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 5211 #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 5212 #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 5213 #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 5214 #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 5215 #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 5216 #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 5217 #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 5218 #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 5219 #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 5220 #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 5221 #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 5222 #define HWRM_STAT_CTX_ALLOC (0xb0UL) 5223 #define HWRM_STAT_CTX_FREE (0xb1UL) 5224 #define HWRM_STAT_CTX_QUERY (0xb2UL) 5225 #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 5226 #define HWRM_FW_RESET (0xc0UL) 5227 #define HWRM_FW_QSTATUS (0xc1UL) 5228 #define HWRM_FW_SET_TIME (0xc8UL) 5229 #define HWRM_FW_GET_TIME (0xc9UL) 5230 #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 5231 #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 5232 #define HWRM_FW_IPC_MAILBOX (0xccUL) 5233 #define HWRM_EXEC_FWD_RESP (0xd0UL) 5234 #define HWRM_REJECT_FWD_RESP (0xd1UL) 5235 #define HWRM_FWD_RESP (0xd2UL) 5236 #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 5237 #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 5238 #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 5239 #define HWRM_WOL_FILTER_FREE (0xf1UL) 5240 #define HWRM_WOL_FILTER_QCFG (0xf2UL) 5241 #define HWRM_WOL_REASON_QCFG (0xf3UL) 5242 #define HWRM_CFA_METER_PROFILE_ALLOC (0xf5UL) 5243 #define HWRM_CFA_METER_PROFILE_FREE (0xf6UL) 5244 #define HWRM_CFA_METER_PROFILE_CFG (0xf7UL) 5245 #define HWRM_CFA_METER_INSTANCE_ALLOC (0xf8UL) 5246 #define HWRM_CFA_METER_INSTANCE_FREE (0xf9UL) 5247 #define HWRM_CFA_VF_PAIR_ALLOC (0x100UL) 5248 #define HWRM_CFA_VF_PAIR_FREE (0x101UL) 5249 #define HWRM_CFA_VF_PAIR_INFO (0x102UL) 5250 #define HWRM_CFA_FLOW_ALLOC (0x103UL) 5251 #define HWRM_CFA_FLOW_FREE (0x104UL) 5252 #define HWRM_CFA_FLOW_FLUSH (0x105UL) 5253 #define HWRM_CFA_FLOW_STATS (0x106UL) 5254 #define HWRM_CFA_FLOW_INFO (0x107UL) 5255 #define HWRM_DBG_READ_DIRECT (0xff10UL) 5256 #define HWRM_DBG_READ_INDIRECT (0xff11UL) 5257 #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 5258 #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 5259 #define HWRM_DBG_DUMP (0xff14UL) 5260 #define HWRM_NVM_VALIDATE_OPTION (0xffefUL) 5261 #define HWRM_NVM_FLUSH (0xfff0UL) 5262 #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 5263 #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 5264 #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 5265 #define HWRM_NVM_MODIFY (0xfff4UL) 5266 #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 5267 #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 5268 #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 5269 #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 5270 #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 5271 #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 5272 #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 5273 #define HWRM_NVM_RAW_DUMP (0xfffcUL) 5274 #define HWRM_NVM_READ (0xfffdUL) 5275 #define HWRM_NVM_WRITE (0xfffeUL) 5276 #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 5277 __le16 unused_0[3]; 5278 }; 5279 5280 /* Return Codes (8 bytes) */ 5281 struct ret_codes { 5282 __le16 error_code; 5283 #define HWRM_ERR_CODE_SUCCESS (0x0UL) 5284 #define HWRM_ERR_CODE_FAIL (0x1UL) 5285 #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 5286 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 5287 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 5288 #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 5289 #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 5290 #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 5291 #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 5292 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 5293 __le16 unused_0[3]; 5294 }; 5295 5296 /* Output (16 bytes) */ 5297 struct hwrm_err_output { 5298 __le16 error_code; 5299 __le16 req_type; 5300 __le16 seq_id; 5301 __le16 resp_len; 5302 __le32 opaque_0; 5303 __le16 opaque_1; 5304 u8 cmd_err; 5305 u8 valid; 5306 }; 5307 5308 /* Port Tx Statistics Formats (408 bytes) */ 5309 struct tx_port_stats { 5310 __le64 tx_64b_frames; 5311 __le64 tx_65b_127b_frames; 5312 __le64 tx_128b_255b_frames; 5313 __le64 tx_256b_511b_frames; 5314 __le64 tx_512b_1023b_frames; 5315 __le64 tx_1024b_1518_frames; 5316 __le64 tx_good_vlan_frames; 5317 __le64 tx_1519b_2047_frames; 5318 __le64 tx_2048b_4095b_frames; 5319 __le64 tx_4096b_9216b_frames; 5320 __le64 tx_9217b_16383b_frames; 5321 __le64 tx_good_frames; 5322 __le64 tx_total_frames; 5323 __le64 tx_ucast_frames; 5324 __le64 tx_mcast_frames; 5325 __le64 tx_bcast_frames; 5326 __le64 tx_pause_frames; 5327 __le64 tx_pfc_frames; 5328 __le64 tx_jabber_frames; 5329 __le64 tx_fcs_err_frames; 5330 __le64 tx_control_frames; 5331 __le64 tx_oversz_frames; 5332 __le64 tx_single_dfrl_frames; 5333 __le64 tx_multi_dfrl_frames; 5334 __le64 tx_single_coll_frames; 5335 __le64 tx_multi_coll_frames; 5336 __le64 tx_late_coll_frames; 5337 __le64 tx_excessive_coll_frames; 5338 __le64 tx_frag_frames; 5339 __le64 tx_err; 5340 __le64 tx_tagged_frames; 5341 __le64 tx_dbl_tagged_frames; 5342 __le64 tx_runt_frames; 5343 __le64 tx_fifo_underruns; 5344 __le64 tx_pfc_ena_frames_pri0; 5345 __le64 tx_pfc_ena_frames_pri1; 5346 __le64 tx_pfc_ena_frames_pri2; 5347 __le64 tx_pfc_ena_frames_pri3; 5348 __le64 tx_pfc_ena_frames_pri4; 5349 __le64 tx_pfc_ena_frames_pri5; 5350 __le64 tx_pfc_ena_frames_pri6; 5351 __le64 tx_pfc_ena_frames_pri7; 5352 __le64 tx_eee_lpi_events; 5353 __le64 tx_eee_lpi_duration; 5354 __le64 tx_llfc_logical_msgs; 5355 __le64 tx_hcfc_msgs; 5356 __le64 tx_total_collisions; 5357 __le64 tx_bytes; 5358 __le64 tx_xthol_frames; 5359 __le64 tx_stat_discard; 5360 __le64 tx_stat_error; 5361 }; 5362 5363 /* Port Rx Statistics Formats (528 bytes) */ 5364 struct rx_port_stats { 5365 __le64 rx_64b_frames; 5366 __le64 rx_65b_127b_frames; 5367 __le64 rx_128b_255b_frames; 5368 __le64 rx_256b_511b_frames; 5369 __le64 rx_512b_1023b_frames; 5370 __le64 rx_1024b_1518_frames; 5371 __le64 rx_good_vlan_frames; 5372 __le64 rx_1519b_2047b_frames; 5373 __le64 rx_2048b_4095b_frames; 5374 __le64 rx_4096b_9216b_frames; 5375 __le64 rx_9217b_16383b_frames; 5376 __le64 rx_total_frames; 5377 __le64 rx_ucast_frames; 5378 __le64 rx_mcast_frames; 5379 __le64 rx_bcast_frames; 5380 __le64 rx_fcs_err_frames; 5381 __le64 rx_ctrl_frames; 5382 __le64 rx_pause_frames; 5383 __le64 rx_pfc_frames; 5384 __le64 rx_unsupported_opcode_frames; 5385 __le64 rx_unsupported_da_pausepfc_frames; 5386 __le64 rx_wrong_sa_frames; 5387 __le64 rx_align_err_frames; 5388 __le64 rx_oor_len_frames; 5389 __le64 rx_code_err_frames; 5390 __le64 rx_false_carrier_frames; 5391 __le64 rx_ovrsz_frames; 5392 __le64 rx_jbr_frames; 5393 __le64 rx_mtu_err_frames; 5394 __le64 rx_match_crc_frames; 5395 __le64 rx_promiscuous_frames; 5396 __le64 rx_tagged_frames; 5397 __le64 rx_double_tagged_frames; 5398 __le64 rx_trunc_frames; 5399 __le64 rx_good_frames; 5400 __le64 rx_pfc_xon2xoff_frames_pri0; 5401 __le64 rx_pfc_xon2xoff_frames_pri1; 5402 __le64 rx_pfc_xon2xoff_frames_pri2; 5403 __le64 rx_pfc_xon2xoff_frames_pri3; 5404 __le64 rx_pfc_xon2xoff_frames_pri4; 5405 __le64 rx_pfc_xon2xoff_frames_pri5; 5406 __le64 rx_pfc_xon2xoff_frames_pri6; 5407 __le64 rx_pfc_xon2xoff_frames_pri7; 5408 __le64 rx_pfc_ena_frames_pri0; 5409 __le64 rx_pfc_ena_frames_pri1; 5410 __le64 rx_pfc_ena_frames_pri2; 5411 __le64 rx_pfc_ena_frames_pri3; 5412 __le64 rx_pfc_ena_frames_pri4; 5413 __le64 rx_pfc_ena_frames_pri5; 5414 __le64 rx_pfc_ena_frames_pri6; 5415 __le64 rx_pfc_ena_frames_pri7; 5416 __le64 rx_sch_crc_err_frames; 5417 __le64 rx_undrsz_frames; 5418 __le64 rx_frag_frames; 5419 __le64 rx_eee_lpi_events; 5420 __le64 rx_eee_lpi_duration; 5421 __le64 rx_llfc_physical_msgs; 5422 __le64 rx_llfc_logical_msgs; 5423 __le64 rx_llfc_msgs_with_crc_err; 5424 __le64 rx_hcfc_msgs; 5425 __le64 rx_hcfc_msgs_with_crc_err; 5426 __le64 rx_bytes; 5427 __le64 rx_runt_bytes; 5428 __le64 rx_runt_frames; 5429 __le64 rx_stat_discard; 5430 __le64 rx_stat_err; 5431 }; 5432 5433 /* Periodic Statistics Context DMA to host (160 bytes) */ 5434 struct ctx_hw_stats { 5435 __le64 rx_ucast_pkts; 5436 __le64 rx_mcast_pkts; 5437 __le64 rx_bcast_pkts; 5438 __le64 rx_discard_pkts; 5439 __le64 rx_drop_pkts; 5440 __le64 rx_ucast_bytes; 5441 __le64 rx_mcast_bytes; 5442 __le64 rx_bcast_bytes; 5443 __le64 tx_ucast_pkts; 5444 __le64 tx_mcast_pkts; 5445 __le64 tx_bcast_pkts; 5446 __le64 tx_discard_pkts; 5447 __le64 tx_drop_pkts; 5448 __le64 tx_ucast_bytes; 5449 __le64 tx_mcast_bytes; 5450 __le64 tx_bcast_bytes; 5451 __le64 tpa_pkts; 5452 __le64 tpa_bytes; 5453 __le64 tpa_events; 5454 __le64 tpa_aborts; 5455 }; 5456 5457 /* Structure data header (16 bytes) */ 5458 struct hwrm_struct_hdr { 5459 __le16 struct_id; 5460 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 5461 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 5462 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 5463 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 5464 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 5465 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 5466 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 5467 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 5468 __le16 len; 5469 u8 version; 5470 u8 count; 5471 __le16 subtype; 5472 __le16 next_offset; 5473 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 5474 __le16 unused_0[3]; 5475 }; 5476 5477 /* DCBX Application configuration structure (1057) (8 bytes) */ 5478 struct hwrm_struct_data_dcbx_app { 5479 __be16 protocol_id; 5480 u8 protocol_selector; 5481 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 5482 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 5483 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 5484 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 5485 u8 priority; 5486 u8 valid; 5487 u8 unused_0[3]; 5488 }; 5489 5490 #endif 5491