1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2019 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * DO NOT MODIFY!!! This file is automatically generated. 11 */ 12 13 #ifndef _BNXT_HSI_H_ 14 #define _BNXT_HSI_H_ 15 16 /* hwrm_cmd_hdr (size:128b/16B) */ 17 struct hwrm_cmd_hdr { 18 __le16 req_type; 19 __le16 cmpl_ring; 20 __le16 seq_id; 21 __le16 target_id; 22 __le64 resp_addr; 23 }; 24 25 /* hwrm_resp_hdr (size:64b/8B) */ 26 struct hwrm_resp_hdr { 27 __le16 error_code; 28 __le16 req_type; 29 __le16 seq_id; 30 __le16 resp_len; 31 }; 32 33 #define CMD_DISCR_TLV_ENCAP 0x8000UL 34 #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 35 36 37 #define TLV_TYPE_HWRM_REQUEST 0x1UL 38 #define TLV_TYPE_HWRM_RESPONSE 0x2UL 39 #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 40 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 41 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 42 #define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL 43 #define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL 44 #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45 #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46 #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 47 #define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 48 #define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL 49 #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 50 #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 51 52 53 /* tlv (size:64b/8B) */ 54 struct tlv { 55 __le16 cmd_discr; 56 u8 reserved_8b; 57 u8 flags; 58 #define TLV_FLAGS_MORE 0x1UL 59 #define TLV_FLAGS_MORE_LAST 0x0UL 60 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 61 #define TLV_FLAGS_REQUIRED 0x2UL 62 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 63 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 64 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 65 __le16 tlv_type; 66 __le16 length; 67 }; 68 69 /* input (size:128b/16B) */ 70 struct input { 71 __le16 req_type; 72 __le16 cmpl_ring; 73 __le16 seq_id; 74 __le16 target_id; 75 __le64 resp_addr; 76 }; 77 78 /* output (size:64b/8B) */ 79 struct output { 80 __le16 error_code; 81 __le16 req_type; 82 __le16 seq_id; 83 __le16 resp_len; 84 }; 85 86 /* hwrm_short_input (size:128b/16B) */ 87 struct hwrm_short_input { 88 __le16 req_type; 89 __le16 signature; 90 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 91 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 92 __le16 unused_0; 93 __le16 size; 94 __le64 req_addr; 95 }; 96 97 /* cmd_nums (size:64b/8B) */ 98 struct cmd_nums { 99 __le16 req_type; 100 #define HWRM_VER_GET 0x0UL 101 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 102 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 103 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 104 #define HWRM_FUNC_VF_CFG 0xfUL 105 #define HWRM_RESERVED1 0x10UL 106 #define HWRM_FUNC_RESET 0x11UL 107 #define HWRM_FUNC_GETFID 0x12UL 108 #define HWRM_FUNC_VF_ALLOC 0x13UL 109 #define HWRM_FUNC_VF_FREE 0x14UL 110 #define HWRM_FUNC_QCAPS 0x15UL 111 #define HWRM_FUNC_QCFG 0x16UL 112 #define HWRM_FUNC_CFG 0x17UL 113 #define HWRM_FUNC_QSTATS 0x18UL 114 #define HWRM_FUNC_CLR_STATS 0x19UL 115 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 116 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 117 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 118 #define HWRM_FUNC_DRV_RGTR 0x1dUL 119 #define HWRM_FUNC_DRV_QVER 0x1eUL 120 #define HWRM_FUNC_BUF_RGTR 0x1fUL 121 #define HWRM_PORT_PHY_CFG 0x20UL 122 #define HWRM_PORT_MAC_CFG 0x21UL 123 #define HWRM_PORT_TS_QUERY 0x22UL 124 #define HWRM_PORT_QSTATS 0x23UL 125 #define HWRM_PORT_LPBK_QSTATS 0x24UL 126 #define HWRM_PORT_CLR_STATS 0x25UL 127 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 128 #define HWRM_PORT_PHY_QCFG 0x27UL 129 #define HWRM_PORT_MAC_QCFG 0x28UL 130 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 131 #define HWRM_PORT_PHY_QCAPS 0x2aUL 132 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 133 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 134 #define HWRM_PORT_LED_CFG 0x2dUL 135 #define HWRM_PORT_LED_QCFG 0x2eUL 136 #define HWRM_PORT_LED_QCAPS 0x2fUL 137 #define HWRM_QUEUE_QPORTCFG 0x30UL 138 #define HWRM_QUEUE_QCFG 0x31UL 139 #define HWRM_QUEUE_CFG 0x32UL 140 #define HWRM_FUNC_VLAN_CFG 0x33UL 141 #define HWRM_FUNC_VLAN_QCFG 0x34UL 142 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 143 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 144 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 145 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 146 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 147 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 148 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 149 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 150 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 151 #define HWRM_VNIC_ALLOC 0x40UL 152 #define HWRM_VNIC_FREE 0x41UL 153 #define HWRM_VNIC_CFG 0x42UL 154 #define HWRM_VNIC_QCFG 0x43UL 155 #define HWRM_VNIC_TPA_CFG 0x44UL 156 #define HWRM_VNIC_TPA_QCFG 0x45UL 157 #define HWRM_VNIC_RSS_CFG 0x46UL 158 #define HWRM_VNIC_RSS_QCFG 0x47UL 159 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 160 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 161 #define HWRM_VNIC_QCAPS 0x4aUL 162 #define HWRM_RING_ALLOC 0x50UL 163 #define HWRM_RING_FREE 0x51UL 164 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 165 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 166 #define HWRM_RING_AGGINT_QCAPS 0x54UL 167 #define HWRM_RING_RESET 0x5eUL 168 #define HWRM_RING_GRP_ALLOC 0x60UL 169 #define HWRM_RING_GRP_FREE 0x61UL 170 #define HWRM_RESERVED5 0x64UL 171 #define HWRM_RESERVED6 0x65UL 172 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 173 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 174 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 175 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 176 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 177 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 178 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 179 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 180 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 181 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 182 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 183 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 184 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 185 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 186 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 187 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 188 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 189 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 190 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 191 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 192 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 193 #define HWRM_STAT_CTX_ALLOC 0xb0UL 194 #define HWRM_STAT_CTX_FREE 0xb1UL 195 #define HWRM_STAT_CTX_QUERY 0xb2UL 196 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 197 #define HWRM_PORT_QSTATS_EXT 0xb4UL 198 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 199 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 200 #define HWRM_FW_RESET 0xc0UL 201 #define HWRM_FW_QSTATUS 0xc1UL 202 #define HWRM_FW_HEALTH_CHECK 0xc2UL 203 #define HWRM_FW_SYNC 0xc3UL 204 #define HWRM_FW_SET_TIME 0xc8UL 205 #define HWRM_FW_GET_TIME 0xc9UL 206 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 207 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 208 #define HWRM_FW_IPC_MAILBOX 0xccUL 209 #define HWRM_EXEC_FWD_RESP 0xd0UL 210 #define HWRM_REJECT_FWD_RESP 0xd1UL 211 #define HWRM_FWD_RESP 0xd2UL 212 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 213 #define HWRM_OEM_CMD 0xd4UL 214 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 215 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 216 #define HWRM_WOL_FILTER_FREE 0xf1UL 217 #define HWRM_WOL_FILTER_QCFG 0xf2UL 218 #define HWRM_WOL_REASON_QCFG 0xf3UL 219 #define HWRM_CFA_METER_QCAPS 0xf4UL 220 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 221 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 222 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 223 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 224 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 225 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 226 #define HWRM_CFA_VFR_ALLOC 0xfdUL 227 #define HWRM_CFA_VFR_FREE 0xfeUL 228 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 229 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 230 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 231 #define HWRM_CFA_FLOW_ALLOC 0x103UL 232 #define HWRM_CFA_FLOW_FREE 0x104UL 233 #define HWRM_CFA_FLOW_FLUSH 0x105UL 234 #define HWRM_CFA_FLOW_STATS 0x106UL 235 #define HWRM_CFA_FLOW_INFO 0x107UL 236 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 237 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 238 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 239 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 240 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 241 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 242 #define HWRM_CFA_PAIR_FREE 0x10eUL 243 #define HWRM_CFA_PAIR_INFO 0x10fUL 244 #define HWRM_FW_IPC_MSG 0x110UL 245 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 246 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 247 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 248 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 249 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 250 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 251 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 252 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 253 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 254 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 255 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 256 #define HWRM_CFA_COUNTER_CFG 0x11cUL 257 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 258 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 259 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 260 #define HWRM_CFA_EEM_QCAPS 0x120UL 261 #define HWRM_CFA_EEM_CFG 0x121UL 262 #define HWRM_CFA_EEM_QCFG 0x122UL 263 #define HWRM_CFA_EEM_OP 0x123UL 264 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 265 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 266 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 267 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 268 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 269 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 270 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 271 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 272 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 273 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 274 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 275 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 276 #define HWRM_ENGINE_QG_QUERY 0x13dUL 277 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 278 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 279 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 280 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 281 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 282 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 283 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 284 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 285 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 286 #define HWRM_ENGINE_SG_QUERY 0x147UL 287 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 288 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 289 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 290 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 291 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 292 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 293 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 294 #define HWRM_ENGINE_STATS_QUERY 0x157UL 295 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 296 #define HWRM_ENGINE_RQ_FREE 0x15fUL 297 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 298 #define HWRM_ENGINE_CQ_FREE 0x161UL 299 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 300 #define HWRM_ENGINE_NQ_FREE 0x163UL 301 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 302 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 303 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 304 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 305 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 306 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 307 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 308 #define HWRM_FUNC_VF_BW_CFG 0x195UL 309 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 310 #define HWRM_SELFTEST_QLIST 0x200UL 311 #define HWRM_SELFTEST_EXEC 0x201UL 312 #define HWRM_SELFTEST_IRQ 0x202UL 313 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 314 #define HWRM_PCIE_QSTATS 0x204UL 315 #define HWRM_DBG_READ_DIRECT 0xff10UL 316 #define HWRM_DBG_READ_INDIRECT 0xff11UL 317 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 318 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 319 #define HWRM_DBG_DUMP 0xff14UL 320 #define HWRM_DBG_ERASE_NVM 0xff15UL 321 #define HWRM_DBG_CFG 0xff16UL 322 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 323 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 324 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 325 #define HWRM_DBG_FW_CLI 0xff1aUL 326 #define HWRM_DBG_I2C_CMD 0xff1bUL 327 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 328 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 329 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 330 #define HWRM_NVM_FLUSH 0xfff0UL 331 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 332 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 333 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 334 #define HWRM_NVM_MODIFY 0xfff4UL 335 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 336 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 337 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 338 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 339 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 340 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 341 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 342 #define HWRM_NVM_RAW_DUMP 0xfffcUL 343 #define HWRM_NVM_READ 0xfffdUL 344 #define HWRM_NVM_WRITE 0xfffeUL 345 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 346 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 347 __le16 unused_0[3]; 348 }; 349 350 /* ret_codes (size:64b/8B) */ 351 struct ret_codes { 352 __le16 error_code; 353 #define HWRM_ERR_CODE_SUCCESS 0x0UL 354 #define HWRM_ERR_CODE_FAIL 0x1UL 355 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 356 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 357 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 358 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 359 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 360 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 361 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 362 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 363 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 364 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 365 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 366 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 367 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 368 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 369 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 370 __le16 unused_0[3]; 371 }; 372 373 /* hwrm_err_output (size:128b/16B) */ 374 struct hwrm_err_output { 375 __le16 error_code; 376 __le16 req_type; 377 __le16 seq_id; 378 __le16 resp_len; 379 __le32 opaque_0; 380 __le16 opaque_1; 381 u8 cmd_err; 382 u8 valid; 383 }; 384 #define HWRM_NA_SIGNATURE ((__le32)(-1)) 385 #define HWRM_MAX_REQ_LEN 128 386 #define HWRM_MAX_RESP_LEN 704 387 #define HW_HASH_INDEX_SIZE 0x80 388 #define HW_HASH_KEY_SIZE 40 389 #define HWRM_RESP_VALID_KEY 1 390 #define HWRM_VERSION_MAJOR 1 391 #define HWRM_VERSION_MINOR 10 392 #define HWRM_VERSION_UPDATE 0 393 #define HWRM_VERSION_RSVD 47 394 #define HWRM_VERSION_STR "1.10.0.47" 395 396 /* hwrm_ver_get_input (size:192b/24B) */ 397 struct hwrm_ver_get_input { 398 __le16 req_type; 399 __le16 cmpl_ring; 400 __le16 seq_id; 401 __le16 target_id; 402 __le64 resp_addr; 403 u8 hwrm_intf_maj; 404 u8 hwrm_intf_min; 405 u8 hwrm_intf_upd; 406 u8 unused_0[5]; 407 }; 408 409 /* hwrm_ver_get_output (size:1408b/176B) */ 410 struct hwrm_ver_get_output { 411 __le16 error_code; 412 __le16 req_type; 413 __le16 seq_id; 414 __le16 resp_len; 415 u8 hwrm_intf_maj_8b; 416 u8 hwrm_intf_min_8b; 417 u8 hwrm_intf_upd_8b; 418 u8 hwrm_intf_rsvd_8b; 419 u8 hwrm_fw_maj_8b; 420 u8 hwrm_fw_min_8b; 421 u8 hwrm_fw_bld_8b; 422 u8 hwrm_fw_rsvd_8b; 423 u8 mgmt_fw_maj_8b; 424 u8 mgmt_fw_min_8b; 425 u8 mgmt_fw_bld_8b; 426 u8 mgmt_fw_rsvd_8b; 427 u8 netctrl_fw_maj_8b; 428 u8 netctrl_fw_min_8b; 429 u8 netctrl_fw_bld_8b; 430 u8 netctrl_fw_rsvd_8b; 431 __le32 dev_caps_cfg; 432 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 433 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 434 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 435 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 436 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 437 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 438 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 439 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 440 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 441 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 442 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 443 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 444 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 445 u8 roce_fw_maj_8b; 446 u8 roce_fw_min_8b; 447 u8 roce_fw_bld_8b; 448 u8 roce_fw_rsvd_8b; 449 char hwrm_fw_name[16]; 450 char mgmt_fw_name[16]; 451 char netctrl_fw_name[16]; 452 u8 reserved2[16]; 453 char roce_fw_name[16]; 454 __le16 chip_num; 455 u8 chip_rev; 456 u8 chip_metal; 457 u8 chip_bond_id; 458 u8 chip_platform_type; 459 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 460 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 461 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 462 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 463 __le16 max_req_win_len; 464 __le16 max_resp_len; 465 __le16 def_req_timeout; 466 u8 flags; 467 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 468 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 469 u8 unused_0[2]; 470 u8 always_1; 471 __le16 hwrm_intf_major; 472 __le16 hwrm_intf_minor; 473 __le16 hwrm_intf_build; 474 __le16 hwrm_intf_patch; 475 __le16 hwrm_fw_major; 476 __le16 hwrm_fw_minor; 477 __le16 hwrm_fw_build; 478 __le16 hwrm_fw_patch; 479 __le16 mgmt_fw_major; 480 __le16 mgmt_fw_minor; 481 __le16 mgmt_fw_build; 482 __le16 mgmt_fw_patch; 483 __le16 netctrl_fw_major; 484 __le16 netctrl_fw_minor; 485 __le16 netctrl_fw_build; 486 __le16 netctrl_fw_patch; 487 __le16 roce_fw_major; 488 __le16 roce_fw_minor; 489 __le16 roce_fw_build; 490 __le16 roce_fw_patch; 491 __le16 max_ext_req_len; 492 u8 unused_1[5]; 493 u8 valid; 494 }; 495 496 /* eject_cmpl (size:128b/16B) */ 497 struct eject_cmpl { 498 __le16 type; 499 #define EJECT_CMPL_TYPE_MASK 0x3fUL 500 #define EJECT_CMPL_TYPE_SFT 0 501 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 502 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 503 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 504 #define EJECT_CMPL_FLAGS_SFT 6 505 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 506 __le16 len; 507 __le32 opaque; 508 __le16 v; 509 #define EJECT_CMPL_V 0x1UL 510 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 511 #define EJECT_CMPL_ERRORS_SFT 1 512 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 513 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 514 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 515 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 516 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 517 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 518 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 519 __le16 reserved16; 520 __le32 unused_2; 521 }; 522 523 /* hwrm_cmpl (size:128b/16B) */ 524 struct hwrm_cmpl { 525 __le16 type; 526 #define CMPL_TYPE_MASK 0x3fUL 527 #define CMPL_TYPE_SFT 0 528 #define CMPL_TYPE_HWRM_DONE 0x20UL 529 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 530 __le16 sequence_id; 531 __le32 unused_1; 532 __le32 v; 533 #define CMPL_V 0x1UL 534 __le32 unused_3; 535 }; 536 537 /* hwrm_fwd_req_cmpl (size:128b/16B) */ 538 struct hwrm_fwd_req_cmpl { 539 __le16 req_len_type; 540 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 541 #define FWD_REQ_CMPL_TYPE_SFT 0 542 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 543 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 544 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 545 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 546 __le16 source_id; 547 __le32 unused0; 548 __le32 req_buf_addr_v[2]; 549 #define FWD_REQ_CMPL_V 0x1UL 550 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 551 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 552 }; 553 554 /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 555 struct hwrm_fwd_resp_cmpl { 556 __le16 type; 557 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 558 #define FWD_RESP_CMPL_TYPE_SFT 0 559 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 560 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 561 __le16 source_id; 562 __le16 resp_len; 563 __le16 unused_1; 564 __le32 resp_buf_addr_v[2]; 565 #define FWD_RESP_CMPL_V 0x1UL 566 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 567 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 568 }; 569 570 /* hwrm_async_event_cmpl (size:128b/16B) */ 571 struct hwrm_async_event_cmpl { 572 __le16 type; 573 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 574 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 575 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 576 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 577 __le16 event_id; 578 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 579 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 580 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 581 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 582 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 583 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 584 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 585 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 586 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 587 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 588 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 589 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 590 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 591 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 592 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 593 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 594 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 595 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 596 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 597 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 598 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 599 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 600 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 601 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 602 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 603 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 604 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 605 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 606 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 607 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 608 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 609 __le32 event_data2; 610 u8 opaque_v; 611 #define ASYNC_EVENT_CMPL_V 0x1UL 612 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 613 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 614 u8 timestamp_lo; 615 __le16 timestamp_hi; 616 __le32 event_data1; 617 }; 618 619 /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 620 struct hwrm_async_event_cmpl_link_status_change { 621 __le16 type; 622 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 623 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 624 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 625 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 626 __le16 event_id; 627 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 628 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 629 __le32 event_data2; 630 u8 opaque_v; 631 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 632 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 633 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 634 u8 timestamp_lo; 635 __le16 timestamp_hi; 636 __le32 event_data1; 637 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 638 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 639 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 640 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 641 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 642 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 643 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 644 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 645 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 646 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 647 }; 648 649 /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 650 struct hwrm_async_event_cmpl_port_conn_not_allowed { 651 __le16 type; 652 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 653 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 654 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 655 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 656 __le16 event_id; 657 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 658 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 659 __le32 event_data2; 660 u8 opaque_v; 661 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 662 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 663 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 664 u8 timestamp_lo; 665 __le16 timestamp_hi; 666 __le32 event_data1; 667 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 668 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 669 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 670 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 671 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 672 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 673 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 674 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 675 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 676 }; 677 678 /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 679 struct hwrm_async_event_cmpl_link_speed_cfg_change { 680 __le16 type; 681 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 682 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 683 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 684 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 685 __le16 event_id; 686 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 687 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 688 __le32 event_data2; 689 u8 opaque_v; 690 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 691 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 692 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 693 u8 timestamp_lo; 694 __le16 timestamp_hi; 695 __le32 event_data1; 696 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 697 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 698 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 699 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 700 }; 701 702 /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 703 struct hwrm_async_event_cmpl_reset_notify { 704 __le16 type; 705 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 706 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 707 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 708 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 709 __le16 event_id; 710 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 711 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 712 __le32 event_data2; 713 u8 opaque_v; 714 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 715 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 716 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 717 u8 timestamp_lo; 718 __le16 timestamp_hi; 719 __le32 event_data1; 720 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 721 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 722 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 723 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 724 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 725 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 726 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 727 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 728 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 729 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 730 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 731 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 732 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 733 }; 734 735 /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 736 struct hwrm_async_event_cmpl_error_recovery { 737 __le16 type; 738 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 739 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 740 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 741 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 742 __le16 event_id; 743 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 744 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 745 __le32 event_data2; 746 u8 opaque_v; 747 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 748 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 749 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 750 u8 timestamp_lo; 751 __le16 timestamp_hi; 752 __le32 event_data1; 753 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 754 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 755 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 756 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 757 }; 758 759 /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 760 struct hwrm_async_event_cmpl_vf_cfg_change { 761 __le16 type; 762 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 763 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 764 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 765 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 766 __le16 event_id; 767 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 768 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 769 __le32 event_data2; 770 u8 opaque_v; 771 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 772 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 773 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 774 u8 timestamp_lo; 775 __le16 timestamp_hi; 776 __le32 event_data1; 777 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 778 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 779 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 780 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 781 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 782 }; 783 784 /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 785 struct hwrm_async_event_cmpl_hw_flow_aged { 786 __le16 type; 787 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 788 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 789 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 790 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 791 __le16 event_id; 792 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 793 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 794 __le32 event_data2; 795 u8 opaque_v; 796 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 797 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 798 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 799 u8 timestamp_lo; 800 __le16 timestamp_hi; 801 __le32 event_data1; 802 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 803 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 804 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 805 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 806 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 807 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 808 }; 809 810 /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 811 struct hwrm_async_event_cmpl_eem_cache_flush_req { 812 __le16 type; 813 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 814 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 815 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 816 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 817 __le16 event_id; 818 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 819 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 820 __le32 event_data2; 821 u8 opaque_v; 822 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 823 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 824 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 825 u8 timestamp_lo; 826 __le16 timestamp_hi; 827 __le32 event_data1; 828 }; 829 830 /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 831 struct hwrm_async_event_cmpl_eem_cache_flush_done { 832 __le16 type; 833 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 834 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 835 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 836 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 837 __le16 event_id; 838 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 839 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 840 __le32 event_data2; 841 u8 opaque_v; 842 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 843 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 844 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 845 u8 timestamp_lo; 846 __le16 timestamp_hi; 847 __le32 event_data1; 848 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 849 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 850 }; 851 852 /* hwrm_func_reset_input (size:192b/24B) */ 853 struct hwrm_func_reset_input { 854 __le16 req_type; 855 __le16 cmpl_ring; 856 __le16 seq_id; 857 __le16 target_id; 858 __le64 resp_addr; 859 __le32 enables; 860 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 861 __le16 vf_id; 862 u8 func_reset_level; 863 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 864 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 865 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 866 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 867 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 868 u8 unused_0; 869 }; 870 871 /* hwrm_func_reset_output (size:128b/16B) */ 872 struct hwrm_func_reset_output { 873 __le16 error_code; 874 __le16 req_type; 875 __le16 seq_id; 876 __le16 resp_len; 877 u8 unused_0[7]; 878 u8 valid; 879 }; 880 881 /* hwrm_func_getfid_input (size:192b/24B) */ 882 struct hwrm_func_getfid_input { 883 __le16 req_type; 884 __le16 cmpl_ring; 885 __le16 seq_id; 886 __le16 target_id; 887 __le64 resp_addr; 888 __le32 enables; 889 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 890 __le16 pci_id; 891 u8 unused_0[2]; 892 }; 893 894 /* hwrm_func_getfid_output (size:128b/16B) */ 895 struct hwrm_func_getfid_output { 896 __le16 error_code; 897 __le16 req_type; 898 __le16 seq_id; 899 __le16 resp_len; 900 __le16 fid; 901 u8 unused_0[5]; 902 u8 valid; 903 }; 904 905 /* hwrm_func_vf_alloc_input (size:192b/24B) */ 906 struct hwrm_func_vf_alloc_input { 907 __le16 req_type; 908 __le16 cmpl_ring; 909 __le16 seq_id; 910 __le16 target_id; 911 __le64 resp_addr; 912 __le32 enables; 913 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 914 __le16 first_vf_id; 915 __le16 num_vfs; 916 }; 917 918 /* hwrm_func_vf_alloc_output (size:128b/16B) */ 919 struct hwrm_func_vf_alloc_output { 920 __le16 error_code; 921 __le16 req_type; 922 __le16 seq_id; 923 __le16 resp_len; 924 __le16 first_vf_id; 925 u8 unused_0[5]; 926 u8 valid; 927 }; 928 929 /* hwrm_func_vf_free_input (size:192b/24B) */ 930 struct hwrm_func_vf_free_input { 931 __le16 req_type; 932 __le16 cmpl_ring; 933 __le16 seq_id; 934 __le16 target_id; 935 __le64 resp_addr; 936 __le32 enables; 937 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 938 __le16 first_vf_id; 939 __le16 num_vfs; 940 }; 941 942 /* hwrm_func_vf_free_output (size:128b/16B) */ 943 struct hwrm_func_vf_free_output { 944 __le16 error_code; 945 __le16 req_type; 946 __le16 seq_id; 947 __le16 resp_len; 948 u8 unused_0[7]; 949 u8 valid; 950 }; 951 952 /* hwrm_func_vf_cfg_input (size:448b/56B) */ 953 struct hwrm_func_vf_cfg_input { 954 __le16 req_type; 955 __le16 cmpl_ring; 956 __le16 seq_id; 957 __le16 target_id; 958 __le64 resp_addr; 959 __le32 enables; 960 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 961 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 962 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 963 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 964 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 965 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 966 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 967 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 968 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 969 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 970 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 971 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 972 __le16 mtu; 973 __le16 guest_vlan; 974 __le16 async_event_cr; 975 u8 dflt_mac_addr[6]; 976 __le32 flags; 977 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 978 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 979 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 980 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 981 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 982 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 983 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 984 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 985 __le16 num_rsscos_ctxs; 986 __le16 num_cmpl_rings; 987 __le16 num_tx_rings; 988 __le16 num_rx_rings; 989 __le16 num_l2_ctxs; 990 __le16 num_vnics; 991 __le16 num_stat_ctxs; 992 __le16 num_hw_ring_grps; 993 u8 unused_0[4]; 994 }; 995 996 /* hwrm_func_vf_cfg_output (size:128b/16B) */ 997 struct hwrm_func_vf_cfg_output { 998 __le16 error_code; 999 __le16 req_type; 1000 __le16 seq_id; 1001 __le16 resp_len; 1002 u8 unused_0[7]; 1003 u8 valid; 1004 }; 1005 1006 /* hwrm_func_qcaps_input (size:192b/24B) */ 1007 struct hwrm_func_qcaps_input { 1008 __le16 req_type; 1009 __le16 cmpl_ring; 1010 __le16 seq_id; 1011 __le16 target_id; 1012 __le64 resp_addr; 1013 __le16 fid; 1014 u8 unused_0[6]; 1015 }; 1016 1017 /* hwrm_func_qcaps_output (size:640b/80B) */ 1018 struct hwrm_func_qcaps_output { 1019 __le16 error_code; 1020 __le16 req_type; 1021 __le16 seq_id; 1022 __le16 resp_len; 1023 __le16 fid; 1024 __le16 port_id; 1025 __le32 flags; 1026 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1027 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1028 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1029 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1030 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1031 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1032 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1033 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1034 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1035 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1036 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1037 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1038 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1039 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1040 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1041 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1042 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1043 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1044 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1045 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1046 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1047 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1048 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1049 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1050 u8 mac_address[6]; 1051 __le16 max_rsscos_ctx; 1052 __le16 max_cmpl_rings; 1053 __le16 max_tx_rings; 1054 __le16 max_rx_rings; 1055 __le16 max_l2_ctxs; 1056 __le16 max_vnics; 1057 __le16 first_vf_id; 1058 __le16 max_vfs; 1059 __le16 max_stat_ctx; 1060 __le32 max_encap_records; 1061 __le32 max_decap_records; 1062 __le32 max_tx_em_flows; 1063 __le32 max_tx_wm_flows; 1064 __le32 max_rx_em_flows; 1065 __le32 max_rx_wm_flows; 1066 __le32 max_mcast_filters; 1067 __le32 max_flow_id; 1068 __le32 max_hw_ring_grps; 1069 __le16 max_sp_tx_rings; 1070 u8 unused_0; 1071 u8 valid; 1072 }; 1073 1074 /* hwrm_func_qcfg_input (size:192b/24B) */ 1075 struct hwrm_func_qcfg_input { 1076 __le16 req_type; 1077 __le16 cmpl_ring; 1078 __le16 seq_id; 1079 __le16 target_id; 1080 __le64 resp_addr; 1081 __le16 fid; 1082 u8 unused_0[6]; 1083 }; 1084 1085 /* hwrm_func_qcfg_output (size:704b/88B) */ 1086 struct hwrm_func_qcfg_output { 1087 __le16 error_code; 1088 __le16 req_type; 1089 __le16 seq_id; 1090 __le16 resp_len; 1091 __le16 fid; 1092 __le16 port_id; 1093 __le16 vlan; 1094 __le16 flags; 1095 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1096 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1097 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1098 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1099 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1100 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1101 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1102 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1103 u8 mac_address[6]; 1104 __le16 pci_id; 1105 __le16 alloc_rsscos_ctx; 1106 __le16 alloc_cmpl_rings; 1107 __le16 alloc_tx_rings; 1108 __le16 alloc_rx_rings; 1109 __le16 alloc_l2_ctx; 1110 __le16 alloc_vnics; 1111 __le16 mtu; 1112 __le16 mru; 1113 __le16 stat_ctx_id; 1114 u8 port_partition_type; 1115 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1116 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1117 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1118 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1119 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1120 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1121 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 1122 u8 port_pf_cnt; 1123 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1124 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 1125 __le16 dflt_vnic_id; 1126 __le16 max_mtu_configured; 1127 __le32 min_bw; 1128 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1129 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1130 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1131 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1132 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1133 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1134 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1135 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1136 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1137 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1138 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1139 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1140 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1141 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1142 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 1143 __le32 max_bw; 1144 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1145 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1146 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1147 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1148 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1149 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1150 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1151 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1152 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1153 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1154 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1155 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1156 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1157 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1158 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 1159 u8 evb_mode; 1160 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1161 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1162 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1163 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1164 u8 options; 1165 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1166 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1167 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1168 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1169 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 1170 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1171 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 1172 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1173 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1174 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1175 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 1176 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 1177 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1178 __le16 alloc_vfs; 1179 __le32 alloc_mcast_filters; 1180 __le32 alloc_hw_ring_grps; 1181 __le16 alloc_sp_tx_rings; 1182 __le16 alloc_stat_ctx; 1183 __le16 alloc_msix; 1184 __le16 registered_vfs; 1185 u8 unused_1[3]; 1186 u8 always_1; 1187 __le32 reset_addr_poll; 1188 u8 unused_2[3]; 1189 u8 valid; 1190 }; 1191 1192 /* hwrm_func_cfg_input (size:704b/88B) */ 1193 struct hwrm_func_cfg_input { 1194 __le16 req_type; 1195 __le16 cmpl_ring; 1196 __le16 seq_id; 1197 __le16 target_id; 1198 __le64 resp_addr; 1199 __le16 fid; 1200 __le16 num_msix; 1201 __le32 flags; 1202 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1203 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1204 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1205 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1206 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1207 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1208 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1209 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1210 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1211 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1212 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1213 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1214 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1215 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1216 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1217 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1218 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 1219 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 1220 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 1221 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 1222 __le32 enables; 1223 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1224 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1225 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1226 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1227 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1228 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1229 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1230 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1231 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1232 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1233 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1234 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1235 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1236 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1237 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1238 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1239 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1240 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1241 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1242 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1243 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1244 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 1245 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1246 __le16 mtu; 1247 __le16 mru; 1248 __le16 num_rsscos_ctxs; 1249 __le16 num_cmpl_rings; 1250 __le16 num_tx_rings; 1251 __le16 num_rx_rings; 1252 __le16 num_l2_ctxs; 1253 __le16 num_vnics; 1254 __le16 num_stat_ctxs; 1255 __le16 num_hw_ring_grps; 1256 u8 dflt_mac_addr[6]; 1257 __le16 dflt_vlan; 1258 __be32 dflt_ip_addr[4]; 1259 __le32 min_bw; 1260 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1261 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1262 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1263 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1264 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1265 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1266 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1267 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1268 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1269 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1270 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1271 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1272 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1273 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1274 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1275 __le32 max_bw; 1276 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1277 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1278 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1279 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1280 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1281 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1282 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1283 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1284 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1285 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1286 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1287 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1288 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1289 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1290 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1291 __le16 async_event_cr; 1292 u8 vlan_antispoof_mode; 1293 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1294 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1295 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1296 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1297 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1298 u8 allowed_vlan_pris; 1299 u8 evb_mode; 1300 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1301 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1302 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1303 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1304 u8 options; 1305 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1306 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1307 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1308 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1309 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1310 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 1311 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 1312 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 1313 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 1314 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 1315 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 1316 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 1317 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1318 __le16 num_mcast_filters; 1319 }; 1320 1321 /* hwrm_func_cfg_output (size:128b/16B) */ 1322 struct hwrm_func_cfg_output { 1323 __le16 error_code; 1324 __le16 req_type; 1325 __le16 seq_id; 1326 __le16 resp_len; 1327 u8 unused_0[7]; 1328 u8 valid; 1329 }; 1330 1331 /* hwrm_func_qstats_input (size:192b/24B) */ 1332 struct hwrm_func_qstats_input { 1333 __le16 req_type; 1334 __le16 cmpl_ring; 1335 __le16 seq_id; 1336 __le16 target_id; 1337 __le64 resp_addr; 1338 __le16 fid; 1339 u8 unused_0[6]; 1340 }; 1341 1342 /* hwrm_func_qstats_output (size:1408b/176B) */ 1343 struct hwrm_func_qstats_output { 1344 __le16 error_code; 1345 __le16 req_type; 1346 __le16 seq_id; 1347 __le16 resp_len; 1348 __le64 tx_ucast_pkts; 1349 __le64 tx_mcast_pkts; 1350 __le64 tx_bcast_pkts; 1351 __le64 tx_discard_pkts; 1352 __le64 tx_drop_pkts; 1353 __le64 tx_ucast_bytes; 1354 __le64 tx_mcast_bytes; 1355 __le64 tx_bcast_bytes; 1356 __le64 rx_ucast_pkts; 1357 __le64 rx_mcast_pkts; 1358 __le64 rx_bcast_pkts; 1359 __le64 rx_discard_pkts; 1360 __le64 rx_drop_pkts; 1361 __le64 rx_ucast_bytes; 1362 __le64 rx_mcast_bytes; 1363 __le64 rx_bcast_bytes; 1364 __le64 rx_agg_pkts; 1365 __le64 rx_agg_bytes; 1366 __le64 rx_agg_events; 1367 __le64 rx_agg_aborts; 1368 u8 unused_0[7]; 1369 u8 valid; 1370 }; 1371 1372 /* hwrm_func_clr_stats_input (size:192b/24B) */ 1373 struct hwrm_func_clr_stats_input { 1374 __le16 req_type; 1375 __le16 cmpl_ring; 1376 __le16 seq_id; 1377 __le16 target_id; 1378 __le64 resp_addr; 1379 __le16 fid; 1380 u8 unused_0[6]; 1381 }; 1382 1383 /* hwrm_func_clr_stats_output (size:128b/16B) */ 1384 struct hwrm_func_clr_stats_output { 1385 __le16 error_code; 1386 __le16 req_type; 1387 __le16 seq_id; 1388 __le16 resp_len; 1389 u8 unused_0[7]; 1390 u8 valid; 1391 }; 1392 1393 /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1394 struct hwrm_func_vf_resc_free_input { 1395 __le16 req_type; 1396 __le16 cmpl_ring; 1397 __le16 seq_id; 1398 __le16 target_id; 1399 __le64 resp_addr; 1400 __le16 vf_id; 1401 u8 unused_0[6]; 1402 }; 1403 1404 /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1405 struct hwrm_func_vf_resc_free_output { 1406 __le16 error_code; 1407 __le16 req_type; 1408 __le16 seq_id; 1409 __le16 resp_len; 1410 u8 unused_0[7]; 1411 u8 valid; 1412 }; 1413 1414 /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1415 struct hwrm_func_drv_rgtr_input { 1416 __le16 req_type; 1417 __le16 cmpl_ring; 1418 __le16 seq_id; 1419 __le16 target_id; 1420 __le64 resp_addr; 1421 __le32 flags; 1422 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1423 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1424 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1425 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 1426 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1427 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1428 __le32 enables; 1429 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1430 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1431 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1432 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1433 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1434 __le16 os_type; 1435 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1436 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1437 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1438 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1439 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1440 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1441 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1442 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1443 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1444 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1445 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1446 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1447 u8 ver_maj_8b; 1448 u8 ver_min_8b; 1449 u8 ver_upd_8b; 1450 u8 unused_0[3]; 1451 __le32 timestamp; 1452 u8 unused_1[4]; 1453 __le32 vf_req_fwd[8]; 1454 __le32 async_event_fwd[8]; 1455 __le16 ver_maj; 1456 __le16 ver_min; 1457 __le16 ver_upd; 1458 __le16 ver_patch; 1459 }; 1460 1461 /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1462 struct hwrm_func_drv_rgtr_output { 1463 __le16 error_code; 1464 __le16 req_type; 1465 __le16 seq_id; 1466 __le16 resp_len; 1467 __le32 flags; 1468 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 1469 u8 unused_0[3]; 1470 u8 valid; 1471 }; 1472 1473 /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1474 struct hwrm_func_drv_unrgtr_input { 1475 __le16 req_type; 1476 __le16 cmpl_ring; 1477 __le16 seq_id; 1478 __le16 target_id; 1479 __le64 resp_addr; 1480 __le32 flags; 1481 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1482 u8 unused_0[4]; 1483 }; 1484 1485 /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1486 struct hwrm_func_drv_unrgtr_output { 1487 __le16 error_code; 1488 __le16 req_type; 1489 __le16 seq_id; 1490 __le16 resp_len; 1491 u8 unused_0[7]; 1492 u8 valid; 1493 }; 1494 1495 /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1496 struct hwrm_func_buf_rgtr_input { 1497 __le16 req_type; 1498 __le16 cmpl_ring; 1499 __le16 seq_id; 1500 __le16 target_id; 1501 __le64 resp_addr; 1502 __le32 enables; 1503 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1504 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1505 __le16 vf_id; 1506 __le16 req_buf_num_pages; 1507 __le16 req_buf_page_size; 1508 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1509 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1510 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1511 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1512 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1513 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1514 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1515 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1516 __le16 req_buf_len; 1517 __le16 resp_buf_len; 1518 u8 unused_0[2]; 1519 __le64 req_buf_page_addr0; 1520 __le64 req_buf_page_addr1; 1521 __le64 req_buf_page_addr2; 1522 __le64 req_buf_page_addr3; 1523 __le64 req_buf_page_addr4; 1524 __le64 req_buf_page_addr5; 1525 __le64 req_buf_page_addr6; 1526 __le64 req_buf_page_addr7; 1527 __le64 req_buf_page_addr8; 1528 __le64 req_buf_page_addr9; 1529 __le64 error_buf_addr; 1530 __le64 resp_buf_addr; 1531 }; 1532 1533 /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1534 struct hwrm_func_buf_rgtr_output { 1535 __le16 error_code; 1536 __le16 req_type; 1537 __le16 seq_id; 1538 __le16 resp_len; 1539 u8 unused_0[7]; 1540 u8 valid; 1541 }; 1542 1543 /* hwrm_func_drv_qver_input (size:192b/24B) */ 1544 struct hwrm_func_drv_qver_input { 1545 __le16 req_type; 1546 __le16 cmpl_ring; 1547 __le16 seq_id; 1548 __le16 target_id; 1549 __le64 resp_addr; 1550 __le32 reserved; 1551 __le16 fid; 1552 u8 unused_0[2]; 1553 }; 1554 1555 /* hwrm_func_drv_qver_output (size:256b/32B) */ 1556 struct hwrm_func_drv_qver_output { 1557 __le16 error_code; 1558 __le16 req_type; 1559 __le16 seq_id; 1560 __le16 resp_len; 1561 __le16 os_type; 1562 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1563 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1564 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1565 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1566 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1567 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1568 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1569 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1570 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1571 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1572 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1573 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1574 u8 ver_maj_8b; 1575 u8 ver_min_8b; 1576 u8 ver_upd_8b; 1577 u8 unused_0[3]; 1578 __le16 ver_maj; 1579 __le16 ver_min; 1580 __le16 ver_upd; 1581 __le16 ver_patch; 1582 u8 unused_1[7]; 1583 u8 valid; 1584 }; 1585 1586 /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1587 struct hwrm_func_resource_qcaps_input { 1588 __le16 req_type; 1589 __le16 cmpl_ring; 1590 __le16 seq_id; 1591 __le16 target_id; 1592 __le64 resp_addr; 1593 __le16 fid; 1594 u8 unused_0[6]; 1595 }; 1596 1597 /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1598 struct hwrm_func_resource_qcaps_output { 1599 __le16 error_code; 1600 __le16 req_type; 1601 __le16 seq_id; 1602 __le16 resp_len; 1603 __le16 max_vfs; 1604 __le16 max_msix; 1605 __le16 vf_reservation_strategy; 1606 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1607 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1608 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1609 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1610 __le16 min_rsscos_ctx; 1611 __le16 max_rsscos_ctx; 1612 __le16 min_cmpl_rings; 1613 __le16 max_cmpl_rings; 1614 __le16 min_tx_rings; 1615 __le16 max_tx_rings; 1616 __le16 min_rx_rings; 1617 __le16 max_rx_rings; 1618 __le16 min_l2_ctxs; 1619 __le16 max_l2_ctxs; 1620 __le16 min_vnics; 1621 __le16 max_vnics; 1622 __le16 min_stat_ctx; 1623 __le16 max_stat_ctx; 1624 __le16 min_hw_ring_grps; 1625 __le16 max_hw_ring_grps; 1626 __le16 max_tx_scheduler_inputs; 1627 __le16 flags; 1628 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 1629 u8 unused_0[5]; 1630 u8 valid; 1631 }; 1632 1633 /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1634 struct hwrm_func_vf_resource_cfg_input { 1635 __le16 req_type; 1636 __le16 cmpl_ring; 1637 __le16 seq_id; 1638 __le16 target_id; 1639 __le64 resp_addr; 1640 __le16 vf_id; 1641 __le16 max_msix; 1642 __le16 min_rsscos_ctx; 1643 __le16 max_rsscos_ctx; 1644 __le16 min_cmpl_rings; 1645 __le16 max_cmpl_rings; 1646 __le16 min_tx_rings; 1647 __le16 max_tx_rings; 1648 __le16 min_rx_rings; 1649 __le16 max_rx_rings; 1650 __le16 min_l2_ctxs; 1651 __le16 max_l2_ctxs; 1652 __le16 min_vnics; 1653 __le16 max_vnics; 1654 __le16 min_stat_ctx; 1655 __le16 max_stat_ctx; 1656 __le16 min_hw_ring_grps; 1657 __le16 max_hw_ring_grps; 1658 __le16 flags; 1659 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 1660 u8 unused_0[2]; 1661 }; 1662 1663 /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1664 struct hwrm_func_vf_resource_cfg_output { 1665 __le16 error_code; 1666 __le16 req_type; 1667 __le16 seq_id; 1668 __le16 resp_len; 1669 __le16 reserved_rsscos_ctx; 1670 __le16 reserved_cmpl_rings; 1671 __le16 reserved_tx_rings; 1672 __le16 reserved_rx_rings; 1673 __le16 reserved_l2_ctxs; 1674 __le16 reserved_vnics; 1675 __le16 reserved_stat_ctx; 1676 __le16 reserved_hw_ring_grps; 1677 u8 unused_0[7]; 1678 u8 valid; 1679 }; 1680 1681 /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 1682 struct hwrm_func_backing_store_qcaps_input { 1683 __le16 req_type; 1684 __le16 cmpl_ring; 1685 __le16 seq_id; 1686 __le16 target_id; 1687 __le64 resp_addr; 1688 }; 1689 1690 /* hwrm_func_backing_store_qcaps_output (size:576b/72B) */ 1691 struct hwrm_func_backing_store_qcaps_output { 1692 __le16 error_code; 1693 __le16 req_type; 1694 __le16 seq_id; 1695 __le16 resp_len; 1696 __le32 qp_max_entries; 1697 __le16 qp_min_qp1_entries; 1698 __le16 qp_max_l2_entries; 1699 __le16 qp_entry_size; 1700 __le16 srq_max_l2_entries; 1701 __le32 srq_max_entries; 1702 __le16 srq_entry_size; 1703 __le16 cq_max_l2_entries; 1704 __le32 cq_max_entries; 1705 __le16 cq_entry_size; 1706 __le16 vnic_max_vnic_entries; 1707 __le16 vnic_max_ring_table_entries; 1708 __le16 vnic_entry_size; 1709 __le32 stat_max_entries; 1710 __le16 stat_entry_size; 1711 __le16 tqm_entry_size; 1712 __le32 tqm_min_entries_per_ring; 1713 __le32 tqm_max_entries_per_ring; 1714 __le32 mrav_max_entries; 1715 __le16 mrav_entry_size; 1716 __le16 tim_entry_size; 1717 __le32 tim_max_entries; 1718 u8 unused_0[2]; 1719 u8 tqm_entries_multiple; 1720 u8 valid; 1721 }; 1722 1723 /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 1724 struct hwrm_func_backing_store_cfg_input { 1725 __le16 req_type; 1726 __le16 cmpl_ring; 1727 __le16 seq_id; 1728 __le16 target_id; 1729 __le64 resp_addr; 1730 __le32 flags; 1731 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 1732 __le32 enables; 1733 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 1734 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 1735 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 1736 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 1737 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 1738 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 1739 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 1740 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 1741 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 1742 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 1743 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 1744 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 1745 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 1746 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 1747 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 1748 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 1749 u8 qpc_pg_size_qpc_lvl; 1750 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 1751 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 1752 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 1753 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 1754 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 1755 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 1756 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 1757 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 1758 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 1759 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 1760 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 1761 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 1762 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 1763 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 1764 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 1765 u8 srq_pg_size_srq_lvl; 1766 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 1767 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 1768 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 1769 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 1770 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 1771 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 1772 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 1773 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 1774 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 1775 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 1776 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 1777 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 1778 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 1779 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 1780 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 1781 u8 cq_pg_size_cq_lvl; 1782 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 1783 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 1784 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 1785 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 1786 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 1787 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 1788 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 1789 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 1790 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 1791 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 1792 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 1793 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 1794 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 1795 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 1796 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 1797 u8 vnic_pg_size_vnic_lvl; 1798 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 1799 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 1800 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 1801 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 1802 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 1803 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 1804 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 1805 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 1806 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 1807 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 1808 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 1809 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 1810 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 1811 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 1812 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 1813 u8 stat_pg_size_stat_lvl; 1814 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 1815 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 1816 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 1817 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 1818 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 1819 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 1820 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 1821 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 1822 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 1823 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 1824 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 1825 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 1826 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 1827 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 1828 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 1829 u8 tqm_sp_pg_size_tqm_sp_lvl; 1830 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 1831 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 1832 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 1833 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 1834 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 1835 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 1836 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 1837 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 1838 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 1839 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 1840 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 1841 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 1842 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 1843 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 1844 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 1845 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 1846 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 1847 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 1848 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 1849 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 1850 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 1851 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 1852 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 1853 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 1854 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 1855 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 1856 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 1857 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 1858 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 1859 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 1860 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 1861 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 1862 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 1863 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 1864 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 1865 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 1866 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 1867 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 1868 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 1869 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 1870 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 1871 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 1872 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 1873 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 1874 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 1875 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 1876 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 1877 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 1878 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 1879 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 1880 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 1881 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 1882 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 1883 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 1884 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 1885 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 1886 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 1887 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 1888 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 1889 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 1890 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 1891 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 1892 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 1893 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 1894 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 1895 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 1896 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 1897 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 1898 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 1899 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 1900 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 1901 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 1902 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 1903 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 1904 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 1905 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 1906 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 1907 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 1908 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 1909 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 1910 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 1911 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 1912 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 1913 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 1914 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 1915 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 1916 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 1917 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 1918 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 1919 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 1920 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 1921 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 1922 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 1923 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 1924 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 1925 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 1926 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 1927 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 1928 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 1929 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 1930 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 1931 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 1932 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 1933 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 1934 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 1935 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 1936 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 1937 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 1938 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 1939 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 1940 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 1941 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 1942 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 1943 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 1944 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 1945 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 1946 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 1947 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 1948 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 1949 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 1950 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 1951 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 1952 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 1953 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 1954 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 1955 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 1956 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 1957 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 1958 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 1959 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 1960 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 1961 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 1962 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 1963 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 1964 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 1965 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 1966 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 1967 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 1968 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 1969 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 1970 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 1971 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 1972 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 1973 u8 mrav_pg_size_mrav_lvl; 1974 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 1975 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 1976 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 1977 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 1978 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 1979 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 1980 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 1981 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 1982 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 1983 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 1984 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 1985 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 1986 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 1987 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 1988 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 1989 u8 tim_pg_size_tim_lvl; 1990 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 1991 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 1992 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 1993 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 1994 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 1995 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 1996 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 1997 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 1998 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 1999 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 2000 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 2001 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 2002 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 2003 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 2004 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 2005 __le64 qpc_page_dir; 2006 __le64 srq_page_dir; 2007 __le64 cq_page_dir; 2008 __le64 vnic_page_dir; 2009 __le64 stat_page_dir; 2010 __le64 tqm_sp_page_dir; 2011 __le64 tqm_ring0_page_dir; 2012 __le64 tqm_ring1_page_dir; 2013 __le64 tqm_ring2_page_dir; 2014 __le64 tqm_ring3_page_dir; 2015 __le64 tqm_ring4_page_dir; 2016 __le64 tqm_ring5_page_dir; 2017 __le64 tqm_ring6_page_dir; 2018 __le64 tqm_ring7_page_dir; 2019 __le64 mrav_page_dir; 2020 __le64 tim_page_dir; 2021 __le32 qp_num_entries; 2022 __le32 srq_num_entries; 2023 __le32 cq_num_entries; 2024 __le32 stat_num_entries; 2025 __le32 tqm_sp_num_entries; 2026 __le32 tqm_ring0_num_entries; 2027 __le32 tqm_ring1_num_entries; 2028 __le32 tqm_ring2_num_entries; 2029 __le32 tqm_ring3_num_entries; 2030 __le32 tqm_ring4_num_entries; 2031 __le32 tqm_ring5_num_entries; 2032 __le32 tqm_ring6_num_entries; 2033 __le32 tqm_ring7_num_entries; 2034 __le32 mrav_num_entries; 2035 __le32 tim_num_entries; 2036 __le16 qp_num_qp1_entries; 2037 __le16 qp_num_l2_entries; 2038 __le16 qp_entry_size; 2039 __le16 srq_num_l2_entries; 2040 __le16 srq_entry_size; 2041 __le16 cq_num_l2_entries; 2042 __le16 cq_entry_size; 2043 __le16 vnic_num_vnic_entries; 2044 __le16 vnic_num_ring_table_entries; 2045 __le16 vnic_entry_size; 2046 __le16 stat_entry_size; 2047 __le16 tqm_entry_size; 2048 __le16 mrav_entry_size; 2049 __le16 tim_entry_size; 2050 }; 2051 2052 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 2053 struct hwrm_func_backing_store_cfg_output { 2054 __le16 error_code; 2055 __le16 req_type; 2056 __le16 seq_id; 2057 __le16 resp_len; 2058 u8 unused_0[7]; 2059 u8 valid; 2060 }; 2061 2062 /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 2063 struct hwrm_error_recovery_qcfg_input { 2064 __le16 req_type; 2065 __le16 cmpl_ring; 2066 __le16 seq_id; 2067 __le16 target_id; 2068 __le64 resp_addr; 2069 u8 unused_0[8]; 2070 }; 2071 2072 /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 2073 struct hwrm_error_recovery_qcfg_output { 2074 __le16 error_code; 2075 __le16 req_type; 2076 __le16 seq_id; 2077 __le16 resp_len; 2078 __le32 flags; 2079 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 2080 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 2081 __le32 driver_polling_freq; 2082 __le32 master_func_wait_period; 2083 __le32 normal_func_wait_period; 2084 __le32 master_func_wait_period_after_reset; 2085 __le32 max_bailout_time_after_reset; 2086 __le32 fw_health_status_reg; 2087 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 2088 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 2089 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2090 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 2091 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 2092 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 2093 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 2094 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 2095 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 2096 __le32 fw_heartbeat_reg; 2097 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 2098 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 2099 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2100 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 2101 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 2102 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 2103 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 2104 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 2105 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 2106 __le32 fw_reset_cnt_reg; 2107 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 2108 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 2109 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2110 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 2111 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2112 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2113 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 2114 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 2115 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 2116 __le32 reset_inprogress_reg; 2117 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 2118 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 2119 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2120 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 2121 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 2122 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 2123 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 2124 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 2125 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 2126 __le32 reset_inprogress_reg_mask; 2127 u8 unused_0[3]; 2128 u8 reg_array_cnt; 2129 __le32 reset_reg[16]; 2130 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 2131 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 2132 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2133 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 2134 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 2135 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 2136 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 2137 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 2138 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 2139 __le32 reset_reg_val[16]; 2140 u8 delay_after_reset[16]; 2141 u8 unused_1[7]; 2142 u8 valid; 2143 }; 2144 2145 /* hwrm_func_drv_if_change_input (size:192b/24B) */ 2146 struct hwrm_func_drv_if_change_input { 2147 __le16 req_type; 2148 __le16 cmpl_ring; 2149 __le16 seq_id; 2150 __le16 target_id; 2151 __le64 resp_addr; 2152 __le32 flags; 2153 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 2154 __le32 unused; 2155 }; 2156 2157 /* hwrm_func_drv_if_change_output (size:128b/16B) */ 2158 struct hwrm_func_drv_if_change_output { 2159 __le16 error_code; 2160 __le16 req_type; 2161 __le16 seq_id; 2162 __le16 resp_len; 2163 __le32 flags; 2164 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 2165 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 2166 u8 unused_0[3]; 2167 u8 valid; 2168 }; 2169 2170 /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2171 struct hwrm_port_phy_cfg_input { 2172 __le16 req_type; 2173 __le16 cmpl_ring; 2174 __le16 seq_id; 2175 __le16 target_id; 2176 __le64 resp_addr; 2177 __le32 flags; 2178 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 2179 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2180 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2181 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 2182 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 2183 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 2184 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 2185 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2186 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2187 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2188 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2189 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2190 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2191 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 2192 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2193 __le32 enables; 2194 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2195 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2196 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2197 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2198 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2199 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2200 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2201 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2202 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 2203 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 2204 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2205 __le16 port_id; 2206 __le16 force_link_speed; 2207 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2208 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2209 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2210 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2211 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2212 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2213 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2214 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2215 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2216 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2217 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_200GB 0x7d0UL 2218 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2219 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2220 u8 auto_mode; 2221 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2222 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2223 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2224 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2225 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2226 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2227 u8 auto_duplex; 2228 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2229 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2230 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2231 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2232 u8 auto_pause; 2233 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2234 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 2235 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2236 u8 unused_0; 2237 __le16 auto_link_speed; 2238 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2239 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2240 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2241 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2242 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2243 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2244 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2245 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2246 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2247 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2248 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_200GB 0x7d0UL 2249 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2250 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2251 __le16 auto_link_speed_mask; 2252 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2253 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2254 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2255 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2256 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2257 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2258 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2259 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2260 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2261 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2262 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2263 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2264 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2265 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2266 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2267 u8 wirespeed; 2268 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2269 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2270 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2271 u8 lpbk; 2272 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2273 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2274 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 2275 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 2276 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2277 u8 force_pause; 2278 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2279 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2280 u8 unused_1; 2281 __le32 preemphasis; 2282 __le16 eee_link_speed_mask; 2283 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2284 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 2285 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2286 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 2287 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2288 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2289 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2290 u8 unused_2[2]; 2291 __le32 tx_lpi_timer; 2292 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 2293 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2294 __le32 unused_3; 2295 }; 2296 2297 /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2298 struct hwrm_port_phy_cfg_output { 2299 __le16 error_code; 2300 __le16 req_type; 2301 __le16 seq_id; 2302 __le16 resp_len; 2303 u8 unused_0[7]; 2304 u8 valid; 2305 }; 2306 2307 /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2308 struct hwrm_port_phy_cfg_cmd_err { 2309 u8 code; 2310 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2311 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2312 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2313 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2314 u8 unused_0[7]; 2315 }; 2316 2317 /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2318 struct hwrm_port_phy_qcfg_input { 2319 __le16 req_type; 2320 __le16 cmpl_ring; 2321 __le16 seq_id; 2322 __le16 target_id; 2323 __le64 resp_addr; 2324 __le16 port_id; 2325 u8 unused_0[6]; 2326 }; 2327 2328 /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2329 struct hwrm_port_phy_qcfg_output { 2330 __le16 error_code; 2331 __le16 req_type; 2332 __le16 seq_id; 2333 __le16 resp_len; 2334 u8 link; 2335 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2336 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2337 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2338 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 2339 u8 unused_0; 2340 __le16 link_speed; 2341 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2342 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2343 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2344 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2345 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2346 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2347 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2348 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2349 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2350 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 2351 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2352 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2353 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2354 u8 duplex_cfg; 2355 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2356 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2357 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2358 u8 pause; 2359 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2360 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2361 __le16 support_speeds; 2362 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2363 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2364 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2365 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2366 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2367 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2368 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2369 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2370 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2371 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2372 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 2373 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 2374 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 2375 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2376 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_200GB 0x4000UL 2377 __le16 force_link_speed; 2378 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2379 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2380 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2381 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2382 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2383 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2384 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2385 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2386 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2387 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2388 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_200GB 0x7d0UL 2389 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2390 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2391 u8 auto_mode; 2392 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2393 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2394 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2395 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2396 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2397 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2398 u8 auto_pause; 2399 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2400 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 2401 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2402 __le16 auto_link_speed; 2403 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2404 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2405 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2406 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2407 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2408 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2409 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2410 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2411 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2412 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2413 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_200GB 0x7d0UL 2414 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2415 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2416 __le16 auto_link_speed_mask; 2417 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2418 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2419 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2420 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2421 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2422 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2423 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2424 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2425 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2426 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2427 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 2428 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 2429 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 2430 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2431 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_200GB 0x4000UL 2432 u8 wirespeed; 2433 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2434 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2435 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2436 u8 lpbk; 2437 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2438 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2439 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 2440 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 2441 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2442 u8 force_pause; 2443 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2444 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 2445 u8 module_status; 2446 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2447 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2448 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2449 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2450 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 2451 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2452 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2453 __le32 preemphasis; 2454 u8 phy_maj; 2455 u8 phy_min; 2456 u8 phy_bld; 2457 u8 phy_type; 2458 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2459 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2460 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2461 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2462 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2463 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2464 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2465 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2466 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2467 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2468 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2469 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2470 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2471 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2472 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2473 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2474 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2475 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2476 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2477 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2478 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2479 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2480 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2481 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2482 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2483 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2484 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2485 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 2486 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 2487 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 2488 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 2489 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 2490 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2491 u8 media_type; 2492 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2493 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2494 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2495 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2496 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 2497 u8 xcvr_pkg_type; 2498 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2499 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2500 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 2501 u8 eee_config_phy_addr; 2502 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2503 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2504 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2505 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 2506 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 2507 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 2508 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 2509 u8 parallel_detect; 2510 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2511 __le16 link_partner_adv_speeds; 2512 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2513 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2514 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2515 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2516 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2517 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2518 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2519 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2520 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2521 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2522 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 2523 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 2524 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 2525 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2526 u8 link_partner_adv_auto_mode; 2527 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2528 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2529 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2530 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2531 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2532 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2533 u8 link_partner_adv_pause; 2534 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2535 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 2536 __le16 adv_eee_link_speed_mask; 2537 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2538 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2539 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2540 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2541 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2542 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2543 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2544 __le16 link_partner_adv_eee_link_speed_mask; 2545 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 2546 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 2547 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 2548 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 2549 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 2550 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 2551 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 2552 __le32 xcvr_identifier_type_tx_lpi_timer; 2553 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 2554 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 2555 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 2556 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 2557 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 2558 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 2559 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 2560 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 2561 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 2562 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 2563 __le16 fec_cfg; 2564 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 2565 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 2566 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 2567 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 2568 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 2569 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 2570 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 2571 u8 duplex_state; 2572 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 2573 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 2574 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 2575 u8 option_flags; 2576 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2577 char phy_vendor_name[16]; 2578 char phy_vendor_partnumber[16]; 2579 u8 unused_2[7]; 2580 u8 valid; 2581 }; 2582 2583 /* hwrm_port_mac_cfg_input (size:320b/40B) */ 2584 struct hwrm_port_mac_cfg_input { 2585 __le16 req_type; 2586 __le16 cmpl_ring; 2587 __le16 seq_id; 2588 __le16 target_id; 2589 __le64 resp_addr; 2590 __le32 flags; 2591 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 2592 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 2593 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 2594 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 2595 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 2596 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 2597 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 2598 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 2599 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 2600 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 2601 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 2602 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 2603 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 2604 __le32 enables; 2605 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 2606 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 2607 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 2608 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 2609 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 2610 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 2611 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 2612 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 2613 __le16 port_id; 2614 u8 ipg; 2615 u8 lpbk; 2616 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 2617 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 2618 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 2619 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 2620 u8 vlan_pri2cos_map_pri; 2621 u8 reserved1; 2622 u8 tunnel_pri2cos_map_pri; 2623 u8 dscp2pri_map_pri; 2624 __le16 rx_ts_capture_ptp_msg_type; 2625 __le16 tx_ts_capture_ptp_msg_type; 2626 u8 cos_field_cfg; 2627 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 2628 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 2629 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 2630 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 2631 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 2632 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 2633 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 2634 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 2635 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 2636 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 2637 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 2638 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 2639 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 2640 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 2641 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 2642 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 2643 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 2644 u8 unused_0[3]; 2645 }; 2646 2647 /* hwrm_port_mac_cfg_output (size:128b/16B) */ 2648 struct hwrm_port_mac_cfg_output { 2649 __le16 error_code; 2650 __le16 req_type; 2651 __le16 seq_id; 2652 __le16 resp_len; 2653 __le16 mru; 2654 __le16 mtu; 2655 u8 ipg; 2656 u8 lpbk; 2657 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 2658 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 2659 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 2660 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 2661 u8 unused_0; 2662 u8 valid; 2663 }; 2664 2665 /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 2666 struct hwrm_port_mac_ptp_qcfg_input { 2667 __le16 req_type; 2668 __le16 cmpl_ring; 2669 __le16 seq_id; 2670 __le16 target_id; 2671 __le64 resp_addr; 2672 __le16 port_id; 2673 u8 unused_0[6]; 2674 }; 2675 2676 /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 2677 struct hwrm_port_mac_ptp_qcfg_output { 2678 __le16 error_code; 2679 __le16 req_type; 2680 __le16 seq_id; 2681 __le16 resp_len; 2682 u8 flags; 2683 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 2684 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 2685 u8 unused_0[3]; 2686 __le32 rx_ts_reg_off_lower; 2687 __le32 rx_ts_reg_off_upper; 2688 __le32 rx_ts_reg_off_seq_id; 2689 __le32 rx_ts_reg_off_src_id_0; 2690 __le32 rx_ts_reg_off_src_id_1; 2691 __le32 rx_ts_reg_off_src_id_2; 2692 __le32 rx_ts_reg_off_domain_id; 2693 __le32 rx_ts_reg_off_fifo; 2694 __le32 rx_ts_reg_off_fifo_adv; 2695 __le32 rx_ts_reg_off_granularity; 2696 __le32 tx_ts_reg_off_lower; 2697 __le32 tx_ts_reg_off_upper; 2698 __le32 tx_ts_reg_off_seq_id; 2699 __le32 tx_ts_reg_off_fifo; 2700 __le32 tx_ts_reg_off_granularity; 2701 u8 unused_1[7]; 2702 u8 valid; 2703 }; 2704 2705 /* tx_port_stats (size:3264b/408B) */ 2706 struct tx_port_stats { 2707 __le64 tx_64b_frames; 2708 __le64 tx_65b_127b_frames; 2709 __le64 tx_128b_255b_frames; 2710 __le64 tx_256b_511b_frames; 2711 __le64 tx_512b_1023b_frames; 2712 __le64 tx_1024b_1518b_frames; 2713 __le64 tx_good_vlan_frames; 2714 __le64 tx_1519b_2047b_frames; 2715 __le64 tx_2048b_4095b_frames; 2716 __le64 tx_4096b_9216b_frames; 2717 __le64 tx_9217b_16383b_frames; 2718 __le64 tx_good_frames; 2719 __le64 tx_total_frames; 2720 __le64 tx_ucast_frames; 2721 __le64 tx_mcast_frames; 2722 __le64 tx_bcast_frames; 2723 __le64 tx_pause_frames; 2724 __le64 tx_pfc_frames; 2725 __le64 tx_jabber_frames; 2726 __le64 tx_fcs_err_frames; 2727 __le64 tx_control_frames; 2728 __le64 tx_oversz_frames; 2729 __le64 tx_single_dfrl_frames; 2730 __le64 tx_multi_dfrl_frames; 2731 __le64 tx_single_coll_frames; 2732 __le64 tx_multi_coll_frames; 2733 __le64 tx_late_coll_frames; 2734 __le64 tx_excessive_coll_frames; 2735 __le64 tx_frag_frames; 2736 __le64 tx_err; 2737 __le64 tx_tagged_frames; 2738 __le64 tx_dbl_tagged_frames; 2739 __le64 tx_runt_frames; 2740 __le64 tx_fifo_underruns; 2741 __le64 tx_pfc_ena_frames_pri0; 2742 __le64 tx_pfc_ena_frames_pri1; 2743 __le64 tx_pfc_ena_frames_pri2; 2744 __le64 tx_pfc_ena_frames_pri3; 2745 __le64 tx_pfc_ena_frames_pri4; 2746 __le64 tx_pfc_ena_frames_pri5; 2747 __le64 tx_pfc_ena_frames_pri6; 2748 __le64 tx_pfc_ena_frames_pri7; 2749 __le64 tx_eee_lpi_events; 2750 __le64 tx_eee_lpi_duration; 2751 __le64 tx_llfc_logical_msgs; 2752 __le64 tx_hcfc_msgs; 2753 __le64 tx_total_collisions; 2754 __le64 tx_bytes; 2755 __le64 tx_xthol_frames; 2756 __le64 tx_stat_discard; 2757 __le64 tx_stat_error; 2758 }; 2759 2760 /* rx_port_stats (size:4224b/528B) */ 2761 struct rx_port_stats { 2762 __le64 rx_64b_frames; 2763 __le64 rx_65b_127b_frames; 2764 __le64 rx_128b_255b_frames; 2765 __le64 rx_256b_511b_frames; 2766 __le64 rx_512b_1023b_frames; 2767 __le64 rx_1024b_1518b_frames; 2768 __le64 rx_good_vlan_frames; 2769 __le64 rx_1519b_2047b_frames; 2770 __le64 rx_2048b_4095b_frames; 2771 __le64 rx_4096b_9216b_frames; 2772 __le64 rx_9217b_16383b_frames; 2773 __le64 rx_total_frames; 2774 __le64 rx_ucast_frames; 2775 __le64 rx_mcast_frames; 2776 __le64 rx_bcast_frames; 2777 __le64 rx_fcs_err_frames; 2778 __le64 rx_ctrl_frames; 2779 __le64 rx_pause_frames; 2780 __le64 rx_pfc_frames; 2781 __le64 rx_unsupported_opcode_frames; 2782 __le64 rx_unsupported_da_pausepfc_frames; 2783 __le64 rx_wrong_sa_frames; 2784 __le64 rx_align_err_frames; 2785 __le64 rx_oor_len_frames; 2786 __le64 rx_code_err_frames; 2787 __le64 rx_false_carrier_frames; 2788 __le64 rx_ovrsz_frames; 2789 __le64 rx_jbr_frames; 2790 __le64 rx_mtu_err_frames; 2791 __le64 rx_match_crc_frames; 2792 __le64 rx_promiscuous_frames; 2793 __le64 rx_tagged_frames; 2794 __le64 rx_double_tagged_frames; 2795 __le64 rx_trunc_frames; 2796 __le64 rx_good_frames; 2797 __le64 rx_pfc_xon2xoff_frames_pri0; 2798 __le64 rx_pfc_xon2xoff_frames_pri1; 2799 __le64 rx_pfc_xon2xoff_frames_pri2; 2800 __le64 rx_pfc_xon2xoff_frames_pri3; 2801 __le64 rx_pfc_xon2xoff_frames_pri4; 2802 __le64 rx_pfc_xon2xoff_frames_pri5; 2803 __le64 rx_pfc_xon2xoff_frames_pri6; 2804 __le64 rx_pfc_xon2xoff_frames_pri7; 2805 __le64 rx_pfc_ena_frames_pri0; 2806 __le64 rx_pfc_ena_frames_pri1; 2807 __le64 rx_pfc_ena_frames_pri2; 2808 __le64 rx_pfc_ena_frames_pri3; 2809 __le64 rx_pfc_ena_frames_pri4; 2810 __le64 rx_pfc_ena_frames_pri5; 2811 __le64 rx_pfc_ena_frames_pri6; 2812 __le64 rx_pfc_ena_frames_pri7; 2813 __le64 rx_sch_crc_err_frames; 2814 __le64 rx_undrsz_frames; 2815 __le64 rx_frag_frames; 2816 __le64 rx_eee_lpi_events; 2817 __le64 rx_eee_lpi_duration; 2818 __le64 rx_llfc_physical_msgs; 2819 __le64 rx_llfc_logical_msgs; 2820 __le64 rx_llfc_msgs_with_crc_err; 2821 __le64 rx_hcfc_msgs; 2822 __le64 rx_hcfc_msgs_with_crc_err; 2823 __le64 rx_bytes; 2824 __le64 rx_runt_bytes; 2825 __le64 rx_runt_frames; 2826 __le64 rx_stat_discard; 2827 __le64 rx_stat_err; 2828 }; 2829 2830 /* hwrm_port_qstats_input (size:320b/40B) */ 2831 struct hwrm_port_qstats_input { 2832 __le16 req_type; 2833 __le16 cmpl_ring; 2834 __le16 seq_id; 2835 __le16 target_id; 2836 __le64 resp_addr; 2837 __le16 port_id; 2838 u8 unused_0[6]; 2839 __le64 tx_stat_host_addr; 2840 __le64 rx_stat_host_addr; 2841 }; 2842 2843 /* hwrm_port_qstats_output (size:128b/16B) */ 2844 struct hwrm_port_qstats_output { 2845 __le16 error_code; 2846 __le16 req_type; 2847 __le16 seq_id; 2848 __le16 resp_len; 2849 __le16 tx_stat_size; 2850 __le16 rx_stat_size; 2851 u8 unused_0[3]; 2852 u8 valid; 2853 }; 2854 2855 /* tx_port_stats_ext (size:2048b/256B) */ 2856 struct tx_port_stats_ext { 2857 __le64 tx_bytes_cos0; 2858 __le64 tx_bytes_cos1; 2859 __le64 tx_bytes_cos2; 2860 __le64 tx_bytes_cos3; 2861 __le64 tx_bytes_cos4; 2862 __le64 tx_bytes_cos5; 2863 __le64 tx_bytes_cos6; 2864 __le64 tx_bytes_cos7; 2865 __le64 tx_packets_cos0; 2866 __le64 tx_packets_cos1; 2867 __le64 tx_packets_cos2; 2868 __le64 tx_packets_cos3; 2869 __le64 tx_packets_cos4; 2870 __le64 tx_packets_cos5; 2871 __le64 tx_packets_cos6; 2872 __le64 tx_packets_cos7; 2873 __le64 pfc_pri0_tx_duration_us; 2874 __le64 pfc_pri0_tx_transitions; 2875 __le64 pfc_pri1_tx_duration_us; 2876 __le64 pfc_pri1_tx_transitions; 2877 __le64 pfc_pri2_tx_duration_us; 2878 __le64 pfc_pri2_tx_transitions; 2879 __le64 pfc_pri3_tx_duration_us; 2880 __le64 pfc_pri3_tx_transitions; 2881 __le64 pfc_pri4_tx_duration_us; 2882 __le64 pfc_pri4_tx_transitions; 2883 __le64 pfc_pri5_tx_duration_us; 2884 __le64 pfc_pri5_tx_transitions; 2885 __le64 pfc_pri6_tx_duration_us; 2886 __le64 pfc_pri6_tx_transitions; 2887 __le64 pfc_pri7_tx_duration_us; 2888 __le64 pfc_pri7_tx_transitions; 2889 }; 2890 2891 /* rx_port_stats_ext (size:2368b/296B) */ 2892 struct rx_port_stats_ext { 2893 __le64 link_down_events; 2894 __le64 continuous_pause_events; 2895 __le64 resume_pause_events; 2896 __le64 continuous_roce_pause_events; 2897 __le64 resume_roce_pause_events; 2898 __le64 rx_bytes_cos0; 2899 __le64 rx_bytes_cos1; 2900 __le64 rx_bytes_cos2; 2901 __le64 rx_bytes_cos3; 2902 __le64 rx_bytes_cos4; 2903 __le64 rx_bytes_cos5; 2904 __le64 rx_bytes_cos6; 2905 __le64 rx_bytes_cos7; 2906 __le64 rx_packets_cos0; 2907 __le64 rx_packets_cos1; 2908 __le64 rx_packets_cos2; 2909 __le64 rx_packets_cos3; 2910 __le64 rx_packets_cos4; 2911 __le64 rx_packets_cos5; 2912 __le64 rx_packets_cos6; 2913 __le64 rx_packets_cos7; 2914 __le64 pfc_pri0_rx_duration_us; 2915 __le64 pfc_pri0_rx_transitions; 2916 __le64 pfc_pri1_rx_duration_us; 2917 __le64 pfc_pri1_rx_transitions; 2918 __le64 pfc_pri2_rx_duration_us; 2919 __le64 pfc_pri2_rx_transitions; 2920 __le64 pfc_pri3_rx_duration_us; 2921 __le64 pfc_pri3_rx_transitions; 2922 __le64 pfc_pri4_rx_duration_us; 2923 __le64 pfc_pri4_rx_transitions; 2924 __le64 pfc_pri5_rx_duration_us; 2925 __le64 pfc_pri5_rx_transitions; 2926 __le64 pfc_pri6_rx_duration_us; 2927 __le64 pfc_pri6_rx_transitions; 2928 __le64 pfc_pri7_rx_duration_us; 2929 __le64 pfc_pri7_rx_transitions; 2930 }; 2931 2932 /* hwrm_port_qstats_ext_input (size:320b/40B) */ 2933 struct hwrm_port_qstats_ext_input { 2934 __le16 req_type; 2935 __le16 cmpl_ring; 2936 __le16 seq_id; 2937 __le16 target_id; 2938 __le64 resp_addr; 2939 __le16 port_id; 2940 __le16 tx_stat_size; 2941 __le16 rx_stat_size; 2942 u8 unused_0[2]; 2943 __le64 tx_stat_host_addr; 2944 __le64 rx_stat_host_addr; 2945 }; 2946 2947 /* hwrm_port_qstats_ext_output (size:128b/16B) */ 2948 struct hwrm_port_qstats_ext_output { 2949 __le16 error_code; 2950 __le16 req_type; 2951 __le16 seq_id; 2952 __le16 resp_len; 2953 __le16 tx_stat_size; 2954 __le16 rx_stat_size; 2955 __le16 total_active_cos_queues; 2956 u8 flags; 2957 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 2958 u8 valid; 2959 }; 2960 2961 /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 2962 struct hwrm_port_lpbk_qstats_input { 2963 __le16 req_type; 2964 __le16 cmpl_ring; 2965 __le16 seq_id; 2966 __le16 target_id; 2967 __le64 resp_addr; 2968 }; 2969 2970 /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 2971 struct hwrm_port_lpbk_qstats_output { 2972 __le16 error_code; 2973 __le16 req_type; 2974 __le16 seq_id; 2975 __le16 resp_len; 2976 __le64 lpbk_ucast_frames; 2977 __le64 lpbk_mcast_frames; 2978 __le64 lpbk_bcast_frames; 2979 __le64 lpbk_ucast_bytes; 2980 __le64 lpbk_mcast_bytes; 2981 __le64 lpbk_bcast_bytes; 2982 __le64 tx_stat_discard; 2983 __le64 tx_stat_error; 2984 __le64 rx_stat_discard; 2985 __le64 rx_stat_error; 2986 u8 unused_0[7]; 2987 u8 valid; 2988 }; 2989 2990 /* hwrm_port_clr_stats_input (size:192b/24B) */ 2991 struct hwrm_port_clr_stats_input { 2992 __le16 req_type; 2993 __le16 cmpl_ring; 2994 __le16 seq_id; 2995 __le16 target_id; 2996 __le64 resp_addr; 2997 __le16 port_id; 2998 u8 flags; 2999 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 3000 u8 unused_0[5]; 3001 }; 3002 3003 /* hwrm_port_clr_stats_output (size:128b/16B) */ 3004 struct hwrm_port_clr_stats_output { 3005 __le16 error_code; 3006 __le16 req_type; 3007 __le16 seq_id; 3008 __le16 resp_len; 3009 u8 unused_0[7]; 3010 u8 valid; 3011 }; 3012 3013 /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3014 struct hwrm_port_lpbk_clr_stats_input { 3015 __le16 req_type; 3016 __le16 cmpl_ring; 3017 __le16 seq_id; 3018 __le16 target_id; 3019 __le64 resp_addr; 3020 }; 3021 3022 /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3023 struct hwrm_port_lpbk_clr_stats_output { 3024 __le16 error_code; 3025 __le16 req_type; 3026 __le16 seq_id; 3027 __le16 resp_len; 3028 u8 unused_0[7]; 3029 u8 valid; 3030 }; 3031 3032 /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 3033 struct hwrm_port_phy_qcaps_input { 3034 __le16 req_type; 3035 __le16 cmpl_ring; 3036 __le16 seq_id; 3037 __le16 target_id; 3038 __le64 resp_addr; 3039 __le16 port_id; 3040 u8 unused_0[6]; 3041 }; 3042 3043 /* hwrm_port_phy_qcaps_output (size:192b/24B) */ 3044 struct hwrm_port_phy_qcaps_output { 3045 __le16 error_code; 3046 __le16 req_type; 3047 __le16 seq_id; 3048 __le16 resp_len; 3049 u8 flags; 3050 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 3051 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 3052 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfcUL 3053 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 2 3054 u8 port_cnt; 3055 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3056 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 3057 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 3058 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 3059 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3060 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 3061 __le16 supported_speeds_force_mode; 3062 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 3063 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 3064 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 3065 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 3066 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 3067 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 3068 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 3069 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 3070 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 3071 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 3072 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 3073 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 3074 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 3075 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 3076 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_200GB 0x4000UL 3077 __le16 supported_speeds_auto_mode; 3078 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 3079 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 3080 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 3081 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 3082 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 3083 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 3084 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 3085 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 3086 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 3087 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 3088 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 3089 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 3090 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 3091 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 3092 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_200GB 0x4000UL 3093 __le16 supported_speeds_eee_mode; 3094 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 3095 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 3096 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 3097 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 3098 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 3099 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 3100 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 3101 __le32 tx_lpi_timer_low; 3102 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 3103 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 3104 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 3105 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 3106 __le32 valid_tx_lpi_timer_high; 3107 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 3108 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3109 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 3110 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 3111 }; 3112 3113 /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 3114 struct hwrm_port_phy_i2c_read_input { 3115 __le16 req_type; 3116 __le16 cmpl_ring; 3117 __le16 seq_id; 3118 __le16 target_id; 3119 __le64 resp_addr; 3120 __le32 flags; 3121 __le32 enables; 3122 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 3123 __le16 port_id; 3124 u8 i2c_slave_addr; 3125 u8 unused_0; 3126 __le16 page_number; 3127 __le16 page_offset; 3128 u8 data_length; 3129 u8 unused_1[7]; 3130 }; 3131 3132 /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 3133 struct hwrm_port_phy_i2c_read_output { 3134 __le16 error_code; 3135 __le16 req_type; 3136 __le16 seq_id; 3137 __le16 resp_len; 3138 __le32 data[16]; 3139 u8 unused_0[7]; 3140 u8 valid; 3141 }; 3142 3143 /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 3144 struct hwrm_port_phy_mdio_write_input { 3145 __le16 req_type; 3146 __le16 cmpl_ring; 3147 __le16 seq_id; 3148 __le16 target_id; 3149 __le64 resp_addr; 3150 __le32 unused_0[2]; 3151 __le16 port_id; 3152 u8 phy_addr; 3153 u8 dev_addr; 3154 __le16 reg_addr; 3155 __le16 reg_data; 3156 u8 cl45_mdio; 3157 u8 unused_1[7]; 3158 }; 3159 3160 /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 3161 struct hwrm_port_phy_mdio_write_output { 3162 __le16 error_code; 3163 __le16 req_type; 3164 __le16 seq_id; 3165 __le16 resp_len; 3166 u8 unused_0[7]; 3167 u8 valid; 3168 }; 3169 3170 /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 3171 struct hwrm_port_phy_mdio_read_input { 3172 __le16 req_type; 3173 __le16 cmpl_ring; 3174 __le16 seq_id; 3175 __le16 target_id; 3176 __le64 resp_addr; 3177 __le32 unused_0[2]; 3178 __le16 port_id; 3179 u8 phy_addr; 3180 u8 dev_addr; 3181 __le16 reg_addr; 3182 u8 cl45_mdio; 3183 u8 unused_1; 3184 }; 3185 3186 /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 3187 struct hwrm_port_phy_mdio_read_output { 3188 __le16 error_code; 3189 __le16 req_type; 3190 __le16 seq_id; 3191 __le16 resp_len; 3192 __le16 reg_data; 3193 u8 unused_0[5]; 3194 u8 valid; 3195 }; 3196 3197 /* hwrm_port_led_cfg_input (size:512b/64B) */ 3198 struct hwrm_port_led_cfg_input { 3199 __le16 req_type; 3200 __le16 cmpl_ring; 3201 __le16 seq_id; 3202 __le16 target_id; 3203 __le64 resp_addr; 3204 __le32 enables; 3205 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3206 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3207 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3208 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3209 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3210 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3211 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3212 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3213 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3214 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3215 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3216 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3217 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3218 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3219 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3220 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3221 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3222 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3223 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3224 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3225 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3226 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3227 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3228 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3229 __le16 port_id; 3230 u8 num_leds; 3231 u8 rsvd; 3232 u8 led0_id; 3233 u8 led0_state; 3234 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3235 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3236 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3237 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3238 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3239 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3240 u8 led0_color; 3241 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3242 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3243 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3244 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3245 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3246 u8 unused_0; 3247 __le16 led0_blink_on; 3248 __le16 led0_blink_off; 3249 u8 led0_group_id; 3250 u8 rsvd0; 3251 u8 led1_id; 3252 u8 led1_state; 3253 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3254 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3255 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3256 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3257 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3258 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3259 u8 led1_color; 3260 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3261 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3262 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3263 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3264 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3265 u8 unused_1; 3266 __le16 led1_blink_on; 3267 __le16 led1_blink_off; 3268 u8 led1_group_id; 3269 u8 rsvd1; 3270 u8 led2_id; 3271 u8 led2_state; 3272 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3273 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3274 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3275 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3276 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3277 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3278 u8 led2_color; 3279 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3280 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3281 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3282 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3283 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3284 u8 unused_2; 3285 __le16 led2_blink_on; 3286 __le16 led2_blink_off; 3287 u8 led2_group_id; 3288 u8 rsvd2; 3289 u8 led3_id; 3290 u8 led3_state; 3291 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3292 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3293 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3294 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3295 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3296 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3297 u8 led3_color; 3298 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3299 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3300 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3301 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3302 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3303 u8 unused_3; 3304 __le16 led3_blink_on; 3305 __le16 led3_blink_off; 3306 u8 led3_group_id; 3307 u8 rsvd3; 3308 }; 3309 3310 /* hwrm_port_led_cfg_output (size:128b/16B) */ 3311 struct hwrm_port_led_cfg_output { 3312 __le16 error_code; 3313 __le16 req_type; 3314 __le16 seq_id; 3315 __le16 resp_len; 3316 u8 unused_0[7]; 3317 u8 valid; 3318 }; 3319 3320 /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3321 struct hwrm_port_led_qcfg_input { 3322 __le16 req_type; 3323 __le16 cmpl_ring; 3324 __le16 seq_id; 3325 __le16 target_id; 3326 __le64 resp_addr; 3327 __le16 port_id; 3328 u8 unused_0[6]; 3329 }; 3330 3331 /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3332 struct hwrm_port_led_qcfg_output { 3333 __le16 error_code; 3334 __le16 req_type; 3335 __le16 seq_id; 3336 __le16 resp_len; 3337 u8 num_leds; 3338 u8 led0_id; 3339 u8 led0_type; 3340 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3341 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3342 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3343 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3344 u8 led0_state; 3345 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3346 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3347 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3348 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3349 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3350 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3351 u8 led0_color; 3352 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3353 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3354 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3355 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3356 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3357 u8 unused_0; 3358 __le16 led0_blink_on; 3359 __le16 led0_blink_off; 3360 u8 led0_group_id; 3361 u8 led1_id; 3362 u8 led1_type; 3363 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3364 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3365 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3366 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3367 u8 led1_state; 3368 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3369 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3370 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3371 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3372 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3373 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3374 u8 led1_color; 3375 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3376 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3377 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3378 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3379 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3380 u8 unused_1; 3381 __le16 led1_blink_on; 3382 __le16 led1_blink_off; 3383 u8 led1_group_id; 3384 u8 led2_id; 3385 u8 led2_type; 3386 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3387 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3388 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3389 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3390 u8 led2_state; 3391 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3392 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3393 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3394 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3395 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3396 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3397 u8 led2_color; 3398 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3399 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3400 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3401 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3402 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3403 u8 unused_2; 3404 __le16 led2_blink_on; 3405 __le16 led2_blink_off; 3406 u8 led2_group_id; 3407 u8 led3_id; 3408 u8 led3_type; 3409 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3410 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3411 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3412 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3413 u8 led3_state; 3414 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 3415 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 3416 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 3417 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 3418 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 3419 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 3420 u8 led3_color; 3421 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 3422 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 3423 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 3424 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 3425 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 3426 u8 unused_3; 3427 __le16 led3_blink_on; 3428 __le16 led3_blink_off; 3429 u8 led3_group_id; 3430 u8 unused_4[6]; 3431 u8 valid; 3432 }; 3433 3434 /* hwrm_port_led_qcaps_input (size:192b/24B) */ 3435 struct hwrm_port_led_qcaps_input { 3436 __le16 req_type; 3437 __le16 cmpl_ring; 3438 __le16 seq_id; 3439 __le16 target_id; 3440 __le64 resp_addr; 3441 __le16 port_id; 3442 u8 unused_0[6]; 3443 }; 3444 3445 /* hwrm_port_led_qcaps_output (size:384b/48B) */ 3446 struct hwrm_port_led_qcaps_output { 3447 __le16 error_code; 3448 __le16 req_type; 3449 __le16 seq_id; 3450 __le16 resp_len; 3451 u8 num_leds; 3452 u8 unused[3]; 3453 u8 led0_id; 3454 u8 led0_type; 3455 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 3456 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 3457 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 3458 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 3459 u8 led0_group_id; 3460 u8 unused_0; 3461 __le16 led0_state_caps; 3462 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 3463 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 3464 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 3465 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3466 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3467 __le16 led0_color_caps; 3468 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 3469 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3470 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3471 u8 led1_id; 3472 u8 led1_type; 3473 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 3474 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 3475 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 3476 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 3477 u8 led1_group_id; 3478 u8 unused_1; 3479 __le16 led1_state_caps; 3480 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 3481 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 3482 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 3483 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3484 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3485 __le16 led1_color_caps; 3486 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 3487 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3488 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3489 u8 led2_id; 3490 u8 led2_type; 3491 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 3492 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 3493 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 3494 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 3495 u8 led2_group_id; 3496 u8 unused_2; 3497 __le16 led2_state_caps; 3498 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 3499 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 3500 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 3501 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3502 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3503 __le16 led2_color_caps; 3504 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 3505 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3506 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3507 u8 led3_id; 3508 u8 led3_type; 3509 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 3510 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 3511 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 3512 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 3513 u8 led3_group_id; 3514 u8 unused_3; 3515 __le16 led3_state_caps; 3516 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 3517 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 3518 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 3519 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 3520 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 3521 __le16 led3_color_caps; 3522 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 3523 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 3524 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 3525 u8 unused_4[3]; 3526 u8 valid; 3527 }; 3528 3529 /* hwrm_queue_qportcfg_input (size:192b/24B) */ 3530 struct hwrm_queue_qportcfg_input { 3531 __le16 req_type; 3532 __le16 cmpl_ring; 3533 __le16 seq_id; 3534 __le16 target_id; 3535 __le64 resp_addr; 3536 __le32 flags; 3537 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 3538 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 3539 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 3540 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 3541 __le16 port_id; 3542 u8 drv_qmap_cap; 3543 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 3544 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 3545 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 3546 u8 unused_0; 3547 }; 3548 3549 /* hwrm_queue_qportcfg_output (size:256b/32B) */ 3550 struct hwrm_queue_qportcfg_output { 3551 __le16 error_code; 3552 __le16 req_type; 3553 __le16 seq_id; 3554 __le16 resp_len; 3555 u8 max_configurable_queues; 3556 u8 max_configurable_lossless_queues; 3557 u8 queue_cfg_allowed; 3558 u8 queue_cfg_info; 3559 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3560 u8 queue_pfcenable_cfg_allowed; 3561 u8 queue_pri2cos_cfg_allowed; 3562 u8 queue_cos2bw_cfg_allowed; 3563 u8 queue_id0; 3564 u8 queue_id0_service_profile; 3565 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 3566 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 3567 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3568 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3569 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3570 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 3571 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 3572 u8 queue_id1; 3573 u8 queue_id1_service_profile; 3574 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 3575 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 3576 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3577 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3578 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3579 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 3580 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 3581 u8 queue_id2; 3582 u8 queue_id2_service_profile; 3583 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 3584 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 3585 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3586 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3587 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3588 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 3589 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 3590 u8 queue_id3; 3591 u8 queue_id3_service_profile; 3592 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 3593 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 3594 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3595 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3596 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3597 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 3598 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 3599 u8 queue_id4; 3600 u8 queue_id4_service_profile; 3601 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 3602 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 3603 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3604 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3605 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3606 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 3607 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 3608 u8 queue_id5; 3609 u8 queue_id5_service_profile; 3610 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 3611 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 3612 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3613 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3614 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3615 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 3616 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 3617 u8 queue_id6; 3618 u8 queue_id6_service_profile; 3619 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 3620 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 3621 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3622 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3623 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3624 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 3625 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 3626 u8 queue_id7; 3627 u8 queue_id7_service_profile; 3628 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 3629 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 3630 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 3631 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 3632 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 3633 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 3634 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 3635 u8 valid; 3636 }; 3637 3638 /* hwrm_queue_cfg_input (size:320b/40B) */ 3639 struct hwrm_queue_cfg_input { 3640 __le16 req_type; 3641 __le16 cmpl_ring; 3642 __le16 seq_id; 3643 __le16 target_id; 3644 __le64 resp_addr; 3645 __le32 flags; 3646 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3647 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 3648 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 3649 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 3650 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3651 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 3652 __le32 enables; 3653 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 3654 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 3655 __le32 queue_id; 3656 __le32 dflt_len; 3657 u8 service_profile; 3658 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 3659 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 3660 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 3661 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 3662 u8 unused_0[7]; 3663 }; 3664 3665 /* hwrm_queue_cfg_output (size:128b/16B) */ 3666 struct hwrm_queue_cfg_output { 3667 __le16 error_code; 3668 __le16 req_type; 3669 __le16 seq_id; 3670 __le16 resp_len; 3671 u8 unused_0[7]; 3672 u8 valid; 3673 }; 3674 3675 /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 3676 struct hwrm_queue_pfcenable_qcfg_input { 3677 __le16 req_type; 3678 __le16 cmpl_ring; 3679 __le16 seq_id; 3680 __le16 target_id; 3681 __le64 resp_addr; 3682 __le16 port_id; 3683 u8 unused_0[6]; 3684 }; 3685 3686 /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 3687 struct hwrm_queue_pfcenable_qcfg_output { 3688 __le16 error_code; 3689 __le16 req_type; 3690 __le16 seq_id; 3691 __le16 resp_len; 3692 __le32 flags; 3693 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 3694 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 3695 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 3696 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 3697 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 3698 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 3699 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 3700 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 3701 u8 unused_0[3]; 3702 u8 valid; 3703 }; 3704 3705 /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 3706 struct hwrm_queue_pfcenable_cfg_input { 3707 __le16 req_type; 3708 __le16 cmpl_ring; 3709 __le16 seq_id; 3710 __le16 target_id; 3711 __le64 resp_addr; 3712 __le32 flags; 3713 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 3714 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 3715 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 3716 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 3717 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 3718 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 3719 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 3720 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 3721 __le16 port_id; 3722 u8 unused_0[2]; 3723 }; 3724 3725 /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 3726 struct hwrm_queue_pfcenable_cfg_output { 3727 __le16 error_code; 3728 __le16 req_type; 3729 __le16 seq_id; 3730 __le16 resp_len; 3731 u8 unused_0[7]; 3732 u8 valid; 3733 }; 3734 3735 /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 3736 struct hwrm_queue_pri2cos_qcfg_input { 3737 __le16 req_type; 3738 __le16 cmpl_ring; 3739 __le16 seq_id; 3740 __le16 target_id; 3741 __le64 resp_addr; 3742 __le32 flags; 3743 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 3744 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 3745 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 3746 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 3747 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 3748 u8 port_id; 3749 u8 unused_0[3]; 3750 }; 3751 3752 /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 3753 struct hwrm_queue_pri2cos_qcfg_output { 3754 __le16 error_code; 3755 __le16 req_type; 3756 __le16 seq_id; 3757 __le16 resp_len; 3758 u8 pri0_cos_queue_id; 3759 u8 pri1_cos_queue_id; 3760 u8 pri2_cos_queue_id; 3761 u8 pri3_cos_queue_id; 3762 u8 pri4_cos_queue_id; 3763 u8 pri5_cos_queue_id; 3764 u8 pri6_cos_queue_id; 3765 u8 pri7_cos_queue_id; 3766 u8 queue_cfg_info; 3767 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 3768 u8 unused_0[6]; 3769 u8 valid; 3770 }; 3771 3772 /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 3773 struct hwrm_queue_pri2cos_cfg_input { 3774 __le16 req_type; 3775 __le16 cmpl_ring; 3776 __le16 seq_id; 3777 __le16 target_id; 3778 __le64 resp_addr; 3779 __le32 flags; 3780 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 3781 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 3782 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 3783 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 3784 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 3785 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 3786 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 3787 __le32 enables; 3788 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 3789 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 3790 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 3791 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 3792 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 3793 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 3794 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 3795 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 3796 u8 port_id; 3797 u8 pri0_cos_queue_id; 3798 u8 pri1_cos_queue_id; 3799 u8 pri2_cos_queue_id; 3800 u8 pri3_cos_queue_id; 3801 u8 pri4_cos_queue_id; 3802 u8 pri5_cos_queue_id; 3803 u8 pri6_cos_queue_id; 3804 u8 pri7_cos_queue_id; 3805 u8 unused_0[7]; 3806 }; 3807 3808 /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 3809 struct hwrm_queue_pri2cos_cfg_output { 3810 __le16 error_code; 3811 __le16 req_type; 3812 __le16 seq_id; 3813 __le16 resp_len; 3814 u8 unused_0[7]; 3815 u8 valid; 3816 }; 3817 3818 /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 3819 struct hwrm_queue_cos2bw_qcfg_input { 3820 __le16 req_type; 3821 __le16 cmpl_ring; 3822 __le16 seq_id; 3823 __le16 target_id; 3824 __le64 resp_addr; 3825 __le16 port_id; 3826 u8 unused_0[6]; 3827 }; 3828 3829 /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 3830 struct hwrm_queue_cos2bw_qcfg_output { 3831 __le16 error_code; 3832 __le16 req_type; 3833 __le16 seq_id; 3834 __le16 resp_len; 3835 u8 queue_id0; 3836 u8 unused_0; 3837 __le16 unused_1; 3838 __le32 queue_id0_min_bw; 3839 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3840 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3841 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3842 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3843 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3844 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 3845 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3846 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3847 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3848 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3849 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3850 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3851 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3852 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3853 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3854 __le32 queue_id0_max_bw; 3855 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3856 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3857 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3858 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3859 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3860 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 3861 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3862 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3863 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3864 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3865 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3866 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3867 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3868 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3869 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3870 u8 queue_id0_tsa_assign; 3871 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3872 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3873 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3874 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3875 u8 queue_id0_pri_lvl; 3876 u8 queue_id0_bw_weight; 3877 u8 queue_id1; 3878 __le32 queue_id1_min_bw; 3879 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 3885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3894 __le32 queue_id1_max_bw; 3895 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 3901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3903 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3910 u8 queue_id1_tsa_assign; 3911 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3915 u8 queue_id1_pri_lvl; 3916 u8 queue_id1_bw_weight; 3917 u8 queue_id2; 3918 __le32 queue_id2_min_bw; 3919 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 3925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3934 __le32 queue_id2_max_bw; 3935 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 3941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3950 u8 queue_id2_tsa_assign; 3951 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3955 u8 queue_id2_pri_lvl; 3956 u8 queue_id2_bw_weight; 3957 u8 queue_id3; 3958 __le32 queue_id3_min_bw; 3959 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 3965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3974 __le32 queue_id3_max_bw; 3975 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3976 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3980 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 3981 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3982 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3983 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3990 u8 queue_id3_tsa_assign; 3991 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3995 u8 queue_id3_pri_lvl; 3996 u8 queue_id3_bw_weight; 3997 u8 queue_id4; 3998 __le32 queue_id4_min_bw; 3999 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 4005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4014 __le32 queue_id4_max_bw; 4015 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4020 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 4021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4030 u8 queue_id4_tsa_assign; 4031 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4035 u8 queue_id4_pri_lvl; 4036 u8 queue_id4_bw_weight; 4037 u8 queue_id5; 4038 __le32 queue_id5_min_bw; 4039 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4040 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4044 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 4045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4051 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4054 __le32 queue_id5_max_bw; 4055 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4056 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4057 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4058 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4059 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4060 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 4061 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4062 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4063 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4065 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4066 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4067 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4068 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4070 u8 queue_id5_tsa_assign; 4071 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4072 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4075 u8 queue_id5_pri_lvl; 4076 u8 queue_id5_bw_weight; 4077 u8 queue_id6; 4078 __le32 queue_id6_min_bw; 4079 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4080 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4084 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 4085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4091 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4094 __le32 queue_id6_max_bw; 4095 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4096 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4097 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4098 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4099 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4100 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 4101 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4102 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4103 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4105 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4106 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4107 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4108 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4110 u8 queue_id6_tsa_assign; 4111 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4112 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4115 u8 queue_id6_pri_lvl; 4116 u8 queue_id6_bw_weight; 4117 u8 queue_id7; 4118 __le32 queue_id7_min_bw; 4119 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 4125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4134 __le32 queue_id7_max_bw; 4135 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4136 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4140 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 4141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4145 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4146 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4147 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4148 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4150 u8 queue_id7_tsa_assign; 4151 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4152 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4153 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4154 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4155 u8 queue_id7_pri_lvl; 4156 u8 queue_id7_bw_weight; 4157 u8 unused_2[4]; 4158 u8 valid; 4159 }; 4160 4161 /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4162 struct hwrm_queue_cos2bw_cfg_input { 4163 __le16 req_type; 4164 __le16 cmpl_ring; 4165 __le16 seq_id; 4166 __le16 target_id; 4167 __le64 resp_addr; 4168 __le32 flags; 4169 __le32 enables; 4170 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4171 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4172 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4173 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4174 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4175 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4176 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4177 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4178 __le16 port_id; 4179 u8 queue_id0; 4180 u8 unused_0; 4181 __le32 queue_id0_min_bw; 4182 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4183 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4184 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4185 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4186 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4187 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4188 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4189 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4190 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4191 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4192 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4193 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4194 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4195 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4196 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4197 __le32 queue_id0_max_bw; 4198 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4199 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4200 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4201 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4202 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4203 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4204 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4205 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4206 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4207 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4208 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4209 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4210 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4211 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4212 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4213 u8 queue_id0_tsa_assign; 4214 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4215 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4216 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4217 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4218 u8 queue_id0_pri_lvl; 4219 u8 queue_id0_bw_weight; 4220 u8 queue_id1; 4221 __le32 queue_id1_min_bw; 4222 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4237 __le32 queue_id1_max_bw; 4238 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4253 u8 queue_id1_tsa_assign; 4254 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4258 u8 queue_id1_pri_lvl; 4259 u8 queue_id1_bw_weight; 4260 u8 queue_id2; 4261 __le32 queue_id2_min_bw; 4262 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4277 __le32 queue_id2_max_bw; 4278 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4293 u8 queue_id2_tsa_assign; 4294 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4298 u8 queue_id2_pri_lvl; 4299 u8 queue_id2_bw_weight; 4300 u8 queue_id3; 4301 __le32 queue_id3_min_bw; 4302 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4317 __le32 queue_id3_max_bw; 4318 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 4333 u8 queue_id3_tsa_assign; 4334 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 4335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 4336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 4338 u8 queue_id3_pri_lvl; 4339 u8 queue_id3_bw_weight; 4340 u8 queue_id4; 4341 __le32 queue_id4_min_bw; 4342 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 4348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 4357 __le32 queue_id4_max_bw; 4358 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 4364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 4373 u8 queue_id4_tsa_assign; 4374 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 4375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 4376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 4378 u8 queue_id4_pri_lvl; 4379 u8 queue_id4_bw_weight; 4380 u8 queue_id5; 4381 __le32 queue_id5_min_bw; 4382 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 4388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 4397 __le32 queue_id5_max_bw; 4398 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4399 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4403 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 4404 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4405 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4406 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 4413 u8 queue_id5_tsa_assign; 4414 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 4415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 4416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 4418 u8 queue_id5_pri_lvl; 4419 u8 queue_id5_bw_weight; 4420 u8 queue_id6; 4421 __le32 queue_id6_min_bw; 4422 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4427 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 4428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 4437 __le32 queue_id6_max_bw; 4438 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4443 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 4444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 4453 u8 queue_id6_tsa_assign; 4454 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 4455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 4456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 4458 u8 queue_id6_pri_lvl; 4459 u8 queue_id6_bw_weight; 4460 u8 queue_id7; 4461 __le32 queue_id7_min_bw; 4462 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 4468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 4477 __le32 queue_id7_max_bw; 4478 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 4484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 4493 u8 queue_id7_tsa_assign; 4494 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 4495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 4496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 4498 u8 queue_id7_pri_lvl; 4499 u8 queue_id7_bw_weight; 4500 u8 unused_1[5]; 4501 }; 4502 4503 /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 4504 struct hwrm_queue_cos2bw_cfg_output { 4505 __le16 error_code; 4506 __le16 req_type; 4507 __le16 seq_id; 4508 __le16 resp_len; 4509 u8 unused_0[7]; 4510 u8 valid; 4511 }; 4512 4513 /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 4514 struct hwrm_queue_dscp_qcaps_input { 4515 __le16 req_type; 4516 __le16 cmpl_ring; 4517 __le16 seq_id; 4518 __le16 target_id; 4519 __le64 resp_addr; 4520 u8 port_id; 4521 u8 unused_0[7]; 4522 }; 4523 4524 /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 4525 struct hwrm_queue_dscp_qcaps_output { 4526 __le16 error_code; 4527 __le16 req_type; 4528 __le16 seq_id; 4529 __le16 resp_len; 4530 u8 num_dscp_bits; 4531 u8 unused_0; 4532 __le16 max_entries; 4533 u8 unused_1[3]; 4534 u8 valid; 4535 }; 4536 4537 /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 4538 struct hwrm_queue_dscp2pri_qcfg_input { 4539 __le16 req_type; 4540 __le16 cmpl_ring; 4541 __le16 seq_id; 4542 __le16 target_id; 4543 __le64 resp_addr; 4544 __le64 dest_data_addr; 4545 u8 port_id; 4546 u8 unused_0; 4547 __le16 dest_data_buffer_size; 4548 u8 unused_1[4]; 4549 }; 4550 4551 /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 4552 struct hwrm_queue_dscp2pri_qcfg_output { 4553 __le16 error_code; 4554 __le16 req_type; 4555 __le16 seq_id; 4556 __le16 resp_len; 4557 __le16 entry_cnt; 4558 u8 default_pri; 4559 u8 unused_0[4]; 4560 u8 valid; 4561 }; 4562 4563 /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 4564 struct hwrm_queue_dscp2pri_cfg_input { 4565 __le16 req_type; 4566 __le16 cmpl_ring; 4567 __le16 seq_id; 4568 __le16 target_id; 4569 __le64 resp_addr; 4570 __le64 src_data_addr; 4571 __le32 flags; 4572 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 4573 __le32 enables; 4574 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 4575 u8 port_id; 4576 u8 default_pri; 4577 __le16 entry_cnt; 4578 u8 unused_0[4]; 4579 }; 4580 4581 /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 4582 struct hwrm_queue_dscp2pri_cfg_output { 4583 __le16 error_code; 4584 __le16 req_type; 4585 __le16 seq_id; 4586 __le16 resp_len; 4587 u8 unused_0[7]; 4588 u8 valid; 4589 }; 4590 4591 /* hwrm_vnic_alloc_input (size:192b/24B) */ 4592 struct hwrm_vnic_alloc_input { 4593 __le16 req_type; 4594 __le16 cmpl_ring; 4595 __le16 seq_id; 4596 __le16 target_id; 4597 __le64 resp_addr; 4598 __le32 flags; 4599 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 4600 u8 unused_0[4]; 4601 }; 4602 4603 /* hwrm_vnic_alloc_output (size:128b/16B) */ 4604 struct hwrm_vnic_alloc_output { 4605 __le16 error_code; 4606 __le16 req_type; 4607 __le16 seq_id; 4608 __le16 resp_len; 4609 __le32 vnic_id; 4610 u8 unused_0[3]; 4611 u8 valid; 4612 }; 4613 4614 /* hwrm_vnic_free_input (size:192b/24B) */ 4615 struct hwrm_vnic_free_input { 4616 __le16 req_type; 4617 __le16 cmpl_ring; 4618 __le16 seq_id; 4619 __le16 target_id; 4620 __le64 resp_addr; 4621 __le32 vnic_id; 4622 u8 unused_0[4]; 4623 }; 4624 4625 /* hwrm_vnic_free_output (size:128b/16B) */ 4626 struct hwrm_vnic_free_output { 4627 __le16 error_code; 4628 __le16 req_type; 4629 __le16 seq_id; 4630 __le16 resp_len; 4631 u8 unused_0[7]; 4632 u8 valid; 4633 }; 4634 4635 /* hwrm_vnic_cfg_input (size:320b/40B) */ 4636 struct hwrm_vnic_cfg_input { 4637 __le16 req_type; 4638 __le16 cmpl_ring; 4639 __le16 seq_id; 4640 __le16 target_id; 4641 __le64 resp_addr; 4642 __le32 flags; 4643 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 4644 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 4645 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 4646 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 4647 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 4648 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 4649 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 4650 __le32 enables; 4651 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 4652 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 4653 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 4654 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 4655 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 4656 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 4657 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 4658 __le16 vnic_id; 4659 __le16 dflt_ring_grp; 4660 __le16 rss_rule; 4661 __le16 cos_rule; 4662 __le16 lb_rule; 4663 __le16 mru; 4664 __le16 default_rx_ring_id; 4665 __le16 default_cmpl_ring_id; 4666 }; 4667 4668 /* hwrm_vnic_cfg_output (size:128b/16B) */ 4669 struct hwrm_vnic_cfg_output { 4670 __le16 error_code; 4671 __le16 req_type; 4672 __le16 seq_id; 4673 __le16 resp_len; 4674 u8 unused_0[7]; 4675 u8 valid; 4676 }; 4677 4678 /* hwrm_vnic_qcaps_input (size:192b/24B) */ 4679 struct hwrm_vnic_qcaps_input { 4680 __le16 req_type; 4681 __le16 cmpl_ring; 4682 __le16 seq_id; 4683 __le16 target_id; 4684 __le64 resp_addr; 4685 __le32 enables; 4686 u8 unused_0[4]; 4687 }; 4688 4689 /* hwrm_vnic_qcaps_output (size:192b/24B) */ 4690 struct hwrm_vnic_qcaps_output { 4691 __le16 error_code; 4692 __le16 req_type; 4693 __le16 seq_id; 4694 __le16 resp_len; 4695 __le16 mru; 4696 u8 unused_0[2]; 4697 __le32 flags; 4698 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 4699 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 4700 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 4701 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 4702 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 4703 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 4704 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 4705 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 4706 u8 unused_1[7]; 4707 u8 valid; 4708 }; 4709 4710 /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 4711 struct hwrm_vnic_tpa_cfg_input { 4712 __le16 req_type; 4713 __le16 cmpl_ring; 4714 __le16 seq_id; 4715 __le16 target_id; 4716 __le64 resp_addr; 4717 __le32 flags; 4718 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 4719 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 4720 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 4721 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 4722 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 4723 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4724 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 4725 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 4726 __le32 enables; 4727 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 4728 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 4729 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 4730 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 4731 __le16 vnic_id; 4732 __le16 max_agg_segs; 4733 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 4734 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 4735 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 4736 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 4737 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 4738 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 4739 __le16 max_aggs; 4740 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 4741 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 4742 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 4743 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 4744 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 4745 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 4746 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 4747 u8 unused_0[2]; 4748 __le32 max_agg_timer; 4749 __le32 min_agg_len; 4750 }; 4751 4752 /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 4753 struct hwrm_vnic_tpa_cfg_output { 4754 __le16 error_code; 4755 __le16 req_type; 4756 __le16 seq_id; 4757 __le16 resp_len; 4758 u8 unused_0[7]; 4759 u8 valid; 4760 }; 4761 4762 /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 4763 struct hwrm_vnic_tpa_qcfg_input { 4764 __le16 req_type; 4765 __le16 cmpl_ring; 4766 __le16 seq_id; 4767 __le16 target_id; 4768 __le64 resp_addr; 4769 __le16 vnic_id; 4770 u8 unused_0[6]; 4771 }; 4772 4773 /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 4774 struct hwrm_vnic_tpa_qcfg_output { 4775 __le16 error_code; 4776 __le16 req_type; 4777 __le16 seq_id; 4778 __le16 resp_len; 4779 __le32 flags; 4780 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 4781 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 4782 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 4783 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 4784 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 4785 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 4786 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 4787 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 4788 __le16 max_agg_segs; 4789 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 4790 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 4791 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 4792 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 4793 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 4794 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 4795 __le16 max_aggs; 4796 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 4797 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 4798 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 4799 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 4800 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 4801 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 4802 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 4803 __le32 max_agg_timer; 4804 __le32 min_agg_len; 4805 u8 unused_0[7]; 4806 u8 valid; 4807 }; 4808 4809 /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 4810 struct hwrm_vnic_rss_cfg_input { 4811 __le16 req_type; 4812 __le16 cmpl_ring; 4813 __le16 seq_id; 4814 __le16 target_id; 4815 __le64 resp_addr; 4816 __le32 hash_type; 4817 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 4818 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 4819 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 4820 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 4821 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 4822 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 4823 __le16 vnic_id; 4824 u8 ring_table_pair_index; 4825 u8 hash_mode_flags; 4826 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 4827 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 4828 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 4829 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 4830 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 4831 __le64 ring_grp_tbl_addr; 4832 __le64 hash_key_tbl_addr; 4833 __le16 rss_ctx_idx; 4834 u8 unused_1[6]; 4835 }; 4836 4837 /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 4838 struct hwrm_vnic_rss_cfg_output { 4839 __le16 error_code; 4840 __le16 req_type; 4841 __le16 seq_id; 4842 __le16 resp_len; 4843 u8 unused_0[7]; 4844 u8 valid; 4845 }; 4846 4847 /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 4848 struct hwrm_vnic_plcmodes_cfg_input { 4849 __le16 req_type; 4850 __le16 cmpl_ring; 4851 __le16 seq_id; 4852 __le16 target_id; 4853 __le64 resp_addr; 4854 __le32 flags; 4855 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 4856 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 4857 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 4858 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 4859 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 4860 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 4861 __le32 enables; 4862 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 4863 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 4864 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 4865 __le32 vnic_id; 4866 __le16 jumbo_thresh; 4867 __le16 hds_offset; 4868 __le16 hds_threshold; 4869 u8 unused_0[6]; 4870 }; 4871 4872 /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 4873 struct hwrm_vnic_plcmodes_cfg_output { 4874 __le16 error_code; 4875 __le16 req_type; 4876 __le16 seq_id; 4877 __le16 resp_len; 4878 u8 unused_0[7]; 4879 u8 valid; 4880 }; 4881 4882 /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 4883 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 4884 __le16 req_type; 4885 __le16 cmpl_ring; 4886 __le16 seq_id; 4887 __le16 target_id; 4888 __le64 resp_addr; 4889 }; 4890 4891 /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 4892 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 4893 __le16 error_code; 4894 __le16 req_type; 4895 __le16 seq_id; 4896 __le16 resp_len; 4897 __le16 rss_cos_lb_ctx_id; 4898 u8 unused_0[5]; 4899 u8 valid; 4900 }; 4901 4902 /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 4903 struct hwrm_vnic_rss_cos_lb_ctx_free_input { 4904 __le16 req_type; 4905 __le16 cmpl_ring; 4906 __le16 seq_id; 4907 __le16 target_id; 4908 __le64 resp_addr; 4909 __le16 rss_cos_lb_ctx_id; 4910 u8 unused_0[6]; 4911 }; 4912 4913 /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 4914 struct hwrm_vnic_rss_cos_lb_ctx_free_output { 4915 __le16 error_code; 4916 __le16 req_type; 4917 __le16 seq_id; 4918 __le16 resp_len; 4919 u8 unused_0[7]; 4920 u8 valid; 4921 }; 4922 4923 /* hwrm_ring_alloc_input (size:704b/88B) */ 4924 struct hwrm_ring_alloc_input { 4925 __le16 req_type; 4926 __le16 cmpl_ring; 4927 __le16 seq_id; 4928 __le16 target_id; 4929 __le64 resp_addr; 4930 __le32 enables; 4931 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 4932 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 4933 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 4934 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 4935 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 4936 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 4937 u8 ring_type; 4938 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 4939 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 4940 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 4941 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4942 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 4943 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 4944 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 4945 u8 unused_0; 4946 __le16 flags; 4947 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 4948 __le64 page_tbl_addr; 4949 __le32 fbo; 4950 u8 page_size; 4951 u8 page_tbl_depth; 4952 u8 unused_1[2]; 4953 __le32 length; 4954 __le16 logical_id; 4955 __le16 cmpl_ring_id; 4956 __le16 queue_id; 4957 __le16 rx_buf_size; 4958 __le16 rx_ring_id; 4959 __le16 nq_ring_id; 4960 __le16 ring_arb_cfg; 4961 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 4962 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 4963 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 4964 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 4965 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 4966 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 4967 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 4968 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 4969 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 4970 __le16 unused_3; 4971 __le32 reserved3; 4972 __le32 stat_ctx_id; 4973 __le32 reserved4; 4974 __le32 max_bw; 4975 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4976 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 4977 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 4978 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 4979 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 4980 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 4981 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4982 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 4983 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4984 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4985 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4986 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4987 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4988 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4989 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 4990 u8 int_mode; 4991 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 4992 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 4993 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 4994 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 4995 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 4996 u8 unused_4[3]; 4997 __le64 cq_handle; 4998 }; 4999 5000 /* hwrm_ring_alloc_output (size:128b/16B) */ 5001 struct hwrm_ring_alloc_output { 5002 __le16 error_code; 5003 __le16 req_type; 5004 __le16 seq_id; 5005 __le16 resp_len; 5006 __le16 ring_id; 5007 __le16 logical_ring_id; 5008 u8 unused_0[3]; 5009 u8 valid; 5010 }; 5011 5012 /* hwrm_ring_free_input (size:192b/24B) */ 5013 struct hwrm_ring_free_input { 5014 __le16 req_type; 5015 __le16 cmpl_ring; 5016 __le16 seq_id; 5017 __le16 target_id; 5018 __le64 resp_addr; 5019 u8 ring_type; 5020 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5021 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5022 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5023 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5024 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 5025 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 5026 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5027 u8 unused_0; 5028 __le16 ring_id; 5029 u8 unused_1[4]; 5030 }; 5031 5032 /* hwrm_ring_free_output (size:128b/16B) */ 5033 struct hwrm_ring_free_output { 5034 __le16 error_code; 5035 __le16 req_type; 5036 __le16 seq_id; 5037 __le16 resp_len; 5038 u8 unused_0[7]; 5039 u8 valid; 5040 }; 5041 5042 /* hwrm_ring_reset_input (size:192b/24B) */ 5043 struct hwrm_ring_reset_input { 5044 __le16 req_type; 5045 __le16 cmpl_ring; 5046 __le16 seq_id; 5047 __le16 target_id; 5048 __le64 resp_addr; 5049 u8 ring_type; 5050 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 5051 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 5052 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 5053 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5054 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL 5055 u8 unused_0; 5056 __le16 ring_id; 5057 u8 unused_1[4]; 5058 }; 5059 5060 /* hwrm_ring_reset_output (size:128b/16B) */ 5061 struct hwrm_ring_reset_output { 5062 __le16 error_code; 5063 __le16 req_type; 5064 __le16 seq_id; 5065 __le16 resp_len; 5066 u8 unused_0[4]; 5067 u8 consumer_idx[3]; 5068 u8 valid; 5069 }; 5070 5071 /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 5072 struct hwrm_ring_aggint_qcaps_input { 5073 __le16 req_type; 5074 __le16 cmpl_ring; 5075 __le16 seq_id; 5076 __le16 target_id; 5077 __le64 resp_addr; 5078 }; 5079 5080 /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 5081 struct hwrm_ring_aggint_qcaps_output { 5082 __le16 error_code; 5083 __le16 req_type; 5084 __le16 seq_id; 5085 __le16 resp_len; 5086 __le32 cmpl_params; 5087 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 5088 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 5089 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 5090 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 5091 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 5092 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 5093 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 5094 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 5095 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 5096 __le32 nq_params; 5097 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 5098 __le16 num_cmpl_dma_aggr_min; 5099 __le16 num_cmpl_dma_aggr_max; 5100 __le16 num_cmpl_dma_aggr_during_int_min; 5101 __le16 num_cmpl_dma_aggr_during_int_max; 5102 __le16 cmpl_aggr_dma_tmr_min; 5103 __le16 cmpl_aggr_dma_tmr_max; 5104 __le16 cmpl_aggr_dma_tmr_during_int_min; 5105 __le16 cmpl_aggr_dma_tmr_during_int_max; 5106 __le16 int_lat_tmr_min_min; 5107 __le16 int_lat_tmr_min_max; 5108 __le16 int_lat_tmr_max_min; 5109 __le16 int_lat_tmr_max_max; 5110 __le16 num_cmpl_aggr_int_min; 5111 __le16 num_cmpl_aggr_int_max; 5112 __le16 timer_units; 5113 u8 unused_0[1]; 5114 u8 valid; 5115 }; 5116 5117 /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5118 struct hwrm_ring_cmpl_ring_qaggint_params_input { 5119 __le16 req_type; 5120 __le16 cmpl_ring; 5121 __le16 seq_id; 5122 __le16 target_id; 5123 __le64 resp_addr; 5124 __le16 ring_id; 5125 u8 unused_0[6]; 5126 }; 5127 5128 /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5129 struct hwrm_ring_cmpl_ring_qaggint_params_output { 5130 __le16 error_code; 5131 __le16 req_type; 5132 __le16 seq_id; 5133 __le16 resp_len; 5134 __le16 flags; 5135 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5136 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5137 __le16 num_cmpl_dma_aggr; 5138 __le16 num_cmpl_dma_aggr_during_int; 5139 __le16 cmpl_aggr_dma_tmr; 5140 __le16 cmpl_aggr_dma_tmr_during_int; 5141 __le16 int_lat_tmr_min; 5142 __le16 int_lat_tmr_max; 5143 __le16 num_cmpl_aggr_int; 5144 u8 unused_0[7]; 5145 u8 valid; 5146 }; 5147 5148 /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5149 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5150 __le16 req_type; 5151 __le16 cmpl_ring; 5152 __le16 seq_id; 5153 __le16 target_id; 5154 __le64 resp_addr; 5155 __le16 ring_id; 5156 __le16 flags; 5157 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5158 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 5159 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5160 __le16 num_cmpl_dma_aggr; 5161 __le16 num_cmpl_dma_aggr_during_int; 5162 __le16 cmpl_aggr_dma_tmr; 5163 __le16 cmpl_aggr_dma_tmr_during_int; 5164 __le16 int_lat_tmr_min; 5165 __le16 int_lat_tmr_max; 5166 __le16 num_cmpl_aggr_int; 5167 __le16 enables; 5168 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 5169 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 5170 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 5171 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 5172 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 5173 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 5174 u8 unused_0[4]; 5175 }; 5176 5177 /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5178 struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5179 __le16 error_code; 5180 __le16 req_type; 5181 __le16 seq_id; 5182 __le16 resp_len; 5183 u8 unused_0[7]; 5184 u8 valid; 5185 }; 5186 5187 /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5188 struct hwrm_ring_grp_alloc_input { 5189 __le16 req_type; 5190 __le16 cmpl_ring; 5191 __le16 seq_id; 5192 __le16 target_id; 5193 __le64 resp_addr; 5194 __le16 cr; 5195 __le16 rr; 5196 __le16 ar; 5197 __le16 sc; 5198 }; 5199 5200 /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5201 struct hwrm_ring_grp_alloc_output { 5202 __le16 error_code; 5203 __le16 req_type; 5204 __le16 seq_id; 5205 __le16 resp_len; 5206 __le32 ring_group_id; 5207 u8 unused_0[3]; 5208 u8 valid; 5209 }; 5210 5211 /* hwrm_ring_grp_free_input (size:192b/24B) */ 5212 struct hwrm_ring_grp_free_input { 5213 __le16 req_type; 5214 __le16 cmpl_ring; 5215 __le16 seq_id; 5216 __le16 target_id; 5217 __le64 resp_addr; 5218 __le32 ring_group_id; 5219 u8 unused_0[4]; 5220 }; 5221 5222 /* hwrm_ring_grp_free_output (size:128b/16B) */ 5223 struct hwrm_ring_grp_free_output { 5224 __le16 error_code; 5225 __le16 req_type; 5226 __le16 seq_id; 5227 __le16 resp_len; 5228 u8 unused_0[7]; 5229 u8 valid; 5230 }; 5231 #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 5232 #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 5233 #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 5234 #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5235 5236 /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5237 struct hwrm_cfa_l2_filter_alloc_input { 5238 __le16 req_type; 5239 __le16 cmpl_ring; 5240 __le16 seq_id; 5241 __le16 target_id; 5242 __le64 resp_addr; 5243 __le32 flags; 5244 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5245 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5246 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 5247 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5248 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5249 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5250 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 5251 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 5252 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 5253 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 5254 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 5255 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 5256 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 5257 __le32 enables; 5258 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5259 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5260 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5261 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5262 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5263 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5264 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5265 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5266 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5267 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5268 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5269 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5270 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5271 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 5272 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 5273 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5274 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5275 u8 l2_addr[6]; 5276 u8 unused_0[2]; 5277 u8 l2_addr_mask[6]; 5278 __le16 l2_ovlan; 5279 __le16 l2_ovlan_mask; 5280 __le16 l2_ivlan; 5281 __le16 l2_ivlan_mask; 5282 u8 unused_1[2]; 5283 u8 t_l2_addr[6]; 5284 u8 unused_2[2]; 5285 u8 t_l2_addr_mask[6]; 5286 __le16 t_l2_ovlan; 5287 __le16 t_l2_ovlan_mask; 5288 __le16 t_l2_ivlan; 5289 __le16 t_l2_ivlan_mask; 5290 u8 src_type; 5291 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 5292 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 5293 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 5294 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 5295 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 5296 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 5297 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 5298 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 5299 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 5300 u8 unused_3; 5301 __le32 src_id; 5302 u8 tunnel_type; 5303 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5304 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5305 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5306 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5307 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5308 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5309 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5310 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5311 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5312 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5313 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5314 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5315 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5316 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5317 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5318 u8 unused_4; 5319 __le16 dst_id; 5320 __le16 mirror_vnic_id; 5321 u8 pri_hint; 5322 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5323 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 5324 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 5325 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 5326 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 5327 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 5328 u8 unused_5; 5329 __le32 unused_6; 5330 __le64 l2_filter_id_hint; 5331 }; 5332 5333 /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 5334 struct hwrm_cfa_l2_filter_alloc_output { 5335 __le16 error_code; 5336 __le16 req_type; 5337 __le16 seq_id; 5338 __le16 resp_len; 5339 __le64 l2_filter_id; 5340 __le32 flow_id; 5341 u8 unused_0[3]; 5342 u8 valid; 5343 }; 5344 5345 /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 5346 struct hwrm_cfa_l2_filter_free_input { 5347 __le16 req_type; 5348 __le16 cmpl_ring; 5349 __le16 seq_id; 5350 __le16 target_id; 5351 __le64 resp_addr; 5352 __le64 l2_filter_id; 5353 }; 5354 5355 /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 5356 struct hwrm_cfa_l2_filter_free_output { 5357 __le16 error_code; 5358 __le16 req_type; 5359 __le16 seq_id; 5360 __le16 resp_len; 5361 u8 unused_0[7]; 5362 u8 valid; 5363 }; 5364 5365 /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 5366 struct hwrm_cfa_l2_filter_cfg_input { 5367 __le16 req_type; 5368 __le16 cmpl_ring; 5369 __le16 seq_id; 5370 __le16 target_id; 5371 __le64 resp_addr; 5372 __le32 flags; 5373 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 5374 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 5375 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 5376 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 5377 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 5378 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 5379 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 5380 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 5381 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 5382 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 5383 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 5384 __le32 enables; 5385 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 5386 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5387 __le64 l2_filter_id; 5388 __le32 dst_id; 5389 __le32 new_mirror_vnic_id; 5390 }; 5391 5392 /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 5393 struct hwrm_cfa_l2_filter_cfg_output { 5394 __le16 error_code; 5395 __le16 req_type; 5396 __le16 seq_id; 5397 __le16 resp_len; 5398 u8 unused_0[7]; 5399 u8 valid; 5400 }; 5401 5402 /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 5403 struct hwrm_cfa_l2_set_rx_mask_input { 5404 __le16 req_type; 5405 __le16 cmpl_ring; 5406 __le16 seq_id; 5407 __le16 target_id; 5408 __le64 resp_addr; 5409 __le32 vnic_id; 5410 __le32 mask; 5411 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 5412 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 5413 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 5414 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 5415 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 5416 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 5417 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 5418 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 5419 __le64 mc_tbl_addr; 5420 __le32 num_mc_entries; 5421 u8 unused_0[4]; 5422 __le64 vlan_tag_tbl_addr; 5423 __le32 num_vlan_tags; 5424 u8 unused_1[4]; 5425 }; 5426 5427 /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 5428 struct hwrm_cfa_l2_set_rx_mask_output { 5429 __le16 error_code; 5430 __le16 req_type; 5431 __le16 seq_id; 5432 __le16 resp_len; 5433 u8 unused_0[7]; 5434 u8 valid; 5435 }; 5436 5437 /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 5438 struct hwrm_cfa_l2_set_rx_mask_cmd_err { 5439 u8 code; 5440 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 5441 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 5442 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 5443 u8 unused_0[7]; 5444 }; 5445 5446 /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 5447 struct hwrm_cfa_tunnel_filter_alloc_input { 5448 __le16 req_type; 5449 __le16 cmpl_ring; 5450 __le16 seq_id; 5451 __le16 target_id; 5452 __le64 resp_addr; 5453 __le32 flags; 5454 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5455 __le32 enables; 5456 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5457 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 5458 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 5459 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 5460 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 5461 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 5462 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 5463 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 5464 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 5465 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 5466 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 5467 __le64 l2_filter_id; 5468 u8 l2_addr[6]; 5469 __le16 l2_ivlan; 5470 __le32 l3_addr[4]; 5471 __le32 t_l3_addr[4]; 5472 u8 l3_addr_type; 5473 u8 t_l3_addr_type; 5474 u8 tunnel_type; 5475 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5476 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5477 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5478 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5479 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5480 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5481 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5482 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5483 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5484 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5485 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5486 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5487 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5488 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5489 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5490 u8 tunnel_flags; 5491 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 5492 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 5493 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 5494 __le32 vni; 5495 __le32 dst_vnic_id; 5496 __le32 mirror_vnic_id; 5497 }; 5498 5499 /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 5500 struct hwrm_cfa_tunnel_filter_alloc_output { 5501 __le16 error_code; 5502 __le16 req_type; 5503 __le16 seq_id; 5504 __le16 resp_len; 5505 __le64 tunnel_filter_id; 5506 __le32 flow_id; 5507 u8 unused_0[3]; 5508 u8 valid; 5509 }; 5510 5511 /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 5512 struct hwrm_cfa_tunnel_filter_free_input { 5513 __le16 req_type; 5514 __le16 cmpl_ring; 5515 __le16 seq_id; 5516 __le16 target_id; 5517 __le64 resp_addr; 5518 __le64 tunnel_filter_id; 5519 }; 5520 5521 /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 5522 struct hwrm_cfa_tunnel_filter_free_output { 5523 __le16 error_code; 5524 __le16 req_type; 5525 __le16 seq_id; 5526 __le16 resp_len; 5527 u8 unused_0[7]; 5528 u8 valid; 5529 }; 5530 5531 /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 5532 struct hwrm_vxlan_ipv4_hdr { 5533 u8 ver_hlen; 5534 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 5535 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 5536 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 5537 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 5538 u8 tos; 5539 __be16 ip_id; 5540 __be16 flags_frag_offset; 5541 u8 ttl; 5542 u8 protocol; 5543 __be32 src_ip_addr; 5544 __be32 dest_ip_addr; 5545 }; 5546 5547 /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 5548 struct hwrm_vxlan_ipv6_hdr { 5549 __be32 ver_tc_flow_label; 5550 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 5551 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 5552 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 5553 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 5554 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 5555 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 5556 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 5557 __be16 payload_len; 5558 u8 next_hdr; 5559 u8 ttl; 5560 __be32 src_ip_addr[4]; 5561 __be32 dest_ip_addr[4]; 5562 }; 5563 5564 /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 5565 struct hwrm_cfa_encap_data_vxlan { 5566 u8 src_mac_addr[6]; 5567 __le16 unused_0; 5568 u8 dst_mac_addr[6]; 5569 u8 num_vlan_tags; 5570 u8 unused_1; 5571 __be16 ovlan_tpid; 5572 __be16 ovlan_tci; 5573 __be16 ivlan_tpid; 5574 __be16 ivlan_tci; 5575 __le32 l3[10]; 5576 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 5577 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 5578 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 5579 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 5580 __be16 src_port; 5581 __be16 dst_port; 5582 __be32 vni; 5583 u8 hdr_rsvd0[3]; 5584 u8 hdr_rsvd1; 5585 u8 hdr_flags; 5586 u8 unused[3]; 5587 }; 5588 5589 /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 5590 struct hwrm_cfa_encap_record_alloc_input { 5591 __le16 req_type; 5592 __le16 cmpl_ring; 5593 __le16 seq_id; 5594 __le16 target_id; 5595 __le64 resp_addr; 5596 __le32 flags; 5597 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5598 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 5599 u8 encap_type; 5600 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 5601 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 5602 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 5603 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 5604 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 5605 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 5606 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 5607 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 5608 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 5609 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 5610 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 5611 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 5612 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 5613 u8 unused_0[3]; 5614 __le32 encap_data[20]; 5615 }; 5616 5617 /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 5618 struct hwrm_cfa_encap_record_alloc_output { 5619 __le16 error_code; 5620 __le16 req_type; 5621 __le16 seq_id; 5622 __le16 resp_len; 5623 __le32 encap_record_id; 5624 u8 unused_0[3]; 5625 u8 valid; 5626 }; 5627 5628 /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 5629 struct hwrm_cfa_encap_record_free_input { 5630 __le16 req_type; 5631 __le16 cmpl_ring; 5632 __le16 seq_id; 5633 __le16 target_id; 5634 __le64 resp_addr; 5635 __le32 encap_record_id; 5636 u8 unused_0[4]; 5637 }; 5638 5639 /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 5640 struct hwrm_cfa_encap_record_free_output { 5641 __le16 error_code; 5642 __le16 req_type; 5643 __le16 seq_id; 5644 __le16 resp_len; 5645 u8 unused_0[7]; 5646 u8 valid; 5647 }; 5648 5649 /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 5650 struct hwrm_cfa_ntuple_filter_alloc_input { 5651 __le16 req_type; 5652 __le16 cmpl_ring; 5653 __le16 seq_id; 5654 __le16 target_id; 5655 __le64 resp_addr; 5656 __le32 flags; 5657 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 5658 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 5659 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 5660 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 5661 __le32 enables; 5662 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 5663 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 5664 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 5665 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 5666 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 5667 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 5668 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 5669 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 5670 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 5671 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 5672 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 5673 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 5674 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 5675 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 5676 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 5677 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 5678 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 5679 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 5680 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 5681 __le64 l2_filter_id; 5682 u8 src_macaddr[6]; 5683 __be16 ethertype; 5684 u8 ip_addr_type; 5685 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5686 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5687 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5688 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5689 u8 ip_protocol; 5690 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5691 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5692 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5693 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5694 __le16 dst_id; 5695 __le16 mirror_vnic_id; 5696 u8 tunnel_type; 5697 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5698 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5699 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5700 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5701 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5702 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5703 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5704 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5705 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5706 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5707 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5708 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5709 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5710 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5711 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5712 u8 pri_hint; 5713 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 5714 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 5715 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 5716 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 5717 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 5718 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 5719 __be32 src_ipaddr[4]; 5720 __be32 src_ipaddr_mask[4]; 5721 __be32 dst_ipaddr[4]; 5722 __be32 dst_ipaddr_mask[4]; 5723 __be16 src_port; 5724 __be16 src_port_mask; 5725 __be16 dst_port; 5726 __be16 dst_port_mask; 5727 __le64 ntuple_filter_id_hint; 5728 }; 5729 5730 /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 5731 struct hwrm_cfa_ntuple_filter_alloc_output { 5732 __le16 error_code; 5733 __le16 req_type; 5734 __le16 seq_id; 5735 __le16 resp_len; 5736 __le64 ntuple_filter_id; 5737 __le32 flow_id; 5738 u8 unused_0[3]; 5739 u8 valid; 5740 }; 5741 5742 /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 5743 struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 5744 u8 code; 5745 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 5746 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 5747 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 5748 u8 unused_0[7]; 5749 }; 5750 5751 /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 5752 struct hwrm_cfa_ntuple_filter_free_input { 5753 __le16 req_type; 5754 __le16 cmpl_ring; 5755 __le16 seq_id; 5756 __le16 target_id; 5757 __le64 resp_addr; 5758 __le64 ntuple_filter_id; 5759 }; 5760 5761 /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 5762 struct hwrm_cfa_ntuple_filter_free_output { 5763 __le16 error_code; 5764 __le16 req_type; 5765 __le16 seq_id; 5766 __le16 resp_len; 5767 u8 unused_0[7]; 5768 u8 valid; 5769 }; 5770 5771 /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 5772 struct hwrm_cfa_ntuple_filter_cfg_input { 5773 __le16 req_type; 5774 __le16 cmpl_ring; 5775 __le16 seq_id; 5776 __le16 target_id; 5777 __le64 resp_addr; 5778 __le32 enables; 5779 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 5780 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 5781 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 5782 __le32 flags; 5783 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 5784 __le64 ntuple_filter_id; 5785 __le32 new_dst_id; 5786 __le32 new_mirror_vnic_id; 5787 __le16 new_meter_instance_id; 5788 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 5789 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 5790 u8 unused_1[6]; 5791 }; 5792 5793 /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 5794 struct hwrm_cfa_ntuple_filter_cfg_output { 5795 __le16 error_code; 5796 __le16 req_type; 5797 __le16 seq_id; 5798 __le16 resp_len; 5799 u8 unused_0[7]; 5800 u8 valid; 5801 }; 5802 5803 /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 5804 struct hwrm_cfa_decap_filter_alloc_input { 5805 __le16 req_type; 5806 __le16 cmpl_ring; 5807 __le16 seq_id; 5808 __le16 target_id; 5809 __le64 resp_addr; 5810 __le32 flags; 5811 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 5812 __le32 enables; 5813 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 5814 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 5815 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 5816 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 5817 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 5818 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 5819 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 5820 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 5821 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 5822 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 5823 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 5824 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 5825 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 5826 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 5827 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 5828 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 5829 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 5830 __be32 tunnel_id; 5831 u8 tunnel_type; 5832 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5833 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5834 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5835 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5836 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5837 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5838 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5839 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5840 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5841 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5842 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5843 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5844 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5845 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5846 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5847 u8 unused_0; 5848 __le16 unused_1; 5849 u8 src_macaddr[6]; 5850 u8 unused_2[2]; 5851 u8 dst_macaddr[6]; 5852 __be16 ovlan_vid; 5853 __be16 ivlan_vid; 5854 __be16 t_ovlan_vid; 5855 __be16 t_ivlan_vid; 5856 __be16 ethertype; 5857 u8 ip_addr_type; 5858 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 5859 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 5860 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 5861 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 5862 u8 ip_protocol; 5863 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 5864 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 5865 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 5866 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 5867 __le16 unused_3; 5868 __le32 unused_4; 5869 __be32 src_ipaddr[4]; 5870 __be32 dst_ipaddr[4]; 5871 __be16 src_port; 5872 __be16 dst_port; 5873 __le16 dst_id; 5874 __le16 l2_ctxt_ref_id; 5875 }; 5876 5877 /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 5878 struct hwrm_cfa_decap_filter_alloc_output { 5879 __le16 error_code; 5880 __le16 req_type; 5881 __le16 seq_id; 5882 __le16 resp_len; 5883 __le32 decap_filter_id; 5884 u8 unused_0[3]; 5885 u8 valid; 5886 }; 5887 5888 /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 5889 struct hwrm_cfa_decap_filter_free_input { 5890 __le16 req_type; 5891 __le16 cmpl_ring; 5892 __le16 seq_id; 5893 __le16 target_id; 5894 __le64 resp_addr; 5895 __le32 decap_filter_id; 5896 u8 unused_0[4]; 5897 }; 5898 5899 /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 5900 struct hwrm_cfa_decap_filter_free_output { 5901 __le16 error_code; 5902 __le16 req_type; 5903 __le16 seq_id; 5904 __le16 resp_len; 5905 u8 unused_0[7]; 5906 u8 valid; 5907 }; 5908 5909 /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 5910 struct hwrm_cfa_flow_alloc_input { 5911 __le16 req_type; 5912 __le16 cmpl_ring; 5913 __le16 seq_id; 5914 __le16 target_id; 5915 __le64 resp_addr; 5916 __le16 flags; 5917 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 5918 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 5919 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 5920 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 5921 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 5922 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 5923 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 5924 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 5925 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 5926 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 5927 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 5928 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 5929 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 5930 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 5931 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 5932 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 5933 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 5934 __le16 src_fid; 5935 __le32 tunnel_handle; 5936 __le16 action_flags; 5937 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 5938 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 5939 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 5940 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 5941 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 5942 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 5943 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 5944 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 5945 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 5946 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 5947 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 5948 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 5949 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 5950 __le16 dst_fid; 5951 __be16 l2_rewrite_vlan_tpid; 5952 __be16 l2_rewrite_vlan_tci; 5953 __le16 act_meter_id; 5954 __le16 ref_flow_handle; 5955 __be16 ethertype; 5956 __be16 outer_vlan_tci; 5957 __be16 dmac[3]; 5958 __be16 inner_vlan_tci; 5959 __be16 smac[3]; 5960 u8 ip_dst_mask_len; 5961 u8 ip_src_mask_len; 5962 __be32 ip_dst[4]; 5963 __be32 ip_src[4]; 5964 __be16 l4_src_port; 5965 __be16 l4_src_port_mask; 5966 __be16 l4_dst_port; 5967 __be16 l4_dst_port_mask; 5968 __be32 nat_ip_address[4]; 5969 __be16 l2_rewrite_dmac[3]; 5970 __be16 nat_port; 5971 __be16 l2_rewrite_smac[3]; 5972 u8 ip_proto; 5973 u8 tunnel_type; 5974 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 5975 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5976 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 5977 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 5978 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 5979 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5980 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 5981 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 5982 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 5983 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5984 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 5985 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 5986 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 5987 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 5988 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 5989 }; 5990 5991 /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 5992 struct hwrm_cfa_flow_alloc_output { 5993 __le16 error_code; 5994 __le16 req_type; 5995 __le16 seq_id; 5996 __le16 resp_len; 5997 __le16 flow_handle; 5998 u8 unused_0[2]; 5999 __le32 flow_id; 6000 __le64 ext_flow_handle; 6001 __le32 flow_counter_id; 6002 u8 unused_1[3]; 6003 u8 valid; 6004 }; 6005 6006 /* hwrm_cfa_flow_free_input (size:256b/32B) */ 6007 struct hwrm_cfa_flow_free_input { 6008 __le16 req_type; 6009 __le16 cmpl_ring; 6010 __le16 seq_id; 6011 __le16 target_id; 6012 __le64 resp_addr; 6013 __le16 flow_handle; 6014 u8 unused_0[6]; 6015 __le64 ext_flow_handle; 6016 }; 6017 6018 /* hwrm_cfa_flow_free_output (size:256b/32B) */ 6019 struct hwrm_cfa_flow_free_output { 6020 __le16 error_code; 6021 __le16 req_type; 6022 __le16 seq_id; 6023 __le16 resp_len; 6024 __le64 packet; 6025 __le64 byte; 6026 u8 unused_0[7]; 6027 u8 valid; 6028 }; 6029 6030 /* hwrm_cfa_flow_info_input (size:256b/32B) */ 6031 struct hwrm_cfa_flow_info_input { 6032 __le16 req_type; 6033 __le16 cmpl_ring; 6034 __le16 seq_id; 6035 __le16 target_id; 6036 __le64 resp_addr; 6037 __le16 flow_handle; 6038 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 6039 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 6040 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 6041 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 6042 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 6043 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 6044 u8 unused_0[6]; 6045 __le64 ext_flow_handle; 6046 }; 6047 6048 /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 6049 struct hwrm_cfa_flow_info_output { 6050 __le16 error_code; 6051 __le16 req_type; 6052 __le16 seq_id; 6053 __le16 resp_len; 6054 u8 flags; 6055 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 6056 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 6057 u8 profile; 6058 __le16 src_fid; 6059 __le16 dst_fid; 6060 __le16 l2_ctxt_id; 6061 __le64 em_info; 6062 __le64 tcam_info; 6063 __le64 vfp_tcam_info; 6064 __le16 ar_id; 6065 __le16 flow_handle; 6066 __le32 tunnel_handle; 6067 __le16 flow_timer; 6068 u8 unused_0[6]; 6069 __le32 flow_key_data[130]; 6070 __le32 flow_action_info[30]; 6071 u8 unused_1[7]; 6072 u8 valid; 6073 }; 6074 6075 /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 6076 struct hwrm_cfa_flow_stats_input { 6077 __le16 req_type; 6078 __le16 cmpl_ring; 6079 __le16 seq_id; 6080 __le16 target_id; 6081 __le64 resp_addr; 6082 __le16 num_flows; 6083 __le16 flow_handle_0; 6084 __le16 flow_handle_1; 6085 __le16 flow_handle_2; 6086 __le16 flow_handle_3; 6087 __le16 flow_handle_4; 6088 __le16 flow_handle_5; 6089 __le16 flow_handle_6; 6090 __le16 flow_handle_7; 6091 __le16 flow_handle_8; 6092 __le16 flow_handle_9; 6093 u8 unused_0[2]; 6094 __le32 flow_id_0; 6095 __le32 flow_id_1; 6096 __le32 flow_id_2; 6097 __le32 flow_id_3; 6098 __le32 flow_id_4; 6099 __le32 flow_id_5; 6100 __le32 flow_id_6; 6101 __le32 flow_id_7; 6102 __le32 flow_id_8; 6103 __le32 flow_id_9; 6104 }; 6105 6106 /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 6107 struct hwrm_cfa_flow_stats_output { 6108 __le16 error_code; 6109 __le16 req_type; 6110 __le16 seq_id; 6111 __le16 resp_len; 6112 __le64 packet_0; 6113 __le64 packet_1; 6114 __le64 packet_2; 6115 __le64 packet_3; 6116 __le64 packet_4; 6117 __le64 packet_5; 6118 __le64 packet_6; 6119 __le64 packet_7; 6120 __le64 packet_8; 6121 __le64 packet_9; 6122 __le64 byte_0; 6123 __le64 byte_1; 6124 __le64 byte_2; 6125 __le64 byte_3; 6126 __le64 byte_4; 6127 __le64 byte_5; 6128 __le64 byte_6; 6129 __le64 byte_7; 6130 __le64 byte_8; 6131 __le64 byte_9; 6132 u8 unused_0[7]; 6133 u8 valid; 6134 }; 6135 6136 /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6137 struct hwrm_cfa_vfr_alloc_input { 6138 __le16 req_type; 6139 __le16 cmpl_ring; 6140 __le16 seq_id; 6141 __le16 target_id; 6142 __le64 resp_addr; 6143 __le16 vf_id; 6144 __le16 reserved; 6145 u8 unused_0[4]; 6146 char vfr_name[32]; 6147 }; 6148 6149 /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6150 struct hwrm_cfa_vfr_alloc_output { 6151 __le16 error_code; 6152 __le16 req_type; 6153 __le16 seq_id; 6154 __le16 resp_len; 6155 __le16 rx_cfa_code; 6156 __le16 tx_cfa_action; 6157 u8 unused_0[3]; 6158 u8 valid; 6159 }; 6160 6161 /* hwrm_cfa_vfr_free_input (size:384b/48B) */ 6162 struct hwrm_cfa_vfr_free_input { 6163 __le16 req_type; 6164 __le16 cmpl_ring; 6165 __le16 seq_id; 6166 __le16 target_id; 6167 __le64 resp_addr; 6168 char vfr_name[32]; 6169 }; 6170 6171 /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6172 struct hwrm_cfa_vfr_free_output { 6173 __le16 error_code; 6174 __le16 req_type; 6175 __le16 seq_id; 6176 __le16 resp_len; 6177 u8 unused_0[7]; 6178 u8 valid; 6179 }; 6180 6181 /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 6182 struct hwrm_cfa_eem_qcaps_input { 6183 __le16 req_type; 6184 __le16 cmpl_ring; 6185 __le16 seq_id; 6186 __le16 target_id; 6187 __le64 resp_addr; 6188 __le32 flags; 6189 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 6190 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 6191 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6192 __le32 unused_0; 6193 }; 6194 6195 /* hwrm_cfa_eem_qcaps_output (size:256b/32B) */ 6196 struct hwrm_cfa_eem_qcaps_output { 6197 __le16 error_code; 6198 __le16 req_type; 6199 __le16 seq_id; 6200 __le16 resp_len; 6201 __le32 flags; 6202 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 6203 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 6204 __le32 unused_0; 6205 __le32 supported; 6206 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 6207 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 6208 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 6209 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 6210 __le32 max_entries_supported; 6211 __le16 key_entry_size; 6212 __le16 record_entry_size; 6213 __le16 efc_entry_size; 6214 u8 unused_1; 6215 u8 valid; 6216 }; 6217 6218 /* hwrm_cfa_eem_cfg_input (size:320b/40B) */ 6219 struct hwrm_cfa_eem_cfg_input { 6220 __le16 req_type; 6221 __le16 cmpl_ring; 6222 __le16 seq_id; 6223 __le16 target_id; 6224 __le64 resp_addr; 6225 __le32 flags; 6226 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 6227 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 6228 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 6229 __le32 unused_0; 6230 __le32 num_entries; 6231 __le32 unused_1; 6232 __le16 key0_ctx_id; 6233 __le16 key1_ctx_id; 6234 __le16 record_ctx_id; 6235 __le16 efc_ctx_id; 6236 }; 6237 6238 /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 6239 struct hwrm_cfa_eem_cfg_output { 6240 __le16 error_code; 6241 __le16 req_type; 6242 __le16 seq_id; 6243 __le16 resp_len; 6244 u8 unused_0[7]; 6245 u8 valid; 6246 }; 6247 6248 /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 6249 struct hwrm_cfa_eem_qcfg_input { 6250 __le16 req_type; 6251 __le16 cmpl_ring; 6252 __le16 seq_id; 6253 __le16 target_id; 6254 __le64 resp_addr; 6255 __le32 flags; 6256 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 6257 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 6258 __le32 unused_0; 6259 }; 6260 6261 /* hwrm_cfa_eem_qcfg_output (size:128b/16B) */ 6262 struct hwrm_cfa_eem_qcfg_output { 6263 __le16 error_code; 6264 __le16 req_type; 6265 __le16 seq_id; 6266 __le16 resp_len; 6267 __le32 flags; 6268 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 6269 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 6270 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 6271 __le32 num_entries; 6272 }; 6273 6274 /* hwrm_cfa_eem_op_input (size:192b/24B) */ 6275 struct hwrm_cfa_eem_op_input { 6276 __le16 req_type; 6277 __le16 cmpl_ring; 6278 __le16 seq_id; 6279 __le16 target_id; 6280 __le64 resp_addr; 6281 __le32 flags; 6282 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 6283 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 6284 __le16 unused_0; 6285 __le16 op; 6286 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 6287 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 6288 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 6289 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 6290 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 6291 }; 6292 6293 /* hwrm_cfa_eem_op_output (size:128b/16B) */ 6294 struct hwrm_cfa_eem_op_output { 6295 __le16 error_code; 6296 __le16 req_type; 6297 __le16 seq_id; 6298 __le16 resp_len; 6299 u8 unused_0[7]; 6300 u8 valid; 6301 }; 6302 6303 /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 6304 struct hwrm_tunnel_dst_port_query_input { 6305 __le16 req_type; 6306 __le16 cmpl_ring; 6307 __le16 seq_id; 6308 __le16 target_id; 6309 __le64 resp_addr; 6310 u8 tunnel_type; 6311 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6312 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6313 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6314 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6315 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6316 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6317 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6318 u8 unused_0[7]; 6319 }; 6320 6321 /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 6322 struct hwrm_tunnel_dst_port_query_output { 6323 __le16 error_code; 6324 __le16 req_type; 6325 __le16 seq_id; 6326 __le16 resp_len; 6327 __le16 tunnel_dst_port_id; 6328 __be16 tunnel_dst_port_val; 6329 u8 unused_0[3]; 6330 u8 valid; 6331 }; 6332 6333 /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 6334 struct hwrm_tunnel_dst_port_alloc_input { 6335 __le16 req_type; 6336 __le16 cmpl_ring; 6337 __le16 seq_id; 6338 __le16 target_id; 6339 __le64 resp_addr; 6340 u8 tunnel_type; 6341 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6342 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6343 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6344 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6345 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6346 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6347 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6348 u8 unused_0; 6349 __be16 tunnel_dst_port_val; 6350 u8 unused_1[4]; 6351 }; 6352 6353 /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 6354 struct hwrm_tunnel_dst_port_alloc_output { 6355 __le16 error_code; 6356 __le16 req_type; 6357 __le16 seq_id; 6358 __le16 resp_len; 6359 __le16 tunnel_dst_port_id; 6360 u8 unused_0[5]; 6361 u8 valid; 6362 }; 6363 6364 /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 6365 struct hwrm_tunnel_dst_port_free_input { 6366 __le16 req_type; 6367 __le16 cmpl_ring; 6368 __le16 seq_id; 6369 __le16 target_id; 6370 __le64 resp_addr; 6371 u8 tunnel_type; 6372 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6373 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6374 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 6375 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 6376 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 6377 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6378 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 6379 u8 unused_0; 6380 __le16 tunnel_dst_port_id; 6381 u8 unused_1[4]; 6382 }; 6383 6384 /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 6385 struct hwrm_tunnel_dst_port_free_output { 6386 __le16 error_code; 6387 __le16 req_type; 6388 __le16 seq_id; 6389 __le16 resp_len; 6390 u8 unused_1[7]; 6391 u8 valid; 6392 }; 6393 6394 /* ctx_hw_stats (size:1280b/160B) */ 6395 struct ctx_hw_stats { 6396 __le64 rx_ucast_pkts; 6397 __le64 rx_mcast_pkts; 6398 __le64 rx_bcast_pkts; 6399 __le64 rx_discard_pkts; 6400 __le64 rx_drop_pkts; 6401 __le64 rx_ucast_bytes; 6402 __le64 rx_mcast_bytes; 6403 __le64 rx_bcast_bytes; 6404 __le64 tx_ucast_pkts; 6405 __le64 tx_mcast_pkts; 6406 __le64 tx_bcast_pkts; 6407 __le64 tx_discard_pkts; 6408 __le64 tx_drop_pkts; 6409 __le64 tx_ucast_bytes; 6410 __le64 tx_mcast_bytes; 6411 __le64 tx_bcast_bytes; 6412 __le64 tpa_pkts; 6413 __le64 tpa_bytes; 6414 __le64 tpa_events; 6415 __le64 tpa_aborts; 6416 }; 6417 6418 /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 6419 struct hwrm_stat_ctx_alloc_input { 6420 __le16 req_type; 6421 __le16 cmpl_ring; 6422 __le16 seq_id; 6423 __le16 target_id; 6424 __le64 resp_addr; 6425 __le64 stats_dma_addr; 6426 __le32 update_period_ms; 6427 u8 stat_ctx_flags; 6428 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 6429 u8 unused_0[3]; 6430 }; 6431 6432 /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 6433 struct hwrm_stat_ctx_alloc_output { 6434 __le16 error_code; 6435 __le16 req_type; 6436 __le16 seq_id; 6437 __le16 resp_len; 6438 __le32 stat_ctx_id; 6439 u8 unused_0[3]; 6440 u8 valid; 6441 }; 6442 6443 /* hwrm_stat_ctx_free_input (size:192b/24B) */ 6444 struct hwrm_stat_ctx_free_input { 6445 __le16 req_type; 6446 __le16 cmpl_ring; 6447 __le16 seq_id; 6448 __le16 target_id; 6449 __le64 resp_addr; 6450 __le32 stat_ctx_id; 6451 u8 unused_0[4]; 6452 }; 6453 6454 /* hwrm_stat_ctx_free_output (size:128b/16B) */ 6455 struct hwrm_stat_ctx_free_output { 6456 __le16 error_code; 6457 __le16 req_type; 6458 __le16 seq_id; 6459 __le16 resp_len; 6460 __le32 stat_ctx_id; 6461 u8 unused_0[3]; 6462 u8 valid; 6463 }; 6464 6465 /* hwrm_stat_ctx_query_input (size:192b/24B) */ 6466 struct hwrm_stat_ctx_query_input { 6467 __le16 req_type; 6468 __le16 cmpl_ring; 6469 __le16 seq_id; 6470 __le16 target_id; 6471 __le64 resp_addr; 6472 __le32 stat_ctx_id; 6473 u8 unused_0[4]; 6474 }; 6475 6476 /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 6477 struct hwrm_stat_ctx_query_output { 6478 __le16 error_code; 6479 __le16 req_type; 6480 __le16 seq_id; 6481 __le16 resp_len; 6482 __le64 tx_ucast_pkts; 6483 __le64 tx_mcast_pkts; 6484 __le64 tx_bcast_pkts; 6485 __le64 tx_err_pkts; 6486 __le64 tx_drop_pkts; 6487 __le64 tx_ucast_bytes; 6488 __le64 tx_mcast_bytes; 6489 __le64 tx_bcast_bytes; 6490 __le64 rx_ucast_pkts; 6491 __le64 rx_mcast_pkts; 6492 __le64 rx_bcast_pkts; 6493 __le64 rx_err_pkts; 6494 __le64 rx_drop_pkts; 6495 __le64 rx_ucast_bytes; 6496 __le64 rx_mcast_bytes; 6497 __le64 rx_bcast_bytes; 6498 __le64 rx_agg_pkts; 6499 __le64 rx_agg_bytes; 6500 __le64 rx_agg_events; 6501 __le64 rx_agg_aborts; 6502 u8 unused_0[7]; 6503 u8 valid; 6504 }; 6505 6506 /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 6507 struct hwrm_stat_ctx_clr_stats_input { 6508 __le16 req_type; 6509 __le16 cmpl_ring; 6510 __le16 seq_id; 6511 __le16 target_id; 6512 __le64 resp_addr; 6513 __le32 stat_ctx_id; 6514 u8 unused_0[4]; 6515 }; 6516 6517 /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 6518 struct hwrm_stat_ctx_clr_stats_output { 6519 __le16 error_code; 6520 __le16 req_type; 6521 __le16 seq_id; 6522 __le16 resp_len; 6523 u8 unused_0[7]; 6524 u8 valid; 6525 }; 6526 6527 /* hwrm_pcie_qstats_input (size:256b/32B) */ 6528 struct hwrm_pcie_qstats_input { 6529 __le16 req_type; 6530 __le16 cmpl_ring; 6531 __le16 seq_id; 6532 __le16 target_id; 6533 __le64 resp_addr; 6534 __le16 pcie_stat_size; 6535 u8 unused_0[6]; 6536 __le64 pcie_stat_host_addr; 6537 }; 6538 6539 /* hwrm_pcie_qstats_output (size:128b/16B) */ 6540 struct hwrm_pcie_qstats_output { 6541 __le16 error_code; 6542 __le16 req_type; 6543 __le16 seq_id; 6544 __le16 resp_len; 6545 __le16 pcie_stat_size; 6546 u8 unused_0[5]; 6547 u8 valid; 6548 }; 6549 6550 /* pcie_ctx_hw_stats (size:768b/96B) */ 6551 struct pcie_ctx_hw_stats { 6552 __le64 pcie_pl_signal_integrity; 6553 __le64 pcie_dl_signal_integrity; 6554 __le64 pcie_tl_signal_integrity; 6555 __le64 pcie_link_integrity; 6556 __le64 pcie_tx_traffic_rate; 6557 __le64 pcie_rx_traffic_rate; 6558 __le64 pcie_tx_dllp_statistics; 6559 __le64 pcie_rx_dllp_statistics; 6560 __le64 pcie_equalization_time; 6561 __le32 pcie_ltssm_histogram[4]; 6562 __le64 pcie_recovery_histogram; 6563 }; 6564 6565 /* hwrm_fw_reset_input (size:192b/24B) */ 6566 struct hwrm_fw_reset_input { 6567 __le16 req_type; 6568 __le16 cmpl_ring; 6569 __le16 seq_id; 6570 __le16 target_id; 6571 __le64 resp_addr; 6572 u8 embedded_proc_type; 6573 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6574 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6575 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6576 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6577 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6578 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6579 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6580 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 6581 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 6582 u8 selfrst_status; 6583 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 6584 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 6585 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6586 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6587 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 6588 u8 host_idx; 6589 u8 flags; 6590 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 6591 u8 unused_0[4]; 6592 }; 6593 6594 /* hwrm_fw_reset_output (size:128b/16B) */ 6595 struct hwrm_fw_reset_output { 6596 __le16 error_code; 6597 __le16 req_type; 6598 __le16 seq_id; 6599 __le16 resp_len; 6600 u8 selfrst_status; 6601 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6602 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6603 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6604 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 6605 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 6606 u8 unused_0[6]; 6607 u8 valid; 6608 }; 6609 6610 /* hwrm_fw_qstatus_input (size:192b/24B) */ 6611 struct hwrm_fw_qstatus_input { 6612 __le16 req_type; 6613 __le16 cmpl_ring; 6614 __le16 seq_id; 6615 __le16 target_id; 6616 __le64 resp_addr; 6617 u8 embedded_proc_type; 6618 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 6619 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 6620 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 6621 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 6622 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 6623 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 6624 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 6625 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 6626 u8 unused_0[7]; 6627 }; 6628 6629 /* hwrm_fw_qstatus_output (size:128b/16B) */ 6630 struct hwrm_fw_qstatus_output { 6631 __le16 error_code; 6632 __le16 req_type; 6633 __le16 seq_id; 6634 __le16 resp_len; 6635 u8 selfrst_status; 6636 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 6637 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 6638 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 6639 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 6640 u8 unused_0[6]; 6641 u8 valid; 6642 }; 6643 6644 /* hwrm_fw_set_time_input (size:256b/32B) */ 6645 struct hwrm_fw_set_time_input { 6646 __le16 req_type; 6647 __le16 cmpl_ring; 6648 __le16 seq_id; 6649 __le16 target_id; 6650 __le64 resp_addr; 6651 __le16 year; 6652 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 6653 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 6654 u8 month; 6655 u8 day; 6656 u8 hour; 6657 u8 minute; 6658 u8 second; 6659 u8 unused_0; 6660 __le16 millisecond; 6661 __le16 zone; 6662 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 6663 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 6664 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 6665 u8 unused_1[4]; 6666 }; 6667 6668 /* hwrm_fw_set_time_output (size:128b/16B) */ 6669 struct hwrm_fw_set_time_output { 6670 __le16 error_code; 6671 __le16 req_type; 6672 __le16 seq_id; 6673 __le16 resp_len; 6674 u8 unused_0[7]; 6675 u8 valid; 6676 }; 6677 6678 /* hwrm_struct_hdr (size:128b/16B) */ 6679 struct hwrm_struct_hdr { 6680 __le16 struct_id; 6681 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 6682 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 6683 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 6684 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 6685 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 6686 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 6687 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 6688 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 6689 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 6690 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 6691 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 6692 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 6693 __le16 len; 6694 u8 version; 6695 u8 count; 6696 __le16 subtype; 6697 __le16 next_offset; 6698 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 6699 u8 unused_0[6]; 6700 }; 6701 6702 /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 6703 struct hwrm_struct_data_dcbx_app { 6704 __be16 protocol_id; 6705 u8 protocol_selector; 6706 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6707 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6708 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6709 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 6710 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 6711 u8 priority; 6712 u8 valid; 6713 u8 unused_0[3]; 6714 }; 6715 6716 /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 6717 struct hwrm_fw_set_structured_data_input { 6718 __le16 req_type; 6719 __le16 cmpl_ring; 6720 __le16 seq_id; 6721 __le16 target_id; 6722 __le64 resp_addr; 6723 __le64 src_data_addr; 6724 __le16 data_len; 6725 u8 hdr_cnt; 6726 u8 unused_0[5]; 6727 }; 6728 6729 /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 6730 struct hwrm_fw_set_structured_data_output { 6731 __le16 error_code; 6732 __le16 req_type; 6733 __le16 seq_id; 6734 __le16 resp_len; 6735 u8 unused_0[7]; 6736 u8 valid; 6737 }; 6738 6739 /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 6740 struct hwrm_fw_set_structured_data_cmd_err { 6741 u8 code; 6742 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6743 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 6744 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 6745 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6746 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6747 u8 unused_0[7]; 6748 }; 6749 6750 /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 6751 struct hwrm_fw_get_structured_data_input { 6752 __le16 req_type; 6753 __le16 cmpl_ring; 6754 __le16 seq_id; 6755 __le16 target_id; 6756 __le64 resp_addr; 6757 __le64 dest_data_addr; 6758 __le16 data_len; 6759 __le16 structure_id; 6760 __le16 subtype; 6761 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 6762 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 6763 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 6764 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 6765 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 6766 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 6767 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 6768 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 6769 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 6770 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 6771 u8 count; 6772 u8 unused_0; 6773 }; 6774 6775 /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 6776 struct hwrm_fw_get_structured_data_output { 6777 __le16 error_code; 6778 __le16 req_type; 6779 __le16 seq_id; 6780 __le16 resp_len; 6781 u8 hdr_cnt; 6782 u8 unused_0[6]; 6783 u8 valid; 6784 }; 6785 6786 /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 6787 struct hwrm_fw_get_structured_data_cmd_err { 6788 u8 code; 6789 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 6790 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 6791 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 6792 u8 unused_0[7]; 6793 }; 6794 6795 /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 6796 struct hwrm_exec_fwd_resp_input { 6797 __le16 req_type; 6798 __le16 cmpl_ring; 6799 __le16 seq_id; 6800 __le16 target_id; 6801 __le64 resp_addr; 6802 __le32 encap_request[26]; 6803 __le16 encap_resp_target_id; 6804 u8 unused_0[6]; 6805 }; 6806 6807 /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 6808 struct hwrm_exec_fwd_resp_output { 6809 __le16 error_code; 6810 __le16 req_type; 6811 __le16 seq_id; 6812 __le16 resp_len; 6813 u8 unused_0[7]; 6814 u8 valid; 6815 }; 6816 6817 /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 6818 struct hwrm_reject_fwd_resp_input { 6819 __le16 req_type; 6820 __le16 cmpl_ring; 6821 __le16 seq_id; 6822 __le16 target_id; 6823 __le64 resp_addr; 6824 __le32 encap_request[26]; 6825 __le16 encap_resp_target_id; 6826 u8 unused_0[6]; 6827 }; 6828 6829 /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 6830 struct hwrm_reject_fwd_resp_output { 6831 __le16 error_code; 6832 __le16 req_type; 6833 __le16 seq_id; 6834 __le16 resp_len; 6835 u8 unused_0[7]; 6836 u8 valid; 6837 }; 6838 6839 /* hwrm_fwd_resp_input (size:1024b/128B) */ 6840 struct hwrm_fwd_resp_input { 6841 __le16 req_type; 6842 __le16 cmpl_ring; 6843 __le16 seq_id; 6844 __le16 target_id; 6845 __le64 resp_addr; 6846 __le16 encap_resp_target_id; 6847 __le16 encap_resp_cmpl_ring; 6848 __le16 encap_resp_len; 6849 u8 unused_0; 6850 u8 unused_1; 6851 __le64 encap_resp_addr; 6852 __le32 encap_resp[24]; 6853 }; 6854 6855 /* hwrm_fwd_resp_output (size:128b/16B) */ 6856 struct hwrm_fwd_resp_output { 6857 __le16 error_code; 6858 __le16 req_type; 6859 __le16 seq_id; 6860 __le16 resp_len; 6861 u8 unused_0[7]; 6862 u8 valid; 6863 }; 6864 6865 /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 6866 struct hwrm_fwd_async_event_cmpl_input { 6867 __le16 req_type; 6868 __le16 cmpl_ring; 6869 __le16 seq_id; 6870 __le16 target_id; 6871 __le64 resp_addr; 6872 __le16 encap_async_event_target_id; 6873 u8 unused_0[6]; 6874 __le32 encap_async_event_cmpl[4]; 6875 }; 6876 6877 /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 6878 struct hwrm_fwd_async_event_cmpl_output { 6879 __le16 error_code; 6880 __le16 req_type; 6881 __le16 seq_id; 6882 __le16 resp_len; 6883 u8 unused_0[7]; 6884 u8 valid; 6885 }; 6886 6887 /* hwrm_temp_monitor_query_input (size:128b/16B) */ 6888 struct hwrm_temp_monitor_query_input { 6889 __le16 req_type; 6890 __le16 cmpl_ring; 6891 __le16 seq_id; 6892 __le16 target_id; 6893 __le64 resp_addr; 6894 }; 6895 6896 /* hwrm_temp_monitor_query_output (size:128b/16B) */ 6897 struct hwrm_temp_monitor_query_output { 6898 __le16 error_code; 6899 __le16 req_type; 6900 __le16 seq_id; 6901 __le16 resp_len; 6902 u8 temp; 6903 u8 unused_0[6]; 6904 u8 valid; 6905 }; 6906 6907 /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 6908 struct hwrm_wol_filter_alloc_input { 6909 __le16 req_type; 6910 __le16 cmpl_ring; 6911 __le16 seq_id; 6912 __le16 target_id; 6913 __le64 resp_addr; 6914 __le32 flags; 6915 __le32 enables; 6916 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 6917 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 6918 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 6919 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 6920 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 6921 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 6922 __le16 port_id; 6923 u8 wol_type; 6924 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 6925 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 6926 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 6927 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 6928 u8 unused_0[5]; 6929 u8 mac_address[6]; 6930 __le16 pattern_offset; 6931 __le16 pattern_buf_size; 6932 __le16 pattern_mask_size; 6933 u8 unused_1[4]; 6934 __le64 pattern_buf_addr; 6935 __le64 pattern_mask_addr; 6936 }; 6937 6938 /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 6939 struct hwrm_wol_filter_alloc_output { 6940 __le16 error_code; 6941 __le16 req_type; 6942 __le16 seq_id; 6943 __le16 resp_len; 6944 u8 wol_filter_id; 6945 u8 unused_0[6]; 6946 u8 valid; 6947 }; 6948 6949 /* hwrm_wol_filter_free_input (size:256b/32B) */ 6950 struct hwrm_wol_filter_free_input { 6951 __le16 req_type; 6952 __le16 cmpl_ring; 6953 __le16 seq_id; 6954 __le16 target_id; 6955 __le64 resp_addr; 6956 __le32 flags; 6957 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 6958 __le32 enables; 6959 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 6960 __le16 port_id; 6961 u8 wol_filter_id; 6962 u8 unused_0[5]; 6963 }; 6964 6965 /* hwrm_wol_filter_free_output (size:128b/16B) */ 6966 struct hwrm_wol_filter_free_output { 6967 __le16 error_code; 6968 __le16 req_type; 6969 __le16 seq_id; 6970 __le16 resp_len; 6971 u8 unused_0[7]; 6972 u8 valid; 6973 }; 6974 6975 /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 6976 struct hwrm_wol_filter_qcfg_input { 6977 __le16 req_type; 6978 __le16 cmpl_ring; 6979 __le16 seq_id; 6980 __le16 target_id; 6981 __le64 resp_addr; 6982 __le16 port_id; 6983 __le16 handle; 6984 u8 unused_0[4]; 6985 __le64 pattern_buf_addr; 6986 __le16 pattern_buf_size; 6987 u8 unused_1[6]; 6988 __le64 pattern_mask_addr; 6989 __le16 pattern_mask_size; 6990 u8 unused_2[6]; 6991 }; 6992 6993 /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 6994 struct hwrm_wol_filter_qcfg_output { 6995 __le16 error_code; 6996 __le16 req_type; 6997 __le16 seq_id; 6998 __le16 resp_len; 6999 __le16 next_handle; 7000 u8 wol_filter_id; 7001 u8 wol_type; 7002 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7003 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7004 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7005 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7006 __le32 unused_0; 7007 u8 mac_address[6]; 7008 __le16 pattern_offset; 7009 __le16 pattern_size; 7010 __le16 pattern_mask_size; 7011 u8 unused_1[3]; 7012 u8 valid; 7013 }; 7014 7015 /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7016 struct hwrm_wol_reason_qcfg_input { 7017 __le16 req_type; 7018 __le16 cmpl_ring; 7019 __le16 seq_id; 7020 __le16 target_id; 7021 __le64 resp_addr; 7022 __le16 port_id; 7023 u8 unused_0[6]; 7024 __le64 wol_pkt_buf_addr; 7025 __le16 wol_pkt_buf_size; 7026 u8 unused_1[6]; 7027 }; 7028 7029 /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7030 struct hwrm_wol_reason_qcfg_output { 7031 __le16 error_code; 7032 __le16 req_type; 7033 __le16 seq_id; 7034 __le16 resp_len; 7035 u8 wol_filter_id; 7036 u8 wol_reason; 7037 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7038 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7039 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7040 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7041 u8 wol_pkt_len; 7042 u8 unused_0[4]; 7043 u8 valid; 7044 }; 7045 7046 /* coredump_segment_record (size:128b/16B) */ 7047 struct coredump_segment_record { 7048 __le16 component_id; 7049 __le16 segment_id; 7050 __le16 max_instances; 7051 u8 version_hi; 7052 u8 version_low; 7053 u8 seg_flags; 7054 u8 unused_0[7]; 7055 }; 7056 7057 /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 7058 struct hwrm_dbg_coredump_list_input { 7059 __le16 req_type; 7060 __le16 cmpl_ring; 7061 __le16 seq_id; 7062 __le16 target_id; 7063 __le64 resp_addr; 7064 __le64 host_dest_addr; 7065 __le32 host_buf_len; 7066 __le16 seq_no; 7067 u8 unused_0[2]; 7068 }; 7069 7070 /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 7071 struct hwrm_dbg_coredump_list_output { 7072 __le16 error_code; 7073 __le16 req_type; 7074 __le16 seq_id; 7075 __le16 resp_len; 7076 u8 flags; 7077 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 7078 u8 unused_0; 7079 __le16 total_segments; 7080 __le16 data_len; 7081 u8 unused_1; 7082 u8 valid; 7083 }; 7084 7085 /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 7086 struct hwrm_dbg_coredump_initiate_input { 7087 __le16 req_type; 7088 __le16 cmpl_ring; 7089 __le16 seq_id; 7090 __le16 target_id; 7091 __le64 resp_addr; 7092 __le16 component_id; 7093 __le16 segment_id; 7094 __le16 instance; 7095 __le16 unused_0; 7096 u8 seg_flags; 7097 u8 unused_1[7]; 7098 }; 7099 7100 /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 7101 struct hwrm_dbg_coredump_initiate_output { 7102 __le16 error_code; 7103 __le16 req_type; 7104 __le16 seq_id; 7105 __le16 resp_len; 7106 u8 unused_0[7]; 7107 u8 valid; 7108 }; 7109 7110 /* coredump_data_hdr (size:128b/16B) */ 7111 struct coredump_data_hdr { 7112 __le32 address; 7113 __le32 flags_length; 7114 __le32 instance; 7115 __le32 next_offset; 7116 }; 7117 7118 /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 7119 struct hwrm_dbg_coredump_retrieve_input { 7120 __le16 req_type; 7121 __le16 cmpl_ring; 7122 __le16 seq_id; 7123 __le16 target_id; 7124 __le64 resp_addr; 7125 __le64 host_dest_addr; 7126 __le32 host_buf_len; 7127 __le32 unused_0; 7128 __le16 component_id; 7129 __le16 segment_id; 7130 __le16 instance; 7131 __le16 unused_1; 7132 u8 seg_flags; 7133 u8 unused_2; 7134 __le16 unused_3; 7135 __le32 unused_4; 7136 __le32 seq_no; 7137 __le32 unused_5; 7138 }; 7139 7140 /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 7141 struct hwrm_dbg_coredump_retrieve_output { 7142 __le16 error_code; 7143 __le16 req_type; 7144 __le16 seq_id; 7145 __le16 resp_len; 7146 u8 flags; 7147 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 7148 u8 unused_0; 7149 __le16 data_len; 7150 u8 unused_1[3]; 7151 u8 valid; 7152 }; 7153 7154 /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 7155 struct hwrm_dbg_ring_info_get_input { 7156 __le16 req_type; 7157 __le16 cmpl_ring; 7158 __le16 seq_id; 7159 __le16 target_id; 7160 __le64 resp_addr; 7161 u8 ring_type; 7162 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 7163 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 7164 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 7165 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_RX 7166 u8 unused_0[3]; 7167 __le32 fw_ring_id; 7168 }; 7169 7170 /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 7171 struct hwrm_dbg_ring_info_get_output { 7172 __le16 error_code; 7173 __le16 req_type; 7174 __le16 seq_id; 7175 __le16 resp_len; 7176 __le32 producer_index; 7177 __le32 consumer_index; 7178 u8 unused_0[7]; 7179 u8 valid; 7180 }; 7181 7182 /* hwrm_nvm_read_input (size:320b/40B) */ 7183 struct hwrm_nvm_read_input { 7184 __le16 req_type; 7185 __le16 cmpl_ring; 7186 __le16 seq_id; 7187 __le16 target_id; 7188 __le64 resp_addr; 7189 __le64 host_dest_addr; 7190 __le16 dir_idx; 7191 u8 unused_0[2]; 7192 __le32 offset; 7193 __le32 len; 7194 u8 unused_1[4]; 7195 }; 7196 7197 /* hwrm_nvm_read_output (size:128b/16B) */ 7198 struct hwrm_nvm_read_output { 7199 __le16 error_code; 7200 __le16 req_type; 7201 __le16 seq_id; 7202 __le16 resp_len; 7203 u8 unused_0[7]; 7204 u8 valid; 7205 }; 7206 7207 /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 7208 struct hwrm_nvm_get_dir_entries_input { 7209 __le16 req_type; 7210 __le16 cmpl_ring; 7211 __le16 seq_id; 7212 __le16 target_id; 7213 __le64 resp_addr; 7214 __le64 host_dest_addr; 7215 }; 7216 7217 /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 7218 struct hwrm_nvm_get_dir_entries_output { 7219 __le16 error_code; 7220 __le16 req_type; 7221 __le16 seq_id; 7222 __le16 resp_len; 7223 u8 unused_0[7]; 7224 u8 valid; 7225 }; 7226 7227 /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 7228 struct hwrm_nvm_get_dir_info_input { 7229 __le16 req_type; 7230 __le16 cmpl_ring; 7231 __le16 seq_id; 7232 __le16 target_id; 7233 __le64 resp_addr; 7234 }; 7235 7236 /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 7237 struct hwrm_nvm_get_dir_info_output { 7238 __le16 error_code; 7239 __le16 req_type; 7240 __le16 seq_id; 7241 __le16 resp_len; 7242 __le32 entries; 7243 __le32 entry_length; 7244 u8 unused_0[7]; 7245 u8 valid; 7246 }; 7247 7248 /* hwrm_nvm_write_input (size:384b/48B) */ 7249 struct hwrm_nvm_write_input { 7250 __le16 req_type; 7251 __le16 cmpl_ring; 7252 __le16 seq_id; 7253 __le16 target_id; 7254 __le64 resp_addr; 7255 __le64 host_src_addr; 7256 __le16 dir_type; 7257 __le16 dir_ordinal; 7258 __le16 dir_ext; 7259 __le16 dir_attr; 7260 __le32 dir_data_length; 7261 __le16 option; 7262 __le16 flags; 7263 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 7264 __le32 dir_item_length; 7265 __le32 unused_0; 7266 }; 7267 7268 /* hwrm_nvm_write_output (size:128b/16B) */ 7269 struct hwrm_nvm_write_output { 7270 __le16 error_code; 7271 __le16 req_type; 7272 __le16 seq_id; 7273 __le16 resp_len; 7274 __le32 dir_item_length; 7275 __le16 dir_idx; 7276 u8 unused_0; 7277 u8 valid; 7278 }; 7279 7280 /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 7281 struct hwrm_nvm_write_cmd_err { 7282 u8 code; 7283 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 7284 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7285 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 7286 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 7287 u8 unused_0[7]; 7288 }; 7289 7290 /* hwrm_nvm_modify_input (size:320b/40B) */ 7291 struct hwrm_nvm_modify_input { 7292 __le16 req_type; 7293 __le16 cmpl_ring; 7294 __le16 seq_id; 7295 __le16 target_id; 7296 __le64 resp_addr; 7297 __le64 host_src_addr; 7298 __le16 dir_idx; 7299 u8 unused_0[2]; 7300 __le32 offset; 7301 __le32 len; 7302 u8 unused_1[4]; 7303 }; 7304 7305 /* hwrm_nvm_modify_output (size:128b/16B) */ 7306 struct hwrm_nvm_modify_output { 7307 __le16 error_code; 7308 __le16 req_type; 7309 __le16 seq_id; 7310 __le16 resp_len; 7311 u8 unused_0[7]; 7312 u8 valid; 7313 }; 7314 7315 /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 7316 struct hwrm_nvm_find_dir_entry_input { 7317 __le16 req_type; 7318 __le16 cmpl_ring; 7319 __le16 seq_id; 7320 __le16 target_id; 7321 __le64 resp_addr; 7322 __le32 enables; 7323 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 7324 __le16 dir_idx; 7325 __le16 dir_type; 7326 __le16 dir_ordinal; 7327 __le16 dir_ext; 7328 u8 opt_ordinal; 7329 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 7330 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 7331 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 7332 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 7333 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 7334 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 7335 u8 unused_0[3]; 7336 }; 7337 7338 /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 7339 struct hwrm_nvm_find_dir_entry_output { 7340 __le16 error_code; 7341 __le16 req_type; 7342 __le16 seq_id; 7343 __le16 resp_len; 7344 __le32 dir_item_length; 7345 __le32 dir_data_length; 7346 __le32 fw_ver; 7347 __le16 dir_ordinal; 7348 __le16 dir_idx; 7349 u8 unused_0[7]; 7350 u8 valid; 7351 }; 7352 7353 /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 7354 struct hwrm_nvm_erase_dir_entry_input { 7355 __le16 req_type; 7356 __le16 cmpl_ring; 7357 __le16 seq_id; 7358 __le16 target_id; 7359 __le64 resp_addr; 7360 __le16 dir_idx; 7361 u8 unused_0[6]; 7362 }; 7363 7364 /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 7365 struct hwrm_nvm_erase_dir_entry_output { 7366 __le16 error_code; 7367 __le16 req_type; 7368 __le16 seq_id; 7369 __le16 resp_len; 7370 u8 unused_0[7]; 7371 u8 valid; 7372 }; 7373 7374 /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 7375 struct hwrm_nvm_get_dev_info_input { 7376 __le16 req_type; 7377 __le16 cmpl_ring; 7378 __le16 seq_id; 7379 __le16 target_id; 7380 __le64 resp_addr; 7381 }; 7382 7383 /* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 7384 struct hwrm_nvm_get_dev_info_output { 7385 __le16 error_code; 7386 __le16 req_type; 7387 __le16 seq_id; 7388 __le16 resp_len; 7389 __le16 manufacturer_id; 7390 __le16 device_id; 7391 __le32 sector_size; 7392 __le32 nvram_size; 7393 __le32 reserved_size; 7394 __le32 available_size; 7395 u8 unused_0[3]; 7396 u8 valid; 7397 }; 7398 7399 /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 7400 struct hwrm_nvm_mod_dir_entry_input { 7401 __le16 req_type; 7402 __le16 cmpl_ring; 7403 __le16 seq_id; 7404 __le16 target_id; 7405 __le64 resp_addr; 7406 __le32 enables; 7407 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 7408 __le16 dir_idx; 7409 __le16 dir_ordinal; 7410 __le16 dir_ext; 7411 __le16 dir_attr; 7412 __le32 checksum; 7413 }; 7414 7415 /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 7416 struct hwrm_nvm_mod_dir_entry_output { 7417 __le16 error_code; 7418 __le16 req_type; 7419 __le16 seq_id; 7420 __le16 resp_len; 7421 u8 unused_0[7]; 7422 u8 valid; 7423 }; 7424 7425 /* hwrm_nvm_verify_update_input (size:192b/24B) */ 7426 struct hwrm_nvm_verify_update_input { 7427 __le16 req_type; 7428 __le16 cmpl_ring; 7429 __le16 seq_id; 7430 __le16 target_id; 7431 __le64 resp_addr; 7432 __le16 dir_type; 7433 __le16 dir_ordinal; 7434 __le16 dir_ext; 7435 u8 unused_0[2]; 7436 }; 7437 7438 /* hwrm_nvm_verify_update_output (size:128b/16B) */ 7439 struct hwrm_nvm_verify_update_output { 7440 __le16 error_code; 7441 __le16 req_type; 7442 __le16 seq_id; 7443 __le16 resp_len; 7444 u8 unused_0[7]; 7445 u8 valid; 7446 }; 7447 7448 /* hwrm_nvm_install_update_input (size:192b/24B) */ 7449 struct hwrm_nvm_install_update_input { 7450 __le16 req_type; 7451 __le16 cmpl_ring; 7452 __le16 seq_id; 7453 __le16 target_id; 7454 __le64 resp_addr; 7455 __le32 install_type; 7456 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 7457 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 7458 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 7459 __le16 flags; 7460 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 7461 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 7462 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 7463 u8 unused_0[2]; 7464 }; 7465 7466 /* hwrm_nvm_install_update_output (size:192b/24B) */ 7467 struct hwrm_nvm_install_update_output { 7468 __le16 error_code; 7469 __le16 req_type; 7470 __le16 seq_id; 7471 __le16 resp_len; 7472 __le64 installed_items; 7473 u8 result; 7474 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 7475 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 7476 u8 problem_item; 7477 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 7478 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 7479 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 7480 u8 reset_required; 7481 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 7482 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 7483 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 7484 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 7485 u8 unused_0[4]; 7486 u8 valid; 7487 }; 7488 7489 /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 7490 struct hwrm_nvm_install_update_cmd_err { 7491 u8 code; 7492 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 7493 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 7494 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 7495 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 7496 u8 unused_0[7]; 7497 }; 7498 7499 /* hwrm_nvm_get_variable_input (size:320b/40B) */ 7500 struct hwrm_nvm_get_variable_input { 7501 __le16 req_type; 7502 __le16 cmpl_ring; 7503 __le16 seq_id; 7504 __le16 target_id; 7505 __le64 resp_addr; 7506 __le64 dest_data_addr; 7507 __le16 data_len; 7508 __le16 option_num; 7509 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7510 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7511 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7512 __le16 dimensions; 7513 __le16 index_0; 7514 __le16 index_1; 7515 __le16 index_2; 7516 __le16 index_3; 7517 u8 flags; 7518 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 7519 u8 unused_0; 7520 }; 7521 7522 /* hwrm_nvm_get_variable_output (size:128b/16B) */ 7523 struct hwrm_nvm_get_variable_output { 7524 __le16 error_code; 7525 __le16 req_type; 7526 __le16 seq_id; 7527 __le16 resp_len; 7528 __le16 data_len; 7529 __le16 option_num; 7530 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 7531 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 7532 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 7533 u8 unused_0[3]; 7534 u8 valid; 7535 }; 7536 7537 /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 7538 struct hwrm_nvm_get_variable_cmd_err { 7539 u8 code; 7540 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7541 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7542 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7543 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 7544 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 7545 u8 unused_0[7]; 7546 }; 7547 7548 /* hwrm_nvm_set_variable_input (size:320b/40B) */ 7549 struct hwrm_nvm_set_variable_input { 7550 __le16 req_type; 7551 __le16 cmpl_ring; 7552 __le16 seq_id; 7553 __le16 target_id; 7554 __le64 resp_addr; 7555 __le64 src_data_addr; 7556 __le16 data_len; 7557 __le16 option_num; 7558 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 7559 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 7560 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 7561 __le16 dimensions; 7562 __le16 index_0; 7563 __le16 index_1; 7564 __le16 index_2; 7565 __le16 index_3; 7566 u8 flags; 7567 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 7568 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 7569 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 7570 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 7571 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 7572 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 7573 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 7574 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 7575 u8 unused_0; 7576 }; 7577 7578 /* hwrm_nvm_set_variable_output (size:128b/16B) */ 7579 struct hwrm_nvm_set_variable_output { 7580 __le16 error_code; 7581 __le16 req_type; 7582 __le16 seq_id; 7583 __le16 resp_len; 7584 u8 unused_0[7]; 7585 u8 valid; 7586 }; 7587 7588 /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 7589 struct hwrm_nvm_set_variable_cmd_err { 7590 u8 code; 7591 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 7592 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 7593 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 7594 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 7595 u8 unused_0[7]; 7596 }; 7597 7598 /* hwrm_selftest_qlist_input (size:128b/16B) */ 7599 struct hwrm_selftest_qlist_input { 7600 __le16 req_type; 7601 __le16 cmpl_ring; 7602 __le16 seq_id; 7603 __le16 target_id; 7604 __le64 resp_addr; 7605 }; 7606 7607 /* hwrm_selftest_qlist_output (size:2240b/280B) */ 7608 struct hwrm_selftest_qlist_output { 7609 __le16 error_code; 7610 __le16 req_type; 7611 __le16 seq_id; 7612 __le16 resp_len; 7613 u8 num_tests; 7614 u8 available_tests; 7615 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 7616 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 7617 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 7618 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 7619 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 7620 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7621 u8 offline_tests; 7622 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 7623 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 7624 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 7625 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 7626 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 7627 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 7628 u8 unused_0; 7629 __le16 test_timeout; 7630 u8 unused_1[2]; 7631 char test0_name[32]; 7632 char test1_name[32]; 7633 char test2_name[32]; 7634 char test3_name[32]; 7635 char test4_name[32]; 7636 char test5_name[32]; 7637 char test6_name[32]; 7638 char test7_name[32]; 7639 u8 unused_2[7]; 7640 u8 valid; 7641 }; 7642 7643 /* hwrm_selftest_exec_input (size:192b/24B) */ 7644 struct hwrm_selftest_exec_input { 7645 __le16 req_type; 7646 __le16 cmpl_ring; 7647 __le16 seq_id; 7648 __le16 target_id; 7649 __le64 resp_addr; 7650 u8 flags; 7651 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 7652 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 7653 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 7654 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 7655 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 7656 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 7657 u8 unused_0[7]; 7658 }; 7659 7660 /* hwrm_selftest_exec_output (size:128b/16B) */ 7661 struct hwrm_selftest_exec_output { 7662 __le16 error_code; 7663 __le16 req_type; 7664 __le16 seq_id; 7665 __le16 resp_len; 7666 u8 requested_tests; 7667 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 7668 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 7669 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 7670 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 7671 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 7672 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 7673 u8 test_success; 7674 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 7675 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 7676 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 7677 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 7678 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 7679 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 7680 u8 unused_0[5]; 7681 u8 valid; 7682 }; 7683 7684 /* hwrm_selftest_irq_input (size:128b/16B) */ 7685 struct hwrm_selftest_irq_input { 7686 __le16 req_type; 7687 __le16 cmpl_ring; 7688 __le16 seq_id; 7689 __le16 target_id; 7690 __le64 resp_addr; 7691 }; 7692 7693 /* hwrm_selftest_irq_output (size:128b/16B) */ 7694 struct hwrm_selftest_irq_output { 7695 __le16 error_code; 7696 __le16 req_type; 7697 __le16 seq_id; 7698 __le16 resp_len; 7699 u8 unused_0[7]; 7700 u8 valid; 7701 }; 7702 7703 #endif /* _BNXT_HSI_H_ */ 7704