1c0c050c5SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2c0c050c5SMichael Chan * 311f15ed3SMichael Chan * Copyright (c) 2014-2016 Broadcom Corporation 4f183886cSMichael Chan * Copyright (c) 2016-2017 Broadcom Limited 5c0c050c5SMichael Chan * 6c0c050c5SMichael Chan * This program is free software; you can redistribute it and/or modify 7c0c050c5SMichael Chan * it under the terms of the GNU General Public License as published by 8c0c050c5SMichael Chan * the Free Software Foundation. 9c0c050c5SMichael Chan */ 10c0c050c5SMichael Chan 11c0c050c5SMichael Chan #ifndef BNXT_HSI_H 12c0c050c5SMichael Chan #define BNXT_HSI_H 13c0c050c5SMichael Chan 14acb20054SMichael Chan /* HSI and HWRM Specification 1.8.0 */ 1587c374deSMichael Chan #define HWRM_VERSION_MAJOR 1 16acb20054SMichael Chan #define HWRM_VERSION_MINOR 8 17acb20054SMichael Chan #define HWRM_VERSION_UPDATE 0 1887c374deSMichael Chan 19acb20054SMichael Chan #define HWRM_VERSION_RSVD 0 /* non-zero means beta version */ 208eb992e8SMichael Chan 21acb20054SMichael Chan #define HWRM_VERSION_STR "1.8.0.0" 2287c374deSMichael Chan /* 2387c374deSMichael Chan * Following is the signature for HWRM message field that indicates not 2487c374deSMichael Chan * applicable (All F's). Need to cast it the size of the field if needed. 2587c374deSMichael Chan */ 2687c374deSMichael Chan #define HWRM_NA_SIGNATURE ((__le32)(-1)) 2787c374deSMichael Chan #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 288eb992e8SMichael Chan #define HWRM_MAX_RESP_LEN (248) /* hwrm_selftest_qlist */ 2987c374deSMichael Chan #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 3087c374deSMichael Chan #define HW_HASH_KEY_SIZE 40 3187c374deSMichael Chan #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 32c0c050c5SMichael Chan 33c0c050c5SMichael Chan /* Statistics Ejection Buffer Completion Record (16 bytes) */ 34c0c050c5SMichael Chan struct eject_cmpl { 35c0c050c5SMichael Chan __le16 type; 36c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_MASK 0x3fUL 37c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_SFT 0 38441cabbbSMichael Chan #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 39c0c050c5SMichael Chan __le16 len; 40c0c050c5SMichael Chan __le32 opaque; 41c0c050c5SMichael Chan __le32 v; 42c0c050c5SMichael Chan #define EJECT_CMPL_V 0x1UL 43c0c050c5SMichael Chan __le32 unused_2; 44c0c050c5SMichael Chan }; 45c0c050c5SMichael Chan 46c0c050c5SMichael Chan /* HWRM Completion Record (16 bytes) */ 47c0c050c5SMichael Chan struct hwrm_cmpl { 48c0c050c5SMichael Chan __le16 type; 4987c374deSMichael Chan #define CMPL_TYPE_MASK 0x3fUL 5087c374deSMichael Chan #define CMPL_TYPE_SFT 0 5187c374deSMichael Chan #define CMPL_TYPE_HWRM_DONE 0x20UL 52c0c050c5SMichael Chan __le16 sequence_id; 53c0c050c5SMichael Chan __le32 unused_1; 54c0c050c5SMichael Chan __le32 v; 5587c374deSMichael Chan #define CMPL_V 0x1UL 56c0c050c5SMichael Chan __le32 unused_3; 57c0c050c5SMichael Chan }; 58c0c050c5SMichael Chan 59c0c050c5SMichael Chan /* HWRM Forwarded Request (16 bytes) */ 60c0c050c5SMichael Chan struct hwrm_fwd_req_cmpl { 61c0c050c5SMichael Chan __le16 req_len_type; 6287c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 6387c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_SFT 0 6487c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 6587c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 6687c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_SFT 6 67c0c050c5SMichael Chan __le16 source_id; 68c0c050c5SMichael Chan __le32 unused_0; 69c0c050c5SMichael Chan __le32 req_buf_addr_v[2]; 7087c374deSMichael Chan #define FWD_REQ_CMPL_V 0x1UL 7187c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 7287c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 73c0c050c5SMichael Chan }; 74c0c050c5SMichael Chan 75c0c050c5SMichael Chan /* HWRM Forwarded Response (16 bytes) */ 76c0c050c5SMichael Chan struct hwrm_fwd_resp_cmpl { 77c0c050c5SMichael Chan __le16 type; 7887c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 7987c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_SFT 0 8087c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 81c0c050c5SMichael Chan __le16 source_id; 82c0c050c5SMichael Chan __le16 resp_len; 83c0c050c5SMichael Chan __le16 unused_1; 84c0c050c5SMichael Chan __le32 resp_buf_addr_v[2]; 8587c374deSMichael Chan #define FWD_RESP_CMPL_V 0x1UL 8687c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 8787c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 88c0c050c5SMichael Chan }; 89c0c050c5SMichael Chan 90c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record (16 bytes) */ 91c0c050c5SMichael Chan struct hwrm_async_event_cmpl { 92c0c050c5SMichael Chan __le16 type; 9387c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 9487c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_SFT 0 9587c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 96c0c050c5SMichael Chan __le16 event_id; 9787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 9887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 9987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 10087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 10187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 10287c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 10387c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 10487c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 10587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 10687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 10787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 10887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 10987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 11087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 11187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 11287c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 11387c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 11487c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 115c0c050c5SMichael Chan __le32 event_data2; 116c0c050c5SMichael Chan u8 opaque_v; 11787c374deSMichael Chan #define ASYNC_EVENT_CMPL_V 0x1UL 11887c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 11987c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 120c193554eSMichael Chan u8 timestamp_lo; 121c193554eSMichael Chan __le16 timestamp_hi; 122c0c050c5SMichael Chan __le32 event_data1; 123c0c050c5SMichael Chan }; 124c0c050c5SMichael Chan 125c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 126c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_status_change { 127c0c050c5SMichael Chan __le16 type; 12887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 12987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 13087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 131c0c050c5SMichael Chan __le16 event_id; 13287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 133c0c050c5SMichael Chan __le32 event_data2; 134c0c050c5SMichael Chan u8 opaque_v; 13587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 13687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 13787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 138c193554eSMichael Chan u8 timestamp_lo; 139c193554eSMichael Chan __le16 timestamp_hi; 140c0c050c5SMichael Chan __le32 event_data1; 14187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 14287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 14387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 14487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 14587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 14687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 14787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 14887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 149c0c050c5SMichael Chan }; 150c0c050c5SMichael Chan 151c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 152c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_mtu_change { 153c0c050c5SMichael Chan __le16 type; 15487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 15587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 15687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 157c0c050c5SMichael Chan __le16 event_id; 15887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE 0x1UL 159c0c050c5SMichael Chan __le32 event_data2; 160c0c050c5SMichael Chan u8 opaque_v; 16187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 16287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 16387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 164c193554eSMichael Chan u8 timestamp_lo; 165c193554eSMichael Chan __le16 timestamp_hi; 166c0c050c5SMichael Chan __le32 event_data1; 16787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 16887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 169c0c050c5SMichael Chan }; 170c0c050c5SMichael Chan 171c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 172c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_speed_change { 173c0c050c5SMichael Chan __le16 type; 17487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 17587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 17687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 177c0c050c5SMichael Chan __le16 event_id; 17887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 179c0c050c5SMichael Chan __le32 event_data2; 180c0c050c5SMichael Chan u8 opaque_v; 18187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 18287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 18387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 184c193554eSMichael Chan u8 timestamp_lo; 185c193554eSMichael Chan __le16 timestamp_hi; 186c0c050c5SMichael Chan __le32 event_data1; 18787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 18887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 18987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 19087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 19187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 19287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 19387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 19487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 19587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 19687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 19787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 19887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 19987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 20087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB 20187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 20287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 203c0c050c5SMichael Chan }; 204c0c050c5SMichael Chan 205c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 206c0c050c5SMichael Chan struct hwrm_async_event_cmpl_dcb_config_change { 207c0c050c5SMichael Chan __le16 type; 20887c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 20987c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 21087c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 211c0c050c5SMichael Chan __le16 event_id; 21287c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 213c0c050c5SMichael Chan __le32 event_data2; 21487c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_ETS 0x1UL 21587c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_PFC 0x2UL 21687c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA2_APP 0x4UL 217c0c050c5SMichael Chan u8 opaque_v; 21887c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 21987c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 22087c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 221c193554eSMichael Chan u8 timestamp_lo; 222c193554eSMichael Chan __le16 timestamp_hi; 223c0c050c5SMichael Chan __le32 event_data1; 22487c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 22587c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 22687c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_MASK 0xff0000UL 22787c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_SFT 16 22887c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE (0xffUL << 16) 22987c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_ROCE_PRIORITY_NONE 23087c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_MASK 0xff000000UL 23187c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_SFT 24 23287c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE (0xffUL << 24) 23387c374deSMichael Chan #define ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_LAST ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_RECOMMEND_L2_PRIORITY_NONE 234c0c050c5SMichael Chan }; 235c0c050c5SMichael Chan 236c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 237c0c050c5SMichael Chan struct hwrm_async_event_cmpl_port_conn_not_allowed { 238c0c050c5SMichael Chan __le16 type; 23987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 24087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 24187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 242c0c050c5SMichael Chan __le16 event_id; 24387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 244c0c050c5SMichael Chan __le32 event_data2; 245c0c050c5SMichael Chan u8 opaque_v; 24687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 24787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 24887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 249c193554eSMichael Chan u8 timestamp_lo; 250c193554eSMichael Chan __le16 timestamp_hi; 251c0c050c5SMichael Chan __le32 event_data1; 25287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 25387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 25487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 25587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 25687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 25787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 25887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 25987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 26087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 26111f15ed3SMichael Chan }; 26211f15ed3SMichael Chan 26311f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 26411f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 26511f15ed3SMichael Chan __le16 type; 26687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 26787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 26887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 26911f15ed3SMichael Chan __le16 event_id; 27087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 27111f15ed3SMichael Chan __le32 event_data2; 27211f15ed3SMichael Chan u8 opaque_v; 27387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 27487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 27587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 27611f15ed3SMichael Chan u8 timestamp_lo; 27711f15ed3SMichael Chan __le16 timestamp_hi; 27811f15ed3SMichael Chan __le32 event_data1; 27987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 28087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 28111f15ed3SMichael Chan }; 28211f15ed3SMichael Chan 28311f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 28411f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_change { 28511f15ed3SMichael Chan __le16 type; 28687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 28787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 28887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 28911f15ed3SMichael Chan __le16 event_id; 29087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 29111f15ed3SMichael Chan __le32 event_data2; 29211f15ed3SMichael Chan u8 opaque_v; 29387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 29487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 29587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 29611f15ed3SMichael Chan u8 timestamp_lo; 29711f15ed3SMichael Chan __le16 timestamp_hi; 29811f15ed3SMichael Chan __le32 event_data1; 29987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 30087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 30187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 30287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 303c0c050c5SMichael Chan }; 304c0c050c5SMichael Chan 305c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 306c0c050c5SMichael Chan struct hwrm_async_event_cmpl_func_drvr_unload { 307c0c050c5SMichael Chan __le16 type; 30887c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 30987c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 31087c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 311c0c050c5SMichael Chan __le16 event_id; 31287c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 313c0c050c5SMichael Chan __le32 event_data2; 314c0c050c5SMichael Chan u8 opaque_v; 31587c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 31687c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 31787c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 318c193554eSMichael Chan u8 timestamp_lo; 319c193554eSMichael Chan __le16 timestamp_hi; 320c0c050c5SMichael Chan __le32 event_data1; 32187c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 32287c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 323c0c050c5SMichael Chan }; 324c0c050c5SMichael Chan 325c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 326c0c050c5SMichael Chan struct hwrm_async_event_cmpl_func_drvr_load { 327c0c050c5SMichael Chan __le16 type; 32887c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 32987c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 33087c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 331c0c050c5SMichael Chan __le16 event_id; 33287c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 333c0c050c5SMichael Chan __le32 event_data2; 334c0c050c5SMichael Chan u8 opaque_v; 33587c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 33687c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 33787c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 338c193554eSMichael Chan u8 timestamp_lo; 339c193554eSMichael Chan __le16 timestamp_hi; 340c0c050c5SMichael Chan __le32 event_data1; 34187c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 34287c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 34387c374deSMichael Chan }; 34487c374deSMichael Chan 34587c374deSMichael Chan /* HWRM Asynchronous Event Completion Record to indicate completion of FLR related processing (16 bytes) */ 34687c374deSMichael Chan struct hwrm_async_event_cmpl_func_flr_proc_cmplt { 34787c374deSMichael Chan __le16 type; 34887c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_MASK 0x3fUL 34987c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_SFT 0 35087c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 35187c374deSMichael Chan __le16 event_id; 35287c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 35387c374deSMichael Chan __le32 event_data2; 35487c374deSMichael Chan u8 opaque_v; 35587c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_V 0x1UL 35687c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_MASK 0xfeUL 35787c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_OPAQUE_SFT 1 35887c374deSMichael Chan u8 timestamp_lo; 35987c374deSMichael Chan __le16 timestamp_hi; 36087c374deSMichael Chan __le32 event_data1; 36187c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 36287c374deSMichael Chan #define ASYNC_EVENT_CMPL_FUNC_FLR_PROC_CMPLT_EVENT_DATA1_FUNC_ID_SFT 0 363c0c050c5SMichael Chan }; 364c0c050c5SMichael Chan 365c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 366c0c050c5SMichael Chan struct hwrm_async_event_cmpl_pf_drvr_unload { 367c0c050c5SMichael Chan __le16 type; 36887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 36987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 37087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 371c0c050c5SMichael Chan __le16 event_id; 37287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 373c0c050c5SMichael Chan __le32 event_data2; 374c0c050c5SMichael Chan u8 opaque_v; 37587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 37687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 37787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 378c193554eSMichael Chan u8 timestamp_lo; 379c193554eSMichael Chan __le16 timestamp_hi; 380c0c050c5SMichael Chan __le32 event_data1; 38187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 38287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 38387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 38487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 385c0c050c5SMichael Chan }; 386c0c050c5SMichael Chan 387c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 388c0c050c5SMichael Chan struct hwrm_async_event_cmpl_pf_drvr_load { 389c0c050c5SMichael Chan __le16 type; 39087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 39187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 39287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 393c0c050c5SMichael Chan __le16 event_id; 39487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD 0x21UL 395c0c050c5SMichael Chan __le32 event_data2; 396c0c050c5SMichael Chan u8 opaque_v; 39787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 39887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 39987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 400c193554eSMichael Chan u8 timestamp_lo; 401c193554eSMichael Chan __le16 timestamp_hi; 402c0c050c5SMichael Chan __le32 event_data1; 40387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 40487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 40587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 40687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 407c0c050c5SMichael Chan }; 408c0c050c5SMichael Chan 409c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 410c0c050c5SMichael Chan struct hwrm_async_event_cmpl_vf_flr { 411c0c050c5SMichael Chan __le16 type; 41287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 41387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 41487c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 415c0c050c5SMichael Chan __le16 event_id; 41687c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR 0x30UL 417c0c050c5SMichael Chan __le32 event_data2; 418c0c050c5SMichael Chan u8 opaque_v; 41987c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 42087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 42187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 422c193554eSMichael Chan u8 timestamp_lo; 423c193554eSMichael Chan __le16 timestamp_hi; 424c0c050c5SMichael Chan __le32 event_data1; 42587c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 42687c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 427c0c050c5SMichael Chan }; 428c0c050c5SMichael Chan 429c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 430c0c050c5SMichael Chan struct hwrm_async_event_cmpl_vf_mac_addr_change { 431c0c050c5SMichael Chan __le16 type; 43287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 43387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 43487c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 435c0c050c5SMichael Chan __le16 event_id; 43687c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 437c0c050c5SMichael Chan __le32 event_data2; 438c0c050c5SMichael Chan u8 opaque_v; 43987c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 44087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 44187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 442c193554eSMichael Chan u8 timestamp_lo; 443c193554eSMichael Chan __le16 timestamp_hi; 444c0c050c5SMichael Chan __le32 event_data1; 44587c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 44687c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 447c0c050c5SMichael Chan }; 448c0c050c5SMichael Chan 44911f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 45011f15ed3SMichael Chan struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 45111f15ed3SMichael Chan __le16 type; 45287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 45387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 45487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 45511f15ed3SMichael Chan __le16 event_id; 45687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 45711f15ed3SMichael Chan __le32 event_data2; 45811f15ed3SMichael Chan u8 opaque_v; 45987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 46087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 46187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 46211f15ed3SMichael Chan u8 timestamp_lo; 46311f15ed3SMichael Chan __le16 timestamp_hi; 46411f15ed3SMichael Chan __le32 event_data1; 46587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 46611f15ed3SMichael Chan }; 46711f15ed3SMichael Chan 46811f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 46911f15ed3SMichael Chan struct hwrm_async_event_cmpl_vf_cfg_change { 47011f15ed3SMichael Chan __le16 type; 47187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 47287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 47387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 47411f15ed3SMichael Chan __le16 event_id; 47587c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 47611f15ed3SMichael Chan __le32 event_data2; 47711f15ed3SMichael Chan u8 opaque_v; 47887c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 47987c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 48087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 48111f15ed3SMichael Chan u8 timestamp_lo; 48211f15ed3SMichael Chan __le16 timestamp_hi; 48311f15ed3SMichael Chan __le32 event_data1; 48487c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 48587c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 48687c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 48787c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 48811f15ed3SMichael Chan }; 48911f15ed3SMichael Chan 490c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 491c0c050c5SMichael Chan struct hwrm_async_event_cmpl_hwrm_error { 492c0c050c5SMichael Chan __le16 type; 49387c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 49487c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 49587c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 496c0c050c5SMichael Chan __le16 event_id; 49787c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 498c0c050c5SMichael Chan __le32 event_data2; 49987c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 50087c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 50187c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 50287c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 50387c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 50487c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 505c0c050c5SMichael Chan u8 opaque_v; 50687c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 50787c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 50887c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 509c193554eSMichael Chan u8 timestamp_lo; 510c193554eSMichael Chan __le16 timestamp_hi; 511c0c050c5SMichael Chan __le32 event_data1; 51287c374deSMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 513c0c050c5SMichael Chan }; 514c0c050c5SMichael Chan 515c0c050c5SMichael Chan /* hwrm_ver_get */ 516c0c050c5SMichael Chan /* Input (24 bytes) */ 517c0c050c5SMichael Chan struct hwrm_ver_get_input { 518c0c050c5SMichael Chan __le16 req_type; 519c0c050c5SMichael Chan __le16 cmpl_ring; 520c0c050c5SMichael Chan __le16 seq_id; 521c0c050c5SMichael Chan __le16 target_id; 522c0c050c5SMichael Chan __le64 resp_addr; 523c0c050c5SMichael Chan u8 hwrm_intf_maj; 524c0c050c5SMichael Chan u8 hwrm_intf_min; 525c0c050c5SMichael Chan u8 hwrm_intf_upd; 526c0c050c5SMichael Chan u8 unused_0[5]; 527c0c050c5SMichael Chan }; 528c0c050c5SMichael Chan 529c0c050c5SMichael Chan /* Output (128 bytes) */ 530c0c050c5SMichael Chan struct hwrm_ver_get_output { 531c0c050c5SMichael Chan __le16 error_code; 532c0c050c5SMichael Chan __le16 req_type; 533c0c050c5SMichael Chan __le16 seq_id; 534c0c050c5SMichael Chan __le16 resp_len; 535c0c050c5SMichael Chan u8 hwrm_intf_maj; 536c0c050c5SMichael Chan u8 hwrm_intf_min; 537c0c050c5SMichael Chan u8 hwrm_intf_upd; 538c0c050c5SMichael Chan u8 hwrm_intf_rsvd; 539c0c050c5SMichael Chan u8 hwrm_fw_maj; 540c0c050c5SMichael Chan u8 hwrm_fw_min; 541c0c050c5SMichael Chan u8 hwrm_fw_bld; 542c0c050c5SMichael Chan u8 hwrm_fw_rsvd; 543c193554eSMichael Chan u8 mgmt_fw_maj; 544c193554eSMichael Chan u8 mgmt_fw_min; 545c193554eSMichael Chan u8 mgmt_fw_bld; 546c193554eSMichael Chan u8 mgmt_fw_rsvd; 547c193554eSMichael Chan u8 netctrl_fw_maj; 548c193554eSMichael Chan u8 netctrl_fw_min; 549c193554eSMichael Chan u8 netctrl_fw_bld; 550c193554eSMichael Chan u8 netctrl_fw_rsvd; 551441cabbbSMichael Chan __le32 dev_caps_cfg; 552441cabbbSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 553441cabbbSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 554f183886cSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 555f183886cSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 556c193554eSMichael Chan u8 roce_fw_maj; 557c193554eSMichael Chan u8 roce_fw_min; 558c193554eSMichael Chan u8 roce_fw_bld; 559c193554eSMichael Chan u8 roce_fw_rsvd; 560c0c050c5SMichael Chan char hwrm_fw_name[16]; 561c193554eSMichael Chan char mgmt_fw_name[16]; 562c193554eSMichael Chan char netctrl_fw_name[16]; 563c193554eSMichael Chan __le32 reserved2[4]; 564c193554eSMichael Chan char roce_fw_name[16]; 565c0c050c5SMichael Chan __le16 chip_num; 566c0c050c5SMichael Chan u8 chip_rev; 567c0c050c5SMichael Chan u8 chip_metal; 568c0c050c5SMichael Chan u8 chip_bond_id; 569c193554eSMichael Chan u8 chip_platform_type; 570441cabbbSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 571441cabbbSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 572441cabbbSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 573c0c050c5SMichael Chan __le16 max_req_win_len; 574c0c050c5SMichael Chan __le16 max_resp_len; 575c0c050c5SMichael Chan __le16 def_req_timeout; 5768eb992e8SMichael Chan u8 init_pending; 5778eb992e8SMichael Chan #define VER_GET_RESP_INIT_PENDING_DEV_NOT_RDY 0x1UL 578c193554eSMichael Chan u8 unused_0; 579c0c050c5SMichael Chan u8 unused_1; 580c0c050c5SMichael Chan u8 valid; 581c0c050c5SMichael Chan }; 582c0c050c5SMichael Chan 583c0c050c5SMichael Chan /* hwrm_func_reset */ 584c0c050c5SMichael Chan /* Input (24 bytes) */ 585c0c050c5SMichael Chan struct hwrm_func_reset_input { 586c0c050c5SMichael Chan __le16 req_type; 587c0c050c5SMichael Chan __le16 cmpl_ring; 588c0c050c5SMichael Chan __le16 seq_id; 589c0c050c5SMichael Chan __le16 target_id; 590c0c050c5SMichael Chan __le64 resp_addr; 591c0c050c5SMichael Chan __le32 enables; 592c0c050c5SMichael Chan #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 593c0c050c5SMichael Chan __le16 vf_id; 594c193554eSMichael Chan u8 func_reset_level; 595441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 596441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 597441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 598441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 599c193554eSMichael Chan u8 unused_0; 600c0c050c5SMichael Chan }; 601c0c050c5SMichael Chan 602c0c050c5SMichael Chan /* Output (16 bytes) */ 603c0c050c5SMichael Chan struct hwrm_func_reset_output { 604c0c050c5SMichael Chan __le16 error_code; 605c0c050c5SMichael Chan __le16 req_type; 606c0c050c5SMichael Chan __le16 seq_id; 607c0c050c5SMichael Chan __le16 resp_len; 608c0c050c5SMichael Chan __le32 unused_0; 609c0c050c5SMichael Chan u8 unused_1; 610c0c050c5SMichael Chan u8 unused_2; 611c0c050c5SMichael Chan u8 unused_3; 612c0c050c5SMichael Chan u8 valid; 613c0c050c5SMichael Chan }; 614c0c050c5SMichael Chan 615c0c050c5SMichael Chan /* hwrm_func_getfid */ 616c0c050c5SMichael Chan /* Input (24 bytes) */ 617c0c050c5SMichael Chan struct hwrm_func_getfid_input { 618c0c050c5SMichael Chan __le16 req_type; 619c0c050c5SMichael Chan __le16 cmpl_ring; 620c0c050c5SMichael Chan __le16 seq_id; 621c0c050c5SMichael Chan __le16 target_id; 622c0c050c5SMichael Chan __le64 resp_addr; 623c0c050c5SMichael Chan __le32 enables; 624c0c050c5SMichael Chan #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 625c0c050c5SMichael Chan __le16 pci_id; 626c0c050c5SMichael Chan __le16 unused_0; 627c0c050c5SMichael Chan }; 628c0c050c5SMichael Chan 629c0c050c5SMichael Chan /* Output (16 bytes) */ 630c0c050c5SMichael Chan struct hwrm_func_getfid_output { 631c0c050c5SMichael Chan __le16 error_code; 632c0c050c5SMichael Chan __le16 req_type; 633c0c050c5SMichael Chan __le16 seq_id; 634c0c050c5SMichael Chan __le16 resp_len; 635c0c050c5SMichael Chan __le16 fid; 636c0c050c5SMichael Chan u8 unused_0; 637c0c050c5SMichael Chan u8 unused_1; 638c0c050c5SMichael Chan u8 unused_2; 639c0c050c5SMichael Chan u8 unused_3; 640c0c050c5SMichael Chan u8 unused_4; 641c0c050c5SMichael Chan u8 valid; 642c0c050c5SMichael Chan }; 643c0c050c5SMichael Chan 644c0c050c5SMichael Chan /* hwrm_func_vf_alloc */ 645c0c050c5SMichael Chan /* Input (24 bytes) */ 646c0c050c5SMichael Chan struct hwrm_func_vf_alloc_input { 647c0c050c5SMichael Chan __le16 req_type; 648c0c050c5SMichael Chan __le16 cmpl_ring; 649c0c050c5SMichael Chan __le16 seq_id; 650c0c050c5SMichael Chan __le16 target_id; 651c0c050c5SMichael Chan __le64 resp_addr; 652c0c050c5SMichael Chan __le32 enables; 653c0c050c5SMichael Chan #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 654c0c050c5SMichael Chan __le16 first_vf_id; 655c0c050c5SMichael Chan __le16 num_vfs; 656c0c050c5SMichael Chan }; 657c0c050c5SMichael Chan 658c0c050c5SMichael Chan /* Output (16 bytes) */ 659c0c050c5SMichael Chan struct hwrm_func_vf_alloc_output { 660c0c050c5SMichael Chan __le16 error_code; 661c0c050c5SMichael Chan __le16 req_type; 662c0c050c5SMichael Chan __le16 seq_id; 663c0c050c5SMichael Chan __le16 resp_len; 664c0c050c5SMichael Chan __le16 first_vf_id; 665c0c050c5SMichael Chan u8 unused_0; 666c0c050c5SMichael Chan u8 unused_1; 667c0c050c5SMichael Chan u8 unused_2; 668c0c050c5SMichael Chan u8 unused_3; 669c0c050c5SMichael Chan u8 unused_4; 670c0c050c5SMichael Chan u8 valid; 671c0c050c5SMichael Chan }; 672c0c050c5SMichael Chan 673c0c050c5SMichael Chan /* hwrm_func_vf_free */ 674c0c050c5SMichael Chan /* Input (24 bytes) */ 675c0c050c5SMichael Chan struct hwrm_func_vf_free_input { 676c0c050c5SMichael Chan __le16 req_type; 677c0c050c5SMichael Chan __le16 cmpl_ring; 678c0c050c5SMichael Chan __le16 seq_id; 679c0c050c5SMichael Chan __le16 target_id; 680c0c050c5SMichael Chan __le64 resp_addr; 681c0c050c5SMichael Chan __le32 enables; 682c0c050c5SMichael Chan #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 683c0c050c5SMichael Chan __le16 first_vf_id; 684c0c050c5SMichael Chan __le16 num_vfs; 685c0c050c5SMichael Chan }; 686c0c050c5SMichael Chan 687c0c050c5SMichael Chan /* Output (16 bytes) */ 688c0c050c5SMichael Chan struct hwrm_func_vf_free_output { 689c0c050c5SMichael Chan __le16 error_code; 690c0c050c5SMichael Chan __le16 req_type; 691c0c050c5SMichael Chan __le16 seq_id; 692c0c050c5SMichael Chan __le16 resp_len; 693c0c050c5SMichael Chan __le32 unused_0; 694c0c050c5SMichael Chan u8 unused_1; 695c0c050c5SMichael Chan u8 unused_2; 696c0c050c5SMichael Chan u8 unused_3; 697c0c050c5SMichael Chan u8 valid; 698c0c050c5SMichael Chan }; 699c0c050c5SMichael Chan 700c0c050c5SMichael Chan /* hwrm_func_vf_cfg */ 701c193554eSMichael Chan /* Input (32 bytes) */ 702c0c050c5SMichael Chan struct hwrm_func_vf_cfg_input { 703c0c050c5SMichael Chan __le16 req_type; 704c0c050c5SMichael Chan __le16 cmpl_ring; 705c0c050c5SMichael Chan __le16 seq_id; 706c0c050c5SMichael Chan __le16 target_id; 707c0c050c5SMichael Chan __le64 resp_addr; 708c0c050c5SMichael Chan __le32 enables; 709c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 710c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 711c193554eSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 71211f15ed3SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 713c0c050c5SMichael Chan __le16 mtu; 714c0c050c5SMichael Chan __le16 guest_vlan; 715c193554eSMichael Chan __le16 async_event_cr; 71611f15ed3SMichael Chan u8 dflt_mac_addr[6]; 717c0c050c5SMichael Chan }; 718c0c050c5SMichael Chan 719c0c050c5SMichael Chan /* Output (16 bytes) */ 720c0c050c5SMichael Chan struct hwrm_func_vf_cfg_output { 721c0c050c5SMichael Chan __le16 error_code; 722c0c050c5SMichael Chan __le16 req_type; 723c0c050c5SMichael Chan __le16 seq_id; 724c0c050c5SMichael Chan __le16 resp_len; 725c0c050c5SMichael Chan __le32 unused_0; 726c0c050c5SMichael Chan u8 unused_1; 727c0c050c5SMichael Chan u8 unused_2; 728c0c050c5SMichael Chan u8 unused_3; 729c0c050c5SMichael Chan u8 valid; 730c0c050c5SMichael Chan }; 731c0c050c5SMichael Chan 732c0c050c5SMichael Chan /* hwrm_func_qcaps */ 733c0c050c5SMichael Chan /* Input (24 bytes) */ 734c0c050c5SMichael Chan struct hwrm_func_qcaps_input { 735c0c050c5SMichael Chan __le16 req_type; 736c0c050c5SMichael Chan __le16 cmpl_ring; 737c0c050c5SMichael Chan __le16 seq_id; 738c0c050c5SMichael Chan __le16 target_id; 739c0c050c5SMichael Chan __le64 resp_addr; 740c0c050c5SMichael Chan __le16 fid; 741c0c050c5SMichael Chan __le16 unused_0[3]; 742c0c050c5SMichael Chan }; 743c0c050c5SMichael Chan 744c0c050c5SMichael Chan /* Output (80 bytes) */ 745c0c050c5SMichael Chan struct hwrm_func_qcaps_output { 746c0c050c5SMichael Chan __le16 error_code; 747c0c050c5SMichael Chan __le16 req_type; 748c0c050c5SMichael Chan __le16 seq_id; 749c0c050c5SMichael Chan __le16 resp_len; 750c0c050c5SMichael Chan __le16 fid; 751c0c050c5SMichael Chan __le16 port_id; 752c0c050c5SMichael Chan __le32 flags; 753c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 754c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 75511f15ed3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 756a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 757a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 758a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 759a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 760441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 761441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 762441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 763441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 76487c374deSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 76511f15ed3SMichael Chan u8 mac_address[6]; 766c0c050c5SMichael Chan __le16 max_rsscos_ctx; 767c0c050c5SMichael Chan __le16 max_cmpl_rings; 768c0c050c5SMichael Chan __le16 max_tx_rings; 769c0c050c5SMichael Chan __le16 max_rx_rings; 770c0c050c5SMichael Chan __le16 max_l2_ctxs; 771c0c050c5SMichael Chan __le16 max_vnics; 772c0c050c5SMichael Chan __le16 first_vf_id; 773c0c050c5SMichael Chan __le16 max_vfs; 774c0c050c5SMichael Chan __le16 max_stat_ctx; 775c0c050c5SMichael Chan __le32 max_encap_records; 776c0c050c5SMichael Chan __le32 max_decap_records; 777c0c050c5SMichael Chan __le32 max_tx_em_flows; 778c0c050c5SMichael Chan __le32 max_tx_wm_flows; 779c0c050c5SMichael Chan __le32 max_rx_em_flows; 780c0c050c5SMichael Chan __le32 max_rx_wm_flows; 781c0c050c5SMichael Chan __le32 max_mcast_filters; 782c0c050c5SMichael Chan __le32 max_flow_id; 783c0c050c5SMichael Chan __le32 max_hw_ring_grps; 784441cabbbSMichael Chan __le16 max_sp_tx_rings; 785c0c050c5SMichael Chan u8 unused_0; 786c0c050c5SMichael Chan u8 valid; 787c0c050c5SMichael Chan }; 788c0c050c5SMichael Chan 78911f15ed3SMichael Chan /* hwrm_func_qcfg */ 79011f15ed3SMichael Chan /* Input (24 bytes) */ 79111f15ed3SMichael Chan struct hwrm_func_qcfg_input { 79211f15ed3SMichael Chan __le16 req_type; 79311f15ed3SMichael Chan __le16 cmpl_ring; 79411f15ed3SMichael Chan __le16 seq_id; 79511f15ed3SMichael Chan __le16 target_id; 79611f15ed3SMichael Chan __le64 resp_addr; 79711f15ed3SMichael Chan __le16 fid; 79811f15ed3SMichael Chan __le16 unused_0[3]; 79911f15ed3SMichael Chan }; 80011f15ed3SMichael Chan 80111f15ed3SMichael Chan /* Output (72 bytes) */ 80211f15ed3SMichael Chan struct hwrm_func_qcfg_output { 80311f15ed3SMichael Chan __le16 error_code; 80411f15ed3SMichael Chan __le16 req_type; 80511f15ed3SMichael Chan __le16 seq_id; 80611f15ed3SMichael Chan __le16 resp_len; 80711f15ed3SMichael Chan __le16 fid; 80811f15ed3SMichael Chan __le16 port_id; 80911f15ed3SMichael Chan __le16 vlan; 810a58a3e68SMichael Chan __le16 flags; 811a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 812a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 813441cabbbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 81487c374deSMichael Chan #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 8158eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 8168eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 81711f15ed3SMichael Chan u8 mac_address[6]; 81811f15ed3SMichael Chan __le16 pci_id; 81911f15ed3SMichael Chan __le16 alloc_rsscos_ctx; 82011f15ed3SMichael Chan __le16 alloc_cmpl_rings; 82111f15ed3SMichael Chan __le16 alloc_tx_rings; 82211f15ed3SMichael Chan __le16 alloc_rx_rings; 82311f15ed3SMichael Chan __le16 alloc_l2_ctx; 82411f15ed3SMichael Chan __le16 alloc_vnics; 82511f15ed3SMichael Chan __le16 mtu; 82611f15ed3SMichael Chan __le16 mru; 82711f15ed3SMichael Chan __le16 stat_ctx_id; 82811f15ed3SMichael Chan u8 port_partition_type; 829441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 830441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 831441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 832441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 833441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 834441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 8358eb992e8SMichael Chan u8 port_pf_cnt; 8368eb992e8SMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 83711f15ed3SMichael Chan __le16 dflt_vnic_id; 8388eb992e8SMichael Chan u8 unused_0; 839acb20054SMichael Chan u8 unused_1; 84011f15ed3SMichael Chan __le32 min_bw; 841441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 842441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 843bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 844bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 845bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 846bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 847441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 848441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 849bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 850bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 851bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 852bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 853441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 854441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 855441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 85611f15ed3SMichael Chan __le32 max_bw; 857441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 858441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 859bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 860bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 861bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 862bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 863441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 864441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 865bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 866bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 867bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 868bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 869441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 870441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 871441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 87211f15ed3SMichael Chan u8 evb_mode; 873441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 874441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 875441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 876acb20054SMichael Chan u8 unused_2; 877441cabbbSMichael Chan __le16 alloc_vfs; 87811f15ed3SMichael Chan __le32 alloc_mcast_filters; 87911f15ed3SMichael Chan __le32 alloc_hw_ring_grps; 880441cabbbSMichael Chan __le16 alloc_sp_tx_rings; 881acb20054SMichael Chan u8 unused_3; 882acb20054SMichael Chan u8 valid; 883acb20054SMichael Chan }; 884acb20054SMichael Chan 885acb20054SMichael Chan /* hwrm_func_vlan_cfg */ 886acb20054SMichael Chan /* Input (48 bytes) */ 887acb20054SMichael Chan struct hwrm_func_vlan_cfg_input { 888acb20054SMichael Chan __le16 req_type; 889acb20054SMichael Chan __le16 cmpl_ring; 890acb20054SMichael Chan __le16 seq_id; 891acb20054SMichael Chan __le16 target_id; 892acb20054SMichael Chan __le64 resp_addr; 893acb20054SMichael Chan __le16 fid; 894acb20054SMichael Chan u8 unused_0; 895acb20054SMichael Chan u8 unused_1; 896acb20054SMichael Chan __le32 enables; 897acb20054SMichael Chan #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL 898acb20054SMichael Chan #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL 899acb20054SMichael Chan #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL 900acb20054SMichael Chan #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL 901acb20054SMichael Chan #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL 902acb20054SMichael Chan #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL 903acb20054SMichael Chan __le16 stag_vid; 904acb20054SMichael Chan u8 stag_pcp; 9058eb992e8SMichael Chan u8 unused_2; 906acb20054SMichael Chan __be16 stag_tpid; 907acb20054SMichael Chan __le16 ctag_vid; 908acb20054SMichael Chan u8 ctag_pcp; 909acb20054SMichael Chan u8 unused_3; 910acb20054SMichael Chan __be16 ctag_tpid; 911acb20054SMichael Chan __le32 rsvd1; 912acb20054SMichael Chan __le32 rsvd2; 913acb20054SMichael Chan __le32 unused_4; 914acb20054SMichael Chan }; 915acb20054SMichael Chan 916acb20054SMichael Chan /* Output (16 bytes) */ 917acb20054SMichael Chan struct hwrm_func_vlan_cfg_output { 918acb20054SMichael Chan __le16 error_code; 919acb20054SMichael Chan __le16 req_type; 920acb20054SMichael Chan __le16 seq_id; 921acb20054SMichael Chan __le16 resp_len; 922acb20054SMichael Chan __le32 unused_0; 923acb20054SMichael Chan u8 unused_1; 924acb20054SMichael Chan u8 unused_2; 925acb20054SMichael Chan u8 unused_3; 92611f15ed3SMichael Chan u8 valid; 92711f15ed3SMichael Chan }; 92811f15ed3SMichael Chan 929c0c050c5SMichael Chan /* hwrm_func_cfg */ 930c0c050c5SMichael Chan /* Input (88 bytes) */ 931c0c050c5SMichael Chan struct hwrm_func_cfg_input { 932c0c050c5SMichael Chan __le16 req_type; 933c0c050c5SMichael Chan __le16 cmpl_ring; 934c0c050c5SMichael Chan __le16 seq_id; 935c0c050c5SMichael Chan __le16 target_id; 936c0c050c5SMichael Chan __le64 resp_addr; 937c193554eSMichael Chan __le16 fid; 938c0c050c5SMichael Chan u8 unused_0; 939c0c050c5SMichael Chan u8 unused_1; 940c0c050c5SMichael Chan __le32 flags; 9418eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 9428eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 9438eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 9448eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 9458eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 9468eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 9478eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 948acb20054SMichael Chan #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 949c0c050c5SMichael Chan __le32 enables; 950c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 951c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 952c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 953c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 954c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 955c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 956c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 957c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 958c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 959c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 960c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 961c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 962c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 963c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 964c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 965c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 966c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 967c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 968c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 969c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 970c0c050c5SMichael Chan __le16 mtu; 971c0c050c5SMichael Chan __le16 mru; 972c0c050c5SMichael Chan __le16 num_rsscos_ctxs; 973c0c050c5SMichael Chan __le16 num_cmpl_rings; 974c0c050c5SMichael Chan __le16 num_tx_rings; 975c0c050c5SMichael Chan __le16 num_rx_rings; 976c0c050c5SMichael Chan __le16 num_l2_ctxs; 977c0c050c5SMichael Chan __le16 num_vnics; 978c0c050c5SMichael Chan __le16 num_stat_ctxs; 979c0c050c5SMichael Chan __le16 num_hw_ring_grps; 980c0c050c5SMichael Chan u8 dflt_mac_addr[6]; 981c0c050c5SMichael Chan __le16 dflt_vlan; 982c0c050c5SMichael Chan __be32 dflt_ip_addr[4]; 983c0c050c5SMichael Chan __le32 min_bw; 984441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 985441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 986bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 987bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 988bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 989bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 990441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 991441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 992bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 993bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 994bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 995bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 996441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 997441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 998441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 999c0c050c5SMichael Chan __le32 max_bw; 1000441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1001441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1002bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1003bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1004bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1005bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1006441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1007441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1008bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1009bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1010bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1011bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1012441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1013441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1014441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1015c0c050c5SMichael Chan __le16 async_event_cr; 1016c0c050c5SMichael Chan u8 vlan_antispoof_mode; 1017441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1018441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1019441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1020441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1021c0c050c5SMichael Chan u8 allowed_vlan_pris; 1022c0c050c5SMichael Chan u8 evb_mode; 1023441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1024441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1025441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1026c0c050c5SMichael Chan u8 unused_2; 1027c0c050c5SMichael Chan __le16 num_mcast_filters; 1028c0c050c5SMichael Chan }; 1029c0c050c5SMichael Chan 1030c0c050c5SMichael Chan /* Output (16 bytes) */ 1031c0c050c5SMichael Chan struct hwrm_func_cfg_output { 1032c0c050c5SMichael Chan __le16 error_code; 1033c0c050c5SMichael Chan __le16 req_type; 1034c0c050c5SMichael Chan __le16 seq_id; 1035c0c050c5SMichael Chan __le16 resp_len; 1036c0c050c5SMichael Chan __le32 unused_0; 1037c0c050c5SMichael Chan u8 unused_1; 1038c0c050c5SMichael Chan u8 unused_2; 1039c0c050c5SMichael Chan u8 unused_3; 1040c0c050c5SMichael Chan u8 valid; 1041c0c050c5SMichael Chan }; 1042c0c050c5SMichael Chan 1043c0c050c5SMichael Chan /* hwrm_func_qstats */ 1044c0c050c5SMichael Chan /* Input (24 bytes) */ 1045c0c050c5SMichael Chan struct hwrm_func_qstats_input { 1046c0c050c5SMichael Chan __le16 req_type; 1047c0c050c5SMichael Chan __le16 cmpl_ring; 1048c0c050c5SMichael Chan __le16 seq_id; 1049c0c050c5SMichael Chan __le16 target_id; 1050c0c050c5SMichael Chan __le64 resp_addr; 1051c0c050c5SMichael Chan __le16 fid; 1052c0c050c5SMichael Chan __le16 unused_0[3]; 1053c0c050c5SMichael Chan }; 1054c0c050c5SMichael Chan 1055c0c050c5SMichael Chan /* Output (176 bytes) */ 1056c0c050c5SMichael Chan struct hwrm_func_qstats_output { 1057c0c050c5SMichael Chan __le16 error_code; 1058c0c050c5SMichael Chan __le16 req_type; 1059c0c050c5SMichael Chan __le16 seq_id; 1060c0c050c5SMichael Chan __le16 resp_len; 1061c0c050c5SMichael Chan __le64 tx_ucast_pkts; 1062c0c050c5SMichael Chan __le64 tx_mcast_pkts; 1063c0c050c5SMichael Chan __le64 tx_bcast_pkts; 10648eb992e8SMichael Chan __le64 tx_discard_pkts; 1065c0c050c5SMichael Chan __le64 tx_drop_pkts; 1066c0c050c5SMichael Chan __le64 tx_ucast_bytes; 1067c0c050c5SMichael Chan __le64 tx_mcast_bytes; 1068c0c050c5SMichael Chan __le64 tx_bcast_bytes; 1069c0c050c5SMichael Chan __le64 rx_ucast_pkts; 1070c0c050c5SMichael Chan __le64 rx_mcast_pkts; 1071c0c050c5SMichael Chan __le64 rx_bcast_pkts; 10728eb992e8SMichael Chan __le64 rx_discard_pkts; 1073c0c050c5SMichael Chan __le64 rx_drop_pkts; 1074c0c050c5SMichael Chan __le64 rx_ucast_bytes; 1075c0c050c5SMichael Chan __le64 rx_mcast_bytes; 1076c0c050c5SMichael Chan __le64 rx_bcast_bytes; 1077c0c050c5SMichael Chan __le64 rx_agg_pkts; 1078c0c050c5SMichael Chan __le64 rx_agg_bytes; 1079c0c050c5SMichael Chan __le64 rx_agg_events; 1080c0c050c5SMichael Chan __le64 rx_agg_aborts; 1081c0c050c5SMichael Chan __le32 unused_0; 1082c0c050c5SMichael Chan u8 unused_1; 1083c0c050c5SMichael Chan u8 unused_2; 1084c0c050c5SMichael Chan u8 unused_3; 1085c0c050c5SMichael Chan u8 valid; 1086c0c050c5SMichael Chan }; 1087c0c050c5SMichael Chan 1088c0c050c5SMichael Chan /* hwrm_func_clr_stats */ 1089c0c050c5SMichael Chan /* Input (24 bytes) */ 1090c0c050c5SMichael Chan struct hwrm_func_clr_stats_input { 1091c0c050c5SMichael Chan __le16 req_type; 1092c0c050c5SMichael Chan __le16 cmpl_ring; 1093c0c050c5SMichael Chan __le16 seq_id; 1094c0c050c5SMichael Chan __le16 target_id; 1095c0c050c5SMichael Chan __le64 resp_addr; 1096c0c050c5SMichael Chan __le16 fid; 1097c0c050c5SMichael Chan __le16 unused_0[3]; 1098c0c050c5SMichael Chan }; 1099c0c050c5SMichael Chan 1100c0c050c5SMichael Chan /* Output (16 bytes) */ 1101c0c050c5SMichael Chan struct hwrm_func_clr_stats_output { 1102c0c050c5SMichael Chan __le16 error_code; 1103c0c050c5SMichael Chan __le16 req_type; 1104c0c050c5SMichael Chan __le16 seq_id; 1105c0c050c5SMichael Chan __le16 resp_len; 1106c0c050c5SMichael Chan __le32 unused_0; 1107c0c050c5SMichael Chan u8 unused_1; 1108c0c050c5SMichael Chan u8 unused_2; 1109c0c050c5SMichael Chan u8 unused_3; 1110c0c050c5SMichael Chan u8 valid; 1111c0c050c5SMichael Chan }; 1112c0c050c5SMichael Chan 1113c0c050c5SMichael Chan /* hwrm_func_vf_resc_free */ 1114c0c050c5SMichael Chan /* Input (24 bytes) */ 1115c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_input { 1116c0c050c5SMichael Chan __le16 req_type; 1117c0c050c5SMichael Chan __le16 cmpl_ring; 1118c0c050c5SMichael Chan __le16 seq_id; 1119c0c050c5SMichael Chan __le16 target_id; 1120c0c050c5SMichael Chan __le64 resp_addr; 1121c0c050c5SMichael Chan __le16 vf_id; 1122c0c050c5SMichael Chan __le16 unused_0[3]; 1123c0c050c5SMichael Chan }; 1124c0c050c5SMichael Chan 1125c0c050c5SMichael Chan /* Output (16 bytes) */ 1126c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_output { 1127c0c050c5SMichael Chan __le16 error_code; 1128c0c050c5SMichael Chan __le16 req_type; 1129c0c050c5SMichael Chan __le16 seq_id; 1130c0c050c5SMichael Chan __le16 resp_len; 1131c0c050c5SMichael Chan __le32 unused_0; 1132c0c050c5SMichael Chan u8 unused_1; 1133c0c050c5SMichael Chan u8 unused_2; 1134c0c050c5SMichael Chan u8 unused_3; 1135c0c050c5SMichael Chan u8 valid; 1136c0c050c5SMichael Chan }; 1137c0c050c5SMichael Chan 1138c0c050c5SMichael Chan /* hwrm_func_vf_vnic_ids_query */ 1139c0c050c5SMichael Chan /* Input (32 bytes) */ 1140c0c050c5SMichael Chan struct hwrm_func_vf_vnic_ids_query_input { 1141c0c050c5SMichael Chan __le16 req_type; 1142c0c050c5SMichael Chan __le16 cmpl_ring; 1143c0c050c5SMichael Chan __le16 seq_id; 1144c0c050c5SMichael Chan __le16 target_id; 1145c0c050c5SMichael Chan __le64 resp_addr; 1146c0c050c5SMichael Chan __le16 vf_id; 1147c0c050c5SMichael Chan u8 unused_0; 1148c0c050c5SMichael Chan u8 unused_1; 1149c0c050c5SMichael Chan __le32 max_vnic_id_cnt; 1150c0c050c5SMichael Chan __le64 vnic_id_tbl_addr; 1151c0c050c5SMichael Chan }; 1152c0c050c5SMichael Chan 1153c0c050c5SMichael Chan /* Output (16 bytes) */ 1154c0c050c5SMichael Chan struct hwrm_func_vf_vnic_ids_query_output { 1155c0c050c5SMichael Chan __le16 error_code; 1156c0c050c5SMichael Chan __le16 req_type; 1157c0c050c5SMichael Chan __le16 seq_id; 1158c0c050c5SMichael Chan __le16 resp_len; 1159c0c050c5SMichael Chan __le32 vnic_id_cnt; 1160c0c050c5SMichael Chan u8 unused_0; 1161c0c050c5SMichael Chan u8 unused_1; 1162c0c050c5SMichael Chan u8 unused_2; 1163c0c050c5SMichael Chan u8 valid; 1164c0c050c5SMichael Chan }; 1165c0c050c5SMichael Chan 1166c0c050c5SMichael Chan /* hwrm_func_drv_rgtr */ 1167c0c050c5SMichael Chan /* Input (80 bytes) */ 1168c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_input { 1169c0c050c5SMichael Chan __le16 req_type; 1170c0c050c5SMichael Chan __le16 cmpl_ring; 1171c0c050c5SMichael Chan __le16 seq_id; 1172c0c050c5SMichael Chan __le16 target_id; 1173c0c050c5SMichael Chan __le64 resp_addr; 1174c0c050c5SMichael Chan __le32 flags; 1175c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1176c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1177c0c050c5SMichael Chan __le32 enables; 1178c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1179c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1180c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1181c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1182c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1183c0c050c5SMichael Chan __le16 os_type; 1184441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1185441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1186441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1187441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1188441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1189441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1190441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1191441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1192441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1193441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 119416d663a6SMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1195c0c050c5SMichael Chan u8 ver_maj; 1196c0c050c5SMichael Chan u8 ver_min; 1197c0c050c5SMichael Chan u8 ver_upd; 1198c0c050c5SMichael Chan u8 unused_0; 1199c0c050c5SMichael Chan __le16 unused_1; 1200c0c050c5SMichael Chan __le32 timestamp; 1201c0c050c5SMichael Chan __le32 unused_2; 1202c0c050c5SMichael Chan __le32 vf_req_fwd[8]; 1203c0c050c5SMichael Chan __le32 async_event_fwd[8]; 1204c0c050c5SMichael Chan }; 1205c0c050c5SMichael Chan 1206c0c050c5SMichael Chan /* Output (16 bytes) */ 1207c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_output { 1208c0c050c5SMichael Chan __le16 error_code; 1209c0c050c5SMichael Chan __le16 req_type; 1210c0c050c5SMichael Chan __le16 seq_id; 1211c0c050c5SMichael Chan __le16 resp_len; 1212c0c050c5SMichael Chan __le32 unused_0; 1213c0c050c5SMichael Chan u8 unused_1; 1214c0c050c5SMichael Chan u8 unused_2; 1215c0c050c5SMichael Chan u8 unused_3; 1216c0c050c5SMichael Chan u8 valid; 1217c0c050c5SMichael Chan }; 1218c0c050c5SMichael Chan 1219c0c050c5SMichael Chan /* hwrm_func_drv_unrgtr */ 1220c0c050c5SMichael Chan /* Input (24 bytes) */ 1221c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_input { 1222c0c050c5SMichael Chan __le16 req_type; 1223c0c050c5SMichael Chan __le16 cmpl_ring; 1224c0c050c5SMichael Chan __le16 seq_id; 1225c0c050c5SMichael Chan __le16 target_id; 1226c0c050c5SMichael Chan __le64 resp_addr; 1227c0c050c5SMichael Chan __le32 flags; 1228c0c050c5SMichael Chan #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1229c0c050c5SMichael Chan __le32 unused_0; 1230c0c050c5SMichael Chan }; 1231c0c050c5SMichael Chan 1232c0c050c5SMichael Chan /* Output (16 bytes) */ 1233c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_output { 1234c0c050c5SMichael Chan __le16 error_code; 1235c0c050c5SMichael Chan __le16 req_type; 1236c0c050c5SMichael Chan __le16 seq_id; 1237c0c050c5SMichael Chan __le16 resp_len; 1238c0c050c5SMichael Chan __le32 unused_0; 1239c0c050c5SMichael Chan u8 unused_1; 1240c0c050c5SMichael Chan u8 unused_2; 1241c0c050c5SMichael Chan u8 unused_3; 1242c0c050c5SMichael Chan u8 valid; 1243c0c050c5SMichael Chan }; 1244c0c050c5SMichael Chan 1245c0c050c5SMichael Chan /* hwrm_func_buf_rgtr */ 1246c0c050c5SMichael Chan /* Input (128 bytes) */ 1247c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_input { 1248c0c050c5SMichael Chan __le16 req_type; 1249c0c050c5SMichael Chan __le16 cmpl_ring; 1250c0c050c5SMichael Chan __le16 seq_id; 1251c0c050c5SMichael Chan __le16 target_id; 1252c0c050c5SMichael Chan __le64 resp_addr; 1253c0c050c5SMichael Chan __le32 enables; 1254c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1255c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1256c0c050c5SMichael Chan __le16 vf_id; 1257c0c050c5SMichael Chan __le16 req_buf_num_pages; 1258c0c050c5SMichael Chan __le16 req_buf_page_size; 1259441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1260441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1261441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1262441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1263441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1264441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1265441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1266c0c050c5SMichael Chan __le16 req_buf_len; 1267c0c050c5SMichael Chan __le16 resp_buf_len; 1268c0c050c5SMichael Chan u8 unused_0; 1269c0c050c5SMichael Chan u8 unused_1; 1270c0c050c5SMichael Chan __le64 req_buf_page_addr0; 1271c0c050c5SMichael Chan __le64 req_buf_page_addr1; 1272c0c050c5SMichael Chan __le64 req_buf_page_addr2; 1273c0c050c5SMichael Chan __le64 req_buf_page_addr3; 1274c0c050c5SMichael Chan __le64 req_buf_page_addr4; 1275c0c050c5SMichael Chan __le64 req_buf_page_addr5; 1276c0c050c5SMichael Chan __le64 req_buf_page_addr6; 1277c0c050c5SMichael Chan __le64 req_buf_page_addr7; 1278c0c050c5SMichael Chan __le64 req_buf_page_addr8; 1279c0c050c5SMichael Chan __le64 req_buf_page_addr9; 1280c0c050c5SMichael Chan __le64 error_buf_addr; 1281c0c050c5SMichael Chan __le64 resp_buf_addr; 1282c0c050c5SMichael Chan }; 1283c0c050c5SMichael Chan 1284c0c050c5SMichael Chan /* Output (16 bytes) */ 1285c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_output { 1286c0c050c5SMichael Chan __le16 error_code; 1287c0c050c5SMichael Chan __le16 req_type; 1288c0c050c5SMichael Chan __le16 seq_id; 1289c0c050c5SMichael Chan __le16 resp_len; 1290c0c050c5SMichael Chan __le32 unused_0; 1291c0c050c5SMichael Chan u8 unused_1; 1292c0c050c5SMichael Chan u8 unused_2; 1293c0c050c5SMichael Chan u8 unused_3; 1294c0c050c5SMichael Chan u8 valid; 1295c0c050c5SMichael Chan }; 1296c0c050c5SMichael Chan 1297c0c050c5SMichael Chan /* hwrm_func_drv_qver */ 1298c0c050c5SMichael Chan /* Input (24 bytes) */ 1299c0c050c5SMichael Chan struct hwrm_func_drv_qver_input { 1300c0c050c5SMichael Chan __le16 req_type; 1301c0c050c5SMichael Chan __le16 cmpl_ring; 1302c0c050c5SMichael Chan __le16 seq_id; 1303c0c050c5SMichael Chan __le16 target_id; 1304c0c050c5SMichael Chan __le64 resp_addr; 1305c193554eSMichael Chan __le32 reserved; 1306c0c050c5SMichael Chan __le16 fid; 1307c0c050c5SMichael Chan __le16 unused_0; 1308c0c050c5SMichael Chan }; 1309c0c050c5SMichael Chan 1310c0c050c5SMichael Chan /* Output (16 bytes) */ 1311c0c050c5SMichael Chan struct hwrm_func_drv_qver_output { 1312c0c050c5SMichael Chan __le16 error_code; 1313c0c050c5SMichael Chan __le16 req_type; 1314c0c050c5SMichael Chan __le16 seq_id; 1315c0c050c5SMichael Chan __le16 resp_len; 1316c0c050c5SMichael Chan __le16 os_type; 1317441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1318441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1319441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1320441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1321441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1322441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1323441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1324441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1325441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1326441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 132787c374deSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1328c0c050c5SMichael Chan u8 ver_maj; 1329c0c050c5SMichael Chan u8 ver_min; 1330c0c050c5SMichael Chan u8 ver_upd; 1331c0c050c5SMichael Chan u8 unused_0; 1332c0c050c5SMichael Chan u8 unused_1; 1333c0c050c5SMichael Chan u8 valid; 1334c0c050c5SMichael Chan }; 1335c0c050c5SMichael Chan 1336c0c050c5SMichael Chan /* hwrm_port_phy_cfg */ 133711f15ed3SMichael Chan /* Input (56 bytes) */ 1338c0c050c5SMichael Chan struct hwrm_port_phy_cfg_input { 1339c0c050c5SMichael Chan __le16 req_type; 1340c0c050c5SMichael Chan __le16 cmpl_ring; 1341c0c050c5SMichael Chan __le16 seq_id; 1342c0c050c5SMichael Chan __le16 target_id; 1343c0c050c5SMichael Chan __le64 resp_addr; 1344c0c050c5SMichael Chan __le32 flags; 1345c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 134616d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1347c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1348c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 134911f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 135011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 135111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 135211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1353a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1354a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1355a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1356a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1357a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1358a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 135916d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1360c0c050c5SMichael Chan __le32 enables; 1361c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1362c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1363c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1364c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1365c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1366c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1367c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1368c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1369c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 137011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 137111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1372c0c050c5SMichael Chan __le16 port_id; 1373c0c050c5SMichael Chan __le16 force_link_speed; 1374441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1375441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1376441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1377441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1378441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1379441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1380441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1381441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1382441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1383441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1384441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1385c0c050c5SMichael Chan u8 auto_mode; 1386441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1387441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1388441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1389441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1390441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1391c0c050c5SMichael Chan u8 auto_duplex; 1392441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1393441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1394441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1395c0c050c5SMichael Chan u8 auto_pause; 1396c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1397c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 139811f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1399c0c050c5SMichael Chan u8 unused_0; 1400c0c050c5SMichael Chan __le16 auto_link_speed; 1401441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1402441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1403441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1404441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1405441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1406441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1407441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1408441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1409441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1410441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1411441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1412c0c050c5SMichael Chan __le16 auto_link_speed_mask; 1413c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1414c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1415c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1416c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1417c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1418c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1419c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1420c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1421c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1422c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1423c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 142411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 142511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 142611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1427c0c050c5SMichael Chan u8 wirespeed; 1428441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1429441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1430c0c050c5SMichael Chan u8 lpbk; 1431441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1432441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1433441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1434c0c050c5SMichael Chan u8 force_pause; 1435c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1436c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1437c0c050c5SMichael Chan u8 unused_1; 1438c0c050c5SMichael Chan __le32 preemphasis; 143911f15ed3SMichael Chan __le16 eee_link_speed_mask; 144011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 144111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 144211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 144311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 144411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 144511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 144611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 144711f15ed3SMichael Chan u8 unused_2; 144811f15ed3SMichael Chan u8 unused_3; 144911f15ed3SMichael Chan __le32 tx_lpi_timer; 145011f15ed3SMichael Chan __le32 unused_4; 145111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 145211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1453c0c050c5SMichael Chan }; 1454c0c050c5SMichael Chan 1455c0c050c5SMichael Chan /* Output (16 bytes) */ 1456c0c050c5SMichael Chan struct hwrm_port_phy_cfg_output { 1457c0c050c5SMichael Chan __le16 error_code; 1458c0c050c5SMichael Chan __le16 req_type; 1459c0c050c5SMichael Chan __le16 seq_id; 1460c0c050c5SMichael Chan __le16 resp_len; 1461c0c050c5SMichael Chan __le32 unused_0; 1462c0c050c5SMichael Chan u8 unused_1; 1463c0c050c5SMichael Chan u8 unused_2; 1464c0c050c5SMichael Chan u8 unused_3; 1465c0c050c5SMichael Chan u8 valid; 1466c0c050c5SMichael Chan }; 1467c0c050c5SMichael Chan 1468c0c050c5SMichael Chan /* hwrm_port_phy_qcfg */ 1469c0c050c5SMichael Chan /* Input (24 bytes) */ 1470c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_input { 1471c0c050c5SMichael Chan __le16 req_type; 1472c0c050c5SMichael Chan __le16 cmpl_ring; 1473c0c050c5SMichael Chan __le16 seq_id; 1474c0c050c5SMichael Chan __le16 target_id; 1475c0c050c5SMichael Chan __le64 resp_addr; 1476c0c050c5SMichael Chan __le16 port_id; 1477c0c050c5SMichael Chan __le16 unused_0[3]; 1478c0c050c5SMichael Chan }; 1479c0c050c5SMichael Chan 148011f15ed3SMichael Chan /* Output (96 bytes) */ 1481c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_output { 1482c0c050c5SMichael Chan __le16 error_code; 1483c0c050c5SMichael Chan __le16 req_type; 1484c0c050c5SMichael Chan __le16 seq_id; 1485c0c050c5SMichael Chan __le16 resp_len; 1486c0c050c5SMichael Chan u8 link; 1487441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1488441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1489441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1490c0c050c5SMichael Chan u8 unused_0; 1491c0c050c5SMichael Chan __le16 link_speed; 1492441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1493441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1494441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1495441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1496441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1497441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1498441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1499441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1500441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1501441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1502441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1503acb20054SMichael Chan u8 duplex_cfg; 1504acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 1505acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 1506c0c050c5SMichael Chan u8 pause; 1507c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1508c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1509c0c050c5SMichael Chan __le16 support_speeds; 1510c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1511c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1512c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1513c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1514c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1515c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1516c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1517c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1518c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1519c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1520c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 152111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 152211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 152311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1524c0c050c5SMichael Chan __le16 force_link_speed; 1525441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1526441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1527441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1528441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1529441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1530441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1531441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1532441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1533441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1534441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1535441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1536c0c050c5SMichael Chan u8 auto_mode; 1537441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1538441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1539441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1540441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1541441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1542c0c050c5SMichael Chan u8 auto_pause; 1543c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1544c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 154511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1546c0c050c5SMichael Chan __le16 auto_link_speed; 1547441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1548441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1549441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1550441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1551441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1552441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1553441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1554441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1555441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1556441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1557441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1558c0c050c5SMichael Chan __le16 auto_link_speed_mask; 1559c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1560c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1561c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1562c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1563c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1564c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1565c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1566c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1567c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1568c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1569c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 157011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 157111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 157211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1573c0c050c5SMichael Chan u8 wirespeed; 1574441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1575441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1576c0c050c5SMichael Chan u8 lpbk; 1577441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1578441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1579441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1580c0c050c5SMichael Chan u8 force_pause; 1581c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1582c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 158311f15ed3SMichael Chan u8 module_status; 1584441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1585441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1586441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1587441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1588441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1589441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1590c0c050c5SMichael Chan __le32 preemphasis; 1591c0c050c5SMichael Chan u8 phy_maj; 1592c0c050c5SMichael Chan u8 phy_min; 1593c0c050c5SMichael Chan u8 phy_bld; 1594c0c050c5SMichael Chan u8 phy_type; 1595441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1596441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1597441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1598441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1599441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1600441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1601441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1602441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1603441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1604441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1605441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1606bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1607bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1608bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1609bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1610bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1611bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1612bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1613bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1614bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1615bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1616bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1617bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1618bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1619bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1620acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 1621acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 1622acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 1623c0c050c5SMichael Chan u8 media_type; 1624441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1625441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1626441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1627441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 162811f15ed3SMichael Chan u8 xcvr_pkg_type; 1629441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1630441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 163111f15ed3SMichael Chan u8 eee_config_phy_addr; 1632c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1633c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 163411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 163511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 163611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 163711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 163811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 163911f15ed3SMichael Chan u8 parallel_detect; 164011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 164111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 164211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1643c0c050c5SMichael Chan __le16 link_partner_adv_speeds; 1644c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1645c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1646c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1647c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1648c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1649c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1650c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1651c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1652c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1653c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1654c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 165511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 165611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 165711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1658c0c050c5SMichael Chan u8 link_partner_adv_auto_mode; 1659441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1660441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1661441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1662441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1663441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1664c0c050c5SMichael Chan u8 link_partner_adv_pause; 1665c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1666c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 166711f15ed3SMichael Chan __le16 adv_eee_link_speed_mask; 166811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 166911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 167011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 167111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 167211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 167311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 167411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 167511f15ed3SMichael Chan __le16 link_partner_adv_eee_link_speed_mask; 167611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 167711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 167811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 167911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 168011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 168111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 168211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 168311f15ed3SMichael Chan __le32 xcvr_identifier_type_tx_lpi_timer; 168411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 168511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 168611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 168711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 168811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 168911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 169011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 169111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 169211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1693a58a3e68SMichael Chan __le16 fec_cfg; 1694a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1695a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1696a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1697a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1698a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1699a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1700a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1701acb20054SMichael Chan u8 duplex_state; 1702acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 1703acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 1704a58a3e68SMichael Chan u8 unused_1; 170511f15ed3SMichael Chan char phy_vendor_name[16]; 170611f15ed3SMichael Chan char phy_vendor_partnumber[16]; 1707acb20054SMichael Chan __le32 unused_2; 1708acb20054SMichael Chan u8 unused_3; 1709c0c050c5SMichael Chan u8 unused_4; 1710c0c050c5SMichael Chan u8 unused_5; 1711c0c050c5SMichael Chan u8 valid; 1712c0c050c5SMichael Chan }; 1713c0c050c5SMichael Chan 1714c0c050c5SMichael Chan /* hwrm_port_mac_cfg */ 171511f15ed3SMichael Chan /* Input (40 bytes) */ 1716c0c050c5SMichael Chan struct hwrm_port_mac_cfg_input { 1717c0c050c5SMichael Chan __le16 req_type; 1718c0c050c5SMichael Chan __le16 cmpl_ring; 1719c0c050c5SMichael Chan __le16 seq_id; 1720c0c050c5SMichael Chan __le16 target_id; 1721c0c050c5SMichael Chan __le64 resp_addr; 1722c0c050c5SMichael Chan __le32 flags; 1723c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1724441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1725c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1726c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 172711f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 172811f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 172911f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 173011f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1731a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1732a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1733441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1734441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1735441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1736c0c050c5SMichael Chan __le32 enables; 1737c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1738c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1739441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1740441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_RESERVED1 0x8UL 1741c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1742c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 174311f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 174411f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1745441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1746c0c050c5SMichael Chan __le16 port_id; 1747c0c050c5SMichael Chan u8 ipg; 1748c0c050c5SMichael Chan u8 lpbk; 1749441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1750441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1751441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1752441cabbbSMichael Chan u8 vlan_pri2cos_map_pri; 1753441cabbbSMichael Chan u8 reserved1; 1754c0c050c5SMichael Chan u8 tunnel_pri2cos_map_pri; 1755c0c050c5SMichael Chan u8 dscp2pri_map_pri; 175611f15ed3SMichael Chan __le16 rx_ts_capture_ptp_msg_type; 175711f15ed3SMichael Chan __le16 tx_ts_capture_ptp_msg_type; 1758441cabbbSMichael Chan u8 cos_field_cfg; 1759441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1760441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1761441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1762441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1763441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1764441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1765441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1766441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1767441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1768441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1769441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1770441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1771441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1772441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1773441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1774441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1775441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1776441cabbbSMichael Chan u8 unused_0[3]; 1777c0c050c5SMichael Chan }; 1778c0c050c5SMichael Chan 1779c0c050c5SMichael Chan /* Output (16 bytes) */ 1780c0c050c5SMichael Chan struct hwrm_port_mac_cfg_output { 1781c0c050c5SMichael Chan __le16 error_code; 1782c0c050c5SMichael Chan __le16 req_type; 1783c0c050c5SMichael Chan __le16 seq_id; 1784c0c050c5SMichael Chan __le16 resp_len; 1785c0c050c5SMichael Chan __le16 mru; 1786c0c050c5SMichael Chan __le16 mtu; 1787c0c050c5SMichael Chan u8 ipg; 1788c0c050c5SMichael Chan u8 lpbk; 1789441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1790441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1791441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1792c0c050c5SMichael Chan u8 unused_0; 1793c0c050c5SMichael Chan u8 valid; 1794c0c050c5SMichael Chan }; 1795c0c050c5SMichael Chan 1796acb20054SMichael Chan /* hwrm_port_mac_ptp_qcfg */ 1797acb20054SMichael Chan /* Input (24 bytes) */ 1798acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_input { 1799acb20054SMichael Chan __le16 req_type; 1800acb20054SMichael Chan __le16 cmpl_ring; 1801acb20054SMichael Chan __le16 seq_id; 1802acb20054SMichael Chan __le16 target_id; 1803acb20054SMichael Chan __le64 resp_addr; 1804acb20054SMichael Chan __le16 port_id; 1805acb20054SMichael Chan __le16 unused_0[3]; 1806acb20054SMichael Chan }; 1807acb20054SMichael Chan 1808acb20054SMichael Chan /* Output (80 bytes) */ 1809acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_output { 1810acb20054SMichael Chan __le16 error_code; 1811acb20054SMichael Chan __le16 req_type; 1812acb20054SMichael Chan __le16 seq_id; 1813acb20054SMichael Chan __le16 resp_len; 1814acb20054SMichael Chan u8 flags; 1815acb20054SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 1816acb20054SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 1817acb20054SMichael Chan u8 unused_0; 1818acb20054SMichael Chan __le16 unused_1; 1819acb20054SMichael Chan __le32 rx_ts_reg_off_lower; 1820acb20054SMichael Chan __le32 rx_ts_reg_off_upper; 1821acb20054SMichael Chan __le32 rx_ts_reg_off_seq_id; 1822acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_0; 1823acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_1; 1824acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_2; 1825acb20054SMichael Chan __le32 rx_ts_reg_off_domain_id; 1826acb20054SMichael Chan __le32 rx_ts_reg_off_fifo; 1827acb20054SMichael Chan __le32 rx_ts_reg_off_fifo_adv; 1828acb20054SMichael Chan __le32 rx_ts_reg_off_granularity; 1829acb20054SMichael Chan __le32 tx_ts_reg_off_lower; 1830acb20054SMichael Chan __le32 tx_ts_reg_off_upper; 1831acb20054SMichael Chan __le32 tx_ts_reg_off_seq_id; 1832acb20054SMichael Chan __le32 tx_ts_reg_off_fifo; 1833acb20054SMichael Chan __le32 tx_ts_reg_off_granularity; 1834acb20054SMichael Chan __le32 unused_2; 1835acb20054SMichael Chan u8 unused_3; 1836acb20054SMichael Chan u8 unused_4; 1837acb20054SMichael Chan u8 unused_5; 1838acb20054SMichael Chan u8 valid; 1839acb20054SMichael Chan }; 1840acb20054SMichael Chan 1841c0c050c5SMichael Chan /* hwrm_port_qstats */ 1842c0c050c5SMichael Chan /* Input (40 bytes) */ 1843c0c050c5SMichael Chan struct hwrm_port_qstats_input { 1844c0c050c5SMichael Chan __le16 req_type; 1845c0c050c5SMichael Chan __le16 cmpl_ring; 1846c0c050c5SMichael Chan __le16 seq_id; 1847c0c050c5SMichael Chan __le16 target_id; 1848c0c050c5SMichael Chan __le64 resp_addr; 1849c0c050c5SMichael Chan __le16 port_id; 1850c0c050c5SMichael Chan u8 unused_0; 1851c0c050c5SMichael Chan u8 unused_1; 1852c0c050c5SMichael Chan u8 unused_2[3]; 1853c0c050c5SMichael Chan u8 unused_3; 1854c0c050c5SMichael Chan __le64 tx_stat_host_addr; 1855c0c050c5SMichael Chan __le64 rx_stat_host_addr; 1856c0c050c5SMichael Chan }; 1857c0c050c5SMichael Chan 1858c0c050c5SMichael Chan /* Output (16 bytes) */ 1859c0c050c5SMichael Chan struct hwrm_port_qstats_output { 1860c0c050c5SMichael Chan __le16 error_code; 1861c0c050c5SMichael Chan __le16 req_type; 1862c0c050c5SMichael Chan __le16 seq_id; 1863c0c050c5SMichael Chan __le16 resp_len; 1864c193554eSMichael Chan __le16 tx_stat_size; 1865c193554eSMichael Chan __le16 rx_stat_size; 1866c193554eSMichael Chan u8 unused_0; 1867c0c050c5SMichael Chan u8 unused_1; 1868c0c050c5SMichael Chan u8 unused_2; 1869c0c050c5SMichael Chan u8 valid; 1870c0c050c5SMichael Chan }; 1871c0c050c5SMichael Chan 1872c0c050c5SMichael Chan /* hwrm_port_lpbk_qstats */ 1873c0c050c5SMichael Chan /* Input (16 bytes) */ 1874c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_input { 1875c0c050c5SMichael Chan __le16 req_type; 1876c0c050c5SMichael Chan __le16 cmpl_ring; 1877c0c050c5SMichael Chan __le16 seq_id; 1878c0c050c5SMichael Chan __le16 target_id; 1879c0c050c5SMichael Chan __le64 resp_addr; 1880c0c050c5SMichael Chan }; 1881c0c050c5SMichael Chan 1882c193554eSMichael Chan /* Output (96 bytes) */ 1883c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_output { 1884c0c050c5SMichael Chan __le16 error_code; 1885c0c050c5SMichael Chan __le16 req_type; 1886c0c050c5SMichael Chan __le16 seq_id; 1887c0c050c5SMichael Chan __le16 resp_len; 1888c0c050c5SMichael Chan __le64 lpbk_ucast_frames; 1889c0c050c5SMichael Chan __le64 lpbk_mcast_frames; 1890c0c050c5SMichael Chan __le64 lpbk_bcast_frames; 1891c0c050c5SMichael Chan __le64 lpbk_ucast_bytes; 1892c0c050c5SMichael Chan __le64 lpbk_mcast_bytes; 1893c0c050c5SMichael Chan __le64 lpbk_bcast_bytes; 1894c193554eSMichael Chan __le64 tx_stat_discard; 1895c193554eSMichael Chan __le64 tx_stat_error; 1896c193554eSMichael Chan __le64 rx_stat_discard; 1897c193554eSMichael Chan __le64 rx_stat_error; 1898c0c050c5SMichael Chan __le32 unused_0; 1899c0c050c5SMichael Chan u8 unused_1; 1900c0c050c5SMichael Chan u8 unused_2; 1901c0c050c5SMichael Chan u8 unused_3; 1902c0c050c5SMichael Chan u8 valid; 1903c0c050c5SMichael Chan }; 1904c0c050c5SMichael Chan 1905c0c050c5SMichael Chan /* hwrm_port_clr_stats */ 1906c0c050c5SMichael Chan /* Input (24 bytes) */ 1907c0c050c5SMichael Chan struct hwrm_port_clr_stats_input { 1908c0c050c5SMichael Chan __le16 req_type; 1909c0c050c5SMichael Chan __le16 cmpl_ring; 1910c0c050c5SMichael Chan __le16 seq_id; 1911c0c050c5SMichael Chan __le16 target_id; 1912c0c050c5SMichael Chan __le64 resp_addr; 1913c0c050c5SMichael Chan __le16 port_id; 1914c0c050c5SMichael Chan __le16 unused_0[3]; 1915c0c050c5SMichael Chan }; 1916c0c050c5SMichael Chan 1917c0c050c5SMichael Chan /* Output (16 bytes) */ 1918c0c050c5SMichael Chan struct hwrm_port_clr_stats_output { 1919c0c050c5SMichael Chan __le16 error_code; 1920c0c050c5SMichael Chan __le16 req_type; 1921c0c050c5SMichael Chan __le16 seq_id; 1922c0c050c5SMichael Chan __le16 resp_len; 1923c0c050c5SMichael Chan __le32 unused_0; 1924c0c050c5SMichael Chan u8 unused_1; 1925c0c050c5SMichael Chan u8 unused_2; 1926c0c050c5SMichael Chan u8 unused_3; 1927c0c050c5SMichael Chan u8 valid; 1928c0c050c5SMichael Chan }; 1929c0c050c5SMichael Chan 1930c0c050c5SMichael Chan /* hwrm_port_lpbk_clr_stats */ 1931c0c050c5SMichael Chan /* Input (16 bytes) */ 1932c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_input { 1933c0c050c5SMichael Chan __le16 req_type; 1934c0c050c5SMichael Chan __le16 cmpl_ring; 1935c0c050c5SMichael Chan __le16 seq_id; 1936c0c050c5SMichael Chan __le16 target_id; 1937c0c050c5SMichael Chan __le64 resp_addr; 1938c0c050c5SMichael Chan }; 1939c0c050c5SMichael Chan 1940c0c050c5SMichael Chan /* Output (16 bytes) */ 1941c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_output { 1942c0c050c5SMichael Chan __le16 error_code; 1943c0c050c5SMichael Chan __le16 req_type; 1944c0c050c5SMichael Chan __le16 seq_id; 1945c0c050c5SMichael Chan __le16 resp_len; 1946c0c050c5SMichael Chan __le32 unused_0; 1947c0c050c5SMichael Chan u8 unused_1; 1948c0c050c5SMichael Chan u8 unused_2; 1949c0c050c5SMichael Chan u8 unused_3; 1950c0c050c5SMichael Chan u8 valid; 1951c0c050c5SMichael Chan }; 1952c0c050c5SMichael Chan 195311f15ed3SMichael Chan /* hwrm_port_phy_qcaps */ 195411f15ed3SMichael Chan /* Input (24 bytes) */ 195511f15ed3SMichael Chan struct hwrm_port_phy_qcaps_input { 195611f15ed3SMichael Chan __le16 req_type; 195711f15ed3SMichael Chan __le16 cmpl_ring; 195811f15ed3SMichael Chan __le16 seq_id; 195911f15ed3SMichael Chan __le16 target_id; 196011f15ed3SMichael Chan __le64 resp_addr; 196111f15ed3SMichael Chan __le16 port_id; 196211f15ed3SMichael Chan __le16 unused_0[3]; 196311f15ed3SMichael Chan }; 196411f15ed3SMichael Chan 196511f15ed3SMichael Chan /* Output (24 bytes) */ 196611f15ed3SMichael Chan struct hwrm_port_phy_qcaps_output { 196711f15ed3SMichael Chan __le16 error_code; 196811f15ed3SMichael Chan __le16 req_type; 196911f15ed3SMichael Chan __le16 seq_id; 197011f15ed3SMichael Chan __le16 resp_len; 1971acb20054SMichael Chan u8 flags; 1972acb20054SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 1973acb20054SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 1974acb20054SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 197511f15ed3SMichael Chan u8 unused_0; 197611f15ed3SMichael Chan __le16 supported_speeds_force_mode; 197711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 197811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 197911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 198011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 198111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 198211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 198311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 198411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 198511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 198611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 198711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 198811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 198911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 199011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 199111f15ed3SMichael Chan __le16 supported_speeds_auto_mode; 199211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 199311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 199411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 199511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 199611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 199711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 199811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 199911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 200011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 200111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 200211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 200311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 200411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 200511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 200611f15ed3SMichael Chan __le16 supported_speeds_eee_mode; 200711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 200811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 200911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 201011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 201111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 201211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 201311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 201411f15ed3SMichael Chan __le32 tx_lpi_timer_low; 201511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 201611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 201711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 201811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 201911f15ed3SMichael Chan __le32 valid_tx_lpi_timer_high; 202011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 202111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 202211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 202311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 202411f15ed3SMichael Chan }; 202511f15ed3SMichael Chan 202642ee18feSAjit Khaparde /* hwrm_port_phy_i2c_read */ 202742ee18feSAjit Khaparde /* Input (40 bytes) */ 202842ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_input { 202942ee18feSAjit Khaparde __le16 req_type; 203042ee18feSAjit Khaparde __le16 cmpl_ring; 203142ee18feSAjit Khaparde __le16 seq_id; 203242ee18feSAjit Khaparde __le16 target_id; 203342ee18feSAjit Khaparde __le64 resp_addr; 203442ee18feSAjit Khaparde __le32 flags; 203542ee18feSAjit Khaparde __le32 enables; 203642ee18feSAjit Khaparde #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 203742ee18feSAjit Khaparde __le16 port_id; 203842ee18feSAjit Khaparde u8 i2c_slave_addr; 203942ee18feSAjit Khaparde u8 unused_0; 204042ee18feSAjit Khaparde __le16 page_number; 204142ee18feSAjit Khaparde __le16 page_offset; 204242ee18feSAjit Khaparde u8 data_length; 204342ee18feSAjit Khaparde u8 unused_1[7]; 204442ee18feSAjit Khaparde }; 204542ee18feSAjit Khaparde 204642ee18feSAjit Khaparde /* Output (80 bytes) */ 204742ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_output { 204842ee18feSAjit Khaparde __le16 error_code; 204942ee18feSAjit Khaparde __le16 req_type; 205042ee18feSAjit Khaparde __le16 seq_id; 205142ee18feSAjit Khaparde __le16 resp_len; 205242ee18feSAjit Khaparde __le32 data[16]; 205342ee18feSAjit Khaparde __le32 unused_0; 205442ee18feSAjit Khaparde u8 unused_1; 205542ee18feSAjit Khaparde u8 unused_2; 205642ee18feSAjit Khaparde u8 unused_3; 205742ee18feSAjit Khaparde u8 valid; 205842ee18feSAjit Khaparde }; 205942ee18feSAjit Khaparde 2060f183886cSMichael Chan /* hwrm_port_led_cfg */ 2061f183886cSMichael Chan /* Input (64 bytes) */ 2062f183886cSMichael Chan struct hwrm_port_led_cfg_input { 2063f183886cSMichael Chan __le16 req_type; 2064f183886cSMichael Chan __le16 cmpl_ring; 2065f183886cSMichael Chan __le16 seq_id; 2066f183886cSMichael Chan __le16 target_id; 2067f183886cSMichael Chan __le64 resp_addr; 2068f183886cSMichael Chan __le32 enables; 2069f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2070f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2071f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2072f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2073f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2074f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2075f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2076f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2077f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2078f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2079f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2080f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2081f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2082f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2083f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2084f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2085f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2086f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2087f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2088f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2089f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2090f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2091f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2092f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2093f183886cSMichael Chan __le16 port_id; 2094f183886cSMichael Chan u8 num_leds; 2095f183886cSMichael Chan u8 rsvd; 2096f183886cSMichael Chan u8 led0_id; 2097f183886cSMichael Chan u8 led0_state; 2098f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2099f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2100f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2101f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2102f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2103f183886cSMichael Chan u8 led0_color; 2104f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2105f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2106f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2107f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2108f183886cSMichael Chan u8 unused_0; 2109f183886cSMichael Chan __le16 led0_blink_on; 2110f183886cSMichael Chan __le16 led0_blink_off; 2111f183886cSMichael Chan u8 led0_group_id; 2112f183886cSMichael Chan u8 rsvd0; 2113f183886cSMichael Chan u8 led1_id; 2114f183886cSMichael Chan u8 led1_state; 2115f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2116f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2117f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2118f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2119f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2120f183886cSMichael Chan u8 led1_color; 2121f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2122f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2123f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2124f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2125f183886cSMichael Chan u8 unused_1; 2126f183886cSMichael Chan __le16 led1_blink_on; 2127f183886cSMichael Chan __le16 led1_blink_off; 2128f183886cSMichael Chan u8 led1_group_id; 2129f183886cSMichael Chan u8 rsvd1; 2130f183886cSMichael Chan u8 led2_id; 2131f183886cSMichael Chan u8 led2_state; 2132f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2133f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2134f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2135f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2136f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2137f183886cSMichael Chan u8 led2_color; 2138f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2139f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2140f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2141f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2142f183886cSMichael Chan u8 unused_2; 2143f183886cSMichael Chan __le16 led2_blink_on; 2144f183886cSMichael Chan __le16 led2_blink_off; 2145f183886cSMichael Chan u8 led2_group_id; 2146f183886cSMichael Chan u8 rsvd2; 2147f183886cSMichael Chan u8 led3_id; 2148f183886cSMichael Chan u8 led3_state; 2149f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2150f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2151f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2152f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2153f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2154f183886cSMichael Chan u8 led3_color; 2155f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2156f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2157f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2158f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2159f183886cSMichael Chan u8 unused_3; 2160f183886cSMichael Chan __le16 led3_blink_on; 2161f183886cSMichael Chan __le16 led3_blink_off; 2162f183886cSMichael Chan u8 led3_group_id; 2163f183886cSMichael Chan u8 rsvd3; 2164f183886cSMichael Chan }; 2165f183886cSMichael Chan 2166f183886cSMichael Chan /* Output (16 bytes) */ 2167f183886cSMichael Chan struct hwrm_port_led_cfg_output { 2168f183886cSMichael Chan __le16 error_code; 2169f183886cSMichael Chan __le16 req_type; 2170f183886cSMichael Chan __le16 seq_id; 2171f183886cSMichael Chan __le16 resp_len; 2172f183886cSMichael Chan __le32 unused_0; 2173f183886cSMichael Chan u8 unused_1; 2174f183886cSMichael Chan u8 unused_2; 2175f183886cSMichael Chan u8 unused_3; 2176f183886cSMichael Chan u8 valid; 2177f183886cSMichael Chan }; 2178f183886cSMichael Chan 2179f183886cSMichael Chan /* hwrm_port_led_qcaps */ 2180f183886cSMichael Chan /* Input (24 bytes) */ 2181f183886cSMichael Chan struct hwrm_port_led_qcaps_input { 2182f183886cSMichael Chan __le16 req_type; 2183f183886cSMichael Chan __le16 cmpl_ring; 2184f183886cSMichael Chan __le16 seq_id; 2185f183886cSMichael Chan __le16 target_id; 2186f183886cSMichael Chan __le64 resp_addr; 2187f183886cSMichael Chan __le16 port_id; 2188f183886cSMichael Chan __le16 unused_0[3]; 2189f183886cSMichael Chan }; 2190f183886cSMichael Chan 2191f183886cSMichael Chan /* Output (48 bytes) */ 2192f183886cSMichael Chan struct hwrm_port_led_qcaps_output { 2193f183886cSMichael Chan __le16 error_code; 2194f183886cSMichael Chan __le16 req_type; 2195f183886cSMichael Chan __le16 seq_id; 2196f183886cSMichael Chan __le16 resp_len; 2197f183886cSMichael Chan u8 num_leds; 2198f183886cSMichael Chan u8 unused_0[3]; 2199f183886cSMichael Chan u8 led0_id; 2200f183886cSMichael Chan u8 led0_type; 2201f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2202f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2203f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2204f183886cSMichael Chan u8 led0_group_id; 2205f183886cSMichael Chan u8 unused_1; 2206f183886cSMichael Chan __le16 led0_state_caps; 2207f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2208f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2209f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2210f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2211f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2212f183886cSMichael Chan __le16 led0_color_caps; 2213f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2214f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2215f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2216f183886cSMichael Chan u8 led1_id; 2217f183886cSMichael Chan u8 led1_type; 2218f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2219f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2220f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2221f183886cSMichael Chan u8 led1_group_id; 2222f183886cSMichael Chan u8 unused_2; 2223f183886cSMichael Chan __le16 led1_state_caps; 2224f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2225f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2226f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2227f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2228f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2229f183886cSMichael Chan __le16 led1_color_caps; 2230f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2231f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2232f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2233f183886cSMichael Chan u8 led2_id; 2234f183886cSMichael Chan u8 led2_type; 2235f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2236f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2237f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2238f183886cSMichael Chan u8 led2_group_id; 2239f183886cSMichael Chan u8 unused_3; 2240f183886cSMichael Chan __le16 led2_state_caps; 2241f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2242f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2243f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2244f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2245f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2246f183886cSMichael Chan __le16 led2_color_caps; 2247f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2248f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2249f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2250f183886cSMichael Chan u8 led3_id; 2251f183886cSMichael Chan u8 led3_type; 2252f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2253f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2254f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2255f183886cSMichael Chan u8 led3_group_id; 2256f183886cSMichael Chan u8 unused_4; 2257f183886cSMichael Chan __le16 led3_state_caps; 2258f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2259f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2260f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2261f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2262f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2263f183886cSMichael Chan __le16 led3_color_caps; 2264f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2265f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2266f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2267f183886cSMichael Chan u8 unused_5; 2268f183886cSMichael Chan u8 unused_6; 2269f183886cSMichael Chan u8 unused_7; 2270f183886cSMichael Chan u8 valid; 2271f183886cSMichael Chan }; 2272f183886cSMichael Chan 2273a58a3e68SMichael Chan /* hwrm_queue_qportcfg */ 2274c0c050c5SMichael Chan /* Input (24 bytes) */ 2275c0c050c5SMichael Chan struct hwrm_queue_qportcfg_input { 2276c0c050c5SMichael Chan __le16 req_type; 2277c0c050c5SMichael Chan __le16 cmpl_ring; 2278c0c050c5SMichael Chan __le16 seq_id; 2279c0c050c5SMichael Chan __le16 target_id; 2280c0c050c5SMichael Chan __le64 resp_addr; 2281c0c050c5SMichael Chan __le32 flags; 2282c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2283441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2284441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 228511f15ed3SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2286c0c050c5SMichael Chan __le16 port_id; 2287c0c050c5SMichael Chan __le16 unused_0; 2288c0c050c5SMichael Chan }; 2289c0c050c5SMichael Chan 2290c0c050c5SMichael Chan /* Output (32 bytes) */ 2291c0c050c5SMichael Chan struct hwrm_queue_qportcfg_output { 2292c0c050c5SMichael Chan __le16 error_code; 2293c0c050c5SMichael Chan __le16 req_type; 2294c0c050c5SMichael Chan __le16 seq_id; 2295c0c050c5SMichael Chan __le16 resp_len; 2296c0c050c5SMichael Chan u8 max_configurable_queues; 2297c0c050c5SMichael Chan u8 max_configurable_lossless_queues; 2298c0c050c5SMichael Chan u8 queue_cfg_allowed; 2299441cabbbSMichael Chan u8 queue_cfg_info; 2300441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2301c0c050c5SMichael Chan u8 queue_pfcenable_cfg_allowed; 2302c0c050c5SMichael Chan u8 queue_pri2cos_cfg_allowed; 2303c0c050c5SMichael Chan u8 queue_cos2bw_cfg_allowed; 2304c0c050c5SMichael Chan u8 queue_id0; 2305c0c050c5SMichael Chan u8 queue_id0_service_profile; 2306441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2307441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 2308441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2309c0c050c5SMichael Chan u8 queue_id1; 2310c0c050c5SMichael Chan u8 queue_id1_service_profile; 2311441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2312441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 2313441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2314c0c050c5SMichael Chan u8 queue_id2; 2315c0c050c5SMichael Chan u8 queue_id2_service_profile; 2316441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2317441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 2318441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2319c0c050c5SMichael Chan u8 queue_id3; 2320c0c050c5SMichael Chan u8 queue_id3_service_profile; 2321441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2322441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 2323441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2324c0c050c5SMichael Chan u8 queue_id4; 2325c0c050c5SMichael Chan u8 queue_id4_service_profile; 2326441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2327441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 2328441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2329c0c050c5SMichael Chan u8 queue_id5; 2330c0c050c5SMichael Chan u8 queue_id5_service_profile; 2331441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2332441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 2333441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2334c0c050c5SMichael Chan u8 queue_id6; 2335c0c050c5SMichael Chan u8 queue_id6_service_profile; 2336441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2337441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 2338441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2339c0c050c5SMichael Chan u8 queue_id7; 2340c0c050c5SMichael Chan u8 queue_id7_service_profile; 2341441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2342441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 2343441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2344c0c050c5SMichael Chan u8 valid; 2345c0c050c5SMichael Chan }; 2346c0c050c5SMichael Chan 2347c0c050c5SMichael Chan /* hwrm_queue_cfg */ 2348c0c050c5SMichael Chan /* Input (40 bytes) */ 2349c0c050c5SMichael Chan struct hwrm_queue_cfg_input { 2350c0c050c5SMichael Chan __le16 req_type; 2351c0c050c5SMichael Chan __le16 cmpl_ring; 2352c0c050c5SMichael Chan __le16 seq_id; 2353c0c050c5SMichael Chan __le16 target_id; 2354c0c050c5SMichael Chan __le64 resp_addr; 2355c0c050c5SMichael Chan __le32 flags; 2356441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2357441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2358441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2359441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2360441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2361441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2362c0c050c5SMichael Chan __le32 enables; 2363c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2364c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2365c0c050c5SMichael Chan __le32 queue_id; 2366c0c050c5SMichael Chan __le32 dflt_len; 2367c0c050c5SMichael Chan u8 service_profile; 2368441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2369441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2370441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2371c0c050c5SMichael Chan u8 unused_0[7]; 2372c0c050c5SMichael Chan }; 2373c0c050c5SMichael Chan 2374c0c050c5SMichael Chan /* Output (16 bytes) */ 2375c0c050c5SMichael Chan struct hwrm_queue_cfg_output { 2376c0c050c5SMichael Chan __le16 error_code; 2377c0c050c5SMichael Chan __le16 req_type; 2378c0c050c5SMichael Chan __le16 seq_id; 2379c0c050c5SMichael Chan __le16 resp_len; 2380c0c050c5SMichael Chan __le32 unused_0; 2381c0c050c5SMichael Chan u8 unused_1; 2382c0c050c5SMichael Chan u8 unused_2; 2383c0c050c5SMichael Chan u8 unused_3; 2384c0c050c5SMichael Chan u8 valid; 2385c0c050c5SMichael Chan }; 2386c0c050c5SMichael Chan 238787c374deSMichael Chan /* hwrm_queue_pfcenable_qcfg */ 238887c374deSMichael Chan /* Input (24 bytes) */ 238987c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_input { 239087c374deSMichael Chan __le16 req_type; 239187c374deSMichael Chan __le16 cmpl_ring; 239287c374deSMichael Chan __le16 seq_id; 239387c374deSMichael Chan __le16 target_id; 239487c374deSMichael Chan __le64 resp_addr; 239587c374deSMichael Chan __le16 port_id; 239687c374deSMichael Chan __le16 unused_0[3]; 239787c374deSMichael Chan }; 239887c374deSMichael Chan 239987c374deSMichael Chan /* Output (16 bytes) */ 240087c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_output { 240187c374deSMichael Chan __le16 error_code; 240287c374deSMichael Chan __le16 req_type; 240387c374deSMichael Chan __le16 seq_id; 240487c374deSMichael Chan __le16 resp_len; 240587c374deSMichael Chan __le32 flags; 240687c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 240787c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 240887c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 240987c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 241087c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 241187c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 241287c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 241387c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 241487c374deSMichael Chan u8 unused_0; 241587c374deSMichael Chan u8 unused_1; 241687c374deSMichael Chan u8 unused_2; 241787c374deSMichael Chan u8 valid; 241887c374deSMichael Chan }; 241987c374deSMichael Chan 2420c0c050c5SMichael Chan /* hwrm_queue_pfcenable_cfg */ 2421c0c050c5SMichael Chan /* Input (24 bytes) */ 2422c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_input { 2423c0c050c5SMichael Chan __le16 req_type; 2424c0c050c5SMichael Chan __le16 cmpl_ring; 2425c0c050c5SMichael Chan __le16 seq_id; 2426c0c050c5SMichael Chan __le16 target_id; 2427c0c050c5SMichael Chan __le64 resp_addr; 2428c193554eSMichael Chan __le32 flags; 2429c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2430c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2431c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2432c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2433c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2434c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2435c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2436c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2437c0c050c5SMichael Chan __le16 port_id; 2438c0c050c5SMichael Chan __le16 unused_0; 2439c0c050c5SMichael Chan }; 2440c0c050c5SMichael Chan 2441c0c050c5SMichael Chan /* Output (16 bytes) */ 2442c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_output { 2443c0c050c5SMichael Chan __le16 error_code; 2444c0c050c5SMichael Chan __le16 req_type; 2445c0c050c5SMichael Chan __le16 seq_id; 2446c0c050c5SMichael Chan __le16 resp_len; 2447c0c050c5SMichael Chan __le32 unused_0; 2448c0c050c5SMichael Chan u8 unused_1; 2449c0c050c5SMichael Chan u8 unused_2; 2450c0c050c5SMichael Chan u8 unused_3; 2451c0c050c5SMichael Chan u8 valid; 2452c0c050c5SMichael Chan }; 2453c0c050c5SMichael Chan 245487c374deSMichael Chan /* hwrm_queue_pri2cos_qcfg */ 245587c374deSMichael Chan /* Input (24 bytes) */ 245687c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_input { 245787c374deSMichael Chan __le16 req_type; 245887c374deSMichael Chan __le16 cmpl_ring; 245987c374deSMichael Chan __le16 seq_id; 246087c374deSMichael Chan __le16 target_id; 246187c374deSMichael Chan __le64 resp_addr; 246287c374deSMichael Chan __le32 flags; 246387c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 246487c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 246587c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 246687c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 246787c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 246887c374deSMichael Chan u8 port_id; 246987c374deSMichael Chan u8 unused_0[3]; 247087c374deSMichael Chan }; 247187c374deSMichael Chan 247287c374deSMichael Chan /* Output (24 bytes) */ 247387c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_output { 247487c374deSMichael Chan __le16 error_code; 247587c374deSMichael Chan __le16 req_type; 247687c374deSMichael Chan __le16 seq_id; 247787c374deSMichael Chan __le16 resp_len; 247887c374deSMichael Chan u8 pri0_cos_queue_id; 247987c374deSMichael Chan u8 pri1_cos_queue_id; 248087c374deSMichael Chan u8 pri2_cos_queue_id; 248187c374deSMichael Chan u8 pri3_cos_queue_id; 248287c374deSMichael Chan u8 pri4_cos_queue_id; 248387c374deSMichael Chan u8 pri5_cos_queue_id; 248487c374deSMichael Chan u8 pri6_cos_queue_id; 248587c374deSMichael Chan u8 pri7_cos_queue_id; 248687c374deSMichael Chan u8 queue_cfg_info; 248787c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 248887c374deSMichael Chan u8 unused_0; 248987c374deSMichael Chan __le16 unused_1; 249087c374deSMichael Chan u8 unused_2; 249187c374deSMichael Chan u8 unused_3; 249287c374deSMichael Chan u8 unused_4; 249387c374deSMichael Chan u8 valid; 249487c374deSMichael Chan }; 249587c374deSMichael Chan 2496c0c050c5SMichael Chan /* hwrm_queue_pri2cos_cfg */ 2497c0c050c5SMichael Chan /* Input (40 bytes) */ 2498c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_input { 2499c0c050c5SMichael Chan __le16 req_type; 2500c0c050c5SMichael Chan __le16 cmpl_ring; 2501c0c050c5SMichael Chan __le16 seq_id; 2502c0c050c5SMichael Chan __le16 target_id; 2503c0c050c5SMichael Chan __le64 resp_addr; 2504c0c050c5SMichael Chan __le32 flags; 2505441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2506441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2507c0c050c5SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2508c0c050c5SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 2509441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR (0x2UL << 0) 2510441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2511441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2512c0c050c5SMichael Chan __le32 enables; 2513441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2514441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2515441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2516441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2517441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2518441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2519441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2520441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2521c0c050c5SMichael Chan u8 port_id; 2522c193554eSMichael Chan u8 pri0_cos_queue_id; 2523c193554eSMichael Chan u8 pri1_cos_queue_id; 2524c193554eSMichael Chan u8 pri2_cos_queue_id; 2525c193554eSMichael Chan u8 pri3_cos_queue_id; 2526c193554eSMichael Chan u8 pri4_cos_queue_id; 2527c193554eSMichael Chan u8 pri5_cos_queue_id; 2528c193554eSMichael Chan u8 pri6_cos_queue_id; 2529c193554eSMichael Chan u8 pri7_cos_queue_id; 2530c0c050c5SMichael Chan u8 unused_0[7]; 2531c0c050c5SMichael Chan }; 2532c0c050c5SMichael Chan 2533c0c050c5SMichael Chan /* Output (16 bytes) */ 2534c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_output { 2535c0c050c5SMichael Chan __le16 error_code; 2536c0c050c5SMichael Chan __le16 req_type; 2537c0c050c5SMichael Chan __le16 seq_id; 2538c0c050c5SMichael Chan __le16 resp_len; 2539c0c050c5SMichael Chan __le32 unused_0; 2540c0c050c5SMichael Chan u8 unused_1; 2541c0c050c5SMichael Chan u8 unused_2; 2542c0c050c5SMichael Chan u8 unused_3; 2543c0c050c5SMichael Chan u8 valid; 2544c0c050c5SMichael Chan }; 2545c0c050c5SMichael Chan 254687c374deSMichael Chan /* hwrm_queue_cos2bw_qcfg */ 254787c374deSMichael Chan /* Input (24 bytes) */ 254887c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_input { 254987c374deSMichael Chan __le16 req_type; 255087c374deSMichael Chan __le16 cmpl_ring; 255187c374deSMichael Chan __le16 seq_id; 255287c374deSMichael Chan __le16 target_id; 255387c374deSMichael Chan __le64 resp_addr; 255487c374deSMichael Chan __le16 port_id; 255587c374deSMichael Chan __le16 unused_0[3]; 255687c374deSMichael Chan }; 255787c374deSMichael Chan 255887c374deSMichael Chan /* Output (112 bytes) */ 255987c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_output { 256087c374deSMichael Chan __le16 error_code; 256187c374deSMichael Chan __le16 req_type; 256287c374deSMichael Chan __le16 seq_id; 256387c374deSMichael Chan __le16 resp_len; 256487c374deSMichael Chan u8 queue_id0; 256587c374deSMichael Chan u8 unused_0; 256687c374deSMichael Chan __le16 unused_1; 256787c374deSMichael Chan __le32 queue_id0_min_bw; 256887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 256987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2570bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2571bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2572bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2573bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 257487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 257587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2576bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2577bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2578bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2579bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 258087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 258187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 258287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 258387c374deSMichael Chan __le32 queue_id0_max_bw; 258487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 258587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2586bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2587bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2588bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2589bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 259087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 259187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2592bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2593bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2594bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2595bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 259687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 259787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 259887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 259987c374deSMichael Chan u8 queue_id0_tsa_assign; 260087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 260187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 260287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 260387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 260487c374deSMichael Chan u8 queue_id0_pri_lvl; 260587c374deSMichael Chan u8 queue_id0_bw_weight; 260687c374deSMichael Chan u8 queue_id1; 260787c374deSMichael Chan __le32 queue_id1_min_bw; 260887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 260987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2610bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2611bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2612bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2613bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 261487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 261587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2616bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2617bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2618bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2619bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 262087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 262187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 262287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 262387c374deSMichael Chan __le32 queue_id1_max_bw; 262487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 262587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2626bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2627bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2628bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2629bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 263087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 263187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2632bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2633bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2634bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2635bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 263687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 263787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 263887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 263987c374deSMichael Chan u8 queue_id1_tsa_assign; 264087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 264187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 264287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 264387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 264487c374deSMichael Chan u8 queue_id1_pri_lvl; 264587c374deSMichael Chan u8 queue_id1_bw_weight; 264687c374deSMichael Chan u8 queue_id2; 264787c374deSMichael Chan __le32 queue_id2_min_bw; 264887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 264987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2650bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2651bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2652bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2653bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 265487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 265587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2656bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2657bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2658bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2659bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 266087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 266187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 266287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 266387c374deSMichael Chan __le32 queue_id2_max_bw; 266487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 266587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2666bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2667bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2668bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2669bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 267087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 267187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2672bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2673bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2674bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2675bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 267687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 267787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 267887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 267987c374deSMichael Chan u8 queue_id2_tsa_assign; 268087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 268187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 268287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 268387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 268487c374deSMichael Chan u8 queue_id2_pri_lvl; 268587c374deSMichael Chan u8 queue_id2_bw_weight; 268687c374deSMichael Chan u8 queue_id3; 268787c374deSMichael Chan __le32 queue_id3_min_bw; 268887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 268987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 2690bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 2691bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 2692bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 2693bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 269487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 269587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 2696bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2697bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2698bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2699bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 270087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 270187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 270287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 270387c374deSMichael Chan __le32 queue_id3_max_bw; 270487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 270587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 2706bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 2707bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 2708bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 2709bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 271087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 271187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 2712bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2713bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2714bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2715bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 271687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 271787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 271887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 271987c374deSMichael Chan u8 queue_id3_tsa_assign; 272087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 272187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 272287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 272387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 272487c374deSMichael Chan u8 queue_id3_pri_lvl; 272587c374deSMichael Chan u8 queue_id3_bw_weight; 272687c374deSMichael Chan u8 queue_id4; 272787c374deSMichael Chan __le32 queue_id4_min_bw; 272887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 272987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 2730bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 2731bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 2732bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 2733bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 273487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 273587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 2736bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2737bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2738bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2739bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 274087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 274187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 274287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 274387c374deSMichael Chan __le32 queue_id4_max_bw; 274487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 274587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 2746bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 2747bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 2748bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 2749bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 275087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 275187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 2752bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2753bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2754bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2755bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 275687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 275787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 275887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 275987c374deSMichael Chan u8 queue_id4_tsa_assign; 276087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 276187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 276287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 276387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 276487c374deSMichael Chan u8 queue_id4_pri_lvl; 276587c374deSMichael Chan u8 queue_id4_bw_weight; 276687c374deSMichael Chan u8 queue_id5; 276787c374deSMichael Chan __le32 queue_id5_min_bw; 276887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 276987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 2770bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 2771bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 2772bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 2773bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 277487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 277587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 2776bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2777bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2778bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2779bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 278087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 278187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 278287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 278387c374deSMichael Chan __le32 queue_id5_max_bw; 278487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 278587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 2786bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 2787bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 2788bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 2789bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 279087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 279187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 2792bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2793bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2794bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2795bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 279687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 279787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 279887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 279987c374deSMichael Chan u8 queue_id5_tsa_assign; 280087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 280187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 280287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 280387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 280487c374deSMichael Chan u8 queue_id5_pri_lvl; 280587c374deSMichael Chan u8 queue_id5_bw_weight; 280687c374deSMichael Chan u8 queue_id6; 280787c374deSMichael Chan __le32 queue_id6_min_bw; 280887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 280987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 2810bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 2811bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 2812bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 2813bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 281487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 281587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 2816bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2817bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2818bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2819bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 282087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 282187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 282287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 282387c374deSMichael Chan __le32 queue_id6_max_bw; 282487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 282587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 2826bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 2827bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 2828bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 2829bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 283087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 283187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 2832bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2833bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2834bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2835bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 283687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 283787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 283887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 283987c374deSMichael Chan u8 queue_id6_tsa_assign; 284087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 284187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 284287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 284387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 284487c374deSMichael Chan u8 queue_id6_pri_lvl; 284587c374deSMichael Chan u8 queue_id6_bw_weight; 284687c374deSMichael Chan u8 queue_id7; 284787c374deSMichael Chan __le32 queue_id7_min_bw; 284887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 284987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 2850bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 2851bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 2852bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 2853bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 285487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 285587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 2856bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2857bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2858bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2859bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 286087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 286187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 286287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 286387c374deSMichael Chan __le32 queue_id7_max_bw; 286487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 286587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 2866bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 2867bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 2868bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 2869bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 287087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 287187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 2872bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2873bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2874bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2875bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 287687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 287787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 287887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 287987c374deSMichael Chan u8 queue_id7_tsa_assign; 288087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 288187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 288287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 288387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 288487c374deSMichael Chan u8 queue_id7_pri_lvl; 288587c374deSMichael Chan u8 queue_id7_bw_weight; 288687c374deSMichael Chan u8 unused_2; 288787c374deSMichael Chan u8 unused_3; 288887c374deSMichael Chan u8 unused_4; 288987c374deSMichael Chan u8 unused_5; 289087c374deSMichael Chan u8 valid; 289187c374deSMichael Chan }; 289287c374deSMichael Chan 2893c0c050c5SMichael Chan /* hwrm_queue_cos2bw_cfg */ 2894c0c050c5SMichael Chan /* Input (128 bytes) */ 2895c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_input { 2896c0c050c5SMichael Chan __le16 req_type; 2897c0c050c5SMichael Chan __le16 cmpl_ring; 2898c0c050c5SMichael Chan __le16 seq_id; 2899c0c050c5SMichael Chan __le16 target_id; 2900c0c050c5SMichael Chan __le64 resp_addr; 2901c0c050c5SMichael Chan __le32 flags; 2902c0c050c5SMichael Chan __le32 enables; 2903c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2904c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2905c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2906c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2907c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2908c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2909c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2910c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2911c0c050c5SMichael Chan __le16 port_id; 2912c0c050c5SMichael Chan u8 queue_id0; 2913c0c050c5SMichael Chan u8 unused_0; 2914c0c050c5SMichael Chan __le32 queue_id0_min_bw; 2915441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2916441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2917bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2918bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2919bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2920bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 2921441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2922441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2923bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2924bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2925bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2926bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2927441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2928441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2929441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2930c0c050c5SMichael Chan __le32 queue_id0_max_bw; 2931441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2932441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2933bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2934bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2935bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2936bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 2937441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2938441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2939bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2940bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2941bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2942bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2943441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2944441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2945441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2946c0c050c5SMichael Chan u8 queue_id0_tsa_assign; 2947441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2948441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2949441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2950441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2951c0c050c5SMichael Chan u8 queue_id0_pri_lvl; 2952c0c050c5SMichael Chan u8 queue_id0_bw_weight; 2953c0c050c5SMichael Chan u8 queue_id1; 2954c0c050c5SMichael Chan __le32 queue_id1_min_bw; 2955441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2956441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2957bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2958bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2959bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2960bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 2961441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2962441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2963bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2964bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2965bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2966bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2967441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2968441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2969441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2970c0c050c5SMichael Chan __le32 queue_id1_max_bw; 2971441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2972441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2973bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2974bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2975bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2976bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 2977441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2978441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2979bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2980bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2981bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2982bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2983441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2984441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2985441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2986c0c050c5SMichael Chan u8 queue_id1_tsa_assign; 2987441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2988441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2989441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2990441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2991c0c050c5SMichael Chan u8 queue_id1_pri_lvl; 2992c0c050c5SMichael Chan u8 queue_id1_bw_weight; 2993c0c050c5SMichael Chan u8 queue_id2; 2994c0c050c5SMichael Chan __le32 queue_id2_min_bw; 2995441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2996441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2997bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2998bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2999bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3000bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3001441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3002441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3003bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3004bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3005bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3006bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3007441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3008441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3009441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3010c0c050c5SMichael Chan __le32 queue_id2_max_bw; 3011441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3012441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3013bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3014bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3015bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3016bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3017441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3018441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3019bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3020bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3021bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3022bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3023441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3024441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3025441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3026c0c050c5SMichael Chan u8 queue_id2_tsa_assign; 3027441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3028441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3029441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3030441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3031c0c050c5SMichael Chan u8 queue_id2_pri_lvl; 3032c0c050c5SMichael Chan u8 queue_id2_bw_weight; 3033c0c050c5SMichael Chan u8 queue_id3; 3034c0c050c5SMichael Chan __le32 queue_id3_min_bw; 3035441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3036441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3037bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3038bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3039bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3040bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3041441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3042441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3043bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3044bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3045bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3046bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3047441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3048441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3049441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3050c0c050c5SMichael Chan __le32 queue_id3_max_bw; 3051441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3052441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3053bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3054bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3055bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3056bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3057441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3058441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3059bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3060bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3061bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3062bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3063441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3064441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3065441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3066c0c050c5SMichael Chan u8 queue_id3_tsa_assign; 3067441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3068441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3069441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3070441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3071c0c050c5SMichael Chan u8 queue_id3_pri_lvl; 3072c0c050c5SMichael Chan u8 queue_id3_bw_weight; 3073c0c050c5SMichael Chan u8 queue_id4; 3074c0c050c5SMichael Chan __le32 queue_id4_min_bw; 3075441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3076441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3077bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3078bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3079bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3080bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 3081441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3082441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3083bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3084bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3085bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3086bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3087441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3088441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3089441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3090c0c050c5SMichael Chan __le32 queue_id4_max_bw; 3091441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3092441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3093bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3094bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3095bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3096bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3097441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3098441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3099bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3100bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3101bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3102bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3103441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3104441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3105441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3106c0c050c5SMichael Chan u8 queue_id4_tsa_assign; 3107441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3108441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3109441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3110441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3111c0c050c5SMichael Chan u8 queue_id4_pri_lvl; 3112c0c050c5SMichael Chan u8 queue_id4_bw_weight; 3113c0c050c5SMichael Chan u8 queue_id5; 3114c0c050c5SMichael Chan __le32 queue_id5_min_bw; 3115441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3116441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3117bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3118bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3119bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3120bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3121441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3122441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3123bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3124bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3125bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3126bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3127441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3128441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3129441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3130c0c050c5SMichael Chan __le32 queue_id5_max_bw; 3131441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3132441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3133bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3134bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3135bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3136bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3137441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3138441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3139bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3140bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3141bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3142bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3143441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3144441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3145441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3146c0c050c5SMichael Chan u8 queue_id5_tsa_assign; 3147441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3148441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3149441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3150441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3151c0c050c5SMichael Chan u8 queue_id5_pri_lvl; 3152c0c050c5SMichael Chan u8 queue_id5_bw_weight; 3153c0c050c5SMichael Chan u8 queue_id6; 3154c0c050c5SMichael Chan __le32 queue_id6_min_bw; 3155441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3156441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3157bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3158bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3159bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3160bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3161441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3162441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3163bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3164bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3165bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3166bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3167441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3168441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3169441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3170c0c050c5SMichael Chan __le32 queue_id6_max_bw; 3171441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3172441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3173bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3174bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3175bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3176bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3177441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3178441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3179bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3180bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3181bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3182bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3183441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3184441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3185441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3186c0c050c5SMichael Chan u8 queue_id6_tsa_assign; 3187441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3188441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3189441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3190441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3191c0c050c5SMichael Chan u8 queue_id6_pri_lvl; 3192c0c050c5SMichael Chan u8 queue_id6_bw_weight; 3193c0c050c5SMichael Chan u8 queue_id7; 3194c0c050c5SMichael Chan __le32 queue_id7_min_bw; 3195441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3196441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3197bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3198bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3199bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3200bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3201441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3202441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3203bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3204bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3205bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3206bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3207441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3208441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3209441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3210c0c050c5SMichael Chan __le32 queue_id7_max_bw; 3211441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3212441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3213bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3214bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3215bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3216bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3217441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3218441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3219bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3220bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3221bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3222bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3223441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3224441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3225441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3226c0c050c5SMichael Chan u8 queue_id7_tsa_assign; 3227441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3228441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3229441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3230441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3231c0c050c5SMichael Chan u8 queue_id7_pri_lvl; 3232c0c050c5SMichael Chan u8 queue_id7_bw_weight; 3233c0c050c5SMichael Chan u8 unused_1[5]; 3234c0c050c5SMichael Chan }; 3235c0c050c5SMichael Chan 3236c0c050c5SMichael Chan /* Output (16 bytes) */ 3237c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_output { 3238c0c050c5SMichael Chan __le16 error_code; 3239c0c050c5SMichael Chan __le16 req_type; 3240c0c050c5SMichael Chan __le16 seq_id; 3241c0c050c5SMichael Chan __le16 resp_len; 3242c0c050c5SMichael Chan __le32 unused_0; 3243c0c050c5SMichael Chan u8 unused_1; 3244c0c050c5SMichael Chan u8 unused_2; 3245c0c050c5SMichael Chan u8 unused_3; 3246c0c050c5SMichael Chan u8 valid; 3247c0c050c5SMichael Chan }; 3248c0c050c5SMichael Chan 3249acb20054SMichael Chan /* hwrm_queue_dscp_qcaps */ 3250acb20054SMichael Chan /* Input (24 bytes) */ 3251acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_input { 3252acb20054SMichael Chan __le16 req_type; 3253acb20054SMichael Chan __le16 cmpl_ring; 3254acb20054SMichael Chan __le16 seq_id; 3255acb20054SMichael Chan __le16 target_id; 3256acb20054SMichael Chan __le64 resp_addr; 3257acb20054SMichael Chan u8 port_id; 3258acb20054SMichael Chan u8 unused_0[7]; 3259acb20054SMichael Chan }; 3260acb20054SMichael Chan 3261acb20054SMichael Chan /* Output (16 bytes) */ 3262acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_output { 3263acb20054SMichael Chan __le16 error_code; 3264acb20054SMichael Chan __le16 req_type; 3265acb20054SMichael Chan __le16 seq_id; 3266acb20054SMichael Chan __le16 resp_len; 3267acb20054SMichael Chan u8 num_dscp_bits; 3268acb20054SMichael Chan u8 unused_0; 3269acb20054SMichael Chan __le16 max_entries; 3270acb20054SMichael Chan u8 unused_1; 3271acb20054SMichael Chan u8 unused_2; 3272acb20054SMichael Chan u8 unused_3; 3273acb20054SMichael Chan u8 valid; 3274acb20054SMichael Chan }; 3275acb20054SMichael Chan 3276acb20054SMichael Chan /* hwrm_queue_dscp2pri_qcfg */ 3277acb20054SMichael Chan /* Input (32 bytes) */ 3278acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_input { 3279acb20054SMichael Chan __le16 req_type; 3280acb20054SMichael Chan __le16 cmpl_ring; 3281acb20054SMichael Chan __le16 seq_id; 3282acb20054SMichael Chan __le16 target_id; 3283acb20054SMichael Chan __le64 resp_addr; 3284acb20054SMichael Chan __le64 dest_data_addr; 3285acb20054SMichael Chan u8 port_id; 3286acb20054SMichael Chan u8 unused_0; 3287acb20054SMichael Chan __le16 dest_data_buffer_size; 3288acb20054SMichael Chan __le32 unused_1; 3289acb20054SMichael Chan }; 3290acb20054SMichael Chan 3291acb20054SMichael Chan /* Output (16 bytes) */ 3292acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_output { 3293acb20054SMichael Chan __le16 error_code; 3294acb20054SMichael Chan __le16 req_type; 3295acb20054SMichael Chan __le16 seq_id; 3296acb20054SMichael Chan __le16 resp_len; 3297acb20054SMichael Chan __le16 entry_cnt; 3298acb20054SMichael Chan u8 default_pri; 3299acb20054SMichael Chan u8 unused_0; 3300acb20054SMichael Chan u8 unused_1; 3301acb20054SMichael Chan u8 unused_2; 3302acb20054SMichael Chan u8 unused_3; 3303acb20054SMichael Chan u8 valid; 3304acb20054SMichael Chan }; 3305acb20054SMichael Chan 3306acb20054SMichael Chan /* hwrm_queue_dscp2pri_cfg */ 3307acb20054SMichael Chan /* Input (40 bytes) */ 3308acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_input { 3309acb20054SMichael Chan __le16 req_type; 3310acb20054SMichael Chan __le16 cmpl_ring; 3311acb20054SMichael Chan __le16 seq_id; 3312acb20054SMichael Chan __le16 target_id; 3313acb20054SMichael Chan __le64 resp_addr; 3314acb20054SMichael Chan __le64 src_data_addr; 3315acb20054SMichael Chan __le32 flags; 3316acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 3317acb20054SMichael Chan __le32 enables; 3318acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 3319acb20054SMichael Chan u8 port_id; 3320acb20054SMichael Chan u8 default_pri; 3321acb20054SMichael Chan __le16 entry_cnt; 3322acb20054SMichael Chan __le32 unused_0; 3323acb20054SMichael Chan }; 3324acb20054SMichael Chan 3325acb20054SMichael Chan /* Output (16 bytes) */ 3326acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_output { 3327acb20054SMichael Chan __le16 error_code; 3328acb20054SMichael Chan __le16 req_type; 3329acb20054SMichael Chan __le16 seq_id; 3330acb20054SMichael Chan __le16 resp_len; 3331acb20054SMichael Chan __le32 unused_0; 3332acb20054SMichael Chan u8 unused_1; 3333acb20054SMichael Chan u8 unused_2; 3334acb20054SMichael Chan u8 unused_3; 3335acb20054SMichael Chan u8 valid; 3336acb20054SMichael Chan }; 3337acb20054SMichael Chan 3338c0c050c5SMichael Chan /* hwrm_vnic_alloc */ 3339c0c050c5SMichael Chan /* Input (24 bytes) */ 3340c0c050c5SMichael Chan struct hwrm_vnic_alloc_input { 3341c0c050c5SMichael Chan __le16 req_type; 3342c0c050c5SMichael Chan __le16 cmpl_ring; 3343c0c050c5SMichael Chan __le16 seq_id; 3344c0c050c5SMichael Chan __le16 target_id; 3345c0c050c5SMichael Chan __le64 resp_addr; 3346c0c050c5SMichael Chan __le32 flags; 3347c0c050c5SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3348c0c050c5SMichael Chan __le32 unused_0; 3349c0c050c5SMichael Chan }; 3350c0c050c5SMichael Chan 3351c0c050c5SMichael Chan /* Output (16 bytes) */ 3352c0c050c5SMichael Chan struct hwrm_vnic_alloc_output { 3353c0c050c5SMichael Chan __le16 error_code; 3354c0c050c5SMichael Chan __le16 req_type; 3355c0c050c5SMichael Chan __le16 seq_id; 3356c0c050c5SMichael Chan __le16 resp_len; 3357c0c050c5SMichael Chan __le32 vnic_id; 3358c0c050c5SMichael Chan u8 unused_0; 3359c0c050c5SMichael Chan u8 unused_1; 3360c0c050c5SMichael Chan u8 unused_2; 3361c0c050c5SMichael Chan u8 valid; 3362c0c050c5SMichael Chan }; 3363c0c050c5SMichael Chan 3364c0c050c5SMichael Chan /* hwrm_vnic_free */ 3365c0c050c5SMichael Chan /* Input (24 bytes) */ 3366c0c050c5SMichael Chan struct hwrm_vnic_free_input { 3367c0c050c5SMichael Chan __le16 req_type; 3368c0c050c5SMichael Chan __le16 cmpl_ring; 3369c0c050c5SMichael Chan __le16 seq_id; 3370c0c050c5SMichael Chan __le16 target_id; 3371c0c050c5SMichael Chan __le64 resp_addr; 3372c0c050c5SMichael Chan __le32 vnic_id; 3373c0c050c5SMichael Chan __le32 unused_0; 3374c0c050c5SMichael Chan }; 3375c0c050c5SMichael Chan 3376c0c050c5SMichael Chan /* Output (16 bytes) */ 3377c0c050c5SMichael Chan struct hwrm_vnic_free_output { 3378c0c050c5SMichael Chan __le16 error_code; 3379c0c050c5SMichael Chan __le16 req_type; 3380c0c050c5SMichael Chan __le16 seq_id; 3381c0c050c5SMichael Chan __le16 resp_len; 3382c0c050c5SMichael Chan __le32 unused_0; 3383c0c050c5SMichael Chan u8 unused_1; 3384c0c050c5SMichael Chan u8 unused_2; 3385c0c050c5SMichael Chan u8 unused_3; 3386c0c050c5SMichael Chan u8 valid; 3387c0c050c5SMichael Chan }; 3388c0c050c5SMichael Chan 3389c0c050c5SMichael Chan /* hwrm_vnic_cfg */ 3390c0c050c5SMichael Chan /* Input (40 bytes) */ 3391c0c050c5SMichael Chan struct hwrm_vnic_cfg_input { 3392c0c050c5SMichael Chan __le16 req_type; 3393c0c050c5SMichael Chan __le16 cmpl_ring; 3394c0c050c5SMichael Chan __le16 seq_id; 3395c0c050c5SMichael Chan __le16 target_id; 3396c0c050c5SMichael Chan __le64 resp_addr; 3397c0c050c5SMichael Chan __le32 flags; 3398c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3399c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3400c193554eSMichael Chan #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 340111f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 340211f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3403441cabbbSMichael Chan #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3404c0c050c5SMichael Chan __le32 enables; 3405c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3406c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3407c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3408c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3409c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3410c0c050c5SMichael Chan __le16 vnic_id; 3411c0c050c5SMichael Chan __le16 dflt_ring_grp; 3412c0c050c5SMichael Chan __le16 rss_rule; 3413c0c050c5SMichael Chan __le16 cos_rule; 3414c0c050c5SMichael Chan __le16 lb_rule; 3415c0c050c5SMichael Chan __le16 mru; 3416c0c050c5SMichael Chan __le32 unused_0; 3417c0c050c5SMichael Chan }; 3418c0c050c5SMichael Chan 3419c0c050c5SMichael Chan /* Output (16 bytes) */ 3420c0c050c5SMichael Chan struct hwrm_vnic_cfg_output { 3421c0c050c5SMichael Chan __le16 error_code; 3422c0c050c5SMichael Chan __le16 req_type; 3423c0c050c5SMichael Chan __le16 seq_id; 3424c0c050c5SMichael Chan __le16 resp_len; 3425c0c050c5SMichael Chan __le32 unused_0; 3426c0c050c5SMichael Chan u8 unused_1; 3427c0c050c5SMichael Chan u8 unused_2; 3428c0c050c5SMichael Chan u8 unused_3; 3429c0c050c5SMichael Chan u8 valid; 3430c0c050c5SMichael Chan }; 3431c0c050c5SMichael Chan 34328fdefd63SMichael Chan /* hwrm_vnic_qcaps */ 34338fdefd63SMichael Chan /* Input (24 bytes) */ 34348fdefd63SMichael Chan struct hwrm_vnic_qcaps_input { 34358fdefd63SMichael Chan __le16 req_type; 34368fdefd63SMichael Chan __le16 cmpl_ring; 34378fdefd63SMichael Chan __le16 seq_id; 34388fdefd63SMichael Chan __le16 target_id; 34398fdefd63SMichael Chan __le64 resp_addr; 34408fdefd63SMichael Chan __le32 enables; 34418fdefd63SMichael Chan __le32 unused_0; 34428fdefd63SMichael Chan }; 34438fdefd63SMichael Chan 34448fdefd63SMichael Chan /* Output (24 bytes) */ 34458fdefd63SMichael Chan struct hwrm_vnic_qcaps_output { 34468fdefd63SMichael Chan __le16 error_code; 34478fdefd63SMichael Chan __le16 req_type; 34488fdefd63SMichael Chan __le16 seq_id; 34498fdefd63SMichael Chan __le16 resp_len; 34508fdefd63SMichael Chan __le16 mru; 34518fdefd63SMichael Chan u8 unused_0; 34528fdefd63SMichael Chan u8 unused_1; 34538fdefd63SMichael Chan __le32 flags; 3454bac9a7e0SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 34558fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 34568fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 34578fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 34588fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 34598fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 34608fdefd63SMichael Chan __le32 unused_2; 34618fdefd63SMichael Chan u8 unused_3; 34628fdefd63SMichael Chan u8 unused_4; 34638fdefd63SMichael Chan u8 unused_5; 34648fdefd63SMichael Chan u8 valid; 34658fdefd63SMichael Chan }; 34668fdefd63SMichael Chan 3467c0c050c5SMichael Chan /* hwrm_vnic_tpa_cfg */ 3468c0c050c5SMichael Chan /* Input (40 bytes) */ 3469c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_input { 3470c0c050c5SMichael Chan __le16 req_type; 3471c0c050c5SMichael Chan __le16 cmpl_ring; 3472c0c050c5SMichael Chan __le16 seq_id; 3473c0c050c5SMichael Chan __le16 target_id; 3474c0c050c5SMichael Chan __le64 resp_addr; 3475c0c050c5SMichael Chan __le32 flags; 3476c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3477c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3478c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3479c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3480c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3481c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3482c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3483c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3484c0c050c5SMichael Chan __le32 enables; 3485c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3486c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3487c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3488c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3489c0c050c5SMichael Chan __le16 vnic_id; 3490c0c050c5SMichael Chan __le16 max_agg_segs; 3491441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3492441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3493441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3494441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3495441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3496c0c050c5SMichael Chan __le16 max_aggs; 3497441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3498441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3499441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3500441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3501441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3502441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3503c0c050c5SMichael Chan u8 unused_0; 3504c0c050c5SMichael Chan u8 unused_1; 3505c0c050c5SMichael Chan __le32 max_agg_timer; 3506c0c050c5SMichael Chan __le32 min_agg_len; 3507c0c050c5SMichael Chan }; 3508c0c050c5SMichael Chan 3509c0c050c5SMichael Chan /* Output (16 bytes) */ 3510c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_output { 3511c0c050c5SMichael Chan __le16 error_code; 3512c0c050c5SMichael Chan __le16 req_type; 3513c0c050c5SMichael Chan __le16 seq_id; 3514c0c050c5SMichael Chan __le16 resp_len; 3515c0c050c5SMichael Chan __le32 unused_0; 3516c0c050c5SMichael Chan u8 unused_1; 3517c0c050c5SMichael Chan u8 unused_2; 3518c0c050c5SMichael Chan u8 unused_3; 3519c0c050c5SMichael Chan u8 valid; 3520c0c050c5SMichael Chan }; 3521c0c050c5SMichael Chan 3522c0c050c5SMichael Chan /* hwrm_vnic_rss_cfg */ 3523c0c050c5SMichael Chan /* Input (48 bytes) */ 3524c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_input { 3525c0c050c5SMichael Chan __le16 req_type; 3526c0c050c5SMichael Chan __le16 cmpl_ring; 3527c0c050c5SMichael Chan __le16 seq_id; 3528c0c050c5SMichael Chan __le16 target_id; 3529c0c050c5SMichael Chan __le64 resp_addr; 3530c0c050c5SMichael Chan __le32 hash_type; 3531c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3532c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3533c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3534c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3535c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3536c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3537c0c050c5SMichael Chan __le32 unused_0; 3538c0c050c5SMichael Chan __le64 ring_grp_tbl_addr; 3539c0c050c5SMichael Chan __le64 hash_key_tbl_addr; 3540c0c050c5SMichael Chan __le16 rss_ctx_idx; 3541c0c050c5SMichael Chan __le16 unused_1[3]; 3542c0c050c5SMichael Chan }; 3543c0c050c5SMichael Chan 3544c0c050c5SMichael Chan /* Output (16 bytes) */ 3545c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_output { 3546c0c050c5SMichael Chan __le16 error_code; 3547c0c050c5SMichael Chan __le16 req_type; 3548c0c050c5SMichael Chan __le16 seq_id; 3549c0c050c5SMichael Chan __le16 resp_len; 3550c0c050c5SMichael Chan __le32 unused_0; 3551c0c050c5SMichael Chan u8 unused_1; 3552c0c050c5SMichael Chan u8 unused_2; 3553c0c050c5SMichael Chan u8 unused_3; 3554c0c050c5SMichael Chan u8 valid; 3555c0c050c5SMichael Chan }; 3556c0c050c5SMichael Chan 3557c0c050c5SMichael Chan /* hwrm_vnic_plcmodes_cfg */ 3558c0c050c5SMichael Chan /* Input (40 bytes) */ 3559c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_input { 3560c0c050c5SMichael Chan __le16 req_type; 3561c0c050c5SMichael Chan __le16 cmpl_ring; 3562c0c050c5SMichael Chan __le16 seq_id; 3563c0c050c5SMichael Chan __le16 target_id; 3564c0c050c5SMichael Chan __le64 resp_addr; 3565c0c050c5SMichael Chan __le32 flags; 3566c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3567c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3568c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3569c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3570c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3571c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3572c0c050c5SMichael Chan __le32 enables; 3573c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3574c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3575c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3576c0c050c5SMichael Chan __le32 vnic_id; 3577c0c050c5SMichael Chan __le16 jumbo_thresh; 3578c0c050c5SMichael Chan __le16 hds_offset; 3579c0c050c5SMichael Chan __le16 hds_threshold; 3580c0c050c5SMichael Chan __le16 unused_0[3]; 3581c0c050c5SMichael Chan }; 3582c0c050c5SMichael Chan 3583c0c050c5SMichael Chan /* Output (16 bytes) */ 3584c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_output { 3585c0c050c5SMichael Chan __le16 error_code; 3586c0c050c5SMichael Chan __le16 req_type; 3587c0c050c5SMichael Chan __le16 seq_id; 3588c0c050c5SMichael Chan __le16 resp_len; 3589c0c050c5SMichael Chan __le32 unused_0; 3590c0c050c5SMichael Chan u8 unused_1; 3591c0c050c5SMichael Chan u8 unused_2; 3592c0c050c5SMichael Chan u8 unused_3; 3593c0c050c5SMichael Chan u8 valid; 3594c0c050c5SMichael Chan }; 3595c0c050c5SMichael Chan 3596c0c050c5SMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 3597c0c050c5SMichael Chan /* Input (16 bytes) */ 3598c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3599c0c050c5SMichael Chan __le16 req_type; 3600c0c050c5SMichael Chan __le16 cmpl_ring; 3601c0c050c5SMichael Chan __le16 seq_id; 3602c0c050c5SMichael Chan __le16 target_id; 3603c0c050c5SMichael Chan __le64 resp_addr; 3604c0c050c5SMichael Chan }; 3605c0c050c5SMichael Chan 3606c0c050c5SMichael Chan /* Output (16 bytes) */ 3607c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3608c0c050c5SMichael Chan __le16 error_code; 3609c0c050c5SMichael Chan __le16 req_type; 3610c0c050c5SMichael Chan __le16 seq_id; 3611c0c050c5SMichael Chan __le16 resp_len; 3612c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 3613c0c050c5SMichael Chan u8 unused_0; 3614c0c050c5SMichael Chan u8 unused_1; 3615c0c050c5SMichael Chan u8 unused_2; 3616c0c050c5SMichael Chan u8 unused_3; 3617c0c050c5SMichael Chan u8 unused_4; 3618c0c050c5SMichael Chan u8 valid; 3619c0c050c5SMichael Chan }; 3620c0c050c5SMichael Chan 3621c0c050c5SMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free */ 3622c0c050c5SMichael Chan /* Input (24 bytes) */ 3623c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3624c0c050c5SMichael Chan __le16 req_type; 3625c0c050c5SMichael Chan __le16 cmpl_ring; 3626c0c050c5SMichael Chan __le16 seq_id; 3627c0c050c5SMichael Chan __le16 target_id; 3628c0c050c5SMichael Chan __le64 resp_addr; 3629c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 3630c0c050c5SMichael Chan __le16 unused_0[3]; 3631c0c050c5SMichael Chan }; 3632c0c050c5SMichael Chan 3633c0c050c5SMichael Chan /* Output (16 bytes) */ 3634c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3635c0c050c5SMichael Chan __le16 error_code; 3636c0c050c5SMichael Chan __le16 req_type; 3637c0c050c5SMichael Chan __le16 seq_id; 3638c0c050c5SMichael Chan __le16 resp_len; 3639c0c050c5SMichael Chan __le32 unused_0; 3640c0c050c5SMichael Chan u8 unused_1; 3641c0c050c5SMichael Chan u8 unused_2; 3642c0c050c5SMichael Chan u8 unused_3; 3643c0c050c5SMichael Chan u8 valid; 3644c0c050c5SMichael Chan }; 3645c0c050c5SMichael Chan 3646c0c050c5SMichael Chan /* hwrm_ring_alloc */ 3647c0c050c5SMichael Chan /* Input (80 bytes) */ 3648c0c050c5SMichael Chan struct hwrm_ring_alloc_input { 3649c0c050c5SMichael Chan __le16 req_type; 3650c0c050c5SMichael Chan __le16 cmpl_ring; 3651c0c050c5SMichael Chan __le16 seq_id; 3652c0c050c5SMichael Chan __le16 target_id; 3653c0c050c5SMichael Chan __le64 resp_addr; 3654c0c050c5SMichael Chan __le32 enables; 3655c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 3656441cabbbSMichael Chan #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3657c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 3658c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3659c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 3660c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3661c0c050c5SMichael Chan u8 ring_type; 3662bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3663441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3664441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3665bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3666c0c050c5SMichael Chan u8 unused_0; 3667c0c050c5SMichael Chan __le16 unused_1; 3668c0c050c5SMichael Chan __le64 page_tbl_addr; 3669c0c050c5SMichael Chan __le32 fbo; 3670c0c050c5SMichael Chan u8 page_size; 3671c0c050c5SMichael Chan u8 page_tbl_depth; 3672c0c050c5SMichael Chan u8 unused_2; 3673c0c050c5SMichael Chan u8 unused_3; 3674c0c050c5SMichael Chan __le32 length; 3675c0c050c5SMichael Chan __le16 logical_id; 3676c0c050c5SMichael Chan __le16 cmpl_ring_id; 3677c0c050c5SMichael Chan __le16 queue_id; 3678c0c050c5SMichael Chan u8 unused_4; 3679c0c050c5SMichael Chan u8 unused_5; 3680c193554eSMichael Chan __le32 reserved1; 3681441cabbbSMichael Chan __le16 ring_arb_cfg; 3682441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3683441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3684441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP (0x1UL << 0) 3685441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ (0x2UL << 0) 3686441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3687441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3688441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3689441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3690441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3691c0c050c5SMichael Chan u8 unused_6; 3692c0c050c5SMichael Chan u8 unused_7; 3693c193554eSMichael Chan __le32 reserved3; 3694c0c050c5SMichael Chan __le32 stat_ctx_id; 3695c193554eSMichael Chan __le32 reserved4; 3696c0c050c5SMichael Chan __le32 max_bw; 3697441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3698441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3699bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 3700bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 3701bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 3702bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 3703441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3704441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 3705bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3706bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3707bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3708bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3709441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3710441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3711441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 3712c0c050c5SMichael Chan u8 int_mode; 3713441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 3714441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 3715441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 3716441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 3717c0c050c5SMichael Chan u8 unused_8[3]; 3718c0c050c5SMichael Chan }; 3719c0c050c5SMichael Chan 3720c0c050c5SMichael Chan /* Output (16 bytes) */ 3721c0c050c5SMichael Chan struct hwrm_ring_alloc_output { 3722c0c050c5SMichael Chan __le16 error_code; 3723c0c050c5SMichael Chan __le16 req_type; 3724c0c050c5SMichael Chan __le16 seq_id; 3725c0c050c5SMichael Chan __le16 resp_len; 3726c0c050c5SMichael Chan __le16 ring_id; 3727c0c050c5SMichael Chan __le16 logical_ring_id; 3728c0c050c5SMichael Chan u8 unused_0; 3729c0c050c5SMichael Chan u8 unused_1; 3730c0c050c5SMichael Chan u8 unused_2; 3731c0c050c5SMichael Chan u8 valid; 3732c0c050c5SMichael Chan }; 3733c0c050c5SMichael Chan 3734c0c050c5SMichael Chan /* hwrm_ring_free */ 3735c0c050c5SMichael Chan /* Input (24 bytes) */ 3736c0c050c5SMichael Chan struct hwrm_ring_free_input { 3737c0c050c5SMichael Chan __le16 req_type; 3738c0c050c5SMichael Chan __le16 cmpl_ring; 3739c0c050c5SMichael Chan __le16 seq_id; 3740c0c050c5SMichael Chan __le16 target_id; 3741c0c050c5SMichael Chan __le64 resp_addr; 3742c0c050c5SMichael Chan u8 ring_type; 3743bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 3744441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 3745441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 3746bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3747c0c050c5SMichael Chan u8 unused_0; 3748c0c050c5SMichael Chan __le16 ring_id; 3749c0c050c5SMichael Chan __le32 unused_1; 3750c0c050c5SMichael Chan }; 3751c0c050c5SMichael Chan 3752c0c050c5SMichael Chan /* Output (16 bytes) */ 3753c0c050c5SMichael Chan struct hwrm_ring_free_output { 3754c0c050c5SMichael Chan __le16 error_code; 3755c0c050c5SMichael Chan __le16 req_type; 3756c0c050c5SMichael Chan __le16 seq_id; 3757c0c050c5SMichael Chan __le16 resp_len; 3758c0c050c5SMichael Chan __le32 unused_0; 3759c0c050c5SMichael Chan u8 unused_1; 3760c0c050c5SMichael Chan u8 unused_2; 3761c0c050c5SMichael Chan u8 unused_3; 3762c0c050c5SMichael Chan u8 valid; 3763c0c050c5SMichael Chan }; 3764c0c050c5SMichael Chan 3765c0c050c5SMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params */ 3766c0c050c5SMichael Chan /* Input (24 bytes) */ 3767c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_input { 3768c0c050c5SMichael Chan __le16 req_type; 3769c0c050c5SMichael Chan __le16 cmpl_ring; 3770c0c050c5SMichael Chan __le16 seq_id; 3771c0c050c5SMichael Chan __le16 target_id; 3772c0c050c5SMichael Chan __le64 resp_addr; 3773c0c050c5SMichael Chan __le16 ring_id; 3774c0c050c5SMichael Chan __le16 unused_0[3]; 3775c0c050c5SMichael Chan }; 3776c0c050c5SMichael Chan 3777c0c050c5SMichael Chan /* Output (32 bytes) */ 3778c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_output { 3779c0c050c5SMichael Chan __le16 error_code; 3780c0c050c5SMichael Chan __le16 req_type; 3781c0c050c5SMichael Chan __le16 seq_id; 3782c0c050c5SMichael Chan __le16 resp_len; 3783c0c050c5SMichael Chan __le16 flags; 3784c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 3785c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 3786c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 3787c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 3788c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 3789c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 3790c0c050c5SMichael Chan __le16 int_lat_tmr_min; 3791c0c050c5SMichael Chan __le16 int_lat_tmr_max; 3792c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 3793c0c050c5SMichael Chan __le32 unused_0; 3794c0c050c5SMichael Chan u8 unused_1; 3795c0c050c5SMichael Chan u8 unused_2; 3796c0c050c5SMichael Chan u8 unused_3; 3797c0c050c5SMichael Chan u8 valid; 3798c0c050c5SMichael Chan }; 3799c0c050c5SMichael Chan 3800c0c050c5SMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 3801c0c050c5SMichael Chan /* Input (40 bytes) */ 3802c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 3803c0c050c5SMichael Chan __le16 req_type; 3804c0c050c5SMichael Chan __le16 cmpl_ring; 3805c0c050c5SMichael Chan __le16 seq_id; 3806c0c050c5SMichael Chan __le16 target_id; 3807c0c050c5SMichael Chan __le64 resp_addr; 3808c0c050c5SMichael Chan __le16 ring_id; 3809c0c050c5SMichael Chan __le16 flags; 3810c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 3811c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 3812c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 3813c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 3814c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 3815c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 3816c0c050c5SMichael Chan __le16 int_lat_tmr_min; 3817c0c050c5SMichael Chan __le16 int_lat_tmr_max; 3818c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 3819c0c050c5SMichael Chan __le16 unused_0[3]; 3820c0c050c5SMichael Chan }; 3821c0c050c5SMichael Chan 3822c0c050c5SMichael Chan /* Output (16 bytes) */ 3823c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 3824c0c050c5SMichael Chan __le16 error_code; 3825c0c050c5SMichael Chan __le16 req_type; 3826c0c050c5SMichael Chan __le16 seq_id; 3827c0c050c5SMichael Chan __le16 resp_len; 3828c0c050c5SMichael Chan __le32 unused_0; 3829c0c050c5SMichael Chan u8 unused_1; 3830c0c050c5SMichael Chan u8 unused_2; 3831c0c050c5SMichael Chan u8 unused_3; 3832c0c050c5SMichael Chan u8 valid; 3833c0c050c5SMichael Chan }; 3834c0c050c5SMichael Chan 3835c0c050c5SMichael Chan /* hwrm_ring_reset */ 3836c0c050c5SMichael Chan /* Input (24 bytes) */ 3837c0c050c5SMichael Chan struct hwrm_ring_reset_input { 3838c0c050c5SMichael Chan __le16 req_type; 3839c0c050c5SMichael Chan __le16 cmpl_ring; 3840c0c050c5SMichael Chan __le16 seq_id; 3841c0c050c5SMichael Chan __le16 target_id; 3842c0c050c5SMichael Chan __le64 resp_addr; 3843c0c050c5SMichael Chan u8 ring_type; 3844bac9a7e0SMichael Chan #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 3845441cabbbSMichael Chan #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 3846441cabbbSMichael Chan #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 3847bac9a7e0SMichael Chan #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3848c0c050c5SMichael Chan u8 unused_0; 3849c0c050c5SMichael Chan __le16 ring_id; 3850c0c050c5SMichael Chan __le32 unused_1; 3851c0c050c5SMichael Chan }; 3852c0c050c5SMichael Chan 3853c0c050c5SMichael Chan /* Output (16 bytes) */ 3854c0c050c5SMichael Chan struct hwrm_ring_reset_output { 3855c0c050c5SMichael Chan __le16 error_code; 3856c0c050c5SMichael Chan __le16 req_type; 3857c0c050c5SMichael Chan __le16 seq_id; 3858c0c050c5SMichael Chan __le16 resp_len; 3859c0c050c5SMichael Chan __le32 unused_0; 3860c0c050c5SMichael Chan u8 unused_1; 3861c0c050c5SMichael Chan u8 unused_2; 3862c0c050c5SMichael Chan u8 unused_3; 3863c0c050c5SMichael Chan u8 valid; 3864c0c050c5SMichael Chan }; 3865c0c050c5SMichael Chan 3866c0c050c5SMichael Chan /* hwrm_ring_grp_alloc */ 3867c0c050c5SMichael Chan /* Input (24 bytes) */ 3868c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_input { 3869c0c050c5SMichael Chan __le16 req_type; 3870c0c050c5SMichael Chan __le16 cmpl_ring; 3871c0c050c5SMichael Chan __le16 seq_id; 3872c0c050c5SMichael Chan __le16 target_id; 3873c0c050c5SMichael Chan __le64 resp_addr; 3874c0c050c5SMichael Chan __le16 cr; 3875c0c050c5SMichael Chan __le16 rr; 3876c0c050c5SMichael Chan __le16 ar; 3877c0c050c5SMichael Chan __le16 sc; 3878c0c050c5SMichael Chan }; 3879c0c050c5SMichael Chan 3880c0c050c5SMichael Chan /* Output (16 bytes) */ 3881c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_output { 3882c0c050c5SMichael Chan __le16 error_code; 3883c0c050c5SMichael Chan __le16 req_type; 3884c0c050c5SMichael Chan __le16 seq_id; 3885c0c050c5SMichael Chan __le16 resp_len; 3886c0c050c5SMichael Chan __le32 ring_group_id; 3887c0c050c5SMichael Chan u8 unused_0; 3888c0c050c5SMichael Chan u8 unused_1; 3889c0c050c5SMichael Chan u8 unused_2; 3890c0c050c5SMichael Chan u8 valid; 3891c0c050c5SMichael Chan }; 3892c0c050c5SMichael Chan 3893c0c050c5SMichael Chan /* hwrm_ring_grp_free */ 3894c0c050c5SMichael Chan /* Input (24 bytes) */ 3895c0c050c5SMichael Chan struct hwrm_ring_grp_free_input { 3896c0c050c5SMichael Chan __le16 req_type; 3897c0c050c5SMichael Chan __le16 cmpl_ring; 3898c0c050c5SMichael Chan __le16 seq_id; 3899c0c050c5SMichael Chan __le16 target_id; 3900c0c050c5SMichael Chan __le64 resp_addr; 3901c0c050c5SMichael Chan __le32 ring_group_id; 3902c0c050c5SMichael Chan __le32 unused_0; 3903c0c050c5SMichael Chan }; 3904c0c050c5SMichael Chan 3905c0c050c5SMichael Chan /* Output (16 bytes) */ 3906c0c050c5SMichael Chan struct hwrm_ring_grp_free_output { 3907c0c050c5SMichael Chan __le16 error_code; 3908c0c050c5SMichael Chan __le16 req_type; 3909c0c050c5SMichael Chan __le16 seq_id; 3910c0c050c5SMichael Chan __le16 resp_len; 3911c0c050c5SMichael Chan __le32 unused_0; 3912c0c050c5SMichael Chan u8 unused_1; 3913c0c050c5SMichael Chan u8 unused_2; 3914c0c050c5SMichael Chan u8 unused_3; 3915c0c050c5SMichael Chan u8 valid; 3916c0c050c5SMichael Chan }; 3917c0c050c5SMichael Chan 3918c0c050c5SMichael Chan /* hwrm_cfa_l2_filter_alloc */ 3919c0c050c5SMichael Chan /* Input (96 bytes) */ 3920c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_input { 3921c0c050c5SMichael Chan __le16 req_type; 3922c0c050c5SMichael Chan __le16 cmpl_ring; 3923c0c050c5SMichael Chan __le16 seq_id; 3924c0c050c5SMichael Chan __le16 target_id; 3925c0c050c5SMichael Chan __le64 resp_addr; 3926c0c050c5SMichael Chan __le32 flags; 3927c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3928c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3929c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 393011f15ed3SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3931c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3932c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3933c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3934c0c050c5SMichael Chan __le32 enables; 3935c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3936c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3937c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3938c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3939c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3940c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3941c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3942c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3943c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3944c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3945c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3946c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3947c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3948c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3949c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3950c193554eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3951c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3952c0c050c5SMichael Chan u8 l2_addr[6]; 3953c0c050c5SMichael Chan u8 unused_0; 3954c0c050c5SMichael Chan u8 unused_1; 3955c0c050c5SMichael Chan u8 l2_addr_mask[6]; 3956c0c050c5SMichael Chan __le16 l2_ovlan; 3957c0c050c5SMichael Chan __le16 l2_ovlan_mask; 3958c0c050c5SMichael Chan __le16 l2_ivlan; 3959c0c050c5SMichael Chan __le16 l2_ivlan_mask; 3960c0c050c5SMichael Chan u8 unused_2; 3961c0c050c5SMichael Chan u8 unused_3; 3962c0c050c5SMichael Chan u8 t_l2_addr[6]; 3963c0c050c5SMichael Chan u8 unused_4; 3964c0c050c5SMichael Chan u8 unused_5; 3965c0c050c5SMichael Chan u8 t_l2_addr_mask[6]; 3966c0c050c5SMichael Chan __le16 t_l2_ovlan; 3967c0c050c5SMichael Chan __le16 t_l2_ovlan_mask; 3968c0c050c5SMichael Chan __le16 t_l2_ivlan; 3969c0c050c5SMichael Chan __le16 t_l2_ivlan_mask; 3970c0c050c5SMichael Chan u8 src_type; 3971441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 3972441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 3973441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 3974441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 3975441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 3976441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 3977441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 3978441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 3979c0c050c5SMichael Chan u8 unused_6; 3980c0c050c5SMichael Chan __le32 src_id; 3981c0c050c5SMichael Chan u8 tunnel_type; 3982441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 3983441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 3984441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 3985441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 3986441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 3987441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 3988441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 3989441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 3990441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 3991441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 3992c0c050c5SMichael Chan u8 unused_7; 3993c193554eSMichael Chan __le16 dst_id; 3994c0c050c5SMichael Chan __le16 mirror_vnic_id; 3995c0c050c5SMichael Chan u8 pri_hint; 3996441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 3997441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 3998441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 3999441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4000441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4001c0c050c5SMichael Chan u8 unused_8; 4002c0c050c5SMichael Chan __le32 unused_9; 4003c0c050c5SMichael Chan __le64 l2_filter_id_hint; 4004c0c050c5SMichael Chan }; 4005c0c050c5SMichael Chan 4006c0c050c5SMichael Chan /* Output (24 bytes) */ 4007c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_output { 4008c0c050c5SMichael Chan __le16 error_code; 4009c0c050c5SMichael Chan __le16 req_type; 4010c0c050c5SMichael Chan __le16 seq_id; 4011c0c050c5SMichael Chan __le16 resp_len; 4012c0c050c5SMichael Chan __le64 l2_filter_id; 4013c0c050c5SMichael Chan __le32 flow_id; 4014c0c050c5SMichael Chan u8 unused_0; 4015c0c050c5SMichael Chan u8 unused_1; 4016c0c050c5SMichael Chan u8 unused_2; 4017c0c050c5SMichael Chan u8 valid; 4018c0c050c5SMichael Chan }; 4019c0c050c5SMichael Chan 4020c0c050c5SMichael Chan /* hwrm_cfa_l2_filter_free */ 4021c0c050c5SMichael Chan /* Input (24 bytes) */ 4022c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_input { 4023c0c050c5SMichael Chan __le16 req_type; 4024c0c050c5SMichael Chan __le16 cmpl_ring; 4025c0c050c5SMichael Chan __le16 seq_id; 4026c0c050c5SMichael Chan __le16 target_id; 4027c0c050c5SMichael Chan __le64 resp_addr; 4028c0c050c5SMichael Chan __le64 l2_filter_id; 4029c0c050c5SMichael Chan }; 4030c0c050c5SMichael Chan 4031c0c050c5SMichael Chan /* Output (16 bytes) */ 4032c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_output { 4033c0c050c5SMichael Chan __le16 error_code; 4034c0c050c5SMichael Chan __le16 req_type; 4035c0c050c5SMichael Chan __le16 seq_id; 4036c0c050c5SMichael Chan __le16 resp_len; 4037c0c050c5SMichael Chan __le32 unused_0; 4038c0c050c5SMichael Chan u8 unused_1; 4039c0c050c5SMichael Chan u8 unused_2; 4040c0c050c5SMichael Chan u8 unused_3; 4041c0c050c5SMichael Chan u8 valid; 4042c0c050c5SMichael Chan }; 4043c0c050c5SMichael Chan 4044c0c050c5SMichael Chan /* hwrm_cfa_l2_filter_cfg */ 4045c0c050c5SMichael Chan /* Input (40 bytes) */ 4046c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_input { 4047c0c050c5SMichael Chan __le16 req_type; 4048c0c050c5SMichael Chan __le16 cmpl_ring; 4049c0c050c5SMichael Chan __le16 seq_id; 4050c0c050c5SMichael Chan __le16 target_id; 4051c0c050c5SMichael Chan __le64 resp_addr; 4052c0c050c5SMichael Chan __le32 flags; 4053c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 4054c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 4055c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 405611f15ed3SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 4057c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 4058c0c050c5SMichael Chan __le32 enables; 4059c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 4060c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4061c0c050c5SMichael Chan __le64 l2_filter_id; 4062c193554eSMichael Chan __le32 dst_id; 4063c193554eSMichael Chan __le32 new_mirror_vnic_id; 4064c0c050c5SMichael Chan }; 4065c0c050c5SMichael Chan 4066c0c050c5SMichael Chan /* Output (16 bytes) */ 4067c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_output { 4068c0c050c5SMichael Chan __le16 error_code; 4069c0c050c5SMichael Chan __le16 req_type; 4070c0c050c5SMichael Chan __le16 seq_id; 4071c0c050c5SMichael Chan __le16 resp_len; 4072c0c050c5SMichael Chan __le32 unused_0; 4073c0c050c5SMichael Chan u8 unused_1; 4074c0c050c5SMichael Chan u8 unused_2; 4075c0c050c5SMichael Chan u8 unused_3; 4076c0c050c5SMichael Chan u8 valid; 4077c0c050c5SMichael Chan }; 4078c0c050c5SMichael Chan 4079c0c050c5SMichael Chan /* hwrm_cfa_l2_set_rx_mask */ 4080a58a3e68SMichael Chan /* Input (56 bytes) */ 4081c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_input { 4082c0c050c5SMichael Chan __le16 req_type; 4083c0c050c5SMichael Chan __le16 cmpl_ring; 4084c0c050c5SMichael Chan __le16 seq_id; 4085c0c050c5SMichael Chan __le16 target_id; 4086c0c050c5SMichael Chan __le64 resp_addr; 4087c193554eSMichael Chan __le32 vnic_id; 4088c0c050c5SMichael Chan __le32 mask; 4089c193554eSMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 4090c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 4091c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 4092c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 4093c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 4094c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 4095a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 4096a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 4097a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 4098c0c050c5SMichael Chan __le64 mc_tbl_addr; 4099c0c050c5SMichael Chan __le32 num_mc_entries; 4100c0c050c5SMichael Chan __le32 unused_0; 4101a58a3e68SMichael Chan __le64 vlan_tag_tbl_addr; 4102a58a3e68SMichael Chan __le32 num_vlan_tags; 4103a58a3e68SMichael Chan __le32 unused_1; 4104c0c050c5SMichael Chan }; 4105c0c050c5SMichael Chan 4106c0c050c5SMichael Chan /* Output (16 bytes) */ 4107c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_output { 4108c0c050c5SMichael Chan __le16 error_code; 4109c0c050c5SMichael Chan __le16 req_type; 4110c0c050c5SMichael Chan __le16 seq_id; 4111c0c050c5SMichael Chan __le16 resp_len; 4112c0c050c5SMichael Chan __le32 unused_0; 4113c0c050c5SMichael Chan u8 unused_1; 4114c0c050c5SMichael Chan u8 unused_2; 4115c0c050c5SMichael Chan u8 unused_3; 4116c0c050c5SMichael Chan u8 valid; 4117c0c050c5SMichael Chan }; 4118c0c050c5SMichael Chan 4119c0c050c5SMichael Chan /* hwrm_cfa_tunnel_filter_alloc */ 4120c0c050c5SMichael Chan /* Input (88 bytes) */ 4121c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_input { 4122c0c050c5SMichael Chan __le16 req_type; 4123c0c050c5SMichael Chan __le16 cmpl_ring; 4124c0c050c5SMichael Chan __le16 seq_id; 4125c0c050c5SMichael Chan __le16 target_id; 4126c0c050c5SMichael Chan __le64 resp_addr; 4127c0c050c5SMichael Chan __le32 flags; 4128c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4129c0c050c5SMichael Chan __le32 enables; 4130c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4131c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 4132c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 4133c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 4134c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 4135c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 4136c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 4137c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 4138c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 4139c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 4140c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 4141c0c050c5SMichael Chan __le64 l2_filter_id; 4142c0c050c5SMichael Chan u8 l2_addr[6]; 4143c0c050c5SMichael Chan __le16 l2_ivlan; 4144c0c050c5SMichael Chan __le32 l3_addr[4]; 4145c0c050c5SMichael Chan __le32 t_l3_addr[4]; 4146c0c050c5SMichael Chan u8 l3_addr_type; 4147c0c050c5SMichael Chan u8 t_l3_addr_type; 4148c0c050c5SMichael Chan u8 tunnel_type; 4149441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4150441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4151441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4152441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4153441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4154441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4155441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4156441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4157441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4158441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4159c0c050c5SMichael Chan u8 unused_0; 4160c0c050c5SMichael Chan __le32 vni; 4161c0c050c5SMichael Chan __le32 dst_vnic_id; 4162c0c050c5SMichael Chan __le32 mirror_vnic_id; 4163c0c050c5SMichael Chan }; 4164c0c050c5SMichael Chan 4165c0c050c5SMichael Chan /* Output (24 bytes) */ 4166c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_output { 4167c0c050c5SMichael Chan __le16 error_code; 4168c0c050c5SMichael Chan __le16 req_type; 4169c0c050c5SMichael Chan __le16 seq_id; 4170c0c050c5SMichael Chan __le16 resp_len; 4171c0c050c5SMichael Chan __le64 tunnel_filter_id; 4172c0c050c5SMichael Chan __le32 flow_id; 4173c0c050c5SMichael Chan u8 unused_0; 4174c0c050c5SMichael Chan u8 unused_1; 4175c0c050c5SMichael Chan u8 unused_2; 4176c0c050c5SMichael Chan u8 valid; 4177c0c050c5SMichael Chan }; 4178c0c050c5SMichael Chan 4179c0c050c5SMichael Chan /* hwrm_cfa_tunnel_filter_free */ 4180c0c050c5SMichael Chan /* Input (24 bytes) */ 4181c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_input { 4182c0c050c5SMichael Chan __le16 req_type; 4183c0c050c5SMichael Chan __le16 cmpl_ring; 4184c0c050c5SMichael Chan __le16 seq_id; 4185c0c050c5SMichael Chan __le16 target_id; 4186c0c050c5SMichael Chan __le64 resp_addr; 4187c0c050c5SMichael Chan __le64 tunnel_filter_id; 4188c0c050c5SMichael Chan }; 4189c0c050c5SMichael Chan 4190c0c050c5SMichael Chan /* Output (16 bytes) */ 4191c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_output { 4192c0c050c5SMichael Chan __le16 error_code; 4193c0c050c5SMichael Chan __le16 req_type; 4194c0c050c5SMichael Chan __le16 seq_id; 4195c0c050c5SMichael Chan __le16 resp_len; 4196c0c050c5SMichael Chan __le32 unused_0; 4197c0c050c5SMichael Chan u8 unused_1; 4198c0c050c5SMichael Chan u8 unused_2; 4199c0c050c5SMichael Chan u8 unused_3; 4200c0c050c5SMichael Chan u8 valid; 4201c0c050c5SMichael Chan }; 4202c0c050c5SMichael Chan 4203c0c050c5SMichael Chan /* hwrm_cfa_encap_record_alloc */ 4204c0c050c5SMichael Chan /* Input (32 bytes) */ 4205c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_input { 4206c0c050c5SMichael Chan __le16 req_type; 4207c0c050c5SMichael Chan __le16 cmpl_ring; 4208c0c050c5SMichael Chan __le16 seq_id; 4209c0c050c5SMichael Chan __le16 target_id; 4210c0c050c5SMichael Chan __le64 resp_addr; 4211c0c050c5SMichael Chan __le32 flags; 4212c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4213c0c050c5SMichael Chan u8 encap_type; 4214441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4215441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4216441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4217441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4218441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4219441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4220441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4221441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4222c0c050c5SMichael Chan u8 unused_0; 4223c0c050c5SMichael Chan __le16 unused_1; 4224acb20054SMichael Chan __le32 encap_data[20]; 4225c0c050c5SMichael Chan }; 4226c0c050c5SMichael Chan 4227c193554eSMichael Chan /* Output (16 bytes) */ 4228c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_output { 4229c0c050c5SMichael Chan __le16 error_code; 4230c0c050c5SMichael Chan __le16 req_type; 4231c0c050c5SMichael Chan __le16 seq_id; 4232c0c050c5SMichael Chan __le16 resp_len; 4233c193554eSMichael Chan __le32 encap_record_id; 4234c193554eSMichael Chan u8 unused_0; 4235c0c050c5SMichael Chan u8 unused_1; 4236c0c050c5SMichael Chan u8 unused_2; 4237c0c050c5SMichael Chan u8 valid; 4238c0c050c5SMichael Chan }; 4239c0c050c5SMichael Chan 4240c0c050c5SMichael Chan /* hwrm_cfa_encap_record_free */ 4241c0c050c5SMichael Chan /* Input (24 bytes) */ 4242c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_input { 4243c0c050c5SMichael Chan __le16 req_type; 4244c0c050c5SMichael Chan __le16 cmpl_ring; 4245c0c050c5SMichael Chan __le16 seq_id; 4246c0c050c5SMichael Chan __le16 target_id; 4247c0c050c5SMichael Chan __le64 resp_addr; 4248c193554eSMichael Chan __le32 encap_record_id; 4249c193554eSMichael Chan __le32 unused_0; 4250c0c050c5SMichael Chan }; 4251c0c050c5SMichael Chan 4252c0c050c5SMichael Chan /* Output (16 bytes) */ 4253c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_output { 4254c0c050c5SMichael Chan __le16 error_code; 4255c0c050c5SMichael Chan __le16 req_type; 4256c0c050c5SMichael Chan __le16 seq_id; 4257c0c050c5SMichael Chan __le16 resp_len; 4258c0c050c5SMichael Chan __le32 unused_0; 4259c0c050c5SMichael Chan u8 unused_1; 4260c0c050c5SMichael Chan u8 unused_2; 4261c0c050c5SMichael Chan u8 unused_3; 4262c0c050c5SMichael Chan u8 valid; 4263c0c050c5SMichael Chan }; 4264c0c050c5SMichael Chan 4265c0c050c5SMichael Chan /* hwrm_cfa_ntuple_filter_alloc */ 4266c0c050c5SMichael Chan /* Input (128 bytes) */ 4267c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_input { 4268c0c050c5SMichael Chan __le16 req_type; 4269c0c050c5SMichael Chan __le16 cmpl_ring; 4270c0c050c5SMichael Chan __le16 seq_id; 4271c0c050c5SMichael Chan __le16 target_id; 4272c0c050c5SMichael Chan __le64 resp_addr; 4273c0c050c5SMichael Chan __le32 flags; 4274c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4275c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4276bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4277c0c050c5SMichael Chan __le32 enables; 4278c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4279c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4280c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4281c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4282c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4283c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4284c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4285c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4286c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4287c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4288c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4289c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4290c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4291c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4292c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4293c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4294c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4295c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4296c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4297c0c050c5SMichael Chan __le64 l2_filter_id; 4298c0c050c5SMichael Chan u8 src_macaddr[6]; 4299c0c050c5SMichael Chan __be16 ethertype; 4300c193554eSMichael Chan u8 ip_addr_type; 4301441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4302441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4303441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4304c0c050c5SMichael Chan u8 ip_protocol; 4305441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4306acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4307acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4308c193554eSMichael Chan __le16 dst_id; 4309c0c050c5SMichael Chan __le16 mirror_vnic_id; 4310c0c050c5SMichael Chan u8 tunnel_type; 4311441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4312441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4313441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4314441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4315441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4316441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4317441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4318441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4319441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4320441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4321c0c050c5SMichael Chan u8 pri_hint; 4322441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4323441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4324441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4325441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4326441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4327c0c050c5SMichael Chan __be32 src_ipaddr[4]; 4328c0c050c5SMichael Chan __be32 src_ipaddr_mask[4]; 4329c0c050c5SMichael Chan __be32 dst_ipaddr[4]; 4330c0c050c5SMichael Chan __be32 dst_ipaddr_mask[4]; 4331c0c050c5SMichael Chan __be16 src_port; 4332c0c050c5SMichael Chan __be16 src_port_mask; 4333c0c050c5SMichael Chan __be16 dst_port; 4334c0c050c5SMichael Chan __be16 dst_port_mask; 4335c0c050c5SMichael Chan __le64 ntuple_filter_id_hint; 4336c0c050c5SMichael Chan }; 4337c0c050c5SMichael Chan 4338c0c050c5SMichael Chan /* Output (24 bytes) */ 4339c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_output { 4340c0c050c5SMichael Chan __le16 error_code; 4341c0c050c5SMichael Chan __le16 req_type; 4342c0c050c5SMichael Chan __le16 seq_id; 4343c0c050c5SMichael Chan __le16 resp_len; 4344c0c050c5SMichael Chan __le64 ntuple_filter_id; 4345c0c050c5SMichael Chan __le32 flow_id; 4346c0c050c5SMichael Chan u8 unused_0; 4347c0c050c5SMichael Chan u8 unused_1; 4348c0c050c5SMichael Chan u8 unused_2; 4349c0c050c5SMichael Chan u8 valid; 4350c0c050c5SMichael Chan }; 4351c0c050c5SMichael Chan 4352c0c050c5SMichael Chan /* hwrm_cfa_ntuple_filter_free */ 4353c0c050c5SMichael Chan /* Input (24 bytes) */ 4354c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_input { 4355c0c050c5SMichael Chan __le16 req_type; 4356c0c050c5SMichael Chan __le16 cmpl_ring; 4357c0c050c5SMichael Chan __le16 seq_id; 4358c0c050c5SMichael Chan __le16 target_id; 4359c0c050c5SMichael Chan __le64 resp_addr; 4360c0c050c5SMichael Chan __le64 ntuple_filter_id; 4361c0c050c5SMichael Chan }; 4362c0c050c5SMichael Chan 4363c0c050c5SMichael Chan /* Output (16 bytes) */ 4364c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_output { 4365c0c050c5SMichael Chan __le16 error_code; 4366c0c050c5SMichael Chan __le16 req_type; 4367c0c050c5SMichael Chan __le16 seq_id; 4368c0c050c5SMichael Chan __le16 resp_len; 4369c0c050c5SMichael Chan __le32 unused_0; 4370c0c050c5SMichael Chan u8 unused_1; 4371c0c050c5SMichael Chan u8 unused_2; 4372c0c050c5SMichael Chan u8 unused_3; 4373c0c050c5SMichael Chan u8 valid; 4374c0c050c5SMichael Chan }; 4375c0c050c5SMichael Chan 4376c0c050c5SMichael Chan /* hwrm_cfa_ntuple_filter_cfg */ 4377bac9a7e0SMichael Chan /* Input (48 bytes) */ 4378c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_input { 4379c0c050c5SMichael Chan __le16 req_type; 4380c0c050c5SMichael Chan __le16 cmpl_ring; 4381c0c050c5SMichael Chan __le16 seq_id; 4382c0c050c5SMichael Chan __le16 target_id; 4383c0c050c5SMichael Chan __le64 resp_addr; 4384c0c050c5SMichael Chan __le32 enables; 4385c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4386c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4387bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4388c0c050c5SMichael Chan __le32 unused_0; 4389c0c050c5SMichael Chan __le64 ntuple_filter_id; 4390c193554eSMichael Chan __le32 new_dst_id; 4391c0c050c5SMichael Chan __le32 new_mirror_vnic_id; 4392bac9a7e0SMichael Chan __le16 new_meter_instance_id; 4393bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4394bac9a7e0SMichael Chan __le16 unused_1[3]; 4395c0c050c5SMichael Chan }; 4396c0c050c5SMichael Chan 4397c0c050c5SMichael Chan /* Output (16 bytes) */ 4398c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_output { 4399c0c050c5SMichael Chan __le16 error_code; 4400c0c050c5SMichael Chan __le16 req_type; 4401c0c050c5SMichael Chan __le16 seq_id; 4402c0c050c5SMichael Chan __le16 resp_len; 4403c0c050c5SMichael Chan __le32 unused_0; 4404c0c050c5SMichael Chan u8 unused_1; 4405c0c050c5SMichael Chan u8 unused_2; 4406c0c050c5SMichael Chan u8 unused_3; 4407c0c050c5SMichael Chan u8 valid; 4408c0c050c5SMichael Chan }; 4409c0c050c5SMichael Chan 4410acb20054SMichael Chan /* hwrm_cfa_vfr_alloc */ 4411acb20054SMichael Chan /* Input (32 bytes) */ 4412acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_input { 4413acb20054SMichael Chan __le16 req_type; 4414acb20054SMichael Chan __le16 cmpl_ring; 4415acb20054SMichael Chan __le16 seq_id; 4416acb20054SMichael Chan __le16 target_id; 4417acb20054SMichael Chan __le64 resp_addr; 4418acb20054SMichael Chan __le16 vf_id; 4419acb20054SMichael Chan __le16 reserved; 4420acb20054SMichael Chan __le32 unused_0; 4421acb20054SMichael Chan char vfr_name[32]; 4422acb20054SMichael Chan }; 4423acb20054SMichael Chan 4424acb20054SMichael Chan /* Output (16 bytes) */ 4425acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_output { 4426acb20054SMichael Chan __le16 error_code; 4427acb20054SMichael Chan __le16 req_type; 4428acb20054SMichael Chan __le16 seq_id; 4429acb20054SMichael Chan __le16 resp_len; 4430acb20054SMichael Chan __le16 rx_cfa_code; 4431acb20054SMichael Chan __le16 tx_cfa_action; 4432acb20054SMichael Chan u8 unused_0; 4433acb20054SMichael Chan u8 unused_1; 4434acb20054SMichael Chan u8 unused_2; 4435acb20054SMichael Chan u8 valid; 4436acb20054SMichael Chan }; 4437acb20054SMichael Chan 4438acb20054SMichael Chan /* hwrm_cfa_vfr_free */ 4439acb20054SMichael Chan /* Input (24 bytes) */ 4440acb20054SMichael Chan struct hwrm_cfa_vfr_free_input { 4441acb20054SMichael Chan __le16 req_type; 4442acb20054SMichael Chan __le16 cmpl_ring; 4443acb20054SMichael Chan __le16 seq_id; 4444acb20054SMichael Chan __le16 target_id; 4445acb20054SMichael Chan __le64 resp_addr; 4446acb20054SMichael Chan char vfr_name[32]; 4447acb20054SMichael Chan }; 4448acb20054SMichael Chan 4449acb20054SMichael Chan /* Output (16 bytes) */ 4450acb20054SMichael Chan struct hwrm_cfa_vfr_free_output { 4451acb20054SMichael Chan __le16 error_code; 4452acb20054SMichael Chan __le16 req_type; 4453acb20054SMichael Chan __le16 seq_id; 4454acb20054SMichael Chan __le16 resp_len; 4455acb20054SMichael Chan __le32 unused_0; 4456acb20054SMichael Chan u8 unused_1; 4457acb20054SMichael Chan u8 unused_2; 4458acb20054SMichael Chan u8 unused_3; 4459acb20054SMichael Chan u8 valid; 4460acb20054SMichael Chan }; 4461acb20054SMichael Chan 4462c0c050c5SMichael Chan /* hwrm_tunnel_dst_port_query */ 4463c0c050c5SMichael Chan /* Input (24 bytes) */ 4464c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_input { 4465c0c050c5SMichael Chan __le16 req_type; 4466c0c050c5SMichael Chan __le16 cmpl_ring; 4467c0c050c5SMichael Chan __le16 seq_id; 4468c0c050c5SMichael Chan __le16 target_id; 4469c0c050c5SMichael Chan __le64 resp_addr; 4470c0c050c5SMichael Chan u8 tunnel_type; 4471441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4472441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4473c0c050c5SMichael Chan u8 unused_0[7]; 4474c0c050c5SMichael Chan }; 4475c0c050c5SMichael Chan 4476c0c050c5SMichael Chan /* Output (16 bytes) */ 4477c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_output { 4478c0c050c5SMichael Chan __le16 error_code; 4479c0c050c5SMichael Chan __le16 req_type; 4480c0c050c5SMichael Chan __le16 seq_id; 4481c0c050c5SMichael Chan __le16 resp_len; 4482c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 4483c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 4484c0c050c5SMichael Chan u8 unused_0; 4485c0c050c5SMichael Chan u8 unused_1; 4486c0c050c5SMichael Chan u8 unused_2; 4487c0c050c5SMichael Chan u8 valid; 4488c0c050c5SMichael Chan }; 4489c0c050c5SMichael Chan 4490c0c050c5SMichael Chan /* hwrm_tunnel_dst_port_alloc */ 4491c0c050c5SMichael Chan /* Input (24 bytes) */ 4492c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_input { 4493c0c050c5SMichael Chan __le16 req_type; 4494c0c050c5SMichael Chan __le16 cmpl_ring; 4495c0c050c5SMichael Chan __le16 seq_id; 4496c0c050c5SMichael Chan __le16 target_id; 4497c0c050c5SMichael Chan __le64 resp_addr; 4498c0c050c5SMichael Chan u8 tunnel_type; 4499441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4500441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4501c0c050c5SMichael Chan u8 unused_0; 4502c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 4503c0c050c5SMichael Chan __le32 unused_1; 4504c0c050c5SMichael Chan }; 4505c0c050c5SMichael Chan 4506c0c050c5SMichael Chan /* Output (16 bytes) */ 4507c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_output { 4508c0c050c5SMichael Chan __le16 error_code; 4509c0c050c5SMichael Chan __le16 req_type; 4510c0c050c5SMichael Chan __le16 seq_id; 4511c0c050c5SMichael Chan __le16 resp_len; 4512c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 4513c0c050c5SMichael Chan u8 unused_0; 4514c0c050c5SMichael Chan u8 unused_1; 4515c0c050c5SMichael Chan u8 unused_2; 4516c0c050c5SMichael Chan u8 unused_3; 4517c0c050c5SMichael Chan u8 unused_4; 4518c0c050c5SMichael Chan u8 valid; 4519c0c050c5SMichael Chan }; 4520c0c050c5SMichael Chan 4521c0c050c5SMichael Chan /* hwrm_tunnel_dst_port_free */ 4522c0c050c5SMichael Chan /* Input (24 bytes) */ 4523c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_input { 4524c0c050c5SMichael Chan __le16 req_type; 4525c0c050c5SMichael Chan __le16 cmpl_ring; 4526c0c050c5SMichael Chan __le16 seq_id; 4527c0c050c5SMichael Chan __le16 target_id; 4528c0c050c5SMichael Chan __le64 resp_addr; 4529c0c050c5SMichael Chan u8 tunnel_type; 4530441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4531441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4532c0c050c5SMichael Chan u8 unused_0; 4533c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 4534c0c050c5SMichael Chan __le32 unused_1; 4535c0c050c5SMichael Chan }; 4536c0c050c5SMichael Chan 4537c0c050c5SMichael Chan /* Output (16 bytes) */ 4538c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_output { 4539c0c050c5SMichael Chan __le16 error_code; 4540c0c050c5SMichael Chan __le16 req_type; 4541c0c050c5SMichael Chan __le16 seq_id; 4542c0c050c5SMichael Chan __le16 resp_len; 4543c0c050c5SMichael Chan __le32 unused_0; 4544c0c050c5SMichael Chan u8 unused_1; 4545c0c050c5SMichael Chan u8 unused_2; 4546c0c050c5SMichael Chan u8 unused_3; 4547c0c050c5SMichael Chan u8 valid; 4548c0c050c5SMichael Chan }; 4549c0c050c5SMichael Chan 4550c0c050c5SMichael Chan /* hwrm_stat_ctx_alloc */ 4551c0c050c5SMichael Chan /* Input (32 bytes) */ 4552c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_input { 4553c0c050c5SMichael Chan __le16 req_type; 4554c0c050c5SMichael Chan __le16 cmpl_ring; 4555c0c050c5SMichael Chan __le16 seq_id; 4556c0c050c5SMichael Chan __le16 target_id; 4557c0c050c5SMichael Chan __le64 resp_addr; 4558c0c050c5SMichael Chan __le64 stats_dma_addr; 4559c0c050c5SMichael Chan __le32 update_period_ms; 456087c374deSMichael Chan u8 stat_ctx_flags; 456187c374deSMichael Chan #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 456287c374deSMichael Chan u8 unused_0[3]; 4563c0c050c5SMichael Chan }; 4564c0c050c5SMichael Chan 4565c0c050c5SMichael Chan /* Output (16 bytes) */ 4566c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_output { 4567c0c050c5SMichael Chan __le16 error_code; 4568c0c050c5SMichael Chan __le16 req_type; 4569c0c050c5SMichael Chan __le16 seq_id; 4570c0c050c5SMichael Chan __le16 resp_len; 4571c0c050c5SMichael Chan __le32 stat_ctx_id; 4572c0c050c5SMichael Chan u8 unused_0; 4573c0c050c5SMichael Chan u8 unused_1; 4574c0c050c5SMichael Chan u8 unused_2; 4575c0c050c5SMichael Chan u8 valid; 4576c0c050c5SMichael Chan }; 4577c0c050c5SMichael Chan 4578c0c050c5SMichael Chan /* hwrm_stat_ctx_free */ 4579c0c050c5SMichael Chan /* Input (24 bytes) */ 4580c0c050c5SMichael Chan struct hwrm_stat_ctx_free_input { 4581c0c050c5SMichael Chan __le16 req_type; 4582c0c050c5SMichael Chan __le16 cmpl_ring; 4583c0c050c5SMichael Chan __le16 seq_id; 4584c0c050c5SMichael Chan __le16 target_id; 4585c0c050c5SMichael Chan __le64 resp_addr; 4586c0c050c5SMichael Chan __le32 stat_ctx_id; 4587c0c050c5SMichael Chan __le32 unused_0; 4588c0c050c5SMichael Chan }; 4589c0c050c5SMichael Chan 4590c0c050c5SMichael Chan /* Output (16 bytes) */ 4591c0c050c5SMichael Chan struct hwrm_stat_ctx_free_output { 4592c0c050c5SMichael Chan __le16 error_code; 4593c0c050c5SMichael Chan __le16 req_type; 4594c0c050c5SMichael Chan __le16 seq_id; 4595c0c050c5SMichael Chan __le16 resp_len; 4596c0c050c5SMichael Chan __le32 stat_ctx_id; 4597c0c050c5SMichael Chan u8 unused_0; 4598c0c050c5SMichael Chan u8 unused_1; 4599c0c050c5SMichael Chan u8 unused_2; 4600c0c050c5SMichael Chan u8 valid; 4601c0c050c5SMichael Chan }; 4602c0c050c5SMichael Chan 4603c0c050c5SMichael Chan /* hwrm_stat_ctx_query */ 4604c0c050c5SMichael Chan /* Input (24 bytes) */ 4605c0c050c5SMichael Chan struct hwrm_stat_ctx_query_input { 4606c0c050c5SMichael Chan __le16 req_type; 4607c0c050c5SMichael Chan __le16 cmpl_ring; 4608c0c050c5SMichael Chan __le16 seq_id; 4609c0c050c5SMichael Chan __le16 target_id; 4610c0c050c5SMichael Chan __le64 resp_addr; 4611c0c050c5SMichael Chan __le32 stat_ctx_id; 4612c0c050c5SMichael Chan __le32 unused_0; 4613c0c050c5SMichael Chan }; 4614c0c050c5SMichael Chan 4615c0c050c5SMichael Chan /* Output (176 bytes) */ 4616c0c050c5SMichael Chan struct hwrm_stat_ctx_query_output { 4617c0c050c5SMichael Chan __le16 error_code; 4618c0c050c5SMichael Chan __le16 req_type; 4619c0c050c5SMichael Chan __le16 seq_id; 4620c0c050c5SMichael Chan __le16 resp_len; 4621c0c050c5SMichael Chan __le64 tx_ucast_pkts; 4622c0c050c5SMichael Chan __le64 tx_mcast_pkts; 4623c0c050c5SMichael Chan __le64 tx_bcast_pkts; 4624c0c050c5SMichael Chan __le64 tx_err_pkts; 4625c0c050c5SMichael Chan __le64 tx_drop_pkts; 4626c0c050c5SMichael Chan __le64 tx_ucast_bytes; 4627c0c050c5SMichael Chan __le64 tx_mcast_bytes; 4628c0c050c5SMichael Chan __le64 tx_bcast_bytes; 4629c0c050c5SMichael Chan __le64 rx_ucast_pkts; 4630c0c050c5SMichael Chan __le64 rx_mcast_pkts; 4631c0c050c5SMichael Chan __le64 rx_bcast_pkts; 4632c0c050c5SMichael Chan __le64 rx_err_pkts; 4633c0c050c5SMichael Chan __le64 rx_drop_pkts; 4634c0c050c5SMichael Chan __le64 rx_ucast_bytes; 4635c0c050c5SMichael Chan __le64 rx_mcast_bytes; 4636c0c050c5SMichael Chan __le64 rx_bcast_bytes; 4637c0c050c5SMichael Chan __le64 rx_agg_pkts; 4638c0c050c5SMichael Chan __le64 rx_agg_bytes; 4639c0c050c5SMichael Chan __le64 rx_agg_events; 4640c0c050c5SMichael Chan __le64 rx_agg_aborts; 4641c0c050c5SMichael Chan __le32 unused_0; 4642c0c050c5SMichael Chan u8 unused_1; 4643c0c050c5SMichael Chan u8 unused_2; 4644c0c050c5SMichael Chan u8 unused_3; 4645c0c050c5SMichael Chan u8 valid; 4646c0c050c5SMichael Chan }; 4647c0c050c5SMichael Chan 4648c0c050c5SMichael Chan /* hwrm_stat_ctx_clr_stats */ 4649c0c050c5SMichael Chan /* Input (24 bytes) */ 4650c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_input { 4651c0c050c5SMichael Chan __le16 req_type; 4652c0c050c5SMichael Chan __le16 cmpl_ring; 4653c0c050c5SMichael Chan __le16 seq_id; 4654c0c050c5SMichael Chan __le16 target_id; 4655c0c050c5SMichael Chan __le64 resp_addr; 4656c0c050c5SMichael Chan __le32 stat_ctx_id; 4657c0c050c5SMichael Chan __le32 unused_0; 4658c0c050c5SMichael Chan }; 4659c0c050c5SMichael Chan 4660c0c050c5SMichael Chan /* Output (16 bytes) */ 4661c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_output { 4662c0c050c5SMichael Chan __le16 error_code; 4663c0c050c5SMichael Chan __le16 req_type; 4664c0c050c5SMichael Chan __le16 seq_id; 4665c0c050c5SMichael Chan __le16 resp_len; 4666c0c050c5SMichael Chan __le32 unused_0; 4667c0c050c5SMichael Chan u8 unused_1; 4668c0c050c5SMichael Chan u8 unused_2; 4669c0c050c5SMichael Chan u8 unused_3; 4670c0c050c5SMichael Chan u8 valid; 4671c0c050c5SMichael Chan }; 4672c0c050c5SMichael Chan 4673c193554eSMichael Chan /* hwrm_fw_reset */ 4674c193554eSMichael Chan /* Input (24 bytes) */ 4675c193554eSMichael Chan struct hwrm_fw_reset_input { 4676c0c050c5SMichael Chan __le16 req_type; 4677c0c050c5SMichael Chan __le16 cmpl_ring; 4678c0c050c5SMichael Chan __le16 seq_id; 4679c0c050c5SMichael Chan __le16 target_id; 4680c0c050c5SMichael Chan __le64 resp_addr; 4681c193554eSMichael Chan u8 embedded_proc_type; 4682441cabbbSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4683441cabbbSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4684441cabbbSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4685441cabbbSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4686acb20054SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 4687c193554eSMichael Chan u8 selfrst_status; 4688441cabbbSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 4689441cabbbSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 4690441cabbbSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4691acb20054SMichael Chan u8 host_idx; 4692acb20054SMichael Chan u8 unused_0[5]; 4693c0c050c5SMichael Chan }; 4694c0c050c5SMichael Chan 4695c0c050c5SMichael Chan /* Output (16 bytes) */ 4696c193554eSMichael Chan struct hwrm_fw_reset_output { 4697c0c050c5SMichael Chan __le16 error_code; 4698c0c050c5SMichael Chan __le16 req_type; 4699c0c050c5SMichael Chan __le16 seq_id; 4700c0c050c5SMichael Chan __le16 resp_len; 4701c193554eSMichael Chan u8 selfrst_status; 4702441cabbbSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4703441cabbbSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4704441cabbbSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 4705c0c050c5SMichael Chan u8 unused_0; 4706c193554eSMichael Chan __le16 unused_1; 4707c0c050c5SMichael Chan u8 unused_2; 4708c0c050c5SMichael Chan u8 unused_3; 4709c0c050c5SMichael Chan u8 unused_4; 4710c0c050c5SMichael Chan u8 valid; 4711c0c050c5SMichael Chan }; 4712c0c050c5SMichael Chan 471311f15ed3SMichael Chan /* hwrm_fw_qstatus */ 471411f15ed3SMichael Chan /* Input (24 bytes) */ 471511f15ed3SMichael Chan struct hwrm_fw_qstatus_input { 471611f15ed3SMichael Chan __le16 req_type; 471711f15ed3SMichael Chan __le16 cmpl_ring; 471811f15ed3SMichael Chan __le16 seq_id; 471911f15ed3SMichael Chan __le16 target_id; 472011f15ed3SMichael Chan __le64 resp_addr; 472111f15ed3SMichael Chan u8 embedded_proc_type; 4722441cabbbSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 4723441cabbbSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 4724441cabbbSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 4725441cabbbSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 4726acb20054SMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 472711f15ed3SMichael Chan u8 unused_0[7]; 472811f15ed3SMichael Chan }; 472911f15ed3SMichael Chan 473011f15ed3SMichael Chan /* Output (16 bytes) */ 473111f15ed3SMichael Chan struct hwrm_fw_qstatus_output { 473211f15ed3SMichael Chan __le16 error_code; 473311f15ed3SMichael Chan __le16 req_type; 473411f15ed3SMichael Chan __le16 seq_id; 473511f15ed3SMichael Chan __le16 resp_len; 473611f15ed3SMichael Chan u8 selfrst_status; 4737441cabbbSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 4738441cabbbSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 4739441cabbbSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 474011f15ed3SMichael Chan u8 unused_0; 474111f15ed3SMichael Chan __le16 unused_1; 474211f15ed3SMichael Chan u8 unused_2; 474311f15ed3SMichael Chan u8 unused_3; 474411f15ed3SMichael Chan u8 unused_4; 474511f15ed3SMichael Chan u8 valid; 474611f15ed3SMichael Chan }; 474711f15ed3SMichael Chan 4748441cabbbSMichael Chan /* hwrm_fw_set_time */ 4749441cabbbSMichael Chan /* Input (32 bytes) */ 4750441cabbbSMichael Chan struct hwrm_fw_set_time_input { 4751441cabbbSMichael Chan __le16 req_type; 4752441cabbbSMichael Chan __le16 cmpl_ring; 4753441cabbbSMichael Chan __le16 seq_id; 4754441cabbbSMichael Chan __le16 target_id; 4755441cabbbSMichael Chan __le64 resp_addr; 4756441cabbbSMichael Chan __le16 year; 4757441cabbbSMichael Chan #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 4758441cabbbSMichael Chan u8 month; 4759441cabbbSMichael Chan u8 day; 4760441cabbbSMichael Chan u8 hour; 4761441cabbbSMichael Chan u8 minute; 4762441cabbbSMichael Chan u8 second; 4763441cabbbSMichael Chan u8 unused_0; 4764441cabbbSMichael Chan __le16 millisecond; 4765441cabbbSMichael Chan __le16 zone; 4766441cabbbSMichael Chan #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 4767441cabbbSMichael Chan #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 4768441cabbbSMichael Chan __le32 unused_1; 4769441cabbbSMichael Chan }; 4770441cabbbSMichael Chan 4771441cabbbSMichael Chan /* Output (16 bytes) */ 4772441cabbbSMichael Chan struct hwrm_fw_set_time_output { 4773441cabbbSMichael Chan __le16 error_code; 4774441cabbbSMichael Chan __le16 req_type; 4775441cabbbSMichael Chan __le16 seq_id; 4776441cabbbSMichael Chan __le16 resp_len; 4777441cabbbSMichael Chan __le32 unused_0; 4778441cabbbSMichael Chan u8 unused_1; 4779441cabbbSMichael Chan u8 unused_2; 4780441cabbbSMichael Chan u8 unused_3; 4781441cabbbSMichael Chan u8 valid; 4782441cabbbSMichael Chan }; 4783441cabbbSMichael Chan 478416d663a6SMichael Chan /* hwrm_fw_set_structured_data */ 478516d663a6SMichael Chan /* Input (32 bytes) */ 478616d663a6SMichael Chan struct hwrm_fw_set_structured_data_input { 478716d663a6SMichael Chan __le16 req_type; 478816d663a6SMichael Chan __le16 cmpl_ring; 478916d663a6SMichael Chan __le16 seq_id; 479016d663a6SMichael Chan __le16 target_id; 479116d663a6SMichael Chan __le64 resp_addr; 479216d663a6SMichael Chan __le64 src_data_addr; 479316d663a6SMichael Chan __le16 data_len; 479416d663a6SMichael Chan u8 hdr_cnt; 4795f183886cSMichael Chan u8 unused_0[5]; 479616d663a6SMichael Chan }; 479716d663a6SMichael Chan 479816d663a6SMichael Chan /* Output (16 bytes) */ 479916d663a6SMichael Chan struct hwrm_fw_set_structured_data_output { 480016d663a6SMichael Chan __le16 error_code; 480116d663a6SMichael Chan __le16 req_type; 480216d663a6SMichael Chan __le16 seq_id; 480316d663a6SMichael Chan __le16 resp_len; 480416d663a6SMichael Chan __le32 unused_0; 480516d663a6SMichael Chan u8 unused_1; 480616d663a6SMichael Chan u8 unused_2; 480716d663a6SMichael Chan u8 unused_3; 480816d663a6SMichael Chan u8 valid; 480916d663a6SMichael Chan }; 481016d663a6SMichael Chan 4811acb20054SMichael Chan /* Command specific Error Codes (8 bytes) */ 4812acb20054SMichael Chan struct hwrm_fw_set_structured_data_cmd_err { 4813acb20054SMichael Chan u8 code; 4814acb20054SMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 4815acb20054SMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 4816acb20054SMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 4817acb20054SMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 4818acb20054SMichael Chan u8 unused_0[7]; 4819acb20054SMichael Chan }; 4820acb20054SMichael Chan 482116d663a6SMichael Chan /* hwrm_fw_get_structured_data */ 4822f183886cSMichael Chan /* Input (32 bytes) */ 482316d663a6SMichael Chan struct hwrm_fw_get_structured_data_input { 482416d663a6SMichael Chan __le16 req_type; 482516d663a6SMichael Chan __le16 cmpl_ring; 482616d663a6SMichael Chan __le16 seq_id; 482716d663a6SMichael Chan __le16 target_id; 482816d663a6SMichael Chan __le64 resp_addr; 482916d663a6SMichael Chan __le64 dest_data_addr; 483016d663a6SMichael Chan __le16 data_len; 483116d663a6SMichael Chan __le16 structure_id; 483216d663a6SMichael Chan __le16 subtype; 483316d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 483416d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 483516d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 483616d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 483716d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 483816d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 483916d663a6SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 4840bac9a7e0SMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 484116d663a6SMichael Chan u8 count; 484216d663a6SMichael Chan u8 unused_0; 484316d663a6SMichael Chan }; 484416d663a6SMichael Chan 484516d663a6SMichael Chan /* Output (16 bytes) */ 484616d663a6SMichael Chan struct hwrm_fw_get_structured_data_output { 484716d663a6SMichael Chan __le16 error_code; 484816d663a6SMichael Chan __le16 req_type; 484916d663a6SMichael Chan __le16 seq_id; 485016d663a6SMichael Chan __le16 resp_len; 485116d663a6SMichael Chan u8 hdr_cnt; 485216d663a6SMichael Chan u8 unused_0; 485316d663a6SMichael Chan __le16 unused_1; 485416d663a6SMichael Chan u8 unused_2; 485516d663a6SMichael Chan u8 unused_3; 485616d663a6SMichael Chan u8 unused_4; 485716d663a6SMichael Chan u8 valid; 485816d663a6SMichael Chan }; 485916d663a6SMichael Chan 4860acb20054SMichael Chan /* Command specific Error Codes (8 bytes) */ 4861acb20054SMichael Chan struct hwrm_fw_get_structured_data_cmd_err { 4862acb20054SMichael Chan u8 code; 4863acb20054SMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 4864acb20054SMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 4865acb20054SMichael Chan u8 unused_0[7]; 4866acb20054SMichael Chan }; 4867acb20054SMichael Chan 4868c193554eSMichael Chan /* hwrm_exec_fwd_resp */ 4869c193554eSMichael Chan /* Input (128 bytes) */ 4870c193554eSMichael Chan struct hwrm_exec_fwd_resp_input { 4871c0c050c5SMichael Chan __le16 req_type; 4872c0c050c5SMichael Chan __le16 cmpl_ring; 4873c0c050c5SMichael Chan __le16 seq_id; 4874c0c050c5SMichael Chan __le16 target_id; 4875c0c050c5SMichael Chan __le64 resp_addr; 4876c193554eSMichael Chan __le32 encap_request[26]; 4877c193554eSMichael Chan __le16 encap_resp_target_id; 4878c0c050c5SMichael Chan __le16 unused_0[3]; 4879c0c050c5SMichael Chan }; 4880c0c050c5SMichael Chan 4881c0c050c5SMichael Chan /* Output (16 bytes) */ 4882c193554eSMichael Chan struct hwrm_exec_fwd_resp_output { 4883c0c050c5SMichael Chan __le16 error_code; 4884c0c050c5SMichael Chan __le16 req_type; 4885c0c050c5SMichael Chan __le16 seq_id; 4886c0c050c5SMichael Chan __le16 resp_len; 4887c0c050c5SMichael Chan __le32 unused_0; 4888c0c050c5SMichael Chan u8 unused_1; 4889c0c050c5SMichael Chan u8 unused_2; 4890c0c050c5SMichael Chan u8 unused_3; 4891c0c050c5SMichael Chan u8 valid; 4892c0c050c5SMichael Chan }; 4893c0c050c5SMichael Chan 4894c193554eSMichael Chan /* hwrm_reject_fwd_resp */ 4895c193554eSMichael Chan /* Input (128 bytes) */ 4896c193554eSMichael Chan struct hwrm_reject_fwd_resp_input { 4897c193554eSMichael Chan __le16 req_type; 4898c193554eSMichael Chan __le16 cmpl_ring; 4899c193554eSMichael Chan __le16 seq_id; 4900c193554eSMichael Chan __le16 target_id; 4901c193554eSMichael Chan __le64 resp_addr; 4902c193554eSMichael Chan __le32 encap_request[26]; 4903c193554eSMichael Chan __le16 encap_resp_target_id; 4904c193554eSMichael Chan __le16 unused_0[3]; 4905c193554eSMichael Chan }; 4906c193554eSMichael Chan 4907c193554eSMichael Chan /* Output (16 bytes) */ 4908c193554eSMichael Chan struct hwrm_reject_fwd_resp_output { 4909c193554eSMichael Chan __le16 error_code; 4910c193554eSMichael Chan __le16 req_type; 4911c193554eSMichael Chan __le16 seq_id; 4912c193554eSMichael Chan __le16 resp_len; 4913c193554eSMichael Chan __le32 unused_0; 4914c193554eSMichael Chan u8 unused_1; 4915c193554eSMichael Chan u8 unused_2; 4916c193554eSMichael Chan u8 unused_3; 4917c193554eSMichael Chan u8 valid; 4918c193554eSMichael Chan }; 4919c193554eSMichael Chan 4920c193554eSMichael Chan /* hwrm_fwd_resp */ 4921c193554eSMichael Chan /* Input (40 bytes) */ 4922c193554eSMichael Chan struct hwrm_fwd_resp_input { 4923c193554eSMichael Chan __le16 req_type; 4924c193554eSMichael Chan __le16 cmpl_ring; 4925c193554eSMichael Chan __le16 seq_id; 4926c193554eSMichael Chan __le16 target_id; 4927c193554eSMichael Chan __le64 resp_addr; 4928c193554eSMichael Chan __le16 encap_resp_target_id; 4929c193554eSMichael Chan __le16 encap_resp_cmpl_ring; 4930c193554eSMichael Chan __le16 encap_resp_len; 4931c193554eSMichael Chan u8 unused_0; 4932c193554eSMichael Chan u8 unused_1; 4933c193554eSMichael Chan __le64 encap_resp_addr; 4934c193554eSMichael Chan __le32 encap_resp[24]; 4935c193554eSMichael Chan }; 4936c193554eSMichael Chan 4937c193554eSMichael Chan /* Output (16 bytes) */ 4938c193554eSMichael Chan struct hwrm_fwd_resp_output { 4939c193554eSMichael Chan __le16 error_code; 4940c193554eSMichael Chan __le16 req_type; 4941c193554eSMichael Chan __le16 seq_id; 4942c193554eSMichael Chan __le16 resp_len; 4943c193554eSMichael Chan __le32 unused_0; 4944c193554eSMichael Chan u8 unused_1; 4945c193554eSMichael Chan u8 unused_2; 4946c193554eSMichael Chan u8 unused_3; 4947c193554eSMichael Chan u8 valid; 4948c193554eSMichael Chan }; 4949c193554eSMichael Chan 4950c193554eSMichael Chan /* hwrm_fwd_async_event_cmpl */ 4951c193554eSMichael Chan /* Input (32 bytes) */ 4952c193554eSMichael Chan struct hwrm_fwd_async_event_cmpl_input { 4953c193554eSMichael Chan __le16 req_type; 4954c193554eSMichael Chan __le16 cmpl_ring; 4955c193554eSMichael Chan __le16 seq_id; 4956c193554eSMichael Chan __le16 target_id; 4957c193554eSMichael Chan __le64 resp_addr; 4958c193554eSMichael Chan __le16 encap_async_event_target_id; 4959c193554eSMichael Chan u8 unused_0; 4960c193554eSMichael Chan u8 unused_1; 4961c193554eSMichael Chan u8 unused_2[3]; 4962c193554eSMichael Chan u8 unused_3; 4963c193554eSMichael Chan __le32 encap_async_event_cmpl[4]; 4964c193554eSMichael Chan }; 4965c193554eSMichael Chan 4966c193554eSMichael Chan /* Output (16 bytes) */ 4967c193554eSMichael Chan struct hwrm_fwd_async_event_cmpl_output { 4968c193554eSMichael Chan __le16 error_code; 4969c193554eSMichael Chan __le16 req_type; 4970c193554eSMichael Chan __le16 seq_id; 4971c193554eSMichael Chan __le16 resp_len; 4972c193554eSMichael Chan __le32 unused_0; 4973c193554eSMichael Chan u8 unused_1; 4974c193554eSMichael Chan u8 unused_2; 4975c193554eSMichael Chan u8 unused_3; 4976c193554eSMichael Chan u8 valid; 4977c193554eSMichael Chan }; 4978c193554eSMichael Chan 4979c193554eSMichael Chan /* hwrm_temp_monitor_query */ 4980c193554eSMichael Chan /* Input (16 bytes) */ 4981c193554eSMichael Chan struct hwrm_temp_monitor_query_input { 4982c193554eSMichael Chan __le16 req_type; 4983c193554eSMichael Chan __le16 cmpl_ring; 4984c193554eSMichael Chan __le16 seq_id; 4985c193554eSMichael Chan __le16 target_id; 4986c193554eSMichael Chan __le64 resp_addr; 4987c193554eSMichael Chan }; 4988c193554eSMichael Chan 4989c193554eSMichael Chan /* Output (16 bytes) */ 4990c193554eSMichael Chan struct hwrm_temp_monitor_query_output { 4991c193554eSMichael Chan __le16 error_code; 4992c193554eSMichael Chan __le16 req_type; 4993c193554eSMichael Chan __le16 seq_id; 4994c193554eSMichael Chan __le16 resp_len; 4995c193554eSMichael Chan u8 temp; 4996c193554eSMichael Chan u8 unused_0; 4997c193554eSMichael Chan __le16 unused_1; 4998c193554eSMichael Chan u8 unused_2; 4999c193554eSMichael Chan u8 unused_3; 5000c193554eSMichael Chan u8 unused_4; 5001c193554eSMichael Chan u8 valid; 5002c193554eSMichael Chan }; 5003c193554eSMichael Chan 50048eb992e8SMichael Chan /* hwrm_wol_filter_alloc */ 50058eb992e8SMichael Chan /* Input (64 bytes) */ 50068eb992e8SMichael Chan struct hwrm_wol_filter_alloc_input { 50078eb992e8SMichael Chan __le16 req_type; 50088eb992e8SMichael Chan __le16 cmpl_ring; 50098eb992e8SMichael Chan __le16 seq_id; 50108eb992e8SMichael Chan __le16 target_id; 50118eb992e8SMichael Chan __le64 resp_addr; 50128eb992e8SMichael Chan __le32 flags; 50138eb992e8SMichael Chan __le32 enables; 50148eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 50158eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 50168eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 50178eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 50188eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 50198eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 50208eb992e8SMichael Chan __le16 port_id; 50218eb992e8SMichael Chan u8 wol_type; 50228eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 50238eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 50248eb992e8SMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 50258eb992e8SMichael Chan u8 unused_0; 50268eb992e8SMichael Chan __le32 unused_1; 50278eb992e8SMichael Chan u8 mac_address[6]; 50288eb992e8SMichael Chan __le16 pattern_offset; 50298eb992e8SMichael Chan __le16 pattern_buf_size; 50308eb992e8SMichael Chan __le16 pattern_mask_size; 50318eb992e8SMichael Chan __le32 unused_2; 50328eb992e8SMichael Chan __le64 pattern_buf_addr; 50338eb992e8SMichael Chan __le64 pattern_mask_addr; 50348eb992e8SMichael Chan }; 50358eb992e8SMichael Chan 50368eb992e8SMichael Chan /* Output (16 bytes) */ 50378eb992e8SMichael Chan struct hwrm_wol_filter_alloc_output { 50388eb992e8SMichael Chan __le16 error_code; 50398eb992e8SMichael Chan __le16 req_type; 50408eb992e8SMichael Chan __le16 seq_id; 50418eb992e8SMichael Chan __le16 resp_len; 50428eb992e8SMichael Chan u8 wol_filter_id; 50438eb992e8SMichael Chan u8 unused_0; 50448eb992e8SMichael Chan __le16 unused_1; 50458eb992e8SMichael Chan u8 unused_2; 50468eb992e8SMichael Chan u8 unused_3; 50478eb992e8SMichael Chan u8 unused_4; 50488eb992e8SMichael Chan u8 valid; 50498eb992e8SMichael Chan }; 50508eb992e8SMichael Chan 50518eb992e8SMichael Chan /* hwrm_wol_filter_free */ 50528eb992e8SMichael Chan /* Input (32 bytes) */ 50538eb992e8SMichael Chan struct hwrm_wol_filter_free_input { 50548eb992e8SMichael Chan __le16 req_type; 50558eb992e8SMichael Chan __le16 cmpl_ring; 50568eb992e8SMichael Chan __le16 seq_id; 50578eb992e8SMichael Chan __le16 target_id; 50588eb992e8SMichael Chan __le64 resp_addr; 50598eb992e8SMichael Chan __le32 flags; 50608eb992e8SMichael Chan #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 50618eb992e8SMichael Chan __le32 enables; 50628eb992e8SMichael Chan #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 50638eb992e8SMichael Chan __le16 port_id; 50648eb992e8SMichael Chan u8 wol_filter_id; 50658eb992e8SMichael Chan u8 unused_0[5]; 50668eb992e8SMichael Chan }; 50678eb992e8SMichael Chan 50688eb992e8SMichael Chan /* Output (16 bytes) */ 50698eb992e8SMichael Chan struct hwrm_wol_filter_free_output { 50708eb992e8SMichael Chan __le16 error_code; 50718eb992e8SMichael Chan __le16 req_type; 50728eb992e8SMichael Chan __le16 seq_id; 50738eb992e8SMichael Chan __le16 resp_len; 50748eb992e8SMichael Chan __le32 unused_0; 50758eb992e8SMichael Chan u8 unused_1; 50768eb992e8SMichael Chan u8 unused_2; 50778eb992e8SMichael Chan u8 unused_3; 50788eb992e8SMichael Chan u8 valid; 50798eb992e8SMichael Chan }; 50808eb992e8SMichael Chan 50818eb992e8SMichael Chan /* hwrm_wol_filter_qcfg */ 50828eb992e8SMichael Chan /* Input (56 bytes) */ 50838eb992e8SMichael Chan struct hwrm_wol_filter_qcfg_input { 50848eb992e8SMichael Chan __le16 req_type; 50858eb992e8SMichael Chan __le16 cmpl_ring; 50868eb992e8SMichael Chan __le16 seq_id; 50878eb992e8SMichael Chan __le16 target_id; 50888eb992e8SMichael Chan __le64 resp_addr; 50898eb992e8SMichael Chan __le16 port_id; 50908eb992e8SMichael Chan __le16 handle; 50918eb992e8SMichael Chan __le32 unused_0; 50928eb992e8SMichael Chan __le64 pattern_buf_addr; 50938eb992e8SMichael Chan __le16 pattern_buf_size; 50948eb992e8SMichael Chan u8 unused_1; 50958eb992e8SMichael Chan u8 unused_2; 50968eb992e8SMichael Chan u8 unused_3[3]; 50978eb992e8SMichael Chan u8 unused_4; 50988eb992e8SMichael Chan __le64 pattern_mask_addr; 50998eb992e8SMichael Chan __le16 pattern_mask_size; 51008eb992e8SMichael Chan __le16 unused_5[3]; 51018eb992e8SMichael Chan }; 51028eb992e8SMichael Chan 51038eb992e8SMichael Chan /* Output (32 bytes) */ 51048eb992e8SMichael Chan struct hwrm_wol_filter_qcfg_output { 51058eb992e8SMichael Chan __le16 error_code; 51068eb992e8SMichael Chan __le16 req_type; 51078eb992e8SMichael Chan __le16 seq_id; 51088eb992e8SMichael Chan __le16 resp_len; 51098eb992e8SMichael Chan __le16 next_handle; 51108eb992e8SMichael Chan u8 wol_filter_id; 51118eb992e8SMichael Chan u8 wol_type; 51128eb992e8SMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 51138eb992e8SMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 51148eb992e8SMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 51158eb992e8SMichael Chan __le32 unused_0; 51168eb992e8SMichael Chan u8 mac_address[6]; 51178eb992e8SMichael Chan __le16 pattern_offset; 51188eb992e8SMichael Chan __le16 pattern_size; 51198eb992e8SMichael Chan __le16 pattern_mask_size; 51208eb992e8SMichael Chan u8 unused_1; 51218eb992e8SMichael Chan u8 unused_2; 51228eb992e8SMichael Chan u8 unused_3; 51238eb992e8SMichael Chan u8 valid; 51248eb992e8SMichael Chan }; 51258eb992e8SMichael Chan 51268eb992e8SMichael Chan /* hwrm_wol_reason_qcfg */ 51278eb992e8SMichael Chan /* Input (40 bytes) */ 51288eb992e8SMichael Chan struct hwrm_wol_reason_qcfg_input { 51298eb992e8SMichael Chan __le16 req_type; 51308eb992e8SMichael Chan __le16 cmpl_ring; 51318eb992e8SMichael Chan __le16 seq_id; 51328eb992e8SMichael Chan __le16 target_id; 51338eb992e8SMichael Chan __le64 resp_addr; 51348eb992e8SMichael Chan __le16 port_id; 51358eb992e8SMichael Chan u8 unused_0; 51368eb992e8SMichael Chan u8 unused_1; 51378eb992e8SMichael Chan u8 unused_2[3]; 51388eb992e8SMichael Chan u8 unused_3; 51398eb992e8SMichael Chan __le64 wol_pkt_buf_addr; 51408eb992e8SMichael Chan __le16 wol_pkt_buf_size; 51418eb992e8SMichael Chan __le16 unused_4[3]; 51428eb992e8SMichael Chan }; 51438eb992e8SMichael Chan 51448eb992e8SMichael Chan /* Output (16 bytes) */ 51458eb992e8SMichael Chan struct hwrm_wol_reason_qcfg_output { 51468eb992e8SMichael Chan __le16 error_code; 51478eb992e8SMichael Chan __le16 req_type; 51488eb992e8SMichael Chan __le16 seq_id; 51498eb992e8SMichael Chan __le16 resp_len; 51508eb992e8SMichael Chan u8 wol_filter_id; 51518eb992e8SMichael Chan u8 wol_reason; 51528eb992e8SMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 51538eb992e8SMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 51548eb992e8SMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 51558eb992e8SMichael Chan u8 wol_pkt_len; 51568eb992e8SMichael Chan u8 unused_0; 51578eb992e8SMichael Chan u8 unused_1; 51588eb992e8SMichael Chan u8 unused_2; 51598eb992e8SMichael Chan u8 unused_3; 51608eb992e8SMichael Chan u8 valid; 51618eb992e8SMichael Chan }; 51628eb992e8SMichael Chan 5163c0c050c5SMichael Chan /* hwrm_nvm_read */ 5164c0c050c5SMichael Chan /* Input (40 bytes) */ 5165c0c050c5SMichael Chan struct hwrm_nvm_read_input { 5166c0c050c5SMichael Chan __le16 req_type; 5167c0c050c5SMichael Chan __le16 cmpl_ring; 5168c0c050c5SMichael Chan __le16 seq_id; 5169c0c050c5SMichael Chan __le16 target_id; 5170c0c050c5SMichael Chan __le64 resp_addr; 5171c0c050c5SMichael Chan __le64 host_dest_addr; 5172c0c050c5SMichael Chan __le16 dir_idx; 5173c0c050c5SMichael Chan u8 unused_0; 5174c0c050c5SMichael Chan u8 unused_1; 5175c0c050c5SMichael Chan __le32 offset; 5176c0c050c5SMichael Chan __le32 len; 5177c0c050c5SMichael Chan __le32 unused_2; 5178c0c050c5SMichael Chan }; 5179c0c050c5SMichael Chan 5180c0c050c5SMichael Chan /* Output (16 bytes) */ 5181c0c050c5SMichael Chan struct hwrm_nvm_read_output { 5182c0c050c5SMichael Chan __le16 error_code; 5183c0c050c5SMichael Chan __le16 req_type; 5184c0c050c5SMichael Chan __le16 seq_id; 5185c0c050c5SMichael Chan __le16 resp_len; 5186c0c050c5SMichael Chan __le32 unused_0; 5187c0c050c5SMichael Chan u8 unused_1; 5188c0c050c5SMichael Chan u8 unused_2; 5189c0c050c5SMichael Chan u8 unused_3; 5190c0c050c5SMichael Chan u8 valid; 5191c0c050c5SMichael Chan }; 5192c0c050c5SMichael Chan 5193c0c050c5SMichael Chan /* hwrm_nvm_get_dir_entries */ 5194c0c050c5SMichael Chan /* Input (24 bytes) */ 5195c0c050c5SMichael Chan struct hwrm_nvm_get_dir_entries_input { 5196c0c050c5SMichael Chan __le16 req_type; 5197c0c050c5SMichael Chan __le16 cmpl_ring; 5198c0c050c5SMichael Chan __le16 seq_id; 5199c0c050c5SMichael Chan __le16 target_id; 5200c0c050c5SMichael Chan __le64 resp_addr; 5201c0c050c5SMichael Chan __le64 host_dest_addr; 5202c0c050c5SMichael Chan }; 5203c0c050c5SMichael Chan 5204c0c050c5SMichael Chan /* Output (16 bytes) */ 5205c0c050c5SMichael Chan struct hwrm_nvm_get_dir_entries_output { 5206c0c050c5SMichael Chan __le16 error_code; 5207c0c050c5SMichael Chan __le16 req_type; 5208c0c050c5SMichael Chan __le16 seq_id; 5209c0c050c5SMichael Chan __le16 resp_len; 5210c0c050c5SMichael Chan __le32 unused_0; 5211c0c050c5SMichael Chan u8 unused_1; 5212c0c050c5SMichael Chan u8 unused_2; 5213c0c050c5SMichael Chan u8 unused_3; 5214c0c050c5SMichael Chan u8 valid; 5215c0c050c5SMichael Chan }; 5216c0c050c5SMichael Chan 5217c0c050c5SMichael Chan /* hwrm_nvm_get_dir_info */ 5218c0c050c5SMichael Chan /* Input (16 bytes) */ 5219c0c050c5SMichael Chan struct hwrm_nvm_get_dir_info_input { 5220c0c050c5SMichael Chan __le16 req_type; 5221c0c050c5SMichael Chan __le16 cmpl_ring; 5222c0c050c5SMichael Chan __le16 seq_id; 5223c0c050c5SMichael Chan __le16 target_id; 5224c0c050c5SMichael Chan __le64 resp_addr; 5225c0c050c5SMichael Chan }; 5226c0c050c5SMichael Chan 5227c0c050c5SMichael Chan /* Output (24 bytes) */ 5228c0c050c5SMichael Chan struct hwrm_nvm_get_dir_info_output { 5229c0c050c5SMichael Chan __le16 error_code; 5230c0c050c5SMichael Chan __le16 req_type; 5231c0c050c5SMichael Chan __le16 seq_id; 5232c0c050c5SMichael Chan __le16 resp_len; 5233c0c050c5SMichael Chan __le32 entries; 5234c0c050c5SMichael Chan __le32 entry_length; 5235c0c050c5SMichael Chan __le32 unused_0; 5236c0c050c5SMichael Chan u8 unused_1; 5237c0c050c5SMichael Chan u8 unused_2; 5238c0c050c5SMichael Chan u8 unused_3; 5239c0c050c5SMichael Chan u8 valid; 5240c0c050c5SMichael Chan }; 5241c0c050c5SMichael Chan 5242c0c050c5SMichael Chan /* hwrm_nvm_write */ 5243c193554eSMichael Chan /* Input (48 bytes) */ 5244c0c050c5SMichael Chan struct hwrm_nvm_write_input { 5245c0c050c5SMichael Chan __le16 req_type; 5246c0c050c5SMichael Chan __le16 cmpl_ring; 5247c0c050c5SMichael Chan __le16 seq_id; 5248c0c050c5SMichael Chan __le16 target_id; 5249c0c050c5SMichael Chan __le64 resp_addr; 5250c0c050c5SMichael Chan __le64 host_src_addr; 5251c0c050c5SMichael Chan __le16 dir_type; 5252c0c050c5SMichael Chan __le16 dir_ordinal; 5253c0c050c5SMichael Chan __le16 dir_ext; 5254c0c050c5SMichael Chan __le16 dir_attr; 5255c0c050c5SMichael Chan __le32 dir_data_length; 5256c0c050c5SMichael Chan __le16 option; 5257c0c050c5SMichael Chan __le16 flags; 5258c0c050c5SMichael Chan #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5259c193554eSMichael Chan __le32 dir_item_length; 5260c193554eSMichael Chan __le32 unused_0; 5261c0c050c5SMichael Chan }; 5262c0c050c5SMichael Chan 5263c0c050c5SMichael Chan /* Output (16 bytes) */ 5264c0c050c5SMichael Chan struct hwrm_nvm_write_output { 5265c0c050c5SMichael Chan __le16 error_code; 5266c0c050c5SMichael Chan __le16 req_type; 5267c0c050c5SMichael Chan __le16 seq_id; 5268c0c050c5SMichael Chan __le16 resp_len; 5269c193554eSMichael Chan __le32 dir_item_length; 5270c193554eSMichael Chan __le16 dir_idx; 5271c193554eSMichael Chan u8 unused_0; 5272c0c050c5SMichael Chan u8 valid; 5273c0c050c5SMichael Chan }; 5274c0c050c5SMichael Chan 52758eb992e8SMichael Chan /* Command specific Error Codes (8 bytes) */ 52768eb992e8SMichael Chan struct hwrm_nvm_write_cmd_err { 52778eb992e8SMichael Chan u8 code; 52788eb992e8SMichael Chan #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 52798eb992e8SMichael Chan #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 52808eb992e8SMichael Chan #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 52818eb992e8SMichael Chan u8 unused_0[7]; 52828eb992e8SMichael Chan }; 52838eb992e8SMichael Chan 5284c0c050c5SMichael Chan /* hwrm_nvm_modify */ 5285c0c050c5SMichael Chan /* Input (40 bytes) */ 5286c0c050c5SMichael Chan struct hwrm_nvm_modify_input { 5287c0c050c5SMichael Chan __le16 req_type; 5288c0c050c5SMichael Chan __le16 cmpl_ring; 5289c0c050c5SMichael Chan __le16 seq_id; 5290c0c050c5SMichael Chan __le16 target_id; 5291c0c050c5SMichael Chan __le64 resp_addr; 5292c0c050c5SMichael Chan __le64 host_src_addr; 5293c0c050c5SMichael Chan __le16 dir_idx; 5294c0c050c5SMichael Chan u8 unused_0; 5295c0c050c5SMichael Chan u8 unused_1; 5296c0c050c5SMichael Chan __le32 offset; 5297c0c050c5SMichael Chan __le32 len; 5298c0c050c5SMichael Chan __le32 unused_2; 5299c0c050c5SMichael Chan }; 5300c0c050c5SMichael Chan 5301c0c050c5SMichael Chan /* Output (16 bytes) */ 5302c0c050c5SMichael Chan struct hwrm_nvm_modify_output { 5303c0c050c5SMichael Chan __le16 error_code; 5304c0c050c5SMichael Chan __le16 req_type; 5305c0c050c5SMichael Chan __le16 seq_id; 5306c0c050c5SMichael Chan __le16 resp_len; 5307c0c050c5SMichael Chan __le32 unused_0; 5308c0c050c5SMichael Chan u8 unused_1; 5309c0c050c5SMichael Chan u8 unused_2; 5310c0c050c5SMichael Chan u8 unused_3; 5311c0c050c5SMichael Chan u8 valid; 5312c0c050c5SMichael Chan }; 5313c0c050c5SMichael Chan 5314c0c050c5SMichael Chan /* hwrm_nvm_find_dir_entry */ 5315c0c050c5SMichael Chan /* Input (32 bytes) */ 5316c0c050c5SMichael Chan struct hwrm_nvm_find_dir_entry_input { 5317c0c050c5SMichael Chan __le16 req_type; 5318c0c050c5SMichael Chan __le16 cmpl_ring; 5319c0c050c5SMichael Chan __le16 seq_id; 5320c0c050c5SMichael Chan __le16 target_id; 5321c0c050c5SMichael Chan __le64 resp_addr; 5322c0c050c5SMichael Chan __le32 enables; 5323c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 5324c0c050c5SMichael Chan __le16 dir_idx; 5325c0c050c5SMichael Chan __le16 dir_type; 5326c0c050c5SMichael Chan __le16 dir_ordinal; 5327c0c050c5SMichael Chan __le16 dir_ext; 5328c0c050c5SMichael Chan u8 opt_ordinal; 5329c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 5330c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 5331441cabbbSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 5332441cabbbSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 5333441cabbbSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 5334c0c050c5SMichael Chan u8 unused_1[3]; 5335c0c050c5SMichael Chan }; 5336c0c050c5SMichael Chan 5337c0c050c5SMichael Chan /* Output (32 bytes) */ 5338c0c050c5SMichael Chan struct hwrm_nvm_find_dir_entry_output { 5339c0c050c5SMichael Chan __le16 error_code; 5340c0c050c5SMichael Chan __le16 req_type; 5341c0c050c5SMichael Chan __le16 seq_id; 5342c0c050c5SMichael Chan __le16 resp_len; 5343c0c050c5SMichael Chan __le32 dir_item_length; 5344c0c050c5SMichael Chan __le32 dir_data_length; 5345c0c050c5SMichael Chan __le32 fw_ver; 5346c0c050c5SMichael Chan __le16 dir_ordinal; 5347c0c050c5SMichael Chan __le16 dir_idx; 5348c0c050c5SMichael Chan __le32 unused_0; 5349c0c050c5SMichael Chan u8 unused_1; 5350c0c050c5SMichael Chan u8 unused_2; 5351c0c050c5SMichael Chan u8 unused_3; 5352c0c050c5SMichael Chan u8 valid; 5353c0c050c5SMichael Chan }; 5354c0c050c5SMichael Chan 5355c0c050c5SMichael Chan /* hwrm_nvm_erase_dir_entry */ 5356c0c050c5SMichael Chan /* Input (24 bytes) */ 5357c0c050c5SMichael Chan struct hwrm_nvm_erase_dir_entry_input { 5358c0c050c5SMichael Chan __le16 req_type; 5359c0c050c5SMichael Chan __le16 cmpl_ring; 5360c0c050c5SMichael Chan __le16 seq_id; 5361c0c050c5SMichael Chan __le16 target_id; 5362c0c050c5SMichael Chan __le64 resp_addr; 5363c0c050c5SMichael Chan __le16 dir_idx; 5364c0c050c5SMichael Chan __le16 unused_0[3]; 5365c0c050c5SMichael Chan }; 5366c0c050c5SMichael Chan 5367c0c050c5SMichael Chan /* Output (16 bytes) */ 5368c0c050c5SMichael Chan struct hwrm_nvm_erase_dir_entry_output { 5369c0c050c5SMichael Chan __le16 error_code; 5370c0c050c5SMichael Chan __le16 req_type; 5371c0c050c5SMichael Chan __le16 seq_id; 5372c0c050c5SMichael Chan __le16 resp_len; 5373c0c050c5SMichael Chan __le32 unused_0; 5374c0c050c5SMichael Chan u8 unused_1; 5375c0c050c5SMichael Chan u8 unused_2; 5376c0c050c5SMichael Chan u8 unused_3; 5377c0c050c5SMichael Chan u8 valid; 5378c0c050c5SMichael Chan }; 5379c0c050c5SMichael Chan 5380c0c050c5SMichael Chan /* hwrm_nvm_get_dev_info */ 5381c0c050c5SMichael Chan /* Input (16 bytes) */ 5382c0c050c5SMichael Chan struct hwrm_nvm_get_dev_info_input { 5383c0c050c5SMichael Chan __le16 req_type; 5384c0c050c5SMichael Chan __le16 cmpl_ring; 5385c0c050c5SMichael Chan __le16 seq_id; 5386c0c050c5SMichael Chan __le16 target_id; 5387c0c050c5SMichael Chan __le64 resp_addr; 5388c0c050c5SMichael Chan }; 5389c0c050c5SMichael Chan 5390c0c050c5SMichael Chan /* Output (32 bytes) */ 5391c0c050c5SMichael Chan struct hwrm_nvm_get_dev_info_output { 5392c0c050c5SMichael Chan __le16 error_code; 5393c0c050c5SMichael Chan __le16 req_type; 5394c0c050c5SMichael Chan __le16 seq_id; 5395c0c050c5SMichael Chan __le16 resp_len; 5396c0c050c5SMichael Chan __le16 manufacturer_id; 5397c0c050c5SMichael Chan __le16 device_id; 5398c0c050c5SMichael Chan __le32 sector_size; 5399c0c050c5SMichael Chan __le32 nvram_size; 5400c0c050c5SMichael Chan __le32 reserved_size; 5401c0c050c5SMichael Chan __le32 available_size; 5402c0c050c5SMichael Chan u8 unused_0; 5403c0c050c5SMichael Chan u8 unused_1; 5404c0c050c5SMichael Chan u8 unused_2; 5405c0c050c5SMichael Chan u8 valid; 5406c0c050c5SMichael Chan }; 5407c0c050c5SMichael Chan 5408c0c050c5SMichael Chan /* hwrm_nvm_mod_dir_entry */ 5409c0c050c5SMichael Chan /* Input (32 bytes) */ 5410c0c050c5SMichael Chan struct hwrm_nvm_mod_dir_entry_input { 5411c0c050c5SMichael Chan __le16 req_type; 5412c0c050c5SMichael Chan __le16 cmpl_ring; 5413c0c050c5SMichael Chan __le16 seq_id; 5414c0c050c5SMichael Chan __le16 target_id; 5415c0c050c5SMichael Chan __le64 resp_addr; 5416c0c050c5SMichael Chan __le32 enables; 5417c0c050c5SMichael Chan #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 5418c0c050c5SMichael Chan __le16 dir_idx; 5419c0c050c5SMichael Chan __le16 dir_ordinal; 5420c0c050c5SMichael Chan __le16 dir_ext; 5421c0c050c5SMichael Chan __le16 dir_attr; 5422c0c050c5SMichael Chan __le32 checksum; 5423c0c050c5SMichael Chan }; 5424c0c050c5SMichael Chan 5425c0c050c5SMichael Chan /* Output (16 bytes) */ 5426c0c050c5SMichael Chan struct hwrm_nvm_mod_dir_entry_output { 5427c0c050c5SMichael Chan __le16 error_code; 5428c0c050c5SMichael Chan __le16 req_type; 5429c0c050c5SMichael Chan __le16 seq_id; 5430c0c050c5SMichael Chan __le16 resp_len; 5431c0c050c5SMichael Chan __le32 unused_0; 5432c0c050c5SMichael Chan u8 unused_1; 5433c0c050c5SMichael Chan u8 unused_2; 5434c0c050c5SMichael Chan u8 unused_3; 5435c0c050c5SMichael Chan u8 valid; 5436c0c050c5SMichael Chan }; 5437c0c050c5SMichael Chan 5438c0c050c5SMichael Chan /* hwrm_nvm_verify_update */ 5439c0c050c5SMichael Chan /* Input (24 bytes) */ 5440c0c050c5SMichael Chan struct hwrm_nvm_verify_update_input { 5441c0c050c5SMichael Chan __le16 req_type; 5442c0c050c5SMichael Chan __le16 cmpl_ring; 5443c0c050c5SMichael Chan __le16 seq_id; 5444c0c050c5SMichael Chan __le16 target_id; 5445c0c050c5SMichael Chan __le64 resp_addr; 5446c0c050c5SMichael Chan __le16 dir_type; 5447c0c050c5SMichael Chan __le16 dir_ordinal; 5448c0c050c5SMichael Chan __le16 dir_ext; 5449c0c050c5SMichael Chan __le16 unused_0; 5450c0c050c5SMichael Chan }; 5451c0c050c5SMichael Chan 5452c0c050c5SMichael Chan /* Output (16 bytes) */ 5453c0c050c5SMichael Chan struct hwrm_nvm_verify_update_output { 5454c0c050c5SMichael Chan __le16 error_code; 5455c0c050c5SMichael Chan __le16 req_type; 5456c0c050c5SMichael Chan __le16 seq_id; 5457c0c050c5SMichael Chan __le16 resp_len; 5458c0c050c5SMichael Chan __le32 unused_0; 5459c0c050c5SMichael Chan u8 unused_1; 5460c0c050c5SMichael Chan u8 unused_2; 5461c0c050c5SMichael Chan u8 unused_3; 5462c0c050c5SMichael Chan u8 valid; 5463c0c050c5SMichael Chan }; 5464c0c050c5SMichael Chan 5465441cabbbSMichael Chan /* hwrm_nvm_install_update */ 5466441cabbbSMichael Chan /* Input (24 bytes) */ 5467441cabbbSMichael Chan struct hwrm_nvm_install_update_input { 5468441cabbbSMichael Chan __le16 req_type; 5469441cabbbSMichael Chan __le16 cmpl_ring; 5470441cabbbSMichael Chan __le16 seq_id; 5471441cabbbSMichael Chan __le16 target_id; 5472441cabbbSMichael Chan __le64 resp_addr; 5473441cabbbSMichael Chan __le32 install_type; 5474441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 5475441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 5476f183886cSMichael Chan __le16 flags; 5477bac9a7e0SMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 5478bac9a7e0SMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 5479bac9a7e0SMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 5480f183886cSMichael Chan __le16 unused_0; 5481441cabbbSMichael Chan }; 5482441cabbbSMichael Chan 5483441cabbbSMichael Chan /* Output (24 bytes) */ 5484441cabbbSMichael Chan struct hwrm_nvm_install_update_output { 5485441cabbbSMichael Chan __le16 error_code; 5486441cabbbSMichael Chan __le16 req_type; 5487441cabbbSMichael Chan __le16 seq_id; 5488441cabbbSMichael Chan __le16 resp_len; 5489441cabbbSMichael Chan __le64 installed_items; 5490441cabbbSMichael Chan u8 result; 5491441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 5492441cabbbSMichael Chan u8 problem_item; 5493441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 5494441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 5495441cabbbSMichael Chan u8 reset_required; 5496441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 5497441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 5498441cabbbSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 5499441cabbbSMichael Chan u8 unused_0; 5500441cabbbSMichael Chan u8 unused_1; 5501441cabbbSMichael Chan u8 unused_2; 5502441cabbbSMichael Chan u8 unused_3; 5503441cabbbSMichael Chan u8 valid; 5504441cabbbSMichael Chan }; 5505441cabbbSMichael Chan 5506bac9a7e0SMichael Chan /* Command specific Error Codes (8 bytes) */ 5507bac9a7e0SMichael Chan struct hwrm_nvm_install_update_cmd_err { 5508bac9a7e0SMichael Chan u8 code; 5509bac9a7e0SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 5510bac9a7e0SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5511bac9a7e0SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 5512bac9a7e0SMichael Chan u8 unused_0[7]; 5513bac9a7e0SMichael Chan }; 5514bac9a7e0SMichael Chan 55158eb992e8SMichael Chan /* hwrm_selftest_qlist */ 55168eb992e8SMichael Chan /* Input (16 bytes) */ 55178eb992e8SMichael Chan struct hwrm_selftest_qlist_input { 55188eb992e8SMichael Chan __le16 req_type; 55198eb992e8SMichael Chan __le16 cmpl_ring; 55208eb992e8SMichael Chan __le16 seq_id; 55218eb992e8SMichael Chan __le16 target_id; 55228eb992e8SMichael Chan __le64 resp_addr; 55238eb992e8SMichael Chan }; 55248eb992e8SMichael Chan 55258eb992e8SMichael Chan /* Output (248 bytes) */ 55268eb992e8SMichael Chan struct hwrm_selftest_qlist_output { 55278eb992e8SMichael Chan __le16 error_code; 55288eb992e8SMichael Chan __le16 req_type; 55298eb992e8SMichael Chan __le16 seq_id; 55308eb992e8SMichael Chan __le16 resp_len; 55318eb992e8SMichael Chan u8 num_tests; 55328eb992e8SMichael Chan u8 available_tests; 55338eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 55348eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 55358eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 55368eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 55378eb992e8SMichael Chan u8 offline_tests; 55388eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 55398eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 55408eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 55418eb992e8SMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 55428eb992e8SMichael Chan u8 unused_0; 55438eb992e8SMichael Chan __le16 test_timeout; 55448eb992e8SMichael Chan u8 unused_1; 55458eb992e8SMichael Chan u8 unused_2; 55468eb992e8SMichael Chan char test0_name[32]; 55478eb992e8SMichael Chan char test1_name[32]; 55488eb992e8SMichael Chan char test2_name[32]; 55498eb992e8SMichael Chan char test3_name[32]; 55508eb992e8SMichael Chan char test4_name[32]; 55518eb992e8SMichael Chan char test5_name[32]; 55528eb992e8SMichael Chan char test6_name[32]; 55538eb992e8SMichael Chan char test7_name[32]; 55548eb992e8SMichael Chan }; 55558eb992e8SMichael Chan 55568eb992e8SMichael Chan /* hwrm_selftest_exec */ 55578eb992e8SMichael Chan /* Input (24 bytes) */ 55588eb992e8SMichael Chan struct hwrm_selftest_exec_input { 55598eb992e8SMichael Chan __le16 req_type; 55608eb992e8SMichael Chan __le16 cmpl_ring; 55618eb992e8SMichael Chan __le16 seq_id; 55628eb992e8SMichael Chan __le16 target_id; 55638eb992e8SMichael Chan __le64 resp_addr; 55648eb992e8SMichael Chan u8 flags; 55658eb992e8SMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 55668eb992e8SMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 55678eb992e8SMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 55688eb992e8SMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 55698eb992e8SMichael Chan u8 unused_0[7]; 55708eb992e8SMichael Chan }; 55718eb992e8SMichael Chan 55728eb992e8SMichael Chan /* Output (16 bytes) */ 55738eb992e8SMichael Chan struct hwrm_selftest_exec_output { 55748eb992e8SMichael Chan __le16 error_code; 55758eb992e8SMichael Chan __le16 req_type; 55768eb992e8SMichael Chan __le16 seq_id; 55778eb992e8SMichael Chan __le16 resp_len; 55788eb992e8SMichael Chan u8 requested_tests; 55798eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 55808eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 55818eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 55828eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 55838eb992e8SMichael Chan u8 test_success; 55848eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 55858eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 55868eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 55878eb992e8SMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 55888eb992e8SMichael Chan __le16 unused_0[3]; 55898eb992e8SMichael Chan }; 55908eb992e8SMichael Chan 55918eb992e8SMichael Chan /* hwrm_selftest_irq */ 55928eb992e8SMichael Chan /* Input (16 bytes) */ 55938eb992e8SMichael Chan struct hwrm_selftest_irq_input { 55948eb992e8SMichael Chan __le16 req_type; 55958eb992e8SMichael Chan __le16 cmpl_ring; 55968eb992e8SMichael Chan __le16 seq_id; 55978eb992e8SMichael Chan __le16 target_id; 55988eb992e8SMichael Chan __le64 resp_addr; 55998eb992e8SMichael Chan }; 56008eb992e8SMichael Chan 56018eb992e8SMichael Chan /* Output (8 bytes) */ 56028eb992e8SMichael Chan struct hwrm_selftest_irq_output { 56038eb992e8SMichael Chan __le16 error_code; 56048eb992e8SMichael Chan __le16 req_type; 56058eb992e8SMichael Chan __le16 seq_id; 56068eb992e8SMichael Chan __le16 resp_len; 56078eb992e8SMichael Chan }; 56088eb992e8SMichael Chan 560987c374deSMichael Chan /* Hardware Resource Manager Specification */ 561087c374deSMichael Chan /* Input (16 bytes) */ 561187c374deSMichael Chan struct input { 561287c374deSMichael Chan __le16 req_type; 561387c374deSMichael Chan __le16 cmpl_ring; 561487c374deSMichael Chan __le16 seq_id; 561587c374deSMichael Chan __le16 target_id; 561687c374deSMichael Chan __le64 resp_addr; 561787c374deSMichael Chan }; 561887c374deSMichael Chan 561987c374deSMichael Chan /* Output (8 bytes) */ 562087c374deSMichael Chan struct output { 562187c374deSMichael Chan __le16 error_code; 562287c374deSMichael Chan __le16 req_type; 562387c374deSMichael Chan __le16 seq_id; 562487c374deSMichael Chan __le16 resp_len; 562587c374deSMichael Chan }; 562687c374deSMichael Chan 56278eb992e8SMichael Chan /* Short Command Structure (16 bytes) */ 56288eb992e8SMichael Chan struct hwrm_short_input { 56298eb992e8SMichael Chan __le16 req_type; 56308eb992e8SMichael Chan __le16 signature; 56318eb992e8SMichael Chan #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 56328eb992e8SMichael Chan __le16 unused_0; 56338eb992e8SMichael Chan __le16 size; 56348eb992e8SMichael Chan __le64 req_addr; 56358eb992e8SMichael Chan }; 56368eb992e8SMichael Chan 563787c374deSMichael Chan /* Command numbering (8 bytes) */ 563887c374deSMichael Chan struct cmd_nums { 563987c374deSMichael Chan __le16 req_type; 564087c374deSMichael Chan #define HWRM_VER_GET (0x0UL) 564187c374deSMichael Chan #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 564287c374deSMichael Chan #define HWRM_FUNC_VF_CFG (0xfUL) 564387c374deSMichael Chan #define RESERVED1 (0x10UL) 564487c374deSMichael Chan #define HWRM_FUNC_RESET (0x11UL) 564587c374deSMichael Chan #define HWRM_FUNC_GETFID (0x12UL) 564687c374deSMichael Chan #define HWRM_FUNC_VF_ALLOC (0x13UL) 564787c374deSMichael Chan #define HWRM_FUNC_VF_FREE (0x14UL) 564887c374deSMichael Chan #define HWRM_FUNC_QCAPS (0x15UL) 564987c374deSMichael Chan #define HWRM_FUNC_QCFG (0x16UL) 565087c374deSMichael Chan #define HWRM_FUNC_CFG (0x17UL) 565187c374deSMichael Chan #define HWRM_FUNC_QSTATS (0x18UL) 565287c374deSMichael Chan #define HWRM_FUNC_CLR_STATS (0x19UL) 565387c374deSMichael Chan #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 565487c374deSMichael Chan #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 565587c374deSMichael Chan #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 565687c374deSMichael Chan #define HWRM_FUNC_DRV_RGTR (0x1dUL) 565787c374deSMichael Chan #define HWRM_FUNC_DRV_QVER (0x1eUL) 565887c374deSMichael Chan #define HWRM_FUNC_BUF_RGTR (0x1fUL) 565987c374deSMichael Chan #define HWRM_PORT_PHY_CFG (0x20UL) 566087c374deSMichael Chan #define HWRM_PORT_MAC_CFG (0x21UL) 566187c374deSMichael Chan #define HWRM_PORT_TS_QUERY (0x22UL) 566287c374deSMichael Chan #define HWRM_PORT_QSTATS (0x23UL) 566387c374deSMichael Chan #define HWRM_PORT_LPBK_QSTATS (0x24UL) 566487c374deSMichael Chan #define HWRM_PORT_CLR_STATS (0x25UL) 566587c374deSMichael Chan #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 566687c374deSMichael Chan #define HWRM_PORT_PHY_QCFG (0x27UL) 566787c374deSMichael Chan #define HWRM_PORT_MAC_QCFG (0x28UL) 5668acb20054SMichael Chan #define HWRM_PORT_MAC_PTP_QCFG (0x29UL) 566987c374deSMichael Chan #define HWRM_PORT_PHY_QCAPS (0x2aUL) 567087c374deSMichael Chan #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 567187c374deSMichael Chan #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 567287c374deSMichael Chan #define HWRM_PORT_LED_CFG (0x2dUL) 567387c374deSMichael Chan #define HWRM_PORT_LED_QCFG (0x2eUL) 567487c374deSMichael Chan #define HWRM_PORT_LED_QCAPS (0x2fUL) 567587c374deSMichael Chan #define HWRM_QUEUE_QPORTCFG (0x30UL) 567687c374deSMichael Chan #define HWRM_QUEUE_QCFG (0x31UL) 567787c374deSMichael Chan #define HWRM_QUEUE_CFG (0x32UL) 5678acb20054SMichael Chan #define HWRM_FUNC_VLAN_CFG (0x33UL) 5679acb20054SMichael Chan #define HWRM_FUNC_VLAN_QCFG (0x34UL) 568087c374deSMichael Chan #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 568187c374deSMichael Chan #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 568287c374deSMichael Chan #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 568387c374deSMichael Chan #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 568487c374deSMichael Chan #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 568587c374deSMichael Chan #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 5686acb20054SMichael Chan #define HWRM_QUEUE_DSCP_QCAPS (0x3bUL) 5687acb20054SMichael Chan #define HWRM_QUEUE_DSCP2PRI_QCFG (0x3cUL) 5688acb20054SMichael Chan #define HWRM_QUEUE_DSCP2PRI_CFG (0x3dUL) 568987c374deSMichael Chan #define HWRM_VNIC_ALLOC (0x40UL) 569087c374deSMichael Chan #define HWRM_VNIC_FREE (0x41UL) 569187c374deSMichael Chan #define HWRM_VNIC_CFG (0x42UL) 569287c374deSMichael Chan #define HWRM_VNIC_QCFG (0x43UL) 569387c374deSMichael Chan #define HWRM_VNIC_TPA_CFG (0x44UL) 569487c374deSMichael Chan #define HWRM_VNIC_TPA_QCFG (0x45UL) 569587c374deSMichael Chan #define HWRM_VNIC_RSS_CFG (0x46UL) 569687c374deSMichael Chan #define HWRM_VNIC_RSS_QCFG (0x47UL) 569787c374deSMichael Chan #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 569887c374deSMichael Chan #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 569987c374deSMichael Chan #define HWRM_VNIC_QCAPS (0x4aUL) 570087c374deSMichael Chan #define HWRM_RING_ALLOC (0x50UL) 570187c374deSMichael Chan #define HWRM_RING_FREE (0x51UL) 570287c374deSMichael Chan #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 570387c374deSMichael Chan #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 570487c374deSMichael Chan #define HWRM_RING_RESET (0x5eUL) 570587c374deSMichael Chan #define HWRM_RING_GRP_ALLOC (0x60UL) 570687c374deSMichael Chan #define HWRM_RING_GRP_FREE (0x61UL) 570787c374deSMichael Chan #define RESERVED5 (0x64UL) 570887c374deSMichael Chan #define RESERVED6 (0x65UL) 570987c374deSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 571087c374deSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 571187c374deSMichael Chan #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 571287c374deSMichael Chan #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 571387c374deSMichael Chan #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 571487c374deSMichael Chan #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 5715acb20054SMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_CFG (0x94UL) 571687c374deSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 571787c374deSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 571887c374deSMichael Chan #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 571987c374deSMichael Chan #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 572087c374deSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 572187c374deSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 572287c374deSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 572387c374deSMichael Chan #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 572487c374deSMichael Chan #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 572587c374deSMichael Chan #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 572687c374deSMichael Chan #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 572787c374deSMichael Chan #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 572887c374deSMichael Chan #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 572987c374deSMichael Chan #define HWRM_STAT_CTX_ALLOC (0xb0UL) 573087c374deSMichael Chan #define HWRM_STAT_CTX_FREE (0xb1UL) 573187c374deSMichael Chan #define HWRM_STAT_CTX_QUERY (0xb2UL) 573287c374deSMichael Chan #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 573387c374deSMichael Chan #define HWRM_FW_RESET (0xc0UL) 573487c374deSMichael Chan #define HWRM_FW_QSTATUS (0xc1UL) 573587c374deSMichael Chan #define HWRM_FW_SET_TIME (0xc8UL) 573687c374deSMichael Chan #define HWRM_FW_GET_TIME (0xc9UL) 573787c374deSMichael Chan #define HWRM_FW_SET_STRUCTURED_DATA (0xcaUL) 573887c374deSMichael Chan #define HWRM_FW_GET_STRUCTURED_DATA (0xcbUL) 573987c374deSMichael Chan #define HWRM_FW_IPC_MAILBOX (0xccUL) 574087c374deSMichael Chan #define HWRM_EXEC_FWD_RESP (0xd0UL) 574187c374deSMichael Chan #define HWRM_REJECT_FWD_RESP (0xd1UL) 574287c374deSMichael Chan #define HWRM_FWD_RESP (0xd2UL) 574387c374deSMichael Chan #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 574487c374deSMichael Chan #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 574587c374deSMichael Chan #define HWRM_WOL_FILTER_ALLOC (0xf0UL) 574687c374deSMichael Chan #define HWRM_WOL_FILTER_FREE (0xf1UL) 574787c374deSMichael Chan #define HWRM_WOL_FILTER_QCFG (0xf2UL) 574887c374deSMichael Chan #define HWRM_WOL_REASON_QCFG (0xf3UL) 5749bac9a7e0SMichael Chan #define HWRM_CFA_METER_PROFILE_ALLOC (0xf5UL) 5750bac9a7e0SMichael Chan #define HWRM_CFA_METER_PROFILE_FREE (0xf6UL) 5751bac9a7e0SMichael Chan #define HWRM_CFA_METER_PROFILE_CFG (0xf7UL) 5752bac9a7e0SMichael Chan #define HWRM_CFA_METER_INSTANCE_ALLOC (0xf8UL) 5753bac9a7e0SMichael Chan #define HWRM_CFA_METER_INSTANCE_FREE (0xf9UL) 5754acb20054SMichael Chan #define HWRM_CFA_VFR_ALLOC (0xfdUL) 5755acb20054SMichael Chan #define HWRM_CFA_VFR_FREE (0xfeUL) 5756bac9a7e0SMichael Chan #define HWRM_CFA_VF_PAIR_ALLOC (0x100UL) 5757bac9a7e0SMichael Chan #define HWRM_CFA_VF_PAIR_FREE (0x101UL) 5758bac9a7e0SMichael Chan #define HWRM_CFA_VF_PAIR_INFO (0x102UL) 5759bac9a7e0SMichael Chan #define HWRM_CFA_FLOW_ALLOC (0x103UL) 5760bac9a7e0SMichael Chan #define HWRM_CFA_FLOW_FREE (0x104UL) 5761bac9a7e0SMichael Chan #define HWRM_CFA_FLOW_FLUSH (0x105UL) 5762bac9a7e0SMichael Chan #define HWRM_CFA_FLOW_STATS (0x106UL) 5763bac9a7e0SMichael Chan #define HWRM_CFA_FLOW_INFO (0x107UL) 5764acb20054SMichael Chan #define HWRM_CFA_DECAP_FILTER_ALLOC (0x108UL) 5765acb20054SMichael Chan #define HWRM_CFA_DECAP_FILTER_FREE (0x109UL) 5766acb20054SMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_QCFG (0x10aUL) 57678eb992e8SMichael Chan #define HWRM_SELFTEST_QLIST (0x200UL) 57688eb992e8SMichael Chan #define HWRM_SELFTEST_EXEC (0x201UL) 57698eb992e8SMichael Chan #define HWRM_SELFTEST_IRQ (0x202UL) 577087c374deSMichael Chan #define HWRM_DBG_READ_DIRECT (0xff10UL) 577187c374deSMichael Chan #define HWRM_DBG_READ_INDIRECT (0xff11UL) 577287c374deSMichael Chan #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 577387c374deSMichael Chan #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 577487c374deSMichael Chan #define HWRM_DBG_DUMP (0xff14UL) 5775acb20054SMichael Chan #define HWRM_DBG_ERASE_NVM (0xff15UL) 5776acb20054SMichael Chan #define HWRM_DBG_CFG (0xff16UL) 57778eb992e8SMichael Chan #define HWRM_NVM_FACTORY_DEFAULTS (0xffeeUL) 5778bac9a7e0SMichael Chan #define HWRM_NVM_VALIDATE_OPTION (0xffefUL) 5779bac9a7e0SMichael Chan #define HWRM_NVM_FLUSH (0xfff0UL) 578087c374deSMichael Chan #define HWRM_NVM_GET_VARIABLE (0xfff1UL) 578187c374deSMichael Chan #define HWRM_NVM_SET_VARIABLE (0xfff2UL) 578287c374deSMichael Chan #define HWRM_NVM_INSTALL_UPDATE (0xfff3UL) 578387c374deSMichael Chan #define HWRM_NVM_MODIFY (0xfff4UL) 578487c374deSMichael Chan #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 578587c374deSMichael Chan #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 578687c374deSMichael Chan #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 578787c374deSMichael Chan #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 578887c374deSMichael Chan #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 578987c374deSMichael Chan #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 579087c374deSMichael Chan #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 579187c374deSMichael Chan #define HWRM_NVM_RAW_DUMP (0xfffcUL) 579287c374deSMichael Chan #define HWRM_NVM_READ (0xfffdUL) 579387c374deSMichael Chan #define HWRM_NVM_WRITE (0xfffeUL) 579487c374deSMichael Chan #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 579587c374deSMichael Chan __le16 unused_0[3]; 579687c374deSMichael Chan }; 579787c374deSMichael Chan 579887c374deSMichael Chan /* Return Codes (8 bytes) */ 579987c374deSMichael Chan struct ret_codes { 580087c374deSMichael Chan __le16 error_code; 580187c374deSMichael Chan #define HWRM_ERR_CODE_SUCCESS (0x0UL) 580287c374deSMichael Chan #define HWRM_ERR_CODE_FAIL (0x1UL) 580387c374deSMichael Chan #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 580487c374deSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 580587c374deSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 580687c374deSMichael Chan #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 580787c374deSMichael Chan #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 580887c374deSMichael Chan #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 580987c374deSMichael Chan #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 581087c374deSMichael Chan #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 581187c374deSMichael Chan __le16 unused_0[3]; 581287c374deSMichael Chan }; 581387c374deSMichael Chan 581487c374deSMichael Chan /* Output (16 bytes) */ 581587c374deSMichael Chan struct hwrm_err_output { 581687c374deSMichael Chan __le16 error_code; 581787c374deSMichael Chan __le16 req_type; 581887c374deSMichael Chan __le16 seq_id; 581987c374deSMichael Chan __le16 resp_len; 582087c374deSMichael Chan __le32 opaque_0; 582187c374deSMichael Chan __le16 opaque_1; 582287c374deSMichael Chan u8 cmd_err; 582387c374deSMichael Chan u8 valid; 582487c374deSMichael Chan }; 582587c374deSMichael Chan 582687c374deSMichael Chan /* Port Tx Statistics Formats (408 bytes) */ 582787c374deSMichael Chan struct tx_port_stats { 582887c374deSMichael Chan __le64 tx_64b_frames; 582987c374deSMichael Chan __le64 tx_65b_127b_frames; 583087c374deSMichael Chan __le64 tx_128b_255b_frames; 583187c374deSMichael Chan __le64 tx_256b_511b_frames; 583287c374deSMichael Chan __le64 tx_512b_1023b_frames; 583387c374deSMichael Chan __le64 tx_1024b_1518_frames; 583487c374deSMichael Chan __le64 tx_good_vlan_frames; 583587c374deSMichael Chan __le64 tx_1519b_2047_frames; 583687c374deSMichael Chan __le64 tx_2048b_4095b_frames; 583787c374deSMichael Chan __le64 tx_4096b_9216b_frames; 583887c374deSMichael Chan __le64 tx_9217b_16383b_frames; 583987c374deSMichael Chan __le64 tx_good_frames; 584087c374deSMichael Chan __le64 tx_total_frames; 584187c374deSMichael Chan __le64 tx_ucast_frames; 584287c374deSMichael Chan __le64 tx_mcast_frames; 584387c374deSMichael Chan __le64 tx_bcast_frames; 584487c374deSMichael Chan __le64 tx_pause_frames; 584587c374deSMichael Chan __le64 tx_pfc_frames; 584687c374deSMichael Chan __le64 tx_jabber_frames; 584787c374deSMichael Chan __le64 tx_fcs_err_frames; 584887c374deSMichael Chan __le64 tx_control_frames; 584987c374deSMichael Chan __le64 tx_oversz_frames; 585087c374deSMichael Chan __le64 tx_single_dfrl_frames; 585187c374deSMichael Chan __le64 tx_multi_dfrl_frames; 585287c374deSMichael Chan __le64 tx_single_coll_frames; 585387c374deSMichael Chan __le64 tx_multi_coll_frames; 585487c374deSMichael Chan __le64 tx_late_coll_frames; 585587c374deSMichael Chan __le64 tx_excessive_coll_frames; 585687c374deSMichael Chan __le64 tx_frag_frames; 585787c374deSMichael Chan __le64 tx_err; 585887c374deSMichael Chan __le64 tx_tagged_frames; 585987c374deSMichael Chan __le64 tx_dbl_tagged_frames; 586087c374deSMichael Chan __le64 tx_runt_frames; 586187c374deSMichael Chan __le64 tx_fifo_underruns; 586287c374deSMichael Chan __le64 tx_pfc_ena_frames_pri0; 586387c374deSMichael Chan __le64 tx_pfc_ena_frames_pri1; 586487c374deSMichael Chan __le64 tx_pfc_ena_frames_pri2; 586587c374deSMichael Chan __le64 tx_pfc_ena_frames_pri3; 586687c374deSMichael Chan __le64 tx_pfc_ena_frames_pri4; 586787c374deSMichael Chan __le64 tx_pfc_ena_frames_pri5; 586887c374deSMichael Chan __le64 tx_pfc_ena_frames_pri6; 586987c374deSMichael Chan __le64 tx_pfc_ena_frames_pri7; 587087c374deSMichael Chan __le64 tx_eee_lpi_events; 587187c374deSMichael Chan __le64 tx_eee_lpi_duration; 587287c374deSMichael Chan __le64 tx_llfc_logical_msgs; 587387c374deSMichael Chan __le64 tx_hcfc_msgs; 587487c374deSMichael Chan __le64 tx_total_collisions; 587587c374deSMichael Chan __le64 tx_bytes; 587687c374deSMichael Chan __le64 tx_xthol_frames; 587787c374deSMichael Chan __le64 tx_stat_discard; 587887c374deSMichael Chan __le64 tx_stat_error; 587987c374deSMichael Chan }; 588087c374deSMichael Chan 588187c374deSMichael Chan /* Port Rx Statistics Formats (528 bytes) */ 588287c374deSMichael Chan struct rx_port_stats { 588387c374deSMichael Chan __le64 rx_64b_frames; 588487c374deSMichael Chan __le64 rx_65b_127b_frames; 588587c374deSMichael Chan __le64 rx_128b_255b_frames; 588687c374deSMichael Chan __le64 rx_256b_511b_frames; 588787c374deSMichael Chan __le64 rx_512b_1023b_frames; 588887c374deSMichael Chan __le64 rx_1024b_1518_frames; 588987c374deSMichael Chan __le64 rx_good_vlan_frames; 589087c374deSMichael Chan __le64 rx_1519b_2047b_frames; 589187c374deSMichael Chan __le64 rx_2048b_4095b_frames; 589287c374deSMichael Chan __le64 rx_4096b_9216b_frames; 589387c374deSMichael Chan __le64 rx_9217b_16383b_frames; 589487c374deSMichael Chan __le64 rx_total_frames; 589587c374deSMichael Chan __le64 rx_ucast_frames; 589687c374deSMichael Chan __le64 rx_mcast_frames; 589787c374deSMichael Chan __le64 rx_bcast_frames; 589887c374deSMichael Chan __le64 rx_fcs_err_frames; 589987c374deSMichael Chan __le64 rx_ctrl_frames; 590087c374deSMichael Chan __le64 rx_pause_frames; 590187c374deSMichael Chan __le64 rx_pfc_frames; 590287c374deSMichael Chan __le64 rx_unsupported_opcode_frames; 590387c374deSMichael Chan __le64 rx_unsupported_da_pausepfc_frames; 590487c374deSMichael Chan __le64 rx_wrong_sa_frames; 590587c374deSMichael Chan __le64 rx_align_err_frames; 590687c374deSMichael Chan __le64 rx_oor_len_frames; 590787c374deSMichael Chan __le64 rx_code_err_frames; 590887c374deSMichael Chan __le64 rx_false_carrier_frames; 590987c374deSMichael Chan __le64 rx_ovrsz_frames; 591087c374deSMichael Chan __le64 rx_jbr_frames; 591187c374deSMichael Chan __le64 rx_mtu_err_frames; 591287c374deSMichael Chan __le64 rx_match_crc_frames; 591387c374deSMichael Chan __le64 rx_promiscuous_frames; 591487c374deSMichael Chan __le64 rx_tagged_frames; 591587c374deSMichael Chan __le64 rx_double_tagged_frames; 591687c374deSMichael Chan __le64 rx_trunc_frames; 591787c374deSMichael Chan __le64 rx_good_frames; 591887c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri0; 591987c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri1; 592087c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri2; 592187c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri3; 592287c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri4; 592387c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri5; 592487c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri6; 592587c374deSMichael Chan __le64 rx_pfc_xon2xoff_frames_pri7; 592687c374deSMichael Chan __le64 rx_pfc_ena_frames_pri0; 592787c374deSMichael Chan __le64 rx_pfc_ena_frames_pri1; 592887c374deSMichael Chan __le64 rx_pfc_ena_frames_pri2; 592987c374deSMichael Chan __le64 rx_pfc_ena_frames_pri3; 593087c374deSMichael Chan __le64 rx_pfc_ena_frames_pri4; 593187c374deSMichael Chan __le64 rx_pfc_ena_frames_pri5; 593287c374deSMichael Chan __le64 rx_pfc_ena_frames_pri6; 593387c374deSMichael Chan __le64 rx_pfc_ena_frames_pri7; 593487c374deSMichael Chan __le64 rx_sch_crc_err_frames; 593587c374deSMichael Chan __le64 rx_undrsz_frames; 593687c374deSMichael Chan __le64 rx_frag_frames; 593787c374deSMichael Chan __le64 rx_eee_lpi_events; 593887c374deSMichael Chan __le64 rx_eee_lpi_duration; 593987c374deSMichael Chan __le64 rx_llfc_physical_msgs; 594087c374deSMichael Chan __le64 rx_llfc_logical_msgs; 594187c374deSMichael Chan __le64 rx_llfc_msgs_with_crc_err; 594287c374deSMichael Chan __le64 rx_hcfc_msgs; 594387c374deSMichael Chan __le64 rx_hcfc_msgs_with_crc_err; 594487c374deSMichael Chan __le64 rx_bytes; 594587c374deSMichael Chan __le64 rx_runt_bytes; 594687c374deSMichael Chan __le64 rx_runt_frames; 594787c374deSMichael Chan __le64 rx_stat_discard; 594887c374deSMichael Chan __le64 rx_stat_err; 594987c374deSMichael Chan }; 595087c374deSMichael Chan 595187c374deSMichael Chan /* Periodic Statistics Context DMA to host (160 bytes) */ 595287c374deSMichael Chan struct ctx_hw_stats { 595387c374deSMichael Chan __le64 rx_ucast_pkts; 595487c374deSMichael Chan __le64 rx_mcast_pkts; 595587c374deSMichael Chan __le64 rx_bcast_pkts; 595687c374deSMichael Chan __le64 rx_discard_pkts; 595787c374deSMichael Chan __le64 rx_drop_pkts; 595887c374deSMichael Chan __le64 rx_ucast_bytes; 595987c374deSMichael Chan __le64 rx_mcast_bytes; 596087c374deSMichael Chan __le64 rx_bcast_bytes; 596187c374deSMichael Chan __le64 tx_ucast_pkts; 596287c374deSMichael Chan __le64 tx_mcast_pkts; 596387c374deSMichael Chan __le64 tx_bcast_pkts; 596487c374deSMichael Chan __le64 tx_discard_pkts; 596587c374deSMichael Chan __le64 tx_drop_pkts; 596687c374deSMichael Chan __le64 tx_ucast_bytes; 596787c374deSMichael Chan __le64 tx_mcast_bytes; 596887c374deSMichael Chan __le64 tx_bcast_bytes; 596987c374deSMichael Chan __le64 tpa_pkts; 597087c374deSMichael Chan __le64 tpa_bytes; 597187c374deSMichael Chan __le64 tpa_events; 597287c374deSMichael Chan __le64 tpa_aborts; 597387c374deSMichael Chan }; 597487c374deSMichael Chan 597587c374deSMichael Chan /* Structure data header (16 bytes) */ 597687c374deSMichael Chan struct hwrm_struct_hdr { 597787c374deSMichael Chan __le16 struct_id; 597887c374deSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 5979f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 5980f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 5981f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 5982f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 5983f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 5984f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 59858eb992e8SMichael Chan #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 5986f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 598787c374deSMichael Chan __le16 len; 598887c374deSMichael Chan u8 version; 598987c374deSMichael Chan u8 count; 599087c374deSMichael Chan __le16 subtype; 599187c374deSMichael Chan __le16 next_offset; 599287c374deSMichael Chan #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 599387c374deSMichael Chan __le16 unused_0[3]; 599487c374deSMichael Chan }; 599587c374deSMichael Chan 5996f183886cSMichael Chan /* DCBX Application configuration structure (1057) (8 bytes) */ 5997f183886cSMichael Chan struct hwrm_struct_data_dcbx_app { 5998f183886cSMichael Chan __be16 protocol_id; 599987c374deSMichael Chan u8 protocol_selector; 6000f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 6001f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 6002f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 6003f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 600487c374deSMichael Chan u8 priority; 600587c374deSMichael Chan u8 valid; 600687c374deSMichael Chan u8 unused_0[3]; 600787c374deSMichael Chan }; 600887c374deSMichael Chan 6009c0c050c5SMichael Chan #endif 6010