1c0c050c5SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2c0c050c5SMichael Chan * 311f15ed3SMichael Chan * Copyright (c) 2014-2016 Broadcom Corporation 42792b5b9SMichael Chan * Copyright (c) 2014-2018 Broadcom Limited 5ad04cc05SMichael Chan * Copyright (c) 2018-2022 Broadcom Inc. 6c0c050c5SMichael Chan * 7c0c050c5SMichael Chan * This program is free software; you can redistribute it and/or modify 8c0c050c5SMichael Chan * it under the terms of the GNU General Public License as published by 9c0c050c5SMichael Chan * the Free Software Foundation. 10894aa69aSMichael Chan * 11894aa69aSMichael Chan * DO NOT MODIFY!!! This file is automatically generated. 12c0c050c5SMichael Chan */ 13c0c050c5SMichael Chan 14894aa69aSMichael Chan #ifndef _BNXT_HSI_H_ 15894aa69aSMichael Chan #define _BNXT_HSI_H_ 16c0c050c5SMichael Chan 17894aa69aSMichael Chan /* hwrm_cmd_hdr (size:128b/16B) */ 18894aa69aSMichael Chan struct hwrm_cmd_hdr { 19894aa69aSMichael Chan __le16 req_type; 20894aa69aSMichael Chan __le16 cmpl_ring; 21894aa69aSMichael Chan __le16 seq_id; 22894aa69aSMichael Chan __le16 target_id; 23894aa69aSMichael Chan __le64 resp_addr; 24894aa69aSMichael Chan }; 2587c374deSMichael Chan 26894aa69aSMichael Chan /* hwrm_resp_hdr (size:64b/8B) */ 27894aa69aSMichael Chan struct hwrm_resp_hdr { 28894aa69aSMichael Chan __le16 error_code; 29894aa69aSMichael Chan __le16 req_type; 30894aa69aSMichael Chan __le16 seq_id; 31894aa69aSMichael Chan __le16 resp_len; 32894aa69aSMichael Chan }; 338eb992e8SMichael Chan 34894aa69aSMichael Chan #define CMD_DISCR_TLV_ENCAP 0x8000UL 35894aa69aSMichael Chan #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36894aa69aSMichael Chan 37894aa69aSMichael Chan 38894aa69aSMichael Chan #define TLV_TYPE_HWRM_REQUEST 0x1UL 39894aa69aSMichael Chan #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40894aa69aSMichael Chan #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 4131d357c0SMichael Chan #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 4231d357c0SMichael Chan #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 432792b5b9SMichael Chan #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 4772e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 482792b5b9SMichael Chan #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 5072e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 5172e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 5272e0c9f9SMichael Chan #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53894aa69aSMichael Chan 54894aa69aSMichael Chan 55894aa69aSMichael Chan /* tlv (size:64b/8B) */ 56894aa69aSMichael Chan struct tlv { 57894aa69aSMichael Chan __le16 cmd_discr; 58894aa69aSMichael Chan u8 reserved_8b; 59894aa69aSMichael Chan u8 flags; 60894aa69aSMichael Chan #define TLV_FLAGS_MORE 0x1UL 61894aa69aSMichael Chan #define TLV_FLAGS_MORE_LAST 0x0UL 62894aa69aSMichael Chan #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED 0x2UL 64894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67894aa69aSMichael Chan __le16 tlv_type; 68894aa69aSMichael Chan __le16 length; 69894aa69aSMichael Chan }; 70894aa69aSMichael Chan 71894aa69aSMichael Chan /* input (size:128b/16B) */ 72894aa69aSMichael Chan struct input { 73894aa69aSMichael Chan __le16 req_type; 74894aa69aSMichael Chan __le16 cmpl_ring; 75894aa69aSMichael Chan __le16 seq_id; 76894aa69aSMichael Chan __le16 target_id; 77894aa69aSMichael Chan __le64 resp_addr; 78894aa69aSMichael Chan }; 79894aa69aSMichael Chan 80894aa69aSMichael Chan /* output (size:64b/8B) */ 81894aa69aSMichael Chan struct output { 82894aa69aSMichael Chan __le16 error_code; 83894aa69aSMichael Chan __le16 req_type; 84894aa69aSMichael Chan __le16 seq_id; 85894aa69aSMichael Chan __le16 resp_len; 86894aa69aSMichael Chan }; 87894aa69aSMichael Chan 88894aa69aSMichael Chan /* hwrm_short_input (size:128b/16B) */ 89894aa69aSMichael Chan struct hwrm_short_input { 90894aa69aSMichael Chan __le16 req_type; 91894aa69aSMichael Chan __le16 signature; 92894aa69aSMichael Chan #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93894aa69aSMichael Chan #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 944a50ddc2SMichael Chan __le16 target_id; 954a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 964a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 974a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98894aa69aSMichael Chan __le16 size; 99894aa69aSMichael Chan __le64 req_addr; 100894aa69aSMichael Chan }; 101894aa69aSMichael Chan 102894aa69aSMichael Chan /* cmd_nums (size:64b/8B) */ 103894aa69aSMichael Chan struct cmd_nums { 104894aa69aSMichael Chan __le16 req_type; 105894aa69aSMichael Chan #define HWRM_VER_GET 0x0UL 10631f67c2eSMichael Chan #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 1073293ec23SMichael Chan #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 1086fc92c33SMichael Chan #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109894aa69aSMichael Chan #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110894aa69aSMichael Chan #define HWRM_FUNC_VF_CFG 0xfUL 111894aa69aSMichael Chan #define HWRM_RESERVED1 0x10UL 112894aa69aSMichael Chan #define HWRM_FUNC_RESET 0x11UL 113894aa69aSMichael Chan #define HWRM_FUNC_GETFID 0x12UL 114894aa69aSMichael Chan #define HWRM_FUNC_VF_ALLOC 0x13UL 115894aa69aSMichael Chan #define HWRM_FUNC_VF_FREE 0x14UL 116894aa69aSMichael Chan #define HWRM_FUNC_QCAPS 0x15UL 117894aa69aSMichael Chan #define HWRM_FUNC_QCFG 0x16UL 118894aa69aSMichael Chan #define HWRM_FUNC_CFG 0x17UL 119894aa69aSMichael Chan #define HWRM_FUNC_QSTATS 0x18UL 120894aa69aSMichael Chan #define HWRM_FUNC_CLR_STATS 0x19UL 121894aa69aSMichael Chan #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122894aa69aSMichael Chan #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123894aa69aSMichael Chan #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124894aa69aSMichael Chan #define HWRM_FUNC_DRV_RGTR 0x1dUL 125894aa69aSMichael Chan #define HWRM_FUNC_DRV_QVER 0x1eUL 126894aa69aSMichael Chan #define HWRM_FUNC_BUF_RGTR 0x1fUL 127894aa69aSMichael Chan #define HWRM_PORT_PHY_CFG 0x20UL 128894aa69aSMichael Chan #define HWRM_PORT_MAC_CFG 0x21UL 129894aa69aSMichael Chan #define HWRM_PORT_TS_QUERY 0x22UL 130894aa69aSMichael Chan #define HWRM_PORT_QSTATS 0x23UL 131894aa69aSMichael Chan #define HWRM_PORT_LPBK_QSTATS 0x24UL 132894aa69aSMichael Chan #define HWRM_PORT_CLR_STATS 0x25UL 133894aa69aSMichael Chan #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134894aa69aSMichael Chan #define HWRM_PORT_PHY_QCFG 0x27UL 135894aa69aSMichael Chan #define HWRM_PORT_MAC_QCFG 0x28UL 136894aa69aSMichael Chan #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137894aa69aSMichael Chan #define HWRM_PORT_PHY_QCAPS 0x2aUL 138894aa69aSMichael Chan #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139894aa69aSMichael Chan #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140894aa69aSMichael Chan #define HWRM_PORT_LED_CFG 0x2dUL 141894aa69aSMichael Chan #define HWRM_PORT_LED_QCFG 0x2eUL 142894aa69aSMichael Chan #define HWRM_PORT_LED_QCAPS 0x2fUL 143894aa69aSMichael Chan #define HWRM_QUEUE_QPORTCFG 0x30UL 144894aa69aSMichael Chan #define HWRM_QUEUE_QCFG 0x31UL 145894aa69aSMichael Chan #define HWRM_QUEUE_CFG 0x32UL 146894aa69aSMichael Chan #define HWRM_FUNC_VLAN_CFG 0x33UL 147894aa69aSMichael Chan #define HWRM_FUNC_VLAN_QCFG 0x34UL 148894aa69aSMichael Chan #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149894aa69aSMichael Chan #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150894aa69aSMichael Chan #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151894aa69aSMichael Chan #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152894aa69aSMichael Chan #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153894aa69aSMichael Chan #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154894aa69aSMichael Chan #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155894aa69aSMichael Chan #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156894aa69aSMichael Chan #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157894aa69aSMichael Chan #define HWRM_VNIC_ALLOC 0x40UL 158894aa69aSMichael Chan #define HWRM_VNIC_FREE 0x41UL 159894aa69aSMichael Chan #define HWRM_VNIC_CFG 0x42UL 160894aa69aSMichael Chan #define HWRM_VNIC_QCFG 0x43UL 161894aa69aSMichael Chan #define HWRM_VNIC_TPA_CFG 0x44UL 162894aa69aSMichael Chan #define HWRM_VNIC_TPA_QCFG 0x45UL 163894aa69aSMichael Chan #define HWRM_VNIC_RSS_CFG 0x46UL 164894aa69aSMichael Chan #define HWRM_VNIC_RSS_QCFG 0x47UL 165894aa69aSMichael Chan #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166894aa69aSMichael Chan #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167894aa69aSMichael Chan #define HWRM_VNIC_QCAPS 0x4aUL 16816db6323SMichael Chan #define HWRM_VNIC_UPDATE 0x4bUL 169894aa69aSMichael Chan #define HWRM_RING_ALLOC 0x50UL 170894aa69aSMichael Chan #define HWRM_RING_FREE 0x51UL 171894aa69aSMichael Chan #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172894aa69aSMichael Chan #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 1736fc92c33SMichael Chan #define HWRM_RING_AGGINT_QCAPS 0x54UL 174bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_ALLOC 0x55UL 175bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_CFG 0x56UL 176bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_FREE 0x57UL 177894aa69aSMichael Chan #define HWRM_RING_RESET 0x5eUL 178894aa69aSMichael Chan #define HWRM_RING_GRP_ALLOC 0x60UL 179894aa69aSMichael Chan #define HWRM_RING_GRP_FREE 0x61UL 180bfc6e5fbSMichael Chan #define HWRM_RING_CFG 0x62UL 181bfc6e5fbSMichael Chan #define HWRM_RING_QCFG 0x63UL 182894aa69aSMichael Chan #define HWRM_RESERVED5 0x64UL 183894aa69aSMichael Chan #define HWRM_RESERVED6 0x65UL 184894aa69aSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185894aa69aSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 18641136ab3SMichael Chan #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 18741136ab3SMichael Chan #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 18841136ab3SMichael Chan #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 18916db6323SMichael Chan #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 19016db6323SMichael Chan #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 19116db6323SMichael Chan #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 19278eeadb8SMichael Chan #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 19378eeadb8SMichael Chan #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197894aa69aSMichael Chan #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198894aa69aSMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199894aa69aSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200894aa69aSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201894aa69aSMichael Chan #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202894aa69aSMichael Chan #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 21231d357c0SMichael Chan #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213894aa69aSMichael Chan #define HWRM_STAT_CTX_ALLOC 0xb0UL 214894aa69aSMichael Chan #define HWRM_STAT_CTX_FREE 0xb1UL 215894aa69aSMichael Chan #define HWRM_STAT_CTX_QUERY 0xb2UL 216894aa69aSMichael Chan #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217d4f52de0SMichael Chan #define HWRM_PORT_QSTATS_EXT 0xb4UL 2183322479eSMichael Chan #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 2193322479eSMichael Chan #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 22072e0c9f9SMichael Chan #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 22172e0c9f9SMichael Chan #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222460c2577SMichael Chan #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 2239d6b648cSMichael Chan #define HWRM_RESERVED7 0xbaUL 2249d6b648cSMichael Chan #define HWRM_PORT_TX_FIR_CFG 0xbbUL 2259d6b648cSMichael Chan #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 2269d6b648cSMichael Chan #define HWRM_PORT_ECN_QSTATS 0xbdUL 22716db6323SMichael Chan #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 22816db6323SMichael Chan #define HWRM_FW_LIVEPATCH 0xbfUL 229894aa69aSMichael Chan #define HWRM_FW_RESET 0xc0UL 230894aa69aSMichael Chan #define HWRM_FW_QSTATUS 0xc1UL 2316fc92c33SMichael Chan #define HWRM_FW_HEALTH_CHECK 0xc2UL 2326fc92c33SMichael Chan #define HWRM_FW_SYNC 0xc3UL 23341136ab3SMichael Chan #define HWRM_FW_STATE_QCAPS 0xc4UL 23472e0c9f9SMichael Chan #define HWRM_FW_STATE_QUIESCE 0xc5UL 23572e0c9f9SMichael Chan #define HWRM_FW_STATE_BACKUP 0xc6UL 23672e0c9f9SMichael Chan #define HWRM_FW_STATE_RESTORE 0xc7UL 237894aa69aSMichael Chan #define HWRM_FW_SET_TIME 0xc8UL 238894aa69aSMichael Chan #define HWRM_FW_GET_TIME 0xc9UL 239894aa69aSMichael Chan #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240894aa69aSMichael Chan #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241894aa69aSMichael Chan #define HWRM_FW_IPC_MAILBOX 0xccUL 242460c2577SMichael Chan #define HWRM_FW_ECN_CFG 0xcdUL 243460c2577SMichael Chan #define HWRM_FW_ECN_QCFG 0xceUL 244bfc6e5fbSMichael Chan #define HWRM_FW_SECURE_CFG 0xcfUL 245894aa69aSMichael Chan #define HWRM_EXEC_FWD_RESP 0xd0UL 246894aa69aSMichael Chan #define HWRM_REJECT_FWD_RESP 0xd1UL 247894aa69aSMichael Chan #define HWRM_FWD_RESP 0xd2UL 248894aa69aSMichael Chan #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249d4f52de0SMichael Chan #define HWRM_OEM_CMD 0xd4UL 2504a50ddc2SMichael Chan #define HWRM_PORT_PRBS_TEST 0xd5UL 25172e0c9f9SMichael Chan #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 25272e0c9f9SMichael Chan #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 25341136ab3SMichael Chan #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 25441136ab3SMichael Chan #define HWRM_PORT_DSC_DUMP 0xd9UL 25578eeadb8SMichael Chan #define HWRM_PORT_EP_TX_QCFG 0xdaUL 25678eeadb8SMichael Chan #define HWRM_PORT_EP_TX_CFG 0xdbUL 25784a911dbSMichael Chan #define HWRM_PORT_CFG 0xdcUL 25884a911dbSMichael Chan #define HWRM_PORT_QCFG 0xddUL 259894aa69aSMichael Chan #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 26072e0c9f9SMichael Chan #define HWRM_REG_POWER_QUERY 0xe1UL 26141136ab3SMichael Chan #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 262460c2577SMichael Chan #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 263894aa69aSMichael Chan #define HWRM_WOL_FILTER_ALLOC 0xf0UL 264894aa69aSMichael Chan #define HWRM_WOL_FILTER_FREE 0xf1UL 265894aa69aSMichael Chan #define HWRM_WOL_FILTER_QCFG 0xf2UL 266894aa69aSMichael Chan #define HWRM_WOL_REASON_QCFG 0xf3UL 2673322479eSMichael Chan #define HWRM_CFA_METER_QCAPS 0xf4UL 268894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 269894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 270894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 271894aa69aSMichael Chan #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 272894aa69aSMichael Chan #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 2733293ec23SMichael Chan #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 274894aa69aSMichael Chan #define HWRM_CFA_VFR_ALLOC 0xfdUL 275894aa69aSMichael Chan #define HWRM_CFA_VFR_FREE 0xfeUL 276894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 277894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_FREE 0x101UL 278894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_INFO 0x102UL 279894aa69aSMichael Chan #define HWRM_CFA_FLOW_ALLOC 0x103UL 280894aa69aSMichael Chan #define HWRM_CFA_FLOW_FREE 0x104UL 281894aa69aSMichael Chan #define HWRM_CFA_FLOW_FLUSH 0x105UL 282894aa69aSMichael Chan #define HWRM_CFA_FLOW_STATS 0x106UL 283894aa69aSMichael Chan #define HWRM_CFA_FLOW_INFO 0x107UL 284894aa69aSMichael Chan #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 285894aa69aSMichael Chan #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 286894aa69aSMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 287894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 288894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 289894aa69aSMichael Chan #define HWRM_CFA_PAIR_ALLOC 0x10dUL 290894aa69aSMichael Chan #define HWRM_CFA_PAIR_FREE 0x10eUL 291894aa69aSMichael Chan #define HWRM_CFA_PAIR_INFO 0x10fUL 292894aa69aSMichael Chan #define HWRM_FW_IPC_MSG 0x110UL 293894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 29431d357c0SMichael Chan #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 2953322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 2963322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 2973322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 2983322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 2993322479eSMichael Chan #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 3003322479eSMichael Chan #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 3013322479eSMichael Chan #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 3023322479eSMichael Chan #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 3033322479eSMichael Chan #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 3043322479eSMichael Chan #define HWRM_CFA_COUNTER_CFG 0x11cUL 3053322479eSMichael Chan #define HWRM_CFA_COUNTER_QCFG 0x11dUL 3063322479eSMichael Chan #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 3073322479eSMichael Chan #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 3083322479eSMichael Chan #define HWRM_CFA_EEM_QCAPS 0x120UL 3093322479eSMichael Chan #define HWRM_CFA_EEM_CFG 0x121UL 3103322479eSMichael Chan #define HWRM_CFA_EEM_QCFG 0x122UL 3113322479eSMichael Chan #define HWRM_CFA_EEM_OP 0x123UL 3123322479eSMichael Chan #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 3134a50ddc2SMichael Chan #define HWRM_CFA_TFLIB 0x125UL 31478eeadb8SMichael Chan #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 31578eeadb8SMichael Chan #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 316ad04cc05SMichael Chan #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 317ad04cc05SMichael Chan #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 318894aa69aSMichael Chan #define HWRM_ENGINE_CKV_STATUS 0x12eUL 319894aa69aSMichael Chan #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 320894aa69aSMichael Chan #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 321894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 322894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 323894aa69aSMichael Chan #define HWRM_ENGINE_CKV_FLUSH 0x133UL 324894aa69aSMichael Chan #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 325894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 3263293ec23SMichael Chan #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 3274a50ddc2SMichael Chan #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 328894aa69aSMichael Chan #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 329894aa69aSMichael Chan #define HWRM_ENGINE_QG_QUERY 0x13dUL 330894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 331894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 332894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 333894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 334894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 335894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_BIND 0x143UL 336894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 337894aa69aSMichael Chan #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 338894aa69aSMichael Chan #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 339894aa69aSMichael Chan #define HWRM_ENGINE_SG_QUERY 0x147UL 340894aa69aSMichael Chan #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 341894aa69aSMichael Chan #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 342894aa69aSMichael Chan #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 343894aa69aSMichael Chan #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 344894aa69aSMichael Chan #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 345894aa69aSMichael Chan #define HWRM_ENGINE_STATS_CONFIG 0x155UL 346894aa69aSMichael Chan #define HWRM_ENGINE_STATS_CLEAR 0x156UL 347894aa69aSMichael Chan #define HWRM_ENGINE_STATS_QUERY 0x157UL 34841136ab3SMichael Chan #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 349894aa69aSMichael Chan #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 350894aa69aSMichael Chan #define HWRM_ENGINE_RQ_FREE 0x15fUL 351894aa69aSMichael Chan #define HWRM_ENGINE_CQ_ALLOC 0x160UL 352894aa69aSMichael Chan #define HWRM_ENGINE_CQ_FREE 0x161UL 353894aa69aSMichael Chan #define HWRM_ENGINE_NQ_ALLOC 0x162UL 354894aa69aSMichael Chan #define HWRM_ENGINE_NQ_FREE 0x163UL 355894aa69aSMichael Chan #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 3563293ec23SMichael Chan #define HWRM_ENGINE_FUNC_QCFG 0x165UL 357894aa69aSMichael Chan #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 358894aa69aSMichael Chan #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 3596fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 3606fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 3616fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 3626fc92c33SMichael Chan #define HWRM_FUNC_VF_BW_CFG 0x195UL 3636fc92c33SMichael Chan #define HWRM_FUNC_VF_BW_QCFG 0x196UL 3642792b5b9SMichael Chan #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 365460c2577SMichael Chan #define HWRM_FUNC_QSTATS_EXT 0x198UL 366bfc6e5fbSMichael Chan #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 36716db6323SMichael Chan #define HWRM_FUNC_SPD_CFG 0x19aUL 36816db6323SMichael Chan #define HWRM_FUNC_SPD_QCFG 0x19bUL 36978eeadb8SMichael Chan #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 37078eeadb8SMichael Chan #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 37178eeadb8SMichael Chan #define HWRM_FUNC_PTP_CFG 0x19eUL 37278eeadb8SMichael Chan #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 37378eeadb8SMichael Chan #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 37478eeadb8SMichael Chan #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 375fbfee257SMichael Chan #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 3762895c153SMichael Chan #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 3772895c153SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 3782895c153SMichael Chan #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 3792895c153SMichael Chan #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 3802895c153SMichael Chan #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 3812895c153SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 382ad04cc05SMichael Chan #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 383ad04cc05SMichael Chan #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 38484a911dbSMichael Chan #define HWRM_FUNC_SYNCE_CFG 0x1abUL 38584a911dbSMichael Chan #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 386894aa69aSMichael Chan #define HWRM_SELFTEST_QLIST 0x200UL 387894aa69aSMichael Chan #define HWRM_SELFTEST_EXEC 0x201UL 388894aa69aSMichael Chan #define HWRM_SELFTEST_IRQ 0x202UL 389894aa69aSMichael Chan #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 390d4f52de0SMichael Chan #define HWRM_PCIE_QSTATS 0x204UL 3914a50ddc2SMichael Chan #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 3924a50ddc2SMichael Chan #define HWRM_MFG_TIMERS_QUERY 0x206UL 3934a50ddc2SMichael Chan #define HWRM_MFG_OTP_CFG 0x207UL 3944a50ddc2SMichael Chan #define HWRM_MFG_OTP_QCFG 0x208UL 3954a50ddc2SMichael Chan #define HWRM_MFG_HDMA_TEST 0x209UL 396460c2577SMichael Chan #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 397460c2577SMichael Chan #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 39816db6323SMichael Chan #define HWRM_MFG_SOC_IMAGE 0x20cUL 39916db6323SMichael Chan #define HWRM_MFG_SOC_QSTATUS 0x20dUL 40016db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 40116db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 40216db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 40378eeadb8SMichael Chan #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 40478eeadb8SMichael Chan #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 40578eeadb8SMichael Chan #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 40678eeadb8SMichael Chan #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 4072895c153SMichael Chan #define HWRM_MFG_PSOC_QSTATUS 0x215UL 4082895c153SMichael Chan #define HWRM_MFG_SELFTEST_QLIST 0x216UL 4092895c153SMichael Chan #define HWRM_MFG_SELFTEST_EXEC 0x217UL 410ad04cc05SMichael Chan #define HWRM_STAT_GENERIC_QSTATS 0x218UL 411460c2577SMichael Chan #define HWRM_TF 0x2bcUL 412460c2577SMichael Chan #define HWRM_TF_VERSION_GET 0x2bdUL 413460c2577SMichael Chan #define HWRM_TF_SESSION_OPEN 0x2c6UL 414460c2577SMichael Chan #define HWRM_TF_SESSION_ATTACH 0x2c7UL 415bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_REGISTER 0x2c8UL 416bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 417bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_CLOSE 0x2caUL 418bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_QCFG 0x2cbUL 419bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 420bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 421bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 422bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 42378eeadb8SMichael Chan #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 42484a911dbSMichael Chan #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 42584a911dbSMichael Chan #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 426bfc6e5fbSMichael Chan #define HWRM_TF_TBL_TYPE_GET 0x2daUL 427bfc6e5fbSMichael Chan #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 428424174f1SVasundhara Volam #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 4299d6b648cSMichael Chan #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 4309d6b648cSMichael Chan #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 431bfc6e5fbSMichael Chan #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 432bfc6e5fbSMichael Chan #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 433bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 434bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_OP 0x2e7UL 435bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_CFG 0x2e8UL 436bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 437bfc6e5fbSMichael Chan #define HWRM_TF_EM_INSERT 0x2eaUL 438bfc6e5fbSMichael Chan #define HWRM_TF_EM_DELETE 0x2ebUL 43916db6323SMichael Chan #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 44078eeadb8SMichael Chan #define HWRM_TF_EM_MOVE 0x2edUL 441bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_SET 0x2f8UL 442bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_GET 0x2f9UL 443bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_MOVE 0x2faUL 444bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_FREE 0x2fbUL 445bfc6e5fbSMichael Chan #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 446bfc6e5fbSMichael Chan #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 4479d6b648cSMichael Chan #define HWRM_TF_IF_TBL_SET 0x2feUL 4489d6b648cSMichael Chan #define HWRM_TF_IF_TBL_GET 0x2ffUL 44984a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 45084a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 45184a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 45284a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 45384a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 45484a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 45584a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 45684a911dbSMichael Chan #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 45784a911dbSMichael Chan #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 45884a911dbSMichael Chan #define HWRM_TFC_SESSION_FID_ADD 0x389UL 45984a911dbSMichael Chan #define HWRM_TFC_SESSION_FID_REM 0x38aUL 46084a911dbSMichael Chan #define HWRM_TFC_IDENT_ALLOC 0x38bUL 46184a911dbSMichael Chan #define HWRM_TFC_IDENT_FREE 0x38cUL 46284a911dbSMichael Chan #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 46384a911dbSMichael Chan #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 46484a911dbSMichael Chan #define HWRM_TFC_IDX_TBL_SET 0x38fUL 46584a911dbSMichael Chan #define HWRM_TFC_IDX_TBL_GET 0x390UL 46684a911dbSMichael Chan #define HWRM_TFC_IDX_TBL_FREE 0x391UL 46784a911dbSMichael Chan #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 468460c2577SMichael Chan #define HWRM_SV 0x400UL 469894aa69aSMichael Chan #define HWRM_DBG_READ_DIRECT 0xff10UL 470894aa69aSMichael Chan #define HWRM_DBG_READ_INDIRECT 0xff11UL 471894aa69aSMichael Chan #define HWRM_DBG_WRITE_DIRECT 0xff12UL 472894aa69aSMichael Chan #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 473894aa69aSMichael Chan #define HWRM_DBG_DUMP 0xff14UL 474894aa69aSMichael Chan #define HWRM_DBG_ERASE_NVM 0xff15UL 475894aa69aSMichael Chan #define HWRM_DBG_CFG 0xff16UL 476894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_LIST 0xff17UL 477894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 478894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 4796fc92c33SMichael Chan #define HWRM_DBG_FW_CLI 0xff1aUL 4806fc92c33SMichael Chan #define HWRM_DBG_I2C_CMD 0xff1bUL 48131d357c0SMichael Chan #define HWRM_DBG_RING_INFO_GET 0xff1cUL 4824a50ddc2SMichael Chan #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 4834a50ddc2SMichael Chan #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 484460c2577SMichael Chan #define HWRM_DBG_DRV_TRACE 0xff1fUL 485460c2577SMichael Chan #define HWRM_DBG_QCAPS 0xff20UL 486460c2577SMichael Chan #define HWRM_DBG_QCFG 0xff21UL 487460c2577SMichael Chan #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 48878eeadb8SMichael Chan #define HWRM_DBG_USEQ_ALLOC 0xff23UL 48978eeadb8SMichael Chan #define HWRM_DBG_USEQ_FREE 0xff24UL 49078eeadb8SMichael Chan #define HWRM_DBG_USEQ_FLUSH 0xff25UL 49178eeadb8SMichael Chan #define HWRM_DBG_USEQ_QCAPS 0xff26UL 49278eeadb8SMichael Chan #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 49378eeadb8SMichael Chan #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 49478eeadb8SMichael Chan #define HWRM_DBG_USEQ_RUN 0xff29UL 49578eeadb8SMichael Chan #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 49678eeadb8SMichael Chan #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 49778eeadb8SMichael Chan #define HWRM_NVM_DEFRAG 0xffecUL 498bfc6e5fbSMichael Chan #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 499894aa69aSMichael Chan #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 500894aa69aSMichael Chan #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 501894aa69aSMichael Chan #define HWRM_NVM_FLUSH 0xfff0UL 502894aa69aSMichael Chan #define HWRM_NVM_GET_VARIABLE 0xfff1UL 503894aa69aSMichael Chan #define HWRM_NVM_SET_VARIABLE 0xfff2UL 504894aa69aSMichael Chan #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 505894aa69aSMichael Chan #define HWRM_NVM_MODIFY 0xfff4UL 506894aa69aSMichael Chan #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 507894aa69aSMichael Chan #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 508894aa69aSMichael Chan #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 509894aa69aSMichael Chan #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 510894aa69aSMichael Chan #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 511894aa69aSMichael Chan #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 512894aa69aSMichael Chan #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 513894aa69aSMichael Chan #define HWRM_NVM_RAW_DUMP 0xfffcUL 514894aa69aSMichael Chan #define HWRM_NVM_READ 0xfffdUL 515894aa69aSMichael Chan #define HWRM_NVM_WRITE 0xfffeUL 516894aa69aSMichael Chan #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 517894aa69aSMichael Chan #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 518894aa69aSMichael Chan __le16 unused_0[3]; 519894aa69aSMichael Chan }; 520894aa69aSMichael Chan 521894aa69aSMichael Chan /* ret_codes (size:64b/8B) */ 522894aa69aSMichael Chan struct ret_codes { 523894aa69aSMichael Chan __le16 error_code; 524894aa69aSMichael Chan #define HWRM_ERR_CODE_SUCCESS 0x0UL 525894aa69aSMichael Chan #define HWRM_ERR_CODE_FAIL 0x1UL 526894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 527894aa69aSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 528894aa69aSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 529894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 530894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 531894aa69aSMichael Chan #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 532894aa69aSMichael Chan #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 5336fc92c33SMichael Chan #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 5343322479eSMichael Chan #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 5353322479eSMichael Chan #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 5364a50ddc2SMichael Chan #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 5374a50ddc2SMichael Chan #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 5384a50ddc2SMichael Chan #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 539894aa69aSMichael Chan #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 54041136ab3SMichael Chan #define HWRM_ERR_CODE_BUSY 0x10UL 5419d6b648cSMichael Chan #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 54278eeadb8SMichael Chan #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 54331d357c0SMichael Chan #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 544894aa69aSMichael Chan #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 545894aa69aSMichael Chan #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 546894aa69aSMichael Chan #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 547894aa69aSMichael Chan __le16 unused_0[3]; 548894aa69aSMichael Chan }; 549894aa69aSMichael Chan 550894aa69aSMichael Chan /* hwrm_err_output (size:128b/16B) */ 551894aa69aSMichael Chan struct hwrm_err_output { 552894aa69aSMichael Chan __le16 error_code; 553894aa69aSMichael Chan __le16 req_type; 554894aa69aSMichael Chan __le16 seq_id; 555894aa69aSMichael Chan __le16 resp_len; 556894aa69aSMichael Chan __le32 opaque_0; 557894aa69aSMichael Chan __le16 opaque_1; 558894aa69aSMichael Chan u8 cmd_err; 559894aa69aSMichael Chan u8 valid; 560894aa69aSMichael Chan }; 56187c374deSMichael Chan #define HWRM_NA_SIGNATURE ((__le32)(-1)) 562894aa69aSMichael Chan #define HWRM_MAX_REQ_LEN 128 5633293ec23SMichael Chan #define HWRM_MAX_RESP_LEN 704 564894aa69aSMichael Chan #define HW_HASH_INDEX_SIZE 0x80 56587c374deSMichael Chan #define HW_HASH_KEY_SIZE 40 566894aa69aSMichael Chan #define HWRM_RESP_VALID_KEY 1 5674a50ddc2SMichael Chan #define HWRM_TARGET_ID_BONO 0xFFF8 5684a50ddc2SMichael Chan #define HWRM_TARGET_ID_KONG 0xFFF9 5694a50ddc2SMichael Chan #define HWRM_TARGET_ID_APE 0xFFFA 5704a50ddc2SMichael Chan #define HWRM_TARGET_ID_TOOLS 0xFFFD 571894aa69aSMichael Chan #define HWRM_VERSION_MAJOR 1 57231d357c0SMichael Chan #define HWRM_VERSION_MINOR 10 57316db6323SMichael Chan #define HWRM_VERSION_UPDATE 2 57484a911dbSMichael Chan #define HWRM_VERSION_RSVD 118 57584a911dbSMichael Chan #define HWRM_VERSION_STR "1.10.2.118" 576c0c050c5SMichael Chan 577894aa69aSMichael Chan /* hwrm_ver_get_input (size:192b/24B) */ 578894aa69aSMichael Chan struct hwrm_ver_get_input { 579894aa69aSMichael Chan __le16 req_type; 580894aa69aSMichael Chan __le16 cmpl_ring; 581894aa69aSMichael Chan __le16 seq_id; 582894aa69aSMichael Chan __le16 target_id; 583894aa69aSMichael Chan __le64 resp_addr; 584894aa69aSMichael Chan u8 hwrm_intf_maj; 585894aa69aSMichael Chan u8 hwrm_intf_min; 586894aa69aSMichael Chan u8 hwrm_intf_upd; 587894aa69aSMichael Chan u8 unused_0[5]; 588894aa69aSMichael Chan }; 589894aa69aSMichael Chan 590894aa69aSMichael Chan /* hwrm_ver_get_output (size:1408b/176B) */ 591894aa69aSMichael Chan struct hwrm_ver_get_output { 592894aa69aSMichael Chan __le16 error_code; 593894aa69aSMichael Chan __le16 req_type; 594894aa69aSMichael Chan __le16 seq_id; 595894aa69aSMichael Chan __le16 resp_len; 596894aa69aSMichael Chan u8 hwrm_intf_maj_8b; 597894aa69aSMichael Chan u8 hwrm_intf_min_8b; 598894aa69aSMichael Chan u8 hwrm_intf_upd_8b; 599894aa69aSMichael Chan u8 hwrm_intf_rsvd_8b; 600894aa69aSMichael Chan u8 hwrm_fw_maj_8b; 601894aa69aSMichael Chan u8 hwrm_fw_min_8b; 602894aa69aSMichael Chan u8 hwrm_fw_bld_8b; 603894aa69aSMichael Chan u8 hwrm_fw_rsvd_8b; 604894aa69aSMichael Chan u8 mgmt_fw_maj_8b; 605894aa69aSMichael Chan u8 mgmt_fw_min_8b; 606894aa69aSMichael Chan u8 mgmt_fw_bld_8b; 607894aa69aSMichael Chan u8 mgmt_fw_rsvd_8b; 608894aa69aSMichael Chan u8 netctrl_fw_maj_8b; 609894aa69aSMichael Chan u8 netctrl_fw_min_8b; 610894aa69aSMichael Chan u8 netctrl_fw_bld_8b; 611894aa69aSMichael Chan u8 netctrl_fw_rsvd_8b; 612894aa69aSMichael Chan __le32 dev_caps_cfg; 613894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 614894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 615894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 616894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 61731d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 61831d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 61931d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 62031d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 62131d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 6223322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 6233322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 6243322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 6253322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 6264a50ddc2SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 627460c2577SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 628fbfee257SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 629894aa69aSMichael Chan u8 roce_fw_maj_8b; 630894aa69aSMichael Chan u8 roce_fw_min_8b; 631894aa69aSMichael Chan u8 roce_fw_bld_8b; 632894aa69aSMichael Chan u8 roce_fw_rsvd_8b; 633894aa69aSMichael Chan char hwrm_fw_name[16]; 634894aa69aSMichael Chan char mgmt_fw_name[16]; 635894aa69aSMichael Chan char netctrl_fw_name[16]; 6364a50ddc2SMichael Chan char active_pkg_name[16]; 637894aa69aSMichael Chan char roce_fw_name[16]; 638894aa69aSMichael Chan __le16 chip_num; 639894aa69aSMichael Chan u8 chip_rev; 640894aa69aSMichael Chan u8 chip_metal; 641894aa69aSMichael Chan u8 chip_bond_id; 642894aa69aSMichael Chan u8 chip_platform_type; 643894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 644894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 645894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 646894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 647894aa69aSMichael Chan __le16 max_req_win_len; 648894aa69aSMichael Chan __le16 max_resp_len; 649894aa69aSMichael Chan __le16 def_req_timeout; 650894aa69aSMichael Chan u8 flags; 651894aa69aSMichael Chan #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 652894aa69aSMichael Chan #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 65316db6323SMichael Chan #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 654894aa69aSMichael Chan u8 unused_0[2]; 655894aa69aSMichael Chan u8 always_1; 656894aa69aSMichael Chan __le16 hwrm_intf_major; 657894aa69aSMichael Chan __le16 hwrm_intf_minor; 658894aa69aSMichael Chan __le16 hwrm_intf_build; 659894aa69aSMichael Chan __le16 hwrm_intf_patch; 660894aa69aSMichael Chan __le16 hwrm_fw_major; 661894aa69aSMichael Chan __le16 hwrm_fw_minor; 662894aa69aSMichael Chan __le16 hwrm_fw_build; 663894aa69aSMichael Chan __le16 hwrm_fw_patch; 664894aa69aSMichael Chan __le16 mgmt_fw_major; 665894aa69aSMichael Chan __le16 mgmt_fw_minor; 666894aa69aSMichael Chan __le16 mgmt_fw_build; 667894aa69aSMichael Chan __le16 mgmt_fw_patch; 668894aa69aSMichael Chan __le16 netctrl_fw_major; 669894aa69aSMichael Chan __le16 netctrl_fw_minor; 670894aa69aSMichael Chan __le16 netctrl_fw_build; 671894aa69aSMichael Chan __le16 netctrl_fw_patch; 672894aa69aSMichael Chan __le16 roce_fw_major; 673894aa69aSMichael Chan __le16 roce_fw_minor; 674894aa69aSMichael Chan __le16 roce_fw_build; 675894aa69aSMichael Chan __le16 roce_fw_patch; 676894aa69aSMichael Chan __le16 max_ext_req_len; 67778eeadb8SMichael Chan __le16 max_req_timeout; 67878eeadb8SMichael Chan u8 unused_1[3]; 679894aa69aSMichael Chan u8 valid; 680894aa69aSMichael Chan }; 681894aa69aSMichael Chan 682894aa69aSMichael Chan /* eject_cmpl (size:128b/16B) */ 683c0c050c5SMichael Chan struct eject_cmpl { 684c0c050c5SMichael Chan __le16 type; 685c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_MASK 0x3fUL 686c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_SFT 0 687441cabbbSMichael Chan #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 688894aa69aSMichael Chan #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 6893322479eSMichael Chan #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 6903322479eSMichael Chan #define EJECT_CMPL_FLAGS_SFT 6 6913322479eSMichael Chan #define EJECT_CMPL_FLAGS_ERROR 0x40UL 692c0c050c5SMichael Chan __le16 len; 693c0c050c5SMichael Chan __le32 opaque; 6943322479eSMichael Chan __le16 v; 695c0c050c5SMichael Chan #define EJECT_CMPL_V 0x1UL 6963322479eSMichael Chan #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 6973322479eSMichael Chan #define EJECT_CMPL_ERRORS_SFT 1 6983322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 6993322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 7003322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 7013322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 7023322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 7033322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 7043322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 7053322479eSMichael Chan __le16 reserved16; 706c0c050c5SMichael Chan __le32 unused_2; 707c0c050c5SMichael Chan }; 708c0c050c5SMichael Chan 709894aa69aSMichael Chan /* hwrm_cmpl (size:128b/16B) */ 710c0c050c5SMichael Chan struct hwrm_cmpl { 711c0c050c5SMichael Chan __le16 type; 71287c374deSMichael Chan #define CMPL_TYPE_MASK 0x3fUL 71387c374deSMichael Chan #define CMPL_TYPE_SFT 0 71487c374deSMichael Chan #define CMPL_TYPE_HWRM_DONE 0x20UL 715894aa69aSMichael Chan #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 716c0c050c5SMichael Chan __le16 sequence_id; 717c0c050c5SMichael Chan __le32 unused_1; 718c0c050c5SMichael Chan __le32 v; 71987c374deSMichael Chan #define CMPL_V 0x1UL 720c0c050c5SMichael Chan __le32 unused_3; 721c0c050c5SMichael Chan }; 722c0c050c5SMichael Chan 723894aa69aSMichael Chan /* hwrm_fwd_req_cmpl (size:128b/16B) */ 724c0c050c5SMichael Chan struct hwrm_fwd_req_cmpl { 725c0c050c5SMichael Chan __le16 req_len_type; 72687c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 72787c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_SFT 0 72887c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 729894aa69aSMichael Chan #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 73087c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 73187c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_SFT 6 732c0c050c5SMichael Chan __le16 source_id; 733894aa69aSMichael Chan __le32 unused0; 734c0c050c5SMichael Chan __le32 req_buf_addr_v[2]; 73587c374deSMichael Chan #define FWD_REQ_CMPL_V 0x1UL 73687c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 73787c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 738c0c050c5SMichael Chan }; 739c0c050c5SMichael Chan 740894aa69aSMichael Chan /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 741c0c050c5SMichael Chan struct hwrm_fwd_resp_cmpl { 742c0c050c5SMichael Chan __le16 type; 74387c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 74487c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_SFT 0 74587c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 746894aa69aSMichael Chan #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 747c0c050c5SMichael Chan __le16 source_id; 748c0c050c5SMichael Chan __le16 resp_len; 749c0c050c5SMichael Chan __le16 unused_1; 750c0c050c5SMichael Chan __le32 resp_buf_addr_v[2]; 75187c374deSMichael Chan #define FWD_RESP_CMPL_V 0x1UL 75287c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 75387c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 754c0c050c5SMichael Chan }; 755c0c050c5SMichael Chan 756894aa69aSMichael Chan /* hwrm_async_event_cmpl (size:128b/16B) */ 757c0c050c5SMichael Chan struct hwrm_async_event_cmpl { 758c0c050c5SMichael Chan __le16 type; 75987c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 76087c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_SFT 0 76187c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 762894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 763c0c050c5SMichael Chan __le16 event_id; 76487c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 76587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 76687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 76787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 76887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 76987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 77087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 77187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 77231d357c0SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 7733293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 7749d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 77587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 77687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 77787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 77887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 77987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 78087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 78187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 78287c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 78387c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 78457922b0aSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 7856fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 78631d357c0SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 7873322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 7883322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 7893322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 7903293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 7913293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 7923293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 7932792b5b9SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 7942792b5b9SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 79541136ab3SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 79641136ab3SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 797460c2577SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 79831f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 7992895c153SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 80078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 80178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 8022895c153SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 803ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 804ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 805ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x49UL 8063322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 80787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 808894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 809c0c050c5SMichael Chan __le32 event_data2; 810c0c050c5SMichael Chan u8 opaque_v; 81187c374deSMichael Chan #define ASYNC_EVENT_CMPL_V 0x1UL 81287c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 81387c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 814c193554eSMichael Chan u8 timestamp_lo; 815c193554eSMichael Chan __le16 timestamp_hi; 816c0c050c5SMichael Chan __le32 event_data1; 817c0c050c5SMichael Chan }; 818c0c050c5SMichael Chan 819894aa69aSMichael Chan /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 820c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_status_change { 821c0c050c5SMichael Chan __le16 type; 82287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 82387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 82487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 825894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 826c0c050c5SMichael Chan __le16 event_id; 82787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 828894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 829c0c050c5SMichael Chan __le32 event_data2; 830c0c050c5SMichael Chan u8 opaque_v; 83187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 83287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 83387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 834c193554eSMichael Chan u8 timestamp_lo; 835c193554eSMichael Chan __le16 timestamp_hi; 836c0c050c5SMichael Chan __le32 event_data1; 83787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 838894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 839894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 84087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 84187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 84287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 84387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 84487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 8456fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 8466fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 847c0c050c5SMichael Chan }; 848c0c050c5SMichael Chan 849894aa69aSMichael Chan /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 850c0c050c5SMichael Chan struct hwrm_async_event_cmpl_port_conn_not_allowed { 851c0c050c5SMichael Chan __le16 type; 85287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 85387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 85487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 855894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 856c0c050c5SMichael Chan __le16 event_id; 85787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 858894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 859c0c050c5SMichael Chan __le32 event_data2; 860c0c050c5SMichael Chan u8 opaque_v; 86187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 86287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 86387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 864c193554eSMichael Chan u8 timestamp_lo; 865c193554eSMichael Chan __le16 timestamp_hi; 866c0c050c5SMichael Chan __le32 event_data1; 86787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 86887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 86987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 87087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 87187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 87287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 87387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 87487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 87587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 87611f15ed3SMichael Chan }; 87711f15ed3SMichael Chan 878894aa69aSMichael Chan /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 87911f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_change { 88011f15ed3SMichael Chan __le16 type; 88187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 88287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 88387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 884894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 88511f15ed3SMichael Chan __le16 event_id; 88687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 887894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 88811f15ed3SMichael Chan __le32 event_data2; 88911f15ed3SMichael Chan u8 opaque_v; 89087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 89187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 89287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 89311f15ed3SMichael Chan u8 timestamp_lo; 89411f15ed3SMichael Chan __le16 timestamp_hi; 89511f15ed3SMichael Chan __le32 event_data1; 89687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 89787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 89887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 89987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 900c0c050c5SMichael Chan }; 901c0c050c5SMichael Chan 9023322479eSMichael Chan /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 9033322479eSMichael Chan struct hwrm_async_event_cmpl_reset_notify { 9043322479eSMichael Chan __le16 type; 9053322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 9063322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 9073322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9083322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 9093322479eSMichael Chan __le16 event_id; 9103322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 9113322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 9123322479eSMichael Chan __le32 event_data2; 91316db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 91416db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 9153322479eSMichael Chan u8 opaque_v; 9163322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 9173322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 9183322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 9193322479eSMichael Chan u8 timestamp_lo; 9203322479eSMichael Chan __le16 timestamp_hi; 9213322479eSMichael Chan __le32 event_data1; 9223322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 9233322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 9243322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 9253322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 9263322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 9273322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 9283322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 9293322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 9303322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 9313322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 93216db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 933fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 934fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 9353322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 9363322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 9373322479eSMichael Chan }; 9383322479eSMichael Chan 9393293ec23SMichael Chan /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 9403293ec23SMichael Chan struct hwrm_async_event_cmpl_error_recovery { 9413293ec23SMichael Chan __le16 type; 9423293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 9433293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 9443293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9453293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 9463293ec23SMichael Chan __le16 event_id; 9473293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 9483293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 9493293ec23SMichael Chan __le32 event_data2; 9503293ec23SMichael Chan u8 opaque_v; 9513293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 9523293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 9533293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 9543293ec23SMichael Chan u8 timestamp_lo; 9553293ec23SMichael Chan __le16 timestamp_hi; 9563293ec23SMichael Chan __le32 event_data1; 9573293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 9583293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 9593293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 9603293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 9613293ec23SMichael Chan }; 9623293ec23SMichael Chan 9639d6b648cSMichael Chan /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 9649d6b648cSMichael Chan struct hwrm_async_event_cmpl_ring_monitor_msg { 9659d6b648cSMichael Chan __le16 type; 9669d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 9679d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 9689d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9699d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 9709d6b648cSMichael Chan __le16 event_id; 9719d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 9729d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 9739d6b648cSMichael Chan __le32 event_data2; 9749d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 9759d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 9769d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 9779d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 9789d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 9799d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 9809d6b648cSMichael Chan u8 opaque_v; 9819d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 9829d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 9839d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 9849d6b648cSMichael Chan u8 timestamp_lo; 9859d6b648cSMichael Chan __le16 timestamp_hi; 9869d6b648cSMichael Chan __le32 event_data1; 9879d6b648cSMichael Chan }; 9889d6b648cSMichael Chan 989894aa69aSMichael Chan /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 99011f15ed3SMichael Chan struct hwrm_async_event_cmpl_vf_cfg_change { 99111f15ed3SMichael Chan __le16 type; 99287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 99387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 99487c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 995894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 99611f15ed3SMichael Chan __le16 event_id; 99787c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 998894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 99911f15ed3SMichael Chan __le32 event_data2; 100078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 100178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 100211f15ed3SMichael Chan u8 opaque_v; 100387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 100487c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 100587c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 100611f15ed3SMichael Chan u8 timestamp_lo; 100711f15ed3SMichael Chan __le16 timestamp_hi; 100811f15ed3SMichael Chan __le32 event_data1; 100987c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 101087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 101187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 101287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 101331d357c0SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 101411f15ed3SMichael Chan }; 101511f15ed3SMichael Chan 101672e0c9f9SMichael Chan /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 101772e0c9f9SMichael Chan struct hwrm_async_event_cmpl_default_vnic_change { 101872e0c9f9SMichael Chan __le16 type; 101972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 102072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 102172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 102272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 102372e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 102472e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 102572e0c9f9SMichael Chan __le16 event_id; 102672e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 102772e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 102872e0c9f9SMichael Chan __le32 event_data2; 102972e0c9f9SMichael Chan u8 opaque_v; 103072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 103172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 103272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 103372e0c9f9SMichael Chan u8 timestamp_lo; 103472e0c9f9SMichael Chan __le16 timestamp_hi; 103572e0c9f9SMichael Chan __le32 event_data1; 103672e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 103772e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 103872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 103972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 104072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 104172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 104272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 104372e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 104472e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 104572e0c9f9SMichael Chan }; 104672e0c9f9SMichael Chan 10473322479eSMichael Chan /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 10483322479eSMichael Chan struct hwrm_async_event_cmpl_hw_flow_aged { 10493322479eSMichael Chan __le16 type; 10503322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 10513322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 10523322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10533322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 10543322479eSMichael Chan __le16 event_id; 10553322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 10563322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 10573322479eSMichael Chan __le32 event_data2; 10583322479eSMichael Chan u8 opaque_v; 10593322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 10603322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 10613322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 10623322479eSMichael Chan u8 timestamp_lo; 10633322479eSMichael Chan __le16 timestamp_hi; 10643322479eSMichael Chan __le32 event_data1; 10653322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 10663322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 10673322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 10683322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 10693322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 10703322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 10713322479eSMichael Chan }; 10723322479eSMichael Chan 10733322479eSMichael Chan /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 10743322479eSMichael Chan struct hwrm_async_event_cmpl_eem_cache_flush_req { 10753322479eSMichael Chan __le16 type; 10763322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 10773322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 10783322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10793322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 10803322479eSMichael Chan __le16 event_id; 10813322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 10823322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 10833322479eSMichael Chan __le32 event_data2; 10843322479eSMichael Chan u8 opaque_v; 10853322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 10863322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 10873322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 10883322479eSMichael Chan u8 timestamp_lo; 10893322479eSMichael Chan __le16 timestamp_hi; 10903322479eSMichael Chan __le32 event_data1; 10913322479eSMichael Chan }; 10923322479eSMichael Chan 10933322479eSMichael Chan /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 10943322479eSMichael Chan struct hwrm_async_event_cmpl_eem_cache_flush_done { 10953322479eSMichael Chan __le16 type; 10963322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 10973322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 10983322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10993322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 11003322479eSMichael Chan __le16 event_id; 11013322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 11023322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 11033322479eSMichael Chan __le32 event_data2; 11043322479eSMichael Chan u8 opaque_v; 11053322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 11063322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 11073322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 11083322479eSMichael Chan u8 timestamp_lo; 11093322479eSMichael Chan __le16 timestamp_hi; 11103322479eSMichael Chan __le32 event_data1; 11113322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 11123322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 11133322479eSMichael Chan }; 11143322479eSMichael Chan 11159d6b648cSMichael Chan /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 11169d6b648cSMichael Chan struct hwrm_async_event_cmpl_deferred_response { 11179d6b648cSMichael Chan __le16 type; 11189d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 11199d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 11209d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 11219d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 11229d6b648cSMichael Chan __le16 event_id; 11239d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 11249d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 11259d6b648cSMichael Chan __le32 event_data2; 11269d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 11279d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 11289d6b648cSMichael Chan u8 opaque_v; 11299d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 11309d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 11319d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 11329d6b648cSMichael Chan u8 timestamp_lo; 11339d6b648cSMichael Chan __le16 timestamp_hi; 11349d6b648cSMichael Chan __le32 event_data1; 11359d6b648cSMichael Chan }; 11369d6b648cSMichael Chan 113731f67c2eSMichael Chan /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 113831f67c2eSMichael Chan struct hwrm_async_event_cmpl_echo_request { 113931f67c2eSMichael Chan __le16 type; 114031f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 114131f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 114231f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 114331f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 114431f67c2eSMichael Chan __le16 event_id; 114531f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 114631f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 114731f67c2eSMichael Chan __le32 event_data2; 114831f67c2eSMichael Chan u8 opaque_v; 114931f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 115031f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 115131f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 115231f67c2eSMichael Chan u8 timestamp_lo; 115331f67c2eSMichael Chan __le16 timestamp_hi; 115431f67c2eSMichael Chan __le32 event_data1; 115531f67c2eSMichael Chan }; 115631f67c2eSMichael Chan 11572895c153SMichael Chan /* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 11582895c153SMichael Chan struct hwrm_async_event_cmpl_phc_update { 115978eeadb8SMichael Chan __le16 type; 11602895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 11612895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 11622895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 11632895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 116478eeadb8SMichael Chan __le16 event_id; 11652895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 11662895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 116778eeadb8SMichael Chan __le32 event_data2; 11682895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 11692895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 11702895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 11712895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 117278eeadb8SMichael Chan u8 opaque_v; 11732895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 11742895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 11752895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 117678eeadb8SMichael Chan u8 timestamp_lo; 117778eeadb8SMichael Chan __le16 timestamp_hi; 117878eeadb8SMichael Chan __le32 event_data1; 11792895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 11802895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 11812895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 11822895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 11832895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 11842895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 11852895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 11862895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 11872895c153SMichael Chan #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 118878eeadb8SMichael Chan }; 118978eeadb8SMichael Chan 119078eeadb8SMichael Chan /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 119178eeadb8SMichael Chan struct hwrm_async_event_cmpl_pps_timestamp { 119278eeadb8SMichael Chan __le16 type; 119378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 119478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 119578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 119678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 119778eeadb8SMichael Chan __le16 event_id; 119878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 119978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 120078eeadb8SMichael Chan __le32 event_data2; 120178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 120278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 120378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 120478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 120578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 120678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 120778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 120878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 120978eeadb8SMichael Chan u8 opaque_v; 121078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 121178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 121278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 121378eeadb8SMichael Chan u8 timestamp_lo; 121478eeadb8SMichael Chan __le16 timestamp_hi; 121578eeadb8SMichael Chan __le32 event_data1; 121678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 121778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 121878eeadb8SMichael Chan }; 121978eeadb8SMichael Chan 122078eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 122178eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report { 122278eeadb8SMichael Chan __le16 type; 122378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 122478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 122578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 122678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 122778eeadb8SMichael Chan __le16 event_id; 122878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 122978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 123078eeadb8SMichael Chan __le32 event_data2; 123178eeadb8SMichael Chan u8 opaque_v; 123278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 123378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 123478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 123578eeadb8SMichael Chan u8 timestamp_lo; 123678eeadb8SMichael Chan __le16 timestamp_hi; 123778eeadb8SMichael Chan __le32 event_data1; 123878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 123978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 124078eeadb8SMichael Chan }; 124178eeadb8SMichael Chan 124278eeadb8SMichael Chan /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 124378eeadb8SMichael Chan struct hwrm_async_event_cmpl_hwrm_error { 124478eeadb8SMichael Chan __le16 type; 124578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 124678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 124778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 124878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 124978eeadb8SMichael Chan __le16 event_id; 125078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 125178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 125278eeadb8SMichael Chan __le32 event_data2; 125378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 125478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 125578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 125678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 125778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 125878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 125978eeadb8SMichael Chan u8 opaque_v; 126078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 126178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 126278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 126378eeadb8SMichael Chan u8 timestamp_lo; 126478eeadb8SMichael Chan __le16 timestamp_hi; 126578eeadb8SMichael Chan __le32 event_data1; 126678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 126778eeadb8SMichael Chan }; 126878eeadb8SMichael Chan 126978eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 127078eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_base { 127178eeadb8SMichael Chan __le16 type; 127278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 127378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 127478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 127578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 127678eeadb8SMichael Chan __le16 event_id; 127778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 127878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 127978eeadb8SMichael Chan __le32 event_data2; 128078eeadb8SMichael Chan u8 opaque_v; 128178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 128278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 128378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 128478eeadb8SMichael Chan u8 timestamp_lo; 128578eeadb8SMichael Chan __le16 timestamp_hi; 128678eeadb8SMichael Chan __le32 event_data1; 128778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 128878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 128978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 129078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 129178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 129278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1293fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1294ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1295ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 129678eeadb8SMichael Chan }; 129778eeadb8SMichael Chan 129878eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 129978eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_pause_storm { 130078eeadb8SMichael Chan __le16 type; 130178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 130278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 130378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 130478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 130578eeadb8SMichael Chan __le16 event_id; 130678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 130778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 130878eeadb8SMichael Chan __le32 event_data2; 130978eeadb8SMichael Chan u8 opaque_v; 131078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 131178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 131278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 131378eeadb8SMichael Chan u8 timestamp_lo; 131478eeadb8SMichael Chan __le16 timestamp_hi; 131578eeadb8SMichael Chan __le32 event_data1; 131678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 131778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 131878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 131978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 132078eeadb8SMichael Chan }; 132178eeadb8SMichael Chan 132278eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 132378eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_invalid_signal { 132478eeadb8SMichael Chan __le16 type; 132578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 132678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 132778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 132878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 132978eeadb8SMichael Chan __le16 event_id; 133078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 133178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 133278eeadb8SMichael Chan __le32 event_data2; 133378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 133478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 133578eeadb8SMichael Chan u8 opaque_v; 133678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 133778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 133878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 133978eeadb8SMichael Chan u8 timestamp_lo; 134078eeadb8SMichael Chan __le16 timestamp_hi; 134178eeadb8SMichael Chan __le32 event_data1; 134278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 134378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 134478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 134578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 134678eeadb8SMichael Chan }; 134778eeadb8SMichael Chan 134878eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 134978eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_nvm { 135078eeadb8SMichael Chan __le16 type; 135178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 135278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 135378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 135478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 135578eeadb8SMichael Chan __le16 event_id; 135678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 135778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 135878eeadb8SMichael Chan __le32 event_data2; 135978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 136078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 136178eeadb8SMichael Chan u8 opaque_v; 136278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 136378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 136478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 136578eeadb8SMichael Chan u8 timestamp_lo; 136678eeadb8SMichael Chan __le16 timestamp_hi; 136778eeadb8SMichael Chan __le32 event_data1; 136878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 136978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 137078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 137178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 137278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 137378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 137478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 137578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 137678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 137778eeadb8SMichael Chan }; 137878eeadb8SMichael Chan 13792895c153SMichael Chan /* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 13802895c153SMichael Chan struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 13812895c153SMichael Chan __le16 type; 13822895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 13832895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 13842895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 13852895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 13862895c153SMichael Chan __le16 event_id; 13872895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 13882895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 13892895c153SMichael Chan __le32 event_data2; 13902895c153SMichael Chan u8 opaque_v; 13912895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 13922895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 13932895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 13942895c153SMichael Chan u8 timestamp_lo; 13952895c153SMichael Chan __le16 timestamp_hi; 13962895c153SMichael Chan __le32 event_data1; 13972895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 13982895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 13992895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 14002895c153SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1401ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1402ad04cc05SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 14032895c153SMichael Chan }; 14042895c153SMichael Chan 1405894aa69aSMichael Chan /* hwrm_func_reset_input (size:192b/24B) */ 1406c0c050c5SMichael Chan struct hwrm_func_reset_input { 1407c0c050c5SMichael Chan __le16 req_type; 1408c0c050c5SMichael Chan __le16 cmpl_ring; 1409c0c050c5SMichael Chan __le16 seq_id; 1410c0c050c5SMichael Chan __le16 target_id; 1411c0c050c5SMichael Chan __le64 resp_addr; 1412c0c050c5SMichael Chan __le32 enables; 1413c0c050c5SMichael Chan #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1414c0c050c5SMichael Chan __le16 vf_id; 1415c193554eSMichael Chan u8 func_reset_level; 1416441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1417441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1418441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1419441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1420894aa69aSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1421c193554eSMichael Chan u8 unused_0; 1422c0c050c5SMichael Chan }; 1423c0c050c5SMichael Chan 1424894aa69aSMichael Chan /* hwrm_func_reset_output (size:128b/16B) */ 1425c0c050c5SMichael Chan struct hwrm_func_reset_output { 1426c0c050c5SMichael Chan __le16 error_code; 1427c0c050c5SMichael Chan __le16 req_type; 1428c0c050c5SMichael Chan __le16 seq_id; 1429c0c050c5SMichael Chan __le16 resp_len; 1430894aa69aSMichael Chan u8 unused_0[7]; 1431c0c050c5SMichael Chan u8 valid; 1432c0c050c5SMichael Chan }; 1433c0c050c5SMichael Chan 1434894aa69aSMichael Chan /* hwrm_func_getfid_input (size:192b/24B) */ 1435c0c050c5SMichael Chan struct hwrm_func_getfid_input { 1436c0c050c5SMichael Chan __le16 req_type; 1437c0c050c5SMichael Chan __le16 cmpl_ring; 1438c0c050c5SMichael Chan __le16 seq_id; 1439c0c050c5SMichael Chan __le16 target_id; 1440c0c050c5SMichael Chan __le64 resp_addr; 1441c0c050c5SMichael Chan __le32 enables; 1442c0c050c5SMichael Chan #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1443c0c050c5SMichael Chan __le16 pci_id; 1444894aa69aSMichael Chan u8 unused_0[2]; 1445c0c050c5SMichael Chan }; 1446c0c050c5SMichael Chan 1447894aa69aSMichael Chan /* hwrm_func_getfid_output (size:128b/16B) */ 1448c0c050c5SMichael Chan struct hwrm_func_getfid_output { 1449c0c050c5SMichael Chan __le16 error_code; 1450c0c050c5SMichael Chan __le16 req_type; 1451c0c050c5SMichael Chan __le16 seq_id; 1452c0c050c5SMichael Chan __le16 resp_len; 1453c0c050c5SMichael Chan __le16 fid; 1454894aa69aSMichael Chan u8 unused_0[5]; 1455c0c050c5SMichael Chan u8 valid; 1456c0c050c5SMichael Chan }; 1457c0c050c5SMichael Chan 1458894aa69aSMichael Chan /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1459c0c050c5SMichael Chan struct hwrm_func_vf_alloc_input { 1460c0c050c5SMichael Chan __le16 req_type; 1461c0c050c5SMichael Chan __le16 cmpl_ring; 1462c0c050c5SMichael Chan __le16 seq_id; 1463c0c050c5SMichael Chan __le16 target_id; 1464c0c050c5SMichael Chan __le64 resp_addr; 1465c0c050c5SMichael Chan __le32 enables; 1466c0c050c5SMichael Chan #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1467c0c050c5SMichael Chan __le16 first_vf_id; 1468c0c050c5SMichael Chan __le16 num_vfs; 1469c0c050c5SMichael Chan }; 1470c0c050c5SMichael Chan 1471894aa69aSMichael Chan /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1472c0c050c5SMichael Chan struct hwrm_func_vf_alloc_output { 1473c0c050c5SMichael Chan __le16 error_code; 1474c0c050c5SMichael Chan __le16 req_type; 1475c0c050c5SMichael Chan __le16 seq_id; 1476c0c050c5SMichael Chan __le16 resp_len; 1477c0c050c5SMichael Chan __le16 first_vf_id; 1478894aa69aSMichael Chan u8 unused_0[5]; 1479c0c050c5SMichael Chan u8 valid; 1480c0c050c5SMichael Chan }; 1481c0c050c5SMichael Chan 1482894aa69aSMichael Chan /* hwrm_func_vf_free_input (size:192b/24B) */ 1483c0c050c5SMichael Chan struct hwrm_func_vf_free_input { 1484c0c050c5SMichael Chan __le16 req_type; 1485c0c050c5SMichael Chan __le16 cmpl_ring; 1486c0c050c5SMichael Chan __le16 seq_id; 1487c0c050c5SMichael Chan __le16 target_id; 1488c0c050c5SMichael Chan __le64 resp_addr; 1489c0c050c5SMichael Chan __le32 enables; 1490c0c050c5SMichael Chan #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1491c0c050c5SMichael Chan __le16 first_vf_id; 1492c0c050c5SMichael Chan __le16 num_vfs; 1493c0c050c5SMichael Chan }; 1494c0c050c5SMichael Chan 1495894aa69aSMichael Chan /* hwrm_func_vf_free_output (size:128b/16B) */ 1496c0c050c5SMichael Chan struct hwrm_func_vf_free_output { 1497c0c050c5SMichael Chan __le16 error_code; 1498c0c050c5SMichael Chan __le16 req_type; 1499c0c050c5SMichael Chan __le16 seq_id; 1500c0c050c5SMichael Chan __le16 resp_len; 1501894aa69aSMichael Chan u8 unused_0[7]; 1502c0c050c5SMichael Chan u8 valid; 1503c0c050c5SMichael Chan }; 1504c0c050c5SMichael Chan 1505894aa69aSMichael Chan /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1506c0c050c5SMichael Chan struct hwrm_func_vf_cfg_input { 1507c0c050c5SMichael Chan __le16 req_type; 1508c0c050c5SMichael Chan __le16 cmpl_ring; 1509c0c050c5SMichael Chan __le16 seq_id; 1510c0c050c5SMichael Chan __le16 target_id; 1511c0c050c5SMichael Chan __le64 resp_addr; 1512c0c050c5SMichael Chan __le32 enables; 1513c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1514c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1515c193554eSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 151611f15ed3SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1517894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1518894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1519894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1520894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1521894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1522894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1523894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1524894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1525fbfee257SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL 1526fbfee257SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL 1527c0c050c5SMichael Chan __le16 mtu; 1528c0c050c5SMichael Chan __le16 guest_vlan; 1529c193554eSMichael Chan __le16 async_event_cr; 153011f15ed3SMichael Chan u8 dflt_mac_addr[6]; 1531894aa69aSMichael Chan __le32 flags; 1532894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1533894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1534894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1535894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1536894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1537894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1538894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1539894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1540bfc6e5fbSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1541bfc6e5fbSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1542894aa69aSMichael Chan __le16 num_rsscos_ctxs; 1543894aa69aSMichael Chan __le16 num_cmpl_rings; 1544894aa69aSMichael Chan __le16 num_tx_rings; 1545894aa69aSMichael Chan __le16 num_rx_rings; 1546894aa69aSMichael Chan __le16 num_l2_ctxs; 1547894aa69aSMichael Chan __le16 num_vnics; 1548894aa69aSMichael Chan __le16 num_stat_ctxs; 1549894aa69aSMichael Chan __le16 num_hw_ring_grps; 1550fbfee257SMichael Chan __le16 num_tx_key_ctxs; 1551fbfee257SMichael Chan __le16 num_rx_key_ctxs; 1552c0c050c5SMichael Chan }; 1553c0c050c5SMichael Chan 1554894aa69aSMichael Chan /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1555c0c050c5SMichael Chan struct hwrm_func_vf_cfg_output { 1556c0c050c5SMichael Chan __le16 error_code; 1557c0c050c5SMichael Chan __le16 req_type; 1558c0c050c5SMichael Chan __le16 seq_id; 1559c0c050c5SMichael Chan __le16 resp_len; 1560894aa69aSMichael Chan u8 unused_0[7]; 1561c0c050c5SMichael Chan u8 valid; 1562c0c050c5SMichael Chan }; 1563c0c050c5SMichael Chan 1564894aa69aSMichael Chan /* hwrm_func_qcaps_input (size:192b/24B) */ 1565c0c050c5SMichael Chan struct hwrm_func_qcaps_input { 1566c0c050c5SMichael Chan __le16 req_type; 1567c0c050c5SMichael Chan __le16 cmpl_ring; 1568c0c050c5SMichael Chan __le16 seq_id; 1569c0c050c5SMichael Chan __le16 target_id; 1570c0c050c5SMichael Chan __le64 resp_addr; 1571c0c050c5SMichael Chan __le16 fid; 1572894aa69aSMichael Chan u8 unused_0[6]; 1573c0c050c5SMichael Chan }; 1574c0c050c5SMichael Chan 1575fbfee257SMichael Chan /* hwrm_func_qcaps_output (size:768b/96B) */ 1576c0c050c5SMichael Chan struct hwrm_func_qcaps_output { 1577c0c050c5SMichael Chan __le16 error_code; 1578c0c050c5SMichael Chan __le16 req_type; 1579c0c050c5SMichael Chan __le16 seq_id; 1580c0c050c5SMichael Chan __le16 resp_len; 1581c0c050c5SMichael Chan __le16 fid; 1582c0c050c5SMichael Chan __le16 port_id; 1583c0c050c5SMichael Chan __le32 flags; 1584c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1585c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 158611f15ed3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1587a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1588a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1589a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1590a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1591441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1592441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1593441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1594441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 159587c374deSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1596894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1597894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1598894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1599894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1600d4f52de0SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 16016fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 16026fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 16036fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 160431d357c0SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 16053322479eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 16063322479eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 16073293ec23SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 16084a50ddc2SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 160972e0c9f9SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 161072e0c9f9SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 161141136ab3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1612460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1613460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1614460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1615460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 161611f15ed3SMichael Chan u8 mac_address[6]; 1617c0c050c5SMichael Chan __le16 max_rsscos_ctx; 1618c0c050c5SMichael Chan __le16 max_cmpl_rings; 1619c0c050c5SMichael Chan __le16 max_tx_rings; 1620c0c050c5SMichael Chan __le16 max_rx_rings; 1621c0c050c5SMichael Chan __le16 max_l2_ctxs; 1622c0c050c5SMichael Chan __le16 max_vnics; 1623c0c050c5SMichael Chan __le16 first_vf_id; 1624c0c050c5SMichael Chan __le16 max_vfs; 1625c0c050c5SMichael Chan __le16 max_stat_ctx; 1626c0c050c5SMichael Chan __le32 max_encap_records; 1627c0c050c5SMichael Chan __le32 max_decap_records; 1628c0c050c5SMichael Chan __le32 max_tx_em_flows; 1629c0c050c5SMichael Chan __le32 max_tx_wm_flows; 1630c0c050c5SMichael Chan __le32 max_rx_em_flows; 1631c0c050c5SMichael Chan __le32 max_rx_wm_flows; 1632c0c050c5SMichael Chan __le32 max_mcast_filters; 1633c0c050c5SMichael Chan __le32 max_flow_id; 1634c0c050c5SMichael Chan __le32 max_hw_ring_grps; 1635441cabbbSMichael Chan __le16 max_sp_tx_rings; 163678eeadb8SMichael Chan __le16 max_msix_vfs; 1637460c2577SMichael Chan __le32 flags_ext; 1638460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1639460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1640460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1641bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1642bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1643bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1644bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1645bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 164616db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 164716db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 164816db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 164916db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 165031f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 165131f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 165231f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 165331f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 165478eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 165578eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 165678eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 165778eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 165878eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 165978eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 166078eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 166178eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 166221e70778SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 166321e70778SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 16642895c153SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 16652895c153SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 16662895c153SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 16672895c153SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1668ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1669ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1670bfc6e5fbSMichael Chan u8 max_schqs; 16719d6b648cSMichael Chan u8 mpc_chnls_cap; 16729d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 16739d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 16749d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 16759d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 16769d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1677fbfee257SMichael Chan __le16 max_key_ctxs_alloc; 1678ad04cc05SMichael Chan __le32 flags_ext2; 1679ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1680ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1681ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1682ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1683ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1684ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 168584a911dbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 168684a911dbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 168784a911dbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 168884a911dbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1689ad04cc05SMichael Chan __le16 tunnel_disable_flag; 1690ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1691ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1692ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1693ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1694ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1695ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1696ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1697ad04cc05SMichael Chan #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1698ad04cc05SMichael Chan u8 unused_1; 1699c0c050c5SMichael Chan u8 valid; 1700c0c050c5SMichael Chan }; 1701c0c050c5SMichael Chan 1702894aa69aSMichael Chan /* hwrm_func_qcfg_input (size:192b/24B) */ 170311f15ed3SMichael Chan struct hwrm_func_qcfg_input { 170411f15ed3SMichael Chan __le16 req_type; 170511f15ed3SMichael Chan __le16 cmpl_ring; 170611f15ed3SMichael Chan __le16 seq_id; 170711f15ed3SMichael Chan __le16 target_id; 170811f15ed3SMichael Chan __le64 resp_addr; 170911f15ed3SMichael Chan __le16 fid; 1710894aa69aSMichael Chan u8 unused_0[6]; 171111f15ed3SMichael Chan }; 171211f15ed3SMichael Chan 1713fbfee257SMichael Chan /* hwrm_func_qcfg_output (size:896b/112B) */ 171411f15ed3SMichael Chan struct hwrm_func_qcfg_output { 171511f15ed3SMichael Chan __le16 error_code; 171611f15ed3SMichael Chan __le16 req_type; 171711f15ed3SMichael Chan __le16 seq_id; 171811f15ed3SMichael Chan __le16 resp_len; 171911f15ed3SMichael Chan __le16 fid; 172011f15ed3SMichael Chan __le16 port_id; 172111f15ed3SMichael Chan __le16 vlan; 1722a58a3e68SMichael Chan __le16 flags; 1723a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1724a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1725441cabbbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 172687c374deSMichael Chan #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 17278eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 17288eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 172931d357c0SMichael Chan #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 17303322479eSMichael Chan #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 17312792b5b9SMichael Chan #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1732bfc6e5fbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1733bfc6e5fbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 17349d6b648cSMichael Chan #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 173516db6323SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 173631f67c2eSMichael Chan #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 173778eeadb8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 173811f15ed3SMichael Chan u8 mac_address[6]; 173911f15ed3SMichael Chan __le16 pci_id; 174011f15ed3SMichael Chan __le16 alloc_rsscos_ctx; 174111f15ed3SMichael Chan __le16 alloc_cmpl_rings; 174211f15ed3SMichael Chan __le16 alloc_tx_rings; 174311f15ed3SMichael Chan __le16 alloc_rx_rings; 174411f15ed3SMichael Chan __le16 alloc_l2_ctx; 174511f15ed3SMichael Chan __le16 alloc_vnics; 174678eeadb8SMichael Chan __le16 admin_mtu; 174711f15ed3SMichael Chan __le16 mru; 174811f15ed3SMichael Chan __le16 stat_ctx_id; 174911f15ed3SMichael Chan u8 port_partition_type; 1750441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1751441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1752441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1753441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1754441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 175578eeadb8SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1756441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1757894aa69aSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 17588eb992e8SMichael Chan u8 port_pf_cnt; 17598eb992e8SMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1760894aa69aSMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 176111f15ed3SMichael Chan __le16 dflt_vnic_id; 176257922b0aSMichael Chan __le16 max_mtu_configured; 176311f15ed3SMichael Chan __le32 min_bw; 1764441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1765441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1766bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1767bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1768bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1769bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1770441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1771441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1772bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1773bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1774bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1775bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1776441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1777441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1778441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 177911f15ed3SMichael Chan __le32 max_bw; 1780441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1781441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1782bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1783bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1784bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1785bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1786441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1787441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1788bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1789bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1790bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1791bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1792441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1793441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1794441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 179511f15ed3SMichael Chan u8 evb_mode; 1796441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1797441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1798441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1799894aa69aSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1800d4f52de0SMichael Chan u8 options; 1801d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1802d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1803d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1804d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1805d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 18066fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 18076fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 18086fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 18096fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 18106fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 18116fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 18126fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 18136fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1814441cabbbSMichael Chan __le16 alloc_vfs; 181511f15ed3SMichael Chan __le32 alloc_mcast_filters; 181611f15ed3SMichael Chan __le32 alloc_hw_ring_grps; 1817441cabbbSMichael Chan __le16 alloc_sp_tx_rings; 1818894aa69aSMichael Chan __le16 alloc_stat_ctx; 18196fc92c33SMichael Chan __le16 alloc_msix; 18203322479eSMichael Chan __le16 registered_vfs; 182172e0c9f9SMichael Chan __le16 l2_doorbell_bar_size_kb; 182272e0c9f9SMichael Chan u8 unused_1; 18233322479eSMichael Chan u8 always_1; 18243322479eSMichael Chan __le32 reset_addr_poll; 182541136ab3SMichael Chan __le16 legacy_l2_db_size_kb; 1826460c2577SMichael Chan __le16 svif_info; 1827460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1828460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1829460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 18309d6b648cSMichael Chan u8 mpc_chnls; 18319d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 18329d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 18339d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 18349d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 18359d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 183684a911dbSMichael Chan u8 db_page_size; 183784a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 183884a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 183984a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 184084a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 184184a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 184284a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 184384a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 184484a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 184584a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 184684a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 184784a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 184884a911dbSMichael Chan #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 184984a911dbSMichael Chan u8 unused_2[2]; 185078eeadb8SMichael Chan __le32 partition_min_bw; 185178eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 185278eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 185378eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 185478eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 185578eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 185678eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 185778eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 185878eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 185978eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 186078eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 186178eeadb8SMichael Chan __le32 partition_max_bw; 186278eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 186378eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 186478eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 186578eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 186678eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 186778eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 186878eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 186978eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 187078eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 187178eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 187278eeadb8SMichael Chan __le16 host_mtu; 1873fbfee257SMichael Chan __le16 alloc_tx_key_ctxs; 1874fbfee257SMichael Chan __le16 alloc_rx_key_ctxs; 1875ad04cc05SMichael Chan u8 port_kdnet_mode; 1876ad04cc05SMichael Chan #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 1877ad04cc05SMichael Chan #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 1878ad04cc05SMichael Chan #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 1879ad04cc05SMichael Chan u8 kdnet_pcie_function; 1880ad04cc05SMichael Chan __le16 port_kdnet_fid; 1881ad04cc05SMichael Chan u8 unused_3; 188211f15ed3SMichael Chan u8 valid; 188311f15ed3SMichael Chan }; 188411f15ed3SMichael Chan 1885ad04cc05SMichael Chan /* hwrm_func_cfg_input (size:960b/120B) */ 1886c0c050c5SMichael Chan struct hwrm_func_cfg_input { 1887c0c050c5SMichael Chan __le16 req_type; 1888c0c050c5SMichael Chan __le16 cmpl_ring; 1889c0c050c5SMichael Chan __le16 seq_id; 1890c0c050c5SMichael Chan __le16 target_id; 1891c0c050c5SMichael Chan __le64 resp_addr; 1892c193554eSMichael Chan __le16 fid; 18936fc92c33SMichael Chan __le16 num_msix; 1894c0c050c5SMichael Chan __le32 flags; 18958eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 18968eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 18978eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 18988eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 18998eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 19008eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 19018eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1902acb20054SMichael Chan #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 19036a17eb27SMichael Chan #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1904894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1905894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1906894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1907894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1908894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1909894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1910894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 191131d357c0SMichael Chan #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 19123322479eSMichael Chan #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 19130b815023SMichael Chan #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 19143293ec23SMichael Chan #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 19152792b5b9SMichael Chan #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1916bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1917bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1918bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 191931f67c2eSMichael Chan #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 192031f67c2eSMichael Chan #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 192184a911dbSMichael Chan #define FUNC_CFG_REQ_FLAGS_KEY_CTX_ASSETS_TEST 0x80000000UL 1922c0c050c5SMichael Chan __le32 enables; 192378eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1924c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1925c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1926c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1927c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1928c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1929c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1930c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1931c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1932c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1933c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1934c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1935c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1936c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1937c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1938c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1939c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1940c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1941c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1942c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1943894aa69aSMichael Chan #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 19446fc92c33SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 19456fc92c33SMichael Chan #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1946bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1947bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 19489d6b648cSMichael Chan #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 194978eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 195078eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 195178eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 195278eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1953fbfee257SMichael Chan #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL 1954fbfee257SMichael Chan #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL 195578eeadb8SMichael Chan __le16 admin_mtu; 1956c0c050c5SMichael Chan __le16 mru; 1957c0c050c5SMichael Chan __le16 num_rsscos_ctxs; 1958c0c050c5SMichael Chan __le16 num_cmpl_rings; 1959c0c050c5SMichael Chan __le16 num_tx_rings; 1960c0c050c5SMichael Chan __le16 num_rx_rings; 1961c0c050c5SMichael Chan __le16 num_l2_ctxs; 1962c0c050c5SMichael Chan __le16 num_vnics; 1963c0c050c5SMichael Chan __le16 num_stat_ctxs; 1964c0c050c5SMichael Chan __le16 num_hw_ring_grps; 1965c0c050c5SMichael Chan u8 dflt_mac_addr[6]; 1966c0c050c5SMichael Chan __le16 dflt_vlan; 1967c0c050c5SMichael Chan __be32 dflt_ip_addr[4]; 1968c0c050c5SMichael Chan __le32 min_bw; 1969441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1970441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1971bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1972bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1973bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1974bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1975441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1976441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1977bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1978bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1979bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1980bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1981441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1982441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1983441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1984c0c050c5SMichael Chan __le32 max_bw; 1985441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1986441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1987bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1988bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1989bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1990bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1991441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1992441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1993bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1994bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1995bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1996bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1997441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1998441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1999441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2000c0c050c5SMichael Chan __le16 async_event_cr; 2001c0c050c5SMichael Chan u8 vlan_antispoof_mode; 2002441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2003441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2004441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2005441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2006894aa69aSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2007c0c050c5SMichael Chan u8 allowed_vlan_pris; 2008c0c050c5SMichael Chan u8 evb_mode; 2009441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2010441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2011441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2012894aa69aSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2013d4f52de0SMichael Chan u8 options; 2014d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2015d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2016d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2017d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2018d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 20196fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 20206fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 20216fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 20226fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 20236fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 20246fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 20256fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 20266fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2027c0c050c5SMichael Chan __le16 num_mcast_filters; 2028bfc6e5fbSMichael Chan __le16 schq_id; 20299d6b648cSMichael Chan __le16 mpc_chnls; 20309d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 20319d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 20329d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 20339d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 20349d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 20359d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 20369d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 20379d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 20389d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 20399d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 204078eeadb8SMichael Chan __le32 partition_min_bw; 204178eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 204278eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 204378eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 204478eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 204578eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 204678eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 204778eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 204878eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 204978eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 205078eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 205178eeadb8SMichael Chan __le32 partition_max_bw; 205278eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 205378eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 205478eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 205578eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 205678eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 205778eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 205878eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 205978eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 206078eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 206178eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 206278eeadb8SMichael Chan __be16 tpid; 206378eeadb8SMichael Chan __le16 host_mtu; 2064fbfee257SMichael Chan __le16 num_tx_key_ctxs; 2065fbfee257SMichael Chan __le16 num_rx_key_ctxs; 2066ad04cc05SMichael Chan __le32 enables2; 2067ad04cc05SMichael Chan #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 206884a911dbSMichael Chan #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2069ad04cc05SMichael Chan u8 port_kdnet_mode; 2070ad04cc05SMichael Chan #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2071ad04cc05SMichael Chan #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2072ad04cc05SMichael Chan #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 207384a911dbSMichael Chan u8 db_page_size; 207484a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 207584a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 207684a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 207784a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 207884a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 207984a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 208084a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 208184a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 208284a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 208384a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 208484a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 208584a911dbSMichael Chan #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 208684a911dbSMichael Chan u8 unused_0[6]; 2087c0c050c5SMichael Chan }; 2088c0c050c5SMichael Chan 2089894aa69aSMichael Chan /* hwrm_func_cfg_output (size:128b/16B) */ 2090c0c050c5SMichael Chan struct hwrm_func_cfg_output { 2091c0c050c5SMichael Chan __le16 error_code; 2092c0c050c5SMichael Chan __le16 req_type; 2093c0c050c5SMichael Chan __le16 seq_id; 2094c0c050c5SMichael Chan __le16 resp_len; 2095894aa69aSMichael Chan u8 unused_0[7]; 2096c0c050c5SMichael Chan u8 valid; 2097c0c050c5SMichael Chan }; 2098c0c050c5SMichael Chan 209921e70778SMichael Chan /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 210021e70778SMichael Chan struct hwrm_func_cfg_cmd_err { 210121e70778SMichael Chan u8 code; 210221e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 210321e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 210421e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 210521e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 210621e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 210721e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 210821e70778SMichael Chan u8 unused_0[7]; 210921e70778SMichael Chan }; 211021e70778SMichael Chan 2111894aa69aSMichael Chan /* hwrm_func_qstats_input (size:192b/24B) */ 2112c0c050c5SMichael Chan struct hwrm_func_qstats_input { 2113c0c050c5SMichael Chan __le16 req_type; 2114c0c050c5SMichael Chan __le16 cmpl_ring; 2115c0c050c5SMichael Chan __le16 seq_id; 2116c0c050c5SMichael Chan __le16 target_id; 2117c0c050c5SMichael Chan __le64 resp_addr; 2118c0c050c5SMichael Chan __le16 fid; 211972e0c9f9SMichael Chan u8 flags; 212072e0c9f9SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2121460c2577SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 212284a911dbSMichael Chan #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 212372e0c9f9SMichael Chan u8 unused_0[5]; 2124c0c050c5SMichael Chan }; 2125c0c050c5SMichael Chan 2126894aa69aSMichael Chan /* hwrm_func_qstats_output (size:1408b/176B) */ 2127c0c050c5SMichael Chan struct hwrm_func_qstats_output { 2128c0c050c5SMichael Chan __le16 error_code; 2129c0c050c5SMichael Chan __le16 req_type; 2130c0c050c5SMichael Chan __le16 seq_id; 2131c0c050c5SMichael Chan __le16 resp_len; 2132c0c050c5SMichael Chan __le64 tx_ucast_pkts; 2133c0c050c5SMichael Chan __le64 tx_mcast_pkts; 2134c0c050c5SMichael Chan __le64 tx_bcast_pkts; 21358eb992e8SMichael Chan __le64 tx_discard_pkts; 2136c0c050c5SMichael Chan __le64 tx_drop_pkts; 2137c0c050c5SMichael Chan __le64 tx_ucast_bytes; 2138c0c050c5SMichael Chan __le64 tx_mcast_bytes; 2139c0c050c5SMichael Chan __le64 tx_bcast_bytes; 2140c0c050c5SMichael Chan __le64 rx_ucast_pkts; 2141c0c050c5SMichael Chan __le64 rx_mcast_pkts; 2142c0c050c5SMichael Chan __le64 rx_bcast_pkts; 21438eb992e8SMichael Chan __le64 rx_discard_pkts; 2144c0c050c5SMichael Chan __le64 rx_drop_pkts; 2145c0c050c5SMichael Chan __le64 rx_ucast_bytes; 2146c0c050c5SMichael Chan __le64 rx_mcast_bytes; 2147c0c050c5SMichael Chan __le64 rx_bcast_bytes; 2148c0c050c5SMichael Chan __le64 rx_agg_pkts; 2149c0c050c5SMichael Chan __le64 rx_agg_bytes; 2150c0c050c5SMichael Chan __le64 rx_agg_events; 2151c0c050c5SMichael Chan __le64 rx_agg_aborts; 215284a911dbSMichael Chan u8 clear_seq; 215384a911dbSMichael Chan u8 unused_0[6]; 2154c0c050c5SMichael Chan u8 valid; 2155c0c050c5SMichael Chan }; 2156c0c050c5SMichael Chan 2157bfc6e5fbSMichael Chan /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2158460c2577SMichael Chan struct hwrm_func_qstats_ext_input { 2159460c2577SMichael Chan __le16 req_type; 2160460c2577SMichael Chan __le16 cmpl_ring; 2161460c2577SMichael Chan __le16 seq_id; 2162460c2577SMichael Chan __le16 target_id; 2163460c2577SMichael Chan __le64 resp_addr; 2164460c2577SMichael Chan __le16 fid; 2165460c2577SMichael Chan u8 flags; 2166460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2167460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2168bfc6e5fbSMichael Chan u8 unused_0[1]; 2169bfc6e5fbSMichael Chan __le32 enables; 2170bfc6e5fbSMichael Chan #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2171bfc6e5fbSMichael Chan __le16 schq_id; 2172bfc6e5fbSMichael Chan __le16 traffic_class; 2173bfc6e5fbSMichael Chan u8 unused_1[4]; 2174460c2577SMichael Chan }; 2175460c2577SMichael Chan 21769d6b648cSMichael Chan /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2177460c2577SMichael Chan struct hwrm_func_qstats_ext_output { 2178460c2577SMichael Chan __le16 error_code; 2179460c2577SMichael Chan __le16 req_type; 2180460c2577SMichael Chan __le16 seq_id; 2181460c2577SMichael Chan __le16 resp_len; 2182460c2577SMichael Chan __le64 rx_ucast_pkts; 2183460c2577SMichael Chan __le64 rx_mcast_pkts; 2184460c2577SMichael Chan __le64 rx_bcast_pkts; 2185460c2577SMichael Chan __le64 rx_discard_pkts; 2186bfc6e5fbSMichael Chan __le64 rx_error_pkts; 2187460c2577SMichael Chan __le64 rx_ucast_bytes; 2188460c2577SMichael Chan __le64 rx_mcast_bytes; 2189460c2577SMichael Chan __le64 rx_bcast_bytes; 2190460c2577SMichael Chan __le64 tx_ucast_pkts; 2191460c2577SMichael Chan __le64 tx_mcast_pkts; 2192460c2577SMichael Chan __le64 tx_bcast_pkts; 2193bfc6e5fbSMichael Chan __le64 tx_error_pkts; 2194460c2577SMichael Chan __le64 tx_discard_pkts; 2195460c2577SMichael Chan __le64 tx_ucast_bytes; 2196460c2577SMichael Chan __le64 tx_mcast_bytes; 2197460c2577SMichael Chan __le64 tx_bcast_bytes; 2198460c2577SMichael Chan __le64 rx_tpa_eligible_pkt; 2199460c2577SMichael Chan __le64 rx_tpa_eligible_bytes; 2200460c2577SMichael Chan __le64 rx_tpa_pkt; 2201460c2577SMichael Chan __le64 rx_tpa_bytes; 2202460c2577SMichael Chan __le64 rx_tpa_errors; 22039d6b648cSMichael Chan __le64 rx_tpa_events; 2204460c2577SMichael Chan u8 unused_0[7]; 2205460c2577SMichael Chan u8 valid; 2206460c2577SMichael Chan }; 2207460c2577SMichael Chan 2208894aa69aSMichael Chan /* hwrm_func_clr_stats_input (size:192b/24B) */ 2209c0c050c5SMichael Chan struct hwrm_func_clr_stats_input { 2210c0c050c5SMichael Chan __le16 req_type; 2211c0c050c5SMichael Chan __le16 cmpl_ring; 2212c0c050c5SMichael Chan __le16 seq_id; 2213c0c050c5SMichael Chan __le16 target_id; 2214c0c050c5SMichael Chan __le64 resp_addr; 2215c0c050c5SMichael Chan __le16 fid; 2216894aa69aSMichael Chan u8 unused_0[6]; 2217c0c050c5SMichael Chan }; 2218c0c050c5SMichael Chan 2219894aa69aSMichael Chan /* hwrm_func_clr_stats_output (size:128b/16B) */ 2220c0c050c5SMichael Chan struct hwrm_func_clr_stats_output { 2221c0c050c5SMichael Chan __le16 error_code; 2222c0c050c5SMichael Chan __le16 req_type; 2223c0c050c5SMichael Chan __le16 seq_id; 2224c0c050c5SMichael Chan __le16 resp_len; 2225894aa69aSMichael Chan u8 unused_0[7]; 2226c0c050c5SMichael Chan u8 valid; 2227c0c050c5SMichael Chan }; 2228c0c050c5SMichael Chan 2229894aa69aSMichael Chan /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2230c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_input { 2231c0c050c5SMichael Chan __le16 req_type; 2232c0c050c5SMichael Chan __le16 cmpl_ring; 2233c0c050c5SMichael Chan __le16 seq_id; 2234c0c050c5SMichael Chan __le16 target_id; 2235c0c050c5SMichael Chan __le64 resp_addr; 2236c0c050c5SMichael Chan __le16 vf_id; 2237894aa69aSMichael Chan u8 unused_0[6]; 2238c0c050c5SMichael Chan }; 2239c0c050c5SMichael Chan 2240894aa69aSMichael Chan /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2241c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_output { 2242c0c050c5SMichael Chan __le16 error_code; 2243c0c050c5SMichael Chan __le16 req_type; 2244c0c050c5SMichael Chan __le16 seq_id; 2245c0c050c5SMichael Chan __le16 resp_len; 2246894aa69aSMichael Chan u8 unused_0[7]; 2247c0c050c5SMichael Chan u8 valid; 2248c0c050c5SMichael Chan }; 2249c0c050c5SMichael Chan 2250d4f52de0SMichael Chan /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2251c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_input { 2252c0c050c5SMichael Chan __le16 req_type; 2253c0c050c5SMichael Chan __le16 cmpl_ring; 2254c0c050c5SMichael Chan __le16 seq_id; 2255c0c050c5SMichael Chan __le16 target_id; 2256c0c050c5SMichael Chan __le64 resp_addr; 2257c0c050c5SMichael Chan __le32 flags; 2258c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2259c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2260d4f52de0SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 226131d357c0SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 22623322479eSMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 22633293ec23SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 226441136ab3SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 226516db6323SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 226678eeadb8SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2267fbfee257SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 226884a911dbSMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2269c0c050c5SMichael Chan __le32 enables; 2270c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2271c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2272c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2273c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2274c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2275c0c050c5SMichael Chan __le16 os_type; 2276441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2277441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2278441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2279441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2280441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2281441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2282441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2283441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2284441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2285441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 228616d663a6SMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2287894aa69aSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2288d4f52de0SMichael Chan u8 ver_maj_8b; 2289d4f52de0SMichael Chan u8 ver_min_8b; 2290d4f52de0SMichael Chan u8 ver_upd_8b; 2291894aa69aSMichael Chan u8 unused_0[3]; 2292c0c050c5SMichael Chan __le32 timestamp; 2293894aa69aSMichael Chan u8 unused_1[4]; 2294c0c050c5SMichael Chan __le32 vf_req_fwd[8]; 2295c0c050c5SMichael Chan __le32 async_event_fwd[8]; 2296d4f52de0SMichael Chan __le16 ver_maj; 2297d4f52de0SMichael Chan __le16 ver_min; 2298d4f52de0SMichael Chan __le16 ver_upd; 2299d4f52de0SMichael Chan __le16 ver_patch; 2300c0c050c5SMichael Chan }; 2301c0c050c5SMichael Chan 2302894aa69aSMichael Chan /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2303c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_output { 2304c0c050c5SMichael Chan __le16 error_code; 2305c0c050c5SMichael Chan __le16 req_type; 2306c0c050c5SMichael Chan __le16 seq_id; 2307c0c050c5SMichael Chan __le16 resp_len; 23086fc92c33SMichael Chan __le32 flags; 23096fc92c33SMichael Chan #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 23106fc92c33SMichael Chan u8 unused_0[3]; 2311c0c050c5SMichael Chan u8 valid; 2312c0c050c5SMichael Chan }; 2313c0c050c5SMichael Chan 2314894aa69aSMichael Chan /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2315c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_input { 2316c0c050c5SMichael Chan __le16 req_type; 2317c0c050c5SMichael Chan __le16 cmpl_ring; 2318c0c050c5SMichael Chan __le16 seq_id; 2319c0c050c5SMichael Chan __le16 target_id; 2320c0c050c5SMichael Chan __le64 resp_addr; 2321c0c050c5SMichael Chan __le32 flags; 2322c0c050c5SMichael Chan #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2323894aa69aSMichael Chan u8 unused_0[4]; 2324c0c050c5SMichael Chan }; 2325c0c050c5SMichael Chan 2326894aa69aSMichael Chan /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2327c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_output { 2328c0c050c5SMichael Chan __le16 error_code; 2329c0c050c5SMichael Chan __le16 req_type; 2330c0c050c5SMichael Chan __le16 seq_id; 2331c0c050c5SMichael Chan __le16 resp_len; 2332894aa69aSMichael Chan u8 unused_0[7]; 2333c0c050c5SMichael Chan u8 valid; 2334c0c050c5SMichael Chan }; 2335c0c050c5SMichael Chan 2336894aa69aSMichael Chan /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2337c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_input { 2338c0c050c5SMichael Chan __le16 req_type; 2339c0c050c5SMichael Chan __le16 cmpl_ring; 2340c0c050c5SMichael Chan __le16 seq_id; 2341c0c050c5SMichael Chan __le16 target_id; 2342c0c050c5SMichael Chan __le64 resp_addr; 2343c0c050c5SMichael Chan __le32 enables; 2344c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2345c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2346c0c050c5SMichael Chan __le16 vf_id; 2347c0c050c5SMichael Chan __le16 req_buf_num_pages; 2348c0c050c5SMichael Chan __le16 req_buf_page_size; 2349441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2350441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2351441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2352441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2353441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2354441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2355441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2356894aa69aSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2357c0c050c5SMichael Chan __le16 req_buf_len; 2358c0c050c5SMichael Chan __le16 resp_buf_len; 2359894aa69aSMichael Chan u8 unused_0[2]; 2360c0c050c5SMichael Chan __le64 req_buf_page_addr0; 2361c0c050c5SMichael Chan __le64 req_buf_page_addr1; 2362c0c050c5SMichael Chan __le64 req_buf_page_addr2; 2363c0c050c5SMichael Chan __le64 req_buf_page_addr3; 2364c0c050c5SMichael Chan __le64 req_buf_page_addr4; 2365c0c050c5SMichael Chan __le64 req_buf_page_addr5; 2366c0c050c5SMichael Chan __le64 req_buf_page_addr6; 2367c0c050c5SMichael Chan __le64 req_buf_page_addr7; 2368c0c050c5SMichael Chan __le64 req_buf_page_addr8; 2369c0c050c5SMichael Chan __le64 req_buf_page_addr9; 2370c0c050c5SMichael Chan __le64 error_buf_addr; 2371c0c050c5SMichael Chan __le64 resp_buf_addr; 2372c0c050c5SMichael Chan }; 2373c0c050c5SMichael Chan 2374894aa69aSMichael Chan /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2375c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_output { 2376c0c050c5SMichael Chan __le16 error_code; 2377c0c050c5SMichael Chan __le16 req_type; 2378c0c050c5SMichael Chan __le16 seq_id; 2379c0c050c5SMichael Chan __le16 resp_len; 2380894aa69aSMichael Chan u8 unused_0[7]; 2381c0c050c5SMichael Chan u8 valid; 2382c0c050c5SMichael Chan }; 2383c0c050c5SMichael Chan 2384894aa69aSMichael Chan /* hwrm_func_drv_qver_input (size:192b/24B) */ 2385c0c050c5SMichael Chan struct hwrm_func_drv_qver_input { 2386c0c050c5SMichael Chan __le16 req_type; 2387c0c050c5SMichael Chan __le16 cmpl_ring; 2388c0c050c5SMichael Chan __le16 seq_id; 2389c0c050c5SMichael Chan __le16 target_id; 2390c0c050c5SMichael Chan __le64 resp_addr; 2391c193554eSMichael Chan __le32 reserved; 2392c0c050c5SMichael Chan __le16 fid; 2393894aa69aSMichael Chan u8 unused_0[2]; 2394c0c050c5SMichael Chan }; 2395c0c050c5SMichael Chan 23966fc92c33SMichael Chan /* hwrm_func_drv_qver_output (size:256b/32B) */ 2397c0c050c5SMichael Chan struct hwrm_func_drv_qver_output { 2398c0c050c5SMichael Chan __le16 error_code; 2399c0c050c5SMichael Chan __le16 req_type; 2400c0c050c5SMichael Chan __le16 seq_id; 2401c0c050c5SMichael Chan __le16 resp_len; 2402c0c050c5SMichael Chan __le16 os_type; 2403441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2404441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2405441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2406441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2407441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2408441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2409441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2410441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2411441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2412441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 241387c374deSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2414894aa69aSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2415d4f52de0SMichael Chan u8 ver_maj_8b; 2416d4f52de0SMichael Chan u8 ver_min_8b; 2417d4f52de0SMichael Chan u8 ver_upd_8b; 24186fc92c33SMichael Chan u8 unused_0[3]; 2419d4f52de0SMichael Chan __le16 ver_maj; 2420d4f52de0SMichael Chan __le16 ver_min; 2421d4f52de0SMichael Chan __le16 ver_upd; 2422d4f52de0SMichael Chan __le16 ver_patch; 24236fc92c33SMichael Chan u8 unused_1[7]; 24246fc92c33SMichael Chan u8 valid; 2425c0c050c5SMichael Chan }; 2426c0c050c5SMichael Chan 2427894aa69aSMichael Chan /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2428894aa69aSMichael Chan struct hwrm_func_resource_qcaps_input { 2429894aa69aSMichael Chan __le16 req_type; 2430894aa69aSMichael Chan __le16 cmpl_ring; 2431894aa69aSMichael Chan __le16 seq_id; 2432894aa69aSMichael Chan __le16 target_id; 2433894aa69aSMichael Chan __le64 resp_addr; 2434894aa69aSMichael Chan __le16 fid; 2435894aa69aSMichael Chan u8 unused_0[6]; 2436894aa69aSMichael Chan }; 2437894aa69aSMichael Chan 2438fbfee257SMichael Chan /* hwrm_func_resource_qcaps_output (size:512b/64B) */ 2439894aa69aSMichael Chan struct hwrm_func_resource_qcaps_output { 2440894aa69aSMichael Chan __le16 error_code; 2441894aa69aSMichael Chan __le16 req_type; 2442894aa69aSMichael Chan __le16 seq_id; 2443894aa69aSMichael Chan __le16 resp_len; 2444894aa69aSMichael Chan __le16 max_vfs; 2445894aa69aSMichael Chan __le16 max_msix; 2446894aa69aSMichael Chan __le16 vf_reservation_strategy; 2447894aa69aSMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2448894aa69aSMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2449d4f52de0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2450d4f52de0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2451894aa69aSMichael Chan __le16 min_rsscos_ctx; 2452894aa69aSMichael Chan __le16 max_rsscos_ctx; 2453894aa69aSMichael Chan __le16 min_cmpl_rings; 2454894aa69aSMichael Chan __le16 max_cmpl_rings; 2455894aa69aSMichael Chan __le16 min_tx_rings; 2456894aa69aSMichael Chan __le16 max_tx_rings; 2457894aa69aSMichael Chan __le16 min_rx_rings; 2458894aa69aSMichael Chan __le16 max_rx_rings; 2459894aa69aSMichael Chan __le16 min_l2_ctxs; 2460894aa69aSMichael Chan __le16 max_l2_ctxs; 2461894aa69aSMichael Chan __le16 min_vnics; 2462894aa69aSMichael Chan __le16 max_vnics; 2463894aa69aSMichael Chan __le16 min_stat_ctx; 2464894aa69aSMichael Chan __le16 max_stat_ctx; 2465894aa69aSMichael Chan __le16 min_hw_ring_grps; 2466894aa69aSMichael Chan __le16 max_hw_ring_grps; 2467d4f52de0SMichael Chan __le16 max_tx_scheduler_inputs; 246831d357c0SMichael Chan __le16 flags; 246931d357c0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2470fbfee257SMichael Chan __le16 min_tx_key_ctxs; 2471fbfee257SMichael Chan __le16 max_tx_key_ctxs; 2472fbfee257SMichael Chan __le16 min_rx_key_ctxs; 2473fbfee257SMichael Chan __le16 max_rx_key_ctxs; 247431d357c0SMichael Chan u8 unused_0[5]; 2475894aa69aSMichael Chan u8 valid; 2476894aa69aSMichael Chan }; 2477894aa69aSMichael Chan 2478fbfee257SMichael Chan /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ 2479894aa69aSMichael Chan struct hwrm_func_vf_resource_cfg_input { 2480894aa69aSMichael Chan __le16 req_type; 2481894aa69aSMichael Chan __le16 cmpl_ring; 2482894aa69aSMichael Chan __le16 seq_id; 2483894aa69aSMichael Chan __le16 target_id; 2484894aa69aSMichael Chan __le64 resp_addr; 2485894aa69aSMichael Chan __le16 vf_id; 2486894aa69aSMichael Chan __le16 max_msix; 2487894aa69aSMichael Chan __le16 min_rsscos_ctx; 2488894aa69aSMichael Chan __le16 max_rsscos_ctx; 2489894aa69aSMichael Chan __le16 min_cmpl_rings; 2490894aa69aSMichael Chan __le16 max_cmpl_rings; 2491894aa69aSMichael Chan __le16 min_tx_rings; 2492894aa69aSMichael Chan __le16 max_tx_rings; 2493894aa69aSMichael Chan __le16 min_rx_rings; 2494894aa69aSMichael Chan __le16 max_rx_rings; 2495894aa69aSMichael Chan __le16 min_l2_ctxs; 2496894aa69aSMichael Chan __le16 max_l2_ctxs; 2497894aa69aSMichael Chan __le16 min_vnics; 2498894aa69aSMichael Chan __le16 max_vnics; 2499894aa69aSMichael Chan __le16 min_stat_ctx; 2500894aa69aSMichael Chan __le16 max_stat_ctx; 2501894aa69aSMichael Chan __le16 min_hw_ring_grps; 2502894aa69aSMichael Chan __le16 max_hw_ring_grps; 250331d357c0SMichael Chan __le16 flags; 250431d357c0SMichael Chan #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2505fbfee257SMichael Chan __le16 min_tx_key_ctxs; 2506fbfee257SMichael Chan __le16 max_tx_key_ctxs; 2507fbfee257SMichael Chan __le16 min_rx_key_ctxs; 2508fbfee257SMichael Chan __le16 max_rx_key_ctxs; 250931d357c0SMichael Chan u8 unused_0[2]; 2510894aa69aSMichael Chan }; 2511894aa69aSMichael Chan 2512894aa69aSMichael Chan /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2513894aa69aSMichael Chan struct hwrm_func_vf_resource_cfg_output { 2514894aa69aSMichael Chan __le16 error_code; 2515894aa69aSMichael Chan __le16 req_type; 2516894aa69aSMichael Chan __le16 seq_id; 2517894aa69aSMichael Chan __le16 resp_len; 2518894aa69aSMichael Chan __le16 reserved_rsscos_ctx; 2519894aa69aSMichael Chan __le16 reserved_cmpl_rings; 2520894aa69aSMichael Chan __le16 reserved_tx_rings; 2521894aa69aSMichael Chan __le16 reserved_rx_rings; 2522894aa69aSMichael Chan __le16 reserved_l2_ctxs; 2523894aa69aSMichael Chan __le16 reserved_vnics; 2524894aa69aSMichael Chan __le16 reserved_stat_ctx; 2525894aa69aSMichael Chan __le16 reserved_hw_ring_grps; 2526fbfee257SMichael Chan __le16 reserved_tx_key_ctxs; 2527fbfee257SMichael Chan __le16 reserved_rx_key_ctxs; 2528fbfee257SMichael Chan u8 unused_0[3]; 2529894aa69aSMichael Chan u8 valid; 2530894aa69aSMichael Chan }; 2531894aa69aSMichael Chan 25326fc92c33SMichael Chan /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 25336fc92c33SMichael Chan struct hwrm_func_backing_store_qcaps_input { 25346fc92c33SMichael Chan __le16 req_type; 25356fc92c33SMichael Chan __le16 cmpl_ring; 25366fc92c33SMichael Chan __le16 seq_id; 25376fc92c33SMichael Chan __le16 target_id; 25386fc92c33SMichael Chan __le64 resp_addr; 25396fc92c33SMichael Chan }; 25406fc92c33SMichael Chan 254178eeadb8SMichael Chan /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 25426fc92c33SMichael Chan struct hwrm_func_backing_store_qcaps_output { 25436fc92c33SMichael Chan __le16 error_code; 25446fc92c33SMichael Chan __le16 req_type; 25456fc92c33SMichael Chan __le16 seq_id; 25466fc92c33SMichael Chan __le16 resp_len; 25476fc92c33SMichael Chan __le32 qp_max_entries; 25486fc92c33SMichael Chan __le16 qp_min_qp1_entries; 25496fc92c33SMichael Chan __le16 qp_max_l2_entries; 25506fc92c33SMichael Chan __le16 qp_entry_size; 25516fc92c33SMichael Chan __le16 srq_max_l2_entries; 25526fc92c33SMichael Chan __le32 srq_max_entries; 25536fc92c33SMichael Chan __le16 srq_entry_size; 25546fc92c33SMichael Chan __le16 cq_max_l2_entries; 25556fc92c33SMichael Chan __le32 cq_max_entries; 25566fc92c33SMichael Chan __le16 cq_entry_size; 25576fc92c33SMichael Chan __le16 vnic_max_vnic_entries; 25586fc92c33SMichael Chan __le16 vnic_max_ring_table_entries; 25596fc92c33SMichael Chan __le16 vnic_entry_size; 25606fc92c33SMichael Chan __le32 stat_max_entries; 25616fc92c33SMichael Chan __le16 stat_entry_size; 25626fc92c33SMichael Chan __le16 tqm_entry_size; 25636fc92c33SMichael Chan __le32 tqm_min_entries_per_ring; 25646fc92c33SMichael Chan __le32 tqm_max_entries_per_ring; 25656fc92c33SMichael Chan __le32 mrav_max_entries; 25666fc92c33SMichael Chan __le16 mrav_entry_size; 25676fc92c33SMichael Chan __le16 tim_entry_size; 25686fc92c33SMichael Chan __le32 tim_max_entries; 25694a50ddc2SMichael Chan __le16 mrav_num_entries_units; 257031d357c0SMichael Chan u8 tqm_entries_multiple; 257141136ab3SMichael Chan u8 ctx_kind_initializer; 257216db6323SMichael Chan __le16 ctx_init_mask; 257316db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 257416db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 257516db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 257616db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 257716db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 257816db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 257978eeadb8SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 258078eeadb8SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 258116db6323SMichael Chan u8 qp_init_offset; 258216db6323SMichael Chan u8 srq_init_offset; 258316db6323SMichael Chan u8 cq_init_offset; 258416db6323SMichael Chan u8 vnic_init_offset; 2585460c2577SMichael Chan u8 tqm_fp_rings_count; 258616db6323SMichael Chan u8 stat_init_offset; 258716db6323SMichael Chan u8 mrav_init_offset; 258831f67c2eSMichael Chan u8 tqm_fp_rings_count_ext; 258978eeadb8SMichael Chan u8 tkc_init_offset; 259078eeadb8SMichael Chan u8 rkc_init_offset; 259178eeadb8SMichael Chan __le16 tkc_entry_size; 259278eeadb8SMichael Chan __le16 rkc_entry_size; 259378eeadb8SMichael Chan __le32 tkc_max_entries; 259478eeadb8SMichael Chan __le32 rkc_max_entries; 25952895c153SMichael Chan u8 rsvd1[7]; 25966fc92c33SMichael Chan u8 valid; 25976fc92c33SMichael Chan }; 25986fc92c33SMichael Chan 259931f67c2eSMichael Chan /* tqm_fp_ring_cfg (size:128b/16B) */ 260031f67c2eSMichael Chan struct tqm_fp_ring_cfg { 260131f67c2eSMichael Chan u8 tqm_ring_pg_size_tqm_ring_lvl; 260231f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 260331f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 260431f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 260531f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 260631f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 260731f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 260831f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 260931f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 261031f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 261131f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 261231f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 261331f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 261431f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 261531f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 261631f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 261731f67c2eSMichael Chan u8 unused[3]; 261831f67c2eSMichael Chan __le32 tqm_ring_num_entries; 261931f67c2eSMichael Chan __le64 tqm_ring_page_dir; 262031f67c2eSMichael Chan }; 262131f67c2eSMichael Chan 262278eeadb8SMichael Chan /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 26236fc92c33SMichael Chan struct hwrm_func_backing_store_cfg_input { 26246fc92c33SMichael Chan __le16 req_type; 26256fc92c33SMichael Chan __le16 cmpl_ring; 26266fc92c33SMichael Chan __le16 seq_id; 26276fc92c33SMichael Chan __le16 target_id; 26286fc92c33SMichael Chan __le64 resp_addr; 26296fc92c33SMichael Chan __le32 flags; 26306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 26314a50ddc2SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 26326fc92c33SMichael Chan __le32 enables; 26336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 26346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 26356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 26366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 26376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 26386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 26396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 26406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 26416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 26426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 26436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 26446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 26456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 26466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 26476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 26486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 264916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 265016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 265116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 265278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 265378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 26546fc92c33SMichael Chan u8 qpc_pg_size_qpc_lvl; 26556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 26566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 26576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 26586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 26596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 26606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 26616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 26626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 26636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 26646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 26656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 26666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 26676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 26686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 26696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 26706fc92c33SMichael Chan u8 srq_pg_size_srq_lvl; 26716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 26726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 26736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 26746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 26756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 26766fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 26776fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 26786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 26796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 26806fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 26816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 26826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 26836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 26846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 26856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 26866fc92c33SMichael Chan u8 cq_pg_size_cq_lvl; 26876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 26886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 26896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 26906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 26916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 26926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 26936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 26946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 26956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 26966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 26976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 26986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 26996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 27006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 27016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 27026fc92c33SMichael Chan u8 vnic_pg_size_vnic_lvl; 27036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 27046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 27056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 27066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 27076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 27086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 27096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 27106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 27116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 27126fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 27136fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 27146fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 27156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 27166fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 27176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 27186fc92c33SMichael Chan u8 stat_pg_size_stat_lvl; 27196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 27206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 27216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 27226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 27236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 27246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 27256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 27266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 27276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 27286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 27296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 27306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 27316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 27326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 27336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 27346fc92c33SMichael Chan u8 tqm_sp_pg_size_tqm_sp_lvl; 27356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 27366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 27376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 27386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 27396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 27406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 27416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 27426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 27436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 27446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 27456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 27466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 27476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 27486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 27496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 27506fc92c33SMichael Chan u8 tqm_ring0_pg_size_tqm_ring0_lvl; 27516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 27526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 27536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 27546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 27556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 27566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 27576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 27586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 27596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 27606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 27616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 27626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 27636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 27646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 27656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 27666fc92c33SMichael Chan u8 tqm_ring1_pg_size_tqm_ring1_lvl; 27676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 27686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 27696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 27706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 27716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 27726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 27736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 27746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 27756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 27766fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 27776fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 27786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 27796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 27806fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 27816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 27826fc92c33SMichael Chan u8 tqm_ring2_pg_size_tqm_ring2_lvl; 27836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 27846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 27856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 27866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 27876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 27886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 27896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 27906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 27916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 27926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 27936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 27946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 27956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 27966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 27976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 27986fc92c33SMichael Chan u8 tqm_ring3_pg_size_tqm_ring3_lvl; 27996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 28006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 28016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 28026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 28036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 28046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 28056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 28066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 28076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 28086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 28096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 28106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 28116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 28126fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 28136fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 28146fc92c33SMichael Chan u8 tqm_ring4_pg_size_tqm_ring4_lvl; 28156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 28166fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 28176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 28186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 28196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 28206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 28216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 28226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 28236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 28246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 28256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 28266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 28276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 28286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 28296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 28306fc92c33SMichael Chan u8 tqm_ring5_pg_size_tqm_ring5_lvl; 28316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 28326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 28336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 28346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 28356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 28366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 28376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 28386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 28396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 28406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 28416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 28426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 28436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 28446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 28456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 28466fc92c33SMichael Chan u8 tqm_ring6_pg_size_tqm_ring6_lvl; 28476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 28486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 28496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 28506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 28516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 28526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 28536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 28546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 28556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 28566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 28576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 28586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 28596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 28606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 28616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 28626fc92c33SMichael Chan u8 tqm_ring7_pg_size_tqm_ring7_lvl; 28636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 28646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 28656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 28666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 28676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 28686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 28696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 28706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 28716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 28726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 28736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 28746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 28756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 28766fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 28776fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 28786fc92c33SMichael Chan u8 mrav_pg_size_mrav_lvl; 28796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 28806fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 28816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 28826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 28836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 28846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 28856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 28866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 28876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 28886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 28896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 28906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 28916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 28926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 28936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 28946fc92c33SMichael Chan u8 tim_pg_size_tim_lvl; 28956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 28966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 28976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 28986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 28996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 29006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 29016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 29026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 29036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 29046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 29056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 29066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 29076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 29086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 29096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 29106fc92c33SMichael Chan __le64 qpc_page_dir; 29116fc92c33SMichael Chan __le64 srq_page_dir; 29126fc92c33SMichael Chan __le64 cq_page_dir; 29136fc92c33SMichael Chan __le64 vnic_page_dir; 29146fc92c33SMichael Chan __le64 stat_page_dir; 29156fc92c33SMichael Chan __le64 tqm_sp_page_dir; 29166fc92c33SMichael Chan __le64 tqm_ring0_page_dir; 29176fc92c33SMichael Chan __le64 tqm_ring1_page_dir; 29186fc92c33SMichael Chan __le64 tqm_ring2_page_dir; 29196fc92c33SMichael Chan __le64 tqm_ring3_page_dir; 29206fc92c33SMichael Chan __le64 tqm_ring4_page_dir; 29216fc92c33SMichael Chan __le64 tqm_ring5_page_dir; 29226fc92c33SMichael Chan __le64 tqm_ring6_page_dir; 29236fc92c33SMichael Chan __le64 tqm_ring7_page_dir; 29246fc92c33SMichael Chan __le64 mrav_page_dir; 29256fc92c33SMichael Chan __le64 tim_page_dir; 29266fc92c33SMichael Chan __le32 qp_num_entries; 29276fc92c33SMichael Chan __le32 srq_num_entries; 29286fc92c33SMichael Chan __le32 cq_num_entries; 29296fc92c33SMichael Chan __le32 stat_num_entries; 29306fc92c33SMichael Chan __le32 tqm_sp_num_entries; 29316fc92c33SMichael Chan __le32 tqm_ring0_num_entries; 29326fc92c33SMichael Chan __le32 tqm_ring1_num_entries; 29336fc92c33SMichael Chan __le32 tqm_ring2_num_entries; 29346fc92c33SMichael Chan __le32 tqm_ring3_num_entries; 29356fc92c33SMichael Chan __le32 tqm_ring4_num_entries; 29366fc92c33SMichael Chan __le32 tqm_ring5_num_entries; 29376fc92c33SMichael Chan __le32 tqm_ring6_num_entries; 29386fc92c33SMichael Chan __le32 tqm_ring7_num_entries; 29396fc92c33SMichael Chan __le32 mrav_num_entries; 29406fc92c33SMichael Chan __le32 tim_num_entries; 29416fc92c33SMichael Chan __le16 qp_num_qp1_entries; 29426fc92c33SMichael Chan __le16 qp_num_l2_entries; 29436fc92c33SMichael Chan __le16 qp_entry_size; 29446fc92c33SMichael Chan __le16 srq_num_l2_entries; 29456fc92c33SMichael Chan __le16 srq_entry_size; 29466fc92c33SMichael Chan __le16 cq_num_l2_entries; 29476fc92c33SMichael Chan __le16 cq_entry_size; 29486fc92c33SMichael Chan __le16 vnic_num_vnic_entries; 29496fc92c33SMichael Chan __le16 vnic_num_ring_table_entries; 29506fc92c33SMichael Chan __le16 vnic_entry_size; 29516fc92c33SMichael Chan __le16 stat_entry_size; 29526fc92c33SMichael Chan __le16 tqm_entry_size; 29536fc92c33SMichael Chan __le16 mrav_entry_size; 29546fc92c33SMichael Chan __le16 tim_entry_size; 295516db6323SMichael Chan u8 tqm_ring8_pg_size_tqm_ring_lvl; 295616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 295716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 295816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 295916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 296016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 296116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 296216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 296316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 296416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 296516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 296616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 296716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 296816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 296916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 297016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 297116db6323SMichael Chan u8 ring8_unused[3]; 297216db6323SMichael Chan __le32 tqm_ring8_num_entries; 297316db6323SMichael Chan __le64 tqm_ring8_page_dir; 297416db6323SMichael Chan u8 tqm_ring9_pg_size_tqm_ring_lvl; 297516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 297616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 297716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 297816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 297916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 298016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 298116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 298216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 298316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 298416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 298516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 298616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 298716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 298816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 298916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 299016db6323SMichael Chan u8 ring9_unused[3]; 299116db6323SMichael Chan __le32 tqm_ring9_num_entries; 299216db6323SMichael Chan __le64 tqm_ring9_page_dir; 299316db6323SMichael Chan u8 tqm_ring10_pg_size_tqm_ring_lvl; 299416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 299516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 299616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 299716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 299816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 299916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 300016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 300116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 300216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 300316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 300416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 300516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 300616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 300716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 300816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 300916db6323SMichael Chan u8 ring10_unused[3]; 301016db6323SMichael Chan __le32 tqm_ring10_num_entries; 301116db6323SMichael Chan __le64 tqm_ring10_page_dir; 301278eeadb8SMichael Chan __le32 tkc_num_entries; 301378eeadb8SMichael Chan __le32 rkc_num_entries; 301478eeadb8SMichael Chan __le64 tkc_page_dir; 301578eeadb8SMichael Chan __le64 rkc_page_dir; 301678eeadb8SMichael Chan __le16 tkc_entry_size; 301778eeadb8SMichael Chan __le16 rkc_entry_size; 301878eeadb8SMichael Chan u8 tkc_pg_size_tkc_lvl; 301978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 302078eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 302178eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 302278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 302378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 302478eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 302578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 302678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 302778eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 302878eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 302978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 303078eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 303178eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 303278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 303378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 303478eeadb8SMichael Chan u8 rkc_pg_size_rkc_lvl; 303578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 303678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 303778eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 303878eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 303978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 304078eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 304178eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 304278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 304378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 304478eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 304578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 304678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 304778eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 304878eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 304978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 305078eeadb8SMichael Chan u8 rsvd[2]; 30516fc92c33SMichael Chan }; 30526fc92c33SMichael Chan 30536fc92c33SMichael Chan /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 30546fc92c33SMichael Chan struct hwrm_func_backing_store_cfg_output { 30556fc92c33SMichael Chan __le16 error_code; 30566fc92c33SMichael Chan __le16 req_type; 30576fc92c33SMichael Chan __le16 seq_id; 30586fc92c33SMichael Chan __le16 resp_len; 30596fc92c33SMichael Chan u8 unused_0[7]; 30606fc92c33SMichael Chan u8 valid; 30616fc92c33SMichael Chan }; 30626fc92c33SMichael Chan 30633293ec23SMichael Chan /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 30643293ec23SMichael Chan struct hwrm_error_recovery_qcfg_input { 30653293ec23SMichael Chan __le16 req_type; 30663293ec23SMichael Chan __le16 cmpl_ring; 30673293ec23SMichael Chan __le16 seq_id; 30683293ec23SMichael Chan __le16 target_id; 30693293ec23SMichael Chan __le64 resp_addr; 30703293ec23SMichael Chan u8 unused_0[8]; 30713293ec23SMichael Chan }; 30723293ec23SMichael Chan 30733293ec23SMichael Chan /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 30743293ec23SMichael Chan struct hwrm_error_recovery_qcfg_output { 30753293ec23SMichael Chan __le16 error_code; 30763293ec23SMichael Chan __le16 req_type; 30773293ec23SMichael Chan __le16 seq_id; 30783293ec23SMichael Chan __le16 resp_len; 30793293ec23SMichael Chan __le32 flags; 30803293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 30813293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 30823293ec23SMichael Chan __le32 driver_polling_freq; 30833293ec23SMichael Chan __le32 master_func_wait_period; 30843293ec23SMichael Chan __le32 normal_func_wait_period; 30853293ec23SMichael Chan __le32 master_func_wait_period_after_reset; 30863293ec23SMichael Chan __le32 max_bailout_time_after_reset; 30873293ec23SMichael Chan __le32 fw_health_status_reg; 30883293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 30893293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 30903293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 30913293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 30923293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 30933293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 30943293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 30953293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 30963293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 30973293ec23SMichael Chan __le32 fw_heartbeat_reg; 30983293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 30993293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 31003293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 31013293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 31023293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 31033293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 31043293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 31053293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 31063293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 31073293ec23SMichael Chan __le32 fw_reset_cnt_reg; 31083293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 31093293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 31103293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 31113293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 31123293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 31133293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 31143293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 31153293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 31163293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 31173293ec23SMichael Chan __le32 reset_inprogress_reg; 31183293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 31193293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 31203293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 31213293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 31223293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 31233293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 31243293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 31253293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 31263293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 31273293ec23SMichael Chan __le32 reset_inprogress_reg_mask; 31283293ec23SMichael Chan u8 unused_0[3]; 31293293ec23SMichael Chan u8 reg_array_cnt; 31303293ec23SMichael Chan __le32 reset_reg[16]; 31313293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 31323293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 31333293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 31343293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 31353293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 31363293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 31373293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 31383293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 31393293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 31403293ec23SMichael Chan __le32 reset_reg_val[16]; 31413293ec23SMichael Chan u8 delay_after_reset[16]; 3142460c2577SMichael Chan __le32 err_recovery_cnt_reg; 3143460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3144460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3145460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3146460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3147460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3148460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3149460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3150460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3151460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3152460c2577SMichael Chan u8 unused_1[3]; 31533293ec23SMichael Chan u8 valid; 31543293ec23SMichael Chan }; 31553293ec23SMichael Chan 315631f67c2eSMichael Chan /* hwrm_func_echo_response_input (size:192b/24B) */ 315731f67c2eSMichael Chan struct hwrm_func_echo_response_input { 315831f67c2eSMichael Chan __le16 req_type; 315931f67c2eSMichael Chan __le16 cmpl_ring; 316031f67c2eSMichael Chan __le16 seq_id; 316131f67c2eSMichael Chan __le16 target_id; 316231f67c2eSMichael Chan __le64 resp_addr; 316331f67c2eSMichael Chan __le32 event_data1; 316431f67c2eSMichael Chan __le32 event_data2; 316531f67c2eSMichael Chan }; 316631f67c2eSMichael Chan 316731f67c2eSMichael Chan /* hwrm_func_echo_response_output (size:128b/16B) */ 316831f67c2eSMichael Chan struct hwrm_func_echo_response_output { 316931f67c2eSMichael Chan __le16 error_code; 317031f67c2eSMichael Chan __le16 req_type; 317131f67c2eSMichael Chan __le16 seq_id; 317231f67c2eSMichael Chan __le16 resp_len; 317331f67c2eSMichael Chan u8 unused_0[7]; 317431f67c2eSMichael Chan u8 valid; 317531f67c2eSMichael Chan }; 317631f67c2eSMichael Chan 317778eeadb8SMichael Chan /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 317878eeadb8SMichael Chan struct hwrm_func_ptp_pin_qcfg_input { 317978eeadb8SMichael Chan __le16 req_type; 318078eeadb8SMichael Chan __le16 cmpl_ring; 318178eeadb8SMichael Chan __le16 seq_id; 318278eeadb8SMichael Chan __le16 target_id; 318378eeadb8SMichael Chan __le64 resp_addr; 318478eeadb8SMichael Chan u8 unused_0[8]; 318578eeadb8SMichael Chan }; 318678eeadb8SMichael Chan 318778eeadb8SMichael Chan /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 318878eeadb8SMichael Chan struct hwrm_func_ptp_pin_qcfg_output { 318978eeadb8SMichael Chan __le16 error_code; 319078eeadb8SMichael Chan __le16 req_type; 319178eeadb8SMichael Chan __le16 seq_id; 319278eeadb8SMichael Chan __le16 resp_len; 319378eeadb8SMichael Chan u8 num_pins; 319478eeadb8SMichael Chan u8 state; 319578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 319678eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 319778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 319878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 319978eeadb8SMichael Chan u8 pin0_usage; 320078eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 320178eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 320278eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 320378eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 320478eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 320578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 320678eeadb8SMichael Chan u8 pin1_usage; 320778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 320878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 320978eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 321078eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 321178eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 321278eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 321378eeadb8SMichael Chan u8 pin2_usage; 321478eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 321578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 321678eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 321778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 321878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 321984a911dbSMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 322084a911dbSMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 322184a911dbSMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 322278eeadb8SMichael Chan u8 pin3_usage; 322378eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 322478eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 322578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 322678eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 322778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 322884a911dbSMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 322984a911dbSMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 323084a911dbSMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 323178eeadb8SMichael Chan u8 unused_0; 323278eeadb8SMichael Chan u8 valid; 323378eeadb8SMichael Chan }; 323478eeadb8SMichael Chan 323578eeadb8SMichael Chan /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 323678eeadb8SMichael Chan struct hwrm_func_ptp_pin_cfg_input { 323778eeadb8SMichael Chan __le16 req_type; 323878eeadb8SMichael Chan __le16 cmpl_ring; 323978eeadb8SMichael Chan __le16 seq_id; 324078eeadb8SMichael Chan __le16 target_id; 324178eeadb8SMichael Chan __le64 resp_addr; 324278eeadb8SMichael Chan __le32 enables; 324378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 324478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 324578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 324678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 324778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 324878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 324978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 325078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 325178eeadb8SMichael Chan u8 pin0_state; 325278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 325378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 325478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 325578eeadb8SMichael Chan u8 pin0_usage; 325678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 325778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 325878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 325978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 326078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 326178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 326278eeadb8SMichael Chan u8 pin1_state; 326378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 326478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 326578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 326678eeadb8SMichael Chan u8 pin1_usage; 326778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 326878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 326978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 327078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 327178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 327278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 327378eeadb8SMichael Chan u8 pin2_state; 327478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 327578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 327678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 327778eeadb8SMichael Chan u8 pin2_usage; 327878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 327978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 328078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 328178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 328278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 328384a911dbSMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 328484a911dbSMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 328584a911dbSMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 328678eeadb8SMichael Chan u8 pin3_state; 328778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 328878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 328978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 329078eeadb8SMichael Chan u8 pin3_usage; 329178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 329278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 329378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 329478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 329578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 329684a911dbSMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 329784a911dbSMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 329884a911dbSMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 329978eeadb8SMichael Chan u8 unused_0[4]; 330078eeadb8SMichael Chan }; 330178eeadb8SMichael Chan 330278eeadb8SMichael Chan /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 330378eeadb8SMichael Chan struct hwrm_func_ptp_pin_cfg_output { 330478eeadb8SMichael Chan __le16 error_code; 330578eeadb8SMichael Chan __le16 req_type; 330678eeadb8SMichael Chan __le16 seq_id; 330778eeadb8SMichael Chan __le16 resp_len; 330878eeadb8SMichael Chan u8 unused_0[7]; 330978eeadb8SMichael Chan u8 valid; 331078eeadb8SMichael Chan }; 331178eeadb8SMichael Chan 33122895c153SMichael Chan /* hwrm_func_ptp_cfg_input (size:384b/48B) */ 331378eeadb8SMichael Chan struct hwrm_func_ptp_cfg_input { 331478eeadb8SMichael Chan __le16 req_type; 331578eeadb8SMichael Chan __le16 cmpl_ring; 331678eeadb8SMichael Chan __le16 seq_id; 331778eeadb8SMichael Chan __le16 target_id; 331878eeadb8SMichael Chan __le64 resp_addr; 331978eeadb8SMichael Chan __le16 enables; 332078eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 332178eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 332278eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 332378eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 332478eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 332578eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 33262895c153SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 332778eeadb8SMichael Chan u8 ptp_pps_event; 332878eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 332978eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 333078eeadb8SMichael Chan u8 ptp_freq_adj_dll_source; 333178eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 333278eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 333378eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 333478eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 333578eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 333678eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 333778eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 333878eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 333978eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 334078eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 334178eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 334278eeadb8SMichael Chan u8 ptp_freq_adj_dll_phase; 334378eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 334478eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 334578eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 334678eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 334778eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 334878eeadb8SMichael Chan u8 unused_0[3]; 334978eeadb8SMichael Chan __le32 ptp_freq_adj_ext_period; 335078eeadb8SMichael Chan __le32 ptp_freq_adj_ext_up; 335178eeadb8SMichael Chan __le32 ptp_freq_adj_ext_phase_lower; 335278eeadb8SMichael Chan __le32 ptp_freq_adj_ext_phase_upper; 33532895c153SMichael Chan __le64 ptp_set_time; 335478eeadb8SMichael Chan }; 335578eeadb8SMichael Chan 335678eeadb8SMichael Chan /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 335778eeadb8SMichael Chan struct hwrm_func_ptp_cfg_output { 335878eeadb8SMichael Chan __le16 error_code; 335978eeadb8SMichael Chan __le16 req_type; 336078eeadb8SMichael Chan __le16 seq_id; 336178eeadb8SMichael Chan __le16 resp_len; 336278eeadb8SMichael Chan u8 unused_0[7]; 336378eeadb8SMichael Chan u8 valid; 336478eeadb8SMichael Chan }; 336578eeadb8SMichael Chan 336678eeadb8SMichael Chan /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 336778eeadb8SMichael Chan struct hwrm_func_ptp_ts_query_input { 336878eeadb8SMichael Chan __le16 req_type; 336978eeadb8SMichael Chan __le16 cmpl_ring; 337078eeadb8SMichael Chan __le16 seq_id; 337178eeadb8SMichael Chan __le16 target_id; 337278eeadb8SMichael Chan __le64 resp_addr; 337378eeadb8SMichael Chan __le32 flags; 337478eeadb8SMichael Chan #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 337578eeadb8SMichael Chan #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 337678eeadb8SMichael Chan u8 unused_0[4]; 337778eeadb8SMichael Chan }; 337878eeadb8SMichael Chan 337978eeadb8SMichael Chan /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 338078eeadb8SMichael Chan struct hwrm_func_ptp_ts_query_output { 338178eeadb8SMichael Chan __le16 error_code; 338278eeadb8SMichael Chan __le16 req_type; 338378eeadb8SMichael Chan __le16 seq_id; 338478eeadb8SMichael Chan __le16 resp_len; 338578eeadb8SMichael Chan __le64 pps_event_ts; 338684a911dbSMichael Chan __le64 ptm_local_ts; 338784a911dbSMichael Chan __le64 ptm_system_ts; 338884a911dbSMichael Chan __le32 ptm_link_delay; 338978eeadb8SMichael Chan u8 unused_0[3]; 339078eeadb8SMichael Chan u8 valid; 339178eeadb8SMichael Chan }; 339278eeadb8SMichael Chan 33932895c153SMichael Chan /* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 33942895c153SMichael Chan struct hwrm_func_ptp_ext_cfg_input { 33952895c153SMichael Chan __le16 req_type; 33962895c153SMichael Chan __le16 cmpl_ring; 33972895c153SMichael Chan __le16 seq_id; 33982895c153SMichael Chan __le16 target_id; 33992895c153SMichael Chan __le64 resp_addr; 34002895c153SMichael Chan __le16 enables; 34012895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 34022895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 34032895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 34042895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 34052895c153SMichael Chan __le16 phc_master_fid; 34062895c153SMichael Chan __le16 phc_sec_fid; 34072895c153SMichael Chan u8 phc_sec_mode; 34082895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 34092895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 34102895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 34112895c153SMichael Chan #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 34122895c153SMichael Chan u8 unused_0; 34132895c153SMichael Chan __le32 failover_timer; 34142895c153SMichael Chan u8 unused_1[4]; 34152895c153SMichael Chan }; 34162895c153SMichael Chan 34172895c153SMichael Chan /* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 34182895c153SMichael Chan struct hwrm_func_ptp_ext_cfg_output { 34192895c153SMichael Chan __le16 error_code; 34202895c153SMichael Chan __le16 req_type; 34212895c153SMichael Chan __le16 seq_id; 34222895c153SMichael Chan __le16 resp_len; 34232895c153SMichael Chan u8 unused_0[7]; 34242895c153SMichael Chan u8 valid; 34252895c153SMichael Chan }; 34262895c153SMichael Chan 34272895c153SMichael Chan /* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 34282895c153SMichael Chan struct hwrm_func_ptp_ext_qcfg_input { 34292895c153SMichael Chan __le16 req_type; 34302895c153SMichael Chan __le16 cmpl_ring; 34312895c153SMichael Chan __le16 seq_id; 34322895c153SMichael Chan __le16 target_id; 34332895c153SMichael Chan __le64 resp_addr; 34342895c153SMichael Chan u8 unused_0[8]; 34352895c153SMichael Chan }; 34362895c153SMichael Chan 34372895c153SMichael Chan /* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 34382895c153SMichael Chan struct hwrm_func_ptp_ext_qcfg_output { 34392895c153SMichael Chan __le16 error_code; 34402895c153SMichael Chan __le16 req_type; 34412895c153SMichael Chan __le16 seq_id; 34422895c153SMichael Chan __le16 resp_len; 34432895c153SMichael Chan __le16 phc_master_fid; 34442895c153SMichael Chan __le16 phc_sec_fid; 34452895c153SMichael Chan __le16 phc_active_fid0; 34462895c153SMichael Chan __le16 phc_active_fid1; 34472895c153SMichael Chan __le32 last_failover_event; 34482895c153SMichael Chan __le16 from_fid; 34492895c153SMichael Chan __le16 to_fid; 34502895c153SMichael Chan u8 unused_0[7]; 34512895c153SMichael Chan u8 valid; 34522895c153SMichael Chan }; 34532895c153SMichael Chan 34542895c153SMichael Chan /* hwrm_func_backing_store_cfg_v2_input (size:448b/56B) */ 34552895c153SMichael Chan struct hwrm_func_backing_store_cfg_v2_input { 34562895c153SMichael Chan __le16 req_type; 34572895c153SMichael Chan __le16 cmpl_ring; 34582895c153SMichael Chan __le16 seq_id; 34592895c153SMichael Chan __le16 target_id; 34602895c153SMichael Chan __le64 resp_addr; 34612895c153SMichael Chan __le16 type; 34622895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 34632895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 34642895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 34652895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 34662895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 34672895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 34682895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 34692895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 34702895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 34712895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TKC 0x13UL 34722895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RKC 0x14UL 34732895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3474ad04cc05SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3475ad04cc05SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3476ad04cc05SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3477ad04cc05SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3478ad04cc05SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3479ad04cc05SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 34802895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 34812895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 34822895c153SMichael Chan __le16 instance; 34832895c153SMichael Chan __le32 flags; 34842895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 348584a911dbSMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 348684a911dbSMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 34872895c153SMichael Chan __le64 page_dir; 34882895c153SMichael Chan __le32 num_entries; 34892895c153SMichael Chan __le16 entry_size; 34902895c153SMichael Chan u8 page_size_pbl_level; 34912895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 34922895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 34932895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 34942895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 34952895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 34962895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 34972895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 34982895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 34992895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 35002895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 35012895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 35022895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 35032895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 35042895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 35052895c153SMichael Chan #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 35062895c153SMichael Chan u8 subtype_valid_cnt; 35072895c153SMichael Chan __le32 split_entry_0; 35082895c153SMichael Chan __le32 split_entry_1; 35092895c153SMichael Chan __le32 split_entry_2; 35102895c153SMichael Chan __le32 split_entry_3; 35112895c153SMichael Chan }; 35122895c153SMichael Chan 35132895c153SMichael Chan /* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 35142895c153SMichael Chan struct hwrm_func_backing_store_cfg_v2_output { 35152895c153SMichael Chan __le16 error_code; 35162895c153SMichael Chan __le16 req_type; 35172895c153SMichael Chan __le16 seq_id; 35182895c153SMichael Chan __le16 resp_len; 35192895c153SMichael Chan u8 rsvd0[7]; 35202895c153SMichael Chan u8 valid; 35212895c153SMichael Chan }; 35222895c153SMichael Chan 35232895c153SMichael Chan /* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 35242895c153SMichael Chan struct hwrm_func_backing_store_qcfg_v2_input { 35252895c153SMichael Chan __le16 req_type; 35262895c153SMichael Chan __le16 cmpl_ring; 35272895c153SMichael Chan __le16 seq_id; 35282895c153SMichael Chan __le16 target_id; 35292895c153SMichael Chan __le64 resp_addr; 35302895c153SMichael Chan __le16 type; 35312895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 35322895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 35332895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 35342895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 35352895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 35362895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 35372895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 35382895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 35392895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 35402895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TKC 0x13UL 35412895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RKC 0x14UL 35422895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3543ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3544ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3545ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3546ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3547ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3548ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QUIC_RKC 0x1bUL 35492895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 35502895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 35512895c153SMichael Chan __le16 instance; 35522895c153SMichael Chan u8 rsvd[4]; 35532895c153SMichael Chan }; 35542895c153SMichael Chan 35552895c153SMichael Chan /* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 35562895c153SMichael Chan struct hwrm_func_backing_store_qcfg_v2_output { 35572895c153SMichael Chan __le16 error_code; 35582895c153SMichael Chan __le16 req_type; 35592895c153SMichael Chan __le16 seq_id; 35602895c153SMichael Chan __le16 resp_len; 35612895c153SMichael Chan __le16 type; 35622895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 35632895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 35642895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 35652895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 35662895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 35672895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 35682895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 35692895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 35702895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 35712895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TKC 0x13UL 35722895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RKC 0x14UL 35732895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3574ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3575ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QUIC_RKC 0x1bUL 35762895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 35772895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 35782895c153SMichael Chan __le16 instance; 35792895c153SMichael Chan __le32 flags; 35802895c153SMichael Chan __le64 page_dir; 35812895c153SMichael Chan __le32 num_entries; 35822895c153SMichael Chan u8 page_size_pbl_level; 35832895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 35842895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 35852895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 35862895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 35872895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 35882895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 35892895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 35902895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 35912895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 35922895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 35932895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 35942895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 35952895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 35962895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 35972895c153SMichael Chan #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 35982895c153SMichael Chan u8 subtype_valid_cnt; 35992895c153SMichael Chan u8 rsvd[2]; 36002895c153SMichael Chan __le32 split_entry_0; 36012895c153SMichael Chan __le32 split_entry_1; 36022895c153SMichael Chan __le32 split_entry_2; 36032895c153SMichael Chan __le32 split_entry_3; 36042895c153SMichael Chan u8 rsvd2[7]; 36052895c153SMichael Chan u8 valid; 36062895c153SMichael Chan }; 36072895c153SMichael Chan 36082895c153SMichael Chan /* qpc_split_entries (size:128b/16B) */ 36092895c153SMichael Chan struct qpc_split_entries { 36102895c153SMichael Chan __le32 qp_num_l2_entries; 36112895c153SMichael Chan __le32 qp_num_qp1_entries; 36122895c153SMichael Chan __le32 rsvd[2]; 36132895c153SMichael Chan }; 36142895c153SMichael Chan 36152895c153SMichael Chan /* srq_split_entries (size:128b/16B) */ 36162895c153SMichael Chan struct srq_split_entries { 36172895c153SMichael Chan __le32 srq_num_l2_entries; 36182895c153SMichael Chan __le32 rsvd; 36192895c153SMichael Chan __le32 rsvd2[2]; 36202895c153SMichael Chan }; 36212895c153SMichael Chan 36222895c153SMichael Chan /* cq_split_entries (size:128b/16B) */ 36232895c153SMichael Chan struct cq_split_entries { 36242895c153SMichael Chan __le32 cq_num_l2_entries; 36252895c153SMichael Chan __le32 rsvd; 36262895c153SMichael Chan __le32 rsvd2[2]; 36272895c153SMichael Chan }; 36282895c153SMichael Chan 36292895c153SMichael Chan /* vnic_split_entries (size:128b/16B) */ 36302895c153SMichael Chan struct vnic_split_entries { 36312895c153SMichael Chan __le32 vnic_num_vnic_entries; 36322895c153SMichael Chan __le32 rsvd; 36332895c153SMichael Chan __le32 rsvd2[2]; 36342895c153SMichael Chan }; 36352895c153SMichael Chan 36362895c153SMichael Chan /* mrav_split_entries (size:128b/16B) */ 36372895c153SMichael Chan struct mrav_split_entries { 36382895c153SMichael Chan __le32 mrav_num_av_entries; 36392895c153SMichael Chan __le32 rsvd; 36402895c153SMichael Chan __le32 rsvd2[2]; 36412895c153SMichael Chan }; 36422895c153SMichael Chan 36432895c153SMichael Chan /* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 36442895c153SMichael Chan struct hwrm_func_backing_store_qcaps_v2_input { 36452895c153SMichael Chan __le16 req_type; 36462895c153SMichael Chan __le16 cmpl_ring; 36472895c153SMichael Chan __le16 seq_id; 36482895c153SMichael Chan __le16 target_id; 36492895c153SMichael Chan __le64 resp_addr; 36502895c153SMichael Chan __le16 type; 36512895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 36522895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 36532895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 36542895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 36552895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 36562895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 36572895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 36582895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 36592895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 36602895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TKC 0x13UL 36612895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RKC 0x14UL 36622895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3663ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3664ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3665ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3666ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3667ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_TKC 0x1aUL 3668ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QUIC_RKC 0x1bUL 36692895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 36702895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 36712895c153SMichael Chan u8 rsvd[6]; 36722895c153SMichael Chan }; 36732895c153SMichael Chan 36742895c153SMichael Chan /* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 36752895c153SMichael Chan struct hwrm_func_backing_store_qcaps_v2_output { 36762895c153SMichael Chan __le16 error_code; 36772895c153SMichael Chan __le16 req_type; 36782895c153SMichael Chan __le16 seq_id; 36792895c153SMichael Chan __le16 resp_len; 36802895c153SMichael Chan __le16 type; 36812895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 36822895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 36832895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 36842895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 36852895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 36862895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 36872895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 36882895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 36892895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 36902895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TKC 0x13UL 36912895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RKC 0x14UL 36922895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3693ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 3694ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 3695ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 3696ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 3697ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_TKC 0x1aUL 3698ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QUIC_RKC 0x1bUL 36992895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 37002895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 37012895c153SMichael Chan __le16 entry_size; 37022895c153SMichael Chan __le32 flags; 37032895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 37042895c153SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 3705ad04cc05SMichael Chan #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 37062895c153SMichael Chan __le32 instance_bit_map; 37072895c153SMichael Chan u8 ctx_init_value; 37082895c153SMichael Chan u8 ctx_init_offset; 37092895c153SMichael Chan u8 entry_multiple; 37102895c153SMichael Chan u8 rsvd; 37112895c153SMichael Chan __le32 max_num_entries; 37122895c153SMichael Chan __le32 min_num_entries; 37132895c153SMichael Chan __le16 next_valid_type; 37142895c153SMichael Chan u8 subtype_valid_cnt; 37152895c153SMichael Chan u8 rsvd2; 37162895c153SMichael Chan __le32 split_entry_0; 37172895c153SMichael Chan __le32 split_entry_1; 37182895c153SMichael Chan __le32 split_entry_2; 37192895c153SMichael Chan __le32 split_entry_3; 37202895c153SMichael Chan u8 rsvd3[3]; 37212895c153SMichael Chan u8 valid; 37222895c153SMichael Chan }; 37232895c153SMichael Chan 37246fc92c33SMichael Chan /* hwrm_func_drv_if_change_input (size:192b/24B) */ 37256fc92c33SMichael Chan struct hwrm_func_drv_if_change_input { 37266fc92c33SMichael Chan __le16 req_type; 37276fc92c33SMichael Chan __le16 cmpl_ring; 37286fc92c33SMichael Chan __le16 seq_id; 37296fc92c33SMichael Chan __le16 target_id; 37306fc92c33SMichael Chan __le64 resp_addr; 37316fc92c33SMichael Chan __le32 flags; 37326fc92c33SMichael Chan #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 37336fc92c33SMichael Chan __le32 unused; 37346fc92c33SMichael Chan }; 37356fc92c33SMichael Chan 37366fc92c33SMichael Chan /* hwrm_func_drv_if_change_output (size:128b/16B) */ 37376fc92c33SMichael Chan struct hwrm_func_drv_if_change_output { 37386fc92c33SMichael Chan __le16 error_code; 37396fc92c33SMichael Chan __le16 req_type; 37406fc92c33SMichael Chan __le16 seq_id; 37416fc92c33SMichael Chan __le16 resp_len; 37426fc92c33SMichael Chan __le32 flags; 37436fc92c33SMichael Chan #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 37443322479eSMichael Chan #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 37456fc92c33SMichael Chan u8 unused_0[3]; 37466fc92c33SMichael Chan u8 valid; 37476fc92c33SMichael Chan }; 37486fc92c33SMichael Chan 3749894aa69aSMichael Chan /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3750c0c050c5SMichael Chan struct hwrm_port_phy_cfg_input { 3751c0c050c5SMichael Chan __le16 req_type; 3752c0c050c5SMichael Chan __le16 cmpl_ring; 3753c0c050c5SMichael Chan __le16 seq_id; 3754c0c050c5SMichael Chan __le16 target_id; 3755c0c050c5SMichael Chan __le64 resp_addr; 3756c0c050c5SMichael Chan __le32 flags; 3757c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 375816d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3759c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3760c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 376111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 376211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 376311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 376411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3765a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3766a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3767a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3768a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3769a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3770a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 377116d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3772bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3773bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 37749d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 37759d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 37769d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 37779d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 37789d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 37799d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3780c0c050c5SMichael Chan __le32 enables; 3781c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3782c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3783c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3784c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3785c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3786c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3787c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3788c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3789c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 379011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 379111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3792bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3793bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3794c0c050c5SMichael Chan __le16 port_id; 3795c0c050c5SMichael Chan __le16 force_link_speed; 3796441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3797441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3798441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3799441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3800441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3801441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3802441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3803441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3804441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3805441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3806441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3807894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3808c0c050c5SMichael Chan u8 auto_mode; 3809441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3810441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3811441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3812441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3813441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3814894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3815c0c050c5SMichael Chan u8 auto_duplex; 3816441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3817441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3818441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3819894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3820c0c050c5SMichael Chan u8 auto_pause; 3821c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3822c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 382311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3824c0c050c5SMichael Chan u8 unused_0; 3825c0c050c5SMichael Chan __le16 auto_link_speed; 3826441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3827441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3828441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3829441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3830441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3831441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3832441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3833441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3834441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3835441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3836441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3837894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3838c0c050c5SMichael Chan __le16 auto_link_speed_mask; 3839c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3840c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3841c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3842c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3843c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3844c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3845c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3846c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3847c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3848c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3849c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 385011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 385111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 385211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3853c0c050c5SMichael Chan u8 wirespeed; 3854441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3855441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3856894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3857c0c050c5SMichael Chan u8 lpbk; 3858441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3859441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3860441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 38616fc92c33SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 38626fc92c33SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3863c0c050c5SMichael Chan u8 force_pause; 3864c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3865c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3866c0c050c5SMichael Chan u8 unused_1; 3867c0c050c5SMichael Chan __le32 preemphasis; 386811f15ed3SMichael Chan __le16 eee_link_speed_mask; 386911f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 387011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 387111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 387211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 387311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 387411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 387511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3876bfc6e5fbSMichael Chan __le16 force_pam4_link_speed; 3877bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3878bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3879bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3880bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 388111f15ed3SMichael Chan __le32 tx_lpi_timer; 388211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 388311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3884bfc6e5fbSMichael Chan __le16 auto_link_pam4_speed_mask; 3885bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3886bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3887bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3888bfc6e5fbSMichael Chan u8 unused_2[2]; 3889c0c050c5SMichael Chan }; 3890c0c050c5SMichael Chan 3891894aa69aSMichael Chan /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3892c0c050c5SMichael Chan struct hwrm_port_phy_cfg_output { 3893c0c050c5SMichael Chan __le16 error_code; 3894c0c050c5SMichael Chan __le16 req_type; 3895c0c050c5SMichael Chan __le16 seq_id; 3896c0c050c5SMichael Chan __le16 resp_len; 3897894aa69aSMichael Chan u8 unused_0[7]; 3898c0c050c5SMichael Chan u8 valid; 3899c0c050c5SMichael Chan }; 3900c0c050c5SMichael Chan 3901d4f52de0SMichael Chan /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3902d4f52de0SMichael Chan struct hwrm_port_phy_cfg_cmd_err { 3903d4f52de0SMichael Chan u8 code; 3904d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3905d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3906d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3907d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3908d4f52de0SMichael Chan u8 unused_0[7]; 3909d4f52de0SMichael Chan }; 3910d4f52de0SMichael Chan 3911894aa69aSMichael Chan /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3912c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_input { 3913c0c050c5SMichael Chan __le16 req_type; 3914c0c050c5SMichael Chan __le16 cmpl_ring; 3915c0c050c5SMichael Chan __le16 seq_id; 3916c0c050c5SMichael Chan __le16 target_id; 3917c0c050c5SMichael Chan __le64 resp_addr; 3918c0c050c5SMichael Chan __le16 port_id; 3919894aa69aSMichael Chan u8 unused_0[6]; 3920c0c050c5SMichael Chan }; 3921c0c050c5SMichael Chan 392284a911dbSMichael Chan /* hwrm_port_phy_qcfg_output (size:832b/104B) */ 3923c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_output { 3924c0c050c5SMichael Chan __le16 error_code; 3925c0c050c5SMichael Chan __le16 req_type; 3926c0c050c5SMichael Chan __le16 seq_id; 3927c0c050c5SMichael Chan __le16 resp_len; 3928c0c050c5SMichael Chan u8 link; 3929441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3930441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3931441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3932894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 39339d6b648cSMichael Chan u8 active_fec_signal_mode; 39349d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 39359d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 39369d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 39379d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 39389d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 39399d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 39409d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 39419d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 39429d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 39439d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 39449d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 39459d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 39469d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 39479d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 39489d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3949c0c050c5SMichael Chan __le16 link_speed; 3950441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3951441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3952441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3953441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3954441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3955441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3956441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3957441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3958441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3959441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 396031d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3961441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3962894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3963acb20054SMichael Chan u8 duplex_cfg; 3964acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3965acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3966894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3967c0c050c5SMichael Chan u8 pause; 3968c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3969c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3970c0c050c5SMichael Chan __le16 support_speeds; 3971c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3972c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3973c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3974c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3975c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3976c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3977c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3978c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3979c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3980c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3981c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 398211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 398311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 398411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3985c0c050c5SMichael Chan __le16 force_link_speed; 3986441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3987441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3988441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3989441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3990441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3991441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3992441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3993441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3994441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3995441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3996441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3997894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3998c0c050c5SMichael Chan u8 auto_mode; 3999441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4000441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4001441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4002441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4003441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4004894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4005c0c050c5SMichael Chan u8 auto_pause; 4006c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4007c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 400811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4009c0c050c5SMichael Chan __le16 auto_link_speed; 4010441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4011441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4012441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4013441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4014441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4015441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4016441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4017441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4018441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4019441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4020441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4021894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4022c0c050c5SMichael Chan __le16 auto_link_speed_mask; 4023c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4024c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4025c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4026c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4027c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4028c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4029c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4030c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4031c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4032c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4033c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 403411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 403511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 403611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4037c0c050c5SMichael Chan u8 wirespeed; 4038441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4039441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4040894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4041c0c050c5SMichael Chan u8 lpbk; 4042441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4043441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4044441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 40456fc92c33SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 40466fc92c33SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4047c0c050c5SMichael Chan u8 force_pause; 4048c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4049c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 405011f15ed3SMichael Chan u8 module_status; 4051441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4052441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4053441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4054441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4055441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 405641136ab3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4057441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4058894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4059c0c050c5SMichael Chan __le32 preemphasis; 4060c0c050c5SMichael Chan u8 phy_maj; 4061c0c050c5SMichael Chan u8 phy_min; 4062c0c050c5SMichael Chan u8 phy_bld; 4063c0c050c5SMichael Chan u8 phy_type; 4064441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4065441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4066441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4067441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4068441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4069441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4070441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4071441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4072441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4073441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4074441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4075bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4076bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4077bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4078bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4079bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4080bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4081bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4082bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4083bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4084bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4085bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4086bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4087bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4088bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4089acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4090acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4091acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 409231d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 409331d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 409431d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 409531d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 409621e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 409721e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 409821e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 409921e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 410021e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 410121e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 410221e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 410321e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 410421e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 4105c0c050c5SMichael Chan u8 media_type; 4106441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4107441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4108441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4109441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4110894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 411111f15ed3SMichael Chan u8 xcvr_pkg_type; 4112441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4113441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4114894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 411511f15ed3SMichael Chan u8 eee_config_phy_addr; 4116c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4117c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4118894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4119894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 412011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 412111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 412211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 412311f15ed3SMichael Chan u8 parallel_detect; 412411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4125c0c050c5SMichael Chan __le16 link_partner_adv_speeds; 4126c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4127c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4128c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4129c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4130c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4131c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4132c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4133c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4134c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4135c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4136c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 413711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 413811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 413911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4140c0c050c5SMichael Chan u8 link_partner_adv_auto_mode; 4141441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4142441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4143441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4144441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4145441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4146894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4147c0c050c5SMichael Chan u8 link_partner_adv_pause; 4148c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4149c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 415011f15ed3SMichael Chan __le16 adv_eee_link_speed_mask; 415111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 415211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 415311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 415411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 415511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 415611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 415711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 415811f15ed3SMichael Chan __le16 link_partner_adv_eee_link_speed_mask; 415911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 416011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 416111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 416211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 416311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 416411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 416511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 416611f15ed3SMichael Chan __le32 xcvr_identifier_type_tx_lpi_timer; 416711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 416811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 416911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 417011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 417111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 417211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 417311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 417411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 417511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4176894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 4177a58a3e68SMichael Chan __le16 fec_cfg; 4178a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4179a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4180a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4181a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4182a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4183a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4184a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4185bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4186bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 41879d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 41889d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 41899d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 41909d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 41919d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 41929d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4193acb20054SMichael Chan u8 duplex_state; 4194acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4195acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4196894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4197894aa69aSMichael Chan u8 option_flags; 4198894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 419916db6323SMichael Chan #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 420011f15ed3SMichael Chan char phy_vendor_name[16]; 420111f15ed3SMichael Chan char phy_vendor_partnumber[16]; 4202bfc6e5fbSMichael Chan __le16 support_pam4_speeds; 4203bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4204bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4205bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4206bfc6e5fbSMichael Chan __le16 force_pam4_link_speed; 4207bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4208bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4209bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4210bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4211bfc6e5fbSMichael Chan __le16 auto_pam4_link_speed_mask; 4212bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4213bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4214bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 42159d6b648cSMichael Chan u8 link_partner_pam4_adv_speeds; 4216bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4217bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4218bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 421984a911dbSMichael Chan u8 link_down_reason; 422084a911dbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 422184a911dbSMichael Chan u8 unused_0[7]; 4222c0c050c5SMichael Chan u8 valid; 4223c0c050c5SMichael Chan }; 4224c0c050c5SMichael Chan 42252895c153SMichael Chan /* hwrm_port_mac_cfg_input (size:448b/56B) */ 4226c0c050c5SMichael Chan struct hwrm_port_mac_cfg_input { 4227c0c050c5SMichael Chan __le16 req_type; 4228c0c050c5SMichael Chan __le16 cmpl_ring; 4229c0c050c5SMichael Chan __le16 seq_id; 4230c0c050c5SMichael Chan __le16 target_id; 4231c0c050c5SMichael Chan __le64 resp_addr; 4232c0c050c5SMichael Chan __le32 flags; 4233c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4234441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4235c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4236c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 423711f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 423811f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 423911f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 424011f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4241a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4242a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4243441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4244441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4245441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 42464a50ddc2SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4247ad04cc05SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4248ad04cc05SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4249c0c050c5SMichael Chan __le32 enables; 4250c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4251c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4252441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4253c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4254c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 425511f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 425611f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4257441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 42584a50ddc2SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 425978eeadb8SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4260c0c050c5SMichael Chan __le16 port_id; 4261c0c050c5SMichael Chan u8 ipg; 4262c0c050c5SMichael Chan u8 lpbk; 4263441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4264441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4265441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4266894aa69aSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4267441cabbbSMichael Chan u8 vlan_pri2cos_map_pri; 4268441cabbbSMichael Chan u8 reserved1; 4269c0c050c5SMichael Chan u8 tunnel_pri2cos_map_pri; 4270c0c050c5SMichael Chan u8 dscp2pri_map_pri; 427111f15ed3SMichael Chan __le16 rx_ts_capture_ptp_msg_type; 427211f15ed3SMichael Chan __le16 tx_ts_capture_ptp_msg_type; 4273441cabbbSMichael Chan u8 cos_field_cfg; 4274441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4275441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4276441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4277441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4278441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4279441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4280441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4281441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4282441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4283441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4284441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4285441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4286441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4287441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4288441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4289441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4290441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4291441cabbbSMichael Chan u8 unused_0[3]; 429278eeadb8SMichael Chan __le32 ptp_freq_adj_ppb; 42932895c153SMichael Chan u8 unused_1[4]; 42942895c153SMichael Chan __le64 ptp_adj_phase; 4295c0c050c5SMichael Chan }; 4296c0c050c5SMichael Chan 4297894aa69aSMichael Chan /* hwrm_port_mac_cfg_output (size:128b/16B) */ 4298c0c050c5SMichael Chan struct hwrm_port_mac_cfg_output { 4299c0c050c5SMichael Chan __le16 error_code; 4300c0c050c5SMichael Chan __le16 req_type; 4301c0c050c5SMichael Chan __le16 seq_id; 4302c0c050c5SMichael Chan __le16 resp_len; 4303c0c050c5SMichael Chan __le16 mru; 4304c0c050c5SMichael Chan __le16 mtu; 4305c0c050c5SMichael Chan u8 ipg; 4306c0c050c5SMichael Chan u8 lpbk; 4307441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4308441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4309441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4310894aa69aSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4311c0c050c5SMichael Chan u8 unused_0; 4312c0c050c5SMichael Chan u8 valid; 4313c0c050c5SMichael Chan }; 4314c0c050c5SMichael Chan 4315894aa69aSMichael Chan /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4316acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_input { 4317acb20054SMichael Chan __le16 req_type; 4318acb20054SMichael Chan __le16 cmpl_ring; 4319acb20054SMichael Chan __le16 seq_id; 4320acb20054SMichael Chan __le16 target_id; 4321acb20054SMichael Chan __le64 resp_addr; 4322acb20054SMichael Chan __le16 port_id; 4323894aa69aSMichael Chan u8 unused_0[6]; 4324acb20054SMichael Chan }; 4325acb20054SMichael Chan 432678eeadb8SMichael Chan /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4327acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_output { 4328acb20054SMichael Chan __le16 error_code; 4329acb20054SMichael Chan __le16 req_type; 4330acb20054SMichael Chan __le16 seq_id; 4331acb20054SMichael Chan __le16 resp_len; 4332acb20054SMichael Chan u8 flags; 4333acb20054SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 43344a50ddc2SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 433541136ab3SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 433678eeadb8SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 43372895c153SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 4338894aa69aSMichael Chan u8 unused_0[3]; 4339acb20054SMichael Chan __le32 rx_ts_reg_off_lower; 4340acb20054SMichael Chan __le32 rx_ts_reg_off_upper; 4341acb20054SMichael Chan __le32 rx_ts_reg_off_seq_id; 4342acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_0; 4343acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_1; 4344acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_2; 4345acb20054SMichael Chan __le32 rx_ts_reg_off_domain_id; 4346acb20054SMichael Chan __le32 rx_ts_reg_off_fifo; 4347acb20054SMichael Chan __le32 rx_ts_reg_off_fifo_adv; 4348acb20054SMichael Chan __le32 rx_ts_reg_off_granularity; 4349acb20054SMichael Chan __le32 tx_ts_reg_off_lower; 4350acb20054SMichael Chan __le32 tx_ts_reg_off_upper; 4351acb20054SMichael Chan __le32 tx_ts_reg_off_seq_id; 4352acb20054SMichael Chan __le32 tx_ts_reg_off_fifo; 4353acb20054SMichael Chan __le32 tx_ts_reg_off_granularity; 435478eeadb8SMichael Chan __le32 ts_ref_clock_reg_lower; 435578eeadb8SMichael Chan __le32 ts_ref_clock_reg_upper; 4356894aa69aSMichael Chan u8 unused_1[7]; 4357acb20054SMichael Chan u8 valid; 4358acb20054SMichael Chan }; 4359acb20054SMichael Chan 43606fc92c33SMichael Chan /* tx_port_stats (size:3264b/408B) */ 43616fc92c33SMichael Chan struct tx_port_stats { 43626fc92c33SMichael Chan __le64 tx_64b_frames; 43636fc92c33SMichael Chan __le64 tx_65b_127b_frames; 43646fc92c33SMichael Chan __le64 tx_128b_255b_frames; 43656fc92c33SMichael Chan __le64 tx_256b_511b_frames; 43666fc92c33SMichael Chan __le64 tx_512b_1023b_frames; 43676fc92c33SMichael Chan __le64 tx_1024b_1518b_frames; 43686fc92c33SMichael Chan __le64 tx_good_vlan_frames; 43696fc92c33SMichael Chan __le64 tx_1519b_2047b_frames; 43706fc92c33SMichael Chan __le64 tx_2048b_4095b_frames; 43716fc92c33SMichael Chan __le64 tx_4096b_9216b_frames; 43726fc92c33SMichael Chan __le64 tx_9217b_16383b_frames; 43736fc92c33SMichael Chan __le64 tx_good_frames; 43746fc92c33SMichael Chan __le64 tx_total_frames; 43756fc92c33SMichael Chan __le64 tx_ucast_frames; 43766fc92c33SMichael Chan __le64 tx_mcast_frames; 43776fc92c33SMichael Chan __le64 tx_bcast_frames; 43786fc92c33SMichael Chan __le64 tx_pause_frames; 43796fc92c33SMichael Chan __le64 tx_pfc_frames; 43806fc92c33SMichael Chan __le64 tx_jabber_frames; 43816fc92c33SMichael Chan __le64 tx_fcs_err_frames; 43826fc92c33SMichael Chan __le64 tx_control_frames; 43836fc92c33SMichael Chan __le64 tx_oversz_frames; 43846fc92c33SMichael Chan __le64 tx_single_dfrl_frames; 43856fc92c33SMichael Chan __le64 tx_multi_dfrl_frames; 43866fc92c33SMichael Chan __le64 tx_single_coll_frames; 43876fc92c33SMichael Chan __le64 tx_multi_coll_frames; 43886fc92c33SMichael Chan __le64 tx_late_coll_frames; 43896fc92c33SMichael Chan __le64 tx_excessive_coll_frames; 43906fc92c33SMichael Chan __le64 tx_frag_frames; 43916fc92c33SMichael Chan __le64 tx_err; 43926fc92c33SMichael Chan __le64 tx_tagged_frames; 43936fc92c33SMichael Chan __le64 tx_dbl_tagged_frames; 43946fc92c33SMichael Chan __le64 tx_runt_frames; 43956fc92c33SMichael Chan __le64 tx_fifo_underruns; 43966fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri0; 43976fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri1; 43986fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri2; 43996fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri3; 44006fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri4; 44016fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri5; 44026fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri6; 44036fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri7; 44046fc92c33SMichael Chan __le64 tx_eee_lpi_events; 44056fc92c33SMichael Chan __le64 tx_eee_lpi_duration; 44066fc92c33SMichael Chan __le64 tx_llfc_logical_msgs; 44076fc92c33SMichael Chan __le64 tx_hcfc_msgs; 44086fc92c33SMichael Chan __le64 tx_total_collisions; 44096fc92c33SMichael Chan __le64 tx_bytes; 44106fc92c33SMichael Chan __le64 tx_xthol_frames; 44116fc92c33SMichael Chan __le64 tx_stat_discard; 44126fc92c33SMichael Chan __le64 tx_stat_error; 44136fc92c33SMichael Chan }; 44146fc92c33SMichael Chan 44156fc92c33SMichael Chan /* rx_port_stats (size:4224b/528B) */ 44166fc92c33SMichael Chan struct rx_port_stats { 44176fc92c33SMichael Chan __le64 rx_64b_frames; 44186fc92c33SMichael Chan __le64 rx_65b_127b_frames; 44196fc92c33SMichael Chan __le64 rx_128b_255b_frames; 44206fc92c33SMichael Chan __le64 rx_256b_511b_frames; 44216fc92c33SMichael Chan __le64 rx_512b_1023b_frames; 44226fc92c33SMichael Chan __le64 rx_1024b_1518b_frames; 44236fc92c33SMichael Chan __le64 rx_good_vlan_frames; 44246fc92c33SMichael Chan __le64 rx_1519b_2047b_frames; 44256fc92c33SMichael Chan __le64 rx_2048b_4095b_frames; 44266fc92c33SMichael Chan __le64 rx_4096b_9216b_frames; 44276fc92c33SMichael Chan __le64 rx_9217b_16383b_frames; 44286fc92c33SMichael Chan __le64 rx_total_frames; 44296fc92c33SMichael Chan __le64 rx_ucast_frames; 44306fc92c33SMichael Chan __le64 rx_mcast_frames; 44316fc92c33SMichael Chan __le64 rx_bcast_frames; 44326fc92c33SMichael Chan __le64 rx_fcs_err_frames; 44336fc92c33SMichael Chan __le64 rx_ctrl_frames; 44346fc92c33SMichael Chan __le64 rx_pause_frames; 44356fc92c33SMichael Chan __le64 rx_pfc_frames; 44366fc92c33SMichael Chan __le64 rx_unsupported_opcode_frames; 44376fc92c33SMichael Chan __le64 rx_unsupported_da_pausepfc_frames; 44386fc92c33SMichael Chan __le64 rx_wrong_sa_frames; 44396fc92c33SMichael Chan __le64 rx_align_err_frames; 44406fc92c33SMichael Chan __le64 rx_oor_len_frames; 44416fc92c33SMichael Chan __le64 rx_code_err_frames; 44426fc92c33SMichael Chan __le64 rx_false_carrier_frames; 44436fc92c33SMichael Chan __le64 rx_ovrsz_frames; 44446fc92c33SMichael Chan __le64 rx_jbr_frames; 44456fc92c33SMichael Chan __le64 rx_mtu_err_frames; 44466fc92c33SMichael Chan __le64 rx_match_crc_frames; 44476fc92c33SMichael Chan __le64 rx_promiscuous_frames; 44486fc92c33SMichael Chan __le64 rx_tagged_frames; 44496fc92c33SMichael Chan __le64 rx_double_tagged_frames; 44506fc92c33SMichael Chan __le64 rx_trunc_frames; 44516fc92c33SMichael Chan __le64 rx_good_frames; 44526fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri0; 44536fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri1; 44546fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri2; 44556fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri3; 44566fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri4; 44576fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri5; 44586fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri6; 44596fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri7; 44606fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri0; 44616fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri1; 44626fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri2; 44636fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri3; 44646fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri4; 44656fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri5; 44666fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri6; 44676fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri7; 44686fc92c33SMichael Chan __le64 rx_sch_crc_err_frames; 44696fc92c33SMichael Chan __le64 rx_undrsz_frames; 44706fc92c33SMichael Chan __le64 rx_frag_frames; 44716fc92c33SMichael Chan __le64 rx_eee_lpi_events; 44726fc92c33SMichael Chan __le64 rx_eee_lpi_duration; 44736fc92c33SMichael Chan __le64 rx_llfc_physical_msgs; 44746fc92c33SMichael Chan __le64 rx_llfc_logical_msgs; 44756fc92c33SMichael Chan __le64 rx_llfc_msgs_with_crc_err; 44766fc92c33SMichael Chan __le64 rx_hcfc_msgs; 44776fc92c33SMichael Chan __le64 rx_hcfc_msgs_with_crc_err; 44786fc92c33SMichael Chan __le64 rx_bytes; 44796fc92c33SMichael Chan __le64 rx_runt_bytes; 44806fc92c33SMichael Chan __le64 rx_runt_frames; 44816fc92c33SMichael Chan __le64 rx_stat_discard; 44826fc92c33SMichael Chan __le64 rx_stat_err; 44836fc92c33SMichael Chan }; 44846fc92c33SMichael Chan 4485894aa69aSMichael Chan /* hwrm_port_qstats_input (size:320b/40B) */ 4486c0c050c5SMichael Chan struct hwrm_port_qstats_input { 4487c0c050c5SMichael Chan __le16 req_type; 4488c0c050c5SMichael Chan __le16 cmpl_ring; 4489c0c050c5SMichael Chan __le16 seq_id; 4490c0c050c5SMichael Chan __le16 target_id; 4491c0c050c5SMichael Chan __le64 resp_addr; 4492c0c050c5SMichael Chan __le16 port_id; 4493460c2577SMichael Chan u8 flags; 4494460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4495460c2577SMichael Chan u8 unused_0[5]; 4496c0c050c5SMichael Chan __le64 tx_stat_host_addr; 4497c0c050c5SMichael Chan __le64 rx_stat_host_addr; 4498c0c050c5SMichael Chan }; 4499c0c050c5SMichael Chan 4500894aa69aSMichael Chan /* hwrm_port_qstats_output (size:128b/16B) */ 4501c0c050c5SMichael Chan struct hwrm_port_qstats_output { 4502c0c050c5SMichael Chan __le16 error_code; 4503c0c050c5SMichael Chan __le16 req_type; 4504c0c050c5SMichael Chan __le16 seq_id; 4505c0c050c5SMichael Chan __le16 resp_len; 4506c193554eSMichael Chan __le16 tx_stat_size; 4507c193554eSMichael Chan __le16 rx_stat_size; 4508894aa69aSMichael Chan u8 unused_0[3]; 4509c0c050c5SMichael Chan u8 valid; 4510c0c050c5SMichael Chan }; 4511c0c050c5SMichael Chan 45126fc92c33SMichael Chan /* tx_port_stats_ext (size:2048b/256B) */ 45136fc92c33SMichael Chan struct tx_port_stats_ext { 45146fc92c33SMichael Chan __le64 tx_bytes_cos0; 45156fc92c33SMichael Chan __le64 tx_bytes_cos1; 45166fc92c33SMichael Chan __le64 tx_bytes_cos2; 45176fc92c33SMichael Chan __le64 tx_bytes_cos3; 45186fc92c33SMichael Chan __le64 tx_bytes_cos4; 45196fc92c33SMichael Chan __le64 tx_bytes_cos5; 45206fc92c33SMichael Chan __le64 tx_bytes_cos6; 45216fc92c33SMichael Chan __le64 tx_bytes_cos7; 45226fc92c33SMichael Chan __le64 tx_packets_cos0; 45236fc92c33SMichael Chan __le64 tx_packets_cos1; 45246fc92c33SMichael Chan __le64 tx_packets_cos2; 45256fc92c33SMichael Chan __le64 tx_packets_cos3; 45266fc92c33SMichael Chan __le64 tx_packets_cos4; 45276fc92c33SMichael Chan __le64 tx_packets_cos5; 45286fc92c33SMichael Chan __le64 tx_packets_cos6; 45296fc92c33SMichael Chan __le64 tx_packets_cos7; 45306fc92c33SMichael Chan __le64 pfc_pri0_tx_duration_us; 45316fc92c33SMichael Chan __le64 pfc_pri0_tx_transitions; 45326fc92c33SMichael Chan __le64 pfc_pri1_tx_duration_us; 45336fc92c33SMichael Chan __le64 pfc_pri1_tx_transitions; 45346fc92c33SMichael Chan __le64 pfc_pri2_tx_duration_us; 45356fc92c33SMichael Chan __le64 pfc_pri2_tx_transitions; 45366fc92c33SMichael Chan __le64 pfc_pri3_tx_duration_us; 45376fc92c33SMichael Chan __le64 pfc_pri3_tx_transitions; 45386fc92c33SMichael Chan __le64 pfc_pri4_tx_duration_us; 45396fc92c33SMichael Chan __le64 pfc_pri4_tx_transitions; 45406fc92c33SMichael Chan __le64 pfc_pri5_tx_duration_us; 45416fc92c33SMichael Chan __le64 pfc_pri5_tx_transitions; 45426fc92c33SMichael Chan __le64 pfc_pri6_tx_duration_us; 45436fc92c33SMichael Chan __le64 pfc_pri6_tx_transitions; 45446fc92c33SMichael Chan __le64 pfc_pri7_tx_duration_us; 45456fc92c33SMichael Chan __le64 pfc_pri7_tx_transitions; 45466fc92c33SMichael Chan }; 45476fc92c33SMichael Chan 454821e70778SMichael Chan /* rx_port_stats_ext (size:3776b/472B) */ 45496fc92c33SMichael Chan struct rx_port_stats_ext { 45506fc92c33SMichael Chan __le64 link_down_events; 45516fc92c33SMichael Chan __le64 continuous_pause_events; 45526fc92c33SMichael Chan __le64 resume_pause_events; 45536fc92c33SMichael Chan __le64 continuous_roce_pause_events; 45546fc92c33SMichael Chan __le64 resume_roce_pause_events; 45556fc92c33SMichael Chan __le64 rx_bytes_cos0; 45566fc92c33SMichael Chan __le64 rx_bytes_cos1; 45576fc92c33SMichael Chan __le64 rx_bytes_cos2; 45586fc92c33SMichael Chan __le64 rx_bytes_cos3; 45596fc92c33SMichael Chan __le64 rx_bytes_cos4; 45606fc92c33SMichael Chan __le64 rx_bytes_cos5; 45616fc92c33SMichael Chan __le64 rx_bytes_cos6; 45626fc92c33SMichael Chan __le64 rx_bytes_cos7; 45636fc92c33SMichael Chan __le64 rx_packets_cos0; 45646fc92c33SMichael Chan __le64 rx_packets_cos1; 45656fc92c33SMichael Chan __le64 rx_packets_cos2; 45666fc92c33SMichael Chan __le64 rx_packets_cos3; 45676fc92c33SMichael Chan __le64 rx_packets_cos4; 45686fc92c33SMichael Chan __le64 rx_packets_cos5; 45696fc92c33SMichael Chan __le64 rx_packets_cos6; 45706fc92c33SMichael Chan __le64 rx_packets_cos7; 45716fc92c33SMichael Chan __le64 pfc_pri0_rx_duration_us; 45726fc92c33SMichael Chan __le64 pfc_pri0_rx_transitions; 45736fc92c33SMichael Chan __le64 pfc_pri1_rx_duration_us; 45746fc92c33SMichael Chan __le64 pfc_pri1_rx_transitions; 45756fc92c33SMichael Chan __le64 pfc_pri2_rx_duration_us; 45766fc92c33SMichael Chan __le64 pfc_pri2_rx_transitions; 45776fc92c33SMichael Chan __le64 pfc_pri3_rx_duration_us; 45786fc92c33SMichael Chan __le64 pfc_pri3_rx_transitions; 45796fc92c33SMichael Chan __le64 pfc_pri4_rx_duration_us; 45806fc92c33SMichael Chan __le64 pfc_pri4_rx_transitions; 45816fc92c33SMichael Chan __le64 pfc_pri5_rx_duration_us; 45826fc92c33SMichael Chan __le64 pfc_pri5_rx_transitions; 45836fc92c33SMichael Chan __le64 pfc_pri6_rx_duration_us; 45846fc92c33SMichael Chan __le64 pfc_pri6_rx_transitions; 45856fc92c33SMichael Chan __le64 pfc_pri7_rx_duration_us; 45866fc92c33SMichael Chan __le64 pfc_pri7_rx_transitions; 45874a50ddc2SMichael Chan __le64 rx_bits; 45884a50ddc2SMichael Chan __le64 rx_buffer_passed_threshold; 45894a50ddc2SMichael Chan __le64 rx_pcs_symbol_err; 45904a50ddc2SMichael Chan __le64 rx_corrected_bits; 45912792b5b9SMichael Chan __le64 rx_discard_bytes_cos0; 45922792b5b9SMichael Chan __le64 rx_discard_bytes_cos1; 45932792b5b9SMichael Chan __le64 rx_discard_bytes_cos2; 45942792b5b9SMichael Chan __le64 rx_discard_bytes_cos3; 45952792b5b9SMichael Chan __le64 rx_discard_bytes_cos4; 45962792b5b9SMichael Chan __le64 rx_discard_bytes_cos5; 45972792b5b9SMichael Chan __le64 rx_discard_bytes_cos6; 45982792b5b9SMichael Chan __le64 rx_discard_bytes_cos7; 45992792b5b9SMichael Chan __le64 rx_discard_packets_cos0; 46002792b5b9SMichael Chan __le64 rx_discard_packets_cos1; 46012792b5b9SMichael Chan __le64 rx_discard_packets_cos2; 46022792b5b9SMichael Chan __le64 rx_discard_packets_cos3; 46032792b5b9SMichael Chan __le64 rx_discard_packets_cos4; 46042792b5b9SMichael Chan __le64 rx_discard_packets_cos5; 46052792b5b9SMichael Chan __le64 rx_discard_packets_cos6; 46062792b5b9SMichael Chan __le64 rx_discard_packets_cos7; 460721e70778SMichael Chan __le64 rx_fec_corrected_blocks; 460821e70778SMichael Chan __le64 rx_fec_uncorrectable_blocks; 46096fc92c33SMichael Chan }; 46106fc92c33SMichael Chan 4611d4f52de0SMichael Chan /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4612d4f52de0SMichael Chan struct hwrm_port_qstats_ext_input { 4613d4f52de0SMichael Chan __le16 req_type; 4614d4f52de0SMichael Chan __le16 cmpl_ring; 4615d4f52de0SMichael Chan __le16 seq_id; 4616d4f52de0SMichael Chan __le16 target_id; 4617d4f52de0SMichael Chan __le64 resp_addr; 4618d4f52de0SMichael Chan __le16 port_id; 4619d4f52de0SMichael Chan __le16 tx_stat_size; 4620d4f52de0SMichael Chan __le16 rx_stat_size; 4621460c2577SMichael Chan u8 flags; 4622460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4623460c2577SMichael Chan u8 unused_0; 4624d4f52de0SMichael Chan __le64 tx_stat_host_addr; 4625d4f52de0SMichael Chan __le64 rx_stat_host_addr; 4626d4f52de0SMichael Chan }; 4627d4f52de0SMichael Chan 4628d4f52de0SMichael Chan /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4629d4f52de0SMichael Chan struct hwrm_port_qstats_ext_output { 4630d4f52de0SMichael Chan __le16 error_code; 4631d4f52de0SMichael Chan __le16 req_type; 4632d4f52de0SMichael Chan __le16 seq_id; 4633d4f52de0SMichael Chan __le16 resp_len; 4634d4f52de0SMichael Chan __le16 tx_stat_size; 4635d4f52de0SMichael Chan __le16 rx_stat_size; 46366fc92c33SMichael Chan __le16 total_active_cos_queues; 463731d357c0SMichael Chan u8 flags; 463831d357c0SMichael Chan #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4639d4f52de0SMichael Chan u8 valid; 4640d4f52de0SMichael Chan }; 4641d4f52de0SMichael Chan 4642894aa69aSMichael Chan /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4643c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_input { 4644c0c050c5SMichael Chan __le16 req_type; 4645c0c050c5SMichael Chan __le16 cmpl_ring; 4646c0c050c5SMichael Chan __le16 seq_id; 4647c0c050c5SMichael Chan __le16 target_id; 4648c0c050c5SMichael Chan __le64 resp_addr; 4649c0c050c5SMichael Chan }; 4650c0c050c5SMichael Chan 4651894aa69aSMichael Chan /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4652c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_output { 4653c0c050c5SMichael Chan __le16 error_code; 4654c0c050c5SMichael Chan __le16 req_type; 4655c0c050c5SMichael Chan __le16 seq_id; 4656c0c050c5SMichael Chan __le16 resp_len; 4657c0c050c5SMichael Chan __le64 lpbk_ucast_frames; 4658c0c050c5SMichael Chan __le64 lpbk_mcast_frames; 4659c0c050c5SMichael Chan __le64 lpbk_bcast_frames; 4660c0c050c5SMichael Chan __le64 lpbk_ucast_bytes; 4661c0c050c5SMichael Chan __le64 lpbk_mcast_bytes; 4662c0c050c5SMichael Chan __le64 lpbk_bcast_bytes; 4663c193554eSMichael Chan __le64 tx_stat_discard; 4664c193554eSMichael Chan __le64 tx_stat_error; 4665c193554eSMichael Chan __le64 rx_stat_discard; 4666c193554eSMichael Chan __le64 rx_stat_error; 4667894aa69aSMichael Chan u8 unused_0[7]; 4668c0c050c5SMichael Chan u8 valid; 4669c0c050c5SMichael Chan }; 4670c0c050c5SMichael Chan 46719d6b648cSMichael Chan /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 46729d6b648cSMichael Chan struct hwrm_port_ecn_qstats_input { 46739d6b648cSMichael Chan __le16 req_type; 46749d6b648cSMichael Chan __le16 cmpl_ring; 46759d6b648cSMichael Chan __le16 seq_id; 46769d6b648cSMichael Chan __le16 target_id; 46779d6b648cSMichael Chan __le64 resp_addr; 46789d6b648cSMichael Chan __le16 port_id; 46799d6b648cSMichael Chan __le16 ecn_stat_buf_size; 46809d6b648cSMichael Chan u8 flags; 46819d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 46829d6b648cSMichael Chan u8 unused_0[3]; 46839d6b648cSMichael Chan __le64 ecn_stat_host_addr; 46849d6b648cSMichael Chan }; 46859d6b648cSMichael Chan 46869d6b648cSMichael Chan /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 46879d6b648cSMichael Chan struct hwrm_port_ecn_qstats_output { 46889d6b648cSMichael Chan __le16 error_code; 46899d6b648cSMichael Chan __le16 req_type; 46909d6b648cSMichael Chan __le16 seq_id; 46919d6b648cSMichael Chan __le16 resp_len; 46929d6b648cSMichael Chan __le16 ecn_stat_buf_size; 46939d6b648cSMichael Chan u8 mark_en; 46949d6b648cSMichael Chan u8 unused_0[4]; 46959d6b648cSMichael Chan u8 valid; 46969d6b648cSMichael Chan }; 46979d6b648cSMichael Chan 46989d6b648cSMichael Chan /* port_stats_ecn (size:512b/64B) */ 46999d6b648cSMichael Chan struct port_stats_ecn { 47009d6b648cSMichael Chan __le64 mark_cnt_cos0; 47019d6b648cSMichael Chan __le64 mark_cnt_cos1; 47029d6b648cSMichael Chan __le64 mark_cnt_cos2; 47039d6b648cSMichael Chan __le64 mark_cnt_cos3; 47049d6b648cSMichael Chan __le64 mark_cnt_cos4; 47059d6b648cSMichael Chan __le64 mark_cnt_cos5; 47069d6b648cSMichael Chan __le64 mark_cnt_cos6; 47079d6b648cSMichael Chan __le64 mark_cnt_cos7; 47089d6b648cSMichael Chan }; 47099d6b648cSMichael Chan 4710894aa69aSMichael Chan /* hwrm_port_clr_stats_input (size:192b/24B) */ 4711c0c050c5SMichael Chan struct hwrm_port_clr_stats_input { 4712c0c050c5SMichael Chan __le16 req_type; 4713c0c050c5SMichael Chan __le16 cmpl_ring; 4714c0c050c5SMichael Chan __le16 seq_id; 4715c0c050c5SMichael Chan __le16 target_id; 4716c0c050c5SMichael Chan __le64 resp_addr; 4717c0c050c5SMichael Chan __le16 port_id; 471831d357c0SMichael Chan u8 flags; 471931d357c0SMichael Chan #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 472031d357c0SMichael Chan u8 unused_0[5]; 4721c0c050c5SMichael Chan }; 4722c0c050c5SMichael Chan 4723894aa69aSMichael Chan /* hwrm_port_clr_stats_output (size:128b/16B) */ 4724c0c050c5SMichael Chan struct hwrm_port_clr_stats_output { 4725c0c050c5SMichael Chan __le16 error_code; 4726c0c050c5SMichael Chan __le16 req_type; 4727c0c050c5SMichael Chan __le16 seq_id; 4728c0c050c5SMichael Chan __le16 resp_len; 4729894aa69aSMichael Chan u8 unused_0[7]; 4730c0c050c5SMichael Chan u8 valid; 4731c0c050c5SMichael Chan }; 4732c0c050c5SMichael Chan 4733894aa69aSMichael Chan /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4734c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_input { 4735c0c050c5SMichael Chan __le16 req_type; 4736c0c050c5SMichael Chan __le16 cmpl_ring; 4737c0c050c5SMichael Chan __le16 seq_id; 4738c0c050c5SMichael Chan __le16 target_id; 4739c0c050c5SMichael Chan __le64 resp_addr; 4740c0c050c5SMichael Chan }; 4741c0c050c5SMichael Chan 4742894aa69aSMichael Chan /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4743c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_output { 4744c0c050c5SMichael Chan __le16 error_code; 4745c0c050c5SMichael Chan __le16 req_type; 4746c0c050c5SMichael Chan __le16 seq_id; 4747c0c050c5SMichael Chan __le16 resp_len; 4748894aa69aSMichael Chan u8 unused_0[7]; 4749c0c050c5SMichael Chan u8 valid; 4750c0c050c5SMichael Chan }; 4751c0c050c5SMichael Chan 4752fbfee257SMichael Chan /* hwrm_port_ts_query_input (size:320b/40B) */ 47534a50ddc2SMichael Chan struct hwrm_port_ts_query_input { 47544a50ddc2SMichael Chan __le16 req_type; 47554a50ddc2SMichael Chan __le16 cmpl_ring; 47564a50ddc2SMichael Chan __le16 seq_id; 47574a50ddc2SMichael Chan __le16 target_id; 47584a50ddc2SMichael Chan __le64 resp_addr; 47594a50ddc2SMichael Chan __le32 flags; 47604a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 47614a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 47624a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 47634a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 47644a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 47654a50ddc2SMichael Chan __le16 port_id; 47664a50ddc2SMichael Chan u8 unused_0[2]; 476778eeadb8SMichael Chan __le16 enables; 476878eeadb8SMichael Chan #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 476978eeadb8SMichael Chan #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4770fbfee257SMichael Chan #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 477178eeadb8SMichael Chan __le16 ts_req_timeout; 477278eeadb8SMichael Chan __le32 ptp_seq_id; 4773fbfee257SMichael Chan __le16 ptp_hdr_offset; 4774fbfee257SMichael Chan u8 unused_1[6]; 47754a50ddc2SMichael Chan }; 47764a50ddc2SMichael Chan 47774a50ddc2SMichael Chan /* hwrm_port_ts_query_output (size:192b/24B) */ 47784a50ddc2SMichael Chan struct hwrm_port_ts_query_output { 47794a50ddc2SMichael Chan __le16 error_code; 47804a50ddc2SMichael Chan __le16 req_type; 47814a50ddc2SMichael Chan __le16 seq_id; 47824a50ddc2SMichael Chan __le16 resp_len; 47834a50ddc2SMichael Chan __le64 ptp_msg_ts; 47844a50ddc2SMichael Chan __le16 ptp_msg_seqid; 47854a50ddc2SMichael Chan u8 unused_0[5]; 47864a50ddc2SMichael Chan u8 valid; 47874a50ddc2SMichael Chan }; 47884a50ddc2SMichael Chan 4789894aa69aSMichael Chan /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 479011f15ed3SMichael Chan struct hwrm_port_phy_qcaps_input { 479111f15ed3SMichael Chan __le16 req_type; 479211f15ed3SMichael Chan __le16 cmpl_ring; 479311f15ed3SMichael Chan __le16 seq_id; 479411f15ed3SMichael Chan __le16 target_id; 479511f15ed3SMichael Chan __le64 resp_addr; 479611f15ed3SMichael Chan __le16 port_id; 4797894aa69aSMichael Chan u8 unused_0[6]; 479811f15ed3SMichael Chan }; 479911f15ed3SMichael Chan 4800bfc6e5fbSMichael Chan /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 480111f15ed3SMichael Chan struct hwrm_port_phy_qcaps_output { 480211f15ed3SMichael Chan __le16 error_code; 480311f15ed3SMichael Chan __le16 req_type; 480411f15ed3SMichael Chan __le16 seq_id; 480511f15ed3SMichael Chan __le16 resp_len; 4806acb20054SMichael Chan u8 flags; 4807acb20054SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 48086fc92c33SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 480941136ab3SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 481041136ab3SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4811bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 48129d6b648cSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 481316db6323SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 481431f67c2eSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 48156a17eb27SMichael Chan u8 port_cnt; 48166a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 48176a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 48186a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 48196a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 48206a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 48212895c153SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 48222895c153SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 482311f15ed3SMichael Chan __le16 supported_speeds_force_mode; 482411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 482511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 482611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 482711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 482811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 482911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 483011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 483111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 483211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 483311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 483411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 483511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 483611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 483711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 483811f15ed3SMichael Chan __le16 supported_speeds_auto_mode; 483911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 484011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 484111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 484211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 484311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 484411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 484511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 484611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 484711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 484811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 484911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 485011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 485111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 485211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 485311f15ed3SMichael Chan __le16 supported_speeds_eee_mode; 485411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 485511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 485611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 485711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 485811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 485911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 486011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 486111f15ed3SMichael Chan __le32 tx_lpi_timer_low; 486211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 486311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 486411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 486511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 486611f15ed3SMichael Chan __le32 valid_tx_lpi_timer_high; 486711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 486811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4869bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4870bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4871bfc6e5fbSMichael Chan __le16 supported_pam4_speeds_auto_mode; 4872bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4873bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4874bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4875bfc6e5fbSMichael Chan __le16 supported_pam4_speeds_force_mode; 4876bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4877bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4878bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 487921e70778SMichael Chan __le16 flags2; 488021e70778SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 488121e70778SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 488284a911dbSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 48832895c153SMichael Chan u8 internal_port_cnt; 4884bfc6e5fbSMichael Chan u8 valid; 488511f15ed3SMichael Chan }; 488611f15ed3SMichael Chan 4887894aa69aSMichael Chan /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 488842ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_input { 488942ee18feSAjit Khaparde __le16 req_type; 489042ee18feSAjit Khaparde __le16 cmpl_ring; 489142ee18feSAjit Khaparde __le16 seq_id; 489242ee18feSAjit Khaparde __le16 target_id; 489342ee18feSAjit Khaparde __le64 resp_addr; 489442ee18feSAjit Khaparde __le32 flags; 489542ee18feSAjit Khaparde __le32 enables; 489642ee18feSAjit Khaparde #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 489784a911dbSMichael Chan #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 489842ee18feSAjit Khaparde __le16 port_id; 489942ee18feSAjit Khaparde u8 i2c_slave_addr; 490084a911dbSMichael Chan u8 bank_number; 490142ee18feSAjit Khaparde __le16 page_number; 490242ee18feSAjit Khaparde __le16 page_offset; 490342ee18feSAjit Khaparde u8 data_length; 490442ee18feSAjit Khaparde u8 unused_1[7]; 490542ee18feSAjit Khaparde }; 490642ee18feSAjit Khaparde 4907894aa69aSMichael Chan /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 490842ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_output { 490942ee18feSAjit Khaparde __le16 error_code; 491042ee18feSAjit Khaparde __le16 req_type; 491142ee18feSAjit Khaparde __le16 seq_id; 491242ee18feSAjit Khaparde __le16 resp_len; 491342ee18feSAjit Khaparde __le32 data[16]; 4914894aa69aSMichael Chan u8 unused_0[7]; 491542ee18feSAjit Khaparde u8 valid; 491642ee18feSAjit Khaparde }; 491742ee18feSAjit Khaparde 49183322479eSMichael Chan /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 49193322479eSMichael Chan struct hwrm_port_phy_mdio_write_input { 49203322479eSMichael Chan __le16 req_type; 49213322479eSMichael Chan __le16 cmpl_ring; 49223322479eSMichael Chan __le16 seq_id; 49233322479eSMichael Chan __le16 target_id; 49243322479eSMichael Chan __le64 resp_addr; 49253322479eSMichael Chan __le32 unused_0[2]; 49263322479eSMichael Chan __le16 port_id; 49273322479eSMichael Chan u8 phy_addr; 49283322479eSMichael Chan u8 dev_addr; 49293322479eSMichael Chan __le16 reg_addr; 49303322479eSMichael Chan __le16 reg_data; 49313322479eSMichael Chan u8 cl45_mdio; 49323322479eSMichael Chan u8 unused_1[7]; 49333322479eSMichael Chan }; 49343322479eSMichael Chan 49353322479eSMichael Chan /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 49363322479eSMichael Chan struct hwrm_port_phy_mdio_write_output { 49373322479eSMichael Chan __le16 error_code; 49383322479eSMichael Chan __le16 req_type; 49393322479eSMichael Chan __le16 seq_id; 49403322479eSMichael Chan __le16 resp_len; 49413322479eSMichael Chan u8 unused_0[7]; 49423322479eSMichael Chan u8 valid; 49433322479eSMichael Chan }; 49443322479eSMichael Chan 49453322479eSMichael Chan /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 49463322479eSMichael Chan struct hwrm_port_phy_mdio_read_input { 49473322479eSMichael Chan __le16 req_type; 49483322479eSMichael Chan __le16 cmpl_ring; 49493322479eSMichael Chan __le16 seq_id; 49503322479eSMichael Chan __le16 target_id; 49513322479eSMichael Chan __le64 resp_addr; 49523322479eSMichael Chan __le32 unused_0[2]; 49533322479eSMichael Chan __le16 port_id; 49543322479eSMichael Chan u8 phy_addr; 49553322479eSMichael Chan u8 dev_addr; 49563322479eSMichael Chan __le16 reg_addr; 49573322479eSMichael Chan u8 cl45_mdio; 49583322479eSMichael Chan u8 unused_1; 49593322479eSMichael Chan }; 49603322479eSMichael Chan 49613322479eSMichael Chan /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 49623322479eSMichael Chan struct hwrm_port_phy_mdio_read_output { 49633322479eSMichael Chan __le16 error_code; 49643322479eSMichael Chan __le16 req_type; 49653322479eSMichael Chan __le16 seq_id; 49663322479eSMichael Chan __le16 resp_len; 49673322479eSMichael Chan __le16 reg_data; 49683322479eSMichael Chan u8 unused_0[5]; 49693322479eSMichael Chan u8 valid; 49703322479eSMichael Chan }; 49713322479eSMichael Chan 4972894aa69aSMichael Chan /* hwrm_port_led_cfg_input (size:512b/64B) */ 4973f183886cSMichael Chan struct hwrm_port_led_cfg_input { 4974f183886cSMichael Chan __le16 req_type; 4975f183886cSMichael Chan __le16 cmpl_ring; 4976f183886cSMichael Chan __le16 seq_id; 4977f183886cSMichael Chan __le16 target_id; 4978f183886cSMichael Chan __le64 resp_addr; 4979f183886cSMichael Chan __le32 enables; 4980f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4981f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4982f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4983f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4984f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4985f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4986f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4987f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4988f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4989f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4990f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4991f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4992f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4993f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4994f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4995f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4996f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4997f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4998f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4999f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5000f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5001f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5002f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5003f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5004f183886cSMichael Chan __le16 port_id; 5005f183886cSMichael Chan u8 num_leds; 5006f183886cSMichael Chan u8 rsvd; 5007f183886cSMichael Chan u8 led0_id; 5008f183886cSMichael Chan u8 led0_state; 5009f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5010f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5011f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5012f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5013f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5014894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5015f183886cSMichael Chan u8 led0_color; 5016f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5017f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5018f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5019f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5020894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5021f183886cSMichael Chan u8 unused_0; 5022f183886cSMichael Chan __le16 led0_blink_on; 5023f183886cSMichael Chan __le16 led0_blink_off; 5024f183886cSMichael Chan u8 led0_group_id; 5025f183886cSMichael Chan u8 rsvd0; 5026f183886cSMichael Chan u8 led1_id; 5027f183886cSMichael Chan u8 led1_state; 5028f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5029f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5030f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5031f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5032f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5033894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5034f183886cSMichael Chan u8 led1_color; 5035f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5036f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5037f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5038f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5039894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5040f183886cSMichael Chan u8 unused_1; 5041f183886cSMichael Chan __le16 led1_blink_on; 5042f183886cSMichael Chan __le16 led1_blink_off; 5043f183886cSMichael Chan u8 led1_group_id; 5044f183886cSMichael Chan u8 rsvd1; 5045f183886cSMichael Chan u8 led2_id; 5046f183886cSMichael Chan u8 led2_state; 5047f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5048f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5049f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5050f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5051f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5052894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5053f183886cSMichael Chan u8 led2_color; 5054f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5055f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5056f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5057f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5058894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5059f183886cSMichael Chan u8 unused_2; 5060f183886cSMichael Chan __le16 led2_blink_on; 5061f183886cSMichael Chan __le16 led2_blink_off; 5062f183886cSMichael Chan u8 led2_group_id; 5063f183886cSMichael Chan u8 rsvd2; 5064f183886cSMichael Chan u8 led3_id; 5065f183886cSMichael Chan u8 led3_state; 5066f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5067f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5068f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5069f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5070f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5071894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5072f183886cSMichael Chan u8 led3_color; 5073f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5074f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5075f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5076f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5077894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5078f183886cSMichael Chan u8 unused_3; 5079f183886cSMichael Chan __le16 led3_blink_on; 5080f183886cSMichael Chan __le16 led3_blink_off; 5081f183886cSMichael Chan u8 led3_group_id; 5082f183886cSMichael Chan u8 rsvd3; 5083f183886cSMichael Chan }; 5084f183886cSMichael Chan 5085894aa69aSMichael Chan /* hwrm_port_led_cfg_output (size:128b/16B) */ 5086f183886cSMichael Chan struct hwrm_port_led_cfg_output { 5087f183886cSMichael Chan __le16 error_code; 5088f183886cSMichael Chan __le16 req_type; 5089f183886cSMichael Chan __le16 seq_id; 5090f183886cSMichael Chan __le16 resp_len; 5091894aa69aSMichael Chan u8 unused_0[7]; 5092f183886cSMichael Chan u8 valid; 5093f183886cSMichael Chan }; 5094f183886cSMichael Chan 5095894aa69aSMichael Chan /* hwrm_port_led_qcfg_input (size:192b/24B) */ 5096894aa69aSMichael Chan struct hwrm_port_led_qcfg_input { 5097894aa69aSMichael Chan __le16 req_type; 5098894aa69aSMichael Chan __le16 cmpl_ring; 5099894aa69aSMichael Chan __le16 seq_id; 5100894aa69aSMichael Chan __le16 target_id; 5101894aa69aSMichael Chan __le64 resp_addr; 5102894aa69aSMichael Chan __le16 port_id; 5103894aa69aSMichael Chan u8 unused_0[6]; 5104894aa69aSMichael Chan }; 5105894aa69aSMichael Chan 5106894aa69aSMichael Chan /* hwrm_port_led_qcfg_output (size:448b/56B) */ 5107894aa69aSMichael Chan struct hwrm_port_led_qcfg_output { 5108894aa69aSMichael Chan __le16 error_code; 5109894aa69aSMichael Chan __le16 req_type; 5110894aa69aSMichael Chan __le16 seq_id; 5111894aa69aSMichael Chan __le16 resp_len; 5112894aa69aSMichael Chan u8 num_leds; 5113894aa69aSMichael Chan u8 led0_id; 5114894aa69aSMichael Chan u8 led0_type; 5115894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5116894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5117894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5118894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5119894aa69aSMichael Chan u8 led0_state; 5120894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5121894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5122894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5123894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5124894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5125894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5126894aa69aSMichael Chan u8 led0_color; 5127894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5128894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5129894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5130894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5131894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5132894aa69aSMichael Chan u8 unused_0; 5133894aa69aSMichael Chan __le16 led0_blink_on; 5134894aa69aSMichael Chan __le16 led0_blink_off; 5135894aa69aSMichael Chan u8 led0_group_id; 5136894aa69aSMichael Chan u8 led1_id; 5137894aa69aSMichael Chan u8 led1_type; 5138894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5139894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5140894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5141894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5142894aa69aSMichael Chan u8 led1_state; 5143894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5144894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5145894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5146894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5147894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5148894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5149894aa69aSMichael Chan u8 led1_color; 5150894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5151894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5152894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5153894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5154894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5155894aa69aSMichael Chan u8 unused_1; 5156894aa69aSMichael Chan __le16 led1_blink_on; 5157894aa69aSMichael Chan __le16 led1_blink_off; 5158894aa69aSMichael Chan u8 led1_group_id; 5159894aa69aSMichael Chan u8 led2_id; 5160894aa69aSMichael Chan u8 led2_type; 5161894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5162894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5163894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5164894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5165894aa69aSMichael Chan u8 led2_state; 5166894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5167894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5168894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5169894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5170894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5171894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5172894aa69aSMichael Chan u8 led2_color; 5173894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5174894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5175894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5176894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5177894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5178894aa69aSMichael Chan u8 unused_2; 5179894aa69aSMichael Chan __le16 led2_blink_on; 5180894aa69aSMichael Chan __le16 led2_blink_off; 5181894aa69aSMichael Chan u8 led2_group_id; 5182894aa69aSMichael Chan u8 led3_id; 5183894aa69aSMichael Chan u8 led3_type; 5184894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5185894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5186894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5187894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5188894aa69aSMichael Chan u8 led3_state; 5189894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5190894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5191894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5192894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5193894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5194894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5195894aa69aSMichael Chan u8 led3_color; 5196894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5197894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5198894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5199894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5200894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5201894aa69aSMichael Chan u8 unused_3; 5202894aa69aSMichael Chan __le16 led3_blink_on; 5203894aa69aSMichael Chan __le16 led3_blink_off; 5204894aa69aSMichael Chan u8 led3_group_id; 5205894aa69aSMichael Chan u8 unused_4[6]; 5206894aa69aSMichael Chan u8 valid; 5207894aa69aSMichael Chan }; 5208894aa69aSMichael Chan 5209894aa69aSMichael Chan /* hwrm_port_led_qcaps_input (size:192b/24B) */ 5210f183886cSMichael Chan struct hwrm_port_led_qcaps_input { 5211f183886cSMichael Chan __le16 req_type; 5212f183886cSMichael Chan __le16 cmpl_ring; 5213f183886cSMichael Chan __le16 seq_id; 5214f183886cSMichael Chan __le16 target_id; 5215f183886cSMichael Chan __le64 resp_addr; 5216f183886cSMichael Chan __le16 port_id; 5217894aa69aSMichael Chan u8 unused_0[6]; 5218f183886cSMichael Chan }; 5219f183886cSMichael Chan 5220894aa69aSMichael Chan /* hwrm_port_led_qcaps_output (size:384b/48B) */ 5221f183886cSMichael Chan struct hwrm_port_led_qcaps_output { 5222f183886cSMichael Chan __le16 error_code; 5223f183886cSMichael Chan __le16 req_type; 5224f183886cSMichael Chan __le16 seq_id; 5225f183886cSMichael Chan __le16 resp_len; 5226f183886cSMichael Chan u8 num_leds; 5227894aa69aSMichael Chan u8 unused[3]; 5228f183886cSMichael Chan u8 led0_id; 5229f183886cSMichael Chan u8 led0_type; 5230f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5231f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5232f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5233894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5234f183886cSMichael Chan u8 led0_group_id; 5235894aa69aSMichael Chan u8 unused_0; 5236f183886cSMichael Chan __le16 led0_state_caps; 5237f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5238f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5239f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5240f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5241f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5242f183886cSMichael Chan __le16 led0_color_caps; 5243f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5244f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5245f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5246f183886cSMichael Chan u8 led1_id; 5247f183886cSMichael Chan u8 led1_type; 5248f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5249f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5250f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5251894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5252f183886cSMichael Chan u8 led1_group_id; 5253894aa69aSMichael Chan u8 unused_1; 5254f183886cSMichael Chan __le16 led1_state_caps; 5255f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 5256f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 5257f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 5258f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5259f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5260f183886cSMichael Chan __le16 led1_color_caps; 5261f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 5262f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5263f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5264f183886cSMichael Chan u8 led2_id; 5265f183886cSMichael Chan u8 led2_type; 5266f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 5267f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 5268f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 5269894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 5270f183886cSMichael Chan u8 led2_group_id; 5271894aa69aSMichael Chan u8 unused_2; 5272f183886cSMichael Chan __le16 led2_state_caps; 5273f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 5274f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 5275f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 5276f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5277f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5278f183886cSMichael Chan __le16 led2_color_caps; 5279f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 5280f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5281f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5282f183886cSMichael Chan u8 led3_id; 5283f183886cSMichael Chan u8 led3_type; 5284f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 5285f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 5286f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 5287894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 5288f183886cSMichael Chan u8 led3_group_id; 5289894aa69aSMichael Chan u8 unused_3; 5290f183886cSMichael Chan __le16 led3_state_caps; 5291f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 5292f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 5293f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 5294f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5295f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5296f183886cSMichael Chan __le16 led3_color_caps; 5297f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 5298f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5299f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5300894aa69aSMichael Chan u8 unused_4[3]; 5301f183886cSMichael Chan u8 valid; 5302f183886cSMichael Chan }; 5303f183886cSMichael Chan 5304894aa69aSMichael Chan /* hwrm_queue_qportcfg_input (size:192b/24B) */ 5305c0c050c5SMichael Chan struct hwrm_queue_qportcfg_input { 5306c0c050c5SMichael Chan __le16 req_type; 5307c0c050c5SMichael Chan __le16 cmpl_ring; 5308c0c050c5SMichael Chan __le16 seq_id; 5309c0c050c5SMichael Chan __le16 target_id; 5310c0c050c5SMichael Chan __le64 resp_addr; 5311c0c050c5SMichael Chan __le32 flags; 5312c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 5313441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 5314441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 531511f15ed3SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 5316c0c050c5SMichael Chan __le16 port_id; 5317d4f52de0SMichael Chan u8 drv_qmap_cap; 5318d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 5319d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 5320d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 5321d4f52de0SMichael Chan u8 unused_0; 5322c0c050c5SMichael Chan }; 5323c0c050c5SMichael Chan 5324bfc6e5fbSMichael Chan /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 5325c0c050c5SMichael Chan struct hwrm_queue_qportcfg_output { 5326c0c050c5SMichael Chan __le16 error_code; 5327c0c050c5SMichael Chan __le16 req_type; 5328c0c050c5SMichael Chan __le16 seq_id; 5329c0c050c5SMichael Chan __le16 resp_len; 5330c0c050c5SMichael Chan u8 max_configurable_queues; 5331c0c050c5SMichael Chan u8 max_configurable_lossless_queues; 5332c0c050c5SMichael Chan u8 queue_cfg_allowed; 5333441cabbbSMichael Chan u8 queue_cfg_info; 5334441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 533578eeadb8SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 5336c0c050c5SMichael Chan u8 queue_pfcenable_cfg_allowed; 5337c0c050c5SMichael Chan u8 queue_pri2cos_cfg_allowed; 5338c0c050c5SMichael Chan u8 queue_cos2bw_cfg_allowed; 5339c0c050c5SMichael Chan u8 queue_id0; 5340c0c050c5SMichael Chan u8 queue_id0_service_profile; 5341441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 53426fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 5343d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5344d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5345d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5346441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 5347894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 5348c0c050c5SMichael Chan u8 queue_id1; 5349c0c050c5SMichael Chan u8 queue_id1_service_profile; 5350441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 53516fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 5352d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5353d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5354d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5355441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 5356894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 5357c0c050c5SMichael Chan u8 queue_id2; 5358c0c050c5SMichael Chan u8 queue_id2_service_profile; 5359441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 53606fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 5361d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5362d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5363d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5364441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 5365894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 5366c0c050c5SMichael Chan u8 queue_id3; 5367c0c050c5SMichael Chan u8 queue_id3_service_profile; 5368441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 53696fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 5370d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5371d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5372d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5373441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 5374894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 5375c0c050c5SMichael Chan u8 queue_id4; 5376c0c050c5SMichael Chan u8 queue_id4_service_profile; 5377441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 53786fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 5379d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5380d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5381d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5382441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 5383894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 5384c0c050c5SMichael Chan u8 queue_id5; 5385c0c050c5SMichael Chan u8 queue_id5_service_profile; 5386441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 53876fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 5388d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5389d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5390d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5391441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 5392894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 5393c0c050c5SMichael Chan u8 queue_id6; 5394c0c050c5SMichael Chan u8 queue_id6_service_profile; 5395441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 53966fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 5397d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5398d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5399d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5400441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 5401894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 5402c0c050c5SMichael Chan u8 queue_id7; 5403c0c050c5SMichael Chan u8 queue_id7_service_profile; 5404441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 54056fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 5406d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 5407d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 5408d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 5409441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 5410894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 541116db6323SMichael Chan u8 queue_id0_service_profile_type; 541216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 541316db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 541416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 5415bfc6e5fbSMichael Chan char qid0_name[16]; 5416bfc6e5fbSMichael Chan char qid1_name[16]; 5417bfc6e5fbSMichael Chan char qid2_name[16]; 5418bfc6e5fbSMichael Chan char qid3_name[16]; 5419bfc6e5fbSMichael Chan char qid4_name[16]; 5420bfc6e5fbSMichael Chan char qid5_name[16]; 5421bfc6e5fbSMichael Chan char qid6_name[16]; 5422bfc6e5fbSMichael Chan char qid7_name[16]; 542316db6323SMichael Chan u8 queue_id1_service_profile_type; 542416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 542516db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 542616db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 542716db6323SMichael Chan u8 queue_id2_service_profile_type; 542816db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 542916db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 543016db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 543116db6323SMichael Chan u8 queue_id3_service_profile_type; 543216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 543316db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 543416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 543516db6323SMichael Chan u8 queue_id4_service_profile_type; 543616db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 543716db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 543816db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 543916db6323SMichael Chan u8 queue_id5_service_profile_type; 544016db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 544116db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 544216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 544316db6323SMichael Chan u8 queue_id6_service_profile_type; 544416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 544516db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 544616db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 544716db6323SMichael Chan u8 queue_id7_service_profile_type; 544816db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 544916db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 545016db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 5451bfc6e5fbSMichael Chan u8 valid; 5452bfc6e5fbSMichael Chan }; 5453bfc6e5fbSMichael Chan 5454bfc6e5fbSMichael Chan /* hwrm_queue_qcfg_input (size:192b/24B) */ 5455bfc6e5fbSMichael Chan struct hwrm_queue_qcfg_input { 5456bfc6e5fbSMichael Chan __le16 req_type; 5457bfc6e5fbSMichael Chan __le16 cmpl_ring; 5458bfc6e5fbSMichael Chan __le16 seq_id; 5459bfc6e5fbSMichael Chan __le16 target_id; 5460bfc6e5fbSMichael Chan __le64 resp_addr; 5461bfc6e5fbSMichael Chan __le32 flags; 5462bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 5463bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5464bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 5465bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 5466bfc6e5fbSMichael Chan __le32 queue_id; 5467bfc6e5fbSMichael Chan }; 5468bfc6e5fbSMichael Chan 5469bfc6e5fbSMichael Chan /* hwrm_queue_qcfg_output (size:128b/16B) */ 5470bfc6e5fbSMichael Chan struct hwrm_queue_qcfg_output { 5471bfc6e5fbSMichael Chan __le16 error_code; 5472bfc6e5fbSMichael Chan __le16 req_type; 5473bfc6e5fbSMichael Chan __le16 seq_id; 5474bfc6e5fbSMichael Chan __le16 resp_len; 5475bfc6e5fbSMichael Chan __le32 queue_len; 5476bfc6e5fbSMichael Chan u8 service_profile; 5477bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 5478bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 5479bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 5480bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 5481bfc6e5fbSMichael Chan u8 queue_cfg_info; 5482bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5483bfc6e5fbSMichael Chan u8 unused_0; 5484c0c050c5SMichael Chan u8 valid; 5485c0c050c5SMichael Chan }; 5486c0c050c5SMichael Chan 5487894aa69aSMichael Chan /* hwrm_queue_cfg_input (size:320b/40B) */ 5488c0c050c5SMichael Chan struct hwrm_queue_cfg_input { 5489c0c050c5SMichael Chan __le16 req_type; 5490c0c050c5SMichael Chan __le16 cmpl_ring; 5491c0c050c5SMichael Chan __le16 seq_id; 5492c0c050c5SMichael Chan __le16 target_id; 5493c0c050c5SMichael Chan __le64 resp_addr; 5494c0c050c5SMichael Chan __le32 flags; 5495441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5496441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5497441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5498441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5499441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5500441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5501c0c050c5SMichael Chan __le32 enables; 5502c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5503c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5504c0c050c5SMichael Chan __le32 queue_id; 5505c0c050c5SMichael Chan __le32 dflt_len; 5506c0c050c5SMichael Chan u8 service_profile; 5507441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5508441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5509441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5510894aa69aSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5511c0c050c5SMichael Chan u8 unused_0[7]; 5512c0c050c5SMichael Chan }; 5513c0c050c5SMichael Chan 5514894aa69aSMichael Chan /* hwrm_queue_cfg_output (size:128b/16B) */ 5515c0c050c5SMichael Chan struct hwrm_queue_cfg_output { 5516c0c050c5SMichael Chan __le16 error_code; 5517c0c050c5SMichael Chan __le16 req_type; 5518c0c050c5SMichael Chan __le16 seq_id; 5519c0c050c5SMichael Chan __le16 resp_len; 5520894aa69aSMichael Chan u8 unused_0[7]; 5521c0c050c5SMichael Chan u8 valid; 5522c0c050c5SMichael Chan }; 5523c0c050c5SMichael Chan 5524894aa69aSMichael Chan /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 552587c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_input { 552687c374deSMichael Chan __le16 req_type; 552787c374deSMichael Chan __le16 cmpl_ring; 552887c374deSMichael Chan __le16 seq_id; 552987c374deSMichael Chan __le16 target_id; 553087c374deSMichael Chan __le64 resp_addr; 553187c374deSMichael Chan __le16 port_id; 5532894aa69aSMichael Chan u8 unused_0[6]; 553387c374deSMichael Chan }; 553487c374deSMichael Chan 5535894aa69aSMichael Chan /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 553687c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_output { 553787c374deSMichael Chan __le16 error_code; 553887c374deSMichael Chan __le16 req_type; 553987c374deSMichael Chan __le16 seq_id; 554087c374deSMichael Chan __le16 resp_len; 554187c374deSMichael Chan __le32 flags; 554287c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 554387c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 554487c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 554587c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 554687c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 554787c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 554887c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 554987c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5550460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5551460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5552460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5553460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5554460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5555460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5556460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5557460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5558894aa69aSMichael Chan u8 unused_0[3]; 555987c374deSMichael Chan u8 valid; 556087c374deSMichael Chan }; 556187c374deSMichael Chan 5562894aa69aSMichael Chan /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5563c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_input { 5564c0c050c5SMichael Chan __le16 req_type; 5565c0c050c5SMichael Chan __le16 cmpl_ring; 5566c0c050c5SMichael Chan __le16 seq_id; 5567c0c050c5SMichael Chan __le16 target_id; 5568c0c050c5SMichael Chan __le64 resp_addr; 5569c193554eSMichael Chan __le32 flags; 5570c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5571c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5572c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5573c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5574c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5575c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5576c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5577c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5578460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5579460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5580460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5581460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5582460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5583460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5584460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5585460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5586c0c050c5SMichael Chan __le16 port_id; 5587894aa69aSMichael Chan u8 unused_0[2]; 5588c0c050c5SMichael Chan }; 5589c0c050c5SMichael Chan 5590894aa69aSMichael Chan /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5591c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_output { 5592c0c050c5SMichael Chan __le16 error_code; 5593c0c050c5SMichael Chan __le16 req_type; 5594c0c050c5SMichael Chan __le16 seq_id; 5595c0c050c5SMichael Chan __le16 resp_len; 5596894aa69aSMichael Chan u8 unused_0[7]; 5597c0c050c5SMichael Chan u8 valid; 5598c0c050c5SMichael Chan }; 5599c0c050c5SMichael Chan 5600894aa69aSMichael Chan /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 560187c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_input { 560287c374deSMichael Chan __le16 req_type; 560387c374deSMichael Chan __le16 cmpl_ring; 560487c374deSMichael Chan __le16 seq_id; 560587c374deSMichael Chan __le16 target_id; 560687c374deSMichael Chan __le64 resp_addr; 560787c374deSMichael Chan __le32 flags; 560887c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5609894aa69aSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5610894aa69aSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 561187c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 561287c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 561387c374deSMichael Chan u8 port_id; 561487c374deSMichael Chan u8 unused_0[3]; 561587c374deSMichael Chan }; 561687c374deSMichael Chan 5617894aa69aSMichael Chan /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 561887c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_output { 561987c374deSMichael Chan __le16 error_code; 562087c374deSMichael Chan __le16 req_type; 562187c374deSMichael Chan __le16 seq_id; 562287c374deSMichael Chan __le16 resp_len; 562387c374deSMichael Chan u8 pri0_cos_queue_id; 562487c374deSMichael Chan u8 pri1_cos_queue_id; 562587c374deSMichael Chan u8 pri2_cos_queue_id; 562687c374deSMichael Chan u8 pri3_cos_queue_id; 562787c374deSMichael Chan u8 pri4_cos_queue_id; 562887c374deSMichael Chan u8 pri5_cos_queue_id; 562987c374deSMichael Chan u8 pri6_cos_queue_id; 563087c374deSMichael Chan u8 pri7_cos_queue_id; 563187c374deSMichael Chan u8 queue_cfg_info; 563287c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5633894aa69aSMichael Chan u8 unused_0[6]; 563487c374deSMichael Chan u8 valid; 563587c374deSMichael Chan }; 563687c374deSMichael Chan 5637894aa69aSMichael Chan /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5638c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_input { 5639c0c050c5SMichael Chan __le16 req_type; 5640c0c050c5SMichael Chan __le16 cmpl_ring; 5641c0c050c5SMichael Chan __le16 seq_id; 5642c0c050c5SMichael Chan __le16 target_id; 5643c0c050c5SMichael Chan __le64 resp_addr; 5644c0c050c5SMichael Chan __le32 flags; 5645441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5646441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5647894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5648894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5649894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5650441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5651441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5652c0c050c5SMichael Chan __le32 enables; 5653441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5654441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5655441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5656441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5657441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5658441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5659441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5660441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5661c0c050c5SMichael Chan u8 port_id; 5662c193554eSMichael Chan u8 pri0_cos_queue_id; 5663c193554eSMichael Chan u8 pri1_cos_queue_id; 5664c193554eSMichael Chan u8 pri2_cos_queue_id; 5665c193554eSMichael Chan u8 pri3_cos_queue_id; 5666c193554eSMichael Chan u8 pri4_cos_queue_id; 5667c193554eSMichael Chan u8 pri5_cos_queue_id; 5668c193554eSMichael Chan u8 pri6_cos_queue_id; 5669c193554eSMichael Chan u8 pri7_cos_queue_id; 5670c0c050c5SMichael Chan u8 unused_0[7]; 5671c0c050c5SMichael Chan }; 5672c0c050c5SMichael Chan 5673894aa69aSMichael Chan /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5674c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_output { 5675c0c050c5SMichael Chan __le16 error_code; 5676c0c050c5SMichael Chan __le16 req_type; 5677c0c050c5SMichael Chan __le16 seq_id; 5678c0c050c5SMichael Chan __le16 resp_len; 5679894aa69aSMichael Chan u8 unused_0[7]; 5680c0c050c5SMichael Chan u8 valid; 5681c0c050c5SMichael Chan }; 5682c0c050c5SMichael Chan 5683894aa69aSMichael Chan /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 568487c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_input { 568587c374deSMichael Chan __le16 req_type; 568687c374deSMichael Chan __le16 cmpl_ring; 568787c374deSMichael Chan __le16 seq_id; 568887c374deSMichael Chan __le16 target_id; 568987c374deSMichael Chan __le64 resp_addr; 569087c374deSMichael Chan __le16 port_id; 5691894aa69aSMichael Chan u8 unused_0[6]; 569287c374deSMichael Chan }; 569387c374deSMichael Chan 5694894aa69aSMichael Chan /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 569587c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_output { 569687c374deSMichael Chan __le16 error_code; 569787c374deSMichael Chan __le16 req_type; 569887c374deSMichael Chan __le16 seq_id; 569987c374deSMichael Chan __le16 resp_len; 570087c374deSMichael Chan u8 queue_id0; 570187c374deSMichael Chan u8 unused_0; 570287c374deSMichael Chan __le16 unused_1; 570387c374deSMichael Chan __le32 queue_id0_min_bw; 570487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 570587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5706bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5707bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5708bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5709bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 571087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 571187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5712bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5713bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5714bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5715bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 571687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 571787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 571887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 571987c374deSMichael Chan __le32 queue_id0_max_bw; 572087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 572187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5722bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5723bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5724bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5725bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 572687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 572787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5728bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5729bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5730bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5731bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 573287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 573387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 573487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 573587c374deSMichael Chan u8 queue_id0_tsa_assign; 573687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 573787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 573887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 573987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 574087c374deSMichael Chan u8 queue_id0_pri_lvl; 574187c374deSMichael Chan u8 queue_id0_bw_weight; 574287c374deSMichael Chan u8 queue_id1; 574387c374deSMichael Chan __le32 queue_id1_min_bw; 574487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 574587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5746bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5747bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5748bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5749bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 575087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 575187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5752bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5753bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5754bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5755bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 575687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 575787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 575887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 575987c374deSMichael Chan __le32 queue_id1_max_bw; 576087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 576187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5762bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5763bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5764bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5765bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 576687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 576787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5768bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5769bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5770bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5771bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 577287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 577387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 577487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 577587c374deSMichael Chan u8 queue_id1_tsa_assign; 577687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 577787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 577887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 577987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 578087c374deSMichael Chan u8 queue_id1_pri_lvl; 578187c374deSMichael Chan u8 queue_id1_bw_weight; 578287c374deSMichael Chan u8 queue_id2; 578387c374deSMichael Chan __le32 queue_id2_min_bw; 578487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 578587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5786bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5787bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5788bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5789bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 579087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 579187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5792bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5793bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5794bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5795bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 579687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 579787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 579887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 579987c374deSMichael Chan __le32 queue_id2_max_bw; 580087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 580187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5802bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5803bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5804bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5805bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 580687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 580787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5808bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5809bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5810bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5811bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 581287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 581387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 581487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 581587c374deSMichael Chan u8 queue_id2_tsa_assign; 581687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 581787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 581887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 581987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 582087c374deSMichael Chan u8 queue_id2_pri_lvl; 582187c374deSMichael Chan u8 queue_id2_bw_weight; 582287c374deSMichael Chan u8 queue_id3; 582387c374deSMichael Chan __le32 queue_id3_min_bw; 582487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 582587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5826bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5827bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5828bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5829bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 583087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 583187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5832bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5833bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5834bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5835bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 583687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 583787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 583887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 583987c374deSMichael Chan __le32 queue_id3_max_bw; 584087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 584187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5842bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5843bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5844bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5845bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 584687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 584787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5848bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5849bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5850bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5851bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 585287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 585387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 585487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 585587c374deSMichael Chan u8 queue_id3_tsa_assign; 585687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 585787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 585887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 585987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 586087c374deSMichael Chan u8 queue_id3_pri_lvl; 586187c374deSMichael Chan u8 queue_id3_bw_weight; 586287c374deSMichael Chan u8 queue_id4; 586387c374deSMichael Chan __le32 queue_id4_min_bw; 586487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 586587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5866bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5867bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5868bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5869bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 587087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 587187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5872bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5873bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5874bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5875bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 587687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 587787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 587887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 587987c374deSMichael Chan __le32 queue_id4_max_bw; 588087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 588187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5882bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5883bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5884bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5885bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 588687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 588787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5888bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5889bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5890bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5891bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 589287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 589387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 589487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 589587c374deSMichael Chan u8 queue_id4_tsa_assign; 589687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 589787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 589887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 589987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 590087c374deSMichael Chan u8 queue_id4_pri_lvl; 590187c374deSMichael Chan u8 queue_id4_bw_weight; 590287c374deSMichael Chan u8 queue_id5; 590387c374deSMichael Chan __le32 queue_id5_min_bw; 590487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 590587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5906bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5907bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5908bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5909bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 591087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 591187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5912bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5913bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5914bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5915bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 591687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 591787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 591887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 591987c374deSMichael Chan __le32 queue_id5_max_bw; 592087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 592187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5922bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5923bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5924bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5925bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 592687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 592787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5928bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5929bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5930bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5931bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 593287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 593387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 593487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 593587c374deSMichael Chan u8 queue_id5_tsa_assign; 593687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 593787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 593887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 593987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 594087c374deSMichael Chan u8 queue_id5_pri_lvl; 594187c374deSMichael Chan u8 queue_id5_bw_weight; 594287c374deSMichael Chan u8 queue_id6; 594387c374deSMichael Chan __le32 queue_id6_min_bw; 594487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 594587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5946bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5947bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5948bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5949bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 595087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 595187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5952bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5953bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5954bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5955bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 595687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 595787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 595887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 595987c374deSMichael Chan __le32 queue_id6_max_bw; 596087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 596187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5962bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5963bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5964bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5965bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 596687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 596787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5968bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5969bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5970bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5971bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 597287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 597387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 597487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 597587c374deSMichael Chan u8 queue_id6_tsa_assign; 597687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 597787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 597887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 597987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 598087c374deSMichael Chan u8 queue_id6_pri_lvl; 598187c374deSMichael Chan u8 queue_id6_bw_weight; 598287c374deSMichael Chan u8 queue_id7; 598387c374deSMichael Chan __le32 queue_id7_min_bw; 598487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 598587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5986bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5987bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5988bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5989bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 599087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 599187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5992bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5993bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5994bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5995bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 599687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 599787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 599887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 599987c374deSMichael Chan __le32 queue_id7_max_bw; 600087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 600187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 6002bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 6003bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 6004bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 6005bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 600687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 600787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 6008bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6009bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6010bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6011bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 601287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 601387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 601487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 601587c374deSMichael Chan u8 queue_id7_tsa_assign; 601687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 601787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 601887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 601987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 602087c374deSMichael Chan u8 queue_id7_pri_lvl; 602187c374deSMichael Chan u8 queue_id7_bw_weight; 6022894aa69aSMichael Chan u8 unused_2[4]; 602387c374deSMichael Chan u8 valid; 602487c374deSMichael Chan }; 602587c374deSMichael Chan 6026894aa69aSMichael Chan /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6027c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_input { 6028c0c050c5SMichael Chan __le16 req_type; 6029c0c050c5SMichael Chan __le16 cmpl_ring; 6030c0c050c5SMichael Chan __le16 seq_id; 6031c0c050c5SMichael Chan __le16 target_id; 6032c0c050c5SMichael Chan __le64 resp_addr; 6033c0c050c5SMichael Chan __le32 flags; 6034c0c050c5SMichael Chan __le32 enables; 6035c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6036c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6037c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6038c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6039c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6040c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6041c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6042c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6043c0c050c5SMichael Chan __le16 port_id; 6044c0c050c5SMichael Chan u8 queue_id0; 6045c0c050c5SMichael Chan u8 unused_0; 6046c0c050c5SMichael Chan __le32 queue_id0_min_bw; 6047441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6048441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6049bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6050bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6051bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6052bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6053441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6054441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6055bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6056bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6057bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6058bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6059441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6060441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6061441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6062c0c050c5SMichael Chan __le32 queue_id0_max_bw; 6063441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6064441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6065bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6066bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6067bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6068bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6069441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6070441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6071bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6072bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6073bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6074bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6075441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6076441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6077441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6078c0c050c5SMichael Chan u8 queue_id0_tsa_assign; 6079441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6080441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6081441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6082441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6083c0c050c5SMichael Chan u8 queue_id0_pri_lvl; 6084c0c050c5SMichael Chan u8 queue_id0_bw_weight; 6085c0c050c5SMichael Chan u8 queue_id1; 6086c0c050c5SMichael Chan __le32 queue_id1_min_bw; 6087441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6088441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 6089bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 6090bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 6091bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 6092bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 6093441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6094441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 6095bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6096bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6097bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6098bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6099441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6100441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6101441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 6102c0c050c5SMichael Chan __le32 queue_id1_max_bw; 6103441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6104441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 6105bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 6106bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 6107bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 6108bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 6109441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6110441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 6111bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6112bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6113bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6114bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6115441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6116441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6117441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 6118c0c050c5SMichael Chan u8 queue_id1_tsa_assign; 6119441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 6120441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 6121441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6122441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 6123c0c050c5SMichael Chan u8 queue_id1_pri_lvl; 6124c0c050c5SMichael Chan u8 queue_id1_bw_weight; 6125c0c050c5SMichael Chan u8 queue_id2; 6126c0c050c5SMichael Chan __le32 queue_id2_min_bw; 6127441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6128441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 6129bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 6130bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 6131bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 6132bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 6133441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6134441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 6135bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6136bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6137bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6138bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6139441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6140441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6141441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 6142c0c050c5SMichael Chan __le32 queue_id2_max_bw; 6143441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6144441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 6145bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 6146bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 6147bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 6148bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 6149441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6150441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 6151bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6152bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6153bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6154bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6155441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6156441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6157441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 6158c0c050c5SMichael Chan u8 queue_id2_tsa_assign; 6159441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 6160441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 6161441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6162441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 6163c0c050c5SMichael Chan u8 queue_id2_pri_lvl; 6164c0c050c5SMichael Chan u8 queue_id2_bw_weight; 6165c0c050c5SMichael Chan u8 queue_id3; 6166c0c050c5SMichael Chan __le32 queue_id3_min_bw; 6167441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6168441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 6169bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 6170bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 6171bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 6172bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 6173441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6174441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 6175bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6176bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6177bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6178bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6179441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6180441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6181441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 6182c0c050c5SMichael Chan __le32 queue_id3_max_bw; 6183441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6184441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 6185bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 6186bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 6187bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 6188bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 6189441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6190441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 6191bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6192bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6193bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6194bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6195441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6196441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6197441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 6198c0c050c5SMichael Chan u8 queue_id3_tsa_assign; 6199441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 6200441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 6201441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6202441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 6203c0c050c5SMichael Chan u8 queue_id3_pri_lvl; 6204c0c050c5SMichael Chan u8 queue_id3_bw_weight; 6205c0c050c5SMichael Chan u8 queue_id4; 6206c0c050c5SMichael Chan __le32 queue_id4_min_bw; 6207441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6208441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 6209bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 6210bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 6211bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 6212bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 6213441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6214441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 6215bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6216bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6217bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6218bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6219441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6220441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6221441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 6222c0c050c5SMichael Chan __le32 queue_id4_max_bw; 6223441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6224441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 6225bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 6226bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 6227bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 6228bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 6229441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6230441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 6231bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6232bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6233bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6234bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6235441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6236441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6237441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 6238c0c050c5SMichael Chan u8 queue_id4_tsa_assign; 6239441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 6240441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 6241441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6242441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 6243c0c050c5SMichael Chan u8 queue_id4_pri_lvl; 6244c0c050c5SMichael Chan u8 queue_id4_bw_weight; 6245c0c050c5SMichael Chan u8 queue_id5; 6246c0c050c5SMichael Chan __le32 queue_id5_min_bw; 6247441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6248441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 6249bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 6250bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 6251bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 6252bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 6253441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6254441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 6255bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6256bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6257bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6258bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6259441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6260441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6261441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 6262c0c050c5SMichael Chan __le32 queue_id5_max_bw; 6263441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6264441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 6265bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 6266bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 6267bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 6268bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 6269441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6270441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 6271bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6272bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6273bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6274bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6275441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6276441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6277441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 6278c0c050c5SMichael Chan u8 queue_id5_tsa_assign; 6279441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 6280441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 6281441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6282441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 6283c0c050c5SMichael Chan u8 queue_id5_pri_lvl; 6284c0c050c5SMichael Chan u8 queue_id5_bw_weight; 6285c0c050c5SMichael Chan u8 queue_id6; 6286c0c050c5SMichael Chan __le32 queue_id6_min_bw; 6287441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6288441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 6289bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 6290bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 6291bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 6292bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 6293441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6294441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 6295bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6296bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6297bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6298bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6299441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6300441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6301441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 6302c0c050c5SMichael Chan __le32 queue_id6_max_bw; 6303441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6304441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 6305bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 6306bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 6307bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 6308bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 6309441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6310441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 6311bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6312bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6313bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6314bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6315441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6316441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6317441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 6318c0c050c5SMichael Chan u8 queue_id6_tsa_assign; 6319441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 6320441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 6321441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6322441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 6323c0c050c5SMichael Chan u8 queue_id6_pri_lvl; 6324c0c050c5SMichael Chan u8 queue_id6_bw_weight; 6325c0c050c5SMichael Chan u8 queue_id7; 6326c0c050c5SMichael Chan __le32 queue_id7_min_bw; 6327441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6328441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 6329bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 6330bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 6331bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 6332bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 6333441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6334441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 6335bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6336bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6337bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6338bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6339441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6340441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6341441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 6342c0c050c5SMichael Chan __le32 queue_id7_max_bw; 6343441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6344441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 6345bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 6346bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 6347bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 6348bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 6349441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6350441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 6351bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6352bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6353bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6354bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6355441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6356441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6357441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 6358c0c050c5SMichael Chan u8 queue_id7_tsa_assign; 6359441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 6360441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 6361441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6362441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 6363c0c050c5SMichael Chan u8 queue_id7_pri_lvl; 6364c0c050c5SMichael Chan u8 queue_id7_bw_weight; 6365c0c050c5SMichael Chan u8 unused_1[5]; 6366c0c050c5SMichael Chan }; 6367c0c050c5SMichael Chan 6368894aa69aSMichael Chan /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6369c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_output { 6370c0c050c5SMichael Chan __le16 error_code; 6371c0c050c5SMichael Chan __le16 req_type; 6372c0c050c5SMichael Chan __le16 seq_id; 6373c0c050c5SMichael Chan __le16 resp_len; 6374894aa69aSMichael Chan u8 unused_0[7]; 6375c0c050c5SMichael Chan u8 valid; 6376c0c050c5SMichael Chan }; 6377c0c050c5SMichael Chan 6378894aa69aSMichael Chan /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6379acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_input { 6380acb20054SMichael Chan __le16 req_type; 6381acb20054SMichael Chan __le16 cmpl_ring; 6382acb20054SMichael Chan __le16 seq_id; 6383acb20054SMichael Chan __le16 target_id; 6384acb20054SMichael Chan __le64 resp_addr; 6385acb20054SMichael Chan u8 port_id; 6386acb20054SMichael Chan u8 unused_0[7]; 6387acb20054SMichael Chan }; 6388acb20054SMichael Chan 6389894aa69aSMichael Chan /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6390acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_output { 6391acb20054SMichael Chan __le16 error_code; 6392acb20054SMichael Chan __le16 req_type; 6393acb20054SMichael Chan __le16 seq_id; 6394acb20054SMichael Chan __le16 resp_len; 6395acb20054SMichael Chan u8 num_dscp_bits; 6396acb20054SMichael Chan u8 unused_0; 6397acb20054SMichael Chan __le16 max_entries; 6398894aa69aSMichael Chan u8 unused_1[3]; 6399acb20054SMichael Chan u8 valid; 6400acb20054SMichael Chan }; 6401acb20054SMichael Chan 6402894aa69aSMichael Chan /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6403acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_input { 6404acb20054SMichael Chan __le16 req_type; 6405acb20054SMichael Chan __le16 cmpl_ring; 6406acb20054SMichael Chan __le16 seq_id; 6407acb20054SMichael Chan __le16 target_id; 6408acb20054SMichael Chan __le64 resp_addr; 6409acb20054SMichael Chan __le64 dest_data_addr; 6410acb20054SMichael Chan u8 port_id; 6411acb20054SMichael Chan u8 unused_0; 6412acb20054SMichael Chan __le16 dest_data_buffer_size; 6413894aa69aSMichael Chan u8 unused_1[4]; 6414acb20054SMichael Chan }; 6415acb20054SMichael Chan 6416894aa69aSMichael Chan /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6417acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_output { 6418acb20054SMichael Chan __le16 error_code; 6419acb20054SMichael Chan __le16 req_type; 6420acb20054SMichael Chan __le16 seq_id; 6421acb20054SMichael Chan __le16 resp_len; 6422acb20054SMichael Chan __le16 entry_cnt; 6423acb20054SMichael Chan u8 default_pri; 6424894aa69aSMichael Chan u8 unused_0[4]; 6425acb20054SMichael Chan u8 valid; 6426acb20054SMichael Chan }; 6427acb20054SMichael Chan 6428894aa69aSMichael Chan /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6429acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_input { 6430acb20054SMichael Chan __le16 req_type; 6431acb20054SMichael Chan __le16 cmpl_ring; 6432acb20054SMichael Chan __le16 seq_id; 6433acb20054SMichael Chan __le16 target_id; 6434acb20054SMichael Chan __le64 resp_addr; 6435acb20054SMichael Chan __le64 src_data_addr; 6436acb20054SMichael Chan __le32 flags; 6437acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6438acb20054SMichael Chan __le32 enables; 6439acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6440acb20054SMichael Chan u8 port_id; 6441acb20054SMichael Chan u8 default_pri; 6442acb20054SMichael Chan __le16 entry_cnt; 6443894aa69aSMichael Chan u8 unused_0[4]; 6444acb20054SMichael Chan }; 6445acb20054SMichael Chan 6446894aa69aSMichael Chan /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6447acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_output { 6448acb20054SMichael Chan __le16 error_code; 6449acb20054SMichael Chan __le16 req_type; 6450acb20054SMichael Chan __le16 seq_id; 6451acb20054SMichael Chan __le16 resp_len; 6452894aa69aSMichael Chan u8 unused_0[7]; 6453acb20054SMichael Chan u8 valid; 6454acb20054SMichael Chan }; 6455acb20054SMichael Chan 6456894aa69aSMichael Chan /* hwrm_vnic_alloc_input (size:192b/24B) */ 6457c0c050c5SMichael Chan struct hwrm_vnic_alloc_input { 6458c0c050c5SMichael Chan __le16 req_type; 6459c0c050c5SMichael Chan __le16 cmpl_ring; 6460c0c050c5SMichael Chan __le16 seq_id; 6461c0c050c5SMichael Chan __le16 target_id; 6462c0c050c5SMichael Chan __le64 resp_addr; 6463c0c050c5SMichael Chan __le32 flags; 6464c0c050c5SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 646516db6323SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 646616db6323SMichael Chan __le16 virtio_net_fid; 646716db6323SMichael Chan u8 unused_0[2]; 6468c0c050c5SMichael Chan }; 6469c0c050c5SMichael Chan 6470894aa69aSMichael Chan /* hwrm_vnic_alloc_output (size:128b/16B) */ 6471c0c050c5SMichael Chan struct hwrm_vnic_alloc_output { 6472c0c050c5SMichael Chan __le16 error_code; 6473c0c050c5SMichael Chan __le16 req_type; 6474c0c050c5SMichael Chan __le16 seq_id; 6475c0c050c5SMichael Chan __le16 resp_len; 6476c0c050c5SMichael Chan __le32 vnic_id; 6477894aa69aSMichael Chan u8 unused_0[3]; 6478c0c050c5SMichael Chan u8 valid; 6479c0c050c5SMichael Chan }; 6480c0c050c5SMichael Chan 6481894aa69aSMichael Chan /* hwrm_vnic_free_input (size:192b/24B) */ 6482c0c050c5SMichael Chan struct hwrm_vnic_free_input { 6483c0c050c5SMichael Chan __le16 req_type; 6484c0c050c5SMichael Chan __le16 cmpl_ring; 6485c0c050c5SMichael Chan __le16 seq_id; 6486c0c050c5SMichael Chan __le16 target_id; 6487c0c050c5SMichael Chan __le64 resp_addr; 6488c0c050c5SMichael Chan __le32 vnic_id; 6489894aa69aSMichael Chan u8 unused_0[4]; 6490c0c050c5SMichael Chan }; 6491c0c050c5SMichael Chan 6492894aa69aSMichael Chan /* hwrm_vnic_free_output (size:128b/16B) */ 6493c0c050c5SMichael Chan struct hwrm_vnic_free_output { 6494c0c050c5SMichael Chan __le16 error_code; 6495c0c050c5SMichael Chan __le16 req_type; 6496c0c050c5SMichael Chan __le16 seq_id; 6497c0c050c5SMichael Chan __le16 resp_len; 6498894aa69aSMichael Chan u8 unused_0[7]; 6499c0c050c5SMichael Chan u8 valid; 6500c0c050c5SMichael Chan }; 6501c0c050c5SMichael Chan 650272e0c9f9SMichael Chan /* hwrm_vnic_cfg_input (size:384b/48B) */ 6503c0c050c5SMichael Chan struct hwrm_vnic_cfg_input { 6504c0c050c5SMichael Chan __le16 req_type; 6505c0c050c5SMichael Chan __le16 cmpl_ring; 6506c0c050c5SMichael Chan __le16 seq_id; 6507c0c050c5SMichael Chan __le16 target_id; 6508c0c050c5SMichael Chan __le64 resp_addr; 6509c0c050c5SMichael Chan __le32 flags; 6510c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6511c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6512c193554eSMichael Chan #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 651311f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 651411f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6515441cabbbSMichael Chan #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 651657922b0aSMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6517c0c050c5SMichael Chan __le32 enables; 6518c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6519c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6520c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6521c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6522c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 65236fc92c33SMichael Chan #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 65246fc92c33SMichael Chan #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 652572e0c9f9SMichael Chan #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6526bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6527ad04cc05SMichael Chan #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6528c0c050c5SMichael Chan __le16 vnic_id; 6529c0c050c5SMichael Chan __le16 dflt_ring_grp; 6530c0c050c5SMichael Chan __le16 rss_rule; 6531c0c050c5SMichael Chan __le16 cos_rule; 6532c0c050c5SMichael Chan __le16 lb_rule; 6533c0c050c5SMichael Chan __le16 mru; 65346fc92c33SMichael Chan __le16 default_rx_ring_id; 65356fc92c33SMichael Chan __le16 default_cmpl_ring_id; 653672e0c9f9SMichael Chan __le16 queue_id; 6537bfc6e5fbSMichael Chan u8 rx_csum_v2_mode; 6538bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6539bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6540bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6541bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6542ad04cc05SMichael Chan u8 l2_cqe_mode; 6543ad04cc05SMichael Chan #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6544ad04cc05SMichael Chan #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6545ad04cc05SMichael Chan #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6546ad04cc05SMichael Chan #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6547ad04cc05SMichael Chan u8 unused0[4]; 6548c0c050c5SMichael Chan }; 6549c0c050c5SMichael Chan 6550894aa69aSMichael Chan /* hwrm_vnic_cfg_output (size:128b/16B) */ 6551c0c050c5SMichael Chan struct hwrm_vnic_cfg_output { 6552c0c050c5SMichael Chan __le16 error_code; 6553c0c050c5SMichael Chan __le16 req_type; 6554c0c050c5SMichael Chan __le16 seq_id; 6555c0c050c5SMichael Chan __le16 resp_len; 6556894aa69aSMichael Chan u8 unused_0[7]; 6557c0c050c5SMichael Chan u8 valid; 6558c0c050c5SMichael Chan }; 6559c0c050c5SMichael Chan 6560894aa69aSMichael Chan /* hwrm_vnic_qcaps_input (size:192b/24B) */ 65618fdefd63SMichael Chan struct hwrm_vnic_qcaps_input { 65628fdefd63SMichael Chan __le16 req_type; 65638fdefd63SMichael Chan __le16 cmpl_ring; 65648fdefd63SMichael Chan __le16 seq_id; 65658fdefd63SMichael Chan __le16 target_id; 65668fdefd63SMichael Chan __le64 resp_addr; 65678fdefd63SMichael Chan __le32 enables; 6568894aa69aSMichael Chan u8 unused_0[4]; 65698fdefd63SMichael Chan }; 65708fdefd63SMichael Chan 6571894aa69aSMichael Chan /* hwrm_vnic_qcaps_output (size:192b/24B) */ 65728fdefd63SMichael Chan struct hwrm_vnic_qcaps_output { 65738fdefd63SMichael Chan __le16 error_code; 65748fdefd63SMichael Chan __le16 req_type; 65758fdefd63SMichael Chan __le16 seq_id; 65768fdefd63SMichael Chan __le16 resp_len; 65778fdefd63SMichael Chan __le16 mru; 6578894aa69aSMichael Chan u8 unused_0[2]; 65798fdefd63SMichael Chan __le32 flags; 6580bac9a7e0SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 65818fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 65828fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 65838fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 65848fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 65858fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6586894aa69aSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 65876fc92c33SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 658872e0c9f9SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6589bfc6e5fbSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 659016db6323SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 659116db6323SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 659231f67c2eSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 659378eeadb8SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 659421e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6595ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6596ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6597ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 659821e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6599ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6600ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 6601ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 6602ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 6603ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 6604ad04cc05SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 660584a911dbSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 66064a50ddc2SMichael Chan __le16 max_aggs_supported; 66074a50ddc2SMichael Chan u8 unused_1[5]; 66088fdefd63SMichael Chan u8 valid; 66098fdefd63SMichael Chan }; 66108fdefd63SMichael Chan 6611894aa69aSMichael Chan /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6612c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_input { 6613c0c050c5SMichael Chan __le16 req_type; 6614c0c050c5SMichael Chan __le16 cmpl_ring; 6615c0c050c5SMichael Chan __le16 seq_id; 6616c0c050c5SMichael Chan __le16 target_id; 6617c0c050c5SMichael Chan __le64 resp_addr; 6618c0c050c5SMichael Chan __le32 flags; 6619c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6620c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6621c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6622c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6623c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6624c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6625c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6626c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 66274a50ddc2SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6628c0c050c5SMichael Chan __le32 enables; 6629c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6630c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6631c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6632c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6633c0c050c5SMichael Chan __le16 vnic_id; 6634c0c050c5SMichael Chan __le16 max_agg_segs; 6635441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6636441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6637441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6638441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6639441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6640894aa69aSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6641c0c050c5SMichael Chan __le16 max_aggs; 6642441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6643441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6644441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6645441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6646441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6647441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6648894aa69aSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6649894aa69aSMichael Chan u8 unused_0[2]; 6650c0c050c5SMichael Chan __le32 max_agg_timer; 6651c0c050c5SMichael Chan __le32 min_agg_len; 6652c0c050c5SMichael Chan }; 6653c0c050c5SMichael Chan 6654894aa69aSMichael Chan /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6655c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_output { 6656c0c050c5SMichael Chan __le16 error_code; 6657c0c050c5SMichael Chan __le16 req_type; 6658c0c050c5SMichael Chan __le16 seq_id; 6659c0c050c5SMichael Chan __le16 resp_len; 6660894aa69aSMichael Chan u8 unused_0[7]; 6661c0c050c5SMichael Chan u8 valid; 6662c0c050c5SMichael Chan }; 6663c0c050c5SMichael Chan 6664894aa69aSMichael Chan /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6665894aa69aSMichael Chan struct hwrm_vnic_tpa_qcfg_input { 6666894aa69aSMichael Chan __le16 req_type; 6667894aa69aSMichael Chan __le16 cmpl_ring; 6668894aa69aSMichael Chan __le16 seq_id; 6669894aa69aSMichael Chan __le16 target_id; 6670894aa69aSMichael Chan __le64 resp_addr; 6671894aa69aSMichael Chan __le16 vnic_id; 6672894aa69aSMichael Chan u8 unused_0[6]; 6673894aa69aSMichael Chan }; 6674894aa69aSMichael Chan 6675894aa69aSMichael Chan /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6676894aa69aSMichael Chan struct hwrm_vnic_tpa_qcfg_output { 6677894aa69aSMichael Chan __le16 error_code; 6678894aa69aSMichael Chan __le16 req_type; 6679894aa69aSMichael Chan __le16 seq_id; 6680894aa69aSMichael Chan __le16 resp_len; 6681894aa69aSMichael Chan __le32 flags; 6682894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6683894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6684894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6685894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6686894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6687894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6688894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6689894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6690894aa69aSMichael Chan __le16 max_agg_segs; 6691894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6692894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6693894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6694894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6695894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6696894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6697894aa69aSMichael Chan __le16 max_aggs; 6698894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6699894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6700894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6701894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6702894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6703894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6704894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6705894aa69aSMichael Chan __le32 max_agg_timer; 6706894aa69aSMichael Chan __le32 min_agg_len; 6707894aa69aSMichael Chan u8 unused_0[7]; 6708894aa69aSMichael Chan u8 valid; 6709894aa69aSMichael Chan }; 6710894aa69aSMichael Chan 6711894aa69aSMichael Chan /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6712c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_input { 6713c0c050c5SMichael Chan __le16 req_type; 6714c0c050c5SMichael Chan __le16 cmpl_ring; 6715c0c050c5SMichael Chan __le16 seq_id; 6716c0c050c5SMichael Chan __le16 target_id; 6717c0c050c5SMichael Chan __le64 resp_addr; 6718c0c050c5SMichael Chan __le32 hash_type; 6719c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6720c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6721c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6722c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6723c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6724c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 67252895c153SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 6726ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 6727ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 6728ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 6729ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 67306fc92c33SMichael Chan __le16 vnic_id; 67316fc92c33SMichael Chan u8 ring_table_pair_index; 67326fc92c33SMichael Chan u8 hash_mode_flags; 67336fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 67346fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 67356fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 67366fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 67376fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6738c0c050c5SMichael Chan __le64 ring_grp_tbl_addr; 6739c0c050c5SMichael Chan __le64 hash_key_tbl_addr; 6740c0c050c5SMichael Chan __le16 rss_ctx_idx; 674121e70778SMichael Chan u8 flags; 674221e70778SMichael Chan #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 674321e70778SMichael Chan #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6744ad04cc05SMichael Chan u8 ring_select_mode; 6745ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 6746ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 6747ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 6748ad04cc05SMichael Chan #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 674921e70778SMichael Chan u8 unused_1[4]; 6750c0c050c5SMichael Chan }; 6751c0c050c5SMichael Chan 6752894aa69aSMichael Chan /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6753c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_output { 6754c0c050c5SMichael Chan __le16 error_code; 6755c0c050c5SMichael Chan __le16 req_type; 6756c0c050c5SMichael Chan __le16 seq_id; 6757c0c050c5SMichael Chan __le16 resp_len; 6758894aa69aSMichael Chan u8 unused_0[7]; 6759c0c050c5SMichael Chan u8 valid; 6760c0c050c5SMichael Chan }; 6761c0c050c5SMichael Chan 676241136ab3SMichael Chan /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 676341136ab3SMichael Chan struct hwrm_vnic_rss_cfg_cmd_err { 676441136ab3SMichael Chan u8 code; 676541136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 676641136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 676741136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 676841136ab3SMichael Chan u8 unused_0[7]; 676941136ab3SMichael Chan }; 677041136ab3SMichael Chan 677198a4322bSEdwin Peer /* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 677298a4322bSEdwin Peer struct hwrm_vnic_rss_qcfg_input { 677398a4322bSEdwin Peer __le16 req_type; 677498a4322bSEdwin Peer __le16 cmpl_ring; 677598a4322bSEdwin Peer __le16 seq_id; 677698a4322bSEdwin Peer __le16 target_id; 677798a4322bSEdwin Peer __le64 resp_addr; 677898a4322bSEdwin Peer __le16 rss_ctx_idx; 677998a4322bSEdwin Peer __le16 vnic_id; 678098a4322bSEdwin Peer u8 unused_0[4]; 678198a4322bSEdwin Peer }; 678298a4322bSEdwin Peer 678398a4322bSEdwin Peer /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 678498a4322bSEdwin Peer struct hwrm_vnic_rss_qcfg_output { 678598a4322bSEdwin Peer __le16 error_code; 678698a4322bSEdwin Peer __le16 req_type; 678798a4322bSEdwin Peer __le16 seq_id; 678898a4322bSEdwin Peer __le16 resp_len; 678998a4322bSEdwin Peer __le32 hash_type; 679098a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 679198a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 679298a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 679398a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 679498a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 679598a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 679698a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 679798a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 679898a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 679998a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 680098a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 680198a4322bSEdwin Peer u8 unused_0[4]; 680298a4322bSEdwin Peer __le32 hash_key[10]; 680398a4322bSEdwin Peer u8 hash_mode_flags; 680498a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 680598a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 680698a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 680798a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 680898a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 680998a4322bSEdwin Peer u8 ring_select_mode; 681098a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 681198a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 681298a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 681398a4322bSEdwin Peer #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 681498a4322bSEdwin Peer u8 unused_1[5]; 681598a4322bSEdwin Peer u8 valid; 681698a4322bSEdwin Peer }; 681798a4322bSEdwin Peer 6818894aa69aSMichael Chan /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6819c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_input { 6820c0c050c5SMichael Chan __le16 req_type; 6821c0c050c5SMichael Chan __le16 cmpl_ring; 6822c0c050c5SMichael Chan __le16 seq_id; 6823c0c050c5SMichael Chan __le16 target_id; 6824c0c050c5SMichael Chan __le64 resp_addr; 6825c0c050c5SMichael Chan __le32 flags; 6826c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6827c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6828c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6829c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6830c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6831c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6832bfc6e5fbSMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6833c0c050c5SMichael Chan __le32 enables; 6834c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6835c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6836c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6837bfc6e5fbSMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6838c0c050c5SMichael Chan __le32 vnic_id; 6839c0c050c5SMichael Chan __le16 jumbo_thresh; 6840c0c050c5SMichael Chan __le16 hds_offset; 6841c0c050c5SMichael Chan __le16 hds_threshold; 6842bfc6e5fbSMichael Chan __le16 max_bds; 6843bfc6e5fbSMichael Chan u8 unused_0[4]; 6844c0c050c5SMichael Chan }; 6845c0c050c5SMichael Chan 6846894aa69aSMichael Chan /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6847c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_output { 6848c0c050c5SMichael Chan __le16 error_code; 6849c0c050c5SMichael Chan __le16 req_type; 6850c0c050c5SMichael Chan __le16 seq_id; 6851c0c050c5SMichael Chan __le16 resp_len; 6852894aa69aSMichael Chan u8 unused_0[7]; 6853c0c050c5SMichael Chan u8 valid; 6854c0c050c5SMichael Chan }; 6855c0c050c5SMichael Chan 6856894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6857c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6858c0c050c5SMichael Chan __le16 req_type; 6859c0c050c5SMichael Chan __le16 cmpl_ring; 6860c0c050c5SMichael Chan __le16 seq_id; 6861c0c050c5SMichael Chan __le16 target_id; 6862c0c050c5SMichael Chan __le64 resp_addr; 6863c0c050c5SMichael Chan }; 6864c0c050c5SMichael Chan 6865894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6866c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6867c0c050c5SMichael Chan __le16 error_code; 6868c0c050c5SMichael Chan __le16 req_type; 6869c0c050c5SMichael Chan __le16 seq_id; 6870c0c050c5SMichael Chan __le16 resp_len; 6871c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 6872894aa69aSMichael Chan u8 unused_0[5]; 6873c0c050c5SMichael Chan u8 valid; 6874c0c050c5SMichael Chan }; 6875c0c050c5SMichael Chan 6876894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6877c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6878c0c050c5SMichael Chan __le16 req_type; 6879c0c050c5SMichael Chan __le16 cmpl_ring; 6880c0c050c5SMichael Chan __le16 seq_id; 6881c0c050c5SMichael Chan __le16 target_id; 6882c0c050c5SMichael Chan __le64 resp_addr; 6883c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 6884894aa69aSMichael Chan u8 unused_0[6]; 6885c0c050c5SMichael Chan }; 6886c0c050c5SMichael Chan 6887894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6888c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6889c0c050c5SMichael Chan __le16 error_code; 6890c0c050c5SMichael Chan __le16 req_type; 6891c0c050c5SMichael Chan __le16 seq_id; 6892c0c050c5SMichael Chan __le16 resp_len; 6893894aa69aSMichael Chan u8 unused_0[7]; 6894c0c050c5SMichael Chan u8 valid; 6895c0c050c5SMichael Chan }; 6896c0c050c5SMichael Chan 68976fc92c33SMichael Chan /* hwrm_ring_alloc_input (size:704b/88B) */ 6898c0c050c5SMichael Chan struct hwrm_ring_alloc_input { 6899c0c050c5SMichael Chan __le16 req_type; 6900c0c050c5SMichael Chan __le16 cmpl_ring; 6901c0c050c5SMichael Chan __le16 seq_id; 6902c0c050c5SMichael Chan __le16 target_id; 6903c0c050c5SMichael Chan __le64 resp_addr; 6904c0c050c5SMichael Chan __le32 enables; 6905441cabbbSMichael Chan #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6906c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6907c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 69086fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 69096fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 69106fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6911bfc6e5fbSMichael Chan #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 69129d6b648cSMichael Chan #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6913c0c050c5SMichael Chan u8 ring_type; 6914bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6915441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6916441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6917bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 69186fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 69196fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 69206fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 692121e70778SMichael Chan u8 cmpl_coal_cnt; 692221e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 692321e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 692421e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 692521e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 692621e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 692721e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 692821e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 692921e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 693021e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 693121e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 693221e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 693321e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 693421e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 693521e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 693621e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 693721e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 693821e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 693931d357c0SMichael Chan __le16 flags; 694031d357c0SMichael Chan #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6941ad04cc05SMichael Chan #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 6942ad04cc05SMichael Chan #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 694384a911dbSMichael Chan #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 6944c0c050c5SMichael Chan __le64 page_tbl_addr; 6945c0c050c5SMichael Chan __le32 fbo; 6946c0c050c5SMichael Chan u8 page_size; 6947c0c050c5SMichael Chan u8 page_tbl_depth; 6948bfc6e5fbSMichael Chan __le16 schq_id; 6949c0c050c5SMichael Chan __le32 length; 6950c0c050c5SMichael Chan __le16 logical_id; 6951c0c050c5SMichael Chan __le16 cmpl_ring_id; 6952c0c050c5SMichael Chan __le16 queue_id; 69536fc92c33SMichael Chan __le16 rx_buf_size; 69546fc92c33SMichael Chan __le16 rx_ring_id; 69556fc92c33SMichael Chan __le16 nq_ring_id; 6956441cabbbSMichael Chan __le16 ring_arb_cfg; 6957441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6958441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6959894aa69aSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6960894aa69aSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6961441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6962441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6963441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6964441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6965441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6966894aa69aSMichael Chan __le16 unused_3; 6967c193554eSMichael Chan __le32 reserved3; 6968c0c050c5SMichael Chan __le32 stat_ctx_id; 6969c193554eSMichael Chan __le32 reserved4; 6970c0c050c5SMichael Chan __le32 max_bw; 6971441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6972441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6973bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6974bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6975bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6976bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6977441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6978441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6979bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6980bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6981bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6982bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6983441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6984441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6985441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6986c0c050c5SMichael Chan u8 int_mode; 6987441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6988441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6989441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6990441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6991894aa69aSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 69929d6b648cSMichael Chan u8 mpc_chnls_type; 69939d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 69949d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 69959d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 69969d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 69979d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 69989d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 69999d6b648cSMichael Chan u8 unused_4[2]; 70006fc92c33SMichael Chan __le64 cq_handle; 7001c0c050c5SMichael Chan }; 7002c0c050c5SMichael Chan 7003894aa69aSMichael Chan /* hwrm_ring_alloc_output (size:128b/16B) */ 7004c0c050c5SMichael Chan struct hwrm_ring_alloc_output { 7005c0c050c5SMichael Chan __le16 error_code; 7006c0c050c5SMichael Chan __le16 req_type; 7007c0c050c5SMichael Chan __le16 seq_id; 7008c0c050c5SMichael Chan __le16 resp_len; 7009c0c050c5SMichael Chan __le16 ring_id; 7010c0c050c5SMichael Chan __le16 logical_ring_id; 701116db6323SMichael Chan u8 push_buffer_index; 701216db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 701316db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 701416db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 701516db6323SMichael Chan u8 unused_0[2]; 7016c0c050c5SMichael Chan u8 valid; 7017c0c050c5SMichael Chan }; 7018c0c050c5SMichael Chan 701931f67c2eSMichael Chan /* hwrm_ring_free_input (size:256b/32B) */ 7020c0c050c5SMichael Chan struct hwrm_ring_free_input { 7021c0c050c5SMichael Chan __le16 req_type; 7022c0c050c5SMichael Chan __le16 cmpl_ring; 7023c0c050c5SMichael Chan __le16 seq_id; 7024c0c050c5SMichael Chan __le16 target_id; 7025c0c050c5SMichael Chan __le64 resp_addr; 7026c0c050c5SMichael Chan u8 ring_type; 7027bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7028441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7029441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7030bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 70316fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 70326fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 70336fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 703431f67c2eSMichael Chan u8 flags; 703531f67c2eSMichael Chan #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 703631f67c2eSMichael Chan #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7037c0c050c5SMichael Chan __le16 ring_id; 703831f67c2eSMichael Chan __le32 prod_idx; 703931f67c2eSMichael Chan __le32 opaque; 704031f67c2eSMichael Chan __le32 unused_1; 7041c0c050c5SMichael Chan }; 7042c0c050c5SMichael Chan 7043894aa69aSMichael Chan /* hwrm_ring_free_output (size:128b/16B) */ 7044c0c050c5SMichael Chan struct hwrm_ring_free_output { 7045c0c050c5SMichael Chan __le16 error_code; 7046c0c050c5SMichael Chan __le16 req_type; 7047c0c050c5SMichael Chan __le16 seq_id; 7048c0c050c5SMichael Chan __le16 resp_len; 7049894aa69aSMichael Chan u8 unused_0[7]; 7050c0c050c5SMichael Chan u8 valid; 7051c0c050c5SMichael Chan }; 7052c0c050c5SMichael Chan 70533293ec23SMichael Chan /* hwrm_ring_reset_input (size:192b/24B) */ 70543293ec23SMichael Chan struct hwrm_ring_reset_input { 70553293ec23SMichael Chan __le16 req_type; 70563293ec23SMichael Chan __le16 cmpl_ring; 70573293ec23SMichael Chan __le16 seq_id; 70583293ec23SMichael Chan __le16 target_id; 70593293ec23SMichael Chan __le64 resp_addr; 70603293ec23SMichael Chan u8 ring_type; 70613293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 70623293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 70633293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 70643293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7065bfc6e5fbSMichael Chan #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7066bfc6e5fbSMichael Chan #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 70673293ec23SMichael Chan u8 unused_0; 70683293ec23SMichael Chan __le16 ring_id; 70693293ec23SMichael Chan u8 unused_1[4]; 70703293ec23SMichael Chan }; 70713293ec23SMichael Chan 70723293ec23SMichael Chan /* hwrm_ring_reset_output (size:128b/16B) */ 70733293ec23SMichael Chan struct hwrm_ring_reset_output { 70743293ec23SMichael Chan __le16 error_code; 70753293ec23SMichael Chan __le16 req_type; 70763293ec23SMichael Chan __le16 seq_id; 70773293ec23SMichael Chan __le16 resp_len; 707816db6323SMichael Chan u8 push_buffer_index; 707916db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 708016db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 708116db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 708216db6323SMichael Chan u8 unused_0[3]; 70833293ec23SMichael Chan u8 consumer_idx[3]; 70843293ec23SMichael Chan u8 valid; 70853293ec23SMichael Chan }; 70863293ec23SMichael Chan 70876fc92c33SMichael Chan /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 70886fc92c33SMichael Chan struct hwrm_ring_aggint_qcaps_input { 70896fc92c33SMichael Chan __le16 req_type; 70906fc92c33SMichael Chan __le16 cmpl_ring; 70916fc92c33SMichael Chan __le16 seq_id; 70926fc92c33SMichael Chan __le16 target_id; 70936fc92c33SMichael Chan __le64 resp_addr; 70946fc92c33SMichael Chan }; 70956fc92c33SMichael Chan 70966fc92c33SMichael Chan /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 70976fc92c33SMichael Chan struct hwrm_ring_aggint_qcaps_output { 70986fc92c33SMichael Chan __le16 error_code; 70996fc92c33SMichael Chan __le16 req_type; 71006fc92c33SMichael Chan __le16 seq_id; 71016fc92c33SMichael Chan __le16 resp_len; 71026fc92c33SMichael Chan __le32 cmpl_params; 71036fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 71046fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 71056fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 71066fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 71076fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 71086fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 71096fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 71106fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 71116fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 71126fc92c33SMichael Chan __le32 nq_params; 71136fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 71146fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_min; 71156fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_max; 71166fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_during_int_min; 71176fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_during_int_max; 71186fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_min; 71196fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_max; 71206fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int_min; 71216fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int_max; 71226fc92c33SMichael Chan __le16 int_lat_tmr_min_min; 71236fc92c33SMichael Chan __le16 int_lat_tmr_min_max; 71246fc92c33SMichael Chan __le16 int_lat_tmr_max_min; 71256fc92c33SMichael Chan __le16 int_lat_tmr_max_max; 71266fc92c33SMichael Chan __le16 num_cmpl_aggr_int_min; 71276fc92c33SMichael Chan __le16 num_cmpl_aggr_int_max; 71286fc92c33SMichael Chan __le16 timer_units; 71296fc92c33SMichael Chan u8 unused_0[1]; 71306fc92c33SMichael Chan u8 valid; 71316fc92c33SMichael Chan }; 71326fc92c33SMichael Chan 7133894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7134c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_input { 7135c0c050c5SMichael Chan __le16 req_type; 7136c0c050c5SMichael Chan __le16 cmpl_ring; 7137c0c050c5SMichael Chan __le16 seq_id; 7138c0c050c5SMichael Chan __le16 target_id; 7139c0c050c5SMichael Chan __le64 resp_addr; 7140c0c050c5SMichael Chan __le16 ring_id; 7141460c2577SMichael Chan __le16 flags; 7142460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7143460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7144460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7145460c2577SMichael Chan u8 unused_0[4]; 7146c0c050c5SMichael Chan }; 7147c0c050c5SMichael Chan 7148894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7149c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_output { 7150c0c050c5SMichael Chan __le16 error_code; 7151c0c050c5SMichael Chan __le16 req_type; 7152c0c050c5SMichael Chan __le16 seq_id; 7153c0c050c5SMichael Chan __le16 resp_len; 7154c0c050c5SMichael Chan __le16 flags; 7155c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7156c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7157c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 7158c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 7159c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 7160c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 7161c0c050c5SMichael Chan __le16 int_lat_tmr_min; 7162c0c050c5SMichael Chan __le16 int_lat_tmr_max; 7163c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 7164894aa69aSMichael Chan u8 unused_0[7]; 7165c0c050c5SMichael Chan u8 valid; 7166c0c050c5SMichael Chan }; 7167c0c050c5SMichael Chan 7168894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7169c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7170c0c050c5SMichael Chan __le16 req_type; 7171c0c050c5SMichael Chan __le16 cmpl_ring; 7172c0c050c5SMichael Chan __le16 seq_id; 7173c0c050c5SMichael Chan __le16 target_id; 7174c0c050c5SMichael Chan __le64 resp_addr; 7175c0c050c5SMichael Chan __le16 ring_id; 7176c0c050c5SMichael Chan __le16 flags; 7177c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7178c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 71796fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7180c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 7181c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 7182c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 7183c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 7184c0c050c5SMichael Chan __le16 int_lat_tmr_min; 7185c0c050c5SMichael Chan __le16 int_lat_tmr_max; 7186c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 71876fc92c33SMichael Chan __le16 enables; 71886fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 71896fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 71906fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 71916fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 71926fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 71936fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 71946fc92c33SMichael Chan u8 unused_0[4]; 7195c0c050c5SMichael Chan }; 7196c0c050c5SMichael Chan 7197894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7198c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7199c0c050c5SMichael Chan __le16 error_code; 7200c0c050c5SMichael Chan __le16 req_type; 7201c0c050c5SMichael Chan __le16 seq_id; 7202c0c050c5SMichael Chan __le16 resp_len; 7203894aa69aSMichael Chan u8 unused_0[7]; 7204c0c050c5SMichael Chan u8 valid; 7205c0c050c5SMichael Chan }; 7206c0c050c5SMichael Chan 7207894aa69aSMichael Chan /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7208c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_input { 7209c0c050c5SMichael Chan __le16 req_type; 7210c0c050c5SMichael Chan __le16 cmpl_ring; 7211c0c050c5SMichael Chan __le16 seq_id; 7212c0c050c5SMichael Chan __le16 target_id; 7213c0c050c5SMichael Chan __le64 resp_addr; 7214c0c050c5SMichael Chan __le16 cr; 7215c0c050c5SMichael Chan __le16 rr; 7216c0c050c5SMichael Chan __le16 ar; 7217c0c050c5SMichael Chan __le16 sc; 7218c0c050c5SMichael Chan }; 7219c0c050c5SMichael Chan 7220894aa69aSMichael Chan /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7221c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_output { 7222c0c050c5SMichael Chan __le16 error_code; 7223c0c050c5SMichael Chan __le16 req_type; 7224c0c050c5SMichael Chan __le16 seq_id; 7225c0c050c5SMichael Chan __le16 resp_len; 7226c0c050c5SMichael Chan __le32 ring_group_id; 7227894aa69aSMichael Chan u8 unused_0[3]; 7228c0c050c5SMichael Chan u8 valid; 7229c0c050c5SMichael Chan }; 7230c0c050c5SMichael Chan 7231894aa69aSMichael Chan /* hwrm_ring_grp_free_input (size:192b/24B) */ 7232c0c050c5SMichael Chan struct hwrm_ring_grp_free_input { 7233c0c050c5SMichael Chan __le16 req_type; 7234c0c050c5SMichael Chan __le16 cmpl_ring; 7235c0c050c5SMichael Chan __le16 seq_id; 7236c0c050c5SMichael Chan __le16 target_id; 7237c0c050c5SMichael Chan __le64 resp_addr; 7238c0c050c5SMichael Chan __le32 ring_group_id; 7239894aa69aSMichael Chan u8 unused_0[4]; 7240c0c050c5SMichael Chan }; 7241c0c050c5SMichael Chan 7242894aa69aSMichael Chan /* hwrm_ring_grp_free_output (size:128b/16B) */ 7243c0c050c5SMichael Chan struct hwrm_ring_grp_free_output { 7244c0c050c5SMichael Chan __le16 error_code; 7245c0c050c5SMichael Chan __le16 req_type; 7246c0c050c5SMichael Chan __le16 seq_id; 7247c0c050c5SMichael Chan __le16 resp_len; 7248894aa69aSMichael Chan u8 unused_0[7]; 7249c0c050c5SMichael Chan u8 valid; 7250c0c050c5SMichael Chan }; 7251bfc6e5fbSMichael Chan 72523322479eSMichael Chan #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 72533322479eSMichael Chan #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 72543322479eSMichael Chan #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 72553322479eSMichael Chan #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7256c0c050c5SMichael Chan 7257894aa69aSMichael Chan /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7258c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_input { 7259c0c050c5SMichael Chan __le16 req_type; 7260c0c050c5SMichael Chan __le16 cmpl_ring; 7261c0c050c5SMichael Chan __le16 seq_id; 7262c0c050c5SMichael Chan __le16 target_id; 7263c0c050c5SMichael Chan __le64 resp_addr; 7264c0c050c5SMichael Chan __le32 flags; 7265c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7266894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7267894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 726811f15ed3SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7269c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7270c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7271c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 727231d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 727331d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 727431d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 727531d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 727631d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 727731d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 72784a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 72794a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7280c0c050c5SMichael Chan __le32 enables; 7281c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7282c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7283c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7284c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7285c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7286c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7287c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7288c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7289c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7290c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7291c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7292c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7293c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7294c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7295c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7296c193554eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7297c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 72984a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 72994a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7300c0c050c5SMichael Chan u8 l2_addr[6]; 73014a50ddc2SMichael Chan u8 num_vlans; 73024a50ddc2SMichael Chan u8 t_num_vlans; 7303c0c050c5SMichael Chan u8 l2_addr_mask[6]; 7304c0c050c5SMichael Chan __le16 l2_ovlan; 7305c0c050c5SMichael Chan __le16 l2_ovlan_mask; 7306c0c050c5SMichael Chan __le16 l2_ivlan; 7307c0c050c5SMichael Chan __le16 l2_ivlan_mask; 7308894aa69aSMichael Chan u8 unused_1[2]; 7309c0c050c5SMichael Chan u8 t_l2_addr[6]; 7310894aa69aSMichael Chan u8 unused_2[2]; 7311c0c050c5SMichael Chan u8 t_l2_addr_mask[6]; 7312c0c050c5SMichael Chan __le16 t_l2_ovlan; 7313c0c050c5SMichael Chan __le16 t_l2_ovlan_mask; 7314c0c050c5SMichael Chan __le16 t_l2_ivlan; 7315c0c050c5SMichael Chan __le16 t_l2_ivlan_mask; 7316c0c050c5SMichael Chan u8 src_type; 7317441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7318441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7319441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7320441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7321441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7322441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7323441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7324441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7325894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7326894aa69aSMichael Chan u8 unused_3; 7327c0c050c5SMichael Chan __le32 src_id; 7328c0c050c5SMichael Chan u8 tunnel_type; 7329441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7330441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7331441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7332441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7333441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7334441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7335441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7336441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7337441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 733857922b0aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 733931d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 734031d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 73413322479eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7342441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7343894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7344894aa69aSMichael Chan u8 unused_4; 7345c193554eSMichael Chan __le16 dst_id; 7346c0c050c5SMichael Chan __le16 mirror_vnic_id; 7347c0c050c5SMichael Chan u8 pri_hint; 7348441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7349441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7350441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7351441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7352441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7353894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7354894aa69aSMichael Chan u8 unused_5; 7355894aa69aSMichael Chan __le32 unused_6; 7356c0c050c5SMichael Chan __le64 l2_filter_id_hint; 7357c0c050c5SMichael Chan }; 7358c0c050c5SMichael Chan 7359894aa69aSMichael Chan /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7360c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_output { 7361c0c050c5SMichael Chan __le16 error_code; 7362c0c050c5SMichael Chan __le16 req_type; 7363c0c050c5SMichael Chan __le16 seq_id; 7364c0c050c5SMichael Chan __le16 resp_len; 7365c0c050c5SMichael Chan __le64 l2_filter_id; 7366c0c050c5SMichael Chan __le32 flow_id; 73674a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 73684a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 73694a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 73704a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 73714a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 73724a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 73734a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 73744a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 73754a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 73764a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7377894aa69aSMichael Chan u8 unused_0[3]; 7378c0c050c5SMichael Chan u8 valid; 7379c0c050c5SMichael Chan }; 7380c0c050c5SMichael Chan 7381894aa69aSMichael Chan /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7382c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_input { 7383c0c050c5SMichael Chan __le16 req_type; 7384c0c050c5SMichael Chan __le16 cmpl_ring; 7385c0c050c5SMichael Chan __le16 seq_id; 7386c0c050c5SMichael Chan __le16 target_id; 7387c0c050c5SMichael Chan __le64 resp_addr; 7388c0c050c5SMichael Chan __le64 l2_filter_id; 7389c0c050c5SMichael Chan }; 7390c0c050c5SMichael Chan 7391894aa69aSMichael Chan /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7392c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_output { 7393c0c050c5SMichael Chan __le16 error_code; 7394c0c050c5SMichael Chan __le16 req_type; 7395c0c050c5SMichael Chan __le16 seq_id; 7396c0c050c5SMichael Chan __le16 resp_len; 7397894aa69aSMichael Chan u8 unused_0[7]; 7398c0c050c5SMichael Chan u8 valid; 7399c0c050c5SMichael Chan }; 7400c0c050c5SMichael Chan 7401894aa69aSMichael Chan /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 7402c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_input { 7403c0c050c5SMichael Chan __le16 req_type; 7404c0c050c5SMichael Chan __le16 cmpl_ring; 7405c0c050c5SMichael Chan __le16 seq_id; 7406c0c050c5SMichael Chan __le16 target_id; 7407c0c050c5SMichael Chan __le64 resp_addr; 7408c0c050c5SMichael Chan __le32 flags; 7409c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7410894aa69aSMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7411894aa69aSMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 741211f15ed3SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7413c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 741431d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 741531d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 741631d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 741731d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 741831d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 741931d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7420c0c050c5SMichael Chan __le32 enables; 7421c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7422c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7423c0c050c5SMichael Chan __le64 l2_filter_id; 7424c193554eSMichael Chan __le32 dst_id; 7425c193554eSMichael Chan __le32 new_mirror_vnic_id; 7426c0c050c5SMichael Chan }; 7427c0c050c5SMichael Chan 7428894aa69aSMichael Chan /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7429c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_output { 7430c0c050c5SMichael Chan __le16 error_code; 7431c0c050c5SMichael Chan __le16 req_type; 7432c0c050c5SMichael Chan __le16 seq_id; 7433c0c050c5SMichael Chan __le16 resp_len; 7434894aa69aSMichael Chan u8 unused_0[7]; 7435c0c050c5SMichael Chan u8 valid; 7436c0c050c5SMichael Chan }; 7437c0c050c5SMichael Chan 7438894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7439c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_input { 7440c0c050c5SMichael Chan __le16 req_type; 7441c0c050c5SMichael Chan __le16 cmpl_ring; 7442c0c050c5SMichael Chan __le16 seq_id; 7443c0c050c5SMichael Chan __le16 target_id; 7444c0c050c5SMichael Chan __le64 resp_addr; 7445c193554eSMichael Chan __le32 vnic_id; 7446c0c050c5SMichael Chan __le32 mask; 7447c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7448c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7449c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7450c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7451c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7452a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7453a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7454a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7455c0c050c5SMichael Chan __le64 mc_tbl_addr; 7456c0c050c5SMichael Chan __le32 num_mc_entries; 7457894aa69aSMichael Chan u8 unused_0[4]; 7458a58a3e68SMichael Chan __le64 vlan_tag_tbl_addr; 7459a58a3e68SMichael Chan __le32 num_vlan_tags; 7460894aa69aSMichael Chan u8 unused_1[4]; 7461c0c050c5SMichael Chan }; 7462c0c050c5SMichael Chan 7463894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7464c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_output { 7465c0c050c5SMichael Chan __le16 error_code; 7466c0c050c5SMichael Chan __le16 req_type; 7467c0c050c5SMichael Chan __le16 seq_id; 7468c0c050c5SMichael Chan __le16 resp_len; 7469894aa69aSMichael Chan u8 unused_0[7]; 7470c0c050c5SMichael Chan u8 valid; 7471c0c050c5SMichael Chan }; 7472c0c050c5SMichael Chan 7473894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 747457922b0aSMichael Chan struct hwrm_cfa_l2_set_rx_mask_cmd_err { 747557922b0aSMichael Chan u8 code; 747657922b0aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 747757922b0aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7478894aa69aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 747957922b0aSMichael Chan u8 unused_0[7]; 748057922b0aSMichael Chan }; 748157922b0aSMichael Chan 7482894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7483c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_input { 7484c0c050c5SMichael Chan __le16 req_type; 7485c0c050c5SMichael Chan __le16 cmpl_ring; 7486c0c050c5SMichael Chan __le16 seq_id; 7487c0c050c5SMichael Chan __le16 target_id; 7488c0c050c5SMichael Chan __le64 resp_addr; 7489c0c050c5SMichael Chan __le32 flags; 7490c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7491c0c050c5SMichael Chan __le32 enables; 7492c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7493c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7494c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7495c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7496c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7497c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7498c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7499c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7500c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7501c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7502c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7503c0c050c5SMichael Chan __le64 l2_filter_id; 7504c0c050c5SMichael Chan u8 l2_addr[6]; 7505c0c050c5SMichael Chan __le16 l2_ivlan; 7506c0c050c5SMichael Chan __le32 l3_addr[4]; 7507c0c050c5SMichael Chan __le32 t_l3_addr[4]; 7508c0c050c5SMichael Chan u8 l3_addr_type; 7509c0c050c5SMichael Chan u8 t_l3_addr_type; 7510c0c050c5SMichael Chan u8 tunnel_type; 7511441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7512441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7513441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7514441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7515441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7516441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7517441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7518441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7519441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 752057922b0aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 752131d357c0SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 752231d357c0SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 75233322479eSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7524441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7525894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7526894aa69aSMichael Chan u8 tunnel_flags; 7527894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 7528894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 7529894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 7530c0c050c5SMichael Chan __le32 vni; 7531c0c050c5SMichael Chan __le32 dst_vnic_id; 7532c0c050c5SMichael Chan __le32 mirror_vnic_id; 7533c0c050c5SMichael Chan }; 7534c0c050c5SMichael Chan 7535894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 7536c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_output { 7537c0c050c5SMichael Chan __le16 error_code; 7538c0c050c5SMichael Chan __le16 req_type; 7539c0c050c5SMichael Chan __le16 seq_id; 7540c0c050c5SMichael Chan __le16 resp_len; 7541c0c050c5SMichael Chan __le64 tunnel_filter_id; 7542c0c050c5SMichael Chan __le32 flow_id; 75434a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 75444a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 75454a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 75464a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 75474a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 75484a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 75494a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 75504a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 75514a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 75524a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7553894aa69aSMichael Chan u8 unused_0[3]; 7554c0c050c5SMichael Chan u8 valid; 7555c0c050c5SMichael Chan }; 7556c0c050c5SMichael Chan 7557894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7558c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_input { 7559c0c050c5SMichael Chan __le16 req_type; 7560c0c050c5SMichael Chan __le16 cmpl_ring; 7561c0c050c5SMichael Chan __le16 seq_id; 7562c0c050c5SMichael Chan __le16 target_id; 7563c0c050c5SMichael Chan __le64 resp_addr; 7564c0c050c5SMichael Chan __le64 tunnel_filter_id; 7565c0c050c5SMichael Chan }; 7566c0c050c5SMichael Chan 7567894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7568c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_output { 7569c0c050c5SMichael Chan __le16 error_code; 7570c0c050c5SMichael Chan __le16 req_type; 7571c0c050c5SMichael Chan __le16 seq_id; 7572c0c050c5SMichael Chan __le16 resp_len; 7573894aa69aSMichael Chan u8 unused_0[7]; 7574c0c050c5SMichael Chan u8 valid; 7575c0c050c5SMichael Chan }; 7576c0c050c5SMichael Chan 7577894aa69aSMichael Chan /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7578894aa69aSMichael Chan struct hwrm_vxlan_ipv4_hdr { 7579894aa69aSMichael Chan u8 ver_hlen; 7580894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7581894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7582894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7583894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7584894aa69aSMichael Chan u8 tos; 7585894aa69aSMichael Chan __be16 ip_id; 7586894aa69aSMichael Chan __be16 flags_frag_offset; 7587894aa69aSMichael Chan u8 ttl; 7588894aa69aSMichael Chan u8 protocol; 7589894aa69aSMichael Chan __be32 src_ip_addr; 7590894aa69aSMichael Chan __be32 dest_ip_addr; 7591894aa69aSMichael Chan }; 7592894aa69aSMichael Chan 7593894aa69aSMichael Chan /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7594894aa69aSMichael Chan struct hwrm_vxlan_ipv6_hdr { 7595894aa69aSMichael Chan __be32 ver_tc_flow_label; 7596894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7597894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7598894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7599894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7600894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7601894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7602894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7603894aa69aSMichael Chan __be16 payload_len; 7604894aa69aSMichael Chan u8 next_hdr; 7605894aa69aSMichael Chan u8 ttl; 7606894aa69aSMichael Chan __be32 src_ip_addr[4]; 7607894aa69aSMichael Chan __be32 dest_ip_addr[4]; 7608894aa69aSMichael Chan }; 7609894aa69aSMichael Chan 761031d357c0SMichael Chan /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7611894aa69aSMichael Chan struct hwrm_cfa_encap_data_vxlan { 7612894aa69aSMichael Chan u8 src_mac_addr[6]; 7613894aa69aSMichael Chan __le16 unused_0; 7614894aa69aSMichael Chan u8 dst_mac_addr[6]; 7615894aa69aSMichael Chan u8 num_vlan_tags; 7616894aa69aSMichael Chan u8 unused_1; 7617894aa69aSMichael Chan __be16 ovlan_tpid; 7618894aa69aSMichael Chan __be16 ovlan_tci; 7619894aa69aSMichael Chan __be16 ivlan_tpid; 7620894aa69aSMichael Chan __be16 ivlan_tci; 7621894aa69aSMichael Chan __le32 l3[10]; 7622894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7623894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7624894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7625894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7626894aa69aSMichael Chan __be16 src_port; 7627894aa69aSMichael Chan __be16 dst_port; 7628894aa69aSMichael Chan __be32 vni; 762931d357c0SMichael Chan u8 hdr_rsvd0[3]; 763031d357c0SMichael Chan u8 hdr_rsvd1; 763131d357c0SMichael Chan u8 hdr_flags; 763231d357c0SMichael Chan u8 unused[3]; 7633894aa69aSMichael Chan }; 7634894aa69aSMichael Chan 7635894aa69aSMichael Chan /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7636c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_input { 7637c0c050c5SMichael Chan __le16 req_type; 7638c0c050c5SMichael Chan __le16 cmpl_ring; 7639c0c050c5SMichael Chan __le16 seq_id; 7640c0c050c5SMichael Chan __le16 target_id; 7641c0c050c5SMichael Chan __le64 resp_addr; 7642c0c050c5SMichael Chan __le32 flags; 7643c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 76443293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7645c0c050c5SMichael Chan u8 encap_type; 7646441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7647441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7648441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7649441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7650441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7651441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7652441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7653441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 765431d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 765531d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 765631d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 76573293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 76583293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7659894aa69aSMichael Chan u8 unused_0[3]; 7660acb20054SMichael Chan __le32 encap_data[20]; 7661c0c050c5SMichael Chan }; 7662c0c050c5SMichael Chan 7663894aa69aSMichael Chan /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7664c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_output { 7665c0c050c5SMichael Chan __le16 error_code; 7666c0c050c5SMichael Chan __le16 req_type; 7667c0c050c5SMichael Chan __le16 seq_id; 7668c0c050c5SMichael Chan __le16 resp_len; 7669c193554eSMichael Chan __le32 encap_record_id; 7670894aa69aSMichael Chan u8 unused_0[3]; 7671c0c050c5SMichael Chan u8 valid; 7672c0c050c5SMichael Chan }; 7673c0c050c5SMichael Chan 7674894aa69aSMichael Chan /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7675c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_input { 7676c0c050c5SMichael Chan __le16 req_type; 7677c0c050c5SMichael Chan __le16 cmpl_ring; 7678c0c050c5SMichael Chan __le16 seq_id; 7679c0c050c5SMichael Chan __le16 target_id; 7680c0c050c5SMichael Chan __le64 resp_addr; 7681c193554eSMichael Chan __le32 encap_record_id; 7682894aa69aSMichael Chan u8 unused_0[4]; 7683c0c050c5SMichael Chan }; 7684c0c050c5SMichael Chan 7685894aa69aSMichael Chan /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7686c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_output { 7687c0c050c5SMichael Chan __le16 error_code; 7688c0c050c5SMichael Chan __le16 req_type; 7689c0c050c5SMichael Chan __le16 seq_id; 7690c0c050c5SMichael Chan __le16 resp_len; 7691894aa69aSMichael Chan u8 unused_0[7]; 7692c0c050c5SMichael Chan u8 valid; 7693c0c050c5SMichael Chan }; 7694c0c050c5SMichael Chan 769541136ab3SMichael Chan /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7696c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_input { 7697c0c050c5SMichael Chan __le16 req_type; 7698c0c050c5SMichael Chan __le16 cmpl_ring; 7699c0c050c5SMichael Chan __le16 seq_id; 7700c0c050c5SMichael Chan __le16 target_id; 7701c0c050c5SMichael Chan __le64 resp_addr; 7702c0c050c5SMichael Chan __le32 flags; 7703c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7704c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7705bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 77063293ec23SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 770741136ab3SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 770841136ab3SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 770921e70778SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7710c0c050c5SMichael Chan __le32 enables; 7711c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7712c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7713c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7714c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7715c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7716c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7717c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7718c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7719c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7720c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7721c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7722c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7723c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7724c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7725c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7726c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7727c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7728c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7729c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 77304a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7731c0c050c5SMichael Chan __le64 l2_filter_id; 7732c0c050c5SMichael Chan u8 src_macaddr[6]; 7733c0c050c5SMichael Chan __be16 ethertype; 7734c193554eSMichael Chan u8 ip_addr_type; 7735441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7736441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7737441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7738894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7739c0c050c5SMichael Chan u8 ip_protocol; 7740441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7741acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7742acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 774384a911dbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 774484a911dbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 774584a911dbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 774684a911dbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 7747c193554eSMichael Chan __le16 dst_id; 7748c0c050c5SMichael Chan __le16 mirror_vnic_id; 7749c0c050c5SMichael Chan u8 tunnel_type; 7750441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7751441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7752441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7753441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7754441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7755441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7756441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7757441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7758441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 775957922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 776031d357c0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 776131d357c0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 77623322479eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7763441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7764894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7765c0c050c5SMichael Chan u8 pri_hint; 7766441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7767441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7768441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7769441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7770441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7771894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7772c0c050c5SMichael Chan __be32 src_ipaddr[4]; 7773c0c050c5SMichael Chan __be32 src_ipaddr_mask[4]; 7774c0c050c5SMichael Chan __be32 dst_ipaddr[4]; 7775c0c050c5SMichael Chan __be32 dst_ipaddr_mask[4]; 7776c0c050c5SMichael Chan __be16 src_port; 7777c0c050c5SMichael Chan __be16 src_port_mask; 7778c0c050c5SMichael Chan __be16 dst_port; 7779c0c050c5SMichael Chan __be16 dst_port_mask; 7780c0c050c5SMichael Chan __le64 ntuple_filter_id_hint; 7781c0c050c5SMichael Chan }; 7782c0c050c5SMichael Chan 7783894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7784c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_output { 7785c0c050c5SMichael Chan __le16 error_code; 7786c0c050c5SMichael Chan __le16 req_type; 7787c0c050c5SMichael Chan __le16 seq_id; 7788c0c050c5SMichael Chan __le16 resp_len; 7789c0c050c5SMichael Chan __le64 ntuple_filter_id; 7790c0c050c5SMichael Chan __le32 flow_id; 77914a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 77924a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 77934a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 77944a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 77954a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 77964a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 77974a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 77984a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 77994a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 78004a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7801894aa69aSMichael Chan u8 unused_0[3]; 7802c0c050c5SMichael Chan u8 valid; 7803c0c050c5SMichael Chan }; 7804c0c050c5SMichael Chan 7805894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 780657922b0aSMichael Chan struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 780757922b0aSMichael Chan u8 code; 780857922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 780957922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7810894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 781157922b0aSMichael Chan u8 unused_0[7]; 781257922b0aSMichael Chan }; 781357922b0aSMichael Chan 7814894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7815c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_input { 7816c0c050c5SMichael Chan __le16 req_type; 7817c0c050c5SMichael Chan __le16 cmpl_ring; 7818c0c050c5SMichael Chan __le16 seq_id; 7819c0c050c5SMichael Chan __le16 target_id; 7820c0c050c5SMichael Chan __le64 resp_addr; 7821c0c050c5SMichael Chan __le64 ntuple_filter_id; 7822c0c050c5SMichael Chan }; 7823c0c050c5SMichael Chan 7824894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7825c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_output { 7826c0c050c5SMichael Chan __le16 error_code; 7827c0c050c5SMichael Chan __le16 req_type; 7828c0c050c5SMichael Chan __le16 seq_id; 7829c0c050c5SMichael Chan __le16 resp_len; 7830894aa69aSMichael Chan u8 unused_0[7]; 7831c0c050c5SMichael Chan u8 valid; 7832c0c050c5SMichael Chan }; 7833c0c050c5SMichael Chan 7834894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7835c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_input { 7836c0c050c5SMichael Chan __le16 req_type; 7837c0c050c5SMichael Chan __le16 cmpl_ring; 7838c0c050c5SMichael Chan __le16 seq_id; 7839c0c050c5SMichael Chan __le16 target_id; 7840c0c050c5SMichael Chan __le64 resp_addr; 7841c0c050c5SMichael Chan __le32 enables; 7842c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7843c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7844bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 78453293ec23SMichael Chan __le32 flags; 78463293ec23SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 784741136ab3SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 784821e70778SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7849c0c050c5SMichael Chan __le64 ntuple_filter_id; 7850c193554eSMichael Chan __le32 new_dst_id; 7851c0c050c5SMichael Chan __le32 new_mirror_vnic_id; 7852bac9a7e0SMichael Chan __le16 new_meter_instance_id; 7853bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7854894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7855894aa69aSMichael Chan u8 unused_1[6]; 7856c0c050c5SMichael Chan }; 7857c0c050c5SMichael Chan 7858894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7859c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_output { 7860c0c050c5SMichael Chan __le16 error_code; 7861c0c050c5SMichael Chan __le16 req_type; 7862c0c050c5SMichael Chan __le16 seq_id; 7863c0c050c5SMichael Chan __le16 resp_len; 7864894aa69aSMichael Chan u8 unused_0[7]; 7865c0c050c5SMichael Chan u8 valid; 7866c0c050c5SMichael Chan }; 7867c0c050c5SMichael Chan 7868894aa69aSMichael Chan /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 786957922b0aSMichael Chan struct hwrm_cfa_decap_filter_alloc_input { 787057922b0aSMichael Chan __le16 req_type; 787157922b0aSMichael Chan __le16 cmpl_ring; 787257922b0aSMichael Chan __le16 seq_id; 787357922b0aSMichael Chan __le16 target_id; 787457922b0aSMichael Chan __le64 resp_addr; 787557922b0aSMichael Chan __le32 flags; 787657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 787757922b0aSMichael Chan __le32 enables; 787857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 787957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 788057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 788157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 788257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 788357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 788457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 788557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 788657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 788757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 788857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 788957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 789057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 789157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 789257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 789357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 789457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 789557922b0aSMichael Chan __be32 tunnel_id; 789657922b0aSMichael Chan u8 tunnel_type; 789757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 789857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 789957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 790057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 790157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 790257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 790357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 790457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 790557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 790657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 790731d357c0SMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 790831d357c0SMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 79093322479eSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 791057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7911894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 791257922b0aSMichael Chan u8 unused_0; 791357922b0aSMichael Chan __le16 unused_1; 791457922b0aSMichael Chan u8 src_macaddr[6]; 7915894aa69aSMichael Chan u8 unused_2[2]; 791657922b0aSMichael Chan u8 dst_macaddr[6]; 791757922b0aSMichael Chan __be16 ovlan_vid; 791857922b0aSMichael Chan __be16 ivlan_vid; 791957922b0aSMichael Chan __be16 t_ovlan_vid; 792057922b0aSMichael Chan __be16 t_ivlan_vid; 792157922b0aSMichael Chan __be16 ethertype; 792257922b0aSMichael Chan u8 ip_addr_type; 792357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 792457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 792557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7926894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 792757922b0aSMichael Chan u8 ip_protocol; 792857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 792957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 793057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7931894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7932894aa69aSMichael Chan __le16 unused_3; 7933894aa69aSMichael Chan __le32 unused_4; 793457922b0aSMichael Chan __be32 src_ipaddr[4]; 793557922b0aSMichael Chan __be32 dst_ipaddr[4]; 793657922b0aSMichael Chan __be16 src_port; 793757922b0aSMichael Chan __be16 dst_port; 793857922b0aSMichael Chan __le16 dst_id; 793957922b0aSMichael Chan __le16 l2_ctxt_ref_id; 794057922b0aSMichael Chan }; 794157922b0aSMichael Chan 7942894aa69aSMichael Chan /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 794357922b0aSMichael Chan struct hwrm_cfa_decap_filter_alloc_output { 794457922b0aSMichael Chan __le16 error_code; 794557922b0aSMichael Chan __le16 req_type; 794657922b0aSMichael Chan __le16 seq_id; 794757922b0aSMichael Chan __le16 resp_len; 794857922b0aSMichael Chan __le32 decap_filter_id; 7949894aa69aSMichael Chan u8 unused_0[3]; 795057922b0aSMichael Chan u8 valid; 795157922b0aSMichael Chan }; 795257922b0aSMichael Chan 7953894aa69aSMichael Chan /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 795457922b0aSMichael Chan struct hwrm_cfa_decap_filter_free_input { 795557922b0aSMichael Chan __le16 req_type; 795657922b0aSMichael Chan __le16 cmpl_ring; 795757922b0aSMichael Chan __le16 seq_id; 795857922b0aSMichael Chan __le16 target_id; 795957922b0aSMichael Chan __le64 resp_addr; 796057922b0aSMichael Chan __le32 decap_filter_id; 7961894aa69aSMichael Chan u8 unused_0[4]; 796257922b0aSMichael Chan }; 796357922b0aSMichael Chan 7964894aa69aSMichael Chan /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 796557922b0aSMichael Chan struct hwrm_cfa_decap_filter_free_output { 796657922b0aSMichael Chan __le16 error_code; 796757922b0aSMichael Chan __le16 req_type; 796857922b0aSMichael Chan __le16 seq_id; 796957922b0aSMichael Chan __le16 resp_len; 7970894aa69aSMichael Chan u8 unused_0[7]; 797157922b0aSMichael Chan u8 valid; 797257922b0aSMichael Chan }; 797357922b0aSMichael Chan 7974894aa69aSMichael Chan /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 79756a17eb27SMichael Chan struct hwrm_cfa_flow_alloc_input { 79766a17eb27SMichael Chan __le16 req_type; 79776a17eb27SMichael Chan __le16 cmpl_ring; 79786a17eb27SMichael Chan __le16 seq_id; 79796a17eb27SMichael Chan __le16 target_id; 79806a17eb27SMichael Chan __le64 resp_addr; 79816a17eb27SMichael Chan __le16 flags; 79826a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 79836a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 79846a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 79856a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 79866a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 79876a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 79886a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 79896a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 79906a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 79916a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 79926a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 79936a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 79946a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 799531d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 799631d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 799731d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 79983322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 79996a17eb27SMichael Chan __le16 src_fid; 80006a17eb27SMichael Chan __le32 tunnel_handle; 80016a17eb27SMichael Chan __le16 action_flags; 80026a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 80036a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 80046a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 80056a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 80066a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 80076a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 80086a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 80096a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 80106a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 80116a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 801231d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 80133322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 80143322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 80154a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 80166a17eb27SMichael Chan __le16 dst_fid; 80176a17eb27SMichael Chan __be16 l2_rewrite_vlan_tpid; 80186a17eb27SMichael Chan __be16 l2_rewrite_vlan_tci; 80196a17eb27SMichael Chan __le16 act_meter_id; 80206a17eb27SMichael Chan __le16 ref_flow_handle; 80216a17eb27SMichael Chan __be16 ethertype; 80226a17eb27SMichael Chan __be16 outer_vlan_tci; 80236a17eb27SMichael Chan __be16 dmac[3]; 80246a17eb27SMichael Chan __be16 inner_vlan_tci; 80256a17eb27SMichael Chan __be16 smac[3]; 80266a17eb27SMichael Chan u8 ip_dst_mask_len; 80276a17eb27SMichael Chan u8 ip_src_mask_len; 80286a17eb27SMichael Chan __be32 ip_dst[4]; 80296a17eb27SMichael Chan __be32 ip_src[4]; 80306a17eb27SMichael Chan __be16 l4_src_port; 80316a17eb27SMichael Chan __be16 l4_src_port_mask; 80326a17eb27SMichael Chan __be16 l4_dst_port; 80336a17eb27SMichael Chan __be16 l4_dst_port_mask; 80346a17eb27SMichael Chan __be32 nat_ip_address[4]; 80356a17eb27SMichael Chan __be16 l2_rewrite_dmac[3]; 80366a17eb27SMichael Chan __be16 nat_port; 80376a17eb27SMichael Chan __be16 l2_rewrite_smac[3]; 80386a17eb27SMichael Chan u8 ip_proto; 803931d357c0SMichael Chan u8 tunnel_type; 804031d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 804131d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 804231d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 804331d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 804431d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 804531d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 804631d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 804731d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 804831d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 804931d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 805031d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 805131d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 80523322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 805331d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 805431d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 80556a17eb27SMichael Chan }; 80566a17eb27SMichael Chan 805731d357c0SMichael Chan /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 80586a17eb27SMichael Chan struct hwrm_cfa_flow_alloc_output { 80596a17eb27SMichael Chan __le16 error_code; 80606a17eb27SMichael Chan __le16 req_type; 80616a17eb27SMichael Chan __le16 seq_id; 80626a17eb27SMichael Chan __le16 resp_len; 80636a17eb27SMichael Chan __le16 flow_handle; 806431d357c0SMichael Chan u8 unused_0[2]; 806531d357c0SMichael Chan __le32 flow_id; 80664a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 80674a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 80684a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 80694a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 80704a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 80714a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 80724a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 80734a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 80744a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 80754a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 807631d357c0SMichael Chan __le64 ext_flow_handle; 80773322479eSMichael Chan __le32 flow_counter_id; 80783322479eSMichael Chan u8 unused_1[3]; 80796a17eb27SMichael Chan u8 valid; 80806a17eb27SMichael Chan }; 80816a17eb27SMichael Chan 80822792b5b9SMichael Chan /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 80832792b5b9SMichael Chan struct hwrm_cfa_flow_alloc_cmd_err { 80842792b5b9SMichael Chan u8 code; 80852792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 80862792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 80872792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 80882792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 80892792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 80902792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 80912792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 80922792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 80932792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 80942792b5b9SMichael Chan u8 unused_0[7]; 80952792b5b9SMichael Chan }; 80962792b5b9SMichael Chan 809731d357c0SMichael Chan /* hwrm_cfa_flow_free_input (size:256b/32B) */ 80986a17eb27SMichael Chan struct hwrm_cfa_flow_free_input { 80996a17eb27SMichael Chan __le16 req_type; 81006a17eb27SMichael Chan __le16 cmpl_ring; 81016a17eb27SMichael Chan __le16 seq_id; 81026a17eb27SMichael Chan __le16 target_id; 81036a17eb27SMichael Chan __le64 resp_addr; 81046a17eb27SMichael Chan __le16 flow_handle; 81054a50ddc2SMichael Chan __le16 unused_0; 81064a50ddc2SMichael Chan __le32 flow_counter_id; 810731d357c0SMichael Chan __le64 ext_flow_handle; 81086a17eb27SMichael Chan }; 81096a17eb27SMichael Chan 8110894aa69aSMichael Chan /* hwrm_cfa_flow_free_output (size:256b/32B) */ 81116a17eb27SMichael Chan struct hwrm_cfa_flow_free_output { 81126a17eb27SMichael Chan __le16 error_code; 81136a17eb27SMichael Chan __le16 req_type; 81146a17eb27SMichael Chan __le16 seq_id; 81156a17eb27SMichael Chan __le16 resp_len; 81166a17eb27SMichael Chan __le64 packet; 81176a17eb27SMichael Chan __le64 byte; 8118894aa69aSMichael Chan u8 unused_0[7]; 81196a17eb27SMichael Chan u8 valid; 81206a17eb27SMichael Chan }; 81216a17eb27SMichael Chan 81223322479eSMichael Chan /* hwrm_cfa_flow_info_input (size:256b/32B) */ 81233322479eSMichael Chan struct hwrm_cfa_flow_info_input { 81243322479eSMichael Chan __le16 req_type; 81253322479eSMichael Chan __le16 cmpl_ring; 81263322479eSMichael Chan __le16 seq_id; 81273322479eSMichael Chan __le16 target_id; 81283322479eSMichael Chan __le64 resp_addr; 81293322479eSMichael Chan __le16 flow_handle; 81303322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 81313322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 81323322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8133ad04cc05SMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 81343322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 81353322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8136ad04cc05SMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8137ad04cc05SMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8138ad04cc05SMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8139ad04cc05SMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8140ad04cc05SMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 81413322479eSMichael Chan u8 unused_0[6]; 81423322479eSMichael Chan __le64 ext_flow_handle; 81433322479eSMichael Chan }; 81443322479eSMichael Chan 81453293ec23SMichael Chan /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 81463322479eSMichael Chan struct hwrm_cfa_flow_info_output { 81473322479eSMichael Chan __le16 error_code; 81483322479eSMichael Chan __le16 req_type; 81493322479eSMichael Chan __le16 seq_id; 81503322479eSMichael Chan __le16 resp_len; 81513322479eSMichael Chan u8 flags; 81523293ec23SMichael Chan #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 81533293ec23SMichael Chan #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 81543322479eSMichael Chan u8 profile; 81553322479eSMichael Chan __le16 src_fid; 81563322479eSMichael Chan __le16 dst_fid; 81573322479eSMichael Chan __le16 l2_ctxt_id; 81583322479eSMichael Chan __le64 em_info; 81593322479eSMichael Chan __le64 tcam_info; 81603322479eSMichael Chan __le64 vfp_tcam_info; 81613322479eSMichael Chan __le16 ar_id; 81623322479eSMichael Chan __le16 flow_handle; 81633322479eSMichael Chan __le32 tunnel_handle; 81643322479eSMichael Chan __le16 flow_timer; 81653293ec23SMichael Chan u8 unused_0[6]; 81663293ec23SMichael Chan __le32 flow_key_data[130]; 81673293ec23SMichael Chan __le32 flow_action_info[30]; 81683293ec23SMichael Chan u8 unused_1[7]; 81693322479eSMichael Chan u8 valid; 81703322479eSMichael Chan }; 81713322479eSMichael Chan 817231d357c0SMichael Chan /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 81736a17eb27SMichael Chan struct hwrm_cfa_flow_stats_input { 81746a17eb27SMichael Chan __le16 req_type; 81756a17eb27SMichael Chan __le16 cmpl_ring; 81766a17eb27SMichael Chan __le16 seq_id; 81776a17eb27SMichael Chan __le16 target_id; 81786a17eb27SMichael Chan __le64 resp_addr; 81796a17eb27SMichael Chan __le16 num_flows; 81806a17eb27SMichael Chan __le16 flow_handle_0; 81816a17eb27SMichael Chan __le16 flow_handle_1; 81826a17eb27SMichael Chan __le16 flow_handle_2; 81836a17eb27SMichael Chan __le16 flow_handle_3; 81846a17eb27SMichael Chan __le16 flow_handle_4; 81856a17eb27SMichael Chan __le16 flow_handle_5; 81866a17eb27SMichael Chan __le16 flow_handle_6; 81876a17eb27SMichael Chan __le16 flow_handle_7; 81886a17eb27SMichael Chan __le16 flow_handle_8; 81896a17eb27SMichael Chan __le16 flow_handle_9; 8190894aa69aSMichael Chan u8 unused_0[2]; 819131d357c0SMichael Chan __le32 flow_id_0; 819231d357c0SMichael Chan __le32 flow_id_1; 819331d357c0SMichael Chan __le32 flow_id_2; 819431d357c0SMichael Chan __le32 flow_id_3; 819531d357c0SMichael Chan __le32 flow_id_4; 819631d357c0SMichael Chan __le32 flow_id_5; 819731d357c0SMichael Chan __le32 flow_id_6; 819831d357c0SMichael Chan __le32 flow_id_7; 819931d357c0SMichael Chan __le32 flow_id_8; 820031d357c0SMichael Chan __le32 flow_id_9; 82016a17eb27SMichael Chan }; 82026a17eb27SMichael Chan 8203894aa69aSMichael Chan /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 82046a17eb27SMichael Chan struct hwrm_cfa_flow_stats_output { 82056a17eb27SMichael Chan __le16 error_code; 82066a17eb27SMichael Chan __le16 req_type; 82076a17eb27SMichael Chan __le16 seq_id; 82086a17eb27SMichael Chan __le16 resp_len; 82096a17eb27SMichael Chan __le64 packet_0; 82106a17eb27SMichael Chan __le64 packet_1; 82116a17eb27SMichael Chan __le64 packet_2; 82126a17eb27SMichael Chan __le64 packet_3; 82136a17eb27SMichael Chan __le64 packet_4; 82146a17eb27SMichael Chan __le64 packet_5; 82156a17eb27SMichael Chan __le64 packet_6; 82166a17eb27SMichael Chan __le64 packet_7; 82176a17eb27SMichael Chan __le64 packet_8; 82186a17eb27SMichael Chan __le64 packet_9; 82196a17eb27SMichael Chan __le64 byte_0; 82206a17eb27SMichael Chan __le64 byte_1; 82216a17eb27SMichael Chan __le64 byte_2; 82226a17eb27SMichael Chan __le64 byte_3; 82236a17eb27SMichael Chan __le64 byte_4; 82246a17eb27SMichael Chan __le64 byte_5; 82256a17eb27SMichael Chan __le64 byte_6; 82266a17eb27SMichael Chan __le64 byte_7; 82276a17eb27SMichael Chan __le64 byte_8; 82286a17eb27SMichael Chan __le64 byte_9; 8229ad04cc05SMichael Chan __le16 flow_hits; 8230ad04cc05SMichael Chan u8 unused_0[5]; 82316a17eb27SMichael Chan u8 valid; 82326a17eb27SMichael Chan }; 82336a17eb27SMichael Chan 8234894aa69aSMichael Chan /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8235acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_input { 8236acb20054SMichael Chan __le16 req_type; 8237acb20054SMichael Chan __le16 cmpl_ring; 8238acb20054SMichael Chan __le16 seq_id; 8239acb20054SMichael Chan __le16 target_id; 8240acb20054SMichael Chan __le64 resp_addr; 8241acb20054SMichael Chan __le16 vf_id; 8242acb20054SMichael Chan __le16 reserved; 8243894aa69aSMichael Chan u8 unused_0[4]; 8244acb20054SMichael Chan char vfr_name[32]; 8245acb20054SMichael Chan }; 8246acb20054SMichael Chan 8247894aa69aSMichael Chan /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8248acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_output { 8249acb20054SMichael Chan __le16 error_code; 8250acb20054SMichael Chan __le16 req_type; 8251acb20054SMichael Chan __le16 seq_id; 8252acb20054SMichael Chan __le16 resp_len; 8253acb20054SMichael Chan __le16 rx_cfa_code; 8254acb20054SMichael Chan __le16 tx_cfa_action; 8255894aa69aSMichael Chan u8 unused_0[3]; 8256acb20054SMichael Chan u8 valid; 8257acb20054SMichael Chan }; 8258acb20054SMichael Chan 82599d6b648cSMichael Chan /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8260acb20054SMichael Chan struct hwrm_cfa_vfr_free_input { 8261acb20054SMichael Chan __le16 req_type; 8262acb20054SMichael Chan __le16 cmpl_ring; 8263acb20054SMichael Chan __le16 seq_id; 8264acb20054SMichael Chan __le16 target_id; 8265acb20054SMichael Chan __le64 resp_addr; 8266acb20054SMichael Chan char vfr_name[32]; 82679d6b648cSMichael Chan __le16 vf_id; 82689d6b648cSMichael Chan __le16 reserved; 82699d6b648cSMichael Chan u8 unused_0[4]; 8270acb20054SMichael Chan }; 8271acb20054SMichael Chan 8272894aa69aSMichael Chan /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8273acb20054SMichael Chan struct hwrm_cfa_vfr_free_output { 8274acb20054SMichael Chan __le16 error_code; 8275acb20054SMichael Chan __le16 req_type; 8276acb20054SMichael Chan __le16 seq_id; 8277acb20054SMichael Chan __le16 resp_len; 8278894aa69aSMichael Chan u8 unused_0[7]; 8279acb20054SMichael Chan u8 valid; 8280acb20054SMichael Chan }; 8281acb20054SMichael Chan 82823322479eSMichael Chan /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 82833322479eSMichael Chan struct hwrm_cfa_eem_qcaps_input { 82843322479eSMichael Chan __le16 req_type; 82853322479eSMichael Chan __le16 cmpl_ring; 82863322479eSMichael Chan __le16 seq_id; 82873322479eSMichael Chan __le16 target_id; 82883322479eSMichael Chan __le64 resp_addr; 82893322479eSMichael Chan __le32 flags; 82903322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 82913322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 82923322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 82933322479eSMichael Chan __le32 unused_0; 82943322479eSMichael Chan }; 82953322479eSMichael Chan 82962792b5b9SMichael Chan /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 82973322479eSMichael Chan struct hwrm_cfa_eem_qcaps_output { 82983322479eSMichael Chan __le16 error_code; 82993322479eSMichael Chan __le16 req_type; 83003322479eSMichael Chan __le16 seq_id; 83013322479eSMichael Chan __le16 resp_len; 83023322479eSMichael Chan __le32 flags; 83033322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 83043322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 83054a50ddc2SMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 83064a50ddc2SMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 83073322479eSMichael Chan __le32 unused_0; 83083322479eSMichael Chan __le32 supported; 83093322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 83103322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 83113322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 83123322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 83132792b5b9SMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 83143322479eSMichael Chan __le32 max_entries_supported; 83153322479eSMichael Chan __le16 key_entry_size; 83163322479eSMichael Chan __le16 record_entry_size; 83173322479eSMichael Chan __le16 efc_entry_size; 83182792b5b9SMichael Chan __le16 fid_entry_size; 83192792b5b9SMichael Chan u8 unused_1[7]; 83203322479eSMichael Chan u8 valid; 83213322479eSMichael Chan }; 83223322479eSMichael Chan 83232792b5b9SMichael Chan /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 83243322479eSMichael Chan struct hwrm_cfa_eem_cfg_input { 83253322479eSMichael Chan __le16 req_type; 83263322479eSMichael Chan __le16 cmpl_ring; 83273322479eSMichael Chan __le16 seq_id; 83283322479eSMichael Chan __le16 target_id; 83293322479eSMichael Chan __le64 resp_addr; 83303322479eSMichael Chan __le32 flags; 83313322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 83323322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 83333322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 83344a50ddc2SMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 83354a50ddc2SMichael Chan __le16 group_id; 83364a50ddc2SMichael Chan __le16 unused_0; 83373322479eSMichael Chan __le32 num_entries; 83383322479eSMichael Chan __le32 unused_1; 83393322479eSMichael Chan __le16 key0_ctx_id; 83403322479eSMichael Chan __le16 key1_ctx_id; 83413322479eSMichael Chan __le16 record_ctx_id; 83423322479eSMichael Chan __le16 efc_ctx_id; 83432792b5b9SMichael Chan __le16 fid_ctx_id; 83442792b5b9SMichael Chan __le16 unused_2; 83452792b5b9SMichael Chan __le32 unused_3; 83463322479eSMichael Chan }; 83473322479eSMichael Chan 83483322479eSMichael Chan /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 83493322479eSMichael Chan struct hwrm_cfa_eem_cfg_output { 83503322479eSMichael Chan __le16 error_code; 83513322479eSMichael Chan __le16 req_type; 83523322479eSMichael Chan __le16 seq_id; 83533322479eSMichael Chan __le16 resp_len; 83543322479eSMichael Chan u8 unused_0[7]; 83553322479eSMichael Chan u8 valid; 83563322479eSMichael Chan }; 83573322479eSMichael Chan 83583322479eSMichael Chan /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 83593322479eSMichael Chan struct hwrm_cfa_eem_qcfg_input { 83603322479eSMichael Chan __le16 req_type; 83613322479eSMichael Chan __le16 cmpl_ring; 83623322479eSMichael Chan __le16 seq_id; 83633322479eSMichael Chan __le16 target_id; 83643322479eSMichael Chan __le64 resp_addr; 83653322479eSMichael Chan __le32 flags; 83663322479eSMichael Chan #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 83673322479eSMichael Chan #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 83683322479eSMichael Chan __le32 unused_0; 83693322479eSMichael Chan }; 83703322479eSMichael Chan 83712792b5b9SMichael Chan /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 83723322479eSMichael Chan struct hwrm_cfa_eem_qcfg_output { 83733322479eSMichael Chan __le16 error_code; 83743322479eSMichael Chan __le16 req_type; 83753322479eSMichael Chan __le16 seq_id; 83763322479eSMichael Chan __le16 resp_len; 83773322479eSMichael Chan __le32 flags; 83783322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 83793322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 83803322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 83813322479eSMichael Chan __le32 num_entries; 83822792b5b9SMichael Chan __le16 key0_ctx_id; 83832792b5b9SMichael Chan __le16 key1_ctx_id; 83842792b5b9SMichael Chan __le16 record_ctx_id; 83852792b5b9SMichael Chan __le16 efc_ctx_id; 83862792b5b9SMichael Chan __le16 fid_ctx_id; 83872792b5b9SMichael Chan u8 unused_2[5]; 83884a50ddc2SMichael Chan u8 valid; 83893322479eSMichael Chan }; 83903322479eSMichael Chan 83913322479eSMichael Chan /* hwrm_cfa_eem_op_input (size:192b/24B) */ 83923322479eSMichael Chan struct hwrm_cfa_eem_op_input { 83933322479eSMichael Chan __le16 req_type; 83943322479eSMichael Chan __le16 cmpl_ring; 83953322479eSMichael Chan __le16 seq_id; 83963322479eSMichael Chan __le16 target_id; 83973322479eSMichael Chan __le64 resp_addr; 83983322479eSMichael Chan __le32 flags; 83993322479eSMichael Chan #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 84003322479eSMichael Chan #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 84013322479eSMichael Chan __le16 unused_0; 84023322479eSMichael Chan __le16 op; 84033322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 84043322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 84053322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 84063322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 84073322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 84083322479eSMichael Chan }; 84093322479eSMichael Chan 84103322479eSMichael Chan /* hwrm_cfa_eem_op_output (size:128b/16B) */ 84113322479eSMichael Chan struct hwrm_cfa_eem_op_output { 84123322479eSMichael Chan __le16 error_code; 84133322479eSMichael Chan __le16 req_type; 84143322479eSMichael Chan __le16 seq_id; 84153322479eSMichael Chan __le16 resp_len; 84163322479eSMichael Chan u8 unused_0[7]; 84173322479eSMichael Chan u8 valid; 84183322479eSMichael Chan }; 84193322479eSMichael Chan 84204a50ddc2SMichael Chan /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 84214a50ddc2SMichael Chan struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 84224a50ddc2SMichael Chan __le16 req_type; 84234a50ddc2SMichael Chan __le16 cmpl_ring; 84244a50ddc2SMichael Chan __le16 seq_id; 84254a50ddc2SMichael Chan __le16 target_id; 84264a50ddc2SMichael Chan __le64 resp_addr; 84274a50ddc2SMichael Chan __le32 unused_0[4]; 84284a50ddc2SMichael Chan }; 84294a50ddc2SMichael Chan 84304a50ddc2SMichael Chan /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 84314a50ddc2SMichael Chan struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 84324a50ddc2SMichael Chan __le16 error_code; 84334a50ddc2SMichael Chan __le16 req_type; 84344a50ddc2SMichael Chan __le16 seq_id; 84354a50ddc2SMichael Chan __le16 resp_len; 84364a50ddc2SMichael Chan __le32 flags; 84374a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 84384a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 84394a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 84404a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 84414a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 84424a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 84434a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 84444a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 84454a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 84464a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 84474a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 84484a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 844941136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 845041136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 845141136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 845216db6323SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 845316db6323SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 845478eeadb8SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 845521e70778SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8456ad04cc05SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 845784a911dbSMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 84584a50ddc2SMichael Chan u8 unused_0[3]; 84594a50ddc2SMichael Chan u8 valid; 84604a50ddc2SMichael Chan }; 84614a50ddc2SMichael Chan 84622895c153SMichael Chan /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8463c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_input { 8464c0c050c5SMichael Chan __le16 req_type; 8465c0c050c5SMichael Chan __le16 cmpl_ring; 8466c0c050c5SMichael Chan __le16 seq_id; 8467c0c050c5SMichael Chan __le16 target_id; 8468c0c050c5SMichael Chan __le64 resp_addr; 8469c0c050c5SMichael Chan u8 tunnel_type; 8470441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8471441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 847257922b0aSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 84736fc92c33SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 847431d357c0SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 84753322479eSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 847684a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 847784a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 847884a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 8479c0c050c5SMichael Chan u8 unused_0[7]; 8480c0c050c5SMichael Chan }; 8481c0c050c5SMichael Chan 8482894aa69aSMichael Chan /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 8483c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_output { 8484c0c050c5SMichael Chan __le16 error_code; 8485c0c050c5SMichael Chan __le16 req_type; 8486c0c050c5SMichael Chan __le16 seq_id; 8487c0c050c5SMichael Chan __le16 resp_len; 8488c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 8489c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 849084a911dbSMichael Chan u8 upar_in_use; 849184a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 849284a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 849384a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 849484a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 849584a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 849684a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 849784a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 849884a911dbSMichael Chan #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 849984a911dbSMichael Chan u8 unused_0[2]; 8500c0c050c5SMichael Chan u8 valid; 8501c0c050c5SMichael Chan }; 8502c0c050c5SMichael Chan 8503894aa69aSMichael Chan /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 8504c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_input { 8505c0c050c5SMichael Chan __le16 req_type; 8506c0c050c5SMichael Chan __le16 cmpl_ring; 8507c0c050c5SMichael Chan __le16 seq_id; 8508c0c050c5SMichael Chan __le16 target_id; 8509c0c050c5SMichael Chan __le64 resp_addr; 8510c0c050c5SMichael Chan u8 tunnel_type; 8511441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8512441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 851357922b0aSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 85146fc92c33SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 851531d357c0SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 85163322479eSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 851784a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 851884a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 851984a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 8520c0c050c5SMichael Chan u8 unused_0; 8521c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 8522894aa69aSMichael Chan u8 unused_1[4]; 8523c0c050c5SMichael Chan }; 8524c0c050c5SMichael Chan 8525894aa69aSMichael Chan /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 8526c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_output { 8527c0c050c5SMichael Chan __le16 error_code; 8528c0c050c5SMichael Chan __le16 req_type; 8529c0c050c5SMichael Chan __le16 seq_id; 8530c0c050c5SMichael Chan __le16 resp_len; 8531c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 853284a911dbSMichael Chan u8 error_info; 853384a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 853484a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 853584a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 853684a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 853784a911dbSMichael Chan u8 upar_in_use; 853884a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 853984a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 854084a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 854184a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 854284a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 854384a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 854484a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 854584a911dbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 854684a911dbSMichael Chan u8 unused_0[3]; 8547c0c050c5SMichael Chan u8 valid; 8548c0c050c5SMichael Chan }; 8549c0c050c5SMichael Chan 8550894aa69aSMichael Chan /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 8551c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_input { 8552c0c050c5SMichael Chan __le16 req_type; 8553c0c050c5SMichael Chan __le16 cmpl_ring; 8554c0c050c5SMichael Chan __le16 seq_id; 8555c0c050c5SMichael Chan __le16 target_id; 8556c0c050c5SMichael Chan __le64 resp_addr; 8557c0c050c5SMichael Chan u8 tunnel_type; 8558441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8559441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 856057922b0aSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 85616fc92c33SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 856231d357c0SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 85633322479eSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 856484a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 856584a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 856684a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 8567c0c050c5SMichael Chan u8 unused_0; 8568c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 8569894aa69aSMichael Chan u8 unused_1[4]; 8570c0c050c5SMichael Chan }; 8571c0c050c5SMichael Chan 8572894aa69aSMichael Chan /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 8573c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_output { 8574c0c050c5SMichael Chan __le16 error_code; 8575c0c050c5SMichael Chan __le16 req_type; 8576c0c050c5SMichael Chan __le16 seq_id; 8577c0c050c5SMichael Chan __le16 resp_len; 857884a911dbSMichael Chan u8 error_info; 857984a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 858084a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 858184a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 858284a911dbSMichael Chan #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 858384a911dbSMichael Chan u8 unused_1[6]; 8584c0c050c5SMichael Chan u8 valid; 8585c0c050c5SMichael Chan }; 8586c0c050c5SMichael Chan 8587894aa69aSMichael Chan /* ctx_hw_stats (size:1280b/160B) */ 8588894aa69aSMichael Chan struct ctx_hw_stats { 8589894aa69aSMichael Chan __le64 rx_ucast_pkts; 8590894aa69aSMichael Chan __le64 rx_mcast_pkts; 8591894aa69aSMichael Chan __le64 rx_bcast_pkts; 8592894aa69aSMichael Chan __le64 rx_discard_pkts; 8593bfc6e5fbSMichael Chan __le64 rx_error_pkts; 8594894aa69aSMichael Chan __le64 rx_ucast_bytes; 8595894aa69aSMichael Chan __le64 rx_mcast_bytes; 8596894aa69aSMichael Chan __le64 rx_bcast_bytes; 8597894aa69aSMichael Chan __le64 tx_ucast_pkts; 8598894aa69aSMichael Chan __le64 tx_mcast_pkts; 8599894aa69aSMichael Chan __le64 tx_bcast_pkts; 8600bfc6e5fbSMichael Chan __le64 tx_error_pkts; 8601894aa69aSMichael Chan __le64 tx_discard_pkts; 8602894aa69aSMichael Chan __le64 tx_ucast_bytes; 8603894aa69aSMichael Chan __le64 tx_mcast_bytes; 8604894aa69aSMichael Chan __le64 tx_bcast_bytes; 8605894aa69aSMichael Chan __le64 tpa_pkts; 8606894aa69aSMichael Chan __le64 tpa_bytes; 8607894aa69aSMichael Chan __le64 tpa_events; 8608894aa69aSMichael Chan __le64 tpa_aborts; 8609894aa69aSMichael Chan }; 8610894aa69aSMichael Chan 86119d6b648cSMichael Chan /* ctx_hw_stats_ext (size:1408b/176B) */ 86122792b5b9SMichael Chan struct ctx_hw_stats_ext { 86132792b5b9SMichael Chan __le64 rx_ucast_pkts; 86142792b5b9SMichael Chan __le64 rx_mcast_pkts; 86152792b5b9SMichael Chan __le64 rx_bcast_pkts; 86162792b5b9SMichael Chan __le64 rx_discard_pkts; 8617bfc6e5fbSMichael Chan __le64 rx_error_pkts; 86182792b5b9SMichael Chan __le64 rx_ucast_bytes; 86192792b5b9SMichael Chan __le64 rx_mcast_bytes; 86202792b5b9SMichael Chan __le64 rx_bcast_bytes; 86212792b5b9SMichael Chan __le64 tx_ucast_pkts; 86222792b5b9SMichael Chan __le64 tx_mcast_pkts; 86232792b5b9SMichael Chan __le64 tx_bcast_pkts; 8624bfc6e5fbSMichael Chan __le64 tx_error_pkts; 86252792b5b9SMichael Chan __le64 tx_discard_pkts; 86262792b5b9SMichael Chan __le64 tx_ucast_bytes; 86272792b5b9SMichael Chan __le64 tx_mcast_bytes; 86282792b5b9SMichael Chan __le64 tx_bcast_bytes; 86292792b5b9SMichael Chan __le64 rx_tpa_eligible_pkt; 86302792b5b9SMichael Chan __le64 rx_tpa_eligible_bytes; 86312792b5b9SMichael Chan __le64 rx_tpa_pkt; 86322792b5b9SMichael Chan __le64 rx_tpa_bytes; 86332792b5b9SMichael Chan __le64 rx_tpa_errors; 86349d6b648cSMichael Chan __le64 rx_tpa_events; 86352792b5b9SMichael Chan }; 86362792b5b9SMichael Chan 8637894aa69aSMichael Chan /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 8638c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_input { 8639c0c050c5SMichael Chan __le16 req_type; 8640c0c050c5SMichael Chan __le16 cmpl_ring; 8641c0c050c5SMichael Chan __le16 seq_id; 8642c0c050c5SMichael Chan __le16 target_id; 8643c0c050c5SMichael Chan __le64 resp_addr; 8644c0c050c5SMichael Chan __le64 stats_dma_addr; 8645c0c050c5SMichael Chan __le32 update_period_ms; 864687c374deSMichael Chan u8 stat_ctx_flags; 864787c374deSMichael Chan #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 86482792b5b9SMichael Chan u8 unused_0; 86492792b5b9SMichael Chan __le16 stats_dma_length; 8650c0c050c5SMichael Chan }; 8651c0c050c5SMichael Chan 8652894aa69aSMichael Chan /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8653c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_output { 8654c0c050c5SMichael Chan __le16 error_code; 8655c0c050c5SMichael Chan __le16 req_type; 8656c0c050c5SMichael Chan __le16 seq_id; 8657c0c050c5SMichael Chan __le16 resp_len; 8658c0c050c5SMichael Chan __le32 stat_ctx_id; 8659894aa69aSMichael Chan u8 unused_0[3]; 8660c0c050c5SMichael Chan u8 valid; 8661c0c050c5SMichael Chan }; 8662c0c050c5SMichael Chan 8663894aa69aSMichael Chan /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8664c0c050c5SMichael Chan struct hwrm_stat_ctx_free_input { 8665c0c050c5SMichael Chan __le16 req_type; 8666c0c050c5SMichael Chan __le16 cmpl_ring; 8667c0c050c5SMichael Chan __le16 seq_id; 8668c0c050c5SMichael Chan __le16 target_id; 8669c0c050c5SMichael Chan __le64 resp_addr; 8670c0c050c5SMichael Chan __le32 stat_ctx_id; 8671894aa69aSMichael Chan u8 unused_0[4]; 8672c0c050c5SMichael Chan }; 8673c0c050c5SMichael Chan 8674894aa69aSMichael Chan /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8675c0c050c5SMichael Chan struct hwrm_stat_ctx_free_output { 8676c0c050c5SMichael Chan __le16 error_code; 8677c0c050c5SMichael Chan __le16 req_type; 8678c0c050c5SMichael Chan __le16 seq_id; 8679c0c050c5SMichael Chan __le16 resp_len; 8680c0c050c5SMichael Chan __le32 stat_ctx_id; 8681894aa69aSMichael Chan u8 unused_0[3]; 8682c0c050c5SMichael Chan u8 valid; 8683c0c050c5SMichael Chan }; 8684c0c050c5SMichael Chan 8685894aa69aSMichael Chan /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8686c0c050c5SMichael Chan struct hwrm_stat_ctx_query_input { 8687c0c050c5SMichael Chan __le16 req_type; 8688c0c050c5SMichael Chan __le16 cmpl_ring; 8689c0c050c5SMichael Chan __le16 seq_id; 8690c0c050c5SMichael Chan __le16 target_id; 8691c0c050c5SMichael Chan __le64 resp_addr; 8692c0c050c5SMichael Chan __le32 stat_ctx_id; 8693bfc6e5fbSMichael Chan u8 flags; 8694bfc6e5fbSMichael Chan #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8695bfc6e5fbSMichael Chan u8 unused_0[3]; 8696c0c050c5SMichael Chan }; 8697c0c050c5SMichael Chan 8698894aa69aSMichael Chan /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8699c0c050c5SMichael Chan struct hwrm_stat_ctx_query_output { 8700c0c050c5SMichael Chan __le16 error_code; 8701c0c050c5SMichael Chan __le16 req_type; 8702c0c050c5SMichael Chan __le16 seq_id; 8703c0c050c5SMichael Chan __le16 resp_len; 8704c0c050c5SMichael Chan __le64 tx_ucast_pkts; 8705c0c050c5SMichael Chan __le64 tx_mcast_pkts; 8706c0c050c5SMichael Chan __le64 tx_bcast_pkts; 87079d6b648cSMichael Chan __le64 tx_discard_pkts; 87089d6b648cSMichael Chan __le64 tx_error_pkts; 8709c0c050c5SMichael Chan __le64 tx_ucast_bytes; 8710c0c050c5SMichael Chan __le64 tx_mcast_bytes; 8711c0c050c5SMichael Chan __le64 tx_bcast_bytes; 8712c0c050c5SMichael Chan __le64 rx_ucast_pkts; 8713c0c050c5SMichael Chan __le64 rx_mcast_pkts; 8714c0c050c5SMichael Chan __le64 rx_bcast_pkts; 87159d6b648cSMichael Chan __le64 rx_discard_pkts; 87169d6b648cSMichael Chan __le64 rx_error_pkts; 8717c0c050c5SMichael Chan __le64 rx_ucast_bytes; 8718c0c050c5SMichael Chan __le64 rx_mcast_bytes; 8719c0c050c5SMichael Chan __le64 rx_bcast_bytes; 8720c0c050c5SMichael Chan __le64 rx_agg_pkts; 8721c0c050c5SMichael Chan __le64 rx_agg_bytes; 8722c0c050c5SMichael Chan __le64 rx_agg_events; 8723c0c050c5SMichael Chan __le64 rx_agg_aborts; 8724894aa69aSMichael Chan u8 unused_0[7]; 8725c0c050c5SMichael Chan u8 valid; 8726c0c050c5SMichael Chan }; 8727c0c050c5SMichael Chan 8728bfc6e5fbSMichael Chan /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8729bfc6e5fbSMichael Chan struct hwrm_stat_ext_ctx_query_input { 8730bfc6e5fbSMichael Chan __le16 req_type; 8731bfc6e5fbSMichael Chan __le16 cmpl_ring; 8732bfc6e5fbSMichael Chan __le16 seq_id; 8733bfc6e5fbSMichael Chan __le16 target_id; 8734bfc6e5fbSMichael Chan __le64 resp_addr; 8735bfc6e5fbSMichael Chan __le32 stat_ctx_id; 8736bfc6e5fbSMichael Chan u8 flags; 8737bfc6e5fbSMichael Chan #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8738bfc6e5fbSMichael Chan u8 unused_0[3]; 8739bfc6e5fbSMichael Chan }; 8740bfc6e5fbSMichael Chan 87419d6b648cSMichael Chan /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8742bfc6e5fbSMichael Chan struct hwrm_stat_ext_ctx_query_output { 8743bfc6e5fbSMichael Chan __le16 error_code; 8744bfc6e5fbSMichael Chan __le16 req_type; 8745bfc6e5fbSMichael Chan __le16 seq_id; 8746bfc6e5fbSMichael Chan __le16 resp_len; 8747bfc6e5fbSMichael Chan __le64 rx_ucast_pkts; 8748bfc6e5fbSMichael Chan __le64 rx_mcast_pkts; 8749bfc6e5fbSMichael Chan __le64 rx_bcast_pkts; 8750bfc6e5fbSMichael Chan __le64 rx_discard_pkts; 8751bfc6e5fbSMichael Chan __le64 rx_error_pkts; 8752bfc6e5fbSMichael Chan __le64 rx_ucast_bytes; 8753bfc6e5fbSMichael Chan __le64 rx_mcast_bytes; 8754bfc6e5fbSMichael Chan __le64 rx_bcast_bytes; 8755bfc6e5fbSMichael Chan __le64 tx_ucast_pkts; 8756bfc6e5fbSMichael Chan __le64 tx_mcast_pkts; 8757bfc6e5fbSMichael Chan __le64 tx_bcast_pkts; 8758bfc6e5fbSMichael Chan __le64 tx_error_pkts; 8759bfc6e5fbSMichael Chan __le64 tx_discard_pkts; 8760bfc6e5fbSMichael Chan __le64 tx_ucast_bytes; 8761bfc6e5fbSMichael Chan __le64 tx_mcast_bytes; 8762bfc6e5fbSMichael Chan __le64 tx_bcast_bytes; 8763bfc6e5fbSMichael Chan __le64 rx_tpa_eligible_pkt; 8764bfc6e5fbSMichael Chan __le64 rx_tpa_eligible_bytes; 8765bfc6e5fbSMichael Chan __le64 rx_tpa_pkt; 8766bfc6e5fbSMichael Chan __le64 rx_tpa_bytes; 8767bfc6e5fbSMichael Chan __le64 rx_tpa_errors; 87689d6b648cSMichael Chan __le64 rx_tpa_events; 8769bfc6e5fbSMichael Chan u8 unused_0[7]; 8770bfc6e5fbSMichael Chan u8 valid; 8771bfc6e5fbSMichael Chan }; 8772bfc6e5fbSMichael Chan 8773894aa69aSMichael Chan /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8774c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_input { 8775c0c050c5SMichael Chan __le16 req_type; 8776c0c050c5SMichael Chan __le16 cmpl_ring; 8777c0c050c5SMichael Chan __le16 seq_id; 8778c0c050c5SMichael Chan __le16 target_id; 8779c0c050c5SMichael Chan __le64 resp_addr; 8780c0c050c5SMichael Chan __le32 stat_ctx_id; 8781894aa69aSMichael Chan u8 unused_0[4]; 8782c0c050c5SMichael Chan }; 8783c0c050c5SMichael Chan 8784894aa69aSMichael Chan /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8785c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_output { 8786c0c050c5SMichael Chan __le16 error_code; 8787c0c050c5SMichael Chan __le16 req_type; 8788c0c050c5SMichael Chan __le16 seq_id; 8789c0c050c5SMichael Chan __le16 resp_len; 879011f15ed3SMichael Chan u8 unused_0[7]; 879111f15ed3SMichael Chan u8 valid; 879211f15ed3SMichael Chan }; 879311f15ed3SMichael Chan 8794d4f52de0SMichael Chan /* hwrm_pcie_qstats_input (size:256b/32B) */ 8795d4f52de0SMichael Chan struct hwrm_pcie_qstats_input { 8796d4f52de0SMichael Chan __le16 req_type; 8797d4f52de0SMichael Chan __le16 cmpl_ring; 8798d4f52de0SMichael Chan __le16 seq_id; 8799d4f52de0SMichael Chan __le16 target_id; 8800d4f52de0SMichael Chan __le64 resp_addr; 8801d4f52de0SMichael Chan __le16 pcie_stat_size; 8802d4f52de0SMichael Chan u8 unused_0[6]; 8803d4f52de0SMichael Chan __le64 pcie_stat_host_addr; 8804d4f52de0SMichael Chan }; 8805d4f52de0SMichael Chan 8806d4f52de0SMichael Chan /* hwrm_pcie_qstats_output (size:128b/16B) */ 8807d4f52de0SMichael Chan struct hwrm_pcie_qstats_output { 8808d4f52de0SMichael Chan __le16 error_code; 8809d4f52de0SMichael Chan __le16 req_type; 8810d4f52de0SMichael Chan __le16 seq_id; 8811d4f52de0SMichael Chan __le16 resp_len; 8812d4f52de0SMichael Chan __le16 pcie_stat_size; 8813d4f52de0SMichael Chan u8 unused_0[5]; 8814d4f52de0SMichael Chan u8 valid; 8815d4f52de0SMichael Chan }; 8816d4f52de0SMichael Chan 8817d4f52de0SMichael Chan /* pcie_ctx_hw_stats (size:768b/96B) */ 8818d4f52de0SMichael Chan struct pcie_ctx_hw_stats { 8819d4f52de0SMichael Chan __le64 pcie_pl_signal_integrity; 8820d4f52de0SMichael Chan __le64 pcie_dl_signal_integrity; 8821d4f52de0SMichael Chan __le64 pcie_tl_signal_integrity; 8822d4f52de0SMichael Chan __le64 pcie_link_integrity; 8823d4f52de0SMichael Chan __le64 pcie_tx_traffic_rate; 8824d4f52de0SMichael Chan __le64 pcie_rx_traffic_rate; 8825d4f52de0SMichael Chan __le64 pcie_tx_dllp_statistics; 8826d4f52de0SMichael Chan __le64 pcie_rx_dllp_statistics; 8827d4f52de0SMichael Chan __le64 pcie_equalization_time; 8828d4f52de0SMichael Chan __le32 pcie_ltssm_histogram[4]; 8829d4f52de0SMichael Chan __le64 pcie_recovery_histogram; 8830d4f52de0SMichael Chan }; 8831d4f52de0SMichael Chan 8832ad04cc05SMichael Chan /* hwrm_stat_generic_qstats_input (size:256b/32B) */ 8833ad04cc05SMichael Chan struct hwrm_stat_generic_qstats_input { 8834ad04cc05SMichael Chan __le16 req_type; 8835ad04cc05SMichael Chan __le16 cmpl_ring; 8836ad04cc05SMichael Chan __le16 seq_id; 8837ad04cc05SMichael Chan __le16 target_id; 8838ad04cc05SMichael Chan __le64 resp_addr; 8839ad04cc05SMichael Chan __le16 generic_stat_size; 8840ad04cc05SMichael Chan u8 flags; 8841ad04cc05SMichael Chan #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 8842ad04cc05SMichael Chan u8 unused_0[5]; 8843ad04cc05SMichael Chan __le64 generic_stat_host_addr; 8844ad04cc05SMichael Chan }; 8845ad04cc05SMichael Chan 8846ad04cc05SMichael Chan /* hwrm_stat_generic_qstats_output (size:128b/16B) */ 8847ad04cc05SMichael Chan struct hwrm_stat_generic_qstats_output { 8848ad04cc05SMichael Chan __le16 error_code; 8849ad04cc05SMichael Chan __le16 req_type; 8850ad04cc05SMichael Chan __le16 seq_id; 8851ad04cc05SMichael Chan __le16 resp_len; 8852ad04cc05SMichael Chan __le16 generic_stat_size; 8853ad04cc05SMichael Chan u8 unused_0[5]; 8854ad04cc05SMichael Chan u8 valid; 8855ad04cc05SMichael Chan }; 8856ad04cc05SMichael Chan 8857ad04cc05SMichael Chan /* generic_sw_hw_stats (size:1216b/152B) */ 8858ad04cc05SMichael Chan struct generic_sw_hw_stats { 8859ad04cc05SMichael Chan __le64 pcie_statistics_tx_tlp; 8860ad04cc05SMichael Chan __le64 pcie_statistics_rx_tlp; 8861ad04cc05SMichael Chan __le64 pcie_credit_fc_hdr_posted; 8862ad04cc05SMichael Chan __le64 pcie_credit_fc_hdr_nonposted; 8863ad04cc05SMichael Chan __le64 pcie_credit_fc_hdr_cmpl; 8864ad04cc05SMichael Chan __le64 pcie_credit_fc_data_posted; 8865ad04cc05SMichael Chan __le64 pcie_credit_fc_data_nonposted; 8866ad04cc05SMichael Chan __le64 pcie_credit_fc_data_cmpl; 8867ad04cc05SMichael Chan __le64 pcie_credit_fc_tgt_nonposted; 8868ad04cc05SMichael Chan __le64 pcie_credit_fc_tgt_data_posted; 8869ad04cc05SMichael Chan __le64 pcie_credit_fc_tgt_hdr_posted; 8870ad04cc05SMichael Chan __le64 pcie_credit_fc_cmpl_hdr_posted; 8871ad04cc05SMichael Chan __le64 pcie_credit_fc_cmpl_data_posted; 8872ad04cc05SMichael Chan __le64 pcie_cmpl_longest; 8873ad04cc05SMichael Chan __le64 pcie_cmpl_shortest; 8874ad04cc05SMichael Chan __le64 cache_miss_count_cfcq; 8875ad04cc05SMichael Chan __le64 cache_miss_count_cfcs; 8876ad04cc05SMichael Chan __le64 cache_miss_count_cfcc; 8877ad04cc05SMichael Chan __le64 cache_miss_count_cfcm; 8878ad04cc05SMichael Chan }; 8879ad04cc05SMichael Chan 8880894aa69aSMichael Chan /* hwrm_fw_reset_input (size:192b/24B) */ 8881894aa69aSMichael Chan struct hwrm_fw_reset_input { 8882894aa69aSMichael Chan __le16 req_type; 8883894aa69aSMichael Chan __le16 cmpl_ring; 8884894aa69aSMichael Chan __le16 seq_id; 8885894aa69aSMichael Chan __le16 target_id; 8886894aa69aSMichael Chan __le64 resp_addr; 8887894aa69aSMichael Chan u8 embedded_proc_type; 8888894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8889894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8890894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8891894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8892894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8893894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8894894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8895d4f52de0SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 889672e0c9f9SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 889772e0c9f9SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8898894aa69aSMichael Chan u8 selfrst_status; 8899894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8900894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8901894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 890231d357c0SMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 890331d357c0SMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8904894aa69aSMichael Chan u8 host_idx; 89053322479eSMichael Chan u8 flags; 89063322479eSMichael Chan #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8907fbfee257SMichael Chan #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 89083322479eSMichael Chan u8 unused_0[4]; 890957922b0aSMichael Chan }; 891057922b0aSMichael Chan 8911894aa69aSMichael Chan /* hwrm_fw_reset_output (size:128b/16B) */ 8912894aa69aSMichael Chan struct hwrm_fw_reset_output { 8913894aa69aSMichael Chan __le16 error_code; 8914894aa69aSMichael Chan __le16 req_type; 8915894aa69aSMichael Chan __le16 seq_id; 8916894aa69aSMichael Chan __le16 resp_len; 8917894aa69aSMichael Chan u8 selfrst_status; 8918894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8919894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8920894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 892131d357c0SMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 892231d357c0SMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8923894aa69aSMichael Chan u8 unused_0[6]; 8924894aa69aSMichael Chan u8 valid; 892557922b0aSMichael Chan }; 892657922b0aSMichael Chan 8927894aa69aSMichael Chan /* hwrm_fw_qstatus_input (size:192b/24B) */ 8928894aa69aSMichael Chan struct hwrm_fw_qstatus_input { 8929894aa69aSMichael Chan __le16 req_type; 8930894aa69aSMichael Chan __le16 cmpl_ring; 8931894aa69aSMichael Chan __le16 seq_id; 8932894aa69aSMichael Chan __le16 target_id; 8933894aa69aSMichael Chan __le64 resp_addr; 8934894aa69aSMichael Chan u8 embedded_proc_type; 8935894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8936894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8937894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8938894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8939894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8940894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8941894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8942894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8943894aa69aSMichael Chan u8 unused_0[7]; 894457922b0aSMichael Chan }; 894557922b0aSMichael Chan 8946894aa69aSMichael Chan /* hwrm_fw_qstatus_output (size:128b/16B) */ 8947894aa69aSMichael Chan struct hwrm_fw_qstatus_output { 8948894aa69aSMichael Chan __le16 error_code; 8949894aa69aSMichael Chan __le16 req_type; 8950894aa69aSMichael Chan __le16 seq_id; 8951894aa69aSMichael Chan __le16 resp_len; 8952894aa69aSMichael Chan u8 selfrst_status; 8953894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8954894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8955894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 89564a50ddc2SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 89574a50ddc2SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 895831f67c2eSMichael Chan u8 nvm_option_action_status; 895931f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 896031f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 896131f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 896231f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 896331f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 896431f67c2eSMichael Chan u8 unused_0[5]; 8965894aa69aSMichael Chan u8 valid; 896687c374deSMichael Chan }; 896787c374deSMichael Chan 8968894aa69aSMichael Chan /* hwrm_fw_set_time_input (size:256b/32B) */ 8969894aa69aSMichael Chan struct hwrm_fw_set_time_input { 8970894aa69aSMichael Chan __le16 req_type; 8971894aa69aSMichael Chan __le16 cmpl_ring; 8972894aa69aSMichael Chan __le16 seq_id; 8973894aa69aSMichael Chan __le16 target_id; 8974894aa69aSMichael Chan __le64 resp_addr; 8975894aa69aSMichael Chan __le16 year; 8976894aa69aSMichael Chan #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8977894aa69aSMichael Chan #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8978894aa69aSMichael Chan u8 month; 8979894aa69aSMichael Chan u8 day; 8980894aa69aSMichael Chan u8 hour; 8981894aa69aSMichael Chan u8 minute; 8982894aa69aSMichael Chan u8 second; 8983894aa69aSMichael Chan u8 unused_0; 8984894aa69aSMichael Chan __le16 millisecond; 8985894aa69aSMichael Chan __le16 zone; 89864a50ddc2SMichael Chan #define FW_SET_TIME_REQ_ZONE_UTC 0 89874a50ddc2SMichael Chan #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8988894aa69aSMichael Chan #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8989894aa69aSMichael Chan u8 unused_1[4]; 8990894aa69aSMichael Chan }; 8991894aa69aSMichael Chan 8992894aa69aSMichael Chan /* hwrm_fw_set_time_output (size:128b/16B) */ 8993894aa69aSMichael Chan struct hwrm_fw_set_time_output { 8994894aa69aSMichael Chan __le16 error_code; 8995894aa69aSMichael Chan __le16 req_type; 8996894aa69aSMichael Chan __le16 seq_id; 8997894aa69aSMichael Chan __le16 resp_len; 8998894aa69aSMichael Chan u8 unused_0[7]; 8999894aa69aSMichael Chan u8 valid; 9000894aa69aSMichael Chan }; 9001894aa69aSMichael Chan 9002894aa69aSMichael Chan /* hwrm_struct_hdr (size:128b/16B) */ 900387c374deSMichael Chan struct hwrm_struct_hdr { 900487c374deSMichael Chan __le16 struct_id; 900587c374deSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9006f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9007f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9008f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9009f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9010f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9011f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 90123322479eSMichael Chan #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 90138eb992e8SMichael Chan #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9014f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 90156a17eb27SMichael Chan #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 901616db6323SMichael Chan #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 901716db6323SMichael Chan #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 901887c374deSMichael Chan __le16 len; 901987c374deSMichael Chan u8 version; 902087c374deSMichael Chan u8 count; 902187c374deSMichael Chan __le16 subtype; 902287c374deSMichael Chan __le16 next_offset; 902387c374deSMichael Chan #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9024894aa69aSMichael Chan u8 unused_0[6]; 902587c374deSMichael Chan }; 902687c374deSMichael Chan 9027894aa69aSMichael Chan /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9028f183886cSMichael Chan struct hwrm_struct_data_dcbx_app { 9029f183886cSMichael Chan __be16 protocol_id; 903087c374deSMichael Chan u8 protocol_selector; 9031f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9032f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9033f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9034f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9035894aa69aSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 903687c374deSMichael Chan u8 priority; 903787c374deSMichael Chan u8 valid; 903887c374deSMichael Chan u8 unused_0[3]; 903987c374deSMichael Chan }; 904087c374deSMichael Chan 9041894aa69aSMichael Chan /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9042894aa69aSMichael Chan struct hwrm_fw_set_structured_data_input { 9043894aa69aSMichael Chan __le16 req_type; 9044894aa69aSMichael Chan __le16 cmpl_ring; 9045894aa69aSMichael Chan __le16 seq_id; 9046894aa69aSMichael Chan __le16 target_id; 9047894aa69aSMichael Chan __le64 resp_addr; 9048894aa69aSMichael Chan __le64 src_data_addr; 9049894aa69aSMichael Chan __le16 data_len; 9050894aa69aSMichael Chan u8 hdr_cnt; 9051894aa69aSMichael Chan u8 unused_0[5]; 9052894aa69aSMichael Chan }; 9053894aa69aSMichael Chan 9054894aa69aSMichael Chan /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9055894aa69aSMichael Chan struct hwrm_fw_set_structured_data_output { 9056894aa69aSMichael Chan __le16 error_code; 9057894aa69aSMichael Chan __le16 req_type; 9058894aa69aSMichael Chan __le16 seq_id; 9059894aa69aSMichael Chan __le16 resp_len; 9060894aa69aSMichael Chan u8 unused_0[7]; 9061894aa69aSMichael Chan u8 valid; 9062894aa69aSMichael Chan }; 9063894aa69aSMichael Chan 9064894aa69aSMichael Chan /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9065894aa69aSMichael Chan struct hwrm_fw_set_structured_data_cmd_err { 9066894aa69aSMichael Chan u8 code; 9067894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9068894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9069894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9070894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9071894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9072894aa69aSMichael Chan u8 unused_0[7]; 9073894aa69aSMichael Chan }; 9074894aa69aSMichael Chan 9075894aa69aSMichael Chan /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9076894aa69aSMichael Chan struct hwrm_fw_get_structured_data_input { 9077894aa69aSMichael Chan __le16 req_type; 9078894aa69aSMichael Chan __le16 cmpl_ring; 9079894aa69aSMichael Chan __le16 seq_id; 9080894aa69aSMichael Chan __le16 target_id; 9081894aa69aSMichael Chan __le64 resp_addr; 9082894aa69aSMichael Chan __le64 dest_data_addr; 9083894aa69aSMichael Chan __le16 data_len; 9084894aa69aSMichael Chan __le16 structure_id; 9085894aa69aSMichael Chan __le16 subtype; 9086894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9087894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9088894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9089894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9090894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9091894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9092894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9093894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9094894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9095894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 9096894aa69aSMichael Chan u8 count; 9097894aa69aSMichael Chan u8 unused_0; 9098894aa69aSMichael Chan }; 9099894aa69aSMichael Chan 9100894aa69aSMichael Chan /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9101894aa69aSMichael Chan struct hwrm_fw_get_structured_data_output { 9102894aa69aSMichael Chan __le16 error_code; 9103894aa69aSMichael Chan __le16 req_type; 9104894aa69aSMichael Chan __le16 seq_id; 9105894aa69aSMichael Chan __le16 resp_len; 9106894aa69aSMichael Chan u8 hdr_cnt; 9107894aa69aSMichael Chan u8 unused_0[6]; 9108894aa69aSMichael Chan u8 valid; 9109894aa69aSMichael Chan }; 9110894aa69aSMichael Chan 9111894aa69aSMichael Chan /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9112894aa69aSMichael Chan struct hwrm_fw_get_structured_data_cmd_err { 9113894aa69aSMichael Chan u8 code; 9114894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9115894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9116894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9117894aa69aSMichael Chan u8 unused_0[7]; 9118894aa69aSMichael Chan }; 9119894aa69aSMichael Chan 912021e70778SMichael Chan /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 912121e70778SMichael Chan struct hwrm_fw_livepatch_query_input { 912221e70778SMichael Chan __le16 req_type; 912321e70778SMichael Chan __le16 cmpl_ring; 912421e70778SMichael Chan __le16 seq_id; 912521e70778SMichael Chan __le16 target_id; 912621e70778SMichael Chan __le64 resp_addr; 912721e70778SMichael Chan u8 fw_target; 912821e70778SMichael Chan #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 912921e70778SMichael Chan #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 913021e70778SMichael Chan #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 913121e70778SMichael Chan u8 unused_0[7]; 913221e70778SMichael Chan }; 913321e70778SMichael Chan 913421e70778SMichael Chan /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 913521e70778SMichael Chan struct hwrm_fw_livepatch_query_output { 913621e70778SMichael Chan __le16 error_code; 913721e70778SMichael Chan __le16 req_type; 913821e70778SMichael Chan __le16 seq_id; 913921e70778SMichael Chan __le16 resp_len; 914021e70778SMichael Chan char install_ver[32]; 914121e70778SMichael Chan char active_ver[32]; 914221e70778SMichael Chan __le16 status_flags; 914321e70778SMichael Chan #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 914421e70778SMichael Chan #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 914521e70778SMichael Chan u8 unused_0[5]; 914621e70778SMichael Chan u8 valid; 914721e70778SMichael Chan }; 914821e70778SMichael Chan 914921e70778SMichael Chan /* hwrm_fw_livepatch_input (size:256b/32B) */ 915021e70778SMichael Chan struct hwrm_fw_livepatch_input { 915121e70778SMichael Chan __le16 req_type; 915221e70778SMichael Chan __le16 cmpl_ring; 915321e70778SMichael Chan __le16 seq_id; 915421e70778SMichael Chan __le16 target_id; 915521e70778SMichael Chan __le64 resp_addr; 915621e70778SMichael Chan u8 opcode; 915721e70778SMichael Chan #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 915821e70778SMichael Chan #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 915921e70778SMichael Chan #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 916021e70778SMichael Chan u8 fw_target; 916121e70778SMichael Chan #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 916221e70778SMichael Chan #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 916321e70778SMichael Chan #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 916421e70778SMichael Chan u8 loadtype; 916521e70778SMichael Chan #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 916621e70778SMichael Chan #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 916721e70778SMichael Chan #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 916821e70778SMichael Chan u8 flags; 916921e70778SMichael Chan __le32 patch_len; 917021e70778SMichael Chan __le64 host_addr; 917121e70778SMichael Chan }; 917221e70778SMichael Chan 917321e70778SMichael Chan /* hwrm_fw_livepatch_output (size:128b/16B) */ 917421e70778SMichael Chan struct hwrm_fw_livepatch_output { 917521e70778SMichael Chan __le16 error_code; 917621e70778SMichael Chan __le16 req_type; 917721e70778SMichael Chan __le16 seq_id; 917821e70778SMichael Chan __le16 resp_len; 917921e70778SMichael Chan u8 unused_0[7]; 918021e70778SMichael Chan u8 valid; 918121e70778SMichael Chan }; 918221e70778SMichael Chan 918321e70778SMichael Chan /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 918421e70778SMichael Chan struct hwrm_fw_livepatch_cmd_err { 918521e70778SMichael Chan u8 code; 918621e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 918721e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 918821e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 918921e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 919021e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 919121e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 919221e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 919321e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 919421e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 919521e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 919621e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 919721e70778SMichael Chan u8 unused_0[7]; 919821e70778SMichael Chan }; 919921e70778SMichael Chan 9200894aa69aSMichael Chan /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9201894aa69aSMichael Chan struct hwrm_exec_fwd_resp_input { 9202894aa69aSMichael Chan __le16 req_type; 9203894aa69aSMichael Chan __le16 cmpl_ring; 9204894aa69aSMichael Chan __le16 seq_id; 9205894aa69aSMichael Chan __le16 target_id; 9206894aa69aSMichael Chan __le64 resp_addr; 9207894aa69aSMichael Chan __le32 encap_request[26]; 9208894aa69aSMichael Chan __le16 encap_resp_target_id; 9209894aa69aSMichael Chan u8 unused_0[6]; 9210894aa69aSMichael Chan }; 9211894aa69aSMichael Chan 9212894aa69aSMichael Chan /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9213894aa69aSMichael Chan struct hwrm_exec_fwd_resp_output { 9214894aa69aSMichael Chan __le16 error_code; 9215894aa69aSMichael Chan __le16 req_type; 9216894aa69aSMichael Chan __le16 seq_id; 9217894aa69aSMichael Chan __le16 resp_len; 9218894aa69aSMichael Chan u8 unused_0[7]; 9219894aa69aSMichael Chan u8 valid; 9220894aa69aSMichael Chan }; 9221894aa69aSMichael Chan 9222894aa69aSMichael Chan /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9223894aa69aSMichael Chan struct hwrm_reject_fwd_resp_input { 9224894aa69aSMichael Chan __le16 req_type; 9225894aa69aSMichael Chan __le16 cmpl_ring; 9226894aa69aSMichael Chan __le16 seq_id; 9227894aa69aSMichael Chan __le16 target_id; 9228894aa69aSMichael Chan __le64 resp_addr; 9229894aa69aSMichael Chan __le32 encap_request[26]; 9230894aa69aSMichael Chan __le16 encap_resp_target_id; 9231894aa69aSMichael Chan u8 unused_0[6]; 9232894aa69aSMichael Chan }; 9233894aa69aSMichael Chan 9234894aa69aSMichael Chan /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9235894aa69aSMichael Chan struct hwrm_reject_fwd_resp_output { 9236894aa69aSMichael Chan __le16 error_code; 9237894aa69aSMichael Chan __le16 req_type; 9238894aa69aSMichael Chan __le16 seq_id; 9239894aa69aSMichael Chan __le16 resp_len; 9240894aa69aSMichael Chan u8 unused_0[7]; 9241894aa69aSMichael Chan u8 valid; 9242894aa69aSMichael Chan }; 9243894aa69aSMichael Chan 9244894aa69aSMichael Chan /* hwrm_fwd_resp_input (size:1024b/128B) */ 9245894aa69aSMichael Chan struct hwrm_fwd_resp_input { 9246894aa69aSMichael Chan __le16 req_type; 9247894aa69aSMichael Chan __le16 cmpl_ring; 9248894aa69aSMichael Chan __le16 seq_id; 9249894aa69aSMichael Chan __le16 target_id; 9250894aa69aSMichael Chan __le64 resp_addr; 9251894aa69aSMichael Chan __le16 encap_resp_target_id; 9252894aa69aSMichael Chan __le16 encap_resp_cmpl_ring; 9253894aa69aSMichael Chan __le16 encap_resp_len; 9254894aa69aSMichael Chan u8 unused_0; 9255894aa69aSMichael Chan u8 unused_1; 9256894aa69aSMichael Chan __le64 encap_resp_addr; 9257894aa69aSMichael Chan __le32 encap_resp[24]; 9258894aa69aSMichael Chan }; 9259894aa69aSMichael Chan 9260894aa69aSMichael Chan /* hwrm_fwd_resp_output (size:128b/16B) */ 9261894aa69aSMichael Chan struct hwrm_fwd_resp_output { 9262894aa69aSMichael Chan __le16 error_code; 9263894aa69aSMichael Chan __le16 req_type; 9264894aa69aSMichael Chan __le16 seq_id; 9265894aa69aSMichael Chan __le16 resp_len; 9266894aa69aSMichael Chan u8 unused_0[7]; 9267894aa69aSMichael Chan u8 valid; 9268894aa69aSMichael Chan }; 9269894aa69aSMichael Chan 9270894aa69aSMichael Chan /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9271894aa69aSMichael Chan struct hwrm_fwd_async_event_cmpl_input { 9272894aa69aSMichael Chan __le16 req_type; 9273894aa69aSMichael Chan __le16 cmpl_ring; 9274894aa69aSMichael Chan __le16 seq_id; 9275894aa69aSMichael Chan __le16 target_id; 9276894aa69aSMichael Chan __le64 resp_addr; 9277894aa69aSMichael Chan __le16 encap_async_event_target_id; 9278894aa69aSMichael Chan u8 unused_0[6]; 9279894aa69aSMichael Chan __le32 encap_async_event_cmpl[4]; 9280894aa69aSMichael Chan }; 9281894aa69aSMichael Chan 9282894aa69aSMichael Chan /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9283894aa69aSMichael Chan struct hwrm_fwd_async_event_cmpl_output { 9284894aa69aSMichael Chan __le16 error_code; 9285894aa69aSMichael Chan __le16 req_type; 9286894aa69aSMichael Chan __le16 seq_id; 9287894aa69aSMichael Chan __le16 resp_len; 9288894aa69aSMichael Chan u8 unused_0[7]; 9289894aa69aSMichael Chan u8 valid; 9290894aa69aSMichael Chan }; 9291894aa69aSMichael Chan 9292894aa69aSMichael Chan /* hwrm_temp_monitor_query_input (size:128b/16B) */ 9293894aa69aSMichael Chan struct hwrm_temp_monitor_query_input { 9294894aa69aSMichael Chan __le16 req_type; 9295894aa69aSMichael Chan __le16 cmpl_ring; 9296894aa69aSMichael Chan __le16 seq_id; 9297894aa69aSMichael Chan __le16 target_id; 9298894aa69aSMichael Chan __le64 resp_addr; 9299894aa69aSMichael Chan }; 9300894aa69aSMichael Chan 9301894aa69aSMichael Chan /* hwrm_temp_monitor_query_output (size:128b/16B) */ 9302894aa69aSMichael Chan struct hwrm_temp_monitor_query_output { 9303894aa69aSMichael Chan __le16 error_code; 9304894aa69aSMichael Chan __le16 req_type; 9305894aa69aSMichael Chan __le16 seq_id; 9306894aa69aSMichael Chan __le16 resp_len; 9307894aa69aSMichael Chan u8 temp; 930872e0c9f9SMichael Chan u8 phy_temp; 930972e0c9f9SMichael Chan u8 om_temp; 931072e0c9f9SMichael Chan u8 flags; 931172e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 931272e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 931372e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 931472e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 931578eeadb8SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 931678eeadb8SMichael Chan u8 temp2; 931778eeadb8SMichael Chan u8 phy_temp2; 931878eeadb8SMichael Chan u8 om_temp2; 9319894aa69aSMichael Chan u8 valid; 9320894aa69aSMichael Chan }; 9321894aa69aSMichael Chan 9322894aa69aSMichael Chan /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9323894aa69aSMichael Chan struct hwrm_wol_filter_alloc_input { 9324894aa69aSMichael Chan __le16 req_type; 9325894aa69aSMichael Chan __le16 cmpl_ring; 9326894aa69aSMichael Chan __le16 seq_id; 9327894aa69aSMichael Chan __le16 target_id; 9328894aa69aSMichael Chan __le64 resp_addr; 9329894aa69aSMichael Chan __le32 flags; 9330894aa69aSMichael Chan __le32 enables; 9331894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9332894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9333894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9334894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9335894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9336894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9337894aa69aSMichael Chan __le16 port_id; 9338894aa69aSMichael Chan u8 wol_type; 9339894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9340894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9341894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9342894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9343894aa69aSMichael Chan u8 unused_0[5]; 9344894aa69aSMichael Chan u8 mac_address[6]; 9345894aa69aSMichael Chan __le16 pattern_offset; 9346894aa69aSMichael Chan __le16 pattern_buf_size; 9347894aa69aSMichael Chan __le16 pattern_mask_size; 9348894aa69aSMichael Chan u8 unused_1[4]; 9349894aa69aSMichael Chan __le64 pattern_buf_addr; 9350894aa69aSMichael Chan __le64 pattern_mask_addr; 9351894aa69aSMichael Chan }; 9352894aa69aSMichael Chan 9353894aa69aSMichael Chan /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9354894aa69aSMichael Chan struct hwrm_wol_filter_alloc_output { 9355894aa69aSMichael Chan __le16 error_code; 9356894aa69aSMichael Chan __le16 req_type; 9357894aa69aSMichael Chan __le16 seq_id; 9358894aa69aSMichael Chan __le16 resp_len; 9359894aa69aSMichael Chan u8 wol_filter_id; 9360894aa69aSMichael Chan u8 unused_0[6]; 9361894aa69aSMichael Chan u8 valid; 9362894aa69aSMichael Chan }; 9363894aa69aSMichael Chan 9364894aa69aSMichael Chan /* hwrm_wol_filter_free_input (size:256b/32B) */ 9365894aa69aSMichael Chan struct hwrm_wol_filter_free_input { 9366894aa69aSMichael Chan __le16 req_type; 9367894aa69aSMichael Chan __le16 cmpl_ring; 9368894aa69aSMichael Chan __le16 seq_id; 9369894aa69aSMichael Chan __le16 target_id; 9370894aa69aSMichael Chan __le64 resp_addr; 9371894aa69aSMichael Chan __le32 flags; 9372894aa69aSMichael Chan #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9373894aa69aSMichael Chan __le32 enables; 9374894aa69aSMichael Chan #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 9375894aa69aSMichael Chan __le16 port_id; 9376894aa69aSMichael Chan u8 wol_filter_id; 9377894aa69aSMichael Chan u8 unused_0[5]; 9378894aa69aSMichael Chan }; 9379894aa69aSMichael Chan 9380894aa69aSMichael Chan /* hwrm_wol_filter_free_output (size:128b/16B) */ 9381894aa69aSMichael Chan struct hwrm_wol_filter_free_output { 9382894aa69aSMichael Chan __le16 error_code; 9383894aa69aSMichael Chan __le16 req_type; 9384894aa69aSMichael Chan __le16 seq_id; 9385894aa69aSMichael Chan __le16 resp_len; 9386894aa69aSMichael Chan u8 unused_0[7]; 9387894aa69aSMichael Chan u8 valid; 9388894aa69aSMichael Chan }; 9389894aa69aSMichael Chan 9390894aa69aSMichael Chan /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 9391894aa69aSMichael Chan struct hwrm_wol_filter_qcfg_input { 9392894aa69aSMichael Chan __le16 req_type; 9393894aa69aSMichael Chan __le16 cmpl_ring; 9394894aa69aSMichael Chan __le16 seq_id; 9395894aa69aSMichael Chan __le16 target_id; 9396894aa69aSMichael Chan __le64 resp_addr; 9397894aa69aSMichael Chan __le16 port_id; 9398894aa69aSMichael Chan __le16 handle; 9399894aa69aSMichael Chan u8 unused_0[4]; 9400894aa69aSMichael Chan __le64 pattern_buf_addr; 9401894aa69aSMichael Chan __le16 pattern_buf_size; 9402894aa69aSMichael Chan u8 unused_1[6]; 9403894aa69aSMichael Chan __le64 pattern_mask_addr; 9404894aa69aSMichael Chan __le16 pattern_mask_size; 9405894aa69aSMichael Chan u8 unused_2[6]; 9406894aa69aSMichael Chan }; 9407894aa69aSMichael Chan 9408894aa69aSMichael Chan /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 9409894aa69aSMichael Chan struct hwrm_wol_filter_qcfg_output { 9410894aa69aSMichael Chan __le16 error_code; 9411894aa69aSMichael Chan __le16 req_type; 9412894aa69aSMichael Chan __le16 seq_id; 9413894aa69aSMichael Chan __le16 resp_len; 9414894aa69aSMichael Chan __le16 next_handle; 9415894aa69aSMichael Chan u8 wol_filter_id; 9416894aa69aSMichael Chan u8 wol_type; 9417894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 9418894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 9419894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 9420894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 9421894aa69aSMichael Chan __le32 unused_0; 9422894aa69aSMichael Chan u8 mac_address[6]; 9423894aa69aSMichael Chan __le16 pattern_offset; 9424894aa69aSMichael Chan __le16 pattern_size; 9425894aa69aSMichael Chan __le16 pattern_mask_size; 9426894aa69aSMichael Chan u8 unused_1[3]; 9427894aa69aSMichael Chan u8 valid; 9428894aa69aSMichael Chan }; 9429894aa69aSMichael Chan 9430894aa69aSMichael Chan /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 9431894aa69aSMichael Chan struct hwrm_wol_reason_qcfg_input { 9432894aa69aSMichael Chan __le16 req_type; 9433894aa69aSMichael Chan __le16 cmpl_ring; 9434894aa69aSMichael Chan __le16 seq_id; 9435894aa69aSMichael Chan __le16 target_id; 9436894aa69aSMichael Chan __le64 resp_addr; 9437894aa69aSMichael Chan __le16 port_id; 9438894aa69aSMichael Chan u8 unused_0[6]; 9439894aa69aSMichael Chan __le64 wol_pkt_buf_addr; 9440894aa69aSMichael Chan __le16 wol_pkt_buf_size; 9441894aa69aSMichael Chan u8 unused_1[6]; 9442894aa69aSMichael Chan }; 9443894aa69aSMichael Chan 9444894aa69aSMichael Chan /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 9445894aa69aSMichael Chan struct hwrm_wol_reason_qcfg_output { 9446894aa69aSMichael Chan __le16 error_code; 9447894aa69aSMichael Chan __le16 req_type; 9448894aa69aSMichael Chan __le16 seq_id; 9449894aa69aSMichael Chan __le16 resp_len; 9450894aa69aSMichael Chan u8 wol_filter_id; 9451894aa69aSMichael Chan u8 wol_reason; 9452894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 9453894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 9454894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 9455894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 9456894aa69aSMichael Chan u8 wol_pkt_len; 9457894aa69aSMichael Chan u8 unused_0[4]; 9458894aa69aSMichael Chan u8 valid; 9459894aa69aSMichael Chan }; 9460894aa69aSMichael Chan 9461bfc6e5fbSMichael Chan /* hwrm_dbg_read_direct_input (size:256b/32B) */ 9462bfc6e5fbSMichael Chan struct hwrm_dbg_read_direct_input { 9463bfc6e5fbSMichael Chan __le16 req_type; 9464bfc6e5fbSMichael Chan __le16 cmpl_ring; 9465bfc6e5fbSMichael Chan __le16 seq_id; 9466bfc6e5fbSMichael Chan __le16 target_id; 9467bfc6e5fbSMichael Chan __le64 resp_addr; 9468bfc6e5fbSMichael Chan __le64 host_dest_addr; 9469bfc6e5fbSMichael Chan __le32 read_addr; 9470bfc6e5fbSMichael Chan __le32 read_len32; 9471bfc6e5fbSMichael Chan }; 9472bfc6e5fbSMichael Chan 9473bfc6e5fbSMichael Chan /* hwrm_dbg_read_direct_output (size:128b/16B) */ 9474bfc6e5fbSMichael Chan struct hwrm_dbg_read_direct_output { 9475bfc6e5fbSMichael Chan __le16 error_code; 9476bfc6e5fbSMichael Chan __le16 req_type; 9477bfc6e5fbSMichael Chan __le16 seq_id; 9478bfc6e5fbSMichael Chan __le16 resp_len; 9479bfc6e5fbSMichael Chan __le32 crc32; 9480bfc6e5fbSMichael Chan u8 unused_0[3]; 9481bfc6e5fbSMichael Chan u8 valid; 9482bfc6e5fbSMichael Chan }; 9483bfc6e5fbSMichael Chan 94849d6b648cSMichael Chan /* hwrm_dbg_qcaps_input (size:192b/24B) */ 94859d6b648cSMichael Chan struct hwrm_dbg_qcaps_input { 94869d6b648cSMichael Chan __le16 req_type; 94879d6b648cSMichael Chan __le16 cmpl_ring; 94889d6b648cSMichael Chan __le16 seq_id; 94899d6b648cSMichael Chan __le16 target_id; 94909d6b648cSMichael Chan __le64 resp_addr; 94919d6b648cSMichael Chan __le16 fid; 94929d6b648cSMichael Chan u8 unused_0[6]; 94939d6b648cSMichael Chan }; 94949d6b648cSMichael Chan 94959d6b648cSMichael Chan /* hwrm_dbg_qcaps_output (size:192b/24B) */ 94969d6b648cSMichael Chan struct hwrm_dbg_qcaps_output { 94979d6b648cSMichael Chan __le16 error_code; 94989d6b648cSMichael Chan __le16 req_type; 94999d6b648cSMichael Chan __le16 seq_id; 95009d6b648cSMichael Chan __le16 resp_len; 95019d6b648cSMichael Chan __le16 fid; 95029d6b648cSMichael Chan u8 unused_0[2]; 95039d6b648cSMichael Chan __le32 coredump_component_disable_caps; 95049d6b648cSMichael Chan #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 95059d6b648cSMichael Chan __le32 flags; 95069d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 95079d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 95089d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 950978eeadb8SMichael Chan #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 95109d6b648cSMichael Chan u8 unused_1[3]; 95119d6b648cSMichael Chan u8 valid; 95129d6b648cSMichael Chan }; 95139d6b648cSMichael Chan 95149d6b648cSMichael Chan /* hwrm_dbg_qcfg_input (size:192b/24B) */ 95159d6b648cSMichael Chan struct hwrm_dbg_qcfg_input { 95169d6b648cSMichael Chan __le16 req_type; 95179d6b648cSMichael Chan __le16 cmpl_ring; 95189d6b648cSMichael Chan __le16 seq_id; 95199d6b648cSMichael Chan __le16 target_id; 95209d6b648cSMichael Chan __le64 resp_addr; 95219d6b648cSMichael Chan __le16 fid; 95229d6b648cSMichael Chan __le16 flags; 95239d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 95249d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 95259d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 95269d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 95279d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 95289d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 95299d6b648cSMichael Chan __le32 coredump_component_disable_flags; 95309d6b648cSMichael Chan #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 95319d6b648cSMichael Chan }; 95329d6b648cSMichael Chan 95339d6b648cSMichael Chan /* hwrm_dbg_qcfg_output (size:256b/32B) */ 95349d6b648cSMichael Chan struct hwrm_dbg_qcfg_output { 95359d6b648cSMichael Chan __le16 error_code; 95369d6b648cSMichael Chan __le16 req_type; 95379d6b648cSMichael Chan __le16 seq_id; 95389d6b648cSMichael Chan __le16 resp_len; 95399d6b648cSMichael Chan __le16 fid; 95409d6b648cSMichael Chan u8 unused_0[2]; 95419d6b648cSMichael Chan __le32 coredump_size; 95429d6b648cSMichael Chan __le32 flags; 95439d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 95449d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 95459d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 95469d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 95479d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 95489d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 95499d6b648cSMichael Chan __le16 async_cmpl_ring; 95509d6b648cSMichael Chan u8 unused_2[2]; 95519d6b648cSMichael Chan __le32 crashdump_size; 95529d6b648cSMichael Chan u8 unused_3[3]; 95539d6b648cSMichael Chan u8 valid; 95549d6b648cSMichael Chan }; 95559d6b648cSMichael Chan 95562895c153SMichael Chan /* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 95572895c153SMichael Chan struct hwrm_dbg_crashdump_medium_cfg_input { 95582895c153SMichael Chan __le16 req_type; 95592895c153SMichael Chan __le16 cmpl_ring; 95602895c153SMichael Chan __le16 seq_id; 95612895c153SMichael Chan __le16 target_id; 95622895c153SMichael Chan __le64 resp_addr; 95632895c153SMichael Chan __le16 output_dest_flags; 95642895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 95652895c153SMichael Chan __le16 pg_size_lvl; 95662895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 95672895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 95682895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 95692895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 95702895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 95712895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 95722895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 95732895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 95742895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 95752895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 95762895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 95772895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 95782895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 95792895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 95802895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 95812895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 95822895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 95832895c153SMichael Chan __le32 size; 95842895c153SMichael Chan __le32 coredump_component_disable_flags; 95852895c153SMichael Chan #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 95862895c153SMichael Chan __le32 unused_0; 95872895c153SMichael Chan __le64 pbl; 95882895c153SMichael Chan }; 95892895c153SMichael Chan 95902895c153SMichael Chan /* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 95912895c153SMichael Chan struct hwrm_dbg_crashdump_medium_cfg_output { 95922895c153SMichael Chan __le16 error_code; 95932895c153SMichael Chan __le16 req_type; 95942895c153SMichael Chan __le16 seq_id; 95952895c153SMichael Chan __le16 resp_len; 95962895c153SMichael Chan u8 unused_1[7]; 95972895c153SMichael Chan u8 valid; 95982895c153SMichael Chan }; 95992895c153SMichael Chan 96006fc92c33SMichael Chan /* coredump_segment_record (size:128b/16B) */ 96016fc92c33SMichael Chan struct coredump_segment_record { 96026fc92c33SMichael Chan __le16 component_id; 96036fc92c33SMichael Chan __le16 segment_id; 96046fc92c33SMichael Chan __le16 max_instances; 96056fc92c33SMichael Chan u8 version_hi; 96066fc92c33SMichael Chan u8 version_low; 96076fc92c33SMichael Chan u8 seg_flags; 96082792b5b9SMichael Chan u8 compress_flags; 96092792b5b9SMichael Chan #define SFLAG_COMPRESSED_ZLIB 0x1UL 9610bfc6e5fbSMichael Chan u8 unused_0[2]; 9611bfc6e5fbSMichael Chan __le32 segment_len; 96126fc92c33SMichael Chan }; 96136fc92c33SMichael Chan 96146fc92c33SMichael Chan /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 96156fc92c33SMichael Chan struct hwrm_dbg_coredump_list_input { 96166fc92c33SMichael Chan __le16 req_type; 96176fc92c33SMichael Chan __le16 cmpl_ring; 96186fc92c33SMichael Chan __le16 seq_id; 96196fc92c33SMichael Chan __le16 target_id; 96206fc92c33SMichael Chan __le64 resp_addr; 96216fc92c33SMichael Chan __le64 host_dest_addr; 96226fc92c33SMichael Chan __le32 host_buf_len; 96236fc92c33SMichael Chan __le16 seq_no; 96244a50ddc2SMichael Chan u8 flags; 96254a50ddc2SMichael Chan #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 96264a50ddc2SMichael Chan u8 unused_0[1]; 96276fc92c33SMichael Chan }; 96286fc92c33SMichael Chan 96296fc92c33SMichael Chan /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 96306fc92c33SMichael Chan struct hwrm_dbg_coredump_list_output { 96316fc92c33SMichael Chan __le16 error_code; 96326fc92c33SMichael Chan __le16 req_type; 96336fc92c33SMichael Chan __le16 seq_id; 96346fc92c33SMichael Chan __le16 resp_len; 96356fc92c33SMichael Chan u8 flags; 96366fc92c33SMichael Chan #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 96376fc92c33SMichael Chan u8 unused_0; 96386fc92c33SMichael Chan __le16 total_segments; 96396fc92c33SMichael Chan __le16 data_len; 96406fc92c33SMichael Chan u8 unused_1; 96416fc92c33SMichael Chan u8 valid; 96426fc92c33SMichael Chan }; 96436fc92c33SMichael Chan 96446fc92c33SMichael Chan /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 96456fc92c33SMichael Chan struct hwrm_dbg_coredump_initiate_input { 96466fc92c33SMichael Chan __le16 req_type; 96476fc92c33SMichael Chan __le16 cmpl_ring; 96486fc92c33SMichael Chan __le16 seq_id; 96496fc92c33SMichael Chan __le16 target_id; 96506fc92c33SMichael Chan __le64 resp_addr; 96516fc92c33SMichael Chan __le16 component_id; 96526fc92c33SMichael Chan __le16 segment_id; 96536fc92c33SMichael Chan __le16 instance; 96546fc92c33SMichael Chan __le16 unused_0; 96556fc92c33SMichael Chan u8 seg_flags; 96566fc92c33SMichael Chan u8 unused_1[7]; 96576fc92c33SMichael Chan }; 96586fc92c33SMichael Chan 96596fc92c33SMichael Chan /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 96606fc92c33SMichael Chan struct hwrm_dbg_coredump_initiate_output { 96616fc92c33SMichael Chan __le16 error_code; 96626fc92c33SMichael Chan __le16 req_type; 96636fc92c33SMichael Chan __le16 seq_id; 96646fc92c33SMichael Chan __le16 resp_len; 96656fc92c33SMichael Chan u8 unused_0[7]; 96666fc92c33SMichael Chan u8 valid; 96676fc92c33SMichael Chan }; 96686fc92c33SMichael Chan 96696fc92c33SMichael Chan /* coredump_data_hdr (size:128b/16B) */ 96706fc92c33SMichael Chan struct coredump_data_hdr { 96716fc92c33SMichael Chan __le32 address; 96726fc92c33SMichael Chan __le32 flags_length; 967316db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 967416db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 967516db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 96766fc92c33SMichael Chan __le32 instance; 96776fc92c33SMichael Chan __le32 next_offset; 96786fc92c33SMichael Chan }; 96796fc92c33SMichael Chan 96806fc92c33SMichael Chan /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 96816fc92c33SMichael Chan struct hwrm_dbg_coredump_retrieve_input { 96826fc92c33SMichael Chan __le16 req_type; 96836fc92c33SMichael Chan __le16 cmpl_ring; 96846fc92c33SMichael Chan __le16 seq_id; 96856fc92c33SMichael Chan __le16 target_id; 96866fc92c33SMichael Chan __le64 resp_addr; 96876fc92c33SMichael Chan __le64 host_dest_addr; 96886fc92c33SMichael Chan __le32 host_buf_len; 96896fc92c33SMichael Chan __le32 unused_0; 96906fc92c33SMichael Chan __le16 component_id; 96916fc92c33SMichael Chan __le16 segment_id; 96926fc92c33SMichael Chan __le16 instance; 96936fc92c33SMichael Chan __le16 unused_1; 96946fc92c33SMichael Chan u8 seg_flags; 96956fc92c33SMichael Chan u8 unused_2; 96966fc92c33SMichael Chan __le16 unused_3; 96976fc92c33SMichael Chan __le32 unused_4; 96986fc92c33SMichael Chan __le32 seq_no; 96996fc92c33SMichael Chan __le32 unused_5; 97006fc92c33SMichael Chan }; 97016fc92c33SMichael Chan 97026fc92c33SMichael Chan /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 97036fc92c33SMichael Chan struct hwrm_dbg_coredump_retrieve_output { 97046fc92c33SMichael Chan __le16 error_code; 97056fc92c33SMichael Chan __le16 req_type; 97066fc92c33SMichael Chan __le16 seq_id; 97076fc92c33SMichael Chan __le16 resp_len; 97086fc92c33SMichael Chan u8 flags; 97096fc92c33SMichael Chan #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 97106fc92c33SMichael Chan u8 unused_0; 97116fc92c33SMichael Chan __le16 data_len; 97126fc92c33SMichael Chan u8 unused_1[3]; 97136fc92c33SMichael Chan u8 valid; 97146fc92c33SMichael Chan }; 97156fc92c33SMichael Chan 971631d357c0SMichael Chan /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 971731d357c0SMichael Chan struct hwrm_dbg_ring_info_get_input { 971831d357c0SMichael Chan __le16 req_type; 971931d357c0SMichael Chan __le16 cmpl_ring; 972031d357c0SMichael Chan __le16 seq_id; 972131d357c0SMichael Chan __le16 target_id; 972231d357c0SMichael Chan __le64 resp_addr; 972331d357c0SMichael Chan u8 ring_type; 972431d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 972531d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 972631d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9727bfc6e5fbSMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9728bfc6e5fbSMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 972931d357c0SMichael Chan u8 unused_0[3]; 973031d357c0SMichael Chan __le32 fw_ring_id; 973131d357c0SMichael Chan }; 973231d357c0SMichael Chan 973331d357c0SMichael Chan /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 973431d357c0SMichael Chan struct hwrm_dbg_ring_info_get_output { 973531d357c0SMichael Chan __le16 error_code; 973631d357c0SMichael Chan __le16 req_type; 973731d357c0SMichael Chan __le16 seq_id; 973831d357c0SMichael Chan __le16 resp_len; 973931d357c0SMichael Chan __le32 producer_index; 974031d357c0SMichael Chan __le32 consumer_index; 9741bfc6e5fbSMichael Chan __le32 cag_vector_ctrl; 9742bfc6e5fbSMichael Chan u8 unused_0[3]; 974331d357c0SMichael Chan u8 valid; 974431d357c0SMichael Chan }; 974531d357c0SMichael Chan 9746894aa69aSMichael Chan /* hwrm_nvm_read_input (size:320b/40B) */ 9747894aa69aSMichael Chan struct hwrm_nvm_read_input { 9748894aa69aSMichael Chan __le16 req_type; 9749894aa69aSMichael Chan __le16 cmpl_ring; 9750894aa69aSMichael Chan __le16 seq_id; 9751894aa69aSMichael Chan __le16 target_id; 9752894aa69aSMichael Chan __le64 resp_addr; 9753894aa69aSMichael Chan __le64 host_dest_addr; 9754894aa69aSMichael Chan __le16 dir_idx; 9755894aa69aSMichael Chan u8 unused_0[2]; 9756894aa69aSMichael Chan __le32 offset; 9757894aa69aSMichael Chan __le32 len; 9758894aa69aSMichael Chan u8 unused_1[4]; 9759894aa69aSMichael Chan }; 9760894aa69aSMichael Chan 9761894aa69aSMichael Chan /* hwrm_nvm_read_output (size:128b/16B) */ 9762894aa69aSMichael Chan struct hwrm_nvm_read_output { 9763894aa69aSMichael Chan __le16 error_code; 9764894aa69aSMichael Chan __le16 req_type; 9765894aa69aSMichael Chan __le16 seq_id; 9766894aa69aSMichael Chan __le16 resp_len; 9767894aa69aSMichael Chan u8 unused_0[7]; 9768894aa69aSMichael Chan u8 valid; 9769894aa69aSMichael Chan }; 9770894aa69aSMichael Chan 9771894aa69aSMichael Chan /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9772894aa69aSMichael Chan struct hwrm_nvm_get_dir_entries_input { 9773894aa69aSMichael Chan __le16 req_type; 9774894aa69aSMichael Chan __le16 cmpl_ring; 9775894aa69aSMichael Chan __le16 seq_id; 9776894aa69aSMichael Chan __le16 target_id; 9777894aa69aSMichael Chan __le64 resp_addr; 9778894aa69aSMichael Chan __le64 host_dest_addr; 9779894aa69aSMichael Chan }; 9780894aa69aSMichael Chan 9781894aa69aSMichael Chan /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9782894aa69aSMichael Chan struct hwrm_nvm_get_dir_entries_output { 9783894aa69aSMichael Chan __le16 error_code; 9784894aa69aSMichael Chan __le16 req_type; 9785894aa69aSMichael Chan __le16 seq_id; 9786894aa69aSMichael Chan __le16 resp_len; 9787894aa69aSMichael Chan u8 unused_0[7]; 9788894aa69aSMichael Chan u8 valid; 9789894aa69aSMichael Chan }; 9790894aa69aSMichael Chan 9791894aa69aSMichael Chan /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9792894aa69aSMichael Chan struct hwrm_nvm_get_dir_info_input { 9793894aa69aSMichael Chan __le16 req_type; 9794894aa69aSMichael Chan __le16 cmpl_ring; 9795894aa69aSMichael Chan __le16 seq_id; 9796894aa69aSMichael Chan __le16 target_id; 9797894aa69aSMichael Chan __le64 resp_addr; 9798894aa69aSMichael Chan }; 9799894aa69aSMichael Chan 9800894aa69aSMichael Chan /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9801894aa69aSMichael Chan struct hwrm_nvm_get_dir_info_output { 9802894aa69aSMichael Chan __le16 error_code; 9803894aa69aSMichael Chan __le16 req_type; 9804894aa69aSMichael Chan __le16 seq_id; 9805894aa69aSMichael Chan __le16 resp_len; 9806894aa69aSMichael Chan __le32 entries; 9807894aa69aSMichael Chan __le32 entry_length; 9808894aa69aSMichael Chan u8 unused_0[7]; 9809894aa69aSMichael Chan u8 valid; 9810894aa69aSMichael Chan }; 9811894aa69aSMichael Chan 9812fbfee257SMichael Chan /* hwrm_nvm_write_input (size:448b/56B) */ 9813894aa69aSMichael Chan struct hwrm_nvm_write_input { 9814894aa69aSMichael Chan __le16 req_type; 9815894aa69aSMichael Chan __le16 cmpl_ring; 9816894aa69aSMichael Chan __le16 seq_id; 9817894aa69aSMichael Chan __le16 target_id; 9818894aa69aSMichael Chan __le64 resp_addr; 9819894aa69aSMichael Chan __le64 host_src_addr; 9820894aa69aSMichael Chan __le16 dir_type; 9821894aa69aSMichael Chan __le16 dir_ordinal; 9822894aa69aSMichael Chan __le16 dir_ext; 9823894aa69aSMichael Chan __le16 dir_attr; 9824894aa69aSMichael Chan __le32 dir_data_length; 9825894aa69aSMichael Chan __le16 option; 9826894aa69aSMichael Chan __le16 flags; 9827894aa69aSMichael Chan #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9828fbfee257SMichael Chan #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9829fbfee257SMichael Chan #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9830894aa69aSMichael Chan __le32 dir_item_length; 9831fbfee257SMichael Chan __le32 offset; 9832fbfee257SMichael Chan __le32 len; 9833894aa69aSMichael Chan __le32 unused_0; 9834894aa69aSMichael Chan }; 9835894aa69aSMichael Chan 9836894aa69aSMichael Chan /* hwrm_nvm_write_output (size:128b/16B) */ 9837894aa69aSMichael Chan struct hwrm_nvm_write_output { 9838894aa69aSMichael Chan __le16 error_code; 9839894aa69aSMichael Chan __le16 req_type; 9840894aa69aSMichael Chan __le16 seq_id; 9841894aa69aSMichael Chan __le16 resp_len; 9842894aa69aSMichael Chan __le32 dir_item_length; 9843894aa69aSMichael Chan __le16 dir_idx; 9844894aa69aSMichael Chan u8 unused_0; 9845894aa69aSMichael Chan u8 valid; 9846894aa69aSMichael Chan }; 9847894aa69aSMichael Chan 9848894aa69aSMichael Chan /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9849894aa69aSMichael Chan struct hwrm_nvm_write_cmd_err { 9850894aa69aSMichael Chan u8 code; 9851894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9852894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9853894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9854894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9855894aa69aSMichael Chan u8 unused_0[7]; 9856894aa69aSMichael Chan }; 9857894aa69aSMichael Chan 9858894aa69aSMichael Chan /* hwrm_nvm_modify_input (size:320b/40B) */ 9859894aa69aSMichael Chan struct hwrm_nvm_modify_input { 9860894aa69aSMichael Chan __le16 req_type; 9861894aa69aSMichael Chan __le16 cmpl_ring; 9862894aa69aSMichael Chan __le16 seq_id; 9863894aa69aSMichael Chan __le16 target_id; 9864894aa69aSMichael Chan __le64 resp_addr; 9865894aa69aSMichael Chan __le64 host_src_addr; 9866894aa69aSMichael Chan __le16 dir_idx; 9867460c2577SMichael Chan __le16 flags; 9868460c2577SMichael Chan #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9869460c2577SMichael Chan #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9870894aa69aSMichael Chan __le32 offset; 9871894aa69aSMichael Chan __le32 len; 9872894aa69aSMichael Chan u8 unused_1[4]; 9873894aa69aSMichael Chan }; 9874894aa69aSMichael Chan 9875894aa69aSMichael Chan /* hwrm_nvm_modify_output (size:128b/16B) */ 9876894aa69aSMichael Chan struct hwrm_nvm_modify_output { 9877894aa69aSMichael Chan __le16 error_code; 9878894aa69aSMichael Chan __le16 req_type; 9879894aa69aSMichael Chan __le16 seq_id; 9880894aa69aSMichael Chan __le16 resp_len; 9881894aa69aSMichael Chan u8 unused_0[7]; 9882894aa69aSMichael Chan u8 valid; 9883894aa69aSMichael Chan }; 9884894aa69aSMichael Chan 9885894aa69aSMichael Chan /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9886894aa69aSMichael Chan struct hwrm_nvm_find_dir_entry_input { 9887894aa69aSMichael Chan __le16 req_type; 9888894aa69aSMichael Chan __le16 cmpl_ring; 9889894aa69aSMichael Chan __le16 seq_id; 9890894aa69aSMichael Chan __le16 target_id; 9891894aa69aSMichael Chan __le64 resp_addr; 9892894aa69aSMichael Chan __le32 enables; 9893894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9894894aa69aSMichael Chan __le16 dir_idx; 9895894aa69aSMichael Chan __le16 dir_type; 9896894aa69aSMichael Chan __le16 dir_ordinal; 9897894aa69aSMichael Chan __le16 dir_ext; 9898894aa69aSMichael Chan u8 opt_ordinal; 9899894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9900894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9901894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9902894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9903894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9904894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9905894aa69aSMichael Chan u8 unused_0[3]; 9906894aa69aSMichael Chan }; 9907894aa69aSMichael Chan 9908894aa69aSMichael Chan /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9909894aa69aSMichael Chan struct hwrm_nvm_find_dir_entry_output { 9910894aa69aSMichael Chan __le16 error_code; 9911894aa69aSMichael Chan __le16 req_type; 9912894aa69aSMichael Chan __le16 seq_id; 9913894aa69aSMichael Chan __le16 resp_len; 9914894aa69aSMichael Chan __le32 dir_item_length; 9915894aa69aSMichael Chan __le32 dir_data_length; 9916894aa69aSMichael Chan __le32 fw_ver; 9917894aa69aSMichael Chan __le16 dir_ordinal; 9918894aa69aSMichael Chan __le16 dir_idx; 9919894aa69aSMichael Chan u8 unused_0[7]; 9920894aa69aSMichael Chan u8 valid; 9921894aa69aSMichael Chan }; 9922894aa69aSMichael Chan 9923894aa69aSMichael Chan /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9924894aa69aSMichael Chan struct hwrm_nvm_erase_dir_entry_input { 9925894aa69aSMichael Chan __le16 req_type; 9926894aa69aSMichael Chan __le16 cmpl_ring; 9927894aa69aSMichael Chan __le16 seq_id; 9928894aa69aSMichael Chan __le16 target_id; 9929894aa69aSMichael Chan __le64 resp_addr; 9930894aa69aSMichael Chan __le16 dir_idx; 9931894aa69aSMichael Chan u8 unused_0[6]; 9932894aa69aSMichael Chan }; 9933894aa69aSMichael Chan 9934894aa69aSMichael Chan /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9935894aa69aSMichael Chan struct hwrm_nvm_erase_dir_entry_output { 9936894aa69aSMichael Chan __le16 error_code; 9937894aa69aSMichael Chan __le16 req_type; 9938894aa69aSMichael Chan __le16 seq_id; 9939894aa69aSMichael Chan __le16 resp_len; 9940894aa69aSMichael Chan u8 unused_0[7]; 9941894aa69aSMichael Chan u8 valid; 9942894aa69aSMichael Chan }; 9943894aa69aSMichael Chan 9944894aa69aSMichael Chan /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9945894aa69aSMichael Chan struct hwrm_nvm_get_dev_info_input { 9946894aa69aSMichael Chan __le16 req_type; 9947894aa69aSMichael Chan __le16 cmpl_ring; 9948894aa69aSMichael Chan __le16 seq_id; 9949894aa69aSMichael Chan __le16 target_id; 9950894aa69aSMichael Chan __le64 resp_addr; 9951894aa69aSMichael Chan }; 9952894aa69aSMichael Chan 9953424174f1SVasundhara Volam /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9954894aa69aSMichael Chan struct hwrm_nvm_get_dev_info_output { 9955894aa69aSMichael Chan __le16 error_code; 9956894aa69aSMichael Chan __le16 req_type; 9957894aa69aSMichael Chan __le16 seq_id; 9958894aa69aSMichael Chan __le16 resp_len; 9959894aa69aSMichael Chan __le16 manufacturer_id; 9960894aa69aSMichael Chan __le16 device_id; 9961894aa69aSMichael Chan __le32 sector_size; 9962894aa69aSMichael Chan __le32 nvram_size; 9963894aa69aSMichael Chan __le32 reserved_size; 9964894aa69aSMichael Chan __le32 available_size; 99654a50ddc2SMichael Chan u8 nvm_cfg_ver_maj; 99664a50ddc2SMichael Chan u8 nvm_cfg_ver_min; 99674a50ddc2SMichael Chan u8 nvm_cfg_ver_upd; 9968424174f1SVasundhara Volam u8 flags; 9969424174f1SVasundhara Volam #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9970424174f1SVasundhara Volam char pkg_name[16]; 9971424174f1SVasundhara Volam __le16 hwrm_fw_major; 9972424174f1SVasundhara Volam __le16 hwrm_fw_minor; 9973424174f1SVasundhara Volam __le16 hwrm_fw_build; 9974424174f1SVasundhara Volam __le16 hwrm_fw_patch; 9975424174f1SVasundhara Volam __le16 mgmt_fw_major; 9976424174f1SVasundhara Volam __le16 mgmt_fw_minor; 9977424174f1SVasundhara Volam __le16 mgmt_fw_build; 9978424174f1SVasundhara Volam __le16 mgmt_fw_patch; 9979424174f1SVasundhara Volam __le16 roce_fw_major; 9980424174f1SVasundhara Volam __le16 roce_fw_minor; 9981424174f1SVasundhara Volam __le16 roce_fw_build; 9982424174f1SVasundhara Volam __le16 roce_fw_patch; 9983424174f1SVasundhara Volam u8 unused_0[7]; 9984894aa69aSMichael Chan u8 valid; 9985894aa69aSMichael Chan }; 9986894aa69aSMichael Chan 9987894aa69aSMichael Chan /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9988894aa69aSMichael Chan struct hwrm_nvm_mod_dir_entry_input { 9989894aa69aSMichael Chan __le16 req_type; 9990894aa69aSMichael Chan __le16 cmpl_ring; 9991894aa69aSMichael Chan __le16 seq_id; 9992894aa69aSMichael Chan __le16 target_id; 9993894aa69aSMichael Chan __le64 resp_addr; 9994894aa69aSMichael Chan __le32 enables; 9995894aa69aSMichael Chan #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9996894aa69aSMichael Chan __le16 dir_idx; 9997894aa69aSMichael Chan __le16 dir_ordinal; 9998894aa69aSMichael Chan __le16 dir_ext; 9999894aa69aSMichael Chan __le16 dir_attr; 10000894aa69aSMichael Chan __le32 checksum; 10001894aa69aSMichael Chan }; 10002894aa69aSMichael Chan 10003894aa69aSMichael Chan /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10004894aa69aSMichael Chan struct hwrm_nvm_mod_dir_entry_output { 10005894aa69aSMichael Chan __le16 error_code; 10006894aa69aSMichael Chan __le16 req_type; 10007894aa69aSMichael Chan __le16 seq_id; 10008894aa69aSMichael Chan __le16 resp_len; 10009894aa69aSMichael Chan u8 unused_0[7]; 10010894aa69aSMichael Chan u8 valid; 10011894aa69aSMichael Chan }; 10012894aa69aSMichael Chan 10013894aa69aSMichael Chan /* hwrm_nvm_verify_update_input (size:192b/24B) */ 10014894aa69aSMichael Chan struct hwrm_nvm_verify_update_input { 10015894aa69aSMichael Chan __le16 req_type; 10016894aa69aSMichael Chan __le16 cmpl_ring; 10017894aa69aSMichael Chan __le16 seq_id; 10018894aa69aSMichael Chan __le16 target_id; 10019894aa69aSMichael Chan __le64 resp_addr; 10020894aa69aSMichael Chan __le16 dir_type; 10021894aa69aSMichael Chan __le16 dir_ordinal; 10022894aa69aSMichael Chan __le16 dir_ext; 10023894aa69aSMichael Chan u8 unused_0[2]; 10024894aa69aSMichael Chan }; 10025894aa69aSMichael Chan 10026894aa69aSMichael Chan /* hwrm_nvm_verify_update_output (size:128b/16B) */ 10027894aa69aSMichael Chan struct hwrm_nvm_verify_update_output { 10028894aa69aSMichael Chan __le16 error_code; 10029894aa69aSMichael Chan __le16 req_type; 10030894aa69aSMichael Chan __le16 seq_id; 10031894aa69aSMichael Chan __le16 resp_len; 10032894aa69aSMichael Chan u8 unused_0[7]; 10033894aa69aSMichael Chan u8 valid; 10034894aa69aSMichael Chan }; 10035894aa69aSMichael Chan 10036894aa69aSMichael Chan /* hwrm_nvm_install_update_input (size:192b/24B) */ 10037894aa69aSMichael Chan struct hwrm_nvm_install_update_input { 10038894aa69aSMichael Chan __le16 req_type; 10039894aa69aSMichael Chan __le16 cmpl_ring; 10040894aa69aSMichael Chan __le16 seq_id; 10041894aa69aSMichael Chan __le16 target_id; 10042894aa69aSMichael Chan __le64 resp_addr; 10043894aa69aSMichael Chan __le32 install_type; 10044894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10045894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10046894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10047894aa69aSMichael Chan __le16 flags; 10048894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10049894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10050894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10051bfc6e5fbSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10052894aa69aSMichael Chan u8 unused_0[2]; 10053894aa69aSMichael Chan }; 10054894aa69aSMichael Chan 10055894aa69aSMichael Chan /* hwrm_nvm_install_update_output (size:192b/24B) */ 10056894aa69aSMichael Chan struct hwrm_nvm_install_update_output { 10057894aa69aSMichael Chan __le16 error_code; 10058894aa69aSMichael Chan __le16 req_type; 10059894aa69aSMichael Chan __le16 seq_id; 10060894aa69aSMichael Chan __le16 resp_len; 10061894aa69aSMichael Chan __le64 installed_items; 10062894aa69aSMichael Chan u8 result; 10063894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 100642895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 100652895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 100662895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 100672895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 100682895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 100692895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 100702895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 100712895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 100722895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 100732895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 100742895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 100752895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 100762895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 100772895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 100782895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 100792895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 100802895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 100812895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 100822895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 100832895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 100842895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 100852895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 100862895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 100872895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 100882895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 100892895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 100902895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 100912895c153SMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10092894aa69aSMichael Chan u8 problem_item; 10093894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10094894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10095894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10096894aa69aSMichael Chan u8 reset_required; 10097894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10098894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10099894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10100894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10101894aa69aSMichael Chan u8 unused_0[4]; 10102894aa69aSMichael Chan u8 valid; 10103894aa69aSMichael Chan }; 10104894aa69aSMichael Chan 10105894aa69aSMichael Chan /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10106894aa69aSMichael Chan struct hwrm_nvm_install_update_cmd_err { 10107894aa69aSMichael Chan u8 code; 10108894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10109894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10110894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 1011178eeadb8SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10112ad04cc05SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10113ad04cc05SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 10114894aa69aSMichael Chan u8 unused_0[7]; 10115894aa69aSMichael Chan }; 10116894aa69aSMichael Chan 10117894aa69aSMichael Chan /* hwrm_nvm_get_variable_input (size:320b/40B) */ 10118894aa69aSMichael Chan struct hwrm_nvm_get_variable_input { 10119894aa69aSMichael Chan __le16 req_type; 10120894aa69aSMichael Chan __le16 cmpl_ring; 10121894aa69aSMichael Chan __le16 seq_id; 10122894aa69aSMichael Chan __le16 target_id; 10123894aa69aSMichael Chan __le64 resp_addr; 10124894aa69aSMichael Chan __le64 dest_data_addr; 10125894aa69aSMichael Chan __le16 data_len; 10126894aa69aSMichael Chan __le16 option_num; 10127894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10128894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10129894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10130894aa69aSMichael Chan __le16 dimensions; 10131894aa69aSMichael Chan __le16 index_0; 10132894aa69aSMichael Chan __le16 index_1; 10133894aa69aSMichael Chan __le16 index_2; 10134894aa69aSMichael Chan __le16 index_3; 10135894aa69aSMichael Chan u8 flags; 10136894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10137894aa69aSMichael Chan u8 unused_0; 10138894aa69aSMichael Chan }; 10139894aa69aSMichael Chan 10140894aa69aSMichael Chan /* hwrm_nvm_get_variable_output (size:128b/16B) */ 10141894aa69aSMichael Chan struct hwrm_nvm_get_variable_output { 10142894aa69aSMichael Chan __le16 error_code; 10143894aa69aSMichael Chan __le16 req_type; 10144894aa69aSMichael Chan __le16 seq_id; 10145894aa69aSMichael Chan __le16 resp_len; 10146894aa69aSMichael Chan __le16 data_len; 10147894aa69aSMichael Chan __le16 option_num; 10148894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10149894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10150894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10151894aa69aSMichael Chan u8 unused_0[3]; 10152894aa69aSMichael Chan u8 valid; 10153894aa69aSMichael Chan }; 10154894aa69aSMichael Chan 10155894aa69aSMichael Chan /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10156894aa69aSMichael Chan struct hwrm_nvm_get_variable_cmd_err { 10157894aa69aSMichael Chan u8 code; 10158894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10159894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10160894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10161894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10162894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 10163894aa69aSMichael Chan u8 unused_0[7]; 10164894aa69aSMichael Chan }; 10165894aa69aSMichael Chan 10166894aa69aSMichael Chan /* hwrm_nvm_set_variable_input (size:320b/40B) */ 10167894aa69aSMichael Chan struct hwrm_nvm_set_variable_input { 10168894aa69aSMichael Chan __le16 req_type; 10169894aa69aSMichael Chan __le16 cmpl_ring; 10170894aa69aSMichael Chan __le16 seq_id; 10171894aa69aSMichael Chan __le16 target_id; 10172894aa69aSMichael Chan __le64 resp_addr; 10173894aa69aSMichael Chan __le64 src_data_addr; 10174894aa69aSMichael Chan __le16 data_len; 10175894aa69aSMichael Chan __le16 option_num; 10176894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10177894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10178894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10179894aa69aSMichael Chan __le16 dimensions; 10180894aa69aSMichael Chan __le16 index_0; 10181894aa69aSMichael Chan __le16 index_1; 10182894aa69aSMichael Chan __le16 index_2; 10183894aa69aSMichael Chan __le16 index_3; 10184894aa69aSMichael Chan u8 flags; 10185894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10186894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10187894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10188894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10189894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 101906fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 101916fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 101926fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 101932792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 101942792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 101952792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10196894aa69aSMichael Chan u8 unused_0; 10197894aa69aSMichael Chan }; 10198894aa69aSMichael Chan 10199894aa69aSMichael Chan /* hwrm_nvm_set_variable_output (size:128b/16B) */ 10200894aa69aSMichael Chan struct hwrm_nvm_set_variable_output { 10201894aa69aSMichael Chan __le16 error_code; 10202894aa69aSMichael Chan __le16 req_type; 10203894aa69aSMichael Chan __le16 seq_id; 10204894aa69aSMichael Chan __le16 resp_len; 10205894aa69aSMichael Chan u8 unused_0[7]; 10206894aa69aSMichael Chan u8 valid; 10207894aa69aSMichael Chan }; 10208894aa69aSMichael Chan 10209894aa69aSMichael Chan /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10210894aa69aSMichael Chan struct hwrm_nvm_set_variable_cmd_err { 10211894aa69aSMichael Chan u8 code; 10212894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10213894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10214894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10215894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 10216894aa69aSMichael Chan u8 unused_0[7]; 10217894aa69aSMichael Chan }; 10218894aa69aSMichael Chan 10219894aa69aSMichael Chan /* hwrm_selftest_qlist_input (size:128b/16B) */ 10220894aa69aSMichael Chan struct hwrm_selftest_qlist_input { 10221894aa69aSMichael Chan __le16 req_type; 10222894aa69aSMichael Chan __le16 cmpl_ring; 10223894aa69aSMichael Chan __le16 seq_id; 10224894aa69aSMichael Chan __le16 target_id; 10225894aa69aSMichael Chan __le64 resp_addr; 10226894aa69aSMichael Chan }; 10227894aa69aSMichael Chan 10228894aa69aSMichael Chan /* hwrm_selftest_qlist_output (size:2240b/280B) */ 10229894aa69aSMichael Chan struct hwrm_selftest_qlist_output { 10230894aa69aSMichael Chan __le16 error_code; 10231894aa69aSMichael Chan __le16 req_type; 10232894aa69aSMichael Chan __le16 seq_id; 10233894aa69aSMichael Chan __le16 resp_len; 10234894aa69aSMichael Chan u8 num_tests; 10235894aa69aSMichael Chan u8 available_tests; 10236894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10237894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10238894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10239894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10240894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10241894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10242894aa69aSMichael Chan u8 offline_tests; 10243894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10244894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10245894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10246894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10247894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10248894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10249894aa69aSMichael Chan u8 unused_0; 10250894aa69aSMichael Chan __le16 test_timeout; 10251894aa69aSMichael Chan u8 unused_1[2]; 10252d3e599c0SKees Cook char test_name[8][32]; 10253bfc6e5fbSMichael Chan u8 eyescope_target_BER_support; 10254bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10255bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10256bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10257bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10258bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10259bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10260bfc6e5fbSMichael Chan u8 unused_2[6]; 10261894aa69aSMichael Chan u8 valid; 10262894aa69aSMichael Chan }; 10263894aa69aSMichael Chan 10264894aa69aSMichael Chan /* hwrm_selftest_exec_input (size:192b/24B) */ 10265894aa69aSMichael Chan struct hwrm_selftest_exec_input { 10266894aa69aSMichael Chan __le16 req_type; 10267894aa69aSMichael Chan __le16 cmpl_ring; 10268894aa69aSMichael Chan __le16 seq_id; 10269894aa69aSMichael Chan __le16 target_id; 10270894aa69aSMichael Chan __le64 resp_addr; 10271894aa69aSMichael Chan u8 flags; 10272894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10273894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10274894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10275894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10276894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10277894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10278d4f52de0SMichael Chan u8 unused_0[7]; 10279894aa69aSMichael Chan }; 10280894aa69aSMichael Chan 10281894aa69aSMichael Chan /* hwrm_selftest_exec_output (size:128b/16B) */ 10282894aa69aSMichael Chan struct hwrm_selftest_exec_output { 10283894aa69aSMichael Chan __le16 error_code; 10284894aa69aSMichael Chan __le16 req_type; 10285894aa69aSMichael Chan __le16 seq_id; 10286894aa69aSMichael Chan __le16 resp_len; 10287894aa69aSMichael Chan u8 requested_tests; 10288894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10289894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 10290894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 10291894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 10292894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 10293894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 10294894aa69aSMichael Chan u8 test_success; 10295894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 10296894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 10297894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 10298894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 10299894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 10300894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 10301894aa69aSMichael Chan u8 unused_0[5]; 10302894aa69aSMichael Chan u8 valid; 10303894aa69aSMichael Chan }; 10304894aa69aSMichael Chan 10305894aa69aSMichael Chan /* hwrm_selftest_irq_input (size:128b/16B) */ 10306894aa69aSMichael Chan struct hwrm_selftest_irq_input { 10307894aa69aSMichael Chan __le16 req_type; 10308894aa69aSMichael Chan __le16 cmpl_ring; 10309894aa69aSMichael Chan __le16 seq_id; 10310894aa69aSMichael Chan __le16 target_id; 10311894aa69aSMichael Chan __le64 resp_addr; 10312894aa69aSMichael Chan }; 10313894aa69aSMichael Chan 10314894aa69aSMichael Chan /* hwrm_selftest_irq_output (size:128b/16B) */ 10315894aa69aSMichael Chan struct hwrm_selftest_irq_output { 10316894aa69aSMichael Chan __le16 error_code; 10317894aa69aSMichael Chan __le16 req_type; 10318894aa69aSMichael Chan __le16 seq_id; 10319894aa69aSMichael Chan __le16 resp_len; 10320894aa69aSMichael Chan u8 unused_0[7]; 10321894aa69aSMichael Chan u8 valid; 10322894aa69aSMichael Chan }; 10323894aa69aSMichael Chan 10324*a9a457f3SSelvin Xavier /* dbc_dbc (size:64b/8B) */ 10325*a9a457f3SSelvin Xavier struct dbc_dbc { 10326*a9a457f3SSelvin Xavier u32 index; 10327*a9a457f3SSelvin Xavier #define DBC_DBC_INDEX_MASK 0xffffffUL 10328*a9a457f3SSelvin Xavier #define DBC_DBC_INDEX_SFT 0 10329*a9a457f3SSelvin Xavier #define DBC_DBC_EPOCH 0x1000000UL 10330*a9a457f3SSelvin Xavier #define DBC_DBC_TOGGLE_MASK 0x6000000UL 10331*a9a457f3SSelvin Xavier #define DBC_DBC_TOGGLE_SFT 25 10332*a9a457f3SSelvin Xavier u32 type_path_xid; 10333*a9a457f3SSelvin Xavier #define DBC_DBC_XID_MASK 0xfffffUL 10334*a9a457f3SSelvin Xavier #define DBC_DBC_XID_SFT 0 10335*a9a457f3SSelvin Xavier #define DBC_DBC_PATH_MASK 0x3000000UL 10336*a9a457f3SSelvin Xavier #define DBC_DBC_PATH_SFT 24 10337*a9a457f3SSelvin Xavier #define DBC_DBC_PATH_ROCE (0x0UL << 24) 10338*a9a457f3SSelvin Xavier #define DBC_DBC_PATH_L2 (0x1UL << 24) 10339*a9a457f3SSelvin Xavier #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 10340*a9a457f3SSelvin Xavier #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 10341*a9a457f3SSelvin Xavier #define DBC_DBC_VALID 0x4000000UL 10342*a9a457f3SSelvin Xavier #define DBC_DBC_DEBUG_TRACE 0x8000000UL 10343*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_MASK 0xf0000000UL 10344*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_SFT 28 10345*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_SQ (0x0UL << 28) 10346*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_RQ (0x1UL << 28) 10347*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 10348*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 10349*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_CQ (0x4UL << 28) 10350*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 10351*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 10352*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 10353*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 10354*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 10355*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_NQ (0xaUL << 28) 10356*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 10357*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 10358*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_NULL (0xfUL << 28) 10359*a9a457f3SSelvin Xavier #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 10360*a9a457f3SSelvin Xavier }; 10361*a9a457f3SSelvin Xavier 10362*a9a457f3SSelvin Xavier /* db_push_start (size:64b/8B) */ 10363*a9a457f3SSelvin Xavier struct db_push_start { 10364*a9a457f3SSelvin Xavier u64 db; 10365*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 10366*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_INDEX_SFT 0 10367*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 10368*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_PI_LO_SFT 24 10369*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 10370*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_XID_SFT 32 10371*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 10372*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_PI_HI_SFT 52 10373*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 10374*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_TYPE_SFT 60 10375*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 10376*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 10377*a9a457f3SSelvin Xavier #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 10378*a9a457f3SSelvin Xavier }; 10379*a9a457f3SSelvin Xavier 10380*a9a457f3SSelvin Xavier /* db_push_end (size:64b/8B) */ 10381*a9a457f3SSelvin Xavier struct db_push_end { 10382*a9a457f3SSelvin Xavier u64 db; 10383*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 10384*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_INDEX_SFT 0 10385*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 10386*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PI_LO_SFT 24 10387*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 10388*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_XID_SFT 32 10389*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 10390*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PI_HI_SFT 52 10391*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 10392*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PATH_SFT 56 10393*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 10394*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 10395*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 10396*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 10397*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 10398*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 10399*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_TYPE_SFT 60 10400*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 10401*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 10402*a9a457f3SSelvin Xavier #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 10403*a9a457f3SSelvin Xavier }; 10404*a9a457f3SSelvin Xavier 104059d6b648cSMichael Chan /* db_push_info (size:64b/8B) */ 104069d6b648cSMichael Chan struct db_push_info { 104079d6b648cSMichael Chan u32 push_size_push_index; 104089d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 104099d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 104109d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 104119d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 104129d6b648cSMichael Chan u32 reserved32; 104139d6b648cSMichael Chan }; 104149d6b648cSMichael Chan 10415460c2577SMichael Chan /* fw_status_reg (size:32b/4B) */ 10416460c2577SMichael Chan struct fw_status_reg { 10417460c2577SMichael Chan u32 fw_status; 10418460c2577SMichael Chan #define FW_STATUS_REG_CODE_MASK 0xffffUL 10419460c2577SMichael Chan #define FW_STATUS_REG_CODE_SFT 0 10420460c2577SMichael Chan #define FW_STATUS_REG_CODE_READY 0x8000UL 10421460c2577SMichael Chan #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 10422460c2577SMichael Chan #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 10423460c2577SMichael Chan #define FW_STATUS_REG_RECOVERABLE 0x20000UL 10424460c2577SMichael Chan #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 10425460c2577SMichael Chan #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 10426460c2577SMichael Chan #define FW_STATUS_REG_SHUTDOWN 0x100000UL 10427424174f1SVasundhara Volam #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 1042878eeadb8SMichael Chan #define FW_STATUS_REG_RECOVERING 0x400000UL 1042984a911dbSMichael Chan #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 10430460c2577SMichael Chan }; 10431460c2577SMichael Chan 104329d6b648cSMichael Chan /* hcomm_status (size:64b/8B) */ 104339d6b648cSMichael Chan struct hcomm_status { 104349d6b648cSMichael Chan u32 sig_ver; 104359d6b648cSMichael Chan #define HCOMM_STATUS_VER_MASK 0xffUL 104369d6b648cSMichael Chan #define HCOMM_STATUS_VER_SFT 0 104379d6b648cSMichael Chan #define HCOMM_STATUS_VER_LATEST 0x1UL 104389d6b648cSMichael Chan #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 104399d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 104409d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_SFT 8 104419d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 104429d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 104439d6b648cSMichael Chan u32 fw_status_loc; 104449d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 104459d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 104469d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 104479d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 104489d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 104499d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 104509d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 104519d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 104529d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 104539d6b648cSMichael Chan }; 104549d6b648cSMichael Chan #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 104559d6b648cSMichael Chan 10456894aa69aSMichael Chan #endif /* _BNXT_HSI_H_ */ 10457