1c0c050c5SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2c0c050c5SMichael Chan * 311f15ed3SMichael Chan * Copyright (c) 2014-2016 Broadcom Corporation 4c0c050c5SMichael Chan * 5c0c050c5SMichael Chan * This program is free software; you can redistribute it and/or modify 6c0c050c5SMichael Chan * it under the terms of the GNU General Public License as published by 7c0c050c5SMichael Chan * the Free Software Foundation. 8c0c050c5SMichael Chan */ 9c0c050c5SMichael Chan 10c0c050c5SMichael Chan #ifndef BNXT_HSI_H 11c0c050c5SMichael Chan #define BNXT_HSI_H 12c0c050c5SMichael Chan 13c0c050c5SMichael Chan /* per-context HW statistics -- chip view */ 14c0c050c5SMichael Chan struct ctx_hw_stats { 15c0c050c5SMichael Chan __le64 rx_ucast_pkts; 16c0c050c5SMichael Chan __le64 rx_mcast_pkts; 17c0c050c5SMichael Chan __le64 rx_bcast_pkts; 18c0c050c5SMichael Chan __le64 rx_discard_pkts; 19c0c050c5SMichael Chan __le64 rx_drop_pkts; 20c0c050c5SMichael Chan __le64 rx_ucast_bytes; 21c0c050c5SMichael Chan __le64 rx_mcast_bytes; 22c0c050c5SMichael Chan __le64 rx_bcast_bytes; 23c0c050c5SMichael Chan __le64 tx_ucast_pkts; 24c0c050c5SMichael Chan __le64 tx_mcast_pkts; 25c0c050c5SMichael Chan __le64 tx_bcast_pkts; 26c0c050c5SMichael Chan __le64 tx_discard_pkts; 27c0c050c5SMichael Chan __le64 tx_drop_pkts; 28c0c050c5SMichael Chan __le64 tx_ucast_bytes; 29c0c050c5SMichael Chan __le64 tx_mcast_bytes; 30c0c050c5SMichael Chan __le64 tx_bcast_bytes; 31c0c050c5SMichael Chan __le64 tpa_pkts; 32c0c050c5SMichael Chan __le64 tpa_bytes; 33c0c050c5SMichael Chan __le64 tpa_events; 34c0c050c5SMichael Chan __le64 tpa_aborts; 35c0c050c5SMichael Chan }; 36c0c050c5SMichael Chan 37c0c050c5SMichael Chan /* Statistics Ejection Buffer Completion Record (16 bytes) */ 38c0c050c5SMichael Chan struct eject_cmpl { 39c0c050c5SMichael Chan __le16 type; 40c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_MASK 0x3fUL 41c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_SFT 0 42c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_STAT_EJECT (0x1aUL << 0) 43c0c050c5SMichael Chan __le16 len; 44c0c050c5SMichael Chan __le32 opaque; 45c0c050c5SMichael Chan __le32 v; 46c0c050c5SMichael Chan #define EJECT_CMPL_V 0x1UL 47c0c050c5SMichael Chan __le32 unused_2; 48c0c050c5SMichael Chan }; 49c0c050c5SMichael Chan 50c0c050c5SMichael Chan /* HWRM Completion Record (16 bytes) */ 51c0c050c5SMichael Chan struct hwrm_cmpl { 52c0c050c5SMichael Chan __le16 type; 53c0c050c5SMichael Chan #define HWRM_CMPL_TYPE_MASK 0x3fUL 54c0c050c5SMichael Chan #define HWRM_CMPL_TYPE_SFT 0 55c0c050c5SMichael Chan #define HWRM_CMPL_TYPE_HWRM_DONE (0x20UL << 0) 56c0c050c5SMichael Chan __le16 sequence_id; 57c0c050c5SMichael Chan __le32 unused_1; 58c0c050c5SMichael Chan __le32 v; 59c0c050c5SMichael Chan #define HWRM_CMPL_V 0x1UL 60c0c050c5SMichael Chan __le32 unused_3; 61c0c050c5SMichael Chan }; 62c0c050c5SMichael Chan 63c0c050c5SMichael Chan /* HWRM Forwarded Request (16 bytes) */ 64c0c050c5SMichael Chan struct hwrm_fwd_req_cmpl { 65c0c050c5SMichael Chan __le16 req_len_type; 66c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_TYPE_MASK 0x3fUL 67c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_TYPE_SFT 0 68c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ (0x22UL << 0) 69c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 70c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_REQ_LEN_SFT 6 71c0c050c5SMichael Chan __le16 source_id; 72c0c050c5SMichael Chan __le32 unused_0; 73c0c050c5SMichael Chan __le32 req_buf_addr_v[2]; 74c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_V 0x1UL 75c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 76c0c050c5SMichael Chan #define HWRM_FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 77c0c050c5SMichael Chan }; 78c0c050c5SMichael Chan 79c0c050c5SMichael Chan /* HWRM Forwarded Response (16 bytes) */ 80c0c050c5SMichael Chan struct hwrm_fwd_resp_cmpl { 81c0c050c5SMichael Chan __le16 type; 82c0c050c5SMichael Chan #define HWRM_FWD_RESP_CMPL_TYPE_MASK 0x3fUL 83c0c050c5SMichael Chan #define HWRM_FWD_RESP_CMPL_TYPE_SFT 0 84c0c050c5SMichael Chan #define HWRM_FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP (0x24UL << 0) 85c0c050c5SMichael Chan __le16 source_id; 86c0c050c5SMichael Chan __le16 resp_len; 87c0c050c5SMichael Chan __le16 unused_1; 88c0c050c5SMichael Chan __le32 resp_buf_addr_v[2]; 89c0c050c5SMichael Chan #define HWRM_FWD_RESP_CMPL_V 0x1UL 90c0c050c5SMichael Chan #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 91c0c050c5SMichael Chan #define HWRM_FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 92c0c050c5SMichael Chan }; 93c0c050c5SMichael Chan 94c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record (16 bytes) */ 95c0c050c5SMichael Chan struct hwrm_async_event_cmpl { 96c0c050c5SMichael Chan __le16 type; 97c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 98c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_TYPE_SFT 0 99c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 100c0c050c5SMichael Chan __le16 event_id; 101c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0) 102c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0) 103c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) 104c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) 105c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) 106c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0) 10711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0) 108c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) 109c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) 110c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) 111c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0) 112c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR (0x30UL << 0) 113c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) 114c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0) 11511f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0) 116c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR (0xffUL << 0) 117c0c050c5SMichael Chan __le32 event_data2; 118c0c050c5SMichael Chan u8 opaque_v; 119c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_V 0x1UL 120c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 121c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_OPAQUE_SFT 1 122c193554eSMichael Chan u8 timestamp_lo; 123c193554eSMichael Chan __le16 timestamp_hi; 124c0c050c5SMichael Chan __le32 event_data1; 125c0c050c5SMichael Chan }; 126c0c050c5SMichael Chan 127c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for link status change (16 bytes) */ 128c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_status_change { 129c0c050c5SMichael Chan __le16 type; 130c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 131c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 132c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 133c0c050c5SMichael Chan __le16 event_id; 134c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE (0x0UL << 0) 135c0c050c5SMichael Chan __le32 event_data2; 136c0c050c5SMichael Chan u8 opaque_v; 137c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 138c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 139c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 140c193554eSMichael Chan u8 timestamp_lo; 141c193554eSMichael Chan __le16 timestamp_hi; 142c0c050c5SMichael Chan __le32 event_data1; 143c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 144c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN (0x0UL << 0) 145c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP (0x1UL << 0) 14611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 147c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 148c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 149c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 150c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 151c0c050c5SMichael Chan }; 152c0c050c5SMichael Chan 153c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for link MTU change (16 bytes) */ 154c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_mtu_change { 155c0c050c5SMichael Chan __le16 type; 156c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_MASK 0x3fUL 157c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_SFT 0 158c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 159c0c050c5SMichael Chan __le16 event_id; 160c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_ID_LINK_MTU_CHANGE (0x1UL << 0) 161c0c050c5SMichael Chan __le32 event_data2; 162c0c050c5SMichael Chan u8 opaque_v; 163c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_V 0x1UL 164c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_MASK 0xfeUL 165c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_OPAQUE_SFT 1 166c193554eSMichael Chan u8 timestamp_lo; 167c193554eSMichael Chan __le16 timestamp_hi; 168c0c050c5SMichael Chan __le32 event_data1; 169c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_MASK 0xffffUL 170c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_MTU_CHANGE_EVENT_DATA1_NEW_MTU_SFT 0 171c0c050c5SMichael Chan }; 172c0c050c5SMichael Chan 173c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for link speed change (16 bytes) */ 174c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_speed_change { 175c0c050c5SMichael Chan __le16 type; 176c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_MASK 0x3fUL 177c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_SFT 0 178c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 179c0c050c5SMichael Chan __le16 event_id; 180c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_ID_LINK_SPEED_CHANGE (0x2UL << 0) 181c0c050c5SMichael Chan __le32 event_data2; 182c0c050c5SMichael Chan u8 opaque_v; 183c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_V 0x1UL 184c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_MASK 0xfeUL 185c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_OPAQUE_SFT 1 186c193554eSMichael Chan u8 timestamp_lo; 187c193554eSMichael Chan __le16 timestamp_hi; 188c0c050c5SMichael Chan __le32 event_data1; 189c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_FORCE 0x1UL 190c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_MASK 0xfffeUL 191c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_SFT 1 192c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100MB (0x1UL << 1) 193c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_1GB (0xaUL << 1) 194c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2GB (0x14UL << 1) 195c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_2_5GB (0x19UL << 1) 196c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10GB (0x64UL << 1) 197c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_20GB (0xc8UL << 1) 198c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_25GB (0xfaUL << 1) 199c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_40GB (0x190UL << 1) 200c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_50GB (0x1f4UL << 1) 20111f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_100GB (0x3e8UL << 1) 20211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB (0xffffUL << 1) 20311f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_LAST HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_NEW_LINK_SPEED_100MBPS_10MB 204c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0000UL 205c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CHANGE_EVENT_DATA1_PORT_ID_SFT 16 206c0c050c5SMichael Chan }; 207c0c050c5SMichael Chan 208c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for DCB Config change (16 bytes) */ 209c0c050c5SMichael Chan struct hwrm_async_event_cmpl_dcb_config_change { 210c0c050c5SMichael Chan __le16 type; 211c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_MASK 0x3fUL 212c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_SFT 0 213c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 214c0c050c5SMichael Chan __le16 event_id; 215c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_ID_DCB_CONFIG_CHANGE (0x3UL << 0) 216c0c050c5SMichael Chan __le32 event_data2; 217c0c050c5SMichael Chan u8 opaque_v; 218c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_V 0x1UL 219c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_MASK 0xfeUL 220c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_OPAQUE_SFT 1 221c193554eSMichael Chan u8 timestamp_lo; 222c193554eSMichael Chan __le16 timestamp_hi; 223c0c050c5SMichael Chan __le32 event_data1; 224c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 225c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_DCB_CONFIG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 226c0c050c5SMichael Chan }; 227c0c050c5SMichael Chan 228c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for port connection not allowed (16 bytes) */ 229c0c050c5SMichael Chan struct hwrm_async_event_cmpl_port_conn_not_allowed { 230c0c050c5SMichael Chan __le16 type; 231c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 232c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 233c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 234c0c050c5SMichael Chan __le16 event_id; 235c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED (0x4UL << 0) 236c0c050c5SMichael Chan __le32 event_data2; 237c0c050c5SMichael Chan u8 opaque_v; 238c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 239c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 240c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 241c193554eSMichael Chan u8 timestamp_lo; 242c193554eSMichael Chan __le16 timestamp_hi; 243c0c050c5SMichael Chan __le32 event_data1; 244c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 245c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 24611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 24711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 24811f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 24911f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 25011f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 25111f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 25211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 25311f15ed3SMichael Chan }; 25411f15ed3SMichael Chan 25511f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for link speed config not allowed (16 bytes) */ 25611f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_not_allowed { 25711f15ed3SMichael Chan __le16 type; 25811f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_MASK 0x3fUL 25911f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_SFT 0 26011f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 26111f15ed3SMichael Chan __le16 event_id; 26211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED (0x5UL << 0) 26311f15ed3SMichael Chan __le32 event_data2; 26411f15ed3SMichael Chan u8 opaque_v; 26511f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_V 0x1UL 26611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 26711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_OPAQUE_SFT 1 26811f15ed3SMichael Chan u8 timestamp_lo; 26911f15ed3SMichael Chan __le16 timestamp_hi; 27011f15ed3SMichael Chan __le32 event_data1; 27111f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 27211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 27311f15ed3SMichael Chan }; 27411f15ed3SMichael Chan 27511f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for link speed configuration change (16 bytes) */ 27611f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_change { 27711f15ed3SMichael Chan __le16 type; 27811f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 27911f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 28011f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 28111f15ed3SMichael Chan __le16 event_id; 28211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE (0x6UL << 0) 28311f15ed3SMichael Chan __le32 event_data2; 28411f15ed3SMichael Chan u8 opaque_v; 28511f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 28611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 28711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 28811f15ed3SMichael Chan u8 timestamp_lo; 28911f15ed3SMichael Chan __le16 timestamp_hi; 29011f15ed3SMichael Chan __le32 event_data1; 29111f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 29211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 29311f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 29411f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 295c0c050c5SMichael Chan }; 296c0c050c5SMichael Chan 297c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for Function Driver Unload (16 bytes) */ 298c0c050c5SMichael Chan struct hwrm_async_event_cmpl_func_drvr_unload { 299c0c050c5SMichael Chan __le16 type; 300c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_MASK 0x3fUL 301c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_SFT 0 302c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 303c0c050c5SMichael Chan __le16 event_id; 304c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_ID_FUNC_DRVR_UNLOAD (0x10UL << 0) 305c0c050c5SMichael Chan __le32 event_data2; 306c0c050c5SMichael Chan u8 opaque_v; 307c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_V 0x1UL 308c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 309c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_OPAQUE_SFT 1 310c193554eSMichael Chan u8 timestamp_lo; 311c193554eSMichael Chan __le16 timestamp_hi; 312c0c050c5SMichael Chan __le32 event_data1; 313c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 314c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 315c0c050c5SMichael Chan }; 316c0c050c5SMichael Chan 317c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for Function Driver load (16 bytes) */ 318c0c050c5SMichael Chan struct hwrm_async_event_cmpl_func_drvr_load { 319c0c050c5SMichael Chan __le16 type; 320c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_MASK 0x3fUL 321c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_SFT 0 322c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 323c0c050c5SMichael Chan __le16 event_id; 324c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_ID_FUNC_DRVR_LOAD (0x11UL << 0) 325c0c050c5SMichael Chan __le32 event_data2; 326c0c050c5SMichael Chan u8 opaque_v; 327c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_V 0x1UL 328c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_MASK 0xfeUL 329c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_OPAQUE_SFT 1 330c193554eSMichael Chan u8 timestamp_lo; 331c193554eSMichael Chan __le16 timestamp_hi; 332c0c050c5SMichael Chan __le32 event_data1; 333c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 334c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_FUNC_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 335c0c050c5SMichael Chan }; 336c0c050c5SMichael Chan 337c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for PF Driver Unload (16 bytes) */ 338c0c050c5SMichael Chan struct hwrm_async_event_cmpl_pf_drvr_unload { 339c0c050c5SMichael Chan __le16 type; 340c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_MASK 0x3fUL 341c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_SFT 0 342c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 343c0c050c5SMichael Chan __le16 event_id; 344c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_ID_PF_DRVR_UNLOAD (0x20UL << 0) 345c0c050c5SMichael Chan __le32 event_data2; 346c0c050c5SMichael Chan u8 opaque_v; 347c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_V 0x1UL 348c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_MASK 0xfeUL 349c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_OPAQUE_SFT 1 350c193554eSMichael Chan u8 timestamp_lo; 351c193554eSMichael Chan __le16 timestamp_hi; 352c0c050c5SMichael Chan __le32 event_data1; 353c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 354c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_FUNC_ID_SFT 0 355c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_MASK 0x70000UL 356c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_UNLOAD_EVENT_DATA1_PORT_SFT 16 357c0c050c5SMichael Chan }; 358c0c050c5SMichael Chan 359c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for PF Driver load (16 bytes) */ 360c0c050c5SMichael Chan struct hwrm_async_event_cmpl_pf_drvr_load { 361c0c050c5SMichael Chan __le16 type; 362c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_MASK 0x3fUL 363c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_SFT 0 364c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 365c0c050c5SMichael Chan __le16 event_id; 366c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_ID_PF_DRVR_LOAD (0x21UL << 0) 367c0c050c5SMichael Chan __le32 event_data2; 368c0c050c5SMichael Chan u8 opaque_v; 369c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_V 0x1UL 370c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_MASK 0xfeUL 371c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_OPAQUE_SFT 1 372c193554eSMichael Chan u8 timestamp_lo; 373c193554eSMichael Chan __le16 timestamp_hi; 374c0c050c5SMichael Chan __le32 event_data1; 375c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_MASK 0xffffUL 376c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_FUNC_ID_SFT 0 377c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_MASK 0x70000UL 378c193554eSMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_DRVR_LOAD_EVENT_DATA1_PORT_SFT 16 379c0c050c5SMichael Chan }; 380c0c050c5SMichael Chan 381c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for VF FLR (16 bytes) */ 382c0c050c5SMichael Chan struct hwrm_async_event_cmpl_vf_flr { 383c0c050c5SMichael Chan __le16 type; 384c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_MASK 0x3fUL 385c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_SFT 0 386c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 387c0c050c5SMichael Chan __le16 event_id; 388c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_ID_VF_FLR (0x30UL << 0) 389c0c050c5SMichael Chan __le32 event_data2; 390c0c050c5SMichael Chan u8 opaque_v; 391c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_V 0x1UL 392c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_MASK 0xfeUL 393c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_OPAQUE_SFT 1 394c193554eSMichael Chan u8 timestamp_lo; 395c193554eSMichael Chan __le16 timestamp_hi; 396c0c050c5SMichael Chan __le32 event_data1; 397c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_MASK 0xffffUL 398c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_FLR_EVENT_DATA1_VF_ID_SFT 0 399c0c050c5SMichael Chan }; 400c0c050c5SMichael Chan 401c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for VF MAC Addr change (16 bytes) */ 402c0c050c5SMichael Chan struct hwrm_async_event_cmpl_vf_mac_addr_change { 403c0c050c5SMichael Chan __le16 type; 404c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_MASK 0x3fUL 405c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_SFT 0 406c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 407c0c050c5SMichael Chan __le16 event_id; 408c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_ID_VF_MAC_ADDR_CHANGE (0x31UL << 0) 409c0c050c5SMichael Chan __le32 event_data2; 410c0c050c5SMichael Chan u8 opaque_v; 411c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_V 0x1UL 412c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_MASK 0xfeUL 413c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_OPAQUE_SFT 1 414c193554eSMichael Chan u8 timestamp_lo; 415c193554eSMichael Chan __le16 timestamp_hi; 416c0c050c5SMichael Chan __le32 event_data1; 417c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_MASK 0xffffUL 418c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_MAC_ADDR_CHANGE_EVENT_DATA1_VF_ID_SFT 0 419c0c050c5SMichael Chan }; 420c0c050c5SMichael Chan 42111f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for PF-VF communication status change (16 bytes) */ 42211f15ed3SMichael Chan struct hwrm_async_event_cmpl_pf_vf_comm_status_change { 42311f15ed3SMichael Chan __le16 type; 42411f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_MASK 0x3fUL 42511f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_SFT 0 42611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 42711f15ed3SMichael Chan __le16 event_id; 42811f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_ID_PF_VF_COMM_STATUS_CHANGE (0x32UL << 0) 42911f15ed3SMichael Chan __le32 event_data2; 43011f15ed3SMichael Chan u8 opaque_v; 43111f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_V 0x1UL 43211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 43311f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_OPAQUE_SFT 1 43411f15ed3SMichael Chan u8 timestamp_lo; 43511f15ed3SMichael Chan __le16 timestamp_hi; 43611f15ed3SMichael Chan __le32 event_data1; 43711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_PF_VF_COMM_STATUS_CHANGE_EVENT_DATA1_COMM_ESTABLISHED 0x1UL 43811f15ed3SMichael Chan }; 43911f15ed3SMichael Chan 44011f15ed3SMichael Chan /* HWRM Asynchronous Event Completion Record for VF configuration change (16 bytes) */ 44111f15ed3SMichael Chan struct hwrm_async_event_cmpl_vf_cfg_change { 44211f15ed3SMichael Chan __le16 type; 44311f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 44411f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 44511f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 44611f15ed3SMichael Chan __le16 event_id; 44711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE (0x33UL << 0) 44811f15ed3SMichael Chan __le32 event_data2; 44911f15ed3SMichael Chan u8 opaque_v; 45011f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 45111f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 45211f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 45311f15ed3SMichael Chan u8 timestamp_lo; 45411f15ed3SMichael Chan __le16 timestamp_hi; 45511f15ed3SMichael Chan __le32 event_data1; 45611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 45711f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 45811f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 45911f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 46011f15ed3SMichael Chan }; 46111f15ed3SMichael Chan 462c0c050c5SMichael Chan /* HWRM Asynchronous Event Completion Record for HWRM Error (16 bytes) */ 463c0c050c5SMichael Chan struct hwrm_async_event_cmpl_hwrm_error { 464c0c050c5SMichael Chan __le16 type; 465c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 466c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 467c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0) 468c0c050c5SMichael Chan __le16 event_id; 469c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR (0xffUL << 0) 470c0c050c5SMichael Chan __le32 event_data2; 471c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 472c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 473c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING (0x0UL << 0) 474c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL (0x1UL << 0) 475c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL (0x2UL << 0) 47611f15ed3SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 477c0c050c5SMichael Chan u8 opaque_v; 478c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 479c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 480c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 481c193554eSMichael Chan u8 timestamp_lo; 482c193554eSMichael Chan __le16 timestamp_hi; 483c0c050c5SMichael Chan __le32 event_data1; 484c0c050c5SMichael Chan #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 485c0c050c5SMichael Chan }; 486c0c050c5SMichael Chan 48711f15ed3SMichael Chan /* HW Resource Manager Specification 1.2.2 */ 488c193554eSMichael Chan #define HWRM_VERSION_MAJOR 1 48911f15ed3SMichael Chan #define HWRM_VERSION_MINOR 2 49011f15ed3SMichael Chan #define HWRM_VERSION_UPDATE 2 491c0c050c5SMichael Chan 49211f15ed3SMichael Chan #define HWRM_VERSION_STR "1.2.2" 493c193554eSMichael Chan /* 494c193554eSMichael Chan * Following is the signature for HWRM message field that indicates not 495c0c050c5SMichael Chan * applicable (All F's). Need to cast it the size of the field if needed. 496c0c050c5SMichael Chan */ 497c0c050c5SMichael Chan #define HWRM_NA_SIGNATURE ((__le32)(-1)) 498c0c050c5SMichael Chan #define HWRM_MAX_REQ_LEN (128) /* hwrm_func_buf_rgtr */ 499c0c050c5SMichael Chan #define HWRM_MAX_RESP_LEN (176) /* hwrm_func_qstats */ 500c0c050c5SMichael Chan #define HW_HASH_INDEX_SIZE 0x80 /* 7 bit indirection table index. */ 501c0c050c5SMichael Chan #define HW_HASH_KEY_SIZE 40 502c0c050c5SMichael Chan #define HWRM_RESP_VALID_KEY 1 /* valid key for HWRM response */ 503c0c050c5SMichael Chan /* Input (16 bytes) */ 504c0c050c5SMichael Chan struct input { 505c0c050c5SMichael Chan __le16 req_type; 506c0c050c5SMichael Chan __le16 cmpl_ring; 507c0c050c5SMichael Chan __le16 seq_id; 508c0c050c5SMichael Chan __le16 target_id; 509c0c050c5SMichael Chan __le64 resp_addr; 510c0c050c5SMichael Chan }; 511c0c050c5SMichael Chan 512c0c050c5SMichael Chan /* Output (8 bytes) */ 513c0c050c5SMichael Chan struct output { 514c0c050c5SMichael Chan __le16 error_code; 515c0c050c5SMichael Chan __le16 req_type; 516c0c050c5SMichael Chan __le16 seq_id; 517c0c050c5SMichael Chan __le16 resp_len; 518c0c050c5SMichael Chan }; 519c0c050c5SMichael Chan 520c0c050c5SMichael Chan /* Command numbering (8 bytes) */ 521c0c050c5SMichael Chan struct cmd_nums { 522c0c050c5SMichael Chan __le16 req_type; 523c0c050c5SMichael Chan #define HWRM_VER_GET (0x0UL) 524c193554eSMichael Chan #define HWRM_FUNC_BUF_UNRGTR (0xeUL) 525c193554eSMichael Chan #define HWRM_FUNC_VF_CFG (0xfUL) 526c193554eSMichael Chan #define RESERVED1 (0x10UL) 527c0c050c5SMichael Chan #define HWRM_FUNC_RESET (0x11UL) 528c0c050c5SMichael Chan #define HWRM_FUNC_GETFID (0x12UL) 529c0c050c5SMichael Chan #define HWRM_FUNC_VF_ALLOC (0x13UL) 530c0c050c5SMichael Chan #define HWRM_FUNC_VF_FREE (0x14UL) 531c0c050c5SMichael Chan #define HWRM_FUNC_QCAPS (0x15UL) 532c0c050c5SMichael Chan #define HWRM_FUNC_QCFG (0x16UL) 533c0c050c5SMichael Chan #define HWRM_FUNC_CFG (0x17UL) 534c0c050c5SMichael Chan #define HWRM_FUNC_QSTATS (0x18UL) 535c0c050c5SMichael Chan #define HWRM_FUNC_CLR_STATS (0x19UL) 536c0c050c5SMichael Chan #define HWRM_FUNC_DRV_UNRGTR (0x1aUL) 537c0c050c5SMichael Chan #define HWRM_FUNC_VF_RESC_FREE (0x1bUL) 538c0c050c5SMichael Chan #define HWRM_FUNC_VF_VNIC_IDS_QUERY (0x1cUL) 539c0c050c5SMichael Chan #define HWRM_FUNC_DRV_RGTR (0x1dUL) 540c0c050c5SMichael Chan #define HWRM_FUNC_DRV_QVER (0x1eUL) 541c0c050c5SMichael Chan #define HWRM_FUNC_BUF_RGTR (0x1fUL) 542c0c050c5SMichael Chan #define HWRM_PORT_PHY_CFG (0x20UL) 543c0c050c5SMichael Chan #define HWRM_PORT_MAC_CFG (0x21UL) 54411f15ed3SMichael Chan #define HWRM_PORT_TS_QUERY (0x22UL) 545c0c050c5SMichael Chan #define HWRM_PORT_QSTATS (0x23UL) 546c0c050c5SMichael Chan #define HWRM_PORT_LPBK_QSTATS (0x24UL) 547c0c050c5SMichael Chan #define HWRM_PORT_CLR_STATS (0x25UL) 548c0c050c5SMichael Chan #define HWRM_PORT_LPBK_CLR_STATS (0x26UL) 549c0c050c5SMichael Chan #define HWRM_PORT_PHY_QCFG (0x27UL) 550c0c050c5SMichael Chan #define HWRM_PORT_MAC_QCFG (0x28UL) 551c0c050c5SMichael Chan #define HWRM_PORT_BLINK_LED (0x29UL) 55211f15ed3SMichael Chan #define HWRM_PORT_PHY_QCAPS (0x2aUL) 55311f15ed3SMichael Chan #define HWRM_PORT_PHY_I2C_WRITE (0x2bUL) 55411f15ed3SMichael Chan #define HWRM_PORT_PHY_I2C_READ (0x2cUL) 555c0c050c5SMichael Chan #define HWRM_QUEUE_QPORTCFG (0x30UL) 556c0c050c5SMichael Chan #define HWRM_QUEUE_QCFG (0x31UL) 557c0c050c5SMichael Chan #define HWRM_QUEUE_CFG (0x32UL) 558c0c050c5SMichael Chan #define HWRM_QUEUE_BUFFERS_QCFG (0x33UL) 559c0c050c5SMichael Chan #define HWRM_QUEUE_BUFFERS_CFG (0x34UL) 560c0c050c5SMichael Chan #define HWRM_QUEUE_PFCENABLE_QCFG (0x35UL) 561c0c050c5SMichael Chan #define HWRM_QUEUE_PFCENABLE_CFG (0x36UL) 562c0c050c5SMichael Chan #define HWRM_QUEUE_PRI2COS_QCFG (0x37UL) 563c0c050c5SMichael Chan #define HWRM_QUEUE_PRI2COS_CFG (0x38UL) 564c0c050c5SMichael Chan #define HWRM_QUEUE_COS2BW_QCFG (0x39UL) 565c0c050c5SMichael Chan #define HWRM_QUEUE_COS2BW_CFG (0x3aUL) 566c0c050c5SMichael Chan #define HWRM_VNIC_ALLOC (0x40UL) 567c0c050c5SMichael Chan #define HWRM_VNIC_FREE (0x41UL) 568c0c050c5SMichael Chan #define HWRM_VNIC_CFG (0x42UL) 569c0c050c5SMichael Chan #define HWRM_VNIC_QCFG (0x43UL) 570c0c050c5SMichael Chan #define HWRM_VNIC_TPA_CFG (0x44UL) 571c0c050c5SMichael Chan #define HWRM_VNIC_TPA_QCFG (0x45UL) 572c0c050c5SMichael Chan #define HWRM_VNIC_RSS_CFG (0x46UL) 573c0c050c5SMichael Chan #define HWRM_VNIC_RSS_QCFG (0x47UL) 574c0c050c5SMichael Chan #define HWRM_VNIC_PLCMODES_CFG (0x48UL) 575c0c050c5SMichael Chan #define HWRM_VNIC_PLCMODES_QCFG (0x49UL) 576c0c050c5SMichael Chan #define HWRM_RING_ALLOC (0x50UL) 577c0c050c5SMichael Chan #define HWRM_RING_FREE (0x51UL) 578c0c050c5SMichael Chan #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS (0x52UL) 579c0c050c5SMichael Chan #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS (0x53UL) 580c0c050c5SMichael Chan #define HWRM_RING_RESET (0x5eUL) 581c0c050c5SMichael Chan #define HWRM_RING_GRP_ALLOC (0x60UL) 582c0c050c5SMichael Chan #define HWRM_RING_GRP_FREE (0x61UL) 583c0c050c5SMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC (0x70UL) 584c0c050c5SMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_FREE (0x71UL) 585c0c050c5SMichael Chan #define HWRM_CFA_L2_FILTER_ALLOC (0x90UL) 586c0c050c5SMichael Chan #define HWRM_CFA_L2_FILTER_FREE (0x91UL) 587c0c050c5SMichael Chan #define HWRM_CFA_L2_FILTER_CFG (0x92UL) 588c0c050c5SMichael Chan #define HWRM_CFA_L2_SET_RX_MASK (0x93UL) 589c193554eSMichael Chan #define RESERVED3 (0x94UL) 590c0c050c5SMichael Chan #define HWRM_CFA_TUNNEL_FILTER_ALLOC (0x95UL) 591c0c050c5SMichael Chan #define HWRM_CFA_TUNNEL_FILTER_FREE (0x96UL) 592c0c050c5SMichael Chan #define HWRM_CFA_ENCAP_RECORD_ALLOC (0x97UL) 593c0c050c5SMichael Chan #define HWRM_CFA_ENCAP_RECORD_FREE (0x98UL) 594c0c050c5SMichael Chan #define HWRM_CFA_NTUPLE_FILTER_ALLOC (0x99UL) 595c0c050c5SMichael Chan #define HWRM_CFA_NTUPLE_FILTER_FREE (0x9aUL) 596c0c050c5SMichael Chan #define HWRM_CFA_NTUPLE_FILTER_CFG (0x9bUL) 597c193554eSMichael Chan #define HWRM_CFA_EM_FLOW_ALLOC (0x9cUL) 598c193554eSMichael Chan #define HWRM_CFA_EM_FLOW_FREE (0x9dUL) 599c193554eSMichael Chan #define HWRM_CFA_EM_FLOW_CFG (0x9eUL) 600c0c050c5SMichael Chan #define HWRM_TUNNEL_DST_PORT_QUERY (0xa0UL) 601c0c050c5SMichael Chan #define HWRM_TUNNEL_DST_PORT_ALLOC (0xa1UL) 602c0c050c5SMichael Chan #define HWRM_TUNNEL_DST_PORT_FREE (0xa2UL) 603c0c050c5SMichael Chan #define HWRM_STAT_CTX_ALLOC (0xb0UL) 604c0c050c5SMichael Chan #define HWRM_STAT_CTX_FREE (0xb1UL) 605c0c050c5SMichael Chan #define HWRM_STAT_CTX_QUERY (0xb2UL) 606c0c050c5SMichael Chan #define HWRM_STAT_CTX_CLR_STATS (0xb3UL) 607c0c050c5SMichael Chan #define HWRM_FW_RESET (0xc0UL) 608c0c050c5SMichael Chan #define HWRM_FW_QSTATUS (0xc1UL) 609c0c050c5SMichael Chan #define HWRM_EXEC_FWD_RESP (0xd0UL) 610c0c050c5SMichael Chan #define HWRM_REJECT_FWD_RESP (0xd1UL) 611c0c050c5SMichael Chan #define HWRM_FWD_RESP (0xd2UL) 612c0c050c5SMichael Chan #define HWRM_FWD_ASYNC_EVENT_CMPL (0xd3UL) 613c0c050c5SMichael Chan #define HWRM_TEMP_MONITOR_QUERY (0xe0UL) 614c0c050c5SMichael Chan #define HWRM_DBG_READ_DIRECT (0xff10UL) 615c0c050c5SMichael Chan #define HWRM_DBG_READ_INDIRECT (0xff11UL) 616c0c050c5SMichael Chan #define HWRM_DBG_WRITE_DIRECT (0xff12UL) 617c0c050c5SMichael Chan #define HWRM_DBG_WRITE_INDIRECT (0xff13UL) 618c0c050c5SMichael Chan #define HWRM_DBG_DUMP (0xff14UL) 619c0c050c5SMichael Chan #define HWRM_NVM_MODIFY (0xfff4UL) 620c0c050c5SMichael Chan #define HWRM_NVM_VERIFY_UPDATE (0xfff5UL) 621c0c050c5SMichael Chan #define HWRM_NVM_GET_DEV_INFO (0xfff6UL) 622c0c050c5SMichael Chan #define HWRM_NVM_ERASE_DIR_ENTRY (0xfff7UL) 623c0c050c5SMichael Chan #define HWRM_NVM_MOD_DIR_ENTRY (0xfff8UL) 624c0c050c5SMichael Chan #define HWRM_NVM_FIND_DIR_ENTRY (0xfff9UL) 625c0c050c5SMichael Chan #define HWRM_NVM_GET_DIR_ENTRIES (0xfffaUL) 626c0c050c5SMichael Chan #define HWRM_NVM_GET_DIR_INFO (0xfffbUL) 627c0c050c5SMichael Chan #define HWRM_NVM_RAW_DUMP (0xfffcUL) 628c0c050c5SMichael Chan #define HWRM_NVM_READ (0xfffdUL) 629c0c050c5SMichael Chan #define HWRM_NVM_WRITE (0xfffeUL) 630c0c050c5SMichael Chan #define HWRM_NVM_RAW_WRITE_BLK (0xffffUL) 631c0c050c5SMichael Chan __le16 unused_0[3]; 632c0c050c5SMichael Chan }; 633c0c050c5SMichael Chan 63411f15ed3SMichael Chan /* Return Codes (8 bytes) */ 635c0c050c5SMichael Chan struct ret_codes { 636c0c050c5SMichael Chan __le16 error_code; 637c0c050c5SMichael Chan #define HWRM_ERR_CODE_SUCCESS (0x0UL) 638c0c050c5SMichael Chan #define HWRM_ERR_CODE_FAIL (0x1UL) 639c0c050c5SMichael Chan #define HWRM_ERR_CODE_INVALID_PARAMS (0x2UL) 640c0c050c5SMichael Chan #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED (0x3UL) 641c0c050c5SMichael Chan #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR (0x4UL) 642c0c050c5SMichael Chan #define HWRM_ERR_CODE_INVALID_FLAGS (0x5UL) 643c0c050c5SMichael Chan #define HWRM_ERR_CODE_INVALID_ENABLES (0x6UL) 644c0c050c5SMichael Chan #define HWRM_ERR_CODE_HWRM_ERROR (0xfUL) 645c0c050c5SMichael Chan #define HWRM_ERR_CODE_UNKNOWN_ERR (0xfffeUL) 646c0c050c5SMichael Chan #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED (0xffffUL) 647c0c050c5SMichael Chan __le16 unused_0[3]; 648c0c050c5SMichael Chan }; 649c0c050c5SMichael Chan 650c0c050c5SMichael Chan /* Output (16 bytes) */ 651c0c050c5SMichael Chan struct hwrm_err_output { 652c0c050c5SMichael Chan __le16 error_code; 653c0c050c5SMichael Chan __le16 req_type; 654c0c050c5SMichael Chan __le16 seq_id; 655c0c050c5SMichael Chan __le16 resp_len; 656c0c050c5SMichael Chan __le32 opaque_0; 657c0c050c5SMichael Chan __le16 opaque_1; 658c193554eSMichael Chan u8 cmd_err; 659c0c050c5SMichael Chan u8 valid; 660c0c050c5SMichael Chan }; 661c0c050c5SMichael Chan 662c0c050c5SMichael Chan /* Port Tx Statistics Formats (408 bytes) */ 663c0c050c5SMichael Chan struct tx_port_stats { 664c0c050c5SMichael Chan __le64 tx_64b_frames; 665c0c050c5SMichael Chan __le64 tx_65b_127b_frames; 666c0c050c5SMichael Chan __le64 tx_128b_255b_frames; 667c0c050c5SMichael Chan __le64 tx_256b_511b_frames; 668c0c050c5SMichael Chan __le64 tx_512b_1023b_frames; 669c0c050c5SMichael Chan __le64 tx_1024b_1518_frames; 670c0c050c5SMichael Chan __le64 tx_good_vlan_frames; 671c0c050c5SMichael Chan __le64 tx_1519b_2047_frames; 672c0c050c5SMichael Chan __le64 tx_2048b_4095b_frames; 673c0c050c5SMichael Chan __le64 tx_4096b_9216b_frames; 674c0c050c5SMichael Chan __le64 tx_9217b_16383b_frames; 675c0c050c5SMichael Chan __le64 tx_good_frames; 676c0c050c5SMichael Chan __le64 tx_total_frames; 677c0c050c5SMichael Chan __le64 tx_ucast_frames; 678c0c050c5SMichael Chan __le64 tx_mcast_frames; 679c0c050c5SMichael Chan __le64 tx_bcast_frames; 680c0c050c5SMichael Chan __le64 tx_pause_frames; 681c0c050c5SMichael Chan __le64 tx_pfc_frames; 682c0c050c5SMichael Chan __le64 tx_jabber_frames; 683c0c050c5SMichael Chan __le64 tx_fcs_err_frames; 684c0c050c5SMichael Chan __le64 tx_control_frames; 685c0c050c5SMichael Chan __le64 tx_oversz_frames; 686c0c050c5SMichael Chan __le64 tx_single_dfrl_frames; 687c0c050c5SMichael Chan __le64 tx_multi_dfrl_frames; 688c0c050c5SMichael Chan __le64 tx_single_coll_frames; 689c0c050c5SMichael Chan __le64 tx_multi_coll_frames; 690c0c050c5SMichael Chan __le64 tx_late_coll_frames; 691c0c050c5SMichael Chan __le64 tx_excessive_coll_frames; 692c0c050c5SMichael Chan __le64 tx_frag_frames; 693c0c050c5SMichael Chan __le64 tx_err; 694c0c050c5SMichael Chan __le64 tx_tagged_frames; 695c0c050c5SMichael Chan __le64 tx_dbl_tagged_frames; 696c0c050c5SMichael Chan __le64 tx_runt_frames; 697c0c050c5SMichael Chan __le64 tx_fifo_underruns; 698c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri0; 699c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri1; 700c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri2; 701c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri3; 702c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri4; 703c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri5; 704c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri6; 705c0c050c5SMichael Chan __le64 tx_pfc_ena_frames_pri7; 706c0c050c5SMichael Chan __le64 tx_eee_lpi_events; 707c0c050c5SMichael Chan __le64 tx_eee_lpi_duration; 708c0c050c5SMichael Chan __le64 tx_llfc_logical_msgs; 709c0c050c5SMichael Chan __le64 tx_hcfc_msgs; 710c0c050c5SMichael Chan __le64 tx_total_collisions; 711c0c050c5SMichael Chan __le64 tx_bytes; 712c0c050c5SMichael Chan __le64 tx_xthol_frames; 713c0c050c5SMichael Chan __le64 tx_stat_discard; 714c0c050c5SMichael Chan __le64 tx_stat_error; 715c0c050c5SMichael Chan }; 716c0c050c5SMichael Chan 717c0c050c5SMichael Chan /* Port Rx Statistics Formats (528 bytes) */ 718c0c050c5SMichael Chan struct rx_port_stats { 719c0c050c5SMichael Chan __le64 rx_64b_frames; 720c0c050c5SMichael Chan __le64 rx_65b_127b_frames; 721c0c050c5SMichael Chan __le64 rx_128b_255b_frames; 722c0c050c5SMichael Chan __le64 rx_256b_511b_frames; 723c0c050c5SMichael Chan __le64 rx_512b_1023b_frames; 724c0c050c5SMichael Chan __le64 rx_1024b_1518_frames; 725c0c050c5SMichael Chan __le64 rx_good_vlan_frames; 726c0c050c5SMichael Chan __le64 rx_1519b_2047b_frames; 727c0c050c5SMichael Chan __le64 rx_2048b_4095b_frames; 728c0c050c5SMichael Chan __le64 rx_4096b_9216b_frames; 729c0c050c5SMichael Chan __le64 rx_9217b_16383b_frames; 730c0c050c5SMichael Chan __le64 rx_total_frames; 731c0c050c5SMichael Chan __le64 rx_ucast_frames; 732c0c050c5SMichael Chan __le64 rx_mcast_frames; 733c0c050c5SMichael Chan __le64 rx_bcast_frames; 734c0c050c5SMichael Chan __le64 rx_fcs_err_frames; 735c0c050c5SMichael Chan __le64 rx_ctrl_frames; 736c0c050c5SMichael Chan __le64 rx_pause_frames; 737c0c050c5SMichael Chan __le64 rx_pfc_frames; 738c0c050c5SMichael Chan __le64 rx_unsupported_opcode_frames; 739c0c050c5SMichael Chan __le64 rx_unsupported_da_pausepfc_frames; 740c0c050c5SMichael Chan __le64 rx_wrong_sa_frames; 741c0c050c5SMichael Chan __le64 rx_align_err_frames; 742c0c050c5SMichael Chan __le64 rx_oor_len_frames; 743c0c050c5SMichael Chan __le64 rx_code_err_frames; 744c0c050c5SMichael Chan __le64 rx_false_carrier_frames; 745c0c050c5SMichael Chan __le64 rx_ovrsz_frames; 746c0c050c5SMichael Chan __le64 rx_jbr_frames; 747c0c050c5SMichael Chan __le64 rx_mtu_err_frames; 748c0c050c5SMichael Chan __le64 rx_match_crc_frames; 749c0c050c5SMichael Chan __le64 rx_promiscuous_frames; 750c0c050c5SMichael Chan __le64 rx_tagged_frames; 751c0c050c5SMichael Chan __le64 rx_double_tagged_frames; 752c0c050c5SMichael Chan __le64 rx_trunc_frames; 753c0c050c5SMichael Chan __le64 rx_good_frames; 754c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri0; 755c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri1; 756c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri2; 757c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri3; 758c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri4; 759c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri5; 760c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri6; 761c0c050c5SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri7; 762c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri0; 763c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri1; 764c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri2; 765c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri3; 766c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri4; 767c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri5; 768c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri6; 769c0c050c5SMichael Chan __le64 rx_pfc_ena_frames_pri7; 770c0c050c5SMichael Chan __le64 rx_sch_crc_err_frames; 771c0c050c5SMichael Chan __le64 rx_undrsz_frames; 772c0c050c5SMichael Chan __le64 rx_frag_frames; 773c0c050c5SMichael Chan __le64 rx_eee_lpi_events; 774c0c050c5SMichael Chan __le64 rx_eee_lpi_duration; 775c0c050c5SMichael Chan __le64 rx_llfc_physical_msgs; 776c0c050c5SMichael Chan __le64 rx_llfc_logical_msgs; 777c0c050c5SMichael Chan __le64 rx_llfc_msgs_with_crc_err; 778c0c050c5SMichael Chan __le64 rx_hcfc_msgs; 779c0c050c5SMichael Chan __le64 rx_hcfc_msgs_with_crc_err; 780c0c050c5SMichael Chan __le64 rx_bytes; 781c0c050c5SMichael Chan __le64 rx_runt_bytes; 782c0c050c5SMichael Chan __le64 rx_runt_frames; 783c0c050c5SMichael Chan __le64 rx_stat_discard; 784c0c050c5SMichael Chan __le64 rx_stat_err; 785c0c050c5SMichael Chan }; 786c0c050c5SMichael Chan 787c0c050c5SMichael Chan /* hwrm_ver_get */ 788c0c050c5SMichael Chan /* Input (24 bytes) */ 789c0c050c5SMichael Chan struct hwrm_ver_get_input { 790c0c050c5SMichael Chan __le16 req_type; 791c0c050c5SMichael Chan __le16 cmpl_ring; 792c0c050c5SMichael Chan __le16 seq_id; 793c0c050c5SMichael Chan __le16 target_id; 794c0c050c5SMichael Chan __le64 resp_addr; 795c0c050c5SMichael Chan u8 hwrm_intf_maj; 796c0c050c5SMichael Chan u8 hwrm_intf_min; 797c0c050c5SMichael Chan u8 hwrm_intf_upd; 798c0c050c5SMichael Chan u8 unused_0[5]; 799c0c050c5SMichael Chan }; 800c0c050c5SMichael Chan 801c0c050c5SMichael Chan /* Output (128 bytes) */ 802c0c050c5SMichael Chan struct hwrm_ver_get_output { 803c0c050c5SMichael Chan __le16 error_code; 804c0c050c5SMichael Chan __le16 req_type; 805c0c050c5SMichael Chan __le16 seq_id; 806c0c050c5SMichael Chan __le16 resp_len; 807c0c050c5SMichael Chan u8 hwrm_intf_maj; 808c0c050c5SMichael Chan u8 hwrm_intf_min; 809c0c050c5SMichael Chan u8 hwrm_intf_upd; 810c0c050c5SMichael Chan u8 hwrm_intf_rsvd; 811c0c050c5SMichael Chan u8 hwrm_fw_maj; 812c0c050c5SMichael Chan u8 hwrm_fw_min; 813c0c050c5SMichael Chan u8 hwrm_fw_bld; 814c0c050c5SMichael Chan u8 hwrm_fw_rsvd; 815c193554eSMichael Chan u8 mgmt_fw_maj; 816c193554eSMichael Chan u8 mgmt_fw_min; 817c193554eSMichael Chan u8 mgmt_fw_bld; 818c193554eSMichael Chan u8 mgmt_fw_rsvd; 819c193554eSMichael Chan u8 netctrl_fw_maj; 820c193554eSMichael Chan u8 netctrl_fw_min; 821c193554eSMichael Chan u8 netctrl_fw_bld; 822c193554eSMichael Chan u8 netctrl_fw_rsvd; 823c193554eSMichael Chan __le32 reserved1; 824c193554eSMichael Chan u8 roce_fw_maj; 825c193554eSMichael Chan u8 roce_fw_min; 826c193554eSMichael Chan u8 roce_fw_bld; 827c193554eSMichael Chan u8 roce_fw_rsvd; 828c0c050c5SMichael Chan char hwrm_fw_name[16]; 829c193554eSMichael Chan char mgmt_fw_name[16]; 830c193554eSMichael Chan char netctrl_fw_name[16]; 831c193554eSMichael Chan __le32 reserved2[4]; 832c193554eSMichael Chan char roce_fw_name[16]; 833c0c050c5SMichael Chan __le16 chip_num; 834c0c050c5SMichael Chan u8 chip_rev; 835c0c050c5SMichael Chan u8 chip_metal; 836c0c050c5SMichael Chan u8 chip_bond_id; 837c193554eSMichael Chan u8 chip_platform_type; 838c193554eSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC (0x0UL << 0) 839c193554eSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA (0x1UL << 0) 840c193554eSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM (0x2UL << 0) 841c0c050c5SMichael Chan __le16 max_req_win_len; 842c0c050c5SMichael Chan __le16 max_resp_len; 843c0c050c5SMichael Chan __le16 def_req_timeout; 844c193554eSMichael Chan u8 unused_0; 845c0c050c5SMichael Chan u8 unused_1; 846c0c050c5SMichael Chan u8 unused_2; 847c0c050c5SMichael Chan u8 valid; 848c0c050c5SMichael Chan }; 849c0c050c5SMichael Chan 850c0c050c5SMichael Chan /* hwrm_func_reset */ 851c0c050c5SMichael Chan /* Input (24 bytes) */ 852c0c050c5SMichael Chan struct hwrm_func_reset_input { 853c0c050c5SMichael Chan __le16 req_type; 854c0c050c5SMichael Chan __le16 cmpl_ring; 855c0c050c5SMichael Chan __le16 seq_id; 856c0c050c5SMichael Chan __le16 target_id; 857c0c050c5SMichael Chan __le64 resp_addr; 858c0c050c5SMichael Chan __le32 enables; 859c0c050c5SMichael Chan #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 860c0c050c5SMichael Chan __le16 vf_id; 861c193554eSMichael Chan u8 func_reset_level; 862c193554eSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL (0x0UL << 0) 863c193554eSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME (0x1UL << 0) 864c193554eSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN (0x2UL << 0) 865c193554eSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF (0x3UL << 0) 866c193554eSMichael Chan u8 unused_0; 867c0c050c5SMichael Chan }; 868c0c050c5SMichael Chan 869c0c050c5SMichael Chan /* Output (16 bytes) */ 870c0c050c5SMichael Chan struct hwrm_func_reset_output { 871c0c050c5SMichael Chan __le16 error_code; 872c0c050c5SMichael Chan __le16 req_type; 873c0c050c5SMichael Chan __le16 seq_id; 874c0c050c5SMichael Chan __le16 resp_len; 875c0c050c5SMichael Chan __le32 unused_0; 876c0c050c5SMichael Chan u8 unused_1; 877c0c050c5SMichael Chan u8 unused_2; 878c0c050c5SMichael Chan u8 unused_3; 879c0c050c5SMichael Chan u8 valid; 880c0c050c5SMichael Chan }; 881c0c050c5SMichael Chan 882c0c050c5SMichael Chan /* hwrm_func_getfid */ 883c0c050c5SMichael Chan /* Input (24 bytes) */ 884c0c050c5SMichael Chan struct hwrm_func_getfid_input { 885c0c050c5SMichael Chan __le16 req_type; 886c0c050c5SMichael Chan __le16 cmpl_ring; 887c0c050c5SMichael Chan __le16 seq_id; 888c0c050c5SMichael Chan __le16 target_id; 889c0c050c5SMichael Chan __le64 resp_addr; 890c0c050c5SMichael Chan __le32 enables; 891c0c050c5SMichael Chan #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 892c0c050c5SMichael Chan __le16 pci_id; 893c0c050c5SMichael Chan __le16 unused_0; 894c0c050c5SMichael Chan }; 895c0c050c5SMichael Chan 896c0c050c5SMichael Chan /* Output (16 bytes) */ 897c0c050c5SMichael Chan struct hwrm_func_getfid_output { 898c0c050c5SMichael Chan __le16 error_code; 899c0c050c5SMichael Chan __le16 req_type; 900c0c050c5SMichael Chan __le16 seq_id; 901c0c050c5SMichael Chan __le16 resp_len; 902c0c050c5SMichael Chan __le16 fid; 903c0c050c5SMichael Chan u8 unused_0; 904c0c050c5SMichael Chan u8 unused_1; 905c0c050c5SMichael Chan u8 unused_2; 906c0c050c5SMichael Chan u8 unused_3; 907c0c050c5SMichael Chan u8 unused_4; 908c0c050c5SMichael Chan u8 valid; 909c0c050c5SMichael Chan }; 910c0c050c5SMichael Chan 911c0c050c5SMichael Chan /* hwrm_func_vf_alloc */ 912c0c050c5SMichael Chan /* Input (24 bytes) */ 913c0c050c5SMichael Chan struct hwrm_func_vf_alloc_input { 914c0c050c5SMichael Chan __le16 req_type; 915c0c050c5SMichael Chan __le16 cmpl_ring; 916c0c050c5SMichael Chan __le16 seq_id; 917c0c050c5SMichael Chan __le16 target_id; 918c0c050c5SMichael Chan __le64 resp_addr; 919c0c050c5SMichael Chan __le32 enables; 920c0c050c5SMichael Chan #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 921c0c050c5SMichael Chan __le16 first_vf_id; 922c0c050c5SMichael Chan __le16 num_vfs; 923c0c050c5SMichael Chan }; 924c0c050c5SMichael Chan 925c0c050c5SMichael Chan /* Output (16 bytes) */ 926c0c050c5SMichael Chan struct hwrm_func_vf_alloc_output { 927c0c050c5SMichael Chan __le16 error_code; 928c0c050c5SMichael Chan __le16 req_type; 929c0c050c5SMichael Chan __le16 seq_id; 930c0c050c5SMichael Chan __le16 resp_len; 931c0c050c5SMichael Chan __le16 first_vf_id; 932c0c050c5SMichael Chan u8 unused_0; 933c0c050c5SMichael Chan u8 unused_1; 934c0c050c5SMichael Chan u8 unused_2; 935c0c050c5SMichael Chan u8 unused_3; 936c0c050c5SMichael Chan u8 unused_4; 937c0c050c5SMichael Chan u8 valid; 938c0c050c5SMichael Chan }; 939c0c050c5SMichael Chan 940c0c050c5SMichael Chan /* hwrm_func_vf_free */ 941c0c050c5SMichael Chan /* Input (24 bytes) */ 942c0c050c5SMichael Chan struct hwrm_func_vf_free_input { 943c0c050c5SMichael Chan __le16 req_type; 944c0c050c5SMichael Chan __le16 cmpl_ring; 945c0c050c5SMichael Chan __le16 seq_id; 946c0c050c5SMichael Chan __le16 target_id; 947c0c050c5SMichael Chan __le64 resp_addr; 948c0c050c5SMichael Chan __le32 enables; 949c0c050c5SMichael Chan #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 950c0c050c5SMichael Chan __le16 first_vf_id; 951c0c050c5SMichael Chan __le16 num_vfs; 952c0c050c5SMichael Chan }; 953c0c050c5SMichael Chan 954c0c050c5SMichael Chan /* Output (16 bytes) */ 955c0c050c5SMichael Chan struct hwrm_func_vf_free_output { 956c0c050c5SMichael Chan __le16 error_code; 957c0c050c5SMichael Chan __le16 req_type; 958c0c050c5SMichael Chan __le16 seq_id; 959c0c050c5SMichael Chan __le16 resp_len; 960c0c050c5SMichael Chan __le32 unused_0; 961c0c050c5SMichael Chan u8 unused_1; 962c0c050c5SMichael Chan u8 unused_2; 963c0c050c5SMichael Chan u8 unused_3; 964c0c050c5SMichael Chan u8 valid; 965c0c050c5SMichael Chan }; 966c0c050c5SMichael Chan 967c0c050c5SMichael Chan /* hwrm_func_vf_cfg */ 968c193554eSMichael Chan /* Input (32 bytes) */ 969c0c050c5SMichael Chan struct hwrm_func_vf_cfg_input { 970c0c050c5SMichael Chan __le16 req_type; 971c0c050c5SMichael Chan __le16 cmpl_ring; 972c0c050c5SMichael Chan __le16 seq_id; 973c0c050c5SMichael Chan __le16 target_id; 974c0c050c5SMichael Chan __le64 resp_addr; 975c0c050c5SMichael Chan __le32 enables; 976c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 977c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 978c193554eSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 97911f15ed3SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 980c0c050c5SMichael Chan __le16 mtu; 981c0c050c5SMichael Chan __le16 guest_vlan; 982c193554eSMichael Chan __le16 async_event_cr; 98311f15ed3SMichael Chan u8 dflt_mac_addr[6]; 984c0c050c5SMichael Chan }; 985c0c050c5SMichael Chan 986c0c050c5SMichael Chan /* Output (16 bytes) */ 987c0c050c5SMichael Chan struct hwrm_func_vf_cfg_output { 988c0c050c5SMichael Chan __le16 error_code; 989c0c050c5SMichael Chan __le16 req_type; 990c0c050c5SMichael Chan __le16 seq_id; 991c0c050c5SMichael Chan __le16 resp_len; 992c0c050c5SMichael Chan __le32 unused_0; 993c0c050c5SMichael Chan u8 unused_1; 994c0c050c5SMichael Chan u8 unused_2; 995c0c050c5SMichael Chan u8 unused_3; 996c0c050c5SMichael Chan u8 valid; 997c0c050c5SMichael Chan }; 998c0c050c5SMichael Chan 999c0c050c5SMichael Chan /* hwrm_func_qcaps */ 1000c0c050c5SMichael Chan /* Input (24 bytes) */ 1001c0c050c5SMichael Chan struct hwrm_func_qcaps_input { 1002c0c050c5SMichael Chan __le16 req_type; 1003c0c050c5SMichael Chan __le16 cmpl_ring; 1004c0c050c5SMichael Chan __le16 seq_id; 1005c0c050c5SMichael Chan __le16 target_id; 1006c0c050c5SMichael Chan __le64 resp_addr; 1007c0c050c5SMichael Chan __le16 fid; 1008c0c050c5SMichael Chan __le16 unused_0[3]; 1009c0c050c5SMichael Chan }; 1010c0c050c5SMichael Chan 1011c0c050c5SMichael Chan /* Output (80 bytes) */ 1012c0c050c5SMichael Chan struct hwrm_func_qcaps_output { 1013c0c050c5SMichael Chan __le16 error_code; 1014c0c050c5SMichael Chan __le16 req_type; 1015c0c050c5SMichael Chan __le16 seq_id; 1016c0c050c5SMichael Chan __le16 resp_len; 1017c0c050c5SMichael Chan __le16 fid; 1018c0c050c5SMichael Chan __le16 port_id; 1019c0c050c5SMichael Chan __le32 flags; 1020c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1021c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 102211f15ed3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 102311f15ed3SMichael Chan u8 mac_address[6]; 1024c0c050c5SMichael Chan __le16 max_rsscos_ctx; 1025c0c050c5SMichael Chan __le16 max_cmpl_rings; 1026c0c050c5SMichael Chan __le16 max_tx_rings; 1027c0c050c5SMichael Chan __le16 max_rx_rings; 1028c0c050c5SMichael Chan __le16 max_l2_ctxs; 1029c0c050c5SMichael Chan __le16 max_vnics; 1030c0c050c5SMichael Chan __le16 first_vf_id; 1031c0c050c5SMichael Chan __le16 max_vfs; 1032c0c050c5SMichael Chan __le16 max_stat_ctx; 1033c0c050c5SMichael Chan __le32 max_encap_records; 1034c0c050c5SMichael Chan __le32 max_decap_records; 1035c0c050c5SMichael Chan __le32 max_tx_em_flows; 1036c0c050c5SMichael Chan __le32 max_tx_wm_flows; 1037c0c050c5SMichael Chan __le32 max_rx_em_flows; 1038c0c050c5SMichael Chan __le32 max_rx_wm_flows; 1039c0c050c5SMichael Chan __le32 max_mcast_filters; 1040c0c050c5SMichael Chan __le32 max_flow_id; 1041c0c050c5SMichael Chan __le32 max_hw_ring_grps; 1042c0c050c5SMichael Chan u8 unused_0; 1043c0c050c5SMichael Chan u8 unused_1; 1044c0c050c5SMichael Chan u8 unused_2; 1045c0c050c5SMichael Chan u8 valid; 1046c0c050c5SMichael Chan }; 1047c0c050c5SMichael Chan 104811f15ed3SMichael Chan /* hwrm_func_qcfg */ 104911f15ed3SMichael Chan /* Input (24 bytes) */ 105011f15ed3SMichael Chan struct hwrm_func_qcfg_input { 105111f15ed3SMichael Chan __le16 req_type; 105211f15ed3SMichael Chan __le16 cmpl_ring; 105311f15ed3SMichael Chan __le16 seq_id; 105411f15ed3SMichael Chan __le16 target_id; 105511f15ed3SMichael Chan __le64 resp_addr; 105611f15ed3SMichael Chan __le16 fid; 105711f15ed3SMichael Chan __le16 unused_0[3]; 105811f15ed3SMichael Chan }; 105911f15ed3SMichael Chan 106011f15ed3SMichael Chan /* Output (72 bytes) */ 106111f15ed3SMichael Chan struct hwrm_func_qcfg_output { 106211f15ed3SMichael Chan __le16 error_code; 106311f15ed3SMichael Chan __le16 req_type; 106411f15ed3SMichael Chan __le16 seq_id; 106511f15ed3SMichael Chan __le16 resp_len; 106611f15ed3SMichael Chan __le16 fid; 106711f15ed3SMichael Chan __le16 port_id; 106811f15ed3SMichael Chan __le16 vlan; 106911f15ed3SMichael Chan u8 unused_0; 107011f15ed3SMichael Chan u8 unused_1; 107111f15ed3SMichael Chan u8 mac_address[6]; 107211f15ed3SMichael Chan __le16 pci_id; 107311f15ed3SMichael Chan __le16 alloc_rsscos_ctx; 107411f15ed3SMichael Chan __le16 alloc_cmpl_rings; 107511f15ed3SMichael Chan __le16 alloc_tx_rings; 107611f15ed3SMichael Chan __le16 alloc_rx_rings; 107711f15ed3SMichael Chan __le16 alloc_l2_ctx; 107811f15ed3SMichael Chan __le16 alloc_vnics; 107911f15ed3SMichael Chan __le16 mtu; 108011f15ed3SMichael Chan __le16 mru; 108111f15ed3SMichael Chan __le16 stat_ctx_id; 108211f15ed3SMichael Chan u8 port_partition_type; 108311f15ed3SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF (0x0UL << 0) 108411f15ed3SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS (0x1UL << 0) 108511f15ed3SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 (0x2UL << 0) 108611f15ed3SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 (0x3UL << 0) 108711f15ed3SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 (0x4UL << 0) 108811f15ed3SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN (0xffUL << 0) 108911f15ed3SMichael Chan u8 unused_2; 109011f15ed3SMichael Chan __le16 dflt_vnic_id; 109111f15ed3SMichael Chan u8 unused_3; 109211f15ed3SMichael Chan u8 unused_4; 109311f15ed3SMichael Chan __le32 min_bw; 109411f15ed3SMichael Chan __le32 max_bw; 109511f15ed3SMichael Chan u8 evb_mode; 109611f15ed3SMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB (0x0UL << 0) 109711f15ed3SMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEB (0x1UL << 0) 109811f15ed3SMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEPA (0x2UL << 0) 109911f15ed3SMichael Chan u8 unused_5; 110011f15ed3SMichael Chan __le16 unused_6; 110111f15ed3SMichael Chan __le32 alloc_mcast_filters; 110211f15ed3SMichael Chan __le32 alloc_hw_ring_grps; 110311f15ed3SMichael Chan u8 unused_7; 110411f15ed3SMichael Chan u8 unused_8; 110511f15ed3SMichael Chan u8 unused_9; 110611f15ed3SMichael Chan u8 valid; 110711f15ed3SMichael Chan }; 110811f15ed3SMichael Chan 1109c0c050c5SMichael Chan /* hwrm_func_cfg */ 1110c0c050c5SMichael Chan /* Input (88 bytes) */ 1111c0c050c5SMichael Chan struct hwrm_func_cfg_input { 1112c0c050c5SMichael Chan __le16 req_type; 1113c0c050c5SMichael Chan __le16 cmpl_ring; 1114c0c050c5SMichael Chan __le16 seq_id; 1115c0c050c5SMichael Chan __le16 target_id; 1116c0c050c5SMichael Chan __le64 resp_addr; 1117c193554eSMichael Chan __le16 fid; 1118c0c050c5SMichael Chan u8 unused_0; 1119c0c050c5SMichael Chan u8 unused_1; 1120c0c050c5SMichael Chan __le32 flags; 1121c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_PROM_MODE 0x1UL 1122c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK 0x2UL 1123c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_IP_ADDR_CHECK 0x4UL 1124c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_VLAN_PRI_MATCH 0x8UL 1125c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_DFLT_PRI_NOMATCH 0x10UL 1126c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_DISABLE_PAUSE 0x20UL 1127c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_DISABLE_STP 0x40UL 1128c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_DISABLE_LLDP 0x80UL 1129c0c050c5SMichael Chan #define FUNC_CFG_REQ_FLAGS_DISABLE_PTPV2 0x100UL 1130c0c050c5SMichael Chan __le32 enables; 1131c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1132c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1133c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1134c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1135c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1136c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1137c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1138c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1139c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1140c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1141c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1142c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1143c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1144c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1145c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1146c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1147c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1148c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1149c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1150c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1151c0c050c5SMichael Chan __le16 mtu; 1152c0c050c5SMichael Chan __le16 mru; 1153c0c050c5SMichael Chan __le16 num_rsscos_ctxs; 1154c0c050c5SMichael Chan __le16 num_cmpl_rings; 1155c0c050c5SMichael Chan __le16 num_tx_rings; 1156c0c050c5SMichael Chan __le16 num_rx_rings; 1157c0c050c5SMichael Chan __le16 num_l2_ctxs; 1158c0c050c5SMichael Chan __le16 num_vnics; 1159c0c050c5SMichael Chan __le16 num_stat_ctxs; 1160c0c050c5SMichael Chan __le16 num_hw_ring_grps; 1161c0c050c5SMichael Chan u8 dflt_mac_addr[6]; 1162c0c050c5SMichael Chan __le16 dflt_vlan; 1163c0c050c5SMichael Chan __be32 dflt_ip_addr[4]; 1164c0c050c5SMichael Chan __le32 min_bw; 1165c0c050c5SMichael Chan __le32 max_bw; 1166c0c050c5SMichael Chan __le16 async_event_cr; 1167c0c050c5SMichael Chan u8 vlan_antispoof_mode; 1168c0c050c5SMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK (0x0UL << 0) 1169c0c050c5SMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN (0x1UL << 0) 1170c0c050c5SMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE (0x2UL << 0) 1171c0c050c5SMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN (0x3UL << 0) 1172c0c050c5SMichael Chan u8 allowed_vlan_pris; 1173c0c050c5SMichael Chan u8 evb_mode; 1174c0c050c5SMichael Chan #define FUNC_CFG_REQ_EVB_MODE_NO_EVB (0x0UL << 0) 1175c0c050c5SMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEB (0x1UL << 0) 1176c0c050c5SMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEPA (0x2UL << 0) 1177c0c050c5SMichael Chan u8 unused_2; 1178c0c050c5SMichael Chan __le16 num_mcast_filters; 1179c0c050c5SMichael Chan }; 1180c0c050c5SMichael Chan 1181c0c050c5SMichael Chan /* Output (16 bytes) */ 1182c0c050c5SMichael Chan struct hwrm_func_cfg_output { 1183c0c050c5SMichael Chan __le16 error_code; 1184c0c050c5SMichael Chan __le16 req_type; 1185c0c050c5SMichael Chan __le16 seq_id; 1186c0c050c5SMichael Chan __le16 resp_len; 1187c0c050c5SMichael Chan __le32 unused_0; 1188c0c050c5SMichael Chan u8 unused_1; 1189c0c050c5SMichael Chan u8 unused_2; 1190c0c050c5SMichael Chan u8 unused_3; 1191c0c050c5SMichael Chan u8 valid; 1192c0c050c5SMichael Chan }; 1193c0c050c5SMichael Chan 1194c0c050c5SMichael Chan /* hwrm_func_qstats */ 1195c0c050c5SMichael Chan /* Input (24 bytes) */ 1196c0c050c5SMichael Chan struct hwrm_func_qstats_input { 1197c0c050c5SMichael Chan __le16 req_type; 1198c0c050c5SMichael Chan __le16 cmpl_ring; 1199c0c050c5SMichael Chan __le16 seq_id; 1200c0c050c5SMichael Chan __le16 target_id; 1201c0c050c5SMichael Chan __le64 resp_addr; 1202c0c050c5SMichael Chan __le16 fid; 1203c0c050c5SMichael Chan __le16 unused_0[3]; 1204c0c050c5SMichael Chan }; 1205c0c050c5SMichael Chan 1206c0c050c5SMichael Chan /* Output (176 bytes) */ 1207c0c050c5SMichael Chan struct hwrm_func_qstats_output { 1208c0c050c5SMichael Chan __le16 error_code; 1209c0c050c5SMichael Chan __le16 req_type; 1210c0c050c5SMichael Chan __le16 seq_id; 1211c0c050c5SMichael Chan __le16 resp_len; 1212c0c050c5SMichael Chan __le64 tx_ucast_pkts; 1213c0c050c5SMichael Chan __le64 tx_mcast_pkts; 1214c0c050c5SMichael Chan __le64 tx_bcast_pkts; 1215c0c050c5SMichael Chan __le64 tx_err_pkts; 1216c0c050c5SMichael Chan __le64 tx_drop_pkts; 1217c0c050c5SMichael Chan __le64 tx_ucast_bytes; 1218c0c050c5SMichael Chan __le64 tx_mcast_bytes; 1219c0c050c5SMichael Chan __le64 tx_bcast_bytes; 1220c0c050c5SMichael Chan __le64 rx_ucast_pkts; 1221c0c050c5SMichael Chan __le64 rx_mcast_pkts; 1222c0c050c5SMichael Chan __le64 rx_bcast_pkts; 1223c0c050c5SMichael Chan __le64 rx_err_pkts; 1224c0c050c5SMichael Chan __le64 rx_drop_pkts; 1225c0c050c5SMichael Chan __le64 rx_ucast_bytes; 1226c0c050c5SMichael Chan __le64 rx_mcast_bytes; 1227c0c050c5SMichael Chan __le64 rx_bcast_bytes; 1228c0c050c5SMichael Chan __le64 rx_agg_pkts; 1229c0c050c5SMichael Chan __le64 rx_agg_bytes; 1230c0c050c5SMichael Chan __le64 rx_agg_events; 1231c0c050c5SMichael Chan __le64 rx_agg_aborts; 1232c0c050c5SMichael Chan __le32 unused_0; 1233c0c050c5SMichael Chan u8 unused_1; 1234c0c050c5SMichael Chan u8 unused_2; 1235c0c050c5SMichael Chan u8 unused_3; 1236c0c050c5SMichael Chan u8 valid; 1237c0c050c5SMichael Chan }; 1238c0c050c5SMichael Chan 1239c0c050c5SMichael Chan /* hwrm_func_clr_stats */ 1240c0c050c5SMichael Chan /* Input (24 bytes) */ 1241c0c050c5SMichael Chan struct hwrm_func_clr_stats_input { 1242c0c050c5SMichael Chan __le16 req_type; 1243c0c050c5SMichael Chan __le16 cmpl_ring; 1244c0c050c5SMichael Chan __le16 seq_id; 1245c0c050c5SMichael Chan __le16 target_id; 1246c0c050c5SMichael Chan __le64 resp_addr; 1247c0c050c5SMichael Chan __le16 fid; 1248c0c050c5SMichael Chan __le16 unused_0[3]; 1249c0c050c5SMichael Chan }; 1250c0c050c5SMichael Chan 1251c0c050c5SMichael Chan /* Output (16 bytes) */ 1252c0c050c5SMichael Chan struct hwrm_func_clr_stats_output { 1253c0c050c5SMichael Chan __le16 error_code; 1254c0c050c5SMichael Chan __le16 req_type; 1255c0c050c5SMichael Chan __le16 seq_id; 1256c0c050c5SMichael Chan __le16 resp_len; 1257c0c050c5SMichael Chan __le32 unused_0; 1258c0c050c5SMichael Chan u8 unused_1; 1259c0c050c5SMichael Chan u8 unused_2; 1260c0c050c5SMichael Chan u8 unused_3; 1261c0c050c5SMichael Chan u8 valid; 1262c0c050c5SMichael Chan }; 1263c0c050c5SMichael Chan 1264c0c050c5SMichael Chan /* hwrm_func_vf_resc_free */ 1265c0c050c5SMichael Chan /* Input (24 bytes) */ 1266c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_input { 1267c0c050c5SMichael Chan __le16 req_type; 1268c0c050c5SMichael Chan __le16 cmpl_ring; 1269c0c050c5SMichael Chan __le16 seq_id; 1270c0c050c5SMichael Chan __le16 target_id; 1271c0c050c5SMichael Chan __le64 resp_addr; 1272c0c050c5SMichael Chan __le16 vf_id; 1273c0c050c5SMichael Chan __le16 unused_0[3]; 1274c0c050c5SMichael Chan }; 1275c0c050c5SMichael Chan 1276c0c050c5SMichael Chan /* Output (16 bytes) */ 1277c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_output { 1278c0c050c5SMichael Chan __le16 error_code; 1279c0c050c5SMichael Chan __le16 req_type; 1280c0c050c5SMichael Chan __le16 seq_id; 1281c0c050c5SMichael Chan __le16 resp_len; 1282c0c050c5SMichael Chan __le32 unused_0; 1283c0c050c5SMichael Chan u8 unused_1; 1284c0c050c5SMichael Chan u8 unused_2; 1285c0c050c5SMichael Chan u8 unused_3; 1286c0c050c5SMichael Chan u8 valid; 1287c0c050c5SMichael Chan }; 1288c0c050c5SMichael Chan 1289c0c050c5SMichael Chan /* hwrm_func_vf_vnic_ids_query */ 1290c0c050c5SMichael Chan /* Input (32 bytes) */ 1291c0c050c5SMichael Chan struct hwrm_func_vf_vnic_ids_query_input { 1292c0c050c5SMichael Chan __le16 req_type; 1293c0c050c5SMichael Chan __le16 cmpl_ring; 1294c0c050c5SMichael Chan __le16 seq_id; 1295c0c050c5SMichael Chan __le16 target_id; 1296c0c050c5SMichael Chan __le64 resp_addr; 1297c0c050c5SMichael Chan __le16 vf_id; 1298c0c050c5SMichael Chan u8 unused_0; 1299c0c050c5SMichael Chan u8 unused_1; 1300c0c050c5SMichael Chan __le32 max_vnic_id_cnt; 1301c0c050c5SMichael Chan __le64 vnic_id_tbl_addr; 1302c0c050c5SMichael Chan }; 1303c0c050c5SMichael Chan 1304c0c050c5SMichael Chan /* Output (16 bytes) */ 1305c0c050c5SMichael Chan struct hwrm_func_vf_vnic_ids_query_output { 1306c0c050c5SMichael Chan __le16 error_code; 1307c0c050c5SMichael Chan __le16 req_type; 1308c0c050c5SMichael Chan __le16 seq_id; 1309c0c050c5SMichael Chan __le16 resp_len; 1310c0c050c5SMichael Chan __le32 vnic_id_cnt; 1311c0c050c5SMichael Chan u8 unused_0; 1312c0c050c5SMichael Chan u8 unused_1; 1313c0c050c5SMichael Chan u8 unused_2; 1314c0c050c5SMichael Chan u8 valid; 1315c0c050c5SMichael Chan }; 1316c0c050c5SMichael Chan 1317c0c050c5SMichael Chan /* hwrm_func_drv_rgtr */ 1318c0c050c5SMichael Chan /* Input (80 bytes) */ 1319c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_input { 1320c0c050c5SMichael Chan __le16 req_type; 1321c0c050c5SMichael Chan __le16 cmpl_ring; 1322c0c050c5SMichael Chan __le16 seq_id; 1323c0c050c5SMichael Chan __le16 target_id; 1324c0c050c5SMichael Chan __le64 resp_addr; 1325c0c050c5SMichael Chan __le32 flags; 1326c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1327c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1328c0c050c5SMichael Chan __le32 enables; 1329c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1330c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1331c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1332c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1333c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1334c0c050c5SMichael Chan __le16 os_type; 1335c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN (0x0UL << 0) 1336c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER (0x1UL << 0) 1337c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS (0xeUL << 0) 133811f15ed3SMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS (0x12UL << 0) 1339c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS (0x1dUL << 0) 1340c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX (0x24UL << 0) 1341c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD (0x2aUL << 0) 1342c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI (0x68UL << 0) 1343c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 (0x73UL << 0) 1344c193554eSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 (0x74UL << 0) 1345c0c050c5SMichael Chan u8 ver_maj; 1346c0c050c5SMichael Chan u8 ver_min; 1347c0c050c5SMichael Chan u8 ver_upd; 1348c0c050c5SMichael Chan u8 unused_0; 1349c0c050c5SMichael Chan __le16 unused_1; 1350c0c050c5SMichael Chan __le32 timestamp; 1351c0c050c5SMichael Chan __le32 unused_2; 1352c0c050c5SMichael Chan __le32 vf_req_fwd[8]; 1353c0c050c5SMichael Chan __le32 async_event_fwd[8]; 1354c0c050c5SMichael Chan }; 1355c0c050c5SMichael Chan 1356c0c050c5SMichael Chan /* Output (16 bytes) */ 1357c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_output { 1358c0c050c5SMichael Chan __le16 error_code; 1359c0c050c5SMichael Chan __le16 req_type; 1360c0c050c5SMichael Chan __le16 seq_id; 1361c0c050c5SMichael Chan __le16 resp_len; 1362c0c050c5SMichael Chan __le32 unused_0; 1363c0c050c5SMichael Chan u8 unused_1; 1364c0c050c5SMichael Chan u8 unused_2; 1365c0c050c5SMichael Chan u8 unused_3; 1366c0c050c5SMichael Chan u8 valid; 1367c0c050c5SMichael Chan }; 1368c0c050c5SMichael Chan 1369c0c050c5SMichael Chan /* hwrm_func_drv_unrgtr */ 1370c0c050c5SMichael Chan /* Input (24 bytes) */ 1371c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_input { 1372c0c050c5SMichael Chan __le16 req_type; 1373c0c050c5SMichael Chan __le16 cmpl_ring; 1374c0c050c5SMichael Chan __le16 seq_id; 1375c0c050c5SMichael Chan __le16 target_id; 1376c0c050c5SMichael Chan __le64 resp_addr; 1377c0c050c5SMichael Chan __le32 flags; 1378c0c050c5SMichael Chan #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1379c0c050c5SMichael Chan __le32 unused_0; 1380c0c050c5SMichael Chan }; 1381c0c050c5SMichael Chan 1382c0c050c5SMichael Chan /* Output (16 bytes) */ 1383c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_output { 1384c0c050c5SMichael Chan __le16 error_code; 1385c0c050c5SMichael Chan __le16 req_type; 1386c0c050c5SMichael Chan __le16 seq_id; 1387c0c050c5SMichael Chan __le16 resp_len; 1388c0c050c5SMichael Chan __le32 unused_0; 1389c0c050c5SMichael Chan u8 unused_1; 1390c0c050c5SMichael Chan u8 unused_2; 1391c0c050c5SMichael Chan u8 unused_3; 1392c0c050c5SMichael Chan u8 valid; 1393c0c050c5SMichael Chan }; 1394c0c050c5SMichael Chan 1395c0c050c5SMichael Chan /* hwrm_func_buf_rgtr */ 1396c0c050c5SMichael Chan /* Input (128 bytes) */ 1397c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_input { 1398c0c050c5SMichael Chan __le16 req_type; 1399c0c050c5SMichael Chan __le16 cmpl_ring; 1400c0c050c5SMichael Chan __le16 seq_id; 1401c0c050c5SMichael Chan __le16 target_id; 1402c0c050c5SMichael Chan __le64 resp_addr; 1403c0c050c5SMichael Chan __le32 enables; 1404c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1405c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1406c0c050c5SMichael Chan __le16 vf_id; 1407c0c050c5SMichael Chan __le16 req_buf_num_pages; 1408c0c050c5SMichael Chan __le16 req_buf_page_size; 1409c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B (0x4UL << 0) 1410c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K (0xcUL << 0) 1411c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K (0xdUL << 0) 1412c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K (0x10UL << 0) 1413c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M (0x16UL << 0) 1414c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M (0x17UL << 0) 1415c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G (0x1eUL << 0) 1416c0c050c5SMichael Chan __le16 req_buf_len; 1417c0c050c5SMichael Chan __le16 resp_buf_len; 1418c0c050c5SMichael Chan u8 unused_0; 1419c0c050c5SMichael Chan u8 unused_1; 1420c0c050c5SMichael Chan __le64 req_buf_page_addr0; 1421c0c050c5SMichael Chan __le64 req_buf_page_addr1; 1422c0c050c5SMichael Chan __le64 req_buf_page_addr2; 1423c0c050c5SMichael Chan __le64 req_buf_page_addr3; 1424c0c050c5SMichael Chan __le64 req_buf_page_addr4; 1425c0c050c5SMichael Chan __le64 req_buf_page_addr5; 1426c0c050c5SMichael Chan __le64 req_buf_page_addr6; 1427c0c050c5SMichael Chan __le64 req_buf_page_addr7; 1428c0c050c5SMichael Chan __le64 req_buf_page_addr8; 1429c0c050c5SMichael Chan __le64 req_buf_page_addr9; 1430c0c050c5SMichael Chan __le64 error_buf_addr; 1431c0c050c5SMichael Chan __le64 resp_buf_addr; 1432c0c050c5SMichael Chan }; 1433c0c050c5SMichael Chan 1434c0c050c5SMichael Chan /* Output (16 bytes) */ 1435c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_output { 1436c0c050c5SMichael Chan __le16 error_code; 1437c0c050c5SMichael Chan __le16 req_type; 1438c0c050c5SMichael Chan __le16 seq_id; 1439c0c050c5SMichael Chan __le16 resp_len; 1440c0c050c5SMichael Chan __le32 unused_0; 1441c0c050c5SMichael Chan u8 unused_1; 1442c0c050c5SMichael Chan u8 unused_2; 1443c0c050c5SMichael Chan u8 unused_3; 1444c0c050c5SMichael Chan u8 valid; 1445c0c050c5SMichael Chan }; 1446c0c050c5SMichael Chan 1447c0c050c5SMichael Chan /* hwrm_func_drv_qver */ 1448c0c050c5SMichael Chan /* Input (24 bytes) */ 1449c0c050c5SMichael Chan struct hwrm_func_drv_qver_input { 1450c0c050c5SMichael Chan __le16 req_type; 1451c0c050c5SMichael Chan __le16 cmpl_ring; 1452c0c050c5SMichael Chan __le16 seq_id; 1453c0c050c5SMichael Chan __le16 target_id; 1454c0c050c5SMichael Chan __le64 resp_addr; 1455c193554eSMichael Chan __le32 reserved; 1456c0c050c5SMichael Chan __le16 fid; 1457c0c050c5SMichael Chan __le16 unused_0; 1458c0c050c5SMichael Chan }; 1459c0c050c5SMichael Chan 1460c0c050c5SMichael Chan /* Output (16 bytes) */ 1461c0c050c5SMichael Chan struct hwrm_func_drv_qver_output { 1462c0c050c5SMichael Chan __le16 error_code; 1463c0c050c5SMichael Chan __le16 req_type; 1464c0c050c5SMichael Chan __le16 seq_id; 1465c0c050c5SMichael Chan __le16 resp_len; 1466c0c050c5SMichael Chan __le16 os_type; 1467c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN (0x0UL << 0) 1468c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER (0x1UL << 0) 1469c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS (0xeUL << 0) 147011f15ed3SMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS (0x12UL << 0) 1471c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS (0x1dUL << 0) 1472c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX (0x24UL << 0) 1473c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD (0x2aUL << 0) 1474c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI (0x68UL << 0) 1475c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 (0x73UL << 0) 1476c193554eSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 (0x74UL << 0) 1477c0c050c5SMichael Chan u8 ver_maj; 1478c0c050c5SMichael Chan u8 ver_min; 1479c0c050c5SMichael Chan u8 ver_upd; 1480c0c050c5SMichael Chan u8 unused_0; 1481c0c050c5SMichael Chan u8 unused_1; 1482c0c050c5SMichael Chan u8 valid; 1483c0c050c5SMichael Chan }; 1484c0c050c5SMichael Chan 1485c0c050c5SMichael Chan /* hwrm_port_phy_cfg */ 148611f15ed3SMichael Chan /* Input (56 bytes) */ 1487c0c050c5SMichael Chan struct hwrm_port_phy_cfg_input { 1488c0c050c5SMichael Chan __le16 req_type; 1489c0c050c5SMichael Chan __le16 cmpl_ring; 1490c0c050c5SMichael Chan __le16 seq_id; 1491c0c050c5SMichael Chan __le16 target_id; 1492c0c050c5SMichael Chan __le64 resp_addr; 1493c0c050c5SMichael Chan __le32 flags; 1494c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1495c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN 0x2UL 1496c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1497c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 149811f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 149911f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 150011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 150111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1502c0c050c5SMichael Chan __le32 enables; 1503c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1504c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1505c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1506c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1507c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1508c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1509c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1510c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1511c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 151211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 151311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1514c0c050c5SMichael Chan __le16 port_id; 1515c0c050c5SMichael Chan __le16 force_link_speed; 1516c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB (0x1UL << 0) 1517c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB (0xaUL << 0) 1518c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB (0x14UL << 0) 1519c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB (0x19UL << 0) 1520c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB (0x64UL << 0) 1521c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB (0xc8UL << 0) 1522c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB (0xfaUL << 0) 1523c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB (0x190UL << 0) 1524c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB (0x1f4UL << 0) 152511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB (0x3e8UL << 0) 152611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB (0xffffUL << 0) 1527c0c050c5SMichael Chan u8 auto_mode; 1528c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE (0x0UL << 0) 1529c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1530c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1531c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 153211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK (0x4UL << 0) 1533c0c050c5SMichael Chan u8 auto_duplex; 1534c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF (0x0UL << 0) 1535c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL (0x1UL << 0) 1536c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH (0x2UL << 0) 1537c0c050c5SMichael Chan u8 auto_pause; 1538c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1539c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 154011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1541c0c050c5SMichael Chan u8 unused_0; 1542c0c050c5SMichael Chan __le16 auto_link_speed; 1543c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB (0x1UL << 0) 1544c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB (0xaUL << 0) 1545c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB (0x14UL << 0) 1546c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB (0x19UL << 0) 1547c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB (0x64UL << 0) 1548c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB (0xc8UL << 0) 1549c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB (0xfaUL << 0) 1550c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB (0x190UL << 0) 1551c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB (0x1f4UL << 0) 155211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB (0x3e8UL << 0) 155311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB (0xffffUL << 0) 1554c0c050c5SMichael Chan __le16 auto_link_speed_mask; 1555c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1556c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1557c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1558c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1559c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1560c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1561c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1562c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1563c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1564c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1565c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 156611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 156711f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 156811f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1569c0c050c5SMichael Chan u8 wirespeed; 1570c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_OFF (0x0UL << 0) 1571c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_ON (0x1UL << 0) 1572c0c050c5SMichael Chan u8 lpbk; 1573c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_NONE (0x0UL << 0) 1574c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LOCAL (0x1UL << 0) 1575c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_REMOTE (0x2UL << 0) 1576c0c050c5SMichael Chan u8 force_pause; 1577c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1578c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1579c0c050c5SMichael Chan u8 unused_1; 1580c0c050c5SMichael Chan __le32 preemphasis; 158111f15ed3SMichael Chan __le16 eee_link_speed_mask; 158211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 158311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 158411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 158511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 158611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 158711f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 158811f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 158911f15ed3SMichael Chan u8 unused_2; 159011f15ed3SMichael Chan u8 unused_3; 159111f15ed3SMichael Chan __le32 tx_lpi_timer; 159211f15ed3SMichael Chan __le32 unused_4; 159311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 159411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1595c0c050c5SMichael Chan }; 1596c0c050c5SMichael Chan 1597c0c050c5SMichael Chan /* Output (16 bytes) */ 1598c0c050c5SMichael Chan struct hwrm_port_phy_cfg_output { 1599c0c050c5SMichael Chan __le16 error_code; 1600c0c050c5SMichael Chan __le16 req_type; 1601c0c050c5SMichael Chan __le16 seq_id; 1602c0c050c5SMichael Chan __le16 resp_len; 1603c0c050c5SMichael Chan __le32 unused_0; 1604c0c050c5SMichael Chan u8 unused_1; 1605c0c050c5SMichael Chan u8 unused_2; 1606c0c050c5SMichael Chan u8 unused_3; 1607c0c050c5SMichael Chan u8 valid; 1608c0c050c5SMichael Chan }; 1609c0c050c5SMichael Chan 1610c0c050c5SMichael Chan /* hwrm_port_phy_qcfg */ 1611c0c050c5SMichael Chan /* Input (24 bytes) */ 1612c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_input { 1613c0c050c5SMichael Chan __le16 req_type; 1614c0c050c5SMichael Chan __le16 cmpl_ring; 1615c0c050c5SMichael Chan __le16 seq_id; 1616c0c050c5SMichael Chan __le16 target_id; 1617c0c050c5SMichael Chan __le64 resp_addr; 1618c0c050c5SMichael Chan __le16 port_id; 1619c0c050c5SMichael Chan __le16 unused_0[3]; 1620c0c050c5SMichael Chan }; 1621c0c050c5SMichael Chan 162211f15ed3SMichael Chan /* Output (96 bytes) */ 1623c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_output { 1624c0c050c5SMichael Chan __le16 error_code; 1625c0c050c5SMichael Chan __le16 req_type; 1626c0c050c5SMichael Chan __le16 seq_id; 1627c0c050c5SMichael Chan __le16 resp_len; 1628c0c050c5SMichael Chan u8 link; 1629c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_NO_LINK (0x0UL << 0) 1630c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SIGNAL (0x1UL << 0) 1631c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LINK (0x2UL << 0) 1632c0c050c5SMichael Chan u8 unused_0; 1633c0c050c5SMichael Chan __le16 link_speed; 1634c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB (0x1UL << 0) 1635c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB (0xaUL << 0) 1636c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB (0x14UL << 0) 1637c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB (0x19UL << 0) 1638c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB (0x64UL << 0) 1639c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB (0xc8UL << 0) 1640c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB (0xfaUL << 0) 1641c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB (0x190UL << 0) 1642c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB (0x1f4UL << 0) 164311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB (0x3e8UL << 0) 164411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB (0xffffUL << 0) 1645c0c050c5SMichael Chan u8 duplex; 1646c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_HALF (0x0UL << 0) 1647c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_FULL (0x1UL << 0) 1648c0c050c5SMichael Chan u8 pause; 1649c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1650c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1651c0c050c5SMichael Chan __le16 support_speeds; 1652c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1653c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1654c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1655c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1656c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1657c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1658c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1659c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1660c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1661c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1662c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 166311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 166411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 166511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1666c0c050c5SMichael Chan __le16 force_link_speed; 1667c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB (0x1UL << 0) 1668c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB (0xaUL << 0) 1669c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB (0x14UL << 0) 1670c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB (0x19UL << 0) 1671c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB (0x64UL << 0) 1672c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB (0xc8UL << 0) 1673c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB (0xfaUL << 0) 1674c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB (0x190UL << 0) 1675c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB (0x1f4UL << 0) 167611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB (0x3e8UL << 0) 167711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB (0xffffUL << 0) 1678c0c050c5SMichael Chan u8 auto_mode; 1679c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE (0x0UL << 0) 1680c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1681c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1682c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 168311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK (0x4UL << 0) 1684c0c050c5SMichael Chan u8 auto_pause; 1685c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1686c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 168711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1688c0c050c5SMichael Chan __le16 auto_link_speed; 1689c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB (0x1UL << 0) 1690c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB (0xaUL << 0) 1691c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB (0x14UL << 0) 1692c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB (0x19UL << 0) 1693c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB (0x64UL << 0) 1694c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB (0xc8UL << 0) 1695c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB (0xfaUL << 0) 1696c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB (0x190UL << 0) 1697c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB (0x1f4UL << 0) 169811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB (0x3e8UL << 0) 169911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB (0xffffUL << 0) 1700c0c050c5SMichael Chan __le16 auto_link_speed_mask; 1701c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1702c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1703c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1704c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1705c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1706c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1707c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1708c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1709c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1710c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1711c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 171211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 171311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 171411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1715c0c050c5SMichael Chan u8 wirespeed; 1716c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF (0x0UL << 0) 1717c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_ON (0x1UL << 0) 1718c0c050c5SMichael Chan u8 lpbk; 1719c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_NONE (0x0UL << 0) 1720c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LOCAL (0x1UL << 0) 1721c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_REMOTE (0x2UL << 0) 1722c0c050c5SMichael Chan u8 force_pause; 1723c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1724c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 172511f15ed3SMichael Chan u8 module_status; 172611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE (0x0UL << 0) 172711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX (0x1UL << 0) 172811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG (0x2UL << 0) 172911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN (0x3UL << 0) 173011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED (0x4UL << 0) 173111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE (0xffUL << 0) 1732c0c050c5SMichael Chan __le32 preemphasis; 1733c0c050c5SMichael Chan u8 phy_maj; 1734c0c050c5SMichael Chan u8 phy_min; 1735c0c050c5SMichael Chan u8 phy_bld; 1736c0c050c5SMichael Chan u8 phy_type; 173711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN (0x0UL << 0) 173811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR (0x1UL << 0) 1739c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 (0x2UL << 0) 174011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR (0x3UL << 0) 174111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR (0x4UL << 0) 1742c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 (0x5UL << 0) 174311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX (0x6UL << 0) 1744c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR (0x7UL << 0) 1745c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET (0x8UL << 0) 174611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE (0x9UL << 0) 174711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY (0xaUL << 0) 1748c0c050c5SMichael Chan u8 media_type; 174911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN (0x0UL << 0) 1750c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP (0x1UL << 0) 1751c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC (0x2UL << 0) 1752c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE (0x3UL << 0) 175311f15ed3SMichael Chan u8 xcvr_pkg_type; 175411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL (0x1UL << 0) 175511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL (0x2UL << 0) 175611f15ed3SMichael Chan u8 eee_config_phy_addr; 1757c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1758c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 175911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 176011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 176111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 176211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 176311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 176411f15ed3SMichael Chan u8 parallel_detect; 176511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 176611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_RESERVED_MASK 0xfeUL 176711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_RESERVED_SFT 1 1768c0c050c5SMichael Chan __le16 link_partner_adv_speeds; 1769c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1770c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1771c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1772c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1773c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1774c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1775c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1776c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1777c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1778c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1779c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 178011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 178111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 178211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1783c0c050c5SMichael Chan u8 link_partner_adv_auto_mode; 1784c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE (0x0UL << 0) 1785c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS (0x1UL << 0) 1786c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED (0x2UL << 0) 1787c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW (0x3UL << 0) 178811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK (0x4UL << 0) 1789c0c050c5SMichael Chan u8 link_partner_adv_pause; 1790c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1791c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 179211f15ed3SMichael Chan __le16 adv_eee_link_speed_mask; 179311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 179411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 179511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 179611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 179711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 179811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 179911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 180011f15ed3SMichael Chan __le16 link_partner_adv_eee_link_speed_mask; 180111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 180211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 180311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 180411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 180511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 180611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 180711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 180811f15ed3SMichael Chan __le32 xcvr_identifier_type_tx_lpi_timer; 180911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 181011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 181111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 181211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 181311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 181411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 181511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 181611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 181711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 181811f15ed3SMichael Chan __le32 unused_1; 181911f15ed3SMichael Chan char phy_vendor_name[16]; 182011f15ed3SMichael Chan char phy_vendor_partnumber[16]; 182111f15ed3SMichael Chan __le32 unused_2; 1822c0c050c5SMichael Chan u8 unused_3; 1823c0c050c5SMichael Chan u8 unused_4; 1824c0c050c5SMichael Chan u8 unused_5; 1825c0c050c5SMichael Chan u8 valid; 1826c0c050c5SMichael Chan }; 1827c0c050c5SMichael Chan 1828c0c050c5SMichael Chan /* hwrm_port_mac_cfg */ 182911f15ed3SMichael Chan /* Input (40 bytes) */ 1830c0c050c5SMichael Chan struct hwrm_port_mac_cfg_input { 1831c0c050c5SMichael Chan __le16 req_type; 1832c0c050c5SMichael Chan __le16 cmpl_ring; 1833c0c050c5SMichael Chan __le16 seq_id; 1834c0c050c5SMichael Chan __le16 target_id; 1835c0c050c5SMichael Chan __le64 resp_addr; 1836c0c050c5SMichael Chan __le32 flags; 1837c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1838c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_COS_ASSIGNMENT_ENABLE 0x2UL 1839c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1840c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 184111f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 184211f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 184311f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 184411f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1845c0c050c5SMichael Chan __le32 enables; 1846c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1847c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1848c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_IVLAN_PRI2COS_MAP_PRI 0x4UL 1849c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_LCOS_MAP_PRI 0x8UL 1850c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1851c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 185211f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 185311f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1854c0c050c5SMichael Chan __le16 port_id; 1855c0c050c5SMichael Chan u8 ipg; 1856c0c050c5SMichael Chan u8 lpbk; 1857c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_LPBK_NONE (0x0UL << 0) 1858c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LOCAL (0x1UL << 0) 1859c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_LPBK_REMOTE (0x2UL << 0) 1860c0c050c5SMichael Chan u8 ivlan_pri2cos_map_pri; 1861c0c050c5SMichael Chan u8 lcos_map_pri; 1862c0c050c5SMichael Chan u8 tunnel_pri2cos_map_pri; 1863c0c050c5SMichael Chan u8 dscp2pri_map_pri; 186411f15ed3SMichael Chan __le16 rx_ts_capture_ptp_msg_type; 186511f15ed3SMichael Chan __le16 tx_ts_capture_ptp_msg_type; 186611f15ed3SMichael Chan __le32 unused_0; 1867c0c050c5SMichael Chan }; 1868c0c050c5SMichael Chan 1869c0c050c5SMichael Chan /* Output (16 bytes) */ 1870c0c050c5SMichael Chan struct hwrm_port_mac_cfg_output { 1871c0c050c5SMichael Chan __le16 error_code; 1872c0c050c5SMichael Chan __le16 req_type; 1873c0c050c5SMichael Chan __le16 seq_id; 1874c0c050c5SMichael Chan __le16 resp_len; 1875c0c050c5SMichael Chan __le16 mru; 1876c0c050c5SMichael Chan __le16 mtu; 1877c0c050c5SMichael Chan u8 ipg; 1878c0c050c5SMichael Chan u8 lpbk; 1879c0c050c5SMichael Chan #define PORT_MAC_CFG_RESP_LPBK_NONE (0x0UL << 0) 1880c0c050c5SMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LOCAL (0x1UL << 0) 1881c0c050c5SMichael Chan #define PORT_MAC_CFG_RESP_LPBK_REMOTE (0x2UL << 0) 1882c0c050c5SMichael Chan u8 unused_0; 1883c0c050c5SMichael Chan u8 valid; 1884c0c050c5SMichael Chan }; 1885c0c050c5SMichael Chan 1886c0c050c5SMichael Chan /* hwrm_port_qstats */ 1887c0c050c5SMichael Chan /* Input (40 bytes) */ 1888c0c050c5SMichael Chan struct hwrm_port_qstats_input { 1889c0c050c5SMichael Chan __le16 req_type; 1890c0c050c5SMichael Chan __le16 cmpl_ring; 1891c0c050c5SMichael Chan __le16 seq_id; 1892c0c050c5SMichael Chan __le16 target_id; 1893c0c050c5SMichael Chan __le64 resp_addr; 1894c0c050c5SMichael Chan __le16 port_id; 1895c0c050c5SMichael Chan u8 unused_0; 1896c0c050c5SMichael Chan u8 unused_1; 1897c0c050c5SMichael Chan u8 unused_2[3]; 1898c0c050c5SMichael Chan u8 unused_3; 1899c0c050c5SMichael Chan __le64 tx_stat_host_addr; 1900c0c050c5SMichael Chan __le64 rx_stat_host_addr; 1901c0c050c5SMichael Chan }; 1902c0c050c5SMichael Chan 1903c0c050c5SMichael Chan /* Output (16 bytes) */ 1904c0c050c5SMichael Chan struct hwrm_port_qstats_output { 1905c0c050c5SMichael Chan __le16 error_code; 1906c0c050c5SMichael Chan __le16 req_type; 1907c0c050c5SMichael Chan __le16 seq_id; 1908c0c050c5SMichael Chan __le16 resp_len; 1909c193554eSMichael Chan __le16 tx_stat_size; 1910c193554eSMichael Chan __le16 rx_stat_size; 1911c193554eSMichael Chan u8 unused_0; 1912c0c050c5SMichael Chan u8 unused_1; 1913c0c050c5SMichael Chan u8 unused_2; 1914c0c050c5SMichael Chan u8 valid; 1915c0c050c5SMichael Chan }; 1916c0c050c5SMichael Chan 1917c0c050c5SMichael Chan /* hwrm_port_lpbk_qstats */ 1918c0c050c5SMichael Chan /* Input (16 bytes) */ 1919c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_input { 1920c0c050c5SMichael Chan __le16 req_type; 1921c0c050c5SMichael Chan __le16 cmpl_ring; 1922c0c050c5SMichael Chan __le16 seq_id; 1923c0c050c5SMichael Chan __le16 target_id; 1924c0c050c5SMichael Chan __le64 resp_addr; 1925c0c050c5SMichael Chan }; 1926c0c050c5SMichael Chan 1927c193554eSMichael Chan /* Output (96 bytes) */ 1928c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_output { 1929c0c050c5SMichael Chan __le16 error_code; 1930c0c050c5SMichael Chan __le16 req_type; 1931c0c050c5SMichael Chan __le16 seq_id; 1932c0c050c5SMichael Chan __le16 resp_len; 1933c0c050c5SMichael Chan __le64 lpbk_ucast_frames; 1934c0c050c5SMichael Chan __le64 lpbk_mcast_frames; 1935c0c050c5SMichael Chan __le64 lpbk_bcast_frames; 1936c0c050c5SMichael Chan __le64 lpbk_ucast_bytes; 1937c0c050c5SMichael Chan __le64 lpbk_mcast_bytes; 1938c0c050c5SMichael Chan __le64 lpbk_bcast_bytes; 1939c193554eSMichael Chan __le64 tx_stat_discard; 1940c193554eSMichael Chan __le64 tx_stat_error; 1941c193554eSMichael Chan __le64 rx_stat_discard; 1942c193554eSMichael Chan __le64 rx_stat_error; 1943c0c050c5SMichael Chan __le32 unused_0; 1944c0c050c5SMichael Chan u8 unused_1; 1945c0c050c5SMichael Chan u8 unused_2; 1946c0c050c5SMichael Chan u8 unused_3; 1947c0c050c5SMichael Chan u8 valid; 1948c0c050c5SMichael Chan }; 1949c0c050c5SMichael Chan 1950c0c050c5SMichael Chan /* hwrm_port_clr_stats */ 1951c0c050c5SMichael Chan /* Input (24 bytes) */ 1952c0c050c5SMichael Chan struct hwrm_port_clr_stats_input { 1953c0c050c5SMichael Chan __le16 req_type; 1954c0c050c5SMichael Chan __le16 cmpl_ring; 1955c0c050c5SMichael Chan __le16 seq_id; 1956c0c050c5SMichael Chan __le16 target_id; 1957c0c050c5SMichael Chan __le64 resp_addr; 1958c0c050c5SMichael Chan __le16 port_id; 1959c0c050c5SMichael Chan __le16 unused_0[3]; 1960c0c050c5SMichael Chan }; 1961c0c050c5SMichael Chan 1962c0c050c5SMichael Chan /* Output (16 bytes) */ 1963c0c050c5SMichael Chan struct hwrm_port_clr_stats_output { 1964c0c050c5SMichael Chan __le16 error_code; 1965c0c050c5SMichael Chan __le16 req_type; 1966c0c050c5SMichael Chan __le16 seq_id; 1967c0c050c5SMichael Chan __le16 resp_len; 1968c0c050c5SMichael Chan __le32 unused_0; 1969c0c050c5SMichael Chan u8 unused_1; 1970c0c050c5SMichael Chan u8 unused_2; 1971c0c050c5SMichael Chan u8 unused_3; 1972c0c050c5SMichael Chan u8 valid; 1973c0c050c5SMichael Chan }; 1974c0c050c5SMichael Chan 1975c0c050c5SMichael Chan /* hwrm_port_lpbk_clr_stats */ 1976c0c050c5SMichael Chan /* Input (16 bytes) */ 1977c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_input { 1978c0c050c5SMichael Chan __le16 req_type; 1979c0c050c5SMichael Chan __le16 cmpl_ring; 1980c0c050c5SMichael Chan __le16 seq_id; 1981c0c050c5SMichael Chan __le16 target_id; 1982c0c050c5SMichael Chan __le64 resp_addr; 1983c0c050c5SMichael Chan }; 1984c0c050c5SMichael Chan 1985c0c050c5SMichael Chan /* Output (16 bytes) */ 1986c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_output { 1987c0c050c5SMichael Chan __le16 error_code; 1988c0c050c5SMichael Chan __le16 req_type; 1989c0c050c5SMichael Chan __le16 seq_id; 1990c0c050c5SMichael Chan __le16 resp_len; 1991c0c050c5SMichael Chan __le32 unused_0; 1992c0c050c5SMichael Chan u8 unused_1; 1993c0c050c5SMichael Chan u8 unused_2; 1994c0c050c5SMichael Chan u8 unused_3; 1995c0c050c5SMichael Chan u8 valid; 1996c0c050c5SMichael Chan }; 1997c0c050c5SMichael Chan 1998c0c050c5SMichael Chan /* hwrm_port_blink_led */ 1999c0c050c5SMichael Chan /* Input (24 bytes) */ 2000c0c050c5SMichael Chan struct hwrm_port_blink_led_input { 2001c0c050c5SMichael Chan __le16 req_type; 2002c0c050c5SMichael Chan __le16 cmpl_ring; 2003c0c050c5SMichael Chan __le16 seq_id; 2004c0c050c5SMichael Chan __le16 target_id; 2005c0c050c5SMichael Chan __le64 resp_addr; 2006c0c050c5SMichael Chan __le32 num_blinks; 2007c0c050c5SMichael Chan __le32 unused_0; 2008c0c050c5SMichael Chan }; 2009c0c050c5SMichael Chan 2010c0c050c5SMichael Chan /* Output (16 bytes) */ 2011c0c050c5SMichael Chan struct hwrm_port_blink_led_output { 2012c0c050c5SMichael Chan __le16 error_code; 2013c0c050c5SMichael Chan __le16 req_type; 2014c0c050c5SMichael Chan __le16 seq_id; 2015c0c050c5SMichael Chan __le16 resp_len; 2016c0c050c5SMichael Chan __le32 unused_0; 2017c0c050c5SMichael Chan u8 unused_1; 2018c0c050c5SMichael Chan u8 unused_2; 2019c0c050c5SMichael Chan u8 unused_3; 2020c0c050c5SMichael Chan u8 valid; 2021c0c050c5SMichael Chan }; 2022c0c050c5SMichael Chan 202311f15ed3SMichael Chan /* hwrm_port_phy_qcaps */ 202411f15ed3SMichael Chan /* Input (24 bytes) */ 202511f15ed3SMichael Chan struct hwrm_port_phy_qcaps_input { 202611f15ed3SMichael Chan __le16 req_type; 202711f15ed3SMichael Chan __le16 cmpl_ring; 202811f15ed3SMichael Chan __le16 seq_id; 202911f15ed3SMichael Chan __le16 target_id; 203011f15ed3SMichael Chan __le64 resp_addr; 203111f15ed3SMichael Chan __le16 port_id; 203211f15ed3SMichael Chan __le16 unused_0[3]; 203311f15ed3SMichael Chan }; 203411f15ed3SMichael Chan 203511f15ed3SMichael Chan /* Output (24 bytes) */ 203611f15ed3SMichael Chan struct hwrm_port_phy_qcaps_output { 203711f15ed3SMichael Chan __le16 error_code; 203811f15ed3SMichael Chan __le16 req_type; 203911f15ed3SMichael Chan __le16 seq_id; 204011f15ed3SMichael Chan __le16 resp_len; 204111f15ed3SMichael Chan u8 eee_supported; 204211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_EEE_SUPPORTED 0x1UL 204311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD1_MASK 0xfeUL 204411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD1_SFT 1 204511f15ed3SMichael Chan u8 unused_0; 204611f15ed3SMichael Chan __le16 supported_speeds_force_mode; 204711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 204811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 204911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 205011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 205111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 205211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 205311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 205411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 205511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 205611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 205711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 205811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 205911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 206011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 206111f15ed3SMichael Chan __le16 supported_speeds_auto_mode; 206211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 206311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 206411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 206511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 206611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 206711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 206811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 206911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 207011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 207111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 207211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 207311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 207411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 207511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 207611f15ed3SMichael Chan __le16 supported_speeds_eee_mode; 207711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 207811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 207911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 208011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 208111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 208211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 208311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 208411f15ed3SMichael Chan __le32 tx_lpi_timer_low; 208511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 208611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 208711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 208811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 208911f15ed3SMichael Chan __le32 valid_tx_lpi_timer_high; 209011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 209111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 209211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 209311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 209411f15ed3SMichael Chan }; 209511f15ed3SMichael Chan 209642ee18feSAjit Khaparde /* hwrm_port_phy_i2c_read */ 209742ee18feSAjit Khaparde /* Input (40 bytes) */ 209842ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_input { 209942ee18feSAjit Khaparde __le16 req_type; 210042ee18feSAjit Khaparde __le16 cmpl_ring; 210142ee18feSAjit Khaparde __le16 seq_id; 210242ee18feSAjit Khaparde __le16 target_id; 210342ee18feSAjit Khaparde __le64 resp_addr; 210442ee18feSAjit Khaparde __le32 flags; 210542ee18feSAjit Khaparde __le32 enables; 210642ee18feSAjit Khaparde #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 210742ee18feSAjit Khaparde __le16 port_id; 210842ee18feSAjit Khaparde u8 i2c_slave_addr; 210942ee18feSAjit Khaparde u8 unused_0; 211042ee18feSAjit Khaparde __le16 page_number; 211142ee18feSAjit Khaparde __le16 page_offset; 211242ee18feSAjit Khaparde u8 data_length; 211342ee18feSAjit Khaparde u8 unused_1[7]; 211442ee18feSAjit Khaparde }; 211542ee18feSAjit Khaparde 211642ee18feSAjit Khaparde /* Output (80 bytes) */ 211742ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_output { 211842ee18feSAjit Khaparde __le16 error_code; 211942ee18feSAjit Khaparde __le16 req_type; 212042ee18feSAjit Khaparde __le16 seq_id; 212142ee18feSAjit Khaparde __le16 resp_len; 212242ee18feSAjit Khaparde __le32 data[16]; 212342ee18feSAjit Khaparde __le32 unused_0; 212442ee18feSAjit Khaparde u8 unused_1; 212542ee18feSAjit Khaparde u8 unused_2; 212642ee18feSAjit Khaparde u8 unused_3; 212742ee18feSAjit Khaparde u8 valid; 212842ee18feSAjit Khaparde }; 212942ee18feSAjit Khaparde 2130c0c050c5SMichael Chan /* Input (24 bytes) */ 2131c0c050c5SMichael Chan struct hwrm_queue_qportcfg_input { 2132c0c050c5SMichael Chan __le16 req_type; 2133c0c050c5SMichael Chan __le16 cmpl_ring; 2134c0c050c5SMichael Chan __le16 seq_id; 2135c0c050c5SMichael Chan __le16 target_id; 2136c0c050c5SMichael Chan __le64 resp_addr; 2137c0c050c5SMichael Chan __le32 flags; 2138c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2139c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2140c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 214111f15ed3SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2142c0c050c5SMichael Chan __le16 port_id; 2143c0c050c5SMichael Chan __le16 unused_0; 2144c0c050c5SMichael Chan }; 2145c0c050c5SMichael Chan 2146c0c050c5SMichael Chan /* Output (32 bytes) */ 2147c0c050c5SMichael Chan struct hwrm_queue_qportcfg_output { 2148c0c050c5SMichael Chan __le16 error_code; 2149c0c050c5SMichael Chan __le16 req_type; 2150c0c050c5SMichael Chan __le16 seq_id; 2151c0c050c5SMichael Chan __le16 resp_len; 2152c0c050c5SMichael Chan u8 max_configurable_queues; 2153c0c050c5SMichael Chan u8 max_configurable_lossless_queues; 2154c0c050c5SMichael Chan u8 queue_cfg_allowed; 2155c0c050c5SMichael Chan u8 queue_buffers_cfg_allowed; 2156c0c050c5SMichael Chan u8 queue_pfcenable_cfg_allowed; 2157c0c050c5SMichael Chan u8 queue_pri2cos_cfg_allowed; 2158c0c050c5SMichael Chan u8 queue_cos2bw_cfg_allowed; 2159c0c050c5SMichael Chan u8 queue_id0; 2160c0c050c5SMichael Chan u8 queue_id0_service_profile; 2161c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2162c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2163c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2164c0c050c5SMichael Chan u8 queue_id1; 2165c0c050c5SMichael Chan u8 queue_id1_service_profile; 2166c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2167c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2168c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2169c0c050c5SMichael Chan u8 queue_id2; 2170c0c050c5SMichael Chan u8 queue_id2_service_profile; 2171c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2172c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2173c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2174c0c050c5SMichael Chan u8 queue_id3; 2175c0c050c5SMichael Chan u8 queue_id3_service_profile; 2176c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2177c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2178c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2179c0c050c5SMichael Chan u8 queue_id4; 2180c0c050c5SMichael Chan u8 queue_id4_service_profile; 2181c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2182c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2183c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2184c0c050c5SMichael Chan u8 queue_id5; 2185c0c050c5SMichael Chan u8 queue_id5_service_profile; 2186c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2187c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2188c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2189c0c050c5SMichael Chan u8 queue_id6; 2190c0c050c5SMichael Chan u8 queue_id6_service_profile; 2191c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2192c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2193c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2194c0c050c5SMichael Chan u8 queue_id7; 2195c0c050c5SMichael Chan u8 queue_id7_service_profile; 2196c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2197c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2198c0c050c5SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2199c0c050c5SMichael Chan u8 valid; 2200c0c050c5SMichael Chan }; 2201c0c050c5SMichael Chan 2202c0c050c5SMichael Chan /* hwrm_queue_cfg */ 2203c0c050c5SMichael Chan /* Input (40 bytes) */ 2204c0c050c5SMichael Chan struct hwrm_queue_cfg_input { 2205c0c050c5SMichael Chan __le16 req_type; 2206c0c050c5SMichael Chan __le16 cmpl_ring; 2207c0c050c5SMichael Chan __le16 seq_id; 2208c0c050c5SMichael Chan __le16 target_id; 2209c0c050c5SMichael Chan __le64 resp_addr; 2210c0c050c5SMichael Chan __le32 flags; 2211c0c050c5SMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH 0x1UL 2212c0c050c5SMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2213c0c050c5SMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 221411f15ed3SMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_RX 2215c0c050c5SMichael Chan __le32 enables; 2216c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2217c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2218c0c050c5SMichael Chan __le32 queue_id; 2219c0c050c5SMichael Chan __le32 dflt_len; 2220c0c050c5SMichael Chan u8 service_profile; 2221c0c050c5SMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY (0x0UL << 0) 2222c0c050c5SMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS (0x1UL << 0) 2223c0c050c5SMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN (0xffUL << 0) 2224c0c050c5SMichael Chan u8 unused_0[7]; 2225c0c050c5SMichael Chan }; 2226c0c050c5SMichael Chan 2227c0c050c5SMichael Chan /* Output (16 bytes) */ 2228c0c050c5SMichael Chan struct hwrm_queue_cfg_output { 2229c0c050c5SMichael Chan __le16 error_code; 2230c0c050c5SMichael Chan __le16 req_type; 2231c0c050c5SMichael Chan __le16 seq_id; 2232c0c050c5SMichael Chan __le16 resp_len; 2233c0c050c5SMichael Chan __le32 unused_0; 2234c0c050c5SMichael Chan u8 unused_1; 2235c0c050c5SMichael Chan u8 unused_2; 2236c0c050c5SMichael Chan u8 unused_3; 2237c0c050c5SMichael Chan u8 valid; 2238c0c050c5SMichael Chan }; 2239c0c050c5SMichael Chan 2240c0c050c5SMichael Chan /* hwrm_queue_buffers_cfg */ 2241c0c050c5SMichael Chan /* Input (56 bytes) */ 2242c0c050c5SMichael Chan struct hwrm_queue_buffers_cfg_input { 2243c0c050c5SMichael Chan __le16 req_type; 2244c0c050c5SMichael Chan __le16 cmpl_ring; 2245c0c050c5SMichael Chan __le16 seq_id; 2246c0c050c5SMichael Chan __le16 target_id; 2247c0c050c5SMichael Chan __le64 resp_addr; 2248c0c050c5SMichael Chan __le32 flags; 2249c0c050c5SMichael Chan #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH 0x1UL 2250c0c050c5SMichael Chan #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2251c0c050c5SMichael Chan #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 225211f15ed3SMichael Chan #define QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_LAST QUEUE_BUFFERS_CFG_REQ_FLAGS_PATH_RX 2253c0c050c5SMichael Chan __le32 enables; 2254c0c050c5SMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_RESERVED 0x1UL 2255c0c050c5SMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_SHARED 0x2UL 2256c193554eSMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XOFF 0x4UL 2257c193554eSMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_XON 0x8UL 2258c193554eSMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_FULL 0x10UL 2259c193554eSMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_NOTFULL 0x20UL 2260c193554eSMichael Chan #define QUEUE_BUFFERS_CFG_REQ_ENABLES_MAX 0x40UL 2261c0c050c5SMichael Chan __le32 queue_id; 2262c0c050c5SMichael Chan __le32 reserved; 2263c0c050c5SMichael Chan __le32 shared; 2264c0c050c5SMichael Chan __le32 xoff; 2265c0c050c5SMichael Chan __le32 xon; 2266c0c050c5SMichael Chan __le32 full; 2267c0c050c5SMichael Chan __le32 notfull; 2268c0c050c5SMichael Chan __le32 max; 2269c0c050c5SMichael Chan }; 2270c0c050c5SMichael Chan 2271c0c050c5SMichael Chan /* Output (16 bytes) */ 2272c0c050c5SMichael Chan struct hwrm_queue_buffers_cfg_output { 2273c0c050c5SMichael Chan __le16 error_code; 2274c0c050c5SMichael Chan __le16 req_type; 2275c0c050c5SMichael Chan __le16 seq_id; 2276c0c050c5SMichael Chan __le16 resp_len; 2277c0c050c5SMichael Chan __le32 unused_0; 2278c0c050c5SMichael Chan u8 unused_1; 2279c0c050c5SMichael Chan u8 unused_2; 2280c0c050c5SMichael Chan u8 unused_3; 2281c0c050c5SMichael Chan u8 valid; 2282c0c050c5SMichael Chan }; 2283c0c050c5SMichael Chan 2284c0c050c5SMichael Chan /* hwrm_queue_pfcenable_cfg */ 2285c0c050c5SMichael Chan /* Input (24 bytes) */ 2286c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_input { 2287c0c050c5SMichael Chan __le16 req_type; 2288c0c050c5SMichael Chan __le16 cmpl_ring; 2289c0c050c5SMichael Chan __le16 seq_id; 2290c0c050c5SMichael Chan __le16 target_id; 2291c0c050c5SMichael Chan __le64 resp_addr; 2292c193554eSMichael Chan __le32 flags; 2293c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2294c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2295c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2296c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2297c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2298c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2299c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2300c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2301c0c050c5SMichael Chan __le16 port_id; 2302c0c050c5SMichael Chan __le16 unused_0; 2303c0c050c5SMichael Chan }; 2304c0c050c5SMichael Chan 2305c0c050c5SMichael Chan /* Output (16 bytes) */ 2306c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_output { 2307c0c050c5SMichael Chan __le16 error_code; 2308c0c050c5SMichael Chan __le16 req_type; 2309c0c050c5SMichael Chan __le16 seq_id; 2310c0c050c5SMichael Chan __le16 resp_len; 2311c0c050c5SMichael Chan __le32 unused_0; 2312c0c050c5SMichael Chan u8 unused_1; 2313c0c050c5SMichael Chan u8 unused_2; 2314c0c050c5SMichael Chan u8 unused_3; 2315c0c050c5SMichael Chan u8 valid; 2316c0c050c5SMichael Chan }; 2317c0c050c5SMichael Chan 2318c0c050c5SMichael Chan /* hwrm_queue_pri2cos_cfg */ 2319c0c050c5SMichael Chan /* Input (40 bytes) */ 2320c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_input { 2321c0c050c5SMichael Chan __le16 req_type; 2322c0c050c5SMichael Chan __le16 cmpl_ring; 2323c0c050c5SMichael Chan __le16 seq_id; 2324c0c050c5SMichael Chan __le16 target_id; 2325c0c050c5SMichael Chan __le64 resp_addr; 2326c0c050c5SMichael Chan __le32 flags; 2327c0c050c5SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH 0x1UL 2328c0c050c5SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 2329c0c050c5SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 233011f15ed3SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 2331c0c050c5SMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x2UL 2332c0c050c5SMichael Chan __le32 enables; 2333c0c050c5SMichael Chan u8 port_id; 2334c193554eSMichael Chan u8 pri0_cos_queue_id; 2335c193554eSMichael Chan u8 pri1_cos_queue_id; 2336c193554eSMichael Chan u8 pri2_cos_queue_id; 2337c193554eSMichael Chan u8 pri3_cos_queue_id; 2338c193554eSMichael Chan u8 pri4_cos_queue_id; 2339c193554eSMichael Chan u8 pri5_cos_queue_id; 2340c193554eSMichael Chan u8 pri6_cos_queue_id; 2341c193554eSMichael Chan u8 pri7_cos_queue_id; 2342c0c050c5SMichael Chan u8 unused_0[7]; 2343c0c050c5SMichael Chan }; 2344c0c050c5SMichael Chan 2345c0c050c5SMichael Chan /* Output (16 bytes) */ 2346c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_output { 2347c0c050c5SMichael Chan __le16 error_code; 2348c0c050c5SMichael Chan __le16 req_type; 2349c0c050c5SMichael Chan __le16 seq_id; 2350c0c050c5SMichael Chan __le16 resp_len; 2351c0c050c5SMichael Chan __le32 unused_0; 2352c0c050c5SMichael Chan u8 unused_1; 2353c0c050c5SMichael Chan u8 unused_2; 2354c0c050c5SMichael Chan u8 unused_3; 2355c0c050c5SMichael Chan u8 valid; 2356c0c050c5SMichael Chan }; 2357c0c050c5SMichael Chan 2358c0c050c5SMichael Chan /* hwrm_queue_cos2bw_cfg */ 2359c0c050c5SMichael Chan /* Input (128 bytes) */ 2360c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_input { 2361c0c050c5SMichael Chan __le16 req_type; 2362c0c050c5SMichael Chan __le16 cmpl_ring; 2363c0c050c5SMichael Chan __le16 seq_id; 2364c0c050c5SMichael Chan __le16 target_id; 2365c0c050c5SMichael Chan __le64 resp_addr; 2366c0c050c5SMichael Chan __le32 flags; 2367c0c050c5SMichael Chan __le32 enables; 2368c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 2369c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 2370c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 2371c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 2372c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 2373c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 2374c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 2375c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 2376c0c050c5SMichael Chan __le16 port_id; 2377c0c050c5SMichael Chan u8 queue_id0; 2378c0c050c5SMichael Chan u8 unused_0; 2379c0c050c5SMichael Chan __le32 queue_id0_min_bw; 2380c0c050c5SMichael Chan __le32 queue_id0_max_bw; 2381c0c050c5SMichael Chan u8 queue_id0_tsa_assign; 2382c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP (0x0UL << 0) 2383c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS (0x1UL << 0) 2384c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2385c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2386c0c050c5SMichael Chan u8 queue_id0_pri_lvl; 2387c0c050c5SMichael Chan u8 queue_id0_bw_weight; 2388c0c050c5SMichael Chan u8 queue_id1; 2389c0c050c5SMichael Chan __le32 queue_id1_min_bw; 2390c0c050c5SMichael Chan __le32 queue_id1_max_bw; 2391c0c050c5SMichael Chan u8 queue_id1_tsa_assign; 2392c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP (0x0UL << 0) 2393c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS (0x1UL << 0) 2394c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2395c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2396c0c050c5SMichael Chan u8 queue_id1_pri_lvl; 2397c0c050c5SMichael Chan u8 queue_id1_bw_weight; 2398c0c050c5SMichael Chan u8 queue_id2; 2399c0c050c5SMichael Chan __le32 queue_id2_min_bw; 2400c0c050c5SMichael Chan __le32 queue_id2_max_bw; 2401c0c050c5SMichael Chan u8 queue_id2_tsa_assign; 2402c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP (0x0UL << 0) 2403c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS (0x1UL << 0) 2404c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2405c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2406c0c050c5SMichael Chan u8 queue_id2_pri_lvl; 2407c0c050c5SMichael Chan u8 queue_id2_bw_weight; 2408c0c050c5SMichael Chan u8 queue_id3; 2409c0c050c5SMichael Chan __le32 queue_id3_min_bw; 2410c0c050c5SMichael Chan __le32 queue_id3_max_bw; 2411c0c050c5SMichael Chan u8 queue_id3_tsa_assign; 2412c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP (0x0UL << 0) 2413c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS (0x1UL << 0) 2414c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2415c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2416c0c050c5SMichael Chan u8 queue_id3_pri_lvl; 2417c0c050c5SMichael Chan u8 queue_id3_bw_weight; 2418c0c050c5SMichael Chan u8 queue_id4; 2419c0c050c5SMichael Chan __le32 queue_id4_min_bw; 2420c0c050c5SMichael Chan __le32 queue_id4_max_bw; 2421c0c050c5SMichael Chan u8 queue_id4_tsa_assign; 2422c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP (0x0UL << 0) 2423c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS (0x1UL << 0) 2424c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2425c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2426c0c050c5SMichael Chan u8 queue_id4_pri_lvl; 2427c0c050c5SMichael Chan u8 queue_id4_bw_weight; 2428c0c050c5SMichael Chan u8 queue_id5; 2429c0c050c5SMichael Chan __le32 queue_id5_min_bw; 2430c0c050c5SMichael Chan __le32 queue_id5_max_bw; 2431c0c050c5SMichael Chan u8 queue_id5_tsa_assign; 2432c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP (0x0UL << 0) 2433c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS (0x1UL << 0) 2434c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2435c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2436c0c050c5SMichael Chan u8 queue_id5_pri_lvl; 2437c0c050c5SMichael Chan u8 queue_id5_bw_weight; 2438c0c050c5SMichael Chan u8 queue_id6; 2439c0c050c5SMichael Chan __le32 queue_id6_min_bw; 2440c0c050c5SMichael Chan __le32 queue_id6_max_bw; 2441c0c050c5SMichael Chan u8 queue_id6_tsa_assign; 2442c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP (0x0UL << 0) 2443c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS (0x1UL << 0) 2444c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2445c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2446c0c050c5SMichael Chan u8 queue_id6_pri_lvl; 2447c0c050c5SMichael Chan u8 queue_id6_bw_weight; 2448c0c050c5SMichael Chan u8 queue_id7; 2449c0c050c5SMichael Chan __le32 queue_id7_min_bw; 2450c0c050c5SMichael Chan __le32 queue_id7_max_bw; 2451c0c050c5SMichael Chan u8 queue_id7_tsa_assign; 2452c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP (0x0UL << 0) 2453c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS (0x1UL << 0) 2454c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST (0x2UL << 0) 2455c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST (0xffffUL << 0) 2456c0c050c5SMichael Chan u8 queue_id7_pri_lvl; 2457c0c050c5SMichael Chan u8 queue_id7_bw_weight; 2458c0c050c5SMichael Chan u8 unused_1[5]; 2459c0c050c5SMichael Chan }; 2460c0c050c5SMichael Chan 2461c0c050c5SMichael Chan /* Output (16 bytes) */ 2462c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_output { 2463c0c050c5SMichael Chan __le16 error_code; 2464c0c050c5SMichael Chan __le16 req_type; 2465c0c050c5SMichael Chan __le16 seq_id; 2466c0c050c5SMichael Chan __le16 resp_len; 2467c0c050c5SMichael Chan __le32 unused_0; 2468c0c050c5SMichael Chan u8 unused_1; 2469c0c050c5SMichael Chan u8 unused_2; 2470c0c050c5SMichael Chan u8 unused_3; 2471c0c050c5SMichael Chan u8 valid; 2472c0c050c5SMichael Chan }; 2473c0c050c5SMichael Chan 2474c0c050c5SMichael Chan /* hwrm_vnic_alloc */ 2475c0c050c5SMichael Chan /* Input (24 bytes) */ 2476c0c050c5SMichael Chan struct hwrm_vnic_alloc_input { 2477c0c050c5SMichael Chan __le16 req_type; 2478c0c050c5SMichael Chan __le16 cmpl_ring; 2479c0c050c5SMichael Chan __le16 seq_id; 2480c0c050c5SMichael Chan __le16 target_id; 2481c0c050c5SMichael Chan __le64 resp_addr; 2482c0c050c5SMichael Chan __le32 flags; 2483c0c050c5SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 2484c0c050c5SMichael Chan __le32 unused_0; 2485c0c050c5SMichael Chan }; 2486c0c050c5SMichael Chan 2487c0c050c5SMichael Chan /* Output (16 bytes) */ 2488c0c050c5SMichael Chan struct hwrm_vnic_alloc_output { 2489c0c050c5SMichael Chan __le16 error_code; 2490c0c050c5SMichael Chan __le16 req_type; 2491c0c050c5SMichael Chan __le16 seq_id; 2492c0c050c5SMichael Chan __le16 resp_len; 2493c0c050c5SMichael Chan __le32 vnic_id; 2494c0c050c5SMichael Chan u8 unused_0; 2495c0c050c5SMichael Chan u8 unused_1; 2496c0c050c5SMichael Chan u8 unused_2; 2497c0c050c5SMichael Chan u8 valid; 2498c0c050c5SMichael Chan }; 2499c0c050c5SMichael Chan 2500c0c050c5SMichael Chan /* hwrm_vnic_free */ 2501c0c050c5SMichael Chan /* Input (24 bytes) */ 2502c0c050c5SMichael Chan struct hwrm_vnic_free_input { 2503c0c050c5SMichael Chan __le16 req_type; 2504c0c050c5SMichael Chan __le16 cmpl_ring; 2505c0c050c5SMichael Chan __le16 seq_id; 2506c0c050c5SMichael Chan __le16 target_id; 2507c0c050c5SMichael Chan __le64 resp_addr; 2508c0c050c5SMichael Chan __le32 vnic_id; 2509c0c050c5SMichael Chan __le32 unused_0; 2510c0c050c5SMichael Chan }; 2511c0c050c5SMichael Chan 2512c0c050c5SMichael Chan /* Output (16 bytes) */ 2513c0c050c5SMichael Chan struct hwrm_vnic_free_output { 2514c0c050c5SMichael Chan __le16 error_code; 2515c0c050c5SMichael Chan __le16 req_type; 2516c0c050c5SMichael Chan __le16 seq_id; 2517c0c050c5SMichael Chan __le16 resp_len; 2518c0c050c5SMichael Chan __le32 unused_0; 2519c0c050c5SMichael Chan u8 unused_1; 2520c0c050c5SMichael Chan u8 unused_2; 2521c0c050c5SMichael Chan u8 unused_3; 2522c0c050c5SMichael Chan u8 valid; 2523c0c050c5SMichael Chan }; 2524c0c050c5SMichael Chan 2525c0c050c5SMichael Chan /* hwrm_vnic_cfg */ 2526c0c050c5SMichael Chan /* Input (40 bytes) */ 2527c0c050c5SMichael Chan struct hwrm_vnic_cfg_input { 2528c0c050c5SMichael Chan __le16 req_type; 2529c0c050c5SMichael Chan __le16 cmpl_ring; 2530c0c050c5SMichael Chan __le16 seq_id; 2531c0c050c5SMichael Chan __le16 target_id; 2532c0c050c5SMichael Chan __le64 resp_addr; 2533c0c050c5SMichael Chan __le32 flags; 2534c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 2535c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 2536c193554eSMichael Chan #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 253711f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 253811f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 2539c0c050c5SMichael Chan __le32 enables; 2540c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 2541c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 2542c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 2543c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 2544c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 2545c0c050c5SMichael Chan __le16 vnic_id; 2546c0c050c5SMichael Chan __le16 dflt_ring_grp; 2547c0c050c5SMichael Chan __le16 rss_rule; 2548c0c050c5SMichael Chan __le16 cos_rule; 2549c0c050c5SMichael Chan __le16 lb_rule; 2550c0c050c5SMichael Chan __le16 mru; 2551c0c050c5SMichael Chan __le32 unused_0; 2552c0c050c5SMichael Chan }; 2553c0c050c5SMichael Chan 2554c0c050c5SMichael Chan /* Output (16 bytes) */ 2555c0c050c5SMichael Chan struct hwrm_vnic_cfg_output { 2556c0c050c5SMichael Chan __le16 error_code; 2557c0c050c5SMichael Chan __le16 req_type; 2558c0c050c5SMichael Chan __le16 seq_id; 2559c0c050c5SMichael Chan __le16 resp_len; 2560c0c050c5SMichael Chan __le32 unused_0; 2561c0c050c5SMichael Chan u8 unused_1; 2562c0c050c5SMichael Chan u8 unused_2; 2563c0c050c5SMichael Chan u8 unused_3; 2564c0c050c5SMichael Chan u8 valid; 2565c0c050c5SMichael Chan }; 2566c0c050c5SMichael Chan 2567c0c050c5SMichael Chan /* hwrm_vnic_tpa_cfg */ 2568c0c050c5SMichael Chan /* Input (40 bytes) */ 2569c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_input { 2570c0c050c5SMichael Chan __le16 req_type; 2571c0c050c5SMichael Chan __le16 cmpl_ring; 2572c0c050c5SMichael Chan __le16 seq_id; 2573c0c050c5SMichael Chan __le16 target_id; 2574c0c050c5SMichael Chan __le64 resp_addr; 2575c0c050c5SMichael Chan __le32 flags; 2576c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 2577c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 2578c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 2579c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 2580c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 2581c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 2582c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 2583c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 2584c0c050c5SMichael Chan __le32 enables; 2585c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 2586c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 2587c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 2588c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 2589c0c050c5SMichael Chan __le16 vnic_id; 2590c0c050c5SMichael Chan __le16 max_agg_segs; 2591c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 (0x0UL << 0) 2592c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 (0x1UL << 0) 2593c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 (0x2UL << 0) 2594c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 (0x3UL << 0) 2595c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX (0x1fUL << 0) 2596c0c050c5SMichael Chan __le16 max_aggs; 2597c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 (0x0UL << 0) 2598c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 (0x1UL << 0) 2599c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 (0x2UL << 0) 2600c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 (0x3UL << 0) 2601c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 (0x4UL << 0) 2602c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX (0x7UL << 0) 2603c0c050c5SMichael Chan u8 unused_0; 2604c0c050c5SMichael Chan u8 unused_1; 2605c0c050c5SMichael Chan __le32 max_agg_timer; 2606c0c050c5SMichael Chan __le32 min_agg_len; 2607c0c050c5SMichael Chan }; 2608c0c050c5SMichael Chan 2609c0c050c5SMichael Chan /* Output (16 bytes) */ 2610c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_output { 2611c0c050c5SMichael Chan __le16 error_code; 2612c0c050c5SMichael Chan __le16 req_type; 2613c0c050c5SMichael Chan __le16 seq_id; 2614c0c050c5SMichael Chan __le16 resp_len; 2615c0c050c5SMichael Chan __le32 unused_0; 2616c0c050c5SMichael Chan u8 unused_1; 2617c0c050c5SMichael Chan u8 unused_2; 2618c0c050c5SMichael Chan u8 unused_3; 2619c0c050c5SMichael Chan u8 valid; 2620c0c050c5SMichael Chan }; 2621c0c050c5SMichael Chan 2622c0c050c5SMichael Chan /* hwrm_vnic_rss_cfg */ 2623c0c050c5SMichael Chan /* Input (48 bytes) */ 2624c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_input { 2625c0c050c5SMichael Chan __le16 req_type; 2626c0c050c5SMichael Chan __le16 cmpl_ring; 2627c0c050c5SMichael Chan __le16 seq_id; 2628c0c050c5SMichael Chan __le16 target_id; 2629c0c050c5SMichael Chan __le64 resp_addr; 2630c0c050c5SMichael Chan __le32 hash_type; 2631c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 2632c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 2633c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 2634c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 2635c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 2636c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 2637c0c050c5SMichael Chan __le32 unused_0; 2638c0c050c5SMichael Chan __le64 ring_grp_tbl_addr; 2639c0c050c5SMichael Chan __le64 hash_key_tbl_addr; 2640c0c050c5SMichael Chan __le16 rss_ctx_idx; 2641c0c050c5SMichael Chan __le16 unused_1[3]; 2642c0c050c5SMichael Chan }; 2643c0c050c5SMichael Chan 2644c0c050c5SMichael Chan /* Output (16 bytes) */ 2645c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_output { 2646c0c050c5SMichael Chan __le16 error_code; 2647c0c050c5SMichael Chan __le16 req_type; 2648c0c050c5SMichael Chan __le16 seq_id; 2649c0c050c5SMichael Chan __le16 resp_len; 2650c0c050c5SMichael Chan __le32 unused_0; 2651c0c050c5SMichael Chan u8 unused_1; 2652c0c050c5SMichael Chan u8 unused_2; 2653c0c050c5SMichael Chan u8 unused_3; 2654c0c050c5SMichael Chan u8 valid; 2655c0c050c5SMichael Chan }; 2656c0c050c5SMichael Chan 2657c0c050c5SMichael Chan /* hwrm_vnic_plcmodes_cfg */ 2658c0c050c5SMichael Chan /* Input (40 bytes) */ 2659c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_input { 2660c0c050c5SMichael Chan __le16 req_type; 2661c0c050c5SMichael Chan __le16 cmpl_ring; 2662c0c050c5SMichael Chan __le16 seq_id; 2663c0c050c5SMichael Chan __le16 target_id; 2664c0c050c5SMichael Chan __le64 resp_addr; 2665c0c050c5SMichael Chan __le32 flags; 2666c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 2667c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 2668c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 2669c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 2670c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 2671c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 2672c0c050c5SMichael Chan __le32 enables; 2673c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 2674c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 2675c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 2676c0c050c5SMichael Chan __le32 vnic_id; 2677c0c050c5SMichael Chan __le16 jumbo_thresh; 2678c0c050c5SMichael Chan __le16 hds_offset; 2679c0c050c5SMichael Chan __le16 hds_threshold; 2680c0c050c5SMichael Chan __le16 unused_0[3]; 2681c0c050c5SMichael Chan }; 2682c0c050c5SMichael Chan 2683c0c050c5SMichael Chan /* Output (16 bytes) */ 2684c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_output { 2685c0c050c5SMichael Chan __le16 error_code; 2686c0c050c5SMichael Chan __le16 req_type; 2687c0c050c5SMichael Chan __le16 seq_id; 2688c0c050c5SMichael Chan __le16 resp_len; 2689c0c050c5SMichael Chan __le32 unused_0; 2690c0c050c5SMichael Chan u8 unused_1; 2691c0c050c5SMichael Chan u8 unused_2; 2692c0c050c5SMichael Chan u8 unused_3; 2693c0c050c5SMichael Chan u8 valid; 2694c0c050c5SMichael Chan }; 2695c0c050c5SMichael Chan 2696c0c050c5SMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc */ 2697c0c050c5SMichael Chan /* Input (16 bytes) */ 2698c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 2699c0c050c5SMichael Chan __le16 req_type; 2700c0c050c5SMichael Chan __le16 cmpl_ring; 2701c0c050c5SMichael Chan __le16 seq_id; 2702c0c050c5SMichael Chan __le16 target_id; 2703c0c050c5SMichael Chan __le64 resp_addr; 2704c0c050c5SMichael Chan }; 2705c0c050c5SMichael Chan 2706c0c050c5SMichael Chan /* Output (16 bytes) */ 2707c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 2708c0c050c5SMichael Chan __le16 error_code; 2709c0c050c5SMichael Chan __le16 req_type; 2710c0c050c5SMichael Chan __le16 seq_id; 2711c0c050c5SMichael Chan __le16 resp_len; 2712c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 2713c0c050c5SMichael Chan u8 unused_0; 2714c0c050c5SMichael Chan u8 unused_1; 2715c0c050c5SMichael Chan u8 unused_2; 2716c0c050c5SMichael Chan u8 unused_3; 2717c0c050c5SMichael Chan u8 unused_4; 2718c0c050c5SMichael Chan u8 valid; 2719c0c050c5SMichael Chan }; 2720c0c050c5SMichael Chan 2721c0c050c5SMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free */ 2722c0c050c5SMichael Chan /* Input (24 bytes) */ 2723c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_input { 2724c0c050c5SMichael Chan __le16 req_type; 2725c0c050c5SMichael Chan __le16 cmpl_ring; 2726c0c050c5SMichael Chan __le16 seq_id; 2727c0c050c5SMichael Chan __le16 target_id; 2728c0c050c5SMichael Chan __le64 resp_addr; 2729c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 2730c0c050c5SMichael Chan __le16 unused_0[3]; 2731c0c050c5SMichael Chan }; 2732c0c050c5SMichael Chan 2733c0c050c5SMichael Chan /* Output (16 bytes) */ 2734c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_output { 2735c0c050c5SMichael Chan __le16 error_code; 2736c0c050c5SMichael Chan __le16 req_type; 2737c0c050c5SMichael Chan __le16 seq_id; 2738c0c050c5SMichael Chan __le16 resp_len; 2739c0c050c5SMichael Chan __le32 unused_0; 2740c0c050c5SMichael Chan u8 unused_1; 2741c0c050c5SMichael Chan u8 unused_2; 2742c0c050c5SMichael Chan u8 unused_3; 2743c0c050c5SMichael Chan u8 valid; 2744c0c050c5SMichael Chan }; 2745c0c050c5SMichael Chan 2746c0c050c5SMichael Chan /* hwrm_ring_alloc */ 2747c0c050c5SMichael Chan /* Input (80 bytes) */ 2748c0c050c5SMichael Chan struct hwrm_ring_alloc_input { 2749c0c050c5SMichael Chan __le16 req_type; 2750c0c050c5SMichael Chan __le16 cmpl_ring; 2751c0c050c5SMichael Chan __le16 seq_id; 2752c0c050c5SMichael Chan __le16 target_id; 2753c0c050c5SMichael Chan __le64 resp_addr; 2754c0c050c5SMichael Chan __le32 enables; 2755c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED1 0x1UL 2756c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED2 0x2UL 2757c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED3 0x4UL 2758c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 2759c193554eSMichael Chan #define RING_ALLOC_REQ_ENABLES_RESERVED4 0x10UL 2760c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 2761c0c050c5SMichael Chan u8 ring_type; 2762c0c050c5SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_CMPL (0x0UL << 0) 2763c0c050c5SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_TX (0x1UL << 0) 2764c0c050c5SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX (0x2UL << 0) 2765c0c050c5SMichael Chan u8 unused_0; 2766c0c050c5SMichael Chan __le16 unused_1; 2767c0c050c5SMichael Chan __le64 page_tbl_addr; 2768c0c050c5SMichael Chan __le32 fbo; 2769c0c050c5SMichael Chan u8 page_size; 2770c0c050c5SMichael Chan u8 page_tbl_depth; 2771c0c050c5SMichael Chan u8 unused_2; 2772c0c050c5SMichael Chan u8 unused_3; 2773c0c050c5SMichael Chan __le32 length; 2774c0c050c5SMichael Chan __le16 logical_id; 2775c0c050c5SMichael Chan __le16 cmpl_ring_id; 2776c0c050c5SMichael Chan __le16 queue_id; 2777c0c050c5SMichael Chan u8 unused_4; 2778c0c050c5SMichael Chan u8 unused_5; 2779c193554eSMichael Chan __le32 reserved1; 2780c193554eSMichael Chan __le16 reserved2; 2781c0c050c5SMichael Chan u8 unused_6; 2782c0c050c5SMichael Chan u8 unused_7; 2783c193554eSMichael Chan __le32 reserved3; 2784c0c050c5SMichael Chan __le32 stat_ctx_id; 2785c193554eSMichael Chan __le32 reserved4; 2786c0c050c5SMichael Chan __le32 max_bw; 2787c0c050c5SMichael Chan u8 int_mode; 2788c0c050c5SMichael Chan #define RING_ALLOC_REQ_INT_MODE_LEGACY (0x0UL << 0) 2789c193554eSMichael Chan #define RING_ALLOC_REQ_INT_MODE_RSVD (0x1UL << 0) 2790c0c050c5SMichael Chan #define RING_ALLOC_REQ_INT_MODE_MSIX (0x2UL << 0) 2791c0c050c5SMichael Chan #define RING_ALLOC_REQ_INT_MODE_POLL (0x3UL << 0) 2792c0c050c5SMichael Chan u8 unused_8[3]; 2793c0c050c5SMichael Chan }; 2794c0c050c5SMichael Chan 2795c0c050c5SMichael Chan /* Output (16 bytes) */ 2796c0c050c5SMichael Chan struct hwrm_ring_alloc_output { 2797c0c050c5SMichael Chan __le16 error_code; 2798c0c050c5SMichael Chan __le16 req_type; 2799c0c050c5SMichael Chan __le16 seq_id; 2800c0c050c5SMichael Chan __le16 resp_len; 2801c0c050c5SMichael Chan __le16 ring_id; 2802c0c050c5SMichael Chan __le16 logical_ring_id; 2803c0c050c5SMichael Chan u8 unused_0; 2804c0c050c5SMichael Chan u8 unused_1; 2805c0c050c5SMichael Chan u8 unused_2; 2806c0c050c5SMichael Chan u8 valid; 2807c0c050c5SMichael Chan }; 2808c0c050c5SMichael Chan 2809c0c050c5SMichael Chan /* hwrm_ring_free */ 2810c0c050c5SMichael Chan /* Input (24 bytes) */ 2811c0c050c5SMichael Chan struct hwrm_ring_free_input { 2812c0c050c5SMichael Chan __le16 req_type; 2813c0c050c5SMichael Chan __le16 cmpl_ring; 2814c0c050c5SMichael Chan __le16 seq_id; 2815c0c050c5SMichael Chan __le16 target_id; 2816c0c050c5SMichael Chan __le64 resp_addr; 2817c0c050c5SMichael Chan u8 ring_type; 2818c0c050c5SMichael Chan #define RING_FREE_REQ_RING_TYPE_CMPL (0x0UL << 0) 2819c0c050c5SMichael Chan #define RING_FREE_REQ_RING_TYPE_TX (0x1UL << 0) 2820c0c050c5SMichael Chan #define RING_FREE_REQ_RING_TYPE_RX (0x2UL << 0) 2821c0c050c5SMichael Chan u8 unused_0; 2822c0c050c5SMichael Chan __le16 ring_id; 2823c0c050c5SMichael Chan __le32 unused_1; 2824c0c050c5SMichael Chan }; 2825c0c050c5SMichael Chan 2826c0c050c5SMichael Chan /* Output (16 bytes) */ 2827c0c050c5SMichael Chan struct hwrm_ring_free_output { 2828c0c050c5SMichael Chan __le16 error_code; 2829c0c050c5SMichael Chan __le16 req_type; 2830c0c050c5SMichael Chan __le16 seq_id; 2831c0c050c5SMichael Chan __le16 resp_len; 2832c0c050c5SMichael Chan __le32 unused_0; 2833c0c050c5SMichael Chan u8 unused_1; 2834c0c050c5SMichael Chan u8 unused_2; 2835c0c050c5SMichael Chan u8 unused_3; 2836c0c050c5SMichael Chan u8 valid; 2837c0c050c5SMichael Chan }; 2838c0c050c5SMichael Chan 2839c0c050c5SMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params */ 2840c0c050c5SMichael Chan /* Input (24 bytes) */ 2841c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_input { 2842c0c050c5SMichael Chan __le16 req_type; 2843c0c050c5SMichael Chan __le16 cmpl_ring; 2844c0c050c5SMichael Chan __le16 seq_id; 2845c0c050c5SMichael Chan __le16 target_id; 2846c0c050c5SMichael Chan __le64 resp_addr; 2847c0c050c5SMichael Chan __le16 ring_id; 2848c0c050c5SMichael Chan __le16 unused_0[3]; 2849c0c050c5SMichael Chan }; 2850c0c050c5SMichael Chan 2851c0c050c5SMichael Chan /* Output (32 bytes) */ 2852c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_output { 2853c0c050c5SMichael Chan __le16 error_code; 2854c0c050c5SMichael Chan __le16 req_type; 2855c0c050c5SMichael Chan __le16 seq_id; 2856c0c050c5SMichael Chan __le16 resp_len; 2857c0c050c5SMichael Chan __le16 flags; 2858c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 2859c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 2860c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 2861c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 2862c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 2863c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 2864c0c050c5SMichael Chan __le16 int_lat_tmr_min; 2865c0c050c5SMichael Chan __le16 int_lat_tmr_max; 2866c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 2867c0c050c5SMichael Chan __le32 unused_0; 2868c0c050c5SMichael Chan u8 unused_1; 2869c0c050c5SMichael Chan u8 unused_2; 2870c0c050c5SMichael Chan u8 unused_3; 2871c0c050c5SMichael Chan u8 valid; 2872c0c050c5SMichael Chan }; 2873c0c050c5SMichael Chan 2874c0c050c5SMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params */ 2875c0c050c5SMichael Chan /* Input (40 bytes) */ 2876c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 2877c0c050c5SMichael Chan __le16 req_type; 2878c0c050c5SMichael Chan __le16 cmpl_ring; 2879c0c050c5SMichael Chan __le16 seq_id; 2880c0c050c5SMichael Chan __le16 target_id; 2881c0c050c5SMichael Chan __le64 resp_addr; 2882c0c050c5SMichael Chan __le16 ring_id; 2883c0c050c5SMichael Chan __le16 flags; 2884c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 2885c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 2886c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 2887c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 2888c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 2889c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 2890c0c050c5SMichael Chan __le16 int_lat_tmr_min; 2891c0c050c5SMichael Chan __le16 int_lat_tmr_max; 2892c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 2893c0c050c5SMichael Chan __le16 unused_0[3]; 2894c0c050c5SMichael Chan }; 2895c0c050c5SMichael Chan 2896c0c050c5SMichael Chan /* Output (16 bytes) */ 2897c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 2898c0c050c5SMichael Chan __le16 error_code; 2899c0c050c5SMichael Chan __le16 req_type; 2900c0c050c5SMichael Chan __le16 seq_id; 2901c0c050c5SMichael Chan __le16 resp_len; 2902c0c050c5SMichael Chan __le32 unused_0; 2903c0c050c5SMichael Chan u8 unused_1; 2904c0c050c5SMichael Chan u8 unused_2; 2905c0c050c5SMichael Chan u8 unused_3; 2906c0c050c5SMichael Chan u8 valid; 2907c0c050c5SMichael Chan }; 2908c0c050c5SMichael Chan 2909c0c050c5SMichael Chan /* hwrm_ring_reset */ 2910c0c050c5SMichael Chan /* Input (24 bytes) */ 2911c0c050c5SMichael Chan struct hwrm_ring_reset_input { 2912c0c050c5SMichael Chan __le16 req_type; 2913c0c050c5SMichael Chan __le16 cmpl_ring; 2914c0c050c5SMichael Chan __le16 seq_id; 2915c0c050c5SMichael Chan __le16 target_id; 2916c0c050c5SMichael Chan __le64 resp_addr; 2917c0c050c5SMichael Chan u8 ring_type; 2918c0c050c5SMichael Chan #define RING_RESET_REQ_RING_TYPE_CMPL (0x0UL << 0) 2919c0c050c5SMichael Chan #define RING_RESET_REQ_RING_TYPE_TX (0x1UL << 0) 2920c0c050c5SMichael Chan #define RING_RESET_REQ_RING_TYPE_RX (0x2UL << 0) 2921c0c050c5SMichael Chan u8 unused_0; 2922c0c050c5SMichael Chan __le16 ring_id; 2923c0c050c5SMichael Chan __le32 unused_1; 2924c0c050c5SMichael Chan }; 2925c0c050c5SMichael Chan 2926c0c050c5SMichael Chan /* Output (16 bytes) */ 2927c0c050c5SMichael Chan struct hwrm_ring_reset_output { 2928c0c050c5SMichael Chan __le16 error_code; 2929c0c050c5SMichael Chan __le16 req_type; 2930c0c050c5SMichael Chan __le16 seq_id; 2931c0c050c5SMichael Chan __le16 resp_len; 2932c0c050c5SMichael Chan __le32 unused_0; 2933c0c050c5SMichael Chan u8 unused_1; 2934c0c050c5SMichael Chan u8 unused_2; 2935c0c050c5SMichael Chan u8 unused_3; 2936c0c050c5SMichael Chan u8 valid; 2937c0c050c5SMichael Chan }; 2938c0c050c5SMichael Chan 2939c0c050c5SMichael Chan /* hwrm_ring_grp_alloc */ 2940c0c050c5SMichael Chan /* Input (24 bytes) */ 2941c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_input { 2942c0c050c5SMichael Chan __le16 req_type; 2943c0c050c5SMichael Chan __le16 cmpl_ring; 2944c0c050c5SMichael Chan __le16 seq_id; 2945c0c050c5SMichael Chan __le16 target_id; 2946c0c050c5SMichael Chan __le64 resp_addr; 2947c0c050c5SMichael Chan __le16 cr; 2948c0c050c5SMichael Chan __le16 rr; 2949c0c050c5SMichael Chan __le16 ar; 2950c0c050c5SMichael Chan __le16 sc; 2951c0c050c5SMichael Chan }; 2952c0c050c5SMichael Chan 2953c0c050c5SMichael Chan /* Output (16 bytes) */ 2954c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_output { 2955c0c050c5SMichael Chan __le16 error_code; 2956c0c050c5SMichael Chan __le16 req_type; 2957c0c050c5SMichael Chan __le16 seq_id; 2958c0c050c5SMichael Chan __le16 resp_len; 2959c0c050c5SMichael Chan __le32 ring_group_id; 2960c0c050c5SMichael Chan u8 unused_0; 2961c0c050c5SMichael Chan u8 unused_1; 2962c0c050c5SMichael Chan u8 unused_2; 2963c0c050c5SMichael Chan u8 valid; 2964c0c050c5SMichael Chan }; 2965c0c050c5SMichael Chan 2966c0c050c5SMichael Chan /* hwrm_ring_grp_free */ 2967c0c050c5SMichael Chan /* Input (24 bytes) */ 2968c0c050c5SMichael Chan struct hwrm_ring_grp_free_input { 2969c0c050c5SMichael Chan __le16 req_type; 2970c0c050c5SMichael Chan __le16 cmpl_ring; 2971c0c050c5SMichael Chan __le16 seq_id; 2972c0c050c5SMichael Chan __le16 target_id; 2973c0c050c5SMichael Chan __le64 resp_addr; 2974c0c050c5SMichael Chan __le32 ring_group_id; 2975c0c050c5SMichael Chan __le32 unused_0; 2976c0c050c5SMichael Chan }; 2977c0c050c5SMichael Chan 2978c0c050c5SMichael Chan /* Output (16 bytes) */ 2979c0c050c5SMichael Chan struct hwrm_ring_grp_free_output { 2980c0c050c5SMichael Chan __le16 error_code; 2981c0c050c5SMichael Chan __le16 req_type; 2982c0c050c5SMichael Chan __le16 seq_id; 2983c0c050c5SMichael Chan __le16 resp_len; 2984c0c050c5SMichael Chan __le32 unused_0; 2985c0c050c5SMichael Chan u8 unused_1; 2986c0c050c5SMichael Chan u8 unused_2; 2987c0c050c5SMichael Chan u8 unused_3; 2988c0c050c5SMichael Chan u8 valid; 2989c0c050c5SMichael Chan }; 2990c0c050c5SMichael Chan 2991c0c050c5SMichael Chan /* hwrm_cfa_l2_filter_alloc */ 2992c0c050c5SMichael Chan /* Input (96 bytes) */ 2993c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_input { 2994c0c050c5SMichael Chan __le16 req_type; 2995c0c050c5SMichael Chan __le16 cmpl_ring; 2996c0c050c5SMichael Chan __le16 seq_id; 2997c0c050c5SMichael Chan __le16 target_id; 2998c0c050c5SMichael Chan __le64 resp_addr; 2999c0c050c5SMichael Chan __le32 flags; 3000c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 3001c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX (0x0UL << 0) 3002c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX (0x1UL << 0) 300311f15ed3SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 3004c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 3005c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 3006c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 3007c0c050c5SMichael Chan __le32 enables; 3008c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 3009c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 3010c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 3011c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 3012c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 3013c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 3014c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 3015c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 3016c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 3017c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 3018c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 3019c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 3020c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 3021c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 3022c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 3023c193554eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 3024c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 3025c0c050c5SMichael Chan u8 l2_addr[6]; 3026c0c050c5SMichael Chan u8 unused_0; 3027c0c050c5SMichael Chan u8 unused_1; 3028c0c050c5SMichael Chan u8 l2_addr_mask[6]; 3029c0c050c5SMichael Chan __le16 l2_ovlan; 3030c0c050c5SMichael Chan __le16 l2_ovlan_mask; 3031c0c050c5SMichael Chan __le16 l2_ivlan; 3032c0c050c5SMichael Chan __le16 l2_ivlan_mask; 3033c0c050c5SMichael Chan u8 unused_2; 3034c0c050c5SMichael Chan u8 unused_3; 3035c0c050c5SMichael Chan u8 t_l2_addr[6]; 3036c0c050c5SMichael Chan u8 unused_4; 3037c0c050c5SMichael Chan u8 unused_5; 3038c0c050c5SMichael Chan u8 t_l2_addr_mask[6]; 3039c0c050c5SMichael Chan __le16 t_l2_ovlan; 3040c0c050c5SMichael Chan __le16 t_l2_ovlan_mask; 3041c0c050c5SMichael Chan __le16 t_l2_ivlan; 3042c0c050c5SMichael Chan __le16 t_l2_ivlan_mask; 3043c0c050c5SMichael Chan u8 src_type; 3044c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT (0x0UL << 0) 3045c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF (0x1UL << 0) 3046c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF (0x2UL << 0) 3047c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC (0x3UL << 0) 3048c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG (0x4UL << 0) 3049c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE (0x5UL << 0) 3050c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO (0x6UL << 0) 3051c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG (0x7UL << 0) 3052c0c050c5SMichael Chan u8 unused_6; 3053c0c050c5SMichael Chan __le32 src_id; 3054c0c050c5SMichael Chan u8 tunnel_type; 3055c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3056c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3057c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3058c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3059c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3060c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3061c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3062c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3063c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3064c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3065c0c050c5SMichael Chan u8 unused_7; 3066c193554eSMichael Chan __le16 dst_id; 3067c0c050c5SMichael Chan __le16 mirror_vnic_id; 3068c0c050c5SMichael Chan u8 pri_hint; 3069c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) 3070c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER (0x1UL << 0) 3071c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER (0x2UL << 0) 3072c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX (0x3UL << 0) 3073c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN (0x4UL << 0) 3074c0c050c5SMichael Chan u8 unused_8; 3075c0c050c5SMichael Chan __le32 unused_9; 3076c0c050c5SMichael Chan __le64 l2_filter_id_hint; 3077c0c050c5SMichael Chan }; 3078c0c050c5SMichael Chan 3079c0c050c5SMichael Chan /* Output (24 bytes) */ 3080c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_output { 3081c0c050c5SMichael Chan __le16 error_code; 3082c0c050c5SMichael Chan __le16 req_type; 3083c0c050c5SMichael Chan __le16 seq_id; 3084c0c050c5SMichael Chan __le16 resp_len; 3085c0c050c5SMichael Chan __le64 l2_filter_id; 3086c0c050c5SMichael Chan __le32 flow_id; 3087c0c050c5SMichael Chan u8 unused_0; 3088c0c050c5SMichael Chan u8 unused_1; 3089c0c050c5SMichael Chan u8 unused_2; 3090c0c050c5SMichael Chan u8 valid; 3091c0c050c5SMichael Chan }; 3092c0c050c5SMichael Chan 3093c0c050c5SMichael Chan /* hwrm_cfa_l2_filter_free */ 3094c0c050c5SMichael Chan /* Input (24 bytes) */ 3095c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_input { 3096c0c050c5SMichael Chan __le16 req_type; 3097c0c050c5SMichael Chan __le16 cmpl_ring; 3098c0c050c5SMichael Chan __le16 seq_id; 3099c0c050c5SMichael Chan __le16 target_id; 3100c0c050c5SMichael Chan __le64 resp_addr; 3101c0c050c5SMichael Chan __le64 l2_filter_id; 3102c0c050c5SMichael Chan }; 3103c0c050c5SMichael Chan 3104c0c050c5SMichael Chan /* Output (16 bytes) */ 3105c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_output { 3106c0c050c5SMichael Chan __le16 error_code; 3107c0c050c5SMichael Chan __le16 req_type; 3108c0c050c5SMichael Chan __le16 seq_id; 3109c0c050c5SMichael Chan __le16 resp_len; 3110c0c050c5SMichael Chan __le32 unused_0; 3111c0c050c5SMichael Chan u8 unused_1; 3112c0c050c5SMichael Chan u8 unused_2; 3113c0c050c5SMichael Chan u8 unused_3; 3114c0c050c5SMichael Chan u8 valid; 3115c0c050c5SMichael Chan }; 3116c0c050c5SMichael Chan 3117c0c050c5SMichael Chan /* hwrm_cfa_l2_filter_cfg */ 3118c0c050c5SMichael Chan /* Input (40 bytes) */ 3119c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_input { 3120c0c050c5SMichael Chan __le16 req_type; 3121c0c050c5SMichael Chan __le16 cmpl_ring; 3122c0c050c5SMichael Chan __le16 seq_id; 3123c0c050c5SMichael Chan __le16 target_id; 3124c0c050c5SMichael Chan __le64 resp_addr; 3125c0c050c5SMichael Chan __le32 flags; 3126c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 3127c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX (0x0UL << 0) 3128c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX (0x1UL << 0) 312911f15ed3SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 3130c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 3131c0c050c5SMichael Chan __le32 enables; 3132c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 3133c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3134c0c050c5SMichael Chan __le64 l2_filter_id; 3135c193554eSMichael Chan __le32 dst_id; 3136c193554eSMichael Chan __le32 new_mirror_vnic_id; 3137c0c050c5SMichael Chan }; 3138c0c050c5SMichael Chan 3139c0c050c5SMichael Chan /* Output (16 bytes) */ 3140c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_output { 3141c0c050c5SMichael Chan __le16 error_code; 3142c0c050c5SMichael Chan __le16 req_type; 3143c0c050c5SMichael Chan __le16 seq_id; 3144c0c050c5SMichael Chan __le16 resp_len; 3145c0c050c5SMichael Chan __le32 unused_0; 3146c0c050c5SMichael Chan u8 unused_1; 3147c0c050c5SMichael Chan u8 unused_2; 3148c0c050c5SMichael Chan u8 unused_3; 3149c0c050c5SMichael Chan u8 valid; 3150c0c050c5SMichael Chan }; 3151c0c050c5SMichael Chan 3152c0c050c5SMichael Chan /* hwrm_cfa_l2_set_rx_mask */ 3153c0c050c5SMichael Chan /* Input (40 bytes) */ 3154c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_input { 3155c0c050c5SMichael Chan __le16 req_type; 3156c0c050c5SMichael Chan __le16 cmpl_ring; 3157c0c050c5SMichael Chan __le16 seq_id; 3158c0c050c5SMichael Chan __le16 target_id; 3159c0c050c5SMichael Chan __le64 resp_addr; 3160c193554eSMichael Chan __le32 vnic_id; 3161c0c050c5SMichael Chan __le32 mask; 3162c193554eSMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_RESERVED 0x1UL 3163c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 3164c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 3165c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 3166c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 3167c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 3168c0c050c5SMichael Chan __le64 mc_tbl_addr; 3169c0c050c5SMichael Chan __le32 num_mc_entries; 3170c0c050c5SMichael Chan __le32 unused_0; 3171c0c050c5SMichael Chan }; 3172c0c050c5SMichael Chan 3173c0c050c5SMichael Chan /* Output (16 bytes) */ 3174c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_output { 3175c0c050c5SMichael Chan __le16 error_code; 3176c0c050c5SMichael Chan __le16 req_type; 3177c0c050c5SMichael Chan __le16 seq_id; 3178c0c050c5SMichael Chan __le16 resp_len; 3179c0c050c5SMichael Chan __le32 unused_0; 3180c0c050c5SMichael Chan u8 unused_1; 3181c0c050c5SMichael Chan u8 unused_2; 3182c0c050c5SMichael Chan u8 unused_3; 3183c0c050c5SMichael Chan u8 valid; 3184c0c050c5SMichael Chan }; 3185c0c050c5SMichael Chan 3186c0c050c5SMichael Chan /* hwrm_cfa_tunnel_filter_alloc */ 3187c0c050c5SMichael Chan /* Input (88 bytes) */ 3188c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_input { 3189c0c050c5SMichael Chan __le16 req_type; 3190c0c050c5SMichael Chan __le16 cmpl_ring; 3191c0c050c5SMichael Chan __le16 seq_id; 3192c0c050c5SMichael Chan __le16 target_id; 3193c0c050c5SMichael Chan __le64 resp_addr; 3194c0c050c5SMichael Chan __le32 flags; 3195c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3196c0c050c5SMichael Chan __le32 enables; 3197c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3198c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 3199c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 3200c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 3201c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 3202c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 3203c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 3204c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 3205c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 3206c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 3207c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 3208c0c050c5SMichael Chan __le64 l2_filter_id; 3209c0c050c5SMichael Chan u8 l2_addr[6]; 3210c0c050c5SMichael Chan __le16 l2_ivlan; 3211c0c050c5SMichael Chan __le32 l3_addr[4]; 3212c0c050c5SMichael Chan __le32 t_l3_addr[4]; 3213c0c050c5SMichael Chan u8 l3_addr_type; 3214c0c050c5SMichael Chan u8 t_l3_addr_type; 3215c0c050c5SMichael Chan u8 tunnel_type; 3216c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3217c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3218c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3219c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3220c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3221c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3222c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3223c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3224c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3225c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3226c0c050c5SMichael Chan u8 unused_0; 3227c0c050c5SMichael Chan __le32 vni; 3228c0c050c5SMichael Chan __le32 dst_vnic_id; 3229c0c050c5SMichael Chan __le32 mirror_vnic_id; 3230c0c050c5SMichael Chan }; 3231c0c050c5SMichael Chan 3232c0c050c5SMichael Chan /* Output (24 bytes) */ 3233c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_output { 3234c0c050c5SMichael Chan __le16 error_code; 3235c0c050c5SMichael Chan __le16 req_type; 3236c0c050c5SMichael Chan __le16 seq_id; 3237c0c050c5SMichael Chan __le16 resp_len; 3238c0c050c5SMichael Chan __le64 tunnel_filter_id; 3239c0c050c5SMichael Chan __le32 flow_id; 3240c0c050c5SMichael Chan u8 unused_0; 3241c0c050c5SMichael Chan u8 unused_1; 3242c0c050c5SMichael Chan u8 unused_2; 3243c0c050c5SMichael Chan u8 valid; 3244c0c050c5SMichael Chan }; 3245c0c050c5SMichael Chan 3246c0c050c5SMichael Chan /* hwrm_cfa_tunnel_filter_free */ 3247c0c050c5SMichael Chan /* Input (24 bytes) */ 3248c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_input { 3249c0c050c5SMichael Chan __le16 req_type; 3250c0c050c5SMichael Chan __le16 cmpl_ring; 3251c0c050c5SMichael Chan __le16 seq_id; 3252c0c050c5SMichael Chan __le16 target_id; 3253c0c050c5SMichael Chan __le64 resp_addr; 3254c0c050c5SMichael Chan __le64 tunnel_filter_id; 3255c0c050c5SMichael Chan }; 3256c0c050c5SMichael Chan 3257c0c050c5SMichael Chan /* Output (16 bytes) */ 3258c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_output { 3259c0c050c5SMichael Chan __le16 error_code; 3260c0c050c5SMichael Chan __le16 req_type; 3261c0c050c5SMichael Chan __le16 seq_id; 3262c0c050c5SMichael Chan __le16 resp_len; 3263c0c050c5SMichael Chan __le32 unused_0; 3264c0c050c5SMichael Chan u8 unused_1; 3265c0c050c5SMichael Chan u8 unused_2; 3266c0c050c5SMichael Chan u8 unused_3; 3267c0c050c5SMichael Chan u8 valid; 3268c0c050c5SMichael Chan }; 3269c0c050c5SMichael Chan 3270c0c050c5SMichael Chan /* hwrm_cfa_encap_record_alloc */ 3271c0c050c5SMichael Chan /* Input (32 bytes) */ 3272c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_input { 3273c0c050c5SMichael Chan __le16 req_type; 3274c0c050c5SMichael Chan __le16 cmpl_ring; 3275c0c050c5SMichael Chan __le16 seq_id; 3276c0c050c5SMichael Chan __le16 target_id; 3277c0c050c5SMichael Chan __le64 resp_addr; 3278c0c050c5SMichael Chan __le32 flags; 3279c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3280c0c050c5SMichael Chan u8 encap_type; 3281c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN (0x1UL << 0) 3282c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE (0x2UL << 0) 3283c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE (0x3UL << 0) 3284c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP (0x4UL << 0) 3285c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE (0x5UL << 0) 3286c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS (0x6UL << 0) 3287c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN (0x7UL << 0) 3288c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE (0x8UL << 0) 3289c0c050c5SMichael Chan u8 unused_0; 3290c0c050c5SMichael Chan __le16 unused_1; 3291c0c050c5SMichael Chan __le32 encap_data[16]; 3292c0c050c5SMichael Chan }; 3293c0c050c5SMichael Chan 3294c193554eSMichael Chan /* Output (16 bytes) */ 3295c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_output { 3296c0c050c5SMichael Chan __le16 error_code; 3297c0c050c5SMichael Chan __le16 req_type; 3298c0c050c5SMichael Chan __le16 seq_id; 3299c0c050c5SMichael Chan __le16 resp_len; 3300c193554eSMichael Chan __le32 encap_record_id; 3301c193554eSMichael Chan u8 unused_0; 3302c0c050c5SMichael Chan u8 unused_1; 3303c0c050c5SMichael Chan u8 unused_2; 3304c0c050c5SMichael Chan u8 valid; 3305c0c050c5SMichael Chan }; 3306c0c050c5SMichael Chan 3307c0c050c5SMichael Chan /* hwrm_cfa_encap_record_free */ 3308c0c050c5SMichael Chan /* Input (24 bytes) */ 3309c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_input { 3310c0c050c5SMichael Chan __le16 req_type; 3311c0c050c5SMichael Chan __le16 cmpl_ring; 3312c0c050c5SMichael Chan __le16 seq_id; 3313c0c050c5SMichael Chan __le16 target_id; 3314c0c050c5SMichael Chan __le64 resp_addr; 3315c193554eSMichael Chan __le32 encap_record_id; 3316c193554eSMichael Chan __le32 unused_0; 3317c0c050c5SMichael Chan }; 3318c0c050c5SMichael Chan 3319c0c050c5SMichael Chan /* Output (16 bytes) */ 3320c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_output { 3321c0c050c5SMichael Chan __le16 error_code; 3322c0c050c5SMichael Chan __le16 req_type; 3323c0c050c5SMichael Chan __le16 seq_id; 3324c0c050c5SMichael Chan __le16 resp_len; 3325c0c050c5SMichael Chan __le32 unused_0; 3326c0c050c5SMichael Chan u8 unused_1; 3327c0c050c5SMichael Chan u8 unused_2; 3328c0c050c5SMichael Chan u8 unused_3; 3329c0c050c5SMichael Chan u8 valid; 3330c0c050c5SMichael Chan }; 3331c0c050c5SMichael Chan 3332c0c050c5SMichael Chan /* hwrm_cfa_ntuple_filter_alloc */ 3333c0c050c5SMichael Chan /* Input (128 bytes) */ 3334c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_input { 3335c0c050c5SMichael Chan __le16 req_type; 3336c0c050c5SMichael Chan __le16 cmpl_ring; 3337c0c050c5SMichael Chan __le16 seq_id; 3338c0c050c5SMichael Chan __le16 target_id; 3339c0c050c5SMichael Chan __le64 resp_addr; 3340c0c050c5SMichael Chan __le32 flags; 3341c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 3342c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 3343c0c050c5SMichael Chan __le32 enables; 3344c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 3345c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 3346c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 3347c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 3348c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 3349c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 3350c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 3351c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 3352c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 3353c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 3354c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 3355c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 3356c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 3357c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 3358c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 3359c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 3360c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 3361c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 3362c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 3363c0c050c5SMichael Chan __le64 l2_filter_id; 3364c0c050c5SMichael Chan u8 src_macaddr[6]; 3365c0c050c5SMichael Chan __be16 ethertype; 3366c193554eSMichael Chan u8 ip_addr_type; 3367c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN (0x0UL << 0) 3368c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 (0x4UL << 0) 3369c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 (0x6UL << 0) 3370c0c050c5SMichael Chan u8 ip_protocol; 3371c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN (0x0UL << 0) 3372c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP (0x6UL << 0) 3373c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP (0x11UL << 0) 3374c193554eSMichael Chan __le16 dst_id; 3375c0c050c5SMichael Chan __le16 mirror_vnic_id; 3376c0c050c5SMichael Chan u8 tunnel_type; 3377c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL (0x0UL << 0) 3378c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3379c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE (0x2UL << 0) 3380c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE (0x3UL << 0) 3381c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP (0x4UL << 0) 3382c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3383c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS (0x6UL << 0) 3384c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT (0x7UL << 0) 3385c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE (0x8UL << 0) 3386c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL (0xffUL << 0) 3387c0c050c5SMichael Chan u8 pri_hint; 3388c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER (0x0UL << 0) 3389c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE (0x1UL << 0) 3390c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW (0x2UL << 0) 3391c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST (0x3UL << 0) 3392c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST (0x4UL << 0) 3393c0c050c5SMichael Chan __be32 src_ipaddr[4]; 3394c0c050c5SMichael Chan __be32 src_ipaddr_mask[4]; 3395c0c050c5SMichael Chan __be32 dst_ipaddr[4]; 3396c0c050c5SMichael Chan __be32 dst_ipaddr_mask[4]; 3397c0c050c5SMichael Chan __be16 src_port; 3398c0c050c5SMichael Chan __be16 src_port_mask; 3399c0c050c5SMichael Chan __be16 dst_port; 3400c0c050c5SMichael Chan __be16 dst_port_mask; 3401c0c050c5SMichael Chan __le64 ntuple_filter_id_hint; 3402c0c050c5SMichael Chan }; 3403c0c050c5SMichael Chan 3404c0c050c5SMichael Chan /* Output (24 bytes) */ 3405c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_output { 3406c0c050c5SMichael Chan __le16 error_code; 3407c0c050c5SMichael Chan __le16 req_type; 3408c0c050c5SMichael Chan __le16 seq_id; 3409c0c050c5SMichael Chan __le16 resp_len; 3410c0c050c5SMichael Chan __le64 ntuple_filter_id; 3411c0c050c5SMichael Chan __le32 flow_id; 3412c0c050c5SMichael Chan u8 unused_0; 3413c0c050c5SMichael Chan u8 unused_1; 3414c0c050c5SMichael Chan u8 unused_2; 3415c0c050c5SMichael Chan u8 valid; 3416c0c050c5SMichael Chan }; 3417c0c050c5SMichael Chan 3418c0c050c5SMichael Chan /* hwrm_cfa_ntuple_filter_free */ 3419c0c050c5SMichael Chan /* Input (24 bytes) */ 3420c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_input { 3421c0c050c5SMichael Chan __le16 req_type; 3422c0c050c5SMichael Chan __le16 cmpl_ring; 3423c0c050c5SMichael Chan __le16 seq_id; 3424c0c050c5SMichael Chan __le16 target_id; 3425c0c050c5SMichael Chan __le64 resp_addr; 3426c0c050c5SMichael Chan __le64 ntuple_filter_id; 3427c0c050c5SMichael Chan }; 3428c0c050c5SMichael Chan 3429c0c050c5SMichael Chan /* Output (16 bytes) */ 3430c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_output { 3431c0c050c5SMichael Chan __le16 error_code; 3432c0c050c5SMichael Chan __le16 req_type; 3433c0c050c5SMichael Chan __le16 seq_id; 3434c0c050c5SMichael Chan __le16 resp_len; 3435c0c050c5SMichael Chan __le32 unused_0; 3436c0c050c5SMichael Chan u8 unused_1; 3437c0c050c5SMichael Chan u8 unused_2; 3438c0c050c5SMichael Chan u8 unused_3; 3439c0c050c5SMichael Chan u8 valid; 3440c0c050c5SMichael Chan }; 3441c0c050c5SMichael Chan 3442c0c050c5SMichael Chan /* hwrm_cfa_ntuple_filter_cfg */ 3443c0c050c5SMichael Chan /* Input (40 bytes) */ 3444c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_input { 3445c0c050c5SMichael Chan __le16 req_type; 3446c0c050c5SMichael Chan __le16 cmpl_ring; 3447c0c050c5SMichael Chan __le16 seq_id; 3448c0c050c5SMichael Chan __le16 target_id; 3449c0c050c5SMichael Chan __le64 resp_addr; 3450c0c050c5SMichael Chan __le32 enables; 3451c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 3452c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 3453c0c050c5SMichael Chan __le32 unused_0; 3454c0c050c5SMichael Chan __le64 ntuple_filter_id; 3455c193554eSMichael Chan __le32 new_dst_id; 3456c0c050c5SMichael Chan __le32 new_mirror_vnic_id; 3457c0c050c5SMichael Chan }; 3458c0c050c5SMichael Chan 3459c0c050c5SMichael Chan /* Output (16 bytes) */ 3460c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_output { 3461c0c050c5SMichael Chan __le16 error_code; 3462c0c050c5SMichael Chan __le16 req_type; 3463c0c050c5SMichael Chan __le16 seq_id; 3464c0c050c5SMichael Chan __le16 resp_len; 3465c0c050c5SMichael Chan __le32 unused_0; 3466c0c050c5SMichael Chan u8 unused_1; 3467c0c050c5SMichael Chan u8 unused_2; 3468c0c050c5SMichael Chan u8 unused_3; 3469c0c050c5SMichael Chan u8 valid; 3470c0c050c5SMichael Chan }; 3471c0c050c5SMichael Chan 3472c0c050c5SMichael Chan /* hwrm_tunnel_dst_port_query */ 3473c0c050c5SMichael Chan /* Input (24 bytes) */ 3474c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_input { 3475c0c050c5SMichael Chan __le16 req_type; 3476c0c050c5SMichael Chan __le16 cmpl_ring; 3477c0c050c5SMichael Chan __le16 seq_id; 3478c0c050c5SMichael Chan __le16 target_id; 3479c0c050c5SMichael Chan __le64 resp_addr; 3480c0c050c5SMichael Chan u8 tunnel_type; 3481c0c050c5SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3482c0c050c5SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3483c0c050c5SMichael Chan u8 unused_0[7]; 3484c0c050c5SMichael Chan }; 3485c0c050c5SMichael Chan 3486c0c050c5SMichael Chan /* Output (16 bytes) */ 3487c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_output { 3488c0c050c5SMichael Chan __le16 error_code; 3489c0c050c5SMichael Chan __le16 req_type; 3490c0c050c5SMichael Chan __le16 seq_id; 3491c0c050c5SMichael Chan __le16 resp_len; 3492c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 3493c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 3494c0c050c5SMichael Chan u8 unused_0; 3495c0c050c5SMichael Chan u8 unused_1; 3496c0c050c5SMichael Chan u8 unused_2; 3497c0c050c5SMichael Chan u8 valid; 3498c0c050c5SMichael Chan }; 3499c0c050c5SMichael Chan 3500c0c050c5SMichael Chan /* hwrm_tunnel_dst_port_alloc */ 3501c0c050c5SMichael Chan /* Input (24 bytes) */ 3502c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_input { 3503c0c050c5SMichael Chan __le16 req_type; 3504c0c050c5SMichael Chan __le16 cmpl_ring; 3505c0c050c5SMichael Chan __le16 seq_id; 3506c0c050c5SMichael Chan __le16 target_id; 3507c0c050c5SMichael Chan __le64 resp_addr; 3508c0c050c5SMichael Chan u8 tunnel_type; 3509c0c050c5SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3510c0c050c5SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3511c0c050c5SMichael Chan u8 unused_0; 3512c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 3513c0c050c5SMichael Chan __le32 unused_1; 3514c0c050c5SMichael Chan }; 3515c0c050c5SMichael Chan 3516c0c050c5SMichael Chan /* Output (16 bytes) */ 3517c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_output { 3518c0c050c5SMichael Chan __le16 error_code; 3519c0c050c5SMichael Chan __le16 req_type; 3520c0c050c5SMichael Chan __le16 seq_id; 3521c0c050c5SMichael Chan __le16 resp_len; 3522c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 3523c0c050c5SMichael Chan u8 unused_0; 3524c0c050c5SMichael Chan u8 unused_1; 3525c0c050c5SMichael Chan u8 unused_2; 3526c0c050c5SMichael Chan u8 unused_3; 3527c0c050c5SMichael Chan u8 unused_4; 3528c0c050c5SMichael Chan u8 valid; 3529c0c050c5SMichael Chan }; 3530c0c050c5SMichael Chan 3531c0c050c5SMichael Chan /* hwrm_tunnel_dst_port_free */ 3532c0c050c5SMichael Chan /* Input (24 bytes) */ 3533c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_input { 3534c0c050c5SMichael Chan __le16 req_type; 3535c0c050c5SMichael Chan __le16 cmpl_ring; 3536c0c050c5SMichael Chan __le16 seq_id; 3537c0c050c5SMichael Chan __le16 target_id; 3538c0c050c5SMichael Chan __le64 resp_addr; 3539c0c050c5SMichael Chan u8 tunnel_type; 3540c0c050c5SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN (0x1UL << 0) 3541c0c050c5SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE (0x5UL << 0) 3542c0c050c5SMichael Chan u8 unused_0; 3543c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 3544c0c050c5SMichael Chan __le32 unused_1; 3545c0c050c5SMichael Chan }; 3546c0c050c5SMichael Chan 3547c0c050c5SMichael Chan /* Output (16 bytes) */ 3548c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_output { 3549c0c050c5SMichael Chan __le16 error_code; 3550c0c050c5SMichael Chan __le16 req_type; 3551c0c050c5SMichael Chan __le16 seq_id; 3552c0c050c5SMichael Chan __le16 resp_len; 3553c0c050c5SMichael Chan __le32 unused_0; 3554c0c050c5SMichael Chan u8 unused_1; 3555c0c050c5SMichael Chan u8 unused_2; 3556c0c050c5SMichael Chan u8 unused_3; 3557c0c050c5SMichael Chan u8 valid; 3558c0c050c5SMichael Chan }; 3559c0c050c5SMichael Chan 3560c0c050c5SMichael Chan /* hwrm_stat_ctx_alloc */ 3561c0c050c5SMichael Chan /* Input (32 bytes) */ 3562c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_input { 3563c0c050c5SMichael Chan __le16 req_type; 3564c0c050c5SMichael Chan __le16 cmpl_ring; 3565c0c050c5SMichael Chan __le16 seq_id; 3566c0c050c5SMichael Chan __le16 target_id; 3567c0c050c5SMichael Chan __le64 resp_addr; 3568c0c050c5SMichael Chan __le64 stats_dma_addr; 3569c0c050c5SMichael Chan __le32 update_period_ms; 3570c0c050c5SMichael Chan __le32 unused_0; 3571c0c050c5SMichael Chan }; 3572c0c050c5SMichael Chan 3573c0c050c5SMichael Chan /* Output (16 bytes) */ 3574c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_output { 3575c0c050c5SMichael Chan __le16 error_code; 3576c0c050c5SMichael Chan __le16 req_type; 3577c0c050c5SMichael Chan __le16 seq_id; 3578c0c050c5SMichael Chan __le16 resp_len; 3579c0c050c5SMichael Chan __le32 stat_ctx_id; 3580c0c050c5SMichael Chan u8 unused_0; 3581c0c050c5SMichael Chan u8 unused_1; 3582c0c050c5SMichael Chan u8 unused_2; 3583c0c050c5SMichael Chan u8 valid; 3584c0c050c5SMichael Chan }; 3585c0c050c5SMichael Chan 3586c0c050c5SMichael Chan /* hwrm_stat_ctx_free */ 3587c0c050c5SMichael Chan /* Input (24 bytes) */ 3588c0c050c5SMichael Chan struct hwrm_stat_ctx_free_input { 3589c0c050c5SMichael Chan __le16 req_type; 3590c0c050c5SMichael Chan __le16 cmpl_ring; 3591c0c050c5SMichael Chan __le16 seq_id; 3592c0c050c5SMichael Chan __le16 target_id; 3593c0c050c5SMichael Chan __le64 resp_addr; 3594c0c050c5SMichael Chan __le32 stat_ctx_id; 3595c0c050c5SMichael Chan __le32 unused_0; 3596c0c050c5SMichael Chan }; 3597c0c050c5SMichael Chan 3598c0c050c5SMichael Chan /* Output (16 bytes) */ 3599c0c050c5SMichael Chan struct hwrm_stat_ctx_free_output { 3600c0c050c5SMichael Chan __le16 error_code; 3601c0c050c5SMichael Chan __le16 req_type; 3602c0c050c5SMichael Chan __le16 seq_id; 3603c0c050c5SMichael Chan __le16 resp_len; 3604c0c050c5SMichael Chan __le32 stat_ctx_id; 3605c0c050c5SMichael Chan u8 unused_0; 3606c0c050c5SMichael Chan u8 unused_1; 3607c0c050c5SMichael Chan u8 unused_2; 3608c0c050c5SMichael Chan u8 valid; 3609c0c050c5SMichael Chan }; 3610c0c050c5SMichael Chan 3611c0c050c5SMichael Chan /* hwrm_stat_ctx_query */ 3612c0c050c5SMichael Chan /* Input (24 bytes) */ 3613c0c050c5SMichael Chan struct hwrm_stat_ctx_query_input { 3614c0c050c5SMichael Chan __le16 req_type; 3615c0c050c5SMichael Chan __le16 cmpl_ring; 3616c0c050c5SMichael Chan __le16 seq_id; 3617c0c050c5SMichael Chan __le16 target_id; 3618c0c050c5SMichael Chan __le64 resp_addr; 3619c0c050c5SMichael Chan __le32 stat_ctx_id; 3620c0c050c5SMichael Chan __le32 unused_0; 3621c0c050c5SMichael Chan }; 3622c0c050c5SMichael Chan 3623c0c050c5SMichael Chan /* Output (176 bytes) */ 3624c0c050c5SMichael Chan struct hwrm_stat_ctx_query_output { 3625c0c050c5SMichael Chan __le16 error_code; 3626c0c050c5SMichael Chan __le16 req_type; 3627c0c050c5SMichael Chan __le16 seq_id; 3628c0c050c5SMichael Chan __le16 resp_len; 3629c0c050c5SMichael Chan __le64 tx_ucast_pkts; 3630c0c050c5SMichael Chan __le64 tx_mcast_pkts; 3631c0c050c5SMichael Chan __le64 tx_bcast_pkts; 3632c0c050c5SMichael Chan __le64 tx_err_pkts; 3633c0c050c5SMichael Chan __le64 tx_drop_pkts; 3634c0c050c5SMichael Chan __le64 tx_ucast_bytes; 3635c0c050c5SMichael Chan __le64 tx_mcast_bytes; 3636c0c050c5SMichael Chan __le64 tx_bcast_bytes; 3637c0c050c5SMichael Chan __le64 rx_ucast_pkts; 3638c0c050c5SMichael Chan __le64 rx_mcast_pkts; 3639c0c050c5SMichael Chan __le64 rx_bcast_pkts; 3640c0c050c5SMichael Chan __le64 rx_err_pkts; 3641c0c050c5SMichael Chan __le64 rx_drop_pkts; 3642c0c050c5SMichael Chan __le64 rx_ucast_bytes; 3643c0c050c5SMichael Chan __le64 rx_mcast_bytes; 3644c0c050c5SMichael Chan __le64 rx_bcast_bytes; 3645c0c050c5SMichael Chan __le64 rx_agg_pkts; 3646c0c050c5SMichael Chan __le64 rx_agg_bytes; 3647c0c050c5SMichael Chan __le64 rx_agg_events; 3648c0c050c5SMichael Chan __le64 rx_agg_aborts; 3649c0c050c5SMichael Chan __le32 unused_0; 3650c0c050c5SMichael Chan u8 unused_1; 3651c0c050c5SMichael Chan u8 unused_2; 3652c0c050c5SMichael Chan u8 unused_3; 3653c0c050c5SMichael Chan u8 valid; 3654c0c050c5SMichael Chan }; 3655c0c050c5SMichael Chan 3656c0c050c5SMichael Chan /* hwrm_stat_ctx_clr_stats */ 3657c0c050c5SMichael Chan /* Input (24 bytes) */ 3658c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_input { 3659c0c050c5SMichael Chan __le16 req_type; 3660c0c050c5SMichael Chan __le16 cmpl_ring; 3661c0c050c5SMichael Chan __le16 seq_id; 3662c0c050c5SMichael Chan __le16 target_id; 3663c0c050c5SMichael Chan __le64 resp_addr; 3664c0c050c5SMichael Chan __le32 stat_ctx_id; 3665c0c050c5SMichael Chan __le32 unused_0; 3666c0c050c5SMichael Chan }; 3667c0c050c5SMichael Chan 3668c0c050c5SMichael Chan /* Output (16 bytes) */ 3669c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_output { 3670c0c050c5SMichael Chan __le16 error_code; 3671c0c050c5SMichael Chan __le16 req_type; 3672c0c050c5SMichael Chan __le16 seq_id; 3673c0c050c5SMichael Chan __le16 resp_len; 3674c0c050c5SMichael Chan __le32 unused_0; 3675c0c050c5SMichael Chan u8 unused_1; 3676c0c050c5SMichael Chan u8 unused_2; 3677c0c050c5SMichael Chan u8 unused_3; 3678c0c050c5SMichael Chan u8 valid; 3679c0c050c5SMichael Chan }; 3680c0c050c5SMichael Chan 3681c193554eSMichael Chan /* hwrm_fw_reset */ 3682c193554eSMichael Chan /* Input (24 bytes) */ 3683c193554eSMichael Chan struct hwrm_fw_reset_input { 3684c0c050c5SMichael Chan __le16 req_type; 3685c0c050c5SMichael Chan __le16 cmpl_ring; 3686c0c050c5SMichael Chan __le16 seq_id; 3687c0c050c5SMichael Chan __le16 target_id; 3688c0c050c5SMichael Chan __le64 resp_addr; 3689c193554eSMichael Chan u8 embedded_proc_type; 3690c193554eSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0) 3691c193554eSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0) 3692c193554eSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0) 3693c193554eSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0) 3694c193554eSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0) 3695c193554eSMichael Chan u8 selfrst_status; 3696c193554eSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3697c193554eSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3698c193554eSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3699c193554eSMichael Chan __le16 unused_0[3]; 3700c0c050c5SMichael Chan }; 3701c0c050c5SMichael Chan 3702c0c050c5SMichael Chan /* Output (16 bytes) */ 3703c193554eSMichael Chan struct hwrm_fw_reset_output { 3704c0c050c5SMichael Chan __le16 error_code; 3705c0c050c5SMichael Chan __le16 req_type; 3706c0c050c5SMichael Chan __le16 seq_id; 3707c0c050c5SMichael Chan __le16 resp_len; 3708c193554eSMichael Chan u8 selfrst_status; 3709c193554eSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 3710c193554eSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 3711c193554eSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 3712c0c050c5SMichael Chan u8 unused_0; 3713c193554eSMichael Chan __le16 unused_1; 3714c0c050c5SMichael Chan u8 unused_2; 3715c0c050c5SMichael Chan u8 unused_3; 3716c0c050c5SMichael Chan u8 unused_4; 3717c0c050c5SMichael Chan u8 valid; 3718c0c050c5SMichael Chan }; 3719c0c050c5SMichael Chan 372011f15ed3SMichael Chan /* hwrm_fw_qstatus */ 372111f15ed3SMichael Chan /* Input (24 bytes) */ 372211f15ed3SMichael Chan struct hwrm_fw_qstatus_input { 372311f15ed3SMichael Chan __le16 req_type; 372411f15ed3SMichael Chan __le16 cmpl_ring; 372511f15ed3SMichael Chan __le16 seq_id; 372611f15ed3SMichael Chan __le16 target_id; 372711f15ed3SMichael Chan __le64 resp_addr; 372811f15ed3SMichael Chan u8 embedded_proc_type; 372911f15ed3SMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT (0x0UL << 0) 373011f15ed3SMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT (0x1UL << 0) 373111f15ed3SMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL (0x2UL << 0) 373211f15ed3SMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE (0x3UL << 0) 373311f15ed3SMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_RSVD (0x4UL << 0) 373411f15ed3SMichael Chan u8 unused_0[7]; 373511f15ed3SMichael Chan }; 373611f15ed3SMichael Chan 373711f15ed3SMichael Chan /* Output (16 bytes) */ 373811f15ed3SMichael Chan struct hwrm_fw_qstatus_output { 373911f15ed3SMichael Chan __le16 error_code; 374011f15ed3SMichael Chan __le16 req_type; 374111f15ed3SMichael Chan __le16 seq_id; 374211f15ed3SMichael Chan __le16 resp_len; 374311f15ed3SMichael Chan u8 selfrst_status; 374411f15ed3SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE (0x0UL << 0) 374511f15ed3SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP (0x1UL << 0) 374611f15ed3SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST (0x2UL << 0) 374711f15ed3SMichael Chan u8 unused_0; 374811f15ed3SMichael Chan __le16 unused_1; 374911f15ed3SMichael Chan u8 unused_2; 375011f15ed3SMichael Chan u8 unused_3; 375111f15ed3SMichael Chan u8 unused_4; 375211f15ed3SMichael Chan u8 valid; 375311f15ed3SMichael Chan }; 375411f15ed3SMichael Chan 3755c193554eSMichael Chan /* hwrm_exec_fwd_resp */ 3756c193554eSMichael Chan /* Input (128 bytes) */ 3757c193554eSMichael Chan struct hwrm_exec_fwd_resp_input { 3758c0c050c5SMichael Chan __le16 req_type; 3759c0c050c5SMichael Chan __le16 cmpl_ring; 3760c0c050c5SMichael Chan __le16 seq_id; 3761c0c050c5SMichael Chan __le16 target_id; 3762c0c050c5SMichael Chan __le64 resp_addr; 3763c193554eSMichael Chan __le32 encap_request[26]; 3764c193554eSMichael Chan __le16 encap_resp_target_id; 3765c0c050c5SMichael Chan __le16 unused_0[3]; 3766c0c050c5SMichael Chan }; 3767c0c050c5SMichael Chan 3768c0c050c5SMichael Chan /* Output (16 bytes) */ 3769c193554eSMichael Chan struct hwrm_exec_fwd_resp_output { 3770c0c050c5SMichael Chan __le16 error_code; 3771c0c050c5SMichael Chan __le16 req_type; 3772c0c050c5SMichael Chan __le16 seq_id; 3773c0c050c5SMichael Chan __le16 resp_len; 3774c0c050c5SMichael Chan __le32 unused_0; 3775c0c050c5SMichael Chan u8 unused_1; 3776c0c050c5SMichael Chan u8 unused_2; 3777c0c050c5SMichael Chan u8 unused_3; 3778c0c050c5SMichael Chan u8 valid; 3779c0c050c5SMichael Chan }; 3780c0c050c5SMichael Chan 3781c193554eSMichael Chan /* hwrm_reject_fwd_resp */ 3782c193554eSMichael Chan /* Input (128 bytes) */ 3783c193554eSMichael Chan struct hwrm_reject_fwd_resp_input { 3784c193554eSMichael Chan __le16 req_type; 3785c193554eSMichael Chan __le16 cmpl_ring; 3786c193554eSMichael Chan __le16 seq_id; 3787c193554eSMichael Chan __le16 target_id; 3788c193554eSMichael Chan __le64 resp_addr; 3789c193554eSMichael Chan __le32 encap_request[26]; 3790c193554eSMichael Chan __le16 encap_resp_target_id; 3791c193554eSMichael Chan __le16 unused_0[3]; 3792c193554eSMichael Chan }; 3793c193554eSMichael Chan 3794c193554eSMichael Chan /* Output (16 bytes) */ 3795c193554eSMichael Chan struct hwrm_reject_fwd_resp_output { 3796c193554eSMichael Chan __le16 error_code; 3797c193554eSMichael Chan __le16 req_type; 3798c193554eSMichael Chan __le16 seq_id; 3799c193554eSMichael Chan __le16 resp_len; 3800c193554eSMichael Chan __le32 unused_0; 3801c193554eSMichael Chan u8 unused_1; 3802c193554eSMichael Chan u8 unused_2; 3803c193554eSMichael Chan u8 unused_3; 3804c193554eSMichael Chan u8 valid; 3805c193554eSMichael Chan }; 3806c193554eSMichael Chan 3807c193554eSMichael Chan /* hwrm_fwd_resp */ 3808c193554eSMichael Chan /* Input (40 bytes) */ 3809c193554eSMichael Chan struct hwrm_fwd_resp_input { 3810c193554eSMichael Chan __le16 req_type; 3811c193554eSMichael Chan __le16 cmpl_ring; 3812c193554eSMichael Chan __le16 seq_id; 3813c193554eSMichael Chan __le16 target_id; 3814c193554eSMichael Chan __le64 resp_addr; 3815c193554eSMichael Chan __le16 encap_resp_target_id; 3816c193554eSMichael Chan __le16 encap_resp_cmpl_ring; 3817c193554eSMichael Chan __le16 encap_resp_len; 3818c193554eSMichael Chan u8 unused_0; 3819c193554eSMichael Chan u8 unused_1; 3820c193554eSMichael Chan __le64 encap_resp_addr; 3821c193554eSMichael Chan __le32 encap_resp[24]; 3822c193554eSMichael Chan }; 3823c193554eSMichael Chan 3824c193554eSMichael Chan /* Output (16 bytes) */ 3825c193554eSMichael Chan struct hwrm_fwd_resp_output { 3826c193554eSMichael Chan __le16 error_code; 3827c193554eSMichael Chan __le16 req_type; 3828c193554eSMichael Chan __le16 seq_id; 3829c193554eSMichael Chan __le16 resp_len; 3830c193554eSMichael Chan __le32 unused_0; 3831c193554eSMichael Chan u8 unused_1; 3832c193554eSMichael Chan u8 unused_2; 3833c193554eSMichael Chan u8 unused_3; 3834c193554eSMichael Chan u8 valid; 3835c193554eSMichael Chan }; 3836c193554eSMichael Chan 3837c193554eSMichael Chan /* hwrm_fwd_async_event_cmpl */ 3838c193554eSMichael Chan /* Input (32 bytes) */ 3839c193554eSMichael Chan struct hwrm_fwd_async_event_cmpl_input { 3840c193554eSMichael Chan __le16 req_type; 3841c193554eSMichael Chan __le16 cmpl_ring; 3842c193554eSMichael Chan __le16 seq_id; 3843c193554eSMichael Chan __le16 target_id; 3844c193554eSMichael Chan __le64 resp_addr; 3845c193554eSMichael Chan __le16 encap_async_event_target_id; 3846c193554eSMichael Chan u8 unused_0; 3847c193554eSMichael Chan u8 unused_1; 3848c193554eSMichael Chan u8 unused_2[3]; 3849c193554eSMichael Chan u8 unused_3; 3850c193554eSMichael Chan __le32 encap_async_event_cmpl[4]; 3851c193554eSMichael Chan }; 3852c193554eSMichael Chan 3853c193554eSMichael Chan /* Output (16 bytes) */ 3854c193554eSMichael Chan struct hwrm_fwd_async_event_cmpl_output { 3855c193554eSMichael Chan __le16 error_code; 3856c193554eSMichael Chan __le16 req_type; 3857c193554eSMichael Chan __le16 seq_id; 3858c193554eSMichael Chan __le16 resp_len; 3859c193554eSMichael Chan __le32 unused_0; 3860c193554eSMichael Chan u8 unused_1; 3861c193554eSMichael Chan u8 unused_2; 3862c193554eSMichael Chan u8 unused_3; 3863c193554eSMichael Chan u8 valid; 3864c193554eSMichael Chan }; 3865c193554eSMichael Chan 3866c193554eSMichael Chan /* hwrm_temp_monitor_query */ 3867c193554eSMichael Chan /* Input (16 bytes) */ 3868c193554eSMichael Chan struct hwrm_temp_monitor_query_input { 3869c193554eSMichael Chan __le16 req_type; 3870c193554eSMichael Chan __le16 cmpl_ring; 3871c193554eSMichael Chan __le16 seq_id; 3872c193554eSMichael Chan __le16 target_id; 3873c193554eSMichael Chan __le64 resp_addr; 3874c193554eSMichael Chan }; 3875c193554eSMichael Chan 3876c193554eSMichael Chan /* Output (16 bytes) */ 3877c193554eSMichael Chan struct hwrm_temp_monitor_query_output { 3878c193554eSMichael Chan __le16 error_code; 3879c193554eSMichael Chan __le16 req_type; 3880c193554eSMichael Chan __le16 seq_id; 3881c193554eSMichael Chan __le16 resp_len; 3882c193554eSMichael Chan u8 temp; 3883c193554eSMichael Chan u8 unused_0; 3884c193554eSMichael Chan __le16 unused_1; 3885c193554eSMichael Chan u8 unused_2; 3886c193554eSMichael Chan u8 unused_3; 3887c193554eSMichael Chan u8 unused_4; 3888c193554eSMichael Chan u8 valid; 3889c193554eSMichael Chan }; 3890c193554eSMichael Chan 3891c0c050c5SMichael Chan /* hwrm_nvm_raw_write_blk */ 3892c0c050c5SMichael Chan /* Input (32 bytes) */ 3893c0c050c5SMichael Chan struct hwrm_nvm_raw_write_blk_input { 3894c0c050c5SMichael Chan __le16 req_type; 3895c0c050c5SMichael Chan __le16 cmpl_ring; 3896c0c050c5SMichael Chan __le16 seq_id; 3897c0c050c5SMichael Chan __le16 target_id; 3898c0c050c5SMichael Chan __le64 resp_addr; 3899c0c050c5SMichael Chan __le64 host_src_addr; 3900c0c050c5SMichael Chan __le32 dest_addr; 3901c0c050c5SMichael Chan __le32 len; 3902c0c050c5SMichael Chan }; 3903c0c050c5SMichael Chan 3904c0c050c5SMichael Chan /* Output (16 bytes) */ 3905c0c050c5SMichael Chan struct hwrm_nvm_raw_write_blk_output { 3906c0c050c5SMichael Chan __le16 error_code; 3907c0c050c5SMichael Chan __le16 req_type; 3908c0c050c5SMichael Chan __le16 seq_id; 3909c0c050c5SMichael Chan __le16 resp_len; 3910c0c050c5SMichael Chan __le32 unused_0; 3911c0c050c5SMichael Chan u8 unused_1; 3912c0c050c5SMichael Chan u8 unused_2; 3913c0c050c5SMichael Chan u8 unused_3; 3914c0c050c5SMichael Chan u8 valid; 3915c0c050c5SMichael Chan }; 3916c0c050c5SMichael Chan 3917c0c050c5SMichael Chan /* hwrm_nvm_read */ 3918c0c050c5SMichael Chan /* Input (40 bytes) */ 3919c0c050c5SMichael Chan struct hwrm_nvm_read_input { 3920c0c050c5SMichael Chan __le16 req_type; 3921c0c050c5SMichael Chan __le16 cmpl_ring; 3922c0c050c5SMichael Chan __le16 seq_id; 3923c0c050c5SMichael Chan __le16 target_id; 3924c0c050c5SMichael Chan __le64 resp_addr; 3925c0c050c5SMichael Chan __le64 host_dest_addr; 3926c0c050c5SMichael Chan __le16 dir_idx; 3927c0c050c5SMichael Chan u8 unused_0; 3928c0c050c5SMichael Chan u8 unused_1; 3929c0c050c5SMichael Chan __le32 offset; 3930c0c050c5SMichael Chan __le32 len; 3931c0c050c5SMichael Chan __le32 unused_2; 3932c0c050c5SMichael Chan }; 3933c0c050c5SMichael Chan 3934c0c050c5SMichael Chan /* Output (16 bytes) */ 3935c0c050c5SMichael Chan struct hwrm_nvm_read_output { 3936c0c050c5SMichael Chan __le16 error_code; 3937c0c050c5SMichael Chan __le16 req_type; 3938c0c050c5SMichael Chan __le16 seq_id; 3939c0c050c5SMichael Chan __le16 resp_len; 3940c0c050c5SMichael Chan __le32 unused_0; 3941c0c050c5SMichael Chan u8 unused_1; 3942c0c050c5SMichael Chan u8 unused_2; 3943c0c050c5SMichael Chan u8 unused_3; 3944c0c050c5SMichael Chan u8 valid; 3945c0c050c5SMichael Chan }; 3946c0c050c5SMichael Chan 3947c0c050c5SMichael Chan /* hwrm_nvm_raw_dump */ 3948c0c050c5SMichael Chan /* Input (32 bytes) */ 3949c0c050c5SMichael Chan struct hwrm_nvm_raw_dump_input { 3950c0c050c5SMichael Chan __le16 req_type; 3951c0c050c5SMichael Chan __le16 cmpl_ring; 3952c0c050c5SMichael Chan __le16 seq_id; 3953c0c050c5SMichael Chan __le16 target_id; 3954c0c050c5SMichael Chan __le64 resp_addr; 3955c0c050c5SMichael Chan __le64 host_dest_addr; 3956c0c050c5SMichael Chan __le32 offset; 3957c0c050c5SMichael Chan __le32 len; 3958c0c050c5SMichael Chan }; 3959c0c050c5SMichael Chan 3960c0c050c5SMichael Chan /* Output (16 bytes) */ 3961c0c050c5SMichael Chan struct hwrm_nvm_raw_dump_output { 3962c0c050c5SMichael Chan __le16 error_code; 3963c0c050c5SMichael Chan __le16 req_type; 3964c0c050c5SMichael Chan __le16 seq_id; 3965c0c050c5SMichael Chan __le16 resp_len; 3966c0c050c5SMichael Chan __le32 unused_0; 3967c0c050c5SMichael Chan u8 unused_1; 3968c0c050c5SMichael Chan u8 unused_2; 3969c0c050c5SMichael Chan u8 unused_3; 3970c0c050c5SMichael Chan u8 valid; 3971c0c050c5SMichael Chan }; 3972c0c050c5SMichael Chan 3973c0c050c5SMichael Chan /* hwrm_nvm_get_dir_entries */ 3974c0c050c5SMichael Chan /* Input (24 bytes) */ 3975c0c050c5SMichael Chan struct hwrm_nvm_get_dir_entries_input { 3976c0c050c5SMichael Chan __le16 req_type; 3977c0c050c5SMichael Chan __le16 cmpl_ring; 3978c0c050c5SMichael Chan __le16 seq_id; 3979c0c050c5SMichael Chan __le16 target_id; 3980c0c050c5SMichael Chan __le64 resp_addr; 3981c0c050c5SMichael Chan __le64 host_dest_addr; 3982c0c050c5SMichael Chan }; 3983c0c050c5SMichael Chan 3984c0c050c5SMichael Chan /* Output (16 bytes) */ 3985c0c050c5SMichael Chan struct hwrm_nvm_get_dir_entries_output { 3986c0c050c5SMichael Chan __le16 error_code; 3987c0c050c5SMichael Chan __le16 req_type; 3988c0c050c5SMichael Chan __le16 seq_id; 3989c0c050c5SMichael Chan __le16 resp_len; 3990c0c050c5SMichael Chan __le32 unused_0; 3991c0c050c5SMichael Chan u8 unused_1; 3992c0c050c5SMichael Chan u8 unused_2; 3993c0c050c5SMichael Chan u8 unused_3; 3994c0c050c5SMichael Chan u8 valid; 3995c0c050c5SMichael Chan }; 3996c0c050c5SMichael Chan 3997c0c050c5SMichael Chan /* hwrm_nvm_get_dir_info */ 3998c0c050c5SMichael Chan /* Input (16 bytes) */ 3999c0c050c5SMichael Chan struct hwrm_nvm_get_dir_info_input { 4000c0c050c5SMichael Chan __le16 req_type; 4001c0c050c5SMichael Chan __le16 cmpl_ring; 4002c0c050c5SMichael Chan __le16 seq_id; 4003c0c050c5SMichael Chan __le16 target_id; 4004c0c050c5SMichael Chan __le64 resp_addr; 4005c0c050c5SMichael Chan }; 4006c0c050c5SMichael Chan 4007c0c050c5SMichael Chan /* Output (24 bytes) */ 4008c0c050c5SMichael Chan struct hwrm_nvm_get_dir_info_output { 4009c0c050c5SMichael Chan __le16 error_code; 4010c0c050c5SMichael Chan __le16 req_type; 4011c0c050c5SMichael Chan __le16 seq_id; 4012c0c050c5SMichael Chan __le16 resp_len; 4013c0c050c5SMichael Chan __le32 entries; 4014c0c050c5SMichael Chan __le32 entry_length; 4015c0c050c5SMichael Chan __le32 unused_0; 4016c0c050c5SMichael Chan u8 unused_1; 4017c0c050c5SMichael Chan u8 unused_2; 4018c0c050c5SMichael Chan u8 unused_3; 4019c0c050c5SMichael Chan u8 valid; 4020c0c050c5SMichael Chan }; 4021c0c050c5SMichael Chan 4022c0c050c5SMichael Chan /* hwrm_nvm_write */ 4023c193554eSMichael Chan /* Input (48 bytes) */ 4024c0c050c5SMichael Chan struct hwrm_nvm_write_input { 4025c0c050c5SMichael Chan __le16 req_type; 4026c0c050c5SMichael Chan __le16 cmpl_ring; 4027c0c050c5SMichael Chan __le16 seq_id; 4028c0c050c5SMichael Chan __le16 target_id; 4029c0c050c5SMichael Chan __le64 resp_addr; 4030c0c050c5SMichael Chan __le64 host_src_addr; 4031c0c050c5SMichael Chan __le16 dir_type; 4032c0c050c5SMichael Chan __le16 dir_ordinal; 4033c0c050c5SMichael Chan __le16 dir_ext; 4034c0c050c5SMichael Chan __le16 dir_attr; 4035c0c050c5SMichael Chan __le32 dir_data_length; 4036c0c050c5SMichael Chan __le16 option; 4037c0c050c5SMichael Chan __le16 flags; 4038c0c050c5SMichael Chan #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 4039c193554eSMichael Chan __le32 dir_item_length; 4040c193554eSMichael Chan __le32 unused_0; 4041c0c050c5SMichael Chan }; 4042c0c050c5SMichael Chan 4043c0c050c5SMichael Chan /* Output (16 bytes) */ 4044c0c050c5SMichael Chan struct hwrm_nvm_write_output { 4045c0c050c5SMichael Chan __le16 error_code; 4046c0c050c5SMichael Chan __le16 req_type; 4047c0c050c5SMichael Chan __le16 seq_id; 4048c0c050c5SMichael Chan __le16 resp_len; 4049c193554eSMichael Chan __le32 dir_item_length; 4050c193554eSMichael Chan __le16 dir_idx; 4051c193554eSMichael Chan u8 unused_0; 4052c0c050c5SMichael Chan u8 valid; 4053c0c050c5SMichael Chan }; 4054c0c050c5SMichael Chan 4055c0c050c5SMichael Chan /* hwrm_nvm_modify */ 4056c0c050c5SMichael Chan /* Input (40 bytes) */ 4057c0c050c5SMichael Chan struct hwrm_nvm_modify_input { 4058c0c050c5SMichael Chan __le16 req_type; 4059c0c050c5SMichael Chan __le16 cmpl_ring; 4060c0c050c5SMichael Chan __le16 seq_id; 4061c0c050c5SMichael Chan __le16 target_id; 4062c0c050c5SMichael Chan __le64 resp_addr; 4063c0c050c5SMichael Chan __le64 host_src_addr; 4064c0c050c5SMichael Chan __le16 dir_idx; 4065c0c050c5SMichael Chan u8 unused_0; 4066c0c050c5SMichael Chan u8 unused_1; 4067c0c050c5SMichael Chan __le32 offset; 4068c0c050c5SMichael Chan __le32 len; 4069c0c050c5SMichael Chan __le32 unused_2; 4070c0c050c5SMichael Chan }; 4071c0c050c5SMichael Chan 4072c0c050c5SMichael Chan /* Output (16 bytes) */ 4073c0c050c5SMichael Chan struct hwrm_nvm_modify_output { 4074c0c050c5SMichael Chan __le16 error_code; 4075c0c050c5SMichael Chan __le16 req_type; 4076c0c050c5SMichael Chan __le16 seq_id; 4077c0c050c5SMichael Chan __le16 resp_len; 4078c0c050c5SMichael Chan __le32 unused_0; 4079c0c050c5SMichael Chan u8 unused_1; 4080c0c050c5SMichael Chan u8 unused_2; 4081c0c050c5SMichael Chan u8 unused_3; 4082c0c050c5SMichael Chan u8 valid; 4083c0c050c5SMichael Chan }; 4084c0c050c5SMichael Chan 4085c0c050c5SMichael Chan /* hwrm_nvm_find_dir_entry */ 4086c0c050c5SMichael Chan /* Input (32 bytes) */ 4087c0c050c5SMichael Chan struct hwrm_nvm_find_dir_entry_input { 4088c0c050c5SMichael Chan __le16 req_type; 4089c0c050c5SMichael Chan __le16 cmpl_ring; 4090c0c050c5SMichael Chan __le16 seq_id; 4091c0c050c5SMichael Chan __le16 target_id; 4092c0c050c5SMichael Chan __le64 resp_addr; 4093c0c050c5SMichael Chan __le32 enables; 4094c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 4095c0c050c5SMichael Chan __le16 dir_idx; 4096c0c050c5SMichael Chan __le16 dir_type; 4097c0c050c5SMichael Chan __le16 dir_ordinal; 4098c0c050c5SMichael Chan __le16 dir_ext; 4099c0c050c5SMichael Chan u8 opt_ordinal; 4100c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 4101c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 4102c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ (0x0UL << 0) 4103c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE (0x1UL << 0) 4104c0c050c5SMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT (0x2UL << 0) 4105c0c050c5SMichael Chan u8 unused_1[3]; 4106c0c050c5SMichael Chan }; 4107c0c050c5SMichael Chan 4108c0c050c5SMichael Chan /* Output (32 bytes) */ 4109c0c050c5SMichael Chan struct hwrm_nvm_find_dir_entry_output { 4110c0c050c5SMichael Chan __le16 error_code; 4111c0c050c5SMichael Chan __le16 req_type; 4112c0c050c5SMichael Chan __le16 seq_id; 4113c0c050c5SMichael Chan __le16 resp_len; 4114c0c050c5SMichael Chan __le32 dir_item_length; 4115c0c050c5SMichael Chan __le32 dir_data_length; 4116c0c050c5SMichael Chan __le32 fw_ver; 4117c0c050c5SMichael Chan __le16 dir_ordinal; 4118c0c050c5SMichael Chan __le16 dir_idx; 4119c0c050c5SMichael Chan __le32 unused_0; 4120c0c050c5SMichael Chan u8 unused_1; 4121c0c050c5SMichael Chan u8 unused_2; 4122c0c050c5SMichael Chan u8 unused_3; 4123c0c050c5SMichael Chan u8 valid; 4124c0c050c5SMichael Chan }; 4125c0c050c5SMichael Chan 4126c0c050c5SMichael Chan /* hwrm_nvm_erase_dir_entry */ 4127c0c050c5SMichael Chan /* Input (24 bytes) */ 4128c0c050c5SMichael Chan struct hwrm_nvm_erase_dir_entry_input { 4129c0c050c5SMichael Chan __le16 req_type; 4130c0c050c5SMichael Chan __le16 cmpl_ring; 4131c0c050c5SMichael Chan __le16 seq_id; 4132c0c050c5SMichael Chan __le16 target_id; 4133c0c050c5SMichael Chan __le64 resp_addr; 4134c0c050c5SMichael Chan __le16 dir_idx; 4135c0c050c5SMichael Chan __le16 unused_0[3]; 4136c0c050c5SMichael Chan }; 4137c0c050c5SMichael Chan 4138c0c050c5SMichael Chan /* Output (16 bytes) */ 4139c0c050c5SMichael Chan struct hwrm_nvm_erase_dir_entry_output { 4140c0c050c5SMichael Chan __le16 error_code; 4141c0c050c5SMichael Chan __le16 req_type; 4142c0c050c5SMichael Chan __le16 seq_id; 4143c0c050c5SMichael Chan __le16 resp_len; 4144c0c050c5SMichael Chan __le32 unused_0; 4145c0c050c5SMichael Chan u8 unused_1; 4146c0c050c5SMichael Chan u8 unused_2; 4147c0c050c5SMichael Chan u8 unused_3; 4148c0c050c5SMichael Chan u8 valid; 4149c0c050c5SMichael Chan }; 4150c0c050c5SMichael Chan 4151c0c050c5SMichael Chan /* hwrm_nvm_get_dev_info */ 4152c0c050c5SMichael Chan /* Input (16 bytes) */ 4153c0c050c5SMichael Chan struct hwrm_nvm_get_dev_info_input { 4154c0c050c5SMichael Chan __le16 req_type; 4155c0c050c5SMichael Chan __le16 cmpl_ring; 4156c0c050c5SMichael Chan __le16 seq_id; 4157c0c050c5SMichael Chan __le16 target_id; 4158c0c050c5SMichael Chan __le64 resp_addr; 4159c0c050c5SMichael Chan }; 4160c0c050c5SMichael Chan 4161c0c050c5SMichael Chan /* Output (32 bytes) */ 4162c0c050c5SMichael Chan struct hwrm_nvm_get_dev_info_output { 4163c0c050c5SMichael Chan __le16 error_code; 4164c0c050c5SMichael Chan __le16 req_type; 4165c0c050c5SMichael Chan __le16 seq_id; 4166c0c050c5SMichael Chan __le16 resp_len; 4167c0c050c5SMichael Chan __le16 manufacturer_id; 4168c0c050c5SMichael Chan __le16 device_id; 4169c0c050c5SMichael Chan __le32 sector_size; 4170c0c050c5SMichael Chan __le32 nvram_size; 4171c0c050c5SMichael Chan __le32 reserved_size; 4172c0c050c5SMichael Chan __le32 available_size; 4173c0c050c5SMichael Chan u8 unused_0; 4174c0c050c5SMichael Chan u8 unused_1; 4175c0c050c5SMichael Chan u8 unused_2; 4176c0c050c5SMichael Chan u8 valid; 4177c0c050c5SMichael Chan }; 4178c0c050c5SMichael Chan 4179c0c050c5SMichael Chan /* hwrm_nvm_mod_dir_entry */ 4180c0c050c5SMichael Chan /* Input (32 bytes) */ 4181c0c050c5SMichael Chan struct hwrm_nvm_mod_dir_entry_input { 4182c0c050c5SMichael Chan __le16 req_type; 4183c0c050c5SMichael Chan __le16 cmpl_ring; 4184c0c050c5SMichael Chan __le16 seq_id; 4185c0c050c5SMichael Chan __le16 target_id; 4186c0c050c5SMichael Chan __le64 resp_addr; 4187c0c050c5SMichael Chan __le32 enables; 4188c0c050c5SMichael Chan #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 4189c0c050c5SMichael Chan __le16 dir_idx; 4190c0c050c5SMichael Chan __le16 dir_ordinal; 4191c0c050c5SMichael Chan __le16 dir_ext; 4192c0c050c5SMichael Chan __le16 dir_attr; 4193c0c050c5SMichael Chan __le32 checksum; 4194c0c050c5SMichael Chan }; 4195c0c050c5SMichael Chan 4196c0c050c5SMichael Chan /* Output (16 bytes) */ 4197c0c050c5SMichael Chan struct hwrm_nvm_mod_dir_entry_output { 4198c0c050c5SMichael Chan __le16 error_code; 4199c0c050c5SMichael Chan __le16 req_type; 4200c0c050c5SMichael Chan __le16 seq_id; 4201c0c050c5SMichael Chan __le16 resp_len; 4202c0c050c5SMichael Chan __le32 unused_0; 4203c0c050c5SMichael Chan u8 unused_1; 4204c0c050c5SMichael Chan u8 unused_2; 4205c0c050c5SMichael Chan u8 unused_3; 4206c0c050c5SMichael Chan u8 valid; 4207c0c050c5SMichael Chan }; 4208c0c050c5SMichael Chan 4209c0c050c5SMichael Chan /* hwrm_nvm_verify_update */ 4210c0c050c5SMichael Chan /* Input (24 bytes) */ 4211c0c050c5SMichael Chan struct hwrm_nvm_verify_update_input { 4212c0c050c5SMichael Chan __le16 req_type; 4213c0c050c5SMichael Chan __le16 cmpl_ring; 4214c0c050c5SMichael Chan __le16 seq_id; 4215c0c050c5SMichael Chan __le16 target_id; 4216c0c050c5SMichael Chan __le64 resp_addr; 4217c0c050c5SMichael Chan __le16 dir_type; 4218c0c050c5SMichael Chan __le16 dir_ordinal; 4219c0c050c5SMichael Chan __le16 dir_ext; 4220c0c050c5SMichael Chan __le16 unused_0; 4221c0c050c5SMichael Chan }; 4222c0c050c5SMichael Chan 4223c0c050c5SMichael Chan /* Output (16 bytes) */ 4224c0c050c5SMichael Chan struct hwrm_nvm_verify_update_output { 4225c0c050c5SMichael Chan __le16 error_code; 4226c0c050c5SMichael Chan __le16 req_type; 4227c0c050c5SMichael Chan __le16 seq_id; 4228c0c050c5SMichael Chan __le16 resp_len; 4229c0c050c5SMichael Chan __le32 unused_0; 4230c0c050c5SMichael Chan u8 unused_1; 4231c0c050c5SMichael Chan u8 unused_2; 4232c0c050c5SMichael Chan u8 unused_3; 4233c0c050c5SMichael Chan u8 valid; 4234c0c050c5SMichael Chan }; 4235c0c050c5SMichael Chan 4236c0c050c5SMichael Chan #endif 4237