1c0c050c5SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2c0c050c5SMichael Chan * 311f15ed3SMichael Chan * Copyright (c) 2014-2016 Broadcom Corporation 42792b5b9SMichael Chan * Copyright (c) 2014-2018 Broadcom Limited 516db6323SMichael Chan * Copyright (c) 2018-2021 Broadcom Inc. 6c0c050c5SMichael Chan * 7c0c050c5SMichael Chan * This program is free software; you can redistribute it and/or modify 8c0c050c5SMichael Chan * it under the terms of the GNU General Public License as published by 9c0c050c5SMichael Chan * the Free Software Foundation. 10894aa69aSMichael Chan * 11894aa69aSMichael Chan * DO NOT MODIFY!!! This file is automatically generated. 12c0c050c5SMichael Chan */ 13c0c050c5SMichael Chan 14894aa69aSMichael Chan #ifndef _BNXT_HSI_H_ 15894aa69aSMichael Chan #define _BNXT_HSI_H_ 16c0c050c5SMichael Chan 17894aa69aSMichael Chan /* hwrm_cmd_hdr (size:128b/16B) */ 18894aa69aSMichael Chan struct hwrm_cmd_hdr { 19894aa69aSMichael Chan __le16 req_type; 20894aa69aSMichael Chan __le16 cmpl_ring; 21894aa69aSMichael Chan __le16 seq_id; 22894aa69aSMichael Chan __le16 target_id; 23894aa69aSMichael Chan __le64 resp_addr; 24894aa69aSMichael Chan }; 2587c374deSMichael Chan 26894aa69aSMichael Chan /* hwrm_resp_hdr (size:64b/8B) */ 27894aa69aSMichael Chan struct hwrm_resp_hdr { 28894aa69aSMichael Chan __le16 error_code; 29894aa69aSMichael Chan __le16 req_type; 30894aa69aSMichael Chan __le16 seq_id; 31894aa69aSMichael Chan __le16 resp_len; 32894aa69aSMichael Chan }; 338eb992e8SMichael Chan 34894aa69aSMichael Chan #define CMD_DISCR_TLV_ENCAP 0x8000UL 35894aa69aSMichael Chan #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36894aa69aSMichael Chan 37894aa69aSMichael Chan 38894aa69aSMichael Chan #define TLV_TYPE_HWRM_REQUEST 0x1UL 39894aa69aSMichael Chan #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40894aa69aSMichael Chan #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 4131d357c0SMichael Chan #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 4231d357c0SMichael Chan #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 432792b5b9SMichael Chan #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 4772e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 482792b5b9SMichael Chan #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 5072e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 5172e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 5272e0c9f9SMichael Chan #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53894aa69aSMichael Chan 54894aa69aSMichael Chan 55894aa69aSMichael Chan /* tlv (size:64b/8B) */ 56894aa69aSMichael Chan struct tlv { 57894aa69aSMichael Chan __le16 cmd_discr; 58894aa69aSMichael Chan u8 reserved_8b; 59894aa69aSMichael Chan u8 flags; 60894aa69aSMichael Chan #define TLV_FLAGS_MORE 0x1UL 61894aa69aSMichael Chan #define TLV_FLAGS_MORE_LAST 0x0UL 62894aa69aSMichael Chan #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED 0x2UL 64894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67894aa69aSMichael Chan __le16 tlv_type; 68894aa69aSMichael Chan __le16 length; 69894aa69aSMichael Chan }; 70894aa69aSMichael Chan 71894aa69aSMichael Chan /* input (size:128b/16B) */ 72894aa69aSMichael Chan struct input { 73894aa69aSMichael Chan __le16 req_type; 74894aa69aSMichael Chan __le16 cmpl_ring; 75894aa69aSMichael Chan __le16 seq_id; 76894aa69aSMichael Chan __le16 target_id; 77894aa69aSMichael Chan __le64 resp_addr; 78894aa69aSMichael Chan }; 79894aa69aSMichael Chan 80894aa69aSMichael Chan /* output (size:64b/8B) */ 81894aa69aSMichael Chan struct output { 82894aa69aSMichael Chan __le16 error_code; 83894aa69aSMichael Chan __le16 req_type; 84894aa69aSMichael Chan __le16 seq_id; 85894aa69aSMichael Chan __le16 resp_len; 86894aa69aSMichael Chan }; 87894aa69aSMichael Chan 88894aa69aSMichael Chan /* hwrm_short_input (size:128b/16B) */ 89894aa69aSMichael Chan struct hwrm_short_input { 90894aa69aSMichael Chan __le16 req_type; 91894aa69aSMichael Chan __le16 signature; 92894aa69aSMichael Chan #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93894aa69aSMichael Chan #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 944a50ddc2SMichael Chan __le16 target_id; 954a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 964a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 974a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98894aa69aSMichael Chan __le16 size; 99894aa69aSMichael Chan __le64 req_addr; 100894aa69aSMichael Chan }; 101894aa69aSMichael Chan 102894aa69aSMichael Chan /* cmd_nums (size:64b/8B) */ 103894aa69aSMichael Chan struct cmd_nums { 104894aa69aSMichael Chan __le16 req_type; 105894aa69aSMichael Chan #define HWRM_VER_GET 0x0UL 10631f67c2eSMichael Chan #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 1073293ec23SMichael Chan #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 1086fc92c33SMichael Chan #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 109894aa69aSMichael Chan #define HWRM_FUNC_BUF_UNRGTR 0xeUL 110894aa69aSMichael Chan #define HWRM_FUNC_VF_CFG 0xfUL 111894aa69aSMichael Chan #define HWRM_RESERVED1 0x10UL 112894aa69aSMichael Chan #define HWRM_FUNC_RESET 0x11UL 113894aa69aSMichael Chan #define HWRM_FUNC_GETFID 0x12UL 114894aa69aSMichael Chan #define HWRM_FUNC_VF_ALLOC 0x13UL 115894aa69aSMichael Chan #define HWRM_FUNC_VF_FREE 0x14UL 116894aa69aSMichael Chan #define HWRM_FUNC_QCAPS 0x15UL 117894aa69aSMichael Chan #define HWRM_FUNC_QCFG 0x16UL 118894aa69aSMichael Chan #define HWRM_FUNC_CFG 0x17UL 119894aa69aSMichael Chan #define HWRM_FUNC_QSTATS 0x18UL 120894aa69aSMichael Chan #define HWRM_FUNC_CLR_STATS 0x19UL 121894aa69aSMichael Chan #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 122894aa69aSMichael Chan #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 123894aa69aSMichael Chan #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 124894aa69aSMichael Chan #define HWRM_FUNC_DRV_RGTR 0x1dUL 125894aa69aSMichael Chan #define HWRM_FUNC_DRV_QVER 0x1eUL 126894aa69aSMichael Chan #define HWRM_FUNC_BUF_RGTR 0x1fUL 127894aa69aSMichael Chan #define HWRM_PORT_PHY_CFG 0x20UL 128894aa69aSMichael Chan #define HWRM_PORT_MAC_CFG 0x21UL 129894aa69aSMichael Chan #define HWRM_PORT_TS_QUERY 0x22UL 130894aa69aSMichael Chan #define HWRM_PORT_QSTATS 0x23UL 131894aa69aSMichael Chan #define HWRM_PORT_LPBK_QSTATS 0x24UL 132894aa69aSMichael Chan #define HWRM_PORT_CLR_STATS 0x25UL 133894aa69aSMichael Chan #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 134894aa69aSMichael Chan #define HWRM_PORT_PHY_QCFG 0x27UL 135894aa69aSMichael Chan #define HWRM_PORT_MAC_QCFG 0x28UL 136894aa69aSMichael Chan #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 137894aa69aSMichael Chan #define HWRM_PORT_PHY_QCAPS 0x2aUL 138894aa69aSMichael Chan #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 139894aa69aSMichael Chan #define HWRM_PORT_PHY_I2C_READ 0x2cUL 140894aa69aSMichael Chan #define HWRM_PORT_LED_CFG 0x2dUL 141894aa69aSMichael Chan #define HWRM_PORT_LED_QCFG 0x2eUL 142894aa69aSMichael Chan #define HWRM_PORT_LED_QCAPS 0x2fUL 143894aa69aSMichael Chan #define HWRM_QUEUE_QPORTCFG 0x30UL 144894aa69aSMichael Chan #define HWRM_QUEUE_QCFG 0x31UL 145894aa69aSMichael Chan #define HWRM_QUEUE_CFG 0x32UL 146894aa69aSMichael Chan #define HWRM_FUNC_VLAN_CFG 0x33UL 147894aa69aSMichael Chan #define HWRM_FUNC_VLAN_QCFG 0x34UL 148894aa69aSMichael Chan #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 149894aa69aSMichael Chan #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 150894aa69aSMichael Chan #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 151894aa69aSMichael Chan #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 152894aa69aSMichael Chan #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 153894aa69aSMichael Chan #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 154894aa69aSMichael Chan #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 155894aa69aSMichael Chan #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 156894aa69aSMichael Chan #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 157894aa69aSMichael Chan #define HWRM_VNIC_ALLOC 0x40UL 158894aa69aSMichael Chan #define HWRM_VNIC_FREE 0x41UL 159894aa69aSMichael Chan #define HWRM_VNIC_CFG 0x42UL 160894aa69aSMichael Chan #define HWRM_VNIC_QCFG 0x43UL 161894aa69aSMichael Chan #define HWRM_VNIC_TPA_CFG 0x44UL 162894aa69aSMichael Chan #define HWRM_VNIC_TPA_QCFG 0x45UL 163894aa69aSMichael Chan #define HWRM_VNIC_RSS_CFG 0x46UL 164894aa69aSMichael Chan #define HWRM_VNIC_RSS_QCFG 0x47UL 165894aa69aSMichael Chan #define HWRM_VNIC_PLCMODES_CFG 0x48UL 166894aa69aSMichael Chan #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 167894aa69aSMichael Chan #define HWRM_VNIC_QCAPS 0x4aUL 16816db6323SMichael Chan #define HWRM_VNIC_UPDATE 0x4bUL 169894aa69aSMichael Chan #define HWRM_RING_ALLOC 0x50UL 170894aa69aSMichael Chan #define HWRM_RING_FREE 0x51UL 171894aa69aSMichael Chan #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 172894aa69aSMichael Chan #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 1736fc92c33SMichael Chan #define HWRM_RING_AGGINT_QCAPS 0x54UL 174bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_ALLOC 0x55UL 175bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_CFG 0x56UL 176bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_FREE 0x57UL 177894aa69aSMichael Chan #define HWRM_RING_RESET 0x5eUL 178894aa69aSMichael Chan #define HWRM_RING_GRP_ALLOC 0x60UL 179894aa69aSMichael Chan #define HWRM_RING_GRP_FREE 0x61UL 180bfc6e5fbSMichael Chan #define HWRM_RING_CFG 0x62UL 181bfc6e5fbSMichael Chan #define HWRM_RING_QCFG 0x63UL 182894aa69aSMichael Chan #define HWRM_RESERVED5 0x64UL 183894aa69aSMichael Chan #define HWRM_RESERVED6 0x65UL 184894aa69aSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 185894aa69aSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 18641136ab3SMichael Chan #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 18741136ab3SMichael Chan #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 18841136ab3SMichael Chan #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 18916db6323SMichael Chan #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 19016db6323SMichael Chan #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 19116db6323SMichael Chan #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 19278eeadb8SMichael Chan #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 19378eeadb8SMichael Chan #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 194894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 195894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_FREE 0x91UL 196894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_CFG 0x92UL 197894aa69aSMichael Chan #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 198894aa69aSMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 199894aa69aSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 200894aa69aSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 201894aa69aSMichael Chan #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 202894aa69aSMichael Chan #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 203894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 204894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 205894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 206894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 207894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 208894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 209894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 210894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 211894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 21231d357c0SMichael Chan #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 213894aa69aSMichael Chan #define HWRM_STAT_CTX_ALLOC 0xb0UL 214894aa69aSMichael Chan #define HWRM_STAT_CTX_FREE 0xb1UL 215894aa69aSMichael Chan #define HWRM_STAT_CTX_QUERY 0xb2UL 216894aa69aSMichael Chan #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 217d4f52de0SMichael Chan #define HWRM_PORT_QSTATS_EXT 0xb4UL 2183322479eSMichael Chan #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 2193322479eSMichael Chan #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 22072e0c9f9SMichael Chan #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 22172e0c9f9SMichael Chan #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 222460c2577SMichael Chan #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 2239d6b648cSMichael Chan #define HWRM_RESERVED7 0xbaUL 2249d6b648cSMichael Chan #define HWRM_PORT_TX_FIR_CFG 0xbbUL 2259d6b648cSMichael Chan #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 2269d6b648cSMichael Chan #define HWRM_PORT_ECN_QSTATS 0xbdUL 22716db6323SMichael Chan #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 22816db6323SMichael Chan #define HWRM_FW_LIVEPATCH 0xbfUL 229894aa69aSMichael Chan #define HWRM_FW_RESET 0xc0UL 230894aa69aSMichael Chan #define HWRM_FW_QSTATUS 0xc1UL 2316fc92c33SMichael Chan #define HWRM_FW_HEALTH_CHECK 0xc2UL 2326fc92c33SMichael Chan #define HWRM_FW_SYNC 0xc3UL 23341136ab3SMichael Chan #define HWRM_FW_STATE_QCAPS 0xc4UL 23472e0c9f9SMichael Chan #define HWRM_FW_STATE_QUIESCE 0xc5UL 23572e0c9f9SMichael Chan #define HWRM_FW_STATE_BACKUP 0xc6UL 23672e0c9f9SMichael Chan #define HWRM_FW_STATE_RESTORE 0xc7UL 237894aa69aSMichael Chan #define HWRM_FW_SET_TIME 0xc8UL 238894aa69aSMichael Chan #define HWRM_FW_GET_TIME 0xc9UL 239894aa69aSMichael Chan #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 240894aa69aSMichael Chan #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 241894aa69aSMichael Chan #define HWRM_FW_IPC_MAILBOX 0xccUL 242460c2577SMichael Chan #define HWRM_FW_ECN_CFG 0xcdUL 243460c2577SMichael Chan #define HWRM_FW_ECN_QCFG 0xceUL 244bfc6e5fbSMichael Chan #define HWRM_FW_SECURE_CFG 0xcfUL 245894aa69aSMichael Chan #define HWRM_EXEC_FWD_RESP 0xd0UL 246894aa69aSMichael Chan #define HWRM_REJECT_FWD_RESP 0xd1UL 247894aa69aSMichael Chan #define HWRM_FWD_RESP 0xd2UL 248894aa69aSMichael Chan #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 249d4f52de0SMichael Chan #define HWRM_OEM_CMD 0xd4UL 2504a50ddc2SMichael Chan #define HWRM_PORT_PRBS_TEST 0xd5UL 25172e0c9f9SMichael Chan #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 25272e0c9f9SMichael Chan #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 25341136ab3SMichael Chan #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 25441136ab3SMichael Chan #define HWRM_PORT_DSC_DUMP 0xd9UL 25578eeadb8SMichael Chan #define HWRM_PORT_EP_TX_QCFG 0xdaUL 25678eeadb8SMichael Chan #define HWRM_PORT_EP_TX_CFG 0xdbUL 257894aa69aSMichael Chan #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 25872e0c9f9SMichael Chan #define HWRM_REG_POWER_QUERY 0xe1UL 25941136ab3SMichael Chan #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 260460c2577SMichael Chan #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 261894aa69aSMichael Chan #define HWRM_WOL_FILTER_ALLOC 0xf0UL 262894aa69aSMichael Chan #define HWRM_WOL_FILTER_FREE 0xf1UL 263894aa69aSMichael Chan #define HWRM_WOL_FILTER_QCFG 0xf2UL 264894aa69aSMichael Chan #define HWRM_WOL_REASON_QCFG 0xf3UL 2653322479eSMichael Chan #define HWRM_CFA_METER_QCAPS 0xf4UL 266894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 267894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 268894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 269894aa69aSMichael Chan #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 270894aa69aSMichael Chan #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 2713293ec23SMichael Chan #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 272894aa69aSMichael Chan #define HWRM_CFA_VFR_ALLOC 0xfdUL 273894aa69aSMichael Chan #define HWRM_CFA_VFR_FREE 0xfeUL 274894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 275894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_FREE 0x101UL 276894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_INFO 0x102UL 277894aa69aSMichael Chan #define HWRM_CFA_FLOW_ALLOC 0x103UL 278894aa69aSMichael Chan #define HWRM_CFA_FLOW_FREE 0x104UL 279894aa69aSMichael Chan #define HWRM_CFA_FLOW_FLUSH 0x105UL 280894aa69aSMichael Chan #define HWRM_CFA_FLOW_STATS 0x106UL 281894aa69aSMichael Chan #define HWRM_CFA_FLOW_INFO 0x107UL 282894aa69aSMichael Chan #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 283894aa69aSMichael Chan #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 284894aa69aSMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 285894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 286894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 287894aa69aSMichael Chan #define HWRM_CFA_PAIR_ALLOC 0x10dUL 288894aa69aSMichael Chan #define HWRM_CFA_PAIR_FREE 0x10eUL 289894aa69aSMichael Chan #define HWRM_CFA_PAIR_INFO 0x10fUL 290894aa69aSMichael Chan #define HWRM_FW_IPC_MSG 0x110UL 291894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 29231d357c0SMichael Chan #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 2933322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 2943322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 2953322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 2963322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 2973322479eSMichael Chan #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 2983322479eSMichael Chan #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 2993322479eSMichael Chan #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 3003322479eSMichael Chan #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 3013322479eSMichael Chan #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 3023322479eSMichael Chan #define HWRM_CFA_COUNTER_CFG 0x11cUL 3033322479eSMichael Chan #define HWRM_CFA_COUNTER_QCFG 0x11dUL 3043322479eSMichael Chan #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 3053322479eSMichael Chan #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 3063322479eSMichael Chan #define HWRM_CFA_EEM_QCAPS 0x120UL 3073322479eSMichael Chan #define HWRM_CFA_EEM_CFG 0x121UL 3083322479eSMichael Chan #define HWRM_CFA_EEM_QCFG 0x122UL 3093322479eSMichael Chan #define HWRM_CFA_EEM_OP 0x123UL 3103322479eSMichael Chan #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 3114a50ddc2SMichael Chan #define HWRM_CFA_TFLIB 0x125UL 31278eeadb8SMichael Chan #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 31378eeadb8SMichael Chan #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 314894aa69aSMichael Chan #define HWRM_ENGINE_CKV_STATUS 0x12eUL 315894aa69aSMichael Chan #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 316894aa69aSMichael Chan #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 317894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 318894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 319894aa69aSMichael Chan #define HWRM_ENGINE_CKV_FLUSH 0x133UL 320894aa69aSMichael Chan #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 321894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 3223293ec23SMichael Chan #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 3234a50ddc2SMichael Chan #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 324894aa69aSMichael Chan #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 325894aa69aSMichael Chan #define HWRM_ENGINE_QG_QUERY 0x13dUL 326894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 327894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 328894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 329894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 330894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 331894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_BIND 0x143UL 332894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 333894aa69aSMichael Chan #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 334894aa69aSMichael Chan #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 335894aa69aSMichael Chan #define HWRM_ENGINE_SG_QUERY 0x147UL 336894aa69aSMichael Chan #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 337894aa69aSMichael Chan #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 338894aa69aSMichael Chan #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 339894aa69aSMichael Chan #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 340894aa69aSMichael Chan #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 341894aa69aSMichael Chan #define HWRM_ENGINE_STATS_CONFIG 0x155UL 342894aa69aSMichael Chan #define HWRM_ENGINE_STATS_CLEAR 0x156UL 343894aa69aSMichael Chan #define HWRM_ENGINE_STATS_QUERY 0x157UL 34441136ab3SMichael Chan #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 345894aa69aSMichael Chan #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 346894aa69aSMichael Chan #define HWRM_ENGINE_RQ_FREE 0x15fUL 347894aa69aSMichael Chan #define HWRM_ENGINE_CQ_ALLOC 0x160UL 348894aa69aSMichael Chan #define HWRM_ENGINE_CQ_FREE 0x161UL 349894aa69aSMichael Chan #define HWRM_ENGINE_NQ_ALLOC 0x162UL 350894aa69aSMichael Chan #define HWRM_ENGINE_NQ_FREE 0x163UL 351894aa69aSMichael Chan #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 3523293ec23SMichael Chan #define HWRM_ENGINE_FUNC_QCFG 0x165UL 353894aa69aSMichael Chan #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 354894aa69aSMichael Chan #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 3556fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 3566fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 3576fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 3586fc92c33SMichael Chan #define HWRM_FUNC_VF_BW_CFG 0x195UL 3596fc92c33SMichael Chan #define HWRM_FUNC_VF_BW_QCFG 0x196UL 3602792b5b9SMichael Chan #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 361460c2577SMichael Chan #define HWRM_FUNC_QSTATS_EXT 0x198UL 362bfc6e5fbSMichael Chan #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 36316db6323SMichael Chan #define HWRM_FUNC_SPD_CFG 0x19aUL 36416db6323SMichael Chan #define HWRM_FUNC_SPD_QCFG 0x19bUL 36578eeadb8SMichael Chan #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 36678eeadb8SMichael Chan #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 36778eeadb8SMichael Chan #define HWRM_FUNC_PTP_CFG 0x19eUL 36878eeadb8SMichael Chan #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 36978eeadb8SMichael Chan #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 37078eeadb8SMichael Chan #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 371fbfee257SMichael Chan #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 372894aa69aSMichael Chan #define HWRM_SELFTEST_QLIST 0x200UL 373894aa69aSMichael Chan #define HWRM_SELFTEST_EXEC 0x201UL 374894aa69aSMichael Chan #define HWRM_SELFTEST_IRQ 0x202UL 375894aa69aSMichael Chan #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 376d4f52de0SMichael Chan #define HWRM_PCIE_QSTATS 0x204UL 3774a50ddc2SMichael Chan #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 3784a50ddc2SMichael Chan #define HWRM_MFG_TIMERS_QUERY 0x206UL 3794a50ddc2SMichael Chan #define HWRM_MFG_OTP_CFG 0x207UL 3804a50ddc2SMichael Chan #define HWRM_MFG_OTP_QCFG 0x208UL 3814a50ddc2SMichael Chan #define HWRM_MFG_HDMA_TEST 0x209UL 382460c2577SMichael Chan #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 383460c2577SMichael Chan #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 38416db6323SMichael Chan #define HWRM_MFG_SOC_IMAGE 0x20cUL 38516db6323SMichael Chan #define HWRM_MFG_SOC_QSTATUS 0x20dUL 38616db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 38716db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 38816db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 38978eeadb8SMichael Chan #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 39078eeadb8SMichael Chan #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 39178eeadb8SMichael Chan #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 39278eeadb8SMichael Chan #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 393460c2577SMichael Chan #define HWRM_TF 0x2bcUL 394460c2577SMichael Chan #define HWRM_TF_VERSION_GET 0x2bdUL 395460c2577SMichael Chan #define HWRM_TF_SESSION_OPEN 0x2c6UL 396460c2577SMichael Chan #define HWRM_TF_SESSION_ATTACH 0x2c7UL 397bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_REGISTER 0x2c8UL 398bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 399bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_CLOSE 0x2caUL 400bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_QCFG 0x2cbUL 401bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 402bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 403bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 404bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 40578eeadb8SMichael Chan #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 406bfc6e5fbSMichael Chan #define HWRM_TF_TBL_TYPE_GET 0x2daUL 407bfc6e5fbSMichael Chan #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 408424174f1SVasundhara Volam #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 4099d6b648cSMichael Chan #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 4109d6b648cSMichael Chan #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 411bfc6e5fbSMichael Chan #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 412bfc6e5fbSMichael Chan #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 413bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 414bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_OP 0x2e7UL 415bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_CFG 0x2e8UL 416bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 417bfc6e5fbSMichael Chan #define HWRM_TF_EM_INSERT 0x2eaUL 418bfc6e5fbSMichael Chan #define HWRM_TF_EM_DELETE 0x2ebUL 41916db6323SMichael Chan #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 42078eeadb8SMichael Chan #define HWRM_TF_EM_MOVE 0x2edUL 421bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_SET 0x2f8UL 422bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_GET 0x2f9UL 423bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_MOVE 0x2faUL 424bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_FREE 0x2fbUL 425bfc6e5fbSMichael Chan #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 426bfc6e5fbSMichael Chan #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 4279d6b648cSMichael Chan #define HWRM_TF_IF_TBL_SET 0x2feUL 4289d6b648cSMichael Chan #define HWRM_TF_IF_TBL_GET 0x2ffUL 429460c2577SMichael Chan #define HWRM_SV 0x400UL 430894aa69aSMichael Chan #define HWRM_DBG_READ_DIRECT 0xff10UL 431894aa69aSMichael Chan #define HWRM_DBG_READ_INDIRECT 0xff11UL 432894aa69aSMichael Chan #define HWRM_DBG_WRITE_DIRECT 0xff12UL 433894aa69aSMichael Chan #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 434894aa69aSMichael Chan #define HWRM_DBG_DUMP 0xff14UL 435894aa69aSMichael Chan #define HWRM_DBG_ERASE_NVM 0xff15UL 436894aa69aSMichael Chan #define HWRM_DBG_CFG 0xff16UL 437894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_LIST 0xff17UL 438894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 439894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 4406fc92c33SMichael Chan #define HWRM_DBG_FW_CLI 0xff1aUL 4416fc92c33SMichael Chan #define HWRM_DBG_I2C_CMD 0xff1bUL 44231d357c0SMichael Chan #define HWRM_DBG_RING_INFO_GET 0xff1cUL 4434a50ddc2SMichael Chan #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 4444a50ddc2SMichael Chan #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 445460c2577SMichael Chan #define HWRM_DBG_DRV_TRACE 0xff1fUL 446460c2577SMichael Chan #define HWRM_DBG_QCAPS 0xff20UL 447460c2577SMichael Chan #define HWRM_DBG_QCFG 0xff21UL 448460c2577SMichael Chan #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 44978eeadb8SMichael Chan #define HWRM_DBG_USEQ_ALLOC 0xff23UL 45078eeadb8SMichael Chan #define HWRM_DBG_USEQ_FREE 0xff24UL 45178eeadb8SMichael Chan #define HWRM_DBG_USEQ_FLUSH 0xff25UL 45278eeadb8SMichael Chan #define HWRM_DBG_USEQ_QCAPS 0xff26UL 45378eeadb8SMichael Chan #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 45478eeadb8SMichael Chan #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 45578eeadb8SMichael Chan #define HWRM_DBG_USEQ_RUN 0xff29UL 45678eeadb8SMichael Chan #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 45778eeadb8SMichael Chan #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 45878eeadb8SMichael Chan #define HWRM_NVM_DEFRAG 0xffecUL 459bfc6e5fbSMichael Chan #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 460894aa69aSMichael Chan #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 461894aa69aSMichael Chan #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 462894aa69aSMichael Chan #define HWRM_NVM_FLUSH 0xfff0UL 463894aa69aSMichael Chan #define HWRM_NVM_GET_VARIABLE 0xfff1UL 464894aa69aSMichael Chan #define HWRM_NVM_SET_VARIABLE 0xfff2UL 465894aa69aSMichael Chan #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 466894aa69aSMichael Chan #define HWRM_NVM_MODIFY 0xfff4UL 467894aa69aSMichael Chan #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 468894aa69aSMichael Chan #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 469894aa69aSMichael Chan #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 470894aa69aSMichael Chan #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 471894aa69aSMichael Chan #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 472894aa69aSMichael Chan #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 473894aa69aSMichael Chan #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 474894aa69aSMichael Chan #define HWRM_NVM_RAW_DUMP 0xfffcUL 475894aa69aSMichael Chan #define HWRM_NVM_READ 0xfffdUL 476894aa69aSMichael Chan #define HWRM_NVM_WRITE 0xfffeUL 477894aa69aSMichael Chan #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 478894aa69aSMichael Chan #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 479894aa69aSMichael Chan __le16 unused_0[3]; 480894aa69aSMichael Chan }; 481894aa69aSMichael Chan 482894aa69aSMichael Chan /* ret_codes (size:64b/8B) */ 483894aa69aSMichael Chan struct ret_codes { 484894aa69aSMichael Chan __le16 error_code; 485894aa69aSMichael Chan #define HWRM_ERR_CODE_SUCCESS 0x0UL 486894aa69aSMichael Chan #define HWRM_ERR_CODE_FAIL 0x1UL 487894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 488894aa69aSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 489894aa69aSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 490894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 491894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 492894aa69aSMichael Chan #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 493894aa69aSMichael Chan #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 4946fc92c33SMichael Chan #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 4953322479eSMichael Chan #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 4963322479eSMichael Chan #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 4974a50ddc2SMichael Chan #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 4984a50ddc2SMichael Chan #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 4994a50ddc2SMichael Chan #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 500894aa69aSMichael Chan #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 50141136ab3SMichael Chan #define HWRM_ERR_CODE_BUSY 0x10UL 5029d6b648cSMichael Chan #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 50378eeadb8SMichael Chan #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 50431d357c0SMichael Chan #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 505894aa69aSMichael Chan #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 506894aa69aSMichael Chan #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 507894aa69aSMichael Chan #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 508894aa69aSMichael Chan __le16 unused_0[3]; 509894aa69aSMichael Chan }; 510894aa69aSMichael Chan 511894aa69aSMichael Chan /* hwrm_err_output (size:128b/16B) */ 512894aa69aSMichael Chan struct hwrm_err_output { 513894aa69aSMichael Chan __le16 error_code; 514894aa69aSMichael Chan __le16 req_type; 515894aa69aSMichael Chan __le16 seq_id; 516894aa69aSMichael Chan __le16 resp_len; 517894aa69aSMichael Chan __le32 opaque_0; 518894aa69aSMichael Chan __le16 opaque_1; 519894aa69aSMichael Chan u8 cmd_err; 520894aa69aSMichael Chan u8 valid; 521894aa69aSMichael Chan }; 52287c374deSMichael Chan #define HWRM_NA_SIGNATURE ((__le32)(-1)) 523894aa69aSMichael Chan #define HWRM_MAX_REQ_LEN 128 5243293ec23SMichael Chan #define HWRM_MAX_RESP_LEN 704 525894aa69aSMichael Chan #define HW_HASH_INDEX_SIZE 0x80 52687c374deSMichael Chan #define HW_HASH_KEY_SIZE 40 527894aa69aSMichael Chan #define HWRM_RESP_VALID_KEY 1 5284a50ddc2SMichael Chan #define HWRM_TARGET_ID_BONO 0xFFF8 5294a50ddc2SMichael Chan #define HWRM_TARGET_ID_KONG 0xFFF9 5304a50ddc2SMichael Chan #define HWRM_TARGET_ID_APE 0xFFFA 5314a50ddc2SMichael Chan #define HWRM_TARGET_ID_TOOLS 0xFFFD 532894aa69aSMichael Chan #define HWRM_VERSION_MAJOR 1 53331d357c0SMichael Chan #define HWRM_VERSION_MINOR 10 53416db6323SMichael Chan #define HWRM_VERSION_UPDATE 2 535*21e70778SMichael Chan #define HWRM_VERSION_RSVD 63 536*21e70778SMichael Chan #define HWRM_VERSION_STR "1.10.2.63" 537c0c050c5SMichael Chan 538894aa69aSMichael Chan /* hwrm_ver_get_input (size:192b/24B) */ 539894aa69aSMichael Chan struct hwrm_ver_get_input { 540894aa69aSMichael Chan __le16 req_type; 541894aa69aSMichael Chan __le16 cmpl_ring; 542894aa69aSMichael Chan __le16 seq_id; 543894aa69aSMichael Chan __le16 target_id; 544894aa69aSMichael Chan __le64 resp_addr; 545894aa69aSMichael Chan u8 hwrm_intf_maj; 546894aa69aSMichael Chan u8 hwrm_intf_min; 547894aa69aSMichael Chan u8 hwrm_intf_upd; 548894aa69aSMichael Chan u8 unused_0[5]; 549894aa69aSMichael Chan }; 550894aa69aSMichael Chan 551894aa69aSMichael Chan /* hwrm_ver_get_output (size:1408b/176B) */ 552894aa69aSMichael Chan struct hwrm_ver_get_output { 553894aa69aSMichael Chan __le16 error_code; 554894aa69aSMichael Chan __le16 req_type; 555894aa69aSMichael Chan __le16 seq_id; 556894aa69aSMichael Chan __le16 resp_len; 557894aa69aSMichael Chan u8 hwrm_intf_maj_8b; 558894aa69aSMichael Chan u8 hwrm_intf_min_8b; 559894aa69aSMichael Chan u8 hwrm_intf_upd_8b; 560894aa69aSMichael Chan u8 hwrm_intf_rsvd_8b; 561894aa69aSMichael Chan u8 hwrm_fw_maj_8b; 562894aa69aSMichael Chan u8 hwrm_fw_min_8b; 563894aa69aSMichael Chan u8 hwrm_fw_bld_8b; 564894aa69aSMichael Chan u8 hwrm_fw_rsvd_8b; 565894aa69aSMichael Chan u8 mgmt_fw_maj_8b; 566894aa69aSMichael Chan u8 mgmt_fw_min_8b; 567894aa69aSMichael Chan u8 mgmt_fw_bld_8b; 568894aa69aSMichael Chan u8 mgmt_fw_rsvd_8b; 569894aa69aSMichael Chan u8 netctrl_fw_maj_8b; 570894aa69aSMichael Chan u8 netctrl_fw_min_8b; 571894aa69aSMichael Chan u8 netctrl_fw_bld_8b; 572894aa69aSMichael Chan u8 netctrl_fw_rsvd_8b; 573894aa69aSMichael Chan __le32 dev_caps_cfg; 574894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 575894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 576894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 577894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 57831d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 57931d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 58031d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 58131d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 58231d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 5833322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 5843322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 5853322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 5863322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 5874a50ddc2SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 588460c2577SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 589fbfee257SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 590894aa69aSMichael Chan u8 roce_fw_maj_8b; 591894aa69aSMichael Chan u8 roce_fw_min_8b; 592894aa69aSMichael Chan u8 roce_fw_bld_8b; 593894aa69aSMichael Chan u8 roce_fw_rsvd_8b; 594894aa69aSMichael Chan char hwrm_fw_name[16]; 595894aa69aSMichael Chan char mgmt_fw_name[16]; 596894aa69aSMichael Chan char netctrl_fw_name[16]; 5974a50ddc2SMichael Chan char active_pkg_name[16]; 598894aa69aSMichael Chan char roce_fw_name[16]; 599894aa69aSMichael Chan __le16 chip_num; 600894aa69aSMichael Chan u8 chip_rev; 601894aa69aSMichael Chan u8 chip_metal; 602894aa69aSMichael Chan u8 chip_bond_id; 603894aa69aSMichael Chan u8 chip_platform_type; 604894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 605894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 606894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 607894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 608894aa69aSMichael Chan __le16 max_req_win_len; 609894aa69aSMichael Chan __le16 max_resp_len; 610894aa69aSMichael Chan __le16 def_req_timeout; 611894aa69aSMichael Chan u8 flags; 612894aa69aSMichael Chan #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 613894aa69aSMichael Chan #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 61416db6323SMichael Chan #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 615894aa69aSMichael Chan u8 unused_0[2]; 616894aa69aSMichael Chan u8 always_1; 617894aa69aSMichael Chan __le16 hwrm_intf_major; 618894aa69aSMichael Chan __le16 hwrm_intf_minor; 619894aa69aSMichael Chan __le16 hwrm_intf_build; 620894aa69aSMichael Chan __le16 hwrm_intf_patch; 621894aa69aSMichael Chan __le16 hwrm_fw_major; 622894aa69aSMichael Chan __le16 hwrm_fw_minor; 623894aa69aSMichael Chan __le16 hwrm_fw_build; 624894aa69aSMichael Chan __le16 hwrm_fw_patch; 625894aa69aSMichael Chan __le16 mgmt_fw_major; 626894aa69aSMichael Chan __le16 mgmt_fw_minor; 627894aa69aSMichael Chan __le16 mgmt_fw_build; 628894aa69aSMichael Chan __le16 mgmt_fw_patch; 629894aa69aSMichael Chan __le16 netctrl_fw_major; 630894aa69aSMichael Chan __le16 netctrl_fw_minor; 631894aa69aSMichael Chan __le16 netctrl_fw_build; 632894aa69aSMichael Chan __le16 netctrl_fw_patch; 633894aa69aSMichael Chan __le16 roce_fw_major; 634894aa69aSMichael Chan __le16 roce_fw_minor; 635894aa69aSMichael Chan __le16 roce_fw_build; 636894aa69aSMichael Chan __le16 roce_fw_patch; 637894aa69aSMichael Chan __le16 max_ext_req_len; 63878eeadb8SMichael Chan __le16 max_req_timeout; 63978eeadb8SMichael Chan u8 unused_1[3]; 640894aa69aSMichael Chan u8 valid; 641894aa69aSMichael Chan }; 642894aa69aSMichael Chan 643894aa69aSMichael Chan /* eject_cmpl (size:128b/16B) */ 644c0c050c5SMichael Chan struct eject_cmpl { 645c0c050c5SMichael Chan __le16 type; 646c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_MASK 0x3fUL 647c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_SFT 0 648441cabbbSMichael Chan #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 649894aa69aSMichael Chan #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 6503322479eSMichael Chan #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 6513322479eSMichael Chan #define EJECT_CMPL_FLAGS_SFT 6 6523322479eSMichael Chan #define EJECT_CMPL_FLAGS_ERROR 0x40UL 653c0c050c5SMichael Chan __le16 len; 654c0c050c5SMichael Chan __le32 opaque; 6553322479eSMichael Chan __le16 v; 656c0c050c5SMichael Chan #define EJECT_CMPL_V 0x1UL 6573322479eSMichael Chan #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 6583322479eSMichael Chan #define EJECT_CMPL_ERRORS_SFT 1 6593322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 6603322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 6613322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 6623322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 6633322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 6643322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 6653322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 6663322479eSMichael Chan __le16 reserved16; 667c0c050c5SMichael Chan __le32 unused_2; 668c0c050c5SMichael Chan }; 669c0c050c5SMichael Chan 670894aa69aSMichael Chan /* hwrm_cmpl (size:128b/16B) */ 671c0c050c5SMichael Chan struct hwrm_cmpl { 672c0c050c5SMichael Chan __le16 type; 67387c374deSMichael Chan #define CMPL_TYPE_MASK 0x3fUL 67487c374deSMichael Chan #define CMPL_TYPE_SFT 0 67587c374deSMichael Chan #define CMPL_TYPE_HWRM_DONE 0x20UL 676894aa69aSMichael Chan #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 677c0c050c5SMichael Chan __le16 sequence_id; 678c0c050c5SMichael Chan __le32 unused_1; 679c0c050c5SMichael Chan __le32 v; 68087c374deSMichael Chan #define CMPL_V 0x1UL 681c0c050c5SMichael Chan __le32 unused_3; 682c0c050c5SMichael Chan }; 683c0c050c5SMichael Chan 684894aa69aSMichael Chan /* hwrm_fwd_req_cmpl (size:128b/16B) */ 685c0c050c5SMichael Chan struct hwrm_fwd_req_cmpl { 686c0c050c5SMichael Chan __le16 req_len_type; 68787c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 68887c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_SFT 0 68987c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 690894aa69aSMichael Chan #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 69187c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 69287c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_SFT 6 693c0c050c5SMichael Chan __le16 source_id; 694894aa69aSMichael Chan __le32 unused0; 695c0c050c5SMichael Chan __le32 req_buf_addr_v[2]; 69687c374deSMichael Chan #define FWD_REQ_CMPL_V 0x1UL 69787c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 69887c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 699c0c050c5SMichael Chan }; 700c0c050c5SMichael Chan 701894aa69aSMichael Chan /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 702c0c050c5SMichael Chan struct hwrm_fwd_resp_cmpl { 703c0c050c5SMichael Chan __le16 type; 70487c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 70587c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_SFT 0 70687c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 707894aa69aSMichael Chan #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 708c0c050c5SMichael Chan __le16 source_id; 709c0c050c5SMichael Chan __le16 resp_len; 710c0c050c5SMichael Chan __le16 unused_1; 711c0c050c5SMichael Chan __le32 resp_buf_addr_v[2]; 71287c374deSMichael Chan #define FWD_RESP_CMPL_V 0x1UL 71387c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 71487c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 715c0c050c5SMichael Chan }; 716c0c050c5SMichael Chan 717894aa69aSMichael Chan /* hwrm_async_event_cmpl (size:128b/16B) */ 718c0c050c5SMichael Chan struct hwrm_async_event_cmpl { 719c0c050c5SMichael Chan __le16 type; 72087c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 72187c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_SFT 0 72287c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 723894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 724c0c050c5SMichael Chan __le16 event_id; 72587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 72687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 72787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 72887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 72987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 73087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 73187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 73287c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 73331d357c0SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 7343293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 7359d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 73687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 73787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 73887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 73987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 74087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 74187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 74287c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 74387c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 74487c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 74557922b0aSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 7466fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 74731d357c0SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 7483322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 7493322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 7503322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 7513293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 7523293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 7533293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 7542792b5b9SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 7552792b5b9SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 75641136ab3SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 75741136ab3SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 758460c2577SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 75931f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 76078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER 0x43UL 76178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 76278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 76378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x46UL 7643322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 76587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 766894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 767c0c050c5SMichael Chan __le32 event_data2; 768c0c050c5SMichael Chan u8 opaque_v; 76987c374deSMichael Chan #define ASYNC_EVENT_CMPL_V 0x1UL 77087c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 77187c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 772c193554eSMichael Chan u8 timestamp_lo; 773c193554eSMichael Chan __le16 timestamp_hi; 774c0c050c5SMichael Chan __le32 event_data1; 775c0c050c5SMichael Chan }; 776c0c050c5SMichael Chan 777894aa69aSMichael Chan /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 778c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_status_change { 779c0c050c5SMichael Chan __le16 type; 78087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 78187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 78287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 783894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 784c0c050c5SMichael Chan __le16 event_id; 78587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 786894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 787c0c050c5SMichael Chan __le32 event_data2; 788c0c050c5SMichael Chan u8 opaque_v; 78987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 79087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 79187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 792c193554eSMichael Chan u8 timestamp_lo; 793c193554eSMichael Chan __le16 timestamp_hi; 794c0c050c5SMichael Chan __le32 event_data1; 79587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 796894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 797894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 79887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 79987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 80087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 80187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 80287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 8036fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 8046fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 805c0c050c5SMichael Chan }; 806c0c050c5SMichael Chan 807894aa69aSMichael Chan /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 808c0c050c5SMichael Chan struct hwrm_async_event_cmpl_port_conn_not_allowed { 809c0c050c5SMichael Chan __le16 type; 81087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 81187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 81287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 813894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 814c0c050c5SMichael Chan __le16 event_id; 81587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 816894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 817c0c050c5SMichael Chan __le32 event_data2; 818c0c050c5SMichael Chan u8 opaque_v; 81987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 82087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 82187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 822c193554eSMichael Chan u8 timestamp_lo; 823c193554eSMichael Chan __le16 timestamp_hi; 824c0c050c5SMichael Chan __le32 event_data1; 82587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 82687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 82787c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 82887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 82987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 83087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 83187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 83287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 83387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 83411f15ed3SMichael Chan }; 83511f15ed3SMichael Chan 836894aa69aSMichael Chan /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 83711f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_change { 83811f15ed3SMichael Chan __le16 type; 83987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 84087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 84187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 842894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 84311f15ed3SMichael Chan __le16 event_id; 84487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 845894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 84611f15ed3SMichael Chan __le32 event_data2; 84711f15ed3SMichael Chan u8 opaque_v; 84887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 84987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 85087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 85111f15ed3SMichael Chan u8 timestamp_lo; 85211f15ed3SMichael Chan __le16 timestamp_hi; 85311f15ed3SMichael Chan __le32 event_data1; 85487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 85587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 85687c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 85787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 858c0c050c5SMichael Chan }; 859c0c050c5SMichael Chan 8603322479eSMichael Chan /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 8613322479eSMichael Chan struct hwrm_async_event_cmpl_reset_notify { 8623322479eSMichael Chan __le16 type; 8633322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 8643322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 8653322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 8663322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 8673322479eSMichael Chan __le16 event_id; 8683322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 8693322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 8703322479eSMichael Chan __le32 event_data2; 87116db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 87216db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 8733322479eSMichael Chan u8 opaque_v; 8743322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 8753322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 8763322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 8773322479eSMichael Chan u8 timestamp_lo; 8783322479eSMichael Chan __le16 timestamp_hi; 8793322479eSMichael Chan __le32 event_data1; 8803322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 8813322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 8823322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 8833322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 8843322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 8853322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 8863322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 8873322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 8883322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 8893322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 89016db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 891fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 892fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 8933322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 8943322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 8953322479eSMichael Chan }; 8963322479eSMichael Chan 8973293ec23SMichael Chan /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 8983293ec23SMichael Chan struct hwrm_async_event_cmpl_error_recovery { 8993293ec23SMichael Chan __le16 type; 9003293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 9013293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 9023293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9033293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 9043293ec23SMichael Chan __le16 event_id; 9053293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 9063293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 9073293ec23SMichael Chan __le32 event_data2; 9083293ec23SMichael Chan u8 opaque_v; 9093293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 9103293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 9113293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 9123293ec23SMichael Chan u8 timestamp_lo; 9133293ec23SMichael Chan __le16 timestamp_hi; 9143293ec23SMichael Chan __le32 event_data1; 9153293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 9163293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 9173293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 9183293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 9193293ec23SMichael Chan }; 9203293ec23SMichael Chan 9219d6b648cSMichael Chan /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 9229d6b648cSMichael Chan struct hwrm_async_event_cmpl_ring_monitor_msg { 9239d6b648cSMichael Chan __le16 type; 9249d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 9259d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 9269d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9279d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 9289d6b648cSMichael Chan __le16 event_id; 9299d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 9309d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 9319d6b648cSMichael Chan __le32 event_data2; 9329d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 9339d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 9349d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 9359d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 9369d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 9379d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 9389d6b648cSMichael Chan u8 opaque_v; 9399d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 9409d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 9419d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 9429d6b648cSMichael Chan u8 timestamp_lo; 9439d6b648cSMichael Chan __le16 timestamp_hi; 9449d6b648cSMichael Chan __le32 event_data1; 9459d6b648cSMichael Chan }; 9469d6b648cSMichael Chan 947894aa69aSMichael Chan /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 94811f15ed3SMichael Chan struct hwrm_async_event_cmpl_vf_cfg_change { 94911f15ed3SMichael Chan __le16 type; 95087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 95187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 95287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 953894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 95411f15ed3SMichael Chan __le16 event_id; 95587c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 956894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 95711f15ed3SMichael Chan __le32 event_data2; 95878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 95978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 96011f15ed3SMichael Chan u8 opaque_v; 96187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 96287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 96387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 96411f15ed3SMichael Chan u8 timestamp_lo; 96511f15ed3SMichael Chan __le16 timestamp_hi; 96611f15ed3SMichael Chan __le32 event_data1; 96787c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 96887c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 96987c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 97087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 97131d357c0SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 97211f15ed3SMichael Chan }; 97311f15ed3SMichael Chan 97472e0c9f9SMichael Chan /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 97572e0c9f9SMichael Chan struct hwrm_async_event_cmpl_default_vnic_change { 97672e0c9f9SMichael Chan __le16 type; 97772e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 97872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 97972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 98072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 98172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 98272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 98372e0c9f9SMichael Chan __le16 event_id; 98472e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 98572e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 98672e0c9f9SMichael Chan __le32 event_data2; 98772e0c9f9SMichael Chan u8 opaque_v; 98872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 98972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 99072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 99172e0c9f9SMichael Chan u8 timestamp_lo; 99272e0c9f9SMichael Chan __le16 timestamp_hi; 99372e0c9f9SMichael Chan __le32 event_data1; 99472e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 99572e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 99672e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 99772e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 99872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 99972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 100072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 100172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 100272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 100372e0c9f9SMichael Chan }; 100472e0c9f9SMichael Chan 10053322479eSMichael Chan /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 10063322479eSMichael Chan struct hwrm_async_event_cmpl_hw_flow_aged { 10073322479eSMichael Chan __le16 type; 10083322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 10093322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 10103322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10113322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 10123322479eSMichael Chan __le16 event_id; 10133322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 10143322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 10153322479eSMichael Chan __le32 event_data2; 10163322479eSMichael Chan u8 opaque_v; 10173322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 10183322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 10193322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 10203322479eSMichael Chan u8 timestamp_lo; 10213322479eSMichael Chan __le16 timestamp_hi; 10223322479eSMichael Chan __le32 event_data1; 10233322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 10243322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 10253322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 10263322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 10273322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 10283322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 10293322479eSMichael Chan }; 10303322479eSMichael Chan 10313322479eSMichael Chan /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 10323322479eSMichael Chan struct hwrm_async_event_cmpl_eem_cache_flush_req { 10333322479eSMichael Chan __le16 type; 10343322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 10353322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 10363322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10373322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 10383322479eSMichael Chan __le16 event_id; 10393322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 10403322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 10413322479eSMichael Chan __le32 event_data2; 10423322479eSMichael Chan u8 opaque_v; 10433322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 10443322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 10453322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 10463322479eSMichael Chan u8 timestamp_lo; 10473322479eSMichael Chan __le16 timestamp_hi; 10483322479eSMichael Chan __le32 event_data1; 10493322479eSMichael Chan }; 10503322479eSMichael Chan 10513322479eSMichael Chan /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 10523322479eSMichael Chan struct hwrm_async_event_cmpl_eem_cache_flush_done { 10533322479eSMichael Chan __le16 type; 10543322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 10553322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 10563322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10573322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 10583322479eSMichael Chan __le16 event_id; 10593322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 10603322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 10613322479eSMichael Chan __le32 event_data2; 10623322479eSMichael Chan u8 opaque_v; 10633322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 10643322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 10653322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 10663322479eSMichael Chan u8 timestamp_lo; 10673322479eSMichael Chan __le16 timestamp_hi; 10683322479eSMichael Chan __le32 event_data1; 10693322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 10703322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 10713322479eSMichael Chan }; 10723322479eSMichael Chan 10739d6b648cSMichael Chan /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 10749d6b648cSMichael Chan struct hwrm_async_event_cmpl_deferred_response { 10759d6b648cSMichael Chan __le16 type; 10769d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 10779d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 10789d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10799d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 10809d6b648cSMichael Chan __le16 event_id; 10819d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 10829d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 10839d6b648cSMichael Chan __le32 event_data2; 10849d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 10859d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 10869d6b648cSMichael Chan u8 opaque_v; 10879d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 10889d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 10899d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 10909d6b648cSMichael Chan u8 timestamp_lo; 10919d6b648cSMichael Chan __le16 timestamp_hi; 10929d6b648cSMichael Chan __le32 event_data1; 10939d6b648cSMichael Chan }; 10949d6b648cSMichael Chan 109531f67c2eSMichael Chan /* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 109631f67c2eSMichael Chan struct hwrm_async_event_cmpl_echo_request { 109731f67c2eSMichael Chan __le16 type; 109831f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 109931f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 110031f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 110131f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 110231f67c2eSMichael Chan __le16 event_id; 110331f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 110431f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 110531f67c2eSMichael Chan __le32 event_data2; 110631f67c2eSMichael Chan u8 opaque_v; 110731f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 110831f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 110931f67c2eSMichael Chan #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 111031f67c2eSMichael Chan u8 timestamp_lo; 111131f67c2eSMichael Chan __le16 timestamp_hi; 111231f67c2eSMichael Chan __le32 event_data1; 111331f67c2eSMichael Chan }; 111431f67c2eSMichael Chan 111578eeadb8SMichael Chan /* hwrm_async_event_cmpl_phc_master (size:128b/16B) */ 111678eeadb8SMichael Chan struct hwrm_async_event_cmpl_phc_master { 111778eeadb8SMichael Chan __le16 type; 111878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK 0x3fUL 111978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT 0 112078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 112178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT 112278eeadb8SMichael Chan __le16 event_id; 112378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL 112478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 112578eeadb8SMichael Chan __le32 event_data2; 112678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 112778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0 112878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 112978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT 16 113078eeadb8SMichael Chan u8 opaque_v; 113178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_V 0x1UL 113278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL 113378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1 113478eeadb8SMichael Chan u8 timestamp_lo; 113578eeadb8SMichael Chan __le16 timestamp_hi; 113678eeadb8SMichael Chan __le32 event_data1; 113778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK 0xfUL 113878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT 0 113978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 114078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 114178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 114278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER 114378eeadb8SMichael Chan }; 114478eeadb8SMichael Chan 114578eeadb8SMichael Chan /* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 114678eeadb8SMichael Chan struct hwrm_async_event_cmpl_pps_timestamp { 114778eeadb8SMichael Chan __le16 type; 114878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 114978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 115078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 115178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 115278eeadb8SMichael Chan __le16 event_id; 115378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 115478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 115578eeadb8SMichael Chan __le32 event_data2; 115678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 115778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 115878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 115978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 116078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 116178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 116278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 116378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 116478eeadb8SMichael Chan u8 opaque_v; 116578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 116678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 116778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 116878eeadb8SMichael Chan u8 timestamp_lo; 116978eeadb8SMichael Chan __le16 timestamp_hi; 117078eeadb8SMichael Chan __le32 event_data1; 117178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 117278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 117378eeadb8SMichael Chan }; 117478eeadb8SMichael Chan 117578eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 117678eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report { 117778eeadb8SMichael Chan __le16 type; 117878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 117978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 118078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 118178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 118278eeadb8SMichael Chan __le16 event_id; 118378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 118478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 118578eeadb8SMichael Chan __le32 event_data2; 118678eeadb8SMichael Chan u8 opaque_v; 118778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 118878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 118978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 119078eeadb8SMichael Chan u8 timestamp_lo; 119178eeadb8SMichael Chan __le16 timestamp_hi; 119278eeadb8SMichael Chan __le32 event_data1; 119378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 119478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 119578eeadb8SMichael Chan }; 119678eeadb8SMichael Chan 119778eeadb8SMichael Chan /* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 119878eeadb8SMichael Chan struct hwrm_async_event_cmpl_hwrm_error { 119978eeadb8SMichael Chan __le16 type; 120078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 120178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 120278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 120378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 120478eeadb8SMichael Chan __le16 event_id; 120578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 120678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 120778eeadb8SMichael Chan __le32 event_data2; 120878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 120978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 121078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 121178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 121278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 121378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 121478eeadb8SMichael Chan u8 opaque_v; 121578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 121678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 121778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 121878eeadb8SMichael Chan u8 timestamp_lo; 121978eeadb8SMichael Chan __le16 timestamp_hi; 122078eeadb8SMichael Chan __le32 event_data1; 122178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 122278eeadb8SMichael Chan }; 122378eeadb8SMichael Chan 122478eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 122578eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_base { 122678eeadb8SMichael Chan __le16 type; 122778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 122878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 122978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 123078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 123178eeadb8SMichael Chan __le16 event_id; 123278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 123378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 123478eeadb8SMichael Chan __le32 event_data2; 123578eeadb8SMichael Chan u8 opaque_v; 123678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 123778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 123878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 123978eeadb8SMichael Chan u8 timestamp_lo; 124078eeadb8SMichael Chan __le16 timestamp_hi; 124178eeadb8SMichael Chan __le32 event_data1; 124278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 124378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 124478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 124578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 124678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 124778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1248fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1249fbfee257SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 125078eeadb8SMichael Chan }; 125178eeadb8SMichael Chan 125278eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 125378eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_pause_storm { 125478eeadb8SMichael Chan __le16 type; 125578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 125678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 125778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 125878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 125978eeadb8SMichael Chan __le16 event_id; 126078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 126178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 126278eeadb8SMichael Chan __le32 event_data2; 126378eeadb8SMichael Chan u8 opaque_v; 126478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 126578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 126678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 126778eeadb8SMichael Chan u8 timestamp_lo; 126878eeadb8SMichael Chan __le16 timestamp_hi; 126978eeadb8SMichael Chan __le32 event_data1; 127078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 127178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 127278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 127378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 127478eeadb8SMichael Chan }; 127578eeadb8SMichael Chan 127678eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 127778eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_invalid_signal { 127878eeadb8SMichael Chan __le16 type; 127978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 128078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 128178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 128278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 128378eeadb8SMichael Chan __le16 event_id; 128478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 128578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 128678eeadb8SMichael Chan __le32 event_data2; 128778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 128878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 128978eeadb8SMichael Chan u8 opaque_v; 129078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 129178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 129278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 129378eeadb8SMichael Chan u8 timestamp_lo; 129478eeadb8SMichael Chan __le16 timestamp_hi; 129578eeadb8SMichael Chan __le32 event_data1; 129678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 129778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 129878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 129978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 130078eeadb8SMichael Chan }; 130178eeadb8SMichael Chan 130278eeadb8SMichael Chan /* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 130378eeadb8SMichael Chan struct hwrm_async_event_cmpl_error_report_nvm { 130478eeadb8SMichael Chan __le16 type; 130578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 130678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 130778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 130878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 130978eeadb8SMichael Chan __le16 event_id; 131078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 131178eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 131278eeadb8SMichael Chan __le32 event_data2; 131378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 131478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 131578eeadb8SMichael Chan u8 opaque_v; 131678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 131778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 131878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 131978eeadb8SMichael Chan u8 timestamp_lo; 132078eeadb8SMichael Chan __le16 timestamp_hi; 132178eeadb8SMichael Chan __le32 event_data1; 132278eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 132378eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 132478eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 132578eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 132678eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 132778eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 132878eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 132978eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 133078eeadb8SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 133178eeadb8SMichael Chan }; 133278eeadb8SMichael Chan 1333894aa69aSMichael Chan /* hwrm_func_reset_input (size:192b/24B) */ 1334c0c050c5SMichael Chan struct hwrm_func_reset_input { 1335c0c050c5SMichael Chan __le16 req_type; 1336c0c050c5SMichael Chan __le16 cmpl_ring; 1337c0c050c5SMichael Chan __le16 seq_id; 1338c0c050c5SMichael Chan __le16 target_id; 1339c0c050c5SMichael Chan __le64 resp_addr; 1340c0c050c5SMichael Chan __le32 enables; 1341c0c050c5SMichael Chan #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1342c0c050c5SMichael Chan __le16 vf_id; 1343c193554eSMichael Chan u8 func_reset_level; 1344441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1345441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1346441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1347441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1348894aa69aSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1349c193554eSMichael Chan u8 unused_0; 1350c0c050c5SMichael Chan }; 1351c0c050c5SMichael Chan 1352894aa69aSMichael Chan /* hwrm_func_reset_output (size:128b/16B) */ 1353c0c050c5SMichael Chan struct hwrm_func_reset_output { 1354c0c050c5SMichael Chan __le16 error_code; 1355c0c050c5SMichael Chan __le16 req_type; 1356c0c050c5SMichael Chan __le16 seq_id; 1357c0c050c5SMichael Chan __le16 resp_len; 1358894aa69aSMichael Chan u8 unused_0[7]; 1359c0c050c5SMichael Chan u8 valid; 1360c0c050c5SMichael Chan }; 1361c0c050c5SMichael Chan 1362894aa69aSMichael Chan /* hwrm_func_getfid_input (size:192b/24B) */ 1363c0c050c5SMichael Chan struct hwrm_func_getfid_input { 1364c0c050c5SMichael Chan __le16 req_type; 1365c0c050c5SMichael Chan __le16 cmpl_ring; 1366c0c050c5SMichael Chan __le16 seq_id; 1367c0c050c5SMichael Chan __le16 target_id; 1368c0c050c5SMichael Chan __le64 resp_addr; 1369c0c050c5SMichael Chan __le32 enables; 1370c0c050c5SMichael Chan #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1371c0c050c5SMichael Chan __le16 pci_id; 1372894aa69aSMichael Chan u8 unused_0[2]; 1373c0c050c5SMichael Chan }; 1374c0c050c5SMichael Chan 1375894aa69aSMichael Chan /* hwrm_func_getfid_output (size:128b/16B) */ 1376c0c050c5SMichael Chan struct hwrm_func_getfid_output { 1377c0c050c5SMichael Chan __le16 error_code; 1378c0c050c5SMichael Chan __le16 req_type; 1379c0c050c5SMichael Chan __le16 seq_id; 1380c0c050c5SMichael Chan __le16 resp_len; 1381c0c050c5SMichael Chan __le16 fid; 1382894aa69aSMichael Chan u8 unused_0[5]; 1383c0c050c5SMichael Chan u8 valid; 1384c0c050c5SMichael Chan }; 1385c0c050c5SMichael Chan 1386894aa69aSMichael Chan /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1387c0c050c5SMichael Chan struct hwrm_func_vf_alloc_input { 1388c0c050c5SMichael Chan __le16 req_type; 1389c0c050c5SMichael Chan __le16 cmpl_ring; 1390c0c050c5SMichael Chan __le16 seq_id; 1391c0c050c5SMichael Chan __le16 target_id; 1392c0c050c5SMichael Chan __le64 resp_addr; 1393c0c050c5SMichael Chan __le32 enables; 1394c0c050c5SMichael Chan #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1395c0c050c5SMichael Chan __le16 first_vf_id; 1396c0c050c5SMichael Chan __le16 num_vfs; 1397c0c050c5SMichael Chan }; 1398c0c050c5SMichael Chan 1399894aa69aSMichael Chan /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1400c0c050c5SMichael Chan struct hwrm_func_vf_alloc_output { 1401c0c050c5SMichael Chan __le16 error_code; 1402c0c050c5SMichael Chan __le16 req_type; 1403c0c050c5SMichael Chan __le16 seq_id; 1404c0c050c5SMichael Chan __le16 resp_len; 1405c0c050c5SMichael Chan __le16 first_vf_id; 1406894aa69aSMichael Chan u8 unused_0[5]; 1407c0c050c5SMichael Chan u8 valid; 1408c0c050c5SMichael Chan }; 1409c0c050c5SMichael Chan 1410894aa69aSMichael Chan /* hwrm_func_vf_free_input (size:192b/24B) */ 1411c0c050c5SMichael Chan struct hwrm_func_vf_free_input { 1412c0c050c5SMichael Chan __le16 req_type; 1413c0c050c5SMichael Chan __le16 cmpl_ring; 1414c0c050c5SMichael Chan __le16 seq_id; 1415c0c050c5SMichael Chan __le16 target_id; 1416c0c050c5SMichael Chan __le64 resp_addr; 1417c0c050c5SMichael Chan __le32 enables; 1418c0c050c5SMichael Chan #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1419c0c050c5SMichael Chan __le16 first_vf_id; 1420c0c050c5SMichael Chan __le16 num_vfs; 1421c0c050c5SMichael Chan }; 1422c0c050c5SMichael Chan 1423894aa69aSMichael Chan /* hwrm_func_vf_free_output (size:128b/16B) */ 1424c0c050c5SMichael Chan struct hwrm_func_vf_free_output { 1425c0c050c5SMichael Chan __le16 error_code; 1426c0c050c5SMichael Chan __le16 req_type; 1427c0c050c5SMichael Chan __le16 seq_id; 1428c0c050c5SMichael Chan __le16 resp_len; 1429894aa69aSMichael Chan u8 unused_0[7]; 1430c0c050c5SMichael Chan u8 valid; 1431c0c050c5SMichael Chan }; 1432c0c050c5SMichael Chan 1433894aa69aSMichael Chan /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1434c0c050c5SMichael Chan struct hwrm_func_vf_cfg_input { 1435c0c050c5SMichael Chan __le16 req_type; 1436c0c050c5SMichael Chan __le16 cmpl_ring; 1437c0c050c5SMichael Chan __le16 seq_id; 1438c0c050c5SMichael Chan __le16 target_id; 1439c0c050c5SMichael Chan __le64 resp_addr; 1440c0c050c5SMichael Chan __le32 enables; 1441c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1442c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1443c193554eSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 144411f15ed3SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1445894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1446894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1447894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1448894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1449894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1450894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1451894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1452894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1453fbfee257SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS 0x1000UL 1454fbfee257SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS 0x2000UL 1455c0c050c5SMichael Chan __le16 mtu; 1456c0c050c5SMichael Chan __le16 guest_vlan; 1457c193554eSMichael Chan __le16 async_event_cr; 145811f15ed3SMichael Chan u8 dflt_mac_addr[6]; 1459894aa69aSMichael Chan __le32 flags; 1460894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1461894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1462894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1463894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1464894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1465894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1466894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1467894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1468bfc6e5fbSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1469bfc6e5fbSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1470894aa69aSMichael Chan __le16 num_rsscos_ctxs; 1471894aa69aSMichael Chan __le16 num_cmpl_rings; 1472894aa69aSMichael Chan __le16 num_tx_rings; 1473894aa69aSMichael Chan __le16 num_rx_rings; 1474894aa69aSMichael Chan __le16 num_l2_ctxs; 1475894aa69aSMichael Chan __le16 num_vnics; 1476894aa69aSMichael Chan __le16 num_stat_ctxs; 1477894aa69aSMichael Chan __le16 num_hw_ring_grps; 1478fbfee257SMichael Chan __le16 num_tx_key_ctxs; 1479fbfee257SMichael Chan __le16 num_rx_key_ctxs; 1480c0c050c5SMichael Chan }; 1481c0c050c5SMichael Chan 1482894aa69aSMichael Chan /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1483c0c050c5SMichael Chan struct hwrm_func_vf_cfg_output { 1484c0c050c5SMichael Chan __le16 error_code; 1485c0c050c5SMichael Chan __le16 req_type; 1486c0c050c5SMichael Chan __le16 seq_id; 1487c0c050c5SMichael Chan __le16 resp_len; 1488894aa69aSMichael Chan u8 unused_0[7]; 1489c0c050c5SMichael Chan u8 valid; 1490c0c050c5SMichael Chan }; 1491c0c050c5SMichael Chan 1492894aa69aSMichael Chan /* hwrm_func_qcaps_input (size:192b/24B) */ 1493c0c050c5SMichael Chan struct hwrm_func_qcaps_input { 1494c0c050c5SMichael Chan __le16 req_type; 1495c0c050c5SMichael Chan __le16 cmpl_ring; 1496c0c050c5SMichael Chan __le16 seq_id; 1497c0c050c5SMichael Chan __le16 target_id; 1498c0c050c5SMichael Chan __le64 resp_addr; 1499c0c050c5SMichael Chan __le16 fid; 1500894aa69aSMichael Chan u8 unused_0[6]; 1501c0c050c5SMichael Chan }; 1502c0c050c5SMichael Chan 1503fbfee257SMichael Chan /* hwrm_func_qcaps_output (size:768b/96B) */ 1504c0c050c5SMichael Chan struct hwrm_func_qcaps_output { 1505c0c050c5SMichael Chan __le16 error_code; 1506c0c050c5SMichael Chan __le16 req_type; 1507c0c050c5SMichael Chan __le16 seq_id; 1508c0c050c5SMichael Chan __le16 resp_len; 1509c0c050c5SMichael Chan __le16 fid; 1510c0c050c5SMichael Chan __le16 port_id; 1511c0c050c5SMichael Chan __le32 flags; 1512c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1513c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 151411f15ed3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1515a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1516a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1517a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1518a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1519441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1520441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1521441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1522441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 152387c374deSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1524894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1525894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1526894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1527894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1528d4f52de0SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 15296fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 15306fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 15316fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 153231d357c0SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 15333322479eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 15343322479eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 15353293ec23SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 15364a50ddc2SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 153772e0c9f9SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 153872e0c9f9SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 153941136ab3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1540460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1541460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1542460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1543460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 154411f15ed3SMichael Chan u8 mac_address[6]; 1545c0c050c5SMichael Chan __le16 max_rsscos_ctx; 1546c0c050c5SMichael Chan __le16 max_cmpl_rings; 1547c0c050c5SMichael Chan __le16 max_tx_rings; 1548c0c050c5SMichael Chan __le16 max_rx_rings; 1549c0c050c5SMichael Chan __le16 max_l2_ctxs; 1550c0c050c5SMichael Chan __le16 max_vnics; 1551c0c050c5SMichael Chan __le16 first_vf_id; 1552c0c050c5SMichael Chan __le16 max_vfs; 1553c0c050c5SMichael Chan __le16 max_stat_ctx; 1554c0c050c5SMichael Chan __le32 max_encap_records; 1555c0c050c5SMichael Chan __le32 max_decap_records; 1556c0c050c5SMichael Chan __le32 max_tx_em_flows; 1557c0c050c5SMichael Chan __le32 max_tx_wm_flows; 1558c0c050c5SMichael Chan __le32 max_rx_em_flows; 1559c0c050c5SMichael Chan __le32 max_rx_wm_flows; 1560c0c050c5SMichael Chan __le32 max_mcast_filters; 1561c0c050c5SMichael Chan __le32 max_flow_id; 1562c0c050c5SMichael Chan __le32 max_hw_ring_grps; 1563441cabbbSMichael Chan __le16 max_sp_tx_rings; 156478eeadb8SMichael Chan __le16 max_msix_vfs; 1565460c2577SMichael Chan __le32 flags_ext; 1566460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1567460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1568460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1569bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1570bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1571bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1572bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1573bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 157416db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 157516db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 157616db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 157716db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 157831f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 157931f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 158031f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 158131f67c2eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 158278eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 158378eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 158478eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 158578eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 158678eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 158778eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 158878eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 158978eeadb8SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1590*21e70778SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1591*21e70778SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1592bfc6e5fbSMichael Chan u8 max_schqs; 15939d6b648cSMichael Chan u8 mpc_chnls_cap; 15949d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 15959d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 15969d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 15979d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 15989d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1599fbfee257SMichael Chan __le16 max_key_ctxs_alloc; 1600fbfee257SMichael Chan u8 unused_1[7]; 1601c0c050c5SMichael Chan u8 valid; 1602c0c050c5SMichael Chan }; 1603c0c050c5SMichael Chan 1604894aa69aSMichael Chan /* hwrm_func_qcfg_input (size:192b/24B) */ 160511f15ed3SMichael Chan struct hwrm_func_qcfg_input { 160611f15ed3SMichael Chan __le16 req_type; 160711f15ed3SMichael Chan __le16 cmpl_ring; 160811f15ed3SMichael Chan __le16 seq_id; 160911f15ed3SMichael Chan __le16 target_id; 161011f15ed3SMichael Chan __le64 resp_addr; 161111f15ed3SMichael Chan __le16 fid; 1612894aa69aSMichael Chan u8 unused_0[6]; 161311f15ed3SMichael Chan }; 161411f15ed3SMichael Chan 1615fbfee257SMichael Chan /* hwrm_func_qcfg_output (size:896b/112B) */ 161611f15ed3SMichael Chan struct hwrm_func_qcfg_output { 161711f15ed3SMichael Chan __le16 error_code; 161811f15ed3SMichael Chan __le16 req_type; 161911f15ed3SMichael Chan __le16 seq_id; 162011f15ed3SMichael Chan __le16 resp_len; 162111f15ed3SMichael Chan __le16 fid; 162211f15ed3SMichael Chan __le16 port_id; 162311f15ed3SMichael Chan __le16 vlan; 1624a58a3e68SMichael Chan __le16 flags; 1625a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1626a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1627441cabbbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 162887c374deSMichael Chan #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 16298eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 16308eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 163131d357c0SMichael Chan #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 16323322479eSMichael Chan #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 16332792b5b9SMichael Chan #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1634bfc6e5fbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1635bfc6e5fbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 16369d6b648cSMichael Chan #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 163716db6323SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 163831f67c2eSMichael Chan #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 163978eeadb8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 164011f15ed3SMichael Chan u8 mac_address[6]; 164111f15ed3SMichael Chan __le16 pci_id; 164211f15ed3SMichael Chan __le16 alloc_rsscos_ctx; 164311f15ed3SMichael Chan __le16 alloc_cmpl_rings; 164411f15ed3SMichael Chan __le16 alloc_tx_rings; 164511f15ed3SMichael Chan __le16 alloc_rx_rings; 164611f15ed3SMichael Chan __le16 alloc_l2_ctx; 164711f15ed3SMichael Chan __le16 alloc_vnics; 164878eeadb8SMichael Chan __le16 admin_mtu; 164911f15ed3SMichael Chan __le16 mru; 165011f15ed3SMichael Chan __le16 stat_ctx_id; 165111f15ed3SMichael Chan u8 port_partition_type; 1652441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1653441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1654441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1655441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1656441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 165778eeadb8SMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1658441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1659894aa69aSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 16608eb992e8SMichael Chan u8 port_pf_cnt; 16618eb992e8SMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1662894aa69aSMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 166311f15ed3SMichael Chan __le16 dflt_vnic_id; 166457922b0aSMichael Chan __le16 max_mtu_configured; 166511f15ed3SMichael Chan __le32 min_bw; 1666441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1667441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1668bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1669bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1670bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1671bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1672441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1673441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1674bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1675bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1676bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1677bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1678441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1679441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1680441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 168111f15ed3SMichael Chan __le32 max_bw; 1682441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1683441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1684bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1685bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1686bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1687bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1688441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1689441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1690bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1691bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1692bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1693bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1694441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1695441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1696441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 169711f15ed3SMichael Chan u8 evb_mode; 1698441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1699441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1700441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1701894aa69aSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1702d4f52de0SMichael Chan u8 options; 1703d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1704d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1705d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1706d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1707d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 17086fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 17096fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 17106fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 17116fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 17126fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 17136fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 17146fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 17156fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1716441cabbbSMichael Chan __le16 alloc_vfs; 171711f15ed3SMichael Chan __le32 alloc_mcast_filters; 171811f15ed3SMichael Chan __le32 alloc_hw_ring_grps; 1719441cabbbSMichael Chan __le16 alloc_sp_tx_rings; 1720894aa69aSMichael Chan __le16 alloc_stat_ctx; 17216fc92c33SMichael Chan __le16 alloc_msix; 17223322479eSMichael Chan __le16 registered_vfs; 172372e0c9f9SMichael Chan __le16 l2_doorbell_bar_size_kb; 172472e0c9f9SMichael Chan u8 unused_1; 17253322479eSMichael Chan u8 always_1; 17263322479eSMichael Chan __le32 reset_addr_poll; 172741136ab3SMichael Chan __le16 legacy_l2_db_size_kb; 1728460c2577SMichael Chan __le16 svif_info; 1729460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1730460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1731460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 17329d6b648cSMichael Chan u8 mpc_chnls; 17339d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 17349d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 17359d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 17369d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 17379d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 173878eeadb8SMichael Chan u8 unused_2[3]; 173978eeadb8SMichael Chan __le32 partition_min_bw; 174078eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 174178eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 174278eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 174378eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 174478eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 174578eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 174678eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 174778eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 174878eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 174978eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 175078eeadb8SMichael Chan __le32 partition_max_bw; 175178eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 175278eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 175378eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 175478eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 175578eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 175678eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 175778eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 175878eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 175978eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 176078eeadb8SMichael Chan #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 176178eeadb8SMichael Chan __le16 host_mtu; 1762fbfee257SMichael Chan __le16 alloc_tx_key_ctxs; 1763fbfee257SMichael Chan __le16 alloc_rx_key_ctxs; 1764fbfee257SMichael Chan u8 unused_3[5]; 176511f15ed3SMichael Chan u8 valid; 176611f15ed3SMichael Chan }; 176711f15ed3SMichael Chan 1768fbfee257SMichael Chan /* hwrm_func_cfg_input (size:896b/112B) */ 1769c0c050c5SMichael Chan struct hwrm_func_cfg_input { 1770c0c050c5SMichael Chan __le16 req_type; 1771c0c050c5SMichael Chan __le16 cmpl_ring; 1772c0c050c5SMichael Chan __le16 seq_id; 1773c0c050c5SMichael Chan __le16 target_id; 1774c0c050c5SMichael Chan __le64 resp_addr; 1775c193554eSMichael Chan __le16 fid; 17766fc92c33SMichael Chan __le16 num_msix; 1777c0c050c5SMichael Chan __le32 flags; 17788eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 17798eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 17808eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 17818eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 17828eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 17838eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 17848eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1785acb20054SMichael Chan #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 17866a17eb27SMichael Chan #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1787894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1788894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1789894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1790894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1791894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1792894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1793894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 179431d357c0SMichael Chan #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 17953322479eSMichael Chan #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 17960b815023SMichael Chan #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 17973293ec23SMichael Chan #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 17982792b5b9SMichael Chan #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1799bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1800bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1801bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 180231f67c2eSMichael Chan #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 180331f67c2eSMichael Chan #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 1804c0c050c5SMichael Chan __le32 enables; 180578eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 1806c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1807c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1808c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1809c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1810c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1811c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1812c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1813c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1814c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1815c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1816c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1817c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1818c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1819c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1820c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1821c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1822c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1823c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1824c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1825894aa69aSMichael Chan #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 18266fc92c33SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 18276fc92c33SMichael Chan #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1828bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1829bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 18309d6b648cSMichael Chan #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 183178eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 183278eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 183378eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 183478eeadb8SMichael Chan #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 1835fbfee257SMichael Chan #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS 0x40000000UL 1836fbfee257SMichael Chan #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS 0x80000000UL 183778eeadb8SMichael Chan __le16 admin_mtu; 1838c0c050c5SMichael Chan __le16 mru; 1839c0c050c5SMichael Chan __le16 num_rsscos_ctxs; 1840c0c050c5SMichael Chan __le16 num_cmpl_rings; 1841c0c050c5SMichael Chan __le16 num_tx_rings; 1842c0c050c5SMichael Chan __le16 num_rx_rings; 1843c0c050c5SMichael Chan __le16 num_l2_ctxs; 1844c0c050c5SMichael Chan __le16 num_vnics; 1845c0c050c5SMichael Chan __le16 num_stat_ctxs; 1846c0c050c5SMichael Chan __le16 num_hw_ring_grps; 1847c0c050c5SMichael Chan u8 dflt_mac_addr[6]; 1848c0c050c5SMichael Chan __le16 dflt_vlan; 1849c0c050c5SMichael Chan __be32 dflt_ip_addr[4]; 1850c0c050c5SMichael Chan __le32 min_bw; 1851441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1852441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1853bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1854bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1855bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1856bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1857441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1858441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1859bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1860bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1861bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1862bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1863441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1864441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1865441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1866c0c050c5SMichael Chan __le32 max_bw; 1867441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1868441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1869bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1870bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1871bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1872bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1873441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1874441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1875bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1876bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1877bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1878bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1879441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1880441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1881441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1882c0c050c5SMichael Chan __le16 async_event_cr; 1883c0c050c5SMichael Chan u8 vlan_antispoof_mode; 1884441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1885441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1886441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1887441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1888894aa69aSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1889c0c050c5SMichael Chan u8 allowed_vlan_pris; 1890c0c050c5SMichael Chan u8 evb_mode; 1891441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1892441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1893441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1894894aa69aSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1895d4f52de0SMichael Chan u8 options; 1896d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1897d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1898d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1899d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1900d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 19016fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 19026fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 19036fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 19046fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 19056fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 19066fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 19076fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 19086fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1909c0c050c5SMichael Chan __le16 num_mcast_filters; 1910bfc6e5fbSMichael Chan __le16 schq_id; 19119d6b648cSMichael Chan __le16 mpc_chnls; 19129d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 19139d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 19149d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 19159d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 19169d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 19179d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 19189d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 19199d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 19209d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 19219d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 192278eeadb8SMichael Chan __le32 partition_min_bw; 192378eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 192478eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 192578eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 192678eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 192778eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 192878eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 192978eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 193078eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 193178eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 193278eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 193378eeadb8SMichael Chan __le32 partition_max_bw; 193478eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 193578eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 193678eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 193778eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 193878eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 193978eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 194078eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 194178eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 194278eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 194378eeadb8SMichael Chan #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 194478eeadb8SMichael Chan __be16 tpid; 194578eeadb8SMichael Chan __le16 host_mtu; 1946fbfee257SMichael Chan __le16 num_tx_key_ctxs; 1947fbfee257SMichael Chan __le16 num_rx_key_ctxs; 1948fbfee257SMichael Chan u8 unused_0[4]; 1949c0c050c5SMichael Chan }; 1950c0c050c5SMichael Chan 1951894aa69aSMichael Chan /* hwrm_func_cfg_output (size:128b/16B) */ 1952c0c050c5SMichael Chan struct hwrm_func_cfg_output { 1953c0c050c5SMichael Chan __le16 error_code; 1954c0c050c5SMichael Chan __le16 req_type; 1955c0c050c5SMichael Chan __le16 seq_id; 1956c0c050c5SMichael Chan __le16 resp_len; 1957894aa69aSMichael Chan u8 unused_0[7]; 1958c0c050c5SMichael Chan u8 valid; 1959c0c050c5SMichael Chan }; 1960c0c050c5SMichael Chan 1961*21e70778SMichael Chan /* hwrm_func_cfg_cmd_err (size:64b/8B) */ 1962*21e70778SMichael Chan struct hwrm_func_cfg_cmd_err { 1963*21e70778SMichael Chan u8 code; 1964*21e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 1965*21e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_RANGE 0x1UL 1966*21e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_MORE_THAN_MAX 0x2UL 1967*21e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_MIN_BW_UNSUPPORTED 0x3UL 1968*21e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 0x4UL 1969*21e70778SMichael Chan #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_PERCENT 1970*21e70778SMichael Chan u8 unused_0[7]; 1971*21e70778SMichael Chan }; 1972*21e70778SMichael Chan 1973894aa69aSMichael Chan /* hwrm_func_qstats_input (size:192b/24B) */ 1974c0c050c5SMichael Chan struct hwrm_func_qstats_input { 1975c0c050c5SMichael Chan __le16 req_type; 1976c0c050c5SMichael Chan __le16 cmpl_ring; 1977c0c050c5SMichael Chan __le16 seq_id; 1978c0c050c5SMichael Chan __le16 target_id; 1979c0c050c5SMichael Chan __le64 resp_addr; 1980c0c050c5SMichael Chan __le16 fid; 198172e0c9f9SMichael Chan u8 flags; 198272e0c9f9SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 198372e0c9f9SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1984460c2577SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1985460c2577SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 198672e0c9f9SMichael Chan u8 unused_0[5]; 1987c0c050c5SMichael Chan }; 1988c0c050c5SMichael Chan 1989894aa69aSMichael Chan /* hwrm_func_qstats_output (size:1408b/176B) */ 1990c0c050c5SMichael Chan struct hwrm_func_qstats_output { 1991c0c050c5SMichael Chan __le16 error_code; 1992c0c050c5SMichael Chan __le16 req_type; 1993c0c050c5SMichael Chan __le16 seq_id; 1994c0c050c5SMichael Chan __le16 resp_len; 1995c0c050c5SMichael Chan __le64 tx_ucast_pkts; 1996c0c050c5SMichael Chan __le64 tx_mcast_pkts; 1997c0c050c5SMichael Chan __le64 tx_bcast_pkts; 19988eb992e8SMichael Chan __le64 tx_discard_pkts; 1999c0c050c5SMichael Chan __le64 tx_drop_pkts; 2000c0c050c5SMichael Chan __le64 tx_ucast_bytes; 2001c0c050c5SMichael Chan __le64 tx_mcast_bytes; 2002c0c050c5SMichael Chan __le64 tx_bcast_bytes; 2003c0c050c5SMichael Chan __le64 rx_ucast_pkts; 2004c0c050c5SMichael Chan __le64 rx_mcast_pkts; 2005c0c050c5SMichael Chan __le64 rx_bcast_pkts; 20068eb992e8SMichael Chan __le64 rx_discard_pkts; 2007c0c050c5SMichael Chan __le64 rx_drop_pkts; 2008c0c050c5SMichael Chan __le64 rx_ucast_bytes; 2009c0c050c5SMichael Chan __le64 rx_mcast_bytes; 2010c0c050c5SMichael Chan __le64 rx_bcast_bytes; 2011c0c050c5SMichael Chan __le64 rx_agg_pkts; 2012c0c050c5SMichael Chan __le64 rx_agg_bytes; 2013c0c050c5SMichael Chan __le64 rx_agg_events; 2014c0c050c5SMichael Chan __le64 rx_agg_aborts; 2015894aa69aSMichael Chan u8 unused_0[7]; 2016c0c050c5SMichael Chan u8 valid; 2017c0c050c5SMichael Chan }; 2018c0c050c5SMichael Chan 2019bfc6e5fbSMichael Chan /* hwrm_func_qstats_ext_input (size:256b/32B) */ 2020460c2577SMichael Chan struct hwrm_func_qstats_ext_input { 2021460c2577SMichael Chan __le16 req_type; 2022460c2577SMichael Chan __le16 cmpl_ring; 2023460c2577SMichael Chan __le16 seq_id; 2024460c2577SMichael Chan __le16 target_id; 2025460c2577SMichael Chan __le64 resp_addr; 2026460c2577SMichael Chan __le16 fid; 2027460c2577SMichael Chan u8 flags; 2028460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 2029460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2030460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2031460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 2032bfc6e5fbSMichael Chan u8 unused_0[1]; 2033bfc6e5fbSMichael Chan __le32 enables; 2034bfc6e5fbSMichael Chan #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2035bfc6e5fbSMichael Chan __le16 schq_id; 2036bfc6e5fbSMichael Chan __le16 traffic_class; 2037bfc6e5fbSMichael Chan u8 unused_1[4]; 2038460c2577SMichael Chan }; 2039460c2577SMichael Chan 20409d6b648cSMichael Chan /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2041460c2577SMichael Chan struct hwrm_func_qstats_ext_output { 2042460c2577SMichael Chan __le16 error_code; 2043460c2577SMichael Chan __le16 req_type; 2044460c2577SMichael Chan __le16 seq_id; 2045460c2577SMichael Chan __le16 resp_len; 2046460c2577SMichael Chan __le64 rx_ucast_pkts; 2047460c2577SMichael Chan __le64 rx_mcast_pkts; 2048460c2577SMichael Chan __le64 rx_bcast_pkts; 2049460c2577SMichael Chan __le64 rx_discard_pkts; 2050bfc6e5fbSMichael Chan __le64 rx_error_pkts; 2051460c2577SMichael Chan __le64 rx_ucast_bytes; 2052460c2577SMichael Chan __le64 rx_mcast_bytes; 2053460c2577SMichael Chan __le64 rx_bcast_bytes; 2054460c2577SMichael Chan __le64 tx_ucast_pkts; 2055460c2577SMichael Chan __le64 tx_mcast_pkts; 2056460c2577SMichael Chan __le64 tx_bcast_pkts; 2057bfc6e5fbSMichael Chan __le64 tx_error_pkts; 2058460c2577SMichael Chan __le64 tx_discard_pkts; 2059460c2577SMichael Chan __le64 tx_ucast_bytes; 2060460c2577SMichael Chan __le64 tx_mcast_bytes; 2061460c2577SMichael Chan __le64 tx_bcast_bytes; 2062460c2577SMichael Chan __le64 rx_tpa_eligible_pkt; 2063460c2577SMichael Chan __le64 rx_tpa_eligible_bytes; 2064460c2577SMichael Chan __le64 rx_tpa_pkt; 2065460c2577SMichael Chan __le64 rx_tpa_bytes; 2066460c2577SMichael Chan __le64 rx_tpa_errors; 20679d6b648cSMichael Chan __le64 rx_tpa_events; 2068460c2577SMichael Chan u8 unused_0[7]; 2069460c2577SMichael Chan u8 valid; 2070460c2577SMichael Chan }; 2071460c2577SMichael Chan 2072894aa69aSMichael Chan /* hwrm_func_clr_stats_input (size:192b/24B) */ 2073c0c050c5SMichael Chan struct hwrm_func_clr_stats_input { 2074c0c050c5SMichael Chan __le16 req_type; 2075c0c050c5SMichael Chan __le16 cmpl_ring; 2076c0c050c5SMichael Chan __le16 seq_id; 2077c0c050c5SMichael Chan __le16 target_id; 2078c0c050c5SMichael Chan __le64 resp_addr; 2079c0c050c5SMichael Chan __le16 fid; 2080894aa69aSMichael Chan u8 unused_0[6]; 2081c0c050c5SMichael Chan }; 2082c0c050c5SMichael Chan 2083894aa69aSMichael Chan /* hwrm_func_clr_stats_output (size:128b/16B) */ 2084c0c050c5SMichael Chan struct hwrm_func_clr_stats_output { 2085c0c050c5SMichael Chan __le16 error_code; 2086c0c050c5SMichael Chan __le16 req_type; 2087c0c050c5SMichael Chan __le16 seq_id; 2088c0c050c5SMichael Chan __le16 resp_len; 2089894aa69aSMichael Chan u8 unused_0[7]; 2090c0c050c5SMichael Chan u8 valid; 2091c0c050c5SMichael Chan }; 2092c0c050c5SMichael Chan 2093894aa69aSMichael Chan /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2094c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_input { 2095c0c050c5SMichael Chan __le16 req_type; 2096c0c050c5SMichael Chan __le16 cmpl_ring; 2097c0c050c5SMichael Chan __le16 seq_id; 2098c0c050c5SMichael Chan __le16 target_id; 2099c0c050c5SMichael Chan __le64 resp_addr; 2100c0c050c5SMichael Chan __le16 vf_id; 2101894aa69aSMichael Chan u8 unused_0[6]; 2102c0c050c5SMichael Chan }; 2103c0c050c5SMichael Chan 2104894aa69aSMichael Chan /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2105c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_output { 2106c0c050c5SMichael Chan __le16 error_code; 2107c0c050c5SMichael Chan __le16 req_type; 2108c0c050c5SMichael Chan __le16 seq_id; 2109c0c050c5SMichael Chan __le16 resp_len; 2110894aa69aSMichael Chan u8 unused_0[7]; 2111c0c050c5SMichael Chan u8 valid; 2112c0c050c5SMichael Chan }; 2113c0c050c5SMichael Chan 2114d4f52de0SMichael Chan /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2115c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_input { 2116c0c050c5SMichael Chan __le16 req_type; 2117c0c050c5SMichael Chan __le16 cmpl_ring; 2118c0c050c5SMichael Chan __le16 seq_id; 2119c0c050c5SMichael Chan __le16 target_id; 2120c0c050c5SMichael Chan __le64 resp_addr; 2121c0c050c5SMichael Chan __le32 flags; 2122c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2123c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2124d4f52de0SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 212531d357c0SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 21263322479eSMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 21273293ec23SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 212841136ab3SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 212916db6323SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 213078eeadb8SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2131fbfee257SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2132c0c050c5SMichael Chan __le32 enables; 2133c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2134c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2135c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2136c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2137c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2138c0c050c5SMichael Chan __le16 os_type; 2139441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2140441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2141441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2142441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2143441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2144441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2145441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2146441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2147441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2148441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 214916d663a6SMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2150894aa69aSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2151d4f52de0SMichael Chan u8 ver_maj_8b; 2152d4f52de0SMichael Chan u8 ver_min_8b; 2153d4f52de0SMichael Chan u8 ver_upd_8b; 2154894aa69aSMichael Chan u8 unused_0[3]; 2155c0c050c5SMichael Chan __le32 timestamp; 2156894aa69aSMichael Chan u8 unused_1[4]; 2157c0c050c5SMichael Chan __le32 vf_req_fwd[8]; 2158c0c050c5SMichael Chan __le32 async_event_fwd[8]; 2159d4f52de0SMichael Chan __le16 ver_maj; 2160d4f52de0SMichael Chan __le16 ver_min; 2161d4f52de0SMichael Chan __le16 ver_upd; 2162d4f52de0SMichael Chan __le16 ver_patch; 2163c0c050c5SMichael Chan }; 2164c0c050c5SMichael Chan 2165894aa69aSMichael Chan /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2166c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_output { 2167c0c050c5SMichael Chan __le16 error_code; 2168c0c050c5SMichael Chan __le16 req_type; 2169c0c050c5SMichael Chan __le16 seq_id; 2170c0c050c5SMichael Chan __le16 resp_len; 21716fc92c33SMichael Chan __le32 flags; 21726fc92c33SMichael Chan #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 21736fc92c33SMichael Chan u8 unused_0[3]; 2174c0c050c5SMichael Chan u8 valid; 2175c0c050c5SMichael Chan }; 2176c0c050c5SMichael Chan 2177894aa69aSMichael Chan /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2178c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_input { 2179c0c050c5SMichael Chan __le16 req_type; 2180c0c050c5SMichael Chan __le16 cmpl_ring; 2181c0c050c5SMichael Chan __le16 seq_id; 2182c0c050c5SMichael Chan __le16 target_id; 2183c0c050c5SMichael Chan __le64 resp_addr; 2184c0c050c5SMichael Chan __le32 flags; 2185c0c050c5SMichael Chan #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2186894aa69aSMichael Chan u8 unused_0[4]; 2187c0c050c5SMichael Chan }; 2188c0c050c5SMichael Chan 2189894aa69aSMichael Chan /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2190c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_output { 2191c0c050c5SMichael Chan __le16 error_code; 2192c0c050c5SMichael Chan __le16 req_type; 2193c0c050c5SMichael Chan __le16 seq_id; 2194c0c050c5SMichael Chan __le16 resp_len; 2195894aa69aSMichael Chan u8 unused_0[7]; 2196c0c050c5SMichael Chan u8 valid; 2197c0c050c5SMichael Chan }; 2198c0c050c5SMichael Chan 2199894aa69aSMichael Chan /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2200c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_input { 2201c0c050c5SMichael Chan __le16 req_type; 2202c0c050c5SMichael Chan __le16 cmpl_ring; 2203c0c050c5SMichael Chan __le16 seq_id; 2204c0c050c5SMichael Chan __le16 target_id; 2205c0c050c5SMichael Chan __le64 resp_addr; 2206c0c050c5SMichael Chan __le32 enables; 2207c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2208c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2209c0c050c5SMichael Chan __le16 vf_id; 2210c0c050c5SMichael Chan __le16 req_buf_num_pages; 2211c0c050c5SMichael Chan __le16 req_buf_page_size; 2212441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2213441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2214441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2215441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2216441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2217441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2218441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2219894aa69aSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2220c0c050c5SMichael Chan __le16 req_buf_len; 2221c0c050c5SMichael Chan __le16 resp_buf_len; 2222894aa69aSMichael Chan u8 unused_0[2]; 2223c0c050c5SMichael Chan __le64 req_buf_page_addr0; 2224c0c050c5SMichael Chan __le64 req_buf_page_addr1; 2225c0c050c5SMichael Chan __le64 req_buf_page_addr2; 2226c0c050c5SMichael Chan __le64 req_buf_page_addr3; 2227c0c050c5SMichael Chan __le64 req_buf_page_addr4; 2228c0c050c5SMichael Chan __le64 req_buf_page_addr5; 2229c0c050c5SMichael Chan __le64 req_buf_page_addr6; 2230c0c050c5SMichael Chan __le64 req_buf_page_addr7; 2231c0c050c5SMichael Chan __le64 req_buf_page_addr8; 2232c0c050c5SMichael Chan __le64 req_buf_page_addr9; 2233c0c050c5SMichael Chan __le64 error_buf_addr; 2234c0c050c5SMichael Chan __le64 resp_buf_addr; 2235c0c050c5SMichael Chan }; 2236c0c050c5SMichael Chan 2237894aa69aSMichael Chan /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2238c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_output { 2239c0c050c5SMichael Chan __le16 error_code; 2240c0c050c5SMichael Chan __le16 req_type; 2241c0c050c5SMichael Chan __le16 seq_id; 2242c0c050c5SMichael Chan __le16 resp_len; 2243894aa69aSMichael Chan u8 unused_0[7]; 2244c0c050c5SMichael Chan u8 valid; 2245c0c050c5SMichael Chan }; 2246c0c050c5SMichael Chan 2247894aa69aSMichael Chan /* hwrm_func_drv_qver_input (size:192b/24B) */ 2248c0c050c5SMichael Chan struct hwrm_func_drv_qver_input { 2249c0c050c5SMichael Chan __le16 req_type; 2250c0c050c5SMichael Chan __le16 cmpl_ring; 2251c0c050c5SMichael Chan __le16 seq_id; 2252c0c050c5SMichael Chan __le16 target_id; 2253c0c050c5SMichael Chan __le64 resp_addr; 2254c193554eSMichael Chan __le32 reserved; 2255c0c050c5SMichael Chan __le16 fid; 2256894aa69aSMichael Chan u8 unused_0[2]; 2257c0c050c5SMichael Chan }; 2258c0c050c5SMichael Chan 22596fc92c33SMichael Chan /* hwrm_func_drv_qver_output (size:256b/32B) */ 2260c0c050c5SMichael Chan struct hwrm_func_drv_qver_output { 2261c0c050c5SMichael Chan __le16 error_code; 2262c0c050c5SMichael Chan __le16 req_type; 2263c0c050c5SMichael Chan __le16 seq_id; 2264c0c050c5SMichael Chan __le16 resp_len; 2265c0c050c5SMichael Chan __le16 os_type; 2266441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2267441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2268441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2269441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2270441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2271441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2272441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2273441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2274441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2275441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 227687c374deSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2277894aa69aSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2278d4f52de0SMichael Chan u8 ver_maj_8b; 2279d4f52de0SMichael Chan u8 ver_min_8b; 2280d4f52de0SMichael Chan u8 ver_upd_8b; 22816fc92c33SMichael Chan u8 unused_0[3]; 2282d4f52de0SMichael Chan __le16 ver_maj; 2283d4f52de0SMichael Chan __le16 ver_min; 2284d4f52de0SMichael Chan __le16 ver_upd; 2285d4f52de0SMichael Chan __le16 ver_patch; 22866fc92c33SMichael Chan u8 unused_1[7]; 22876fc92c33SMichael Chan u8 valid; 2288c0c050c5SMichael Chan }; 2289c0c050c5SMichael Chan 2290894aa69aSMichael Chan /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2291894aa69aSMichael Chan struct hwrm_func_resource_qcaps_input { 2292894aa69aSMichael Chan __le16 req_type; 2293894aa69aSMichael Chan __le16 cmpl_ring; 2294894aa69aSMichael Chan __le16 seq_id; 2295894aa69aSMichael Chan __le16 target_id; 2296894aa69aSMichael Chan __le64 resp_addr; 2297894aa69aSMichael Chan __le16 fid; 2298894aa69aSMichael Chan u8 unused_0[6]; 2299894aa69aSMichael Chan }; 2300894aa69aSMichael Chan 2301fbfee257SMichael Chan /* hwrm_func_resource_qcaps_output (size:512b/64B) */ 2302894aa69aSMichael Chan struct hwrm_func_resource_qcaps_output { 2303894aa69aSMichael Chan __le16 error_code; 2304894aa69aSMichael Chan __le16 req_type; 2305894aa69aSMichael Chan __le16 seq_id; 2306894aa69aSMichael Chan __le16 resp_len; 2307894aa69aSMichael Chan __le16 max_vfs; 2308894aa69aSMichael Chan __le16 max_msix; 2309894aa69aSMichael Chan __le16 vf_reservation_strategy; 2310894aa69aSMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2311894aa69aSMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2312d4f52de0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2313d4f52de0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2314894aa69aSMichael Chan __le16 min_rsscos_ctx; 2315894aa69aSMichael Chan __le16 max_rsscos_ctx; 2316894aa69aSMichael Chan __le16 min_cmpl_rings; 2317894aa69aSMichael Chan __le16 max_cmpl_rings; 2318894aa69aSMichael Chan __le16 min_tx_rings; 2319894aa69aSMichael Chan __le16 max_tx_rings; 2320894aa69aSMichael Chan __le16 min_rx_rings; 2321894aa69aSMichael Chan __le16 max_rx_rings; 2322894aa69aSMichael Chan __le16 min_l2_ctxs; 2323894aa69aSMichael Chan __le16 max_l2_ctxs; 2324894aa69aSMichael Chan __le16 min_vnics; 2325894aa69aSMichael Chan __le16 max_vnics; 2326894aa69aSMichael Chan __le16 min_stat_ctx; 2327894aa69aSMichael Chan __le16 max_stat_ctx; 2328894aa69aSMichael Chan __le16 min_hw_ring_grps; 2329894aa69aSMichael Chan __le16 max_hw_ring_grps; 2330d4f52de0SMichael Chan __le16 max_tx_scheduler_inputs; 233131d357c0SMichael Chan __le16 flags; 233231d357c0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2333fbfee257SMichael Chan __le16 min_tx_key_ctxs; 2334fbfee257SMichael Chan __le16 max_tx_key_ctxs; 2335fbfee257SMichael Chan __le16 min_rx_key_ctxs; 2336fbfee257SMichael Chan __le16 max_rx_key_ctxs; 233731d357c0SMichael Chan u8 unused_0[5]; 2338894aa69aSMichael Chan u8 valid; 2339894aa69aSMichael Chan }; 2340894aa69aSMichael Chan 2341fbfee257SMichael Chan /* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ 2342894aa69aSMichael Chan struct hwrm_func_vf_resource_cfg_input { 2343894aa69aSMichael Chan __le16 req_type; 2344894aa69aSMichael Chan __le16 cmpl_ring; 2345894aa69aSMichael Chan __le16 seq_id; 2346894aa69aSMichael Chan __le16 target_id; 2347894aa69aSMichael Chan __le64 resp_addr; 2348894aa69aSMichael Chan __le16 vf_id; 2349894aa69aSMichael Chan __le16 max_msix; 2350894aa69aSMichael Chan __le16 min_rsscos_ctx; 2351894aa69aSMichael Chan __le16 max_rsscos_ctx; 2352894aa69aSMichael Chan __le16 min_cmpl_rings; 2353894aa69aSMichael Chan __le16 max_cmpl_rings; 2354894aa69aSMichael Chan __le16 min_tx_rings; 2355894aa69aSMichael Chan __le16 max_tx_rings; 2356894aa69aSMichael Chan __le16 min_rx_rings; 2357894aa69aSMichael Chan __le16 max_rx_rings; 2358894aa69aSMichael Chan __le16 min_l2_ctxs; 2359894aa69aSMichael Chan __le16 max_l2_ctxs; 2360894aa69aSMichael Chan __le16 min_vnics; 2361894aa69aSMichael Chan __le16 max_vnics; 2362894aa69aSMichael Chan __le16 min_stat_ctx; 2363894aa69aSMichael Chan __le16 max_stat_ctx; 2364894aa69aSMichael Chan __le16 min_hw_ring_grps; 2365894aa69aSMichael Chan __le16 max_hw_ring_grps; 236631d357c0SMichael Chan __le16 flags; 236731d357c0SMichael Chan #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2368fbfee257SMichael Chan __le16 min_tx_key_ctxs; 2369fbfee257SMichael Chan __le16 max_tx_key_ctxs; 2370fbfee257SMichael Chan __le16 min_rx_key_ctxs; 2371fbfee257SMichael Chan __le16 max_rx_key_ctxs; 237231d357c0SMichael Chan u8 unused_0[2]; 2373894aa69aSMichael Chan }; 2374894aa69aSMichael Chan 2375894aa69aSMichael Chan /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 2376894aa69aSMichael Chan struct hwrm_func_vf_resource_cfg_output { 2377894aa69aSMichael Chan __le16 error_code; 2378894aa69aSMichael Chan __le16 req_type; 2379894aa69aSMichael Chan __le16 seq_id; 2380894aa69aSMichael Chan __le16 resp_len; 2381894aa69aSMichael Chan __le16 reserved_rsscos_ctx; 2382894aa69aSMichael Chan __le16 reserved_cmpl_rings; 2383894aa69aSMichael Chan __le16 reserved_tx_rings; 2384894aa69aSMichael Chan __le16 reserved_rx_rings; 2385894aa69aSMichael Chan __le16 reserved_l2_ctxs; 2386894aa69aSMichael Chan __le16 reserved_vnics; 2387894aa69aSMichael Chan __le16 reserved_stat_ctx; 2388894aa69aSMichael Chan __le16 reserved_hw_ring_grps; 2389fbfee257SMichael Chan __le16 reserved_tx_key_ctxs; 2390fbfee257SMichael Chan __le16 reserved_rx_key_ctxs; 2391fbfee257SMichael Chan u8 unused_0[3]; 2392894aa69aSMichael Chan u8 valid; 2393894aa69aSMichael Chan }; 2394894aa69aSMichael Chan 23956fc92c33SMichael Chan /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 23966fc92c33SMichael Chan struct hwrm_func_backing_store_qcaps_input { 23976fc92c33SMichael Chan __le16 req_type; 23986fc92c33SMichael Chan __le16 cmpl_ring; 23996fc92c33SMichael Chan __le16 seq_id; 24006fc92c33SMichael Chan __le16 target_id; 24016fc92c33SMichael Chan __le64 resp_addr; 24026fc92c33SMichael Chan }; 24036fc92c33SMichael Chan 240478eeadb8SMichael Chan /* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 24056fc92c33SMichael Chan struct hwrm_func_backing_store_qcaps_output { 24066fc92c33SMichael Chan __le16 error_code; 24076fc92c33SMichael Chan __le16 req_type; 24086fc92c33SMichael Chan __le16 seq_id; 24096fc92c33SMichael Chan __le16 resp_len; 24106fc92c33SMichael Chan __le32 qp_max_entries; 24116fc92c33SMichael Chan __le16 qp_min_qp1_entries; 24126fc92c33SMichael Chan __le16 qp_max_l2_entries; 24136fc92c33SMichael Chan __le16 qp_entry_size; 24146fc92c33SMichael Chan __le16 srq_max_l2_entries; 24156fc92c33SMichael Chan __le32 srq_max_entries; 24166fc92c33SMichael Chan __le16 srq_entry_size; 24176fc92c33SMichael Chan __le16 cq_max_l2_entries; 24186fc92c33SMichael Chan __le32 cq_max_entries; 24196fc92c33SMichael Chan __le16 cq_entry_size; 24206fc92c33SMichael Chan __le16 vnic_max_vnic_entries; 24216fc92c33SMichael Chan __le16 vnic_max_ring_table_entries; 24226fc92c33SMichael Chan __le16 vnic_entry_size; 24236fc92c33SMichael Chan __le32 stat_max_entries; 24246fc92c33SMichael Chan __le16 stat_entry_size; 24256fc92c33SMichael Chan __le16 tqm_entry_size; 24266fc92c33SMichael Chan __le32 tqm_min_entries_per_ring; 24276fc92c33SMichael Chan __le32 tqm_max_entries_per_ring; 24286fc92c33SMichael Chan __le32 mrav_max_entries; 24296fc92c33SMichael Chan __le16 mrav_entry_size; 24306fc92c33SMichael Chan __le16 tim_entry_size; 24316fc92c33SMichael Chan __le32 tim_max_entries; 24324a50ddc2SMichael Chan __le16 mrav_num_entries_units; 243331d357c0SMichael Chan u8 tqm_entries_multiple; 243441136ab3SMichael Chan u8 ctx_kind_initializer; 243516db6323SMichael Chan __le16 ctx_init_mask; 243616db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 243716db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 243816db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 243916db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 244016db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 244116db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 244278eeadb8SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 244378eeadb8SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 244416db6323SMichael Chan u8 qp_init_offset; 244516db6323SMichael Chan u8 srq_init_offset; 244616db6323SMichael Chan u8 cq_init_offset; 244716db6323SMichael Chan u8 vnic_init_offset; 2448460c2577SMichael Chan u8 tqm_fp_rings_count; 244916db6323SMichael Chan u8 stat_init_offset; 245016db6323SMichael Chan u8 mrav_init_offset; 245131f67c2eSMichael Chan u8 tqm_fp_rings_count_ext; 245278eeadb8SMichael Chan u8 tkc_init_offset; 245378eeadb8SMichael Chan u8 rkc_init_offset; 245478eeadb8SMichael Chan __le16 tkc_entry_size; 245578eeadb8SMichael Chan __le16 rkc_entry_size; 245678eeadb8SMichael Chan __le32 tkc_max_entries; 245778eeadb8SMichael Chan __le32 rkc_max_entries; 245878eeadb8SMichael Chan u8 rsvd[7]; 24596fc92c33SMichael Chan u8 valid; 24606fc92c33SMichael Chan }; 24616fc92c33SMichael Chan 246231f67c2eSMichael Chan /* tqm_fp_ring_cfg (size:128b/16B) */ 246331f67c2eSMichael Chan struct tqm_fp_ring_cfg { 246431f67c2eSMichael Chan u8 tqm_ring_pg_size_tqm_ring_lvl; 246531f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 246631f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 246731f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 246831f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 246931f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 247031f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 247131f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 247231f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 247331f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 247431f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 247531f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 247631f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 247731f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 247831f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 247931f67c2eSMichael Chan #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 248031f67c2eSMichael Chan u8 unused[3]; 248131f67c2eSMichael Chan __le32 tqm_ring_num_entries; 248231f67c2eSMichael Chan __le64 tqm_ring_page_dir; 248331f67c2eSMichael Chan }; 248431f67c2eSMichael Chan 248578eeadb8SMichael Chan /* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 24866fc92c33SMichael Chan struct hwrm_func_backing_store_cfg_input { 24876fc92c33SMichael Chan __le16 req_type; 24886fc92c33SMichael Chan __le16 cmpl_ring; 24896fc92c33SMichael Chan __le16 seq_id; 24906fc92c33SMichael Chan __le16 target_id; 24916fc92c33SMichael Chan __le64 resp_addr; 24926fc92c33SMichael Chan __le32 flags; 24936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 24944a50ddc2SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 24956fc92c33SMichael Chan __le32 enables; 24966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 24976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 24986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 24996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 25006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 25016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 25026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 25036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 25046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 25056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 25066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 25076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 25086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 25096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 25106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 25116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 251216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 251316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 251416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 251578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 251678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 25176fc92c33SMichael Chan u8 qpc_pg_size_qpc_lvl; 25186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 25196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 25206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 25216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 25226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 25236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 25246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 25256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 25266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 25276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 25286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 25296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 25306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 25316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 25326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 25336fc92c33SMichael Chan u8 srq_pg_size_srq_lvl; 25346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 25356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 25366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 25376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 25386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 25396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 25406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 25416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 25426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 25436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 25446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 25456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 25466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 25476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 25486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 25496fc92c33SMichael Chan u8 cq_pg_size_cq_lvl; 25506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 25516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 25526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 25536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 25546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 25556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 25566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 25576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 25586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 25596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 25606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 25616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 25626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 25636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 25646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 25656fc92c33SMichael Chan u8 vnic_pg_size_vnic_lvl; 25666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 25676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 25686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 25696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 25706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 25716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 25726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 25736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 25746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 25756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 25766fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 25776fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 25786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 25796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 25806fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 25816fc92c33SMichael Chan u8 stat_pg_size_stat_lvl; 25826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 25836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 25846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 25856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 25866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 25876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 25886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 25896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 25906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 25916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 25926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 25936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 25946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 25956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 25966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 25976fc92c33SMichael Chan u8 tqm_sp_pg_size_tqm_sp_lvl; 25986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 25996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 26006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 26016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 26026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 26036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 26046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 26056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 26066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 26076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 26086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 26096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 26106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 26116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 26126fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 26136fc92c33SMichael Chan u8 tqm_ring0_pg_size_tqm_ring0_lvl; 26146fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 26156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 26166fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 26176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 26186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 26196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 26206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 26216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 26226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 26236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 26246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 26256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 26266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 26276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 26286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 26296fc92c33SMichael Chan u8 tqm_ring1_pg_size_tqm_ring1_lvl; 26306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 26316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 26326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 26336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 26346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 26356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 26366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 26376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 26386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 26396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 26406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 26416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 26426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 26436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 26446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 26456fc92c33SMichael Chan u8 tqm_ring2_pg_size_tqm_ring2_lvl; 26466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 26476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 26486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 26496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 26506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 26516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 26526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 26536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 26546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 26556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 26566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 26576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 26586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 26596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 26606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 26616fc92c33SMichael Chan u8 tqm_ring3_pg_size_tqm_ring3_lvl; 26626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 26636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 26646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 26656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 26666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 26676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 26686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 26696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 26706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 26716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 26726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 26736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 26746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 26756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 26766fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 26776fc92c33SMichael Chan u8 tqm_ring4_pg_size_tqm_ring4_lvl; 26786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 26796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 26806fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 26816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 26826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 26836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 26846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 26856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 26866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 26876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 26886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 26896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 26906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 26916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 26926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 26936fc92c33SMichael Chan u8 tqm_ring5_pg_size_tqm_ring5_lvl; 26946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 26956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 26966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 26976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 26986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 26996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 27006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 27016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 27026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 27036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 27046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 27056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 27066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 27076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 27086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 27096fc92c33SMichael Chan u8 tqm_ring6_pg_size_tqm_ring6_lvl; 27106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 27116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 27126fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 27136fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 27146fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 27156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 27166fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 27176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 27186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 27196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 27206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 27216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 27226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 27236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 27246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 27256fc92c33SMichael Chan u8 tqm_ring7_pg_size_tqm_ring7_lvl; 27266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 27276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 27286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 27296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 27306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 27316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 27326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 27336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 27346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 27356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 27366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 27376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 27386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 27396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 27406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 27416fc92c33SMichael Chan u8 mrav_pg_size_mrav_lvl; 27426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 27436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 27446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 27456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 27466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 27476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 27486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 27496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 27506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 27516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 27526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 27536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 27546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 27556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 27566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 27576fc92c33SMichael Chan u8 tim_pg_size_tim_lvl; 27586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 27596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 27606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 27616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 27626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 27636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 27646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 27656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 27666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 27676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 27686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 27696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 27706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 27716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 27726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 27736fc92c33SMichael Chan __le64 qpc_page_dir; 27746fc92c33SMichael Chan __le64 srq_page_dir; 27756fc92c33SMichael Chan __le64 cq_page_dir; 27766fc92c33SMichael Chan __le64 vnic_page_dir; 27776fc92c33SMichael Chan __le64 stat_page_dir; 27786fc92c33SMichael Chan __le64 tqm_sp_page_dir; 27796fc92c33SMichael Chan __le64 tqm_ring0_page_dir; 27806fc92c33SMichael Chan __le64 tqm_ring1_page_dir; 27816fc92c33SMichael Chan __le64 tqm_ring2_page_dir; 27826fc92c33SMichael Chan __le64 tqm_ring3_page_dir; 27836fc92c33SMichael Chan __le64 tqm_ring4_page_dir; 27846fc92c33SMichael Chan __le64 tqm_ring5_page_dir; 27856fc92c33SMichael Chan __le64 tqm_ring6_page_dir; 27866fc92c33SMichael Chan __le64 tqm_ring7_page_dir; 27876fc92c33SMichael Chan __le64 mrav_page_dir; 27886fc92c33SMichael Chan __le64 tim_page_dir; 27896fc92c33SMichael Chan __le32 qp_num_entries; 27906fc92c33SMichael Chan __le32 srq_num_entries; 27916fc92c33SMichael Chan __le32 cq_num_entries; 27926fc92c33SMichael Chan __le32 stat_num_entries; 27936fc92c33SMichael Chan __le32 tqm_sp_num_entries; 27946fc92c33SMichael Chan __le32 tqm_ring0_num_entries; 27956fc92c33SMichael Chan __le32 tqm_ring1_num_entries; 27966fc92c33SMichael Chan __le32 tqm_ring2_num_entries; 27976fc92c33SMichael Chan __le32 tqm_ring3_num_entries; 27986fc92c33SMichael Chan __le32 tqm_ring4_num_entries; 27996fc92c33SMichael Chan __le32 tqm_ring5_num_entries; 28006fc92c33SMichael Chan __le32 tqm_ring6_num_entries; 28016fc92c33SMichael Chan __le32 tqm_ring7_num_entries; 28026fc92c33SMichael Chan __le32 mrav_num_entries; 28036fc92c33SMichael Chan __le32 tim_num_entries; 28046fc92c33SMichael Chan __le16 qp_num_qp1_entries; 28056fc92c33SMichael Chan __le16 qp_num_l2_entries; 28066fc92c33SMichael Chan __le16 qp_entry_size; 28076fc92c33SMichael Chan __le16 srq_num_l2_entries; 28086fc92c33SMichael Chan __le16 srq_entry_size; 28096fc92c33SMichael Chan __le16 cq_num_l2_entries; 28106fc92c33SMichael Chan __le16 cq_entry_size; 28116fc92c33SMichael Chan __le16 vnic_num_vnic_entries; 28126fc92c33SMichael Chan __le16 vnic_num_ring_table_entries; 28136fc92c33SMichael Chan __le16 vnic_entry_size; 28146fc92c33SMichael Chan __le16 stat_entry_size; 28156fc92c33SMichael Chan __le16 tqm_entry_size; 28166fc92c33SMichael Chan __le16 mrav_entry_size; 28176fc92c33SMichael Chan __le16 tim_entry_size; 281816db6323SMichael Chan u8 tqm_ring8_pg_size_tqm_ring_lvl; 281916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 282016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 282116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 282216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 282316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 282416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 282516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 282616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 282716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 282816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 282916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 283016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 283116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 283216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 283316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 283416db6323SMichael Chan u8 ring8_unused[3]; 283516db6323SMichael Chan __le32 tqm_ring8_num_entries; 283616db6323SMichael Chan __le64 tqm_ring8_page_dir; 283716db6323SMichael Chan u8 tqm_ring9_pg_size_tqm_ring_lvl; 283816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 283916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 284016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 284116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 284216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 284316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 284416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 284516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 284616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 284716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 284816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 284916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 285016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 285116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 285216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 285316db6323SMichael Chan u8 ring9_unused[3]; 285416db6323SMichael Chan __le32 tqm_ring9_num_entries; 285516db6323SMichael Chan __le64 tqm_ring9_page_dir; 285616db6323SMichael Chan u8 tqm_ring10_pg_size_tqm_ring_lvl; 285716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 285816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 285916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 286016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 286116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 286216db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 286316db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 286416db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 286516db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 286616db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 286716db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 286816db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 286916db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 287016db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 287116db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 287216db6323SMichael Chan u8 ring10_unused[3]; 287316db6323SMichael Chan __le32 tqm_ring10_num_entries; 287416db6323SMichael Chan __le64 tqm_ring10_page_dir; 287578eeadb8SMichael Chan __le32 tkc_num_entries; 287678eeadb8SMichael Chan __le32 rkc_num_entries; 287778eeadb8SMichael Chan __le64 tkc_page_dir; 287878eeadb8SMichael Chan __le64 rkc_page_dir; 287978eeadb8SMichael Chan __le16 tkc_entry_size; 288078eeadb8SMichael Chan __le16 rkc_entry_size; 288178eeadb8SMichael Chan u8 tkc_pg_size_tkc_lvl; 288278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 288378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 288478eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 288578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 288678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 288778eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 288878eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 288978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 289078eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 289178eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 289278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 289378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 289478eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 289578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 289678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 289778eeadb8SMichael Chan u8 rkc_pg_size_rkc_lvl; 289878eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 289978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 290078eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 290178eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 290278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 290378eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 290478eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 290578eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 290678eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 290778eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 290878eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 290978eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 291078eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 291178eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 291278eeadb8SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 291378eeadb8SMichael Chan u8 rsvd[2]; 29146fc92c33SMichael Chan }; 29156fc92c33SMichael Chan 29166fc92c33SMichael Chan /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 29176fc92c33SMichael Chan struct hwrm_func_backing_store_cfg_output { 29186fc92c33SMichael Chan __le16 error_code; 29196fc92c33SMichael Chan __le16 req_type; 29206fc92c33SMichael Chan __le16 seq_id; 29216fc92c33SMichael Chan __le16 resp_len; 29226fc92c33SMichael Chan u8 unused_0[7]; 29236fc92c33SMichael Chan u8 valid; 29246fc92c33SMichael Chan }; 29256fc92c33SMichael Chan 29263293ec23SMichael Chan /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 29273293ec23SMichael Chan struct hwrm_error_recovery_qcfg_input { 29283293ec23SMichael Chan __le16 req_type; 29293293ec23SMichael Chan __le16 cmpl_ring; 29303293ec23SMichael Chan __le16 seq_id; 29313293ec23SMichael Chan __le16 target_id; 29323293ec23SMichael Chan __le64 resp_addr; 29333293ec23SMichael Chan u8 unused_0[8]; 29343293ec23SMichael Chan }; 29353293ec23SMichael Chan 29363293ec23SMichael Chan /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 29373293ec23SMichael Chan struct hwrm_error_recovery_qcfg_output { 29383293ec23SMichael Chan __le16 error_code; 29393293ec23SMichael Chan __le16 req_type; 29403293ec23SMichael Chan __le16 seq_id; 29413293ec23SMichael Chan __le16 resp_len; 29423293ec23SMichael Chan __le32 flags; 29433293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 29443293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 29453293ec23SMichael Chan __le32 driver_polling_freq; 29463293ec23SMichael Chan __le32 master_func_wait_period; 29473293ec23SMichael Chan __le32 normal_func_wait_period; 29483293ec23SMichael Chan __le32 master_func_wait_period_after_reset; 29493293ec23SMichael Chan __le32 max_bailout_time_after_reset; 29503293ec23SMichael Chan __le32 fw_health_status_reg; 29513293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 29523293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 29533293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 29543293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 29553293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 29563293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 29573293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 29583293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 29593293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 29603293ec23SMichael Chan __le32 fw_heartbeat_reg; 29613293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 29623293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 29633293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 29643293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 29653293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 29663293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 29673293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 29683293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 29693293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 29703293ec23SMichael Chan __le32 fw_reset_cnt_reg; 29713293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 29723293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 29733293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 29743293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 29753293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 29763293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 29773293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 29783293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 29793293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 29803293ec23SMichael Chan __le32 reset_inprogress_reg; 29813293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 29823293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 29833293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 29843293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 29853293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 29863293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 29873293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 29883293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 29893293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 29903293ec23SMichael Chan __le32 reset_inprogress_reg_mask; 29913293ec23SMichael Chan u8 unused_0[3]; 29923293ec23SMichael Chan u8 reg_array_cnt; 29933293ec23SMichael Chan __le32 reset_reg[16]; 29943293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 29953293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 29963293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 29973293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 29983293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 29993293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 30003293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 30013293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 30023293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 30033293ec23SMichael Chan __le32 reset_reg_val[16]; 30043293ec23SMichael Chan u8 delay_after_reset[16]; 3005460c2577SMichael Chan __le32 err_recovery_cnt_reg; 3006460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3007460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3008460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3009460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3010460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3011460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3012460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3013460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3014460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3015460c2577SMichael Chan u8 unused_1[3]; 30163293ec23SMichael Chan u8 valid; 30173293ec23SMichael Chan }; 30183293ec23SMichael Chan 301931f67c2eSMichael Chan /* hwrm_func_echo_response_input (size:192b/24B) */ 302031f67c2eSMichael Chan struct hwrm_func_echo_response_input { 302131f67c2eSMichael Chan __le16 req_type; 302231f67c2eSMichael Chan __le16 cmpl_ring; 302331f67c2eSMichael Chan __le16 seq_id; 302431f67c2eSMichael Chan __le16 target_id; 302531f67c2eSMichael Chan __le64 resp_addr; 302631f67c2eSMichael Chan __le32 event_data1; 302731f67c2eSMichael Chan __le32 event_data2; 302831f67c2eSMichael Chan }; 302931f67c2eSMichael Chan 303031f67c2eSMichael Chan /* hwrm_func_echo_response_output (size:128b/16B) */ 303131f67c2eSMichael Chan struct hwrm_func_echo_response_output { 303231f67c2eSMichael Chan __le16 error_code; 303331f67c2eSMichael Chan __le16 req_type; 303431f67c2eSMichael Chan __le16 seq_id; 303531f67c2eSMichael Chan __le16 resp_len; 303631f67c2eSMichael Chan u8 unused_0[7]; 303731f67c2eSMichael Chan u8 valid; 303831f67c2eSMichael Chan }; 303931f67c2eSMichael Chan 304078eeadb8SMichael Chan /* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 304178eeadb8SMichael Chan struct hwrm_func_ptp_pin_qcfg_input { 304278eeadb8SMichael Chan __le16 req_type; 304378eeadb8SMichael Chan __le16 cmpl_ring; 304478eeadb8SMichael Chan __le16 seq_id; 304578eeadb8SMichael Chan __le16 target_id; 304678eeadb8SMichael Chan __le64 resp_addr; 304778eeadb8SMichael Chan u8 unused_0[8]; 304878eeadb8SMichael Chan }; 304978eeadb8SMichael Chan 305078eeadb8SMichael Chan /* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 305178eeadb8SMichael Chan struct hwrm_func_ptp_pin_qcfg_output { 305278eeadb8SMichael Chan __le16 error_code; 305378eeadb8SMichael Chan __le16 req_type; 305478eeadb8SMichael Chan __le16 seq_id; 305578eeadb8SMichael Chan __le16 resp_len; 305678eeadb8SMichael Chan u8 num_pins; 305778eeadb8SMichael Chan u8 state; 305878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 305978eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 306078eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 306178eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 306278eeadb8SMichael Chan u8 pin0_usage; 306378eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 306478eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 306578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 306678eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 306778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 306878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 306978eeadb8SMichael Chan u8 pin1_usage; 307078eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 307178eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 307278eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 307378eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 307478eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 307578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 307678eeadb8SMichael Chan u8 pin2_usage; 307778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 307878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 307978eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 308078eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 308178eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 308278eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 308378eeadb8SMichael Chan u8 pin3_usage; 308478eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 308578eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 308678eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 308778eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 308878eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 308978eeadb8SMichael Chan #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 309078eeadb8SMichael Chan u8 unused_0; 309178eeadb8SMichael Chan u8 valid; 309278eeadb8SMichael Chan }; 309378eeadb8SMichael Chan 309478eeadb8SMichael Chan /* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 309578eeadb8SMichael Chan struct hwrm_func_ptp_pin_cfg_input { 309678eeadb8SMichael Chan __le16 req_type; 309778eeadb8SMichael Chan __le16 cmpl_ring; 309878eeadb8SMichael Chan __le16 seq_id; 309978eeadb8SMichael Chan __le16 target_id; 310078eeadb8SMichael Chan __le64 resp_addr; 310178eeadb8SMichael Chan __le32 enables; 310278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 310378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 310478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 310578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 310678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 310778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 310878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 310978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 311078eeadb8SMichael Chan u8 pin0_state; 311178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 311278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 311378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 311478eeadb8SMichael Chan u8 pin0_usage; 311578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 311678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 311778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 311878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 311978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 312078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 312178eeadb8SMichael Chan u8 pin1_state; 312278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 312378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 312478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 312578eeadb8SMichael Chan u8 pin1_usage; 312678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 312778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 312878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 312978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 313078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 313178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 313278eeadb8SMichael Chan u8 pin2_state; 313378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 313478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 313578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 313678eeadb8SMichael Chan u8 pin2_usage; 313778eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 313878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 313978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 314078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 314178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 314278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 314378eeadb8SMichael Chan u8 pin3_state; 314478eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 314578eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 314678eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 314778eeadb8SMichael Chan u8 pin3_usage; 314878eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 314978eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 315078eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 315178eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 315278eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 315378eeadb8SMichael Chan #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 315478eeadb8SMichael Chan u8 unused_0[4]; 315578eeadb8SMichael Chan }; 315678eeadb8SMichael Chan 315778eeadb8SMichael Chan /* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 315878eeadb8SMichael Chan struct hwrm_func_ptp_pin_cfg_output { 315978eeadb8SMichael Chan __le16 error_code; 316078eeadb8SMichael Chan __le16 req_type; 316178eeadb8SMichael Chan __le16 seq_id; 316278eeadb8SMichael Chan __le16 resp_len; 316378eeadb8SMichael Chan u8 unused_0[7]; 316478eeadb8SMichael Chan u8 valid; 316578eeadb8SMichael Chan }; 316678eeadb8SMichael Chan 316778eeadb8SMichael Chan /* hwrm_func_ptp_cfg_input (size:320b/40B) */ 316878eeadb8SMichael Chan struct hwrm_func_ptp_cfg_input { 316978eeadb8SMichael Chan __le16 req_type; 317078eeadb8SMichael Chan __le16 cmpl_ring; 317178eeadb8SMichael Chan __le16 seq_id; 317278eeadb8SMichael Chan __le16 target_id; 317378eeadb8SMichael Chan __le64 resp_addr; 317478eeadb8SMichael Chan __le16 enables; 317578eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 317678eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 317778eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 317878eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 317978eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 318078eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 318178eeadb8SMichael Chan u8 ptp_pps_event; 318278eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 318378eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 318478eeadb8SMichael Chan u8 ptp_freq_adj_dll_source; 318578eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 318678eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 318778eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 318878eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 318978eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 319078eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 319178eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 319278eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 319378eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 319478eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 319578eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 319678eeadb8SMichael Chan u8 ptp_freq_adj_dll_phase; 319778eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 319878eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 319978eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 320078eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 320178eeadb8SMichael Chan #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 320278eeadb8SMichael Chan u8 unused_0[3]; 320378eeadb8SMichael Chan __le32 ptp_freq_adj_ext_period; 320478eeadb8SMichael Chan __le32 ptp_freq_adj_ext_up; 320578eeadb8SMichael Chan __le32 ptp_freq_adj_ext_phase_lower; 320678eeadb8SMichael Chan __le32 ptp_freq_adj_ext_phase_upper; 320778eeadb8SMichael Chan }; 320878eeadb8SMichael Chan 320978eeadb8SMichael Chan /* hwrm_func_ptp_cfg_output (size:128b/16B) */ 321078eeadb8SMichael Chan struct hwrm_func_ptp_cfg_output { 321178eeadb8SMichael Chan __le16 error_code; 321278eeadb8SMichael Chan __le16 req_type; 321378eeadb8SMichael Chan __le16 seq_id; 321478eeadb8SMichael Chan __le16 resp_len; 321578eeadb8SMichael Chan u8 unused_0[7]; 321678eeadb8SMichael Chan u8 valid; 321778eeadb8SMichael Chan }; 321878eeadb8SMichael Chan 321978eeadb8SMichael Chan /* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 322078eeadb8SMichael Chan struct hwrm_func_ptp_ts_query_input { 322178eeadb8SMichael Chan __le16 req_type; 322278eeadb8SMichael Chan __le16 cmpl_ring; 322378eeadb8SMichael Chan __le16 seq_id; 322478eeadb8SMichael Chan __le16 target_id; 322578eeadb8SMichael Chan __le64 resp_addr; 322678eeadb8SMichael Chan __le32 flags; 322778eeadb8SMichael Chan #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 322878eeadb8SMichael Chan #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 322978eeadb8SMichael Chan u8 unused_0[4]; 323078eeadb8SMichael Chan }; 323178eeadb8SMichael Chan 323278eeadb8SMichael Chan /* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 323378eeadb8SMichael Chan struct hwrm_func_ptp_ts_query_output { 323478eeadb8SMichael Chan __le16 error_code; 323578eeadb8SMichael Chan __le16 req_type; 323678eeadb8SMichael Chan __le16 seq_id; 323778eeadb8SMichael Chan __le16 resp_len; 323878eeadb8SMichael Chan __le64 pps_event_ts; 323978eeadb8SMichael Chan __le64 ptm_res_local_ts; 324078eeadb8SMichael Chan __le64 ptm_pmstr_ts; 324178eeadb8SMichael Chan __le32 ptm_mstr_prop_dly; 324278eeadb8SMichael Chan u8 unused_0[3]; 324378eeadb8SMichael Chan u8 valid; 324478eeadb8SMichael Chan }; 324578eeadb8SMichael Chan 32466fc92c33SMichael Chan /* hwrm_func_drv_if_change_input (size:192b/24B) */ 32476fc92c33SMichael Chan struct hwrm_func_drv_if_change_input { 32486fc92c33SMichael Chan __le16 req_type; 32496fc92c33SMichael Chan __le16 cmpl_ring; 32506fc92c33SMichael Chan __le16 seq_id; 32516fc92c33SMichael Chan __le16 target_id; 32526fc92c33SMichael Chan __le64 resp_addr; 32536fc92c33SMichael Chan __le32 flags; 32546fc92c33SMichael Chan #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 32556fc92c33SMichael Chan __le32 unused; 32566fc92c33SMichael Chan }; 32576fc92c33SMichael Chan 32586fc92c33SMichael Chan /* hwrm_func_drv_if_change_output (size:128b/16B) */ 32596fc92c33SMichael Chan struct hwrm_func_drv_if_change_output { 32606fc92c33SMichael Chan __le16 error_code; 32616fc92c33SMichael Chan __le16 req_type; 32626fc92c33SMichael Chan __le16 seq_id; 32636fc92c33SMichael Chan __le16 resp_len; 32646fc92c33SMichael Chan __le32 flags; 32656fc92c33SMichael Chan #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 32663322479eSMichael Chan #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 32676fc92c33SMichael Chan u8 unused_0[3]; 32686fc92c33SMichael Chan u8 valid; 32696fc92c33SMichael Chan }; 32706fc92c33SMichael Chan 3271894aa69aSMichael Chan /* hwrm_port_phy_cfg_input (size:448b/56B) */ 3272c0c050c5SMichael Chan struct hwrm_port_phy_cfg_input { 3273c0c050c5SMichael Chan __le16 req_type; 3274c0c050c5SMichael Chan __le16 cmpl_ring; 3275c0c050c5SMichael Chan __le16 seq_id; 3276c0c050c5SMichael Chan __le16 target_id; 3277c0c050c5SMichael Chan __le64 resp_addr; 3278c0c050c5SMichael Chan __le32 flags; 3279c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 328016d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 3281c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 3282c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 328311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 328411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 328511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 328611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 3287a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 3288a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 3289a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 3290a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 3291a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 3292a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 329316d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 3294bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 3295bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 32969d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 32979d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 32989d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 32999d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 33009d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 33019d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 3302c0c050c5SMichael Chan __le32 enables; 3303c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 3304c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 3305c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 3306c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 3307c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 3308c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 3309c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 3310c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 3311c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 331211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 331311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 3314bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 3315bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 3316c0c050c5SMichael Chan __le16 port_id; 3317c0c050c5SMichael Chan __le16 force_link_speed; 3318441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 3319441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 3320441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 3321441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 3322441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 3323441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 3324441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 3325441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 3326441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 3327441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 3328441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 3329894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 3330c0c050c5SMichael Chan u8 auto_mode; 3331441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 3332441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 3333441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 3334441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 3335441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 3336894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 3337c0c050c5SMichael Chan u8 auto_duplex; 3338441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 3339441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 3340441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 3341894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 3342c0c050c5SMichael Chan u8 auto_pause; 3343c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 3344c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 334511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3346c0c050c5SMichael Chan u8 unused_0; 3347c0c050c5SMichael Chan __le16 auto_link_speed; 3348441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 3349441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 3350441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 3351441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 3352441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 3353441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 3354441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 3355441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 3356441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 3357441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 3358441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 3359894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 3360c0c050c5SMichael Chan __le16 auto_link_speed_mask; 3361c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3362c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3363c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3364c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3365c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3366c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3367c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3368c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3369c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3370c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3371c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 337211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 337311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 337411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3375c0c050c5SMichael Chan u8 wirespeed; 3376441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 3377441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 3378894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 3379c0c050c5SMichael Chan u8 lpbk; 3380441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 3381441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 3382441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 33836fc92c33SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 33846fc92c33SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 3385c0c050c5SMichael Chan u8 force_pause; 3386c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 3387c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 3388c0c050c5SMichael Chan u8 unused_1; 3389c0c050c5SMichael Chan __le32 preemphasis; 339011f15ed3SMichael Chan __le16 eee_link_speed_mask; 339111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 339211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 339311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 339411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 339511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 339611f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 339711f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 3398bfc6e5fbSMichael Chan __le16 force_pam4_link_speed; 3399bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3400bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3401bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3402bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 340311f15ed3SMichael Chan __le32 tx_lpi_timer; 340411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 340511f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 3406bfc6e5fbSMichael Chan __le16 auto_link_pam4_speed_mask; 3407bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 3408bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 3409bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 3410bfc6e5fbSMichael Chan u8 unused_2[2]; 3411c0c050c5SMichael Chan }; 3412c0c050c5SMichael Chan 3413894aa69aSMichael Chan /* hwrm_port_phy_cfg_output (size:128b/16B) */ 3414c0c050c5SMichael Chan struct hwrm_port_phy_cfg_output { 3415c0c050c5SMichael Chan __le16 error_code; 3416c0c050c5SMichael Chan __le16 req_type; 3417c0c050c5SMichael Chan __le16 seq_id; 3418c0c050c5SMichael Chan __le16 resp_len; 3419894aa69aSMichael Chan u8 unused_0[7]; 3420c0c050c5SMichael Chan u8 valid; 3421c0c050c5SMichael Chan }; 3422c0c050c5SMichael Chan 3423d4f52de0SMichael Chan /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 3424d4f52de0SMichael Chan struct hwrm_port_phy_cfg_cmd_err { 3425d4f52de0SMichael Chan u8 code; 3426d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 3427d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 3428d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 3429d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 3430d4f52de0SMichael Chan u8 unused_0[7]; 3431d4f52de0SMichael Chan }; 3432d4f52de0SMichael Chan 3433894aa69aSMichael Chan /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 3434c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_input { 3435c0c050c5SMichael Chan __le16 req_type; 3436c0c050c5SMichael Chan __le16 cmpl_ring; 3437c0c050c5SMichael Chan __le16 seq_id; 3438c0c050c5SMichael Chan __le16 target_id; 3439c0c050c5SMichael Chan __le64 resp_addr; 3440c0c050c5SMichael Chan __le16 port_id; 3441894aa69aSMichael Chan u8 unused_0[6]; 3442c0c050c5SMichael Chan }; 3443c0c050c5SMichael Chan 34449d6b648cSMichael Chan /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 3445c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_output { 3446c0c050c5SMichael Chan __le16 error_code; 3447c0c050c5SMichael Chan __le16 req_type; 3448c0c050c5SMichael Chan __le16 seq_id; 3449c0c050c5SMichael Chan __le16 resp_len; 3450c0c050c5SMichael Chan u8 link; 3451441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 3452441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 3453441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 3454894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 34559d6b648cSMichael Chan u8 active_fec_signal_mode; 34569d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 34579d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 34589d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 34599d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 34609d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 34619d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 34629d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 34639d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 34649d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 34659d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 34669d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 34679d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 34689d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 34699d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 34709d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 3471c0c050c5SMichael Chan __le16 link_speed; 3472441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 3473441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 3474441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 3475441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 3476441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 3477441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 3478441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 3479441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 3480441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 3481441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 348231d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 3483441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 3484894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 3485acb20054SMichael Chan u8 duplex_cfg; 3486acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 3487acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 3488894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 3489c0c050c5SMichael Chan u8 pause; 3490c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 3491c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 3492c0c050c5SMichael Chan __le16 support_speeds; 3493c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 3494c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 3495c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 3496c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 3497c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 3498c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 3499c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 3500c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 3501c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 3502c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 3503c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 350411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 350511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 350611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 3507c0c050c5SMichael Chan __le16 force_link_speed; 3508441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 3509441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 3510441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 3511441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 3512441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 3513441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 3514441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 3515441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 3516441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 3517441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 3518441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 3519894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 3520c0c050c5SMichael Chan u8 auto_mode; 3521441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 3522441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 3523441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 3524441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 3525441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 3526894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 3527c0c050c5SMichael Chan u8 auto_pause; 3528c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 3529c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 353011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 3531c0c050c5SMichael Chan __le16 auto_link_speed; 3532441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 3533441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 3534441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 3535441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 3536441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 3537441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 3538441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 3539441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 3540441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 3541441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 3542441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 3543894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 3544c0c050c5SMichael Chan __le16 auto_link_speed_mask; 3545c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 3546c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 3547c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 3548c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 3549c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 3550c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 3551c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 3552c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 3553c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 3554c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 3555c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 355611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 355711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 355811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 3559c0c050c5SMichael Chan u8 wirespeed; 3560441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 3561441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 3562894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 3563c0c050c5SMichael Chan u8 lpbk; 3564441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 3565441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 3566441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 35676fc92c33SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 35686fc92c33SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 3569c0c050c5SMichael Chan u8 force_pause; 3570c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 3571c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 357211f15ed3SMichael Chan u8 module_status; 3573441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 3574441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 3575441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 3576441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 3577441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 357841136ab3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 3579441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 3580894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 3581c0c050c5SMichael Chan __le32 preemphasis; 3582c0c050c5SMichael Chan u8 phy_maj; 3583c0c050c5SMichael Chan u8 phy_min; 3584c0c050c5SMichael Chan u8 phy_bld; 3585c0c050c5SMichael Chan u8 phy_type; 3586441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 3587441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 3588441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 3589441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 3590441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 3591441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 3592441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 3593441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 3594441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 3595441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 3596441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 3597bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 3598bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 3599bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 3600bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 3601bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 3602bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 3603bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 3604bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 3605bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 3606bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 3607bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 3608bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 3609bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 3610bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 3611acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 3612acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 3613acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 361431d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 361531d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 361631d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 361731d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 3618*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 3619*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 3620*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 3621*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 3622*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 3623*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 3624*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 3625*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 3626*21e70778SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 3627c0c050c5SMichael Chan u8 media_type; 3628441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 3629441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 3630441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 3631441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 3632894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 363311f15ed3SMichael Chan u8 xcvr_pkg_type; 3634441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 3635441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 3636894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 363711f15ed3SMichael Chan u8 eee_config_phy_addr; 3638c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 3639c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 3640894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 3641894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 364211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 364311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 364411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 364511f15ed3SMichael Chan u8 parallel_detect; 364611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 3647c0c050c5SMichael Chan __le16 link_partner_adv_speeds; 3648c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 3649c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 3650c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 3651c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 3652c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 3653c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 3654c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 3655c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 3656c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 3657c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 3658c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 365911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 366011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 366111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 3662c0c050c5SMichael Chan u8 link_partner_adv_auto_mode; 3663441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 3664441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 3665441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 3666441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 3667441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 3668894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 3669c0c050c5SMichael Chan u8 link_partner_adv_pause; 3670c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 3671c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 367211f15ed3SMichael Chan __le16 adv_eee_link_speed_mask; 367311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 367411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 367511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 367611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 367711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 367811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 367911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 368011f15ed3SMichael Chan __le16 link_partner_adv_eee_link_speed_mask; 368111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 368211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 368311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 368411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 368511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 368611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 368711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 368811f15ed3SMichael Chan __le32 xcvr_identifier_type_tx_lpi_timer; 368911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 369011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 369111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 369211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 369311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 369411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 369511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 369611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 369711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3698894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3699a58a3e68SMichael Chan __le16 fec_cfg; 3700a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3701a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3702a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3703a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3704a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3705a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3706a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3707bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3708bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 37099d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 37109d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 37119d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 37129d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 37139d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 37149d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3715acb20054SMichael Chan u8 duplex_state; 3716acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3717acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3718894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3719894aa69aSMichael Chan u8 option_flags; 3720894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 372116db6323SMichael Chan #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 372211f15ed3SMichael Chan char phy_vendor_name[16]; 372311f15ed3SMichael Chan char phy_vendor_partnumber[16]; 3724bfc6e5fbSMichael Chan __le16 support_pam4_speeds; 3725bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3726bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3727bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3728bfc6e5fbSMichael Chan __le16 force_pam4_link_speed; 3729bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3730bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3731bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3732bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3733bfc6e5fbSMichael Chan __le16 auto_pam4_link_speed_mask; 3734bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3735bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3736bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 37379d6b648cSMichael Chan u8 link_partner_pam4_adv_speeds; 3738bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3739bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3740bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3741c0c050c5SMichael Chan u8 valid; 3742c0c050c5SMichael Chan }; 3743c0c050c5SMichael Chan 37444a50ddc2SMichael Chan /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3745c0c050c5SMichael Chan struct hwrm_port_mac_cfg_input { 3746c0c050c5SMichael Chan __le16 req_type; 3747c0c050c5SMichael Chan __le16 cmpl_ring; 3748c0c050c5SMichael Chan __le16 seq_id; 3749c0c050c5SMichael Chan __le16 target_id; 3750c0c050c5SMichael Chan __le64 resp_addr; 3751c0c050c5SMichael Chan __le32 flags; 3752c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3753441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3754c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3755c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 375611f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 375711f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 375811f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 375911f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3760a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3761a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3762441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3763441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3764441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 37654a50ddc2SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3766c0c050c5SMichael Chan __le32 enables; 3767c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3768c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3769441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3770c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3771c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 377211f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 377311f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3774441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 37754a50ddc2SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 377678eeadb8SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 3777c0c050c5SMichael Chan __le16 port_id; 3778c0c050c5SMichael Chan u8 ipg; 3779c0c050c5SMichael Chan u8 lpbk; 3780441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3781441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3782441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3783894aa69aSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3784441cabbbSMichael Chan u8 vlan_pri2cos_map_pri; 3785441cabbbSMichael Chan u8 reserved1; 3786c0c050c5SMichael Chan u8 tunnel_pri2cos_map_pri; 3787c0c050c5SMichael Chan u8 dscp2pri_map_pri; 378811f15ed3SMichael Chan __le16 rx_ts_capture_ptp_msg_type; 378911f15ed3SMichael Chan __le16 tx_ts_capture_ptp_msg_type; 3790441cabbbSMichael Chan u8 cos_field_cfg; 3791441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3792441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3793441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3794441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3795441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3796441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3797441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3798441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3799441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3800441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3801441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3802441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3803441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3804441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3805441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3806441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3807441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3808441cabbbSMichael Chan u8 unused_0[3]; 380978eeadb8SMichael Chan __le32 ptp_freq_adj_ppb; 381078eeadb8SMichael Chan __le32 ptp_adj_phase; 3811c0c050c5SMichael Chan }; 3812c0c050c5SMichael Chan 3813894aa69aSMichael Chan /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3814c0c050c5SMichael Chan struct hwrm_port_mac_cfg_output { 3815c0c050c5SMichael Chan __le16 error_code; 3816c0c050c5SMichael Chan __le16 req_type; 3817c0c050c5SMichael Chan __le16 seq_id; 3818c0c050c5SMichael Chan __le16 resp_len; 3819c0c050c5SMichael Chan __le16 mru; 3820c0c050c5SMichael Chan __le16 mtu; 3821c0c050c5SMichael Chan u8 ipg; 3822c0c050c5SMichael Chan u8 lpbk; 3823441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3824441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3825441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3826894aa69aSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3827c0c050c5SMichael Chan u8 unused_0; 3828c0c050c5SMichael Chan u8 valid; 3829c0c050c5SMichael Chan }; 3830c0c050c5SMichael Chan 3831894aa69aSMichael Chan /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3832acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_input { 3833acb20054SMichael Chan __le16 req_type; 3834acb20054SMichael Chan __le16 cmpl_ring; 3835acb20054SMichael Chan __le16 seq_id; 3836acb20054SMichael Chan __le16 target_id; 3837acb20054SMichael Chan __le64 resp_addr; 3838acb20054SMichael Chan __le16 port_id; 3839894aa69aSMichael Chan u8 unused_0[6]; 3840acb20054SMichael Chan }; 3841acb20054SMichael Chan 384278eeadb8SMichael Chan /* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 3843acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_output { 3844acb20054SMichael Chan __le16 error_code; 3845acb20054SMichael Chan __le16 req_type; 3846acb20054SMichael Chan __le16 seq_id; 3847acb20054SMichael Chan __le16 resp_len; 3848acb20054SMichael Chan u8 flags; 3849acb20054SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 38504a50ddc2SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 385141136ab3SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 385278eeadb8SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 3853894aa69aSMichael Chan u8 unused_0[3]; 3854acb20054SMichael Chan __le32 rx_ts_reg_off_lower; 3855acb20054SMichael Chan __le32 rx_ts_reg_off_upper; 3856acb20054SMichael Chan __le32 rx_ts_reg_off_seq_id; 3857acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_0; 3858acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_1; 3859acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_2; 3860acb20054SMichael Chan __le32 rx_ts_reg_off_domain_id; 3861acb20054SMichael Chan __le32 rx_ts_reg_off_fifo; 3862acb20054SMichael Chan __le32 rx_ts_reg_off_fifo_adv; 3863acb20054SMichael Chan __le32 rx_ts_reg_off_granularity; 3864acb20054SMichael Chan __le32 tx_ts_reg_off_lower; 3865acb20054SMichael Chan __le32 tx_ts_reg_off_upper; 3866acb20054SMichael Chan __le32 tx_ts_reg_off_seq_id; 3867acb20054SMichael Chan __le32 tx_ts_reg_off_fifo; 3868acb20054SMichael Chan __le32 tx_ts_reg_off_granularity; 386978eeadb8SMichael Chan __le32 ts_ref_clock_reg_lower; 387078eeadb8SMichael Chan __le32 ts_ref_clock_reg_upper; 3871894aa69aSMichael Chan u8 unused_1[7]; 3872acb20054SMichael Chan u8 valid; 3873acb20054SMichael Chan }; 3874acb20054SMichael Chan 38756fc92c33SMichael Chan /* tx_port_stats (size:3264b/408B) */ 38766fc92c33SMichael Chan struct tx_port_stats { 38776fc92c33SMichael Chan __le64 tx_64b_frames; 38786fc92c33SMichael Chan __le64 tx_65b_127b_frames; 38796fc92c33SMichael Chan __le64 tx_128b_255b_frames; 38806fc92c33SMichael Chan __le64 tx_256b_511b_frames; 38816fc92c33SMichael Chan __le64 tx_512b_1023b_frames; 38826fc92c33SMichael Chan __le64 tx_1024b_1518b_frames; 38836fc92c33SMichael Chan __le64 tx_good_vlan_frames; 38846fc92c33SMichael Chan __le64 tx_1519b_2047b_frames; 38856fc92c33SMichael Chan __le64 tx_2048b_4095b_frames; 38866fc92c33SMichael Chan __le64 tx_4096b_9216b_frames; 38876fc92c33SMichael Chan __le64 tx_9217b_16383b_frames; 38886fc92c33SMichael Chan __le64 tx_good_frames; 38896fc92c33SMichael Chan __le64 tx_total_frames; 38906fc92c33SMichael Chan __le64 tx_ucast_frames; 38916fc92c33SMichael Chan __le64 tx_mcast_frames; 38926fc92c33SMichael Chan __le64 tx_bcast_frames; 38936fc92c33SMichael Chan __le64 tx_pause_frames; 38946fc92c33SMichael Chan __le64 tx_pfc_frames; 38956fc92c33SMichael Chan __le64 tx_jabber_frames; 38966fc92c33SMichael Chan __le64 tx_fcs_err_frames; 38976fc92c33SMichael Chan __le64 tx_control_frames; 38986fc92c33SMichael Chan __le64 tx_oversz_frames; 38996fc92c33SMichael Chan __le64 tx_single_dfrl_frames; 39006fc92c33SMichael Chan __le64 tx_multi_dfrl_frames; 39016fc92c33SMichael Chan __le64 tx_single_coll_frames; 39026fc92c33SMichael Chan __le64 tx_multi_coll_frames; 39036fc92c33SMichael Chan __le64 tx_late_coll_frames; 39046fc92c33SMichael Chan __le64 tx_excessive_coll_frames; 39056fc92c33SMichael Chan __le64 tx_frag_frames; 39066fc92c33SMichael Chan __le64 tx_err; 39076fc92c33SMichael Chan __le64 tx_tagged_frames; 39086fc92c33SMichael Chan __le64 tx_dbl_tagged_frames; 39096fc92c33SMichael Chan __le64 tx_runt_frames; 39106fc92c33SMichael Chan __le64 tx_fifo_underruns; 39116fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri0; 39126fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri1; 39136fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri2; 39146fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri3; 39156fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri4; 39166fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri5; 39176fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri6; 39186fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri7; 39196fc92c33SMichael Chan __le64 tx_eee_lpi_events; 39206fc92c33SMichael Chan __le64 tx_eee_lpi_duration; 39216fc92c33SMichael Chan __le64 tx_llfc_logical_msgs; 39226fc92c33SMichael Chan __le64 tx_hcfc_msgs; 39236fc92c33SMichael Chan __le64 tx_total_collisions; 39246fc92c33SMichael Chan __le64 tx_bytes; 39256fc92c33SMichael Chan __le64 tx_xthol_frames; 39266fc92c33SMichael Chan __le64 tx_stat_discard; 39276fc92c33SMichael Chan __le64 tx_stat_error; 39286fc92c33SMichael Chan }; 39296fc92c33SMichael Chan 39306fc92c33SMichael Chan /* rx_port_stats (size:4224b/528B) */ 39316fc92c33SMichael Chan struct rx_port_stats { 39326fc92c33SMichael Chan __le64 rx_64b_frames; 39336fc92c33SMichael Chan __le64 rx_65b_127b_frames; 39346fc92c33SMichael Chan __le64 rx_128b_255b_frames; 39356fc92c33SMichael Chan __le64 rx_256b_511b_frames; 39366fc92c33SMichael Chan __le64 rx_512b_1023b_frames; 39376fc92c33SMichael Chan __le64 rx_1024b_1518b_frames; 39386fc92c33SMichael Chan __le64 rx_good_vlan_frames; 39396fc92c33SMichael Chan __le64 rx_1519b_2047b_frames; 39406fc92c33SMichael Chan __le64 rx_2048b_4095b_frames; 39416fc92c33SMichael Chan __le64 rx_4096b_9216b_frames; 39426fc92c33SMichael Chan __le64 rx_9217b_16383b_frames; 39436fc92c33SMichael Chan __le64 rx_total_frames; 39446fc92c33SMichael Chan __le64 rx_ucast_frames; 39456fc92c33SMichael Chan __le64 rx_mcast_frames; 39466fc92c33SMichael Chan __le64 rx_bcast_frames; 39476fc92c33SMichael Chan __le64 rx_fcs_err_frames; 39486fc92c33SMichael Chan __le64 rx_ctrl_frames; 39496fc92c33SMichael Chan __le64 rx_pause_frames; 39506fc92c33SMichael Chan __le64 rx_pfc_frames; 39516fc92c33SMichael Chan __le64 rx_unsupported_opcode_frames; 39526fc92c33SMichael Chan __le64 rx_unsupported_da_pausepfc_frames; 39536fc92c33SMichael Chan __le64 rx_wrong_sa_frames; 39546fc92c33SMichael Chan __le64 rx_align_err_frames; 39556fc92c33SMichael Chan __le64 rx_oor_len_frames; 39566fc92c33SMichael Chan __le64 rx_code_err_frames; 39576fc92c33SMichael Chan __le64 rx_false_carrier_frames; 39586fc92c33SMichael Chan __le64 rx_ovrsz_frames; 39596fc92c33SMichael Chan __le64 rx_jbr_frames; 39606fc92c33SMichael Chan __le64 rx_mtu_err_frames; 39616fc92c33SMichael Chan __le64 rx_match_crc_frames; 39626fc92c33SMichael Chan __le64 rx_promiscuous_frames; 39636fc92c33SMichael Chan __le64 rx_tagged_frames; 39646fc92c33SMichael Chan __le64 rx_double_tagged_frames; 39656fc92c33SMichael Chan __le64 rx_trunc_frames; 39666fc92c33SMichael Chan __le64 rx_good_frames; 39676fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri0; 39686fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri1; 39696fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri2; 39706fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri3; 39716fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri4; 39726fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri5; 39736fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri6; 39746fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri7; 39756fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri0; 39766fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri1; 39776fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri2; 39786fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri3; 39796fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri4; 39806fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri5; 39816fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri6; 39826fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri7; 39836fc92c33SMichael Chan __le64 rx_sch_crc_err_frames; 39846fc92c33SMichael Chan __le64 rx_undrsz_frames; 39856fc92c33SMichael Chan __le64 rx_frag_frames; 39866fc92c33SMichael Chan __le64 rx_eee_lpi_events; 39876fc92c33SMichael Chan __le64 rx_eee_lpi_duration; 39886fc92c33SMichael Chan __le64 rx_llfc_physical_msgs; 39896fc92c33SMichael Chan __le64 rx_llfc_logical_msgs; 39906fc92c33SMichael Chan __le64 rx_llfc_msgs_with_crc_err; 39916fc92c33SMichael Chan __le64 rx_hcfc_msgs; 39926fc92c33SMichael Chan __le64 rx_hcfc_msgs_with_crc_err; 39936fc92c33SMichael Chan __le64 rx_bytes; 39946fc92c33SMichael Chan __le64 rx_runt_bytes; 39956fc92c33SMichael Chan __le64 rx_runt_frames; 39966fc92c33SMichael Chan __le64 rx_stat_discard; 39976fc92c33SMichael Chan __le64 rx_stat_err; 39986fc92c33SMichael Chan }; 39996fc92c33SMichael Chan 4000894aa69aSMichael Chan /* hwrm_port_qstats_input (size:320b/40B) */ 4001c0c050c5SMichael Chan struct hwrm_port_qstats_input { 4002c0c050c5SMichael Chan __le16 req_type; 4003c0c050c5SMichael Chan __le16 cmpl_ring; 4004c0c050c5SMichael Chan __le16 seq_id; 4005c0c050c5SMichael Chan __le16 target_id; 4006c0c050c5SMichael Chan __le64 resp_addr; 4007c0c050c5SMichael Chan __le16 port_id; 4008460c2577SMichael Chan u8 flags; 4009460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 4010460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 4011460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 4012460c2577SMichael Chan u8 unused_0[5]; 4013c0c050c5SMichael Chan __le64 tx_stat_host_addr; 4014c0c050c5SMichael Chan __le64 rx_stat_host_addr; 4015c0c050c5SMichael Chan }; 4016c0c050c5SMichael Chan 4017894aa69aSMichael Chan /* hwrm_port_qstats_output (size:128b/16B) */ 4018c0c050c5SMichael Chan struct hwrm_port_qstats_output { 4019c0c050c5SMichael Chan __le16 error_code; 4020c0c050c5SMichael Chan __le16 req_type; 4021c0c050c5SMichael Chan __le16 seq_id; 4022c0c050c5SMichael Chan __le16 resp_len; 4023c193554eSMichael Chan __le16 tx_stat_size; 4024c193554eSMichael Chan __le16 rx_stat_size; 4025894aa69aSMichael Chan u8 unused_0[3]; 4026c0c050c5SMichael Chan u8 valid; 4027c0c050c5SMichael Chan }; 4028c0c050c5SMichael Chan 40296fc92c33SMichael Chan /* tx_port_stats_ext (size:2048b/256B) */ 40306fc92c33SMichael Chan struct tx_port_stats_ext { 40316fc92c33SMichael Chan __le64 tx_bytes_cos0; 40326fc92c33SMichael Chan __le64 tx_bytes_cos1; 40336fc92c33SMichael Chan __le64 tx_bytes_cos2; 40346fc92c33SMichael Chan __le64 tx_bytes_cos3; 40356fc92c33SMichael Chan __le64 tx_bytes_cos4; 40366fc92c33SMichael Chan __le64 tx_bytes_cos5; 40376fc92c33SMichael Chan __le64 tx_bytes_cos6; 40386fc92c33SMichael Chan __le64 tx_bytes_cos7; 40396fc92c33SMichael Chan __le64 tx_packets_cos0; 40406fc92c33SMichael Chan __le64 tx_packets_cos1; 40416fc92c33SMichael Chan __le64 tx_packets_cos2; 40426fc92c33SMichael Chan __le64 tx_packets_cos3; 40436fc92c33SMichael Chan __le64 tx_packets_cos4; 40446fc92c33SMichael Chan __le64 tx_packets_cos5; 40456fc92c33SMichael Chan __le64 tx_packets_cos6; 40466fc92c33SMichael Chan __le64 tx_packets_cos7; 40476fc92c33SMichael Chan __le64 pfc_pri0_tx_duration_us; 40486fc92c33SMichael Chan __le64 pfc_pri0_tx_transitions; 40496fc92c33SMichael Chan __le64 pfc_pri1_tx_duration_us; 40506fc92c33SMichael Chan __le64 pfc_pri1_tx_transitions; 40516fc92c33SMichael Chan __le64 pfc_pri2_tx_duration_us; 40526fc92c33SMichael Chan __le64 pfc_pri2_tx_transitions; 40536fc92c33SMichael Chan __le64 pfc_pri3_tx_duration_us; 40546fc92c33SMichael Chan __le64 pfc_pri3_tx_transitions; 40556fc92c33SMichael Chan __le64 pfc_pri4_tx_duration_us; 40566fc92c33SMichael Chan __le64 pfc_pri4_tx_transitions; 40576fc92c33SMichael Chan __le64 pfc_pri5_tx_duration_us; 40586fc92c33SMichael Chan __le64 pfc_pri5_tx_transitions; 40596fc92c33SMichael Chan __le64 pfc_pri6_tx_duration_us; 40606fc92c33SMichael Chan __le64 pfc_pri6_tx_transitions; 40616fc92c33SMichael Chan __le64 pfc_pri7_tx_duration_us; 40626fc92c33SMichael Chan __le64 pfc_pri7_tx_transitions; 40636fc92c33SMichael Chan }; 40646fc92c33SMichael Chan 4065*21e70778SMichael Chan /* rx_port_stats_ext (size:3776b/472B) */ 40666fc92c33SMichael Chan struct rx_port_stats_ext { 40676fc92c33SMichael Chan __le64 link_down_events; 40686fc92c33SMichael Chan __le64 continuous_pause_events; 40696fc92c33SMichael Chan __le64 resume_pause_events; 40706fc92c33SMichael Chan __le64 continuous_roce_pause_events; 40716fc92c33SMichael Chan __le64 resume_roce_pause_events; 40726fc92c33SMichael Chan __le64 rx_bytes_cos0; 40736fc92c33SMichael Chan __le64 rx_bytes_cos1; 40746fc92c33SMichael Chan __le64 rx_bytes_cos2; 40756fc92c33SMichael Chan __le64 rx_bytes_cos3; 40766fc92c33SMichael Chan __le64 rx_bytes_cos4; 40776fc92c33SMichael Chan __le64 rx_bytes_cos5; 40786fc92c33SMichael Chan __le64 rx_bytes_cos6; 40796fc92c33SMichael Chan __le64 rx_bytes_cos7; 40806fc92c33SMichael Chan __le64 rx_packets_cos0; 40816fc92c33SMichael Chan __le64 rx_packets_cos1; 40826fc92c33SMichael Chan __le64 rx_packets_cos2; 40836fc92c33SMichael Chan __le64 rx_packets_cos3; 40846fc92c33SMichael Chan __le64 rx_packets_cos4; 40856fc92c33SMichael Chan __le64 rx_packets_cos5; 40866fc92c33SMichael Chan __le64 rx_packets_cos6; 40876fc92c33SMichael Chan __le64 rx_packets_cos7; 40886fc92c33SMichael Chan __le64 pfc_pri0_rx_duration_us; 40896fc92c33SMichael Chan __le64 pfc_pri0_rx_transitions; 40906fc92c33SMichael Chan __le64 pfc_pri1_rx_duration_us; 40916fc92c33SMichael Chan __le64 pfc_pri1_rx_transitions; 40926fc92c33SMichael Chan __le64 pfc_pri2_rx_duration_us; 40936fc92c33SMichael Chan __le64 pfc_pri2_rx_transitions; 40946fc92c33SMichael Chan __le64 pfc_pri3_rx_duration_us; 40956fc92c33SMichael Chan __le64 pfc_pri3_rx_transitions; 40966fc92c33SMichael Chan __le64 pfc_pri4_rx_duration_us; 40976fc92c33SMichael Chan __le64 pfc_pri4_rx_transitions; 40986fc92c33SMichael Chan __le64 pfc_pri5_rx_duration_us; 40996fc92c33SMichael Chan __le64 pfc_pri5_rx_transitions; 41006fc92c33SMichael Chan __le64 pfc_pri6_rx_duration_us; 41016fc92c33SMichael Chan __le64 pfc_pri6_rx_transitions; 41026fc92c33SMichael Chan __le64 pfc_pri7_rx_duration_us; 41036fc92c33SMichael Chan __le64 pfc_pri7_rx_transitions; 41044a50ddc2SMichael Chan __le64 rx_bits; 41054a50ddc2SMichael Chan __le64 rx_buffer_passed_threshold; 41064a50ddc2SMichael Chan __le64 rx_pcs_symbol_err; 41074a50ddc2SMichael Chan __le64 rx_corrected_bits; 41082792b5b9SMichael Chan __le64 rx_discard_bytes_cos0; 41092792b5b9SMichael Chan __le64 rx_discard_bytes_cos1; 41102792b5b9SMichael Chan __le64 rx_discard_bytes_cos2; 41112792b5b9SMichael Chan __le64 rx_discard_bytes_cos3; 41122792b5b9SMichael Chan __le64 rx_discard_bytes_cos4; 41132792b5b9SMichael Chan __le64 rx_discard_bytes_cos5; 41142792b5b9SMichael Chan __le64 rx_discard_bytes_cos6; 41152792b5b9SMichael Chan __le64 rx_discard_bytes_cos7; 41162792b5b9SMichael Chan __le64 rx_discard_packets_cos0; 41172792b5b9SMichael Chan __le64 rx_discard_packets_cos1; 41182792b5b9SMichael Chan __le64 rx_discard_packets_cos2; 41192792b5b9SMichael Chan __le64 rx_discard_packets_cos3; 41202792b5b9SMichael Chan __le64 rx_discard_packets_cos4; 41212792b5b9SMichael Chan __le64 rx_discard_packets_cos5; 41222792b5b9SMichael Chan __le64 rx_discard_packets_cos6; 41232792b5b9SMichael Chan __le64 rx_discard_packets_cos7; 4124*21e70778SMichael Chan __le64 rx_fec_corrected_blocks; 4125*21e70778SMichael Chan __le64 rx_fec_uncorrectable_blocks; 41266fc92c33SMichael Chan }; 41276fc92c33SMichael Chan 4128d4f52de0SMichael Chan /* hwrm_port_qstats_ext_input (size:320b/40B) */ 4129d4f52de0SMichael Chan struct hwrm_port_qstats_ext_input { 4130d4f52de0SMichael Chan __le16 req_type; 4131d4f52de0SMichael Chan __le16 cmpl_ring; 4132d4f52de0SMichael Chan __le16 seq_id; 4133d4f52de0SMichael Chan __le16 target_id; 4134d4f52de0SMichael Chan __le64 resp_addr; 4135d4f52de0SMichael Chan __le16 port_id; 4136d4f52de0SMichael Chan __le16 tx_stat_size; 4137d4f52de0SMichael Chan __le16 rx_stat_size; 4138460c2577SMichael Chan u8 flags; 4139460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 4140460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 4141460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 4142460c2577SMichael Chan u8 unused_0; 4143d4f52de0SMichael Chan __le64 tx_stat_host_addr; 4144d4f52de0SMichael Chan __le64 rx_stat_host_addr; 4145d4f52de0SMichael Chan }; 4146d4f52de0SMichael Chan 4147d4f52de0SMichael Chan /* hwrm_port_qstats_ext_output (size:128b/16B) */ 4148d4f52de0SMichael Chan struct hwrm_port_qstats_ext_output { 4149d4f52de0SMichael Chan __le16 error_code; 4150d4f52de0SMichael Chan __le16 req_type; 4151d4f52de0SMichael Chan __le16 seq_id; 4152d4f52de0SMichael Chan __le16 resp_len; 4153d4f52de0SMichael Chan __le16 tx_stat_size; 4154d4f52de0SMichael Chan __le16 rx_stat_size; 41556fc92c33SMichael Chan __le16 total_active_cos_queues; 415631d357c0SMichael Chan u8 flags; 415731d357c0SMichael Chan #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 4158d4f52de0SMichael Chan u8 valid; 4159d4f52de0SMichael Chan }; 4160d4f52de0SMichael Chan 4161894aa69aSMichael Chan /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 4162c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_input { 4163c0c050c5SMichael Chan __le16 req_type; 4164c0c050c5SMichael Chan __le16 cmpl_ring; 4165c0c050c5SMichael Chan __le16 seq_id; 4166c0c050c5SMichael Chan __le16 target_id; 4167c0c050c5SMichael Chan __le64 resp_addr; 4168c0c050c5SMichael Chan }; 4169c0c050c5SMichael Chan 4170894aa69aSMichael Chan /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 4171c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_output { 4172c0c050c5SMichael Chan __le16 error_code; 4173c0c050c5SMichael Chan __le16 req_type; 4174c0c050c5SMichael Chan __le16 seq_id; 4175c0c050c5SMichael Chan __le16 resp_len; 4176c0c050c5SMichael Chan __le64 lpbk_ucast_frames; 4177c0c050c5SMichael Chan __le64 lpbk_mcast_frames; 4178c0c050c5SMichael Chan __le64 lpbk_bcast_frames; 4179c0c050c5SMichael Chan __le64 lpbk_ucast_bytes; 4180c0c050c5SMichael Chan __le64 lpbk_mcast_bytes; 4181c0c050c5SMichael Chan __le64 lpbk_bcast_bytes; 4182c193554eSMichael Chan __le64 tx_stat_discard; 4183c193554eSMichael Chan __le64 tx_stat_error; 4184c193554eSMichael Chan __le64 rx_stat_discard; 4185c193554eSMichael Chan __le64 rx_stat_error; 4186894aa69aSMichael Chan u8 unused_0[7]; 4187c0c050c5SMichael Chan u8 valid; 4188c0c050c5SMichael Chan }; 4189c0c050c5SMichael Chan 41909d6b648cSMichael Chan /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 41919d6b648cSMichael Chan struct hwrm_port_ecn_qstats_input { 41929d6b648cSMichael Chan __le16 req_type; 41939d6b648cSMichael Chan __le16 cmpl_ring; 41949d6b648cSMichael Chan __le16 seq_id; 41959d6b648cSMichael Chan __le16 target_id; 41969d6b648cSMichael Chan __le64 resp_addr; 41979d6b648cSMichael Chan __le16 port_id; 41989d6b648cSMichael Chan __le16 ecn_stat_buf_size; 41999d6b648cSMichael Chan u8 flags; 42009d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 42019d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 42029d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 42039d6b648cSMichael Chan u8 unused_0[3]; 42049d6b648cSMichael Chan __le64 ecn_stat_host_addr; 42059d6b648cSMichael Chan }; 42069d6b648cSMichael Chan 42079d6b648cSMichael Chan /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 42089d6b648cSMichael Chan struct hwrm_port_ecn_qstats_output { 42099d6b648cSMichael Chan __le16 error_code; 42109d6b648cSMichael Chan __le16 req_type; 42119d6b648cSMichael Chan __le16 seq_id; 42129d6b648cSMichael Chan __le16 resp_len; 42139d6b648cSMichael Chan __le16 ecn_stat_buf_size; 42149d6b648cSMichael Chan u8 mark_en; 42159d6b648cSMichael Chan u8 unused_0[4]; 42169d6b648cSMichael Chan u8 valid; 42179d6b648cSMichael Chan }; 42189d6b648cSMichael Chan 42199d6b648cSMichael Chan /* port_stats_ecn (size:512b/64B) */ 42209d6b648cSMichael Chan struct port_stats_ecn { 42219d6b648cSMichael Chan __le64 mark_cnt_cos0; 42229d6b648cSMichael Chan __le64 mark_cnt_cos1; 42239d6b648cSMichael Chan __le64 mark_cnt_cos2; 42249d6b648cSMichael Chan __le64 mark_cnt_cos3; 42259d6b648cSMichael Chan __le64 mark_cnt_cos4; 42269d6b648cSMichael Chan __le64 mark_cnt_cos5; 42279d6b648cSMichael Chan __le64 mark_cnt_cos6; 42289d6b648cSMichael Chan __le64 mark_cnt_cos7; 42299d6b648cSMichael Chan }; 42309d6b648cSMichael Chan 4231894aa69aSMichael Chan /* hwrm_port_clr_stats_input (size:192b/24B) */ 4232c0c050c5SMichael Chan struct hwrm_port_clr_stats_input { 4233c0c050c5SMichael Chan __le16 req_type; 4234c0c050c5SMichael Chan __le16 cmpl_ring; 4235c0c050c5SMichael Chan __le16 seq_id; 4236c0c050c5SMichael Chan __le16 target_id; 4237c0c050c5SMichael Chan __le64 resp_addr; 4238c0c050c5SMichael Chan __le16 port_id; 423931d357c0SMichael Chan u8 flags; 424031d357c0SMichael Chan #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 424131d357c0SMichael Chan u8 unused_0[5]; 4242c0c050c5SMichael Chan }; 4243c0c050c5SMichael Chan 4244894aa69aSMichael Chan /* hwrm_port_clr_stats_output (size:128b/16B) */ 4245c0c050c5SMichael Chan struct hwrm_port_clr_stats_output { 4246c0c050c5SMichael Chan __le16 error_code; 4247c0c050c5SMichael Chan __le16 req_type; 4248c0c050c5SMichael Chan __le16 seq_id; 4249c0c050c5SMichael Chan __le16 resp_len; 4250894aa69aSMichael Chan u8 unused_0[7]; 4251c0c050c5SMichael Chan u8 valid; 4252c0c050c5SMichael Chan }; 4253c0c050c5SMichael Chan 4254894aa69aSMichael Chan /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 4255c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_input { 4256c0c050c5SMichael Chan __le16 req_type; 4257c0c050c5SMichael Chan __le16 cmpl_ring; 4258c0c050c5SMichael Chan __le16 seq_id; 4259c0c050c5SMichael Chan __le16 target_id; 4260c0c050c5SMichael Chan __le64 resp_addr; 4261c0c050c5SMichael Chan }; 4262c0c050c5SMichael Chan 4263894aa69aSMichael Chan /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 4264c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_output { 4265c0c050c5SMichael Chan __le16 error_code; 4266c0c050c5SMichael Chan __le16 req_type; 4267c0c050c5SMichael Chan __le16 seq_id; 4268c0c050c5SMichael Chan __le16 resp_len; 4269894aa69aSMichael Chan u8 unused_0[7]; 4270c0c050c5SMichael Chan u8 valid; 4271c0c050c5SMichael Chan }; 4272c0c050c5SMichael Chan 4273fbfee257SMichael Chan /* hwrm_port_ts_query_input (size:320b/40B) */ 42744a50ddc2SMichael Chan struct hwrm_port_ts_query_input { 42754a50ddc2SMichael Chan __le16 req_type; 42764a50ddc2SMichael Chan __le16 cmpl_ring; 42774a50ddc2SMichael Chan __le16 seq_id; 42784a50ddc2SMichael Chan __le16 target_id; 42794a50ddc2SMichael Chan __le64 resp_addr; 42804a50ddc2SMichael Chan __le32 flags; 42814a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 42824a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 42834a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 42844a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 42854a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 42864a50ddc2SMichael Chan __le16 port_id; 42874a50ddc2SMichael Chan u8 unused_0[2]; 428878eeadb8SMichael Chan __le16 enables; 428978eeadb8SMichael Chan #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 429078eeadb8SMichael Chan #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 4291fbfee257SMichael Chan #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 429278eeadb8SMichael Chan __le16 ts_req_timeout; 429378eeadb8SMichael Chan __le32 ptp_seq_id; 4294fbfee257SMichael Chan __le16 ptp_hdr_offset; 4295fbfee257SMichael Chan u8 unused_1[6]; 42964a50ddc2SMichael Chan }; 42974a50ddc2SMichael Chan 42984a50ddc2SMichael Chan /* hwrm_port_ts_query_output (size:192b/24B) */ 42994a50ddc2SMichael Chan struct hwrm_port_ts_query_output { 43004a50ddc2SMichael Chan __le16 error_code; 43014a50ddc2SMichael Chan __le16 req_type; 43024a50ddc2SMichael Chan __le16 seq_id; 43034a50ddc2SMichael Chan __le16 resp_len; 43044a50ddc2SMichael Chan __le64 ptp_msg_ts; 43054a50ddc2SMichael Chan __le16 ptp_msg_seqid; 43064a50ddc2SMichael Chan u8 unused_0[5]; 43074a50ddc2SMichael Chan u8 valid; 43084a50ddc2SMichael Chan }; 43094a50ddc2SMichael Chan 4310894aa69aSMichael Chan /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 431111f15ed3SMichael Chan struct hwrm_port_phy_qcaps_input { 431211f15ed3SMichael Chan __le16 req_type; 431311f15ed3SMichael Chan __le16 cmpl_ring; 431411f15ed3SMichael Chan __le16 seq_id; 431511f15ed3SMichael Chan __le16 target_id; 431611f15ed3SMichael Chan __le64 resp_addr; 431711f15ed3SMichael Chan __le16 port_id; 4318894aa69aSMichael Chan u8 unused_0[6]; 431911f15ed3SMichael Chan }; 432011f15ed3SMichael Chan 4321bfc6e5fbSMichael Chan /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 432211f15ed3SMichael Chan struct hwrm_port_phy_qcaps_output { 432311f15ed3SMichael Chan __le16 error_code; 432411f15ed3SMichael Chan __le16 req_type; 432511f15ed3SMichael Chan __le16 seq_id; 432611f15ed3SMichael Chan __le16 resp_len; 4327acb20054SMichael Chan u8 flags; 4328acb20054SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 43296fc92c33SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 433041136ab3SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 433141136ab3SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 4332bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 43339d6b648cSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 433416db6323SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 433531f67c2eSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 43366a17eb27SMichael Chan u8 port_cnt; 43376a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 43386a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 43396a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 43406a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 43416a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 4342894aa69aSMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 434311f15ed3SMichael Chan __le16 supported_speeds_force_mode; 434411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 434511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 434611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 434711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 434811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 434911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 435011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 435111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 435211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 435311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 435411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 435511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 435611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 435711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 435811f15ed3SMichael Chan __le16 supported_speeds_auto_mode; 435911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 436011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 436111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 436211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 436311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 436411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 436511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 436611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 436711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 436811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 436911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 437011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 437111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 437211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 437311f15ed3SMichael Chan __le16 supported_speeds_eee_mode; 437411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 437511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 437611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 437711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 437811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 437911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 438011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 438111f15ed3SMichael Chan __le32 tx_lpi_timer_low; 438211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 438311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 438411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 438511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 438611f15ed3SMichael Chan __le32 valid_tx_lpi_timer_high; 438711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 438811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 4389bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 4390bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 4391bfc6e5fbSMichael Chan __le16 supported_pam4_speeds_auto_mode; 4392bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 4393bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 4394bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 4395bfc6e5fbSMichael Chan __le16 supported_pam4_speeds_force_mode; 4396bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 4397bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 4398bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 4399*21e70778SMichael Chan __le16 flags2; 4400*21e70778SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 4401*21e70778SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 4402*21e70778SMichael Chan u8 unused_0[1]; 4403bfc6e5fbSMichael Chan u8 valid; 440411f15ed3SMichael Chan }; 440511f15ed3SMichael Chan 4406894aa69aSMichael Chan /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 440742ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_input { 440842ee18feSAjit Khaparde __le16 req_type; 440942ee18feSAjit Khaparde __le16 cmpl_ring; 441042ee18feSAjit Khaparde __le16 seq_id; 441142ee18feSAjit Khaparde __le16 target_id; 441242ee18feSAjit Khaparde __le64 resp_addr; 441342ee18feSAjit Khaparde __le32 flags; 441442ee18feSAjit Khaparde __le32 enables; 441542ee18feSAjit Khaparde #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 441642ee18feSAjit Khaparde __le16 port_id; 441742ee18feSAjit Khaparde u8 i2c_slave_addr; 441842ee18feSAjit Khaparde u8 unused_0; 441942ee18feSAjit Khaparde __le16 page_number; 442042ee18feSAjit Khaparde __le16 page_offset; 442142ee18feSAjit Khaparde u8 data_length; 442242ee18feSAjit Khaparde u8 unused_1[7]; 442342ee18feSAjit Khaparde }; 442442ee18feSAjit Khaparde 4425894aa69aSMichael Chan /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 442642ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_output { 442742ee18feSAjit Khaparde __le16 error_code; 442842ee18feSAjit Khaparde __le16 req_type; 442942ee18feSAjit Khaparde __le16 seq_id; 443042ee18feSAjit Khaparde __le16 resp_len; 443142ee18feSAjit Khaparde __le32 data[16]; 4432894aa69aSMichael Chan u8 unused_0[7]; 443342ee18feSAjit Khaparde u8 valid; 443442ee18feSAjit Khaparde }; 443542ee18feSAjit Khaparde 44363322479eSMichael Chan /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 44373322479eSMichael Chan struct hwrm_port_phy_mdio_write_input { 44383322479eSMichael Chan __le16 req_type; 44393322479eSMichael Chan __le16 cmpl_ring; 44403322479eSMichael Chan __le16 seq_id; 44413322479eSMichael Chan __le16 target_id; 44423322479eSMichael Chan __le64 resp_addr; 44433322479eSMichael Chan __le32 unused_0[2]; 44443322479eSMichael Chan __le16 port_id; 44453322479eSMichael Chan u8 phy_addr; 44463322479eSMichael Chan u8 dev_addr; 44473322479eSMichael Chan __le16 reg_addr; 44483322479eSMichael Chan __le16 reg_data; 44493322479eSMichael Chan u8 cl45_mdio; 44503322479eSMichael Chan u8 unused_1[7]; 44513322479eSMichael Chan }; 44523322479eSMichael Chan 44533322479eSMichael Chan /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 44543322479eSMichael Chan struct hwrm_port_phy_mdio_write_output { 44553322479eSMichael Chan __le16 error_code; 44563322479eSMichael Chan __le16 req_type; 44573322479eSMichael Chan __le16 seq_id; 44583322479eSMichael Chan __le16 resp_len; 44593322479eSMichael Chan u8 unused_0[7]; 44603322479eSMichael Chan u8 valid; 44613322479eSMichael Chan }; 44623322479eSMichael Chan 44633322479eSMichael Chan /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 44643322479eSMichael Chan struct hwrm_port_phy_mdio_read_input { 44653322479eSMichael Chan __le16 req_type; 44663322479eSMichael Chan __le16 cmpl_ring; 44673322479eSMichael Chan __le16 seq_id; 44683322479eSMichael Chan __le16 target_id; 44693322479eSMichael Chan __le64 resp_addr; 44703322479eSMichael Chan __le32 unused_0[2]; 44713322479eSMichael Chan __le16 port_id; 44723322479eSMichael Chan u8 phy_addr; 44733322479eSMichael Chan u8 dev_addr; 44743322479eSMichael Chan __le16 reg_addr; 44753322479eSMichael Chan u8 cl45_mdio; 44763322479eSMichael Chan u8 unused_1; 44773322479eSMichael Chan }; 44783322479eSMichael Chan 44793322479eSMichael Chan /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 44803322479eSMichael Chan struct hwrm_port_phy_mdio_read_output { 44813322479eSMichael Chan __le16 error_code; 44823322479eSMichael Chan __le16 req_type; 44833322479eSMichael Chan __le16 seq_id; 44843322479eSMichael Chan __le16 resp_len; 44853322479eSMichael Chan __le16 reg_data; 44863322479eSMichael Chan u8 unused_0[5]; 44873322479eSMichael Chan u8 valid; 44883322479eSMichael Chan }; 44893322479eSMichael Chan 4490894aa69aSMichael Chan /* hwrm_port_led_cfg_input (size:512b/64B) */ 4491f183886cSMichael Chan struct hwrm_port_led_cfg_input { 4492f183886cSMichael Chan __le16 req_type; 4493f183886cSMichael Chan __le16 cmpl_ring; 4494f183886cSMichael Chan __le16 seq_id; 4495f183886cSMichael Chan __le16 target_id; 4496f183886cSMichael Chan __le64 resp_addr; 4497f183886cSMichael Chan __le32 enables; 4498f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 4499f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 4500f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 4501f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 4502f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 4503f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 4504f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 4505f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 4506f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 4507f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 4508f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 4509f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 4510f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 4511f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 4512f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 4513f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 4514f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 4515f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 4516f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 4517f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 4518f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 4519f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 4520f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 4521f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 4522f183886cSMichael Chan __le16 port_id; 4523f183886cSMichael Chan u8 num_leds; 4524f183886cSMichael Chan u8 rsvd; 4525f183886cSMichael Chan u8 led0_id; 4526f183886cSMichael Chan u8 led0_state; 4527f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 4528f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 4529f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 4530f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 4531f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 4532894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 4533f183886cSMichael Chan u8 led0_color; 4534f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 4535f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 4536f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 4537f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 4538894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 4539f183886cSMichael Chan u8 unused_0; 4540f183886cSMichael Chan __le16 led0_blink_on; 4541f183886cSMichael Chan __le16 led0_blink_off; 4542f183886cSMichael Chan u8 led0_group_id; 4543f183886cSMichael Chan u8 rsvd0; 4544f183886cSMichael Chan u8 led1_id; 4545f183886cSMichael Chan u8 led1_state; 4546f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 4547f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 4548f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 4549f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 4550f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 4551894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 4552f183886cSMichael Chan u8 led1_color; 4553f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 4554f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 4555f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 4556f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 4557894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 4558f183886cSMichael Chan u8 unused_1; 4559f183886cSMichael Chan __le16 led1_blink_on; 4560f183886cSMichael Chan __le16 led1_blink_off; 4561f183886cSMichael Chan u8 led1_group_id; 4562f183886cSMichael Chan u8 rsvd1; 4563f183886cSMichael Chan u8 led2_id; 4564f183886cSMichael Chan u8 led2_state; 4565f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 4566f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 4567f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 4568f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 4569f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 4570894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 4571f183886cSMichael Chan u8 led2_color; 4572f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 4573f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 4574f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 4575f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 4576894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 4577f183886cSMichael Chan u8 unused_2; 4578f183886cSMichael Chan __le16 led2_blink_on; 4579f183886cSMichael Chan __le16 led2_blink_off; 4580f183886cSMichael Chan u8 led2_group_id; 4581f183886cSMichael Chan u8 rsvd2; 4582f183886cSMichael Chan u8 led3_id; 4583f183886cSMichael Chan u8 led3_state; 4584f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 4585f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 4586f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 4587f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 4588f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 4589894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 4590f183886cSMichael Chan u8 led3_color; 4591f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 4592f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 4593f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 4594f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 4595894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 4596f183886cSMichael Chan u8 unused_3; 4597f183886cSMichael Chan __le16 led3_blink_on; 4598f183886cSMichael Chan __le16 led3_blink_off; 4599f183886cSMichael Chan u8 led3_group_id; 4600f183886cSMichael Chan u8 rsvd3; 4601f183886cSMichael Chan }; 4602f183886cSMichael Chan 4603894aa69aSMichael Chan /* hwrm_port_led_cfg_output (size:128b/16B) */ 4604f183886cSMichael Chan struct hwrm_port_led_cfg_output { 4605f183886cSMichael Chan __le16 error_code; 4606f183886cSMichael Chan __le16 req_type; 4607f183886cSMichael Chan __le16 seq_id; 4608f183886cSMichael Chan __le16 resp_len; 4609894aa69aSMichael Chan u8 unused_0[7]; 4610f183886cSMichael Chan u8 valid; 4611f183886cSMichael Chan }; 4612f183886cSMichael Chan 4613894aa69aSMichael Chan /* hwrm_port_led_qcfg_input (size:192b/24B) */ 4614894aa69aSMichael Chan struct hwrm_port_led_qcfg_input { 4615894aa69aSMichael Chan __le16 req_type; 4616894aa69aSMichael Chan __le16 cmpl_ring; 4617894aa69aSMichael Chan __le16 seq_id; 4618894aa69aSMichael Chan __le16 target_id; 4619894aa69aSMichael Chan __le64 resp_addr; 4620894aa69aSMichael Chan __le16 port_id; 4621894aa69aSMichael Chan u8 unused_0[6]; 4622894aa69aSMichael Chan }; 4623894aa69aSMichael Chan 4624894aa69aSMichael Chan /* hwrm_port_led_qcfg_output (size:448b/56B) */ 4625894aa69aSMichael Chan struct hwrm_port_led_qcfg_output { 4626894aa69aSMichael Chan __le16 error_code; 4627894aa69aSMichael Chan __le16 req_type; 4628894aa69aSMichael Chan __le16 seq_id; 4629894aa69aSMichael Chan __le16 resp_len; 4630894aa69aSMichael Chan u8 num_leds; 4631894aa69aSMichael Chan u8 led0_id; 4632894aa69aSMichael Chan u8 led0_type; 4633894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 4634894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 4635894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 4636894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 4637894aa69aSMichael Chan u8 led0_state; 4638894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 4639894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 4640894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 4641894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 4642894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 4643894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 4644894aa69aSMichael Chan u8 led0_color; 4645894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 4646894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 4647894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 4648894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 4649894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 4650894aa69aSMichael Chan u8 unused_0; 4651894aa69aSMichael Chan __le16 led0_blink_on; 4652894aa69aSMichael Chan __le16 led0_blink_off; 4653894aa69aSMichael Chan u8 led0_group_id; 4654894aa69aSMichael Chan u8 led1_id; 4655894aa69aSMichael Chan u8 led1_type; 4656894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 4657894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 4658894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 4659894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 4660894aa69aSMichael Chan u8 led1_state; 4661894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 4662894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 4663894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 4664894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 4665894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 4666894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 4667894aa69aSMichael Chan u8 led1_color; 4668894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 4669894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 4670894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 4671894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 4672894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 4673894aa69aSMichael Chan u8 unused_1; 4674894aa69aSMichael Chan __le16 led1_blink_on; 4675894aa69aSMichael Chan __le16 led1_blink_off; 4676894aa69aSMichael Chan u8 led1_group_id; 4677894aa69aSMichael Chan u8 led2_id; 4678894aa69aSMichael Chan u8 led2_type; 4679894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 4680894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 4681894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 4682894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 4683894aa69aSMichael Chan u8 led2_state; 4684894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 4685894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 4686894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 4687894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 4688894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 4689894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 4690894aa69aSMichael Chan u8 led2_color; 4691894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 4692894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 4693894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 4694894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 4695894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 4696894aa69aSMichael Chan u8 unused_2; 4697894aa69aSMichael Chan __le16 led2_blink_on; 4698894aa69aSMichael Chan __le16 led2_blink_off; 4699894aa69aSMichael Chan u8 led2_group_id; 4700894aa69aSMichael Chan u8 led3_id; 4701894aa69aSMichael Chan u8 led3_type; 4702894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 4703894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 4704894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 4705894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 4706894aa69aSMichael Chan u8 led3_state; 4707894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4708894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4709894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4710894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4711894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4712894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4713894aa69aSMichael Chan u8 led3_color; 4714894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4715894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4716894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4717894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4718894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4719894aa69aSMichael Chan u8 unused_3; 4720894aa69aSMichael Chan __le16 led3_blink_on; 4721894aa69aSMichael Chan __le16 led3_blink_off; 4722894aa69aSMichael Chan u8 led3_group_id; 4723894aa69aSMichael Chan u8 unused_4[6]; 4724894aa69aSMichael Chan u8 valid; 4725894aa69aSMichael Chan }; 4726894aa69aSMichael Chan 4727894aa69aSMichael Chan /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4728f183886cSMichael Chan struct hwrm_port_led_qcaps_input { 4729f183886cSMichael Chan __le16 req_type; 4730f183886cSMichael Chan __le16 cmpl_ring; 4731f183886cSMichael Chan __le16 seq_id; 4732f183886cSMichael Chan __le16 target_id; 4733f183886cSMichael Chan __le64 resp_addr; 4734f183886cSMichael Chan __le16 port_id; 4735894aa69aSMichael Chan u8 unused_0[6]; 4736f183886cSMichael Chan }; 4737f183886cSMichael Chan 4738894aa69aSMichael Chan /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4739f183886cSMichael Chan struct hwrm_port_led_qcaps_output { 4740f183886cSMichael Chan __le16 error_code; 4741f183886cSMichael Chan __le16 req_type; 4742f183886cSMichael Chan __le16 seq_id; 4743f183886cSMichael Chan __le16 resp_len; 4744f183886cSMichael Chan u8 num_leds; 4745894aa69aSMichael Chan u8 unused[3]; 4746f183886cSMichael Chan u8 led0_id; 4747f183886cSMichael Chan u8 led0_type; 4748f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4749f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4750f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4751894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4752f183886cSMichael Chan u8 led0_group_id; 4753894aa69aSMichael Chan u8 unused_0; 4754f183886cSMichael Chan __le16 led0_state_caps; 4755f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4756f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4757f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4758f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4759f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4760f183886cSMichael Chan __le16 led0_color_caps; 4761f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4762f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4763f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4764f183886cSMichael Chan u8 led1_id; 4765f183886cSMichael Chan u8 led1_type; 4766f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4767f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4768f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4769894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4770f183886cSMichael Chan u8 led1_group_id; 4771894aa69aSMichael Chan u8 unused_1; 4772f183886cSMichael Chan __le16 led1_state_caps; 4773f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4774f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4775f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4776f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4777f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4778f183886cSMichael Chan __le16 led1_color_caps; 4779f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4780f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4781f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4782f183886cSMichael Chan u8 led2_id; 4783f183886cSMichael Chan u8 led2_type; 4784f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4785f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4786f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4787894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4788f183886cSMichael Chan u8 led2_group_id; 4789894aa69aSMichael Chan u8 unused_2; 4790f183886cSMichael Chan __le16 led2_state_caps; 4791f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4792f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4793f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4794f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4795f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4796f183886cSMichael Chan __le16 led2_color_caps; 4797f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4798f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4799f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4800f183886cSMichael Chan u8 led3_id; 4801f183886cSMichael Chan u8 led3_type; 4802f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4803f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4804f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4805894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4806f183886cSMichael Chan u8 led3_group_id; 4807894aa69aSMichael Chan u8 unused_3; 4808f183886cSMichael Chan __le16 led3_state_caps; 4809f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4810f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4811f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4812f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4813f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4814f183886cSMichael Chan __le16 led3_color_caps; 4815f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4816f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4817f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4818894aa69aSMichael Chan u8 unused_4[3]; 4819f183886cSMichael Chan u8 valid; 4820f183886cSMichael Chan }; 4821f183886cSMichael Chan 4822894aa69aSMichael Chan /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4823c0c050c5SMichael Chan struct hwrm_queue_qportcfg_input { 4824c0c050c5SMichael Chan __le16 req_type; 4825c0c050c5SMichael Chan __le16 cmpl_ring; 4826c0c050c5SMichael Chan __le16 seq_id; 4827c0c050c5SMichael Chan __le16 target_id; 4828c0c050c5SMichael Chan __le64 resp_addr; 4829c0c050c5SMichael Chan __le32 flags; 4830c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4831441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4832441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 483311f15ed3SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4834c0c050c5SMichael Chan __le16 port_id; 4835d4f52de0SMichael Chan u8 drv_qmap_cap; 4836d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4837d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4838d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4839d4f52de0SMichael Chan u8 unused_0; 4840c0c050c5SMichael Chan }; 4841c0c050c5SMichael Chan 4842bfc6e5fbSMichael Chan /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4843c0c050c5SMichael Chan struct hwrm_queue_qportcfg_output { 4844c0c050c5SMichael Chan __le16 error_code; 4845c0c050c5SMichael Chan __le16 req_type; 4846c0c050c5SMichael Chan __le16 seq_id; 4847c0c050c5SMichael Chan __le16 resp_len; 4848c0c050c5SMichael Chan u8 max_configurable_queues; 4849c0c050c5SMichael Chan u8 max_configurable_lossless_queues; 4850c0c050c5SMichael Chan u8 queue_cfg_allowed; 4851441cabbbSMichael Chan u8 queue_cfg_info; 4852441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 485378eeadb8SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 4854c0c050c5SMichael Chan u8 queue_pfcenable_cfg_allowed; 4855c0c050c5SMichael Chan u8 queue_pri2cos_cfg_allowed; 4856c0c050c5SMichael Chan u8 queue_cos2bw_cfg_allowed; 4857c0c050c5SMichael Chan u8 queue_id0; 4858c0c050c5SMichael Chan u8 queue_id0_service_profile; 4859441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 48606fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4861d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4862d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4863d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4864441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4865894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4866c0c050c5SMichael Chan u8 queue_id1; 4867c0c050c5SMichael Chan u8 queue_id1_service_profile; 4868441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 48696fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4870d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4871d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4872d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4873441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4874894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4875c0c050c5SMichael Chan u8 queue_id2; 4876c0c050c5SMichael Chan u8 queue_id2_service_profile; 4877441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 48786fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4879d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4880d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4881d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4882441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4883894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4884c0c050c5SMichael Chan u8 queue_id3; 4885c0c050c5SMichael Chan u8 queue_id3_service_profile; 4886441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 48876fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4888d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4889d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4890d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4891441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4892894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4893c0c050c5SMichael Chan u8 queue_id4; 4894c0c050c5SMichael Chan u8 queue_id4_service_profile; 4895441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 48966fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4897d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4898d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4899d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4900441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4901894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4902c0c050c5SMichael Chan u8 queue_id5; 4903c0c050c5SMichael Chan u8 queue_id5_service_profile; 4904441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 49056fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4906d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4907d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4908d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4909441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4910894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4911c0c050c5SMichael Chan u8 queue_id6; 4912c0c050c5SMichael Chan u8 queue_id6_service_profile; 4913441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 49146fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4915d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4916d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4917d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4918441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4919894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4920c0c050c5SMichael Chan u8 queue_id7; 4921c0c050c5SMichael Chan u8 queue_id7_service_profile; 4922441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 49236fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4924d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4925d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4926d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4927441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4928894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 492916db6323SMichael Chan u8 queue_id0_service_profile_type; 493016db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 493116db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 493216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4933bfc6e5fbSMichael Chan char qid0_name[16]; 4934bfc6e5fbSMichael Chan char qid1_name[16]; 4935bfc6e5fbSMichael Chan char qid2_name[16]; 4936bfc6e5fbSMichael Chan char qid3_name[16]; 4937bfc6e5fbSMichael Chan char qid4_name[16]; 4938bfc6e5fbSMichael Chan char qid5_name[16]; 4939bfc6e5fbSMichael Chan char qid6_name[16]; 4940bfc6e5fbSMichael Chan char qid7_name[16]; 494116db6323SMichael Chan u8 queue_id1_service_profile_type; 494216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 494316db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 494416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 494516db6323SMichael Chan u8 queue_id2_service_profile_type; 494616db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 494716db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 494816db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 494916db6323SMichael Chan u8 queue_id3_service_profile_type; 495016db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 495116db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 495216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 495316db6323SMichael Chan u8 queue_id4_service_profile_type; 495416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 495516db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 495616db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 495716db6323SMichael Chan u8 queue_id5_service_profile_type; 495816db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 495916db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 496016db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 496116db6323SMichael Chan u8 queue_id6_service_profile_type; 496216db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 496316db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 496416db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 496516db6323SMichael Chan u8 queue_id7_service_profile_type; 496616db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 496716db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 496816db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4969bfc6e5fbSMichael Chan u8 valid; 4970bfc6e5fbSMichael Chan }; 4971bfc6e5fbSMichael Chan 4972bfc6e5fbSMichael Chan /* hwrm_queue_qcfg_input (size:192b/24B) */ 4973bfc6e5fbSMichael Chan struct hwrm_queue_qcfg_input { 4974bfc6e5fbSMichael Chan __le16 req_type; 4975bfc6e5fbSMichael Chan __le16 cmpl_ring; 4976bfc6e5fbSMichael Chan __le16 seq_id; 4977bfc6e5fbSMichael Chan __le16 target_id; 4978bfc6e5fbSMichael Chan __le64 resp_addr; 4979bfc6e5fbSMichael Chan __le32 flags; 4980bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4981bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4982bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4983bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4984bfc6e5fbSMichael Chan __le32 queue_id; 4985bfc6e5fbSMichael Chan }; 4986bfc6e5fbSMichael Chan 4987bfc6e5fbSMichael Chan /* hwrm_queue_qcfg_output (size:128b/16B) */ 4988bfc6e5fbSMichael Chan struct hwrm_queue_qcfg_output { 4989bfc6e5fbSMichael Chan __le16 error_code; 4990bfc6e5fbSMichael Chan __le16 req_type; 4991bfc6e5fbSMichael Chan __le16 seq_id; 4992bfc6e5fbSMichael Chan __le16 resp_len; 4993bfc6e5fbSMichael Chan __le32 queue_len; 4994bfc6e5fbSMichael Chan u8 service_profile; 4995bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4996bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4997bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4998bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4999bfc6e5fbSMichael Chan u8 queue_cfg_info; 5000bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5001bfc6e5fbSMichael Chan u8 unused_0; 5002c0c050c5SMichael Chan u8 valid; 5003c0c050c5SMichael Chan }; 5004c0c050c5SMichael Chan 5005894aa69aSMichael Chan /* hwrm_queue_cfg_input (size:320b/40B) */ 5006c0c050c5SMichael Chan struct hwrm_queue_cfg_input { 5007c0c050c5SMichael Chan __le16 req_type; 5008c0c050c5SMichael Chan __le16 cmpl_ring; 5009c0c050c5SMichael Chan __le16 seq_id; 5010c0c050c5SMichael Chan __le16 target_id; 5011c0c050c5SMichael Chan __le64 resp_addr; 5012c0c050c5SMichael Chan __le32 flags; 5013441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5014441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 5015441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 5016441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 5017441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5018441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 5019c0c050c5SMichael Chan __le32 enables; 5020c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 5021c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 5022c0c050c5SMichael Chan __le32 queue_id; 5023c0c050c5SMichael Chan __le32 dflt_len; 5024c0c050c5SMichael Chan u8 service_profile; 5025441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 5026441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 5027441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 5028894aa69aSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 5029c0c050c5SMichael Chan u8 unused_0[7]; 5030c0c050c5SMichael Chan }; 5031c0c050c5SMichael Chan 5032894aa69aSMichael Chan /* hwrm_queue_cfg_output (size:128b/16B) */ 5033c0c050c5SMichael Chan struct hwrm_queue_cfg_output { 5034c0c050c5SMichael Chan __le16 error_code; 5035c0c050c5SMichael Chan __le16 req_type; 5036c0c050c5SMichael Chan __le16 seq_id; 5037c0c050c5SMichael Chan __le16 resp_len; 5038894aa69aSMichael Chan u8 unused_0[7]; 5039c0c050c5SMichael Chan u8 valid; 5040c0c050c5SMichael Chan }; 5041c0c050c5SMichael Chan 5042894aa69aSMichael Chan /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 504387c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_input { 504487c374deSMichael Chan __le16 req_type; 504587c374deSMichael Chan __le16 cmpl_ring; 504687c374deSMichael Chan __le16 seq_id; 504787c374deSMichael Chan __le16 target_id; 504887c374deSMichael Chan __le64 resp_addr; 504987c374deSMichael Chan __le16 port_id; 5050894aa69aSMichael Chan u8 unused_0[6]; 505187c374deSMichael Chan }; 505287c374deSMichael Chan 5053894aa69aSMichael Chan /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 505487c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_output { 505587c374deSMichael Chan __le16 error_code; 505687c374deSMichael Chan __le16 req_type; 505787c374deSMichael Chan __le16 seq_id; 505887c374deSMichael Chan __le16 resp_len; 505987c374deSMichael Chan __le32 flags; 506087c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 506187c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 506287c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 506387c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 506487c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 506587c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 506687c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 506787c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 5068460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5069460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5070460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5071460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5072460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5073460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5074460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5075460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5076894aa69aSMichael Chan u8 unused_0[3]; 507787c374deSMichael Chan u8 valid; 507887c374deSMichael Chan }; 507987c374deSMichael Chan 5080894aa69aSMichael Chan /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 5081c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_input { 5082c0c050c5SMichael Chan __le16 req_type; 5083c0c050c5SMichael Chan __le16 cmpl_ring; 5084c0c050c5SMichael Chan __le16 seq_id; 5085c0c050c5SMichael Chan __le16 target_id; 5086c0c050c5SMichael Chan __le64 resp_addr; 5087c193554eSMichael Chan __le32 flags; 5088c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 5089c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 5090c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 5091c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 5092c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 5093c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 5094c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 5095c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 5096460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 5097460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 5098460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 5099460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 5100460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 5101460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 5102460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 5103460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 5104c0c050c5SMichael Chan __le16 port_id; 5105894aa69aSMichael Chan u8 unused_0[2]; 5106c0c050c5SMichael Chan }; 5107c0c050c5SMichael Chan 5108894aa69aSMichael Chan /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 5109c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_output { 5110c0c050c5SMichael Chan __le16 error_code; 5111c0c050c5SMichael Chan __le16 req_type; 5112c0c050c5SMichael Chan __le16 seq_id; 5113c0c050c5SMichael Chan __le16 resp_len; 5114894aa69aSMichael Chan u8 unused_0[7]; 5115c0c050c5SMichael Chan u8 valid; 5116c0c050c5SMichael Chan }; 5117c0c050c5SMichael Chan 5118894aa69aSMichael Chan /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 511987c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_input { 512087c374deSMichael Chan __le16 req_type; 512187c374deSMichael Chan __le16 cmpl_ring; 512287c374deSMichael Chan __le16 seq_id; 512387c374deSMichael Chan __le16 target_id; 512487c374deSMichael Chan __le64 resp_addr; 512587c374deSMichael Chan __le32 flags; 512687c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 5127894aa69aSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 5128894aa69aSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 512987c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 513087c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 513187c374deSMichael Chan u8 port_id; 513287c374deSMichael Chan u8 unused_0[3]; 513387c374deSMichael Chan }; 513487c374deSMichael Chan 5135894aa69aSMichael Chan /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 513687c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_output { 513787c374deSMichael Chan __le16 error_code; 513887c374deSMichael Chan __le16 req_type; 513987c374deSMichael Chan __le16 seq_id; 514087c374deSMichael Chan __le16 resp_len; 514187c374deSMichael Chan u8 pri0_cos_queue_id; 514287c374deSMichael Chan u8 pri1_cos_queue_id; 514387c374deSMichael Chan u8 pri2_cos_queue_id; 514487c374deSMichael Chan u8 pri3_cos_queue_id; 514587c374deSMichael Chan u8 pri4_cos_queue_id; 514687c374deSMichael Chan u8 pri5_cos_queue_id; 514787c374deSMichael Chan u8 pri6_cos_queue_id; 514887c374deSMichael Chan u8 pri7_cos_queue_id; 514987c374deSMichael Chan u8 queue_cfg_info; 515087c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 5151894aa69aSMichael Chan u8 unused_0[6]; 515287c374deSMichael Chan u8 valid; 515387c374deSMichael Chan }; 515487c374deSMichael Chan 5155894aa69aSMichael Chan /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 5156c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_input { 5157c0c050c5SMichael Chan __le16 req_type; 5158c0c050c5SMichael Chan __le16 cmpl_ring; 5159c0c050c5SMichael Chan __le16 seq_id; 5160c0c050c5SMichael Chan __le16 target_id; 5161c0c050c5SMichael Chan __le64 resp_addr; 5162c0c050c5SMichael Chan __le32 flags; 5163441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 5164441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 5165894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 5166894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 5167894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 5168441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 5169441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 5170c0c050c5SMichael Chan __le32 enables; 5171441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 5172441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 5173441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 5174441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 5175441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 5176441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 5177441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 5178441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 5179c0c050c5SMichael Chan u8 port_id; 5180c193554eSMichael Chan u8 pri0_cos_queue_id; 5181c193554eSMichael Chan u8 pri1_cos_queue_id; 5182c193554eSMichael Chan u8 pri2_cos_queue_id; 5183c193554eSMichael Chan u8 pri3_cos_queue_id; 5184c193554eSMichael Chan u8 pri4_cos_queue_id; 5185c193554eSMichael Chan u8 pri5_cos_queue_id; 5186c193554eSMichael Chan u8 pri6_cos_queue_id; 5187c193554eSMichael Chan u8 pri7_cos_queue_id; 5188c0c050c5SMichael Chan u8 unused_0[7]; 5189c0c050c5SMichael Chan }; 5190c0c050c5SMichael Chan 5191894aa69aSMichael Chan /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 5192c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_output { 5193c0c050c5SMichael Chan __le16 error_code; 5194c0c050c5SMichael Chan __le16 req_type; 5195c0c050c5SMichael Chan __le16 seq_id; 5196c0c050c5SMichael Chan __le16 resp_len; 5197894aa69aSMichael Chan u8 unused_0[7]; 5198c0c050c5SMichael Chan u8 valid; 5199c0c050c5SMichael Chan }; 5200c0c050c5SMichael Chan 5201894aa69aSMichael Chan /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 520287c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_input { 520387c374deSMichael Chan __le16 req_type; 520487c374deSMichael Chan __le16 cmpl_ring; 520587c374deSMichael Chan __le16 seq_id; 520687c374deSMichael Chan __le16 target_id; 520787c374deSMichael Chan __le64 resp_addr; 520887c374deSMichael Chan __le16 port_id; 5209894aa69aSMichael Chan u8 unused_0[6]; 521087c374deSMichael Chan }; 521187c374deSMichael Chan 5212894aa69aSMichael Chan /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 521387c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_output { 521487c374deSMichael Chan __le16 error_code; 521587c374deSMichael Chan __le16 req_type; 521687c374deSMichael Chan __le16 seq_id; 521787c374deSMichael Chan __le16 resp_len; 521887c374deSMichael Chan u8 queue_id0; 521987c374deSMichael Chan u8 unused_0; 522087c374deSMichael Chan __le16 unused_1; 522187c374deSMichael Chan __le32 queue_id0_min_bw; 522287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 522387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5224bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5225bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5226bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5227bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 522887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 522987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5230bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5231bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5232bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5233bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 523487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 523587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 523687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 523787c374deSMichael Chan __le32 queue_id0_max_bw; 523887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 523987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5240bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5241bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5242bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5243bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 524487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 524587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5246bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5247bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5248bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5249bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 525087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 525187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 525287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 525387c374deSMichael Chan u8 queue_id0_tsa_assign; 525487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 525587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 525687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 525787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 525887c374deSMichael Chan u8 queue_id0_pri_lvl; 525987c374deSMichael Chan u8 queue_id0_bw_weight; 526087c374deSMichael Chan u8 queue_id1; 526187c374deSMichael Chan __le32 queue_id1_min_bw; 526287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 526387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5264bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5265bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5266bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5267bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 526887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 526987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5270bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5271bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5272bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5273bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 527487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 527587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 527687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 527787c374deSMichael Chan __le32 queue_id1_max_bw; 527887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 527987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5280bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5281bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5282bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5283bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 528487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 528587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5286bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5287bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5288bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5289bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 529087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 529187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 529287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 529387c374deSMichael Chan u8 queue_id1_tsa_assign; 529487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 529587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 529687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 529787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 529887c374deSMichael Chan u8 queue_id1_pri_lvl; 529987c374deSMichael Chan u8 queue_id1_bw_weight; 530087c374deSMichael Chan u8 queue_id2; 530187c374deSMichael Chan __le32 queue_id2_min_bw; 530287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 530387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5304bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5305bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5306bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5307bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 530887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 530987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5310bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5311bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5312bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5313bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 531487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 531587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 531687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 531787c374deSMichael Chan __le32 queue_id2_max_bw; 531887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 531987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5320bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5321bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5322bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5323bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 532487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 532587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5326bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5327bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5328bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5329bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 533087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 533187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 533287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 533387c374deSMichael Chan u8 queue_id2_tsa_assign; 533487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 533587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 533687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 533787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 533887c374deSMichael Chan u8 queue_id2_pri_lvl; 533987c374deSMichael Chan u8 queue_id2_bw_weight; 534087c374deSMichael Chan u8 queue_id3; 534187c374deSMichael Chan __le32 queue_id3_min_bw; 534287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 534387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5344bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5345bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5346bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5347bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 534887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 534987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5350bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5351bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5352bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5353bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 535487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 535587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 535687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 535787c374deSMichael Chan __le32 queue_id3_max_bw; 535887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 535987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5360bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5361bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5362bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5363bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 536487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 536587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5366bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5367bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5368bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5369bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 537087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 537187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 537287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 537387c374deSMichael Chan u8 queue_id3_tsa_assign; 537487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 537587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 537687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 537787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 537887c374deSMichael Chan u8 queue_id3_pri_lvl; 537987c374deSMichael Chan u8 queue_id3_bw_weight; 538087c374deSMichael Chan u8 queue_id4; 538187c374deSMichael Chan __le32 queue_id4_min_bw; 538287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 538387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5384bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5385bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5386bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5387bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 538887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 538987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5390bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5391bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5392bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5393bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 539487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 539587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 539687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 539787c374deSMichael Chan __le32 queue_id4_max_bw; 539887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 539987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5400bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5401bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5402bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5403bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 540487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 540587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5406bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5407bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5408bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5409bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 541087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 541187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 541287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 541387c374deSMichael Chan u8 queue_id4_tsa_assign; 541487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 541587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 541687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 541787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 541887c374deSMichael Chan u8 queue_id4_pri_lvl; 541987c374deSMichael Chan u8 queue_id4_bw_weight; 542087c374deSMichael Chan u8 queue_id5; 542187c374deSMichael Chan __le32 queue_id5_min_bw; 542287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 542387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5424bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5425bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5426bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5427bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 542887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 542987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5430bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5431bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5432bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5433bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 543487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 543587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 543687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 543787c374deSMichael Chan __le32 queue_id5_max_bw; 543887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 543987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5440bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5441bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5442bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5443bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 544487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 544587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5446bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5447bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5448bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5449bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 545087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 545187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 545287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 545387c374deSMichael Chan u8 queue_id5_tsa_assign; 545487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 545587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 545687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 545787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 545887c374deSMichael Chan u8 queue_id5_pri_lvl; 545987c374deSMichael Chan u8 queue_id5_bw_weight; 546087c374deSMichael Chan u8 queue_id6; 546187c374deSMichael Chan __le32 queue_id6_min_bw; 546287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 546387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5464bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5465bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5466bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5467bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 546887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 546987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5470bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5471bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5472bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5473bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 547487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 547587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 547687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 547787c374deSMichael Chan __le32 queue_id6_max_bw; 547887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 547987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5480bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5481bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5482bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5483bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 548487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 548587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5486bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5487bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5488bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5489bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 549087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 549187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 549287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 549387c374deSMichael Chan u8 queue_id6_tsa_assign; 549487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 549587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 549687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 549787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 549887c374deSMichael Chan u8 queue_id6_pri_lvl; 549987c374deSMichael Chan u8 queue_id6_bw_weight; 550087c374deSMichael Chan u8 queue_id7; 550187c374deSMichael Chan __le32 queue_id7_min_bw; 550287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 550387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5504bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5505bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5506bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5507bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 550887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 550987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5510bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5511bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5512bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5513bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 551487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 551587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 551687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 551787c374deSMichael Chan __le32 queue_id7_max_bw; 551887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 551987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5520bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5521bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5522bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5523bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 552487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 552587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5526bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5527bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5528bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5529bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 553087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 553187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 553287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 553387c374deSMichael Chan u8 queue_id7_tsa_assign; 553487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 553587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 553687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 553787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 553887c374deSMichael Chan u8 queue_id7_pri_lvl; 553987c374deSMichael Chan u8 queue_id7_bw_weight; 5540894aa69aSMichael Chan u8 unused_2[4]; 554187c374deSMichael Chan u8 valid; 554287c374deSMichael Chan }; 554387c374deSMichael Chan 5544894aa69aSMichael Chan /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 5545c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_input { 5546c0c050c5SMichael Chan __le16 req_type; 5547c0c050c5SMichael Chan __le16 cmpl_ring; 5548c0c050c5SMichael Chan __le16 seq_id; 5549c0c050c5SMichael Chan __le16 target_id; 5550c0c050c5SMichael Chan __le64 resp_addr; 5551c0c050c5SMichael Chan __le32 flags; 5552c0c050c5SMichael Chan __le32 enables; 5553c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 5554c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 5555c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 5556c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 5557c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 5558c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 5559c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 5560c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 5561c0c050c5SMichael Chan __le16 port_id; 5562c0c050c5SMichael Chan u8 queue_id0; 5563c0c050c5SMichael Chan u8 unused_0; 5564c0c050c5SMichael Chan __le32 queue_id0_min_bw; 5565441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5566441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 5567bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 5568bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 5569bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 5570bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 5571441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5572441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 5573bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5574bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5575bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5576bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5577441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5578441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5579441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 5580c0c050c5SMichael Chan __le32 queue_id0_max_bw; 5581441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5582441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 5583bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 5584bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 5585bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 5586bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 5587441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5588441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 5589bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5590bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5591bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5592bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5593441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5594441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5595441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 5596c0c050c5SMichael Chan u8 queue_id0_tsa_assign; 5597441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 5598441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 5599441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5600441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 5601c0c050c5SMichael Chan u8 queue_id0_pri_lvl; 5602c0c050c5SMichael Chan u8 queue_id0_bw_weight; 5603c0c050c5SMichael Chan u8 queue_id1; 5604c0c050c5SMichael Chan __le32 queue_id1_min_bw; 5605441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5606441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 5607bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 5608bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 5609bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 5610bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 5611441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5612441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 5613bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5614bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5615bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5616bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5617441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5618441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5619441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 5620c0c050c5SMichael Chan __le32 queue_id1_max_bw; 5621441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5622441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 5623bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 5624bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 5625bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 5626bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 5627441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5628441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 5629bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5630bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5631bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5632bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5633441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5634441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5635441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 5636c0c050c5SMichael Chan u8 queue_id1_tsa_assign; 5637441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 5638441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 5639441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5640441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 5641c0c050c5SMichael Chan u8 queue_id1_pri_lvl; 5642c0c050c5SMichael Chan u8 queue_id1_bw_weight; 5643c0c050c5SMichael Chan u8 queue_id2; 5644c0c050c5SMichael Chan __le32 queue_id2_min_bw; 5645441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5646441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 5647bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 5648bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 5649bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 5650bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 5651441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5652441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 5653bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5654bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5655bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5656bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5657441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5658441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5659441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 5660c0c050c5SMichael Chan __le32 queue_id2_max_bw; 5661441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5662441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 5663bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 5664bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 5665bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 5666bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 5667441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5668441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 5669bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5670bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5671bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5672bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5673441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5674441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5675441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 5676c0c050c5SMichael Chan u8 queue_id2_tsa_assign; 5677441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 5678441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 5679441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5680441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 5681c0c050c5SMichael Chan u8 queue_id2_pri_lvl; 5682c0c050c5SMichael Chan u8 queue_id2_bw_weight; 5683c0c050c5SMichael Chan u8 queue_id3; 5684c0c050c5SMichael Chan __le32 queue_id3_min_bw; 5685441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5686441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 5687bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 5688bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 5689bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 5690bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 5691441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5692441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 5693bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5694bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5695bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5696bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5697441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5698441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5699441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 5700c0c050c5SMichael Chan __le32 queue_id3_max_bw; 5701441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5702441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 5703bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 5704bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 5705bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 5706bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 5707441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5708441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5709bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5710bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5711bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5712bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5713441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5714441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5715441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5716c0c050c5SMichael Chan u8 queue_id3_tsa_assign; 5717441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5718441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5719441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5720441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5721c0c050c5SMichael Chan u8 queue_id3_pri_lvl; 5722c0c050c5SMichael Chan u8 queue_id3_bw_weight; 5723c0c050c5SMichael Chan u8 queue_id4; 5724c0c050c5SMichael Chan __le32 queue_id4_min_bw; 5725441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5726441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5727bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5728bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5729bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5730bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5731441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5732441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5733bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5734bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5735bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5736bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5737441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5738441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5739441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5740c0c050c5SMichael Chan __le32 queue_id4_max_bw; 5741441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5742441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5743bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5744bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5745bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5746bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5747441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5748441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5749bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5750bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5751bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5752bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5753441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5754441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5755441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5756c0c050c5SMichael Chan u8 queue_id4_tsa_assign; 5757441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5758441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5759441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5760441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5761c0c050c5SMichael Chan u8 queue_id4_pri_lvl; 5762c0c050c5SMichael Chan u8 queue_id4_bw_weight; 5763c0c050c5SMichael Chan u8 queue_id5; 5764c0c050c5SMichael Chan __le32 queue_id5_min_bw; 5765441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5766441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5767bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5768bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5769bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5770bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5771441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5772441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5773bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5774bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5775bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5776bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5777441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5778441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5779441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5780c0c050c5SMichael Chan __le32 queue_id5_max_bw; 5781441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5782441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5783bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5784bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5785bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5786bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5787441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5788441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5789bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5790bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5791bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5792bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5793441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5794441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5795441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5796c0c050c5SMichael Chan u8 queue_id5_tsa_assign; 5797441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5798441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5799441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5800441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5801c0c050c5SMichael Chan u8 queue_id5_pri_lvl; 5802c0c050c5SMichael Chan u8 queue_id5_bw_weight; 5803c0c050c5SMichael Chan u8 queue_id6; 5804c0c050c5SMichael Chan __le32 queue_id6_min_bw; 5805441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5806441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5807bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5808bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5809bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5810bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5811441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5812441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5813bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5814bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5815bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5816bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5817441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5818441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5819441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5820c0c050c5SMichael Chan __le32 queue_id6_max_bw; 5821441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5822441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5823bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5824bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5825bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5826bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5827441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5828441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5829bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5830bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5831bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5832bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5833441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5834441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5835441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5836c0c050c5SMichael Chan u8 queue_id6_tsa_assign; 5837441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5838441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5839441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5840441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5841c0c050c5SMichael Chan u8 queue_id6_pri_lvl; 5842c0c050c5SMichael Chan u8 queue_id6_bw_weight; 5843c0c050c5SMichael Chan u8 queue_id7; 5844c0c050c5SMichael Chan __le32 queue_id7_min_bw; 5845441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5846441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5847bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5848bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5849bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5850bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5851441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5852441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5853bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5854bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5855bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5856bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5857441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5858441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5859441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5860c0c050c5SMichael Chan __le32 queue_id7_max_bw; 5861441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5862441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5863bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5864bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5865bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5866bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5867441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5868441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5869bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5870bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5871bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5872bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5873441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5874441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5875441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5876c0c050c5SMichael Chan u8 queue_id7_tsa_assign; 5877441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5878441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5879441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5880441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5881c0c050c5SMichael Chan u8 queue_id7_pri_lvl; 5882c0c050c5SMichael Chan u8 queue_id7_bw_weight; 5883c0c050c5SMichael Chan u8 unused_1[5]; 5884c0c050c5SMichael Chan }; 5885c0c050c5SMichael Chan 5886894aa69aSMichael Chan /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5887c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_output { 5888c0c050c5SMichael Chan __le16 error_code; 5889c0c050c5SMichael Chan __le16 req_type; 5890c0c050c5SMichael Chan __le16 seq_id; 5891c0c050c5SMichael Chan __le16 resp_len; 5892894aa69aSMichael Chan u8 unused_0[7]; 5893c0c050c5SMichael Chan u8 valid; 5894c0c050c5SMichael Chan }; 5895c0c050c5SMichael Chan 5896894aa69aSMichael Chan /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5897acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_input { 5898acb20054SMichael Chan __le16 req_type; 5899acb20054SMichael Chan __le16 cmpl_ring; 5900acb20054SMichael Chan __le16 seq_id; 5901acb20054SMichael Chan __le16 target_id; 5902acb20054SMichael Chan __le64 resp_addr; 5903acb20054SMichael Chan u8 port_id; 5904acb20054SMichael Chan u8 unused_0[7]; 5905acb20054SMichael Chan }; 5906acb20054SMichael Chan 5907894aa69aSMichael Chan /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5908acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_output { 5909acb20054SMichael Chan __le16 error_code; 5910acb20054SMichael Chan __le16 req_type; 5911acb20054SMichael Chan __le16 seq_id; 5912acb20054SMichael Chan __le16 resp_len; 5913acb20054SMichael Chan u8 num_dscp_bits; 5914acb20054SMichael Chan u8 unused_0; 5915acb20054SMichael Chan __le16 max_entries; 5916894aa69aSMichael Chan u8 unused_1[3]; 5917acb20054SMichael Chan u8 valid; 5918acb20054SMichael Chan }; 5919acb20054SMichael Chan 5920894aa69aSMichael Chan /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5921acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_input { 5922acb20054SMichael Chan __le16 req_type; 5923acb20054SMichael Chan __le16 cmpl_ring; 5924acb20054SMichael Chan __le16 seq_id; 5925acb20054SMichael Chan __le16 target_id; 5926acb20054SMichael Chan __le64 resp_addr; 5927acb20054SMichael Chan __le64 dest_data_addr; 5928acb20054SMichael Chan u8 port_id; 5929acb20054SMichael Chan u8 unused_0; 5930acb20054SMichael Chan __le16 dest_data_buffer_size; 5931894aa69aSMichael Chan u8 unused_1[4]; 5932acb20054SMichael Chan }; 5933acb20054SMichael Chan 5934894aa69aSMichael Chan /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5935acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_output { 5936acb20054SMichael Chan __le16 error_code; 5937acb20054SMichael Chan __le16 req_type; 5938acb20054SMichael Chan __le16 seq_id; 5939acb20054SMichael Chan __le16 resp_len; 5940acb20054SMichael Chan __le16 entry_cnt; 5941acb20054SMichael Chan u8 default_pri; 5942894aa69aSMichael Chan u8 unused_0[4]; 5943acb20054SMichael Chan u8 valid; 5944acb20054SMichael Chan }; 5945acb20054SMichael Chan 5946894aa69aSMichael Chan /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5947acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_input { 5948acb20054SMichael Chan __le16 req_type; 5949acb20054SMichael Chan __le16 cmpl_ring; 5950acb20054SMichael Chan __le16 seq_id; 5951acb20054SMichael Chan __le16 target_id; 5952acb20054SMichael Chan __le64 resp_addr; 5953acb20054SMichael Chan __le64 src_data_addr; 5954acb20054SMichael Chan __le32 flags; 5955acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5956acb20054SMichael Chan __le32 enables; 5957acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5958acb20054SMichael Chan u8 port_id; 5959acb20054SMichael Chan u8 default_pri; 5960acb20054SMichael Chan __le16 entry_cnt; 5961894aa69aSMichael Chan u8 unused_0[4]; 5962acb20054SMichael Chan }; 5963acb20054SMichael Chan 5964894aa69aSMichael Chan /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5965acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_output { 5966acb20054SMichael Chan __le16 error_code; 5967acb20054SMichael Chan __le16 req_type; 5968acb20054SMichael Chan __le16 seq_id; 5969acb20054SMichael Chan __le16 resp_len; 5970894aa69aSMichael Chan u8 unused_0[7]; 5971acb20054SMichael Chan u8 valid; 5972acb20054SMichael Chan }; 5973acb20054SMichael Chan 5974894aa69aSMichael Chan /* hwrm_vnic_alloc_input (size:192b/24B) */ 5975c0c050c5SMichael Chan struct hwrm_vnic_alloc_input { 5976c0c050c5SMichael Chan __le16 req_type; 5977c0c050c5SMichael Chan __le16 cmpl_ring; 5978c0c050c5SMichael Chan __le16 seq_id; 5979c0c050c5SMichael Chan __le16 target_id; 5980c0c050c5SMichael Chan __le64 resp_addr; 5981c0c050c5SMichael Chan __le32 flags; 5982c0c050c5SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 598316db6323SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 598416db6323SMichael Chan __le16 virtio_net_fid; 598516db6323SMichael Chan u8 unused_0[2]; 5986c0c050c5SMichael Chan }; 5987c0c050c5SMichael Chan 5988894aa69aSMichael Chan /* hwrm_vnic_alloc_output (size:128b/16B) */ 5989c0c050c5SMichael Chan struct hwrm_vnic_alloc_output { 5990c0c050c5SMichael Chan __le16 error_code; 5991c0c050c5SMichael Chan __le16 req_type; 5992c0c050c5SMichael Chan __le16 seq_id; 5993c0c050c5SMichael Chan __le16 resp_len; 5994c0c050c5SMichael Chan __le32 vnic_id; 5995894aa69aSMichael Chan u8 unused_0[3]; 5996c0c050c5SMichael Chan u8 valid; 5997c0c050c5SMichael Chan }; 5998c0c050c5SMichael Chan 5999894aa69aSMichael Chan /* hwrm_vnic_free_input (size:192b/24B) */ 6000c0c050c5SMichael Chan struct hwrm_vnic_free_input { 6001c0c050c5SMichael Chan __le16 req_type; 6002c0c050c5SMichael Chan __le16 cmpl_ring; 6003c0c050c5SMichael Chan __le16 seq_id; 6004c0c050c5SMichael Chan __le16 target_id; 6005c0c050c5SMichael Chan __le64 resp_addr; 6006c0c050c5SMichael Chan __le32 vnic_id; 6007894aa69aSMichael Chan u8 unused_0[4]; 6008c0c050c5SMichael Chan }; 6009c0c050c5SMichael Chan 6010894aa69aSMichael Chan /* hwrm_vnic_free_output (size:128b/16B) */ 6011c0c050c5SMichael Chan struct hwrm_vnic_free_output { 6012c0c050c5SMichael Chan __le16 error_code; 6013c0c050c5SMichael Chan __le16 req_type; 6014c0c050c5SMichael Chan __le16 seq_id; 6015c0c050c5SMichael Chan __le16 resp_len; 6016894aa69aSMichael Chan u8 unused_0[7]; 6017c0c050c5SMichael Chan u8 valid; 6018c0c050c5SMichael Chan }; 6019c0c050c5SMichael Chan 602072e0c9f9SMichael Chan /* hwrm_vnic_cfg_input (size:384b/48B) */ 6021c0c050c5SMichael Chan struct hwrm_vnic_cfg_input { 6022c0c050c5SMichael Chan __le16 req_type; 6023c0c050c5SMichael Chan __le16 cmpl_ring; 6024c0c050c5SMichael Chan __le16 seq_id; 6025c0c050c5SMichael Chan __le16 target_id; 6026c0c050c5SMichael Chan __le64 resp_addr; 6027c0c050c5SMichael Chan __le32 flags; 6028c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6029c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6030c193554eSMichael Chan #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 603111f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 603211f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6033441cabbbSMichael Chan #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 603457922b0aSMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6035c0c050c5SMichael Chan __le32 enables; 6036c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6037c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6038c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6039c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6040c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 60416fc92c33SMichael Chan #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 60426fc92c33SMichael Chan #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 604372e0c9f9SMichael Chan #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6044bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6045c0c050c5SMichael Chan __le16 vnic_id; 6046c0c050c5SMichael Chan __le16 dflt_ring_grp; 6047c0c050c5SMichael Chan __le16 rss_rule; 6048c0c050c5SMichael Chan __le16 cos_rule; 6049c0c050c5SMichael Chan __le16 lb_rule; 6050c0c050c5SMichael Chan __le16 mru; 60516fc92c33SMichael Chan __le16 default_rx_ring_id; 60526fc92c33SMichael Chan __le16 default_cmpl_ring_id; 605372e0c9f9SMichael Chan __le16 queue_id; 6054bfc6e5fbSMichael Chan u8 rx_csum_v2_mode; 6055bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6056bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6057bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6058bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6059bfc6e5fbSMichael Chan u8 unused0[5]; 6060c0c050c5SMichael Chan }; 6061c0c050c5SMichael Chan 6062894aa69aSMichael Chan /* hwrm_vnic_cfg_output (size:128b/16B) */ 6063c0c050c5SMichael Chan struct hwrm_vnic_cfg_output { 6064c0c050c5SMichael Chan __le16 error_code; 6065c0c050c5SMichael Chan __le16 req_type; 6066c0c050c5SMichael Chan __le16 seq_id; 6067c0c050c5SMichael Chan __le16 resp_len; 6068894aa69aSMichael Chan u8 unused_0[7]; 6069c0c050c5SMichael Chan u8 valid; 6070c0c050c5SMichael Chan }; 6071c0c050c5SMichael Chan 6072894aa69aSMichael Chan /* hwrm_vnic_qcaps_input (size:192b/24B) */ 60738fdefd63SMichael Chan struct hwrm_vnic_qcaps_input { 60748fdefd63SMichael Chan __le16 req_type; 60758fdefd63SMichael Chan __le16 cmpl_ring; 60768fdefd63SMichael Chan __le16 seq_id; 60778fdefd63SMichael Chan __le16 target_id; 60788fdefd63SMichael Chan __le64 resp_addr; 60798fdefd63SMichael Chan __le32 enables; 6080894aa69aSMichael Chan u8 unused_0[4]; 60818fdefd63SMichael Chan }; 60828fdefd63SMichael Chan 6083894aa69aSMichael Chan /* hwrm_vnic_qcaps_output (size:192b/24B) */ 60848fdefd63SMichael Chan struct hwrm_vnic_qcaps_output { 60858fdefd63SMichael Chan __le16 error_code; 60868fdefd63SMichael Chan __le16 req_type; 60878fdefd63SMichael Chan __le16 seq_id; 60888fdefd63SMichael Chan __le16 resp_len; 60898fdefd63SMichael Chan __le16 mru; 6090894aa69aSMichael Chan u8 unused_0[2]; 60918fdefd63SMichael Chan __le32 flags; 6092bac9a7e0SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 60938fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 60948fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 60958fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 60968fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 60978fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6098894aa69aSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 60996fc92c33SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 610072e0c9f9SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6101bfc6e5fbSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 610216db6323SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 610316db6323SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 610431f67c2eSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 610578eeadb8SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6106*21e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6107*21e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_TOEPLITZ_CAP 0x8000UL 6108*21e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_XOR_CAP 0x10000UL 6109*21e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_FUNCTION_CHKSM_CAP 0x20000UL 6110*21e70778SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 61114a50ddc2SMichael Chan __le16 max_aggs_supported; 61124a50ddc2SMichael Chan u8 unused_1[5]; 61138fdefd63SMichael Chan u8 valid; 61148fdefd63SMichael Chan }; 61158fdefd63SMichael Chan 6116894aa69aSMichael Chan /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 6117c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_input { 6118c0c050c5SMichael Chan __le16 req_type; 6119c0c050c5SMichael Chan __le16 cmpl_ring; 6120c0c050c5SMichael Chan __le16 seq_id; 6121c0c050c5SMichael Chan __le16 target_id; 6122c0c050c5SMichael Chan __le64 resp_addr; 6123c0c050c5SMichael Chan __le32 flags; 6124c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 6125c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 6126c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 6127c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 6128c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 6129c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6130c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 6131c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 61324a50ddc2SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 6133c0c050c5SMichael Chan __le32 enables; 6134c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 6135c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 6136c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 6137c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 6138c0c050c5SMichael Chan __le16 vnic_id; 6139c0c050c5SMichael Chan __le16 max_agg_segs; 6140441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 6141441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 6142441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 6143441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 6144441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 6145894aa69aSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 6146c0c050c5SMichael Chan __le16 max_aggs; 6147441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 6148441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 6149441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 6150441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 6151441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 6152441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 6153894aa69aSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 6154894aa69aSMichael Chan u8 unused_0[2]; 6155c0c050c5SMichael Chan __le32 max_agg_timer; 6156c0c050c5SMichael Chan __le32 min_agg_len; 6157c0c050c5SMichael Chan }; 6158c0c050c5SMichael Chan 6159894aa69aSMichael Chan /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 6160c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_output { 6161c0c050c5SMichael Chan __le16 error_code; 6162c0c050c5SMichael Chan __le16 req_type; 6163c0c050c5SMichael Chan __le16 seq_id; 6164c0c050c5SMichael Chan __le16 resp_len; 6165894aa69aSMichael Chan u8 unused_0[7]; 6166c0c050c5SMichael Chan u8 valid; 6167c0c050c5SMichael Chan }; 6168c0c050c5SMichael Chan 6169894aa69aSMichael Chan /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 6170894aa69aSMichael Chan struct hwrm_vnic_tpa_qcfg_input { 6171894aa69aSMichael Chan __le16 req_type; 6172894aa69aSMichael Chan __le16 cmpl_ring; 6173894aa69aSMichael Chan __le16 seq_id; 6174894aa69aSMichael Chan __le16 target_id; 6175894aa69aSMichael Chan __le64 resp_addr; 6176894aa69aSMichael Chan __le16 vnic_id; 6177894aa69aSMichael Chan u8 unused_0[6]; 6178894aa69aSMichael Chan }; 6179894aa69aSMichael Chan 6180894aa69aSMichael Chan /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 6181894aa69aSMichael Chan struct hwrm_vnic_tpa_qcfg_output { 6182894aa69aSMichael Chan __le16 error_code; 6183894aa69aSMichael Chan __le16 req_type; 6184894aa69aSMichael Chan __le16 seq_id; 6185894aa69aSMichael Chan __le16 resp_len; 6186894aa69aSMichael Chan __le32 flags; 6187894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 6188894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 6189894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 6190894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 6191894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 6192894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 6193894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 6194894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 6195894aa69aSMichael Chan __le16 max_agg_segs; 6196894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 6197894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 6198894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 6199894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 6200894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 6201894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 6202894aa69aSMichael Chan __le16 max_aggs; 6203894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 6204894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 6205894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 6206894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 6207894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 6208894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 6209894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 6210894aa69aSMichael Chan __le32 max_agg_timer; 6211894aa69aSMichael Chan __le32 min_agg_len; 6212894aa69aSMichael Chan u8 unused_0[7]; 6213894aa69aSMichael Chan u8 valid; 6214894aa69aSMichael Chan }; 6215894aa69aSMichael Chan 6216894aa69aSMichael Chan /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 6217c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_input { 6218c0c050c5SMichael Chan __le16 req_type; 6219c0c050c5SMichael Chan __le16 cmpl_ring; 6220c0c050c5SMichael Chan __le16 seq_id; 6221c0c050c5SMichael Chan __le16 target_id; 6222c0c050c5SMichael Chan __le64 resp_addr; 6223c0c050c5SMichael Chan __le32 hash_type; 6224c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 6225c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 6226c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 6227c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 6228c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 6229c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 62306fc92c33SMichael Chan __le16 vnic_id; 62316fc92c33SMichael Chan u8 ring_table_pair_index; 62326fc92c33SMichael Chan u8 hash_mode_flags; 62336fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 62346fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 62356fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 62366fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 62376fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 6238c0c050c5SMichael Chan __le64 ring_grp_tbl_addr; 6239c0c050c5SMichael Chan __le64 hash_key_tbl_addr; 6240c0c050c5SMichael Chan __le16 rss_ctx_idx; 6241*21e70778SMichael Chan u8 flags; 6242*21e70778SMichael Chan #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 6243*21e70778SMichael Chan #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 6244*21e70778SMichael Chan u8 rss_hash_function; 6245*21e70778SMichael Chan #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_TOEPLITZ 0x0UL 6246*21e70778SMichael Chan #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_XOR 0x1UL 6247*21e70778SMichael Chan #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 0x2UL 6248*21e70778SMichael Chan #define VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_LAST VNIC_RSS_CFG_REQ_RSS_HASH_FUNCTION_CHECKSUM 6249*21e70778SMichael Chan u8 unused_1[4]; 6250c0c050c5SMichael Chan }; 6251c0c050c5SMichael Chan 6252894aa69aSMichael Chan /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 6253c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_output { 6254c0c050c5SMichael Chan __le16 error_code; 6255c0c050c5SMichael Chan __le16 req_type; 6256c0c050c5SMichael Chan __le16 seq_id; 6257c0c050c5SMichael Chan __le16 resp_len; 6258894aa69aSMichael Chan u8 unused_0[7]; 6259c0c050c5SMichael Chan u8 valid; 6260c0c050c5SMichael Chan }; 6261c0c050c5SMichael Chan 626241136ab3SMichael Chan /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 626341136ab3SMichael Chan struct hwrm_vnic_rss_cfg_cmd_err { 626441136ab3SMichael Chan u8 code; 626541136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 626641136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 626741136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 626841136ab3SMichael Chan u8 unused_0[7]; 626941136ab3SMichael Chan }; 627041136ab3SMichael Chan 6271894aa69aSMichael Chan /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 6272c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_input { 6273c0c050c5SMichael Chan __le16 req_type; 6274c0c050c5SMichael Chan __le16 cmpl_ring; 6275c0c050c5SMichael Chan __le16 seq_id; 6276c0c050c5SMichael Chan __le16 target_id; 6277c0c050c5SMichael Chan __le64 resp_addr; 6278c0c050c5SMichael Chan __le32 flags; 6279c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 6280c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 6281c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 6282c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 6283c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 6284c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 6285bfc6e5fbSMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 6286c0c050c5SMichael Chan __le32 enables; 6287c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 6288c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 6289c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 6290bfc6e5fbSMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 6291c0c050c5SMichael Chan __le32 vnic_id; 6292c0c050c5SMichael Chan __le16 jumbo_thresh; 6293c0c050c5SMichael Chan __le16 hds_offset; 6294c0c050c5SMichael Chan __le16 hds_threshold; 6295bfc6e5fbSMichael Chan __le16 max_bds; 6296bfc6e5fbSMichael Chan u8 unused_0[4]; 6297c0c050c5SMichael Chan }; 6298c0c050c5SMichael Chan 6299894aa69aSMichael Chan /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 6300c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_output { 6301c0c050c5SMichael Chan __le16 error_code; 6302c0c050c5SMichael Chan __le16 req_type; 6303c0c050c5SMichael Chan __le16 seq_id; 6304c0c050c5SMichael Chan __le16 resp_len; 6305894aa69aSMichael Chan u8 unused_0[7]; 6306c0c050c5SMichael Chan u8 valid; 6307c0c050c5SMichael Chan }; 6308c0c050c5SMichael Chan 6309894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 6310c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 6311c0c050c5SMichael Chan __le16 req_type; 6312c0c050c5SMichael Chan __le16 cmpl_ring; 6313c0c050c5SMichael Chan __le16 seq_id; 6314c0c050c5SMichael Chan __le16 target_id; 6315c0c050c5SMichael Chan __le64 resp_addr; 6316c0c050c5SMichael Chan }; 6317c0c050c5SMichael Chan 6318894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 6319c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 6320c0c050c5SMichael Chan __le16 error_code; 6321c0c050c5SMichael Chan __le16 req_type; 6322c0c050c5SMichael Chan __le16 seq_id; 6323c0c050c5SMichael Chan __le16 resp_len; 6324c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 6325894aa69aSMichael Chan u8 unused_0[5]; 6326c0c050c5SMichael Chan u8 valid; 6327c0c050c5SMichael Chan }; 6328c0c050c5SMichael Chan 6329894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 6330c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_input { 6331c0c050c5SMichael Chan __le16 req_type; 6332c0c050c5SMichael Chan __le16 cmpl_ring; 6333c0c050c5SMichael Chan __le16 seq_id; 6334c0c050c5SMichael Chan __le16 target_id; 6335c0c050c5SMichael Chan __le64 resp_addr; 6336c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 6337894aa69aSMichael Chan u8 unused_0[6]; 6338c0c050c5SMichael Chan }; 6339c0c050c5SMichael Chan 6340894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 6341c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_output { 6342c0c050c5SMichael Chan __le16 error_code; 6343c0c050c5SMichael Chan __le16 req_type; 6344c0c050c5SMichael Chan __le16 seq_id; 6345c0c050c5SMichael Chan __le16 resp_len; 6346894aa69aSMichael Chan u8 unused_0[7]; 6347c0c050c5SMichael Chan u8 valid; 6348c0c050c5SMichael Chan }; 6349c0c050c5SMichael Chan 63506fc92c33SMichael Chan /* hwrm_ring_alloc_input (size:704b/88B) */ 6351c0c050c5SMichael Chan struct hwrm_ring_alloc_input { 6352c0c050c5SMichael Chan __le16 req_type; 6353c0c050c5SMichael Chan __le16 cmpl_ring; 6354c0c050c5SMichael Chan __le16 seq_id; 6355c0c050c5SMichael Chan __le16 target_id; 6356c0c050c5SMichael Chan __le64 resp_addr; 6357c0c050c5SMichael Chan __le32 enables; 6358441cabbbSMichael Chan #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 6359c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 6360c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 63616fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 63626fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 63636fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 6364bfc6e5fbSMichael Chan #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 63659d6b648cSMichael Chan #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 6366c0c050c5SMichael Chan u8 ring_type; 6367bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 6368441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 6369441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 6370bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 63716fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 63726fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 63736fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 6374*21e70778SMichael Chan u8 cmpl_coal_cnt; 6375*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 6376*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 6377*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 6378*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 6379*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 6380*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 6381*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 6382*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 6383*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 6384*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 6385*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 6386*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 6387*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 6388*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 6389*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 6390*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 6391*21e70778SMichael Chan #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 639231d357c0SMichael Chan __le16 flags; 639331d357c0SMichael Chan #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 6394c0c050c5SMichael Chan __le64 page_tbl_addr; 6395c0c050c5SMichael Chan __le32 fbo; 6396c0c050c5SMichael Chan u8 page_size; 6397c0c050c5SMichael Chan u8 page_tbl_depth; 6398bfc6e5fbSMichael Chan __le16 schq_id; 6399c0c050c5SMichael Chan __le32 length; 6400c0c050c5SMichael Chan __le16 logical_id; 6401c0c050c5SMichael Chan __le16 cmpl_ring_id; 6402c0c050c5SMichael Chan __le16 queue_id; 64036fc92c33SMichael Chan __le16 rx_buf_size; 64046fc92c33SMichael Chan __le16 rx_ring_id; 64056fc92c33SMichael Chan __le16 nq_ring_id; 6406441cabbbSMichael Chan __le16 ring_arb_cfg; 6407441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 6408441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 6409894aa69aSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 6410894aa69aSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 6411441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 6412441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 6413441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 6414441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 6415441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 6416894aa69aSMichael Chan __le16 unused_3; 6417c193554eSMichael Chan __le32 reserved3; 6418c0c050c5SMichael Chan __le32 stat_ctx_id; 6419c193554eSMichael Chan __le32 reserved4; 6420c0c050c5SMichael Chan __le32 max_bw; 6421441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6422441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 6423bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 6424bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 6425bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 6426bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 6427441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6428441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 6429bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6430bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6431bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6432bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6433441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6434441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6435441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 6436c0c050c5SMichael Chan u8 int_mode; 6437441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 6438441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 6439441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 6440441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 6441894aa69aSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 64429d6b648cSMichael Chan u8 mpc_chnls_type; 64439d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 64449d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 64459d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 64469d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 64479d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 64489d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 64499d6b648cSMichael Chan u8 unused_4[2]; 64506fc92c33SMichael Chan __le64 cq_handle; 6451c0c050c5SMichael Chan }; 6452c0c050c5SMichael Chan 6453894aa69aSMichael Chan /* hwrm_ring_alloc_output (size:128b/16B) */ 6454c0c050c5SMichael Chan struct hwrm_ring_alloc_output { 6455c0c050c5SMichael Chan __le16 error_code; 6456c0c050c5SMichael Chan __le16 req_type; 6457c0c050c5SMichael Chan __le16 seq_id; 6458c0c050c5SMichael Chan __le16 resp_len; 6459c0c050c5SMichael Chan __le16 ring_id; 6460c0c050c5SMichael Chan __le16 logical_ring_id; 646116db6323SMichael Chan u8 push_buffer_index; 646216db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 646316db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 646416db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 646516db6323SMichael Chan u8 unused_0[2]; 6466c0c050c5SMichael Chan u8 valid; 6467c0c050c5SMichael Chan }; 6468c0c050c5SMichael Chan 646931f67c2eSMichael Chan /* hwrm_ring_free_input (size:256b/32B) */ 6470c0c050c5SMichael Chan struct hwrm_ring_free_input { 6471c0c050c5SMichael Chan __le16 req_type; 6472c0c050c5SMichael Chan __le16 cmpl_ring; 6473c0c050c5SMichael Chan __le16 seq_id; 6474c0c050c5SMichael Chan __le16 target_id; 6475c0c050c5SMichael Chan __le64 resp_addr; 6476c0c050c5SMichael Chan u8 ring_type; 6477bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 6478441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 6479441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 6480bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 64816fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 64826fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 64836fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 648431f67c2eSMichael Chan u8 flags; 648531f67c2eSMichael Chan #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 648631f67c2eSMichael Chan #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 6487c0c050c5SMichael Chan __le16 ring_id; 648831f67c2eSMichael Chan __le32 prod_idx; 648931f67c2eSMichael Chan __le32 opaque; 649031f67c2eSMichael Chan __le32 unused_1; 6491c0c050c5SMichael Chan }; 6492c0c050c5SMichael Chan 6493894aa69aSMichael Chan /* hwrm_ring_free_output (size:128b/16B) */ 6494c0c050c5SMichael Chan struct hwrm_ring_free_output { 6495c0c050c5SMichael Chan __le16 error_code; 6496c0c050c5SMichael Chan __le16 req_type; 6497c0c050c5SMichael Chan __le16 seq_id; 6498c0c050c5SMichael Chan __le16 resp_len; 6499894aa69aSMichael Chan u8 unused_0[7]; 6500c0c050c5SMichael Chan u8 valid; 6501c0c050c5SMichael Chan }; 6502c0c050c5SMichael Chan 65033293ec23SMichael Chan /* hwrm_ring_reset_input (size:192b/24B) */ 65043293ec23SMichael Chan struct hwrm_ring_reset_input { 65053293ec23SMichael Chan __le16 req_type; 65063293ec23SMichael Chan __le16 cmpl_ring; 65073293ec23SMichael Chan __le16 seq_id; 65083293ec23SMichael Chan __le16 target_id; 65093293ec23SMichael Chan __le64 resp_addr; 65103293ec23SMichael Chan u8 ring_type; 65113293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 65123293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 65133293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 65143293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 6515bfc6e5fbSMichael Chan #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 6516bfc6e5fbSMichael Chan #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 65173293ec23SMichael Chan u8 unused_0; 65183293ec23SMichael Chan __le16 ring_id; 65193293ec23SMichael Chan u8 unused_1[4]; 65203293ec23SMichael Chan }; 65213293ec23SMichael Chan 65223293ec23SMichael Chan /* hwrm_ring_reset_output (size:128b/16B) */ 65233293ec23SMichael Chan struct hwrm_ring_reset_output { 65243293ec23SMichael Chan __le16 error_code; 65253293ec23SMichael Chan __le16 req_type; 65263293ec23SMichael Chan __le16 seq_id; 65273293ec23SMichael Chan __le16 resp_len; 652816db6323SMichael Chan u8 push_buffer_index; 652916db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 653016db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 653116db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 653216db6323SMichael Chan u8 unused_0[3]; 65333293ec23SMichael Chan u8 consumer_idx[3]; 65343293ec23SMichael Chan u8 valid; 65353293ec23SMichael Chan }; 65363293ec23SMichael Chan 65376fc92c33SMichael Chan /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 65386fc92c33SMichael Chan struct hwrm_ring_aggint_qcaps_input { 65396fc92c33SMichael Chan __le16 req_type; 65406fc92c33SMichael Chan __le16 cmpl_ring; 65416fc92c33SMichael Chan __le16 seq_id; 65426fc92c33SMichael Chan __le16 target_id; 65436fc92c33SMichael Chan __le64 resp_addr; 65446fc92c33SMichael Chan }; 65456fc92c33SMichael Chan 65466fc92c33SMichael Chan /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 65476fc92c33SMichael Chan struct hwrm_ring_aggint_qcaps_output { 65486fc92c33SMichael Chan __le16 error_code; 65496fc92c33SMichael Chan __le16 req_type; 65506fc92c33SMichael Chan __le16 seq_id; 65516fc92c33SMichael Chan __le16 resp_len; 65526fc92c33SMichael Chan __le32 cmpl_params; 65536fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 65546fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 65556fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 65566fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 65576fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 65586fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 65596fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 65606fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 65616fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 65626fc92c33SMichael Chan __le32 nq_params; 65636fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 65646fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_min; 65656fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_max; 65666fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_during_int_min; 65676fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_during_int_max; 65686fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_min; 65696fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_max; 65706fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int_min; 65716fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int_max; 65726fc92c33SMichael Chan __le16 int_lat_tmr_min_min; 65736fc92c33SMichael Chan __le16 int_lat_tmr_min_max; 65746fc92c33SMichael Chan __le16 int_lat_tmr_max_min; 65756fc92c33SMichael Chan __le16 int_lat_tmr_max_max; 65766fc92c33SMichael Chan __le16 num_cmpl_aggr_int_min; 65776fc92c33SMichael Chan __le16 num_cmpl_aggr_int_max; 65786fc92c33SMichael Chan __le16 timer_units; 65796fc92c33SMichael Chan u8 unused_0[1]; 65806fc92c33SMichael Chan u8 valid; 65816fc92c33SMichael Chan }; 65826fc92c33SMichael Chan 6583894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 6584c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_input { 6585c0c050c5SMichael Chan __le16 req_type; 6586c0c050c5SMichael Chan __le16 cmpl_ring; 6587c0c050c5SMichael Chan __le16 seq_id; 6588c0c050c5SMichael Chan __le16 target_id; 6589c0c050c5SMichael Chan __le64 resp_addr; 6590c0c050c5SMichael Chan __le16 ring_id; 6591460c2577SMichael Chan __le16 flags; 6592460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 6593460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 6594460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6595460c2577SMichael Chan u8 unused_0[4]; 6596c0c050c5SMichael Chan }; 6597c0c050c5SMichael Chan 6598894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 6599c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_output { 6600c0c050c5SMichael Chan __le16 error_code; 6601c0c050c5SMichael Chan __le16 req_type; 6602c0c050c5SMichael Chan __le16 seq_id; 6603c0c050c5SMichael Chan __le16 resp_len; 6604c0c050c5SMichael Chan __le16 flags; 6605c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 6606c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 6607c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 6608c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 6609c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 6610c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 6611c0c050c5SMichael Chan __le16 int_lat_tmr_min; 6612c0c050c5SMichael Chan __le16 int_lat_tmr_max; 6613c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 6614894aa69aSMichael Chan u8 unused_0[7]; 6615c0c050c5SMichael Chan u8 valid; 6616c0c050c5SMichael Chan }; 6617c0c050c5SMichael Chan 6618894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 6619c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 6620c0c050c5SMichael Chan __le16 req_type; 6621c0c050c5SMichael Chan __le16 cmpl_ring; 6622c0c050c5SMichael Chan __le16 seq_id; 6623c0c050c5SMichael Chan __le16 target_id; 6624c0c050c5SMichael Chan __le64 resp_addr; 6625c0c050c5SMichael Chan __le16 ring_id; 6626c0c050c5SMichael Chan __le16 flags; 6627c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 6628c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 66296fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 6630c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 6631c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 6632c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 6633c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 6634c0c050c5SMichael Chan __le16 int_lat_tmr_min; 6635c0c050c5SMichael Chan __le16 int_lat_tmr_max; 6636c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 66376fc92c33SMichael Chan __le16 enables; 66386fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 66396fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 66406fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 66416fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 66426fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 66436fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 66446fc92c33SMichael Chan u8 unused_0[4]; 6645c0c050c5SMichael Chan }; 6646c0c050c5SMichael Chan 6647894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 6648c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 6649c0c050c5SMichael Chan __le16 error_code; 6650c0c050c5SMichael Chan __le16 req_type; 6651c0c050c5SMichael Chan __le16 seq_id; 6652c0c050c5SMichael Chan __le16 resp_len; 6653894aa69aSMichael Chan u8 unused_0[7]; 6654c0c050c5SMichael Chan u8 valid; 6655c0c050c5SMichael Chan }; 6656c0c050c5SMichael Chan 6657894aa69aSMichael Chan /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 6658c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_input { 6659c0c050c5SMichael Chan __le16 req_type; 6660c0c050c5SMichael Chan __le16 cmpl_ring; 6661c0c050c5SMichael Chan __le16 seq_id; 6662c0c050c5SMichael Chan __le16 target_id; 6663c0c050c5SMichael Chan __le64 resp_addr; 6664c0c050c5SMichael Chan __le16 cr; 6665c0c050c5SMichael Chan __le16 rr; 6666c0c050c5SMichael Chan __le16 ar; 6667c0c050c5SMichael Chan __le16 sc; 6668c0c050c5SMichael Chan }; 6669c0c050c5SMichael Chan 6670894aa69aSMichael Chan /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 6671c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_output { 6672c0c050c5SMichael Chan __le16 error_code; 6673c0c050c5SMichael Chan __le16 req_type; 6674c0c050c5SMichael Chan __le16 seq_id; 6675c0c050c5SMichael Chan __le16 resp_len; 6676c0c050c5SMichael Chan __le32 ring_group_id; 6677894aa69aSMichael Chan u8 unused_0[3]; 6678c0c050c5SMichael Chan u8 valid; 6679c0c050c5SMichael Chan }; 6680c0c050c5SMichael Chan 6681894aa69aSMichael Chan /* hwrm_ring_grp_free_input (size:192b/24B) */ 6682c0c050c5SMichael Chan struct hwrm_ring_grp_free_input { 6683c0c050c5SMichael Chan __le16 req_type; 6684c0c050c5SMichael Chan __le16 cmpl_ring; 6685c0c050c5SMichael Chan __le16 seq_id; 6686c0c050c5SMichael Chan __le16 target_id; 6687c0c050c5SMichael Chan __le64 resp_addr; 6688c0c050c5SMichael Chan __le32 ring_group_id; 6689894aa69aSMichael Chan u8 unused_0[4]; 6690c0c050c5SMichael Chan }; 6691c0c050c5SMichael Chan 6692894aa69aSMichael Chan /* hwrm_ring_grp_free_output (size:128b/16B) */ 6693c0c050c5SMichael Chan struct hwrm_ring_grp_free_output { 6694c0c050c5SMichael Chan __le16 error_code; 6695c0c050c5SMichael Chan __le16 req_type; 6696c0c050c5SMichael Chan __le16 seq_id; 6697c0c050c5SMichael Chan __le16 resp_len; 6698894aa69aSMichael Chan u8 unused_0[7]; 6699c0c050c5SMichael Chan u8 valid; 6700c0c050c5SMichael Chan }; 6701bfc6e5fbSMichael Chan 67023322479eSMichael Chan #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 67033322479eSMichael Chan #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 67043322479eSMichael Chan #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 67053322479eSMichael Chan #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 6706c0c050c5SMichael Chan 6707894aa69aSMichael Chan /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 6708c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_input { 6709c0c050c5SMichael Chan __le16 req_type; 6710c0c050c5SMichael Chan __le16 cmpl_ring; 6711c0c050c5SMichael Chan __le16 seq_id; 6712c0c050c5SMichael Chan __le16 target_id; 6713c0c050c5SMichael Chan __le64 resp_addr; 6714c0c050c5SMichael Chan __le32 flags; 6715c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 6716894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 6717894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 671811f15ed3SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 6719c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 6720c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 6721c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 672231d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 672331d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 672431d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 672531d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 672631d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 672731d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 67284a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 67294a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 6730c0c050c5SMichael Chan __le32 enables; 6731c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 6732c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 6733c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 6734c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 6735c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 6736c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 6737c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 6738c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 6739c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 6740c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 6741c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 6742c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 6743c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 6744c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6745c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6746c193554eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6747c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 67484a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 67494a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6750c0c050c5SMichael Chan u8 l2_addr[6]; 67514a50ddc2SMichael Chan u8 num_vlans; 67524a50ddc2SMichael Chan u8 t_num_vlans; 6753c0c050c5SMichael Chan u8 l2_addr_mask[6]; 6754c0c050c5SMichael Chan __le16 l2_ovlan; 6755c0c050c5SMichael Chan __le16 l2_ovlan_mask; 6756c0c050c5SMichael Chan __le16 l2_ivlan; 6757c0c050c5SMichael Chan __le16 l2_ivlan_mask; 6758894aa69aSMichael Chan u8 unused_1[2]; 6759c0c050c5SMichael Chan u8 t_l2_addr[6]; 6760894aa69aSMichael Chan u8 unused_2[2]; 6761c0c050c5SMichael Chan u8 t_l2_addr_mask[6]; 6762c0c050c5SMichael Chan __le16 t_l2_ovlan; 6763c0c050c5SMichael Chan __le16 t_l2_ovlan_mask; 6764c0c050c5SMichael Chan __le16 t_l2_ivlan; 6765c0c050c5SMichael Chan __le16 t_l2_ivlan_mask; 6766c0c050c5SMichael Chan u8 src_type; 6767441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6768441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6769441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6770441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6771441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6772441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6773441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6774441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6775894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6776894aa69aSMichael Chan u8 unused_3; 6777c0c050c5SMichael Chan __le32 src_id; 6778c0c050c5SMichael Chan u8 tunnel_type; 6779441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6780441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6781441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6782441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6783441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6784441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6785441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6786441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6787441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 678857922b0aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 678931d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 679031d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 67913322479eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6792441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6793894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6794894aa69aSMichael Chan u8 unused_4; 6795c193554eSMichael Chan __le16 dst_id; 6796c0c050c5SMichael Chan __le16 mirror_vnic_id; 6797c0c050c5SMichael Chan u8 pri_hint; 6798441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6799441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6800441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6801441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6802441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6803894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6804894aa69aSMichael Chan u8 unused_5; 6805894aa69aSMichael Chan __le32 unused_6; 6806c0c050c5SMichael Chan __le64 l2_filter_id_hint; 6807c0c050c5SMichael Chan }; 6808c0c050c5SMichael Chan 6809894aa69aSMichael Chan /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6810c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_output { 6811c0c050c5SMichael Chan __le16 error_code; 6812c0c050c5SMichael Chan __le16 req_type; 6813c0c050c5SMichael Chan __le16 seq_id; 6814c0c050c5SMichael Chan __le16 resp_len; 6815c0c050c5SMichael Chan __le64 l2_filter_id; 6816c0c050c5SMichael Chan __le32 flow_id; 68174a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 68184a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 68194a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 68204a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 68214a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 68224a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 68234a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 68244a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 68254a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 68264a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6827894aa69aSMichael Chan u8 unused_0[3]; 6828c0c050c5SMichael Chan u8 valid; 6829c0c050c5SMichael Chan }; 6830c0c050c5SMichael Chan 6831894aa69aSMichael Chan /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6832c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_input { 6833c0c050c5SMichael Chan __le16 req_type; 6834c0c050c5SMichael Chan __le16 cmpl_ring; 6835c0c050c5SMichael Chan __le16 seq_id; 6836c0c050c5SMichael Chan __le16 target_id; 6837c0c050c5SMichael Chan __le64 resp_addr; 6838c0c050c5SMichael Chan __le64 l2_filter_id; 6839c0c050c5SMichael Chan }; 6840c0c050c5SMichael Chan 6841894aa69aSMichael Chan /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6842c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_output { 6843c0c050c5SMichael Chan __le16 error_code; 6844c0c050c5SMichael Chan __le16 req_type; 6845c0c050c5SMichael Chan __le16 seq_id; 6846c0c050c5SMichael Chan __le16 resp_len; 6847894aa69aSMichael Chan u8 unused_0[7]; 6848c0c050c5SMichael Chan u8 valid; 6849c0c050c5SMichael Chan }; 6850c0c050c5SMichael Chan 6851894aa69aSMichael Chan /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6852c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_input { 6853c0c050c5SMichael Chan __le16 req_type; 6854c0c050c5SMichael Chan __le16 cmpl_ring; 6855c0c050c5SMichael Chan __le16 seq_id; 6856c0c050c5SMichael Chan __le16 target_id; 6857c0c050c5SMichael Chan __le64 resp_addr; 6858c0c050c5SMichael Chan __le32 flags; 6859c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6860894aa69aSMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6861894aa69aSMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 686211f15ed3SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6863c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 686431d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 686531d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 686631d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 686731d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 686831d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 686931d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6870c0c050c5SMichael Chan __le32 enables; 6871c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6872c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6873c0c050c5SMichael Chan __le64 l2_filter_id; 6874c193554eSMichael Chan __le32 dst_id; 6875c193554eSMichael Chan __le32 new_mirror_vnic_id; 6876c0c050c5SMichael Chan }; 6877c0c050c5SMichael Chan 6878894aa69aSMichael Chan /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6879c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_output { 6880c0c050c5SMichael Chan __le16 error_code; 6881c0c050c5SMichael Chan __le16 req_type; 6882c0c050c5SMichael Chan __le16 seq_id; 6883c0c050c5SMichael Chan __le16 resp_len; 6884894aa69aSMichael Chan u8 unused_0[7]; 6885c0c050c5SMichael Chan u8 valid; 6886c0c050c5SMichael Chan }; 6887c0c050c5SMichael Chan 6888894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6889c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_input { 6890c0c050c5SMichael Chan __le16 req_type; 6891c0c050c5SMichael Chan __le16 cmpl_ring; 6892c0c050c5SMichael Chan __le16 seq_id; 6893c0c050c5SMichael Chan __le16 target_id; 6894c0c050c5SMichael Chan __le64 resp_addr; 6895c193554eSMichael Chan __le32 vnic_id; 6896c0c050c5SMichael Chan __le32 mask; 6897c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6898c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6899c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6900c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6901c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6902a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6903a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6904a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6905c0c050c5SMichael Chan __le64 mc_tbl_addr; 6906c0c050c5SMichael Chan __le32 num_mc_entries; 6907894aa69aSMichael Chan u8 unused_0[4]; 6908a58a3e68SMichael Chan __le64 vlan_tag_tbl_addr; 6909a58a3e68SMichael Chan __le32 num_vlan_tags; 6910894aa69aSMichael Chan u8 unused_1[4]; 6911c0c050c5SMichael Chan }; 6912c0c050c5SMichael Chan 6913894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6914c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_output { 6915c0c050c5SMichael Chan __le16 error_code; 6916c0c050c5SMichael Chan __le16 req_type; 6917c0c050c5SMichael Chan __le16 seq_id; 6918c0c050c5SMichael Chan __le16 resp_len; 6919894aa69aSMichael Chan u8 unused_0[7]; 6920c0c050c5SMichael Chan u8 valid; 6921c0c050c5SMichael Chan }; 6922c0c050c5SMichael Chan 6923894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 692457922b0aSMichael Chan struct hwrm_cfa_l2_set_rx_mask_cmd_err { 692557922b0aSMichael Chan u8 code; 692657922b0aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 692757922b0aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6928894aa69aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 692957922b0aSMichael Chan u8 unused_0[7]; 693057922b0aSMichael Chan }; 693157922b0aSMichael Chan 6932894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6933c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_input { 6934c0c050c5SMichael Chan __le16 req_type; 6935c0c050c5SMichael Chan __le16 cmpl_ring; 6936c0c050c5SMichael Chan __le16 seq_id; 6937c0c050c5SMichael Chan __le16 target_id; 6938c0c050c5SMichael Chan __le64 resp_addr; 6939c0c050c5SMichael Chan __le32 flags; 6940c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6941c0c050c5SMichael Chan __le32 enables; 6942c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6943c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6944c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6945c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6946c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6947c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6948c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6949c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6950c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6951c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6952c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6953c0c050c5SMichael Chan __le64 l2_filter_id; 6954c0c050c5SMichael Chan u8 l2_addr[6]; 6955c0c050c5SMichael Chan __le16 l2_ivlan; 6956c0c050c5SMichael Chan __le32 l3_addr[4]; 6957c0c050c5SMichael Chan __le32 t_l3_addr[4]; 6958c0c050c5SMichael Chan u8 l3_addr_type; 6959c0c050c5SMichael Chan u8 t_l3_addr_type; 6960c0c050c5SMichael Chan u8 tunnel_type; 6961441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6962441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6963441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6964441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6965441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6966441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6967441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6968441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6969441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 697057922b0aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 697131d357c0SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 697231d357c0SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 69733322479eSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6974441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6975894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6976894aa69aSMichael Chan u8 tunnel_flags; 6977894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6978894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6979894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6980c0c050c5SMichael Chan __le32 vni; 6981c0c050c5SMichael Chan __le32 dst_vnic_id; 6982c0c050c5SMichael Chan __le32 mirror_vnic_id; 6983c0c050c5SMichael Chan }; 6984c0c050c5SMichael Chan 6985894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6986c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_output { 6987c0c050c5SMichael Chan __le16 error_code; 6988c0c050c5SMichael Chan __le16 req_type; 6989c0c050c5SMichael Chan __le16 seq_id; 6990c0c050c5SMichael Chan __le16 resp_len; 6991c0c050c5SMichael Chan __le64 tunnel_filter_id; 6992c0c050c5SMichael Chan __le32 flow_id; 69934a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 69944a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 69954a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 69964a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 69974a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 69984a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 69994a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 70004a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 70014a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 70024a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7003894aa69aSMichael Chan u8 unused_0[3]; 7004c0c050c5SMichael Chan u8 valid; 7005c0c050c5SMichael Chan }; 7006c0c050c5SMichael Chan 7007894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 7008c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_input { 7009c0c050c5SMichael Chan __le16 req_type; 7010c0c050c5SMichael Chan __le16 cmpl_ring; 7011c0c050c5SMichael Chan __le16 seq_id; 7012c0c050c5SMichael Chan __le16 target_id; 7013c0c050c5SMichael Chan __le64 resp_addr; 7014c0c050c5SMichael Chan __le64 tunnel_filter_id; 7015c0c050c5SMichael Chan }; 7016c0c050c5SMichael Chan 7017894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 7018c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_output { 7019c0c050c5SMichael Chan __le16 error_code; 7020c0c050c5SMichael Chan __le16 req_type; 7021c0c050c5SMichael Chan __le16 seq_id; 7022c0c050c5SMichael Chan __le16 resp_len; 7023894aa69aSMichael Chan u8 unused_0[7]; 7024c0c050c5SMichael Chan u8 valid; 7025c0c050c5SMichael Chan }; 7026c0c050c5SMichael Chan 7027894aa69aSMichael Chan /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 7028894aa69aSMichael Chan struct hwrm_vxlan_ipv4_hdr { 7029894aa69aSMichael Chan u8 ver_hlen; 7030894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 7031894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 7032894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 7033894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 7034894aa69aSMichael Chan u8 tos; 7035894aa69aSMichael Chan __be16 ip_id; 7036894aa69aSMichael Chan __be16 flags_frag_offset; 7037894aa69aSMichael Chan u8 ttl; 7038894aa69aSMichael Chan u8 protocol; 7039894aa69aSMichael Chan __be32 src_ip_addr; 7040894aa69aSMichael Chan __be32 dest_ip_addr; 7041894aa69aSMichael Chan }; 7042894aa69aSMichael Chan 7043894aa69aSMichael Chan /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 7044894aa69aSMichael Chan struct hwrm_vxlan_ipv6_hdr { 7045894aa69aSMichael Chan __be32 ver_tc_flow_label; 7046894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 7047894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 7048894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 7049894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 7050894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 7051894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 7052894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 7053894aa69aSMichael Chan __be16 payload_len; 7054894aa69aSMichael Chan u8 next_hdr; 7055894aa69aSMichael Chan u8 ttl; 7056894aa69aSMichael Chan __be32 src_ip_addr[4]; 7057894aa69aSMichael Chan __be32 dest_ip_addr[4]; 7058894aa69aSMichael Chan }; 7059894aa69aSMichael Chan 706031d357c0SMichael Chan /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 7061894aa69aSMichael Chan struct hwrm_cfa_encap_data_vxlan { 7062894aa69aSMichael Chan u8 src_mac_addr[6]; 7063894aa69aSMichael Chan __le16 unused_0; 7064894aa69aSMichael Chan u8 dst_mac_addr[6]; 7065894aa69aSMichael Chan u8 num_vlan_tags; 7066894aa69aSMichael Chan u8 unused_1; 7067894aa69aSMichael Chan __be16 ovlan_tpid; 7068894aa69aSMichael Chan __be16 ovlan_tci; 7069894aa69aSMichael Chan __be16 ivlan_tpid; 7070894aa69aSMichael Chan __be16 ivlan_tci; 7071894aa69aSMichael Chan __le32 l3[10]; 7072894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 7073894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 7074894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 7075894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 7076894aa69aSMichael Chan __be16 src_port; 7077894aa69aSMichael Chan __be16 dst_port; 7078894aa69aSMichael Chan __be32 vni; 707931d357c0SMichael Chan u8 hdr_rsvd0[3]; 708031d357c0SMichael Chan u8 hdr_rsvd1; 708131d357c0SMichael Chan u8 hdr_flags; 708231d357c0SMichael Chan u8 unused[3]; 7083894aa69aSMichael Chan }; 7084894aa69aSMichael Chan 7085894aa69aSMichael Chan /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 7086c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_input { 7087c0c050c5SMichael Chan __le16 req_type; 7088c0c050c5SMichael Chan __le16 cmpl_ring; 7089c0c050c5SMichael Chan __le16 seq_id; 7090c0c050c5SMichael Chan __le16 target_id; 7091c0c050c5SMichael Chan __le64 resp_addr; 7092c0c050c5SMichael Chan __le32 flags; 7093c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 70943293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 7095c0c050c5SMichael Chan u8 encap_type; 7096441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 7097441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 7098441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 7099441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 7100441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 7101441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 7102441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 7103441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 710431d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 710531d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 710631d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 71073293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 71083293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 7109894aa69aSMichael Chan u8 unused_0[3]; 7110acb20054SMichael Chan __le32 encap_data[20]; 7111c0c050c5SMichael Chan }; 7112c0c050c5SMichael Chan 7113894aa69aSMichael Chan /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 7114c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_output { 7115c0c050c5SMichael Chan __le16 error_code; 7116c0c050c5SMichael Chan __le16 req_type; 7117c0c050c5SMichael Chan __le16 seq_id; 7118c0c050c5SMichael Chan __le16 resp_len; 7119c193554eSMichael Chan __le32 encap_record_id; 7120894aa69aSMichael Chan u8 unused_0[3]; 7121c0c050c5SMichael Chan u8 valid; 7122c0c050c5SMichael Chan }; 7123c0c050c5SMichael Chan 7124894aa69aSMichael Chan /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 7125c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_input { 7126c0c050c5SMichael Chan __le16 req_type; 7127c0c050c5SMichael Chan __le16 cmpl_ring; 7128c0c050c5SMichael Chan __le16 seq_id; 7129c0c050c5SMichael Chan __le16 target_id; 7130c0c050c5SMichael Chan __le64 resp_addr; 7131c193554eSMichael Chan __le32 encap_record_id; 7132894aa69aSMichael Chan u8 unused_0[4]; 7133c0c050c5SMichael Chan }; 7134c0c050c5SMichael Chan 7135894aa69aSMichael Chan /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 7136c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_output { 7137c0c050c5SMichael Chan __le16 error_code; 7138c0c050c5SMichael Chan __le16 req_type; 7139c0c050c5SMichael Chan __le16 seq_id; 7140c0c050c5SMichael Chan __le16 resp_len; 7141894aa69aSMichael Chan u8 unused_0[7]; 7142c0c050c5SMichael Chan u8 valid; 7143c0c050c5SMichael Chan }; 7144c0c050c5SMichael Chan 714541136ab3SMichael Chan /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 7146c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_input { 7147c0c050c5SMichael Chan __le16 req_type; 7148c0c050c5SMichael Chan __le16 cmpl_ring; 7149c0c050c5SMichael Chan __le16 seq_id; 7150c0c050c5SMichael Chan __le16 target_id; 7151c0c050c5SMichael Chan __le64 resp_addr; 7152c0c050c5SMichael Chan __le32 flags; 7153c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7154c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 7155bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 71563293ec23SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 715741136ab3SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 715841136ab3SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 7159*21e70778SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 7160c0c050c5SMichael Chan __le32 enables; 7161c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7162c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 7163c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 7164c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 7165c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 7166c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 7167c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 7168c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 7169c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 7170c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 7171c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 7172c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 7173c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 7174c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 7175c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 7176c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 7177c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 7178c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 7179c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 71804a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 7181c0c050c5SMichael Chan __le64 l2_filter_id; 7182c0c050c5SMichael Chan u8 src_macaddr[6]; 7183c0c050c5SMichael Chan __be16 ethertype; 7184c193554eSMichael Chan u8 ip_addr_type; 7185441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 7186441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 7187441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7188894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 7189c0c050c5SMichael Chan u8 ip_protocol; 7190441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 7191acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 7192acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7193894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7194c193554eSMichael Chan __le16 dst_id; 7195c0c050c5SMichael Chan __le16 mirror_vnic_id; 7196c0c050c5SMichael Chan u8 tunnel_type; 7197441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7198441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7199441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7200441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7201441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7202441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7203441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7204441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7205441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 720657922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 720731d357c0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 720831d357c0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 72093322479eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7210441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7211894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7212c0c050c5SMichael Chan u8 pri_hint; 7213441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7214441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 7215441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 7216441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 7217441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 7218894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 7219c0c050c5SMichael Chan __be32 src_ipaddr[4]; 7220c0c050c5SMichael Chan __be32 src_ipaddr_mask[4]; 7221c0c050c5SMichael Chan __be32 dst_ipaddr[4]; 7222c0c050c5SMichael Chan __be32 dst_ipaddr_mask[4]; 7223c0c050c5SMichael Chan __be16 src_port; 7224c0c050c5SMichael Chan __be16 src_port_mask; 7225c0c050c5SMichael Chan __be16 dst_port; 7226c0c050c5SMichael Chan __be16 dst_port_mask; 7227c0c050c5SMichael Chan __le64 ntuple_filter_id_hint; 7228c0c050c5SMichael Chan }; 7229c0c050c5SMichael Chan 7230894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 7231c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_output { 7232c0c050c5SMichael Chan __le16 error_code; 7233c0c050c5SMichael Chan __le16 req_type; 7234c0c050c5SMichael Chan __le16 seq_id; 7235c0c050c5SMichael Chan __le16 resp_len; 7236c0c050c5SMichael Chan __le64 ntuple_filter_id; 7237c0c050c5SMichael Chan __le32 flow_id; 72384a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 72394a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 72404a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 72414a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 72424a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 72434a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 72444a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 72454a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 72464a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 72474a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7248894aa69aSMichael Chan u8 unused_0[3]; 7249c0c050c5SMichael Chan u8 valid; 7250c0c050c5SMichael Chan }; 7251c0c050c5SMichael Chan 7252894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 725357922b0aSMichael Chan struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 725457922b0aSMichael Chan u8 code; 725557922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 725657922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 7257894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 725857922b0aSMichael Chan u8 unused_0[7]; 725957922b0aSMichael Chan }; 726057922b0aSMichael Chan 7261894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 7262c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_input { 7263c0c050c5SMichael Chan __le16 req_type; 7264c0c050c5SMichael Chan __le16 cmpl_ring; 7265c0c050c5SMichael Chan __le16 seq_id; 7266c0c050c5SMichael Chan __le16 target_id; 7267c0c050c5SMichael Chan __le64 resp_addr; 7268c0c050c5SMichael Chan __le64 ntuple_filter_id; 7269c0c050c5SMichael Chan }; 7270c0c050c5SMichael Chan 7271894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 7272c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_output { 7273c0c050c5SMichael Chan __le16 error_code; 7274c0c050c5SMichael Chan __le16 req_type; 7275c0c050c5SMichael Chan __le16 seq_id; 7276c0c050c5SMichael Chan __le16 resp_len; 7277894aa69aSMichael Chan u8 unused_0[7]; 7278c0c050c5SMichael Chan u8 valid; 7279c0c050c5SMichael Chan }; 7280c0c050c5SMichael Chan 7281894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 7282c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_input { 7283c0c050c5SMichael Chan __le16 req_type; 7284c0c050c5SMichael Chan __le16 cmpl_ring; 7285c0c050c5SMichael Chan __le16 seq_id; 7286c0c050c5SMichael Chan __le16 target_id; 7287c0c050c5SMichael Chan __le64 resp_addr; 7288c0c050c5SMichael Chan __le32 enables; 7289c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 7290c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7291bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 72923293ec23SMichael Chan __le32 flags; 72933293ec23SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 729441136ab3SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 7295*21e70778SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 7296c0c050c5SMichael Chan __le64 ntuple_filter_id; 7297c193554eSMichael Chan __le32 new_dst_id; 7298c0c050c5SMichael Chan __le32 new_mirror_vnic_id; 7299bac9a7e0SMichael Chan __le16 new_meter_instance_id; 7300bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 7301894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 7302894aa69aSMichael Chan u8 unused_1[6]; 7303c0c050c5SMichael Chan }; 7304c0c050c5SMichael Chan 7305894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 7306c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_output { 7307c0c050c5SMichael Chan __le16 error_code; 7308c0c050c5SMichael Chan __le16 req_type; 7309c0c050c5SMichael Chan __le16 seq_id; 7310c0c050c5SMichael Chan __le16 resp_len; 7311894aa69aSMichael Chan u8 unused_0[7]; 7312c0c050c5SMichael Chan u8 valid; 7313c0c050c5SMichael Chan }; 7314c0c050c5SMichael Chan 7315894aa69aSMichael Chan /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 731657922b0aSMichael Chan struct hwrm_cfa_decap_filter_alloc_input { 731757922b0aSMichael Chan __le16 req_type; 731857922b0aSMichael Chan __le16 cmpl_ring; 731957922b0aSMichael Chan __le16 seq_id; 732057922b0aSMichael Chan __le16 target_id; 732157922b0aSMichael Chan __le64 resp_addr; 732257922b0aSMichael Chan __le32 flags; 732357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 732457922b0aSMichael Chan __le32 enables; 732557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 732657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 732757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 732857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 732957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 733057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 733157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 733257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 733357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 733457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 733557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 733657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 733757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 733857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 733957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 734057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 734157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 734257922b0aSMichael Chan __be32 tunnel_id; 734357922b0aSMichael Chan u8 tunnel_type; 734457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 734557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 734657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 734757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 734857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 734957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 735057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 735157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 735257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 735357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 735431d357c0SMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 735531d357c0SMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 73563322479eSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 735757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7358894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 735957922b0aSMichael Chan u8 unused_0; 736057922b0aSMichael Chan __le16 unused_1; 736157922b0aSMichael Chan u8 src_macaddr[6]; 7362894aa69aSMichael Chan u8 unused_2[2]; 736357922b0aSMichael Chan u8 dst_macaddr[6]; 736457922b0aSMichael Chan __be16 ovlan_vid; 736557922b0aSMichael Chan __be16 ivlan_vid; 736657922b0aSMichael Chan __be16 t_ovlan_vid; 736757922b0aSMichael Chan __be16 t_ivlan_vid; 736857922b0aSMichael Chan __be16 ethertype; 736957922b0aSMichael Chan u8 ip_addr_type; 737057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 737157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 737257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 7373894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 737457922b0aSMichael Chan u8 ip_protocol; 737557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 737657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 737757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 7378894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 7379894aa69aSMichael Chan __le16 unused_3; 7380894aa69aSMichael Chan __le32 unused_4; 738157922b0aSMichael Chan __be32 src_ipaddr[4]; 738257922b0aSMichael Chan __be32 dst_ipaddr[4]; 738357922b0aSMichael Chan __be16 src_port; 738457922b0aSMichael Chan __be16 dst_port; 738557922b0aSMichael Chan __le16 dst_id; 738657922b0aSMichael Chan __le16 l2_ctxt_ref_id; 738757922b0aSMichael Chan }; 738857922b0aSMichael Chan 7389894aa69aSMichael Chan /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 739057922b0aSMichael Chan struct hwrm_cfa_decap_filter_alloc_output { 739157922b0aSMichael Chan __le16 error_code; 739257922b0aSMichael Chan __le16 req_type; 739357922b0aSMichael Chan __le16 seq_id; 739457922b0aSMichael Chan __le16 resp_len; 739557922b0aSMichael Chan __le32 decap_filter_id; 7396894aa69aSMichael Chan u8 unused_0[3]; 739757922b0aSMichael Chan u8 valid; 739857922b0aSMichael Chan }; 739957922b0aSMichael Chan 7400894aa69aSMichael Chan /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 740157922b0aSMichael Chan struct hwrm_cfa_decap_filter_free_input { 740257922b0aSMichael Chan __le16 req_type; 740357922b0aSMichael Chan __le16 cmpl_ring; 740457922b0aSMichael Chan __le16 seq_id; 740557922b0aSMichael Chan __le16 target_id; 740657922b0aSMichael Chan __le64 resp_addr; 740757922b0aSMichael Chan __le32 decap_filter_id; 7408894aa69aSMichael Chan u8 unused_0[4]; 740957922b0aSMichael Chan }; 741057922b0aSMichael Chan 7411894aa69aSMichael Chan /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 741257922b0aSMichael Chan struct hwrm_cfa_decap_filter_free_output { 741357922b0aSMichael Chan __le16 error_code; 741457922b0aSMichael Chan __le16 req_type; 741557922b0aSMichael Chan __le16 seq_id; 741657922b0aSMichael Chan __le16 resp_len; 7417894aa69aSMichael Chan u8 unused_0[7]; 741857922b0aSMichael Chan u8 valid; 741957922b0aSMichael Chan }; 742057922b0aSMichael Chan 7421894aa69aSMichael Chan /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 74226a17eb27SMichael Chan struct hwrm_cfa_flow_alloc_input { 74236a17eb27SMichael Chan __le16 req_type; 74246a17eb27SMichael Chan __le16 cmpl_ring; 74256a17eb27SMichael Chan __le16 seq_id; 74266a17eb27SMichael Chan __le16 target_id; 74276a17eb27SMichael Chan __le64 resp_addr; 74286a17eb27SMichael Chan __le16 flags; 74296a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 74306a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 74316a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 74326a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 74336a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 74346a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 74356a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 74366a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 74376a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 74386a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 74396a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 74406a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 74416a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 744231d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 744331d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 744431d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 74453322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 74466a17eb27SMichael Chan __le16 src_fid; 74476a17eb27SMichael Chan __le32 tunnel_handle; 74486a17eb27SMichael Chan __le16 action_flags; 74496a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 74506a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 74516a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 74526a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 74536a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 74546a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 74556a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 74566a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 74576a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 74586a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 745931d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 74603322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 74613322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 74624a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 74636a17eb27SMichael Chan __le16 dst_fid; 74646a17eb27SMichael Chan __be16 l2_rewrite_vlan_tpid; 74656a17eb27SMichael Chan __be16 l2_rewrite_vlan_tci; 74666a17eb27SMichael Chan __le16 act_meter_id; 74676a17eb27SMichael Chan __le16 ref_flow_handle; 74686a17eb27SMichael Chan __be16 ethertype; 74696a17eb27SMichael Chan __be16 outer_vlan_tci; 74706a17eb27SMichael Chan __be16 dmac[3]; 74716a17eb27SMichael Chan __be16 inner_vlan_tci; 74726a17eb27SMichael Chan __be16 smac[3]; 74736a17eb27SMichael Chan u8 ip_dst_mask_len; 74746a17eb27SMichael Chan u8 ip_src_mask_len; 74756a17eb27SMichael Chan __be32 ip_dst[4]; 74766a17eb27SMichael Chan __be32 ip_src[4]; 74776a17eb27SMichael Chan __be16 l4_src_port; 74786a17eb27SMichael Chan __be16 l4_src_port_mask; 74796a17eb27SMichael Chan __be16 l4_dst_port; 74806a17eb27SMichael Chan __be16 l4_dst_port_mask; 74816a17eb27SMichael Chan __be32 nat_ip_address[4]; 74826a17eb27SMichael Chan __be16 l2_rewrite_dmac[3]; 74836a17eb27SMichael Chan __be16 nat_port; 74846a17eb27SMichael Chan __be16 l2_rewrite_smac[3]; 74856a17eb27SMichael Chan u8 ip_proto; 748631d357c0SMichael Chan u8 tunnel_type; 748731d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 748831d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 748931d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 749031d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 749131d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 749231d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 749331d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 749431d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 749531d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 749631d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 749731d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 749831d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 74993322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 750031d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 750131d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 75026a17eb27SMichael Chan }; 75036a17eb27SMichael Chan 750431d357c0SMichael Chan /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 75056a17eb27SMichael Chan struct hwrm_cfa_flow_alloc_output { 75066a17eb27SMichael Chan __le16 error_code; 75076a17eb27SMichael Chan __le16 req_type; 75086a17eb27SMichael Chan __le16 seq_id; 75096a17eb27SMichael Chan __le16 resp_len; 75106a17eb27SMichael Chan __le16 flow_handle; 751131d357c0SMichael Chan u8 unused_0[2]; 751231d357c0SMichael Chan __le32 flow_id; 75134a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 75144a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 75154a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 75164a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 75174a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 75184a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 75194a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 75204a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 75214a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 75224a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 752331d357c0SMichael Chan __le64 ext_flow_handle; 75243322479eSMichael Chan __le32 flow_counter_id; 75253322479eSMichael Chan u8 unused_1[3]; 75266a17eb27SMichael Chan u8 valid; 75276a17eb27SMichael Chan }; 75286a17eb27SMichael Chan 75292792b5b9SMichael Chan /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 75302792b5b9SMichael Chan struct hwrm_cfa_flow_alloc_cmd_err { 75312792b5b9SMichael Chan u8 code; 75322792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 75332792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 75342792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 75352792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 75362792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 75372792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 75382792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 75392792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 75402792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 75412792b5b9SMichael Chan u8 unused_0[7]; 75422792b5b9SMichael Chan }; 75432792b5b9SMichael Chan 754431d357c0SMichael Chan /* hwrm_cfa_flow_free_input (size:256b/32B) */ 75456a17eb27SMichael Chan struct hwrm_cfa_flow_free_input { 75466a17eb27SMichael Chan __le16 req_type; 75476a17eb27SMichael Chan __le16 cmpl_ring; 75486a17eb27SMichael Chan __le16 seq_id; 75496a17eb27SMichael Chan __le16 target_id; 75506a17eb27SMichael Chan __le64 resp_addr; 75516a17eb27SMichael Chan __le16 flow_handle; 75524a50ddc2SMichael Chan __le16 unused_0; 75534a50ddc2SMichael Chan __le32 flow_counter_id; 755431d357c0SMichael Chan __le64 ext_flow_handle; 75556a17eb27SMichael Chan }; 75566a17eb27SMichael Chan 7557894aa69aSMichael Chan /* hwrm_cfa_flow_free_output (size:256b/32B) */ 75586a17eb27SMichael Chan struct hwrm_cfa_flow_free_output { 75596a17eb27SMichael Chan __le16 error_code; 75606a17eb27SMichael Chan __le16 req_type; 75616a17eb27SMichael Chan __le16 seq_id; 75626a17eb27SMichael Chan __le16 resp_len; 75636a17eb27SMichael Chan __le64 packet; 75646a17eb27SMichael Chan __le64 byte; 7565894aa69aSMichael Chan u8 unused_0[7]; 75666a17eb27SMichael Chan u8 valid; 75676a17eb27SMichael Chan }; 75686a17eb27SMichael Chan 75693322479eSMichael Chan /* hwrm_cfa_flow_info_input (size:256b/32B) */ 75703322479eSMichael Chan struct hwrm_cfa_flow_info_input { 75713322479eSMichael Chan __le16 req_type; 75723322479eSMichael Chan __le16 cmpl_ring; 75733322479eSMichael Chan __le16 seq_id; 75743322479eSMichael Chan __le16 target_id; 75753322479eSMichael Chan __le64 resp_addr; 75763322479eSMichael Chan __le16 flow_handle; 75773322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 75783322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 75793322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 75803322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 75813322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 75823322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 75833322479eSMichael Chan u8 unused_0[6]; 75843322479eSMichael Chan __le64 ext_flow_handle; 75853322479eSMichael Chan }; 75863322479eSMichael Chan 75873293ec23SMichael Chan /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 75883322479eSMichael Chan struct hwrm_cfa_flow_info_output { 75893322479eSMichael Chan __le16 error_code; 75903322479eSMichael Chan __le16 req_type; 75913322479eSMichael Chan __le16 seq_id; 75923322479eSMichael Chan __le16 resp_len; 75933322479eSMichael Chan u8 flags; 75943293ec23SMichael Chan #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 75953293ec23SMichael Chan #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 75963322479eSMichael Chan u8 profile; 75973322479eSMichael Chan __le16 src_fid; 75983322479eSMichael Chan __le16 dst_fid; 75993322479eSMichael Chan __le16 l2_ctxt_id; 76003322479eSMichael Chan __le64 em_info; 76013322479eSMichael Chan __le64 tcam_info; 76023322479eSMichael Chan __le64 vfp_tcam_info; 76033322479eSMichael Chan __le16 ar_id; 76043322479eSMichael Chan __le16 flow_handle; 76053322479eSMichael Chan __le32 tunnel_handle; 76063322479eSMichael Chan __le16 flow_timer; 76073293ec23SMichael Chan u8 unused_0[6]; 76083293ec23SMichael Chan __le32 flow_key_data[130]; 76093293ec23SMichael Chan __le32 flow_action_info[30]; 76103293ec23SMichael Chan u8 unused_1[7]; 76113322479eSMichael Chan u8 valid; 76123322479eSMichael Chan }; 76133322479eSMichael Chan 761431d357c0SMichael Chan /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 76156a17eb27SMichael Chan struct hwrm_cfa_flow_stats_input { 76166a17eb27SMichael Chan __le16 req_type; 76176a17eb27SMichael Chan __le16 cmpl_ring; 76186a17eb27SMichael Chan __le16 seq_id; 76196a17eb27SMichael Chan __le16 target_id; 76206a17eb27SMichael Chan __le64 resp_addr; 76216a17eb27SMichael Chan __le16 num_flows; 76226a17eb27SMichael Chan __le16 flow_handle_0; 76236a17eb27SMichael Chan __le16 flow_handle_1; 76246a17eb27SMichael Chan __le16 flow_handle_2; 76256a17eb27SMichael Chan __le16 flow_handle_3; 76266a17eb27SMichael Chan __le16 flow_handle_4; 76276a17eb27SMichael Chan __le16 flow_handle_5; 76286a17eb27SMichael Chan __le16 flow_handle_6; 76296a17eb27SMichael Chan __le16 flow_handle_7; 76306a17eb27SMichael Chan __le16 flow_handle_8; 76316a17eb27SMichael Chan __le16 flow_handle_9; 7632894aa69aSMichael Chan u8 unused_0[2]; 763331d357c0SMichael Chan __le32 flow_id_0; 763431d357c0SMichael Chan __le32 flow_id_1; 763531d357c0SMichael Chan __le32 flow_id_2; 763631d357c0SMichael Chan __le32 flow_id_3; 763731d357c0SMichael Chan __le32 flow_id_4; 763831d357c0SMichael Chan __le32 flow_id_5; 763931d357c0SMichael Chan __le32 flow_id_6; 764031d357c0SMichael Chan __le32 flow_id_7; 764131d357c0SMichael Chan __le32 flow_id_8; 764231d357c0SMichael Chan __le32 flow_id_9; 76436a17eb27SMichael Chan }; 76446a17eb27SMichael Chan 7645894aa69aSMichael Chan /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 76466a17eb27SMichael Chan struct hwrm_cfa_flow_stats_output { 76476a17eb27SMichael Chan __le16 error_code; 76486a17eb27SMichael Chan __le16 req_type; 76496a17eb27SMichael Chan __le16 seq_id; 76506a17eb27SMichael Chan __le16 resp_len; 76516a17eb27SMichael Chan __le64 packet_0; 76526a17eb27SMichael Chan __le64 packet_1; 76536a17eb27SMichael Chan __le64 packet_2; 76546a17eb27SMichael Chan __le64 packet_3; 76556a17eb27SMichael Chan __le64 packet_4; 76566a17eb27SMichael Chan __le64 packet_5; 76576a17eb27SMichael Chan __le64 packet_6; 76586a17eb27SMichael Chan __le64 packet_7; 76596a17eb27SMichael Chan __le64 packet_8; 76606a17eb27SMichael Chan __le64 packet_9; 76616a17eb27SMichael Chan __le64 byte_0; 76626a17eb27SMichael Chan __le64 byte_1; 76636a17eb27SMichael Chan __le64 byte_2; 76646a17eb27SMichael Chan __le64 byte_3; 76656a17eb27SMichael Chan __le64 byte_4; 76666a17eb27SMichael Chan __le64 byte_5; 76676a17eb27SMichael Chan __le64 byte_6; 76686a17eb27SMichael Chan __le64 byte_7; 76696a17eb27SMichael Chan __le64 byte_8; 76706a17eb27SMichael Chan __le64 byte_9; 7671894aa69aSMichael Chan u8 unused_0[7]; 76726a17eb27SMichael Chan u8 valid; 76736a17eb27SMichael Chan }; 76746a17eb27SMichael Chan 7675894aa69aSMichael Chan /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 7676acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_input { 7677acb20054SMichael Chan __le16 req_type; 7678acb20054SMichael Chan __le16 cmpl_ring; 7679acb20054SMichael Chan __le16 seq_id; 7680acb20054SMichael Chan __le16 target_id; 7681acb20054SMichael Chan __le64 resp_addr; 7682acb20054SMichael Chan __le16 vf_id; 7683acb20054SMichael Chan __le16 reserved; 7684894aa69aSMichael Chan u8 unused_0[4]; 7685acb20054SMichael Chan char vfr_name[32]; 7686acb20054SMichael Chan }; 7687acb20054SMichael Chan 7688894aa69aSMichael Chan /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 7689acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_output { 7690acb20054SMichael Chan __le16 error_code; 7691acb20054SMichael Chan __le16 req_type; 7692acb20054SMichael Chan __le16 seq_id; 7693acb20054SMichael Chan __le16 resp_len; 7694acb20054SMichael Chan __le16 rx_cfa_code; 7695acb20054SMichael Chan __le16 tx_cfa_action; 7696894aa69aSMichael Chan u8 unused_0[3]; 7697acb20054SMichael Chan u8 valid; 7698acb20054SMichael Chan }; 7699acb20054SMichael Chan 77009d6b648cSMichael Chan /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 7701acb20054SMichael Chan struct hwrm_cfa_vfr_free_input { 7702acb20054SMichael Chan __le16 req_type; 7703acb20054SMichael Chan __le16 cmpl_ring; 7704acb20054SMichael Chan __le16 seq_id; 7705acb20054SMichael Chan __le16 target_id; 7706acb20054SMichael Chan __le64 resp_addr; 7707acb20054SMichael Chan char vfr_name[32]; 77089d6b648cSMichael Chan __le16 vf_id; 77099d6b648cSMichael Chan __le16 reserved; 77109d6b648cSMichael Chan u8 unused_0[4]; 7711acb20054SMichael Chan }; 7712acb20054SMichael Chan 7713894aa69aSMichael Chan /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 7714acb20054SMichael Chan struct hwrm_cfa_vfr_free_output { 7715acb20054SMichael Chan __le16 error_code; 7716acb20054SMichael Chan __le16 req_type; 7717acb20054SMichael Chan __le16 seq_id; 7718acb20054SMichael Chan __le16 resp_len; 7719894aa69aSMichael Chan u8 unused_0[7]; 7720acb20054SMichael Chan u8 valid; 7721acb20054SMichael Chan }; 7722acb20054SMichael Chan 77233322479eSMichael Chan /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 77243322479eSMichael Chan struct hwrm_cfa_eem_qcaps_input { 77253322479eSMichael Chan __le16 req_type; 77263322479eSMichael Chan __le16 cmpl_ring; 77273322479eSMichael Chan __le16 seq_id; 77283322479eSMichael Chan __le16 target_id; 77293322479eSMichael Chan __le64 resp_addr; 77303322479eSMichael Chan __le32 flags; 77313322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 77323322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 77333322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 77343322479eSMichael Chan __le32 unused_0; 77353322479eSMichael Chan }; 77363322479eSMichael Chan 77372792b5b9SMichael Chan /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 77383322479eSMichael Chan struct hwrm_cfa_eem_qcaps_output { 77393322479eSMichael Chan __le16 error_code; 77403322479eSMichael Chan __le16 req_type; 77413322479eSMichael Chan __le16 seq_id; 77423322479eSMichael Chan __le16 resp_len; 77433322479eSMichael Chan __le32 flags; 77443322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 77453322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 77464a50ddc2SMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 77474a50ddc2SMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 77483322479eSMichael Chan __le32 unused_0; 77493322479eSMichael Chan __le32 supported; 77503322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 77513322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 77523322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 77533322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 77542792b5b9SMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 77553322479eSMichael Chan __le32 max_entries_supported; 77563322479eSMichael Chan __le16 key_entry_size; 77573322479eSMichael Chan __le16 record_entry_size; 77583322479eSMichael Chan __le16 efc_entry_size; 77592792b5b9SMichael Chan __le16 fid_entry_size; 77602792b5b9SMichael Chan u8 unused_1[7]; 77613322479eSMichael Chan u8 valid; 77623322479eSMichael Chan }; 77633322479eSMichael Chan 77642792b5b9SMichael Chan /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 77653322479eSMichael Chan struct hwrm_cfa_eem_cfg_input { 77663322479eSMichael Chan __le16 req_type; 77673322479eSMichael Chan __le16 cmpl_ring; 77683322479eSMichael Chan __le16 seq_id; 77693322479eSMichael Chan __le16 target_id; 77703322479eSMichael Chan __le64 resp_addr; 77713322479eSMichael Chan __le32 flags; 77723322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 77733322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 77743322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 77754a50ddc2SMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 77764a50ddc2SMichael Chan __le16 group_id; 77774a50ddc2SMichael Chan __le16 unused_0; 77783322479eSMichael Chan __le32 num_entries; 77793322479eSMichael Chan __le32 unused_1; 77803322479eSMichael Chan __le16 key0_ctx_id; 77813322479eSMichael Chan __le16 key1_ctx_id; 77823322479eSMichael Chan __le16 record_ctx_id; 77833322479eSMichael Chan __le16 efc_ctx_id; 77842792b5b9SMichael Chan __le16 fid_ctx_id; 77852792b5b9SMichael Chan __le16 unused_2; 77862792b5b9SMichael Chan __le32 unused_3; 77873322479eSMichael Chan }; 77883322479eSMichael Chan 77893322479eSMichael Chan /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 77903322479eSMichael Chan struct hwrm_cfa_eem_cfg_output { 77913322479eSMichael Chan __le16 error_code; 77923322479eSMichael Chan __le16 req_type; 77933322479eSMichael Chan __le16 seq_id; 77943322479eSMichael Chan __le16 resp_len; 77953322479eSMichael Chan u8 unused_0[7]; 77963322479eSMichael Chan u8 valid; 77973322479eSMichael Chan }; 77983322479eSMichael Chan 77993322479eSMichael Chan /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 78003322479eSMichael Chan struct hwrm_cfa_eem_qcfg_input { 78013322479eSMichael Chan __le16 req_type; 78023322479eSMichael Chan __le16 cmpl_ring; 78033322479eSMichael Chan __le16 seq_id; 78043322479eSMichael Chan __le16 target_id; 78053322479eSMichael Chan __le64 resp_addr; 78063322479eSMichael Chan __le32 flags; 78073322479eSMichael Chan #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 78083322479eSMichael Chan #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 78093322479eSMichael Chan __le32 unused_0; 78103322479eSMichael Chan }; 78113322479eSMichael Chan 78122792b5b9SMichael Chan /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 78133322479eSMichael Chan struct hwrm_cfa_eem_qcfg_output { 78143322479eSMichael Chan __le16 error_code; 78153322479eSMichael Chan __le16 req_type; 78163322479eSMichael Chan __le16 seq_id; 78173322479eSMichael Chan __le16 resp_len; 78183322479eSMichael Chan __le32 flags; 78193322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 78203322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 78213322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 78223322479eSMichael Chan __le32 num_entries; 78232792b5b9SMichael Chan __le16 key0_ctx_id; 78242792b5b9SMichael Chan __le16 key1_ctx_id; 78252792b5b9SMichael Chan __le16 record_ctx_id; 78262792b5b9SMichael Chan __le16 efc_ctx_id; 78272792b5b9SMichael Chan __le16 fid_ctx_id; 78282792b5b9SMichael Chan u8 unused_2[5]; 78294a50ddc2SMichael Chan u8 valid; 78303322479eSMichael Chan }; 78313322479eSMichael Chan 78323322479eSMichael Chan /* hwrm_cfa_eem_op_input (size:192b/24B) */ 78333322479eSMichael Chan struct hwrm_cfa_eem_op_input { 78343322479eSMichael Chan __le16 req_type; 78353322479eSMichael Chan __le16 cmpl_ring; 78363322479eSMichael Chan __le16 seq_id; 78373322479eSMichael Chan __le16 target_id; 78383322479eSMichael Chan __le64 resp_addr; 78393322479eSMichael Chan __le32 flags; 78403322479eSMichael Chan #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 78413322479eSMichael Chan #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 78423322479eSMichael Chan __le16 unused_0; 78433322479eSMichael Chan __le16 op; 78443322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 78453322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 78463322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 78473322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 78483322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 78493322479eSMichael Chan }; 78503322479eSMichael Chan 78513322479eSMichael Chan /* hwrm_cfa_eem_op_output (size:128b/16B) */ 78523322479eSMichael Chan struct hwrm_cfa_eem_op_output { 78533322479eSMichael Chan __le16 error_code; 78543322479eSMichael Chan __le16 req_type; 78553322479eSMichael Chan __le16 seq_id; 78563322479eSMichael Chan __le16 resp_len; 78573322479eSMichael Chan u8 unused_0[7]; 78583322479eSMichael Chan u8 valid; 78593322479eSMichael Chan }; 78603322479eSMichael Chan 78614a50ddc2SMichael Chan /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 78624a50ddc2SMichael Chan struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 78634a50ddc2SMichael Chan __le16 req_type; 78644a50ddc2SMichael Chan __le16 cmpl_ring; 78654a50ddc2SMichael Chan __le16 seq_id; 78664a50ddc2SMichael Chan __le16 target_id; 78674a50ddc2SMichael Chan __le64 resp_addr; 78684a50ddc2SMichael Chan __le32 unused_0[4]; 78694a50ddc2SMichael Chan }; 78704a50ddc2SMichael Chan 78714a50ddc2SMichael Chan /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 78724a50ddc2SMichael Chan struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 78734a50ddc2SMichael Chan __le16 error_code; 78744a50ddc2SMichael Chan __le16 req_type; 78754a50ddc2SMichael Chan __le16 seq_id; 78764a50ddc2SMichael Chan __le16 resp_len; 78774a50ddc2SMichael Chan __le32 flags; 78784a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 78794a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 78804a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 78814a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 78824a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 78834a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 78844a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 78854a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 78864a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 78874a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 78884a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 78894a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 789041136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 789141136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 789241136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 789316db6323SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 789416db6323SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 789578eeadb8SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 7896*21e70778SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 78974a50ddc2SMichael Chan u8 unused_0[3]; 78984a50ddc2SMichael Chan u8 valid; 78994a50ddc2SMichael Chan }; 79004a50ddc2SMichael Chan 7901c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_input { 7902c0c050c5SMichael Chan __le16 req_type; 7903c0c050c5SMichael Chan __le16 cmpl_ring; 7904c0c050c5SMichael Chan __le16 seq_id; 7905c0c050c5SMichael Chan __le16 target_id; 7906c0c050c5SMichael Chan __le64 resp_addr; 7907c0c050c5SMichael Chan u8 tunnel_type; 7908441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7909441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 791057922b0aSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 79116fc92c33SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 791231d357c0SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 79133322479eSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 79143322479eSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7915c0c050c5SMichael Chan u8 unused_0[7]; 7916c0c050c5SMichael Chan }; 7917c0c050c5SMichael Chan 7918894aa69aSMichael Chan /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7919c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_output { 7920c0c050c5SMichael Chan __le16 error_code; 7921c0c050c5SMichael Chan __le16 req_type; 7922c0c050c5SMichael Chan __le16 seq_id; 7923c0c050c5SMichael Chan __le16 resp_len; 7924c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 7925c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 7926894aa69aSMichael Chan u8 unused_0[3]; 7927c0c050c5SMichael Chan u8 valid; 7928c0c050c5SMichael Chan }; 7929c0c050c5SMichael Chan 7930894aa69aSMichael Chan /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7931c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_input { 7932c0c050c5SMichael Chan __le16 req_type; 7933c0c050c5SMichael Chan __le16 cmpl_ring; 7934c0c050c5SMichael Chan __le16 seq_id; 7935c0c050c5SMichael Chan __le16 target_id; 7936c0c050c5SMichael Chan __le64 resp_addr; 7937c0c050c5SMichael Chan u8 tunnel_type; 7938441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7939441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 794057922b0aSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 79416fc92c33SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 794231d357c0SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 79433322479eSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 79443322479eSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7945c0c050c5SMichael Chan u8 unused_0; 7946c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 7947894aa69aSMichael Chan u8 unused_1[4]; 7948c0c050c5SMichael Chan }; 7949c0c050c5SMichael Chan 7950894aa69aSMichael Chan /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7951c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_output { 7952c0c050c5SMichael Chan __le16 error_code; 7953c0c050c5SMichael Chan __le16 req_type; 7954c0c050c5SMichael Chan __le16 seq_id; 7955c0c050c5SMichael Chan __le16 resp_len; 7956c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 7957894aa69aSMichael Chan u8 unused_0[5]; 7958c0c050c5SMichael Chan u8 valid; 7959c0c050c5SMichael Chan }; 7960c0c050c5SMichael Chan 7961894aa69aSMichael Chan /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7962c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_input { 7963c0c050c5SMichael Chan __le16 req_type; 7964c0c050c5SMichael Chan __le16 cmpl_ring; 7965c0c050c5SMichael Chan __le16 seq_id; 7966c0c050c5SMichael Chan __le16 target_id; 7967c0c050c5SMichael Chan __le64 resp_addr; 7968c0c050c5SMichael Chan u8 tunnel_type; 7969441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7970441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 797157922b0aSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 79726fc92c33SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 797331d357c0SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 79743322479eSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 79753322479eSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7976c0c050c5SMichael Chan u8 unused_0; 7977c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 7978894aa69aSMichael Chan u8 unused_1[4]; 7979c0c050c5SMichael Chan }; 7980c0c050c5SMichael Chan 7981894aa69aSMichael Chan /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7982c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_output { 7983c0c050c5SMichael Chan __le16 error_code; 7984c0c050c5SMichael Chan __le16 req_type; 7985c0c050c5SMichael Chan __le16 seq_id; 7986c0c050c5SMichael Chan __le16 resp_len; 7987894aa69aSMichael Chan u8 unused_1[7]; 7988c0c050c5SMichael Chan u8 valid; 7989c0c050c5SMichael Chan }; 7990c0c050c5SMichael Chan 7991894aa69aSMichael Chan /* ctx_hw_stats (size:1280b/160B) */ 7992894aa69aSMichael Chan struct ctx_hw_stats { 7993894aa69aSMichael Chan __le64 rx_ucast_pkts; 7994894aa69aSMichael Chan __le64 rx_mcast_pkts; 7995894aa69aSMichael Chan __le64 rx_bcast_pkts; 7996894aa69aSMichael Chan __le64 rx_discard_pkts; 7997bfc6e5fbSMichael Chan __le64 rx_error_pkts; 7998894aa69aSMichael Chan __le64 rx_ucast_bytes; 7999894aa69aSMichael Chan __le64 rx_mcast_bytes; 8000894aa69aSMichael Chan __le64 rx_bcast_bytes; 8001894aa69aSMichael Chan __le64 tx_ucast_pkts; 8002894aa69aSMichael Chan __le64 tx_mcast_pkts; 8003894aa69aSMichael Chan __le64 tx_bcast_pkts; 8004bfc6e5fbSMichael Chan __le64 tx_error_pkts; 8005894aa69aSMichael Chan __le64 tx_discard_pkts; 8006894aa69aSMichael Chan __le64 tx_ucast_bytes; 8007894aa69aSMichael Chan __le64 tx_mcast_bytes; 8008894aa69aSMichael Chan __le64 tx_bcast_bytes; 8009894aa69aSMichael Chan __le64 tpa_pkts; 8010894aa69aSMichael Chan __le64 tpa_bytes; 8011894aa69aSMichael Chan __le64 tpa_events; 8012894aa69aSMichael Chan __le64 tpa_aborts; 8013894aa69aSMichael Chan }; 8014894aa69aSMichael Chan 80159d6b648cSMichael Chan /* ctx_hw_stats_ext (size:1408b/176B) */ 80162792b5b9SMichael Chan struct ctx_hw_stats_ext { 80172792b5b9SMichael Chan __le64 rx_ucast_pkts; 80182792b5b9SMichael Chan __le64 rx_mcast_pkts; 80192792b5b9SMichael Chan __le64 rx_bcast_pkts; 80202792b5b9SMichael Chan __le64 rx_discard_pkts; 8021bfc6e5fbSMichael Chan __le64 rx_error_pkts; 80222792b5b9SMichael Chan __le64 rx_ucast_bytes; 80232792b5b9SMichael Chan __le64 rx_mcast_bytes; 80242792b5b9SMichael Chan __le64 rx_bcast_bytes; 80252792b5b9SMichael Chan __le64 tx_ucast_pkts; 80262792b5b9SMichael Chan __le64 tx_mcast_pkts; 80272792b5b9SMichael Chan __le64 tx_bcast_pkts; 8028bfc6e5fbSMichael Chan __le64 tx_error_pkts; 80292792b5b9SMichael Chan __le64 tx_discard_pkts; 80302792b5b9SMichael Chan __le64 tx_ucast_bytes; 80312792b5b9SMichael Chan __le64 tx_mcast_bytes; 80322792b5b9SMichael Chan __le64 tx_bcast_bytes; 80332792b5b9SMichael Chan __le64 rx_tpa_eligible_pkt; 80342792b5b9SMichael Chan __le64 rx_tpa_eligible_bytes; 80352792b5b9SMichael Chan __le64 rx_tpa_pkt; 80362792b5b9SMichael Chan __le64 rx_tpa_bytes; 80372792b5b9SMichael Chan __le64 rx_tpa_errors; 80389d6b648cSMichael Chan __le64 rx_tpa_events; 80392792b5b9SMichael Chan }; 80402792b5b9SMichael Chan 8041894aa69aSMichael Chan /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 8042c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_input { 8043c0c050c5SMichael Chan __le16 req_type; 8044c0c050c5SMichael Chan __le16 cmpl_ring; 8045c0c050c5SMichael Chan __le16 seq_id; 8046c0c050c5SMichael Chan __le16 target_id; 8047c0c050c5SMichael Chan __le64 resp_addr; 8048c0c050c5SMichael Chan __le64 stats_dma_addr; 8049c0c050c5SMichael Chan __le32 update_period_ms; 805087c374deSMichael Chan u8 stat_ctx_flags; 805187c374deSMichael Chan #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 80522792b5b9SMichael Chan u8 unused_0; 80532792b5b9SMichael Chan __le16 stats_dma_length; 8054c0c050c5SMichael Chan }; 8055c0c050c5SMichael Chan 8056894aa69aSMichael Chan /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 8057c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_output { 8058c0c050c5SMichael Chan __le16 error_code; 8059c0c050c5SMichael Chan __le16 req_type; 8060c0c050c5SMichael Chan __le16 seq_id; 8061c0c050c5SMichael Chan __le16 resp_len; 8062c0c050c5SMichael Chan __le32 stat_ctx_id; 8063894aa69aSMichael Chan u8 unused_0[3]; 8064c0c050c5SMichael Chan u8 valid; 8065c0c050c5SMichael Chan }; 8066c0c050c5SMichael Chan 8067894aa69aSMichael Chan /* hwrm_stat_ctx_free_input (size:192b/24B) */ 8068c0c050c5SMichael Chan struct hwrm_stat_ctx_free_input { 8069c0c050c5SMichael Chan __le16 req_type; 8070c0c050c5SMichael Chan __le16 cmpl_ring; 8071c0c050c5SMichael Chan __le16 seq_id; 8072c0c050c5SMichael Chan __le16 target_id; 8073c0c050c5SMichael Chan __le64 resp_addr; 8074c0c050c5SMichael Chan __le32 stat_ctx_id; 8075894aa69aSMichael Chan u8 unused_0[4]; 8076c0c050c5SMichael Chan }; 8077c0c050c5SMichael Chan 8078894aa69aSMichael Chan /* hwrm_stat_ctx_free_output (size:128b/16B) */ 8079c0c050c5SMichael Chan struct hwrm_stat_ctx_free_output { 8080c0c050c5SMichael Chan __le16 error_code; 8081c0c050c5SMichael Chan __le16 req_type; 8082c0c050c5SMichael Chan __le16 seq_id; 8083c0c050c5SMichael Chan __le16 resp_len; 8084c0c050c5SMichael Chan __le32 stat_ctx_id; 8085894aa69aSMichael Chan u8 unused_0[3]; 8086c0c050c5SMichael Chan u8 valid; 8087c0c050c5SMichael Chan }; 8088c0c050c5SMichael Chan 8089894aa69aSMichael Chan /* hwrm_stat_ctx_query_input (size:192b/24B) */ 8090c0c050c5SMichael Chan struct hwrm_stat_ctx_query_input { 8091c0c050c5SMichael Chan __le16 req_type; 8092c0c050c5SMichael Chan __le16 cmpl_ring; 8093c0c050c5SMichael Chan __le16 seq_id; 8094c0c050c5SMichael Chan __le16 target_id; 8095c0c050c5SMichael Chan __le64 resp_addr; 8096c0c050c5SMichael Chan __le32 stat_ctx_id; 8097bfc6e5fbSMichael Chan u8 flags; 8098bfc6e5fbSMichael Chan #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8099bfc6e5fbSMichael Chan u8 unused_0[3]; 8100c0c050c5SMichael Chan }; 8101c0c050c5SMichael Chan 8102894aa69aSMichael Chan /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 8103c0c050c5SMichael Chan struct hwrm_stat_ctx_query_output { 8104c0c050c5SMichael Chan __le16 error_code; 8105c0c050c5SMichael Chan __le16 req_type; 8106c0c050c5SMichael Chan __le16 seq_id; 8107c0c050c5SMichael Chan __le16 resp_len; 8108c0c050c5SMichael Chan __le64 tx_ucast_pkts; 8109c0c050c5SMichael Chan __le64 tx_mcast_pkts; 8110c0c050c5SMichael Chan __le64 tx_bcast_pkts; 81119d6b648cSMichael Chan __le64 tx_discard_pkts; 81129d6b648cSMichael Chan __le64 tx_error_pkts; 8113c0c050c5SMichael Chan __le64 tx_ucast_bytes; 8114c0c050c5SMichael Chan __le64 tx_mcast_bytes; 8115c0c050c5SMichael Chan __le64 tx_bcast_bytes; 8116c0c050c5SMichael Chan __le64 rx_ucast_pkts; 8117c0c050c5SMichael Chan __le64 rx_mcast_pkts; 8118c0c050c5SMichael Chan __le64 rx_bcast_pkts; 81199d6b648cSMichael Chan __le64 rx_discard_pkts; 81209d6b648cSMichael Chan __le64 rx_error_pkts; 8121c0c050c5SMichael Chan __le64 rx_ucast_bytes; 8122c0c050c5SMichael Chan __le64 rx_mcast_bytes; 8123c0c050c5SMichael Chan __le64 rx_bcast_bytes; 8124c0c050c5SMichael Chan __le64 rx_agg_pkts; 8125c0c050c5SMichael Chan __le64 rx_agg_bytes; 8126c0c050c5SMichael Chan __le64 rx_agg_events; 8127c0c050c5SMichael Chan __le64 rx_agg_aborts; 8128894aa69aSMichael Chan u8 unused_0[7]; 8129c0c050c5SMichael Chan u8 valid; 8130c0c050c5SMichael Chan }; 8131c0c050c5SMichael Chan 8132bfc6e5fbSMichael Chan /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 8133bfc6e5fbSMichael Chan struct hwrm_stat_ext_ctx_query_input { 8134bfc6e5fbSMichael Chan __le16 req_type; 8135bfc6e5fbSMichael Chan __le16 cmpl_ring; 8136bfc6e5fbSMichael Chan __le16 seq_id; 8137bfc6e5fbSMichael Chan __le16 target_id; 8138bfc6e5fbSMichael Chan __le64 resp_addr; 8139bfc6e5fbSMichael Chan __le32 stat_ctx_id; 8140bfc6e5fbSMichael Chan u8 flags; 8141bfc6e5fbSMichael Chan #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 8142bfc6e5fbSMichael Chan u8 unused_0[3]; 8143bfc6e5fbSMichael Chan }; 8144bfc6e5fbSMichael Chan 81459d6b648cSMichael Chan /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 8146bfc6e5fbSMichael Chan struct hwrm_stat_ext_ctx_query_output { 8147bfc6e5fbSMichael Chan __le16 error_code; 8148bfc6e5fbSMichael Chan __le16 req_type; 8149bfc6e5fbSMichael Chan __le16 seq_id; 8150bfc6e5fbSMichael Chan __le16 resp_len; 8151bfc6e5fbSMichael Chan __le64 rx_ucast_pkts; 8152bfc6e5fbSMichael Chan __le64 rx_mcast_pkts; 8153bfc6e5fbSMichael Chan __le64 rx_bcast_pkts; 8154bfc6e5fbSMichael Chan __le64 rx_discard_pkts; 8155bfc6e5fbSMichael Chan __le64 rx_error_pkts; 8156bfc6e5fbSMichael Chan __le64 rx_ucast_bytes; 8157bfc6e5fbSMichael Chan __le64 rx_mcast_bytes; 8158bfc6e5fbSMichael Chan __le64 rx_bcast_bytes; 8159bfc6e5fbSMichael Chan __le64 tx_ucast_pkts; 8160bfc6e5fbSMichael Chan __le64 tx_mcast_pkts; 8161bfc6e5fbSMichael Chan __le64 tx_bcast_pkts; 8162bfc6e5fbSMichael Chan __le64 tx_error_pkts; 8163bfc6e5fbSMichael Chan __le64 tx_discard_pkts; 8164bfc6e5fbSMichael Chan __le64 tx_ucast_bytes; 8165bfc6e5fbSMichael Chan __le64 tx_mcast_bytes; 8166bfc6e5fbSMichael Chan __le64 tx_bcast_bytes; 8167bfc6e5fbSMichael Chan __le64 rx_tpa_eligible_pkt; 8168bfc6e5fbSMichael Chan __le64 rx_tpa_eligible_bytes; 8169bfc6e5fbSMichael Chan __le64 rx_tpa_pkt; 8170bfc6e5fbSMichael Chan __le64 rx_tpa_bytes; 8171bfc6e5fbSMichael Chan __le64 rx_tpa_errors; 81729d6b648cSMichael Chan __le64 rx_tpa_events; 8173bfc6e5fbSMichael Chan u8 unused_0[7]; 8174bfc6e5fbSMichael Chan u8 valid; 8175bfc6e5fbSMichael Chan }; 8176bfc6e5fbSMichael Chan 8177894aa69aSMichael Chan /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 8178c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_input { 8179c0c050c5SMichael Chan __le16 req_type; 8180c0c050c5SMichael Chan __le16 cmpl_ring; 8181c0c050c5SMichael Chan __le16 seq_id; 8182c0c050c5SMichael Chan __le16 target_id; 8183c0c050c5SMichael Chan __le64 resp_addr; 8184c0c050c5SMichael Chan __le32 stat_ctx_id; 8185894aa69aSMichael Chan u8 unused_0[4]; 8186c0c050c5SMichael Chan }; 8187c0c050c5SMichael Chan 8188894aa69aSMichael Chan /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 8189c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_output { 8190c0c050c5SMichael Chan __le16 error_code; 8191c0c050c5SMichael Chan __le16 req_type; 8192c0c050c5SMichael Chan __le16 seq_id; 8193c0c050c5SMichael Chan __le16 resp_len; 819411f15ed3SMichael Chan u8 unused_0[7]; 819511f15ed3SMichael Chan u8 valid; 819611f15ed3SMichael Chan }; 819711f15ed3SMichael Chan 8198d4f52de0SMichael Chan /* hwrm_pcie_qstats_input (size:256b/32B) */ 8199d4f52de0SMichael Chan struct hwrm_pcie_qstats_input { 8200d4f52de0SMichael Chan __le16 req_type; 8201d4f52de0SMichael Chan __le16 cmpl_ring; 8202d4f52de0SMichael Chan __le16 seq_id; 8203d4f52de0SMichael Chan __le16 target_id; 8204d4f52de0SMichael Chan __le64 resp_addr; 8205d4f52de0SMichael Chan __le16 pcie_stat_size; 8206d4f52de0SMichael Chan u8 unused_0[6]; 8207d4f52de0SMichael Chan __le64 pcie_stat_host_addr; 8208d4f52de0SMichael Chan }; 8209d4f52de0SMichael Chan 8210d4f52de0SMichael Chan /* hwrm_pcie_qstats_output (size:128b/16B) */ 8211d4f52de0SMichael Chan struct hwrm_pcie_qstats_output { 8212d4f52de0SMichael Chan __le16 error_code; 8213d4f52de0SMichael Chan __le16 req_type; 8214d4f52de0SMichael Chan __le16 seq_id; 8215d4f52de0SMichael Chan __le16 resp_len; 8216d4f52de0SMichael Chan __le16 pcie_stat_size; 8217d4f52de0SMichael Chan u8 unused_0[5]; 8218d4f52de0SMichael Chan u8 valid; 8219d4f52de0SMichael Chan }; 8220d4f52de0SMichael Chan 8221d4f52de0SMichael Chan /* pcie_ctx_hw_stats (size:768b/96B) */ 8222d4f52de0SMichael Chan struct pcie_ctx_hw_stats { 8223d4f52de0SMichael Chan __le64 pcie_pl_signal_integrity; 8224d4f52de0SMichael Chan __le64 pcie_dl_signal_integrity; 8225d4f52de0SMichael Chan __le64 pcie_tl_signal_integrity; 8226d4f52de0SMichael Chan __le64 pcie_link_integrity; 8227d4f52de0SMichael Chan __le64 pcie_tx_traffic_rate; 8228d4f52de0SMichael Chan __le64 pcie_rx_traffic_rate; 8229d4f52de0SMichael Chan __le64 pcie_tx_dllp_statistics; 8230d4f52de0SMichael Chan __le64 pcie_rx_dllp_statistics; 8231d4f52de0SMichael Chan __le64 pcie_equalization_time; 8232d4f52de0SMichael Chan __le32 pcie_ltssm_histogram[4]; 8233d4f52de0SMichael Chan __le64 pcie_recovery_histogram; 8234d4f52de0SMichael Chan }; 8235d4f52de0SMichael Chan 8236894aa69aSMichael Chan /* hwrm_fw_reset_input (size:192b/24B) */ 8237894aa69aSMichael Chan struct hwrm_fw_reset_input { 8238894aa69aSMichael Chan __le16 req_type; 8239894aa69aSMichael Chan __le16 cmpl_ring; 8240894aa69aSMichael Chan __le16 seq_id; 8241894aa69aSMichael Chan __le16 target_id; 8242894aa69aSMichael Chan __le64 resp_addr; 8243894aa69aSMichael Chan u8 embedded_proc_type; 8244894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8245894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8246894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8247894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8248894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8249894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8250894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8251d4f52de0SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 825272e0c9f9SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 825372e0c9f9SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 8254894aa69aSMichael Chan u8 selfrst_status; 8255894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 8256894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 8257894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 825831d357c0SMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 825931d357c0SMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 8260894aa69aSMichael Chan u8 host_idx; 82613322479eSMichael Chan u8 flags; 82623322479eSMichael Chan #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 8263fbfee257SMichael Chan #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 82643322479eSMichael Chan u8 unused_0[4]; 826557922b0aSMichael Chan }; 826657922b0aSMichael Chan 8267894aa69aSMichael Chan /* hwrm_fw_reset_output (size:128b/16B) */ 8268894aa69aSMichael Chan struct hwrm_fw_reset_output { 8269894aa69aSMichael Chan __le16 error_code; 8270894aa69aSMichael Chan __le16 req_type; 8271894aa69aSMichael Chan __le16 seq_id; 8272894aa69aSMichael Chan __le16 resp_len; 8273894aa69aSMichael Chan u8 selfrst_status; 8274894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8275894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8276894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 827731d357c0SMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 827831d357c0SMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 8279894aa69aSMichael Chan u8 unused_0[6]; 8280894aa69aSMichael Chan u8 valid; 828157922b0aSMichael Chan }; 828257922b0aSMichael Chan 8283894aa69aSMichael Chan /* hwrm_fw_qstatus_input (size:192b/24B) */ 8284894aa69aSMichael Chan struct hwrm_fw_qstatus_input { 8285894aa69aSMichael Chan __le16 req_type; 8286894aa69aSMichael Chan __le16 cmpl_ring; 8287894aa69aSMichael Chan __le16 seq_id; 8288894aa69aSMichael Chan __le16 target_id; 8289894aa69aSMichael Chan __le64 resp_addr; 8290894aa69aSMichael Chan u8 embedded_proc_type; 8291894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 8292894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 8293894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 8294894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 8295894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 8296894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 8297894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 8298894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 8299894aa69aSMichael Chan u8 unused_0[7]; 830057922b0aSMichael Chan }; 830157922b0aSMichael Chan 8302894aa69aSMichael Chan /* hwrm_fw_qstatus_output (size:128b/16B) */ 8303894aa69aSMichael Chan struct hwrm_fw_qstatus_output { 8304894aa69aSMichael Chan __le16 error_code; 8305894aa69aSMichael Chan __le16 req_type; 8306894aa69aSMichael Chan __le16 seq_id; 8307894aa69aSMichael Chan __le16 resp_len; 8308894aa69aSMichael Chan u8 selfrst_status; 8309894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 8310894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 8311894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 83124a50ddc2SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 83134a50ddc2SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 831431f67c2eSMichael Chan u8 nvm_option_action_status; 831531f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 831631f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 831731f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 831831f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 831931f67c2eSMichael Chan #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 832031f67c2eSMichael Chan u8 unused_0[5]; 8321894aa69aSMichael Chan u8 valid; 832287c374deSMichael Chan }; 832387c374deSMichael Chan 8324894aa69aSMichael Chan /* hwrm_fw_set_time_input (size:256b/32B) */ 8325894aa69aSMichael Chan struct hwrm_fw_set_time_input { 8326894aa69aSMichael Chan __le16 req_type; 8327894aa69aSMichael Chan __le16 cmpl_ring; 8328894aa69aSMichael Chan __le16 seq_id; 8329894aa69aSMichael Chan __le16 target_id; 8330894aa69aSMichael Chan __le64 resp_addr; 8331894aa69aSMichael Chan __le16 year; 8332894aa69aSMichael Chan #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 8333894aa69aSMichael Chan #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 8334894aa69aSMichael Chan u8 month; 8335894aa69aSMichael Chan u8 day; 8336894aa69aSMichael Chan u8 hour; 8337894aa69aSMichael Chan u8 minute; 8338894aa69aSMichael Chan u8 second; 8339894aa69aSMichael Chan u8 unused_0; 8340894aa69aSMichael Chan __le16 millisecond; 8341894aa69aSMichael Chan __le16 zone; 83424a50ddc2SMichael Chan #define FW_SET_TIME_REQ_ZONE_UTC 0 83434a50ddc2SMichael Chan #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 8344894aa69aSMichael Chan #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 8345894aa69aSMichael Chan u8 unused_1[4]; 8346894aa69aSMichael Chan }; 8347894aa69aSMichael Chan 8348894aa69aSMichael Chan /* hwrm_fw_set_time_output (size:128b/16B) */ 8349894aa69aSMichael Chan struct hwrm_fw_set_time_output { 8350894aa69aSMichael Chan __le16 error_code; 8351894aa69aSMichael Chan __le16 req_type; 8352894aa69aSMichael Chan __le16 seq_id; 8353894aa69aSMichael Chan __le16 resp_len; 8354894aa69aSMichael Chan u8 unused_0[7]; 8355894aa69aSMichael Chan u8 valid; 8356894aa69aSMichael Chan }; 8357894aa69aSMichael Chan 8358894aa69aSMichael Chan /* hwrm_struct_hdr (size:128b/16B) */ 835987c374deSMichael Chan struct hwrm_struct_hdr { 836087c374deSMichael Chan __le16 struct_id; 836187c374deSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 8362f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 8363f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 8364f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 8365f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 8366f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 8367f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 83683322479eSMichael Chan #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 83698eb992e8SMichael Chan #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 8370f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 83716a17eb27SMichael Chan #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 837216db6323SMichael Chan #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 837316db6323SMichael Chan #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 837487c374deSMichael Chan __le16 len; 837587c374deSMichael Chan u8 version; 837687c374deSMichael Chan u8 count; 837787c374deSMichael Chan __le16 subtype; 837887c374deSMichael Chan __le16 next_offset; 837987c374deSMichael Chan #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 8380894aa69aSMichael Chan u8 unused_0[6]; 838187c374deSMichael Chan }; 838287c374deSMichael Chan 8383894aa69aSMichael Chan /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 8384f183886cSMichael Chan struct hwrm_struct_data_dcbx_app { 8385f183886cSMichael Chan __be16 protocol_id; 838687c374deSMichael Chan u8 protocol_selector; 8387f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 8388f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 8389f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 8390f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 8391894aa69aSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 839287c374deSMichael Chan u8 priority; 839387c374deSMichael Chan u8 valid; 839487c374deSMichael Chan u8 unused_0[3]; 839587c374deSMichael Chan }; 839687c374deSMichael Chan 8397894aa69aSMichael Chan /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 8398894aa69aSMichael Chan struct hwrm_fw_set_structured_data_input { 8399894aa69aSMichael Chan __le16 req_type; 8400894aa69aSMichael Chan __le16 cmpl_ring; 8401894aa69aSMichael Chan __le16 seq_id; 8402894aa69aSMichael Chan __le16 target_id; 8403894aa69aSMichael Chan __le64 resp_addr; 8404894aa69aSMichael Chan __le64 src_data_addr; 8405894aa69aSMichael Chan __le16 data_len; 8406894aa69aSMichael Chan u8 hdr_cnt; 8407894aa69aSMichael Chan u8 unused_0[5]; 8408894aa69aSMichael Chan }; 8409894aa69aSMichael Chan 8410894aa69aSMichael Chan /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 8411894aa69aSMichael Chan struct hwrm_fw_set_structured_data_output { 8412894aa69aSMichael Chan __le16 error_code; 8413894aa69aSMichael Chan __le16 req_type; 8414894aa69aSMichael Chan __le16 seq_id; 8415894aa69aSMichael Chan __le16 resp_len; 8416894aa69aSMichael Chan u8 unused_0[7]; 8417894aa69aSMichael Chan u8 valid; 8418894aa69aSMichael Chan }; 8419894aa69aSMichael Chan 8420894aa69aSMichael Chan /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 8421894aa69aSMichael Chan struct hwrm_fw_set_structured_data_cmd_err { 8422894aa69aSMichael Chan u8 code; 8423894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8424894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 8425894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 8426894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8427894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8428894aa69aSMichael Chan u8 unused_0[7]; 8429894aa69aSMichael Chan }; 8430894aa69aSMichael Chan 8431894aa69aSMichael Chan /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 8432894aa69aSMichael Chan struct hwrm_fw_get_structured_data_input { 8433894aa69aSMichael Chan __le16 req_type; 8434894aa69aSMichael Chan __le16 cmpl_ring; 8435894aa69aSMichael Chan __le16 seq_id; 8436894aa69aSMichael Chan __le16 target_id; 8437894aa69aSMichael Chan __le64 resp_addr; 8438894aa69aSMichael Chan __le64 dest_data_addr; 8439894aa69aSMichael Chan __le16 data_len; 8440894aa69aSMichael Chan __le16 structure_id; 8441894aa69aSMichael Chan __le16 subtype; 8442894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 8443894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 8444894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 8445894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 8446894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 8447894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 8448894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 8449894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 8450894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 8451894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 8452894aa69aSMichael Chan u8 count; 8453894aa69aSMichael Chan u8 unused_0; 8454894aa69aSMichael Chan }; 8455894aa69aSMichael Chan 8456894aa69aSMichael Chan /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 8457894aa69aSMichael Chan struct hwrm_fw_get_structured_data_output { 8458894aa69aSMichael Chan __le16 error_code; 8459894aa69aSMichael Chan __le16 req_type; 8460894aa69aSMichael Chan __le16 seq_id; 8461894aa69aSMichael Chan __le16 resp_len; 8462894aa69aSMichael Chan u8 hdr_cnt; 8463894aa69aSMichael Chan u8 unused_0[6]; 8464894aa69aSMichael Chan u8 valid; 8465894aa69aSMichael Chan }; 8466894aa69aSMichael Chan 8467894aa69aSMichael Chan /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 8468894aa69aSMichael Chan struct hwrm_fw_get_structured_data_cmd_err { 8469894aa69aSMichael Chan u8 code; 8470894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 8471894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 8472894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 8473894aa69aSMichael Chan u8 unused_0[7]; 8474894aa69aSMichael Chan }; 8475894aa69aSMichael Chan 8476*21e70778SMichael Chan /* hwrm_fw_livepatch_query_input (size:192b/24B) */ 8477*21e70778SMichael Chan struct hwrm_fw_livepatch_query_input { 8478*21e70778SMichael Chan __le16 req_type; 8479*21e70778SMichael Chan __le16 cmpl_ring; 8480*21e70778SMichael Chan __le16 seq_id; 8481*21e70778SMichael Chan __le16 target_id; 8482*21e70778SMichael Chan __le64 resp_addr; 8483*21e70778SMichael Chan u8 fw_target; 8484*21e70778SMichael Chan #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 8485*21e70778SMichael Chan #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 8486*21e70778SMichael Chan #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 8487*21e70778SMichael Chan u8 unused_0[7]; 8488*21e70778SMichael Chan }; 8489*21e70778SMichael Chan 8490*21e70778SMichael Chan /* hwrm_fw_livepatch_query_output (size:640b/80B) */ 8491*21e70778SMichael Chan struct hwrm_fw_livepatch_query_output { 8492*21e70778SMichael Chan __le16 error_code; 8493*21e70778SMichael Chan __le16 req_type; 8494*21e70778SMichael Chan __le16 seq_id; 8495*21e70778SMichael Chan __le16 resp_len; 8496*21e70778SMichael Chan char install_ver[32]; 8497*21e70778SMichael Chan char active_ver[32]; 8498*21e70778SMichael Chan __le16 status_flags; 8499*21e70778SMichael Chan #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 8500*21e70778SMichael Chan #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 8501*21e70778SMichael Chan u8 unused_0[5]; 8502*21e70778SMichael Chan u8 valid; 8503*21e70778SMichael Chan }; 8504*21e70778SMichael Chan 8505*21e70778SMichael Chan /* hwrm_fw_livepatch_input (size:256b/32B) */ 8506*21e70778SMichael Chan struct hwrm_fw_livepatch_input { 8507*21e70778SMichael Chan __le16 req_type; 8508*21e70778SMichael Chan __le16 cmpl_ring; 8509*21e70778SMichael Chan __le16 seq_id; 8510*21e70778SMichael Chan __le16 target_id; 8511*21e70778SMichael Chan __le64 resp_addr; 8512*21e70778SMichael Chan u8 opcode; 8513*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 8514*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 8515*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 8516*21e70778SMichael Chan u8 fw_target; 8517*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 8518*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 8519*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 8520*21e70778SMichael Chan u8 loadtype; 8521*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 8522*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 8523*21e70778SMichael Chan #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 8524*21e70778SMichael Chan u8 flags; 8525*21e70778SMichael Chan __le32 patch_len; 8526*21e70778SMichael Chan __le64 host_addr; 8527*21e70778SMichael Chan }; 8528*21e70778SMichael Chan 8529*21e70778SMichael Chan /* hwrm_fw_livepatch_output (size:128b/16B) */ 8530*21e70778SMichael Chan struct hwrm_fw_livepatch_output { 8531*21e70778SMichael Chan __le16 error_code; 8532*21e70778SMichael Chan __le16 req_type; 8533*21e70778SMichael Chan __le16 seq_id; 8534*21e70778SMichael Chan __le16 resp_len; 8535*21e70778SMichael Chan u8 unused_0[7]; 8536*21e70778SMichael Chan u8 valid; 8537*21e70778SMichael Chan }; 8538*21e70778SMichael Chan 8539*21e70778SMichael Chan /* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 8540*21e70778SMichael Chan struct hwrm_fw_livepatch_cmd_err { 8541*21e70778SMichael Chan u8 code; 8542*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 8543*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 8544*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 8545*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 8546*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 8547*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 8548*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 8549*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 8550*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 8551*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 8552*21e70778SMichael Chan #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 8553*21e70778SMichael Chan u8 unused_0[7]; 8554*21e70778SMichael Chan }; 8555*21e70778SMichael Chan 8556894aa69aSMichael Chan /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 8557894aa69aSMichael Chan struct hwrm_exec_fwd_resp_input { 8558894aa69aSMichael Chan __le16 req_type; 8559894aa69aSMichael Chan __le16 cmpl_ring; 8560894aa69aSMichael Chan __le16 seq_id; 8561894aa69aSMichael Chan __le16 target_id; 8562894aa69aSMichael Chan __le64 resp_addr; 8563894aa69aSMichael Chan __le32 encap_request[26]; 8564894aa69aSMichael Chan __le16 encap_resp_target_id; 8565894aa69aSMichael Chan u8 unused_0[6]; 8566894aa69aSMichael Chan }; 8567894aa69aSMichael Chan 8568894aa69aSMichael Chan /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 8569894aa69aSMichael Chan struct hwrm_exec_fwd_resp_output { 8570894aa69aSMichael Chan __le16 error_code; 8571894aa69aSMichael Chan __le16 req_type; 8572894aa69aSMichael Chan __le16 seq_id; 8573894aa69aSMichael Chan __le16 resp_len; 8574894aa69aSMichael Chan u8 unused_0[7]; 8575894aa69aSMichael Chan u8 valid; 8576894aa69aSMichael Chan }; 8577894aa69aSMichael Chan 8578894aa69aSMichael Chan /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 8579894aa69aSMichael Chan struct hwrm_reject_fwd_resp_input { 8580894aa69aSMichael Chan __le16 req_type; 8581894aa69aSMichael Chan __le16 cmpl_ring; 8582894aa69aSMichael Chan __le16 seq_id; 8583894aa69aSMichael Chan __le16 target_id; 8584894aa69aSMichael Chan __le64 resp_addr; 8585894aa69aSMichael Chan __le32 encap_request[26]; 8586894aa69aSMichael Chan __le16 encap_resp_target_id; 8587894aa69aSMichael Chan u8 unused_0[6]; 8588894aa69aSMichael Chan }; 8589894aa69aSMichael Chan 8590894aa69aSMichael Chan /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 8591894aa69aSMichael Chan struct hwrm_reject_fwd_resp_output { 8592894aa69aSMichael Chan __le16 error_code; 8593894aa69aSMichael Chan __le16 req_type; 8594894aa69aSMichael Chan __le16 seq_id; 8595894aa69aSMichael Chan __le16 resp_len; 8596894aa69aSMichael Chan u8 unused_0[7]; 8597894aa69aSMichael Chan u8 valid; 8598894aa69aSMichael Chan }; 8599894aa69aSMichael Chan 8600894aa69aSMichael Chan /* hwrm_fwd_resp_input (size:1024b/128B) */ 8601894aa69aSMichael Chan struct hwrm_fwd_resp_input { 8602894aa69aSMichael Chan __le16 req_type; 8603894aa69aSMichael Chan __le16 cmpl_ring; 8604894aa69aSMichael Chan __le16 seq_id; 8605894aa69aSMichael Chan __le16 target_id; 8606894aa69aSMichael Chan __le64 resp_addr; 8607894aa69aSMichael Chan __le16 encap_resp_target_id; 8608894aa69aSMichael Chan __le16 encap_resp_cmpl_ring; 8609894aa69aSMichael Chan __le16 encap_resp_len; 8610894aa69aSMichael Chan u8 unused_0; 8611894aa69aSMichael Chan u8 unused_1; 8612894aa69aSMichael Chan __le64 encap_resp_addr; 8613894aa69aSMichael Chan __le32 encap_resp[24]; 8614894aa69aSMichael Chan }; 8615894aa69aSMichael Chan 8616894aa69aSMichael Chan /* hwrm_fwd_resp_output (size:128b/16B) */ 8617894aa69aSMichael Chan struct hwrm_fwd_resp_output { 8618894aa69aSMichael Chan __le16 error_code; 8619894aa69aSMichael Chan __le16 req_type; 8620894aa69aSMichael Chan __le16 seq_id; 8621894aa69aSMichael Chan __le16 resp_len; 8622894aa69aSMichael Chan u8 unused_0[7]; 8623894aa69aSMichael Chan u8 valid; 8624894aa69aSMichael Chan }; 8625894aa69aSMichael Chan 8626894aa69aSMichael Chan /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 8627894aa69aSMichael Chan struct hwrm_fwd_async_event_cmpl_input { 8628894aa69aSMichael Chan __le16 req_type; 8629894aa69aSMichael Chan __le16 cmpl_ring; 8630894aa69aSMichael Chan __le16 seq_id; 8631894aa69aSMichael Chan __le16 target_id; 8632894aa69aSMichael Chan __le64 resp_addr; 8633894aa69aSMichael Chan __le16 encap_async_event_target_id; 8634894aa69aSMichael Chan u8 unused_0[6]; 8635894aa69aSMichael Chan __le32 encap_async_event_cmpl[4]; 8636894aa69aSMichael Chan }; 8637894aa69aSMichael Chan 8638894aa69aSMichael Chan /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 8639894aa69aSMichael Chan struct hwrm_fwd_async_event_cmpl_output { 8640894aa69aSMichael Chan __le16 error_code; 8641894aa69aSMichael Chan __le16 req_type; 8642894aa69aSMichael Chan __le16 seq_id; 8643894aa69aSMichael Chan __le16 resp_len; 8644894aa69aSMichael Chan u8 unused_0[7]; 8645894aa69aSMichael Chan u8 valid; 8646894aa69aSMichael Chan }; 8647894aa69aSMichael Chan 8648894aa69aSMichael Chan /* hwrm_temp_monitor_query_input (size:128b/16B) */ 8649894aa69aSMichael Chan struct hwrm_temp_monitor_query_input { 8650894aa69aSMichael Chan __le16 req_type; 8651894aa69aSMichael Chan __le16 cmpl_ring; 8652894aa69aSMichael Chan __le16 seq_id; 8653894aa69aSMichael Chan __le16 target_id; 8654894aa69aSMichael Chan __le64 resp_addr; 8655894aa69aSMichael Chan }; 8656894aa69aSMichael Chan 8657894aa69aSMichael Chan /* hwrm_temp_monitor_query_output (size:128b/16B) */ 8658894aa69aSMichael Chan struct hwrm_temp_monitor_query_output { 8659894aa69aSMichael Chan __le16 error_code; 8660894aa69aSMichael Chan __le16 req_type; 8661894aa69aSMichael Chan __le16 seq_id; 8662894aa69aSMichael Chan __le16 resp_len; 8663894aa69aSMichael Chan u8 temp; 866472e0c9f9SMichael Chan u8 phy_temp; 866572e0c9f9SMichael Chan u8 om_temp; 866672e0c9f9SMichael Chan u8 flags; 866772e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 866872e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 866972e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 867072e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 867178eeadb8SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 867278eeadb8SMichael Chan u8 temp2; 867378eeadb8SMichael Chan u8 phy_temp2; 867478eeadb8SMichael Chan u8 om_temp2; 8675894aa69aSMichael Chan u8 valid; 8676894aa69aSMichael Chan }; 8677894aa69aSMichael Chan 8678894aa69aSMichael Chan /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 8679894aa69aSMichael Chan struct hwrm_wol_filter_alloc_input { 8680894aa69aSMichael Chan __le16 req_type; 8681894aa69aSMichael Chan __le16 cmpl_ring; 8682894aa69aSMichael Chan __le16 seq_id; 8683894aa69aSMichael Chan __le16 target_id; 8684894aa69aSMichael Chan __le64 resp_addr; 8685894aa69aSMichael Chan __le32 flags; 8686894aa69aSMichael Chan __le32 enables; 8687894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 8688894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 8689894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 8690894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 8691894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 8692894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 8693894aa69aSMichael Chan __le16 port_id; 8694894aa69aSMichael Chan u8 wol_type; 8695894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 8696894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 8697894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 8698894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 8699894aa69aSMichael Chan u8 unused_0[5]; 8700894aa69aSMichael Chan u8 mac_address[6]; 8701894aa69aSMichael Chan __le16 pattern_offset; 8702894aa69aSMichael Chan __le16 pattern_buf_size; 8703894aa69aSMichael Chan __le16 pattern_mask_size; 8704894aa69aSMichael Chan u8 unused_1[4]; 8705894aa69aSMichael Chan __le64 pattern_buf_addr; 8706894aa69aSMichael Chan __le64 pattern_mask_addr; 8707894aa69aSMichael Chan }; 8708894aa69aSMichael Chan 8709894aa69aSMichael Chan /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 8710894aa69aSMichael Chan struct hwrm_wol_filter_alloc_output { 8711894aa69aSMichael Chan __le16 error_code; 8712894aa69aSMichael Chan __le16 req_type; 8713894aa69aSMichael Chan __le16 seq_id; 8714894aa69aSMichael Chan __le16 resp_len; 8715894aa69aSMichael Chan u8 wol_filter_id; 8716894aa69aSMichael Chan u8 unused_0[6]; 8717894aa69aSMichael Chan u8 valid; 8718894aa69aSMichael Chan }; 8719894aa69aSMichael Chan 8720894aa69aSMichael Chan /* hwrm_wol_filter_free_input (size:256b/32B) */ 8721894aa69aSMichael Chan struct hwrm_wol_filter_free_input { 8722894aa69aSMichael Chan __le16 req_type; 8723894aa69aSMichael Chan __le16 cmpl_ring; 8724894aa69aSMichael Chan __le16 seq_id; 8725894aa69aSMichael Chan __le16 target_id; 8726894aa69aSMichael Chan __le64 resp_addr; 8727894aa69aSMichael Chan __le32 flags; 8728894aa69aSMichael Chan #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 8729894aa69aSMichael Chan __le32 enables; 8730894aa69aSMichael Chan #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 8731894aa69aSMichael Chan __le16 port_id; 8732894aa69aSMichael Chan u8 wol_filter_id; 8733894aa69aSMichael Chan u8 unused_0[5]; 8734894aa69aSMichael Chan }; 8735894aa69aSMichael Chan 8736894aa69aSMichael Chan /* hwrm_wol_filter_free_output (size:128b/16B) */ 8737894aa69aSMichael Chan struct hwrm_wol_filter_free_output { 8738894aa69aSMichael Chan __le16 error_code; 8739894aa69aSMichael Chan __le16 req_type; 8740894aa69aSMichael Chan __le16 seq_id; 8741894aa69aSMichael Chan __le16 resp_len; 8742894aa69aSMichael Chan u8 unused_0[7]; 8743894aa69aSMichael Chan u8 valid; 8744894aa69aSMichael Chan }; 8745894aa69aSMichael Chan 8746894aa69aSMichael Chan /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 8747894aa69aSMichael Chan struct hwrm_wol_filter_qcfg_input { 8748894aa69aSMichael Chan __le16 req_type; 8749894aa69aSMichael Chan __le16 cmpl_ring; 8750894aa69aSMichael Chan __le16 seq_id; 8751894aa69aSMichael Chan __le16 target_id; 8752894aa69aSMichael Chan __le64 resp_addr; 8753894aa69aSMichael Chan __le16 port_id; 8754894aa69aSMichael Chan __le16 handle; 8755894aa69aSMichael Chan u8 unused_0[4]; 8756894aa69aSMichael Chan __le64 pattern_buf_addr; 8757894aa69aSMichael Chan __le16 pattern_buf_size; 8758894aa69aSMichael Chan u8 unused_1[6]; 8759894aa69aSMichael Chan __le64 pattern_mask_addr; 8760894aa69aSMichael Chan __le16 pattern_mask_size; 8761894aa69aSMichael Chan u8 unused_2[6]; 8762894aa69aSMichael Chan }; 8763894aa69aSMichael Chan 8764894aa69aSMichael Chan /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 8765894aa69aSMichael Chan struct hwrm_wol_filter_qcfg_output { 8766894aa69aSMichael Chan __le16 error_code; 8767894aa69aSMichael Chan __le16 req_type; 8768894aa69aSMichael Chan __le16 seq_id; 8769894aa69aSMichael Chan __le16 resp_len; 8770894aa69aSMichael Chan __le16 next_handle; 8771894aa69aSMichael Chan u8 wol_filter_id; 8772894aa69aSMichael Chan u8 wol_type; 8773894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 8774894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 8775894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 8776894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 8777894aa69aSMichael Chan __le32 unused_0; 8778894aa69aSMichael Chan u8 mac_address[6]; 8779894aa69aSMichael Chan __le16 pattern_offset; 8780894aa69aSMichael Chan __le16 pattern_size; 8781894aa69aSMichael Chan __le16 pattern_mask_size; 8782894aa69aSMichael Chan u8 unused_1[3]; 8783894aa69aSMichael Chan u8 valid; 8784894aa69aSMichael Chan }; 8785894aa69aSMichael Chan 8786894aa69aSMichael Chan /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 8787894aa69aSMichael Chan struct hwrm_wol_reason_qcfg_input { 8788894aa69aSMichael Chan __le16 req_type; 8789894aa69aSMichael Chan __le16 cmpl_ring; 8790894aa69aSMichael Chan __le16 seq_id; 8791894aa69aSMichael Chan __le16 target_id; 8792894aa69aSMichael Chan __le64 resp_addr; 8793894aa69aSMichael Chan __le16 port_id; 8794894aa69aSMichael Chan u8 unused_0[6]; 8795894aa69aSMichael Chan __le64 wol_pkt_buf_addr; 8796894aa69aSMichael Chan __le16 wol_pkt_buf_size; 8797894aa69aSMichael Chan u8 unused_1[6]; 8798894aa69aSMichael Chan }; 8799894aa69aSMichael Chan 8800894aa69aSMichael Chan /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 8801894aa69aSMichael Chan struct hwrm_wol_reason_qcfg_output { 8802894aa69aSMichael Chan __le16 error_code; 8803894aa69aSMichael Chan __le16 req_type; 8804894aa69aSMichael Chan __le16 seq_id; 8805894aa69aSMichael Chan __le16 resp_len; 8806894aa69aSMichael Chan u8 wol_filter_id; 8807894aa69aSMichael Chan u8 wol_reason; 8808894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 8809894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 8810894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 8811894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 8812894aa69aSMichael Chan u8 wol_pkt_len; 8813894aa69aSMichael Chan u8 unused_0[4]; 8814894aa69aSMichael Chan u8 valid; 8815894aa69aSMichael Chan }; 8816894aa69aSMichael Chan 8817bfc6e5fbSMichael Chan /* hwrm_dbg_read_direct_input (size:256b/32B) */ 8818bfc6e5fbSMichael Chan struct hwrm_dbg_read_direct_input { 8819bfc6e5fbSMichael Chan __le16 req_type; 8820bfc6e5fbSMichael Chan __le16 cmpl_ring; 8821bfc6e5fbSMichael Chan __le16 seq_id; 8822bfc6e5fbSMichael Chan __le16 target_id; 8823bfc6e5fbSMichael Chan __le64 resp_addr; 8824bfc6e5fbSMichael Chan __le64 host_dest_addr; 8825bfc6e5fbSMichael Chan __le32 read_addr; 8826bfc6e5fbSMichael Chan __le32 read_len32; 8827bfc6e5fbSMichael Chan }; 8828bfc6e5fbSMichael Chan 8829bfc6e5fbSMichael Chan /* hwrm_dbg_read_direct_output (size:128b/16B) */ 8830bfc6e5fbSMichael Chan struct hwrm_dbg_read_direct_output { 8831bfc6e5fbSMichael Chan __le16 error_code; 8832bfc6e5fbSMichael Chan __le16 req_type; 8833bfc6e5fbSMichael Chan __le16 seq_id; 8834bfc6e5fbSMichael Chan __le16 resp_len; 8835bfc6e5fbSMichael Chan __le32 crc32; 8836bfc6e5fbSMichael Chan u8 unused_0[3]; 8837bfc6e5fbSMichael Chan u8 valid; 8838bfc6e5fbSMichael Chan }; 8839bfc6e5fbSMichael Chan 88409d6b648cSMichael Chan /* hwrm_dbg_qcaps_input (size:192b/24B) */ 88419d6b648cSMichael Chan struct hwrm_dbg_qcaps_input { 88429d6b648cSMichael Chan __le16 req_type; 88439d6b648cSMichael Chan __le16 cmpl_ring; 88449d6b648cSMichael Chan __le16 seq_id; 88459d6b648cSMichael Chan __le16 target_id; 88469d6b648cSMichael Chan __le64 resp_addr; 88479d6b648cSMichael Chan __le16 fid; 88489d6b648cSMichael Chan u8 unused_0[6]; 88499d6b648cSMichael Chan }; 88509d6b648cSMichael Chan 88519d6b648cSMichael Chan /* hwrm_dbg_qcaps_output (size:192b/24B) */ 88529d6b648cSMichael Chan struct hwrm_dbg_qcaps_output { 88539d6b648cSMichael Chan __le16 error_code; 88549d6b648cSMichael Chan __le16 req_type; 88559d6b648cSMichael Chan __le16 seq_id; 88569d6b648cSMichael Chan __le16 resp_len; 88579d6b648cSMichael Chan __le16 fid; 88589d6b648cSMichael Chan u8 unused_0[2]; 88599d6b648cSMichael Chan __le32 coredump_component_disable_caps; 88609d6b648cSMichael Chan #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 88619d6b648cSMichael Chan __le32 flags; 88629d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 88639d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 88649d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 886578eeadb8SMichael Chan #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 88669d6b648cSMichael Chan u8 unused_1[3]; 88679d6b648cSMichael Chan u8 valid; 88689d6b648cSMichael Chan }; 88699d6b648cSMichael Chan 88709d6b648cSMichael Chan /* hwrm_dbg_qcfg_input (size:192b/24B) */ 88719d6b648cSMichael Chan struct hwrm_dbg_qcfg_input { 88729d6b648cSMichael Chan __le16 req_type; 88739d6b648cSMichael Chan __le16 cmpl_ring; 88749d6b648cSMichael Chan __le16 seq_id; 88759d6b648cSMichael Chan __le16 target_id; 88769d6b648cSMichael Chan __le64 resp_addr; 88779d6b648cSMichael Chan __le16 fid; 88789d6b648cSMichael Chan __le16 flags; 88799d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 88809d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 88819d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 88829d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 88839d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 88849d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 88859d6b648cSMichael Chan __le32 coredump_component_disable_flags; 88869d6b648cSMichael Chan #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 88879d6b648cSMichael Chan }; 88889d6b648cSMichael Chan 88899d6b648cSMichael Chan /* hwrm_dbg_qcfg_output (size:256b/32B) */ 88909d6b648cSMichael Chan struct hwrm_dbg_qcfg_output { 88919d6b648cSMichael Chan __le16 error_code; 88929d6b648cSMichael Chan __le16 req_type; 88939d6b648cSMichael Chan __le16 seq_id; 88949d6b648cSMichael Chan __le16 resp_len; 88959d6b648cSMichael Chan __le16 fid; 88969d6b648cSMichael Chan u8 unused_0[2]; 88979d6b648cSMichael Chan __le32 coredump_size; 88989d6b648cSMichael Chan __le32 flags; 88999d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 89009d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 89019d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 89029d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 89039d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 89049d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 89059d6b648cSMichael Chan __le16 async_cmpl_ring; 89069d6b648cSMichael Chan u8 unused_2[2]; 89079d6b648cSMichael Chan __le32 crashdump_size; 89089d6b648cSMichael Chan u8 unused_3[3]; 89099d6b648cSMichael Chan u8 valid; 89109d6b648cSMichael Chan }; 89119d6b648cSMichael Chan 89126fc92c33SMichael Chan /* coredump_segment_record (size:128b/16B) */ 89136fc92c33SMichael Chan struct coredump_segment_record { 89146fc92c33SMichael Chan __le16 component_id; 89156fc92c33SMichael Chan __le16 segment_id; 89166fc92c33SMichael Chan __le16 max_instances; 89176fc92c33SMichael Chan u8 version_hi; 89186fc92c33SMichael Chan u8 version_low; 89196fc92c33SMichael Chan u8 seg_flags; 89202792b5b9SMichael Chan u8 compress_flags; 89212792b5b9SMichael Chan #define SFLAG_COMPRESSED_ZLIB 0x1UL 8922bfc6e5fbSMichael Chan u8 unused_0[2]; 8923bfc6e5fbSMichael Chan __le32 segment_len; 89246fc92c33SMichael Chan }; 89256fc92c33SMichael Chan 89266fc92c33SMichael Chan /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 89276fc92c33SMichael Chan struct hwrm_dbg_coredump_list_input { 89286fc92c33SMichael Chan __le16 req_type; 89296fc92c33SMichael Chan __le16 cmpl_ring; 89306fc92c33SMichael Chan __le16 seq_id; 89316fc92c33SMichael Chan __le16 target_id; 89326fc92c33SMichael Chan __le64 resp_addr; 89336fc92c33SMichael Chan __le64 host_dest_addr; 89346fc92c33SMichael Chan __le32 host_buf_len; 89356fc92c33SMichael Chan __le16 seq_no; 89364a50ddc2SMichael Chan u8 flags; 89374a50ddc2SMichael Chan #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 89384a50ddc2SMichael Chan u8 unused_0[1]; 89396fc92c33SMichael Chan }; 89406fc92c33SMichael Chan 89416fc92c33SMichael Chan /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 89426fc92c33SMichael Chan struct hwrm_dbg_coredump_list_output { 89436fc92c33SMichael Chan __le16 error_code; 89446fc92c33SMichael Chan __le16 req_type; 89456fc92c33SMichael Chan __le16 seq_id; 89466fc92c33SMichael Chan __le16 resp_len; 89476fc92c33SMichael Chan u8 flags; 89486fc92c33SMichael Chan #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 89496fc92c33SMichael Chan u8 unused_0; 89506fc92c33SMichael Chan __le16 total_segments; 89516fc92c33SMichael Chan __le16 data_len; 89526fc92c33SMichael Chan u8 unused_1; 89536fc92c33SMichael Chan u8 valid; 89546fc92c33SMichael Chan }; 89556fc92c33SMichael Chan 89566fc92c33SMichael Chan /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 89576fc92c33SMichael Chan struct hwrm_dbg_coredump_initiate_input { 89586fc92c33SMichael Chan __le16 req_type; 89596fc92c33SMichael Chan __le16 cmpl_ring; 89606fc92c33SMichael Chan __le16 seq_id; 89616fc92c33SMichael Chan __le16 target_id; 89626fc92c33SMichael Chan __le64 resp_addr; 89636fc92c33SMichael Chan __le16 component_id; 89646fc92c33SMichael Chan __le16 segment_id; 89656fc92c33SMichael Chan __le16 instance; 89666fc92c33SMichael Chan __le16 unused_0; 89676fc92c33SMichael Chan u8 seg_flags; 89686fc92c33SMichael Chan u8 unused_1[7]; 89696fc92c33SMichael Chan }; 89706fc92c33SMichael Chan 89716fc92c33SMichael Chan /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 89726fc92c33SMichael Chan struct hwrm_dbg_coredump_initiate_output { 89736fc92c33SMichael Chan __le16 error_code; 89746fc92c33SMichael Chan __le16 req_type; 89756fc92c33SMichael Chan __le16 seq_id; 89766fc92c33SMichael Chan __le16 resp_len; 89776fc92c33SMichael Chan u8 unused_0[7]; 89786fc92c33SMichael Chan u8 valid; 89796fc92c33SMichael Chan }; 89806fc92c33SMichael Chan 89816fc92c33SMichael Chan /* coredump_data_hdr (size:128b/16B) */ 89826fc92c33SMichael Chan struct coredump_data_hdr { 89836fc92c33SMichael Chan __le32 address; 89846fc92c33SMichael Chan __le32 flags_length; 898516db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 898616db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 898716db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 89886fc92c33SMichael Chan __le32 instance; 89896fc92c33SMichael Chan __le32 next_offset; 89906fc92c33SMichael Chan }; 89916fc92c33SMichael Chan 89926fc92c33SMichael Chan /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 89936fc92c33SMichael Chan struct hwrm_dbg_coredump_retrieve_input { 89946fc92c33SMichael Chan __le16 req_type; 89956fc92c33SMichael Chan __le16 cmpl_ring; 89966fc92c33SMichael Chan __le16 seq_id; 89976fc92c33SMichael Chan __le16 target_id; 89986fc92c33SMichael Chan __le64 resp_addr; 89996fc92c33SMichael Chan __le64 host_dest_addr; 90006fc92c33SMichael Chan __le32 host_buf_len; 90016fc92c33SMichael Chan __le32 unused_0; 90026fc92c33SMichael Chan __le16 component_id; 90036fc92c33SMichael Chan __le16 segment_id; 90046fc92c33SMichael Chan __le16 instance; 90056fc92c33SMichael Chan __le16 unused_1; 90066fc92c33SMichael Chan u8 seg_flags; 90076fc92c33SMichael Chan u8 unused_2; 90086fc92c33SMichael Chan __le16 unused_3; 90096fc92c33SMichael Chan __le32 unused_4; 90106fc92c33SMichael Chan __le32 seq_no; 90116fc92c33SMichael Chan __le32 unused_5; 90126fc92c33SMichael Chan }; 90136fc92c33SMichael Chan 90146fc92c33SMichael Chan /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 90156fc92c33SMichael Chan struct hwrm_dbg_coredump_retrieve_output { 90166fc92c33SMichael Chan __le16 error_code; 90176fc92c33SMichael Chan __le16 req_type; 90186fc92c33SMichael Chan __le16 seq_id; 90196fc92c33SMichael Chan __le16 resp_len; 90206fc92c33SMichael Chan u8 flags; 90216fc92c33SMichael Chan #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 90226fc92c33SMichael Chan u8 unused_0; 90236fc92c33SMichael Chan __le16 data_len; 90246fc92c33SMichael Chan u8 unused_1[3]; 90256fc92c33SMichael Chan u8 valid; 90266fc92c33SMichael Chan }; 90276fc92c33SMichael Chan 902831d357c0SMichael Chan /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 902931d357c0SMichael Chan struct hwrm_dbg_ring_info_get_input { 903031d357c0SMichael Chan __le16 req_type; 903131d357c0SMichael Chan __le16 cmpl_ring; 903231d357c0SMichael Chan __le16 seq_id; 903331d357c0SMichael Chan __le16 target_id; 903431d357c0SMichael Chan __le64 resp_addr; 903531d357c0SMichael Chan u8 ring_type; 903631d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 903731d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 903831d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 9039bfc6e5fbSMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 9040bfc6e5fbSMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 904131d357c0SMichael Chan u8 unused_0[3]; 904231d357c0SMichael Chan __le32 fw_ring_id; 904331d357c0SMichael Chan }; 904431d357c0SMichael Chan 904531d357c0SMichael Chan /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 904631d357c0SMichael Chan struct hwrm_dbg_ring_info_get_output { 904731d357c0SMichael Chan __le16 error_code; 904831d357c0SMichael Chan __le16 req_type; 904931d357c0SMichael Chan __le16 seq_id; 905031d357c0SMichael Chan __le16 resp_len; 905131d357c0SMichael Chan __le32 producer_index; 905231d357c0SMichael Chan __le32 consumer_index; 9053bfc6e5fbSMichael Chan __le32 cag_vector_ctrl; 9054bfc6e5fbSMichael Chan u8 unused_0[3]; 905531d357c0SMichael Chan u8 valid; 905631d357c0SMichael Chan }; 905731d357c0SMichael Chan 9058894aa69aSMichael Chan /* hwrm_nvm_read_input (size:320b/40B) */ 9059894aa69aSMichael Chan struct hwrm_nvm_read_input { 9060894aa69aSMichael Chan __le16 req_type; 9061894aa69aSMichael Chan __le16 cmpl_ring; 9062894aa69aSMichael Chan __le16 seq_id; 9063894aa69aSMichael Chan __le16 target_id; 9064894aa69aSMichael Chan __le64 resp_addr; 9065894aa69aSMichael Chan __le64 host_dest_addr; 9066894aa69aSMichael Chan __le16 dir_idx; 9067894aa69aSMichael Chan u8 unused_0[2]; 9068894aa69aSMichael Chan __le32 offset; 9069894aa69aSMichael Chan __le32 len; 9070894aa69aSMichael Chan u8 unused_1[4]; 9071894aa69aSMichael Chan }; 9072894aa69aSMichael Chan 9073894aa69aSMichael Chan /* hwrm_nvm_read_output (size:128b/16B) */ 9074894aa69aSMichael Chan struct hwrm_nvm_read_output { 9075894aa69aSMichael Chan __le16 error_code; 9076894aa69aSMichael Chan __le16 req_type; 9077894aa69aSMichael Chan __le16 seq_id; 9078894aa69aSMichael Chan __le16 resp_len; 9079894aa69aSMichael Chan u8 unused_0[7]; 9080894aa69aSMichael Chan u8 valid; 9081894aa69aSMichael Chan }; 9082894aa69aSMichael Chan 9083894aa69aSMichael Chan /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 9084894aa69aSMichael Chan struct hwrm_nvm_get_dir_entries_input { 9085894aa69aSMichael Chan __le16 req_type; 9086894aa69aSMichael Chan __le16 cmpl_ring; 9087894aa69aSMichael Chan __le16 seq_id; 9088894aa69aSMichael Chan __le16 target_id; 9089894aa69aSMichael Chan __le64 resp_addr; 9090894aa69aSMichael Chan __le64 host_dest_addr; 9091894aa69aSMichael Chan }; 9092894aa69aSMichael Chan 9093894aa69aSMichael Chan /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 9094894aa69aSMichael Chan struct hwrm_nvm_get_dir_entries_output { 9095894aa69aSMichael Chan __le16 error_code; 9096894aa69aSMichael Chan __le16 req_type; 9097894aa69aSMichael Chan __le16 seq_id; 9098894aa69aSMichael Chan __le16 resp_len; 9099894aa69aSMichael Chan u8 unused_0[7]; 9100894aa69aSMichael Chan u8 valid; 9101894aa69aSMichael Chan }; 9102894aa69aSMichael Chan 9103894aa69aSMichael Chan /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 9104894aa69aSMichael Chan struct hwrm_nvm_get_dir_info_input { 9105894aa69aSMichael Chan __le16 req_type; 9106894aa69aSMichael Chan __le16 cmpl_ring; 9107894aa69aSMichael Chan __le16 seq_id; 9108894aa69aSMichael Chan __le16 target_id; 9109894aa69aSMichael Chan __le64 resp_addr; 9110894aa69aSMichael Chan }; 9111894aa69aSMichael Chan 9112894aa69aSMichael Chan /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 9113894aa69aSMichael Chan struct hwrm_nvm_get_dir_info_output { 9114894aa69aSMichael Chan __le16 error_code; 9115894aa69aSMichael Chan __le16 req_type; 9116894aa69aSMichael Chan __le16 seq_id; 9117894aa69aSMichael Chan __le16 resp_len; 9118894aa69aSMichael Chan __le32 entries; 9119894aa69aSMichael Chan __le32 entry_length; 9120894aa69aSMichael Chan u8 unused_0[7]; 9121894aa69aSMichael Chan u8 valid; 9122894aa69aSMichael Chan }; 9123894aa69aSMichael Chan 9124fbfee257SMichael Chan /* hwrm_nvm_write_input (size:448b/56B) */ 9125894aa69aSMichael Chan struct hwrm_nvm_write_input { 9126894aa69aSMichael Chan __le16 req_type; 9127894aa69aSMichael Chan __le16 cmpl_ring; 9128894aa69aSMichael Chan __le16 seq_id; 9129894aa69aSMichael Chan __le16 target_id; 9130894aa69aSMichael Chan __le64 resp_addr; 9131894aa69aSMichael Chan __le64 host_src_addr; 9132894aa69aSMichael Chan __le16 dir_type; 9133894aa69aSMichael Chan __le16 dir_ordinal; 9134894aa69aSMichael Chan __le16 dir_ext; 9135894aa69aSMichael Chan __le16 dir_attr; 9136894aa69aSMichael Chan __le32 dir_data_length; 9137894aa69aSMichael Chan __le16 option; 9138894aa69aSMichael Chan __le16 flags; 9139894aa69aSMichael Chan #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 9140fbfee257SMichael Chan #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 9141fbfee257SMichael Chan #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 9142894aa69aSMichael Chan __le32 dir_item_length; 9143fbfee257SMichael Chan __le32 offset; 9144fbfee257SMichael Chan __le32 len; 9145894aa69aSMichael Chan __le32 unused_0; 9146894aa69aSMichael Chan }; 9147894aa69aSMichael Chan 9148894aa69aSMichael Chan /* hwrm_nvm_write_output (size:128b/16B) */ 9149894aa69aSMichael Chan struct hwrm_nvm_write_output { 9150894aa69aSMichael Chan __le16 error_code; 9151894aa69aSMichael Chan __le16 req_type; 9152894aa69aSMichael Chan __le16 seq_id; 9153894aa69aSMichael Chan __le16 resp_len; 9154894aa69aSMichael Chan __le32 dir_item_length; 9155894aa69aSMichael Chan __le16 dir_idx; 9156894aa69aSMichael Chan u8 unused_0; 9157894aa69aSMichael Chan u8 valid; 9158894aa69aSMichael Chan }; 9159894aa69aSMichael Chan 9160894aa69aSMichael Chan /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 9161894aa69aSMichael Chan struct hwrm_nvm_write_cmd_err { 9162894aa69aSMichael Chan u8 code; 9163894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 9164894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9165894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 9166894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 9167894aa69aSMichael Chan u8 unused_0[7]; 9168894aa69aSMichael Chan }; 9169894aa69aSMichael Chan 9170894aa69aSMichael Chan /* hwrm_nvm_modify_input (size:320b/40B) */ 9171894aa69aSMichael Chan struct hwrm_nvm_modify_input { 9172894aa69aSMichael Chan __le16 req_type; 9173894aa69aSMichael Chan __le16 cmpl_ring; 9174894aa69aSMichael Chan __le16 seq_id; 9175894aa69aSMichael Chan __le16 target_id; 9176894aa69aSMichael Chan __le64 resp_addr; 9177894aa69aSMichael Chan __le64 host_src_addr; 9178894aa69aSMichael Chan __le16 dir_idx; 9179460c2577SMichael Chan __le16 flags; 9180460c2577SMichael Chan #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 9181460c2577SMichael Chan #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 9182894aa69aSMichael Chan __le32 offset; 9183894aa69aSMichael Chan __le32 len; 9184894aa69aSMichael Chan u8 unused_1[4]; 9185894aa69aSMichael Chan }; 9186894aa69aSMichael Chan 9187894aa69aSMichael Chan /* hwrm_nvm_modify_output (size:128b/16B) */ 9188894aa69aSMichael Chan struct hwrm_nvm_modify_output { 9189894aa69aSMichael Chan __le16 error_code; 9190894aa69aSMichael Chan __le16 req_type; 9191894aa69aSMichael Chan __le16 seq_id; 9192894aa69aSMichael Chan __le16 resp_len; 9193894aa69aSMichael Chan u8 unused_0[7]; 9194894aa69aSMichael Chan u8 valid; 9195894aa69aSMichael Chan }; 9196894aa69aSMichael Chan 9197894aa69aSMichael Chan /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 9198894aa69aSMichael Chan struct hwrm_nvm_find_dir_entry_input { 9199894aa69aSMichael Chan __le16 req_type; 9200894aa69aSMichael Chan __le16 cmpl_ring; 9201894aa69aSMichael Chan __le16 seq_id; 9202894aa69aSMichael Chan __le16 target_id; 9203894aa69aSMichael Chan __le64 resp_addr; 9204894aa69aSMichael Chan __le32 enables; 9205894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 9206894aa69aSMichael Chan __le16 dir_idx; 9207894aa69aSMichael Chan __le16 dir_type; 9208894aa69aSMichael Chan __le16 dir_ordinal; 9209894aa69aSMichael Chan __le16 dir_ext; 9210894aa69aSMichael Chan u8 opt_ordinal; 9211894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 9212894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 9213894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 9214894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 9215894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 9216894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 9217894aa69aSMichael Chan u8 unused_0[3]; 9218894aa69aSMichael Chan }; 9219894aa69aSMichael Chan 9220894aa69aSMichael Chan /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 9221894aa69aSMichael Chan struct hwrm_nvm_find_dir_entry_output { 9222894aa69aSMichael Chan __le16 error_code; 9223894aa69aSMichael Chan __le16 req_type; 9224894aa69aSMichael Chan __le16 seq_id; 9225894aa69aSMichael Chan __le16 resp_len; 9226894aa69aSMichael Chan __le32 dir_item_length; 9227894aa69aSMichael Chan __le32 dir_data_length; 9228894aa69aSMichael Chan __le32 fw_ver; 9229894aa69aSMichael Chan __le16 dir_ordinal; 9230894aa69aSMichael Chan __le16 dir_idx; 9231894aa69aSMichael Chan u8 unused_0[7]; 9232894aa69aSMichael Chan u8 valid; 9233894aa69aSMichael Chan }; 9234894aa69aSMichael Chan 9235894aa69aSMichael Chan /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 9236894aa69aSMichael Chan struct hwrm_nvm_erase_dir_entry_input { 9237894aa69aSMichael Chan __le16 req_type; 9238894aa69aSMichael Chan __le16 cmpl_ring; 9239894aa69aSMichael Chan __le16 seq_id; 9240894aa69aSMichael Chan __le16 target_id; 9241894aa69aSMichael Chan __le64 resp_addr; 9242894aa69aSMichael Chan __le16 dir_idx; 9243894aa69aSMichael Chan u8 unused_0[6]; 9244894aa69aSMichael Chan }; 9245894aa69aSMichael Chan 9246894aa69aSMichael Chan /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 9247894aa69aSMichael Chan struct hwrm_nvm_erase_dir_entry_output { 9248894aa69aSMichael Chan __le16 error_code; 9249894aa69aSMichael Chan __le16 req_type; 9250894aa69aSMichael Chan __le16 seq_id; 9251894aa69aSMichael Chan __le16 resp_len; 9252894aa69aSMichael Chan u8 unused_0[7]; 9253894aa69aSMichael Chan u8 valid; 9254894aa69aSMichael Chan }; 9255894aa69aSMichael Chan 9256894aa69aSMichael Chan /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 9257894aa69aSMichael Chan struct hwrm_nvm_get_dev_info_input { 9258894aa69aSMichael Chan __le16 req_type; 9259894aa69aSMichael Chan __le16 cmpl_ring; 9260894aa69aSMichael Chan __le16 seq_id; 9261894aa69aSMichael Chan __le16 target_id; 9262894aa69aSMichael Chan __le64 resp_addr; 9263894aa69aSMichael Chan }; 9264894aa69aSMichael Chan 9265424174f1SVasundhara Volam /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 9266894aa69aSMichael Chan struct hwrm_nvm_get_dev_info_output { 9267894aa69aSMichael Chan __le16 error_code; 9268894aa69aSMichael Chan __le16 req_type; 9269894aa69aSMichael Chan __le16 seq_id; 9270894aa69aSMichael Chan __le16 resp_len; 9271894aa69aSMichael Chan __le16 manufacturer_id; 9272894aa69aSMichael Chan __le16 device_id; 9273894aa69aSMichael Chan __le32 sector_size; 9274894aa69aSMichael Chan __le32 nvram_size; 9275894aa69aSMichael Chan __le32 reserved_size; 9276894aa69aSMichael Chan __le32 available_size; 92774a50ddc2SMichael Chan u8 nvm_cfg_ver_maj; 92784a50ddc2SMichael Chan u8 nvm_cfg_ver_min; 92794a50ddc2SMichael Chan u8 nvm_cfg_ver_upd; 9280424174f1SVasundhara Volam u8 flags; 9281424174f1SVasundhara Volam #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 9282424174f1SVasundhara Volam char pkg_name[16]; 9283424174f1SVasundhara Volam __le16 hwrm_fw_major; 9284424174f1SVasundhara Volam __le16 hwrm_fw_minor; 9285424174f1SVasundhara Volam __le16 hwrm_fw_build; 9286424174f1SVasundhara Volam __le16 hwrm_fw_patch; 9287424174f1SVasundhara Volam __le16 mgmt_fw_major; 9288424174f1SVasundhara Volam __le16 mgmt_fw_minor; 9289424174f1SVasundhara Volam __le16 mgmt_fw_build; 9290424174f1SVasundhara Volam __le16 mgmt_fw_patch; 9291424174f1SVasundhara Volam __le16 roce_fw_major; 9292424174f1SVasundhara Volam __le16 roce_fw_minor; 9293424174f1SVasundhara Volam __le16 roce_fw_build; 9294424174f1SVasundhara Volam __le16 roce_fw_patch; 9295424174f1SVasundhara Volam u8 unused_0[7]; 9296894aa69aSMichael Chan u8 valid; 9297894aa69aSMichael Chan }; 9298894aa69aSMichael Chan 9299894aa69aSMichael Chan /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 9300894aa69aSMichael Chan struct hwrm_nvm_mod_dir_entry_input { 9301894aa69aSMichael Chan __le16 req_type; 9302894aa69aSMichael Chan __le16 cmpl_ring; 9303894aa69aSMichael Chan __le16 seq_id; 9304894aa69aSMichael Chan __le16 target_id; 9305894aa69aSMichael Chan __le64 resp_addr; 9306894aa69aSMichael Chan __le32 enables; 9307894aa69aSMichael Chan #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 9308894aa69aSMichael Chan __le16 dir_idx; 9309894aa69aSMichael Chan __le16 dir_ordinal; 9310894aa69aSMichael Chan __le16 dir_ext; 9311894aa69aSMichael Chan __le16 dir_attr; 9312894aa69aSMichael Chan __le32 checksum; 9313894aa69aSMichael Chan }; 9314894aa69aSMichael Chan 9315894aa69aSMichael Chan /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 9316894aa69aSMichael Chan struct hwrm_nvm_mod_dir_entry_output { 9317894aa69aSMichael Chan __le16 error_code; 9318894aa69aSMichael Chan __le16 req_type; 9319894aa69aSMichael Chan __le16 seq_id; 9320894aa69aSMichael Chan __le16 resp_len; 9321894aa69aSMichael Chan u8 unused_0[7]; 9322894aa69aSMichael Chan u8 valid; 9323894aa69aSMichael Chan }; 9324894aa69aSMichael Chan 9325894aa69aSMichael Chan /* hwrm_nvm_verify_update_input (size:192b/24B) */ 9326894aa69aSMichael Chan struct hwrm_nvm_verify_update_input { 9327894aa69aSMichael Chan __le16 req_type; 9328894aa69aSMichael Chan __le16 cmpl_ring; 9329894aa69aSMichael Chan __le16 seq_id; 9330894aa69aSMichael Chan __le16 target_id; 9331894aa69aSMichael Chan __le64 resp_addr; 9332894aa69aSMichael Chan __le16 dir_type; 9333894aa69aSMichael Chan __le16 dir_ordinal; 9334894aa69aSMichael Chan __le16 dir_ext; 9335894aa69aSMichael Chan u8 unused_0[2]; 9336894aa69aSMichael Chan }; 9337894aa69aSMichael Chan 9338894aa69aSMichael Chan /* hwrm_nvm_verify_update_output (size:128b/16B) */ 9339894aa69aSMichael Chan struct hwrm_nvm_verify_update_output { 9340894aa69aSMichael Chan __le16 error_code; 9341894aa69aSMichael Chan __le16 req_type; 9342894aa69aSMichael Chan __le16 seq_id; 9343894aa69aSMichael Chan __le16 resp_len; 9344894aa69aSMichael Chan u8 unused_0[7]; 9345894aa69aSMichael Chan u8 valid; 9346894aa69aSMichael Chan }; 9347894aa69aSMichael Chan 9348894aa69aSMichael Chan /* hwrm_nvm_install_update_input (size:192b/24B) */ 9349894aa69aSMichael Chan struct hwrm_nvm_install_update_input { 9350894aa69aSMichael Chan __le16 req_type; 9351894aa69aSMichael Chan __le16 cmpl_ring; 9352894aa69aSMichael Chan __le16 seq_id; 9353894aa69aSMichael Chan __le16 target_id; 9354894aa69aSMichael Chan __le64 resp_addr; 9355894aa69aSMichael Chan __le32 install_type; 9356894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 9357894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 9358894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 9359894aa69aSMichael Chan __le16 flags; 9360894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 9361894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 9362894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 9363bfc6e5fbSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 9364894aa69aSMichael Chan u8 unused_0[2]; 9365894aa69aSMichael Chan }; 9366894aa69aSMichael Chan 9367894aa69aSMichael Chan /* hwrm_nvm_install_update_output (size:192b/24B) */ 9368894aa69aSMichael Chan struct hwrm_nvm_install_update_output { 9369894aa69aSMichael Chan __le16 error_code; 9370894aa69aSMichael Chan __le16 req_type; 9371894aa69aSMichael Chan __le16 seq_id; 9372894aa69aSMichael Chan __le16 resp_len; 9373894aa69aSMichael Chan __le64 installed_items; 9374894aa69aSMichael Chan u8 result; 9375894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 9376894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 9377894aa69aSMichael Chan u8 problem_item; 9378894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 9379894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 9380894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 9381894aa69aSMichael Chan u8 reset_required; 9382894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 9383894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 9384894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 9385894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 9386894aa69aSMichael Chan u8 unused_0[4]; 9387894aa69aSMichael Chan u8 valid; 9388894aa69aSMichael Chan }; 9389894aa69aSMichael Chan 9390894aa69aSMichael Chan /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 9391894aa69aSMichael Chan struct hwrm_nvm_install_update_cmd_err { 9392894aa69aSMichael Chan u8 code; 9393894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 9394894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 9395894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 939678eeadb8SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 939778eeadb8SMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 9398894aa69aSMichael Chan u8 unused_0[7]; 9399894aa69aSMichael Chan }; 9400894aa69aSMichael Chan 9401894aa69aSMichael Chan /* hwrm_nvm_get_variable_input (size:320b/40B) */ 9402894aa69aSMichael Chan struct hwrm_nvm_get_variable_input { 9403894aa69aSMichael Chan __le16 req_type; 9404894aa69aSMichael Chan __le16 cmpl_ring; 9405894aa69aSMichael Chan __le16 seq_id; 9406894aa69aSMichael Chan __le16 target_id; 9407894aa69aSMichael Chan __le64 resp_addr; 9408894aa69aSMichael Chan __le64 dest_data_addr; 9409894aa69aSMichael Chan __le16 data_len; 9410894aa69aSMichael Chan __le16 option_num; 9411894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9412894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9413894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9414894aa69aSMichael Chan __le16 dimensions; 9415894aa69aSMichael Chan __le16 index_0; 9416894aa69aSMichael Chan __le16 index_1; 9417894aa69aSMichael Chan __le16 index_2; 9418894aa69aSMichael Chan __le16 index_3; 9419894aa69aSMichael Chan u8 flags; 9420894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 9421894aa69aSMichael Chan u8 unused_0; 9422894aa69aSMichael Chan }; 9423894aa69aSMichael Chan 9424894aa69aSMichael Chan /* hwrm_nvm_get_variable_output (size:128b/16B) */ 9425894aa69aSMichael Chan struct hwrm_nvm_get_variable_output { 9426894aa69aSMichael Chan __le16 error_code; 9427894aa69aSMichael Chan __le16 req_type; 9428894aa69aSMichael Chan __le16 seq_id; 9429894aa69aSMichael Chan __le16 resp_len; 9430894aa69aSMichael Chan __le16 data_len; 9431894aa69aSMichael Chan __le16 option_num; 9432894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 9433894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 9434894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 9435894aa69aSMichael Chan u8 unused_0[3]; 9436894aa69aSMichael Chan u8 valid; 9437894aa69aSMichael Chan }; 9438894aa69aSMichael Chan 9439894aa69aSMichael Chan /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 9440894aa69aSMichael Chan struct hwrm_nvm_get_variable_cmd_err { 9441894aa69aSMichael Chan u8 code; 9442894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9443894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9444894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9445894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 9446894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 9447894aa69aSMichael Chan u8 unused_0[7]; 9448894aa69aSMichael Chan }; 9449894aa69aSMichael Chan 9450894aa69aSMichael Chan /* hwrm_nvm_set_variable_input (size:320b/40B) */ 9451894aa69aSMichael Chan struct hwrm_nvm_set_variable_input { 9452894aa69aSMichael Chan __le16 req_type; 9453894aa69aSMichael Chan __le16 cmpl_ring; 9454894aa69aSMichael Chan __le16 seq_id; 9455894aa69aSMichael Chan __le16 target_id; 9456894aa69aSMichael Chan __le64 resp_addr; 9457894aa69aSMichael Chan __le64 src_data_addr; 9458894aa69aSMichael Chan __le16 data_len; 9459894aa69aSMichael Chan __le16 option_num; 9460894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 9461894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 9462894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 9463894aa69aSMichael Chan __le16 dimensions; 9464894aa69aSMichael Chan __le16 index_0; 9465894aa69aSMichael Chan __le16 index_1; 9466894aa69aSMichael Chan __le16 index_2; 9467894aa69aSMichael Chan __le16 index_3; 9468894aa69aSMichael Chan u8 flags; 9469894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 9470894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 9471894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 9472894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 9473894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 94746fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 94756fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 94766fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 94772792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 94782792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 94792792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 9480894aa69aSMichael Chan u8 unused_0; 9481894aa69aSMichael Chan }; 9482894aa69aSMichael Chan 9483894aa69aSMichael Chan /* hwrm_nvm_set_variable_output (size:128b/16B) */ 9484894aa69aSMichael Chan struct hwrm_nvm_set_variable_output { 9485894aa69aSMichael Chan __le16 error_code; 9486894aa69aSMichael Chan __le16 req_type; 9487894aa69aSMichael Chan __le16 seq_id; 9488894aa69aSMichael Chan __le16 resp_len; 9489894aa69aSMichael Chan u8 unused_0[7]; 9490894aa69aSMichael Chan u8 valid; 9491894aa69aSMichael Chan }; 9492894aa69aSMichael Chan 9493894aa69aSMichael Chan /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 9494894aa69aSMichael Chan struct hwrm_nvm_set_variable_cmd_err { 9495894aa69aSMichael Chan u8 code; 9496894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 9497894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 9498894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 9499894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 9500894aa69aSMichael Chan u8 unused_0[7]; 9501894aa69aSMichael Chan }; 9502894aa69aSMichael Chan 9503894aa69aSMichael Chan /* hwrm_selftest_qlist_input (size:128b/16B) */ 9504894aa69aSMichael Chan struct hwrm_selftest_qlist_input { 9505894aa69aSMichael Chan __le16 req_type; 9506894aa69aSMichael Chan __le16 cmpl_ring; 9507894aa69aSMichael Chan __le16 seq_id; 9508894aa69aSMichael Chan __le16 target_id; 9509894aa69aSMichael Chan __le64 resp_addr; 9510894aa69aSMichael Chan }; 9511894aa69aSMichael Chan 9512894aa69aSMichael Chan /* hwrm_selftest_qlist_output (size:2240b/280B) */ 9513894aa69aSMichael Chan struct hwrm_selftest_qlist_output { 9514894aa69aSMichael Chan __le16 error_code; 9515894aa69aSMichael Chan __le16 req_type; 9516894aa69aSMichael Chan __le16 seq_id; 9517894aa69aSMichael Chan __le16 resp_len; 9518894aa69aSMichael Chan u8 num_tests; 9519894aa69aSMichael Chan u8 available_tests; 9520894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 9521894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 9522894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 9523894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 9524894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 9525894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9526894aa69aSMichael Chan u8 offline_tests; 9527894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 9528894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 9529894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 9530894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 9531894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 9532894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 9533894aa69aSMichael Chan u8 unused_0; 9534894aa69aSMichael Chan __le16 test_timeout; 9535894aa69aSMichael Chan u8 unused_1[2]; 9536894aa69aSMichael Chan char test0_name[32]; 9537894aa69aSMichael Chan char test1_name[32]; 9538894aa69aSMichael Chan char test2_name[32]; 9539894aa69aSMichael Chan char test3_name[32]; 9540894aa69aSMichael Chan char test4_name[32]; 9541894aa69aSMichael Chan char test5_name[32]; 9542894aa69aSMichael Chan char test6_name[32]; 9543894aa69aSMichael Chan char test7_name[32]; 9544bfc6e5fbSMichael Chan u8 eyescope_target_BER_support; 9545bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 9546bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 9547bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 9548bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 9549bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 9550bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 9551bfc6e5fbSMichael Chan u8 unused_2[6]; 9552894aa69aSMichael Chan u8 valid; 9553894aa69aSMichael Chan }; 9554894aa69aSMichael Chan 9555894aa69aSMichael Chan /* hwrm_selftest_exec_input (size:192b/24B) */ 9556894aa69aSMichael Chan struct hwrm_selftest_exec_input { 9557894aa69aSMichael Chan __le16 req_type; 9558894aa69aSMichael Chan __le16 cmpl_ring; 9559894aa69aSMichael Chan __le16 seq_id; 9560894aa69aSMichael Chan __le16 target_id; 9561894aa69aSMichael Chan __le64 resp_addr; 9562894aa69aSMichael Chan u8 flags; 9563894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 9564894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 9565894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 9566894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 9567894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 9568894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 9569d4f52de0SMichael Chan u8 unused_0[7]; 9570894aa69aSMichael Chan }; 9571894aa69aSMichael Chan 9572894aa69aSMichael Chan /* hwrm_selftest_exec_output (size:128b/16B) */ 9573894aa69aSMichael Chan struct hwrm_selftest_exec_output { 9574894aa69aSMichael Chan __le16 error_code; 9575894aa69aSMichael Chan __le16 req_type; 9576894aa69aSMichael Chan __le16 seq_id; 9577894aa69aSMichael Chan __le16 resp_len; 9578894aa69aSMichael Chan u8 requested_tests; 9579894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 9580894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 9581894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 9582894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 9583894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 9584894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 9585894aa69aSMichael Chan u8 test_success; 9586894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 9587894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 9588894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 9589894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 9590894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 9591894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 9592894aa69aSMichael Chan u8 unused_0[5]; 9593894aa69aSMichael Chan u8 valid; 9594894aa69aSMichael Chan }; 9595894aa69aSMichael Chan 9596894aa69aSMichael Chan /* hwrm_selftest_irq_input (size:128b/16B) */ 9597894aa69aSMichael Chan struct hwrm_selftest_irq_input { 9598894aa69aSMichael Chan __le16 req_type; 9599894aa69aSMichael Chan __le16 cmpl_ring; 9600894aa69aSMichael Chan __le16 seq_id; 9601894aa69aSMichael Chan __le16 target_id; 9602894aa69aSMichael Chan __le64 resp_addr; 9603894aa69aSMichael Chan }; 9604894aa69aSMichael Chan 9605894aa69aSMichael Chan /* hwrm_selftest_irq_output (size:128b/16B) */ 9606894aa69aSMichael Chan struct hwrm_selftest_irq_output { 9607894aa69aSMichael Chan __le16 error_code; 9608894aa69aSMichael Chan __le16 req_type; 9609894aa69aSMichael Chan __le16 seq_id; 9610894aa69aSMichael Chan __le16 resp_len; 9611894aa69aSMichael Chan u8 unused_0[7]; 9612894aa69aSMichael Chan u8 valid; 9613894aa69aSMichael Chan }; 9614894aa69aSMichael Chan 96159d6b648cSMichael Chan /* db_push_info (size:64b/8B) */ 96169d6b648cSMichael Chan struct db_push_info { 96179d6b648cSMichael Chan u32 push_size_push_index; 96189d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 96199d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 96209d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 96219d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 96229d6b648cSMichael Chan u32 reserved32; 96239d6b648cSMichael Chan }; 96249d6b648cSMichael Chan 9625460c2577SMichael Chan /* fw_status_reg (size:32b/4B) */ 9626460c2577SMichael Chan struct fw_status_reg { 9627460c2577SMichael Chan u32 fw_status; 9628460c2577SMichael Chan #define FW_STATUS_REG_CODE_MASK 0xffffUL 9629460c2577SMichael Chan #define FW_STATUS_REG_CODE_SFT 0 9630460c2577SMichael Chan #define FW_STATUS_REG_CODE_READY 0x8000UL 9631460c2577SMichael Chan #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 9632460c2577SMichael Chan #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 9633460c2577SMichael Chan #define FW_STATUS_REG_RECOVERABLE 0x20000UL 9634460c2577SMichael Chan #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 9635460c2577SMichael Chan #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 9636460c2577SMichael Chan #define FW_STATUS_REG_SHUTDOWN 0x100000UL 9637424174f1SVasundhara Volam #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 963878eeadb8SMichael Chan #define FW_STATUS_REG_RECOVERING 0x400000UL 9639460c2577SMichael Chan }; 9640460c2577SMichael Chan 96419d6b648cSMichael Chan /* hcomm_status (size:64b/8B) */ 96429d6b648cSMichael Chan struct hcomm_status { 96439d6b648cSMichael Chan u32 sig_ver; 96449d6b648cSMichael Chan #define HCOMM_STATUS_VER_MASK 0xffUL 96459d6b648cSMichael Chan #define HCOMM_STATUS_VER_SFT 0 96469d6b648cSMichael Chan #define HCOMM_STATUS_VER_LATEST 0x1UL 96479d6b648cSMichael Chan #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 96489d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 96499d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_SFT 8 96509d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 96519d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 96529d6b648cSMichael Chan u32 fw_status_loc; 96539d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 96549d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 96559d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 96569d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 96579d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 96589d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 96599d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 96609d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 96619d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 96629d6b648cSMichael Chan }; 96639d6b648cSMichael Chan #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 96649d6b648cSMichael Chan 9665894aa69aSMichael Chan #endif /* _BNXT_HSI_H_ */ 9666