1c0c050c5SMichael Chan /* Broadcom NetXtreme-C/E network driver. 2c0c050c5SMichael Chan * 311f15ed3SMichael Chan * Copyright (c) 2014-2016 Broadcom Corporation 42792b5b9SMichael Chan * Copyright (c) 2014-2018 Broadcom Limited 5*16db6323SMichael Chan * Copyright (c) 2018-2021 Broadcom Inc. 6c0c050c5SMichael Chan * 7c0c050c5SMichael Chan * This program is free software; you can redistribute it and/or modify 8c0c050c5SMichael Chan * it under the terms of the GNU General Public License as published by 9c0c050c5SMichael Chan * the Free Software Foundation. 10894aa69aSMichael Chan * 11894aa69aSMichael Chan * DO NOT MODIFY!!! This file is automatically generated. 12c0c050c5SMichael Chan */ 13c0c050c5SMichael Chan 14894aa69aSMichael Chan #ifndef _BNXT_HSI_H_ 15894aa69aSMichael Chan #define _BNXT_HSI_H_ 16c0c050c5SMichael Chan 17894aa69aSMichael Chan /* hwrm_cmd_hdr (size:128b/16B) */ 18894aa69aSMichael Chan struct hwrm_cmd_hdr { 19894aa69aSMichael Chan __le16 req_type; 20894aa69aSMichael Chan __le16 cmpl_ring; 21894aa69aSMichael Chan __le16 seq_id; 22894aa69aSMichael Chan __le16 target_id; 23894aa69aSMichael Chan __le64 resp_addr; 24894aa69aSMichael Chan }; 2587c374deSMichael Chan 26894aa69aSMichael Chan /* hwrm_resp_hdr (size:64b/8B) */ 27894aa69aSMichael Chan struct hwrm_resp_hdr { 28894aa69aSMichael Chan __le16 error_code; 29894aa69aSMichael Chan __le16 req_type; 30894aa69aSMichael Chan __le16 seq_id; 31894aa69aSMichael Chan __le16 resp_len; 32894aa69aSMichael Chan }; 338eb992e8SMichael Chan 34894aa69aSMichael Chan #define CMD_DISCR_TLV_ENCAP 0x8000UL 35894aa69aSMichael Chan #define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36894aa69aSMichael Chan 37894aa69aSMichael Chan 38894aa69aSMichael Chan #define TLV_TYPE_HWRM_REQUEST 0x1UL 39894aa69aSMichael Chan #define TLV_TYPE_HWRM_RESPONSE 0x2UL 40894aa69aSMichael Chan #define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 4131d357c0SMichael Chan #define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 4231d357c0SMichael Chan #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 432792b5b9SMichael Chan #define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 44894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 45894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 46894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 4772e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 482792b5b9SMichael Chan #define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 49894aa69aSMichael Chan #define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 5072e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 5172e0c9f9SMichael Chan #define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 5272e0c9f9SMichael Chan #define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 53894aa69aSMichael Chan 54894aa69aSMichael Chan 55894aa69aSMichael Chan /* tlv (size:64b/8B) */ 56894aa69aSMichael Chan struct tlv { 57894aa69aSMichael Chan __le16 cmd_discr; 58894aa69aSMichael Chan u8 reserved_8b; 59894aa69aSMichael Chan u8 flags; 60894aa69aSMichael Chan #define TLV_FLAGS_MORE 0x1UL 61894aa69aSMichael Chan #define TLV_FLAGS_MORE_LAST 0x0UL 62894aa69aSMichael Chan #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 63894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED 0x2UL 64894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 65894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 66894aa69aSMichael Chan #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 67894aa69aSMichael Chan __le16 tlv_type; 68894aa69aSMichael Chan __le16 length; 69894aa69aSMichael Chan }; 70894aa69aSMichael Chan 71894aa69aSMichael Chan /* input (size:128b/16B) */ 72894aa69aSMichael Chan struct input { 73894aa69aSMichael Chan __le16 req_type; 74894aa69aSMichael Chan __le16 cmpl_ring; 75894aa69aSMichael Chan __le16 seq_id; 76894aa69aSMichael Chan __le16 target_id; 77894aa69aSMichael Chan __le64 resp_addr; 78894aa69aSMichael Chan }; 79894aa69aSMichael Chan 80894aa69aSMichael Chan /* output (size:64b/8B) */ 81894aa69aSMichael Chan struct output { 82894aa69aSMichael Chan __le16 error_code; 83894aa69aSMichael Chan __le16 req_type; 84894aa69aSMichael Chan __le16 seq_id; 85894aa69aSMichael Chan __le16 resp_len; 86894aa69aSMichael Chan }; 87894aa69aSMichael Chan 88894aa69aSMichael Chan /* hwrm_short_input (size:128b/16B) */ 89894aa69aSMichael Chan struct hwrm_short_input { 90894aa69aSMichael Chan __le16 req_type; 91894aa69aSMichael Chan __le16 signature; 92894aa69aSMichael Chan #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 93894aa69aSMichael Chan #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 944a50ddc2SMichael Chan __le16 target_id; 954a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 964a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 974a50ddc2SMichael Chan #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 98894aa69aSMichael Chan __le16 size; 99894aa69aSMichael Chan __le64 req_addr; 100894aa69aSMichael Chan }; 101894aa69aSMichael Chan 102894aa69aSMichael Chan /* cmd_nums (size:64b/8B) */ 103894aa69aSMichael Chan struct cmd_nums { 104894aa69aSMichael Chan __le16 req_type; 105894aa69aSMichael Chan #define HWRM_VER_GET 0x0UL 1063293ec23SMichael Chan #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 1076fc92c33SMichael Chan #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 108894aa69aSMichael Chan #define HWRM_FUNC_BUF_UNRGTR 0xeUL 109894aa69aSMichael Chan #define HWRM_FUNC_VF_CFG 0xfUL 110894aa69aSMichael Chan #define HWRM_RESERVED1 0x10UL 111894aa69aSMichael Chan #define HWRM_FUNC_RESET 0x11UL 112894aa69aSMichael Chan #define HWRM_FUNC_GETFID 0x12UL 113894aa69aSMichael Chan #define HWRM_FUNC_VF_ALLOC 0x13UL 114894aa69aSMichael Chan #define HWRM_FUNC_VF_FREE 0x14UL 115894aa69aSMichael Chan #define HWRM_FUNC_QCAPS 0x15UL 116894aa69aSMichael Chan #define HWRM_FUNC_QCFG 0x16UL 117894aa69aSMichael Chan #define HWRM_FUNC_CFG 0x17UL 118894aa69aSMichael Chan #define HWRM_FUNC_QSTATS 0x18UL 119894aa69aSMichael Chan #define HWRM_FUNC_CLR_STATS 0x19UL 120894aa69aSMichael Chan #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 121894aa69aSMichael Chan #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 122894aa69aSMichael Chan #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 123894aa69aSMichael Chan #define HWRM_FUNC_DRV_RGTR 0x1dUL 124894aa69aSMichael Chan #define HWRM_FUNC_DRV_QVER 0x1eUL 125894aa69aSMichael Chan #define HWRM_FUNC_BUF_RGTR 0x1fUL 126894aa69aSMichael Chan #define HWRM_PORT_PHY_CFG 0x20UL 127894aa69aSMichael Chan #define HWRM_PORT_MAC_CFG 0x21UL 128894aa69aSMichael Chan #define HWRM_PORT_TS_QUERY 0x22UL 129894aa69aSMichael Chan #define HWRM_PORT_QSTATS 0x23UL 130894aa69aSMichael Chan #define HWRM_PORT_LPBK_QSTATS 0x24UL 131894aa69aSMichael Chan #define HWRM_PORT_CLR_STATS 0x25UL 132894aa69aSMichael Chan #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 133894aa69aSMichael Chan #define HWRM_PORT_PHY_QCFG 0x27UL 134894aa69aSMichael Chan #define HWRM_PORT_MAC_QCFG 0x28UL 135894aa69aSMichael Chan #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 136894aa69aSMichael Chan #define HWRM_PORT_PHY_QCAPS 0x2aUL 137894aa69aSMichael Chan #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 138894aa69aSMichael Chan #define HWRM_PORT_PHY_I2C_READ 0x2cUL 139894aa69aSMichael Chan #define HWRM_PORT_LED_CFG 0x2dUL 140894aa69aSMichael Chan #define HWRM_PORT_LED_QCFG 0x2eUL 141894aa69aSMichael Chan #define HWRM_PORT_LED_QCAPS 0x2fUL 142894aa69aSMichael Chan #define HWRM_QUEUE_QPORTCFG 0x30UL 143894aa69aSMichael Chan #define HWRM_QUEUE_QCFG 0x31UL 144894aa69aSMichael Chan #define HWRM_QUEUE_CFG 0x32UL 145894aa69aSMichael Chan #define HWRM_FUNC_VLAN_CFG 0x33UL 146894aa69aSMichael Chan #define HWRM_FUNC_VLAN_QCFG 0x34UL 147894aa69aSMichael Chan #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 148894aa69aSMichael Chan #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 149894aa69aSMichael Chan #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 150894aa69aSMichael Chan #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 151894aa69aSMichael Chan #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 152894aa69aSMichael Chan #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 153894aa69aSMichael Chan #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 154894aa69aSMichael Chan #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 155894aa69aSMichael Chan #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 156894aa69aSMichael Chan #define HWRM_VNIC_ALLOC 0x40UL 157894aa69aSMichael Chan #define HWRM_VNIC_FREE 0x41UL 158894aa69aSMichael Chan #define HWRM_VNIC_CFG 0x42UL 159894aa69aSMichael Chan #define HWRM_VNIC_QCFG 0x43UL 160894aa69aSMichael Chan #define HWRM_VNIC_TPA_CFG 0x44UL 161894aa69aSMichael Chan #define HWRM_VNIC_TPA_QCFG 0x45UL 162894aa69aSMichael Chan #define HWRM_VNIC_RSS_CFG 0x46UL 163894aa69aSMichael Chan #define HWRM_VNIC_RSS_QCFG 0x47UL 164894aa69aSMichael Chan #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165894aa69aSMichael Chan #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166894aa69aSMichael Chan #define HWRM_VNIC_QCAPS 0x4aUL 167*16db6323SMichael Chan #define HWRM_VNIC_UPDATE 0x4bUL 168894aa69aSMichael Chan #define HWRM_RING_ALLOC 0x50UL 169894aa69aSMichael Chan #define HWRM_RING_FREE 0x51UL 170894aa69aSMichael Chan #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 171894aa69aSMichael Chan #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 1726fc92c33SMichael Chan #define HWRM_RING_AGGINT_QCAPS 0x54UL 173bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_ALLOC 0x55UL 174bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_CFG 0x56UL 175bfc6e5fbSMichael Chan #define HWRM_RING_SCHQ_FREE 0x57UL 176894aa69aSMichael Chan #define HWRM_RING_RESET 0x5eUL 177894aa69aSMichael Chan #define HWRM_RING_GRP_ALLOC 0x60UL 178894aa69aSMichael Chan #define HWRM_RING_GRP_FREE 0x61UL 179bfc6e5fbSMichael Chan #define HWRM_RING_CFG 0x62UL 180bfc6e5fbSMichael Chan #define HWRM_RING_QCFG 0x63UL 181894aa69aSMichael Chan #define HWRM_RESERVED5 0x64UL 182894aa69aSMichael Chan #define HWRM_RESERVED6 0x65UL 183894aa69aSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 184894aa69aSMichael Chan #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 18541136ab3SMichael Chan #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 18641136ab3SMichael Chan #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 18741136ab3SMichael Chan #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 188*16db6323SMichael Chan #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 189*16db6323SMichael Chan #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 190*16db6323SMichael Chan #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 191894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 192894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_FREE 0x91UL 193894aa69aSMichael Chan #define HWRM_CFA_L2_FILTER_CFG 0x92UL 194894aa69aSMichael Chan #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 195894aa69aSMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 196894aa69aSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 197894aa69aSMichael Chan #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 198894aa69aSMichael Chan #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 199894aa69aSMichael Chan #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 200894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 201894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 202894aa69aSMichael Chan #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 203894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 204894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 205894aa69aSMichael Chan #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 206894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 207894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 208894aa69aSMichael Chan #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 20931d357c0SMichael Chan #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 210894aa69aSMichael Chan #define HWRM_STAT_CTX_ALLOC 0xb0UL 211894aa69aSMichael Chan #define HWRM_STAT_CTX_FREE 0xb1UL 212894aa69aSMichael Chan #define HWRM_STAT_CTX_QUERY 0xb2UL 213894aa69aSMichael Chan #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 214d4f52de0SMichael Chan #define HWRM_PORT_QSTATS_EXT 0xb4UL 2153322479eSMichael Chan #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 2163322479eSMichael Chan #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 21772e0c9f9SMichael Chan #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 21872e0c9f9SMichael Chan #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 219460c2577SMichael Chan #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 2209d6b648cSMichael Chan #define HWRM_RESERVED7 0xbaUL 2219d6b648cSMichael Chan #define HWRM_PORT_TX_FIR_CFG 0xbbUL 2229d6b648cSMichael Chan #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 2239d6b648cSMichael Chan #define HWRM_PORT_ECN_QSTATS 0xbdUL 224*16db6323SMichael Chan #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 225*16db6323SMichael Chan #define HWRM_FW_LIVEPATCH 0xbfUL 226894aa69aSMichael Chan #define HWRM_FW_RESET 0xc0UL 227894aa69aSMichael Chan #define HWRM_FW_QSTATUS 0xc1UL 2286fc92c33SMichael Chan #define HWRM_FW_HEALTH_CHECK 0xc2UL 2296fc92c33SMichael Chan #define HWRM_FW_SYNC 0xc3UL 23041136ab3SMichael Chan #define HWRM_FW_STATE_QCAPS 0xc4UL 23172e0c9f9SMichael Chan #define HWRM_FW_STATE_QUIESCE 0xc5UL 23272e0c9f9SMichael Chan #define HWRM_FW_STATE_BACKUP 0xc6UL 23372e0c9f9SMichael Chan #define HWRM_FW_STATE_RESTORE 0xc7UL 234894aa69aSMichael Chan #define HWRM_FW_SET_TIME 0xc8UL 235894aa69aSMichael Chan #define HWRM_FW_GET_TIME 0xc9UL 236894aa69aSMichael Chan #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 237894aa69aSMichael Chan #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 238894aa69aSMichael Chan #define HWRM_FW_IPC_MAILBOX 0xccUL 239460c2577SMichael Chan #define HWRM_FW_ECN_CFG 0xcdUL 240460c2577SMichael Chan #define HWRM_FW_ECN_QCFG 0xceUL 241bfc6e5fbSMichael Chan #define HWRM_FW_SECURE_CFG 0xcfUL 242894aa69aSMichael Chan #define HWRM_EXEC_FWD_RESP 0xd0UL 243894aa69aSMichael Chan #define HWRM_REJECT_FWD_RESP 0xd1UL 244894aa69aSMichael Chan #define HWRM_FWD_RESP 0xd2UL 245894aa69aSMichael Chan #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 246d4f52de0SMichael Chan #define HWRM_OEM_CMD 0xd4UL 2474a50ddc2SMichael Chan #define HWRM_PORT_PRBS_TEST 0xd5UL 24872e0c9f9SMichael Chan #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 24972e0c9f9SMichael Chan #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 25041136ab3SMichael Chan #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 25141136ab3SMichael Chan #define HWRM_PORT_DSC_DUMP 0xd9UL 252894aa69aSMichael Chan #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 25372e0c9f9SMichael Chan #define HWRM_REG_POWER_QUERY 0xe1UL 25441136ab3SMichael Chan #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 255460c2577SMichael Chan #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 256894aa69aSMichael Chan #define HWRM_WOL_FILTER_ALLOC 0xf0UL 257894aa69aSMichael Chan #define HWRM_WOL_FILTER_FREE 0xf1UL 258894aa69aSMichael Chan #define HWRM_WOL_FILTER_QCFG 0xf2UL 259894aa69aSMichael Chan #define HWRM_WOL_REASON_QCFG 0xf3UL 2603322479eSMichael Chan #define HWRM_CFA_METER_QCAPS 0xf4UL 261894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 262894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 263894aa69aSMichael Chan #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 264894aa69aSMichael Chan #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 265894aa69aSMichael Chan #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 2663293ec23SMichael Chan #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 267894aa69aSMichael Chan #define HWRM_CFA_VFR_ALLOC 0xfdUL 268894aa69aSMichael Chan #define HWRM_CFA_VFR_FREE 0xfeUL 269894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 270894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_FREE 0x101UL 271894aa69aSMichael Chan #define HWRM_CFA_VF_PAIR_INFO 0x102UL 272894aa69aSMichael Chan #define HWRM_CFA_FLOW_ALLOC 0x103UL 273894aa69aSMichael Chan #define HWRM_CFA_FLOW_FREE 0x104UL 274894aa69aSMichael Chan #define HWRM_CFA_FLOW_FLUSH 0x105UL 275894aa69aSMichael Chan #define HWRM_CFA_FLOW_STATS 0x106UL 276894aa69aSMichael Chan #define HWRM_CFA_FLOW_INFO 0x107UL 277894aa69aSMichael Chan #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 278894aa69aSMichael Chan #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 279894aa69aSMichael Chan #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 280894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 281894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 282894aa69aSMichael Chan #define HWRM_CFA_PAIR_ALLOC 0x10dUL 283894aa69aSMichael Chan #define HWRM_CFA_PAIR_FREE 0x10eUL 284894aa69aSMichael Chan #define HWRM_CFA_PAIR_INFO 0x10fUL 285894aa69aSMichael Chan #define HWRM_FW_IPC_MSG 0x110UL 286894aa69aSMichael Chan #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 28731d357c0SMichael Chan #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 2883322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 2893322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 2903322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 2913322479eSMichael Chan #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 2923322479eSMichael Chan #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 2933322479eSMichael Chan #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 2943322479eSMichael Chan #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 2953322479eSMichael Chan #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 2963322479eSMichael Chan #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 2973322479eSMichael Chan #define HWRM_CFA_COUNTER_CFG 0x11cUL 2983322479eSMichael Chan #define HWRM_CFA_COUNTER_QCFG 0x11dUL 2993322479eSMichael Chan #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 3003322479eSMichael Chan #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 3013322479eSMichael Chan #define HWRM_CFA_EEM_QCAPS 0x120UL 3023322479eSMichael Chan #define HWRM_CFA_EEM_CFG 0x121UL 3033322479eSMichael Chan #define HWRM_CFA_EEM_QCFG 0x122UL 3043322479eSMichael Chan #define HWRM_CFA_EEM_OP 0x123UL 3053322479eSMichael Chan #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 3064a50ddc2SMichael Chan #define HWRM_CFA_TFLIB 0x125UL 307894aa69aSMichael Chan #define HWRM_ENGINE_CKV_STATUS 0x12eUL 308894aa69aSMichael Chan #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 309894aa69aSMichael Chan #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 310894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 311894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 312894aa69aSMichael Chan #define HWRM_ENGINE_CKV_FLUSH 0x133UL 313894aa69aSMichael Chan #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 314894aa69aSMichael Chan #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 3153293ec23SMichael Chan #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 3164a50ddc2SMichael Chan #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 317894aa69aSMichael Chan #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 318894aa69aSMichael Chan #define HWRM_ENGINE_QG_QUERY 0x13dUL 319894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 320894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 321894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 322894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 323894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 324894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_BIND 0x143UL 325894aa69aSMichael Chan #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 326894aa69aSMichael Chan #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 327894aa69aSMichael Chan #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 328894aa69aSMichael Chan #define HWRM_ENGINE_SG_QUERY 0x147UL 329894aa69aSMichael Chan #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 330894aa69aSMichael Chan #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 331894aa69aSMichael Chan #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 332894aa69aSMichael Chan #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 333894aa69aSMichael Chan #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 334894aa69aSMichael Chan #define HWRM_ENGINE_STATS_CONFIG 0x155UL 335894aa69aSMichael Chan #define HWRM_ENGINE_STATS_CLEAR 0x156UL 336894aa69aSMichael Chan #define HWRM_ENGINE_STATS_QUERY 0x157UL 33741136ab3SMichael Chan #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 338894aa69aSMichael Chan #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 339894aa69aSMichael Chan #define HWRM_ENGINE_RQ_FREE 0x15fUL 340894aa69aSMichael Chan #define HWRM_ENGINE_CQ_ALLOC 0x160UL 341894aa69aSMichael Chan #define HWRM_ENGINE_CQ_FREE 0x161UL 342894aa69aSMichael Chan #define HWRM_ENGINE_NQ_ALLOC 0x162UL 343894aa69aSMichael Chan #define HWRM_ENGINE_NQ_FREE 0x163UL 344894aa69aSMichael Chan #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 3453293ec23SMichael Chan #define HWRM_ENGINE_FUNC_QCFG 0x165UL 346894aa69aSMichael Chan #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 347894aa69aSMichael Chan #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 3486fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 3496fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 3506fc92c33SMichael Chan #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 3516fc92c33SMichael Chan #define HWRM_FUNC_VF_BW_CFG 0x195UL 3526fc92c33SMichael Chan #define HWRM_FUNC_VF_BW_QCFG 0x196UL 3532792b5b9SMichael Chan #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 354460c2577SMichael Chan #define HWRM_FUNC_QSTATS_EXT 0x198UL 355bfc6e5fbSMichael Chan #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 356*16db6323SMichael Chan #define HWRM_FUNC_SPD_CFG 0x19aUL 357*16db6323SMichael Chan #define HWRM_FUNC_SPD_QCFG 0x19bUL 358894aa69aSMichael Chan #define HWRM_SELFTEST_QLIST 0x200UL 359894aa69aSMichael Chan #define HWRM_SELFTEST_EXEC 0x201UL 360894aa69aSMichael Chan #define HWRM_SELFTEST_IRQ 0x202UL 361894aa69aSMichael Chan #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 362d4f52de0SMichael Chan #define HWRM_PCIE_QSTATS 0x204UL 3634a50ddc2SMichael Chan #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 3644a50ddc2SMichael Chan #define HWRM_MFG_TIMERS_QUERY 0x206UL 3654a50ddc2SMichael Chan #define HWRM_MFG_OTP_CFG 0x207UL 3664a50ddc2SMichael Chan #define HWRM_MFG_OTP_QCFG 0x208UL 3674a50ddc2SMichael Chan #define HWRM_MFG_HDMA_TEST 0x209UL 368460c2577SMichael Chan #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 369460c2577SMichael Chan #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 370*16db6323SMichael Chan #define HWRM_MFG_SOC_IMAGE 0x20cUL 371*16db6323SMichael Chan #define HWRM_MFG_SOC_QSTATUS 0x20dUL 372*16db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 373*16db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 374*16db6323SMichael Chan #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 375460c2577SMichael Chan #define HWRM_TF 0x2bcUL 376460c2577SMichael Chan #define HWRM_TF_VERSION_GET 0x2bdUL 377460c2577SMichael Chan #define HWRM_TF_SESSION_OPEN 0x2c6UL 378460c2577SMichael Chan #define HWRM_TF_SESSION_ATTACH 0x2c7UL 379bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_REGISTER 0x2c8UL 380bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 381bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_CLOSE 0x2caUL 382bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_QCFG 0x2cbUL 383bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 384bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 385bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 386bfc6e5fbSMichael Chan #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 387bfc6e5fbSMichael Chan #define HWRM_TF_TBL_TYPE_GET 0x2daUL 388bfc6e5fbSMichael Chan #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 389424174f1SVasundhara Volam #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 3909d6b648cSMichael Chan #define HWRM_TF_CTXT_MEM_ALLOC 0x2e2UL 3919d6b648cSMichael Chan #define HWRM_TF_CTXT_MEM_FREE 0x2e3UL 392bfc6e5fbSMichael Chan #define HWRM_TF_CTXT_MEM_RGTR 0x2e4UL 393bfc6e5fbSMichael Chan #define HWRM_TF_CTXT_MEM_UNRGTR 0x2e5UL 394bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_QCAPS 0x2e6UL 395bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_OP 0x2e7UL 396bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_CFG 0x2e8UL 397bfc6e5fbSMichael Chan #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 398bfc6e5fbSMichael Chan #define HWRM_TF_EM_INSERT 0x2eaUL 399bfc6e5fbSMichael Chan #define HWRM_TF_EM_DELETE 0x2ebUL 400*16db6323SMichael Chan #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 401bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_SET 0x2f8UL 402bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_GET 0x2f9UL 403bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_MOVE 0x2faUL 404bfc6e5fbSMichael Chan #define HWRM_TF_TCAM_FREE 0x2fbUL 405bfc6e5fbSMichael Chan #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 406bfc6e5fbSMichael Chan #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 4079d6b648cSMichael Chan #define HWRM_TF_IF_TBL_SET 0x2feUL 4089d6b648cSMichael Chan #define HWRM_TF_IF_TBL_GET 0x2ffUL 409460c2577SMichael Chan #define HWRM_SV 0x400UL 410894aa69aSMichael Chan #define HWRM_DBG_READ_DIRECT 0xff10UL 411894aa69aSMichael Chan #define HWRM_DBG_READ_INDIRECT 0xff11UL 412894aa69aSMichael Chan #define HWRM_DBG_WRITE_DIRECT 0xff12UL 413894aa69aSMichael Chan #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 414894aa69aSMichael Chan #define HWRM_DBG_DUMP 0xff14UL 415894aa69aSMichael Chan #define HWRM_DBG_ERASE_NVM 0xff15UL 416894aa69aSMichael Chan #define HWRM_DBG_CFG 0xff16UL 417894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_LIST 0xff17UL 418894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 419894aa69aSMichael Chan #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 4206fc92c33SMichael Chan #define HWRM_DBG_FW_CLI 0xff1aUL 4216fc92c33SMichael Chan #define HWRM_DBG_I2C_CMD 0xff1bUL 42231d357c0SMichael Chan #define HWRM_DBG_RING_INFO_GET 0xff1cUL 4234a50ddc2SMichael Chan #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 4244a50ddc2SMichael Chan #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 425460c2577SMichael Chan #define HWRM_DBG_DRV_TRACE 0xff1fUL 426460c2577SMichael Chan #define HWRM_DBG_QCAPS 0xff20UL 427460c2577SMichael Chan #define HWRM_DBG_QCFG 0xff21UL 428460c2577SMichael Chan #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 429bfc6e5fbSMichael Chan #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 430894aa69aSMichael Chan #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 431894aa69aSMichael Chan #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 432894aa69aSMichael Chan #define HWRM_NVM_FLUSH 0xfff0UL 433894aa69aSMichael Chan #define HWRM_NVM_GET_VARIABLE 0xfff1UL 434894aa69aSMichael Chan #define HWRM_NVM_SET_VARIABLE 0xfff2UL 435894aa69aSMichael Chan #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 436894aa69aSMichael Chan #define HWRM_NVM_MODIFY 0xfff4UL 437894aa69aSMichael Chan #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 438894aa69aSMichael Chan #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 439894aa69aSMichael Chan #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 440894aa69aSMichael Chan #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 441894aa69aSMichael Chan #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 442894aa69aSMichael Chan #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 443894aa69aSMichael Chan #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 444894aa69aSMichael Chan #define HWRM_NVM_RAW_DUMP 0xfffcUL 445894aa69aSMichael Chan #define HWRM_NVM_READ 0xfffdUL 446894aa69aSMichael Chan #define HWRM_NVM_WRITE 0xfffeUL 447894aa69aSMichael Chan #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 448894aa69aSMichael Chan #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 449894aa69aSMichael Chan __le16 unused_0[3]; 450894aa69aSMichael Chan }; 451894aa69aSMichael Chan 452894aa69aSMichael Chan /* ret_codes (size:64b/8B) */ 453894aa69aSMichael Chan struct ret_codes { 454894aa69aSMichael Chan __le16 error_code; 455894aa69aSMichael Chan #define HWRM_ERR_CODE_SUCCESS 0x0UL 456894aa69aSMichael Chan #define HWRM_ERR_CODE_FAIL 0x1UL 457894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 458894aa69aSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 459894aa69aSMichael Chan #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 460894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 461894aa69aSMichael Chan #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 462894aa69aSMichael Chan #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 463894aa69aSMichael Chan #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 4646fc92c33SMichael Chan #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 4653322479eSMichael Chan #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 4663322479eSMichael Chan #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 4674a50ddc2SMichael Chan #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 4684a50ddc2SMichael Chan #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 4694a50ddc2SMichael Chan #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 470894aa69aSMichael Chan #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 47141136ab3SMichael Chan #define HWRM_ERR_CODE_BUSY 0x10UL 4729d6b648cSMichael Chan #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 47331d357c0SMichael Chan #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 474894aa69aSMichael Chan #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 475894aa69aSMichael Chan #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 476894aa69aSMichael Chan #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 477894aa69aSMichael Chan __le16 unused_0[3]; 478894aa69aSMichael Chan }; 479894aa69aSMichael Chan 480894aa69aSMichael Chan /* hwrm_err_output (size:128b/16B) */ 481894aa69aSMichael Chan struct hwrm_err_output { 482894aa69aSMichael Chan __le16 error_code; 483894aa69aSMichael Chan __le16 req_type; 484894aa69aSMichael Chan __le16 seq_id; 485894aa69aSMichael Chan __le16 resp_len; 486894aa69aSMichael Chan __le32 opaque_0; 487894aa69aSMichael Chan __le16 opaque_1; 488894aa69aSMichael Chan u8 cmd_err; 489894aa69aSMichael Chan u8 valid; 490894aa69aSMichael Chan }; 49187c374deSMichael Chan #define HWRM_NA_SIGNATURE ((__le32)(-1)) 492894aa69aSMichael Chan #define HWRM_MAX_REQ_LEN 128 4933293ec23SMichael Chan #define HWRM_MAX_RESP_LEN 704 494894aa69aSMichael Chan #define HW_HASH_INDEX_SIZE 0x80 49587c374deSMichael Chan #define HW_HASH_KEY_SIZE 40 496894aa69aSMichael Chan #define HWRM_RESP_VALID_KEY 1 4974a50ddc2SMichael Chan #define HWRM_TARGET_ID_BONO 0xFFF8 4984a50ddc2SMichael Chan #define HWRM_TARGET_ID_KONG 0xFFF9 4994a50ddc2SMichael Chan #define HWRM_TARGET_ID_APE 0xFFFA 5004a50ddc2SMichael Chan #define HWRM_TARGET_ID_TOOLS 0xFFFD 501894aa69aSMichael Chan #define HWRM_VERSION_MAJOR 1 50231d357c0SMichael Chan #define HWRM_VERSION_MINOR 10 503*16db6323SMichael Chan #define HWRM_VERSION_UPDATE 2 504*16db6323SMichael Chan #define HWRM_VERSION_RSVD 11 505*16db6323SMichael Chan #define HWRM_VERSION_STR "1.10.2.11" 506c0c050c5SMichael Chan 507894aa69aSMichael Chan /* hwrm_ver_get_input (size:192b/24B) */ 508894aa69aSMichael Chan struct hwrm_ver_get_input { 509894aa69aSMichael Chan __le16 req_type; 510894aa69aSMichael Chan __le16 cmpl_ring; 511894aa69aSMichael Chan __le16 seq_id; 512894aa69aSMichael Chan __le16 target_id; 513894aa69aSMichael Chan __le64 resp_addr; 514894aa69aSMichael Chan u8 hwrm_intf_maj; 515894aa69aSMichael Chan u8 hwrm_intf_min; 516894aa69aSMichael Chan u8 hwrm_intf_upd; 517894aa69aSMichael Chan u8 unused_0[5]; 518894aa69aSMichael Chan }; 519894aa69aSMichael Chan 520894aa69aSMichael Chan /* hwrm_ver_get_output (size:1408b/176B) */ 521894aa69aSMichael Chan struct hwrm_ver_get_output { 522894aa69aSMichael Chan __le16 error_code; 523894aa69aSMichael Chan __le16 req_type; 524894aa69aSMichael Chan __le16 seq_id; 525894aa69aSMichael Chan __le16 resp_len; 526894aa69aSMichael Chan u8 hwrm_intf_maj_8b; 527894aa69aSMichael Chan u8 hwrm_intf_min_8b; 528894aa69aSMichael Chan u8 hwrm_intf_upd_8b; 529894aa69aSMichael Chan u8 hwrm_intf_rsvd_8b; 530894aa69aSMichael Chan u8 hwrm_fw_maj_8b; 531894aa69aSMichael Chan u8 hwrm_fw_min_8b; 532894aa69aSMichael Chan u8 hwrm_fw_bld_8b; 533894aa69aSMichael Chan u8 hwrm_fw_rsvd_8b; 534894aa69aSMichael Chan u8 mgmt_fw_maj_8b; 535894aa69aSMichael Chan u8 mgmt_fw_min_8b; 536894aa69aSMichael Chan u8 mgmt_fw_bld_8b; 537894aa69aSMichael Chan u8 mgmt_fw_rsvd_8b; 538894aa69aSMichael Chan u8 netctrl_fw_maj_8b; 539894aa69aSMichael Chan u8 netctrl_fw_min_8b; 540894aa69aSMichael Chan u8 netctrl_fw_bld_8b; 541894aa69aSMichael Chan u8 netctrl_fw_rsvd_8b; 542894aa69aSMichael Chan __le32 dev_caps_cfg; 543894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 544894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 545894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 546894aa69aSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 54731d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 54831d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 54931d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 55031d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 55131d357c0SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 5523322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 5533322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 5543322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 5553322479eSMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 5564a50ddc2SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 557460c2577SMichael Chan #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 558894aa69aSMichael Chan u8 roce_fw_maj_8b; 559894aa69aSMichael Chan u8 roce_fw_min_8b; 560894aa69aSMichael Chan u8 roce_fw_bld_8b; 561894aa69aSMichael Chan u8 roce_fw_rsvd_8b; 562894aa69aSMichael Chan char hwrm_fw_name[16]; 563894aa69aSMichael Chan char mgmt_fw_name[16]; 564894aa69aSMichael Chan char netctrl_fw_name[16]; 5654a50ddc2SMichael Chan char active_pkg_name[16]; 566894aa69aSMichael Chan char roce_fw_name[16]; 567894aa69aSMichael Chan __le16 chip_num; 568894aa69aSMichael Chan u8 chip_rev; 569894aa69aSMichael Chan u8 chip_metal; 570894aa69aSMichael Chan u8 chip_bond_id; 571894aa69aSMichael Chan u8 chip_platform_type; 572894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 573894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 574894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 575894aa69aSMichael Chan #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 576894aa69aSMichael Chan __le16 max_req_win_len; 577894aa69aSMichael Chan __le16 max_resp_len; 578894aa69aSMichael Chan __le16 def_req_timeout; 579894aa69aSMichael Chan u8 flags; 580894aa69aSMichael Chan #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 581894aa69aSMichael Chan #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 582*16db6323SMichael Chan #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 583894aa69aSMichael Chan u8 unused_0[2]; 584894aa69aSMichael Chan u8 always_1; 585894aa69aSMichael Chan __le16 hwrm_intf_major; 586894aa69aSMichael Chan __le16 hwrm_intf_minor; 587894aa69aSMichael Chan __le16 hwrm_intf_build; 588894aa69aSMichael Chan __le16 hwrm_intf_patch; 589894aa69aSMichael Chan __le16 hwrm_fw_major; 590894aa69aSMichael Chan __le16 hwrm_fw_minor; 591894aa69aSMichael Chan __le16 hwrm_fw_build; 592894aa69aSMichael Chan __le16 hwrm_fw_patch; 593894aa69aSMichael Chan __le16 mgmt_fw_major; 594894aa69aSMichael Chan __le16 mgmt_fw_minor; 595894aa69aSMichael Chan __le16 mgmt_fw_build; 596894aa69aSMichael Chan __le16 mgmt_fw_patch; 597894aa69aSMichael Chan __le16 netctrl_fw_major; 598894aa69aSMichael Chan __le16 netctrl_fw_minor; 599894aa69aSMichael Chan __le16 netctrl_fw_build; 600894aa69aSMichael Chan __le16 netctrl_fw_patch; 601894aa69aSMichael Chan __le16 roce_fw_major; 602894aa69aSMichael Chan __le16 roce_fw_minor; 603894aa69aSMichael Chan __le16 roce_fw_build; 604894aa69aSMichael Chan __le16 roce_fw_patch; 605894aa69aSMichael Chan __le16 max_ext_req_len; 606894aa69aSMichael Chan u8 unused_1[5]; 607894aa69aSMichael Chan u8 valid; 608894aa69aSMichael Chan }; 609894aa69aSMichael Chan 610894aa69aSMichael Chan /* eject_cmpl (size:128b/16B) */ 611c0c050c5SMichael Chan struct eject_cmpl { 612c0c050c5SMichael Chan __le16 type; 613c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_MASK 0x3fUL 614c0c050c5SMichael Chan #define EJECT_CMPL_TYPE_SFT 0 615441cabbbSMichael Chan #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 616894aa69aSMichael Chan #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 6173322479eSMichael Chan #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 6183322479eSMichael Chan #define EJECT_CMPL_FLAGS_SFT 6 6193322479eSMichael Chan #define EJECT_CMPL_FLAGS_ERROR 0x40UL 620c0c050c5SMichael Chan __le16 len; 621c0c050c5SMichael Chan __le32 opaque; 6223322479eSMichael Chan __le16 v; 623c0c050c5SMichael Chan #define EJECT_CMPL_V 0x1UL 6243322479eSMichael Chan #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 6253322479eSMichael Chan #define EJECT_CMPL_ERRORS_SFT 1 6263322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 6273322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 6283322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 6293322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 6303322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 6313322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 6323322479eSMichael Chan #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 6333322479eSMichael Chan __le16 reserved16; 634c0c050c5SMichael Chan __le32 unused_2; 635c0c050c5SMichael Chan }; 636c0c050c5SMichael Chan 637894aa69aSMichael Chan /* hwrm_cmpl (size:128b/16B) */ 638c0c050c5SMichael Chan struct hwrm_cmpl { 639c0c050c5SMichael Chan __le16 type; 64087c374deSMichael Chan #define CMPL_TYPE_MASK 0x3fUL 64187c374deSMichael Chan #define CMPL_TYPE_SFT 0 64287c374deSMichael Chan #define CMPL_TYPE_HWRM_DONE 0x20UL 643894aa69aSMichael Chan #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 644c0c050c5SMichael Chan __le16 sequence_id; 645c0c050c5SMichael Chan __le32 unused_1; 646c0c050c5SMichael Chan __le32 v; 64787c374deSMichael Chan #define CMPL_V 0x1UL 648c0c050c5SMichael Chan __le32 unused_3; 649c0c050c5SMichael Chan }; 650c0c050c5SMichael Chan 651894aa69aSMichael Chan /* hwrm_fwd_req_cmpl (size:128b/16B) */ 652c0c050c5SMichael Chan struct hwrm_fwd_req_cmpl { 653c0c050c5SMichael Chan __le16 req_len_type; 65487c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 65587c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_SFT 0 65687c374deSMichael Chan #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 657894aa69aSMichael Chan #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 65887c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 65987c374deSMichael Chan #define FWD_REQ_CMPL_REQ_LEN_SFT 6 660c0c050c5SMichael Chan __le16 source_id; 661894aa69aSMichael Chan __le32 unused0; 662c0c050c5SMichael Chan __le32 req_buf_addr_v[2]; 66387c374deSMichael Chan #define FWD_REQ_CMPL_V 0x1UL 66487c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 66587c374deSMichael Chan #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 666c0c050c5SMichael Chan }; 667c0c050c5SMichael Chan 668894aa69aSMichael Chan /* hwrm_fwd_resp_cmpl (size:128b/16B) */ 669c0c050c5SMichael Chan struct hwrm_fwd_resp_cmpl { 670c0c050c5SMichael Chan __le16 type; 67187c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 67287c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_SFT 0 67387c374deSMichael Chan #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 674894aa69aSMichael Chan #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 675c0c050c5SMichael Chan __le16 source_id; 676c0c050c5SMichael Chan __le16 resp_len; 677c0c050c5SMichael Chan __le16 unused_1; 678c0c050c5SMichael Chan __le32 resp_buf_addr_v[2]; 67987c374deSMichael Chan #define FWD_RESP_CMPL_V 0x1UL 68087c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 68187c374deSMichael Chan #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 682c0c050c5SMichael Chan }; 683c0c050c5SMichael Chan 684894aa69aSMichael Chan /* hwrm_async_event_cmpl (size:128b/16B) */ 685c0c050c5SMichael Chan struct hwrm_async_event_cmpl { 686c0c050c5SMichael Chan __le16 type; 68787c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 68887c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_SFT 0 68987c374deSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 690894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 691c0c050c5SMichael Chan __le16 event_id; 69287c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 69387c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 69487c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 69587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 69687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 69787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 69887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 69987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 70031d357c0SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 7013293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 7029d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 70387c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 70487c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 70587c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 70687c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 70787c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 70887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 70987c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 71087c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 71187c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 71257922b0aSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 7136fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 71431d357c0SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 7153322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 7163322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 7173322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 7183293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 7193293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 7203293ec23SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 7212792b5b9SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 7222792b5b9SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 72341136ab3SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 72441136ab3SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 725460c2577SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 726*16db6323SMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x42UL 7273322479eSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 72887c374deSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 729894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 730c0c050c5SMichael Chan __le32 event_data2; 731c0c050c5SMichael Chan u8 opaque_v; 73287c374deSMichael Chan #define ASYNC_EVENT_CMPL_V 0x1UL 73387c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 73487c374deSMichael Chan #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 735c193554eSMichael Chan u8 timestamp_lo; 736c193554eSMichael Chan __le16 timestamp_hi; 737c0c050c5SMichael Chan __le32 event_data1; 738c0c050c5SMichael Chan }; 739c0c050c5SMichael Chan 740894aa69aSMichael Chan /* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 741c0c050c5SMichael Chan struct hwrm_async_event_cmpl_link_status_change { 742c0c050c5SMichael Chan __le16 type; 74387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 74487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 74587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 746894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 747c0c050c5SMichael Chan __le16 event_id; 74887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 749894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 750c0c050c5SMichael Chan __le32 event_data2; 751c0c050c5SMichael Chan u8 opaque_v; 75287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 75387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 75487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 755c193554eSMichael Chan u8 timestamp_lo; 756c193554eSMichael Chan __le16 timestamp_hi; 757c0c050c5SMichael Chan __le32 event_data1; 75887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 759894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 760894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 76187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 76287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 76387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 76487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 76587c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 7666fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 7676fc92c33SMichael Chan #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 768c0c050c5SMichael Chan }; 769c0c050c5SMichael Chan 770894aa69aSMichael Chan /* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 771c0c050c5SMichael Chan struct hwrm_async_event_cmpl_port_conn_not_allowed { 772c0c050c5SMichael Chan __le16 type; 77387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 77487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 77587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 776894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 777c0c050c5SMichael Chan __le16 event_id; 77887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 779894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 780c0c050c5SMichael Chan __le32 event_data2; 781c0c050c5SMichael Chan u8 opaque_v; 78287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 78387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 78487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 785c193554eSMichael Chan u8 timestamp_lo; 786c193554eSMichael Chan __le16 timestamp_hi; 787c0c050c5SMichael Chan __le32 event_data1; 78887c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 78987c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 79087c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 79187c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 79287c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 79387c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 79487c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 79587c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 79687c374deSMichael Chan #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 79711f15ed3SMichael Chan }; 79811f15ed3SMichael Chan 799894aa69aSMichael Chan /* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 80011f15ed3SMichael Chan struct hwrm_async_event_cmpl_link_speed_cfg_change { 80111f15ed3SMichael Chan __le16 type; 80287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 80387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 80487c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 805894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 80611f15ed3SMichael Chan __le16 event_id; 80787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 808894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 80911f15ed3SMichael Chan __le32 event_data2; 81011f15ed3SMichael Chan u8 opaque_v; 81187c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 81287c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 81387c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 81411f15ed3SMichael Chan u8 timestamp_lo; 81511f15ed3SMichael Chan __le16 timestamp_hi; 81611f15ed3SMichael Chan __le32 event_data1; 81787c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 81887c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 81987c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 82087c374deSMichael Chan #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 821c0c050c5SMichael Chan }; 822c0c050c5SMichael Chan 8233322479eSMichael Chan /* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 8243322479eSMichael Chan struct hwrm_async_event_cmpl_reset_notify { 8253322479eSMichael Chan __le16 type; 8263322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 8273322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 8283322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 8293322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 8303322479eSMichael Chan __le16 event_id; 8313322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 8323322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 8333322479eSMichael Chan __le32 event_data2; 834*16db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 835*16db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 8363322479eSMichael Chan u8 opaque_v; 8373322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 8383322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 8393322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 8403322479eSMichael Chan u8 timestamp_lo; 8413322479eSMichael Chan __le16 timestamp_hi; 8423322479eSMichael Chan __le32 event_data1; 8433322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 8443322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 8453322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 8463322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 8473322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 8483322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 8493322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 8503322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 8513322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 8523322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 853*16db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 854*16db6323SMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET 8553322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 8563322479eSMichael Chan #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 8573322479eSMichael Chan }; 8583322479eSMichael Chan 8593293ec23SMichael Chan /* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 8603293ec23SMichael Chan struct hwrm_async_event_cmpl_error_recovery { 8613293ec23SMichael Chan __le16 type; 8623293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 8633293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 8643293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 8653293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 8663293ec23SMichael Chan __le16 event_id; 8673293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 8683293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 8693293ec23SMichael Chan __le32 event_data2; 8703293ec23SMichael Chan u8 opaque_v; 8713293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 8723293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 8733293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 8743293ec23SMichael Chan u8 timestamp_lo; 8753293ec23SMichael Chan __le16 timestamp_hi; 8763293ec23SMichael Chan __le32 event_data1; 8773293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 8783293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 8793293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 8803293ec23SMichael Chan #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 8813293ec23SMichael Chan }; 8823293ec23SMichael Chan 8839d6b648cSMichael Chan /* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 8849d6b648cSMichael Chan struct hwrm_async_event_cmpl_ring_monitor_msg { 8859d6b648cSMichael Chan __le16 type; 8869d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 8879d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 8889d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 8899d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 8909d6b648cSMichael Chan __le16 event_id; 8919d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 8929d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 8939d6b648cSMichael Chan __le32 event_data2; 8949d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 8959d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 8969d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 8979d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 8989d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 8999d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 9009d6b648cSMichael Chan u8 opaque_v; 9019d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 9029d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 9039d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 9049d6b648cSMichael Chan u8 timestamp_lo; 9059d6b648cSMichael Chan __le16 timestamp_hi; 9069d6b648cSMichael Chan __le32 event_data1; 9079d6b648cSMichael Chan }; 9089d6b648cSMichael Chan 909894aa69aSMichael Chan /* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 91011f15ed3SMichael Chan struct hwrm_async_event_cmpl_vf_cfg_change { 91111f15ed3SMichael Chan __le16 type; 91287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 91387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 91487c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 915894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 91611f15ed3SMichael Chan __le16 event_id; 91787c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 918894aa69aSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 91911f15ed3SMichael Chan __le32 event_data2; 92011f15ed3SMichael Chan u8 opaque_v; 92187c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 92287c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 92387c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 92411f15ed3SMichael Chan u8 timestamp_lo; 92511f15ed3SMichael Chan __le16 timestamp_hi; 92611f15ed3SMichael Chan __le32 event_data1; 92787c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 92887c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 92987c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 93087c374deSMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 93131d357c0SMichael Chan #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 93211f15ed3SMichael Chan }; 93311f15ed3SMichael Chan 93472e0c9f9SMichael Chan /* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 93572e0c9f9SMichael Chan struct hwrm_async_event_cmpl_default_vnic_change { 93672e0c9f9SMichael Chan __le16 type; 93772e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 93872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 93972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 94072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 94172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 94272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 94372e0c9f9SMichael Chan __le16 event_id; 94472e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 94572e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 94672e0c9f9SMichael Chan __le32 event_data2; 94772e0c9f9SMichael Chan u8 opaque_v; 94872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 94972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 95072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 95172e0c9f9SMichael Chan u8 timestamp_lo; 95272e0c9f9SMichael Chan __le16 timestamp_hi; 95372e0c9f9SMichael Chan __le32 event_data1; 95472e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 95572e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 95672e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 95772e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 95872e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 95972e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 96072e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 96172e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 96272e0c9f9SMichael Chan #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 96372e0c9f9SMichael Chan }; 96472e0c9f9SMichael Chan 9653322479eSMichael Chan /* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 9663322479eSMichael Chan struct hwrm_async_event_cmpl_hw_flow_aged { 9673322479eSMichael Chan __le16 type; 9683322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 9693322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 9703322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9713322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 9723322479eSMichael Chan __le16 event_id; 9733322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 9743322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 9753322479eSMichael Chan __le32 event_data2; 9763322479eSMichael Chan u8 opaque_v; 9773322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 9783322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 9793322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 9803322479eSMichael Chan u8 timestamp_lo; 9813322479eSMichael Chan __le16 timestamp_hi; 9823322479eSMichael Chan __le32 event_data1; 9833322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 9843322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 9853322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 9863322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 9873322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 9883322479eSMichael Chan #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 9893322479eSMichael Chan }; 9903322479eSMichael Chan 9913322479eSMichael Chan /* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 9923322479eSMichael Chan struct hwrm_async_event_cmpl_eem_cache_flush_req { 9933322479eSMichael Chan __le16 type; 9943322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 9953322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 9963322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 9973322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 9983322479eSMichael Chan __le16 event_id; 9993322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 10003322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 10013322479eSMichael Chan __le32 event_data2; 10023322479eSMichael Chan u8 opaque_v; 10033322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 10043322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 10053322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 10063322479eSMichael Chan u8 timestamp_lo; 10073322479eSMichael Chan __le16 timestamp_hi; 10083322479eSMichael Chan __le32 event_data1; 10093322479eSMichael Chan }; 10103322479eSMichael Chan 10113322479eSMichael Chan /* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 10123322479eSMichael Chan struct hwrm_async_event_cmpl_eem_cache_flush_done { 10133322479eSMichael Chan __le16 type; 10143322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 10153322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 10163322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10173322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 10183322479eSMichael Chan __le16 event_id; 10193322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 10203322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 10213322479eSMichael Chan __le32 event_data2; 10223322479eSMichael Chan u8 opaque_v; 10233322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 10243322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 10253322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 10263322479eSMichael Chan u8 timestamp_lo; 10273322479eSMichael Chan __le16 timestamp_hi; 10283322479eSMichael Chan __le32 event_data1; 10293322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 10303322479eSMichael Chan #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 10313322479eSMichael Chan }; 10323322479eSMichael Chan 10339d6b648cSMichael Chan /* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 10349d6b648cSMichael Chan struct hwrm_async_event_cmpl_deferred_response { 10359d6b648cSMichael Chan __le16 type; 10369d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 10379d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 10389d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 10399d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 10409d6b648cSMichael Chan __le16 event_id; 10419d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 10429d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 10439d6b648cSMichael Chan __le32 event_data2; 10449d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 10459d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 10469d6b648cSMichael Chan u8 opaque_v; 10479d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 10489d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 10499d6b648cSMichael Chan #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 10509d6b648cSMichael Chan u8 timestamp_lo; 10519d6b648cSMichael Chan __le16 timestamp_hi; 10529d6b648cSMichael Chan __le32 event_data1; 10539d6b648cSMichael Chan }; 10549d6b648cSMichael Chan 1055894aa69aSMichael Chan /* hwrm_func_reset_input (size:192b/24B) */ 1056c0c050c5SMichael Chan struct hwrm_func_reset_input { 1057c0c050c5SMichael Chan __le16 req_type; 1058c0c050c5SMichael Chan __le16 cmpl_ring; 1059c0c050c5SMichael Chan __le16 seq_id; 1060c0c050c5SMichael Chan __le16 target_id; 1061c0c050c5SMichael Chan __le64 resp_addr; 1062c0c050c5SMichael Chan __le32 enables; 1063c0c050c5SMichael Chan #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1064c0c050c5SMichael Chan __le16 vf_id; 1065c193554eSMichael Chan u8 func_reset_level; 1066441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1067441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1068441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1069441cabbbSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1070894aa69aSMichael Chan #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1071c193554eSMichael Chan u8 unused_0; 1072c0c050c5SMichael Chan }; 1073c0c050c5SMichael Chan 1074894aa69aSMichael Chan /* hwrm_func_reset_output (size:128b/16B) */ 1075c0c050c5SMichael Chan struct hwrm_func_reset_output { 1076c0c050c5SMichael Chan __le16 error_code; 1077c0c050c5SMichael Chan __le16 req_type; 1078c0c050c5SMichael Chan __le16 seq_id; 1079c0c050c5SMichael Chan __le16 resp_len; 1080894aa69aSMichael Chan u8 unused_0[7]; 1081c0c050c5SMichael Chan u8 valid; 1082c0c050c5SMichael Chan }; 1083c0c050c5SMichael Chan 1084894aa69aSMichael Chan /* hwrm_func_getfid_input (size:192b/24B) */ 1085c0c050c5SMichael Chan struct hwrm_func_getfid_input { 1086c0c050c5SMichael Chan __le16 req_type; 1087c0c050c5SMichael Chan __le16 cmpl_ring; 1088c0c050c5SMichael Chan __le16 seq_id; 1089c0c050c5SMichael Chan __le16 target_id; 1090c0c050c5SMichael Chan __le64 resp_addr; 1091c0c050c5SMichael Chan __le32 enables; 1092c0c050c5SMichael Chan #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1093c0c050c5SMichael Chan __le16 pci_id; 1094894aa69aSMichael Chan u8 unused_0[2]; 1095c0c050c5SMichael Chan }; 1096c0c050c5SMichael Chan 1097894aa69aSMichael Chan /* hwrm_func_getfid_output (size:128b/16B) */ 1098c0c050c5SMichael Chan struct hwrm_func_getfid_output { 1099c0c050c5SMichael Chan __le16 error_code; 1100c0c050c5SMichael Chan __le16 req_type; 1101c0c050c5SMichael Chan __le16 seq_id; 1102c0c050c5SMichael Chan __le16 resp_len; 1103c0c050c5SMichael Chan __le16 fid; 1104894aa69aSMichael Chan u8 unused_0[5]; 1105c0c050c5SMichael Chan u8 valid; 1106c0c050c5SMichael Chan }; 1107c0c050c5SMichael Chan 1108894aa69aSMichael Chan /* hwrm_func_vf_alloc_input (size:192b/24B) */ 1109c0c050c5SMichael Chan struct hwrm_func_vf_alloc_input { 1110c0c050c5SMichael Chan __le16 req_type; 1111c0c050c5SMichael Chan __le16 cmpl_ring; 1112c0c050c5SMichael Chan __le16 seq_id; 1113c0c050c5SMichael Chan __le16 target_id; 1114c0c050c5SMichael Chan __le64 resp_addr; 1115c0c050c5SMichael Chan __le32 enables; 1116c0c050c5SMichael Chan #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1117c0c050c5SMichael Chan __le16 first_vf_id; 1118c0c050c5SMichael Chan __le16 num_vfs; 1119c0c050c5SMichael Chan }; 1120c0c050c5SMichael Chan 1121894aa69aSMichael Chan /* hwrm_func_vf_alloc_output (size:128b/16B) */ 1122c0c050c5SMichael Chan struct hwrm_func_vf_alloc_output { 1123c0c050c5SMichael Chan __le16 error_code; 1124c0c050c5SMichael Chan __le16 req_type; 1125c0c050c5SMichael Chan __le16 seq_id; 1126c0c050c5SMichael Chan __le16 resp_len; 1127c0c050c5SMichael Chan __le16 first_vf_id; 1128894aa69aSMichael Chan u8 unused_0[5]; 1129c0c050c5SMichael Chan u8 valid; 1130c0c050c5SMichael Chan }; 1131c0c050c5SMichael Chan 1132894aa69aSMichael Chan /* hwrm_func_vf_free_input (size:192b/24B) */ 1133c0c050c5SMichael Chan struct hwrm_func_vf_free_input { 1134c0c050c5SMichael Chan __le16 req_type; 1135c0c050c5SMichael Chan __le16 cmpl_ring; 1136c0c050c5SMichael Chan __le16 seq_id; 1137c0c050c5SMichael Chan __le16 target_id; 1138c0c050c5SMichael Chan __le64 resp_addr; 1139c0c050c5SMichael Chan __le32 enables; 1140c0c050c5SMichael Chan #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1141c0c050c5SMichael Chan __le16 first_vf_id; 1142c0c050c5SMichael Chan __le16 num_vfs; 1143c0c050c5SMichael Chan }; 1144c0c050c5SMichael Chan 1145894aa69aSMichael Chan /* hwrm_func_vf_free_output (size:128b/16B) */ 1146c0c050c5SMichael Chan struct hwrm_func_vf_free_output { 1147c0c050c5SMichael Chan __le16 error_code; 1148c0c050c5SMichael Chan __le16 req_type; 1149c0c050c5SMichael Chan __le16 seq_id; 1150c0c050c5SMichael Chan __le16 resp_len; 1151894aa69aSMichael Chan u8 unused_0[7]; 1152c0c050c5SMichael Chan u8 valid; 1153c0c050c5SMichael Chan }; 1154c0c050c5SMichael Chan 1155894aa69aSMichael Chan /* hwrm_func_vf_cfg_input (size:448b/56B) */ 1156c0c050c5SMichael Chan struct hwrm_func_vf_cfg_input { 1157c0c050c5SMichael Chan __le16 req_type; 1158c0c050c5SMichael Chan __le16 cmpl_ring; 1159c0c050c5SMichael Chan __le16 seq_id; 1160c0c050c5SMichael Chan __le16 target_id; 1161c0c050c5SMichael Chan __le64 resp_addr; 1162c0c050c5SMichael Chan __le32 enables; 1163c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1164c0c050c5SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1165c193554eSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 116611f15ed3SMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1167894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1168894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1169894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1170894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1171894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1172894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1173894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1174894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1175c0c050c5SMichael Chan __le16 mtu; 1176c0c050c5SMichael Chan __le16 guest_vlan; 1177c193554eSMichael Chan __le16 async_event_cr; 117811f15ed3SMichael Chan u8 dflt_mac_addr[6]; 1179894aa69aSMichael Chan __le32 flags; 1180894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1181894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1182894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1183894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1184894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1185894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1186894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1187894aa69aSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1188bfc6e5fbSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1189bfc6e5fbSMichael Chan #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1190894aa69aSMichael Chan __le16 num_rsscos_ctxs; 1191894aa69aSMichael Chan __le16 num_cmpl_rings; 1192894aa69aSMichael Chan __le16 num_tx_rings; 1193894aa69aSMichael Chan __le16 num_rx_rings; 1194894aa69aSMichael Chan __le16 num_l2_ctxs; 1195894aa69aSMichael Chan __le16 num_vnics; 1196894aa69aSMichael Chan __le16 num_stat_ctxs; 1197894aa69aSMichael Chan __le16 num_hw_ring_grps; 1198894aa69aSMichael Chan u8 unused_0[4]; 1199c0c050c5SMichael Chan }; 1200c0c050c5SMichael Chan 1201894aa69aSMichael Chan /* hwrm_func_vf_cfg_output (size:128b/16B) */ 1202c0c050c5SMichael Chan struct hwrm_func_vf_cfg_output { 1203c0c050c5SMichael Chan __le16 error_code; 1204c0c050c5SMichael Chan __le16 req_type; 1205c0c050c5SMichael Chan __le16 seq_id; 1206c0c050c5SMichael Chan __le16 resp_len; 1207894aa69aSMichael Chan u8 unused_0[7]; 1208c0c050c5SMichael Chan u8 valid; 1209c0c050c5SMichael Chan }; 1210c0c050c5SMichael Chan 1211894aa69aSMichael Chan /* hwrm_func_qcaps_input (size:192b/24B) */ 1212c0c050c5SMichael Chan struct hwrm_func_qcaps_input { 1213c0c050c5SMichael Chan __le16 req_type; 1214c0c050c5SMichael Chan __le16 cmpl_ring; 1215c0c050c5SMichael Chan __le16 seq_id; 1216c0c050c5SMichael Chan __le16 target_id; 1217c0c050c5SMichael Chan __le64 resp_addr; 1218c0c050c5SMichael Chan __le16 fid; 1219894aa69aSMichael Chan u8 unused_0[6]; 1220c0c050c5SMichael Chan }; 1221c0c050c5SMichael Chan 1222460c2577SMichael Chan /* hwrm_func_qcaps_output (size:704b/88B) */ 1223c0c050c5SMichael Chan struct hwrm_func_qcaps_output { 1224c0c050c5SMichael Chan __le16 error_code; 1225c0c050c5SMichael Chan __le16 req_type; 1226c0c050c5SMichael Chan __le16 seq_id; 1227c0c050c5SMichael Chan __le16 resp_len; 1228c0c050c5SMichael Chan __le16 fid; 1229c0c050c5SMichael Chan __le16 port_id; 1230c0c050c5SMichael Chan __le32 flags; 1231c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1232c0c050c5SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 123311f15ed3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1234a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1235a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1236a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1237a58a3e68SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1238441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1239441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1240441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1241441cabbbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 124287c374deSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1243894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1244894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1245894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1246894aa69aSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1247d4f52de0SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 12486fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 12496fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 12506fc92c33SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 125131d357c0SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 12523322479eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 12533322479eSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 12543293ec23SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 12554a50ddc2SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 125672e0c9f9SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 125772e0c9f9SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 125841136ab3SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1259460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1260460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1261460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1262460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 126311f15ed3SMichael Chan u8 mac_address[6]; 1264c0c050c5SMichael Chan __le16 max_rsscos_ctx; 1265c0c050c5SMichael Chan __le16 max_cmpl_rings; 1266c0c050c5SMichael Chan __le16 max_tx_rings; 1267c0c050c5SMichael Chan __le16 max_rx_rings; 1268c0c050c5SMichael Chan __le16 max_l2_ctxs; 1269c0c050c5SMichael Chan __le16 max_vnics; 1270c0c050c5SMichael Chan __le16 first_vf_id; 1271c0c050c5SMichael Chan __le16 max_vfs; 1272c0c050c5SMichael Chan __le16 max_stat_ctx; 1273c0c050c5SMichael Chan __le32 max_encap_records; 1274c0c050c5SMichael Chan __le32 max_decap_records; 1275c0c050c5SMichael Chan __le32 max_tx_em_flows; 1276c0c050c5SMichael Chan __le32 max_tx_wm_flows; 1277c0c050c5SMichael Chan __le32 max_rx_em_flows; 1278c0c050c5SMichael Chan __le32 max_rx_wm_flows; 1279c0c050c5SMichael Chan __le32 max_mcast_filters; 1280c0c050c5SMichael Chan __le32 max_flow_id; 1281c0c050c5SMichael Chan __le32 max_hw_ring_grps; 1282441cabbbSMichael Chan __le16 max_sp_tx_rings; 1283460c2577SMichael Chan u8 unused_0[2]; 1284460c2577SMichael Chan __le32 flags_ext; 1285460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1286460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1287460c2577SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1288bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1289bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1290bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1291bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1292bfc6e5fbSMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1293*16db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1294*16db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1295*16db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1296*16db6323SMichael Chan #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1297bfc6e5fbSMichael Chan u8 max_schqs; 12989d6b648cSMichael Chan u8 mpc_chnls_cap; 12999d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 13009d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 13019d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 13029d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 13039d6b648cSMichael Chan #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 13049d6b648cSMichael Chan u8 unused_1; 1305c0c050c5SMichael Chan u8 valid; 1306c0c050c5SMichael Chan }; 1307c0c050c5SMichael Chan 1308894aa69aSMichael Chan /* hwrm_func_qcfg_input (size:192b/24B) */ 130911f15ed3SMichael Chan struct hwrm_func_qcfg_input { 131011f15ed3SMichael Chan __le16 req_type; 131111f15ed3SMichael Chan __le16 cmpl_ring; 131211f15ed3SMichael Chan __le16 seq_id; 131311f15ed3SMichael Chan __le16 target_id; 131411f15ed3SMichael Chan __le64 resp_addr; 131511f15ed3SMichael Chan __le16 fid; 1316894aa69aSMichael Chan u8 unused_0[6]; 131711f15ed3SMichael Chan }; 131811f15ed3SMichael Chan 1319460c2577SMichael Chan /* hwrm_func_qcfg_output (size:768b/96B) */ 132011f15ed3SMichael Chan struct hwrm_func_qcfg_output { 132111f15ed3SMichael Chan __le16 error_code; 132211f15ed3SMichael Chan __le16 req_type; 132311f15ed3SMichael Chan __le16 seq_id; 132411f15ed3SMichael Chan __le16 resp_len; 132511f15ed3SMichael Chan __le16 fid; 132611f15ed3SMichael Chan __le16 port_id; 132711f15ed3SMichael Chan __le16 vlan; 1328a58a3e68SMichael Chan __le16 flags; 1329a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1330a58a3e68SMichael Chan #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1331441cabbbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 133287c374deSMichael Chan #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 13338eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 13348eb992e8SMichael Chan #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 133531d357c0SMichael Chan #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 13363322479eSMichael Chan #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 13372792b5b9SMichael Chan #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1338bfc6e5fbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1339bfc6e5fbSMichael Chan #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 13409d6b648cSMichael Chan #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1341*16db6323SMichael Chan #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 134211f15ed3SMichael Chan u8 mac_address[6]; 134311f15ed3SMichael Chan __le16 pci_id; 134411f15ed3SMichael Chan __le16 alloc_rsscos_ctx; 134511f15ed3SMichael Chan __le16 alloc_cmpl_rings; 134611f15ed3SMichael Chan __le16 alloc_tx_rings; 134711f15ed3SMichael Chan __le16 alloc_rx_rings; 134811f15ed3SMichael Chan __le16 alloc_l2_ctx; 134911f15ed3SMichael Chan __le16 alloc_vnics; 135011f15ed3SMichael Chan __le16 mtu; 135111f15ed3SMichael Chan __le16 mru; 135211f15ed3SMichael Chan __le16 stat_ctx_id; 135311f15ed3SMichael Chan u8 port_partition_type; 1354441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1355441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1356441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1357441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1358441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1359441cabbbSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 1360894aa69aSMichael Chan #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 13618eb992e8SMichael Chan u8 port_pf_cnt; 13628eb992e8SMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 1363894aa69aSMichael Chan #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 136411f15ed3SMichael Chan __le16 dflt_vnic_id; 136557922b0aSMichael Chan __le16 max_mtu_configured; 136611f15ed3SMichael Chan __le32 min_bw; 1367441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1368441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 1369bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 1370bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 1371bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 1372bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 1373441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1374441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 1375bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1376bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1377bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1378bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1379441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1380441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1381441cabbbSMichael Chan #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 138211f15ed3SMichael Chan __le32 max_bw; 1383441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1384441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 1385bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 1386bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 1387bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 1388bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 1389441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1390441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 1391bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1392bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1393bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1394bac9a7e0SMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1395441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1396441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1397441cabbbSMichael Chan #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 139811f15ed3SMichael Chan u8 evb_mode; 1399441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 1400441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 1401441cabbbSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 1402894aa69aSMichael Chan #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 1403d4f52de0SMichael Chan u8 options; 1404d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1405d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 1406d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1407d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1408d4f52de0SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 14096fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 14106fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 14116fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 14126fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 14136fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 14146fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 14156fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 14166fc92c33SMichael Chan #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 1417441cabbbSMichael Chan __le16 alloc_vfs; 141811f15ed3SMichael Chan __le32 alloc_mcast_filters; 141911f15ed3SMichael Chan __le32 alloc_hw_ring_grps; 1420441cabbbSMichael Chan __le16 alloc_sp_tx_rings; 1421894aa69aSMichael Chan __le16 alloc_stat_ctx; 14226fc92c33SMichael Chan __le16 alloc_msix; 14233322479eSMichael Chan __le16 registered_vfs; 142472e0c9f9SMichael Chan __le16 l2_doorbell_bar_size_kb; 142572e0c9f9SMichael Chan u8 unused_1; 14263322479eSMichael Chan u8 always_1; 14273322479eSMichael Chan __le32 reset_addr_poll; 142841136ab3SMichael Chan __le16 legacy_l2_db_size_kb; 1429460c2577SMichael Chan __le16 svif_info; 1430460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 1431460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 1432460c2577SMichael Chan #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 14339d6b648cSMichael Chan u8 mpc_chnls; 14349d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 14359d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 14369d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 14379d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 14389d6b648cSMichael Chan #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 14399d6b648cSMichael Chan u8 unused_2[6]; 144011f15ed3SMichael Chan u8 valid; 144111f15ed3SMichael Chan }; 144211f15ed3SMichael Chan 1443bfc6e5fbSMichael Chan /* hwrm_func_cfg_input (size:768b/96B) */ 1444c0c050c5SMichael Chan struct hwrm_func_cfg_input { 1445c0c050c5SMichael Chan __le16 req_type; 1446c0c050c5SMichael Chan __le16 cmpl_ring; 1447c0c050c5SMichael Chan __le16 seq_id; 1448c0c050c5SMichael Chan __le16 target_id; 1449c0c050c5SMichael Chan __le64 resp_addr; 1450c193554eSMichael Chan __le16 fid; 14516fc92c33SMichael Chan __le16 num_msix; 1452c0c050c5SMichael Chan __le32 flags; 14538eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 14548eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 14558eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 14568eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 14578eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 14588eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 14598eb992e8SMichael Chan #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1460acb20054SMichael Chan #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 14616a17eb27SMichael Chan #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1462894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1463894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1464894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1465894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1466894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1467894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1468894aa69aSMichael Chan #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 146931d357c0SMichael Chan #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 14703322479eSMichael Chan #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 14710b815023SMichael Chan #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 14723293ec23SMichael Chan #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 14732792b5b9SMichael Chan #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 1474bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 1475bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 1476bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 1477c0c050c5SMichael Chan __le32 enables; 1478c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1479c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1480c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1481c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1482c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1483c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1484c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1485c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1486c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1487c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1488c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1489c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1490c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1491c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1492c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1493c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1494c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1495c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1496c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1497c0c050c5SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1498894aa69aSMichael Chan #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 14996fc92c33SMichael Chan #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 15006fc92c33SMichael Chan #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 1501bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 1502bfc6e5fbSMichael Chan #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 15039d6b648cSMichael Chan #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 1504c0c050c5SMichael Chan __le16 mtu; 1505c0c050c5SMichael Chan __le16 mru; 1506c0c050c5SMichael Chan __le16 num_rsscos_ctxs; 1507c0c050c5SMichael Chan __le16 num_cmpl_rings; 1508c0c050c5SMichael Chan __le16 num_tx_rings; 1509c0c050c5SMichael Chan __le16 num_rx_rings; 1510c0c050c5SMichael Chan __le16 num_l2_ctxs; 1511c0c050c5SMichael Chan __le16 num_vnics; 1512c0c050c5SMichael Chan __le16 num_stat_ctxs; 1513c0c050c5SMichael Chan __le16 num_hw_ring_grps; 1514c0c050c5SMichael Chan u8 dflt_mac_addr[6]; 1515c0c050c5SMichael Chan __le16 dflt_vlan; 1516c0c050c5SMichael Chan __be32 dflt_ip_addr[4]; 1517c0c050c5SMichael Chan __le32 min_bw; 1518441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1519441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1520bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1521bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1522bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1523bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1524441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1525441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1526bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1527bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1528bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1529bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1530441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1531441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1532441cabbbSMichael Chan #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1533c0c050c5SMichael Chan __le32 max_bw; 1534441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1535441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1536bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1537bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1538bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1539bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1540441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1541441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1542bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1543bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1544bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1545bac9a7e0SMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1546441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1547441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1548441cabbbSMichael Chan #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1549c0c050c5SMichael Chan __le16 async_event_cr; 1550c0c050c5SMichael Chan u8 vlan_antispoof_mode; 1551441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1552441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1553441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1554441cabbbSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1555894aa69aSMichael Chan #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1556c0c050c5SMichael Chan u8 allowed_vlan_pris; 1557c0c050c5SMichael Chan u8 evb_mode; 1558441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1559441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1560441cabbbSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1561894aa69aSMichael Chan #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1562d4f52de0SMichael Chan u8 options; 1563d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1564d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1565d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1566d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1567d4f52de0SMichael Chan #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 15686fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 15696fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 15706fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 15716fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 15726fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 15736fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 15746fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 15756fc92c33SMichael Chan #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 1576c0c050c5SMichael Chan __le16 num_mcast_filters; 1577bfc6e5fbSMichael Chan __le16 schq_id; 15789d6b648cSMichael Chan __le16 mpc_chnls; 15799d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 15809d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 15819d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 15829d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 15839d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 15849d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 15859d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 15869d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 15879d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 15889d6b648cSMichael Chan #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 15899d6b648cSMichael Chan u8 unused_0[4]; 1590c0c050c5SMichael Chan }; 1591c0c050c5SMichael Chan 1592894aa69aSMichael Chan /* hwrm_func_cfg_output (size:128b/16B) */ 1593c0c050c5SMichael Chan struct hwrm_func_cfg_output { 1594c0c050c5SMichael Chan __le16 error_code; 1595c0c050c5SMichael Chan __le16 req_type; 1596c0c050c5SMichael Chan __le16 seq_id; 1597c0c050c5SMichael Chan __le16 resp_len; 1598894aa69aSMichael Chan u8 unused_0[7]; 1599c0c050c5SMichael Chan u8 valid; 1600c0c050c5SMichael Chan }; 1601c0c050c5SMichael Chan 1602894aa69aSMichael Chan /* hwrm_func_qstats_input (size:192b/24B) */ 1603c0c050c5SMichael Chan struct hwrm_func_qstats_input { 1604c0c050c5SMichael Chan __le16 req_type; 1605c0c050c5SMichael Chan __le16 cmpl_ring; 1606c0c050c5SMichael Chan __le16 seq_id; 1607c0c050c5SMichael Chan __le16 target_id; 1608c0c050c5SMichael Chan __le64 resp_addr; 1609c0c050c5SMichael Chan __le16 fid; 161072e0c9f9SMichael Chan u8 flags; 161172e0c9f9SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_UNUSED 0x0UL 161272e0c9f9SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 1613460c2577SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 1614460c2577SMichael Chan #define FUNC_QSTATS_REQ_FLAGS_LAST FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 161572e0c9f9SMichael Chan u8 unused_0[5]; 1616c0c050c5SMichael Chan }; 1617c0c050c5SMichael Chan 1618894aa69aSMichael Chan /* hwrm_func_qstats_output (size:1408b/176B) */ 1619c0c050c5SMichael Chan struct hwrm_func_qstats_output { 1620c0c050c5SMichael Chan __le16 error_code; 1621c0c050c5SMichael Chan __le16 req_type; 1622c0c050c5SMichael Chan __le16 seq_id; 1623c0c050c5SMichael Chan __le16 resp_len; 1624c0c050c5SMichael Chan __le64 tx_ucast_pkts; 1625c0c050c5SMichael Chan __le64 tx_mcast_pkts; 1626c0c050c5SMichael Chan __le64 tx_bcast_pkts; 16278eb992e8SMichael Chan __le64 tx_discard_pkts; 1628c0c050c5SMichael Chan __le64 tx_drop_pkts; 1629c0c050c5SMichael Chan __le64 tx_ucast_bytes; 1630c0c050c5SMichael Chan __le64 tx_mcast_bytes; 1631c0c050c5SMichael Chan __le64 tx_bcast_bytes; 1632c0c050c5SMichael Chan __le64 rx_ucast_pkts; 1633c0c050c5SMichael Chan __le64 rx_mcast_pkts; 1634c0c050c5SMichael Chan __le64 rx_bcast_pkts; 16358eb992e8SMichael Chan __le64 rx_discard_pkts; 1636c0c050c5SMichael Chan __le64 rx_drop_pkts; 1637c0c050c5SMichael Chan __le64 rx_ucast_bytes; 1638c0c050c5SMichael Chan __le64 rx_mcast_bytes; 1639c0c050c5SMichael Chan __le64 rx_bcast_bytes; 1640c0c050c5SMichael Chan __le64 rx_agg_pkts; 1641c0c050c5SMichael Chan __le64 rx_agg_bytes; 1642c0c050c5SMichael Chan __le64 rx_agg_events; 1643c0c050c5SMichael Chan __le64 rx_agg_aborts; 1644894aa69aSMichael Chan u8 unused_0[7]; 1645c0c050c5SMichael Chan u8 valid; 1646c0c050c5SMichael Chan }; 1647c0c050c5SMichael Chan 1648bfc6e5fbSMichael Chan /* hwrm_func_qstats_ext_input (size:256b/32B) */ 1649460c2577SMichael Chan struct hwrm_func_qstats_ext_input { 1650460c2577SMichael Chan __le16 req_type; 1651460c2577SMichael Chan __le16 cmpl_ring; 1652460c2577SMichael Chan __le16 seq_id; 1653460c2577SMichael Chan __le16 target_id; 1654460c2577SMichael Chan __le64 resp_addr; 1655460c2577SMichael Chan __le16 fid; 1656460c2577SMichael Chan u8 flags; 1657460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 1658460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 1659460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 1660460c2577SMichael Chan #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 1661bfc6e5fbSMichael Chan u8 unused_0[1]; 1662bfc6e5fbSMichael Chan __le32 enables; 1663bfc6e5fbSMichael Chan #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 1664bfc6e5fbSMichael Chan __le16 schq_id; 1665bfc6e5fbSMichael Chan __le16 traffic_class; 1666bfc6e5fbSMichael Chan u8 unused_1[4]; 1667460c2577SMichael Chan }; 1668460c2577SMichael Chan 16699d6b648cSMichael Chan /* hwrm_func_qstats_ext_output (size:1536b/192B) */ 1670460c2577SMichael Chan struct hwrm_func_qstats_ext_output { 1671460c2577SMichael Chan __le16 error_code; 1672460c2577SMichael Chan __le16 req_type; 1673460c2577SMichael Chan __le16 seq_id; 1674460c2577SMichael Chan __le16 resp_len; 1675460c2577SMichael Chan __le64 rx_ucast_pkts; 1676460c2577SMichael Chan __le64 rx_mcast_pkts; 1677460c2577SMichael Chan __le64 rx_bcast_pkts; 1678460c2577SMichael Chan __le64 rx_discard_pkts; 1679bfc6e5fbSMichael Chan __le64 rx_error_pkts; 1680460c2577SMichael Chan __le64 rx_ucast_bytes; 1681460c2577SMichael Chan __le64 rx_mcast_bytes; 1682460c2577SMichael Chan __le64 rx_bcast_bytes; 1683460c2577SMichael Chan __le64 tx_ucast_pkts; 1684460c2577SMichael Chan __le64 tx_mcast_pkts; 1685460c2577SMichael Chan __le64 tx_bcast_pkts; 1686bfc6e5fbSMichael Chan __le64 tx_error_pkts; 1687460c2577SMichael Chan __le64 tx_discard_pkts; 1688460c2577SMichael Chan __le64 tx_ucast_bytes; 1689460c2577SMichael Chan __le64 tx_mcast_bytes; 1690460c2577SMichael Chan __le64 tx_bcast_bytes; 1691460c2577SMichael Chan __le64 rx_tpa_eligible_pkt; 1692460c2577SMichael Chan __le64 rx_tpa_eligible_bytes; 1693460c2577SMichael Chan __le64 rx_tpa_pkt; 1694460c2577SMichael Chan __le64 rx_tpa_bytes; 1695460c2577SMichael Chan __le64 rx_tpa_errors; 16969d6b648cSMichael Chan __le64 rx_tpa_events; 1697460c2577SMichael Chan u8 unused_0[7]; 1698460c2577SMichael Chan u8 valid; 1699460c2577SMichael Chan }; 1700460c2577SMichael Chan 1701894aa69aSMichael Chan /* hwrm_func_clr_stats_input (size:192b/24B) */ 1702c0c050c5SMichael Chan struct hwrm_func_clr_stats_input { 1703c0c050c5SMichael Chan __le16 req_type; 1704c0c050c5SMichael Chan __le16 cmpl_ring; 1705c0c050c5SMichael Chan __le16 seq_id; 1706c0c050c5SMichael Chan __le16 target_id; 1707c0c050c5SMichael Chan __le64 resp_addr; 1708c0c050c5SMichael Chan __le16 fid; 1709894aa69aSMichael Chan u8 unused_0[6]; 1710c0c050c5SMichael Chan }; 1711c0c050c5SMichael Chan 1712894aa69aSMichael Chan /* hwrm_func_clr_stats_output (size:128b/16B) */ 1713c0c050c5SMichael Chan struct hwrm_func_clr_stats_output { 1714c0c050c5SMichael Chan __le16 error_code; 1715c0c050c5SMichael Chan __le16 req_type; 1716c0c050c5SMichael Chan __le16 seq_id; 1717c0c050c5SMichael Chan __le16 resp_len; 1718894aa69aSMichael Chan u8 unused_0[7]; 1719c0c050c5SMichael Chan u8 valid; 1720c0c050c5SMichael Chan }; 1721c0c050c5SMichael Chan 1722894aa69aSMichael Chan /* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1723c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_input { 1724c0c050c5SMichael Chan __le16 req_type; 1725c0c050c5SMichael Chan __le16 cmpl_ring; 1726c0c050c5SMichael Chan __le16 seq_id; 1727c0c050c5SMichael Chan __le16 target_id; 1728c0c050c5SMichael Chan __le64 resp_addr; 1729c0c050c5SMichael Chan __le16 vf_id; 1730894aa69aSMichael Chan u8 unused_0[6]; 1731c0c050c5SMichael Chan }; 1732c0c050c5SMichael Chan 1733894aa69aSMichael Chan /* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1734c0c050c5SMichael Chan struct hwrm_func_vf_resc_free_output { 1735c0c050c5SMichael Chan __le16 error_code; 1736c0c050c5SMichael Chan __le16 req_type; 1737c0c050c5SMichael Chan __le16 seq_id; 1738c0c050c5SMichael Chan __le16 resp_len; 1739894aa69aSMichael Chan u8 unused_0[7]; 1740c0c050c5SMichael Chan u8 valid; 1741c0c050c5SMichael Chan }; 1742c0c050c5SMichael Chan 1743d4f52de0SMichael Chan /* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1744c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_input { 1745c0c050c5SMichael Chan __le16 req_type; 1746c0c050c5SMichael Chan __le16 cmpl_ring; 1747c0c050c5SMichael Chan __le16 seq_id; 1748c0c050c5SMichael Chan __le16 target_id; 1749c0c050c5SMichael Chan __le64 resp_addr; 1750c0c050c5SMichael Chan __le32 flags; 1751c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1752c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1753d4f52de0SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 175431d357c0SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 17553322479eSMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 17563293ec23SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 175741136ab3SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1758*16db6323SMichael Chan #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 1759c0c050c5SMichael Chan __le32 enables; 1760c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1761c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1762c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1763c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1764c0c050c5SMichael Chan #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1765c0c050c5SMichael Chan __le16 os_type; 1766441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1767441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1768441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1769441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1770441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1771441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1772441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1773441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1774441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1775441cabbbSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 177616d663a6SMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1777894aa69aSMichael Chan #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1778d4f52de0SMichael Chan u8 ver_maj_8b; 1779d4f52de0SMichael Chan u8 ver_min_8b; 1780d4f52de0SMichael Chan u8 ver_upd_8b; 1781894aa69aSMichael Chan u8 unused_0[3]; 1782c0c050c5SMichael Chan __le32 timestamp; 1783894aa69aSMichael Chan u8 unused_1[4]; 1784c0c050c5SMichael Chan __le32 vf_req_fwd[8]; 1785c0c050c5SMichael Chan __le32 async_event_fwd[8]; 1786d4f52de0SMichael Chan __le16 ver_maj; 1787d4f52de0SMichael Chan __le16 ver_min; 1788d4f52de0SMichael Chan __le16 ver_upd; 1789d4f52de0SMichael Chan __le16 ver_patch; 1790c0c050c5SMichael Chan }; 1791c0c050c5SMichael Chan 1792894aa69aSMichael Chan /* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1793c0c050c5SMichael Chan struct hwrm_func_drv_rgtr_output { 1794c0c050c5SMichael Chan __le16 error_code; 1795c0c050c5SMichael Chan __le16 req_type; 1796c0c050c5SMichael Chan __le16 seq_id; 1797c0c050c5SMichael Chan __le16 resp_len; 17986fc92c33SMichael Chan __le32 flags; 17996fc92c33SMichael Chan #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 18006fc92c33SMichael Chan u8 unused_0[3]; 1801c0c050c5SMichael Chan u8 valid; 1802c0c050c5SMichael Chan }; 1803c0c050c5SMichael Chan 1804894aa69aSMichael Chan /* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1805c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_input { 1806c0c050c5SMichael Chan __le16 req_type; 1807c0c050c5SMichael Chan __le16 cmpl_ring; 1808c0c050c5SMichael Chan __le16 seq_id; 1809c0c050c5SMichael Chan __le16 target_id; 1810c0c050c5SMichael Chan __le64 resp_addr; 1811c0c050c5SMichael Chan __le32 flags; 1812c0c050c5SMichael Chan #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1813894aa69aSMichael Chan u8 unused_0[4]; 1814c0c050c5SMichael Chan }; 1815c0c050c5SMichael Chan 1816894aa69aSMichael Chan /* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1817c0c050c5SMichael Chan struct hwrm_func_drv_unrgtr_output { 1818c0c050c5SMichael Chan __le16 error_code; 1819c0c050c5SMichael Chan __le16 req_type; 1820c0c050c5SMichael Chan __le16 seq_id; 1821c0c050c5SMichael Chan __le16 resp_len; 1822894aa69aSMichael Chan u8 unused_0[7]; 1823c0c050c5SMichael Chan u8 valid; 1824c0c050c5SMichael Chan }; 1825c0c050c5SMichael Chan 1826894aa69aSMichael Chan /* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1827c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_input { 1828c0c050c5SMichael Chan __le16 req_type; 1829c0c050c5SMichael Chan __le16 cmpl_ring; 1830c0c050c5SMichael Chan __le16 seq_id; 1831c0c050c5SMichael Chan __le16 target_id; 1832c0c050c5SMichael Chan __le64 resp_addr; 1833c0c050c5SMichael Chan __le32 enables; 1834c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1835c0c050c5SMichael Chan #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1836c0c050c5SMichael Chan __le16 vf_id; 1837c0c050c5SMichael Chan __le16 req_buf_num_pages; 1838c0c050c5SMichael Chan __le16 req_buf_page_size; 1839441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1840441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1841441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1842441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1843441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1844441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1845441cabbbSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1846894aa69aSMichael Chan #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1847c0c050c5SMichael Chan __le16 req_buf_len; 1848c0c050c5SMichael Chan __le16 resp_buf_len; 1849894aa69aSMichael Chan u8 unused_0[2]; 1850c0c050c5SMichael Chan __le64 req_buf_page_addr0; 1851c0c050c5SMichael Chan __le64 req_buf_page_addr1; 1852c0c050c5SMichael Chan __le64 req_buf_page_addr2; 1853c0c050c5SMichael Chan __le64 req_buf_page_addr3; 1854c0c050c5SMichael Chan __le64 req_buf_page_addr4; 1855c0c050c5SMichael Chan __le64 req_buf_page_addr5; 1856c0c050c5SMichael Chan __le64 req_buf_page_addr6; 1857c0c050c5SMichael Chan __le64 req_buf_page_addr7; 1858c0c050c5SMichael Chan __le64 req_buf_page_addr8; 1859c0c050c5SMichael Chan __le64 req_buf_page_addr9; 1860c0c050c5SMichael Chan __le64 error_buf_addr; 1861c0c050c5SMichael Chan __le64 resp_buf_addr; 1862c0c050c5SMichael Chan }; 1863c0c050c5SMichael Chan 1864894aa69aSMichael Chan /* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1865c0c050c5SMichael Chan struct hwrm_func_buf_rgtr_output { 1866c0c050c5SMichael Chan __le16 error_code; 1867c0c050c5SMichael Chan __le16 req_type; 1868c0c050c5SMichael Chan __le16 seq_id; 1869c0c050c5SMichael Chan __le16 resp_len; 1870894aa69aSMichael Chan u8 unused_0[7]; 1871c0c050c5SMichael Chan u8 valid; 1872c0c050c5SMichael Chan }; 1873c0c050c5SMichael Chan 1874894aa69aSMichael Chan /* hwrm_func_drv_qver_input (size:192b/24B) */ 1875c0c050c5SMichael Chan struct hwrm_func_drv_qver_input { 1876c0c050c5SMichael Chan __le16 req_type; 1877c0c050c5SMichael Chan __le16 cmpl_ring; 1878c0c050c5SMichael Chan __le16 seq_id; 1879c0c050c5SMichael Chan __le16 target_id; 1880c0c050c5SMichael Chan __le64 resp_addr; 1881c193554eSMichael Chan __le32 reserved; 1882c0c050c5SMichael Chan __le16 fid; 1883894aa69aSMichael Chan u8 unused_0[2]; 1884c0c050c5SMichael Chan }; 1885c0c050c5SMichael Chan 18866fc92c33SMichael Chan /* hwrm_func_drv_qver_output (size:256b/32B) */ 1887c0c050c5SMichael Chan struct hwrm_func_drv_qver_output { 1888c0c050c5SMichael Chan __le16 error_code; 1889c0c050c5SMichael Chan __le16 req_type; 1890c0c050c5SMichael Chan __le16 seq_id; 1891c0c050c5SMichael Chan __le16 resp_len; 1892c0c050c5SMichael Chan __le16 os_type; 1893441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1894441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1895441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1896441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1897441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1898441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1899441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1900441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1901441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1902441cabbbSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 190387c374deSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1904894aa69aSMichael Chan #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1905d4f52de0SMichael Chan u8 ver_maj_8b; 1906d4f52de0SMichael Chan u8 ver_min_8b; 1907d4f52de0SMichael Chan u8 ver_upd_8b; 19086fc92c33SMichael Chan u8 unused_0[3]; 1909d4f52de0SMichael Chan __le16 ver_maj; 1910d4f52de0SMichael Chan __le16 ver_min; 1911d4f52de0SMichael Chan __le16 ver_upd; 1912d4f52de0SMichael Chan __le16 ver_patch; 19136fc92c33SMichael Chan u8 unused_1[7]; 19146fc92c33SMichael Chan u8 valid; 1915c0c050c5SMichael Chan }; 1916c0c050c5SMichael Chan 1917894aa69aSMichael Chan /* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1918894aa69aSMichael Chan struct hwrm_func_resource_qcaps_input { 1919894aa69aSMichael Chan __le16 req_type; 1920894aa69aSMichael Chan __le16 cmpl_ring; 1921894aa69aSMichael Chan __le16 seq_id; 1922894aa69aSMichael Chan __le16 target_id; 1923894aa69aSMichael Chan __le64 resp_addr; 1924894aa69aSMichael Chan __le16 fid; 1925894aa69aSMichael Chan u8 unused_0[6]; 1926894aa69aSMichael Chan }; 1927894aa69aSMichael Chan 1928d4f52de0SMichael Chan /* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1929894aa69aSMichael Chan struct hwrm_func_resource_qcaps_output { 1930894aa69aSMichael Chan __le16 error_code; 1931894aa69aSMichael Chan __le16 req_type; 1932894aa69aSMichael Chan __le16 seq_id; 1933894aa69aSMichael Chan __le16 resp_len; 1934894aa69aSMichael Chan __le16 max_vfs; 1935894aa69aSMichael Chan __le16 max_msix; 1936894aa69aSMichael Chan __le16 vf_reservation_strategy; 1937894aa69aSMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1938894aa69aSMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1939d4f52de0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1940d4f52de0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1941894aa69aSMichael Chan __le16 min_rsscos_ctx; 1942894aa69aSMichael Chan __le16 max_rsscos_ctx; 1943894aa69aSMichael Chan __le16 min_cmpl_rings; 1944894aa69aSMichael Chan __le16 max_cmpl_rings; 1945894aa69aSMichael Chan __le16 min_tx_rings; 1946894aa69aSMichael Chan __le16 max_tx_rings; 1947894aa69aSMichael Chan __le16 min_rx_rings; 1948894aa69aSMichael Chan __le16 max_rx_rings; 1949894aa69aSMichael Chan __le16 min_l2_ctxs; 1950894aa69aSMichael Chan __le16 max_l2_ctxs; 1951894aa69aSMichael Chan __le16 min_vnics; 1952894aa69aSMichael Chan __le16 max_vnics; 1953894aa69aSMichael Chan __le16 min_stat_ctx; 1954894aa69aSMichael Chan __le16 max_stat_ctx; 1955894aa69aSMichael Chan __le16 min_hw_ring_grps; 1956894aa69aSMichael Chan __le16 max_hw_ring_grps; 1957d4f52de0SMichael Chan __le16 max_tx_scheduler_inputs; 195831d357c0SMichael Chan __le16 flags; 195931d357c0SMichael Chan #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 196031d357c0SMichael Chan u8 unused_0[5]; 1961894aa69aSMichael Chan u8 valid; 1962894aa69aSMichael Chan }; 1963894aa69aSMichael Chan 1964894aa69aSMichael Chan /* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1965894aa69aSMichael Chan struct hwrm_func_vf_resource_cfg_input { 1966894aa69aSMichael Chan __le16 req_type; 1967894aa69aSMichael Chan __le16 cmpl_ring; 1968894aa69aSMichael Chan __le16 seq_id; 1969894aa69aSMichael Chan __le16 target_id; 1970894aa69aSMichael Chan __le64 resp_addr; 1971894aa69aSMichael Chan __le16 vf_id; 1972894aa69aSMichael Chan __le16 max_msix; 1973894aa69aSMichael Chan __le16 min_rsscos_ctx; 1974894aa69aSMichael Chan __le16 max_rsscos_ctx; 1975894aa69aSMichael Chan __le16 min_cmpl_rings; 1976894aa69aSMichael Chan __le16 max_cmpl_rings; 1977894aa69aSMichael Chan __le16 min_tx_rings; 1978894aa69aSMichael Chan __le16 max_tx_rings; 1979894aa69aSMichael Chan __le16 min_rx_rings; 1980894aa69aSMichael Chan __le16 max_rx_rings; 1981894aa69aSMichael Chan __le16 min_l2_ctxs; 1982894aa69aSMichael Chan __le16 max_l2_ctxs; 1983894aa69aSMichael Chan __le16 min_vnics; 1984894aa69aSMichael Chan __le16 max_vnics; 1985894aa69aSMichael Chan __le16 min_stat_ctx; 1986894aa69aSMichael Chan __le16 max_stat_ctx; 1987894aa69aSMichael Chan __le16 min_hw_ring_grps; 1988894aa69aSMichael Chan __le16 max_hw_ring_grps; 198931d357c0SMichael Chan __le16 flags; 199031d357c0SMichael Chan #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 199131d357c0SMichael Chan u8 unused_0[2]; 1992894aa69aSMichael Chan }; 1993894aa69aSMichael Chan 1994894aa69aSMichael Chan /* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1995894aa69aSMichael Chan struct hwrm_func_vf_resource_cfg_output { 1996894aa69aSMichael Chan __le16 error_code; 1997894aa69aSMichael Chan __le16 req_type; 1998894aa69aSMichael Chan __le16 seq_id; 1999894aa69aSMichael Chan __le16 resp_len; 2000894aa69aSMichael Chan __le16 reserved_rsscos_ctx; 2001894aa69aSMichael Chan __le16 reserved_cmpl_rings; 2002894aa69aSMichael Chan __le16 reserved_tx_rings; 2003894aa69aSMichael Chan __le16 reserved_rx_rings; 2004894aa69aSMichael Chan __le16 reserved_l2_ctxs; 2005894aa69aSMichael Chan __le16 reserved_vnics; 2006894aa69aSMichael Chan __le16 reserved_stat_ctx; 2007894aa69aSMichael Chan __le16 reserved_hw_ring_grps; 2008894aa69aSMichael Chan u8 unused_0[7]; 2009894aa69aSMichael Chan u8 valid; 2010894aa69aSMichael Chan }; 2011894aa69aSMichael Chan 20126fc92c33SMichael Chan /* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 20136fc92c33SMichael Chan struct hwrm_func_backing_store_qcaps_input { 20146fc92c33SMichael Chan __le16 req_type; 20156fc92c33SMichael Chan __le16 cmpl_ring; 20166fc92c33SMichael Chan __le16 seq_id; 20176fc92c33SMichael Chan __le16 target_id; 20186fc92c33SMichael Chan __le64 resp_addr; 20196fc92c33SMichael Chan }; 20206fc92c33SMichael Chan 2021*16db6323SMichael Chan /* hwrm_func_backing_store_qcaps_output (size:704b/88B) */ 20226fc92c33SMichael Chan struct hwrm_func_backing_store_qcaps_output { 20236fc92c33SMichael Chan __le16 error_code; 20246fc92c33SMichael Chan __le16 req_type; 20256fc92c33SMichael Chan __le16 seq_id; 20266fc92c33SMichael Chan __le16 resp_len; 20276fc92c33SMichael Chan __le32 qp_max_entries; 20286fc92c33SMichael Chan __le16 qp_min_qp1_entries; 20296fc92c33SMichael Chan __le16 qp_max_l2_entries; 20306fc92c33SMichael Chan __le16 qp_entry_size; 20316fc92c33SMichael Chan __le16 srq_max_l2_entries; 20326fc92c33SMichael Chan __le32 srq_max_entries; 20336fc92c33SMichael Chan __le16 srq_entry_size; 20346fc92c33SMichael Chan __le16 cq_max_l2_entries; 20356fc92c33SMichael Chan __le32 cq_max_entries; 20366fc92c33SMichael Chan __le16 cq_entry_size; 20376fc92c33SMichael Chan __le16 vnic_max_vnic_entries; 20386fc92c33SMichael Chan __le16 vnic_max_ring_table_entries; 20396fc92c33SMichael Chan __le16 vnic_entry_size; 20406fc92c33SMichael Chan __le32 stat_max_entries; 20416fc92c33SMichael Chan __le16 stat_entry_size; 20426fc92c33SMichael Chan __le16 tqm_entry_size; 20436fc92c33SMichael Chan __le32 tqm_min_entries_per_ring; 20446fc92c33SMichael Chan __le32 tqm_max_entries_per_ring; 20456fc92c33SMichael Chan __le32 mrav_max_entries; 20466fc92c33SMichael Chan __le16 mrav_entry_size; 20476fc92c33SMichael Chan __le16 tim_entry_size; 20486fc92c33SMichael Chan __le32 tim_max_entries; 20494a50ddc2SMichael Chan __le16 mrav_num_entries_units; 205031d357c0SMichael Chan u8 tqm_entries_multiple; 205141136ab3SMichael Chan u8 ctx_kind_initializer; 2052*16db6323SMichael Chan __le16 ctx_init_mask; 2053*16db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2054*16db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2055*16db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2056*16db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2057*16db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2058*16db6323SMichael Chan #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2059*16db6323SMichael Chan u8 qp_init_offset; 2060*16db6323SMichael Chan u8 srq_init_offset; 2061*16db6323SMichael Chan u8 cq_init_offset; 2062*16db6323SMichael Chan u8 vnic_init_offset; 2063460c2577SMichael Chan u8 tqm_fp_rings_count; 2064*16db6323SMichael Chan u8 stat_init_offset; 2065*16db6323SMichael Chan u8 mrav_init_offset; 2066*16db6323SMichael Chan u8 rsvd[6]; 20676fc92c33SMichael Chan u8 valid; 20686fc92c33SMichael Chan }; 20696fc92c33SMichael Chan 2070*16db6323SMichael Chan /* hwrm_func_backing_store_cfg_input (size:2432b/304B) */ 20716fc92c33SMichael Chan struct hwrm_func_backing_store_cfg_input { 20726fc92c33SMichael Chan __le16 req_type; 20736fc92c33SMichael Chan __le16 cmpl_ring; 20746fc92c33SMichael Chan __le16 seq_id; 20756fc92c33SMichael Chan __le16 target_id; 20766fc92c33SMichael Chan __le64 resp_addr; 20776fc92c33SMichael Chan __le32 flags; 20786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 20794a50ddc2SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 20806fc92c33SMichael Chan __le32 enables; 20816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 20826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 20836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 20846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 20856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 20866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 20876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 20886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 20896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 20906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 20916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 20926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 20936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 20946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 20956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 20966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2097*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2098*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2099*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 21006fc92c33SMichael Chan u8 qpc_pg_size_qpc_lvl; 21016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 21026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 21036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 21046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 21056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 21066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 21076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 21086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 21096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 21106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 21116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 21126fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 21136fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 21146fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 21156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 21166fc92c33SMichael Chan u8 srq_pg_size_srq_lvl; 21176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 21186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 21196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 21206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 21216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 21226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 21236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 21246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 21256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 21266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 21276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 21286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 21296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 21306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 21316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 21326fc92c33SMichael Chan u8 cq_pg_size_cq_lvl; 21336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 21346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 21356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 21366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 21376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 21386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 21396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 21406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 21416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 21426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 21436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 21446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 21456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 21466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 21476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 21486fc92c33SMichael Chan u8 vnic_pg_size_vnic_lvl; 21496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 21506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 21516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 21526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 21536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 21546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 21556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 21566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 21576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 21586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 21596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 21606fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 21616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 21626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 21636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 21646fc92c33SMichael Chan u8 stat_pg_size_stat_lvl; 21656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 21666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 21676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 21686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 21696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 21706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 21716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 21726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 21736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 21746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 21756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 21766fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 21776fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 21786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 21796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 21806fc92c33SMichael Chan u8 tqm_sp_pg_size_tqm_sp_lvl; 21816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 21826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 21836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 21846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 21856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 21866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 21876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 21886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 21896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 21906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 21916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 21926fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 21936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 21946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 21956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 21966fc92c33SMichael Chan u8 tqm_ring0_pg_size_tqm_ring0_lvl; 21976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 21986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 21996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 22006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 22016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 22026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 22036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 22046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 22056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 22066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 22076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 22086fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 22096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 22106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 22116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 22126fc92c33SMichael Chan u8 tqm_ring1_pg_size_tqm_ring1_lvl; 22136fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 22146fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 22156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 22166fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 22176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 22186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 22196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 22206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 22216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 22226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 22236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 22246fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 22256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 22266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 22276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 22286fc92c33SMichael Chan u8 tqm_ring2_pg_size_tqm_ring2_lvl; 22296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 22306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 22316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 22326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 22336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 22346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 22356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 22366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 22376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 22386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 22396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 22406fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 22416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 22426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 22436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 22446fc92c33SMichael Chan u8 tqm_ring3_pg_size_tqm_ring3_lvl; 22456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 22466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 22476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 22486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 22496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 22506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 22516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 22526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 22536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 22546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 22556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 22566fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 22576fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 22586fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 22596fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 22606fc92c33SMichael Chan u8 tqm_ring4_pg_size_tqm_ring4_lvl; 22616fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 22626fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 22636fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 22646fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 22656fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 22666fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 22676fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 22686fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 22696fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 22706fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 22716fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 22726fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 22736fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 22746fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 22756fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 22766fc92c33SMichael Chan u8 tqm_ring5_pg_size_tqm_ring5_lvl; 22776fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 22786fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 22796fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 22806fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 22816fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 22826fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 22836fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 22846fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 22856fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 22866fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 22876fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 22886fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 22896fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 22906fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 22916fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 22926fc92c33SMichael Chan u8 tqm_ring6_pg_size_tqm_ring6_lvl; 22936fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 22946fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 22956fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 22966fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 22976fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 22986fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 22996fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 23006fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 23016fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 23026fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 23036fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 23046fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 23056fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 23066fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 23076fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 23086fc92c33SMichael Chan u8 tqm_ring7_pg_size_tqm_ring7_lvl; 23096fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 23106fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 23116fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 23126fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 23136fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 23146fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 23156fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 23166fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 23176fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 23186fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 23196fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 23206fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 23216fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 23226fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 23236fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 23246fc92c33SMichael Chan u8 mrav_pg_size_mrav_lvl; 23256fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 23266fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 23276fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 23286fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 23296fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 23306fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 23316fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 23326fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 23336fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 23346fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 23356fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 23366fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 23376fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 23386fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 23396fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 23406fc92c33SMichael Chan u8 tim_pg_size_tim_lvl; 23416fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 23426fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 23436fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 23446fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 23456fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 23466fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 23476fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 23486fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 23496fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 23506fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 23516fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 23526fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 23536fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 23546fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 23556fc92c33SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 23566fc92c33SMichael Chan __le64 qpc_page_dir; 23576fc92c33SMichael Chan __le64 srq_page_dir; 23586fc92c33SMichael Chan __le64 cq_page_dir; 23596fc92c33SMichael Chan __le64 vnic_page_dir; 23606fc92c33SMichael Chan __le64 stat_page_dir; 23616fc92c33SMichael Chan __le64 tqm_sp_page_dir; 23626fc92c33SMichael Chan __le64 tqm_ring0_page_dir; 23636fc92c33SMichael Chan __le64 tqm_ring1_page_dir; 23646fc92c33SMichael Chan __le64 tqm_ring2_page_dir; 23656fc92c33SMichael Chan __le64 tqm_ring3_page_dir; 23666fc92c33SMichael Chan __le64 tqm_ring4_page_dir; 23676fc92c33SMichael Chan __le64 tqm_ring5_page_dir; 23686fc92c33SMichael Chan __le64 tqm_ring6_page_dir; 23696fc92c33SMichael Chan __le64 tqm_ring7_page_dir; 23706fc92c33SMichael Chan __le64 mrav_page_dir; 23716fc92c33SMichael Chan __le64 tim_page_dir; 23726fc92c33SMichael Chan __le32 qp_num_entries; 23736fc92c33SMichael Chan __le32 srq_num_entries; 23746fc92c33SMichael Chan __le32 cq_num_entries; 23756fc92c33SMichael Chan __le32 stat_num_entries; 23766fc92c33SMichael Chan __le32 tqm_sp_num_entries; 23776fc92c33SMichael Chan __le32 tqm_ring0_num_entries; 23786fc92c33SMichael Chan __le32 tqm_ring1_num_entries; 23796fc92c33SMichael Chan __le32 tqm_ring2_num_entries; 23806fc92c33SMichael Chan __le32 tqm_ring3_num_entries; 23816fc92c33SMichael Chan __le32 tqm_ring4_num_entries; 23826fc92c33SMichael Chan __le32 tqm_ring5_num_entries; 23836fc92c33SMichael Chan __le32 tqm_ring6_num_entries; 23846fc92c33SMichael Chan __le32 tqm_ring7_num_entries; 23856fc92c33SMichael Chan __le32 mrav_num_entries; 23866fc92c33SMichael Chan __le32 tim_num_entries; 23876fc92c33SMichael Chan __le16 qp_num_qp1_entries; 23886fc92c33SMichael Chan __le16 qp_num_l2_entries; 23896fc92c33SMichael Chan __le16 qp_entry_size; 23906fc92c33SMichael Chan __le16 srq_num_l2_entries; 23916fc92c33SMichael Chan __le16 srq_entry_size; 23926fc92c33SMichael Chan __le16 cq_num_l2_entries; 23936fc92c33SMichael Chan __le16 cq_entry_size; 23946fc92c33SMichael Chan __le16 vnic_num_vnic_entries; 23956fc92c33SMichael Chan __le16 vnic_num_ring_table_entries; 23966fc92c33SMichael Chan __le16 vnic_entry_size; 23976fc92c33SMichael Chan __le16 stat_entry_size; 23986fc92c33SMichael Chan __le16 tqm_entry_size; 23996fc92c33SMichael Chan __le16 mrav_entry_size; 24006fc92c33SMichael Chan __le16 tim_entry_size; 2401*16db6323SMichael Chan u8 tqm_ring8_pg_size_tqm_ring_lvl; 2402*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2403*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2404*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2405*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2406*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2407*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2408*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2409*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2410*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2411*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2412*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2413*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2414*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2415*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2416*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2417*16db6323SMichael Chan u8 ring8_unused[3]; 2418*16db6323SMichael Chan __le32 tqm_ring8_num_entries; 2419*16db6323SMichael Chan __le64 tqm_ring8_page_dir; 2420*16db6323SMichael Chan u8 tqm_ring9_pg_size_tqm_ring_lvl; 2421*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2422*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2423*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2424*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2425*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2426*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2427*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2428*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2429*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2430*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2431*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2432*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2433*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2434*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2435*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2436*16db6323SMichael Chan u8 ring9_unused[3]; 2437*16db6323SMichael Chan __le32 tqm_ring9_num_entries; 2438*16db6323SMichael Chan __le64 tqm_ring9_page_dir; 2439*16db6323SMichael Chan u8 tqm_ring10_pg_size_tqm_ring_lvl; 2440*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2441*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2442*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2443*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2444*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2445*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2446*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2447*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2448*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2449*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2450*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2451*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2452*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2453*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2454*16db6323SMichael Chan #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2455*16db6323SMichael Chan u8 ring10_unused[3]; 2456*16db6323SMichael Chan __le32 tqm_ring10_num_entries; 2457*16db6323SMichael Chan __le64 tqm_ring10_page_dir; 24586fc92c33SMichael Chan }; 24596fc92c33SMichael Chan 24606fc92c33SMichael Chan /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 24616fc92c33SMichael Chan struct hwrm_func_backing_store_cfg_output { 24626fc92c33SMichael Chan __le16 error_code; 24636fc92c33SMichael Chan __le16 req_type; 24646fc92c33SMichael Chan __le16 seq_id; 24656fc92c33SMichael Chan __le16 resp_len; 24666fc92c33SMichael Chan u8 unused_0[7]; 24676fc92c33SMichael Chan u8 valid; 24686fc92c33SMichael Chan }; 24696fc92c33SMichael Chan 24703293ec23SMichael Chan /* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 24713293ec23SMichael Chan struct hwrm_error_recovery_qcfg_input { 24723293ec23SMichael Chan __le16 req_type; 24733293ec23SMichael Chan __le16 cmpl_ring; 24743293ec23SMichael Chan __le16 seq_id; 24753293ec23SMichael Chan __le16 target_id; 24763293ec23SMichael Chan __le64 resp_addr; 24773293ec23SMichael Chan u8 unused_0[8]; 24783293ec23SMichael Chan }; 24793293ec23SMichael Chan 24803293ec23SMichael Chan /* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 24813293ec23SMichael Chan struct hwrm_error_recovery_qcfg_output { 24823293ec23SMichael Chan __le16 error_code; 24833293ec23SMichael Chan __le16 req_type; 24843293ec23SMichael Chan __le16 seq_id; 24853293ec23SMichael Chan __le16 resp_len; 24863293ec23SMichael Chan __le32 flags; 24873293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 24883293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 24893293ec23SMichael Chan __le32 driver_polling_freq; 24903293ec23SMichael Chan __le32 master_func_wait_period; 24913293ec23SMichael Chan __le32 normal_func_wait_period; 24923293ec23SMichael Chan __le32 master_func_wait_period_after_reset; 24933293ec23SMichael Chan __le32 max_bailout_time_after_reset; 24943293ec23SMichael Chan __le32 fw_health_status_reg; 24953293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 24963293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 24973293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 24983293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 24993293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 25003293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 25013293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 25023293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 25033293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 25043293ec23SMichael Chan __le32 fw_heartbeat_reg; 25053293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 25063293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 25073293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 25083293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 25093293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 25103293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 25113293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 25123293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 25133293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 25143293ec23SMichael Chan __le32 fw_reset_cnt_reg; 25153293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 25163293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 25173293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 25183293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 25193293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 25203293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 25213293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 25223293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 25233293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 25243293ec23SMichael Chan __le32 reset_inprogress_reg; 25253293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 25263293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 25273293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 25283293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 25293293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 25303293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 25313293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 25323293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 25333293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 25343293ec23SMichael Chan __le32 reset_inprogress_reg_mask; 25353293ec23SMichael Chan u8 unused_0[3]; 25363293ec23SMichael Chan u8 reg_array_cnt; 25373293ec23SMichael Chan __le32 reset_reg[16]; 25383293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 25393293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 25403293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 25413293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 25423293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 25433293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 25443293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 25453293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 25463293ec23SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 25473293ec23SMichael Chan __le32 reset_reg_val[16]; 25483293ec23SMichael Chan u8 delay_after_reset[16]; 2549460c2577SMichael Chan __le32 err_recovery_cnt_reg; 2550460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 2551460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 2552460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 2553460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 2554460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 2555460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 2556460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 2557460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 2558460c2577SMichael Chan #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 2559460c2577SMichael Chan u8 unused_1[3]; 25603293ec23SMichael Chan u8 valid; 25613293ec23SMichael Chan }; 25623293ec23SMichael Chan 25636fc92c33SMichael Chan /* hwrm_func_drv_if_change_input (size:192b/24B) */ 25646fc92c33SMichael Chan struct hwrm_func_drv_if_change_input { 25656fc92c33SMichael Chan __le16 req_type; 25666fc92c33SMichael Chan __le16 cmpl_ring; 25676fc92c33SMichael Chan __le16 seq_id; 25686fc92c33SMichael Chan __le16 target_id; 25696fc92c33SMichael Chan __le64 resp_addr; 25706fc92c33SMichael Chan __le32 flags; 25716fc92c33SMichael Chan #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 25726fc92c33SMichael Chan __le32 unused; 25736fc92c33SMichael Chan }; 25746fc92c33SMichael Chan 25756fc92c33SMichael Chan /* hwrm_func_drv_if_change_output (size:128b/16B) */ 25766fc92c33SMichael Chan struct hwrm_func_drv_if_change_output { 25776fc92c33SMichael Chan __le16 error_code; 25786fc92c33SMichael Chan __le16 req_type; 25796fc92c33SMichael Chan __le16 seq_id; 25806fc92c33SMichael Chan __le16 resp_len; 25816fc92c33SMichael Chan __le32 flags; 25826fc92c33SMichael Chan #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 25833322479eSMichael Chan #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 25846fc92c33SMichael Chan u8 unused_0[3]; 25856fc92c33SMichael Chan u8 valid; 25866fc92c33SMichael Chan }; 25876fc92c33SMichael Chan 2588894aa69aSMichael Chan /* hwrm_port_phy_cfg_input (size:448b/56B) */ 2589c0c050c5SMichael Chan struct hwrm_port_phy_cfg_input { 2590c0c050c5SMichael Chan __le16 req_type; 2591c0c050c5SMichael Chan __le16 cmpl_ring; 2592c0c050c5SMichael Chan __le16 seq_id; 2593c0c050c5SMichael Chan __le16 target_id; 2594c0c050c5SMichael Chan __le64 resp_addr; 2595c0c050c5SMichael Chan __le32 flags; 2596c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 259716d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 2598c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 2599c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 260011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 260111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 260211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 260311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 2604a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 2605a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 2606a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 2607a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 2608a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 2609a58a3e68SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 261016d663a6SMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 2611bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 2612bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 26139d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 26149d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 26159d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 26169d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 26179d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 26189d6b648cSMichael Chan #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 2619c0c050c5SMichael Chan __le32 enables; 2620c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 2621c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 2622c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 2623c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 2624c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 2625c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 2626c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 2627c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 2628c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 262911f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 263011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 2631bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 2632bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 2633c0c050c5SMichael Chan __le16 port_id; 2634c0c050c5SMichael Chan __le16 force_link_speed; 2635441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 2636441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 2637441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 2638441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 2639441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 2640441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 2641441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 2642441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 2643441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 2644441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 2645441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 2646894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 2647c0c050c5SMichael Chan u8 auto_mode; 2648441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 2649441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 2650441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 2651441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 2652441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 2653894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 2654c0c050c5SMichael Chan u8 auto_duplex; 2655441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 2656441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 2657441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 2658894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 2659c0c050c5SMichael Chan u8 auto_pause; 2660c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 2661c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 266211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2663c0c050c5SMichael Chan u8 unused_0; 2664c0c050c5SMichael Chan __le16 auto_link_speed; 2665441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 2666441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 2667441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 2668441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 2669441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 2670441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 2671441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 2672441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 2673441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 2674441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 2675441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 2676894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 2677c0c050c5SMichael Chan __le16 auto_link_speed_mask; 2678c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2679c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2680c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2681c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2682c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2683c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2684c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2685c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2686c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2687c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2688c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 268911f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 269011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 269111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2692c0c050c5SMichael Chan u8 wirespeed; 2693441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 2694441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 2695894aa69aSMichael Chan #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 2696c0c050c5SMichael Chan u8 lpbk; 2697441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 2698441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 2699441cabbbSMichael Chan #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 27006fc92c33SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 27016fc92c33SMichael Chan #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 2702c0c050c5SMichael Chan u8 force_pause; 2703c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 2704c0c050c5SMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 2705c0c050c5SMichael Chan u8 unused_1; 2706c0c050c5SMichael Chan __le32 preemphasis; 270711f15ed3SMichael Chan __le16 eee_link_speed_mask; 270811f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 270911f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 271011f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 271111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 271211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 271311f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 271411f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 2715bfc6e5fbSMichael Chan __le16 force_pam4_link_speed; 2716bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 2717bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 2718bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 2719bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 272011f15ed3SMichael Chan __le32 tx_lpi_timer; 272111f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 272211f15ed3SMichael Chan #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 2723bfc6e5fbSMichael Chan __le16 auto_link_pam4_speed_mask; 2724bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 2725bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 2726bfc6e5fbSMichael Chan #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 2727bfc6e5fbSMichael Chan u8 unused_2[2]; 2728c0c050c5SMichael Chan }; 2729c0c050c5SMichael Chan 2730894aa69aSMichael Chan /* hwrm_port_phy_cfg_output (size:128b/16B) */ 2731c0c050c5SMichael Chan struct hwrm_port_phy_cfg_output { 2732c0c050c5SMichael Chan __le16 error_code; 2733c0c050c5SMichael Chan __le16 req_type; 2734c0c050c5SMichael Chan __le16 seq_id; 2735c0c050c5SMichael Chan __le16 resp_len; 2736894aa69aSMichael Chan u8 unused_0[7]; 2737c0c050c5SMichael Chan u8 valid; 2738c0c050c5SMichael Chan }; 2739c0c050c5SMichael Chan 2740d4f52de0SMichael Chan /* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 2741d4f52de0SMichael Chan struct hwrm_port_phy_cfg_cmd_err { 2742d4f52de0SMichael Chan u8 code; 2743d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2744d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 2745d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 2746d4f52de0SMichael Chan #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 2747d4f52de0SMichael Chan u8 unused_0[7]; 2748d4f52de0SMichael Chan }; 2749d4f52de0SMichael Chan 2750894aa69aSMichael Chan /* hwrm_port_phy_qcfg_input (size:192b/24B) */ 2751c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_input { 2752c0c050c5SMichael Chan __le16 req_type; 2753c0c050c5SMichael Chan __le16 cmpl_ring; 2754c0c050c5SMichael Chan __le16 seq_id; 2755c0c050c5SMichael Chan __le16 target_id; 2756c0c050c5SMichael Chan __le64 resp_addr; 2757c0c050c5SMichael Chan __le16 port_id; 2758894aa69aSMichael Chan u8 unused_0[6]; 2759c0c050c5SMichael Chan }; 2760c0c050c5SMichael Chan 27619d6b648cSMichael Chan /* hwrm_port_phy_qcfg_output (size:768b/96B) */ 2762c0c050c5SMichael Chan struct hwrm_port_phy_qcfg_output { 2763c0c050c5SMichael Chan __le16 error_code; 2764c0c050c5SMichael Chan __le16 req_type; 2765c0c050c5SMichael Chan __le16 seq_id; 2766c0c050c5SMichael Chan __le16 resp_len; 2767c0c050c5SMichael Chan u8 link; 2768441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 2769441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 2770441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 2771894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 27729d6b648cSMichael Chan u8 active_fec_signal_mode; 27739d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 27749d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 27759d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 27769d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 27779d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 27789d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 27799d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 27809d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 27819d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 27829d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 27839d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 27849d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 27859d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 27869d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 27879d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 2788c0c050c5SMichael Chan __le16 link_speed; 2789441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 2790441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 2791441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 2792441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 2793441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 2794441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 2795441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 2796441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 2797441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 2798441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 279931d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 2800441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 2801894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 2802acb20054SMichael Chan u8 duplex_cfg; 2803acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 2804acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 2805894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 2806c0c050c5SMichael Chan u8 pause; 2807c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 2808c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 2809c0c050c5SMichael Chan __le16 support_speeds; 2810c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 2811c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 2812c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 2813c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 2814c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 2815c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 2816c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 2817c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 2818c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 2819c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 2820c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 282111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 282211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 282311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 2824c0c050c5SMichael Chan __le16 force_link_speed; 2825441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 2826441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 2827441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 2828441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 2829441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 2830441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 2831441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 2832441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 2833441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 2834441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 2835441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 2836894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 2837c0c050c5SMichael Chan u8 auto_mode; 2838441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 2839441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 2840441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 2841441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 2842441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 2843894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 2844c0c050c5SMichael Chan u8 auto_pause; 2845c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 2846c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 284711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 2848c0c050c5SMichael Chan __le16 auto_link_speed; 2849441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 2850441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 2851441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 2852441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 2853441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 2854441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 2855441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 2856441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 2857441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 2858441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 2859441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 2860894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 2861c0c050c5SMichael Chan __le16 auto_link_speed_mask; 2862c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 2863c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 2864c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 2865c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 2866c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 2867c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 2868c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 2869c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 2870c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 2871c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 2872c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 287311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 287411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 287511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 2876c0c050c5SMichael Chan u8 wirespeed; 2877441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 2878441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 2879894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 2880c0c050c5SMichael Chan u8 lpbk; 2881441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 2882441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 2883441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 28846fc92c33SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 28856fc92c33SMichael Chan #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 2886c0c050c5SMichael Chan u8 force_pause; 2887c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 2888c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 288911f15ed3SMichael Chan u8 module_status; 2890441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 2891441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 2892441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 2893441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 2894441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 289541136ab3SMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 2896441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 2897894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 2898c0c050c5SMichael Chan __le32 preemphasis; 2899c0c050c5SMichael Chan u8 phy_maj; 2900c0c050c5SMichael Chan u8 phy_min; 2901c0c050c5SMichael Chan u8 phy_bld; 2902c0c050c5SMichael Chan u8 phy_type; 2903441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 2904441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 2905441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 2906441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 2907441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 2908441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 2909441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 2910441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 2911441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 2912441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 2913441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 2914bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 2915bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 2916bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 2917bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 2918bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 2919bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 2920bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 2921bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 2922bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 2923bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 2924bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 2925bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 2926bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 2927bac9a7e0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 2928acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 2929acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 2930acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 293131d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 293231d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 293331d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 293431d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 293531d357c0SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 2936c0c050c5SMichael Chan u8 media_type; 2937441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 2938441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 2939441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 2940441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 2941894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 294211f15ed3SMichael Chan u8 xcvr_pkg_type; 2943441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 2944441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 2945894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 294611f15ed3SMichael Chan u8 eee_config_phy_addr; 2947c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 2948c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 2949894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 2950894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 295111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 295211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 295311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 295411f15ed3SMichael Chan u8 parallel_detect; 295511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 2956c0c050c5SMichael Chan __le16 link_partner_adv_speeds; 2957c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 2958c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 2959c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 2960c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 2961c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 2962c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 2963c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 2964c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 2965c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 2966c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 2967c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 296811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 296911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 297011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 2971c0c050c5SMichael Chan u8 link_partner_adv_auto_mode; 2972441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 2973441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 2974441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 2975441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 2976441cabbbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 2977894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 2978c0c050c5SMichael Chan u8 link_partner_adv_pause; 2979c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 2980c0c050c5SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 298111f15ed3SMichael Chan __le16 adv_eee_link_speed_mask; 298211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 298311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 298411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 298511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 298611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 298711f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 298811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 298911f15ed3SMichael Chan __le16 link_partner_adv_eee_link_speed_mask; 299011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 299111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 299211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 299311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 299411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 299511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 299611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 299711f15ed3SMichael Chan __le32 xcvr_identifier_type_tx_lpi_timer; 299811f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 299911f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 300011f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 300111f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 300211f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 300311f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 300411f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 300511f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 300611f15ed3SMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 3007894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 3008a58a3e68SMichael Chan __le16 fec_cfg; 3009a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 3010a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 3011a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 3012a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 3013a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 3014a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 3015a58a3e68SMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 3016bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 3017bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 30189d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 30199d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 30209d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 30219d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 30229d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 30239d6b648cSMichael Chan #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 3024acb20054SMichael Chan u8 duplex_state; 3025acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 3026acb20054SMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 3027894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3028894aa69aSMichael Chan u8 option_flags; 3029894aa69aSMichael Chan #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 3030*16db6323SMichael Chan #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 303111f15ed3SMichael Chan char phy_vendor_name[16]; 303211f15ed3SMichael Chan char phy_vendor_partnumber[16]; 3033bfc6e5fbSMichael Chan __le16 support_pam4_speeds; 3034bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 3035bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 3036bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 3037bfc6e5fbSMichael Chan __le16 force_pam4_link_speed; 3038bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 3039bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 3040bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 3041bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 3042bfc6e5fbSMichael Chan __le16 auto_pam4_link_speed_mask; 3043bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 3044bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 3045bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 30469d6b648cSMichael Chan u8 link_partner_pam4_adv_speeds; 3047bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 3048bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 3049bfc6e5fbSMichael Chan #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 3050c0c050c5SMichael Chan u8 valid; 3051c0c050c5SMichael Chan }; 3052c0c050c5SMichael Chan 30534a50ddc2SMichael Chan /* hwrm_port_mac_cfg_input (size:384b/48B) */ 3054c0c050c5SMichael Chan struct hwrm_port_mac_cfg_input { 3055c0c050c5SMichael Chan __le16 req_type; 3056c0c050c5SMichael Chan __le16 cmpl_ring; 3057c0c050c5SMichael Chan __le16 seq_id; 3058c0c050c5SMichael Chan __le16 target_id; 3059c0c050c5SMichael Chan __le64 resp_addr; 3060c0c050c5SMichael Chan __le32 flags; 3061c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 3062441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 3063c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 3064c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 306511f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 306611f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 306711f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 306811f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 3069a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 3070a58a3e68SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 3071441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 3072441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 3073441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 30744a50ddc2SMichael Chan #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 3075c0c050c5SMichael Chan __le32 enables; 3076c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 3077c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 3078441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 3079c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 3080c0c050c5SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 308111f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 308211f15ed3SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 3083441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 30844a50ddc2SMichael Chan #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 3085c0c050c5SMichael Chan __le16 port_id; 3086c0c050c5SMichael Chan u8 ipg; 3087c0c050c5SMichael Chan u8 lpbk; 3088441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 3089441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 3090441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 3091894aa69aSMichael Chan #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 3092441cabbbSMichael Chan u8 vlan_pri2cos_map_pri; 3093441cabbbSMichael Chan u8 reserved1; 3094c0c050c5SMichael Chan u8 tunnel_pri2cos_map_pri; 3095c0c050c5SMichael Chan u8 dscp2pri_map_pri; 309611f15ed3SMichael Chan __le16 rx_ts_capture_ptp_msg_type; 309711f15ed3SMichael Chan __le16 tx_ts_capture_ptp_msg_type; 3098441cabbbSMichael Chan u8 cos_field_cfg; 3099441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 3100441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 3101441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 3102441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 3103441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 3104441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 3105441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 3106441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 3107441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 3108441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 3109441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 3110441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 3111441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 3112441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 3113441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 3114441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 3115441cabbbSMichael Chan #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 3116441cabbbSMichael Chan u8 unused_0[3]; 31174a50ddc2SMichael Chan __s32 ptp_freq_adj_ppb; 31184a50ddc2SMichael Chan u8 unused_1[4]; 3119c0c050c5SMichael Chan }; 3120c0c050c5SMichael Chan 3121894aa69aSMichael Chan /* hwrm_port_mac_cfg_output (size:128b/16B) */ 3122c0c050c5SMichael Chan struct hwrm_port_mac_cfg_output { 3123c0c050c5SMichael Chan __le16 error_code; 3124c0c050c5SMichael Chan __le16 req_type; 3125c0c050c5SMichael Chan __le16 seq_id; 3126c0c050c5SMichael Chan __le16 resp_len; 3127c0c050c5SMichael Chan __le16 mru; 3128c0c050c5SMichael Chan __le16 mtu; 3129c0c050c5SMichael Chan u8 ipg; 3130c0c050c5SMichael Chan u8 lpbk; 3131441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 3132441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 3133441cabbbSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 3134894aa69aSMichael Chan #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 3135c0c050c5SMichael Chan u8 unused_0; 3136c0c050c5SMichael Chan u8 valid; 3137c0c050c5SMichael Chan }; 3138c0c050c5SMichael Chan 3139894aa69aSMichael Chan /* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 3140acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_input { 3141acb20054SMichael Chan __le16 req_type; 3142acb20054SMichael Chan __le16 cmpl_ring; 3143acb20054SMichael Chan __le16 seq_id; 3144acb20054SMichael Chan __le16 target_id; 3145acb20054SMichael Chan __le64 resp_addr; 3146acb20054SMichael Chan __le16 port_id; 3147894aa69aSMichael Chan u8 unused_0[6]; 3148acb20054SMichael Chan }; 3149acb20054SMichael Chan 3150894aa69aSMichael Chan /* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 3151acb20054SMichael Chan struct hwrm_port_mac_ptp_qcfg_output { 3152acb20054SMichael Chan __le16 error_code; 3153acb20054SMichael Chan __le16 req_type; 3154acb20054SMichael Chan __le16 seq_id; 3155acb20054SMichael Chan __le16 resp_len; 3156acb20054SMichael Chan u8 flags; 3157acb20054SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 31584a50ddc2SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 315941136ab3SMichael Chan #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 3160894aa69aSMichael Chan u8 unused_0[3]; 3161acb20054SMichael Chan __le32 rx_ts_reg_off_lower; 3162acb20054SMichael Chan __le32 rx_ts_reg_off_upper; 3163acb20054SMichael Chan __le32 rx_ts_reg_off_seq_id; 3164acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_0; 3165acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_1; 3166acb20054SMichael Chan __le32 rx_ts_reg_off_src_id_2; 3167acb20054SMichael Chan __le32 rx_ts_reg_off_domain_id; 3168acb20054SMichael Chan __le32 rx_ts_reg_off_fifo; 3169acb20054SMichael Chan __le32 rx_ts_reg_off_fifo_adv; 3170acb20054SMichael Chan __le32 rx_ts_reg_off_granularity; 3171acb20054SMichael Chan __le32 tx_ts_reg_off_lower; 3172acb20054SMichael Chan __le32 tx_ts_reg_off_upper; 3173acb20054SMichael Chan __le32 tx_ts_reg_off_seq_id; 3174acb20054SMichael Chan __le32 tx_ts_reg_off_fifo; 3175acb20054SMichael Chan __le32 tx_ts_reg_off_granularity; 3176894aa69aSMichael Chan u8 unused_1[7]; 3177acb20054SMichael Chan u8 valid; 3178acb20054SMichael Chan }; 3179acb20054SMichael Chan 31806fc92c33SMichael Chan /* tx_port_stats (size:3264b/408B) */ 31816fc92c33SMichael Chan struct tx_port_stats { 31826fc92c33SMichael Chan __le64 tx_64b_frames; 31836fc92c33SMichael Chan __le64 tx_65b_127b_frames; 31846fc92c33SMichael Chan __le64 tx_128b_255b_frames; 31856fc92c33SMichael Chan __le64 tx_256b_511b_frames; 31866fc92c33SMichael Chan __le64 tx_512b_1023b_frames; 31876fc92c33SMichael Chan __le64 tx_1024b_1518b_frames; 31886fc92c33SMichael Chan __le64 tx_good_vlan_frames; 31896fc92c33SMichael Chan __le64 tx_1519b_2047b_frames; 31906fc92c33SMichael Chan __le64 tx_2048b_4095b_frames; 31916fc92c33SMichael Chan __le64 tx_4096b_9216b_frames; 31926fc92c33SMichael Chan __le64 tx_9217b_16383b_frames; 31936fc92c33SMichael Chan __le64 tx_good_frames; 31946fc92c33SMichael Chan __le64 tx_total_frames; 31956fc92c33SMichael Chan __le64 tx_ucast_frames; 31966fc92c33SMichael Chan __le64 tx_mcast_frames; 31976fc92c33SMichael Chan __le64 tx_bcast_frames; 31986fc92c33SMichael Chan __le64 tx_pause_frames; 31996fc92c33SMichael Chan __le64 tx_pfc_frames; 32006fc92c33SMichael Chan __le64 tx_jabber_frames; 32016fc92c33SMichael Chan __le64 tx_fcs_err_frames; 32026fc92c33SMichael Chan __le64 tx_control_frames; 32036fc92c33SMichael Chan __le64 tx_oversz_frames; 32046fc92c33SMichael Chan __le64 tx_single_dfrl_frames; 32056fc92c33SMichael Chan __le64 tx_multi_dfrl_frames; 32066fc92c33SMichael Chan __le64 tx_single_coll_frames; 32076fc92c33SMichael Chan __le64 tx_multi_coll_frames; 32086fc92c33SMichael Chan __le64 tx_late_coll_frames; 32096fc92c33SMichael Chan __le64 tx_excessive_coll_frames; 32106fc92c33SMichael Chan __le64 tx_frag_frames; 32116fc92c33SMichael Chan __le64 tx_err; 32126fc92c33SMichael Chan __le64 tx_tagged_frames; 32136fc92c33SMichael Chan __le64 tx_dbl_tagged_frames; 32146fc92c33SMichael Chan __le64 tx_runt_frames; 32156fc92c33SMichael Chan __le64 tx_fifo_underruns; 32166fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri0; 32176fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri1; 32186fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri2; 32196fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri3; 32206fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri4; 32216fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri5; 32226fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri6; 32236fc92c33SMichael Chan __le64 tx_pfc_ena_frames_pri7; 32246fc92c33SMichael Chan __le64 tx_eee_lpi_events; 32256fc92c33SMichael Chan __le64 tx_eee_lpi_duration; 32266fc92c33SMichael Chan __le64 tx_llfc_logical_msgs; 32276fc92c33SMichael Chan __le64 tx_hcfc_msgs; 32286fc92c33SMichael Chan __le64 tx_total_collisions; 32296fc92c33SMichael Chan __le64 tx_bytes; 32306fc92c33SMichael Chan __le64 tx_xthol_frames; 32316fc92c33SMichael Chan __le64 tx_stat_discard; 32326fc92c33SMichael Chan __le64 tx_stat_error; 32336fc92c33SMichael Chan }; 32346fc92c33SMichael Chan 32356fc92c33SMichael Chan /* rx_port_stats (size:4224b/528B) */ 32366fc92c33SMichael Chan struct rx_port_stats { 32376fc92c33SMichael Chan __le64 rx_64b_frames; 32386fc92c33SMichael Chan __le64 rx_65b_127b_frames; 32396fc92c33SMichael Chan __le64 rx_128b_255b_frames; 32406fc92c33SMichael Chan __le64 rx_256b_511b_frames; 32416fc92c33SMichael Chan __le64 rx_512b_1023b_frames; 32426fc92c33SMichael Chan __le64 rx_1024b_1518b_frames; 32436fc92c33SMichael Chan __le64 rx_good_vlan_frames; 32446fc92c33SMichael Chan __le64 rx_1519b_2047b_frames; 32456fc92c33SMichael Chan __le64 rx_2048b_4095b_frames; 32466fc92c33SMichael Chan __le64 rx_4096b_9216b_frames; 32476fc92c33SMichael Chan __le64 rx_9217b_16383b_frames; 32486fc92c33SMichael Chan __le64 rx_total_frames; 32496fc92c33SMichael Chan __le64 rx_ucast_frames; 32506fc92c33SMichael Chan __le64 rx_mcast_frames; 32516fc92c33SMichael Chan __le64 rx_bcast_frames; 32526fc92c33SMichael Chan __le64 rx_fcs_err_frames; 32536fc92c33SMichael Chan __le64 rx_ctrl_frames; 32546fc92c33SMichael Chan __le64 rx_pause_frames; 32556fc92c33SMichael Chan __le64 rx_pfc_frames; 32566fc92c33SMichael Chan __le64 rx_unsupported_opcode_frames; 32576fc92c33SMichael Chan __le64 rx_unsupported_da_pausepfc_frames; 32586fc92c33SMichael Chan __le64 rx_wrong_sa_frames; 32596fc92c33SMichael Chan __le64 rx_align_err_frames; 32606fc92c33SMichael Chan __le64 rx_oor_len_frames; 32616fc92c33SMichael Chan __le64 rx_code_err_frames; 32626fc92c33SMichael Chan __le64 rx_false_carrier_frames; 32636fc92c33SMichael Chan __le64 rx_ovrsz_frames; 32646fc92c33SMichael Chan __le64 rx_jbr_frames; 32656fc92c33SMichael Chan __le64 rx_mtu_err_frames; 32666fc92c33SMichael Chan __le64 rx_match_crc_frames; 32676fc92c33SMichael Chan __le64 rx_promiscuous_frames; 32686fc92c33SMichael Chan __le64 rx_tagged_frames; 32696fc92c33SMichael Chan __le64 rx_double_tagged_frames; 32706fc92c33SMichael Chan __le64 rx_trunc_frames; 32716fc92c33SMichael Chan __le64 rx_good_frames; 32726fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri0; 32736fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri1; 32746fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri2; 32756fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri3; 32766fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri4; 32776fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri5; 32786fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri6; 32796fc92c33SMichael Chan __le64 rx_pfc_xon2xoff_frames_pri7; 32806fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri0; 32816fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri1; 32826fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri2; 32836fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri3; 32846fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri4; 32856fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri5; 32866fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri6; 32876fc92c33SMichael Chan __le64 rx_pfc_ena_frames_pri7; 32886fc92c33SMichael Chan __le64 rx_sch_crc_err_frames; 32896fc92c33SMichael Chan __le64 rx_undrsz_frames; 32906fc92c33SMichael Chan __le64 rx_frag_frames; 32916fc92c33SMichael Chan __le64 rx_eee_lpi_events; 32926fc92c33SMichael Chan __le64 rx_eee_lpi_duration; 32936fc92c33SMichael Chan __le64 rx_llfc_physical_msgs; 32946fc92c33SMichael Chan __le64 rx_llfc_logical_msgs; 32956fc92c33SMichael Chan __le64 rx_llfc_msgs_with_crc_err; 32966fc92c33SMichael Chan __le64 rx_hcfc_msgs; 32976fc92c33SMichael Chan __le64 rx_hcfc_msgs_with_crc_err; 32986fc92c33SMichael Chan __le64 rx_bytes; 32996fc92c33SMichael Chan __le64 rx_runt_bytes; 33006fc92c33SMichael Chan __le64 rx_runt_frames; 33016fc92c33SMichael Chan __le64 rx_stat_discard; 33026fc92c33SMichael Chan __le64 rx_stat_err; 33036fc92c33SMichael Chan }; 33046fc92c33SMichael Chan 3305894aa69aSMichael Chan /* hwrm_port_qstats_input (size:320b/40B) */ 3306c0c050c5SMichael Chan struct hwrm_port_qstats_input { 3307c0c050c5SMichael Chan __le16 req_type; 3308c0c050c5SMichael Chan __le16 cmpl_ring; 3309c0c050c5SMichael Chan __le16 seq_id; 3310c0c050c5SMichael Chan __le16 target_id; 3311c0c050c5SMichael Chan __le64 resp_addr; 3312c0c050c5SMichael Chan __le16 port_id; 3313460c2577SMichael Chan u8 flags; 3314460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_UNUSED 0x0UL 3315460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 3316460c2577SMichael Chan #define PORT_QSTATS_REQ_FLAGS_LAST PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 3317460c2577SMichael Chan u8 unused_0[5]; 3318c0c050c5SMichael Chan __le64 tx_stat_host_addr; 3319c0c050c5SMichael Chan __le64 rx_stat_host_addr; 3320c0c050c5SMichael Chan }; 3321c0c050c5SMichael Chan 3322894aa69aSMichael Chan /* hwrm_port_qstats_output (size:128b/16B) */ 3323c0c050c5SMichael Chan struct hwrm_port_qstats_output { 3324c0c050c5SMichael Chan __le16 error_code; 3325c0c050c5SMichael Chan __le16 req_type; 3326c0c050c5SMichael Chan __le16 seq_id; 3327c0c050c5SMichael Chan __le16 resp_len; 3328c193554eSMichael Chan __le16 tx_stat_size; 3329c193554eSMichael Chan __le16 rx_stat_size; 3330894aa69aSMichael Chan u8 unused_0[3]; 3331c0c050c5SMichael Chan u8 valid; 3332c0c050c5SMichael Chan }; 3333c0c050c5SMichael Chan 33346fc92c33SMichael Chan /* tx_port_stats_ext (size:2048b/256B) */ 33356fc92c33SMichael Chan struct tx_port_stats_ext { 33366fc92c33SMichael Chan __le64 tx_bytes_cos0; 33376fc92c33SMichael Chan __le64 tx_bytes_cos1; 33386fc92c33SMichael Chan __le64 tx_bytes_cos2; 33396fc92c33SMichael Chan __le64 tx_bytes_cos3; 33406fc92c33SMichael Chan __le64 tx_bytes_cos4; 33416fc92c33SMichael Chan __le64 tx_bytes_cos5; 33426fc92c33SMichael Chan __le64 tx_bytes_cos6; 33436fc92c33SMichael Chan __le64 tx_bytes_cos7; 33446fc92c33SMichael Chan __le64 tx_packets_cos0; 33456fc92c33SMichael Chan __le64 tx_packets_cos1; 33466fc92c33SMichael Chan __le64 tx_packets_cos2; 33476fc92c33SMichael Chan __le64 tx_packets_cos3; 33486fc92c33SMichael Chan __le64 tx_packets_cos4; 33496fc92c33SMichael Chan __le64 tx_packets_cos5; 33506fc92c33SMichael Chan __le64 tx_packets_cos6; 33516fc92c33SMichael Chan __le64 tx_packets_cos7; 33526fc92c33SMichael Chan __le64 pfc_pri0_tx_duration_us; 33536fc92c33SMichael Chan __le64 pfc_pri0_tx_transitions; 33546fc92c33SMichael Chan __le64 pfc_pri1_tx_duration_us; 33556fc92c33SMichael Chan __le64 pfc_pri1_tx_transitions; 33566fc92c33SMichael Chan __le64 pfc_pri2_tx_duration_us; 33576fc92c33SMichael Chan __le64 pfc_pri2_tx_transitions; 33586fc92c33SMichael Chan __le64 pfc_pri3_tx_duration_us; 33596fc92c33SMichael Chan __le64 pfc_pri3_tx_transitions; 33606fc92c33SMichael Chan __le64 pfc_pri4_tx_duration_us; 33616fc92c33SMichael Chan __le64 pfc_pri4_tx_transitions; 33626fc92c33SMichael Chan __le64 pfc_pri5_tx_duration_us; 33636fc92c33SMichael Chan __le64 pfc_pri5_tx_transitions; 33646fc92c33SMichael Chan __le64 pfc_pri6_tx_duration_us; 33656fc92c33SMichael Chan __le64 pfc_pri6_tx_transitions; 33666fc92c33SMichael Chan __le64 pfc_pri7_tx_duration_us; 33676fc92c33SMichael Chan __le64 pfc_pri7_tx_transitions; 33686fc92c33SMichael Chan }; 33696fc92c33SMichael Chan 33702792b5b9SMichael Chan /* rx_port_stats_ext (size:3648b/456B) */ 33716fc92c33SMichael Chan struct rx_port_stats_ext { 33726fc92c33SMichael Chan __le64 link_down_events; 33736fc92c33SMichael Chan __le64 continuous_pause_events; 33746fc92c33SMichael Chan __le64 resume_pause_events; 33756fc92c33SMichael Chan __le64 continuous_roce_pause_events; 33766fc92c33SMichael Chan __le64 resume_roce_pause_events; 33776fc92c33SMichael Chan __le64 rx_bytes_cos0; 33786fc92c33SMichael Chan __le64 rx_bytes_cos1; 33796fc92c33SMichael Chan __le64 rx_bytes_cos2; 33806fc92c33SMichael Chan __le64 rx_bytes_cos3; 33816fc92c33SMichael Chan __le64 rx_bytes_cos4; 33826fc92c33SMichael Chan __le64 rx_bytes_cos5; 33836fc92c33SMichael Chan __le64 rx_bytes_cos6; 33846fc92c33SMichael Chan __le64 rx_bytes_cos7; 33856fc92c33SMichael Chan __le64 rx_packets_cos0; 33866fc92c33SMichael Chan __le64 rx_packets_cos1; 33876fc92c33SMichael Chan __le64 rx_packets_cos2; 33886fc92c33SMichael Chan __le64 rx_packets_cos3; 33896fc92c33SMichael Chan __le64 rx_packets_cos4; 33906fc92c33SMichael Chan __le64 rx_packets_cos5; 33916fc92c33SMichael Chan __le64 rx_packets_cos6; 33926fc92c33SMichael Chan __le64 rx_packets_cos7; 33936fc92c33SMichael Chan __le64 pfc_pri0_rx_duration_us; 33946fc92c33SMichael Chan __le64 pfc_pri0_rx_transitions; 33956fc92c33SMichael Chan __le64 pfc_pri1_rx_duration_us; 33966fc92c33SMichael Chan __le64 pfc_pri1_rx_transitions; 33976fc92c33SMichael Chan __le64 pfc_pri2_rx_duration_us; 33986fc92c33SMichael Chan __le64 pfc_pri2_rx_transitions; 33996fc92c33SMichael Chan __le64 pfc_pri3_rx_duration_us; 34006fc92c33SMichael Chan __le64 pfc_pri3_rx_transitions; 34016fc92c33SMichael Chan __le64 pfc_pri4_rx_duration_us; 34026fc92c33SMichael Chan __le64 pfc_pri4_rx_transitions; 34036fc92c33SMichael Chan __le64 pfc_pri5_rx_duration_us; 34046fc92c33SMichael Chan __le64 pfc_pri5_rx_transitions; 34056fc92c33SMichael Chan __le64 pfc_pri6_rx_duration_us; 34066fc92c33SMichael Chan __le64 pfc_pri6_rx_transitions; 34076fc92c33SMichael Chan __le64 pfc_pri7_rx_duration_us; 34086fc92c33SMichael Chan __le64 pfc_pri7_rx_transitions; 34094a50ddc2SMichael Chan __le64 rx_bits; 34104a50ddc2SMichael Chan __le64 rx_buffer_passed_threshold; 34114a50ddc2SMichael Chan __le64 rx_pcs_symbol_err; 34124a50ddc2SMichael Chan __le64 rx_corrected_bits; 34132792b5b9SMichael Chan __le64 rx_discard_bytes_cos0; 34142792b5b9SMichael Chan __le64 rx_discard_bytes_cos1; 34152792b5b9SMichael Chan __le64 rx_discard_bytes_cos2; 34162792b5b9SMichael Chan __le64 rx_discard_bytes_cos3; 34172792b5b9SMichael Chan __le64 rx_discard_bytes_cos4; 34182792b5b9SMichael Chan __le64 rx_discard_bytes_cos5; 34192792b5b9SMichael Chan __le64 rx_discard_bytes_cos6; 34202792b5b9SMichael Chan __le64 rx_discard_bytes_cos7; 34212792b5b9SMichael Chan __le64 rx_discard_packets_cos0; 34222792b5b9SMichael Chan __le64 rx_discard_packets_cos1; 34232792b5b9SMichael Chan __le64 rx_discard_packets_cos2; 34242792b5b9SMichael Chan __le64 rx_discard_packets_cos3; 34252792b5b9SMichael Chan __le64 rx_discard_packets_cos4; 34262792b5b9SMichael Chan __le64 rx_discard_packets_cos5; 34272792b5b9SMichael Chan __le64 rx_discard_packets_cos6; 34282792b5b9SMichael Chan __le64 rx_discard_packets_cos7; 34296fc92c33SMichael Chan }; 34306fc92c33SMichael Chan 3431d4f52de0SMichael Chan /* hwrm_port_qstats_ext_input (size:320b/40B) */ 3432d4f52de0SMichael Chan struct hwrm_port_qstats_ext_input { 3433d4f52de0SMichael Chan __le16 req_type; 3434d4f52de0SMichael Chan __le16 cmpl_ring; 3435d4f52de0SMichael Chan __le16 seq_id; 3436d4f52de0SMichael Chan __le16 target_id; 3437d4f52de0SMichael Chan __le64 resp_addr; 3438d4f52de0SMichael Chan __le16 port_id; 3439d4f52de0SMichael Chan __le16 tx_stat_size; 3440d4f52de0SMichael Chan __le16 rx_stat_size; 3441460c2577SMichael Chan u8 flags; 3442460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_UNUSED 0x0UL 3443460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 3444460c2577SMichael Chan #define PORT_QSTATS_EXT_REQ_FLAGS_LAST PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 3445460c2577SMichael Chan u8 unused_0; 3446d4f52de0SMichael Chan __le64 tx_stat_host_addr; 3447d4f52de0SMichael Chan __le64 rx_stat_host_addr; 3448d4f52de0SMichael Chan }; 3449d4f52de0SMichael Chan 3450d4f52de0SMichael Chan /* hwrm_port_qstats_ext_output (size:128b/16B) */ 3451d4f52de0SMichael Chan struct hwrm_port_qstats_ext_output { 3452d4f52de0SMichael Chan __le16 error_code; 3453d4f52de0SMichael Chan __le16 req_type; 3454d4f52de0SMichael Chan __le16 seq_id; 3455d4f52de0SMichael Chan __le16 resp_len; 3456d4f52de0SMichael Chan __le16 tx_stat_size; 3457d4f52de0SMichael Chan __le16 rx_stat_size; 34586fc92c33SMichael Chan __le16 total_active_cos_queues; 345931d357c0SMichael Chan u8 flags; 346031d357c0SMichael Chan #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 3461d4f52de0SMichael Chan u8 valid; 3462d4f52de0SMichael Chan }; 3463d4f52de0SMichael Chan 3464894aa69aSMichael Chan /* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 3465c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_input { 3466c0c050c5SMichael Chan __le16 req_type; 3467c0c050c5SMichael Chan __le16 cmpl_ring; 3468c0c050c5SMichael Chan __le16 seq_id; 3469c0c050c5SMichael Chan __le16 target_id; 3470c0c050c5SMichael Chan __le64 resp_addr; 3471c0c050c5SMichael Chan }; 3472c0c050c5SMichael Chan 3473894aa69aSMichael Chan /* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 3474c0c050c5SMichael Chan struct hwrm_port_lpbk_qstats_output { 3475c0c050c5SMichael Chan __le16 error_code; 3476c0c050c5SMichael Chan __le16 req_type; 3477c0c050c5SMichael Chan __le16 seq_id; 3478c0c050c5SMichael Chan __le16 resp_len; 3479c0c050c5SMichael Chan __le64 lpbk_ucast_frames; 3480c0c050c5SMichael Chan __le64 lpbk_mcast_frames; 3481c0c050c5SMichael Chan __le64 lpbk_bcast_frames; 3482c0c050c5SMichael Chan __le64 lpbk_ucast_bytes; 3483c0c050c5SMichael Chan __le64 lpbk_mcast_bytes; 3484c0c050c5SMichael Chan __le64 lpbk_bcast_bytes; 3485c193554eSMichael Chan __le64 tx_stat_discard; 3486c193554eSMichael Chan __le64 tx_stat_error; 3487c193554eSMichael Chan __le64 rx_stat_discard; 3488c193554eSMichael Chan __le64 rx_stat_error; 3489894aa69aSMichael Chan u8 unused_0[7]; 3490c0c050c5SMichael Chan u8 valid; 3491c0c050c5SMichael Chan }; 3492c0c050c5SMichael Chan 34939d6b648cSMichael Chan /* hwrm_port_ecn_qstats_input (size:256b/32B) */ 34949d6b648cSMichael Chan struct hwrm_port_ecn_qstats_input { 34959d6b648cSMichael Chan __le16 req_type; 34969d6b648cSMichael Chan __le16 cmpl_ring; 34979d6b648cSMichael Chan __le16 seq_id; 34989d6b648cSMichael Chan __le16 target_id; 34999d6b648cSMichael Chan __le64 resp_addr; 35009d6b648cSMichael Chan __le16 port_id; 35019d6b648cSMichael Chan __le16 ecn_stat_buf_size; 35029d6b648cSMichael Chan u8 flags; 35039d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_UNUSED 0x0UL 35049d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 35059d6b648cSMichael Chan #define PORT_ECN_QSTATS_REQ_FLAGS_LAST PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 35069d6b648cSMichael Chan u8 unused_0[3]; 35079d6b648cSMichael Chan __le64 ecn_stat_host_addr; 35089d6b648cSMichael Chan }; 35099d6b648cSMichael Chan 35109d6b648cSMichael Chan /* hwrm_port_ecn_qstats_output (size:128b/16B) */ 35119d6b648cSMichael Chan struct hwrm_port_ecn_qstats_output { 35129d6b648cSMichael Chan __le16 error_code; 35139d6b648cSMichael Chan __le16 req_type; 35149d6b648cSMichael Chan __le16 seq_id; 35159d6b648cSMichael Chan __le16 resp_len; 35169d6b648cSMichael Chan __le16 ecn_stat_buf_size; 35179d6b648cSMichael Chan u8 mark_en; 35189d6b648cSMichael Chan u8 unused_0[4]; 35199d6b648cSMichael Chan u8 valid; 35209d6b648cSMichael Chan }; 35219d6b648cSMichael Chan 35229d6b648cSMichael Chan /* port_stats_ecn (size:512b/64B) */ 35239d6b648cSMichael Chan struct port_stats_ecn { 35249d6b648cSMichael Chan __le64 mark_cnt_cos0; 35259d6b648cSMichael Chan __le64 mark_cnt_cos1; 35269d6b648cSMichael Chan __le64 mark_cnt_cos2; 35279d6b648cSMichael Chan __le64 mark_cnt_cos3; 35289d6b648cSMichael Chan __le64 mark_cnt_cos4; 35299d6b648cSMichael Chan __le64 mark_cnt_cos5; 35309d6b648cSMichael Chan __le64 mark_cnt_cos6; 35319d6b648cSMichael Chan __le64 mark_cnt_cos7; 35329d6b648cSMichael Chan }; 35339d6b648cSMichael Chan 3534894aa69aSMichael Chan /* hwrm_port_clr_stats_input (size:192b/24B) */ 3535c0c050c5SMichael Chan struct hwrm_port_clr_stats_input { 3536c0c050c5SMichael Chan __le16 req_type; 3537c0c050c5SMichael Chan __le16 cmpl_ring; 3538c0c050c5SMichael Chan __le16 seq_id; 3539c0c050c5SMichael Chan __le16 target_id; 3540c0c050c5SMichael Chan __le64 resp_addr; 3541c0c050c5SMichael Chan __le16 port_id; 354231d357c0SMichael Chan u8 flags; 354331d357c0SMichael Chan #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 354431d357c0SMichael Chan u8 unused_0[5]; 3545c0c050c5SMichael Chan }; 3546c0c050c5SMichael Chan 3547894aa69aSMichael Chan /* hwrm_port_clr_stats_output (size:128b/16B) */ 3548c0c050c5SMichael Chan struct hwrm_port_clr_stats_output { 3549c0c050c5SMichael Chan __le16 error_code; 3550c0c050c5SMichael Chan __le16 req_type; 3551c0c050c5SMichael Chan __le16 seq_id; 3552c0c050c5SMichael Chan __le16 resp_len; 3553894aa69aSMichael Chan u8 unused_0[7]; 3554c0c050c5SMichael Chan u8 valid; 3555c0c050c5SMichael Chan }; 3556c0c050c5SMichael Chan 3557894aa69aSMichael Chan /* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 3558c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_input { 3559c0c050c5SMichael Chan __le16 req_type; 3560c0c050c5SMichael Chan __le16 cmpl_ring; 3561c0c050c5SMichael Chan __le16 seq_id; 3562c0c050c5SMichael Chan __le16 target_id; 3563c0c050c5SMichael Chan __le64 resp_addr; 3564c0c050c5SMichael Chan }; 3565c0c050c5SMichael Chan 3566894aa69aSMichael Chan /* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 3567c0c050c5SMichael Chan struct hwrm_port_lpbk_clr_stats_output { 3568c0c050c5SMichael Chan __le16 error_code; 3569c0c050c5SMichael Chan __le16 req_type; 3570c0c050c5SMichael Chan __le16 seq_id; 3571c0c050c5SMichael Chan __le16 resp_len; 3572894aa69aSMichael Chan u8 unused_0[7]; 3573c0c050c5SMichael Chan u8 valid; 3574c0c050c5SMichael Chan }; 3575c0c050c5SMichael Chan 35764a50ddc2SMichael Chan /* hwrm_port_ts_query_input (size:192b/24B) */ 35774a50ddc2SMichael Chan struct hwrm_port_ts_query_input { 35784a50ddc2SMichael Chan __le16 req_type; 35794a50ddc2SMichael Chan __le16 cmpl_ring; 35804a50ddc2SMichael Chan __le16 seq_id; 35814a50ddc2SMichael Chan __le16 target_id; 35824a50ddc2SMichael Chan __le64 resp_addr; 35834a50ddc2SMichael Chan __le32 flags; 35844a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 35854a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 35864a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 35874a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 35884a50ddc2SMichael Chan #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 35894a50ddc2SMichael Chan __le16 port_id; 35904a50ddc2SMichael Chan u8 unused_0[2]; 35914a50ddc2SMichael Chan }; 35924a50ddc2SMichael Chan 35934a50ddc2SMichael Chan /* hwrm_port_ts_query_output (size:192b/24B) */ 35944a50ddc2SMichael Chan struct hwrm_port_ts_query_output { 35954a50ddc2SMichael Chan __le16 error_code; 35964a50ddc2SMichael Chan __le16 req_type; 35974a50ddc2SMichael Chan __le16 seq_id; 35984a50ddc2SMichael Chan __le16 resp_len; 35994a50ddc2SMichael Chan __le64 ptp_msg_ts; 36004a50ddc2SMichael Chan __le16 ptp_msg_seqid; 36014a50ddc2SMichael Chan u8 unused_0[5]; 36024a50ddc2SMichael Chan u8 valid; 36034a50ddc2SMichael Chan }; 36044a50ddc2SMichael Chan 3605894aa69aSMichael Chan /* hwrm_port_phy_qcaps_input (size:192b/24B) */ 360611f15ed3SMichael Chan struct hwrm_port_phy_qcaps_input { 360711f15ed3SMichael Chan __le16 req_type; 360811f15ed3SMichael Chan __le16 cmpl_ring; 360911f15ed3SMichael Chan __le16 seq_id; 361011f15ed3SMichael Chan __le16 target_id; 361111f15ed3SMichael Chan __le64 resp_addr; 361211f15ed3SMichael Chan __le16 port_id; 3613894aa69aSMichael Chan u8 unused_0[6]; 361411f15ed3SMichael Chan }; 361511f15ed3SMichael Chan 3616bfc6e5fbSMichael Chan /* hwrm_port_phy_qcaps_output (size:256b/32B) */ 361711f15ed3SMichael Chan struct hwrm_port_phy_qcaps_output { 361811f15ed3SMichael Chan __le16 error_code; 361911f15ed3SMichael Chan __le16 req_type; 362011f15ed3SMichael Chan __le16 seq_id; 362111f15ed3SMichael Chan __le16 resp_len; 3622acb20054SMichael Chan u8 flags; 3623acb20054SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 36246fc92c33SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 362541136ab3SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 362641136ab3SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3627bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 36289d6b648cSMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 3629*16db6323SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 3630*16db6323SMichael Chan #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1 0x80UL 36316a17eb27SMichael Chan u8 port_cnt; 36326a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 36336a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 36346a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 36356a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 36366a17eb27SMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 3637894aa69aSMichael Chan #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 363811f15ed3SMichael Chan __le16 supported_speeds_force_mode; 363911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 364011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 364111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 364211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 364311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 364411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 364511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 364611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 364711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 364811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 364911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 365011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 365111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 365211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 365311f15ed3SMichael Chan __le16 supported_speeds_auto_mode; 365411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 365511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 365611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 365711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 365811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 365911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 366011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 366111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 366211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 366311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 366411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 366511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 366611f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 366711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 366811f15ed3SMichael Chan __le16 supported_speeds_eee_mode; 366911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 367011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 367111f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 367211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 367311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 367411f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 367511f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 367611f15ed3SMichael Chan __le32 tx_lpi_timer_low; 367711f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 367811f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 367911f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 368011f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 368111f15ed3SMichael Chan __le32 valid_tx_lpi_timer_high; 368211f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 368311f15ed3SMichael Chan #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 3684bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 3685bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 3686bfc6e5fbSMichael Chan __le16 supported_pam4_speeds_auto_mode; 3687bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 3688bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 3689bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 3690bfc6e5fbSMichael Chan __le16 supported_pam4_speeds_force_mode; 3691bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 3692bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 3693bfc6e5fbSMichael Chan #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 3694bfc6e5fbSMichael Chan u8 unused_0[3]; 3695bfc6e5fbSMichael Chan u8 valid; 369611f15ed3SMichael Chan }; 369711f15ed3SMichael Chan 3698894aa69aSMichael Chan /* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 369942ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_input { 370042ee18feSAjit Khaparde __le16 req_type; 370142ee18feSAjit Khaparde __le16 cmpl_ring; 370242ee18feSAjit Khaparde __le16 seq_id; 370342ee18feSAjit Khaparde __le16 target_id; 370442ee18feSAjit Khaparde __le64 resp_addr; 370542ee18feSAjit Khaparde __le32 flags; 370642ee18feSAjit Khaparde __le32 enables; 370742ee18feSAjit Khaparde #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 370842ee18feSAjit Khaparde __le16 port_id; 370942ee18feSAjit Khaparde u8 i2c_slave_addr; 371042ee18feSAjit Khaparde u8 unused_0; 371142ee18feSAjit Khaparde __le16 page_number; 371242ee18feSAjit Khaparde __le16 page_offset; 371342ee18feSAjit Khaparde u8 data_length; 371442ee18feSAjit Khaparde u8 unused_1[7]; 371542ee18feSAjit Khaparde }; 371642ee18feSAjit Khaparde 3717894aa69aSMichael Chan /* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 371842ee18feSAjit Khaparde struct hwrm_port_phy_i2c_read_output { 371942ee18feSAjit Khaparde __le16 error_code; 372042ee18feSAjit Khaparde __le16 req_type; 372142ee18feSAjit Khaparde __le16 seq_id; 372242ee18feSAjit Khaparde __le16 resp_len; 372342ee18feSAjit Khaparde __le32 data[16]; 3724894aa69aSMichael Chan u8 unused_0[7]; 372542ee18feSAjit Khaparde u8 valid; 372642ee18feSAjit Khaparde }; 372742ee18feSAjit Khaparde 37283322479eSMichael Chan /* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 37293322479eSMichael Chan struct hwrm_port_phy_mdio_write_input { 37303322479eSMichael Chan __le16 req_type; 37313322479eSMichael Chan __le16 cmpl_ring; 37323322479eSMichael Chan __le16 seq_id; 37333322479eSMichael Chan __le16 target_id; 37343322479eSMichael Chan __le64 resp_addr; 37353322479eSMichael Chan __le32 unused_0[2]; 37363322479eSMichael Chan __le16 port_id; 37373322479eSMichael Chan u8 phy_addr; 37383322479eSMichael Chan u8 dev_addr; 37393322479eSMichael Chan __le16 reg_addr; 37403322479eSMichael Chan __le16 reg_data; 37413322479eSMichael Chan u8 cl45_mdio; 37423322479eSMichael Chan u8 unused_1[7]; 37433322479eSMichael Chan }; 37443322479eSMichael Chan 37453322479eSMichael Chan /* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 37463322479eSMichael Chan struct hwrm_port_phy_mdio_write_output { 37473322479eSMichael Chan __le16 error_code; 37483322479eSMichael Chan __le16 req_type; 37493322479eSMichael Chan __le16 seq_id; 37503322479eSMichael Chan __le16 resp_len; 37513322479eSMichael Chan u8 unused_0[7]; 37523322479eSMichael Chan u8 valid; 37533322479eSMichael Chan }; 37543322479eSMichael Chan 37553322479eSMichael Chan /* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 37563322479eSMichael Chan struct hwrm_port_phy_mdio_read_input { 37573322479eSMichael Chan __le16 req_type; 37583322479eSMichael Chan __le16 cmpl_ring; 37593322479eSMichael Chan __le16 seq_id; 37603322479eSMichael Chan __le16 target_id; 37613322479eSMichael Chan __le64 resp_addr; 37623322479eSMichael Chan __le32 unused_0[2]; 37633322479eSMichael Chan __le16 port_id; 37643322479eSMichael Chan u8 phy_addr; 37653322479eSMichael Chan u8 dev_addr; 37663322479eSMichael Chan __le16 reg_addr; 37673322479eSMichael Chan u8 cl45_mdio; 37683322479eSMichael Chan u8 unused_1; 37693322479eSMichael Chan }; 37703322479eSMichael Chan 37713322479eSMichael Chan /* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 37723322479eSMichael Chan struct hwrm_port_phy_mdio_read_output { 37733322479eSMichael Chan __le16 error_code; 37743322479eSMichael Chan __le16 req_type; 37753322479eSMichael Chan __le16 seq_id; 37763322479eSMichael Chan __le16 resp_len; 37773322479eSMichael Chan __le16 reg_data; 37783322479eSMichael Chan u8 unused_0[5]; 37793322479eSMichael Chan u8 valid; 37803322479eSMichael Chan }; 37813322479eSMichael Chan 3782894aa69aSMichael Chan /* hwrm_port_led_cfg_input (size:512b/64B) */ 3783f183886cSMichael Chan struct hwrm_port_led_cfg_input { 3784f183886cSMichael Chan __le16 req_type; 3785f183886cSMichael Chan __le16 cmpl_ring; 3786f183886cSMichael Chan __le16 seq_id; 3787f183886cSMichael Chan __le16 target_id; 3788f183886cSMichael Chan __le64 resp_addr; 3789f183886cSMichael Chan __le32 enables; 3790f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 3791f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 3792f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 3793f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 3794f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 3795f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 3796f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 3797f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 3798f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 3799f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 3800f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 3801f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 3802f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 3803f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 3804f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 3805f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 3806f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 3807f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 3808f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 3809f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 3810f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 3811f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 3812f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 3813f183886cSMichael Chan #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 3814f183886cSMichael Chan __le16 port_id; 3815f183886cSMichael Chan u8 num_leds; 3816f183886cSMichael Chan u8 rsvd; 3817f183886cSMichael Chan u8 led0_id; 3818f183886cSMichael Chan u8 led0_state; 3819f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 3820f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 3821f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 3822f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 3823f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 3824894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 3825f183886cSMichael Chan u8 led0_color; 3826f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 3827f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 3828f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 3829f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 3830894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 3831f183886cSMichael Chan u8 unused_0; 3832f183886cSMichael Chan __le16 led0_blink_on; 3833f183886cSMichael Chan __le16 led0_blink_off; 3834f183886cSMichael Chan u8 led0_group_id; 3835f183886cSMichael Chan u8 rsvd0; 3836f183886cSMichael Chan u8 led1_id; 3837f183886cSMichael Chan u8 led1_state; 3838f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 3839f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 3840f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 3841f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 3842f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 3843894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 3844f183886cSMichael Chan u8 led1_color; 3845f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 3846f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 3847f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 3848f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 3849894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 3850f183886cSMichael Chan u8 unused_1; 3851f183886cSMichael Chan __le16 led1_blink_on; 3852f183886cSMichael Chan __le16 led1_blink_off; 3853f183886cSMichael Chan u8 led1_group_id; 3854f183886cSMichael Chan u8 rsvd1; 3855f183886cSMichael Chan u8 led2_id; 3856f183886cSMichael Chan u8 led2_state; 3857f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 3858f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 3859f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 3860f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 3861f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 3862894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 3863f183886cSMichael Chan u8 led2_color; 3864f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 3865f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 3866f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 3867f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 3868894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 3869f183886cSMichael Chan u8 unused_2; 3870f183886cSMichael Chan __le16 led2_blink_on; 3871f183886cSMichael Chan __le16 led2_blink_off; 3872f183886cSMichael Chan u8 led2_group_id; 3873f183886cSMichael Chan u8 rsvd2; 3874f183886cSMichael Chan u8 led3_id; 3875f183886cSMichael Chan u8 led3_state; 3876f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 3877f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 3878f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 3879f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 3880f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 3881894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 3882f183886cSMichael Chan u8 led3_color; 3883f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 3884f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 3885f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 3886f183886cSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 3887894aa69aSMichael Chan #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 3888f183886cSMichael Chan u8 unused_3; 3889f183886cSMichael Chan __le16 led3_blink_on; 3890f183886cSMichael Chan __le16 led3_blink_off; 3891f183886cSMichael Chan u8 led3_group_id; 3892f183886cSMichael Chan u8 rsvd3; 3893f183886cSMichael Chan }; 3894f183886cSMichael Chan 3895894aa69aSMichael Chan /* hwrm_port_led_cfg_output (size:128b/16B) */ 3896f183886cSMichael Chan struct hwrm_port_led_cfg_output { 3897f183886cSMichael Chan __le16 error_code; 3898f183886cSMichael Chan __le16 req_type; 3899f183886cSMichael Chan __le16 seq_id; 3900f183886cSMichael Chan __le16 resp_len; 3901894aa69aSMichael Chan u8 unused_0[7]; 3902f183886cSMichael Chan u8 valid; 3903f183886cSMichael Chan }; 3904f183886cSMichael Chan 3905894aa69aSMichael Chan /* hwrm_port_led_qcfg_input (size:192b/24B) */ 3906894aa69aSMichael Chan struct hwrm_port_led_qcfg_input { 3907894aa69aSMichael Chan __le16 req_type; 3908894aa69aSMichael Chan __le16 cmpl_ring; 3909894aa69aSMichael Chan __le16 seq_id; 3910894aa69aSMichael Chan __le16 target_id; 3911894aa69aSMichael Chan __le64 resp_addr; 3912894aa69aSMichael Chan __le16 port_id; 3913894aa69aSMichael Chan u8 unused_0[6]; 3914894aa69aSMichael Chan }; 3915894aa69aSMichael Chan 3916894aa69aSMichael Chan /* hwrm_port_led_qcfg_output (size:448b/56B) */ 3917894aa69aSMichael Chan struct hwrm_port_led_qcfg_output { 3918894aa69aSMichael Chan __le16 error_code; 3919894aa69aSMichael Chan __le16 req_type; 3920894aa69aSMichael Chan __le16 seq_id; 3921894aa69aSMichael Chan __le16 resp_len; 3922894aa69aSMichael Chan u8 num_leds; 3923894aa69aSMichael Chan u8 led0_id; 3924894aa69aSMichael Chan u8 led0_type; 3925894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 3926894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 3927894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 3928894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 3929894aa69aSMichael Chan u8 led0_state; 3930894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 3931894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 3932894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 3933894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 3934894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 3935894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 3936894aa69aSMichael Chan u8 led0_color; 3937894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 3938894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 3939894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 3940894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 3941894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 3942894aa69aSMichael Chan u8 unused_0; 3943894aa69aSMichael Chan __le16 led0_blink_on; 3944894aa69aSMichael Chan __le16 led0_blink_off; 3945894aa69aSMichael Chan u8 led0_group_id; 3946894aa69aSMichael Chan u8 led1_id; 3947894aa69aSMichael Chan u8 led1_type; 3948894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 3949894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 3950894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 3951894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 3952894aa69aSMichael Chan u8 led1_state; 3953894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 3954894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 3955894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 3956894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 3957894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 3958894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 3959894aa69aSMichael Chan u8 led1_color; 3960894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 3961894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 3962894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 3963894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 3964894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 3965894aa69aSMichael Chan u8 unused_1; 3966894aa69aSMichael Chan __le16 led1_blink_on; 3967894aa69aSMichael Chan __le16 led1_blink_off; 3968894aa69aSMichael Chan u8 led1_group_id; 3969894aa69aSMichael Chan u8 led2_id; 3970894aa69aSMichael Chan u8 led2_type; 3971894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 3972894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 3973894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 3974894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 3975894aa69aSMichael Chan u8 led2_state; 3976894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 3977894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 3978894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 3979894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 3980894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 3981894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 3982894aa69aSMichael Chan u8 led2_color; 3983894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 3984894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 3985894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 3986894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 3987894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 3988894aa69aSMichael Chan u8 unused_2; 3989894aa69aSMichael Chan __le16 led2_blink_on; 3990894aa69aSMichael Chan __le16 led2_blink_off; 3991894aa69aSMichael Chan u8 led2_group_id; 3992894aa69aSMichael Chan u8 led3_id; 3993894aa69aSMichael Chan u8 led3_type; 3994894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 3995894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 3996894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 3997894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 3998894aa69aSMichael Chan u8 led3_state; 3999894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 4000894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 4001894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 4002894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 4003894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 4004894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 4005894aa69aSMichael Chan u8 led3_color; 4006894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 4007894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 4008894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 4009894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 4010894aa69aSMichael Chan #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 4011894aa69aSMichael Chan u8 unused_3; 4012894aa69aSMichael Chan __le16 led3_blink_on; 4013894aa69aSMichael Chan __le16 led3_blink_off; 4014894aa69aSMichael Chan u8 led3_group_id; 4015894aa69aSMichael Chan u8 unused_4[6]; 4016894aa69aSMichael Chan u8 valid; 4017894aa69aSMichael Chan }; 4018894aa69aSMichael Chan 4019894aa69aSMichael Chan /* hwrm_port_led_qcaps_input (size:192b/24B) */ 4020f183886cSMichael Chan struct hwrm_port_led_qcaps_input { 4021f183886cSMichael Chan __le16 req_type; 4022f183886cSMichael Chan __le16 cmpl_ring; 4023f183886cSMichael Chan __le16 seq_id; 4024f183886cSMichael Chan __le16 target_id; 4025f183886cSMichael Chan __le64 resp_addr; 4026f183886cSMichael Chan __le16 port_id; 4027894aa69aSMichael Chan u8 unused_0[6]; 4028f183886cSMichael Chan }; 4029f183886cSMichael Chan 4030894aa69aSMichael Chan /* hwrm_port_led_qcaps_output (size:384b/48B) */ 4031f183886cSMichael Chan struct hwrm_port_led_qcaps_output { 4032f183886cSMichael Chan __le16 error_code; 4033f183886cSMichael Chan __le16 req_type; 4034f183886cSMichael Chan __le16 seq_id; 4035f183886cSMichael Chan __le16 resp_len; 4036f183886cSMichael Chan u8 num_leds; 4037894aa69aSMichael Chan u8 unused[3]; 4038f183886cSMichael Chan u8 led0_id; 4039f183886cSMichael Chan u8 led0_type; 4040f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 4041f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 4042f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 4043894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 4044f183886cSMichael Chan u8 led0_group_id; 4045894aa69aSMichael Chan u8 unused_0; 4046f183886cSMichael Chan __le16 led0_state_caps; 4047f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 4048f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 4049f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 4050f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4051f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4052f183886cSMichael Chan __le16 led0_color_caps; 4053f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 4054f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4055f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4056f183886cSMichael Chan u8 led1_id; 4057f183886cSMichael Chan u8 led1_type; 4058f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 4059f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 4060f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 4061894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 4062f183886cSMichael Chan u8 led1_group_id; 4063894aa69aSMichael Chan u8 unused_1; 4064f183886cSMichael Chan __le16 led1_state_caps; 4065f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 4066f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 4067f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 4068f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4069f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4070f183886cSMichael Chan __le16 led1_color_caps; 4071f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 4072f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4073f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4074f183886cSMichael Chan u8 led2_id; 4075f183886cSMichael Chan u8 led2_type; 4076f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 4077f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 4078f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 4079894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 4080f183886cSMichael Chan u8 led2_group_id; 4081894aa69aSMichael Chan u8 unused_2; 4082f183886cSMichael Chan __le16 led2_state_caps; 4083f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 4084f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 4085f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 4086f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4087f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4088f183886cSMichael Chan __le16 led2_color_caps; 4089f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 4090f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4091f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4092f183886cSMichael Chan u8 led3_id; 4093f183886cSMichael Chan u8 led3_type; 4094f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 4095f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 4096f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 4097894aa69aSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 4098f183886cSMichael Chan u8 led3_group_id; 4099894aa69aSMichael Chan u8 unused_3; 4100f183886cSMichael Chan __le16 led3_state_caps; 4101f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 4102f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 4103f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 4104f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 4105f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 4106f183886cSMichael Chan __le16 led3_color_caps; 4107f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 4108f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 4109f183886cSMichael Chan #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 4110894aa69aSMichael Chan u8 unused_4[3]; 4111f183886cSMichael Chan u8 valid; 4112f183886cSMichael Chan }; 4113f183886cSMichael Chan 4114894aa69aSMichael Chan /* hwrm_queue_qportcfg_input (size:192b/24B) */ 4115c0c050c5SMichael Chan struct hwrm_queue_qportcfg_input { 4116c0c050c5SMichael Chan __le16 req_type; 4117c0c050c5SMichael Chan __le16 cmpl_ring; 4118c0c050c5SMichael Chan __le16 seq_id; 4119c0c050c5SMichael Chan __le16 target_id; 4120c0c050c5SMichael Chan __le64 resp_addr; 4121c0c050c5SMichael Chan __le32 flags; 4122c0c050c5SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 4123441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 4124441cabbbSMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 412511f15ed3SMichael Chan #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 4126c0c050c5SMichael Chan __le16 port_id; 4127d4f52de0SMichael Chan u8 drv_qmap_cap; 4128d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 4129d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 4130d4f52de0SMichael Chan #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 4131d4f52de0SMichael Chan u8 unused_0; 4132c0c050c5SMichael Chan }; 4133c0c050c5SMichael Chan 4134bfc6e5fbSMichael Chan /* hwrm_queue_qportcfg_output (size:1344b/168B) */ 4135c0c050c5SMichael Chan struct hwrm_queue_qportcfg_output { 4136c0c050c5SMichael Chan __le16 error_code; 4137c0c050c5SMichael Chan __le16 req_type; 4138c0c050c5SMichael Chan __le16 seq_id; 4139c0c050c5SMichael Chan __le16 resp_len; 4140c0c050c5SMichael Chan u8 max_configurable_queues; 4141c0c050c5SMichael Chan u8 max_configurable_lossless_queues; 4142c0c050c5SMichael Chan u8 queue_cfg_allowed; 4143441cabbbSMichael Chan u8 queue_cfg_info; 4144441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4145c0c050c5SMichael Chan u8 queue_pfcenable_cfg_allowed; 4146c0c050c5SMichael Chan u8 queue_pri2cos_cfg_allowed; 4147c0c050c5SMichael Chan u8 queue_cos2bw_cfg_allowed; 4148c0c050c5SMichael Chan u8 queue_id0; 4149c0c050c5SMichael Chan u8 queue_id0_service_profile; 4150441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 41516fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 4152d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4153d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4154d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4155441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 4156894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 4157c0c050c5SMichael Chan u8 queue_id1; 4158c0c050c5SMichael Chan u8 queue_id1_service_profile; 4159441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 41606fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 4161d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4162d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4163d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4164441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 4165894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 4166c0c050c5SMichael Chan u8 queue_id2; 4167c0c050c5SMichael Chan u8 queue_id2_service_profile; 4168441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 41696fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 4170d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4171d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4172d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4173441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 4174894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 4175c0c050c5SMichael Chan u8 queue_id3; 4176c0c050c5SMichael Chan u8 queue_id3_service_profile; 4177441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 41786fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 4179d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4180d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4181d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4182441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 4183894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 4184c0c050c5SMichael Chan u8 queue_id4; 4185c0c050c5SMichael Chan u8 queue_id4_service_profile; 4186441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 41876fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 4188d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4189d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4190d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4191441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 4192894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 4193c0c050c5SMichael Chan u8 queue_id5; 4194c0c050c5SMichael Chan u8 queue_id5_service_profile; 4195441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 41966fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 4197d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4198d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4199d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4200441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 4201894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 4202c0c050c5SMichael Chan u8 queue_id6; 4203c0c050c5SMichael Chan u8 queue_id6_service_profile; 4204441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 42056fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 4206d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4207d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4208d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4209441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 4210894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 4211c0c050c5SMichael Chan u8 queue_id7; 4212c0c050c5SMichael Chan u8 queue_id7_service_profile; 4213441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 42146fc92c33SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 4215d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 4216d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 4217d4f52de0SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4218441cabbbSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4219894aa69aSMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4220*16db6323SMichael Chan u8 queue_id0_service_profile_type; 4221*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4222*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4223*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4224bfc6e5fbSMichael Chan char qid0_name[16]; 4225bfc6e5fbSMichael Chan char qid1_name[16]; 4226bfc6e5fbSMichael Chan char qid2_name[16]; 4227bfc6e5fbSMichael Chan char qid3_name[16]; 4228bfc6e5fbSMichael Chan char qid4_name[16]; 4229bfc6e5fbSMichael Chan char qid5_name[16]; 4230bfc6e5fbSMichael Chan char qid6_name[16]; 4231bfc6e5fbSMichael Chan char qid7_name[16]; 4232*16db6323SMichael Chan u8 queue_id1_service_profile_type; 4233*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4234*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4235*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4236*16db6323SMichael Chan u8 queue_id2_service_profile_type; 4237*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4238*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4239*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4240*16db6323SMichael Chan u8 queue_id3_service_profile_type; 4241*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4242*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4243*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4244*16db6323SMichael Chan u8 queue_id4_service_profile_type; 4245*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4246*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4247*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4248*16db6323SMichael Chan u8 queue_id5_service_profile_type; 4249*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4250*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4251*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4252*16db6323SMichael Chan u8 queue_id6_service_profile_type; 4253*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4254*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4255*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4256*16db6323SMichael Chan u8 queue_id7_service_profile_type; 4257*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4258*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4259*16db6323SMichael Chan #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4260bfc6e5fbSMichael Chan u8 valid; 4261bfc6e5fbSMichael Chan }; 4262bfc6e5fbSMichael Chan 4263bfc6e5fbSMichael Chan /* hwrm_queue_qcfg_input (size:192b/24B) */ 4264bfc6e5fbSMichael Chan struct hwrm_queue_qcfg_input { 4265bfc6e5fbSMichael Chan __le16 req_type; 4266bfc6e5fbSMichael Chan __le16 cmpl_ring; 4267bfc6e5fbSMichael Chan __le16 seq_id; 4268bfc6e5fbSMichael Chan __le16 target_id; 4269bfc6e5fbSMichael Chan __le64 resp_addr; 4270bfc6e5fbSMichael Chan __le32 flags; 4271bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 4272bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4273bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 4274bfc6e5fbSMichael Chan #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 4275bfc6e5fbSMichael Chan __le32 queue_id; 4276bfc6e5fbSMichael Chan }; 4277bfc6e5fbSMichael Chan 4278bfc6e5fbSMichael Chan /* hwrm_queue_qcfg_output (size:128b/16B) */ 4279bfc6e5fbSMichael Chan struct hwrm_queue_qcfg_output { 4280bfc6e5fbSMichael Chan __le16 error_code; 4281bfc6e5fbSMichael Chan __le16 req_type; 4282bfc6e5fbSMichael Chan __le16 seq_id; 4283bfc6e5fbSMichael Chan __le16 resp_len; 4284bfc6e5fbSMichael Chan __le32 queue_len; 4285bfc6e5fbSMichael Chan u8 service_profile; 4286bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 4287bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 4288bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 4289bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 4290bfc6e5fbSMichael Chan u8 queue_cfg_info; 4291bfc6e5fbSMichael Chan #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4292bfc6e5fbSMichael Chan u8 unused_0; 4293c0c050c5SMichael Chan u8 valid; 4294c0c050c5SMichael Chan }; 4295c0c050c5SMichael Chan 4296894aa69aSMichael Chan /* hwrm_queue_cfg_input (size:320b/40B) */ 4297c0c050c5SMichael Chan struct hwrm_queue_cfg_input { 4298c0c050c5SMichael Chan __le16 req_type; 4299c0c050c5SMichael Chan __le16 cmpl_ring; 4300c0c050c5SMichael Chan __le16 seq_id; 4301c0c050c5SMichael Chan __le16 target_id; 4302c0c050c5SMichael Chan __le64 resp_addr; 4303c0c050c5SMichael Chan __le32 flags; 4304441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4305441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 4306441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 4307441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 4308441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4309441cabbbSMichael Chan #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 4310c0c050c5SMichael Chan __le32 enables; 4311c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 4312c0c050c5SMichael Chan #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 4313c0c050c5SMichael Chan __le32 queue_id; 4314c0c050c5SMichael Chan __le32 dflt_len; 4315c0c050c5SMichael Chan u8 service_profile; 4316441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 4317441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 4318441cabbbSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 4319894aa69aSMichael Chan #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 4320c0c050c5SMichael Chan u8 unused_0[7]; 4321c0c050c5SMichael Chan }; 4322c0c050c5SMichael Chan 4323894aa69aSMichael Chan /* hwrm_queue_cfg_output (size:128b/16B) */ 4324c0c050c5SMichael Chan struct hwrm_queue_cfg_output { 4325c0c050c5SMichael Chan __le16 error_code; 4326c0c050c5SMichael Chan __le16 req_type; 4327c0c050c5SMichael Chan __le16 seq_id; 4328c0c050c5SMichael Chan __le16 resp_len; 4329894aa69aSMichael Chan u8 unused_0[7]; 4330c0c050c5SMichael Chan u8 valid; 4331c0c050c5SMichael Chan }; 4332c0c050c5SMichael Chan 4333894aa69aSMichael Chan /* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 433487c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_input { 433587c374deSMichael Chan __le16 req_type; 433687c374deSMichael Chan __le16 cmpl_ring; 433787c374deSMichael Chan __le16 seq_id; 433887c374deSMichael Chan __le16 target_id; 433987c374deSMichael Chan __le64 resp_addr; 434087c374deSMichael Chan __le16 port_id; 4341894aa69aSMichael Chan u8 unused_0[6]; 434287c374deSMichael Chan }; 434387c374deSMichael Chan 4344894aa69aSMichael Chan /* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 434587c374deSMichael Chan struct hwrm_queue_pfcenable_qcfg_output { 434687c374deSMichael Chan __le16 error_code; 434787c374deSMichael Chan __le16 req_type; 434887c374deSMichael Chan __le16 seq_id; 434987c374deSMichael Chan __le16 resp_len; 435087c374deSMichael Chan __le32 flags; 435187c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 435287c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 435387c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 435487c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 435587c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 435687c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 435787c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 435887c374deSMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 4359460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4360460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4361460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4362460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4363460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4364460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4365460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4366460c2577SMichael Chan #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4367894aa69aSMichael Chan u8 unused_0[3]; 436887c374deSMichael Chan u8 valid; 436987c374deSMichael Chan }; 437087c374deSMichael Chan 4371894aa69aSMichael Chan /* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 4372c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_input { 4373c0c050c5SMichael Chan __le16 req_type; 4374c0c050c5SMichael Chan __le16 cmpl_ring; 4375c0c050c5SMichael Chan __le16 seq_id; 4376c0c050c5SMichael Chan __le16 target_id; 4377c0c050c5SMichael Chan __le64 resp_addr; 4378c193554eSMichael Chan __le32 flags; 4379c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 4380c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 4381c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 4382c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 4383c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 4384c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 4385c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 4386c193554eSMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 4387460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 4388460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 4389460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 4390460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 4391460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 4392460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 4393460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 4394460c2577SMichael Chan #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 4395c0c050c5SMichael Chan __le16 port_id; 4396894aa69aSMichael Chan u8 unused_0[2]; 4397c0c050c5SMichael Chan }; 4398c0c050c5SMichael Chan 4399894aa69aSMichael Chan /* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 4400c0c050c5SMichael Chan struct hwrm_queue_pfcenable_cfg_output { 4401c0c050c5SMichael Chan __le16 error_code; 4402c0c050c5SMichael Chan __le16 req_type; 4403c0c050c5SMichael Chan __le16 seq_id; 4404c0c050c5SMichael Chan __le16 resp_len; 4405894aa69aSMichael Chan u8 unused_0[7]; 4406c0c050c5SMichael Chan u8 valid; 4407c0c050c5SMichael Chan }; 4408c0c050c5SMichael Chan 4409894aa69aSMichael Chan /* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 441087c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_input { 441187c374deSMichael Chan __le16 req_type; 441287c374deSMichael Chan __le16 cmpl_ring; 441387c374deSMichael Chan __le16 seq_id; 441487c374deSMichael Chan __le16 target_id; 441587c374deSMichael Chan __le64 resp_addr; 441687c374deSMichael Chan __le32 flags; 441787c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 4418894aa69aSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 4419894aa69aSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 442087c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 442187c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 442287c374deSMichael Chan u8 port_id; 442387c374deSMichael Chan u8 unused_0[3]; 442487c374deSMichael Chan }; 442587c374deSMichael Chan 4426894aa69aSMichael Chan /* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 442787c374deSMichael Chan struct hwrm_queue_pri2cos_qcfg_output { 442887c374deSMichael Chan __le16 error_code; 442987c374deSMichael Chan __le16 req_type; 443087c374deSMichael Chan __le16 seq_id; 443187c374deSMichael Chan __le16 resp_len; 443287c374deSMichael Chan u8 pri0_cos_queue_id; 443387c374deSMichael Chan u8 pri1_cos_queue_id; 443487c374deSMichael Chan u8 pri2_cos_queue_id; 443587c374deSMichael Chan u8 pri3_cos_queue_id; 443687c374deSMichael Chan u8 pri4_cos_queue_id; 443787c374deSMichael Chan u8 pri5_cos_queue_id; 443887c374deSMichael Chan u8 pri6_cos_queue_id; 443987c374deSMichael Chan u8 pri7_cos_queue_id; 444087c374deSMichael Chan u8 queue_cfg_info; 444187c374deSMichael Chan #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 4442894aa69aSMichael Chan u8 unused_0[6]; 444387c374deSMichael Chan u8 valid; 444487c374deSMichael Chan }; 444587c374deSMichael Chan 4446894aa69aSMichael Chan /* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 4447c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_input { 4448c0c050c5SMichael Chan __le16 req_type; 4449c0c050c5SMichael Chan __le16 cmpl_ring; 4450c0c050c5SMichael Chan __le16 seq_id; 4451c0c050c5SMichael Chan __le16 target_id; 4452c0c050c5SMichael Chan __le64 resp_addr; 4453c0c050c5SMichael Chan __le32 flags; 4454441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 4455441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 4456894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 4457894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 4458894aa69aSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 4459441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 4460441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 4461c0c050c5SMichael Chan __le32 enables; 4462441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 4463441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 4464441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 4465441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 4466441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 4467441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 4468441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 4469441cabbbSMichael Chan #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 4470c0c050c5SMichael Chan u8 port_id; 4471c193554eSMichael Chan u8 pri0_cos_queue_id; 4472c193554eSMichael Chan u8 pri1_cos_queue_id; 4473c193554eSMichael Chan u8 pri2_cos_queue_id; 4474c193554eSMichael Chan u8 pri3_cos_queue_id; 4475c193554eSMichael Chan u8 pri4_cos_queue_id; 4476c193554eSMichael Chan u8 pri5_cos_queue_id; 4477c193554eSMichael Chan u8 pri6_cos_queue_id; 4478c193554eSMichael Chan u8 pri7_cos_queue_id; 4479c0c050c5SMichael Chan u8 unused_0[7]; 4480c0c050c5SMichael Chan }; 4481c0c050c5SMichael Chan 4482894aa69aSMichael Chan /* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 4483c0c050c5SMichael Chan struct hwrm_queue_pri2cos_cfg_output { 4484c0c050c5SMichael Chan __le16 error_code; 4485c0c050c5SMichael Chan __le16 req_type; 4486c0c050c5SMichael Chan __le16 seq_id; 4487c0c050c5SMichael Chan __le16 resp_len; 4488894aa69aSMichael Chan u8 unused_0[7]; 4489c0c050c5SMichael Chan u8 valid; 4490c0c050c5SMichael Chan }; 4491c0c050c5SMichael Chan 4492894aa69aSMichael Chan /* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 449387c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_input { 449487c374deSMichael Chan __le16 req_type; 449587c374deSMichael Chan __le16 cmpl_ring; 449687c374deSMichael Chan __le16 seq_id; 449787c374deSMichael Chan __le16 target_id; 449887c374deSMichael Chan __le64 resp_addr; 449987c374deSMichael Chan __le16 port_id; 4500894aa69aSMichael Chan u8 unused_0[6]; 450187c374deSMichael Chan }; 450287c374deSMichael Chan 4503894aa69aSMichael Chan /* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 450487c374deSMichael Chan struct hwrm_queue_cos2bw_qcfg_output { 450587c374deSMichael Chan __le16 error_code; 450687c374deSMichael Chan __le16 req_type; 450787c374deSMichael Chan __le16 seq_id; 450887c374deSMichael Chan __le16 resp_len; 450987c374deSMichael Chan u8 queue_id0; 451087c374deSMichael Chan u8 unused_0; 451187c374deSMichael Chan __le16 unused_1; 451287c374deSMichael Chan __le32 queue_id0_min_bw; 451387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 451487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4515bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4516bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4517bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4518bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 451987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 452087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4521bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4522bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4523bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4524bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 452587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 452687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 452787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 452887c374deSMichael Chan __le32 queue_id0_max_bw; 452987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 453087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4531bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4532bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4533bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4534bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 453587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 453687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4537bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4538bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4539bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4540bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 454187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 454287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 454387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 454487c374deSMichael Chan u8 queue_id0_tsa_assign; 454587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 454687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 454787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 454887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 454987c374deSMichael Chan u8 queue_id0_pri_lvl; 455087c374deSMichael Chan u8 queue_id0_bw_weight; 455187c374deSMichael Chan u8 queue_id1; 455287c374deSMichael Chan __le32 queue_id1_min_bw; 455387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 455487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4555bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4556bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4557bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4558bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 455987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 456087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4561bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4562bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4563bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4564bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 456587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 456687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 456787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 456887c374deSMichael Chan __le32 queue_id1_max_bw; 456987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 457087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4571bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4572bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4573bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4574bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 457587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 457687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4577bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4578bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4579bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4580bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 458187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 458287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 458387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 458487c374deSMichael Chan u8 queue_id1_tsa_assign; 458587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 458687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 458787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 458887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 458987c374deSMichael Chan u8 queue_id1_pri_lvl; 459087c374deSMichael Chan u8 queue_id1_bw_weight; 459187c374deSMichael Chan u8 queue_id2; 459287c374deSMichael Chan __le32 queue_id2_min_bw; 459387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 459487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4595bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4596bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4597bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4598bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 459987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 460087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4601bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4602bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4603bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4604bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 460587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 460687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 460787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 460887c374deSMichael Chan __le32 queue_id2_max_bw; 460987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 461087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4611bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4612bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4613bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4614bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 461587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 461687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4617bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4618bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4619bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4620bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 462187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 462287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 462387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 462487c374deSMichael Chan u8 queue_id2_tsa_assign; 462587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 462687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 462787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 462887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 462987c374deSMichael Chan u8 queue_id2_pri_lvl; 463087c374deSMichael Chan u8 queue_id2_bw_weight; 463187c374deSMichael Chan u8 queue_id3; 463287c374deSMichael Chan __le32 queue_id3_min_bw; 463387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 463487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4635bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4636bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4637bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4638bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 463987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 464087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4641bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4642bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4643bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4644bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 464587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 464687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 464787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 464887c374deSMichael Chan __le32 queue_id3_max_bw; 464987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 465087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4651bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4652bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4653bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4654bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 465587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 465687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 4657bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4658bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4659bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4660bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 466187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 466287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 466387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 466487c374deSMichael Chan u8 queue_id3_tsa_assign; 466587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 466687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 466787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 466887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 466987c374deSMichael Chan u8 queue_id3_pri_lvl; 467087c374deSMichael Chan u8 queue_id3_bw_weight; 467187c374deSMichael Chan u8 queue_id4; 467287c374deSMichael Chan __le32 queue_id4_min_bw; 467387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 467487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 4675bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 4676bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 4677bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 4678bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 467987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 468087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 4681bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4682bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4683bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4684bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 468587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 468687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 468787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 468887c374deSMichael Chan __le32 queue_id4_max_bw; 468987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 469087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 4691bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 4692bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 4693bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 4694bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 469587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 469687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 4697bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4698bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4699bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4700bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 470187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 470287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 470387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 470487c374deSMichael Chan u8 queue_id4_tsa_assign; 470587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 470687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 470787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 470887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 470987c374deSMichael Chan u8 queue_id4_pri_lvl; 471087c374deSMichael Chan u8 queue_id4_bw_weight; 471187c374deSMichael Chan u8 queue_id5; 471287c374deSMichael Chan __le32 queue_id5_min_bw; 471387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 471487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 4715bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 4716bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 4717bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 4718bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 471987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 472087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 4721bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4722bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4723bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4724bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 472587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 472687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 472787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 472887c374deSMichael Chan __le32 queue_id5_max_bw; 472987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 473087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 4731bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 4732bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 4733bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 4734bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 473587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 473687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 4737bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4738bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4739bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4740bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 474187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 474287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 474387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 474487c374deSMichael Chan u8 queue_id5_tsa_assign; 474587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 474687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 474787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 474887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 474987c374deSMichael Chan u8 queue_id5_pri_lvl; 475087c374deSMichael Chan u8 queue_id5_bw_weight; 475187c374deSMichael Chan u8 queue_id6; 475287c374deSMichael Chan __le32 queue_id6_min_bw; 475387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 475487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 4755bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 4756bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 4757bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 4758bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 475987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 476087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 4761bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4762bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4763bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4764bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 476587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 476687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 476787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 476887c374deSMichael Chan __le32 queue_id6_max_bw; 476987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 477087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 4771bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 4772bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 4773bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 4774bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 477587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 477687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 4777bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4778bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4779bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4780bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 478187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 478287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 478387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 478487c374deSMichael Chan u8 queue_id6_tsa_assign; 478587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 478687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 478787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 478887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 478987c374deSMichael Chan u8 queue_id6_pri_lvl; 479087c374deSMichael Chan u8 queue_id6_bw_weight; 479187c374deSMichael Chan u8 queue_id7; 479287c374deSMichael Chan __le32 queue_id7_min_bw; 479387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 479487c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 4795bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 4796bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 4797bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 4798bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 479987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 480087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 4801bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4802bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4803bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4804bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 480587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 480687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 480787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 480887c374deSMichael Chan __le32 queue_id7_max_bw; 480987c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 481087c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 4811bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 4812bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 4813bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 4814bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 481587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 481687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 4817bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4818bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4819bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4820bac9a7e0SMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 482187c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 482287c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 482387c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 482487c374deSMichael Chan u8 queue_id7_tsa_assign; 482587c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 482687c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 482787c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 482887c374deSMichael Chan #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 482987c374deSMichael Chan u8 queue_id7_pri_lvl; 483087c374deSMichael Chan u8 queue_id7_bw_weight; 4831894aa69aSMichael Chan u8 unused_2[4]; 483287c374deSMichael Chan u8 valid; 483387c374deSMichael Chan }; 483487c374deSMichael Chan 4835894aa69aSMichael Chan /* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 4836c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_input { 4837c0c050c5SMichael Chan __le16 req_type; 4838c0c050c5SMichael Chan __le16 cmpl_ring; 4839c0c050c5SMichael Chan __le16 seq_id; 4840c0c050c5SMichael Chan __le16 target_id; 4841c0c050c5SMichael Chan __le64 resp_addr; 4842c0c050c5SMichael Chan __le32 flags; 4843c0c050c5SMichael Chan __le32 enables; 4844c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 4845c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 4846c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 4847c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 4848c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 4849c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 4850c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 4851c0c050c5SMichael Chan #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 4852c0c050c5SMichael Chan __le16 port_id; 4853c0c050c5SMichael Chan u8 queue_id0; 4854c0c050c5SMichael Chan u8 unused_0; 4855c0c050c5SMichael Chan __le32 queue_id0_min_bw; 4856441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4857441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 4858bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 4859bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 4860bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 4861bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 4862441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4863441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 4864bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4865bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4866bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4867bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4868441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4869441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4870441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 4871c0c050c5SMichael Chan __le32 queue_id0_max_bw; 4872441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4873441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 4874bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 4875bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 4876bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 4877bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 4878441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4879441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 4880bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4881bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4882bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4883bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4884441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4885441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4886441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 4887c0c050c5SMichael Chan u8 queue_id0_tsa_assign; 4888441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 4889441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 4890441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4891441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 4892c0c050c5SMichael Chan u8 queue_id0_pri_lvl; 4893c0c050c5SMichael Chan u8 queue_id0_bw_weight; 4894c0c050c5SMichael Chan u8 queue_id1; 4895c0c050c5SMichael Chan __le32 queue_id1_min_bw; 4896441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4897441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 4898bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 4899bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 4900bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 4901bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 4902441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4903441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 4904bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4905bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4906bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4907bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4908441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4909441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4910441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 4911c0c050c5SMichael Chan __le32 queue_id1_max_bw; 4912441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4913441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 4914bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 4915bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 4916bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 4917bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 4918441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4919441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 4920bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4921bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4922bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4923bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4924441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4925441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4926441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 4927c0c050c5SMichael Chan u8 queue_id1_tsa_assign; 4928441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 4929441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 4930441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4931441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 4932c0c050c5SMichael Chan u8 queue_id1_pri_lvl; 4933c0c050c5SMichael Chan u8 queue_id1_bw_weight; 4934c0c050c5SMichael Chan u8 queue_id2; 4935c0c050c5SMichael Chan __le32 queue_id2_min_bw; 4936441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4937441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 4938bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 4939bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 4940bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 4941bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 4942441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4943441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 4944bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4945bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4946bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4947bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4948441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4949441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4950441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 4951c0c050c5SMichael Chan __le32 queue_id2_max_bw; 4952441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4953441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 4954bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 4955bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 4956bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 4957bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 4958441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4959441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 4960bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4961bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4962bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4963bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4964441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4965441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4966441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 4967c0c050c5SMichael Chan u8 queue_id2_tsa_assign; 4968441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 4969441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 4970441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 4971441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 4972c0c050c5SMichael Chan u8 queue_id2_pri_lvl; 4973c0c050c5SMichael Chan u8 queue_id2_bw_weight; 4974c0c050c5SMichael Chan u8 queue_id3; 4975c0c050c5SMichael Chan __le32 queue_id3_min_bw; 4976441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 4977441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 4978bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 4979bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 4980bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 4981bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 4982441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4983441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 4984bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4985bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4986bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4987bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4988441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4989441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4990441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 4991c0c050c5SMichael Chan __le32 queue_id3_max_bw; 4992441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 4993441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 4994bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 4995bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 4996bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 4997bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 4998441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4999441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 5000bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5001bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5002bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5003bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5004441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5005441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5006441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 5007c0c050c5SMichael Chan u8 queue_id3_tsa_assign; 5008441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 5009441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 5010441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5011441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 5012c0c050c5SMichael Chan u8 queue_id3_pri_lvl; 5013c0c050c5SMichael Chan u8 queue_id3_bw_weight; 5014c0c050c5SMichael Chan u8 queue_id4; 5015c0c050c5SMichael Chan __le32 queue_id4_min_bw; 5016441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5017441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 5018bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 5019bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 5020bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 5021bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 5022441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5023441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 5024bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5025bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5026bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5027bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5028441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5029441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5030441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 5031c0c050c5SMichael Chan __le32 queue_id4_max_bw; 5032441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5033441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 5034bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 5035bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 5036bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 5037bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 5038441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5039441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 5040bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5041bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5042bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5043bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5044441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5045441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5046441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 5047c0c050c5SMichael Chan u8 queue_id4_tsa_assign; 5048441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 5049441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 5050441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5051441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 5052c0c050c5SMichael Chan u8 queue_id4_pri_lvl; 5053c0c050c5SMichael Chan u8 queue_id4_bw_weight; 5054c0c050c5SMichael Chan u8 queue_id5; 5055c0c050c5SMichael Chan __le32 queue_id5_min_bw; 5056441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5057441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 5058bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 5059bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 5060bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 5061bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 5062441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5063441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 5064bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5065bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5066bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5067bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5068441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5069441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5070441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 5071c0c050c5SMichael Chan __le32 queue_id5_max_bw; 5072441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5073441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 5074bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 5075bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 5076bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 5077bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 5078441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5079441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 5080bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5081bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5082bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5083bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5084441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5085441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5086441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 5087c0c050c5SMichael Chan u8 queue_id5_tsa_assign; 5088441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 5089441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 5090441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5091441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 5092c0c050c5SMichael Chan u8 queue_id5_pri_lvl; 5093c0c050c5SMichael Chan u8 queue_id5_bw_weight; 5094c0c050c5SMichael Chan u8 queue_id6; 5095c0c050c5SMichael Chan __le32 queue_id6_min_bw; 5096441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5097441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 5098bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 5099bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 5100bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 5101bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 5102441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5103441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 5104bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5105bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5106bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5107bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5108441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5109441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5110441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 5111c0c050c5SMichael Chan __le32 queue_id6_max_bw; 5112441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5113441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 5114bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 5115bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 5116bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 5117bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 5118441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5119441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 5120bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5121bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5122bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5123bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5124441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5125441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5126441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 5127c0c050c5SMichael Chan u8 queue_id6_tsa_assign; 5128441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 5129441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 5130441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5131441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 5132c0c050c5SMichael Chan u8 queue_id6_pri_lvl; 5133c0c050c5SMichael Chan u8 queue_id6_bw_weight; 5134c0c050c5SMichael Chan u8 queue_id7; 5135c0c050c5SMichael Chan __le32 queue_id7_min_bw; 5136441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 5137441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 5138bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 5139bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 5140bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 5141bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 5142441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5143441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 5144bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5145bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5146bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5147bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5148441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5149441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5150441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 5151c0c050c5SMichael Chan __le32 queue_id7_max_bw; 5152441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5153441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 5154bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 5155bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 5156bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 5157bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 5158441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5159441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 5160bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5161bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5162bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5163bac9a7e0SMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5164441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5165441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5166441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 5167c0c050c5SMichael Chan u8 queue_id7_tsa_assign; 5168441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 5169441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 5170441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 5171441cabbbSMichael Chan #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 5172c0c050c5SMichael Chan u8 queue_id7_pri_lvl; 5173c0c050c5SMichael Chan u8 queue_id7_bw_weight; 5174c0c050c5SMichael Chan u8 unused_1[5]; 5175c0c050c5SMichael Chan }; 5176c0c050c5SMichael Chan 5177894aa69aSMichael Chan /* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 5178c0c050c5SMichael Chan struct hwrm_queue_cos2bw_cfg_output { 5179c0c050c5SMichael Chan __le16 error_code; 5180c0c050c5SMichael Chan __le16 req_type; 5181c0c050c5SMichael Chan __le16 seq_id; 5182c0c050c5SMichael Chan __le16 resp_len; 5183894aa69aSMichael Chan u8 unused_0[7]; 5184c0c050c5SMichael Chan u8 valid; 5185c0c050c5SMichael Chan }; 5186c0c050c5SMichael Chan 5187894aa69aSMichael Chan /* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 5188acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_input { 5189acb20054SMichael Chan __le16 req_type; 5190acb20054SMichael Chan __le16 cmpl_ring; 5191acb20054SMichael Chan __le16 seq_id; 5192acb20054SMichael Chan __le16 target_id; 5193acb20054SMichael Chan __le64 resp_addr; 5194acb20054SMichael Chan u8 port_id; 5195acb20054SMichael Chan u8 unused_0[7]; 5196acb20054SMichael Chan }; 5197acb20054SMichael Chan 5198894aa69aSMichael Chan /* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 5199acb20054SMichael Chan struct hwrm_queue_dscp_qcaps_output { 5200acb20054SMichael Chan __le16 error_code; 5201acb20054SMichael Chan __le16 req_type; 5202acb20054SMichael Chan __le16 seq_id; 5203acb20054SMichael Chan __le16 resp_len; 5204acb20054SMichael Chan u8 num_dscp_bits; 5205acb20054SMichael Chan u8 unused_0; 5206acb20054SMichael Chan __le16 max_entries; 5207894aa69aSMichael Chan u8 unused_1[3]; 5208acb20054SMichael Chan u8 valid; 5209acb20054SMichael Chan }; 5210acb20054SMichael Chan 5211894aa69aSMichael Chan /* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 5212acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_input { 5213acb20054SMichael Chan __le16 req_type; 5214acb20054SMichael Chan __le16 cmpl_ring; 5215acb20054SMichael Chan __le16 seq_id; 5216acb20054SMichael Chan __le16 target_id; 5217acb20054SMichael Chan __le64 resp_addr; 5218acb20054SMichael Chan __le64 dest_data_addr; 5219acb20054SMichael Chan u8 port_id; 5220acb20054SMichael Chan u8 unused_0; 5221acb20054SMichael Chan __le16 dest_data_buffer_size; 5222894aa69aSMichael Chan u8 unused_1[4]; 5223acb20054SMichael Chan }; 5224acb20054SMichael Chan 5225894aa69aSMichael Chan /* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 5226acb20054SMichael Chan struct hwrm_queue_dscp2pri_qcfg_output { 5227acb20054SMichael Chan __le16 error_code; 5228acb20054SMichael Chan __le16 req_type; 5229acb20054SMichael Chan __le16 seq_id; 5230acb20054SMichael Chan __le16 resp_len; 5231acb20054SMichael Chan __le16 entry_cnt; 5232acb20054SMichael Chan u8 default_pri; 5233894aa69aSMichael Chan u8 unused_0[4]; 5234acb20054SMichael Chan u8 valid; 5235acb20054SMichael Chan }; 5236acb20054SMichael Chan 5237894aa69aSMichael Chan /* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 5238acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_input { 5239acb20054SMichael Chan __le16 req_type; 5240acb20054SMichael Chan __le16 cmpl_ring; 5241acb20054SMichael Chan __le16 seq_id; 5242acb20054SMichael Chan __le16 target_id; 5243acb20054SMichael Chan __le64 resp_addr; 5244acb20054SMichael Chan __le64 src_data_addr; 5245acb20054SMichael Chan __le32 flags; 5246acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 5247acb20054SMichael Chan __le32 enables; 5248acb20054SMichael Chan #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 5249acb20054SMichael Chan u8 port_id; 5250acb20054SMichael Chan u8 default_pri; 5251acb20054SMichael Chan __le16 entry_cnt; 5252894aa69aSMichael Chan u8 unused_0[4]; 5253acb20054SMichael Chan }; 5254acb20054SMichael Chan 5255894aa69aSMichael Chan /* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 5256acb20054SMichael Chan struct hwrm_queue_dscp2pri_cfg_output { 5257acb20054SMichael Chan __le16 error_code; 5258acb20054SMichael Chan __le16 req_type; 5259acb20054SMichael Chan __le16 seq_id; 5260acb20054SMichael Chan __le16 resp_len; 5261894aa69aSMichael Chan u8 unused_0[7]; 5262acb20054SMichael Chan u8 valid; 5263acb20054SMichael Chan }; 5264acb20054SMichael Chan 5265894aa69aSMichael Chan /* hwrm_vnic_alloc_input (size:192b/24B) */ 5266c0c050c5SMichael Chan struct hwrm_vnic_alloc_input { 5267c0c050c5SMichael Chan __le16 req_type; 5268c0c050c5SMichael Chan __le16 cmpl_ring; 5269c0c050c5SMichael Chan __le16 seq_id; 5270c0c050c5SMichael Chan __le16 target_id; 5271c0c050c5SMichael Chan __le64 resp_addr; 5272c0c050c5SMichael Chan __le32 flags; 5273c0c050c5SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5274*16db6323SMichael Chan #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5275*16db6323SMichael Chan __le16 virtio_net_fid; 5276*16db6323SMichael Chan u8 unused_0[2]; 5277c0c050c5SMichael Chan }; 5278c0c050c5SMichael Chan 5279894aa69aSMichael Chan /* hwrm_vnic_alloc_output (size:128b/16B) */ 5280c0c050c5SMichael Chan struct hwrm_vnic_alloc_output { 5281c0c050c5SMichael Chan __le16 error_code; 5282c0c050c5SMichael Chan __le16 req_type; 5283c0c050c5SMichael Chan __le16 seq_id; 5284c0c050c5SMichael Chan __le16 resp_len; 5285c0c050c5SMichael Chan __le32 vnic_id; 5286894aa69aSMichael Chan u8 unused_0[3]; 5287c0c050c5SMichael Chan u8 valid; 5288c0c050c5SMichael Chan }; 5289c0c050c5SMichael Chan 5290894aa69aSMichael Chan /* hwrm_vnic_free_input (size:192b/24B) */ 5291c0c050c5SMichael Chan struct hwrm_vnic_free_input { 5292c0c050c5SMichael Chan __le16 req_type; 5293c0c050c5SMichael Chan __le16 cmpl_ring; 5294c0c050c5SMichael Chan __le16 seq_id; 5295c0c050c5SMichael Chan __le16 target_id; 5296c0c050c5SMichael Chan __le64 resp_addr; 5297c0c050c5SMichael Chan __le32 vnic_id; 5298894aa69aSMichael Chan u8 unused_0[4]; 5299c0c050c5SMichael Chan }; 5300c0c050c5SMichael Chan 5301894aa69aSMichael Chan /* hwrm_vnic_free_output (size:128b/16B) */ 5302c0c050c5SMichael Chan struct hwrm_vnic_free_output { 5303c0c050c5SMichael Chan __le16 error_code; 5304c0c050c5SMichael Chan __le16 req_type; 5305c0c050c5SMichael Chan __le16 seq_id; 5306c0c050c5SMichael Chan __le16 resp_len; 5307894aa69aSMichael Chan u8 unused_0[7]; 5308c0c050c5SMichael Chan u8 valid; 5309c0c050c5SMichael Chan }; 5310c0c050c5SMichael Chan 531172e0c9f9SMichael Chan /* hwrm_vnic_cfg_input (size:384b/48B) */ 5312c0c050c5SMichael Chan struct hwrm_vnic_cfg_input { 5313c0c050c5SMichael Chan __le16 req_type; 5314c0c050c5SMichael Chan __le16 cmpl_ring; 5315c0c050c5SMichael Chan __le16 seq_id; 5316c0c050c5SMichael Chan __le16 target_id; 5317c0c050c5SMichael Chan __le64 resp_addr; 5318c0c050c5SMichael Chan __le32 flags; 5319c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 5320c0c050c5SMichael Chan #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 5321c193554eSMichael Chan #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 532211f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 532311f15ed3SMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 5324441cabbbSMichael Chan #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 532557922b0aSMichael Chan #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 5326c0c050c5SMichael Chan __le32 enables; 5327c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 5328c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 5329c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 5330c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 5331c0c050c5SMichael Chan #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 53326fc92c33SMichael Chan #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 53336fc92c33SMichael Chan #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 533472e0c9f9SMichael Chan #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 5335bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 5336c0c050c5SMichael Chan __le16 vnic_id; 5337c0c050c5SMichael Chan __le16 dflt_ring_grp; 5338c0c050c5SMichael Chan __le16 rss_rule; 5339c0c050c5SMichael Chan __le16 cos_rule; 5340c0c050c5SMichael Chan __le16 lb_rule; 5341c0c050c5SMichael Chan __le16 mru; 53426fc92c33SMichael Chan __le16 default_rx_ring_id; 53436fc92c33SMichael Chan __le16 default_cmpl_ring_id; 534472e0c9f9SMichael Chan __le16 queue_id; 5345bfc6e5fbSMichael Chan u8 rx_csum_v2_mode; 5346bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 5347bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 5348bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 5349bfc6e5fbSMichael Chan #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 5350bfc6e5fbSMichael Chan u8 unused0[5]; 5351c0c050c5SMichael Chan }; 5352c0c050c5SMichael Chan 5353894aa69aSMichael Chan /* hwrm_vnic_cfg_output (size:128b/16B) */ 5354c0c050c5SMichael Chan struct hwrm_vnic_cfg_output { 5355c0c050c5SMichael Chan __le16 error_code; 5356c0c050c5SMichael Chan __le16 req_type; 5357c0c050c5SMichael Chan __le16 seq_id; 5358c0c050c5SMichael Chan __le16 resp_len; 5359894aa69aSMichael Chan u8 unused_0[7]; 5360c0c050c5SMichael Chan u8 valid; 5361c0c050c5SMichael Chan }; 5362c0c050c5SMichael Chan 5363894aa69aSMichael Chan /* hwrm_vnic_qcaps_input (size:192b/24B) */ 53648fdefd63SMichael Chan struct hwrm_vnic_qcaps_input { 53658fdefd63SMichael Chan __le16 req_type; 53668fdefd63SMichael Chan __le16 cmpl_ring; 53678fdefd63SMichael Chan __le16 seq_id; 53688fdefd63SMichael Chan __le16 target_id; 53698fdefd63SMichael Chan __le64 resp_addr; 53708fdefd63SMichael Chan __le32 enables; 5371894aa69aSMichael Chan u8 unused_0[4]; 53728fdefd63SMichael Chan }; 53738fdefd63SMichael Chan 5374894aa69aSMichael Chan /* hwrm_vnic_qcaps_output (size:192b/24B) */ 53758fdefd63SMichael Chan struct hwrm_vnic_qcaps_output { 53768fdefd63SMichael Chan __le16 error_code; 53778fdefd63SMichael Chan __le16 req_type; 53788fdefd63SMichael Chan __le16 seq_id; 53798fdefd63SMichael Chan __le16 resp_len; 53808fdefd63SMichael Chan __le16 mru; 5381894aa69aSMichael Chan u8 unused_0[2]; 53828fdefd63SMichael Chan __le32 flags; 5383bac9a7e0SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 53848fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 53858fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 53868fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 53878fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 53888fdefd63SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 5389894aa69aSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 53906fc92c33SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 539172e0c9f9SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5392bfc6e5fbSMichael Chan #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5393*16db6323SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 5394*16db6323SMichael Chan #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 53954a50ddc2SMichael Chan __le16 max_aggs_supported; 53964a50ddc2SMichael Chan u8 unused_1[5]; 53978fdefd63SMichael Chan u8 valid; 53988fdefd63SMichael Chan }; 53998fdefd63SMichael Chan 5400894aa69aSMichael Chan /* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 5401c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_input { 5402c0c050c5SMichael Chan __le16 req_type; 5403c0c050c5SMichael Chan __le16 cmpl_ring; 5404c0c050c5SMichael Chan __le16 seq_id; 5405c0c050c5SMichael Chan __le16 target_id; 5406c0c050c5SMichael Chan __le64 resp_addr; 5407c0c050c5SMichael Chan __le32 flags; 5408c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 5409c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 5410c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 5411c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 5412c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 5413c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5414c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 5415c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 54164a50ddc2SMichael Chan #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 5417c0c050c5SMichael Chan __le32 enables; 5418c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 5419c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 5420c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 5421c0c050c5SMichael Chan #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 5422c0c050c5SMichael Chan __le16 vnic_id; 5423c0c050c5SMichael Chan __le16 max_agg_segs; 5424441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 5425441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 5426441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 5427441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 5428441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 5429894aa69aSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 5430c0c050c5SMichael Chan __le16 max_aggs; 5431441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 5432441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 5433441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 5434441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 5435441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 5436441cabbbSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 5437894aa69aSMichael Chan #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 5438894aa69aSMichael Chan u8 unused_0[2]; 5439c0c050c5SMichael Chan __le32 max_agg_timer; 5440c0c050c5SMichael Chan __le32 min_agg_len; 5441c0c050c5SMichael Chan }; 5442c0c050c5SMichael Chan 5443894aa69aSMichael Chan /* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 5444c0c050c5SMichael Chan struct hwrm_vnic_tpa_cfg_output { 5445c0c050c5SMichael Chan __le16 error_code; 5446c0c050c5SMichael Chan __le16 req_type; 5447c0c050c5SMichael Chan __le16 seq_id; 5448c0c050c5SMichael Chan __le16 resp_len; 5449894aa69aSMichael Chan u8 unused_0[7]; 5450c0c050c5SMichael Chan u8 valid; 5451c0c050c5SMichael Chan }; 5452c0c050c5SMichael Chan 5453894aa69aSMichael Chan /* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 5454894aa69aSMichael Chan struct hwrm_vnic_tpa_qcfg_input { 5455894aa69aSMichael Chan __le16 req_type; 5456894aa69aSMichael Chan __le16 cmpl_ring; 5457894aa69aSMichael Chan __le16 seq_id; 5458894aa69aSMichael Chan __le16 target_id; 5459894aa69aSMichael Chan __le64 resp_addr; 5460894aa69aSMichael Chan __le16 vnic_id; 5461894aa69aSMichael Chan u8 unused_0[6]; 5462894aa69aSMichael Chan }; 5463894aa69aSMichael Chan 5464894aa69aSMichael Chan /* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 5465894aa69aSMichael Chan struct hwrm_vnic_tpa_qcfg_output { 5466894aa69aSMichael Chan __le16 error_code; 5467894aa69aSMichael Chan __le16 req_type; 5468894aa69aSMichael Chan __le16 seq_id; 5469894aa69aSMichael Chan __le16 resp_len; 5470894aa69aSMichael Chan __le32 flags; 5471894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 5472894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 5473894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 5474894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 5475894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 5476894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 5477894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 5478894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 5479894aa69aSMichael Chan __le16 max_agg_segs; 5480894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 5481894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 5482894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 5483894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 5484894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 5485894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 5486894aa69aSMichael Chan __le16 max_aggs; 5487894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 5488894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 5489894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 5490894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 5491894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 5492894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 5493894aa69aSMichael Chan #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 5494894aa69aSMichael Chan __le32 max_agg_timer; 5495894aa69aSMichael Chan __le32 min_agg_len; 5496894aa69aSMichael Chan u8 unused_0[7]; 5497894aa69aSMichael Chan u8 valid; 5498894aa69aSMichael Chan }; 5499894aa69aSMichael Chan 5500894aa69aSMichael Chan /* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 5501c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_input { 5502c0c050c5SMichael Chan __le16 req_type; 5503c0c050c5SMichael Chan __le16 cmpl_ring; 5504c0c050c5SMichael Chan __le16 seq_id; 5505c0c050c5SMichael Chan __le16 target_id; 5506c0c050c5SMichael Chan __le64 resp_addr; 5507c0c050c5SMichael Chan __le32 hash_type; 5508c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 5509c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 5510c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 5511c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 5512c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 5513c0c050c5SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 55146fc92c33SMichael Chan __le16 vnic_id; 55156fc92c33SMichael Chan u8 ring_table_pair_index; 55166fc92c33SMichael Chan u8 hash_mode_flags; 55176fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 55186fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 55196fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 55206fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 55216fc92c33SMichael Chan #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 5522c0c050c5SMichael Chan __le64 ring_grp_tbl_addr; 5523c0c050c5SMichael Chan __le64 hash_key_tbl_addr; 5524c0c050c5SMichael Chan __le16 rss_ctx_idx; 5525894aa69aSMichael Chan u8 unused_1[6]; 5526c0c050c5SMichael Chan }; 5527c0c050c5SMichael Chan 5528894aa69aSMichael Chan /* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 5529c0c050c5SMichael Chan struct hwrm_vnic_rss_cfg_output { 5530c0c050c5SMichael Chan __le16 error_code; 5531c0c050c5SMichael Chan __le16 req_type; 5532c0c050c5SMichael Chan __le16 seq_id; 5533c0c050c5SMichael Chan __le16 resp_len; 5534894aa69aSMichael Chan u8 unused_0[7]; 5535c0c050c5SMichael Chan u8 valid; 5536c0c050c5SMichael Chan }; 5537c0c050c5SMichael Chan 553841136ab3SMichael Chan /* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 553941136ab3SMichael Chan struct hwrm_vnic_rss_cfg_cmd_err { 554041136ab3SMichael Chan u8 code; 554141136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 554241136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 554341136ab3SMichael Chan #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 554441136ab3SMichael Chan u8 unused_0[7]; 554541136ab3SMichael Chan }; 554641136ab3SMichael Chan 5547894aa69aSMichael Chan /* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 5548c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_input { 5549c0c050c5SMichael Chan __le16 req_type; 5550c0c050c5SMichael Chan __le16 cmpl_ring; 5551c0c050c5SMichael Chan __le16 seq_id; 5552c0c050c5SMichael Chan __le16 target_id; 5553c0c050c5SMichael Chan __le64 resp_addr; 5554c0c050c5SMichael Chan __le32 flags; 5555c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 5556c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 5557c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 5558c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 5559c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 5560c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 5561bfc6e5fbSMichael Chan #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 5562c0c050c5SMichael Chan __le32 enables; 5563c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 5564c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 5565c0c050c5SMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 5566bfc6e5fbSMichael Chan #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 5567c0c050c5SMichael Chan __le32 vnic_id; 5568c0c050c5SMichael Chan __le16 jumbo_thresh; 5569c0c050c5SMichael Chan __le16 hds_offset; 5570c0c050c5SMichael Chan __le16 hds_threshold; 5571bfc6e5fbSMichael Chan __le16 max_bds; 5572bfc6e5fbSMichael Chan u8 unused_0[4]; 5573c0c050c5SMichael Chan }; 5574c0c050c5SMichael Chan 5575894aa69aSMichael Chan /* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 5576c0c050c5SMichael Chan struct hwrm_vnic_plcmodes_cfg_output { 5577c0c050c5SMichael Chan __le16 error_code; 5578c0c050c5SMichael Chan __le16 req_type; 5579c0c050c5SMichael Chan __le16 seq_id; 5580c0c050c5SMichael Chan __le16 resp_len; 5581894aa69aSMichael Chan u8 unused_0[7]; 5582c0c050c5SMichael Chan u8 valid; 5583c0c050c5SMichael Chan }; 5584c0c050c5SMichael Chan 5585894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 5586c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 5587c0c050c5SMichael Chan __le16 req_type; 5588c0c050c5SMichael Chan __le16 cmpl_ring; 5589c0c050c5SMichael Chan __le16 seq_id; 5590c0c050c5SMichael Chan __le16 target_id; 5591c0c050c5SMichael Chan __le64 resp_addr; 5592c0c050c5SMichael Chan }; 5593c0c050c5SMichael Chan 5594894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 5595c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 5596c0c050c5SMichael Chan __le16 error_code; 5597c0c050c5SMichael Chan __le16 req_type; 5598c0c050c5SMichael Chan __le16 seq_id; 5599c0c050c5SMichael Chan __le16 resp_len; 5600c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 5601894aa69aSMichael Chan u8 unused_0[5]; 5602c0c050c5SMichael Chan u8 valid; 5603c0c050c5SMichael Chan }; 5604c0c050c5SMichael Chan 5605894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 5606c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_input { 5607c0c050c5SMichael Chan __le16 req_type; 5608c0c050c5SMichael Chan __le16 cmpl_ring; 5609c0c050c5SMichael Chan __le16 seq_id; 5610c0c050c5SMichael Chan __le16 target_id; 5611c0c050c5SMichael Chan __le64 resp_addr; 5612c0c050c5SMichael Chan __le16 rss_cos_lb_ctx_id; 5613894aa69aSMichael Chan u8 unused_0[6]; 5614c0c050c5SMichael Chan }; 5615c0c050c5SMichael Chan 5616894aa69aSMichael Chan /* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 5617c0c050c5SMichael Chan struct hwrm_vnic_rss_cos_lb_ctx_free_output { 5618c0c050c5SMichael Chan __le16 error_code; 5619c0c050c5SMichael Chan __le16 req_type; 5620c0c050c5SMichael Chan __le16 seq_id; 5621c0c050c5SMichael Chan __le16 resp_len; 5622894aa69aSMichael Chan u8 unused_0[7]; 5623c0c050c5SMichael Chan u8 valid; 5624c0c050c5SMichael Chan }; 5625c0c050c5SMichael Chan 56266fc92c33SMichael Chan /* hwrm_ring_alloc_input (size:704b/88B) */ 5627c0c050c5SMichael Chan struct hwrm_ring_alloc_input { 5628c0c050c5SMichael Chan __le16 req_type; 5629c0c050c5SMichael Chan __le16 cmpl_ring; 5630c0c050c5SMichael Chan __le16 seq_id; 5631c0c050c5SMichael Chan __le16 target_id; 5632c0c050c5SMichael Chan __le64 resp_addr; 5633c0c050c5SMichael Chan __le32 enables; 5634441cabbbSMichael Chan #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 5635c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 5636c0c050c5SMichael Chan #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 56376fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 56386fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 56396fc92c33SMichael Chan #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 5640bfc6e5fbSMichael Chan #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 56419d6b648cSMichael Chan #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 5642c0c050c5SMichael Chan u8 ring_type; 5643bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 5644441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 5645441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 5646bac9a7e0SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 56476fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 56486fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 56496fc92c33SMichael Chan #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 565031d357c0SMichael Chan u8 unused_0; 565131d357c0SMichael Chan __le16 flags; 565231d357c0SMichael Chan #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 5653c0c050c5SMichael Chan __le64 page_tbl_addr; 5654c0c050c5SMichael Chan __le32 fbo; 5655c0c050c5SMichael Chan u8 page_size; 5656c0c050c5SMichael Chan u8 page_tbl_depth; 5657bfc6e5fbSMichael Chan __le16 schq_id; 5658c0c050c5SMichael Chan __le32 length; 5659c0c050c5SMichael Chan __le16 logical_id; 5660c0c050c5SMichael Chan __le16 cmpl_ring_id; 5661c0c050c5SMichael Chan __le16 queue_id; 56626fc92c33SMichael Chan __le16 rx_buf_size; 56636fc92c33SMichael Chan __le16 rx_ring_id; 56646fc92c33SMichael Chan __le16 nq_ring_id; 5665441cabbbSMichael Chan __le16 ring_arb_cfg; 5666441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 5667441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 5668894aa69aSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 5669894aa69aSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 5670441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 5671441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 5672441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 5673441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 5674441cabbbSMichael Chan #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 5675894aa69aSMichael Chan __le16 unused_3; 5676c193554eSMichael Chan __le32 reserved3; 5677c0c050c5SMichael Chan __le32 stat_ctx_id; 5678c193554eSMichael Chan __le32 reserved4; 5679c0c050c5SMichael Chan __le32 max_bw; 5680441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 5681441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 5682bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 5683bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 5684bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 5685bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 5686441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 5687441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 5688bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 5689bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 5690bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 5691bac9a7e0SMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 5692441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 5693441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 5694441cabbbSMichael Chan #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 5695c0c050c5SMichael Chan u8 int_mode; 5696441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 5697441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 5698441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 5699441cabbbSMichael Chan #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 5700894aa69aSMichael Chan #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 57019d6b648cSMichael Chan u8 mpc_chnls_type; 57029d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 57039d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 57049d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 57059d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 57069d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 57079d6b648cSMichael Chan #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 57089d6b648cSMichael Chan u8 unused_4[2]; 57096fc92c33SMichael Chan __le64 cq_handle; 5710c0c050c5SMichael Chan }; 5711c0c050c5SMichael Chan 5712894aa69aSMichael Chan /* hwrm_ring_alloc_output (size:128b/16B) */ 5713c0c050c5SMichael Chan struct hwrm_ring_alloc_output { 5714c0c050c5SMichael Chan __le16 error_code; 5715c0c050c5SMichael Chan __le16 req_type; 5716c0c050c5SMichael Chan __le16 seq_id; 5717c0c050c5SMichael Chan __le16 resp_len; 5718c0c050c5SMichael Chan __le16 ring_id; 5719c0c050c5SMichael Chan __le16 logical_ring_id; 5720*16db6323SMichael Chan u8 push_buffer_index; 5721*16db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5722*16db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5723*16db6323SMichael Chan #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5724*16db6323SMichael Chan u8 unused_0[2]; 5725c0c050c5SMichael Chan u8 valid; 5726c0c050c5SMichael Chan }; 5727c0c050c5SMichael Chan 5728894aa69aSMichael Chan /* hwrm_ring_free_input (size:192b/24B) */ 5729c0c050c5SMichael Chan struct hwrm_ring_free_input { 5730c0c050c5SMichael Chan __le16 req_type; 5731c0c050c5SMichael Chan __le16 cmpl_ring; 5732c0c050c5SMichael Chan __le16 seq_id; 5733c0c050c5SMichael Chan __le16 target_id; 5734c0c050c5SMichael Chan __le64 resp_addr; 5735c0c050c5SMichael Chan u8 ring_type; 5736bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 5737441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 5738441cabbbSMichael Chan #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 5739bac9a7e0SMichael Chan #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 57406fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 57416fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 57426fc92c33SMichael Chan #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 5743c0c050c5SMichael Chan u8 unused_0; 5744c0c050c5SMichael Chan __le16 ring_id; 5745894aa69aSMichael Chan u8 unused_1[4]; 5746c0c050c5SMichael Chan }; 5747c0c050c5SMichael Chan 5748894aa69aSMichael Chan /* hwrm_ring_free_output (size:128b/16B) */ 5749c0c050c5SMichael Chan struct hwrm_ring_free_output { 5750c0c050c5SMichael Chan __le16 error_code; 5751c0c050c5SMichael Chan __le16 req_type; 5752c0c050c5SMichael Chan __le16 seq_id; 5753c0c050c5SMichael Chan __le16 resp_len; 5754894aa69aSMichael Chan u8 unused_0[7]; 5755c0c050c5SMichael Chan u8 valid; 5756c0c050c5SMichael Chan }; 5757c0c050c5SMichael Chan 57583293ec23SMichael Chan /* hwrm_ring_reset_input (size:192b/24B) */ 57593293ec23SMichael Chan struct hwrm_ring_reset_input { 57603293ec23SMichael Chan __le16 req_type; 57613293ec23SMichael Chan __le16 cmpl_ring; 57623293ec23SMichael Chan __le16 seq_id; 57633293ec23SMichael Chan __le16 target_id; 57643293ec23SMichael Chan __le64 resp_addr; 57653293ec23SMichael Chan u8 ring_type; 57663293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 57673293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 57683293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 57693293ec23SMichael Chan #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 5770bfc6e5fbSMichael Chan #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 5771bfc6e5fbSMichael Chan #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 57723293ec23SMichael Chan u8 unused_0; 57733293ec23SMichael Chan __le16 ring_id; 57743293ec23SMichael Chan u8 unused_1[4]; 57753293ec23SMichael Chan }; 57763293ec23SMichael Chan 57773293ec23SMichael Chan /* hwrm_ring_reset_output (size:128b/16B) */ 57783293ec23SMichael Chan struct hwrm_ring_reset_output { 57793293ec23SMichael Chan __le16 error_code; 57803293ec23SMichael Chan __le16 req_type; 57813293ec23SMichael Chan __le16 seq_id; 57823293ec23SMichael Chan __le16 resp_len; 5783*16db6323SMichael Chan u8 push_buffer_index; 5784*16db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5785*16db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5786*16db6323SMichael Chan #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5787*16db6323SMichael Chan u8 unused_0[3]; 57883293ec23SMichael Chan u8 consumer_idx[3]; 57893293ec23SMichael Chan u8 valid; 57903293ec23SMichael Chan }; 57913293ec23SMichael Chan 57926fc92c33SMichael Chan /* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 57936fc92c33SMichael Chan struct hwrm_ring_aggint_qcaps_input { 57946fc92c33SMichael Chan __le16 req_type; 57956fc92c33SMichael Chan __le16 cmpl_ring; 57966fc92c33SMichael Chan __le16 seq_id; 57976fc92c33SMichael Chan __le16 target_id; 57986fc92c33SMichael Chan __le64 resp_addr; 57996fc92c33SMichael Chan }; 58006fc92c33SMichael Chan 58016fc92c33SMichael Chan /* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 58026fc92c33SMichael Chan struct hwrm_ring_aggint_qcaps_output { 58036fc92c33SMichael Chan __le16 error_code; 58046fc92c33SMichael Chan __le16 req_type; 58056fc92c33SMichael Chan __le16 seq_id; 58066fc92c33SMichael Chan __le16 resp_len; 58076fc92c33SMichael Chan __le32 cmpl_params; 58086fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 58096fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 58106fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 58116fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 58126fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 58136fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 58146fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 58156fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 58166fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 58176fc92c33SMichael Chan __le32 nq_params; 58186fc92c33SMichael Chan #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 58196fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_min; 58206fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_max; 58216fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_during_int_min; 58226fc92c33SMichael Chan __le16 num_cmpl_dma_aggr_during_int_max; 58236fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_min; 58246fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_max; 58256fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int_min; 58266fc92c33SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int_max; 58276fc92c33SMichael Chan __le16 int_lat_tmr_min_min; 58286fc92c33SMichael Chan __le16 int_lat_tmr_min_max; 58296fc92c33SMichael Chan __le16 int_lat_tmr_max_min; 58306fc92c33SMichael Chan __le16 int_lat_tmr_max_max; 58316fc92c33SMichael Chan __le16 num_cmpl_aggr_int_min; 58326fc92c33SMichael Chan __le16 num_cmpl_aggr_int_max; 58336fc92c33SMichael Chan __le16 timer_units; 58346fc92c33SMichael Chan u8 unused_0[1]; 58356fc92c33SMichael Chan u8 valid; 58366fc92c33SMichael Chan }; 58376fc92c33SMichael Chan 5838894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 5839c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_input { 5840c0c050c5SMichael Chan __le16 req_type; 5841c0c050c5SMichael Chan __le16 cmpl_ring; 5842c0c050c5SMichael Chan __le16 seq_id; 5843c0c050c5SMichael Chan __le16 target_id; 5844c0c050c5SMichael Chan __le64 resp_addr; 5845c0c050c5SMichael Chan __le16 ring_id; 5846460c2577SMichael Chan __le16 flags; 5847460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 5848460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 5849460c2577SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5850460c2577SMichael Chan u8 unused_0[4]; 5851c0c050c5SMichael Chan }; 5852c0c050c5SMichael Chan 5853894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 5854c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_qaggint_params_output { 5855c0c050c5SMichael Chan __le16 error_code; 5856c0c050c5SMichael Chan __le16 req_type; 5857c0c050c5SMichael Chan __le16 seq_id; 5858c0c050c5SMichael Chan __le16 resp_len; 5859c0c050c5SMichael Chan __le16 flags; 5860c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 5861c0c050c5SMichael Chan #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 5862c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 5863c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 5864c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 5865c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 5866c0c050c5SMichael Chan __le16 int_lat_tmr_min; 5867c0c050c5SMichael Chan __le16 int_lat_tmr_max; 5868c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 5869894aa69aSMichael Chan u8 unused_0[7]; 5870c0c050c5SMichael Chan u8 valid; 5871c0c050c5SMichael Chan }; 5872c0c050c5SMichael Chan 5873894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 5874c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 5875c0c050c5SMichael Chan __le16 req_type; 5876c0c050c5SMichael Chan __le16 cmpl_ring; 5877c0c050c5SMichael Chan __le16 seq_id; 5878c0c050c5SMichael Chan __le16 target_id; 5879c0c050c5SMichael Chan __le64 resp_addr; 5880c0c050c5SMichael Chan __le16 ring_id; 5881c0c050c5SMichael Chan __le16 flags; 5882c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 5883c0c050c5SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 58846fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 5885c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr; 5886c0c050c5SMichael Chan __le16 num_cmpl_dma_aggr_during_int; 5887c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr; 5888c0c050c5SMichael Chan __le16 cmpl_aggr_dma_tmr_during_int; 5889c0c050c5SMichael Chan __le16 int_lat_tmr_min; 5890c0c050c5SMichael Chan __le16 int_lat_tmr_max; 5891c0c050c5SMichael Chan __le16 num_cmpl_aggr_int; 58926fc92c33SMichael Chan __le16 enables; 58936fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 58946fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 58956fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 58966fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 58976fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 58986fc92c33SMichael Chan #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 58996fc92c33SMichael Chan u8 unused_0[4]; 5900c0c050c5SMichael Chan }; 5901c0c050c5SMichael Chan 5902894aa69aSMichael Chan /* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 5903c0c050c5SMichael Chan struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 5904c0c050c5SMichael Chan __le16 error_code; 5905c0c050c5SMichael Chan __le16 req_type; 5906c0c050c5SMichael Chan __le16 seq_id; 5907c0c050c5SMichael Chan __le16 resp_len; 5908894aa69aSMichael Chan u8 unused_0[7]; 5909c0c050c5SMichael Chan u8 valid; 5910c0c050c5SMichael Chan }; 5911c0c050c5SMichael Chan 5912894aa69aSMichael Chan /* hwrm_ring_grp_alloc_input (size:192b/24B) */ 5913c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_input { 5914c0c050c5SMichael Chan __le16 req_type; 5915c0c050c5SMichael Chan __le16 cmpl_ring; 5916c0c050c5SMichael Chan __le16 seq_id; 5917c0c050c5SMichael Chan __le16 target_id; 5918c0c050c5SMichael Chan __le64 resp_addr; 5919c0c050c5SMichael Chan __le16 cr; 5920c0c050c5SMichael Chan __le16 rr; 5921c0c050c5SMichael Chan __le16 ar; 5922c0c050c5SMichael Chan __le16 sc; 5923c0c050c5SMichael Chan }; 5924c0c050c5SMichael Chan 5925894aa69aSMichael Chan /* hwrm_ring_grp_alloc_output (size:128b/16B) */ 5926c0c050c5SMichael Chan struct hwrm_ring_grp_alloc_output { 5927c0c050c5SMichael Chan __le16 error_code; 5928c0c050c5SMichael Chan __le16 req_type; 5929c0c050c5SMichael Chan __le16 seq_id; 5930c0c050c5SMichael Chan __le16 resp_len; 5931c0c050c5SMichael Chan __le32 ring_group_id; 5932894aa69aSMichael Chan u8 unused_0[3]; 5933c0c050c5SMichael Chan u8 valid; 5934c0c050c5SMichael Chan }; 5935c0c050c5SMichael Chan 5936894aa69aSMichael Chan /* hwrm_ring_grp_free_input (size:192b/24B) */ 5937c0c050c5SMichael Chan struct hwrm_ring_grp_free_input { 5938c0c050c5SMichael Chan __le16 req_type; 5939c0c050c5SMichael Chan __le16 cmpl_ring; 5940c0c050c5SMichael Chan __le16 seq_id; 5941c0c050c5SMichael Chan __le16 target_id; 5942c0c050c5SMichael Chan __le64 resp_addr; 5943c0c050c5SMichael Chan __le32 ring_group_id; 5944894aa69aSMichael Chan u8 unused_0[4]; 5945c0c050c5SMichael Chan }; 5946c0c050c5SMichael Chan 5947894aa69aSMichael Chan /* hwrm_ring_grp_free_output (size:128b/16B) */ 5948c0c050c5SMichael Chan struct hwrm_ring_grp_free_output { 5949c0c050c5SMichael Chan __le16 error_code; 5950c0c050c5SMichael Chan __le16 req_type; 5951c0c050c5SMichael Chan __le16 seq_id; 5952c0c050c5SMichael Chan __le16 resp_len; 5953894aa69aSMichael Chan u8 unused_0[7]; 5954c0c050c5SMichael Chan u8 valid; 5955c0c050c5SMichael Chan }; 5956bfc6e5fbSMichael Chan 59573322479eSMichael Chan #define DEFAULT_FLOW_ID 0xFFFFFFFFUL 59583322479eSMichael Chan #define ROCEV1_FLOW_ID 0xFFFFFFFEUL 59593322479eSMichael Chan #define ROCEV2_FLOW_ID 0xFFFFFFFDUL 59603322479eSMichael Chan #define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 5961c0c050c5SMichael Chan 5962894aa69aSMichael Chan /* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 5963c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_input { 5964c0c050c5SMichael Chan __le16 req_type; 5965c0c050c5SMichael Chan __le16 cmpl_ring; 5966c0c050c5SMichael Chan __le16 seq_id; 5967c0c050c5SMichael Chan __le16 target_id; 5968c0c050c5SMichael Chan __le64 resp_addr; 5969c0c050c5SMichael Chan __le32 flags; 5970c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 5971894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 5972894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 597311f15ed3SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 5974c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 5975c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 5976c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 597731d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 597831d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 597931d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 598031d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 598131d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 598231d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 59834a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 59844a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 5985c0c050c5SMichael Chan __le32 enables; 5986c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 5987c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 5988c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 5989c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 5990c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 5991c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 5992c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 5993c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 5994c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 5995c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 5996c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 5997c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 5998c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 5999c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 6000c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 6001c193554eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 6002c0c050c5SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 60034a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 60044a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 6005c0c050c5SMichael Chan u8 l2_addr[6]; 60064a50ddc2SMichael Chan u8 num_vlans; 60074a50ddc2SMichael Chan u8 t_num_vlans; 6008c0c050c5SMichael Chan u8 l2_addr_mask[6]; 6009c0c050c5SMichael Chan __le16 l2_ovlan; 6010c0c050c5SMichael Chan __le16 l2_ovlan_mask; 6011c0c050c5SMichael Chan __le16 l2_ivlan; 6012c0c050c5SMichael Chan __le16 l2_ivlan_mask; 6013894aa69aSMichael Chan u8 unused_1[2]; 6014c0c050c5SMichael Chan u8 t_l2_addr[6]; 6015894aa69aSMichael Chan u8 unused_2[2]; 6016c0c050c5SMichael Chan u8 t_l2_addr_mask[6]; 6017c0c050c5SMichael Chan __le16 t_l2_ovlan; 6018c0c050c5SMichael Chan __le16 t_l2_ovlan_mask; 6019c0c050c5SMichael Chan __le16 t_l2_ivlan; 6020c0c050c5SMichael Chan __le16 t_l2_ivlan_mask; 6021c0c050c5SMichael Chan u8 src_type; 6022441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 6023441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 6024441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 6025441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 6026441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 6027441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 6028441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 6029441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 6030894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 6031894aa69aSMichael Chan u8 unused_3; 6032c0c050c5SMichael Chan __le32 src_id; 6033c0c050c5SMichael Chan u8 tunnel_type; 6034441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6035441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6036441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6037441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6038441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6039441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6040441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6041441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6042441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 604357922b0aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 604431d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 604531d357c0SMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 60463322479eSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6047441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6048894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6049894aa69aSMichael Chan u8 unused_4; 6050c193554eSMichael Chan __le16 dst_id; 6051c0c050c5SMichael Chan __le16 mirror_vnic_id; 6052c0c050c5SMichael Chan u8 pri_hint; 6053441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6054441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 6055441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 6056441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 6057441cabbbSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 6058894aa69aSMichael Chan #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 6059894aa69aSMichael Chan u8 unused_5; 6060894aa69aSMichael Chan __le32 unused_6; 6061c0c050c5SMichael Chan __le64 l2_filter_id_hint; 6062c0c050c5SMichael Chan }; 6063c0c050c5SMichael Chan 6064894aa69aSMichael Chan /* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 6065c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_alloc_output { 6066c0c050c5SMichael Chan __le16 error_code; 6067c0c050c5SMichael Chan __le16 req_type; 6068c0c050c5SMichael Chan __le16 seq_id; 6069c0c050c5SMichael Chan __le16 resp_len; 6070c0c050c5SMichael Chan __le64 l2_filter_id; 6071c0c050c5SMichael Chan __le32 flow_id; 60724a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 60734a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 60744a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 60754a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 60764a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 60774a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 60784a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 60794a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 60804a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 60814a50ddc2SMichael Chan #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6082894aa69aSMichael Chan u8 unused_0[3]; 6083c0c050c5SMichael Chan u8 valid; 6084c0c050c5SMichael Chan }; 6085c0c050c5SMichael Chan 6086894aa69aSMichael Chan /* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 6087c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_input { 6088c0c050c5SMichael Chan __le16 req_type; 6089c0c050c5SMichael Chan __le16 cmpl_ring; 6090c0c050c5SMichael Chan __le16 seq_id; 6091c0c050c5SMichael Chan __le16 target_id; 6092c0c050c5SMichael Chan __le64 resp_addr; 6093c0c050c5SMichael Chan __le64 l2_filter_id; 6094c0c050c5SMichael Chan }; 6095c0c050c5SMichael Chan 6096894aa69aSMichael Chan /* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 6097c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_free_output { 6098c0c050c5SMichael Chan __le16 error_code; 6099c0c050c5SMichael Chan __le16 req_type; 6100c0c050c5SMichael Chan __le16 seq_id; 6101c0c050c5SMichael Chan __le16 resp_len; 6102894aa69aSMichael Chan u8 unused_0[7]; 6103c0c050c5SMichael Chan u8 valid; 6104c0c050c5SMichael Chan }; 6105c0c050c5SMichael Chan 6106894aa69aSMichael Chan /* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 6107c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_input { 6108c0c050c5SMichael Chan __le16 req_type; 6109c0c050c5SMichael Chan __le16 cmpl_ring; 6110c0c050c5SMichael Chan __le16 seq_id; 6111c0c050c5SMichael Chan __le16 target_id; 6112c0c050c5SMichael Chan __le64 resp_addr; 6113c0c050c5SMichael Chan __le32 flags; 6114c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 6115894aa69aSMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 6116894aa69aSMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 611711f15ed3SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 6118c0c050c5SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 611931d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 612031d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 612131d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 612231d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 612331d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 612431d357c0SMichael Chan #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 6125c0c050c5SMichael Chan __le32 enables; 6126c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 6127c193554eSMichael Chan #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6128c0c050c5SMichael Chan __le64 l2_filter_id; 6129c193554eSMichael Chan __le32 dst_id; 6130c193554eSMichael Chan __le32 new_mirror_vnic_id; 6131c0c050c5SMichael Chan }; 6132c0c050c5SMichael Chan 6133894aa69aSMichael Chan /* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 6134c0c050c5SMichael Chan struct hwrm_cfa_l2_filter_cfg_output { 6135c0c050c5SMichael Chan __le16 error_code; 6136c0c050c5SMichael Chan __le16 req_type; 6137c0c050c5SMichael Chan __le16 seq_id; 6138c0c050c5SMichael Chan __le16 resp_len; 6139894aa69aSMichael Chan u8 unused_0[7]; 6140c0c050c5SMichael Chan u8 valid; 6141c0c050c5SMichael Chan }; 6142c0c050c5SMichael Chan 6143894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 6144c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_input { 6145c0c050c5SMichael Chan __le16 req_type; 6146c0c050c5SMichael Chan __le16 cmpl_ring; 6147c0c050c5SMichael Chan __le16 seq_id; 6148c0c050c5SMichael Chan __le16 target_id; 6149c0c050c5SMichael Chan __le64 resp_addr; 6150c193554eSMichael Chan __le32 vnic_id; 6151c0c050c5SMichael Chan __le32 mask; 6152c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 6153c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 6154c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 6155c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 6156c0c050c5SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 6157a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 6158a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 6159a58a3e68SMichael Chan #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 6160c0c050c5SMichael Chan __le64 mc_tbl_addr; 6161c0c050c5SMichael Chan __le32 num_mc_entries; 6162894aa69aSMichael Chan u8 unused_0[4]; 6163a58a3e68SMichael Chan __le64 vlan_tag_tbl_addr; 6164a58a3e68SMichael Chan __le32 num_vlan_tags; 6165894aa69aSMichael Chan u8 unused_1[4]; 6166c0c050c5SMichael Chan }; 6167c0c050c5SMichael Chan 6168894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 6169c0c050c5SMichael Chan struct hwrm_cfa_l2_set_rx_mask_output { 6170c0c050c5SMichael Chan __le16 error_code; 6171c0c050c5SMichael Chan __le16 req_type; 6172c0c050c5SMichael Chan __le16 seq_id; 6173c0c050c5SMichael Chan __le16 resp_len; 6174894aa69aSMichael Chan u8 unused_0[7]; 6175c0c050c5SMichael Chan u8 valid; 6176c0c050c5SMichael Chan }; 6177c0c050c5SMichael Chan 6178894aa69aSMichael Chan /* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 617957922b0aSMichael Chan struct hwrm_cfa_l2_set_rx_mask_cmd_err { 618057922b0aSMichael Chan u8 code; 618157922b0aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 618257922b0aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 6183894aa69aSMichael Chan #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 618457922b0aSMichael Chan u8 unused_0[7]; 618557922b0aSMichael Chan }; 618657922b0aSMichael Chan 6187894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 6188c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_input { 6189c0c050c5SMichael Chan __le16 req_type; 6190c0c050c5SMichael Chan __le16 cmpl_ring; 6191c0c050c5SMichael Chan __le16 seq_id; 6192c0c050c5SMichael Chan __le16 target_id; 6193c0c050c5SMichael Chan __le64 resp_addr; 6194c0c050c5SMichael Chan __le32 flags; 6195c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6196c0c050c5SMichael Chan __le32 enables; 6197c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6198c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 6199c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 6200c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 6201c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 6202c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 6203c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 6204c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 6205c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 6206c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 6207c0c050c5SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 6208c0c050c5SMichael Chan __le64 l2_filter_id; 6209c0c050c5SMichael Chan u8 l2_addr[6]; 6210c0c050c5SMichael Chan __le16 l2_ivlan; 6211c0c050c5SMichael Chan __le32 l3_addr[4]; 6212c0c050c5SMichael Chan __le32 t_l3_addr[4]; 6213c0c050c5SMichael Chan u8 l3_addr_type; 6214c0c050c5SMichael Chan u8 t_l3_addr_type; 6215c0c050c5SMichael Chan u8 tunnel_type; 6216441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6217441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6218441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6219441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6220441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6221441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6222441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6223441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6224441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 622557922b0aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 622631d357c0SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 622731d357c0SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 62283322479eSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6229441cabbbSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6230894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6231894aa69aSMichael Chan u8 tunnel_flags; 6232894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 6233894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 6234894aa69aSMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 6235c0c050c5SMichael Chan __le32 vni; 6236c0c050c5SMichael Chan __le32 dst_vnic_id; 6237c0c050c5SMichael Chan __le32 mirror_vnic_id; 6238c0c050c5SMichael Chan }; 6239c0c050c5SMichael Chan 6240894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 6241c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_alloc_output { 6242c0c050c5SMichael Chan __le16 error_code; 6243c0c050c5SMichael Chan __le16 req_type; 6244c0c050c5SMichael Chan __le16 seq_id; 6245c0c050c5SMichael Chan __le16 resp_len; 6246c0c050c5SMichael Chan __le64 tunnel_filter_id; 6247c0c050c5SMichael Chan __le32 flow_id; 62484a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 62494a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 62504a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 62514a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 62524a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 62534a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 62544a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 62554a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 62564a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 62574a50ddc2SMichael Chan #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6258894aa69aSMichael Chan u8 unused_0[3]; 6259c0c050c5SMichael Chan u8 valid; 6260c0c050c5SMichael Chan }; 6261c0c050c5SMichael Chan 6262894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 6263c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_input { 6264c0c050c5SMichael Chan __le16 req_type; 6265c0c050c5SMichael Chan __le16 cmpl_ring; 6266c0c050c5SMichael Chan __le16 seq_id; 6267c0c050c5SMichael Chan __le16 target_id; 6268c0c050c5SMichael Chan __le64 resp_addr; 6269c0c050c5SMichael Chan __le64 tunnel_filter_id; 6270c0c050c5SMichael Chan }; 6271c0c050c5SMichael Chan 6272894aa69aSMichael Chan /* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 6273c0c050c5SMichael Chan struct hwrm_cfa_tunnel_filter_free_output { 6274c0c050c5SMichael Chan __le16 error_code; 6275c0c050c5SMichael Chan __le16 req_type; 6276c0c050c5SMichael Chan __le16 seq_id; 6277c0c050c5SMichael Chan __le16 resp_len; 6278894aa69aSMichael Chan u8 unused_0[7]; 6279c0c050c5SMichael Chan u8 valid; 6280c0c050c5SMichael Chan }; 6281c0c050c5SMichael Chan 6282894aa69aSMichael Chan /* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 6283894aa69aSMichael Chan struct hwrm_vxlan_ipv4_hdr { 6284894aa69aSMichael Chan u8 ver_hlen; 6285894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 6286894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 6287894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 6288894aa69aSMichael Chan #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 6289894aa69aSMichael Chan u8 tos; 6290894aa69aSMichael Chan __be16 ip_id; 6291894aa69aSMichael Chan __be16 flags_frag_offset; 6292894aa69aSMichael Chan u8 ttl; 6293894aa69aSMichael Chan u8 protocol; 6294894aa69aSMichael Chan __be32 src_ip_addr; 6295894aa69aSMichael Chan __be32 dest_ip_addr; 6296894aa69aSMichael Chan }; 6297894aa69aSMichael Chan 6298894aa69aSMichael Chan /* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 6299894aa69aSMichael Chan struct hwrm_vxlan_ipv6_hdr { 6300894aa69aSMichael Chan __be32 ver_tc_flow_label; 6301894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 6302894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 6303894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 6304894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 6305894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 6306894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 6307894aa69aSMichael Chan #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 6308894aa69aSMichael Chan __be16 payload_len; 6309894aa69aSMichael Chan u8 next_hdr; 6310894aa69aSMichael Chan u8 ttl; 6311894aa69aSMichael Chan __be32 src_ip_addr[4]; 6312894aa69aSMichael Chan __be32 dest_ip_addr[4]; 6313894aa69aSMichael Chan }; 6314894aa69aSMichael Chan 631531d357c0SMichael Chan /* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 6316894aa69aSMichael Chan struct hwrm_cfa_encap_data_vxlan { 6317894aa69aSMichael Chan u8 src_mac_addr[6]; 6318894aa69aSMichael Chan __le16 unused_0; 6319894aa69aSMichael Chan u8 dst_mac_addr[6]; 6320894aa69aSMichael Chan u8 num_vlan_tags; 6321894aa69aSMichael Chan u8 unused_1; 6322894aa69aSMichael Chan __be16 ovlan_tpid; 6323894aa69aSMichael Chan __be16 ovlan_tci; 6324894aa69aSMichael Chan __be16 ivlan_tpid; 6325894aa69aSMichael Chan __be16 ivlan_tci; 6326894aa69aSMichael Chan __le32 l3[10]; 6327894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 6328894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 6329894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 6330894aa69aSMichael Chan #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 6331894aa69aSMichael Chan __be16 src_port; 6332894aa69aSMichael Chan __be16 dst_port; 6333894aa69aSMichael Chan __be32 vni; 633431d357c0SMichael Chan u8 hdr_rsvd0[3]; 633531d357c0SMichael Chan u8 hdr_rsvd1; 633631d357c0SMichael Chan u8 hdr_flags; 633731d357c0SMichael Chan u8 unused[3]; 6338894aa69aSMichael Chan }; 6339894aa69aSMichael Chan 6340894aa69aSMichael Chan /* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 6341c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_input { 6342c0c050c5SMichael Chan __le16 req_type; 6343c0c050c5SMichael Chan __le16 cmpl_ring; 6344c0c050c5SMichael Chan __le16 seq_id; 6345c0c050c5SMichael Chan __le16 target_id; 6346c0c050c5SMichael Chan __le64 resp_addr; 6347c0c050c5SMichael Chan __le32 flags; 6348c0c050c5SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 63493293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 6350c0c050c5SMichael Chan u8 encap_type; 6351441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 6352441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 6353441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 6354441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 6355441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 6356441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 6357441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 6358441cabbbSMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 635931d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 636031d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 636131d357c0SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 63623293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 63633293ec23SMichael Chan #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 6364894aa69aSMichael Chan u8 unused_0[3]; 6365acb20054SMichael Chan __le32 encap_data[20]; 6366c0c050c5SMichael Chan }; 6367c0c050c5SMichael Chan 6368894aa69aSMichael Chan /* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 6369c0c050c5SMichael Chan struct hwrm_cfa_encap_record_alloc_output { 6370c0c050c5SMichael Chan __le16 error_code; 6371c0c050c5SMichael Chan __le16 req_type; 6372c0c050c5SMichael Chan __le16 seq_id; 6373c0c050c5SMichael Chan __le16 resp_len; 6374c193554eSMichael Chan __le32 encap_record_id; 6375894aa69aSMichael Chan u8 unused_0[3]; 6376c0c050c5SMichael Chan u8 valid; 6377c0c050c5SMichael Chan }; 6378c0c050c5SMichael Chan 6379894aa69aSMichael Chan /* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 6380c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_input { 6381c0c050c5SMichael Chan __le16 req_type; 6382c0c050c5SMichael Chan __le16 cmpl_ring; 6383c0c050c5SMichael Chan __le16 seq_id; 6384c0c050c5SMichael Chan __le16 target_id; 6385c0c050c5SMichael Chan __le64 resp_addr; 6386c193554eSMichael Chan __le32 encap_record_id; 6387894aa69aSMichael Chan u8 unused_0[4]; 6388c0c050c5SMichael Chan }; 6389c0c050c5SMichael Chan 6390894aa69aSMichael Chan /* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 6391c0c050c5SMichael Chan struct hwrm_cfa_encap_record_free_output { 6392c0c050c5SMichael Chan __le16 error_code; 6393c0c050c5SMichael Chan __le16 req_type; 6394c0c050c5SMichael Chan __le16 seq_id; 6395c0c050c5SMichael Chan __le16 resp_len; 6396894aa69aSMichael Chan u8 unused_0[7]; 6397c0c050c5SMichael Chan u8 valid; 6398c0c050c5SMichael Chan }; 6399c0c050c5SMichael Chan 640041136ab3SMichael Chan /* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 6401c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_input { 6402c0c050c5SMichael Chan __le16 req_type; 6403c0c050c5SMichael Chan __le16 cmpl_ring; 6404c0c050c5SMichael Chan __le16 seq_id; 6405c0c050c5SMichael Chan __le16 target_id; 6406c0c050c5SMichael Chan __le64 resp_addr; 6407c0c050c5SMichael Chan __le32 flags; 6408c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 6409c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 6410bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 64113293ec23SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 641241136ab3SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 641341136ab3SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 6414c0c050c5SMichael Chan __le32 enables; 6415c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 6416c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 6417c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 6418c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 6419c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 6420c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 6421c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 6422c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 6423c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 6424c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 6425c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 6426c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 6427c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 6428c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 6429c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 6430c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 6431c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 6432c0c050c5SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 6433c193554eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 64344a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 6435c0c050c5SMichael Chan __le64 l2_filter_id; 6436c0c050c5SMichael Chan u8 src_macaddr[6]; 6437c0c050c5SMichael Chan __be16 ethertype; 6438c193554eSMichael Chan u8 ip_addr_type; 6439441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 6440441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 6441441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6442894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 6443c0c050c5SMichael Chan u8 ip_protocol; 6444441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 6445acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 6446acb20054SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6447894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6448c193554eSMichael Chan __le16 dst_id; 6449c0c050c5SMichael Chan __le16 mirror_vnic_id; 6450c0c050c5SMichael Chan u8 tunnel_type; 6451441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 6452441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 6453441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 6454441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 6455441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 6456441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 6457441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 6458441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 6459441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 646057922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 646131d357c0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 646231d357c0SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 64633322479eSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 6464441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6465894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 6466c0c050c5SMichael Chan u8 pri_hint; 6467441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 6468441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 6469441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 6470441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 6471441cabbbSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 6472894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 6473c0c050c5SMichael Chan __be32 src_ipaddr[4]; 6474c0c050c5SMichael Chan __be32 src_ipaddr_mask[4]; 6475c0c050c5SMichael Chan __be32 dst_ipaddr[4]; 6476c0c050c5SMichael Chan __be32 dst_ipaddr_mask[4]; 6477c0c050c5SMichael Chan __be16 src_port; 6478c0c050c5SMichael Chan __be16 src_port_mask; 6479c0c050c5SMichael Chan __be16 dst_port; 6480c0c050c5SMichael Chan __be16 dst_port_mask; 6481c0c050c5SMichael Chan __le64 ntuple_filter_id_hint; 6482c0c050c5SMichael Chan }; 6483c0c050c5SMichael Chan 6484894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 6485c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_alloc_output { 6486c0c050c5SMichael Chan __le16 error_code; 6487c0c050c5SMichael Chan __le16 req_type; 6488c0c050c5SMichael Chan __le16 seq_id; 6489c0c050c5SMichael Chan __le16 resp_len; 6490c0c050c5SMichael Chan __le64 ntuple_filter_id; 6491c0c050c5SMichael Chan __le32 flow_id; 64924a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 64934a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 64944a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 64954a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 64964a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 64974a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 64984a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 64994a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 65004a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 65014a50ddc2SMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 6502894aa69aSMichael Chan u8 unused_0[3]; 6503c0c050c5SMichael Chan u8 valid; 6504c0c050c5SMichael Chan }; 6505c0c050c5SMichael Chan 6506894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 650757922b0aSMichael Chan struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 650857922b0aSMichael Chan u8 code; 650957922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 651057922b0aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 6511894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 651257922b0aSMichael Chan u8 unused_0[7]; 651357922b0aSMichael Chan }; 651457922b0aSMichael Chan 6515894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 6516c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_input { 6517c0c050c5SMichael Chan __le16 req_type; 6518c0c050c5SMichael Chan __le16 cmpl_ring; 6519c0c050c5SMichael Chan __le16 seq_id; 6520c0c050c5SMichael Chan __le16 target_id; 6521c0c050c5SMichael Chan __le64 resp_addr; 6522c0c050c5SMichael Chan __le64 ntuple_filter_id; 6523c0c050c5SMichael Chan }; 6524c0c050c5SMichael Chan 6525894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 6526c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_free_output { 6527c0c050c5SMichael Chan __le16 error_code; 6528c0c050c5SMichael Chan __le16 req_type; 6529c0c050c5SMichael Chan __le16 seq_id; 6530c0c050c5SMichael Chan __le16 resp_len; 6531894aa69aSMichael Chan u8 unused_0[7]; 6532c0c050c5SMichael Chan u8 valid; 6533c0c050c5SMichael Chan }; 6534c0c050c5SMichael Chan 6535894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 6536c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_input { 6537c0c050c5SMichael Chan __le16 req_type; 6538c0c050c5SMichael Chan __le16 cmpl_ring; 6539c0c050c5SMichael Chan __le16 seq_id; 6540c0c050c5SMichael Chan __le16 target_id; 6541c0c050c5SMichael Chan __le64 resp_addr; 6542c0c050c5SMichael Chan __le32 enables; 6543c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 6544c193554eSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 6545bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 65463293ec23SMichael Chan __le32 flags; 65473293ec23SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 654841136ab3SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 6549c0c050c5SMichael Chan __le64 ntuple_filter_id; 6550c193554eSMichael Chan __le32 new_dst_id; 6551c0c050c5SMichael Chan __le32 new_mirror_vnic_id; 6552bac9a7e0SMichael Chan __le16 new_meter_instance_id; 6553bac9a7e0SMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 6554894aa69aSMichael Chan #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 6555894aa69aSMichael Chan u8 unused_1[6]; 6556c0c050c5SMichael Chan }; 6557c0c050c5SMichael Chan 6558894aa69aSMichael Chan /* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 6559c0c050c5SMichael Chan struct hwrm_cfa_ntuple_filter_cfg_output { 6560c0c050c5SMichael Chan __le16 error_code; 6561c0c050c5SMichael Chan __le16 req_type; 6562c0c050c5SMichael Chan __le16 seq_id; 6563c0c050c5SMichael Chan __le16 resp_len; 6564894aa69aSMichael Chan u8 unused_0[7]; 6565c0c050c5SMichael Chan u8 valid; 6566c0c050c5SMichael Chan }; 6567c0c050c5SMichael Chan 6568894aa69aSMichael Chan /* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 656957922b0aSMichael Chan struct hwrm_cfa_decap_filter_alloc_input { 657057922b0aSMichael Chan __le16 req_type; 657157922b0aSMichael Chan __le16 cmpl_ring; 657257922b0aSMichael Chan __le16 seq_id; 657357922b0aSMichael Chan __le16 target_id; 657457922b0aSMichael Chan __le64 resp_addr; 657557922b0aSMichael Chan __le32 flags; 657657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 657757922b0aSMichael Chan __le32 enables; 657857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 657957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 658057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 658157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 658257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 658357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 658457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 658557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 658657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 658757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 658857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 658957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 659057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 659157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 659257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 659357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 659457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 659557922b0aSMichael Chan __be32 tunnel_id; 659657922b0aSMichael Chan u8 tunnel_type; 659757922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 659857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 659957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 660057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 660157922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 660257922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 660357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 660457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 660557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 660657922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 660731d357c0SMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 660831d357c0SMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 66093322479eSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 661057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 6611894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 661257922b0aSMichael Chan u8 unused_0; 661357922b0aSMichael Chan __le16 unused_1; 661457922b0aSMichael Chan u8 src_macaddr[6]; 6615894aa69aSMichael Chan u8 unused_2[2]; 661657922b0aSMichael Chan u8 dst_macaddr[6]; 661757922b0aSMichael Chan __be16 ovlan_vid; 661857922b0aSMichael Chan __be16 ivlan_vid; 661957922b0aSMichael Chan __be16 t_ovlan_vid; 662057922b0aSMichael Chan __be16 t_ivlan_vid; 662157922b0aSMichael Chan __be16 ethertype; 662257922b0aSMichael Chan u8 ip_addr_type; 662357922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 662457922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 662557922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 6626894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 662757922b0aSMichael Chan u8 ip_protocol; 662857922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 662957922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 663057922b0aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 6631894aa69aSMichael Chan #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 6632894aa69aSMichael Chan __le16 unused_3; 6633894aa69aSMichael Chan __le32 unused_4; 663457922b0aSMichael Chan __be32 src_ipaddr[4]; 663557922b0aSMichael Chan __be32 dst_ipaddr[4]; 663657922b0aSMichael Chan __be16 src_port; 663757922b0aSMichael Chan __be16 dst_port; 663857922b0aSMichael Chan __le16 dst_id; 663957922b0aSMichael Chan __le16 l2_ctxt_ref_id; 664057922b0aSMichael Chan }; 664157922b0aSMichael Chan 6642894aa69aSMichael Chan /* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 664357922b0aSMichael Chan struct hwrm_cfa_decap_filter_alloc_output { 664457922b0aSMichael Chan __le16 error_code; 664557922b0aSMichael Chan __le16 req_type; 664657922b0aSMichael Chan __le16 seq_id; 664757922b0aSMichael Chan __le16 resp_len; 664857922b0aSMichael Chan __le32 decap_filter_id; 6649894aa69aSMichael Chan u8 unused_0[3]; 665057922b0aSMichael Chan u8 valid; 665157922b0aSMichael Chan }; 665257922b0aSMichael Chan 6653894aa69aSMichael Chan /* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 665457922b0aSMichael Chan struct hwrm_cfa_decap_filter_free_input { 665557922b0aSMichael Chan __le16 req_type; 665657922b0aSMichael Chan __le16 cmpl_ring; 665757922b0aSMichael Chan __le16 seq_id; 665857922b0aSMichael Chan __le16 target_id; 665957922b0aSMichael Chan __le64 resp_addr; 666057922b0aSMichael Chan __le32 decap_filter_id; 6661894aa69aSMichael Chan u8 unused_0[4]; 666257922b0aSMichael Chan }; 666357922b0aSMichael Chan 6664894aa69aSMichael Chan /* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 666557922b0aSMichael Chan struct hwrm_cfa_decap_filter_free_output { 666657922b0aSMichael Chan __le16 error_code; 666757922b0aSMichael Chan __le16 req_type; 666857922b0aSMichael Chan __le16 seq_id; 666957922b0aSMichael Chan __le16 resp_len; 6670894aa69aSMichael Chan u8 unused_0[7]; 667157922b0aSMichael Chan u8 valid; 667257922b0aSMichael Chan }; 667357922b0aSMichael Chan 6674894aa69aSMichael Chan /* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 66756a17eb27SMichael Chan struct hwrm_cfa_flow_alloc_input { 66766a17eb27SMichael Chan __le16 req_type; 66776a17eb27SMichael Chan __le16 cmpl_ring; 66786a17eb27SMichael Chan __le16 seq_id; 66796a17eb27SMichael Chan __le16 target_id; 66806a17eb27SMichael Chan __le64 resp_addr; 66816a17eb27SMichael Chan __le16 flags; 66826a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 66836a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 66846a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 66856a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 66866a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 66876a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 66886a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 66896a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 66906a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 66916a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 66926a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 66936a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 66946a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 669531d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 669631d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 669731d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 66983322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 66996a17eb27SMichael Chan __le16 src_fid; 67006a17eb27SMichael Chan __le32 tunnel_handle; 67016a17eb27SMichael Chan __le16 action_flags; 67026a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 67036a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 67046a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 67056a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 67066a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 67076a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 67086a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 67096a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 67106a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 67116a17eb27SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 671231d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 67133322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 67143322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 67154a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 67166a17eb27SMichael Chan __le16 dst_fid; 67176a17eb27SMichael Chan __be16 l2_rewrite_vlan_tpid; 67186a17eb27SMichael Chan __be16 l2_rewrite_vlan_tci; 67196a17eb27SMichael Chan __le16 act_meter_id; 67206a17eb27SMichael Chan __le16 ref_flow_handle; 67216a17eb27SMichael Chan __be16 ethertype; 67226a17eb27SMichael Chan __be16 outer_vlan_tci; 67236a17eb27SMichael Chan __be16 dmac[3]; 67246a17eb27SMichael Chan __be16 inner_vlan_tci; 67256a17eb27SMichael Chan __be16 smac[3]; 67266a17eb27SMichael Chan u8 ip_dst_mask_len; 67276a17eb27SMichael Chan u8 ip_src_mask_len; 67286a17eb27SMichael Chan __be32 ip_dst[4]; 67296a17eb27SMichael Chan __be32 ip_src[4]; 67306a17eb27SMichael Chan __be16 l4_src_port; 67316a17eb27SMichael Chan __be16 l4_src_port_mask; 67326a17eb27SMichael Chan __be16 l4_dst_port; 67336a17eb27SMichael Chan __be16 l4_dst_port_mask; 67346a17eb27SMichael Chan __be32 nat_ip_address[4]; 67356a17eb27SMichael Chan __be16 l2_rewrite_dmac[3]; 67366a17eb27SMichael Chan __be16 nat_port; 67376a17eb27SMichael Chan __be16 l2_rewrite_smac[3]; 67386a17eb27SMichael Chan u8 ip_proto; 673931d357c0SMichael Chan u8 tunnel_type; 674031d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 674131d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 674231d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 674331d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 674431d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 674531d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 674631d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 674731d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 674831d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 674931d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 675031d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 675131d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 67523322479eSMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 675331d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 675431d357c0SMichael Chan #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 67556a17eb27SMichael Chan }; 67566a17eb27SMichael Chan 675731d357c0SMichael Chan /* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 67586a17eb27SMichael Chan struct hwrm_cfa_flow_alloc_output { 67596a17eb27SMichael Chan __le16 error_code; 67606a17eb27SMichael Chan __le16 req_type; 67616a17eb27SMichael Chan __le16 seq_id; 67626a17eb27SMichael Chan __le16 resp_len; 67636a17eb27SMichael Chan __le16 flow_handle; 676431d357c0SMichael Chan u8 unused_0[2]; 676531d357c0SMichael Chan __le32 flow_id; 67664a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 67674a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 67684a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 67694a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 67704a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 67714a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 67724a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 67734a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 67744a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 67754a50ddc2SMichael Chan #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 677631d357c0SMichael Chan __le64 ext_flow_handle; 67773322479eSMichael Chan __le32 flow_counter_id; 67783322479eSMichael Chan u8 unused_1[3]; 67796a17eb27SMichael Chan u8 valid; 67806a17eb27SMichael Chan }; 67816a17eb27SMichael Chan 67822792b5b9SMichael Chan /* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 67832792b5b9SMichael Chan struct hwrm_cfa_flow_alloc_cmd_err { 67842792b5b9SMichael Chan u8 code; 67852792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 67862792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 67872792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 67882792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 67892792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 67902792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 67912792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 67922792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 67932792b5b9SMichael Chan #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 67942792b5b9SMichael Chan u8 unused_0[7]; 67952792b5b9SMichael Chan }; 67962792b5b9SMichael Chan 679731d357c0SMichael Chan /* hwrm_cfa_flow_free_input (size:256b/32B) */ 67986a17eb27SMichael Chan struct hwrm_cfa_flow_free_input { 67996a17eb27SMichael Chan __le16 req_type; 68006a17eb27SMichael Chan __le16 cmpl_ring; 68016a17eb27SMichael Chan __le16 seq_id; 68026a17eb27SMichael Chan __le16 target_id; 68036a17eb27SMichael Chan __le64 resp_addr; 68046a17eb27SMichael Chan __le16 flow_handle; 68054a50ddc2SMichael Chan __le16 unused_0; 68064a50ddc2SMichael Chan __le32 flow_counter_id; 680731d357c0SMichael Chan __le64 ext_flow_handle; 68086a17eb27SMichael Chan }; 68096a17eb27SMichael Chan 6810894aa69aSMichael Chan /* hwrm_cfa_flow_free_output (size:256b/32B) */ 68116a17eb27SMichael Chan struct hwrm_cfa_flow_free_output { 68126a17eb27SMichael Chan __le16 error_code; 68136a17eb27SMichael Chan __le16 req_type; 68146a17eb27SMichael Chan __le16 seq_id; 68156a17eb27SMichael Chan __le16 resp_len; 68166a17eb27SMichael Chan __le64 packet; 68176a17eb27SMichael Chan __le64 byte; 6818894aa69aSMichael Chan u8 unused_0[7]; 68196a17eb27SMichael Chan u8 valid; 68206a17eb27SMichael Chan }; 68216a17eb27SMichael Chan 68223322479eSMichael Chan /* hwrm_cfa_flow_info_input (size:256b/32B) */ 68233322479eSMichael Chan struct hwrm_cfa_flow_info_input { 68243322479eSMichael Chan __le16 req_type; 68253322479eSMichael Chan __le16 cmpl_ring; 68263322479eSMichael Chan __le16 seq_id; 68273322479eSMichael Chan __le16 target_id; 68283322479eSMichael Chan __le64 resp_addr; 68293322479eSMichael Chan __le16 flow_handle; 68303322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 68313322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_SFT 0 68323322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 68333322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 68343322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 68353322479eSMichael Chan #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 68363322479eSMichael Chan u8 unused_0[6]; 68373322479eSMichael Chan __le64 ext_flow_handle; 68383322479eSMichael Chan }; 68393322479eSMichael Chan 68403293ec23SMichael Chan /* hwrm_cfa_flow_info_output (size:5632b/704B) */ 68413322479eSMichael Chan struct hwrm_cfa_flow_info_output { 68423322479eSMichael Chan __le16 error_code; 68433322479eSMichael Chan __le16 req_type; 68443322479eSMichael Chan __le16 seq_id; 68453322479eSMichael Chan __le16 resp_len; 68463322479eSMichael Chan u8 flags; 68473293ec23SMichael Chan #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 68483293ec23SMichael Chan #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 68493322479eSMichael Chan u8 profile; 68503322479eSMichael Chan __le16 src_fid; 68513322479eSMichael Chan __le16 dst_fid; 68523322479eSMichael Chan __le16 l2_ctxt_id; 68533322479eSMichael Chan __le64 em_info; 68543322479eSMichael Chan __le64 tcam_info; 68553322479eSMichael Chan __le64 vfp_tcam_info; 68563322479eSMichael Chan __le16 ar_id; 68573322479eSMichael Chan __le16 flow_handle; 68583322479eSMichael Chan __le32 tunnel_handle; 68593322479eSMichael Chan __le16 flow_timer; 68603293ec23SMichael Chan u8 unused_0[6]; 68613293ec23SMichael Chan __le32 flow_key_data[130]; 68623293ec23SMichael Chan __le32 flow_action_info[30]; 68633293ec23SMichael Chan u8 unused_1[7]; 68643322479eSMichael Chan u8 valid; 68653322479eSMichael Chan }; 68663322479eSMichael Chan 686731d357c0SMichael Chan /* hwrm_cfa_flow_stats_input (size:640b/80B) */ 68686a17eb27SMichael Chan struct hwrm_cfa_flow_stats_input { 68696a17eb27SMichael Chan __le16 req_type; 68706a17eb27SMichael Chan __le16 cmpl_ring; 68716a17eb27SMichael Chan __le16 seq_id; 68726a17eb27SMichael Chan __le16 target_id; 68736a17eb27SMichael Chan __le64 resp_addr; 68746a17eb27SMichael Chan __le16 num_flows; 68756a17eb27SMichael Chan __le16 flow_handle_0; 68766a17eb27SMichael Chan __le16 flow_handle_1; 68776a17eb27SMichael Chan __le16 flow_handle_2; 68786a17eb27SMichael Chan __le16 flow_handle_3; 68796a17eb27SMichael Chan __le16 flow_handle_4; 68806a17eb27SMichael Chan __le16 flow_handle_5; 68816a17eb27SMichael Chan __le16 flow_handle_6; 68826a17eb27SMichael Chan __le16 flow_handle_7; 68836a17eb27SMichael Chan __le16 flow_handle_8; 68846a17eb27SMichael Chan __le16 flow_handle_9; 6885894aa69aSMichael Chan u8 unused_0[2]; 688631d357c0SMichael Chan __le32 flow_id_0; 688731d357c0SMichael Chan __le32 flow_id_1; 688831d357c0SMichael Chan __le32 flow_id_2; 688931d357c0SMichael Chan __le32 flow_id_3; 689031d357c0SMichael Chan __le32 flow_id_4; 689131d357c0SMichael Chan __le32 flow_id_5; 689231d357c0SMichael Chan __le32 flow_id_6; 689331d357c0SMichael Chan __le32 flow_id_7; 689431d357c0SMichael Chan __le32 flow_id_8; 689531d357c0SMichael Chan __le32 flow_id_9; 68966a17eb27SMichael Chan }; 68976a17eb27SMichael Chan 6898894aa69aSMichael Chan /* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 68996a17eb27SMichael Chan struct hwrm_cfa_flow_stats_output { 69006a17eb27SMichael Chan __le16 error_code; 69016a17eb27SMichael Chan __le16 req_type; 69026a17eb27SMichael Chan __le16 seq_id; 69036a17eb27SMichael Chan __le16 resp_len; 69046a17eb27SMichael Chan __le64 packet_0; 69056a17eb27SMichael Chan __le64 packet_1; 69066a17eb27SMichael Chan __le64 packet_2; 69076a17eb27SMichael Chan __le64 packet_3; 69086a17eb27SMichael Chan __le64 packet_4; 69096a17eb27SMichael Chan __le64 packet_5; 69106a17eb27SMichael Chan __le64 packet_6; 69116a17eb27SMichael Chan __le64 packet_7; 69126a17eb27SMichael Chan __le64 packet_8; 69136a17eb27SMichael Chan __le64 packet_9; 69146a17eb27SMichael Chan __le64 byte_0; 69156a17eb27SMichael Chan __le64 byte_1; 69166a17eb27SMichael Chan __le64 byte_2; 69176a17eb27SMichael Chan __le64 byte_3; 69186a17eb27SMichael Chan __le64 byte_4; 69196a17eb27SMichael Chan __le64 byte_5; 69206a17eb27SMichael Chan __le64 byte_6; 69216a17eb27SMichael Chan __le64 byte_7; 69226a17eb27SMichael Chan __le64 byte_8; 69236a17eb27SMichael Chan __le64 byte_9; 6924894aa69aSMichael Chan u8 unused_0[7]; 69256a17eb27SMichael Chan u8 valid; 69266a17eb27SMichael Chan }; 69276a17eb27SMichael Chan 6928894aa69aSMichael Chan /* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 6929acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_input { 6930acb20054SMichael Chan __le16 req_type; 6931acb20054SMichael Chan __le16 cmpl_ring; 6932acb20054SMichael Chan __le16 seq_id; 6933acb20054SMichael Chan __le16 target_id; 6934acb20054SMichael Chan __le64 resp_addr; 6935acb20054SMichael Chan __le16 vf_id; 6936acb20054SMichael Chan __le16 reserved; 6937894aa69aSMichael Chan u8 unused_0[4]; 6938acb20054SMichael Chan char vfr_name[32]; 6939acb20054SMichael Chan }; 6940acb20054SMichael Chan 6941894aa69aSMichael Chan /* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 6942acb20054SMichael Chan struct hwrm_cfa_vfr_alloc_output { 6943acb20054SMichael Chan __le16 error_code; 6944acb20054SMichael Chan __le16 req_type; 6945acb20054SMichael Chan __le16 seq_id; 6946acb20054SMichael Chan __le16 resp_len; 6947acb20054SMichael Chan __le16 rx_cfa_code; 6948acb20054SMichael Chan __le16 tx_cfa_action; 6949894aa69aSMichael Chan u8 unused_0[3]; 6950acb20054SMichael Chan u8 valid; 6951acb20054SMichael Chan }; 6952acb20054SMichael Chan 69539d6b648cSMichael Chan /* hwrm_cfa_vfr_free_input (size:448b/56B) */ 6954acb20054SMichael Chan struct hwrm_cfa_vfr_free_input { 6955acb20054SMichael Chan __le16 req_type; 6956acb20054SMichael Chan __le16 cmpl_ring; 6957acb20054SMichael Chan __le16 seq_id; 6958acb20054SMichael Chan __le16 target_id; 6959acb20054SMichael Chan __le64 resp_addr; 6960acb20054SMichael Chan char vfr_name[32]; 69619d6b648cSMichael Chan __le16 vf_id; 69629d6b648cSMichael Chan __le16 reserved; 69639d6b648cSMichael Chan u8 unused_0[4]; 6964acb20054SMichael Chan }; 6965acb20054SMichael Chan 6966894aa69aSMichael Chan /* hwrm_cfa_vfr_free_output (size:128b/16B) */ 6967acb20054SMichael Chan struct hwrm_cfa_vfr_free_output { 6968acb20054SMichael Chan __le16 error_code; 6969acb20054SMichael Chan __le16 req_type; 6970acb20054SMichael Chan __le16 seq_id; 6971acb20054SMichael Chan __le16 resp_len; 6972894aa69aSMichael Chan u8 unused_0[7]; 6973acb20054SMichael Chan u8 valid; 6974acb20054SMichael Chan }; 6975acb20054SMichael Chan 69763322479eSMichael Chan /* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 69773322479eSMichael Chan struct hwrm_cfa_eem_qcaps_input { 69783322479eSMichael Chan __le16 req_type; 69793322479eSMichael Chan __le16 cmpl_ring; 69803322479eSMichael Chan __le16 seq_id; 69813322479eSMichael Chan __le16 target_id; 69823322479eSMichael Chan __le64 resp_addr; 69833322479eSMichael Chan __le32 flags; 69843322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 69853322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 69863322479eSMichael Chan #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 69873322479eSMichael Chan __le32 unused_0; 69883322479eSMichael Chan }; 69893322479eSMichael Chan 69902792b5b9SMichael Chan /* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 69913322479eSMichael Chan struct hwrm_cfa_eem_qcaps_output { 69923322479eSMichael Chan __le16 error_code; 69933322479eSMichael Chan __le16 req_type; 69943322479eSMichael Chan __le16 seq_id; 69953322479eSMichael Chan __le16 resp_len; 69963322479eSMichael Chan __le32 flags; 69973322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 69983322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 69994a50ddc2SMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 70004a50ddc2SMichael Chan #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 70013322479eSMichael Chan __le32 unused_0; 70023322479eSMichael Chan __le32 supported; 70033322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 70043322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 70053322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 70063322479eSMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 70072792b5b9SMichael Chan #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 70083322479eSMichael Chan __le32 max_entries_supported; 70093322479eSMichael Chan __le16 key_entry_size; 70103322479eSMichael Chan __le16 record_entry_size; 70113322479eSMichael Chan __le16 efc_entry_size; 70122792b5b9SMichael Chan __le16 fid_entry_size; 70132792b5b9SMichael Chan u8 unused_1[7]; 70143322479eSMichael Chan u8 valid; 70153322479eSMichael Chan }; 70163322479eSMichael Chan 70172792b5b9SMichael Chan /* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 70183322479eSMichael Chan struct hwrm_cfa_eem_cfg_input { 70193322479eSMichael Chan __le16 req_type; 70203322479eSMichael Chan __le16 cmpl_ring; 70213322479eSMichael Chan __le16 seq_id; 70223322479eSMichael Chan __le16 target_id; 70233322479eSMichael Chan __le64 resp_addr; 70243322479eSMichael Chan __le32 flags; 70253322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 70263322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 70273322479eSMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 70284a50ddc2SMichael Chan #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 70294a50ddc2SMichael Chan __le16 group_id; 70304a50ddc2SMichael Chan __le16 unused_0; 70313322479eSMichael Chan __le32 num_entries; 70323322479eSMichael Chan __le32 unused_1; 70333322479eSMichael Chan __le16 key0_ctx_id; 70343322479eSMichael Chan __le16 key1_ctx_id; 70353322479eSMichael Chan __le16 record_ctx_id; 70363322479eSMichael Chan __le16 efc_ctx_id; 70372792b5b9SMichael Chan __le16 fid_ctx_id; 70382792b5b9SMichael Chan __le16 unused_2; 70392792b5b9SMichael Chan __le32 unused_3; 70403322479eSMichael Chan }; 70413322479eSMichael Chan 70423322479eSMichael Chan /* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 70433322479eSMichael Chan struct hwrm_cfa_eem_cfg_output { 70443322479eSMichael Chan __le16 error_code; 70453322479eSMichael Chan __le16 req_type; 70463322479eSMichael Chan __le16 seq_id; 70473322479eSMichael Chan __le16 resp_len; 70483322479eSMichael Chan u8 unused_0[7]; 70493322479eSMichael Chan u8 valid; 70503322479eSMichael Chan }; 70513322479eSMichael Chan 70523322479eSMichael Chan /* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 70533322479eSMichael Chan struct hwrm_cfa_eem_qcfg_input { 70543322479eSMichael Chan __le16 req_type; 70553322479eSMichael Chan __le16 cmpl_ring; 70563322479eSMichael Chan __le16 seq_id; 70573322479eSMichael Chan __le16 target_id; 70583322479eSMichael Chan __le64 resp_addr; 70593322479eSMichael Chan __le32 flags; 70603322479eSMichael Chan #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 70613322479eSMichael Chan #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 70623322479eSMichael Chan __le32 unused_0; 70633322479eSMichael Chan }; 70643322479eSMichael Chan 70652792b5b9SMichael Chan /* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 70663322479eSMichael Chan struct hwrm_cfa_eem_qcfg_output { 70673322479eSMichael Chan __le16 error_code; 70683322479eSMichael Chan __le16 req_type; 70693322479eSMichael Chan __le16 seq_id; 70703322479eSMichael Chan __le16 resp_len; 70713322479eSMichael Chan __le32 flags; 70723322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 70733322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 70743322479eSMichael Chan #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 70753322479eSMichael Chan __le32 num_entries; 70762792b5b9SMichael Chan __le16 key0_ctx_id; 70772792b5b9SMichael Chan __le16 key1_ctx_id; 70782792b5b9SMichael Chan __le16 record_ctx_id; 70792792b5b9SMichael Chan __le16 efc_ctx_id; 70802792b5b9SMichael Chan __le16 fid_ctx_id; 70812792b5b9SMichael Chan u8 unused_2[5]; 70824a50ddc2SMichael Chan u8 valid; 70833322479eSMichael Chan }; 70843322479eSMichael Chan 70853322479eSMichael Chan /* hwrm_cfa_eem_op_input (size:192b/24B) */ 70863322479eSMichael Chan struct hwrm_cfa_eem_op_input { 70873322479eSMichael Chan __le16 req_type; 70883322479eSMichael Chan __le16 cmpl_ring; 70893322479eSMichael Chan __le16 seq_id; 70903322479eSMichael Chan __le16 target_id; 70913322479eSMichael Chan __le64 resp_addr; 70923322479eSMichael Chan __le32 flags; 70933322479eSMichael Chan #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 70943322479eSMichael Chan #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 70953322479eSMichael Chan __le16 unused_0; 70963322479eSMichael Chan __le16 op; 70973322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 70983322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 70993322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 71003322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 71013322479eSMichael Chan #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 71023322479eSMichael Chan }; 71033322479eSMichael Chan 71043322479eSMichael Chan /* hwrm_cfa_eem_op_output (size:128b/16B) */ 71053322479eSMichael Chan struct hwrm_cfa_eem_op_output { 71063322479eSMichael Chan __le16 error_code; 71073322479eSMichael Chan __le16 req_type; 71083322479eSMichael Chan __le16 seq_id; 71093322479eSMichael Chan __le16 resp_len; 71103322479eSMichael Chan u8 unused_0[7]; 71113322479eSMichael Chan u8 valid; 71123322479eSMichael Chan }; 71133322479eSMichael Chan 71144a50ddc2SMichael Chan /* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 71154a50ddc2SMichael Chan struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 71164a50ddc2SMichael Chan __le16 req_type; 71174a50ddc2SMichael Chan __le16 cmpl_ring; 71184a50ddc2SMichael Chan __le16 seq_id; 71194a50ddc2SMichael Chan __le16 target_id; 71204a50ddc2SMichael Chan __le64 resp_addr; 71214a50ddc2SMichael Chan __le32 unused_0[4]; 71224a50ddc2SMichael Chan }; 71234a50ddc2SMichael Chan 71244a50ddc2SMichael Chan /* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 71254a50ddc2SMichael Chan struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 71264a50ddc2SMichael Chan __le16 error_code; 71274a50ddc2SMichael Chan __le16 req_type; 71284a50ddc2SMichael Chan __le16 seq_id; 71294a50ddc2SMichael Chan __le16 resp_len; 71304a50ddc2SMichael Chan __le32 flags; 71314a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 71324a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 71334a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 71344a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 71354a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 71364a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 71374a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 71384a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 71394a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 71404a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 71414a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 71424a50ddc2SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 714341136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 714441136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 714541136ab3SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7146*16db6323SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7147*16db6323SMichael Chan #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 71484a50ddc2SMichael Chan u8 unused_0[3]; 71494a50ddc2SMichael Chan u8 valid; 71504a50ddc2SMichael Chan }; 71514a50ddc2SMichael Chan 7152894aa69aSMichael Chan /* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 7153c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_input { 7154c0c050c5SMichael Chan __le16 req_type; 7155c0c050c5SMichael Chan __le16 cmpl_ring; 7156c0c050c5SMichael Chan __le16 seq_id; 7157c0c050c5SMichael Chan __le16 target_id; 7158c0c050c5SMichael Chan __le64 resp_addr; 7159c0c050c5SMichael Chan u8 tunnel_type; 7160441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7161441cabbbSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 716257922b0aSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 71636fc92c33SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 716431d357c0SMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 71653322479eSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 71663322479eSMichael Chan #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7167c0c050c5SMichael Chan u8 unused_0[7]; 7168c0c050c5SMichael Chan }; 7169c0c050c5SMichael Chan 7170894aa69aSMichael Chan /* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 7171c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_query_output { 7172c0c050c5SMichael Chan __le16 error_code; 7173c0c050c5SMichael Chan __le16 req_type; 7174c0c050c5SMichael Chan __le16 seq_id; 7175c0c050c5SMichael Chan __le16 resp_len; 7176c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 7177c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 7178894aa69aSMichael Chan u8 unused_0[3]; 7179c0c050c5SMichael Chan u8 valid; 7180c0c050c5SMichael Chan }; 7181c0c050c5SMichael Chan 7182894aa69aSMichael Chan /* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 7183c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_input { 7184c0c050c5SMichael Chan __le16 req_type; 7185c0c050c5SMichael Chan __le16 cmpl_ring; 7186c0c050c5SMichael Chan __le16 seq_id; 7187c0c050c5SMichael Chan __le16 target_id; 7188c0c050c5SMichael Chan __le64 resp_addr; 7189c0c050c5SMichael Chan u8 tunnel_type; 7190441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7191441cabbbSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 719257922b0aSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 71936fc92c33SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 719431d357c0SMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 71953322479eSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 71963322479eSMichael Chan #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7197c0c050c5SMichael Chan u8 unused_0; 7198c0c050c5SMichael Chan __be16 tunnel_dst_port_val; 7199894aa69aSMichael Chan u8 unused_1[4]; 7200c0c050c5SMichael Chan }; 7201c0c050c5SMichael Chan 7202894aa69aSMichael Chan /* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 7203c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_alloc_output { 7204c0c050c5SMichael Chan __le16 error_code; 7205c0c050c5SMichael Chan __le16 req_type; 7206c0c050c5SMichael Chan __le16 seq_id; 7207c0c050c5SMichael Chan __le16 resp_len; 7208c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 7209894aa69aSMichael Chan u8 unused_0[5]; 7210c0c050c5SMichael Chan u8 valid; 7211c0c050c5SMichael Chan }; 7212c0c050c5SMichael Chan 7213894aa69aSMichael Chan /* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 7214c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_input { 7215c0c050c5SMichael Chan __le16 req_type; 7216c0c050c5SMichael Chan __le16 cmpl_ring; 7217c0c050c5SMichael Chan __le16 seq_id; 7218c0c050c5SMichael Chan __le16 target_id; 7219c0c050c5SMichael Chan __le64 resp_addr; 7220c0c050c5SMichael Chan u8 tunnel_type; 7221441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7222441cabbbSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 722357922b0aSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 72246fc92c33SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 722531d357c0SMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 72263322479eSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 72273322479eSMichael Chan #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 7228c0c050c5SMichael Chan u8 unused_0; 7229c0c050c5SMichael Chan __le16 tunnel_dst_port_id; 7230894aa69aSMichael Chan u8 unused_1[4]; 7231c0c050c5SMichael Chan }; 7232c0c050c5SMichael Chan 7233894aa69aSMichael Chan /* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 7234c0c050c5SMichael Chan struct hwrm_tunnel_dst_port_free_output { 7235c0c050c5SMichael Chan __le16 error_code; 7236c0c050c5SMichael Chan __le16 req_type; 7237c0c050c5SMichael Chan __le16 seq_id; 7238c0c050c5SMichael Chan __le16 resp_len; 7239894aa69aSMichael Chan u8 unused_1[7]; 7240c0c050c5SMichael Chan u8 valid; 7241c0c050c5SMichael Chan }; 7242c0c050c5SMichael Chan 7243894aa69aSMichael Chan /* ctx_hw_stats (size:1280b/160B) */ 7244894aa69aSMichael Chan struct ctx_hw_stats { 7245894aa69aSMichael Chan __le64 rx_ucast_pkts; 7246894aa69aSMichael Chan __le64 rx_mcast_pkts; 7247894aa69aSMichael Chan __le64 rx_bcast_pkts; 7248894aa69aSMichael Chan __le64 rx_discard_pkts; 7249bfc6e5fbSMichael Chan __le64 rx_error_pkts; 7250894aa69aSMichael Chan __le64 rx_ucast_bytes; 7251894aa69aSMichael Chan __le64 rx_mcast_bytes; 7252894aa69aSMichael Chan __le64 rx_bcast_bytes; 7253894aa69aSMichael Chan __le64 tx_ucast_pkts; 7254894aa69aSMichael Chan __le64 tx_mcast_pkts; 7255894aa69aSMichael Chan __le64 tx_bcast_pkts; 7256bfc6e5fbSMichael Chan __le64 tx_error_pkts; 7257894aa69aSMichael Chan __le64 tx_discard_pkts; 7258894aa69aSMichael Chan __le64 tx_ucast_bytes; 7259894aa69aSMichael Chan __le64 tx_mcast_bytes; 7260894aa69aSMichael Chan __le64 tx_bcast_bytes; 7261894aa69aSMichael Chan __le64 tpa_pkts; 7262894aa69aSMichael Chan __le64 tpa_bytes; 7263894aa69aSMichael Chan __le64 tpa_events; 7264894aa69aSMichael Chan __le64 tpa_aborts; 7265894aa69aSMichael Chan }; 7266894aa69aSMichael Chan 72679d6b648cSMichael Chan /* ctx_hw_stats_ext (size:1408b/176B) */ 72682792b5b9SMichael Chan struct ctx_hw_stats_ext { 72692792b5b9SMichael Chan __le64 rx_ucast_pkts; 72702792b5b9SMichael Chan __le64 rx_mcast_pkts; 72712792b5b9SMichael Chan __le64 rx_bcast_pkts; 72722792b5b9SMichael Chan __le64 rx_discard_pkts; 7273bfc6e5fbSMichael Chan __le64 rx_error_pkts; 72742792b5b9SMichael Chan __le64 rx_ucast_bytes; 72752792b5b9SMichael Chan __le64 rx_mcast_bytes; 72762792b5b9SMichael Chan __le64 rx_bcast_bytes; 72772792b5b9SMichael Chan __le64 tx_ucast_pkts; 72782792b5b9SMichael Chan __le64 tx_mcast_pkts; 72792792b5b9SMichael Chan __le64 tx_bcast_pkts; 7280bfc6e5fbSMichael Chan __le64 tx_error_pkts; 72812792b5b9SMichael Chan __le64 tx_discard_pkts; 72822792b5b9SMichael Chan __le64 tx_ucast_bytes; 72832792b5b9SMichael Chan __le64 tx_mcast_bytes; 72842792b5b9SMichael Chan __le64 tx_bcast_bytes; 72852792b5b9SMichael Chan __le64 rx_tpa_eligible_pkt; 72862792b5b9SMichael Chan __le64 rx_tpa_eligible_bytes; 72872792b5b9SMichael Chan __le64 rx_tpa_pkt; 72882792b5b9SMichael Chan __le64 rx_tpa_bytes; 72892792b5b9SMichael Chan __le64 rx_tpa_errors; 72909d6b648cSMichael Chan __le64 rx_tpa_events; 72912792b5b9SMichael Chan }; 72922792b5b9SMichael Chan 7293894aa69aSMichael Chan /* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 7294c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_input { 7295c0c050c5SMichael Chan __le16 req_type; 7296c0c050c5SMichael Chan __le16 cmpl_ring; 7297c0c050c5SMichael Chan __le16 seq_id; 7298c0c050c5SMichael Chan __le16 target_id; 7299c0c050c5SMichael Chan __le64 resp_addr; 7300c0c050c5SMichael Chan __le64 stats_dma_addr; 7301c0c050c5SMichael Chan __le32 update_period_ms; 730287c374deSMichael Chan u8 stat_ctx_flags; 730387c374deSMichael Chan #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 73042792b5b9SMichael Chan u8 unused_0; 73052792b5b9SMichael Chan __le16 stats_dma_length; 7306c0c050c5SMichael Chan }; 7307c0c050c5SMichael Chan 7308894aa69aSMichael Chan /* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 7309c0c050c5SMichael Chan struct hwrm_stat_ctx_alloc_output { 7310c0c050c5SMichael Chan __le16 error_code; 7311c0c050c5SMichael Chan __le16 req_type; 7312c0c050c5SMichael Chan __le16 seq_id; 7313c0c050c5SMichael Chan __le16 resp_len; 7314c0c050c5SMichael Chan __le32 stat_ctx_id; 7315894aa69aSMichael Chan u8 unused_0[3]; 7316c0c050c5SMichael Chan u8 valid; 7317c0c050c5SMichael Chan }; 7318c0c050c5SMichael Chan 7319894aa69aSMichael Chan /* hwrm_stat_ctx_free_input (size:192b/24B) */ 7320c0c050c5SMichael Chan struct hwrm_stat_ctx_free_input { 7321c0c050c5SMichael Chan __le16 req_type; 7322c0c050c5SMichael Chan __le16 cmpl_ring; 7323c0c050c5SMichael Chan __le16 seq_id; 7324c0c050c5SMichael Chan __le16 target_id; 7325c0c050c5SMichael Chan __le64 resp_addr; 7326c0c050c5SMichael Chan __le32 stat_ctx_id; 7327894aa69aSMichael Chan u8 unused_0[4]; 7328c0c050c5SMichael Chan }; 7329c0c050c5SMichael Chan 7330894aa69aSMichael Chan /* hwrm_stat_ctx_free_output (size:128b/16B) */ 7331c0c050c5SMichael Chan struct hwrm_stat_ctx_free_output { 7332c0c050c5SMichael Chan __le16 error_code; 7333c0c050c5SMichael Chan __le16 req_type; 7334c0c050c5SMichael Chan __le16 seq_id; 7335c0c050c5SMichael Chan __le16 resp_len; 7336c0c050c5SMichael Chan __le32 stat_ctx_id; 7337894aa69aSMichael Chan u8 unused_0[3]; 7338c0c050c5SMichael Chan u8 valid; 7339c0c050c5SMichael Chan }; 7340c0c050c5SMichael Chan 7341894aa69aSMichael Chan /* hwrm_stat_ctx_query_input (size:192b/24B) */ 7342c0c050c5SMichael Chan struct hwrm_stat_ctx_query_input { 7343c0c050c5SMichael Chan __le16 req_type; 7344c0c050c5SMichael Chan __le16 cmpl_ring; 7345c0c050c5SMichael Chan __le16 seq_id; 7346c0c050c5SMichael Chan __le16 target_id; 7347c0c050c5SMichael Chan __le64 resp_addr; 7348c0c050c5SMichael Chan __le32 stat_ctx_id; 7349bfc6e5fbSMichael Chan u8 flags; 7350bfc6e5fbSMichael Chan #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7351bfc6e5fbSMichael Chan u8 unused_0[3]; 7352c0c050c5SMichael Chan }; 7353c0c050c5SMichael Chan 7354894aa69aSMichael Chan /* hwrm_stat_ctx_query_output (size:1408b/176B) */ 7355c0c050c5SMichael Chan struct hwrm_stat_ctx_query_output { 7356c0c050c5SMichael Chan __le16 error_code; 7357c0c050c5SMichael Chan __le16 req_type; 7358c0c050c5SMichael Chan __le16 seq_id; 7359c0c050c5SMichael Chan __le16 resp_len; 7360c0c050c5SMichael Chan __le64 tx_ucast_pkts; 7361c0c050c5SMichael Chan __le64 tx_mcast_pkts; 7362c0c050c5SMichael Chan __le64 tx_bcast_pkts; 73639d6b648cSMichael Chan __le64 tx_discard_pkts; 73649d6b648cSMichael Chan __le64 tx_error_pkts; 7365c0c050c5SMichael Chan __le64 tx_ucast_bytes; 7366c0c050c5SMichael Chan __le64 tx_mcast_bytes; 7367c0c050c5SMichael Chan __le64 tx_bcast_bytes; 7368c0c050c5SMichael Chan __le64 rx_ucast_pkts; 7369c0c050c5SMichael Chan __le64 rx_mcast_pkts; 7370c0c050c5SMichael Chan __le64 rx_bcast_pkts; 73719d6b648cSMichael Chan __le64 rx_discard_pkts; 73729d6b648cSMichael Chan __le64 rx_error_pkts; 7373c0c050c5SMichael Chan __le64 rx_ucast_bytes; 7374c0c050c5SMichael Chan __le64 rx_mcast_bytes; 7375c0c050c5SMichael Chan __le64 rx_bcast_bytes; 7376c0c050c5SMichael Chan __le64 rx_agg_pkts; 7377c0c050c5SMichael Chan __le64 rx_agg_bytes; 7378c0c050c5SMichael Chan __le64 rx_agg_events; 7379c0c050c5SMichael Chan __le64 rx_agg_aborts; 7380894aa69aSMichael Chan u8 unused_0[7]; 7381c0c050c5SMichael Chan u8 valid; 7382c0c050c5SMichael Chan }; 7383c0c050c5SMichael Chan 7384bfc6e5fbSMichael Chan /* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 7385bfc6e5fbSMichael Chan struct hwrm_stat_ext_ctx_query_input { 7386bfc6e5fbSMichael Chan __le16 req_type; 7387bfc6e5fbSMichael Chan __le16 cmpl_ring; 7388bfc6e5fbSMichael Chan __le16 seq_id; 7389bfc6e5fbSMichael Chan __le16 target_id; 7390bfc6e5fbSMichael Chan __le64 resp_addr; 7391bfc6e5fbSMichael Chan __le32 stat_ctx_id; 7392bfc6e5fbSMichael Chan u8 flags; 7393bfc6e5fbSMichael Chan #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 7394bfc6e5fbSMichael Chan u8 unused_0[3]; 7395bfc6e5fbSMichael Chan }; 7396bfc6e5fbSMichael Chan 73979d6b648cSMichael Chan /* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 7398bfc6e5fbSMichael Chan struct hwrm_stat_ext_ctx_query_output { 7399bfc6e5fbSMichael Chan __le16 error_code; 7400bfc6e5fbSMichael Chan __le16 req_type; 7401bfc6e5fbSMichael Chan __le16 seq_id; 7402bfc6e5fbSMichael Chan __le16 resp_len; 7403bfc6e5fbSMichael Chan __le64 rx_ucast_pkts; 7404bfc6e5fbSMichael Chan __le64 rx_mcast_pkts; 7405bfc6e5fbSMichael Chan __le64 rx_bcast_pkts; 7406bfc6e5fbSMichael Chan __le64 rx_discard_pkts; 7407bfc6e5fbSMichael Chan __le64 rx_error_pkts; 7408bfc6e5fbSMichael Chan __le64 rx_ucast_bytes; 7409bfc6e5fbSMichael Chan __le64 rx_mcast_bytes; 7410bfc6e5fbSMichael Chan __le64 rx_bcast_bytes; 7411bfc6e5fbSMichael Chan __le64 tx_ucast_pkts; 7412bfc6e5fbSMichael Chan __le64 tx_mcast_pkts; 7413bfc6e5fbSMichael Chan __le64 tx_bcast_pkts; 7414bfc6e5fbSMichael Chan __le64 tx_error_pkts; 7415bfc6e5fbSMichael Chan __le64 tx_discard_pkts; 7416bfc6e5fbSMichael Chan __le64 tx_ucast_bytes; 7417bfc6e5fbSMichael Chan __le64 tx_mcast_bytes; 7418bfc6e5fbSMichael Chan __le64 tx_bcast_bytes; 7419bfc6e5fbSMichael Chan __le64 rx_tpa_eligible_pkt; 7420bfc6e5fbSMichael Chan __le64 rx_tpa_eligible_bytes; 7421bfc6e5fbSMichael Chan __le64 rx_tpa_pkt; 7422bfc6e5fbSMichael Chan __le64 rx_tpa_bytes; 7423bfc6e5fbSMichael Chan __le64 rx_tpa_errors; 74249d6b648cSMichael Chan __le64 rx_tpa_events; 7425bfc6e5fbSMichael Chan u8 unused_0[7]; 7426bfc6e5fbSMichael Chan u8 valid; 7427bfc6e5fbSMichael Chan }; 7428bfc6e5fbSMichael Chan 7429894aa69aSMichael Chan /* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 7430c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_input { 7431c0c050c5SMichael Chan __le16 req_type; 7432c0c050c5SMichael Chan __le16 cmpl_ring; 7433c0c050c5SMichael Chan __le16 seq_id; 7434c0c050c5SMichael Chan __le16 target_id; 7435c0c050c5SMichael Chan __le64 resp_addr; 7436c0c050c5SMichael Chan __le32 stat_ctx_id; 7437894aa69aSMichael Chan u8 unused_0[4]; 7438c0c050c5SMichael Chan }; 7439c0c050c5SMichael Chan 7440894aa69aSMichael Chan /* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 7441c0c050c5SMichael Chan struct hwrm_stat_ctx_clr_stats_output { 7442c0c050c5SMichael Chan __le16 error_code; 7443c0c050c5SMichael Chan __le16 req_type; 7444c0c050c5SMichael Chan __le16 seq_id; 7445c0c050c5SMichael Chan __le16 resp_len; 744611f15ed3SMichael Chan u8 unused_0[7]; 744711f15ed3SMichael Chan u8 valid; 744811f15ed3SMichael Chan }; 744911f15ed3SMichael Chan 7450d4f52de0SMichael Chan /* hwrm_pcie_qstats_input (size:256b/32B) */ 7451d4f52de0SMichael Chan struct hwrm_pcie_qstats_input { 7452d4f52de0SMichael Chan __le16 req_type; 7453d4f52de0SMichael Chan __le16 cmpl_ring; 7454d4f52de0SMichael Chan __le16 seq_id; 7455d4f52de0SMichael Chan __le16 target_id; 7456d4f52de0SMichael Chan __le64 resp_addr; 7457d4f52de0SMichael Chan __le16 pcie_stat_size; 7458d4f52de0SMichael Chan u8 unused_0[6]; 7459d4f52de0SMichael Chan __le64 pcie_stat_host_addr; 7460d4f52de0SMichael Chan }; 7461d4f52de0SMichael Chan 7462d4f52de0SMichael Chan /* hwrm_pcie_qstats_output (size:128b/16B) */ 7463d4f52de0SMichael Chan struct hwrm_pcie_qstats_output { 7464d4f52de0SMichael Chan __le16 error_code; 7465d4f52de0SMichael Chan __le16 req_type; 7466d4f52de0SMichael Chan __le16 seq_id; 7467d4f52de0SMichael Chan __le16 resp_len; 7468d4f52de0SMichael Chan __le16 pcie_stat_size; 7469d4f52de0SMichael Chan u8 unused_0[5]; 7470d4f52de0SMichael Chan u8 valid; 7471d4f52de0SMichael Chan }; 7472d4f52de0SMichael Chan 7473d4f52de0SMichael Chan /* pcie_ctx_hw_stats (size:768b/96B) */ 7474d4f52de0SMichael Chan struct pcie_ctx_hw_stats { 7475d4f52de0SMichael Chan __le64 pcie_pl_signal_integrity; 7476d4f52de0SMichael Chan __le64 pcie_dl_signal_integrity; 7477d4f52de0SMichael Chan __le64 pcie_tl_signal_integrity; 7478d4f52de0SMichael Chan __le64 pcie_link_integrity; 7479d4f52de0SMichael Chan __le64 pcie_tx_traffic_rate; 7480d4f52de0SMichael Chan __le64 pcie_rx_traffic_rate; 7481d4f52de0SMichael Chan __le64 pcie_tx_dllp_statistics; 7482d4f52de0SMichael Chan __le64 pcie_rx_dllp_statistics; 7483d4f52de0SMichael Chan __le64 pcie_equalization_time; 7484d4f52de0SMichael Chan __le32 pcie_ltssm_histogram[4]; 7485d4f52de0SMichael Chan __le64 pcie_recovery_histogram; 7486d4f52de0SMichael Chan }; 7487d4f52de0SMichael Chan 7488894aa69aSMichael Chan /* hwrm_fw_reset_input (size:192b/24B) */ 7489894aa69aSMichael Chan struct hwrm_fw_reset_input { 7490894aa69aSMichael Chan __le16 req_type; 7491894aa69aSMichael Chan __le16 cmpl_ring; 7492894aa69aSMichael Chan __le16 seq_id; 7493894aa69aSMichael Chan __le16 target_id; 7494894aa69aSMichael Chan __le64 resp_addr; 7495894aa69aSMichael Chan u8 embedded_proc_type; 7496894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7497894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7498894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7499894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7500894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7501894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7502894aa69aSMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7503d4f52de0SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 750472e0c9f9SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 750572e0c9f9SMichael Chan #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 7506894aa69aSMichael Chan u8 selfrst_status; 7507894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 7508894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 7509894aa69aSMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 751031d357c0SMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 751131d357c0SMichael Chan #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 7512894aa69aSMichael Chan u8 host_idx; 75133322479eSMichael Chan u8 flags; 75143322479eSMichael Chan #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 75153322479eSMichael Chan u8 unused_0[4]; 751657922b0aSMichael Chan }; 751757922b0aSMichael Chan 7518894aa69aSMichael Chan /* hwrm_fw_reset_output (size:128b/16B) */ 7519894aa69aSMichael Chan struct hwrm_fw_reset_output { 7520894aa69aSMichael Chan __le16 error_code; 7521894aa69aSMichael Chan __le16 req_type; 7522894aa69aSMichael Chan __le16 seq_id; 7523894aa69aSMichael Chan __le16 resp_len; 7524894aa69aSMichael Chan u8 selfrst_status; 7525894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7526894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7527894aa69aSMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 752831d357c0SMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 752931d357c0SMichael Chan #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 7530894aa69aSMichael Chan u8 unused_0[6]; 7531894aa69aSMichael Chan u8 valid; 753257922b0aSMichael Chan }; 753357922b0aSMichael Chan 7534894aa69aSMichael Chan /* hwrm_fw_qstatus_input (size:192b/24B) */ 7535894aa69aSMichael Chan struct hwrm_fw_qstatus_input { 7536894aa69aSMichael Chan __le16 req_type; 7537894aa69aSMichael Chan __le16 cmpl_ring; 7538894aa69aSMichael Chan __le16 seq_id; 7539894aa69aSMichael Chan __le16 target_id; 7540894aa69aSMichael Chan __le64 resp_addr; 7541894aa69aSMichael Chan u8 embedded_proc_type; 7542894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 7543894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 7544894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 7545894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 7546894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 7547894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 7548894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 7549894aa69aSMichael Chan #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 7550894aa69aSMichael Chan u8 unused_0[7]; 755157922b0aSMichael Chan }; 755257922b0aSMichael Chan 7553894aa69aSMichael Chan /* hwrm_fw_qstatus_output (size:128b/16B) */ 7554894aa69aSMichael Chan struct hwrm_fw_qstatus_output { 7555894aa69aSMichael Chan __le16 error_code; 7556894aa69aSMichael Chan __le16 req_type; 7557894aa69aSMichael Chan __le16 seq_id; 7558894aa69aSMichael Chan __le16 resp_len; 7559894aa69aSMichael Chan u8 selfrst_status; 7560894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 7561894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 7562894aa69aSMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 75634a50ddc2SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 75644a50ddc2SMichael Chan #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 7565894aa69aSMichael Chan u8 unused_0[6]; 7566894aa69aSMichael Chan u8 valid; 756787c374deSMichael Chan }; 756887c374deSMichael Chan 7569894aa69aSMichael Chan /* hwrm_fw_set_time_input (size:256b/32B) */ 7570894aa69aSMichael Chan struct hwrm_fw_set_time_input { 7571894aa69aSMichael Chan __le16 req_type; 7572894aa69aSMichael Chan __le16 cmpl_ring; 7573894aa69aSMichael Chan __le16 seq_id; 7574894aa69aSMichael Chan __le16 target_id; 7575894aa69aSMichael Chan __le64 resp_addr; 7576894aa69aSMichael Chan __le16 year; 7577894aa69aSMichael Chan #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 7578894aa69aSMichael Chan #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 7579894aa69aSMichael Chan u8 month; 7580894aa69aSMichael Chan u8 day; 7581894aa69aSMichael Chan u8 hour; 7582894aa69aSMichael Chan u8 minute; 7583894aa69aSMichael Chan u8 second; 7584894aa69aSMichael Chan u8 unused_0; 7585894aa69aSMichael Chan __le16 millisecond; 7586894aa69aSMichael Chan __le16 zone; 75874a50ddc2SMichael Chan #define FW_SET_TIME_REQ_ZONE_UTC 0 75884a50ddc2SMichael Chan #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 7589894aa69aSMichael Chan #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 7590894aa69aSMichael Chan u8 unused_1[4]; 7591894aa69aSMichael Chan }; 7592894aa69aSMichael Chan 7593894aa69aSMichael Chan /* hwrm_fw_set_time_output (size:128b/16B) */ 7594894aa69aSMichael Chan struct hwrm_fw_set_time_output { 7595894aa69aSMichael Chan __le16 error_code; 7596894aa69aSMichael Chan __le16 req_type; 7597894aa69aSMichael Chan __le16 seq_id; 7598894aa69aSMichael Chan __le16 resp_len; 7599894aa69aSMichael Chan u8 unused_0[7]; 7600894aa69aSMichael Chan u8 valid; 7601894aa69aSMichael Chan }; 7602894aa69aSMichael Chan 7603894aa69aSMichael Chan /* hwrm_struct_hdr (size:128b/16B) */ 760487c374deSMichael Chan struct hwrm_struct_hdr { 760587c374deSMichael Chan __le16 struct_id; 760687c374deSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 7607f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 7608f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 7609f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 7610f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 7611f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 7612f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 76133322479eSMichael Chan #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 76148eb992e8SMichael Chan #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7615f183886cSMichael Chan #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 76166a17eb27SMichael Chan #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7617*16db6323SMichael Chan #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 7618*16db6323SMichael Chan #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 761987c374deSMichael Chan __le16 len; 762087c374deSMichael Chan u8 version; 762187c374deSMichael Chan u8 count; 762287c374deSMichael Chan __le16 subtype; 762387c374deSMichael Chan __le16 next_offset; 762487c374deSMichael Chan #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 7625894aa69aSMichael Chan u8 unused_0[6]; 762687c374deSMichael Chan }; 762787c374deSMichael Chan 7628894aa69aSMichael Chan /* hwrm_struct_data_dcbx_app (size:64b/8B) */ 7629f183886cSMichael Chan struct hwrm_struct_data_dcbx_app { 7630f183886cSMichael Chan __be16 protocol_id; 763187c374deSMichael Chan u8 protocol_selector; 7632f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 7633f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 7634f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 7635f183886cSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 7636894aa69aSMichael Chan #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 763787c374deSMichael Chan u8 priority; 763887c374deSMichael Chan u8 valid; 763987c374deSMichael Chan u8 unused_0[3]; 764087c374deSMichael Chan }; 764187c374deSMichael Chan 7642894aa69aSMichael Chan /* hwrm_fw_set_structured_data_input (size:256b/32B) */ 7643894aa69aSMichael Chan struct hwrm_fw_set_structured_data_input { 7644894aa69aSMichael Chan __le16 req_type; 7645894aa69aSMichael Chan __le16 cmpl_ring; 7646894aa69aSMichael Chan __le16 seq_id; 7647894aa69aSMichael Chan __le16 target_id; 7648894aa69aSMichael Chan __le64 resp_addr; 7649894aa69aSMichael Chan __le64 src_data_addr; 7650894aa69aSMichael Chan __le16 data_len; 7651894aa69aSMichael Chan u8 hdr_cnt; 7652894aa69aSMichael Chan u8 unused_0[5]; 7653894aa69aSMichael Chan }; 7654894aa69aSMichael Chan 7655894aa69aSMichael Chan /* hwrm_fw_set_structured_data_output (size:128b/16B) */ 7656894aa69aSMichael Chan struct hwrm_fw_set_structured_data_output { 7657894aa69aSMichael Chan __le16 error_code; 7658894aa69aSMichael Chan __le16 req_type; 7659894aa69aSMichael Chan __le16 seq_id; 7660894aa69aSMichael Chan __le16 resp_len; 7661894aa69aSMichael Chan u8 unused_0[7]; 7662894aa69aSMichael Chan u8 valid; 7663894aa69aSMichael Chan }; 7664894aa69aSMichael Chan 7665894aa69aSMichael Chan /* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 7666894aa69aSMichael Chan struct hwrm_fw_set_structured_data_cmd_err { 7667894aa69aSMichael Chan u8 code; 7668894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7669894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 7670894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 7671894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7672894aa69aSMichael Chan #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7673894aa69aSMichael Chan u8 unused_0[7]; 7674894aa69aSMichael Chan }; 7675894aa69aSMichael Chan 7676894aa69aSMichael Chan /* hwrm_fw_get_structured_data_input (size:256b/32B) */ 7677894aa69aSMichael Chan struct hwrm_fw_get_structured_data_input { 7678894aa69aSMichael Chan __le16 req_type; 7679894aa69aSMichael Chan __le16 cmpl_ring; 7680894aa69aSMichael Chan __le16 seq_id; 7681894aa69aSMichael Chan __le16 target_id; 7682894aa69aSMichael Chan __le64 resp_addr; 7683894aa69aSMichael Chan __le64 dest_data_addr; 7684894aa69aSMichael Chan __le16 data_len; 7685894aa69aSMichael Chan __le16 structure_id; 7686894aa69aSMichael Chan __le16 subtype; 7687894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 7688894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 7689894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 7690894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 7691894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 7692894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 7693894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 7694894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 7695894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 7696894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 7697894aa69aSMichael Chan u8 count; 7698894aa69aSMichael Chan u8 unused_0; 7699894aa69aSMichael Chan }; 7700894aa69aSMichael Chan 7701894aa69aSMichael Chan /* hwrm_fw_get_structured_data_output (size:128b/16B) */ 7702894aa69aSMichael Chan struct hwrm_fw_get_structured_data_output { 7703894aa69aSMichael Chan __le16 error_code; 7704894aa69aSMichael Chan __le16 req_type; 7705894aa69aSMichael Chan __le16 seq_id; 7706894aa69aSMichael Chan __le16 resp_len; 7707894aa69aSMichael Chan u8 hdr_cnt; 7708894aa69aSMichael Chan u8 unused_0[6]; 7709894aa69aSMichael Chan u8 valid; 7710894aa69aSMichael Chan }; 7711894aa69aSMichael Chan 7712894aa69aSMichael Chan /* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 7713894aa69aSMichael Chan struct hwrm_fw_get_structured_data_cmd_err { 7714894aa69aSMichael Chan u8 code; 7715894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 7716894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 7717894aa69aSMichael Chan #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 7718894aa69aSMichael Chan u8 unused_0[7]; 7719894aa69aSMichael Chan }; 7720894aa69aSMichael Chan 7721894aa69aSMichael Chan /* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 7722894aa69aSMichael Chan struct hwrm_exec_fwd_resp_input { 7723894aa69aSMichael Chan __le16 req_type; 7724894aa69aSMichael Chan __le16 cmpl_ring; 7725894aa69aSMichael Chan __le16 seq_id; 7726894aa69aSMichael Chan __le16 target_id; 7727894aa69aSMichael Chan __le64 resp_addr; 7728894aa69aSMichael Chan __le32 encap_request[26]; 7729894aa69aSMichael Chan __le16 encap_resp_target_id; 7730894aa69aSMichael Chan u8 unused_0[6]; 7731894aa69aSMichael Chan }; 7732894aa69aSMichael Chan 7733894aa69aSMichael Chan /* hwrm_exec_fwd_resp_output (size:128b/16B) */ 7734894aa69aSMichael Chan struct hwrm_exec_fwd_resp_output { 7735894aa69aSMichael Chan __le16 error_code; 7736894aa69aSMichael Chan __le16 req_type; 7737894aa69aSMichael Chan __le16 seq_id; 7738894aa69aSMichael Chan __le16 resp_len; 7739894aa69aSMichael Chan u8 unused_0[7]; 7740894aa69aSMichael Chan u8 valid; 7741894aa69aSMichael Chan }; 7742894aa69aSMichael Chan 7743894aa69aSMichael Chan /* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 7744894aa69aSMichael Chan struct hwrm_reject_fwd_resp_input { 7745894aa69aSMichael Chan __le16 req_type; 7746894aa69aSMichael Chan __le16 cmpl_ring; 7747894aa69aSMichael Chan __le16 seq_id; 7748894aa69aSMichael Chan __le16 target_id; 7749894aa69aSMichael Chan __le64 resp_addr; 7750894aa69aSMichael Chan __le32 encap_request[26]; 7751894aa69aSMichael Chan __le16 encap_resp_target_id; 7752894aa69aSMichael Chan u8 unused_0[6]; 7753894aa69aSMichael Chan }; 7754894aa69aSMichael Chan 7755894aa69aSMichael Chan /* hwrm_reject_fwd_resp_output (size:128b/16B) */ 7756894aa69aSMichael Chan struct hwrm_reject_fwd_resp_output { 7757894aa69aSMichael Chan __le16 error_code; 7758894aa69aSMichael Chan __le16 req_type; 7759894aa69aSMichael Chan __le16 seq_id; 7760894aa69aSMichael Chan __le16 resp_len; 7761894aa69aSMichael Chan u8 unused_0[7]; 7762894aa69aSMichael Chan u8 valid; 7763894aa69aSMichael Chan }; 7764894aa69aSMichael Chan 7765894aa69aSMichael Chan /* hwrm_fwd_resp_input (size:1024b/128B) */ 7766894aa69aSMichael Chan struct hwrm_fwd_resp_input { 7767894aa69aSMichael Chan __le16 req_type; 7768894aa69aSMichael Chan __le16 cmpl_ring; 7769894aa69aSMichael Chan __le16 seq_id; 7770894aa69aSMichael Chan __le16 target_id; 7771894aa69aSMichael Chan __le64 resp_addr; 7772894aa69aSMichael Chan __le16 encap_resp_target_id; 7773894aa69aSMichael Chan __le16 encap_resp_cmpl_ring; 7774894aa69aSMichael Chan __le16 encap_resp_len; 7775894aa69aSMichael Chan u8 unused_0; 7776894aa69aSMichael Chan u8 unused_1; 7777894aa69aSMichael Chan __le64 encap_resp_addr; 7778894aa69aSMichael Chan __le32 encap_resp[24]; 7779894aa69aSMichael Chan }; 7780894aa69aSMichael Chan 7781894aa69aSMichael Chan /* hwrm_fwd_resp_output (size:128b/16B) */ 7782894aa69aSMichael Chan struct hwrm_fwd_resp_output { 7783894aa69aSMichael Chan __le16 error_code; 7784894aa69aSMichael Chan __le16 req_type; 7785894aa69aSMichael Chan __le16 seq_id; 7786894aa69aSMichael Chan __le16 resp_len; 7787894aa69aSMichael Chan u8 unused_0[7]; 7788894aa69aSMichael Chan u8 valid; 7789894aa69aSMichael Chan }; 7790894aa69aSMichael Chan 7791894aa69aSMichael Chan /* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 7792894aa69aSMichael Chan struct hwrm_fwd_async_event_cmpl_input { 7793894aa69aSMichael Chan __le16 req_type; 7794894aa69aSMichael Chan __le16 cmpl_ring; 7795894aa69aSMichael Chan __le16 seq_id; 7796894aa69aSMichael Chan __le16 target_id; 7797894aa69aSMichael Chan __le64 resp_addr; 7798894aa69aSMichael Chan __le16 encap_async_event_target_id; 7799894aa69aSMichael Chan u8 unused_0[6]; 7800894aa69aSMichael Chan __le32 encap_async_event_cmpl[4]; 7801894aa69aSMichael Chan }; 7802894aa69aSMichael Chan 7803894aa69aSMichael Chan /* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 7804894aa69aSMichael Chan struct hwrm_fwd_async_event_cmpl_output { 7805894aa69aSMichael Chan __le16 error_code; 7806894aa69aSMichael Chan __le16 req_type; 7807894aa69aSMichael Chan __le16 seq_id; 7808894aa69aSMichael Chan __le16 resp_len; 7809894aa69aSMichael Chan u8 unused_0[7]; 7810894aa69aSMichael Chan u8 valid; 7811894aa69aSMichael Chan }; 7812894aa69aSMichael Chan 7813894aa69aSMichael Chan /* hwrm_temp_monitor_query_input (size:128b/16B) */ 7814894aa69aSMichael Chan struct hwrm_temp_monitor_query_input { 7815894aa69aSMichael Chan __le16 req_type; 7816894aa69aSMichael Chan __le16 cmpl_ring; 7817894aa69aSMichael Chan __le16 seq_id; 7818894aa69aSMichael Chan __le16 target_id; 7819894aa69aSMichael Chan __le64 resp_addr; 7820894aa69aSMichael Chan }; 7821894aa69aSMichael Chan 7822894aa69aSMichael Chan /* hwrm_temp_monitor_query_output (size:128b/16B) */ 7823894aa69aSMichael Chan struct hwrm_temp_monitor_query_output { 7824894aa69aSMichael Chan __le16 error_code; 7825894aa69aSMichael Chan __le16 req_type; 7826894aa69aSMichael Chan __le16 seq_id; 7827894aa69aSMichael Chan __le16 resp_len; 7828894aa69aSMichael Chan u8 temp; 782972e0c9f9SMichael Chan u8 phy_temp; 783072e0c9f9SMichael Chan u8 om_temp; 783172e0c9f9SMichael Chan u8 flags; 783272e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 783372e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 783472e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 783572e0c9f9SMichael Chan #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 783672e0c9f9SMichael Chan u8 unused_0[3]; 7837894aa69aSMichael Chan u8 valid; 7838894aa69aSMichael Chan }; 7839894aa69aSMichael Chan 7840894aa69aSMichael Chan /* hwrm_wol_filter_alloc_input (size:512b/64B) */ 7841894aa69aSMichael Chan struct hwrm_wol_filter_alloc_input { 7842894aa69aSMichael Chan __le16 req_type; 7843894aa69aSMichael Chan __le16 cmpl_ring; 7844894aa69aSMichael Chan __le16 seq_id; 7845894aa69aSMichael Chan __le16 target_id; 7846894aa69aSMichael Chan __le64 resp_addr; 7847894aa69aSMichael Chan __le32 flags; 7848894aa69aSMichael Chan __le32 enables; 7849894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 7850894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 7851894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 7852894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 7853894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 7854894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 7855894aa69aSMichael Chan __le16 port_id; 7856894aa69aSMichael Chan u8 wol_type; 7857894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 7858894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 7859894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 7860894aa69aSMichael Chan #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 7861894aa69aSMichael Chan u8 unused_0[5]; 7862894aa69aSMichael Chan u8 mac_address[6]; 7863894aa69aSMichael Chan __le16 pattern_offset; 7864894aa69aSMichael Chan __le16 pattern_buf_size; 7865894aa69aSMichael Chan __le16 pattern_mask_size; 7866894aa69aSMichael Chan u8 unused_1[4]; 7867894aa69aSMichael Chan __le64 pattern_buf_addr; 7868894aa69aSMichael Chan __le64 pattern_mask_addr; 7869894aa69aSMichael Chan }; 7870894aa69aSMichael Chan 7871894aa69aSMichael Chan /* hwrm_wol_filter_alloc_output (size:128b/16B) */ 7872894aa69aSMichael Chan struct hwrm_wol_filter_alloc_output { 7873894aa69aSMichael Chan __le16 error_code; 7874894aa69aSMichael Chan __le16 req_type; 7875894aa69aSMichael Chan __le16 seq_id; 7876894aa69aSMichael Chan __le16 resp_len; 7877894aa69aSMichael Chan u8 wol_filter_id; 7878894aa69aSMichael Chan u8 unused_0[6]; 7879894aa69aSMichael Chan u8 valid; 7880894aa69aSMichael Chan }; 7881894aa69aSMichael Chan 7882894aa69aSMichael Chan /* hwrm_wol_filter_free_input (size:256b/32B) */ 7883894aa69aSMichael Chan struct hwrm_wol_filter_free_input { 7884894aa69aSMichael Chan __le16 req_type; 7885894aa69aSMichael Chan __le16 cmpl_ring; 7886894aa69aSMichael Chan __le16 seq_id; 7887894aa69aSMichael Chan __le16 target_id; 7888894aa69aSMichael Chan __le64 resp_addr; 7889894aa69aSMichael Chan __le32 flags; 7890894aa69aSMichael Chan #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 7891894aa69aSMichael Chan __le32 enables; 7892894aa69aSMichael Chan #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 7893894aa69aSMichael Chan __le16 port_id; 7894894aa69aSMichael Chan u8 wol_filter_id; 7895894aa69aSMichael Chan u8 unused_0[5]; 7896894aa69aSMichael Chan }; 7897894aa69aSMichael Chan 7898894aa69aSMichael Chan /* hwrm_wol_filter_free_output (size:128b/16B) */ 7899894aa69aSMichael Chan struct hwrm_wol_filter_free_output { 7900894aa69aSMichael Chan __le16 error_code; 7901894aa69aSMichael Chan __le16 req_type; 7902894aa69aSMichael Chan __le16 seq_id; 7903894aa69aSMichael Chan __le16 resp_len; 7904894aa69aSMichael Chan u8 unused_0[7]; 7905894aa69aSMichael Chan u8 valid; 7906894aa69aSMichael Chan }; 7907894aa69aSMichael Chan 7908894aa69aSMichael Chan /* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 7909894aa69aSMichael Chan struct hwrm_wol_filter_qcfg_input { 7910894aa69aSMichael Chan __le16 req_type; 7911894aa69aSMichael Chan __le16 cmpl_ring; 7912894aa69aSMichael Chan __le16 seq_id; 7913894aa69aSMichael Chan __le16 target_id; 7914894aa69aSMichael Chan __le64 resp_addr; 7915894aa69aSMichael Chan __le16 port_id; 7916894aa69aSMichael Chan __le16 handle; 7917894aa69aSMichael Chan u8 unused_0[4]; 7918894aa69aSMichael Chan __le64 pattern_buf_addr; 7919894aa69aSMichael Chan __le16 pattern_buf_size; 7920894aa69aSMichael Chan u8 unused_1[6]; 7921894aa69aSMichael Chan __le64 pattern_mask_addr; 7922894aa69aSMichael Chan __le16 pattern_mask_size; 7923894aa69aSMichael Chan u8 unused_2[6]; 7924894aa69aSMichael Chan }; 7925894aa69aSMichael Chan 7926894aa69aSMichael Chan /* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 7927894aa69aSMichael Chan struct hwrm_wol_filter_qcfg_output { 7928894aa69aSMichael Chan __le16 error_code; 7929894aa69aSMichael Chan __le16 req_type; 7930894aa69aSMichael Chan __le16 seq_id; 7931894aa69aSMichael Chan __le16 resp_len; 7932894aa69aSMichael Chan __le16 next_handle; 7933894aa69aSMichael Chan u8 wol_filter_id; 7934894aa69aSMichael Chan u8 wol_type; 7935894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 7936894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 7937894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 7938894aa69aSMichael Chan #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 7939894aa69aSMichael Chan __le32 unused_0; 7940894aa69aSMichael Chan u8 mac_address[6]; 7941894aa69aSMichael Chan __le16 pattern_offset; 7942894aa69aSMichael Chan __le16 pattern_size; 7943894aa69aSMichael Chan __le16 pattern_mask_size; 7944894aa69aSMichael Chan u8 unused_1[3]; 7945894aa69aSMichael Chan u8 valid; 7946894aa69aSMichael Chan }; 7947894aa69aSMichael Chan 7948894aa69aSMichael Chan /* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 7949894aa69aSMichael Chan struct hwrm_wol_reason_qcfg_input { 7950894aa69aSMichael Chan __le16 req_type; 7951894aa69aSMichael Chan __le16 cmpl_ring; 7952894aa69aSMichael Chan __le16 seq_id; 7953894aa69aSMichael Chan __le16 target_id; 7954894aa69aSMichael Chan __le64 resp_addr; 7955894aa69aSMichael Chan __le16 port_id; 7956894aa69aSMichael Chan u8 unused_0[6]; 7957894aa69aSMichael Chan __le64 wol_pkt_buf_addr; 7958894aa69aSMichael Chan __le16 wol_pkt_buf_size; 7959894aa69aSMichael Chan u8 unused_1[6]; 7960894aa69aSMichael Chan }; 7961894aa69aSMichael Chan 7962894aa69aSMichael Chan /* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 7963894aa69aSMichael Chan struct hwrm_wol_reason_qcfg_output { 7964894aa69aSMichael Chan __le16 error_code; 7965894aa69aSMichael Chan __le16 req_type; 7966894aa69aSMichael Chan __le16 seq_id; 7967894aa69aSMichael Chan __le16 resp_len; 7968894aa69aSMichael Chan u8 wol_filter_id; 7969894aa69aSMichael Chan u8 wol_reason; 7970894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 7971894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 7972894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 7973894aa69aSMichael Chan #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 7974894aa69aSMichael Chan u8 wol_pkt_len; 7975894aa69aSMichael Chan u8 unused_0[4]; 7976894aa69aSMichael Chan u8 valid; 7977894aa69aSMichael Chan }; 7978894aa69aSMichael Chan 7979bfc6e5fbSMichael Chan /* hwrm_dbg_read_direct_input (size:256b/32B) */ 7980bfc6e5fbSMichael Chan struct hwrm_dbg_read_direct_input { 7981bfc6e5fbSMichael Chan __le16 req_type; 7982bfc6e5fbSMichael Chan __le16 cmpl_ring; 7983bfc6e5fbSMichael Chan __le16 seq_id; 7984bfc6e5fbSMichael Chan __le16 target_id; 7985bfc6e5fbSMichael Chan __le64 resp_addr; 7986bfc6e5fbSMichael Chan __le64 host_dest_addr; 7987bfc6e5fbSMichael Chan __le32 read_addr; 7988bfc6e5fbSMichael Chan __le32 read_len32; 7989bfc6e5fbSMichael Chan }; 7990bfc6e5fbSMichael Chan 7991bfc6e5fbSMichael Chan /* hwrm_dbg_read_direct_output (size:128b/16B) */ 7992bfc6e5fbSMichael Chan struct hwrm_dbg_read_direct_output { 7993bfc6e5fbSMichael Chan __le16 error_code; 7994bfc6e5fbSMichael Chan __le16 req_type; 7995bfc6e5fbSMichael Chan __le16 seq_id; 7996bfc6e5fbSMichael Chan __le16 resp_len; 7997bfc6e5fbSMichael Chan __le32 crc32; 7998bfc6e5fbSMichael Chan u8 unused_0[3]; 7999bfc6e5fbSMichael Chan u8 valid; 8000bfc6e5fbSMichael Chan }; 8001bfc6e5fbSMichael Chan 80029d6b648cSMichael Chan /* hwrm_dbg_qcaps_input (size:192b/24B) */ 80039d6b648cSMichael Chan struct hwrm_dbg_qcaps_input { 80049d6b648cSMichael Chan __le16 req_type; 80059d6b648cSMichael Chan __le16 cmpl_ring; 80069d6b648cSMichael Chan __le16 seq_id; 80079d6b648cSMichael Chan __le16 target_id; 80089d6b648cSMichael Chan __le64 resp_addr; 80099d6b648cSMichael Chan __le16 fid; 80109d6b648cSMichael Chan u8 unused_0[6]; 80119d6b648cSMichael Chan }; 80129d6b648cSMichael Chan 80139d6b648cSMichael Chan /* hwrm_dbg_qcaps_output (size:192b/24B) */ 80149d6b648cSMichael Chan struct hwrm_dbg_qcaps_output { 80159d6b648cSMichael Chan __le16 error_code; 80169d6b648cSMichael Chan __le16 req_type; 80179d6b648cSMichael Chan __le16 seq_id; 80189d6b648cSMichael Chan __le16 resp_len; 80199d6b648cSMichael Chan __le16 fid; 80209d6b648cSMichael Chan u8 unused_0[2]; 80219d6b648cSMichael Chan __le32 coredump_component_disable_caps; 80229d6b648cSMichael Chan #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 80239d6b648cSMichael Chan __le32 flags; 80249d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 80259d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 80269d6b648cSMichael Chan #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 80279d6b648cSMichael Chan u8 unused_1[3]; 80289d6b648cSMichael Chan u8 valid; 80299d6b648cSMichael Chan }; 80309d6b648cSMichael Chan 80319d6b648cSMichael Chan /* hwrm_dbg_qcfg_input (size:192b/24B) */ 80329d6b648cSMichael Chan struct hwrm_dbg_qcfg_input { 80339d6b648cSMichael Chan __le16 req_type; 80349d6b648cSMichael Chan __le16 cmpl_ring; 80359d6b648cSMichael Chan __le16 seq_id; 80369d6b648cSMichael Chan __le16 target_id; 80379d6b648cSMichael Chan __le64 resp_addr; 80389d6b648cSMichael Chan __le16 fid; 80399d6b648cSMichael Chan __le16 flags; 80409d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 80419d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 80429d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 80439d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 80449d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 80459d6b648cSMichael Chan #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 80469d6b648cSMichael Chan __le32 coredump_component_disable_flags; 80479d6b648cSMichael Chan #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 80489d6b648cSMichael Chan }; 80499d6b648cSMichael Chan 80509d6b648cSMichael Chan /* hwrm_dbg_qcfg_output (size:256b/32B) */ 80519d6b648cSMichael Chan struct hwrm_dbg_qcfg_output { 80529d6b648cSMichael Chan __le16 error_code; 80539d6b648cSMichael Chan __le16 req_type; 80549d6b648cSMichael Chan __le16 seq_id; 80559d6b648cSMichael Chan __le16 resp_len; 80569d6b648cSMichael Chan __le16 fid; 80579d6b648cSMichael Chan u8 unused_0[2]; 80589d6b648cSMichael Chan __le32 coredump_size; 80599d6b648cSMichael Chan __le32 flags; 80609d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 80619d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 80629d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 80639d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 80649d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 80659d6b648cSMichael Chan #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 80669d6b648cSMichael Chan __le16 async_cmpl_ring; 80679d6b648cSMichael Chan u8 unused_2[2]; 80689d6b648cSMichael Chan __le32 crashdump_size; 80699d6b648cSMichael Chan u8 unused_3[3]; 80709d6b648cSMichael Chan u8 valid; 80719d6b648cSMichael Chan }; 80729d6b648cSMichael Chan 80736fc92c33SMichael Chan /* coredump_segment_record (size:128b/16B) */ 80746fc92c33SMichael Chan struct coredump_segment_record { 80756fc92c33SMichael Chan __le16 component_id; 80766fc92c33SMichael Chan __le16 segment_id; 80776fc92c33SMichael Chan __le16 max_instances; 80786fc92c33SMichael Chan u8 version_hi; 80796fc92c33SMichael Chan u8 version_low; 80806fc92c33SMichael Chan u8 seg_flags; 80812792b5b9SMichael Chan u8 compress_flags; 80822792b5b9SMichael Chan #define SFLAG_COMPRESSED_ZLIB 0x1UL 8083bfc6e5fbSMichael Chan u8 unused_0[2]; 8084bfc6e5fbSMichael Chan __le32 segment_len; 80856fc92c33SMichael Chan }; 80866fc92c33SMichael Chan 80876fc92c33SMichael Chan /* hwrm_dbg_coredump_list_input (size:256b/32B) */ 80886fc92c33SMichael Chan struct hwrm_dbg_coredump_list_input { 80896fc92c33SMichael Chan __le16 req_type; 80906fc92c33SMichael Chan __le16 cmpl_ring; 80916fc92c33SMichael Chan __le16 seq_id; 80926fc92c33SMichael Chan __le16 target_id; 80936fc92c33SMichael Chan __le64 resp_addr; 80946fc92c33SMichael Chan __le64 host_dest_addr; 80956fc92c33SMichael Chan __le32 host_buf_len; 80966fc92c33SMichael Chan __le16 seq_no; 80974a50ddc2SMichael Chan u8 flags; 80984a50ddc2SMichael Chan #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 80994a50ddc2SMichael Chan u8 unused_0[1]; 81006fc92c33SMichael Chan }; 81016fc92c33SMichael Chan 81026fc92c33SMichael Chan /* hwrm_dbg_coredump_list_output (size:128b/16B) */ 81036fc92c33SMichael Chan struct hwrm_dbg_coredump_list_output { 81046fc92c33SMichael Chan __le16 error_code; 81056fc92c33SMichael Chan __le16 req_type; 81066fc92c33SMichael Chan __le16 seq_id; 81076fc92c33SMichael Chan __le16 resp_len; 81086fc92c33SMichael Chan u8 flags; 81096fc92c33SMichael Chan #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 81106fc92c33SMichael Chan u8 unused_0; 81116fc92c33SMichael Chan __le16 total_segments; 81126fc92c33SMichael Chan __le16 data_len; 81136fc92c33SMichael Chan u8 unused_1; 81146fc92c33SMichael Chan u8 valid; 81156fc92c33SMichael Chan }; 81166fc92c33SMichael Chan 81176fc92c33SMichael Chan /* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 81186fc92c33SMichael Chan struct hwrm_dbg_coredump_initiate_input { 81196fc92c33SMichael Chan __le16 req_type; 81206fc92c33SMichael Chan __le16 cmpl_ring; 81216fc92c33SMichael Chan __le16 seq_id; 81226fc92c33SMichael Chan __le16 target_id; 81236fc92c33SMichael Chan __le64 resp_addr; 81246fc92c33SMichael Chan __le16 component_id; 81256fc92c33SMichael Chan __le16 segment_id; 81266fc92c33SMichael Chan __le16 instance; 81276fc92c33SMichael Chan __le16 unused_0; 81286fc92c33SMichael Chan u8 seg_flags; 81296fc92c33SMichael Chan u8 unused_1[7]; 81306fc92c33SMichael Chan }; 81316fc92c33SMichael Chan 81326fc92c33SMichael Chan /* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 81336fc92c33SMichael Chan struct hwrm_dbg_coredump_initiate_output { 81346fc92c33SMichael Chan __le16 error_code; 81356fc92c33SMichael Chan __le16 req_type; 81366fc92c33SMichael Chan __le16 seq_id; 81376fc92c33SMichael Chan __le16 resp_len; 81386fc92c33SMichael Chan u8 unused_0[7]; 81396fc92c33SMichael Chan u8 valid; 81406fc92c33SMichael Chan }; 81416fc92c33SMichael Chan 81426fc92c33SMichael Chan /* coredump_data_hdr (size:128b/16B) */ 81436fc92c33SMichael Chan struct coredump_data_hdr { 81446fc92c33SMichael Chan __le32 address; 81456fc92c33SMichael Chan __le32 flags_length; 8146*16db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8147*16db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8148*16db6323SMichael Chan #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 81496fc92c33SMichael Chan __le32 instance; 81506fc92c33SMichael Chan __le32 next_offset; 81516fc92c33SMichael Chan }; 81526fc92c33SMichael Chan 81536fc92c33SMichael Chan /* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 81546fc92c33SMichael Chan struct hwrm_dbg_coredump_retrieve_input { 81556fc92c33SMichael Chan __le16 req_type; 81566fc92c33SMichael Chan __le16 cmpl_ring; 81576fc92c33SMichael Chan __le16 seq_id; 81586fc92c33SMichael Chan __le16 target_id; 81596fc92c33SMichael Chan __le64 resp_addr; 81606fc92c33SMichael Chan __le64 host_dest_addr; 81616fc92c33SMichael Chan __le32 host_buf_len; 81626fc92c33SMichael Chan __le32 unused_0; 81636fc92c33SMichael Chan __le16 component_id; 81646fc92c33SMichael Chan __le16 segment_id; 81656fc92c33SMichael Chan __le16 instance; 81666fc92c33SMichael Chan __le16 unused_1; 81676fc92c33SMichael Chan u8 seg_flags; 81686fc92c33SMichael Chan u8 unused_2; 81696fc92c33SMichael Chan __le16 unused_3; 81706fc92c33SMichael Chan __le32 unused_4; 81716fc92c33SMichael Chan __le32 seq_no; 81726fc92c33SMichael Chan __le32 unused_5; 81736fc92c33SMichael Chan }; 81746fc92c33SMichael Chan 81756fc92c33SMichael Chan /* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 81766fc92c33SMichael Chan struct hwrm_dbg_coredump_retrieve_output { 81776fc92c33SMichael Chan __le16 error_code; 81786fc92c33SMichael Chan __le16 req_type; 81796fc92c33SMichael Chan __le16 seq_id; 81806fc92c33SMichael Chan __le16 resp_len; 81816fc92c33SMichael Chan u8 flags; 81826fc92c33SMichael Chan #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 81836fc92c33SMichael Chan u8 unused_0; 81846fc92c33SMichael Chan __le16 data_len; 81856fc92c33SMichael Chan u8 unused_1[3]; 81866fc92c33SMichael Chan u8 valid; 81876fc92c33SMichael Chan }; 81886fc92c33SMichael Chan 818931d357c0SMichael Chan /* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 819031d357c0SMichael Chan struct hwrm_dbg_ring_info_get_input { 819131d357c0SMichael Chan __le16 req_type; 819231d357c0SMichael Chan __le16 cmpl_ring; 819331d357c0SMichael Chan __le16 seq_id; 819431d357c0SMichael Chan __le16 target_id; 819531d357c0SMichael Chan __le64 resp_addr; 819631d357c0SMichael Chan u8 ring_type; 819731d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 819831d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 819931d357c0SMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 8200bfc6e5fbSMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 8201bfc6e5fbSMichael Chan #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 820231d357c0SMichael Chan u8 unused_0[3]; 820331d357c0SMichael Chan __le32 fw_ring_id; 820431d357c0SMichael Chan }; 820531d357c0SMichael Chan 820631d357c0SMichael Chan /* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 820731d357c0SMichael Chan struct hwrm_dbg_ring_info_get_output { 820831d357c0SMichael Chan __le16 error_code; 820931d357c0SMichael Chan __le16 req_type; 821031d357c0SMichael Chan __le16 seq_id; 821131d357c0SMichael Chan __le16 resp_len; 821231d357c0SMichael Chan __le32 producer_index; 821331d357c0SMichael Chan __le32 consumer_index; 8214bfc6e5fbSMichael Chan __le32 cag_vector_ctrl; 8215bfc6e5fbSMichael Chan u8 unused_0[3]; 821631d357c0SMichael Chan u8 valid; 821731d357c0SMichael Chan }; 821831d357c0SMichael Chan 8219894aa69aSMichael Chan /* hwrm_nvm_read_input (size:320b/40B) */ 8220894aa69aSMichael Chan struct hwrm_nvm_read_input { 8221894aa69aSMichael Chan __le16 req_type; 8222894aa69aSMichael Chan __le16 cmpl_ring; 8223894aa69aSMichael Chan __le16 seq_id; 8224894aa69aSMichael Chan __le16 target_id; 8225894aa69aSMichael Chan __le64 resp_addr; 8226894aa69aSMichael Chan __le64 host_dest_addr; 8227894aa69aSMichael Chan __le16 dir_idx; 8228894aa69aSMichael Chan u8 unused_0[2]; 8229894aa69aSMichael Chan __le32 offset; 8230894aa69aSMichael Chan __le32 len; 8231894aa69aSMichael Chan u8 unused_1[4]; 8232894aa69aSMichael Chan }; 8233894aa69aSMichael Chan 8234894aa69aSMichael Chan /* hwrm_nvm_read_output (size:128b/16B) */ 8235894aa69aSMichael Chan struct hwrm_nvm_read_output { 8236894aa69aSMichael Chan __le16 error_code; 8237894aa69aSMichael Chan __le16 req_type; 8238894aa69aSMichael Chan __le16 seq_id; 8239894aa69aSMichael Chan __le16 resp_len; 8240894aa69aSMichael Chan u8 unused_0[7]; 8241894aa69aSMichael Chan u8 valid; 8242894aa69aSMichael Chan }; 8243894aa69aSMichael Chan 8244894aa69aSMichael Chan /* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 8245894aa69aSMichael Chan struct hwrm_nvm_get_dir_entries_input { 8246894aa69aSMichael Chan __le16 req_type; 8247894aa69aSMichael Chan __le16 cmpl_ring; 8248894aa69aSMichael Chan __le16 seq_id; 8249894aa69aSMichael Chan __le16 target_id; 8250894aa69aSMichael Chan __le64 resp_addr; 8251894aa69aSMichael Chan __le64 host_dest_addr; 8252894aa69aSMichael Chan }; 8253894aa69aSMichael Chan 8254894aa69aSMichael Chan /* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 8255894aa69aSMichael Chan struct hwrm_nvm_get_dir_entries_output { 8256894aa69aSMichael Chan __le16 error_code; 8257894aa69aSMichael Chan __le16 req_type; 8258894aa69aSMichael Chan __le16 seq_id; 8259894aa69aSMichael Chan __le16 resp_len; 8260894aa69aSMichael Chan u8 unused_0[7]; 8261894aa69aSMichael Chan u8 valid; 8262894aa69aSMichael Chan }; 8263894aa69aSMichael Chan 8264894aa69aSMichael Chan /* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 8265894aa69aSMichael Chan struct hwrm_nvm_get_dir_info_input { 8266894aa69aSMichael Chan __le16 req_type; 8267894aa69aSMichael Chan __le16 cmpl_ring; 8268894aa69aSMichael Chan __le16 seq_id; 8269894aa69aSMichael Chan __le16 target_id; 8270894aa69aSMichael Chan __le64 resp_addr; 8271894aa69aSMichael Chan }; 8272894aa69aSMichael Chan 8273894aa69aSMichael Chan /* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 8274894aa69aSMichael Chan struct hwrm_nvm_get_dir_info_output { 8275894aa69aSMichael Chan __le16 error_code; 8276894aa69aSMichael Chan __le16 req_type; 8277894aa69aSMichael Chan __le16 seq_id; 8278894aa69aSMichael Chan __le16 resp_len; 8279894aa69aSMichael Chan __le32 entries; 8280894aa69aSMichael Chan __le32 entry_length; 8281894aa69aSMichael Chan u8 unused_0[7]; 8282894aa69aSMichael Chan u8 valid; 8283894aa69aSMichael Chan }; 8284894aa69aSMichael Chan 8285894aa69aSMichael Chan /* hwrm_nvm_write_input (size:384b/48B) */ 8286894aa69aSMichael Chan struct hwrm_nvm_write_input { 8287894aa69aSMichael Chan __le16 req_type; 8288894aa69aSMichael Chan __le16 cmpl_ring; 8289894aa69aSMichael Chan __le16 seq_id; 8290894aa69aSMichael Chan __le16 target_id; 8291894aa69aSMichael Chan __le64 resp_addr; 8292894aa69aSMichael Chan __le64 host_src_addr; 8293894aa69aSMichael Chan __le16 dir_type; 8294894aa69aSMichael Chan __le16 dir_ordinal; 8295894aa69aSMichael Chan __le16 dir_ext; 8296894aa69aSMichael Chan __le16 dir_attr; 8297894aa69aSMichael Chan __le32 dir_data_length; 8298894aa69aSMichael Chan __le16 option; 8299894aa69aSMichael Chan __le16 flags; 8300894aa69aSMichael Chan #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 8301894aa69aSMichael Chan __le32 dir_item_length; 8302894aa69aSMichael Chan __le32 unused_0; 8303894aa69aSMichael Chan }; 8304894aa69aSMichael Chan 8305894aa69aSMichael Chan /* hwrm_nvm_write_output (size:128b/16B) */ 8306894aa69aSMichael Chan struct hwrm_nvm_write_output { 8307894aa69aSMichael Chan __le16 error_code; 8308894aa69aSMichael Chan __le16 req_type; 8309894aa69aSMichael Chan __le16 seq_id; 8310894aa69aSMichael Chan __le16 resp_len; 8311894aa69aSMichael Chan __le32 dir_item_length; 8312894aa69aSMichael Chan __le16 dir_idx; 8313894aa69aSMichael Chan u8 unused_0; 8314894aa69aSMichael Chan u8 valid; 8315894aa69aSMichael Chan }; 8316894aa69aSMichael Chan 8317894aa69aSMichael Chan /* hwrm_nvm_write_cmd_err (size:64b/8B) */ 8318894aa69aSMichael Chan struct hwrm_nvm_write_cmd_err { 8319894aa69aSMichael Chan u8 code; 8320894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 8321894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8322894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 8323894aa69aSMichael Chan #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 8324894aa69aSMichael Chan u8 unused_0[7]; 8325894aa69aSMichael Chan }; 8326894aa69aSMichael Chan 8327894aa69aSMichael Chan /* hwrm_nvm_modify_input (size:320b/40B) */ 8328894aa69aSMichael Chan struct hwrm_nvm_modify_input { 8329894aa69aSMichael Chan __le16 req_type; 8330894aa69aSMichael Chan __le16 cmpl_ring; 8331894aa69aSMichael Chan __le16 seq_id; 8332894aa69aSMichael Chan __le16 target_id; 8333894aa69aSMichael Chan __le64 resp_addr; 8334894aa69aSMichael Chan __le64 host_src_addr; 8335894aa69aSMichael Chan __le16 dir_idx; 8336460c2577SMichael Chan __le16 flags; 8337460c2577SMichael Chan #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 8338460c2577SMichael Chan #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 8339894aa69aSMichael Chan __le32 offset; 8340894aa69aSMichael Chan __le32 len; 8341894aa69aSMichael Chan u8 unused_1[4]; 8342894aa69aSMichael Chan }; 8343894aa69aSMichael Chan 8344894aa69aSMichael Chan /* hwrm_nvm_modify_output (size:128b/16B) */ 8345894aa69aSMichael Chan struct hwrm_nvm_modify_output { 8346894aa69aSMichael Chan __le16 error_code; 8347894aa69aSMichael Chan __le16 req_type; 8348894aa69aSMichael Chan __le16 seq_id; 8349894aa69aSMichael Chan __le16 resp_len; 8350894aa69aSMichael Chan u8 unused_0[7]; 8351894aa69aSMichael Chan u8 valid; 8352894aa69aSMichael Chan }; 8353894aa69aSMichael Chan 8354894aa69aSMichael Chan /* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 8355894aa69aSMichael Chan struct hwrm_nvm_find_dir_entry_input { 8356894aa69aSMichael Chan __le16 req_type; 8357894aa69aSMichael Chan __le16 cmpl_ring; 8358894aa69aSMichael Chan __le16 seq_id; 8359894aa69aSMichael Chan __le16 target_id; 8360894aa69aSMichael Chan __le64 resp_addr; 8361894aa69aSMichael Chan __le32 enables; 8362894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 8363894aa69aSMichael Chan __le16 dir_idx; 8364894aa69aSMichael Chan __le16 dir_type; 8365894aa69aSMichael Chan __le16 dir_ordinal; 8366894aa69aSMichael Chan __le16 dir_ext; 8367894aa69aSMichael Chan u8 opt_ordinal; 8368894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 8369894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 8370894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 8371894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 8372894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 8373894aa69aSMichael Chan #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 8374894aa69aSMichael Chan u8 unused_0[3]; 8375894aa69aSMichael Chan }; 8376894aa69aSMichael Chan 8377894aa69aSMichael Chan /* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 8378894aa69aSMichael Chan struct hwrm_nvm_find_dir_entry_output { 8379894aa69aSMichael Chan __le16 error_code; 8380894aa69aSMichael Chan __le16 req_type; 8381894aa69aSMichael Chan __le16 seq_id; 8382894aa69aSMichael Chan __le16 resp_len; 8383894aa69aSMichael Chan __le32 dir_item_length; 8384894aa69aSMichael Chan __le32 dir_data_length; 8385894aa69aSMichael Chan __le32 fw_ver; 8386894aa69aSMichael Chan __le16 dir_ordinal; 8387894aa69aSMichael Chan __le16 dir_idx; 8388894aa69aSMichael Chan u8 unused_0[7]; 8389894aa69aSMichael Chan u8 valid; 8390894aa69aSMichael Chan }; 8391894aa69aSMichael Chan 8392894aa69aSMichael Chan /* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 8393894aa69aSMichael Chan struct hwrm_nvm_erase_dir_entry_input { 8394894aa69aSMichael Chan __le16 req_type; 8395894aa69aSMichael Chan __le16 cmpl_ring; 8396894aa69aSMichael Chan __le16 seq_id; 8397894aa69aSMichael Chan __le16 target_id; 8398894aa69aSMichael Chan __le64 resp_addr; 8399894aa69aSMichael Chan __le16 dir_idx; 8400894aa69aSMichael Chan u8 unused_0[6]; 8401894aa69aSMichael Chan }; 8402894aa69aSMichael Chan 8403894aa69aSMichael Chan /* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 8404894aa69aSMichael Chan struct hwrm_nvm_erase_dir_entry_output { 8405894aa69aSMichael Chan __le16 error_code; 8406894aa69aSMichael Chan __le16 req_type; 8407894aa69aSMichael Chan __le16 seq_id; 8408894aa69aSMichael Chan __le16 resp_len; 8409894aa69aSMichael Chan u8 unused_0[7]; 8410894aa69aSMichael Chan u8 valid; 8411894aa69aSMichael Chan }; 8412894aa69aSMichael Chan 8413894aa69aSMichael Chan /* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 8414894aa69aSMichael Chan struct hwrm_nvm_get_dev_info_input { 8415894aa69aSMichael Chan __le16 req_type; 8416894aa69aSMichael Chan __le16 cmpl_ring; 8417894aa69aSMichael Chan __le16 seq_id; 8418894aa69aSMichael Chan __le16 target_id; 8419894aa69aSMichael Chan __le64 resp_addr; 8420894aa69aSMichael Chan }; 8421894aa69aSMichael Chan 8422424174f1SVasundhara Volam /* hwrm_nvm_get_dev_info_output (size:640b/80B) */ 8423894aa69aSMichael Chan struct hwrm_nvm_get_dev_info_output { 8424894aa69aSMichael Chan __le16 error_code; 8425894aa69aSMichael Chan __le16 req_type; 8426894aa69aSMichael Chan __le16 seq_id; 8427894aa69aSMichael Chan __le16 resp_len; 8428894aa69aSMichael Chan __le16 manufacturer_id; 8429894aa69aSMichael Chan __le16 device_id; 8430894aa69aSMichael Chan __le32 sector_size; 8431894aa69aSMichael Chan __le32 nvram_size; 8432894aa69aSMichael Chan __le32 reserved_size; 8433894aa69aSMichael Chan __le32 available_size; 84344a50ddc2SMichael Chan u8 nvm_cfg_ver_maj; 84354a50ddc2SMichael Chan u8 nvm_cfg_ver_min; 84364a50ddc2SMichael Chan u8 nvm_cfg_ver_upd; 8437424174f1SVasundhara Volam u8 flags; 8438424174f1SVasundhara Volam #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 8439424174f1SVasundhara Volam char pkg_name[16]; 8440424174f1SVasundhara Volam __le16 hwrm_fw_major; 8441424174f1SVasundhara Volam __le16 hwrm_fw_minor; 8442424174f1SVasundhara Volam __le16 hwrm_fw_build; 8443424174f1SVasundhara Volam __le16 hwrm_fw_patch; 8444424174f1SVasundhara Volam __le16 mgmt_fw_major; 8445424174f1SVasundhara Volam __le16 mgmt_fw_minor; 8446424174f1SVasundhara Volam __le16 mgmt_fw_build; 8447424174f1SVasundhara Volam __le16 mgmt_fw_patch; 8448424174f1SVasundhara Volam __le16 roce_fw_major; 8449424174f1SVasundhara Volam __le16 roce_fw_minor; 8450424174f1SVasundhara Volam __le16 roce_fw_build; 8451424174f1SVasundhara Volam __le16 roce_fw_patch; 8452424174f1SVasundhara Volam u8 unused_0[7]; 8453894aa69aSMichael Chan u8 valid; 8454894aa69aSMichael Chan }; 8455894aa69aSMichael Chan 8456894aa69aSMichael Chan /* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 8457894aa69aSMichael Chan struct hwrm_nvm_mod_dir_entry_input { 8458894aa69aSMichael Chan __le16 req_type; 8459894aa69aSMichael Chan __le16 cmpl_ring; 8460894aa69aSMichael Chan __le16 seq_id; 8461894aa69aSMichael Chan __le16 target_id; 8462894aa69aSMichael Chan __le64 resp_addr; 8463894aa69aSMichael Chan __le32 enables; 8464894aa69aSMichael Chan #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 8465894aa69aSMichael Chan __le16 dir_idx; 8466894aa69aSMichael Chan __le16 dir_ordinal; 8467894aa69aSMichael Chan __le16 dir_ext; 8468894aa69aSMichael Chan __le16 dir_attr; 8469894aa69aSMichael Chan __le32 checksum; 8470894aa69aSMichael Chan }; 8471894aa69aSMichael Chan 8472894aa69aSMichael Chan /* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 8473894aa69aSMichael Chan struct hwrm_nvm_mod_dir_entry_output { 8474894aa69aSMichael Chan __le16 error_code; 8475894aa69aSMichael Chan __le16 req_type; 8476894aa69aSMichael Chan __le16 seq_id; 8477894aa69aSMichael Chan __le16 resp_len; 8478894aa69aSMichael Chan u8 unused_0[7]; 8479894aa69aSMichael Chan u8 valid; 8480894aa69aSMichael Chan }; 8481894aa69aSMichael Chan 8482894aa69aSMichael Chan /* hwrm_nvm_verify_update_input (size:192b/24B) */ 8483894aa69aSMichael Chan struct hwrm_nvm_verify_update_input { 8484894aa69aSMichael Chan __le16 req_type; 8485894aa69aSMichael Chan __le16 cmpl_ring; 8486894aa69aSMichael Chan __le16 seq_id; 8487894aa69aSMichael Chan __le16 target_id; 8488894aa69aSMichael Chan __le64 resp_addr; 8489894aa69aSMichael Chan __le16 dir_type; 8490894aa69aSMichael Chan __le16 dir_ordinal; 8491894aa69aSMichael Chan __le16 dir_ext; 8492894aa69aSMichael Chan u8 unused_0[2]; 8493894aa69aSMichael Chan }; 8494894aa69aSMichael Chan 8495894aa69aSMichael Chan /* hwrm_nvm_verify_update_output (size:128b/16B) */ 8496894aa69aSMichael Chan struct hwrm_nvm_verify_update_output { 8497894aa69aSMichael Chan __le16 error_code; 8498894aa69aSMichael Chan __le16 req_type; 8499894aa69aSMichael Chan __le16 seq_id; 8500894aa69aSMichael Chan __le16 resp_len; 8501894aa69aSMichael Chan u8 unused_0[7]; 8502894aa69aSMichael Chan u8 valid; 8503894aa69aSMichael Chan }; 8504894aa69aSMichael Chan 8505894aa69aSMichael Chan /* hwrm_nvm_install_update_input (size:192b/24B) */ 8506894aa69aSMichael Chan struct hwrm_nvm_install_update_input { 8507894aa69aSMichael Chan __le16 req_type; 8508894aa69aSMichael Chan __le16 cmpl_ring; 8509894aa69aSMichael Chan __le16 seq_id; 8510894aa69aSMichael Chan __le16 target_id; 8511894aa69aSMichael Chan __le64 resp_addr; 8512894aa69aSMichael Chan __le32 install_type; 8513894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 8514894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 8515894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 8516894aa69aSMichael Chan __le16 flags; 8517894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 8518894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 8519894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 8520bfc6e5fbSMichael Chan #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 8521894aa69aSMichael Chan u8 unused_0[2]; 8522894aa69aSMichael Chan }; 8523894aa69aSMichael Chan 8524894aa69aSMichael Chan /* hwrm_nvm_install_update_output (size:192b/24B) */ 8525894aa69aSMichael Chan struct hwrm_nvm_install_update_output { 8526894aa69aSMichael Chan __le16 error_code; 8527894aa69aSMichael Chan __le16 req_type; 8528894aa69aSMichael Chan __le16 seq_id; 8529894aa69aSMichael Chan __le16 resp_len; 8530894aa69aSMichael Chan __le64 installed_items; 8531894aa69aSMichael Chan u8 result; 8532894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 8533894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 8534894aa69aSMichael Chan u8 problem_item; 8535894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 8536894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 8537894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 8538894aa69aSMichael Chan u8 reset_required; 8539894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 8540894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 8541894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 8542894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 8543894aa69aSMichael Chan u8 unused_0[4]; 8544894aa69aSMichael Chan u8 valid; 8545894aa69aSMichael Chan }; 8546894aa69aSMichael Chan 8547894aa69aSMichael Chan /* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 8548894aa69aSMichael Chan struct hwrm_nvm_install_update_cmd_err { 8549894aa69aSMichael Chan u8 code; 8550894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 8551894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 8552894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 8553894aa69aSMichael Chan #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 8554894aa69aSMichael Chan u8 unused_0[7]; 8555894aa69aSMichael Chan }; 8556894aa69aSMichael Chan 8557894aa69aSMichael Chan /* hwrm_nvm_get_variable_input (size:320b/40B) */ 8558894aa69aSMichael Chan struct hwrm_nvm_get_variable_input { 8559894aa69aSMichael Chan __le16 req_type; 8560894aa69aSMichael Chan __le16 cmpl_ring; 8561894aa69aSMichael Chan __le16 seq_id; 8562894aa69aSMichael Chan __le16 target_id; 8563894aa69aSMichael Chan __le64 resp_addr; 8564894aa69aSMichael Chan __le64 dest_data_addr; 8565894aa69aSMichael Chan __le16 data_len; 8566894aa69aSMichael Chan __le16 option_num; 8567894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8568894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8569894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8570894aa69aSMichael Chan __le16 dimensions; 8571894aa69aSMichael Chan __le16 index_0; 8572894aa69aSMichael Chan __le16 index_1; 8573894aa69aSMichael Chan __le16 index_2; 8574894aa69aSMichael Chan __le16 index_3; 8575894aa69aSMichael Chan u8 flags; 8576894aa69aSMichael Chan #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 8577894aa69aSMichael Chan u8 unused_0; 8578894aa69aSMichael Chan }; 8579894aa69aSMichael Chan 8580894aa69aSMichael Chan /* hwrm_nvm_get_variable_output (size:128b/16B) */ 8581894aa69aSMichael Chan struct hwrm_nvm_get_variable_output { 8582894aa69aSMichael Chan __le16 error_code; 8583894aa69aSMichael Chan __le16 req_type; 8584894aa69aSMichael Chan __le16 seq_id; 8585894aa69aSMichael Chan __le16 resp_len; 8586894aa69aSMichael Chan __le16 data_len; 8587894aa69aSMichael Chan __le16 option_num; 8588894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 8589894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 8590894aa69aSMichael Chan #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 8591894aa69aSMichael Chan u8 unused_0[3]; 8592894aa69aSMichael Chan u8 valid; 8593894aa69aSMichael Chan }; 8594894aa69aSMichael Chan 8595894aa69aSMichael Chan /* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 8596894aa69aSMichael Chan struct hwrm_nvm_get_variable_cmd_err { 8597894aa69aSMichael Chan u8 code; 8598894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8599894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8600894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8601894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 8602894aa69aSMichael Chan #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 8603894aa69aSMichael Chan u8 unused_0[7]; 8604894aa69aSMichael Chan }; 8605894aa69aSMichael Chan 8606894aa69aSMichael Chan /* hwrm_nvm_set_variable_input (size:320b/40B) */ 8607894aa69aSMichael Chan struct hwrm_nvm_set_variable_input { 8608894aa69aSMichael Chan __le16 req_type; 8609894aa69aSMichael Chan __le16 cmpl_ring; 8610894aa69aSMichael Chan __le16 seq_id; 8611894aa69aSMichael Chan __le16 target_id; 8612894aa69aSMichael Chan __le64 resp_addr; 8613894aa69aSMichael Chan __le64 src_data_addr; 8614894aa69aSMichael Chan __le16 data_len; 8615894aa69aSMichael Chan __le16 option_num; 8616894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 8617894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 8618894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 8619894aa69aSMichael Chan __le16 dimensions; 8620894aa69aSMichael Chan __le16 index_0; 8621894aa69aSMichael Chan __le16 index_1; 8622894aa69aSMichael Chan __le16 index_2; 8623894aa69aSMichael Chan __le16 index_3; 8624894aa69aSMichael Chan u8 flags; 8625894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 8626894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 8627894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 8628894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 8629894aa69aSMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 86306fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 86316fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 86326fc92c33SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 86332792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 86342792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 86352792b5b9SMichael Chan #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 8636894aa69aSMichael Chan u8 unused_0; 8637894aa69aSMichael Chan }; 8638894aa69aSMichael Chan 8639894aa69aSMichael Chan /* hwrm_nvm_set_variable_output (size:128b/16B) */ 8640894aa69aSMichael Chan struct hwrm_nvm_set_variable_output { 8641894aa69aSMichael Chan __le16 error_code; 8642894aa69aSMichael Chan __le16 req_type; 8643894aa69aSMichael Chan __le16 seq_id; 8644894aa69aSMichael Chan __le16 resp_len; 8645894aa69aSMichael Chan u8 unused_0[7]; 8646894aa69aSMichael Chan u8 valid; 8647894aa69aSMichael Chan }; 8648894aa69aSMichael Chan 8649894aa69aSMichael Chan /* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 8650894aa69aSMichael Chan struct hwrm_nvm_set_variable_cmd_err { 8651894aa69aSMichael Chan u8 code; 8652894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 8653894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 8654894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 8655894aa69aSMichael Chan #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 8656894aa69aSMichael Chan u8 unused_0[7]; 8657894aa69aSMichael Chan }; 8658894aa69aSMichael Chan 8659894aa69aSMichael Chan /* hwrm_selftest_qlist_input (size:128b/16B) */ 8660894aa69aSMichael Chan struct hwrm_selftest_qlist_input { 8661894aa69aSMichael Chan __le16 req_type; 8662894aa69aSMichael Chan __le16 cmpl_ring; 8663894aa69aSMichael Chan __le16 seq_id; 8664894aa69aSMichael Chan __le16 target_id; 8665894aa69aSMichael Chan __le64 resp_addr; 8666894aa69aSMichael Chan }; 8667894aa69aSMichael Chan 8668894aa69aSMichael Chan /* hwrm_selftest_qlist_output (size:2240b/280B) */ 8669894aa69aSMichael Chan struct hwrm_selftest_qlist_output { 8670894aa69aSMichael Chan __le16 error_code; 8671894aa69aSMichael Chan __le16 req_type; 8672894aa69aSMichael Chan __le16 seq_id; 8673894aa69aSMichael Chan __le16 resp_len; 8674894aa69aSMichael Chan u8 num_tests; 8675894aa69aSMichael Chan u8 available_tests; 8676894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 8677894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 8678894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 8679894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 8680894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 8681894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8682894aa69aSMichael Chan u8 offline_tests; 8683894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 8684894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 8685894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 8686894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 8687894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 8688894aa69aSMichael Chan #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 8689894aa69aSMichael Chan u8 unused_0; 8690894aa69aSMichael Chan __le16 test_timeout; 8691894aa69aSMichael Chan u8 unused_1[2]; 8692894aa69aSMichael Chan char test0_name[32]; 8693894aa69aSMichael Chan char test1_name[32]; 8694894aa69aSMichael Chan char test2_name[32]; 8695894aa69aSMichael Chan char test3_name[32]; 8696894aa69aSMichael Chan char test4_name[32]; 8697894aa69aSMichael Chan char test5_name[32]; 8698894aa69aSMichael Chan char test6_name[32]; 8699894aa69aSMichael Chan char test7_name[32]; 8700bfc6e5fbSMichael Chan u8 eyescope_target_BER_support; 8701bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 8702bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 8703bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 8704bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 8705bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 8706bfc6e5fbSMichael Chan #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 8707bfc6e5fbSMichael Chan u8 unused_2[6]; 8708894aa69aSMichael Chan u8 valid; 8709894aa69aSMichael Chan }; 8710894aa69aSMichael Chan 8711894aa69aSMichael Chan /* hwrm_selftest_exec_input (size:192b/24B) */ 8712894aa69aSMichael Chan struct hwrm_selftest_exec_input { 8713894aa69aSMichael Chan __le16 req_type; 8714894aa69aSMichael Chan __le16 cmpl_ring; 8715894aa69aSMichael Chan __le16 seq_id; 8716894aa69aSMichael Chan __le16 target_id; 8717894aa69aSMichael Chan __le64 resp_addr; 8718894aa69aSMichael Chan u8 flags; 8719894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 8720894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 8721894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 8722894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 8723894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 8724894aa69aSMichael Chan #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 8725d4f52de0SMichael Chan u8 unused_0[7]; 8726894aa69aSMichael Chan }; 8727894aa69aSMichael Chan 8728894aa69aSMichael Chan /* hwrm_selftest_exec_output (size:128b/16B) */ 8729894aa69aSMichael Chan struct hwrm_selftest_exec_output { 8730894aa69aSMichael Chan __le16 error_code; 8731894aa69aSMichael Chan __le16 req_type; 8732894aa69aSMichael Chan __le16 seq_id; 8733894aa69aSMichael Chan __le16 resp_len; 8734894aa69aSMichael Chan u8 requested_tests; 8735894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 8736894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 8737894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 8738894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 8739894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 8740894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 8741894aa69aSMichael Chan u8 test_success; 8742894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 8743894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 8744894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 8745894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 8746894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 8747894aa69aSMichael Chan #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 8748894aa69aSMichael Chan u8 unused_0[5]; 8749894aa69aSMichael Chan u8 valid; 8750894aa69aSMichael Chan }; 8751894aa69aSMichael Chan 8752894aa69aSMichael Chan /* hwrm_selftest_irq_input (size:128b/16B) */ 8753894aa69aSMichael Chan struct hwrm_selftest_irq_input { 8754894aa69aSMichael Chan __le16 req_type; 8755894aa69aSMichael Chan __le16 cmpl_ring; 8756894aa69aSMichael Chan __le16 seq_id; 8757894aa69aSMichael Chan __le16 target_id; 8758894aa69aSMichael Chan __le64 resp_addr; 8759894aa69aSMichael Chan }; 8760894aa69aSMichael Chan 8761894aa69aSMichael Chan /* hwrm_selftest_irq_output (size:128b/16B) */ 8762894aa69aSMichael Chan struct hwrm_selftest_irq_output { 8763894aa69aSMichael Chan __le16 error_code; 8764894aa69aSMichael Chan __le16 req_type; 8765894aa69aSMichael Chan __le16 seq_id; 8766894aa69aSMichael Chan __le16 resp_len; 8767894aa69aSMichael Chan u8 unused_0[7]; 8768894aa69aSMichael Chan u8 valid; 8769894aa69aSMichael Chan }; 8770894aa69aSMichael Chan 87719d6b648cSMichael Chan /* db_push_info (size:64b/8B) */ 87729d6b648cSMichael Chan struct db_push_info { 87739d6b648cSMichael Chan u32 push_size_push_index; 87749d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 87759d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 87769d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 87779d6b648cSMichael Chan #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 87789d6b648cSMichael Chan u32 reserved32; 87799d6b648cSMichael Chan }; 87809d6b648cSMichael Chan 8781460c2577SMichael Chan /* fw_status_reg (size:32b/4B) */ 8782460c2577SMichael Chan struct fw_status_reg { 8783460c2577SMichael Chan u32 fw_status; 8784460c2577SMichael Chan #define FW_STATUS_REG_CODE_MASK 0xffffUL 8785460c2577SMichael Chan #define FW_STATUS_REG_CODE_SFT 0 8786460c2577SMichael Chan #define FW_STATUS_REG_CODE_READY 0x8000UL 8787460c2577SMichael Chan #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 8788460c2577SMichael Chan #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 8789460c2577SMichael Chan #define FW_STATUS_REG_RECOVERABLE 0x20000UL 8790460c2577SMichael Chan #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 8791460c2577SMichael Chan #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 8792460c2577SMichael Chan #define FW_STATUS_REG_SHUTDOWN 0x100000UL 8793424174f1SVasundhara Volam #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 8794460c2577SMichael Chan }; 8795460c2577SMichael Chan 87969d6b648cSMichael Chan /* hcomm_status (size:64b/8B) */ 87979d6b648cSMichael Chan struct hcomm_status { 87989d6b648cSMichael Chan u32 sig_ver; 87999d6b648cSMichael Chan #define HCOMM_STATUS_VER_MASK 0xffUL 88009d6b648cSMichael Chan #define HCOMM_STATUS_VER_SFT 0 88019d6b648cSMichael Chan #define HCOMM_STATUS_VER_LATEST 0x1UL 88029d6b648cSMichael Chan #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 88039d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 88049d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_SFT 8 88059d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 88069d6b648cSMichael Chan #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 88079d6b648cSMichael Chan u32 fw_status_loc; 88089d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 88099d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 88109d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 88119d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 88129d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 88139d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 88149d6b648cSMichael Chan #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 88159d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 88169d6b648cSMichael Chan #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 88179d6b648cSMichael Chan }; 88189d6b648cSMichael Chan #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 88199d6b648cSMichael Chan 8820894aa69aSMichael Chan #endif /* _BNXT_HSI_H_ */ 8821