1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  */
10 
11 #ifndef BNXT_H
12 #define BNXT_H
13 
14 #define DRV_MODULE_NAME		"bnxt_en"
15 #define DRV_MODULE_VERSION	"1.10.1"
16 
17 #define DRV_VER_MAJ	1
18 #define DRV_VER_MIN	10
19 #define DRV_VER_UPD	1
20 
21 #include <linux/interrupt.h>
22 #include <linux/rhashtable.h>
23 #include <linux/crash_dump.h>
24 #include <net/devlink.h>
25 #include <net/dst_metadata.h>
26 #include <net/xdp.h>
27 #include <linux/dim.h>
28 #ifdef CONFIG_TEE_BNXT_FW
29 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
30 #endif
31 
32 extern struct list_head bnxt_block_cb_list;
33 
34 struct page_pool;
35 
36 struct tx_bd {
37 	__le32 tx_bd_len_flags_type;
38 	#define TX_BD_TYPE					(0x3f << 0)
39 	 #define TX_BD_TYPE_SHORT_TX_BD				 (0x00 << 0)
40 	 #define TX_BD_TYPE_LONG_TX_BD				 (0x10 << 0)
41 	#define TX_BD_FLAGS_PACKET_END				(1 << 6)
42 	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)
43 	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)
44 	 #define TX_BD_FLAGS_BD_CNT_SHIFT			 8
45 	#define TX_BD_FLAGS_LHINT				(3 << 13)
46 	 #define TX_BD_FLAGS_LHINT_SHIFT			 13
47 	 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER		 (0 << 13)
48 	 #define TX_BD_FLAGS_LHINT_512_TO_1023			 (1 << 13)
49 	 #define TX_BD_FLAGS_LHINT_1024_TO_2047			 (2 << 13)
50 	 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER		 (3 << 13)
51 	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)
52 	#define TX_BD_LEN					(0xffff << 16)
53 	 #define TX_BD_LEN_SHIFT				 16
54 
55 	u32 tx_bd_opaque;
56 	__le64 tx_bd_haddr;
57 } __packed;
58 
59 struct tx_bd_ext {
60 	__le32 tx_bd_hsize_lflags;
61 	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 << 0)
62 	#define TX_BD_FLAGS_IP_CKSUM				(1 << 1)
63 	#define TX_BD_FLAGS_NO_CRC				(1 << 2)
64 	#define TX_BD_FLAGS_STAMP				(1 << 3)
65 	#define TX_BD_FLAGS_T_IP_CHKSUM				(1 << 4)
66 	#define TX_BD_FLAGS_LSO					(1 << 5)
67 	#define TX_BD_FLAGS_IPID_FMT				(1 << 6)
68 	#define TX_BD_FLAGS_T_IPID				(1 << 7)
69 	#define TX_BD_HSIZE					(0xff << 16)
70 	 #define TX_BD_HSIZE_SHIFT				 16
71 
72 	__le32 tx_bd_mss;
73 	__le32 tx_bd_cfa_action;
74 	#define TX_BD_CFA_ACTION				(0xffff << 16)
75 	 #define TX_BD_CFA_ACTION_SHIFT				 16
76 
77 	__le32 tx_bd_cfa_meta;
78 	#define TX_BD_CFA_META_MASK                             0xfffffff
79 	#define TX_BD_CFA_META_VID_MASK                         0xfff
80 	#define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
81 	 #define TX_BD_CFA_META_PRI_SHIFT                        12
82 	#define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
83 	 #define TX_BD_CFA_META_TPID_SHIFT                       16
84 	#define TX_BD_CFA_META_KEY                              (0xf << 28)
85 	 #define TX_BD_CFA_META_KEY_SHIFT			 28
86 	#define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
87 };
88 
89 struct rx_bd {
90 	__le32 rx_bd_len_flags_type;
91 	#define RX_BD_TYPE					(0x3f << 0)
92 	 #define RX_BD_TYPE_RX_PACKET_BD			 0x4
93 	 #define RX_BD_TYPE_RX_BUFFER_BD			 0x5
94 	 #define RX_BD_TYPE_RX_AGG_BD				 0x6
95 	 #define RX_BD_TYPE_16B_BD_SIZE				 (0 << 4)
96 	 #define RX_BD_TYPE_32B_BD_SIZE				 (1 << 4)
97 	 #define RX_BD_TYPE_48B_BD_SIZE				 (2 << 4)
98 	 #define RX_BD_TYPE_64B_BD_SIZE				 (3 << 4)
99 	#define RX_BD_FLAGS_SOP					(1 << 6)
100 	#define RX_BD_FLAGS_EOP					(1 << 7)
101 	#define RX_BD_FLAGS_BUFFERS				(3 << 8)
102 	 #define RX_BD_FLAGS_1_BUFFER_PACKET			 (0 << 8)
103 	 #define RX_BD_FLAGS_2_BUFFER_PACKET			 (1 << 8)
104 	 #define RX_BD_FLAGS_3_BUFFER_PACKET			 (2 << 8)
105 	 #define RX_BD_FLAGS_4_BUFFER_PACKET			 (3 << 8)
106 	#define RX_BD_LEN					(0xffff << 16)
107 	 #define RX_BD_LEN_SHIFT				 16
108 
109 	u32 rx_bd_opaque;
110 	__le64 rx_bd_haddr;
111 };
112 
113 struct tx_cmp {
114 	__le32 tx_cmp_flags_type;
115 	#define CMP_TYPE					(0x3f << 0)
116 	 #define CMP_TYPE_TX_L2_CMP				 0
117 	 #define CMP_TYPE_RX_L2_CMP				 17
118 	 #define CMP_TYPE_RX_AGG_CMP				 18
119 	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19
120 	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21
121 	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22
122 	 #define CMP_TYPE_STATUS_CMP				 32
123 	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34
124 	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36
125 	 #define CMP_TYPE_ERROR_STATUS				 48
126 	 #define CMPL_BASE_TYPE_STAT_EJECT			 0x1aUL
127 	 #define CMPL_BASE_TYPE_HWRM_DONE			 0x20UL
128 	 #define CMPL_BASE_TYPE_HWRM_FWD_REQ			 0x22UL
129 	 #define CMPL_BASE_TYPE_HWRM_FWD_RESP			 0x24UL
130 	 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT		 0x2eUL
131 
132 	#define TX_CMP_FLAGS_ERROR				(1 << 6)
133 	#define TX_CMP_FLAGS_PUSH				(1 << 7)
134 
135 	u32 tx_cmp_opaque;
136 	__le32 tx_cmp_errors_v;
137 	#define TX_CMP_V					(1 << 0)
138 	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)
139 	 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		 0
140 	 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		 2
141 	 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG	 4
142 	 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		 5
143 	 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT			 (1 << 4)
144 	 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			 (1 << 5)
145 	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)
146 	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)
147 
148 	__le32 tx_cmp_unsed_3;
149 };
150 
151 struct rx_cmp {
152 	__le32 rx_cmp_len_flags_type;
153 	#define RX_CMP_CMP_TYPE					(0x3f << 0)
154 	#define RX_CMP_FLAGS_ERROR				(1 << 6)
155 	#define RX_CMP_FLAGS_PLACEMENT				(7 << 7)
156 	#define RX_CMP_FLAGS_RSS_VALID				(1 << 10)
157 	#define RX_CMP_FLAGS_UNUSED				(1 << 11)
158 	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12
159 	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 << 12)
160 	 #define RX_CMP_FLAGS_ITYPE_IP				 (1 << 12)
161 	 #define RX_CMP_FLAGS_ITYPE_TCP				 (2 << 12)
162 	 #define RX_CMP_FLAGS_ITYPE_UDP				 (3 << 12)
163 	 #define RX_CMP_FLAGS_ITYPE_FCOE			 (4 << 12)
164 	 #define RX_CMP_FLAGS_ITYPE_ROCE			 (5 << 12)
165 	 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS			 (8 << 12)
166 	 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS			 (9 << 12)
167 	#define RX_CMP_LEN					(0xffff << 16)
168 	 #define RX_CMP_LEN_SHIFT				 16
169 
170 	u32 rx_cmp_opaque;
171 	__le32 rx_cmp_misc_v1;
172 	#define RX_CMP_V1					(1 << 0)
173 	#define RX_CMP_AGG_BUFS					(0x1f << 1)
174 	 #define RX_CMP_AGG_BUFS_SHIFT				 1
175 	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)
176 	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9
177 	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)
178 	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16
179 
180 	__le32 rx_cmp_rss_hash;
181 };
182 
183 #define RX_CMP_HASH_VALID(rxcmp)				\
184 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
185 
186 #define RSS_PROFILE_ID_MASK	0x1f
187 
188 #define RX_CMP_HASH_TYPE(rxcmp)					\
189 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
190 	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
191 
192 struct rx_cmp_ext {
193 	__le32 rx_cmp_flags2;
194 	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1
195 	#define RX_CMP_FLAGS2_L4_CS_CALC			(0x1 << 1)
196 	#define RX_CMP_FLAGS2_T_IP_CS_CALC			(0x1 << 2)
197 	#define RX_CMP_FLAGS2_T_L4_CS_CALC			(0x1 << 3)
198 	#define RX_CMP_FLAGS2_META_FORMAT_VLAN			(0x1 << 4)
199 	__le32 rx_cmp_meta_data;
200 	#define RX_CMP_FLAGS2_METADATA_TCI_MASK			0xffff
201 	#define RX_CMP_FLAGS2_METADATA_VID_MASK			0xfff
202 	#define RX_CMP_FLAGS2_METADATA_TPID_MASK		0xffff0000
203 	 #define RX_CMP_FLAGS2_METADATA_TPID_SFT		 16
204 	__le32 rx_cmp_cfa_code_errors_v2;
205 	#define RX_CMP_V					(1 << 0)
206 	#define RX_CMPL_ERRORS_MASK				(0x7fff << 1)
207 	 #define RX_CMPL_ERRORS_SFT				 1
208 	#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK		(0x7 << 1)
209 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		 (0x0 << 1)
210 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT	 (0x1 << 1)
211 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
212 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		 (0x3 << 1)
213 	#define RX_CMPL_ERRORS_IP_CS_ERROR			(0x1 << 4)
214 	#define RX_CMPL_ERRORS_L4_CS_ERROR			(0x1 << 5)
215 	#define RX_CMPL_ERRORS_T_IP_CS_ERROR			(0x1 << 6)
216 	#define RX_CMPL_ERRORS_T_L4_CS_ERROR			(0x1 << 7)
217 	#define RX_CMPL_ERRORS_CRC_ERROR			(0x1 << 8)
218 	#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK			(0x7 << 9)
219 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		 (0x0 << 9)
220 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	 (0x1 << 9)
221 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	 (0x2 << 9)
222 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	 (0x3 << 9)
223 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	 (0x4 << 9)
224 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	 (0x5 << 9)
225 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL	 (0x6 << 9)
226 	#define RX_CMPL_ERRORS_PKT_ERROR_MASK			(0xf << 12)
227 	 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR		 (0x0 << 12)
228 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION	 (0x1 << 12)
229 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN	 (0x2 << 12)
230 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		 (0x3 << 12)
231 	 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR	 (0x4 << 12)
232 	 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	 (0x5 << 12)
233 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN	 (0x6 << 12)
234 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
235 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN	 (0x8 << 12)
236 
237 	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)
238 	 #define RX_CMPL_CFA_CODE_SFT				 16
239 
240 	__le32 rx_cmp_unused3;
241 };
242 
243 #define RX_CMP_L2_ERRORS						\
244 	cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
245 
246 #define RX_CMP_L4_CS_BITS						\
247 	(cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
248 
249 #define RX_CMP_L4_CS_ERR_BITS						\
250 	(cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
251 
252 #define RX_CMP_L4_CS_OK(rxcmp1)						\
253 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
254 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
255 
256 #define RX_CMP_ENCAP(rxcmp1)						\
257 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
258 	     RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
259 
260 #define RX_CMP_CFA_CODE(rxcmpl1)					\
261 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
262 	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
263 
264 struct rx_agg_cmp {
265 	__le32 rx_agg_cmp_len_flags_type;
266 	#define RX_AGG_CMP_TYPE					(0x3f << 0)
267 	#define RX_AGG_CMP_LEN					(0xffff << 16)
268 	 #define RX_AGG_CMP_LEN_SHIFT				 16
269 	u32 rx_agg_cmp_opaque;
270 	__le32 rx_agg_cmp_v;
271 	#define RX_AGG_CMP_V					(1 << 0)
272 	#define RX_AGG_CMP_AGG_ID				(0xffff << 16)
273 	 #define RX_AGG_CMP_AGG_ID_SHIFT			 16
274 	__le32 rx_agg_cmp_unused;
275 };
276 
277 #define TPA_AGG_AGG_ID(rx_agg)				\
278 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
279 	 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
280 
281 struct rx_tpa_start_cmp {
282 	__le32 rx_tpa_start_cmp_len_flags_type;
283 	#define RX_TPA_START_CMP_TYPE				(0x3f << 0)
284 	#define RX_TPA_START_CMP_FLAGS				(0x3ff << 6)
285 	 #define RX_TPA_START_CMP_FLAGS_SHIFT			 6
286 	#define RX_TPA_START_CMP_FLAGS_ERROR			(0x1 << 6)
287 	#define RX_TPA_START_CMP_FLAGS_PLACEMENT		(0x7 << 7)
288 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT		 7
289 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
290 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
291 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
292 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS	 (0x6 << 7)
293 	#define RX_TPA_START_CMP_FLAGS_RSS_VALID		(0x1 << 10)
294 	#define RX_TPA_START_CMP_FLAGS_TIMESTAMP		(0x1 << 11)
295 	#define RX_TPA_START_CMP_FLAGS_ITYPES			(0xf << 12)
296 	 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT		 12
297 	 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP		 (0x2 << 12)
298 	#define RX_TPA_START_CMP_LEN				(0xffff << 16)
299 	 #define RX_TPA_START_CMP_LEN_SHIFT			 16
300 
301 	u32 rx_tpa_start_cmp_opaque;
302 	__le32 rx_tpa_start_cmp_misc_v1;
303 	#define RX_TPA_START_CMP_V1				(0x1 << 0)
304 	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)
305 	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9
306 	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)
307 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25
308 	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)
309 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16
310 
311 	__le32 rx_tpa_start_cmp_rss_hash;
312 };
313 
314 #define TPA_START_HASH_VALID(rx_tpa_start)				\
315 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
316 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
317 
318 #define TPA_START_HASH_TYPE(rx_tpa_start)				\
319 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
320 	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\
321 	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
322 
323 #define TPA_START_AGG_ID(rx_tpa_start)					\
324 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
325 	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
326 
327 #define TPA_START_AGG_ID_P5(rx_tpa_start)				\
328 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
329 	 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
330 
331 #define TPA_START_ERROR(rx_tpa_start)					\
332 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
333 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
334 
335 struct rx_tpa_start_cmp_ext {
336 	__le32 rx_tpa_start_cmp_flags2;
337 	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)
338 	#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC		(0x1 << 1)
339 	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC		(0x1 << 2)
340 	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC		(0x1 << 3)
341 	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE			(0x1 << 8)
342 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)
343 	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)
344 	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10
345 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)
346 	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16
347 
348 	__le32 rx_tpa_start_cmp_metadata;
349 	__le32 rx_tpa_start_cmp_cfa_code_v2;
350 	#define RX_TPA_START_CMP_V2				(0x1 << 0)
351 	#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK	(0x7 << 1)
352 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT	 1
353 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
354 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
355 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
356 	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)
357 	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16
358 	__le32 rx_tpa_start_cmp_hdr_info;
359 };
360 
361 #define TPA_START_CFA_CODE(rx_tpa_start)				\
362 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
363 	 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
364 
365 #define TPA_START_IS_IPV6(rx_tpa_start)				\
366 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
367 	    cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
368 
369 #define TPA_START_ERROR_CODE(rx_tpa_start)				\
370 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
371 	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\
372 	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
373 
374 struct rx_tpa_end_cmp {
375 	__le32 rx_tpa_end_cmp_len_flags_type;
376 	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)
377 	#define RX_TPA_END_CMP_FLAGS				(0x3ff << 6)
378 	 #define RX_TPA_END_CMP_FLAGS_SHIFT			 6
379 	#define RX_TPA_END_CMP_FLAGS_PLACEMENT			(0x7 << 7)
380 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT		 7
381 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
382 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
383 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
384 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS		 (0x6 << 7)
385 	#define RX_TPA_END_CMP_FLAGS_RSS_VALID			(0x1 << 10)
386 	#define RX_TPA_END_CMP_FLAGS_ITYPES			(0xf << 12)
387 	 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT		 12
388 	 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP			 (0x2 << 12)
389 	#define RX_TPA_END_CMP_LEN				(0xffff << 16)
390 	 #define RX_TPA_END_CMP_LEN_SHIFT			 16
391 
392 	u32 rx_tpa_end_cmp_opaque;
393 	__le32 rx_tpa_end_cmp_misc_v1;
394 	#define RX_TPA_END_CMP_V1				(0x1 << 0)
395 	#define RX_TPA_END_CMP_AGG_BUFS				(0x3f << 1)
396 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT			 1
397 	#define RX_TPA_END_CMP_TPA_SEGS				(0xff << 8)
398 	 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT			 8
399 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET			(0xff << 16)
400 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT		 16
401 	#define RX_TPA_END_CMP_AGG_ID				(0x7f << 25)
402 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT			 25
403 	#define RX_TPA_END_CMP_AGG_ID_P5			(0xffff << 16)
404 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5			 16
405 
406 	__le32 rx_tpa_end_cmp_tsdelta;
407 	#define RX_TPA_END_GRO_TS				(0x1 << 31)
408 };
409 
410 #define TPA_END_AGG_ID(rx_tpa_end)					\
411 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
412 	 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
413 
414 #define TPA_END_AGG_ID_P5(rx_tpa_end)					\
415 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
416 	 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
417 
418 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)					\
419 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
420 	 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
421 
422 #define TPA_END_AGG_BUFS(rx_tpa_end)					\
423 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
424 	 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
425 
426 #define TPA_END_TPA_SEGS(rx_tpa_end)					\
427 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
428 	 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
429 
430 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO				\
431 	cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &		\
432 		    RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
433 
434 #define TPA_END_GRO(rx_tpa_end)						\
435 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
436 	 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
437 
438 #define TPA_END_GRO_TS(rx_tpa_end)					\
439 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
440 	    cpu_to_le32(RX_TPA_END_GRO_TS)))
441 
442 struct rx_tpa_end_cmp_ext {
443 	__le32 rx_tpa_end_cmp_dup_acks;
444 	#define RX_TPA_END_CMP_TPA_DUP_ACKS			(0xf << 0)
445 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5		(0xff << 16)
446 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5		 16
447 	#define RX_TPA_END_CMP_AGG_BUFS_P5			(0xff << 24)
448 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5		 24
449 
450 	__le32 rx_tpa_end_cmp_seg_len;
451 	#define RX_TPA_END_CMP_TPA_SEG_LEN			(0xffff << 0)
452 
453 	__le32 rx_tpa_end_cmp_errors_v2;
454 	#define RX_TPA_END_CMP_V2				(0x1 << 0)
455 	#define RX_TPA_END_CMP_ERRORS				(0x3 << 1)
456 	#define RX_TPA_END_CMP_ERRORS_P5			(0x7 << 1)
457 	#define RX_TPA_END_CMPL_ERRORS_SHIFT			 1
458 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
459 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
460 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT	 (0x3 << 1)
461 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR	 (0x4 << 1)
462 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
463 
464 	u32 rx_tpa_end_cmp_start_opaque;
465 };
466 
467 #define TPA_END_ERRORS(rx_tpa_end_ext)					\
468 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
469 	 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
470 
471 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)				\
472 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
473 	 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>				\
474 	RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
475 
476 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)				\
477 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
478 	 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
479 
480 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\
481 	(((data1) &							\
482 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
483 	 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
484 
485 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\
486 	!!((data1) &							\
487 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
488 
489 #define EVENT_DATA1_RECOVERY_ENABLED(data1)				\
490 	!!((data1) &							\
491 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
492 
493 struct nqe_cn {
494 	__le16	type;
495 	#define NQ_CN_TYPE_MASK           0x3fUL
496 	#define NQ_CN_TYPE_SFT            0
497 	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
498 	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
499 	__le16	reserved16;
500 	__le32	cq_handle_low;
501 	__le32	v;
502 	#define NQ_CN_V     0x1UL
503 	__le32	cq_handle_high;
504 };
505 
506 #define DB_IDX_MASK						0xffffff
507 #define DB_IDX_VALID						(0x1 << 26)
508 #define DB_IRQ_DIS						(0x1 << 27)
509 #define DB_KEY_TX						(0x0 << 28)
510 #define DB_KEY_RX						(0x1 << 28)
511 #define DB_KEY_CP						(0x2 << 28)
512 #define DB_KEY_ST						(0x3 << 28)
513 #define DB_KEY_TX_PUSH						(0x4 << 28)
514 #define DB_LONG_TX_PUSH						(0x2 << 24)
515 
516 #define BNXT_MIN_ROCE_CP_RINGS	2
517 #define BNXT_MIN_ROCE_STAT_CTXS	1
518 
519 /* 64-bit doorbell */
520 #define DBR_INDEX_MASK					0x0000000000ffffffULL
521 #define DBR_XID_MASK					0x000fffff00000000ULL
522 #define DBR_XID_SFT					32
523 #define DBR_PATH_L2					(0x1ULL << 56)
524 #define DBR_TYPE_SQ					(0x0ULL << 60)
525 #define DBR_TYPE_RQ					(0x1ULL << 60)
526 #define DBR_TYPE_SRQ					(0x2ULL << 60)
527 #define DBR_TYPE_SRQ_ARM				(0x3ULL << 60)
528 #define DBR_TYPE_CQ					(0x4ULL << 60)
529 #define DBR_TYPE_CQ_ARMSE				(0x5ULL << 60)
530 #define DBR_TYPE_CQ_ARMALL				(0x6ULL << 60)
531 #define DBR_TYPE_CQ_ARMENA				(0x7ULL << 60)
532 #define DBR_TYPE_SRQ_ARMENA				(0x8ULL << 60)
533 #define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)
534 #define DBR_TYPE_NQ					(0xaULL << 60)
535 #define DBR_TYPE_NQ_ARM					(0xbULL << 60)
536 #define DBR_TYPE_NULL					(0xfULL << 60)
537 
538 #define INVALID_HW_RING_ID	((u16)-1)
539 
540 /* The hardware supports certain page sizes.  Use the supported page sizes
541  * to allocate the rings.
542  */
543 #if (PAGE_SHIFT < 12)
544 #define BNXT_PAGE_SHIFT	12
545 #elif (PAGE_SHIFT <= 13)
546 #define BNXT_PAGE_SHIFT	PAGE_SHIFT
547 #elif (PAGE_SHIFT < 16)
548 #define BNXT_PAGE_SHIFT	13
549 #else
550 #define BNXT_PAGE_SHIFT	16
551 #endif
552 
553 #define BNXT_PAGE_SIZE	(1 << BNXT_PAGE_SHIFT)
554 
555 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
556 #if (PAGE_SHIFT > 15)
557 #define BNXT_RX_PAGE_SHIFT 15
558 #else
559 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
560 #endif
561 
562 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
563 
564 #define BNXT_MAX_MTU		9500
565 #define BNXT_MAX_PAGE_MODE_MTU	\
566 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
567 	 XDP_PACKET_HEADROOM)
568 
569 #define BNXT_MIN_PKT_SIZE	52
570 
571 #define BNXT_DEFAULT_RX_RING_SIZE	511
572 #define BNXT_DEFAULT_TX_RING_SIZE	511
573 
574 #define MAX_TPA		64
575 #define MAX_TPA_P5	256
576 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
577 #define MAX_TPA_SEGS_P5	0x3f
578 
579 #if (BNXT_PAGE_SHIFT == 16)
580 #define MAX_RX_PAGES	1
581 #define MAX_RX_AGG_PAGES	4
582 #define MAX_TX_PAGES	1
583 #define MAX_CP_PAGES	8
584 #else
585 #define MAX_RX_PAGES	8
586 #define MAX_RX_AGG_PAGES	32
587 #define MAX_TX_PAGES	8
588 #define MAX_CP_PAGES	64
589 #endif
590 
591 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
592 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
593 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
594 
595 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
596 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
597 
598 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
599 
600 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
601 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
602 
603 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
604 
605 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
606 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
607 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
608 
609 #define RX_RING(x)	(((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
610 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
611 
612 #define TX_RING(x)	(((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
613 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
614 
615 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
616 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
617 
618 #define TX_CMP_VALID(txcmp, raw_cons)					\
619 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
620 	 !((raw_cons) & bp->cp_bit))
621 
622 #define RX_CMP_VALID(rxcmp1, raw_cons)					\
623 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
624 	 !((raw_cons) & bp->cp_bit))
625 
626 #define RX_AGG_CMP_VALID(agg, raw_cons)				\
627 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
628 	 !((raw_cons) & bp->cp_bit))
629 
630 #define NQ_CMP_VALID(nqcmp, raw_cons)				\
631 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
632 
633 #define TX_CMP_TYPE(txcmp)					\
634 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
635 
636 #define RX_CMP_TYPE(rxcmp)					\
637 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
638 
639 #define NEXT_RX(idx)		(((idx) + 1) & bp->rx_ring_mask)
640 
641 #define NEXT_RX_AGG(idx)	(((idx) + 1) & bp->rx_agg_ring_mask)
642 
643 #define NEXT_TX(idx)		(((idx) + 1) & bp->tx_ring_mask)
644 
645 #define ADV_RAW_CMP(idx, n)	((idx) + (n))
646 #define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)
647 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
648 #define NEXT_CMP(idx)		RING_CMP(ADV_RAW_CMP(idx, 1))
649 
650 #define BNXT_HWRM_MAX_REQ_LEN		(bp->hwrm_max_req_len)
651 #define BNXT_HWRM_SHORT_REQ_LEN		sizeof(struct hwrm_short_input)
652 #define DFLT_HWRM_CMD_TIMEOUT		500
653 #define SHORT_HWRM_CMD_TIMEOUT		20
654 #define HWRM_CMD_TIMEOUT		(bp->hwrm_cmd_timeout)
655 #define HWRM_RESET_TIMEOUT		((HWRM_CMD_TIMEOUT) * 4)
656 #define HWRM_COREDUMP_TIMEOUT		((HWRM_CMD_TIMEOUT) * 12)
657 #define HWRM_RESP_ERR_CODE_MASK		0xffff
658 #define HWRM_RESP_LEN_OFFSET		4
659 #define HWRM_RESP_LEN_MASK		0xffff0000
660 #define HWRM_RESP_LEN_SFT		16
661 #define HWRM_RESP_VALID_MASK		0xff000000
662 #define BNXT_HWRM_REQ_MAX_SIZE		128
663 #define BNXT_HWRM_REQS_PER_PAGE		(BNXT_PAGE_SIZE /	\
664 					 BNXT_HWRM_REQ_MAX_SIZE)
665 #define HWRM_SHORT_MIN_TIMEOUT		3
666 #define HWRM_SHORT_MAX_TIMEOUT		10
667 #define HWRM_SHORT_TIMEOUT_COUNTER	5
668 
669 #define HWRM_MIN_TIMEOUT		25
670 #define HWRM_MAX_TIMEOUT		40
671 
672 #define HWRM_TOTAL_TIMEOUT(n)	(((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?	\
673 	((n) * HWRM_SHORT_MIN_TIMEOUT) :				\
674 	(HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +		\
675 	 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
676 
677 #define HWRM_VALID_BIT_DELAY_USEC	150
678 
679 #define BNXT_HWRM_CHNL_CHIMP	0
680 #define BNXT_HWRM_CHNL_KONG	1
681 
682 #define BNXT_RX_EVENT		1
683 #define BNXT_AGG_EVENT		2
684 #define BNXT_TX_EVENT		4
685 #define BNXT_REDIRECT_EVENT	8
686 
687 struct bnxt_sw_tx_bd {
688 	union {
689 		struct sk_buff		*skb;
690 		struct xdp_frame	*xdpf;
691 	};
692 	DEFINE_DMA_UNMAP_ADDR(mapping);
693 	DEFINE_DMA_UNMAP_LEN(len);
694 	u8			is_gso;
695 	u8			is_push;
696 	u8			action;
697 	union {
698 		unsigned short		nr_frags;
699 		u16			rx_prod;
700 	};
701 };
702 
703 struct bnxt_sw_rx_bd {
704 	void			*data;
705 	u8			*data_ptr;
706 	dma_addr_t		mapping;
707 };
708 
709 struct bnxt_sw_rx_agg_bd {
710 	struct page		*page;
711 	unsigned int		offset;
712 	dma_addr_t		mapping;
713 };
714 
715 struct bnxt_ring_mem_info {
716 	int			nr_pages;
717 	int			page_size;
718 	u16			flags;
719 #define BNXT_RMEM_VALID_PTE_FLAG	1
720 #define BNXT_RMEM_RING_PTE_FLAG		2
721 #define BNXT_RMEM_USE_FULL_PAGE_FLAG	4
722 
723 	u16			depth;
724 	u8			init_val;
725 
726 	void			**pg_arr;
727 	dma_addr_t		*dma_arr;
728 
729 	__le64			*pg_tbl;
730 	dma_addr_t		pg_tbl_map;
731 
732 	int			vmem_size;
733 	void			**vmem;
734 };
735 
736 struct bnxt_ring_struct {
737 	struct bnxt_ring_mem_info	ring_mem;
738 
739 	u16			fw_ring_id; /* Ring id filled by Chimp FW */
740 	union {
741 		u16		grp_idx;
742 		u16		map_idx; /* Used by cmpl rings */
743 	};
744 	u32			handle;
745 	u8			queue_id;
746 };
747 
748 struct tx_push_bd {
749 	__le32			doorbell;
750 	__le32			tx_bd_len_flags_type;
751 	u32			tx_bd_opaque;
752 	struct tx_bd_ext	txbd2;
753 };
754 
755 struct tx_push_buffer {
756 	struct tx_push_bd	push_bd;
757 	u32			data[25];
758 };
759 
760 struct bnxt_db_info {
761 	void __iomem		*doorbell;
762 	union {
763 		u64		db_key64;
764 		u32		db_key32;
765 	};
766 };
767 
768 struct bnxt_tx_ring_info {
769 	struct bnxt_napi	*bnapi;
770 	u16			tx_prod;
771 	u16			tx_cons;
772 	u16			txq_index;
773 	struct bnxt_db_info	tx_db;
774 
775 	struct tx_bd		*tx_desc_ring[MAX_TX_PAGES];
776 	struct bnxt_sw_tx_bd	*tx_buf_ring;
777 
778 	dma_addr_t		tx_desc_mapping[MAX_TX_PAGES];
779 
780 	struct tx_push_buffer	*tx_push;
781 	dma_addr_t		tx_push_mapping;
782 	__le64			data_mapping;
783 
784 #define BNXT_DEV_STATE_CLOSING	0x1
785 	u32			dev_state;
786 
787 	struct bnxt_ring_struct	tx_ring_struct;
788 };
789 
790 #define BNXT_LEGACY_COAL_CMPL_PARAMS					\
791 	(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |		\
792 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |		\
793 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |		\
794 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |			\
795 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |		\
796 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
797 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |		\
798 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
799 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
800 
801 #define BNXT_COAL_CMPL_ENABLES						\
802 	(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
803 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
804 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
805 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
806 
807 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE					\
808 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
809 
810 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE			\
811 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
812 
813 struct bnxt_coal_cap {
814 	u32			cmpl_params;
815 	u32			nq_params;
816 	u16			num_cmpl_dma_aggr_max;
817 	u16			num_cmpl_dma_aggr_during_int_max;
818 	u16			cmpl_aggr_dma_tmr_max;
819 	u16			cmpl_aggr_dma_tmr_during_int_max;
820 	u16			int_lat_tmr_min_max;
821 	u16			int_lat_tmr_max_max;
822 	u16			num_cmpl_aggr_int_max;
823 	u16			timer_units;
824 };
825 
826 struct bnxt_coal {
827 	u16			coal_ticks;
828 	u16			coal_ticks_irq;
829 	u16			coal_bufs;
830 	u16			coal_bufs_irq;
831 			/* RING_IDLE enabled when coal ticks < idle_thresh  */
832 	u16			idle_thresh;
833 	u8			bufs_per_record;
834 	u8			budget;
835 };
836 
837 struct bnxt_tpa_info {
838 	void			*data;
839 	u8			*data_ptr;
840 	dma_addr_t		mapping;
841 	u16			len;
842 	unsigned short		gso_type;
843 	u32			flags2;
844 	u32			metadata;
845 	enum pkt_hash_types	hash_type;
846 	u32			rss_hash;
847 	u32			hdr_info;
848 
849 #define BNXT_TPA_L4_SIZE(hdr_info)	\
850 	(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
851 
852 #define BNXT_TPA_INNER_L3_OFF(hdr_info)	\
853 	(((hdr_info) >> 18) & 0x1ff)
854 
855 #define BNXT_TPA_INNER_L2_OFF(hdr_info)	\
856 	(((hdr_info) >> 9) & 0x1ff)
857 
858 #define BNXT_TPA_OUTER_L3_OFF(hdr_info)	\
859 	((hdr_info) & 0x1ff)
860 
861 	u16			cfa_code; /* cfa_code in TPA start compl */
862 	u8			agg_count;
863 	struct rx_agg_cmp	*agg_arr;
864 };
865 
866 #define BNXT_AGG_IDX_BMAP_SIZE	(MAX_TPA_P5 / BITS_PER_LONG)
867 
868 struct bnxt_tpa_idx_map {
869 	u16		agg_id_tbl[1024];
870 	unsigned long	agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
871 };
872 
873 struct bnxt_rx_ring_info {
874 	struct bnxt_napi	*bnapi;
875 	u16			rx_prod;
876 	u16			rx_agg_prod;
877 	u16			rx_sw_agg_prod;
878 	u16			rx_next_cons;
879 	struct bnxt_db_info	rx_db;
880 	struct bnxt_db_info	rx_agg_db;
881 
882 	struct bpf_prog		*xdp_prog;
883 
884 	struct rx_bd		*rx_desc_ring[MAX_RX_PAGES];
885 	struct bnxt_sw_rx_bd	*rx_buf_ring;
886 
887 	struct rx_bd		*rx_agg_desc_ring[MAX_RX_AGG_PAGES];
888 	struct bnxt_sw_rx_agg_bd	*rx_agg_ring;
889 
890 	unsigned long		*rx_agg_bmap;
891 	u16			rx_agg_bmap_size;
892 
893 	struct page		*rx_page;
894 	unsigned int		rx_page_offset;
895 
896 	dma_addr_t		rx_desc_mapping[MAX_RX_PAGES];
897 	dma_addr_t		rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
898 
899 	struct bnxt_tpa_info	*rx_tpa;
900 	struct bnxt_tpa_idx_map *rx_tpa_idx_map;
901 
902 	struct bnxt_ring_struct	rx_ring_struct;
903 	struct bnxt_ring_struct	rx_agg_ring_struct;
904 	struct xdp_rxq_info	xdp_rxq;
905 	struct page_pool	*page_pool;
906 };
907 
908 struct bnxt_cp_ring_info {
909 	struct bnxt_napi	*bnapi;
910 	u32			cp_raw_cons;
911 	struct bnxt_db_info	cp_db;
912 
913 	u8			had_work_done:1;
914 	u8			has_more_work:1;
915 
916 	u32			last_cp_raw_cons;
917 
918 	struct bnxt_coal	rx_ring_coal;
919 	u64			rx_packets;
920 	u64			rx_bytes;
921 	u64			event_ctr;
922 
923 	struct dim		dim;
924 
925 	union {
926 		struct tx_cmp	*cp_desc_ring[MAX_CP_PAGES];
927 		struct nqe_cn	*nq_desc_ring[MAX_CP_PAGES];
928 	};
929 
930 	dma_addr_t		cp_desc_mapping[MAX_CP_PAGES];
931 
932 	struct ctx_hw_stats	*hw_stats;
933 	dma_addr_t		hw_stats_map;
934 	u32			hw_stats_ctx_id;
935 	u64			rx_l4_csum_errors;
936 	u64			rx_buf_errors;
937 	u64			missed_irqs;
938 
939 	struct bnxt_ring_struct	cp_ring_struct;
940 
941 	struct bnxt_cp_ring_info *cp_ring_arr[2];
942 #define BNXT_RX_HDL	0
943 #define BNXT_TX_HDL	1
944 };
945 
946 struct bnxt_napi {
947 	struct napi_struct	napi;
948 	struct bnxt		*bp;
949 
950 	int			index;
951 	struct bnxt_cp_ring_info	cp_ring;
952 	struct bnxt_rx_ring_info	*rx_ring;
953 	struct bnxt_tx_ring_info	*tx_ring;
954 
955 	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,
956 					  int);
957 	int			tx_pkts;
958 	u8			events;
959 
960 	u32			flags;
961 #define BNXT_NAPI_FLAG_XDP	0x1
962 
963 	bool			in_reset;
964 };
965 
966 struct bnxt_irq {
967 	irq_handler_t	handler;
968 	unsigned int	vector;
969 	u8		requested:1;
970 	u8		have_cpumask:1;
971 	char		name[IFNAMSIZ + 2];
972 	cpumask_var_t	cpu_mask;
973 };
974 
975 #define HWRM_RING_ALLOC_TX	0x1
976 #define HWRM_RING_ALLOC_RX	0x2
977 #define HWRM_RING_ALLOC_AGG	0x4
978 #define HWRM_RING_ALLOC_CMPL	0x8
979 #define HWRM_RING_ALLOC_NQ	0x10
980 
981 #define INVALID_STATS_CTX_ID	-1
982 
983 struct bnxt_ring_grp_info {
984 	u16	fw_stats_ctx;
985 	u16	fw_grp_id;
986 	u16	rx_fw_ring_id;
987 	u16	agg_fw_ring_id;
988 	u16	cp_fw_ring_id;
989 };
990 
991 struct bnxt_vnic_info {
992 	u16		fw_vnic_id; /* returned by Chimp during alloc */
993 #define BNXT_MAX_CTX_PER_VNIC	8
994 	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
995 	u16		fw_l2_ctx_id;
996 #define BNXT_MAX_UC_ADDRS	4
997 	__le64		fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
998 				/* index 0 always dev_addr */
999 	u16		uc_filter_count;
1000 	u8		*uc_list;
1001 
1002 	u16		*fw_grp_ids;
1003 	dma_addr_t	rss_table_dma_addr;
1004 	__le16		*rss_table;
1005 	dma_addr_t	rss_hash_key_dma_addr;
1006 	u64		*rss_hash_key;
1007 	u32		rx_mask;
1008 
1009 	u8		*mc_list;
1010 	int		mc_list_size;
1011 	int		mc_list_count;
1012 	dma_addr_t	mc_list_mapping;
1013 #define BNXT_MAX_MC_ADDRS	16
1014 
1015 	u32		flags;
1016 #define BNXT_VNIC_RSS_FLAG	1
1017 #define BNXT_VNIC_RFS_FLAG	2
1018 #define BNXT_VNIC_MCAST_FLAG	4
1019 #define BNXT_VNIC_UCAST_FLAG	8
1020 #define BNXT_VNIC_RFS_NEW_RSS_FLAG	0x10
1021 };
1022 
1023 struct bnxt_hw_resc {
1024 	u16	min_rsscos_ctxs;
1025 	u16	max_rsscos_ctxs;
1026 	u16	min_cp_rings;
1027 	u16	max_cp_rings;
1028 	u16	resv_cp_rings;
1029 	u16	min_tx_rings;
1030 	u16	max_tx_rings;
1031 	u16	resv_tx_rings;
1032 	u16	max_tx_sch_inputs;
1033 	u16	min_rx_rings;
1034 	u16	max_rx_rings;
1035 	u16	resv_rx_rings;
1036 	u16	min_hw_ring_grps;
1037 	u16	max_hw_ring_grps;
1038 	u16	resv_hw_ring_grps;
1039 	u16	min_l2_ctxs;
1040 	u16	max_l2_ctxs;
1041 	u16	min_vnics;
1042 	u16	max_vnics;
1043 	u16	resv_vnics;
1044 	u16	min_stat_ctxs;
1045 	u16	max_stat_ctxs;
1046 	u16	resv_stat_ctxs;
1047 	u16	max_nqs;
1048 	u16	max_irqs;
1049 	u16	resv_irqs;
1050 };
1051 
1052 #if defined(CONFIG_BNXT_SRIOV)
1053 struct bnxt_vf_info {
1054 	u16	fw_fid;
1055 	u8	mac_addr[ETH_ALEN];	/* PF assigned MAC Address */
1056 	u8	vf_mac_addr[ETH_ALEN];	/* VF assigned MAC address, only
1057 					 * stored by PF.
1058 					 */
1059 	u16	vlan;
1060 	u16	func_qcfg_flags;
1061 	u32	flags;
1062 #define BNXT_VF_QOS		0x1
1063 #define BNXT_VF_SPOOFCHK	0x2
1064 #define BNXT_VF_LINK_FORCED	0x4
1065 #define BNXT_VF_LINK_UP		0x8
1066 #define BNXT_VF_TRUST		0x10
1067 	u32	func_flags; /* func cfg flags */
1068 	u32	min_tx_rate;
1069 	u32	max_tx_rate;
1070 	void	*hwrm_cmd_req_addr;
1071 	dma_addr_t	hwrm_cmd_req_dma_addr;
1072 };
1073 #endif
1074 
1075 struct bnxt_pf_info {
1076 #define BNXT_FIRST_PF_FID	1
1077 #define BNXT_FIRST_VF_FID	128
1078 	u16	fw_fid;
1079 	u16	port_id;
1080 	u8	mac_addr[ETH_ALEN];
1081 	u32	first_vf_id;
1082 	u16	active_vfs;
1083 	u16	registered_vfs;
1084 	u16	max_vfs;
1085 	u32	max_encap_records;
1086 	u32	max_decap_records;
1087 	u32	max_tx_em_flows;
1088 	u32	max_tx_wm_flows;
1089 	u32	max_rx_em_flows;
1090 	u32	max_rx_wm_flows;
1091 	unsigned long	*vf_event_bmap;
1092 	u16	hwrm_cmd_req_pages;
1093 	u8	vf_resv_strategy;
1094 #define BNXT_VF_RESV_STRATEGY_MAXIMAL	0
1095 #define BNXT_VF_RESV_STRATEGY_MINIMAL	1
1096 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC	2
1097 	void			*hwrm_cmd_req_addr[4];
1098 	dma_addr_t		hwrm_cmd_req_dma_addr[4];
1099 	struct bnxt_vf_info	*vf;
1100 };
1101 
1102 struct bnxt_ntuple_filter {
1103 	struct hlist_node	hash;
1104 	u8			dst_mac_addr[ETH_ALEN];
1105 	u8			src_mac_addr[ETH_ALEN];
1106 	struct flow_keys	fkeys;
1107 	__le64			filter_id;
1108 	u16			sw_id;
1109 	u8			l2_fltr_idx;
1110 	u16			rxq;
1111 	u32			flow_id;
1112 	unsigned long		state;
1113 #define BNXT_FLTR_VALID		0
1114 #define BNXT_FLTR_UPDATE	1
1115 };
1116 
1117 struct bnxt_link_info {
1118 	u8			phy_type;
1119 	u8			media_type;
1120 	u8			transceiver;
1121 	u8			phy_addr;
1122 	u8			phy_link_status;
1123 #define BNXT_LINK_NO_LINK	PORT_PHY_QCFG_RESP_LINK_NO_LINK
1124 #define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL
1125 #define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK
1126 	u8			wire_speed;
1127 	u8			loop_back;
1128 	u8			link_up;
1129 	u8			duplex;
1130 #define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1131 #define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1132 	u8			pause;
1133 #define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX
1134 #define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX
1135 #define BNXT_LINK_PAUSE_BOTH	(PORT_PHY_QCFG_RESP_PAUSE_RX | \
1136 				 PORT_PHY_QCFG_RESP_PAUSE_TX)
1137 	u8			lp_pause;
1138 	u8			auto_pause_setting;
1139 	u8			force_pause_setting;
1140 	u8			duplex_setting;
1141 	u8			auto_mode;
1142 #define BNXT_AUTO_MODE(mode)	((mode) > BNXT_LINK_AUTO_NONE && \
1143 				 (mode) <= BNXT_LINK_AUTO_MSK)
1144 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1145 #define BNXT_LINK_AUTO_ALLSPDS	PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1146 #define BNXT_LINK_AUTO_ONESPD	PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1147 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1148 #define BNXT_LINK_AUTO_MSK	PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1149 #define PHY_VER_LEN		3
1150 	u8			phy_ver[PHY_VER_LEN];
1151 	u16			link_speed;
1152 #define BNXT_LINK_SPEED_100MB	PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1153 #define BNXT_LINK_SPEED_1GB	PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1154 #define BNXT_LINK_SPEED_2GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1155 #define BNXT_LINK_SPEED_2_5GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1156 #define BNXT_LINK_SPEED_10GB	PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1157 #define BNXT_LINK_SPEED_20GB	PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1158 #define BNXT_LINK_SPEED_25GB	PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1159 #define BNXT_LINK_SPEED_40GB	PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1160 #define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1161 #define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1162 	u16			support_speeds;
1163 	u16			auto_link_speeds;	/* fw adv setting */
1164 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1165 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1166 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1167 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1168 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1169 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1170 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1171 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1172 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1173 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1174 	u16			support_auto_speeds;
1175 	u16			lp_auto_link_speeds;
1176 	u16			force_link_speed;
1177 	u32			preemphasis;
1178 	u8			module_status;
1179 	u16			fec_cfg;
1180 #define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1181 #define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1182 #define BNXT_FEC_ENC_RS		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1183 
1184 	/* copy of requested setting from ethtool cmd */
1185 	u8			autoneg;
1186 #define BNXT_AUTONEG_SPEED		1
1187 #define BNXT_AUTONEG_FLOW_CTRL		2
1188 	u8			req_duplex;
1189 	u8			req_flow_ctrl;
1190 	u16			req_link_speed;
1191 	u16			advertising;	/* user adv setting */
1192 	bool			force_link_chng;
1193 
1194 	bool			phy_retry;
1195 	unsigned long		phy_retry_expires;
1196 
1197 	/* a copy of phy_qcfg output used to report link
1198 	 * info to VF
1199 	 */
1200 	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1201 };
1202 
1203 #define BNXT_MAX_QUEUE	8
1204 
1205 struct bnxt_queue_info {
1206 	u8	queue_id;
1207 	u8	queue_profile;
1208 };
1209 
1210 #define BNXT_MAX_LED			4
1211 
1212 struct bnxt_led_info {
1213 	u8	led_id;
1214 	u8	led_type;
1215 	u8	led_group_id;
1216 	u8	unused;
1217 	__le16	led_state_caps;
1218 #define BNXT_LED_ALT_BLINK_CAP(x)	((x) &	\
1219 	cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1220 
1221 	__le16	led_color_caps;
1222 };
1223 
1224 #define BNXT_MAX_TEST	8
1225 
1226 struct bnxt_test_info {
1227 	u8 offline_mask;
1228 	u8 flags;
1229 #define BNXT_TEST_FL_EXT_LPBK		0x1
1230 #define BNXT_TEST_FL_AN_PHY_LPBK	0x2
1231 	u16 timeout;
1232 	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1233 };
1234 
1235 #define BNXT_GRCPF_REG_CHIMP_COMM		0x0
1236 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100
1237 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x400
1238 #define BNXT_CAG_REG_LEGACY_INT_STATUS		0x4014
1239 #define BNXT_CAG_REG_BASE			0x300000
1240 
1241 #define BNXT_GRCPF_REG_KONG_COMM		0xA00
1242 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB00
1243 
1244 #define BNXT_GRC_BASE_MASK			0xfffff000
1245 #define BNXT_GRC_OFFSET_MASK			0x00000ffc
1246 
1247 struct bnxt_tc_flow_stats {
1248 	u64		packets;
1249 	u64		bytes;
1250 };
1251 
1252 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1253 struct bnxt_flower_indr_block_cb_priv {
1254 	struct net_device *tunnel_netdev;
1255 	struct bnxt *bp;
1256 	struct list_head list;
1257 };
1258 #endif
1259 
1260 struct bnxt_tc_info {
1261 	bool				enabled;
1262 
1263 	/* hash table to store TC offloaded flows */
1264 	struct rhashtable		flow_table;
1265 	struct rhashtable_params	flow_ht_params;
1266 
1267 	/* hash table to store L2 keys of TC flows */
1268 	struct rhashtable		l2_table;
1269 	struct rhashtable_params	l2_ht_params;
1270 	/* hash table to store L2 keys for TC tunnel decap */
1271 	struct rhashtable		decap_l2_table;
1272 	struct rhashtable_params	decap_l2_ht_params;
1273 	/* hash table to store tunnel decap entries */
1274 	struct rhashtable		decap_table;
1275 	struct rhashtable_params	decap_ht_params;
1276 	/* hash table to store tunnel encap entries */
1277 	struct rhashtable		encap_table;
1278 	struct rhashtable_params	encap_ht_params;
1279 
1280 	/* lock to atomically add/del an l2 node when a flow is
1281 	 * added or deleted.
1282 	 */
1283 	struct mutex			lock;
1284 
1285 	/* Fields used for batching stats query */
1286 	struct rhashtable_iter		iter;
1287 #define BNXT_FLOW_STATS_BATCH_MAX	10
1288 	struct bnxt_tc_stats_batch {
1289 		void			  *flow_node;
1290 		struct bnxt_tc_flow_stats hw_stats;
1291 	} stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1292 
1293 	/* Stat counter mask (width) */
1294 	u64				bytes_mask;
1295 	u64				packets_mask;
1296 };
1297 
1298 struct bnxt_vf_rep_stats {
1299 	u64			packets;
1300 	u64			bytes;
1301 	u64			dropped;
1302 };
1303 
1304 struct bnxt_vf_rep {
1305 	struct bnxt			*bp;
1306 	struct net_device		*dev;
1307 	struct metadata_dst		*dst;
1308 	u16				vf_idx;
1309 	u16				tx_cfa_action;
1310 	u16				rx_cfa_code;
1311 
1312 	struct bnxt_vf_rep_stats	rx_stats;
1313 	struct bnxt_vf_rep_stats	tx_stats;
1314 };
1315 
1316 #define PTU_PTE_VALID             0x1UL
1317 #define PTU_PTE_LAST              0x2UL
1318 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1319 
1320 #define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)
1321 #define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)
1322 
1323 struct bnxt_ctx_pg_info {
1324 	u32		entries;
1325 	u32		nr_pages;
1326 	void		*ctx_pg_arr[MAX_CTX_PAGES];
1327 	dma_addr_t	ctx_dma_arr[MAX_CTX_PAGES];
1328 	struct bnxt_ring_mem_info ring_mem;
1329 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
1330 };
1331 
1332 struct bnxt_ctx_mem_info {
1333 	u32	qp_max_entries;
1334 	u16	qp_min_qp1_entries;
1335 	u16	qp_max_l2_entries;
1336 	u16	qp_entry_size;
1337 	u16	srq_max_l2_entries;
1338 	u32	srq_max_entries;
1339 	u16	srq_entry_size;
1340 	u16	cq_max_l2_entries;
1341 	u32	cq_max_entries;
1342 	u16	cq_entry_size;
1343 	u16	vnic_max_vnic_entries;
1344 	u16	vnic_max_ring_table_entries;
1345 	u16	vnic_entry_size;
1346 	u32	stat_max_entries;
1347 	u16	stat_entry_size;
1348 	u16	tqm_entry_size;
1349 	u32	tqm_min_entries_per_ring;
1350 	u32	tqm_max_entries_per_ring;
1351 	u32	mrav_max_entries;
1352 	u16	mrav_entry_size;
1353 	u16	tim_entry_size;
1354 	u32	tim_max_entries;
1355 	u16	mrav_num_entries_units;
1356 	u8	tqm_entries_multiple;
1357 	u8	ctx_kind_initializer;
1358 
1359 	u32	flags;
1360 	#define BNXT_CTX_FLAG_INITED	0x01
1361 
1362 	struct bnxt_ctx_pg_info qp_mem;
1363 	struct bnxt_ctx_pg_info srq_mem;
1364 	struct bnxt_ctx_pg_info cq_mem;
1365 	struct bnxt_ctx_pg_info vnic_mem;
1366 	struct bnxt_ctx_pg_info stat_mem;
1367 	struct bnxt_ctx_pg_info mrav_mem;
1368 	struct bnxt_ctx_pg_info tim_mem;
1369 	struct bnxt_ctx_pg_info *tqm_mem[9];
1370 };
1371 
1372 struct bnxt_fw_health {
1373 	u32 flags;
1374 	u32 polling_dsecs;
1375 	u32 master_func_wait_dsecs;
1376 	u32 normal_func_wait_dsecs;
1377 	u32 post_reset_wait_dsecs;
1378 	u32 post_reset_max_wait_dsecs;
1379 	u32 regs[4];
1380 	u32 mapped_regs[4];
1381 #define BNXT_FW_HEALTH_REG		0
1382 #define BNXT_FW_HEARTBEAT_REG		1
1383 #define BNXT_FW_RESET_CNT_REG		2
1384 #define BNXT_FW_RESET_INPROG_REG	3
1385 	u32 fw_reset_inprog_reg_mask;
1386 	u32 last_fw_heartbeat;
1387 	u32 last_fw_reset_cnt;
1388 	u8 enabled:1;
1389 	u8 master:1;
1390 	u8 fatal:1;
1391 	u8 tmr_multiplier;
1392 	u8 tmr_counter;
1393 	u8 fw_reset_seq_cnt;
1394 	u32 fw_reset_seq_regs[16];
1395 	u32 fw_reset_seq_vals[16];
1396 	u32 fw_reset_seq_delay_msec[16];
1397 	struct devlink_health_reporter	*fw_reporter;
1398 	struct devlink_health_reporter *fw_reset_reporter;
1399 	struct devlink_health_reporter *fw_fatal_reporter;
1400 };
1401 
1402 struct bnxt_fw_reporter_ctx {
1403 	unsigned long sp_event;
1404 };
1405 
1406 #define BNXT_FW_HEALTH_REG_TYPE_MASK	3
1407 #define BNXT_FW_HEALTH_REG_TYPE_CFG	0
1408 #define BNXT_FW_HEALTH_REG_TYPE_GRC	1
1409 #define BNXT_FW_HEALTH_REG_TYPE_BAR0	2
1410 #define BNXT_FW_HEALTH_REG_TYPE_BAR1	3
1411 
1412 #define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1413 #define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1414 
1415 #define BNXT_FW_HEALTH_WIN_BASE		0x3000
1416 #define BNXT_FW_HEALTH_WIN_MAP_OFF	8
1417 
1418 #define BNXT_FW_STATUS_HEALTHY		0x8000
1419 #define BNXT_FW_STATUS_SHUTDOWN		0x100000
1420 
1421 struct bnxt {
1422 	void __iomem		*bar0;
1423 	void __iomem		*bar1;
1424 	void __iomem		*bar2;
1425 
1426 	u32			reg_base;
1427 	u16			chip_num;
1428 #define CHIP_NUM_57301		0x16c8
1429 #define CHIP_NUM_57302		0x16c9
1430 #define CHIP_NUM_57304		0x16ca
1431 #define CHIP_NUM_58700		0x16cd
1432 #define CHIP_NUM_57402		0x16d0
1433 #define CHIP_NUM_57404		0x16d1
1434 #define CHIP_NUM_57406		0x16d2
1435 #define CHIP_NUM_57407		0x16d5
1436 
1437 #define CHIP_NUM_57311		0x16ce
1438 #define CHIP_NUM_57312		0x16cf
1439 #define CHIP_NUM_57314		0x16df
1440 #define CHIP_NUM_57317		0x16e0
1441 #define CHIP_NUM_57412		0x16d6
1442 #define CHIP_NUM_57414		0x16d7
1443 #define CHIP_NUM_57416		0x16d8
1444 #define CHIP_NUM_57417		0x16d9
1445 #define CHIP_NUM_57412L		0x16da
1446 #define CHIP_NUM_57414L		0x16db
1447 
1448 #define CHIP_NUM_5745X		0xd730
1449 #define CHIP_NUM_57452		0xc452
1450 #define CHIP_NUM_57454		0xc454
1451 
1452 #define CHIP_NUM_57508		0x1750
1453 #define CHIP_NUM_57504		0x1751
1454 #define CHIP_NUM_57502		0x1752
1455 
1456 #define CHIP_NUM_58802		0xd802
1457 #define CHIP_NUM_58804		0xd804
1458 #define CHIP_NUM_58808		0xd808
1459 
1460 	u8			chip_rev;
1461 
1462 #define BNXT_CHIP_NUM_5730X(chip_num)		\
1463 	((chip_num) >= CHIP_NUM_57301 &&	\
1464 	 (chip_num) <= CHIP_NUM_57304)
1465 
1466 #define BNXT_CHIP_NUM_5740X(chip_num)		\
1467 	(((chip_num) >= CHIP_NUM_57402 &&	\
1468 	  (chip_num) <= CHIP_NUM_57406) ||	\
1469 	 (chip_num) == CHIP_NUM_57407)
1470 
1471 #define BNXT_CHIP_NUM_5731X(chip_num)		\
1472 	((chip_num) == CHIP_NUM_57311 ||	\
1473 	 (chip_num) == CHIP_NUM_57312 ||	\
1474 	 (chip_num) == CHIP_NUM_57314 ||	\
1475 	 (chip_num) == CHIP_NUM_57317)
1476 
1477 #define BNXT_CHIP_NUM_5741X(chip_num)		\
1478 	((chip_num) >= CHIP_NUM_57412 &&	\
1479 	 (chip_num) <= CHIP_NUM_57414L)
1480 
1481 #define BNXT_CHIP_NUM_58700(chip_num)		\
1482 	 ((chip_num) == CHIP_NUM_58700)
1483 
1484 #define BNXT_CHIP_NUM_5745X(chip_num)		\
1485 	((chip_num) == CHIP_NUM_5745X ||	\
1486 	 (chip_num) == CHIP_NUM_57452 ||	\
1487 	 (chip_num) == CHIP_NUM_57454)
1488 
1489 
1490 #define BNXT_CHIP_NUM_57X0X(chip_num)		\
1491 	(BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1492 
1493 #define BNXT_CHIP_NUM_57X1X(chip_num)		\
1494 	(BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1495 
1496 #define BNXT_CHIP_NUM_588XX(chip_num)		\
1497 	((chip_num) == CHIP_NUM_58802 ||	\
1498 	 (chip_num) == CHIP_NUM_58804 ||        \
1499 	 (chip_num) == CHIP_NUM_58808)
1500 
1501 	struct net_device	*dev;
1502 	struct pci_dev		*pdev;
1503 
1504 	atomic_t		intr_sem;
1505 
1506 	u32			flags;
1507 	#define BNXT_FLAG_CHIP_P5	0x1
1508 	#define BNXT_FLAG_VF		0x2
1509 	#define BNXT_FLAG_LRO		0x4
1510 #ifdef CONFIG_INET
1511 	#define BNXT_FLAG_GRO		0x8
1512 #else
1513 	/* Cannot support hardware GRO if CONFIG_INET is not set */
1514 	#define BNXT_FLAG_GRO		0x0
1515 #endif
1516 	#define BNXT_FLAG_TPA		(BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1517 	#define BNXT_FLAG_JUMBO		0x10
1518 	#define BNXT_FLAG_STRIP_VLAN	0x20
1519 	#define BNXT_FLAG_AGG_RINGS	(BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1520 					 BNXT_FLAG_LRO)
1521 	#define BNXT_FLAG_USING_MSIX	0x40
1522 	#define BNXT_FLAG_MSIX_CAP	0x80
1523 	#define BNXT_FLAG_RFS		0x100
1524 	#define BNXT_FLAG_SHARED_RINGS	0x200
1525 	#define BNXT_FLAG_PORT_STATS	0x400
1526 	#define BNXT_FLAG_UDP_RSS_CAP	0x800
1527 	#define BNXT_FLAG_EEE_CAP	0x1000
1528 	#define BNXT_FLAG_NEW_RSS_CAP	0x2000
1529 	#define BNXT_FLAG_WOL_CAP	0x4000
1530 	#define BNXT_FLAG_ROCEV1_CAP	0x8000
1531 	#define BNXT_FLAG_ROCEV2_CAP	0x10000
1532 	#define BNXT_FLAG_ROCE_CAP	(BNXT_FLAG_ROCEV1_CAP |	\
1533 					 BNXT_FLAG_ROCEV2_CAP)
1534 	#define BNXT_FLAG_NO_AGG_RINGS	0x20000
1535 	#define BNXT_FLAG_RX_PAGE_MODE	0x40000
1536 	#define BNXT_FLAG_MULTI_HOST	0x100000
1537 	#define BNXT_FLAG_DSN_VALID	0x200000
1538 	#define BNXT_FLAG_DOUBLE_DB	0x400000
1539 	#define BNXT_FLAG_CHIP_NITRO_A0	0x1000000
1540 	#define BNXT_FLAG_DIM		0x2000000
1541 	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x4000000
1542 	#define BNXT_FLAG_PORT_STATS_EXT	0x10000000
1543 	#define BNXT_FLAG_PCIE_STATS	0x40000000
1544 
1545 	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\
1546 					    BNXT_FLAG_RFS |		\
1547 					    BNXT_FLAG_STRIP_VLAN)
1548 
1549 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
1550 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
1551 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
1552 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
1553 #define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1554 #define BNXT_PHY_CFG_ABLE(bp)	(BNXT_SINGLE_PF(bp) ||			\
1555 				 ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG))
1556 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1557 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1558 #define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\
1559 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\
1560 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
1561 
1562 /* Chip class phase 5 */
1563 #define BNXT_CHIP_P5(bp)			\
1564 	((bp)->chip_num == CHIP_NUM_57508 ||	\
1565 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
1566 	 (bp)->chip_num == CHIP_NUM_57502)
1567 
1568 /* Chip class phase 4.x */
1569 #define BNXT_CHIP_P4(bp)			\
1570 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
1571 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
1572 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
1573 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
1574 	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1575 
1576 #define BNXT_CHIP_P4_PLUS(bp)			\
1577 	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1578 
1579 	struct bnxt_en_dev	*edev;
1580 	struct bnxt_en_dev *	(*ulp_probe)(struct net_device *);
1581 
1582 	struct bnxt_napi	**bnapi;
1583 
1584 	struct bnxt_rx_ring_info	*rx_ring;
1585 	struct bnxt_tx_ring_info	*tx_ring;
1586 	u16			*tx_ring_map;
1587 
1588 	struct sk_buff *	(*gro_func)(struct bnxt_tpa_info *, int, int,
1589 					    struct sk_buff *);
1590 
1591 	struct sk_buff *	(*rx_skb_func)(struct bnxt *,
1592 					       struct bnxt_rx_ring_info *,
1593 					       u16, void *, u8 *, dma_addr_t,
1594 					       unsigned int);
1595 
1596 	u16			max_tpa_v2;
1597 	u16			max_tpa;
1598 	u32			rx_buf_size;
1599 	u32			rx_buf_use_size;	/* useable size */
1600 	u16			rx_offset;
1601 	u16			rx_dma_offset;
1602 	enum dma_data_direction	rx_dir;
1603 	u32			rx_ring_size;
1604 	u32			rx_agg_ring_size;
1605 	u32			rx_copy_thresh;
1606 	u32			rx_ring_mask;
1607 	u32			rx_agg_ring_mask;
1608 	int			rx_nr_pages;
1609 	int			rx_agg_nr_pages;
1610 	int			rx_nr_rings;
1611 	int			rsscos_nr_ctxs;
1612 
1613 	u32			tx_ring_size;
1614 	u32			tx_ring_mask;
1615 	int			tx_nr_pages;
1616 	int			tx_nr_rings;
1617 	int			tx_nr_rings_per_tc;
1618 	int			tx_nr_rings_xdp;
1619 
1620 	int			tx_wake_thresh;
1621 	int			tx_push_thresh;
1622 	int			tx_push_size;
1623 
1624 	u32			cp_ring_size;
1625 	u32			cp_ring_mask;
1626 	u32			cp_bit;
1627 	int			cp_nr_pages;
1628 	int			cp_nr_rings;
1629 
1630 	/* grp_info indexed by completion ring index */
1631 	struct bnxt_ring_grp_info	*grp_info;
1632 	struct bnxt_vnic_info	*vnic_info;
1633 	int			nr_vnics;
1634 	u32			rss_hash_cfg;
1635 
1636 	u16			max_mtu;
1637 	u8			max_tc;
1638 	u8			max_lltc;	/* lossless TCs */
1639 	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];
1640 	u8			tc_to_qidx[BNXT_MAX_QUEUE];
1641 	u8			q_ids[BNXT_MAX_QUEUE];
1642 	u8			max_q;
1643 
1644 	unsigned int		current_interval;
1645 #define BNXT_TIMER_INTERVAL	HZ
1646 
1647 	struct timer_list	timer;
1648 
1649 	unsigned long		state;
1650 #define BNXT_STATE_OPEN		0
1651 #define BNXT_STATE_IN_SP_TASK	1
1652 #define BNXT_STATE_READ_STATS	2
1653 #define BNXT_STATE_FW_RESET_DET 3
1654 #define BNXT_STATE_IN_FW_RESET	4
1655 #define BNXT_STATE_ABORT_ERR	5
1656 #define BNXT_STATE_FW_FATAL_COND	6
1657 #define BNXT_STATE_DRV_REGISTERED	7
1658 
1659 	struct bnxt_irq	*irq_tbl;
1660 	int			total_irqs;
1661 	u8			mac_addr[ETH_ALEN];
1662 
1663 #ifdef CONFIG_BNXT_DCB
1664 	struct ieee_pfc		*ieee_pfc;
1665 	struct ieee_ets		*ieee_ets;
1666 	u8			dcbx_cap;
1667 	u8			default_pri;
1668 	u8			max_dscp_value;
1669 #endif /* CONFIG_BNXT_DCB */
1670 
1671 	u32			msg_enable;
1672 
1673 	u32			fw_cap;
1674 	#define BNXT_FW_CAP_SHORT_CMD			0x00000001
1675 	#define BNXT_FW_CAP_LLDP_AGENT			0x00000002
1676 	#define BNXT_FW_CAP_DCBX_AGENT			0x00000004
1677 	#define BNXT_FW_CAP_NEW_RM			0x00000008
1678 	#define BNXT_FW_CAP_IF_CHANGE			0x00000010
1679 	#define BNXT_FW_CAP_KONG_MB_CHNL		0x00000080
1680 	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		0x00000400
1681 	#define BNXT_FW_CAP_TRUSTED_VF			0x00000800
1682 	#define BNXT_FW_CAP_ERROR_RECOVERY		0x00002000
1683 	#define BNXT_FW_CAP_PKG_VER			0x00004000
1684 	#define BNXT_FW_CAP_CFA_ADV_FLOW		0x00008000
1685 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	0x00010000
1686 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	0x00020000
1687 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		0x00040000
1688 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		0x00100000
1689 	#define BNXT_FW_CAP_HOT_RESET			0x00200000
1690 	#define BNXT_FW_CAP_SHARED_PORT_CFG		0x00400000
1691 
1692 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1693 	u32			hwrm_spec_code;
1694 	u16			hwrm_cmd_seq;
1695 	u16                     hwrm_cmd_kong_seq;
1696 	u16			hwrm_intr_seq_id;
1697 	void			*hwrm_short_cmd_req_addr;
1698 	dma_addr_t		hwrm_short_cmd_req_dma_addr;
1699 	void			*hwrm_cmd_resp_addr;
1700 	dma_addr_t		hwrm_cmd_resp_dma_addr;
1701 	void			*hwrm_cmd_kong_resp_addr;
1702 	dma_addr_t		hwrm_cmd_kong_resp_dma_addr;
1703 
1704 	struct rtnl_link_stats64	net_stats_prev;
1705 	struct rx_port_stats	*hw_rx_port_stats;
1706 	struct tx_port_stats	*hw_tx_port_stats;
1707 	struct rx_port_stats_ext	*hw_rx_port_stats_ext;
1708 	struct tx_port_stats_ext	*hw_tx_port_stats_ext;
1709 	struct pcie_ctx_hw_stats	*hw_pcie_stats;
1710 	dma_addr_t		hw_rx_port_stats_map;
1711 	dma_addr_t		hw_tx_port_stats_map;
1712 	dma_addr_t		hw_rx_port_stats_ext_map;
1713 	dma_addr_t		hw_tx_port_stats_ext_map;
1714 	dma_addr_t		hw_pcie_stats_map;
1715 	int			hw_port_stats_size;
1716 	u16			fw_rx_stats_ext_size;
1717 	u16			fw_tx_stats_ext_size;
1718 	u16			hw_ring_stats_size;
1719 	u8			pri2cos[8];
1720 	u8			pri2cos_valid;
1721 
1722 	u16			hwrm_max_req_len;
1723 	u16			hwrm_max_ext_req_len;
1724 	int			hwrm_cmd_timeout;
1725 	struct mutex		hwrm_cmd_lock;	/* serialize hwrm messages */
1726 	struct hwrm_ver_get_output	ver_resp;
1727 #define FW_VER_STR_LEN		32
1728 #define BC_HWRM_STR_LEN		21
1729 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1730 	char			fw_ver_str[FW_VER_STR_LEN];
1731 	__be16			vxlan_port;
1732 	u8			vxlan_port_cnt;
1733 	__le16			vxlan_fw_dst_port_id;
1734 	__be16			nge_port;
1735 	u8			nge_port_cnt;
1736 	__le16			nge_fw_dst_port_id;
1737 	u8			port_partition_type;
1738 	u8			port_count;
1739 	u16			br_mode;
1740 
1741 	struct bnxt_coal_cap	coal_cap;
1742 	struct bnxt_coal	rx_coal;
1743 	struct bnxt_coal	tx_coal;
1744 
1745 	u32			stats_coal_ticks;
1746 #define BNXT_DEF_STATS_COAL_TICKS	 1000000
1747 #define BNXT_MIN_STATS_COAL_TICKS	  250000
1748 #define BNXT_MAX_STATS_COAL_TICKS	 1000000
1749 
1750 	struct work_struct	sp_task;
1751 	unsigned long		sp_event;
1752 #define BNXT_RX_MASK_SP_EVENT		0
1753 #define BNXT_RX_NTP_FLTR_SP_EVENT	1
1754 #define BNXT_LINK_CHNG_SP_EVENT		2
1755 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	3
1756 #define BNXT_VXLAN_ADD_PORT_SP_EVENT	4
1757 #define BNXT_VXLAN_DEL_PORT_SP_EVENT	5
1758 #define BNXT_RESET_TASK_SP_EVENT	6
1759 #define BNXT_RST_RING_SP_EVENT		7
1760 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT	8
1761 #define BNXT_PERIODIC_STATS_SP_EVENT	9
1762 #define BNXT_HWRM_PORT_MODULE_SP_EVENT	10
1763 #define BNXT_RESET_TASK_SILENT_SP_EVENT	11
1764 #define BNXT_GENEVE_ADD_PORT_SP_EVENT	12
1765 #define BNXT_GENEVE_DEL_PORT_SP_EVENT	13
1766 #define BNXT_LINK_SPEED_CHNG_SP_EVENT	14
1767 #define BNXT_FLOW_STATS_SP_EVENT	15
1768 #define BNXT_UPDATE_PHY_SP_EVENT	16
1769 #define BNXT_RING_COAL_NOW_SP_EVENT	17
1770 #define BNXT_FW_RESET_NOTIFY_SP_EVENT	18
1771 #define BNXT_FW_EXCEPTION_SP_EVENT	19
1772 #define BNXT_LINK_CFG_CHANGE_SP_EVENT	21
1773 
1774 	struct delayed_work	fw_reset_task;
1775 	int			fw_reset_state;
1776 #define BNXT_FW_RESET_STATE_POLL_VF	1
1777 #define BNXT_FW_RESET_STATE_RESET_FW	2
1778 #define BNXT_FW_RESET_STATE_ENABLE_DEV	3
1779 #define BNXT_FW_RESET_STATE_POLL_FW	4
1780 #define BNXT_FW_RESET_STATE_OPENING	5
1781 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN	6
1782 
1783 	u16			fw_reset_min_dsecs;
1784 #define BNXT_DFLT_FW_RST_MIN_DSECS	20
1785 	u16			fw_reset_max_dsecs;
1786 #define BNXT_DFLT_FW_RST_MAX_DSECS	60
1787 	unsigned long		fw_reset_timestamp;
1788 
1789 	struct bnxt_fw_health	*fw_health;
1790 
1791 	struct bnxt_hw_resc	hw_resc;
1792 	struct bnxt_pf_info	pf;
1793 	struct bnxt_ctx_mem_info	*ctx;
1794 #ifdef CONFIG_BNXT_SRIOV
1795 	int			nr_vfs;
1796 	struct bnxt_vf_info	vf;
1797 	wait_queue_head_t	sriov_cfg_wait;
1798 	bool			sriov_cfg;
1799 #define BNXT_SRIOV_CFG_WAIT_TMO	msecs_to_jiffies(10000)
1800 
1801 	/* lock to protect VF-rep creation/cleanup via
1802 	 * multiple paths such as ->sriov_configure() and
1803 	 * devlink ->eswitch_mode_set()
1804 	 */
1805 	struct mutex		sriov_lock;
1806 #endif
1807 
1808 #if BITS_PER_LONG == 32
1809 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1810 	spinlock_t		db_lock;
1811 #endif
1812 
1813 #define BNXT_NTP_FLTR_MAX_FLTR	4096
1814 #define BNXT_NTP_FLTR_HASH_SIZE	512
1815 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
1816 	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1817 	spinlock_t		ntp_fltr_lock;	/* for hash table add, del */
1818 
1819 	unsigned long		*ntp_fltr_bmap;
1820 	int			ntp_fltr_count;
1821 
1822 	/* To protect link related settings during link changes and
1823 	 * ethtool settings changes.
1824 	 */
1825 	struct mutex		link_lock;
1826 	struct bnxt_link_info	link_info;
1827 	struct ethtool_eee	eee;
1828 	u32			lpi_tmr_lo;
1829 	u32			lpi_tmr_hi;
1830 
1831 	u8			num_tests;
1832 	struct bnxt_test_info	*test_info;
1833 
1834 	u8			wol_filter_id;
1835 	u8			wol;
1836 
1837 	u8			num_leds;
1838 	struct bnxt_led_info	leds[BNXT_MAX_LED];
1839 	u16			dump_flag;
1840 #define BNXT_DUMP_LIVE		0
1841 #define BNXT_DUMP_CRASH		1
1842 
1843 	struct bpf_prog		*xdp_prog;
1844 
1845 	/* devlink interface and vf-rep structs */
1846 	struct devlink		*dl;
1847 	struct devlink_port	dl_port;
1848 	enum devlink_eswitch_mode eswitch_mode;
1849 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
1850 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
1851 	u8			dsn[8];
1852 	struct bnxt_tc_info	*tc_info;
1853 	struct list_head	tc_indr_block_list;
1854 	struct notifier_block	tc_netdev_nb;
1855 	struct dentry		*debugfs_pdev;
1856 	struct device		*hwmon_dev;
1857 };
1858 
1859 #define BNXT_RX_STATS_OFFSET(counter)			\
1860 	(offsetof(struct rx_port_stats, counter) / 8)
1861 
1862 #define BNXT_TX_STATS_OFFSET(counter)			\
1863 	((offsetof(struct tx_port_stats, counter) +	\
1864 	  sizeof(struct rx_port_stats) + 512) / 8)
1865 
1866 #define BNXT_RX_STATS_EXT_OFFSET(counter)		\
1867 	(offsetof(struct rx_port_stats_ext, counter) / 8)
1868 
1869 #define BNXT_TX_STATS_EXT_OFFSET(counter)		\
1870 	(offsetof(struct tx_port_stats_ext, counter) / 8)
1871 
1872 #define BNXT_PCIE_STATS_OFFSET(counter)			\
1873 	(offsetof(struct pcie_ctx_hw_stats, counter) / 8)
1874 
1875 #define I2C_DEV_ADDR_A0				0xa0
1876 #define I2C_DEV_ADDR_A2				0xa2
1877 #define SFF_DIAG_SUPPORT_OFFSET			0x5c
1878 #define SFF_MODULE_ID_SFP			0x3
1879 #define SFF_MODULE_ID_QSFP			0xc
1880 #define SFF_MODULE_ID_QSFP_PLUS			0xd
1881 #define SFF_MODULE_ID_QSFP28			0x11
1882 #define BNXT_MAX_PHY_I2C_RESP_SIZE		64
1883 
1884 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1885 {
1886 	/* Tell compiler to fetch tx indices from memory. */
1887 	barrier();
1888 
1889 	return bp->tx_ring_size -
1890 		((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1891 }
1892 
1893 #if BITS_PER_LONG == 32
1894 #define writeq(val64, db)			\
1895 do {						\
1896 	spin_lock(&bp->db_lock);		\
1897 	writel((val64) & 0xffffffff, db);	\
1898 	writel((val64) >> 32, (db) + 4);	\
1899 	spin_unlock(&bp->db_lock);		\
1900 } while (0)
1901 
1902 #define writeq_relaxed writeq
1903 #endif
1904 
1905 /* For TX and RX ring doorbells with no ordering guarantee*/
1906 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1907 					 struct bnxt_db_info *db, u32 idx)
1908 {
1909 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
1910 		writeq_relaxed(db->db_key64 | idx, db->doorbell);
1911 	} else {
1912 		u32 db_val = db->db_key32 | idx;
1913 
1914 		writel_relaxed(db_val, db->doorbell);
1915 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1916 			writel_relaxed(db_val, db->doorbell);
1917 	}
1918 }
1919 
1920 /* For TX and RX ring doorbells */
1921 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1922 				 u32 idx)
1923 {
1924 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
1925 		writeq(db->db_key64 | idx, db->doorbell);
1926 	} else {
1927 		u32 db_val = db->db_key32 | idx;
1928 
1929 		writel(db_val, db->doorbell);
1930 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1931 			writel(db_val, db->doorbell);
1932 	}
1933 }
1934 
1935 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
1936 {
1937 	switch (req_type) {
1938 	case HWRM_CFA_ENCAP_RECORD_ALLOC:
1939 	case HWRM_CFA_ENCAP_RECORD_FREE:
1940 	case HWRM_CFA_DECAP_FILTER_ALLOC:
1941 	case HWRM_CFA_DECAP_FILTER_FREE:
1942 	case HWRM_CFA_EM_FLOW_ALLOC:
1943 	case HWRM_CFA_EM_FLOW_FREE:
1944 	case HWRM_CFA_EM_FLOW_CFG:
1945 	case HWRM_CFA_FLOW_ALLOC:
1946 	case HWRM_CFA_FLOW_FREE:
1947 	case HWRM_CFA_FLOW_INFO:
1948 	case HWRM_CFA_FLOW_FLUSH:
1949 	case HWRM_CFA_FLOW_STATS:
1950 	case HWRM_CFA_METER_PROFILE_ALLOC:
1951 	case HWRM_CFA_METER_PROFILE_FREE:
1952 	case HWRM_CFA_METER_PROFILE_CFG:
1953 	case HWRM_CFA_METER_INSTANCE_ALLOC:
1954 	case HWRM_CFA_METER_INSTANCE_FREE:
1955 		return true;
1956 	default:
1957 		return false;
1958 	}
1959 }
1960 
1961 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
1962 {
1963 	return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1964 		bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
1965 }
1966 
1967 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
1968 {
1969 	return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1970 		req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
1971 }
1972 
1973 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
1974 {
1975 	if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
1976 		return bp->hwrm_cmd_kong_resp_addr;
1977 	else
1978 		return bp->hwrm_cmd_resp_addr;
1979 }
1980 
1981 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
1982 {
1983 	u16 seq_id;
1984 
1985 	if (dst == BNXT_HWRM_CHNL_CHIMP)
1986 		seq_id = bp->hwrm_cmd_seq++;
1987 	else
1988 		seq_id = bp->hwrm_cmd_kong_seq++;
1989 	return seq_id;
1990 }
1991 
1992 extern const u16 bnxt_lhint_arr[];
1993 
1994 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1995 		       u16 prod, gfp_t gfp);
1996 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1997 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
1998 void bnxt_set_tpa_flags(struct bnxt *bp);
1999 void bnxt_set_ring_params(struct bnxt *);
2000 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2001 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
2002 int _hwrm_send_message(struct bnxt *, void *, u32, int);
2003 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
2004 int hwrm_send_message(struct bnxt *, void *, u32, int);
2005 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
2006 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2007 			    int bmap_size, bool async_only);
2008 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2009 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2010 int bnxt_nq_rings_in_use(struct bnxt *bp);
2011 int bnxt_hwrm_set_coal(struct bnxt *);
2012 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2013 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2014 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2015 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2016 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2017 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2018 void bnxt_tx_disable(struct bnxt *bp);
2019 void bnxt_tx_enable(struct bnxt *bp);
2020 int bnxt_hwrm_set_pause(struct bnxt *);
2021 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2022 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2023 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2024 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2025 int bnxt_hwrm_fw_set_time(struct bnxt *);
2026 int bnxt_open_nic(struct bnxt *, bool, bool);
2027 int bnxt_half_open_nic(struct bnxt *bp);
2028 void bnxt_half_close_nic(struct bnxt *bp);
2029 int bnxt_close_nic(struct bnxt *, bool, bool);
2030 void bnxt_fw_exception(struct bnxt *bp);
2031 void bnxt_fw_reset(struct bnxt *bp);
2032 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2033 		     int tx_xdp);
2034 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2035 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2036 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2037 int bnxt_get_port_parent_id(struct net_device *dev,
2038 			    struct netdev_phys_item_id *ppid);
2039 void bnxt_dim_work(struct work_struct *work);
2040 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2041 
2042 #endif
2043