1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_H 12 #define BNXT_H 13 14 #define DRV_MODULE_NAME "bnxt_en" 15 #define DRV_MODULE_VERSION "1.9.1" 16 17 #define DRV_VER_MAJ 1 18 #define DRV_VER_MIN 9 19 #define DRV_VER_UPD 1 20 21 #include <linux/interrupt.h> 22 #include <linux/rhashtable.h> 23 #include <net/devlink.h> 24 #include <net/dst_metadata.h> 25 #include <net/switchdev.h> 26 #include <net/xdp.h> 27 #include <linux/net_dim.h> 28 29 struct tx_bd { 30 __le32 tx_bd_len_flags_type; 31 #define TX_BD_TYPE (0x3f << 0) 32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 34 #define TX_BD_FLAGS_PACKET_END (1 << 6) 35 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 38 #define TX_BD_FLAGS_LHINT (3 << 13) 39 #define TX_BD_FLAGS_LHINT_SHIFT 13 40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 44 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 45 #define TX_BD_LEN (0xffff << 16) 46 #define TX_BD_LEN_SHIFT 16 47 48 u32 tx_bd_opaque; 49 __le64 tx_bd_haddr; 50 } __packed; 51 52 struct tx_bd_ext { 53 __le32 tx_bd_hsize_lflags; 54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) 55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1) 56 #define TX_BD_FLAGS_NO_CRC (1 << 2) 57 #define TX_BD_FLAGS_STAMP (1 << 3) 58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) 59 #define TX_BD_FLAGS_LSO (1 << 5) 60 #define TX_BD_FLAGS_IPID_FMT (1 << 6) 61 #define TX_BD_FLAGS_T_IPID (1 << 7) 62 #define TX_BD_HSIZE (0xff << 16) 63 #define TX_BD_HSIZE_SHIFT 16 64 65 __le32 tx_bd_mss; 66 __le32 tx_bd_cfa_action; 67 #define TX_BD_CFA_ACTION (0xffff << 16) 68 #define TX_BD_CFA_ACTION_SHIFT 16 69 70 __le32 tx_bd_cfa_meta; 71 #define TX_BD_CFA_META_MASK 0xfffffff 72 #define TX_BD_CFA_META_VID_MASK 0xfff 73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12) 74 #define TX_BD_CFA_META_PRI_SHIFT 12 75 #define TX_BD_CFA_META_TPID_MASK (3 << 16) 76 #define TX_BD_CFA_META_TPID_SHIFT 16 77 #define TX_BD_CFA_META_KEY (0xf << 28) 78 #define TX_BD_CFA_META_KEY_SHIFT 28 79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28) 80 }; 81 82 struct rx_bd { 83 __le32 rx_bd_len_flags_type; 84 #define RX_BD_TYPE (0x3f << 0) 85 #define RX_BD_TYPE_RX_PACKET_BD 0x4 86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 87 #define RX_BD_TYPE_RX_AGG_BD 0x6 88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 92 #define RX_BD_FLAGS_SOP (1 << 6) 93 #define RX_BD_FLAGS_EOP (1 << 7) 94 #define RX_BD_FLAGS_BUFFERS (3 << 8) 95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 99 #define RX_BD_LEN (0xffff << 16) 100 #define RX_BD_LEN_SHIFT 16 101 102 u32 rx_bd_opaque; 103 __le64 rx_bd_haddr; 104 }; 105 106 struct tx_cmp { 107 __le32 tx_cmp_flags_type; 108 #define CMP_TYPE (0x3f << 0) 109 #define CMP_TYPE_TX_L2_CMP 0 110 #define CMP_TYPE_RX_L2_CMP 17 111 #define CMP_TYPE_RX_AGG_CMP 18 112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 114 #define CMP_TYPE_STATUS_CMP 32 115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 117 #define CMP_TYPE_ERROR_STATUS 48 118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 123 124 #define TX_CMP_FLAGS_ERROR (1 << 6) 125 #define TX_CMP_FLAGS_PUSH (1 << 7) 126 127 u32 tx_cmp_opaque; 128 __le32 tx_cmp_errors_v; 129 #define TX_CMP_V (1 << 0) 130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 139 140 __le32 tx_cmp_unsed_3; 141 }; 142 143 struct rx_cmp { 144 __le32 rx_cmp_len_flags_type; 145 #define RX_CMP_CMP_TYPE (0x3f << 0) 146 #define RX_CMP_FLAGS_ERROR (1 << 6) 147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7) 148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10) 149 #define RX_CMP_FLAGS_UNUSED (1 << 11) 150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12 151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) 152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) 153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) 154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) 155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) 156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) 157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) 158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) 159 #define RX_CMP_LEN (0xffff << 16) 160 #define RX_CMP_LEN_SHIFT 16 161 162 u32 rx_cmp_opaque; 163 __le32 rx_cmp_misc_v1; 164 #define RX_CMP_V1 (1 << 0) 165 #define RX_CMP_AGG_BUFS (0x1f << 1) 166 #define RX_CMP_AGG_BUFS_SHIFT 1 167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) 168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) 170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 171 172 __le32 rx_cmp_rss_hash; 173 }; 174 175 #define RX_CMP_HASH_VALID(rxcmp) \ 176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) 177 178 #define RSS_PROFILE_ID_MASK 0x1f 179 180 #define RX_CMP_HASH_TYPE(rxcmp) \ 181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ 182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 183 184 struct rx_cmp_ext { 185 __le32 rx_cmp_flags2; 186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) 191 __le32 rx_cmp_meta_data; 192 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff 193 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff 194 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 195 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 196 __le32 rx_cmp_cfa_code_errors_v2; 197 #define RX_CMP_V (1 << 0) 198 #define RX_CMPL_ERRORS_MASK (0x7fff << 1) 199 #define RX_CMPL_ERRORS_SFT 1 200 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 201 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 202 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) 203 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 204 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 205 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) 206 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) 207 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) 208 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) 209 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) 210 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) 211 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) 212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) 213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) 214 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) 215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) 216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) 217 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) 218 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) 219 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) 220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) 221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) 222 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) 223 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) 224 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) 225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) 226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) 227 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) 228 229 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) 230 #define RX_CMPL_CFA_CODE_SFT 16 231 232 __le32 rx_cmp_unused3; 233 }; 234 235 #define RX_CMP_L2_ERRORS \ 236 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) 237 238 #define RX_CMP_L4_CS_BITS \ 239 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) 240 241 #define RX_CMP_L4_CS_ERR_BITS \ 242 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) 243 244 #define RX_CMP_L4_CS_OK(rxcmp1) \ 245 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ 246 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) 247 248 #define RX_CMP_ENCAP(rxcmp1) \ 249 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ 250 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) 251 252 #define RX_CMP_CFA_CODE(rxcmpl1) \ 253 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ 254 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) 255 256 struct rx_agg_cmp { 257 __le32 rx_agg_cmp_len_flags_type; 258 #define RX_AGG_CMP_TYPE (0x3f << 0) 259 #define RX_AGG_CMP_LEN (0xffff << 16) 260 #define RX_AGG_CMP_LEN_SHIFT 16 261 u32 rx_agg_cmp_opaque; 262 __le32 rx_agg_cmp_v; 263 #define RX_AGG_CMP_V (1 << 0) 264 __le32 rx_agg_cmp_unused; 265 }; 266 267 struct rx_tpa_start_cmp { 268 __le32 rx_tpa_start_cmp_len_flags_type; 269 #define RX_TPA_START_CMP_TYPE (0x3f << 0) 270 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) 271 #define RX_TPA_START_CMP_FLAGS_SHIFT 6 272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) 273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 277 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 278 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) 279 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) 280 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 281 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 282 #define RX_TPA_START_CMP_LEN (0xffff << 16) 283 #define RX_TPA_START_CMP_LEN_SHIFT 16 284 285 u32 rx_tpa_start_cmp_opaque; 286 __le32 rx_tpa_start_cmp_misc_v1; 287 #define RX_TPA_START_CMP_V1 (0x1 << 0) 288 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) 289 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 290 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) 291 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 292 293 __le32 rx_tpa_start_cmp_rss_hash; 294 }; 295 296 #define TPA_START_HASH_VALID(rx_tpa_start) \ 297 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 298 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) 299 300 #define TPA_START_HASH_TYPE(rx_tpa_start) \ 301 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 302 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ 303 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 304 305 #define TPA_START_AGG_ID(rx_tpa_start) \ 306 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 307 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) 308 309 struct rx_tpa_start_cmp_ext { 310 __le32 rx_tpa_start_cmp_flags2; 311 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) 312 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 313 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 314 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 315 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) 316 317 __le32 rx_tpa_start_cmp_metadata; 318 __le32 rx_tpa_start_cmp_cfa_code_v2; 319 #define RX_TPA_START_CMP_V2 (0x1 << 0) 320 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) 321 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 322 __le32 rx_tpa_start_cmp_hdr_info; 323 }; 324 325 #define TPA_START_CFA_CODE(rx_tpa_start) \ 326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) 328 329 struct rx_tpa_end_cmp { 330 __le32 rx_tpa_end_cmp_len_flags_type; 331 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 332 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) 333 #define RX_TPA_END_CMP_FLAGS_SHIFT 6 334 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) 335 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 336 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 337 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 339 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 340 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) 341 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) 342 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 343 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 344 #define RX_TPA_END_CMP_LEN (0xffff << 16) 345 #define RX_TPA_END_CMP_LEN_SHIFT 16 346 347 u32 rx_tpa_end_cmp_opaque; 348 __le32 rx_tpa_end_cmp_misc_v1; 349 #define RX_TPA_END_CMP_V1 (0x1 << 0) 350 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) 351 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 352 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) 353 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 354 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) 355 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 356 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) 357 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 358 359 __le32 rx_tpa_end_cmp_tsdelta; 360 #define RX_TPA_END_GRO_TS (0x1 << 31) 361 }; 362 363 #define TPA_END_AGG_ID(rx_tpa_end) \ 364 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 365 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) 366 367 #define TPA_END_TPA_SEGS(rx_tpa_end) \ 368 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 369 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) 370 371 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ 372 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ 373 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) 374 375 #define TPA_END_GRO(rx_tpa_end) \ 376 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ 377 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) 378 379 #define TPA_END_GRO_TS(rx_tpa_end) \ 380 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ 381 cpu_to_le32(RX_TPA_END_GRO_TS))) 382 383 struct rx_tpa_end_cmp_ext { 384 __le32 rx_tpa_end_cmp_dup_acks; 385 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) 386 387 __le32 rx_tpa_end_cmp_seg_len; 388 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) 389 390 __le32 rx_tpa_end_cmp_errors_v2; 391 #define RX_TPA_END_CMP_V2 (0x1 << 0) 392 #define RX_TPA_END_CMP_ERRORS (0x3 << 1) 393 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 394 395 u32 rx_tpa_end_cmp_start_opaque; 396 }; 397 398 #define TPA_END_ERRORS(rx_tpa_end_ext) \ 399 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ 400 cpu_to_le32(RX_TPA_END_CMP_ERRORS)) 401 402 #define DB_IDX_MASK 0xffffff 403 #define DB_IDX_VALID (0x1 << 26) 404 #define DB_IRQ_DIS (0x1 << 27) 405 #define DB_KEY_TX (0x0 << 28) 406 #define DB_KEY_RX (0x1 << 28) 407 #define DB_KEY_CP (0x2 << 28) 408 #define DB_KEY_ST (0x3 << 28) 409 #define DB_KEY_TX_PUSH (0x4 << 28) 410 #define DB_LONG_TX_PUSH (0x2 << 24) 411 412 #define BNXT_MIN_ROCE_CP_RINGS 2 413 #define BNXT_MIN_ROCE_STAT_CTXS 1 414 415 #define INVALID_HW_RING_ID ((u16)-1) 416 417 /* The hardware supports certain page sizes. Use the supported page sizes 418 * to allocate the rings. 419 */ 420 #if (PAGE_SHIFT < 12) 421 #define BNXT_PAGE_SHIFT 12 422 #elif (PAGE_SHIFT <= 13) 423 #define BNXT_PAGE_SHIFT PAGE_SHIFT 424 #elif (PAGE_SHIFT < 16) 425 #define BNXT_PAGE_SHIFT 13 426 #else 427 #define BNXT_PAGE_SHIFT 16 428 #endif 429 430 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 431 432 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 433 #if (PAGE_SHIFT > 15) 434 #define BNXT_RX_PAGE_SHIFT 15 435 #else 436 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT 437 #endif 438 439 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) 440 441 #define BNXT_MAX_MTU 9500 442 #define BNXT_MAX_PAGE_MODE_MTU \ 443 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ 444 XDP_PACKET_HEADROOM) 445 446 #define BNXT_MIN_PKT_SIZE 52 447 448 #define BNXT_DEFAULT_RX_RING_SIZE 511 449 #define BNXT_DEFAULT_TX_RING_SIZE 511 450 451 #define MAX_TPA 64 452 453 #if (BNXT_PAGE_SHIFT == 16) 454 #define MAX_RX_PAGES 1 455 #define MAX_RX_AGG_PAGES 4 456 #define MAX_TX_PAGES 1 457 #define MAX_CP_PAGES 8 458 #else 459 #define MAX_RX_PAGES 8 460 #define MAX_RX_AGG_PAGES 32 461 #define MAX_TX_PAGES 8 462 #define MAX_CP_PAGES 64 463 #endif 464 465 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) 466 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) 467 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) 468 469 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) 470 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 471 472 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) 473 474 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) 475 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 476 477 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 478 479 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 480 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 481 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 482 483 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 484 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 485 486 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 487 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 488 489 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 490 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 491 492 #define TX_CMP_VALID(txcmp, raw_cons) \ 493 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ 494 !((raw_cons) & bp->cp_bit)) 495 496 #define RX_CMP_VALID(rxcmp1, raw_cons) \ 497 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ 498 !((raw_cons) & bp->cp_bit)) 499 500 #define RX_AGG_CMP_VALID(agg, raw_cons) \ 501 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ 502 !((raw_cons) & bp->cp_bit)) 503 504 #define TX_CMP_TYPE(txcmp) \ 505 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) 506 507 #define RX_CMP_TYPE(rxcmp) \ 508 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) 509 510 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) 511 512 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) 513 514 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) 515 516 #define ADV_RAW_CMP(idx, n) ((idx) + (n)) 517 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) 518 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) 519 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) 520 521 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) 522 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 523 #define DFLT_HWRM_CMD_TIMEOUT 500 524 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) 525 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) 526 #define HWRM_RESP_ERR_CODE_MASK 0xffff 527 #define HWRM_RESP_LEN_OFFSET 4 528 #define HWRM_RESP_LEN_MASK 0xffff0000 529 #define HWRM_RESP_LEN_SFT 16 530 #define HWRM_RESP_VALID_MASK 0xff000000 531 #define HWRM_SEQ_ID_INVALID -1 532 #define BNXT_HWRM_REQ_MAX_SIZE 128 533 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ 534 BNXT_HWRM_REQ_MAX_SIZE) 535 536 #define BNXT_RX_EVENT 1 537 #define BNXT_AGG_EVENT 2 538 #define BNXT_TX_EVENT 4 539 540 struct bnxt_sw_tx_bd { 541 struct sk_buff *skb; 542 DEFINE_DMA_UNMAP_ADDR(mapping); 543 u8 is_gso; 544 u8 is_push; 545 union { 546 unsigned short nr_frags; 547 u16 rx_prod; 548 }; 549 }; 550 551 struct bnxt_sw_rx_bd { 552 void *data; 553 u8 *data_ptr; 554 dma_addr_t mapping; 555 }; 556 557 struct bnxt_sw_rx_agg_bd { 558 struct page *page; 559 unsigned int offset; 560 dma_addr_t mapping; 561 }; 562 563 struct bnxt_ring_struct { 564 int nr_pages; 565 int page_size; 566 void **pg_arr; 567 dma_addr_t *dma_arr; 568 569 __le64 *pg_tbl; 570 dma_addr_t pg_tbl_map; 571 572 int vmem_size; 573 void **vmem; 574 575 u16 fw_ring_id; /* Ring id filled by Chimp FW */ 576 union { 577 u16 grp_idx; 578 u16 map_idx; /* Used by cmpl rings */ 579 }; 580 u8 queue_id; 581 }; 582 583 struct tx_push_bd { 584 __le32 doorbell; 585 __le32 tx_bd_len_flags_type; 586 u32 tx_bd_opaque; 587 struct tx_bd_ext txbd2; 588 }; 589 590 struct tx_push_buffer { 591 struct tx_push_bd push_bd; 592 u32 data[25]; 593 }; 594 595 struct bnxt_tx_ring_info { 596 struct bnxt_napi *bnapi; 597 u16 tx_prod; 598 u16 tx_cons; 599 u16 txq_index; 600 void __iomem *tx_doorbell; 601 602 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 603 struct bnxt_sw_tx_bd *tx_buf_ring; 604 605 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 606 607 struct tx_push_buffer *tx_push; 608 dma_addr_t tx_push_mapping; 609 __le64 data_mapping; 610 611 #define BNXT_DEV_STATE_CLOSING 0x1 612 u32 dev_state; 613 614 struct bnxt_ring_struct tx_ring_struct; 615 }; 616 617 struct bnxt_coal { 618 u16 coal_ticks; 619 u16 coal_ticks_irq; 620 u16 coal_bufs; 621 u16 coal_bufs_irq; 622 /* RING_IDLE enabled when coal ticks < idle_thresh */ 623 u16 idle_thresh; 624 u8 bufs_per_record; 625 u8 budget; 626 }; 627 628 struct bnxt_tpa_info { 629 void *data; 630 u8 *data_ptr; 631 dma_addr_t mapping; 632 u16 len; 633 unsigned short gso_type; 634 u32 flags2; 635 u32 metadata; 636 enum pkt_hash_types hash_type; 637 u32 rss_hash; 638 u32 hdr_info; 639 640 #define BNXT_TPA_L4_SIZE(hdr_info) \ 641 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) 642 643 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ 644 (((hdr_info) >> 18) & 0x1ff) 645 646 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ 647 (((hdr_info) >> 9) & 0x1ff) 648 649 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ 650 ((hdr_info) & 0x1ff) 651 652 u16 cfa_code; /* cfa_code in TPA start compl */ 653 }; 654 655 struct bnxt_rx_ring_info { 656 struct bnxt_napi *bnapi; 657 u16 rx_prod; 658 u16 rx_agg_prod; 659 u16 rx_sw_agg_prod; 660 u16 rx_next_cons; 661 void __iomem *rx_doorbell; 662 void __iomem *rx_agg_doorbell; 663 664 struct bpf_prog *xdp_prog; 665 666 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 667 struct bnxt_sw_rx_bd *rx_buf_ring; 668 669 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 670 struct bnxt_sw_rx_agg_bd *rx_agg_ring; 671 672 unsigned long *rx_agg_bmap; 673 u16 rx_agg_bmap_size; 674 675 struct page *rx_page; 676 unsigned int rx_page_offset; 677 678 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 679 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 680 681 struct bnxt_tpa_info *rx_tpa; 682 683 struct bnxt_ring_struct rx_ring_struct; 684 struct bnxt_ring_struct rx_agg_ring_struct; 685 struct xdp_rxq_info xdp_rxq; 686 }; 687 688 struct bnxt_cp_ring_info { 689 u32 cp_raw_cons; 690 void __iomem *cp_doorbell; 691 692 struct bnxt_coal rx_ring_coal; 693 u64 rx_packets; 694 u64 rx_bytes; 695 u64 event_ctr; 696 697 struct net_dim dim; 698 699 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; 700 701 dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; 702 703 struct ctx_hw_stats *hw_stats; 704 dma_addr_t hw_stats_map; 705 u32 hw_stats_ctx_id; 706 u64 rx_l4_csum_errors; 707 708 struct bnxt_ring_struct cp_ring_struct; 709 }; 710 711 struct bnxt_napi { 712 struct napi_struct napi; 713 struct bnxt *bp; 714 715 int index; 716 struct bnxt_cp_ring_info cp_ring; 717 struct bnxt_rx_ring_info *rx_ring; 718 struct bnxt_tx_ring_info *tx_ring; 719 720 void (*tx_int)(struct bnxt *, struct bnxt_napi *, 721 int); 722 u32 flags; 723 #define BNXT_NAPI_FLAG_XDP 0x1 724 725 bool in_reset; 726 }; 727 728 struct bnxt_irq { 729 irq_handler_t handler; 730 unsigned int vector; 731 u8 requested:1; 732 u8 have_cpumask:1; 733 char name[IFNAMSIZ + 2]; 734 cpumask_var_t cpu_mask; 735 }; 736 737 #define HWRM_RING_ALLOC_TX 0x1 738 #define HWRM_RING_ALLOC_RX 0x2 739 #define HWRM_RING_ALLOC_AGG 0x4 740 #define HWRM_RING_ALLOC_CMPL 0x8 741 742 #define INVALID_STATS_CTX_ID -1 743 744 struct bnxt_ring_grp_info { 745 u16 fw_stats_ctx; 746 u16 fw_grp_id; 747 u16 rx_fw_ring_id; 748 u16 agg_fw_ring_id; 749 u16 cp_fw_ring_id; 750 }; 751 752 struct bnxt_vnic_info { 753 u16 fw_vnic_id; /* returned by Chimp during alloc */ 754 #define BNXT_MAX_CTX_PER_VNIC 2 755 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 756 u16 fw_l2_ctx_id; 757 #define BNXT_MAX_UC_ADDRS 4 758 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; 759 /* index 0 always dev_addr */ 760 u16 uc_filter_count; 761 u8 *uc_list; 762 763 u16 *fw_grp_ids; 764 dma_addr_t rss_table_dma_addr; 765 __le16 *rss_table; 766 dma_addr_t rss_hash_key_dma_addr; 767 u64 *rss_hash_key; 768 u32 rx_mask; 769 770 u8 *mc_list; 771 int mc_list_size; 772 int mc_list_count; 773 dma_addr_t mc_list_mapping; 774 #define BNXT_MAX_MC_ADDRS 16 775 776 u32 flags; 777 #define BNXT_VNIC_RSS_FLAG 1 778 #define BNXT_VNIC_RFS_FLAG 2 779 #define BNXT_VNIC_MCAST_FLAG 4 780 #define BNXT_VNIC_UCAST_FLAG 8 781 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 782 }; 783 784 struct bnxt_hw_resc { 785 u16 min_rsscos_ctxs; 786 u16 max_rsscos_ctxs; 787 u16 min_cp_rings; 788 u16 max_cp_rings; 789 u16 resv_cp_rings; 790 u16 min_tx_rings; 791 u16 max_tx_rings; 792 u16 resv_tx_rings; 793 u16 max_tx_sch_inputs; 794 u16 min_rx_rings; 795 u16 max_rx_rings; 796 u16 resv_rx_rings; 797 u16 min_hw_ring_grps; 798 u16 max_hw_ring_grps; 799 u16 resv_hw_ring_grps; 800 u16 min_l2_ctxs; 801 u16 max_l2_ctxs; 802 u16 min_vnics; 803 u16 max_vnics; 804 u16 resv_vnics; 805 u16 min_stat_ctxs; 806 u16 max_stat_ctxs; 807 u16 max_irqs; 808 }; 809 810 #if defined(CONFIG_BNXT_SRIOV) 811 struct bnxt_vf_info { 812 u16 fw_fid; 813 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ 814 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only 815 * stored by PF. 816 */ 817 u16 vlan; 818 u32 flags; 819 #define BNXT_VF_QOS 0x1 820 #define BNXT_VF_SPOOFCHK 0x2 821 #define BNXT_VF_LINK_FORCED 0x4 822 #define BNXT_VF_LINK_UP 0x8 823 #define BNXT_VF_TRUST 0x10 824 u32 func_flags; /* func cfg flags */ 825 u32 min_tx_rate; 826 u32 max_tx_rate; 827 void *hwrm_cmd_req_addr; 828 dma_addr_t hwrm_cmd_req_dma_addr; 829 }; 830 #endif 831 832 struct bnxt_pf_info { 833 #define BNXT_FIRST_PF_FID 1 834 #define BNXT_FIRST_VF_FID 128 835 u16 fw_fid; 836 u16 port_id; 837 u8 mac_addr[ETH_ALEN]; 838 u32 first_vf_id; 839 u16 active_vfs; 840 u16 max_vfs; 841 u32 max_encap_records; 842 u32 max_decap_records; 843 u32 max_tx_em_flows; 844 u32 max_tx_wm_flows; 845 u32 max_rx_em_flows; 846 u32 max_rx_wm_flows; 847 unsigned long *vf_event_bmap; 848 u16 hwrm_cmd_req_pages; 849 u8 vf_resv_strategy; 850 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 851 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 852 void *hwrm_cmd_req_addr[4]; 853 dma_addr_t hwrm_cmd_req_dma_addr[4]; 854 struct bnxt_vf_info *vf; 855 }; 856 857 struct bnxt_ntuple_filter { 858 struct hlist_node hash; 859 u8 dst_mac_addr[ETH_ALEN]; 860 u8 src_mac_addr[ETH_ALEN]; 861 struct flow_keys fkeys; 862 __le64 filter_id; 863 u16 sw_id; 864 u8 l2_fltr_idx; 865 u16 rxq; 866 u32 flow_id; 867 unsigned long state; 868 #define BNXT_FLTR_VALID 0 869 #define BNXT_FLTR_UPDATE 1 870 }; 871 872 struct bnxt_link_info { 873 u8 phy_type; 874 u8 media_type; 875 u8 transceiver; 876 u8 phy_addr; 877 u8 phy_link_status; 878 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK 879 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL 880 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 881 u8 wire_speed; 882 u8 loop_back; 883 u8 link_up; 884 u8 duplex; 885 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 886 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 887 u8 pause; 888 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 889 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 890 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 891 PORT_PHY_QCFG_RESP_PAUSE_TX) 892 u8 lp_pause; 893 u8 auto_pause_setting; 894 u8 force_pause_setting; 895 u8 duplex_setting; 896 u8 auto_mode; 897 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ 898 (mode) <= BNXT_LINK_AUTO_MSK) 899 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 900 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 901 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 902 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 903 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 904 #define PHY_VER_LEN 3 905 u8 phy_ver[PHY_VER_LEN]; 906 u16 link_speed; 907 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 908 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 909 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 910 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 911 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 912 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 913 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 914 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 915 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 916 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 917 u16 support_speeds; 918 u16 auto_link_speeds; /* fw adv setting */ 919 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 920 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 921 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 922 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 923 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 924 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 925 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 926 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 927 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 928 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 929 u16 support_auto_speeds; 930 u16 lp_auto_link_speeds; 931 u16 force_link_speed; 932 u32 preemphasis; 933 u8 module_status; 934 u16 fec_cfg; 935 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 936 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 937 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 938 939 /* copy of requested setting from ethtool cmd */ 940 u8 autoneg; 941 #define BNXT_AUTONEG_SPEED 1 942 #define BNXT_AUTONEG_FLOW_CTRL 2 943 u8 req_duplex; 944 u8 req_flow_ctrl; 945 u16 req_link_speed; 946 u16 advertising; /* user adv setting */ 947 bool force_link_chng; 948 949 /* a copy of phy_qcfg output used to report link 950 * info to VF 951 */ 952 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 953 }; 954 955 #define BNXT_MAX_QUEUE 8 956 957 struct bnxt_queue_info { 958 u8 queue_id; 959 u8 queue_profile; 960 }; 961 962 #define BNXT_MAX_LED 4 963 964 struct bnxt_led_info { 965 u8 led_id; 966 u8 led_type; 967 u8 led_group_id; 968 u8 unused; 969 __le16 led_state_caps; 970 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 971 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) 972 973 __le16 led_color_caps; 974 }; 975 976 #define BNXT_MAX_TEST 8 977 978 struct bnxt_test_info { 979 u8 offline_mask; 980 u16 timeout; 981 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; 982 }; 983 984 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 985 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 986 #define BNXT_CAG_REG_BASE 0x300000 987 988 struct bnxt_tc_flow_stats { 989 u64 packets; 990 u64 bytes; 991 }; 992 993 struct bnxt_tc_info { 994 bool enabled; 995 996 /* hash table to store TC offloaded flows */ 997 struct rhashtable flow_table; 998 struct rhashtable_params flow_ht_params; 999 1000 /* hash table to store L2 keys of TC flows */ 1001 struct rhashtable l2_table; 1002 struct rhashtable_params l2_ht_params; 1003 /* hash table to store L2 keys for TC tunnel decap */ 1004 struct rhashtable decap_l2_table; 1005 struct rhashtable_params decap_l2_ht_params; 1006 /* hash table to store tunnel decap entries */ 1007 struct rhashtable decap_table; 1008 struct rhashtable_params decap_ht_params; 1009 /* hash table to store tunnel encap entries */ 1010 struct rhashtable encap_table; 1011 struct rhashtable_params encap_ht_params; 1012 1013 /* lock to atomically add/del an l2 node when a flow is 1014 * added or deleted. 1015 */ 1016 struct mutex lock; 1017 1018 /* Fields used for batching stats query */ 1019 struct rhashtable_iter iter; 1020 #define BNXT_FLOW_STATS_BATCH_MAX 10 1021 struct bnxt_tc_stats_batch { 1022 void *flow_node; 1023 struct bnxt_tc_flow_stats hw_stats; 1024 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; 1025 1026 /* Stat counter mask (width) */ 1027 u64 bytes_mask; 1028 u64 packets_mask; 1029 }; 1030 1031 struct bnxt_vf_rep_stats { 1032 u64 packets; 1033 u64 bytes; 1034 u64 dropped; 1035 }; 1036 1037 struct bnxt_vf_rep { 1038 struct bnxt *bp; 1039 struct net_device *dev; 1040 struct metadata_dst *dst; 1041 u16 vf_idx; 1042 u16 tx_cfa_action; 1043 u16 rx_cfa_code; 1044 1045 struct bnxt_vf_rep_stats rx_stats; 1046 struct bnxt_vf_rep_stats tx_stats; 1047 }; 1048 1049 struct bnxt { 1050 void __iomem *bar0; 1051 void __iomem *bar1; 1052 void __iomem *bar2; 1053 1054 u32 reg_base; 1055 u16 chip_num; 1056 #define CHIP_NUM_57301 0x16c8 1057 #define CHIP_NUM_57302 0x16c9 1058 #define CHIP_NUM_57304 0x16ca 1059 #define CHIP_NUM_58700 0x16cd 1060 #define CHIP_NUM_57402 0x16d0 1061 #define CHIP_NUM_57404 0x16d1 1062 #define CHIP_NUM_57406 0x16d2 1063 #define CHIP_NUM_57407 0x16d5 1064 1065 #define CHIP_NUM_57311 0x16ce 1066 #define CHIP_NUM_57312 0x16cf 1067 #define CHIP_NUM_57314 0x16df 1068 #define CHIP_NUM_57317 0x16e0 1069 #define CHIP_NUM_57412 0x16d6 1070 #define CHIP_NUM_57414 0x16d7 1071 #define CHIP_NUM_57416 0x16d8 1072 #define CHIP_NUM_57417 0x16d9 1073 #define CHIP_NUM_57412L 0x16da 1074 #define CHIP_NUM_57414L 0x16db 1075 1076 #define CHIP_NUM_5745X 0xd730 1077 1078 #define CHIP_NUM_58802 0xd802 1079 #define CHIP_NUM_58804 0xd804 1080 #define CHIP_NUM_58808 0xd808 1081 1082 #define BNXT_CHIP_NUM_5730X(chip_num) \ 1083 ((chip_num) >= CHIP_NUM_57301 && \ 1084 (chip_num) <= CHIP_NUM_57304) 1085 1086 #define BNXT_CHIP_NUM_5740X(chip_num) \ 1087 (((chip_num) >= CHIP_NUM_57402 && \ 1088 (chip_num) <= CHIP_NUM_57406) || \ 1089 (chip_num) == CHIP_NUM_57407) 1090 1091 #define BNXT_CHIP_NUM_5731X(chip_num) \ 1092 ((chip_num) == CHIP_NUM_57311 || \ 1093 (chip_num) == CHIP_NUM_57312 || \ 1094 (chip_num) == CHIP_NUM_57314 || \ 1095 (chip_num) == CHIP_NUM_57317) 1096 1097 #define BNXT_CHIP_NUM_5741X(chip_num) \ 1098 ((chip_num) >= CHIP_NUM_57412 && \ 1099 (chip_num) <= CHIP_NUM_57414L) 1100 1101 #define BNXT_CHIP_NUM_58700(chip_num) \ 1102 ((chip_num) == CHIP_NUM_58700) 1103 1104 #define BNXT_CHIP_NUM_5745X(chip_num) \ 1105 ((chip_num) == CHIP_NUM_5745X) 1106 1107 #define BNXT_CHIP_NUM_57X0X(chip_num) \ 1108 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) 1109 1110 #define BNXT_CHIP_NUM_57X1X(chip_num) \ 1111 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) 1112 1113 #define BNXT_CHIP_NUM_588XX(chip_num) \ 1114 ((chip_num) == CHIP_NUM_58802 || \ 1115 (chip_num) == CHIP_NUM_58804 || \ 1116 (chip_num) == CHIP_NUM_58808) 1117 1118 struct net_device *dev; 1119 struct pci_dev *pdev; 1120 1121 atomic_t intr_sem; 1122 1123 u32 flags; 1124 #define BNXT_FLAG_DCB_ENABLED 0x1 1125 #define BNXT_FLAG_VF 0x2 1126 #define BNXT_FLAG_LRO 0x4 1127 #ifdef CONFIG_INET 1128 #define BNXT_FLAG_GRO 0x8 1129 #else 1130 /* Cannot support hardware GRO if CONFIG_INET is not set */ 1131 #define BNXT_FLAG_GRO 0x0 1132 #endif 1133 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) 1134 #define BNXT_FLAG_JUMBO 0x10 1135 #define BNXT_FLAG_STRIP_VLAN 0x20 1136 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ 1137 BNXT_FLAG_LRO) 1138 #define BNXT_FLAG_USING_MSIX 0x40 1139 #define BNXT_FLAG_MSIX_CAP 0x80 1140 #define BNXT_FLAG_RFS 0x100 1141 #define BNXT_FLAG_SHARED_RINGS 0x200 1142 #define BNXT_FLAG_PORT_STATS 0x400 1143 #define BNXT_FLAG_UDP_RSS_CAP 0x800 1144 #define BNXT_FLAG_EEE_CAP 0x1000 1145 #define BNXT_FLAG_NEW_RSS_CAP 0x2000 1146 #define BNXT_FLAG_WOL_CAP 0x4000 1147 #define BNXT_FLAG_ROCEV1_CAP 0x8000 1148 #define BNXT_FLAG_ROCEV2_CAP 0x10000 1149 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ 1150 BNXT_FLAG_ROCEV2_CAP) 1151 #define BNXT_FLAG_NO_AGG_RINGS 0x20000 1152 #define BNXT_FLAG_RX_PAGE_MODE 0x40000 1153 #define BNXT_FLAG_FW_LLDP_AGENT 0x80000 1154 #define BNXT_FLAG_MULTI_HOST 0x100000 1155 #define BNXT_FLAG_SHORT_CMD 0x200000 1156 #define BNXT_FLAG_DOUBLE_DB 0x400000 1157 #define BNXT_FLAG_FW_DCBX_AGENT 0x800000 1158 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 1159 #define BNXT_FLAG_DIM 0x2000000 1160 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 1161 #define BNXT_FLAG_NEW_RM 0x8000000 1162 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 1163 1164 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 1165 BNXT_FLAG_RFS | \ 1166 BNXT_FLAG_STRIP_VLAN) 1167 1168 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 1169 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 1170 #define BNXT_NPAR(bp) ((bp)->port_partition_type) 1171 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 1172 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 1173 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) 1174 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) 1175 1176 /* Chip class phase 4 and later */ 1177 #define BNXT_CHIP_P4_PLUS(bp) \ 1178 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ 1179 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ 1180 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ 1181 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ 1182 !BNXT_CHIP_TYPE_NITRO_A0(bp))) 1183 1184 struct bnxt_en_dev *edev; 1185 struct bnxt_en_dev * (*ulp_probe)(struct net_device *); 1186 1187 struct bnxt_napi **bnapi; 1188 1189 struct bnxt_rx_ring_info *rx_ring; 1190 struct bnxt_tx_ring_info *tx_ring; 1191 u16 *tx_ring_map; 1192 1193 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, 1194 struct sk_buff *); 1195 1196 struct sk_buff * (*rx_skb_func)(struct bnxt *, 1197 struct bnxt_rx_ring_info *, 1198 u16, void *, u8 *, dma_addr_t, 1199 unsigned int); 1200 1201 u32 rx_buf_size; 1202 u32 rx_buf_use_size; /* useable size */ 1203 u16 rx_offset; 1204 u16 rx_dma_offset; 1205 enum dma_data_direction rx_dir; 1206 u32 rx_ring_size; 1207 u32 rx_agg_ring_size; 1208 u32 rx_copy_thresh; 1209 u32 rx_ring_mask; 1210 u32 rx_agg_ring_mask; 1211 int rx_nr_pages; 1212 int rx_agg_nr_pages; 1213 int rx_nr_rings; 1214 int rsscos_nr_ctxs; 1215 1216 u32 tx_ring_size; 1217 u32 tx_ring_mask; 1218 int tx_nr_pages; 1219 int tx_nr_rings; 1220 int tx_nr_rings_per_tc; 1221 int tx_nr_rings_xdp; 1222 1223 int tx_wake_thresh; 1224 int tx_push_thresh; 1225 int tx_push_size; 1226 1227 u32 cp_ring_size; 1228 u32 cp_ring_mask; 1229 u32 cp_bit; 1230 int cp_nr_pages; 1231 int cp_nr_rings; 1232 1233 int num_stat_ctxs; 1234 1235 /* grp_info indexed by completion ring index */ 1236 struct bnxt_ring_grp_info *grp_info; 1237 struct bnxt_vnic_info *vnic_info; 1238 int nr_vnics; 1239 u32 rss_hash_cfg; 1240 1241 u16 max_mtu; 1242 u8 max_tc; 1243 u8 max_lltc; /* lossless TCs */ 1244 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; 1245 1246 unsigned int current_interval; 1247 #define BNXT_TIMER_INTERVAL HZ 1248 1249 struct timer_list timer; 1250 1251 unsigned long state; 1252 #define BNXT_STATE_OPEN 0 1253 #define BNXT_STATE_IN_SP_TASK 1 1254 #define BNXT_STATE_READ_STATS 2 1255 1256 struct bnxt_irq *irq_tbl; 1257 int total_irqs; 1258 u8 mac_addr[ETH_ALEN]; 1259 1260 #ifdef CONFIG_BNXT_DCB 1261 struct ieee_pfc *ieee_pfc; 1262 struct ieee_ets *ieee_ets; 1263 u8 dcbx_cap; 1264 u8 default_pri; 1265 #endif /* CONFIG_BNXT_DCB */ 1266 1267 u32 msg_enable; 1268 1269 u32 hwrm_spec_code; 1270 u16 hwrm_cmd_seq; 1271 u32 hwrm_intr_seq_id; 1272 void *hwrm_short_cmd_req_addr; 1273 dma_addr_t hwrm_short_cmd_req_dma_addr; 1274 void *hwrm_cmd_resp_addr; 1275 dma_addr_t hwrm_cmd_resp_dma_addr; 1276 void *hwrm_dbg_resp_addr; 1277 dma_addr_t hwrm_dbg_resp_dma_addr; 1278 #define HWRM_DBG_REG_BUF_SIZE 128 1279 1280 struct rx_port_stats *hw_rx_port_stats; 1281 struct tx_port_stats *hw_tx_port_stats; 1282 struct rx_port_stats_ext *hw_rx_port_stats_ext; 1283 dma_addr_t hw_rx_port_stats_map; 1284 dma_addr_t hw_tx_port_stats_map; 1285 dma_addr_t hw_rx_port_stats_ext_map; 1286 int hw_port_stats_size; 1287 1288 u16 hwrm_max_req_len; 1289 int hwrm_cmd_timeout; 1290 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 1291 struct hwrm_ver_get_output ver_resp; 1292 #define FW_VER_STR_LEN 32 1293 #define BC_HWRM_STR_LEN 21 1294 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) 1295 char fw_ver_str[FW_VER_STR_LEN]; 1296 __be16 vxlan_port; 1297 u8 vxlan_port_cnt; 1298 __le16 vxlan_fw_dst_port_id; 1299 __be16 nge_port; 1300 u8 nge_port_cnt; 1301 __le16 nge_fw_dst_port_id; 1302 u8 port_partition_type; 1303 u8 port_count; 1304 u16 br_mode; 1305 1306 struct bnxt_coal rx_coal; 1307 struct bnxt_coal tx_coal; 1308 1309 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 1310 1311 u32 stats_coal_ticks; 1312 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1313 #define BNXT_MIN_STATS_COAL_TICKS 250000 1314 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1315 1316 struct work_struct sp_task; 1317 unsigned long sp_event; 1318 #define BNXT_RX_MASK_SP_EVENT 0 1319 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1320 #define BNXT_LINK_CHNG_SP_EVENT 2 1321 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1322 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1323 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1324 #define BNXT_RESET_TASK_SP_EVENT 6 1325 #define BNXT_RST_RING_SP_EVENT 7 1326 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1327 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1328 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1329 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1330 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1331 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1332 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1333 #define BNXT_FLOW_STATS_SP_EVENT 15 1334 1335 struct bnxt_hw_resc hw_resc; 1336 struct bnxt_pf_info pf; 1337 #ifdef CONFIG_BNXT_SRIOV 1338 int nr_vfs; 1339 struct bnxt_vf_info vf; 1340 wait_queue_head_t sriov_cfg_wait; 1341 bool sriov_cfg; 1342 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) 1343 1344 /* lock to protect VF-rep creation/cleanup via 1345 * multiple paths such as ->sriov_configure() and 1346 * devlink ->eswitch_mode_set() 1347 */ 1348 struct mutex sriov_lock; 1349 #endif 1350 1351 #define BNXT_NTP_FLTR_MAX_FLTR 4096 1352 #define BNXT_NTP_FLTR_HASH_SIZE 512 1353 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) 1354 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; 1355 spinlock_t ntp_fltr_lock; /* for hash table add, del */ 1356 1357 unsigned long *ntp_fltr_bmap; 1358 int ntp_fltr_count; 1359 1360 /* To protect link related settings during link changes and 1361 * ethtool settings changes. 1362 */ 1363 struct mutex link_lock; 1364 struct bnxt_link_info link_info; 1365 struct ethtool_eee eee; 1366 u32 lpi_tmr_lo; 1367 u32 lpi_tmr_hi; 1368 1369 u8 num_tests; 1370 struct bnxt_test_info *test_info; 1371 1372 u8 wol_filter_id; 1373 u8 wol; 1374 1375 u8 num_leds; 1376 struct bnxt_led_info leds[BNXT_MAX_LED]; 1377 1378 struct bpf_prog *xdp_prog; 1379 1380 /* devlink interface and vf-rep structs */ 1381 struct devlink *dl; 1382 enum devlink_eswitch_mode eswitch_mode; 1383 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ 1384 u16 *cfa_code_map; /* cfa_code -> vf_idx map */ 1385 u8 switch_id[8]; 1386 struct bnxt_tc_info *tc_info; 1387 }; 1388 1389 #define BNXT_RX_STATS_OFFSET(counter) \ 1390 (offsetof(struct rx_port_stats, counter) / 8) 1391 1392 #define BNXT_TX_STATS_OFFSET(counter) \ 1393 ((offsetof(struct tx_port_stats, counter) + \ 1394 sizeof(struct rx_port_stats) + 512) / 8) 1395 1396 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 1397 (offsetof(struct rx_port_stats_ext, counter) / 8) 1398 1399 #define I2C_DEV_ADDR_A0 0xa0 1400 #define I2C_DEV_ADDR_A2 0xa2 1401 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e 1402 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1 1403 #define SFF_MODULE_ID_SFP 0x3 1404 #define SFF_MODULE_ID_QSFP 0xc 1405 #define SFF_MODULE_ID_QSFP_PLUS 0xd 1406 #define SFF_MODULE_ID_QSFP28 0x11 1407 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1408 1409 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 1410 { 1411 /* Tell compiler to fetch tx indices from memory. */ 1412 barrier(); 1413 1414 return bp->tx_ring_size - 1415 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 1416 } 1417 1418 /* For TX and RX ring doorbells with no ordering guarantee*/ 1419 static inline void bnxt_db_write_relaxed(struct bnxt *bp, void __iomem *db, 1420 u32 val) 1421 { 1422 writel_relaxed(val, db); 1423 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1424 writel_relaxed(val, db); 1425 } 1426 1427 /* For TX and RX ring doorbells */ 1428 static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val) 1429 { 1430 writel(val, db); 1431 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1432 writel(val, db); 1433 } 1434 1435 extern const u16 bnxt_lhint_arr[]; 1436 1437 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1438 u16 prod, gfp_t gfp); 1439 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); 1440 void bnxt_set_tpa_flags(struct bnxt *bp); 1441 void bnxt_set_ring_params(struct bnxt *); 1442 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); 1443 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); 1444 int _hwrm_send_message(struct bnxt *, void *, u32, int); 1445 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout); 1446 int hwrm_send_message(struct bnxt *, void *, u32, int); 1447 int hwrm_send_message_silent(struct bnxt *, void *, u32, int); 1448 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 1449 int bmap_size); 1450 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); 1451 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); 1452 int bnxt_hwrm_set_coal(struct bnxt *); 1453 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); 1454 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max); 1455 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); 1456 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max); 1457 unsigned int bnxt_get_max_func_irqs(struct bnxt *bp); 1458 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max); 1459 int bnxt_get_avail_msix(struct bnxt *bp, int num); 1460 int bnxt_reserve_rings(struct bnxt *bp); 1461 void bnxt_tx_disable(struct bnxt *bp); 1462 void bnxt_tx_enable(struct bnxt *bp); 1463 int bnxt_hwrm_set_pause(struct bnxt *); 1464 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); 1465 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); 1466 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); 1467 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); 1468 int bnxt_hwrm_fw_set_time(struct bnxt *); 1469 int bnxt_open_nic(struct bnxt *, bool, bool); 1470 int bnxt_half_open_nic(struct bnxt *bp); 1471 void bnxt_half_close_nic(struct bnxt *bp); 1472 int bnxt_close_nic(struct bnxt *, bool, bool); 1473 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 1474 int tx_xdp); 1475 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); 1476 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); 1477 int bnxt_restore_pf_fw_resources(struct bnxt *bp); 1478 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr); 1479 void bnxt_dim_work(struct work_struct *work); 1480 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); 1481 1482 #endif 1483