1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  * Copyright (c) 2016-2018 Broadcom Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation.
9  */
10 
11 #ifndef BNXT_H
12 #define BNXT_H
13 
14 #define DRV_MODULE_NAME		"bnxt_en"
15 
16 /* DO NOT CHANGE DRV_VER_* defines
17  * FIXME: Delete them
18  */
19 #define DRV_VER_MAJ	1
20 #define DRV_VER_MIN	10
21 #define DRV_VER_UPD	2
22 
23 #include <linux/ethtool.h>
24 #include <linux/interrupt.h>
25 #include <linux/rhashtable.h>
26 #include <linux/crash_dump.h>
27 #include <net/devlink.h>
28 #include <net/dst_metadata.h>
29 #include <net/xdp.h>
30 #include <linux/dim.h>
31 #include <linux/io-64-nonatomic-lo-hi.h>
32 #ifdef CONFIG_TEE_BNXT_FW
33 #include <linux/firmware/broadcom/tee_bnxt_fw.h>
34 #endif
35 
36 extern struct list_head bnxt_block_cb_list;
37 
38 struct page_pool;
39 
40 struct tx_bd {
41 	__le32 tx_bd_len_flags_type;
42 	#define TX_BD_TYPE					(0x3f << 0)
43 	 #define TX_BD_TYPE_SHORT_TX_BD				 (0x00 << 0)
44 	 #define TX_BD_TYPE_LONG_TX_BD				 (0x10 << 0)
45 	#define TX_BD_FLAGS_PACKET_END				(1 << 6)
46 	#define TX_BD_FLAGS_NO_CMPL				(1 << 7)
47 	#define TX_BD_FLAGS_BD_CNT				(0x1f << 8)
48 	 #define TX_BD_FLAGS_BD_CNT_SHIFT			 8
49 	#define TX_BD_FLAGS_LHINT				(3 << 13)
50 	 #define TX_BD_FLAGS_LHINT_SHIFT			 13
51 	 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER		 (0 << 13)
52 	 #define TX_BD_FLAGS_LHINT_512_TO_1023			 (1 << 13)
53 	 #define TX_BD_FLAGS_LHINT_1024_TO_2047			 (2 << 13)
54 	 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER		 (3 << 13)
55 	#define TX_BD_FLAGS_COAL_NOW				(1 << 15)
56 	#define TX_BD_LEN					(0xffff << 16)
57 	 #define TX_BD_LEN_SHIFT				 16
58 
59 	u32 tx_bd_opaque;
60 	__le64 tx_bd_haddr;
61 } __packed;
62 
63 struct tx_bd_ext {
64 	__le32 tx_bd_hsize_lflags;
65 	#define TX_BD_FLAGS_TCP_UDP_CHKSUM			(1 << 0)
66 	#define TX_BD_FLAGS_IP_CKSUM				(1 << 1)
67 	#define TX_BD_FLAGS_NO_CRC				(1 << 2)
68 	#define TX_BD_FLAGS_STAMP				(1 << 3)
69 	#define TX_BD_FLAGS_T_IP_CHKSUM				(1 << 4)
70 	#define TX_BD_FLAGS_LSO					(1 << 5)
71 	#define TX_BD_FLAGS_IPID_FMT				(1 << 6)
72 	#define TX_BD_FLAGS_T_IPID				(1 << 7)
73 	#define TX_BD_HSIZE					(0xff << 16)
74 	 #define TX_BD_HSIZE_SHIFT				 16
75 
76 	__le32 tx_bd_mss;
77 	__le32 tx_bd_cfa_action;
78 	#define TX_BD_CFA_ACTION				(0xffff << 16)
79 	 #define TX_BD_CFA_ACTION_SHIFT				 16
80 
81 	__le32 tx_bd_cfa_meta;
82 	#define TX_BD_CFA_META_MASK                             0xfffffff
83 	#define TX_BD_CFA_META_VID_MASK                         0xfff
84 	#define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
85 	 #define TX_BD_CFA_META_PRI_SHIFT                        12
86 	#define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
87 	 #define TX_BD_CFA_META_TPID_SHIFT                       16
88 	#define TX_BD_CFA_META_KEY                              (0xf << 28)
89 	 #define TX_BD_CFA_META_KEY_SHIFT			 28
90 	#define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
91 };
92 
93 #define BNXT_TX_PTP_IS_SET(lflags) ((lflags) & cpu_to_le32(TX_BD_FLAGS_STAMP))
94 
95 struct rx_bd {
96 	__le32 rx_bd_len_flags_type;
97 	#define RX_BD_TYPE					(0x3f << 0)
98 	 #define RX_BD_TYPE_RX_PACKET_BD			 0x4
99 	 #define RX_BD_TYPE_RX_BUFFER_BD			 0x5
100 	 #define RX_BD_TYPE_RX_AGG_BD				 0x6
101 	 #define RX_BD_TYPE_16B_BD_SIZE				 (0 << 4)
102 	 #define RX_BD_TYPE_32B_BD_SIZE				 (1 << 4)
103 	 #define RX_BD_TYPE_48B_BD_SIZE				 (2 << 4)
104 	 #define RX_BD_TYPE_64B_BD_SIZE				 (3 << 4)
105 	#define RX_BD_FLAGS_SOP					(1 << 6)
106 	#define RX_BD_FLAGS_EOP					(1 << 7)
107 	#define RX_BD_FLAGS_BUFFERS				(3 << 8)
108 	 #define RX_BD_FLAGS_1_BUFFER_PACKET			 (0 << 8)
109 	 #define RX_BD_FLAGS_2_BUFFER_PACKET			 (1 << 8)
110 	 #define RX_BD_FLAGS_3_BUFFER_PACKET			 (2 << 8)
111 	 #define RX_BD_FLAGS_4_BUFFER_PACKET			 (3 << 8)
112 	#define RX_BD_LEN					(0xffff << 16)
113 	 #define RX_BD_LEN_SHIFT				 16
114 
115 	u32 rx_bd_opaque;
116 	__le64 rx_bd_haddr;
117 };
118 
119 struct tx_cmp {
120 	__le32 tx_cmp_flags_type;
121 	#define CMP_TYPE					(0x3f << 0)
122 	 #define CMP_TYPE_TX_L2_CMP				 0
123 	 #define CMP_TYPE_RX_L2_CMP				 17
124 	 #define CMP_TYPE_RX_AGG_CMP				 18
125 	 #define CMP_TYPE_RX_L2_TPA_START_CMP			 19
126 	 #define CMP_TYPE_RX_L2_TPA_END_CMP			 21
127 	 #define CMP_TYPE_RX_TPA_AGG_CMP			 22
128 	 #define CMP_TYPE_STATUS_CMP				 32
129 	 #define CMP_TYPE_REMOTE_DRIVER_REQ			 34
130 	 #define CMP_TYPE_REMOTE_DRIVER_RESP			 36
131 	 #define CMP_TYPE_ERROR_STATUS				 48
132 	 #define CMPL_BASE_TYPE_STAT_EJECT			 0x1aUL
133 	 #define CMPL_BASE_TYPE_HWRM_DONE			 0x20UL
134 	 #define CMPL_BASE_TYPE_HWRM_FWD_REQ			 0x22UL
135 	 #define CMPL_BASE_TYPE_HWRM_FWD_RESP			 0x24UL
136 	 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT		 0x2eUL
137 
138 	#define TX_CMP_FLAGS_ERROR				(1 << 6)
139 	#define TX_CMP_FLAGS_PUSH				(1 << 7)
140 
141 	u32 tx_cmp_opaque;
142 	__le32 tx_cmp_errors_v;
143 	#define TX_CMP_V					(1 << 0)
144 	#define TX_CMP_ERRORS_BUFFER_ERROR			(7 << 1)
145 	 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR		 0
146 	 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT		 2
147 	 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG	 4
148 	 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS		 5
149 	 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT			 (1 << 4)
150 	 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN			 (1 << 5)
151 	 #define TX_CMP_ERRORS_DMA_ERROR			 (1 << 6)
152 	 #define TX_CMP_ERRORS_HINT_TOO_SHORT			 (1 << 7)
153 
154 	__le32 tx_cmp_unsed_3;
155 };
156 
157 struct rx_cmp {
158 	__le32 rx_cmp_len_flags_type;
159 	#define RX_CMP_CMP_TYPE					(0x3f << 0)
160 	#define RX_CMP_FLAGS_ERROR				(1 << 6)
161 	#define RX_CMP_FLAGS_PLACEMENT				(7 << 7)
162 	#define RX_CMP_FLAGS_RSS_VALID				(1 << 10)
163 	#define RX_CMP_FLAGS_UNUSED				(1 << 11)
164 	 #define RX_CMP_FLAGS_ITYPES_SHIFT			 12
165 	 #define RX_CMP_FLAGS_ITYPES_MASK			 0xf000
166 	 #define RX_CMP_FLAGS_ITYPE_UNKNOWN			 (0 << 12)
167 	 #define RX_CMP_FLAGS_ITYPE_IP				 (1 << 12)
168 	 #define RX_CMP_FLAGS_ITYPE_TCP				 (2 << 12)
169 	 #define RX_CMP_FLAGS_ITYPE_UDP				 (3 << 12)
170 	 #define RX_CMP_FLAGS_ITYPE_FCOE			 (4 << 12)
171 	 #define RX_CMP_FLAGS_ITYPE_ROCE			 (5 << 12)
172 	 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS			 (8 << 12)
173 	 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS			 (9 << 12)
174 	#define RX_CMP_LEN					(0xffff << 16)
175 	 #define RX_CMP_LEN_SHIFT				 16
176 
177 	u32 rx_cmp_opaque;
178 	__le32 rx_cmp_misc_v1;
179 	#define RX_CMP_V1					(1 << 0)
180 	#define RX_CMP_AGG_BUFS					(0x1f << 1)
181 	 #define RX_CMP_AGG_BUFS_SHIFT				 1
182 	#define RX_CMP_RSS_HASH_TYPE				(0x7f << 9)
183 	 #define RX_CMP_RSS_HASH_TYPE_SHIFT			 9
184 	#define RX_CMP_PAYLOAD_OFFSET				(0xff << 16)
185 	 #define RX_CMP_PAYLOAD_OFFSET_SHIFT			 16
186 
187 	__le32 rx_cmp_rss_hash;
188 };
189 
190 #define RX_CMP_HASH_VALID(rxcmp)				\
191 	((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
192 
193 #define RSS_PROFILE_ID_MASK	0x1f
194 
195 #define RX_CMP_HASH_TYPE(rxcmp)					\
196 	(((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
197 	  RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
198 
199 struct rx_cmp_ext {
200 	__le32 rx_cmp_flags2;
201 	#define RX_CMP_FLAGS2_IP_CS_CALC			0x1
202 	#define RX_CMP_FLAGS2_L4_CS_CALC			(0x1 << 1)
203 	#define RX_CMP_FLAGS2_T_IP_CS_CALC			(0x1 << 2)
204 	#define RX_CMP_FLAGS2_T_L4_CS_CALC			(0x1 << 3)
205 	#define RX_CMP_FLAGS2_META_FORMAT_VLAN			(0x1 << 4)
206 	__le32 rx_cmp_meta_data;
207 	#define RX_CMP_FLAGS2_METADATA_TCI_MASK			0xffff
208 	#define RX_CMP_FLAGS2_METADATA_VID_MASK			0xfff
209 	#define RX_CMP_FLAGS2_METADATA_TPID_MASK		0xffff0000
210 	 #define RX_CMP_FLAGS2_METADATA_TPID_SFT		 16
211 	__le32 rx_cmp_cfa_code_errors_v2;
212 	#define RX_CMP_V					(1 << 0)
213 	#define RX_CMPL_ERRORS_MASK				(0x7fff << 1)
214 	 #define RX_CMPL_ERRORS_SFT				 1
215 	#define RX_CMPL_ERRORS_BUFFER_ERROR_MASK		(0x7 << 1)
216 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER		 (0x0 << 1)
217 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT	 (0x1 << 1)
218 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
219 	 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT		 (0x3 << 1)
220 	#define RX_CMPL_ERRORS_IP_CS_ERROR			(0x1 << 4)
221 	#define RX_CMPL_ERRORS_L4_CS_ERROR			(0x1 << 5)
222 	#define RX_CMPL_ERRORS_T_IP_CS_ERROR			(0x1 << 6)
223 	#define RX_CMPL_ERRORS_T_L4_CS_ERROR			(0x1 << 7)
224 	#define RX_CMPL_ERRORS_CRC_ERROR			(0x1 << 8)
225 	#define RX_CMPL_ERRORS_T_PKT_ERROR_MASK			(0x7 << 9)
226 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR		 (0x0 << 9)
227 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION	 (0x1 << 9)
228 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN	 (0x2 << 9)
229 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR	 (0x3 << 9)
230 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR	 (0x4 << 9)
231 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR	 (0x5 << 9)
232 	 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL	 (0x6 << 9)
233 	#define RX_CMPL_ERRORS_PKT_ERROR_MASK			(0xf << 12)
234 	 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR		 (0x0 << 12)
235 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION	 (0x1 << 12)
236 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN	 (0x2 << 12)
237 	 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL		 (0x3 << 12)
238 	 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR	 (0x4 << 12)
239 	 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR	 (0x5 << 12)
240 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN	 (0x6 << 12)
241 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
242 	 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN	 (0x8 << 12)
243 
244 	#define RX_CMPL_CFA_CODE_MASK				(0xffff << 16)
245 	 #define RX_CMPL_CFA_CODE_SFT				 16
246 
247 	__le32 rx_cmp_timestamp;
248 };
249 
250 #define RX_CMP_L2_ERRORS						\
251 	cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
252 
253 #define RX_CMP_L4_CS_BITS						\
254 	(cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
255 
256 #define RX_CMP_L4_CS_ERR_BITS						\
257 	(cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
258 
259 #define RX_CMP_L4_CS_OK(rxcmp1)						\
260 	    (((rxcmp1)->rx_cmp_flags2 &	RX_CMP_L4_CS_BITS) &&		\
261 	     !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
262 
263 #define RX_CMP_ENCAP(rxcmp1)						\
264 	    ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &			\
265 	     RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
266 
267 #define RX_CMP_CFA_CODE(rxcmpl1)					\
268 	((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &		\
269 	  RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
270 
271 struct rx_agg_cmp {
272 	__le32 rx_agg_cmp_len_flags_type;
273 	#define RX_AGG_CMP_TYPE					(0x3f << 0)
274 	#define RX_AGG_CMP_LEN					(0xffff << 16)
275 	 #define RX_AGG_CMP_LEN_SHIFT				 16
276 	u32 rx_agg_cmp_opaque;
277 	__le32 rx_agg_cmp_v;
278 	#define RX_AGG_CMP_V					(1 << 0)
279 	#define RX_AGG_CMP_AGG_ID				(0xffff << 16)
280 	 #define RX_AGG_CMP_AGG_ID_SHIFT			 16
281 	__le32 rx_agg_cmp_unused;
282 };
283 
284 #define TPA_AGG_AGG_ID(rx_agg)				\
285 	((le32_to_cpu((rx_agg)->rx_agg_cmp_v) &		\
286 	 RX_AGG_CMP_AGG_ID) >> RX_AGG_CMP_AGG_ID_SHIFT)
287 
288 struct rx_tpa_start_cmp {
289 	__le32 rx_tpa_start_cmp_len_flags_type;
290 	#define RX_TPA_START_CMP_TYPE				(0x3f << 0)
291 	#define RX_TPA_START_CMP_FLAGS				(0x3ff << 6)
292 	 #define RX_TPA_START_CMP_FLAGS_SHIFT			 6
293 	#define RX_TPA_START_CMP_FLAGS_ERROR			(0x1 << 6)
294 	#define RX_TPA_START_CMP_FLAGS_PLACEMENT		(0x7 << 7)
295 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT		 7
296 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
297 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
298 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
299 	 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS	 (0x6 << 7)
300 	#define RX_TPA_START_CMP_FLAGS_RSS_VALID		(0x1 << 10)
301 	#define RX_TPA_START_CMP_FLAGS_TIMESTAMP		(0x1 << 11)
302 	#define RX_TPA_START_CMP_FLAGS_ITYPES			(0xf << 12)
303 	 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT		 12
304 	 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP		 (0x2 << 12)
305 	#define RX_TPA_START_CMP_LEN				(0xffff << 16)
306 	 #define RX_TPA_START_CMP_LEN_SHIFT			 16
307 
308 	u32 rx_tpa_start_cmp_opaque;
309 	__le32 rx_tpa_start_cmp_misc_v1;
310 	#define RX_TPA_START_CMP_V1				(0x1 << 0)
311 	#define RX_TPA_START_CMP_RSS_HASH_TYPE			(0x7f << 9)
312 	 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT		 9
313 	#define RX_TPA_START_CMP_AGG_ID				(0x7f << 25)
314 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT			 25
315 	#define RX_TPA_START_CMP_AGG_ID_P5			(0xffff << 16)
316 	 #define RX_TPA_START_CMP_AGG_ID_SHIFT_P5		 16
317 
318 	__le32 rx_tpa_start_cmp_rss_hash;
319 };
320 
321 #define TPA_START_HASH_VALID(rx_tpa_start)				\
322 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
323 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
324 
325 #define TPA_START_HASH_TYPE(rx_tpa_start)				\
326 	(((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
327 	   RX_TPA_START_CMP_RSS_HASH_TYPE) >>				\
328 	  RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
329 
330 #define TPA_START_AGG_ID(rx_tpa_start)					\
331 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
332 	 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
333 
334 #define TPA_START_AGG_ID_P5(rx_tpa_start)				\
335 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &	\
336 	 RX_TPA_START_CMP_AGG_ID_P5) >> RX_TPA_START_CMP_AGG_ID_SHIFT_P5)
337 
338 #define TPA_START_ERROR(rx_tpa_start)					\
339 	((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &		\
340 	 cpu_to_le32(RX_TPA_START_CMP_FLAGS_ERROR))
341 
342 struct rx_tpa_start_cmp_ext {
343 	__le32 rx_tpa_start_cmp_flags2;
344 	#define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC		(0x1 << 0)
345 	#define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC		(0x1 << 1)
346 	#define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC		(0x1 << 2)
347 	#define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC		(0x1 << 3)
348 	#define RX_TPA_START_CMP_FLAGS2_IP_TYPE			(0x1 << 8)
349 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID		(0x1 << 9)
350 	#define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT		(0x3 << 10)
351 	 #define RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT	 10
352 	#define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL		(0xffff << 16)
353 	 #define RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT	 16
354 
355 	__le32 rx_tpa_start_cmp_metadata;
356 	__le32 rx_tpa_start_cmp_cfa_code_v2;
357 	#define RX_TPA_START_CMP_V2				(0x1 << 0)
358 	#define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK	(0x7 << 1)
359 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT	 1
360 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
361 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
362 	 #define RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
363 	#define RX_TPA_START_CMP_CFA_CODE			(0xffff << 16)
364 	 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT		 16
365 	__le32 rx_tpa_start_cmp_hdr_info;
366 };
367 
368 #define TPA_START_CFA_CODE(rx_tpa_start)				\
369 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
370 	 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
371 
372 #define TPA_START_IS_IPV6(rx_tpa_start)				\
373 	(!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &		\
374 	    cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
375 
376 #define TPA_START_ERROR_CODE(rx_tpa_start)				\
377 	((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &	\
378 	  RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK) >>			\
379 	 RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT)
380 
381 struct rx_tpa_end_cmp {
382 	__le32 rx_tpa_end_cmp_len_flags_type;
383 	#define RX_TPA_END_CMP_TYPE				(0x3f << 0)
384 	#define RX_TPA_END_CMP_FLAGS				(0x3ff << 6)
385 	 #define RX_TPA_END_CMP_FLAGS_SHIFT			 6
386 	#define RX_TPA_END_CMP_FLAGS_PLACEMENT			(0x7 << 7)
387 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT		 7
388 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO		 (0x1 << 7)
389 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS		 (0x2 << 7)
390 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO	 (0x5 << 7)
391 	 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS		 (0x6 << 7)
392 	#define RX_TPA_END_CMP_FLAGS_RSS_VALID			(0x1 << 10)
393 	#define RX_TPA_END_CMP_FLAGS_ITYPES			(0xf << 12)
394 	 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT		 12
395 	 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP			 (0x2 << 12)
396 	#define RX_TPA_END_CMP_LEN				(0xffff << 16)
397 	 #define RX_TPA_END_CMP_LEN_SHIFT			 16
398 
399 	u32 rx_tpa_end_cmp_opaque;
400 	__le32 rx_tpa_end_cmp_misc_v1;
401 	#define RX_TPA_END_CMP_V1				(0x1 << 0)
402 	#define RX_TPA_END_CMP_AGG_BUFS				(0x3f << 1)
403 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT			 1
404 	#define RX_TPA_END_CMP_TPA_SEGS				(0xff << 8)
405 	 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT			 8
406 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET			(0xff << 16)
407 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT		 16
408 	#define RX_TPA_END_CMP_AGG_ID				(0x7f << 25)
409 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT			 25
410 	#define RX_TPA_END_CMP_AGG_ID_P5			(0xffff << 16)
411 	 #define RX_TPA_END_CMP_AGG_ID_SHIFT_P5			 16
412 
413 	__le32 rx_tpa_end_cmp_tsdelta;
414 	#define RX_TPA_END_GRO_TS				(0x1 << 31)
415 };
416 
417 #define TPA_END_AGG_ID(rx_tpa_end)					\
418 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
419 	 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
420 
421 #define TPA_END_AGG_ID_P5(rx_tpa_end)					\
422 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
423 	 RX_TPA_END_CMP_AGG_ID_P5) >> RX_TPA_END_CMP_AGG_ID_SHIFT_P5)
424 
425 #define TPA_END_PAYLOAD_OFF(rx_tpa_end)					\
426 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
427 	 RX_TPA_END_CMP_PAYLOAD_OFFSET) >> RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT)
428 
429 #define TPA_END_AGG_BUFS(rx_tpa_end)					\
430 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
431 	 RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT)
432 
433 #define TPA_END_TPA_SEGS(rx_tpa_end)					\
434 	((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &		\
435 	 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
436 
437 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO				\
438 	cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &		\
439 		    RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
440 
441 #define TPA_END_GRO(rx_tpa_end)						\
442 	((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &			\
443 	 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
444 
445 #define TPA_END_GRO_TS(rx_tpa_end)					\
446 	(!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &			\
447 	    cpu_to_le32(RX_TPA_END_GRO_TS)))
448 
449 struct rx_tpa_end_cmp_ext {
450 	__le32 rx_tpa_end_cmp_dup_acks;
451 	#define RX_TPA_END_CMP_TPA_DUP_ACKS			(0xf << 0)
452 	#define RX_TPA_END_CMP_PAYLOAD_OFFSET_P5		(0xff << 16)
453 	 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5		 16
454 	#define RX_TPA_END_CMP_AGG_BUFS_P5			(0xff << 24)
455 	 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5		 24
456 
457 	__le32 rx_tpa_end_cmp_seg_len;
458 	#define RX_TPA_END_CMP_TPA_SEG_LEN			(0xffff << 0)
459 
460 	__le32 rx_tpa_end_cmp_errors_v2;
461 	#define RX_TPA_END_CMP_V2				(0x1 << 0)
462 	#define RX_TPA_END_CMP_ERRORS				(0x3 << 1)
463 	#define RX_TPA_END_CMP_ERRORS_P5			(0x7 << 1)
464 	#define RX_TPA_END_CMPL_ERRORS_SHIFT			 1
465 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER	 (0x0 << 1)
466 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP	 (0x2 << 1)
467 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT	 (0x3 << 1)
468 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR	 (0x4 << 1)
469 	 #define RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH	 (0x5 << 1)
470 
471 	u32 rx_tpa_end_cmp_start_opaque;
472 };
473 
474 #define TPA_END_ERRORS(rx_tpa_end_ext)					\
475 	((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &			\
476 	 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
477 
478 #define TPA_END_PAYLOAD_OFF_P5(rx_tpa_end_ext)				\
479 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
480 	 RX_TPA_END_CMP_PAYLOAD_OFFSET_P5) >>				\
481 	RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5)
482 
483 #define TPA_END_AGG_BUFS_P5(rx_tpa_end_ext)				\
484 	((le32_to_cpu((rx_tpa_end_ext)->rx_tpa_end_cmp_dup_acks) &	\
485 	 RX_TPA_END_CMP_AGG_BUFS_P5) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5)
486 
487 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1)				\
488 	(((data1) &							\
489 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
490 	 ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL)
491 
492 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1)			\
493 	(((data1) &							\
494 	  ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\
495 	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION)
496 
497 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2)			\
498 	((data2) &							\
499 	ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK)
500 
501 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1)				\
502 	!!((data1) &							\
503 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC)
504 
505 #define EVENT_DATA1_RECOVERY_ENABLED(data1)				\
506 	!!((data1) &							\
507 	   ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED)
508 
509 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1)				\
510 	(((data1) &							\
511 	  ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >>\
512 	 ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT)
513 
514 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2)				\
515 	(((data2) &							\
516 	  ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >>\
517 	 ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT)
518 
519 struct nqe_cn {
520 	__le16	type;
521 	#define NQ_CN_TYPE_MASK           0x3fUL
522 	#define NQ_CN_TYPE_SFT            0
523 	#define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
524 	#define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
525 	__le16	reserved16;
526 	__le32	cq_handle_low;
527 	__le32	v;
528 	#define NQ_CN_V     0x1UL
529 	__le32	cq_handle_high;
530 };
531 
532 #define DB_IDX_MASK						0xffffff
533 #define DB_IDX_VALID						(0x1 << 26)
534 #define DB_IRQ_DIS						(0x1 << 27)
535 #define DB_KEY_TX						(0x0 << 28)
536 #define DB_KEY_RX						(0x1 << 28)
537 #define DB_KEY_CP						(0x2 << 28)
538 #define DB_KEY_ST						(0x3 << 28)
539 #define DB_KEY_TX_PUSH						(0x4 << 28)
540 #define DB_LONG_TX_PUSH						(0x2 << 24)
541 
542 #define BNXT_MIN_ROCE_CP_RINGS	2
543 #define BNXT_MIN_ROCE_STAT_CTXS	1
544 
545 /* 64-bit doorbell */
546 #define DBR_INDEX_MASK					0x0000000000ffffffULL
547 #define DBR_XID_MASK					0x000fffff00000000ULL
548 #define DBR_XID_SFT					32
549 #define DBR_PATH_L2					(0x1ULL << 56)
550 #define DBR_TYPE_SQ					(0x0ULL << 60)
551 #define DBR_TYPE_RQ					(0x1ULL << 60)
552 #define DBR_TYPE_SRQ					(0x2ULL << 60)
553 #define DBR_TYPE_SRQ_ARM				(0x3ULL << 60)
554 #define DBR_TYPE_CQ					(0x4ULL << 60)
555 #define DBR_TYPE_CQ_ARMSE				(0x5ULL << 60)
556 #define DBR_TYPE_CQ_ARMALL				(0x6ULL << 60)
557 #define DBR_TYPE_CQ_ARMENA				(0x7ULL << 60)
558 #define DBR_TYPE_SRQ_ARMENA				(0x8ULL << 60)
559 #define DBR_TYPE_CQ_CUTOFF_ACK				(0x9ULL << 60)
560 #define DBR_TYPE_NQ					(0xaULL << 60)
561 #define DBR_TYPE_NQ_ARM					(0xbULL << 60)
562 #define DBR_TYPE_NULL					(0xfULL << 60)
563 
564 #define DB_PF_OFFSET_P5					0x10000
565 #define DB_VF_OFFSET_P5					0x4000
566 
567 #define INVALID_HW_RING_ID	((u16)-1)
568 
569 /* The hardware supports certain page sizes.  Use the supported page sizes
570  * to allocate the rings.
571  */
572 #if (PAGE_SHIFT < 12)
573 #define BNXT_PAGE_SHIFT	12
574 #elif (PAGE_SHIFT <= 13)
575 #define BNXT_PAGE_SHIFT	PAGE_SHIFT
576 #elif (PAGE_SHIFT < 16)
577 #define BNXT_PAGE_SHIFT	13
578 #else
579 #define BNXT_PAGE_SHIFT	16
580 #endif
581 
582 #define BNXT_PAGE_SIZE	(1 << BNXT_PAGE_SHIFT)
583 
584 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
585 #if (PAGE_SHIFT > 15)
586 #define BNXT_RX_PAGE_SHIFT 15
587 #else
588 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
589 #endif
590 
591 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
592 
593 #define BNXT_MAX_MTU		9500
594 #define BNXT_MAX_PAGE_MODE_MTU	\
595 	((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -	\
596 	 XDP_PACKET_HEADROOM - \
597 	 SKB_DATA_ALIGN((unsigned int)sizeof(struct skb_shared_info)))
598 
599 #define BNXT_MIN_PKT_SIZE	52
600 
601 #define BNXT_DEFAULT_RX_RING_SIZE	511
602 #define BNXT_DEFAULT_TX_RING_SIZE	511
603 
604 #define MAX_TPA		64
605 #define MAX_TPA_P5	256
606 #define MAX_TPA_P5_MASK	(MAX_TPA_P5 - 1)
607 #define MAX_TPA_SEGS_P5	0x3f
608 
609 #if (BNXT_PAGE_SHIFT == 16)
610 #define MAX_RX_PAGES_AGG_ENA	1
611 #define MAX_RX_PAGES	4
612 #define MAX_RX_AGG_PAGES	4
613 #define MAX_TX_PAGES	1
614 #define MAX_CP_PAGES	16
615 #else
616 #define MAX_RX_PAGES_AGG_ENA	8
617 #define MAX_RX_PAGES	32
618 #define MAX_RX_AGG_PAGES	32
619 #define MAX_TX_PAGES	8
620 #define MAX_CP_PAGES	128
621 #endif
622 
623 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
624 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
625 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
626 
627 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
628 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
629 
630 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
631 
632 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
633 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
634 
635 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
636 
637 #define BNXT_MAX_RX_DESC_CNT		(RX_DESC_CNT * MAX_RX_PAGES - 1)
638 #define BNXT_MAX_RX_DESC_CNT_JUM_ENA	(RX_DESC_CNT * MAX_RX_PAGES_AGG_ENA - 1)
639 #define BNXT_MAX_RX_JUM_DESC_CNT	(RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
640 #define BNXT_MAX_TX_DESC_CNT		(TX_DESC_CNT * MAX_TX_PAGES - 1)
641 
642 /* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra
643  * BD because the first TX BD is always a long BD.
644  */
645 #define BNXT_MIN_TX_DESC_CNT		(MAX_SKB_FRAGS + 2)
646 
647 #define RX_RING(x)	(((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
648 #define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))
649 
650 #define TX_RING(x)	(((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
651 #define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))
652 
653 #define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
654 #define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))
655 
656 #define TX_CMP_VALID(txcmp, raw_cons)					\
657 	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
658 	 !((raw_cons) & bp->cp_bit))
659 
660 #define RX_CMP_VALID(rxcmp1, raw_cons)					\
661 	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
662 	 !((raw_cons) & bp->cp_bit))
663 
664 #define RX_AGG_CMP_VALID(agg, raw_cons)				\
665 	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
666 	 !((raw_cons) & bp->cp_bit))
667 
668 #define NQ_CMP_VALID(nqcmp, raw_cons)				\
669 	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
670 
671 #define TX_CMP_TYPE(txcmp)					\
672 	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
673 
674 #define RX_CMP_TYPE(rxcmp)					\
675 	(le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
676 
677 #define NEXT_RX(idx)		(((idx) + 1) & bp->rx_ring_mask)
678 
679 #define NEXT_RX_AGG(idx)	(((idx) + 1) & bp->rx_agg_ring_mask)
680 
681 #define NEXT_TX(idx)		(((idx) + 1) & bp->tx_ring_mask)
682 
683 #define ADV_RAW_CMP(idx, n)	((idx) + (n))
684 #define NEXT_RAW_CMP(idx)	ADV_RAW_CMP(idx, 1)
685 #define RING_CMP(idx)		((idx) & bp->cp_ring_mask)
686 #define NEXT_CMP(idx)		RING_CMP(ADV_RAW_CMP(idx, 1))
687 
688 #define DFLT_HWRM_CMD_TIMEOUT		500
689 
690 #define BNXT_RX_EVENT		1
691 #define BNXT_AGG_EVENT		2
692 #define BNXT_TX_EVENT		4
693 #define BNXT_REDIRECT_EVENT	8
694 
695 struct bnxt_sw_tx_bd {
696 	union {
697 		struct sk_buff		*skb;
698 		struct xdp_frame	*xdpf;
699 	};
700 	DEFINE_DMA_UNMAP_ADDR(mapping);
701 	DEFINE_DMA_UNMAP_LEN(len);
702 	u8			is_gso;
703 	u8			is_push;
704 	u8			action;
705 	union {
706 		unsigned short		nr_frags;
707 		u16			rx_prod;
708 	};
709 };
710 
711 struct bnxt_sw_rx_bd {
712 	void			*data;
713 	u8			*data_ptr;
714 	dma_addr_t		mapping;
715 };
716 
717 struct bnxt_sw_rx_agg_bd {
718 	struct page		*page;
719 	unsigned int		offset;
720 	dma_addr_t		mapping;
721 };
722 
723 struct bnxt_mem_init {
724 	u8	init_val;
725 	u16	offset;
726 #define	BNXT_MEM_INVALID_OFFSET	0xffff
727 	u16	size;
728 };
729 
730 struct bnxt_ring_mem_info {
731 	int			nr_pages;
732 	int			page_size;
733 	u16			flags;
734 #define BNXT_RMEM_VALID_PTE_FLAG	1
735 #define BNXT_RMEM_RING_PTE_FLAG		2
736 #define BNXT_RMEM_USE_FULL_PAGE_FLAG	4
737 
738 	u16			depth;
739 	struct bnxt_mem_init	*mem_init;
740 
741 	void			**pg_arr;
742 	dma_addr_t		*dma_arr;
743 
744 	__le64			*pg_tbl;
745 	dma_addr_t		pg_tbl_map;
746 
747 	int			vmem_size;
748 	void			**vmem;
749 };
750 
751 struct bnxt_ring_struct {
752 	struct bnxt_ring_mem_info	ring_mem;
753 
754 	u16			fw_ring_id; /* Ring id filled by Chimp FW */
755 	union {
756 		u16		grp_idx;
757 		u16		map_idx; /* Used by cmpl rings */
758 	};
759 	u32			handle;
760 	u8			queue_id;
761 };
762 
763 struct tx_push_bd {
764 	__le32			doorbell;
765 	__le32			tx_bd_len_flags_type;
766 	u32			tx_bd_opaque;
767 	struct tx_bd_ext	txbd2;
768 };
769 
770 struct tx_push_buffer {
771 	struct tx_push_bd	push_bd;
772 	u32			data[25];
773 };
774 
775 struct bnxt_db_info {
776 	void __iomem		*doorbell;
777 	union {
778 		u64		db_key64;
779 		u32		db_key32;
780 	};
781 };
782 
783 struct bnxt_tx_ring_info {
784 	struct bnxt_napi	*bnapi;
785 	u16			tx_prod;
786 	u16			tx_cons;
787 	u16			txq_index;
788 	u8			kick_pending;
789 	struct bnxt_db_info	tx_db;
790 
791 	struct tx_bd		*tx_desc_ring[MAX_TX_PAGES];
792 	struct bnxt_sw_tx_bd	*tx_buf_ring;
793 
794 	dma_addr_t		tx_desc_mapping[MAX_TX_PAGES];
795 
796 	struct tx_push_buffer	*tx_push;
797 	dma_addr_t		tx_push_mapping;
798 	__le64			data_mapping;
799 
800 #define BNXT_DEV_STATE_CLOSING	0x1
801 	u32			dev_state;
802 
803 	struct bnxt_ring_struct	tx_ring_struct;
804 	/* Synchronize simultaneous xdp_xmit on same ring */
805 	spinlock_t		xdp_tx_lock;
806 };
807 
808 #define BNXT_LEGACY_COAL_CMPL_PARAMS					\
809 	(RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |		\
810 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |		\
811 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |		\
812 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |			\
813 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |		\
814 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
815 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |		\
816 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
817 	 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
818 
819 #define BNXT_COAL_CMPL_ENABLES						\
820 	(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
821 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
822 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
823 	 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
824 
825 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE					\
826 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
827 
828 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE			\
829 	RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
830 
831 struct bnxt_coal_cap {
832 	u32			cmpl_params;
833 	u32			nq_params;
834 	u16			num_cmpl_dma_aggr_max;
835 	u16			num_cmpl_dma_aggr_during_int_max;
836 	u16			cmpl_aggr_dma_tmr_max;
837 	u16			cmpl_aggr_dma_tmr_during_int_max;
838 	u16			int_lat_tmr_min_max;
839 	u16			int_lat_tmr_max_max;
840 	u16			num_cmpl_aggr_int_max;
841 	u16			timer_units;
842 };
843 
844 struct bnxt_coal {
845 	u16			coal_ticks;
846 	u16			coal_ticks_irq;
847 	u16			coal_bufs;
848 	u16			coal_bufs_irq;
849 			/* RING_IDLE enabled when coal ticks < idle_thresh  */
850 	u16			idle_thresh;
851 	u8			bufs_per_record;
852 	u8			budget;
853 	u16			flags;
854 };
855 
856 struct bnxt_tpa_info {
857 	void			*data;
858 	u8			*data_ptr;
859 	dma_addr_t		mapping;
860 	u16			len;
861 	unsigned short		gso_type;
862 	u32			flags2;
863 	u32			metadata;
864 	enum pkt_hash_types	hash_type;
865 	u32			rss_hash;
866 	u32			hdr_info;
867 
868 #define BNXT_TPA_L4_SIZE(hdr_info)	\
869 	(((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
870 
871 #define BNXT_TPA_INNER_L3_OFF(hdr_info)	\
872 	(((hdr_info) >> 18) & 0x1ff)
873 
874 #define BNXT_TPA_INNER_L2_OFF(hdr_info)	\
875 	(((hdr_info) >> 9) & 0x1ff)
876 
877 #define BNXT_TPA_OUTER_L3_OFF(hdr_info)	\
878 	((hdr_info) & 0x1ff)
879 
880 	u16			cfa_code; /* cfa_code in TPA start compl */
881 	u8			agg_count;
882 	struct rx_agg_cmp	*agg_arr;
883 };
884 
885 #define BNXT_AGG_IDX_BMAP_SIZE	(MAX_TPA_P5 / BITS_PER_LONG)
886 
887 struct bnxt_tpa_idx_map {
888 	u16		agg_id_tbl[1024];
889 	unsigned long	agg_idx_bmap[BNXT_AGG_IDX_BMAP_SIZE];
890 };
891 
892 struct bnxt_rx_ring_info {
893 	struct bnxt_napi	*bnapi;
894 	u16			rx_prod;
895 	u16			rx_agg_prod;
896 	u16			rx_sw_agg_prod;
897 	u16			rx_next_cons;
898 	struct bnxt_db_info	rx_db;
899 	struct bnxt_db_info	rx_agg_db;
900 
901 	struct bpf_prog		*xdp_prog;
902 
903 	struct rx_bd		*rx_desc_ring[MAX_RX_PAGES];
904 	struct bnxt_sw_rx_bd	*rx_buf_ring;
905 
906 	struct rx_bd		*rx_agg_desc_ring[MAX_RX_AGG_PAGES];
907 	struct bnxt_sw_rx_agg_bd	*rx_agg_ring;
908 
909 	unsigned long		*rx_agg_bmap;
910 	u16			rx_agg_bmap_size;
911 
912 	struct page		*rx_page;
913 	unsigned int		rx_page_offset;
914 
915 	dma_addr_t		rx_desc_mapping[MAX_RX_PAGES];
916 	dma_addr_t		rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
917 
918 	struct bnxt_tpa_info	*rx_tpa;
919 	struct bnxt_tpa_idx_map *rx_tpa_idx_map;
920 
921 	struct bnxt_ring_struct	rx_ring_struct;
922 	struct bnxt_ring_struct	rx_agg_ring_struct;
923 	struct xdp_rxq_info	xdp_rxq;
924 	struct page_pool	*page_pool;
925 };
926 
927 struct bnxt_rx_sw_stats {
928 	u64			rx_l4_csum_errors;
929 	u64			rx_resets;
930 	u64			rx_buf_errors;
931 	u64			rx_oom_discards;
932 	u64			rx_netpoll_discards;
933 };
934 
935 struct bnxt_cmn_sw_stats {
936 	u64			missed_irqs;
937 };
938 
939 struct bnxt_sw_stats {
940 	struct bnxt_rx_sw_stats rx;
941 	struct bnxt_cmn_sw_stats cmn;
942 };
943 
944 struct bnxt_stats_mem {
945 	u64		*sw_stats;
946 	u64		*hw_masks;
947 	void		*hw_stats;
948 	dma_addr_t	hw_stats_map;
949 	int		len;
950 };
951 
952 struct bnxt_cp_ring_info {
953 	struct bnxt_napi	*bnapi;
954 	u32			cp_raw_cons;
955 	struct bnxt_db_info	cp_db;
956 
957 	u8			had_work_done:1;
958 	u8			has_more_work:1;
959 
960 	u32			last_cp_raw_cons;
961 
962 	struct bnxt_coal	rx_ring_coal;
963 	u64			rx_packets;
964 	u64			rx_bytes;
965 	u64			event_ctr;
966 
967 	struct dim		dim;
968 
969 	union {
970 		struct tx_cmp	**cp_desc_ring;
971 		struct nqe_cn	**nq_desc_ring;
972 	};
973 
974 	dma_addr_t		*cp_desc_mapping;
975 
976 	struct bnxt_stats_mem	stats;
977 	u32			hw_stats_ctx_id;
978 
979 	struct bnxt_sw_stats	sw_stats;
980 
981 	struct bnxt_ring_struct	cp_ring_struct;
982 
983 	struct bnxt_cp_ring_info *cp_ring_arr[2];
984 #define BNXT_RX_HDL	0
985 #define BNXT_TX_HDL	1
986 };
987 
988 struct bnxt_napi {
989 	struct napi_struct	napi;
990 	struct bnxt		*bp;
991 
992 	int			index;
993 	struct bnxt_cp_ring_info	cp_ring;
994 	struct bnxt_rx_ring_info	*rx_ring;
995 	struct bnxt_tx_ring_info	*tx_ring;
996 
997 	void			(*tx_int)(struct bnxt *, struct bnxt_napi *,
998 					  int);
999 	int			tx_pkts;
1000 	u8			events;
1001 
1002 	u32			flags;
1003 #define BNXT_NAPI_FLAG_XDP	0x1
1004 
1005 	bool			in_reset;
1006 };
1007 
1008 struct bnxt_irq {
1009 	irq_handler_t	handler;
1010 	unsigned int	vector;
1011 	u8		requested:1;
1012 	u8		have_cpumask:1;
1013 	char		name[IFNAMSIZ + 2];
1014 	cpumask_var_t	cpu_mask;
1015 };
1016 
1017 #define HWRM_RING_ALLOC_TX	0x1
1018 #define HWRM_RING_ALLOC_RX	0x2
1019 #define HWRM_RING_ALLOC_AGG	0x4
1020 #define HWRM_RING_ALLOC_CMPL	0x8
1021 #define HWRM_RING_ALLOC_NQ	0x10
1022 
1023 #define INVALID_STATS_CTX_ID	-1
1024 
1025 struct bnxt_ring_grp_info {
1026 	u16	fw_stats_ctx;
1027 	u16	fw_grp_id;
1028 	u16	rx_fw_ring_id;
1029 	u16	agg_fw_ring_id;
1030 	u16	cp_fw_ring_id;
1031 };
1032 
1033 struct bnxt_vnic_info {
1034 	u16		fw_vnic_id; /* returned by Chimp during alloc */
1035 #define BNXT_MAX_CTX_PER_VNIC	8
1036 	u16		fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
1037 	u16		fw_l2_ctx_id;
1038 #define BNXT_MAX_UC_ADDRS	4
1039 	__le64		fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
1040 				/* index 0 always dev_addr */
1041 	u16		uc_filter_count;
1042 	u8		*uc_list;
1043 
1044 	u16		*fw_grp_ids;
1045 	dma_addr_t	rss_table_dma_addr;
1046 	__le16		*rss_table;
1047 	dma_addr_t	rss_hash_key_dma_addr;
1048 	u64		*rss_hash_key;
1049 	int		rss_table_size;
1050 #define BNXT_RSS_TABLE_ENTRIES_P5	64
1051 #define BNXT_RSS_TABLE_SIZE_P5		(BNXT_RSS_TABLE_ENTRIES_P5 * 4)
1052 #define BNXT_RSS_TABLE_MAX_TBL_P5	8
1053 #define BNXT_MAX_RSS_TABLE_SIZE_P5				\
1054 	(BNXT_RSS_TABLE_SIZE_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1055 #define BNXT_MAX_RSS_TABLE_ENTRIES_P5				\
1056 	(BNXT_RSS_TABLE_ENTRIES_P5 * BNXT_RSS_TABLE_MAX_TBL_P5)
1057 
1058 	u32		rx_mask;
1059 
1060 	u8		*mc_list;
1061 	int		mc_list_size;
1062 	int		mc_list_count;
1063 	dma_addr_t	mc_list_mapping;
1064 #define BNXT_MAX_MC_ADDRS	16
1065 
1066 	u32		flags;
1067 #define BNXT_VNIC_RSS_FLAG	1
1068 #define BNXT_VNIC_RFS_FLAG	2
1069 #define BNXT_VNIC_MCAST_FLAG	4
1070 #define BNXT_VNIC_UCAST_FLAG	8
1071 #define BNXT_VNIC_RFS_NEW_RSS_FLAG	0x10
1072 };
1073 
1074 struct bnxt_hw_resc {
1075 	u16	min_rsscos_ctxs;
1076 	u16	max_rsscos_ctxs;
1077 	u16	min_cp_rings;
1078 	u16	max_cp_rings;
1079 	u16	resv_cp_rings;
1080 	u16	min_tx_rings;
1081 	u16	max_tx_rings;
1082 	u16	resv_tx_rings;
1083 	u16	max_tx_sch_inputs;
1084 	u16	min_rx_rings;
1085 	u16	max_rx_rings;
1086 	u16	resv_rx_rings;
1087 	u16	min_hw_ring_grps;
1088 	u16	max_hw_ring_grps;
1089 	u16	resv_hw_ring_grps;
1090 	u16	min_l2_ctxs;
1091 	u16	max_l2_ctxs;
1092 	u16	min_vnics;
1093 	u16	max_vnics;
1094 	u16	resv_vnics;
1095 	u16	min_stat_ctxs;
1096 	u16	max_stat_ctxs;
1097 	u16	resv_stat_ctxs;
1098 	u16	max_nqs;
1099 	u16	max_irqs;
1100 	u16	resv_irqs;
1101 };
1102 
1103 #if defined(CONFIG_BNXT_SRIOV)
1104 struct bnxt_vf_info {
1105 	u16	fw_fid;
1106 	u8	mac_addr[ETH_ALEN];	/* PF assigned MAC Address */
1107 	u8	vf_mac_addr[ETH_ALEN];	/* VF assigned MAC address, only
1108 					 * stored by PF.
1109 					 */
1110 	u16	vlan;
1111 	u16	func_qcfg_flags;
1112 	u32	flags;
1113 #define BNXT_VF_QOS		0x1
1114 #define BNXT_VF_SPOOFCHK	0x2
1115 #define BNXT_VF_LINK_FORCED	0x4
1116 #define BNXT_VF_LINK_UP		0x8
1117 #define BNXT_VF_TRUST		0x10
1118 	u32	min_tx_rate;
1119 	u32	max_tx_rate;
1120 	void	*hwrm_cmd_req_addr;
1121 	dma_addr_t	hwrm_cmd_req_dma_addr;
1122 };
1123 #endif
1124 
1125 struct bnxt_pf_info {
1126 #define BNXT_FIRST_PF_FID	1
1127 #define BNXT_FIRST_VF_FID	128
1128 	u16	fw_fid;
1129 	u16	port_id;
1130 	u8	mac_addr[ETH_ALEN];
1131 	u32	first_vf_id;
1132 	u16	active_vfs;
1133 	u16	registered_vfs;
1134 	u16	max_vfs;
1135 	u32	max_encap_records;
1136 	u32	max_decap_records;
1137 	u32	max_tx_em_flows;
1138 	u32	max_tx_wm_flows;
1139 	u32	max_rx_em_flows;
1140 	u32	max_rx_wm_flows;
1141 	unsigned long	*vf_event_bmap;
1142 	u16	hwrm_cmd_req_pages;
1143 	u8	vf_resv_strategy;
1144 #define BNXT_VF_RESV_STRATEGY_MAXIMAL	0
1145 #define BNXT_VF_RESV_STRATEGY_MINIMAL	1
1146 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC	2
1147 	void			*hwrm_cmd_req_addr[4];
1148 	dma_addr_t		hwrm_cmd_req_dma_addr[4];
1149 	struct bnxt_vf_info	*vf;
1150 };
1151 
1152 struct bnxt_ntuple_filter {
1153 	struct hlist_node	hash;
1154 	u8			dst_mac_addr[ETH_ALEN];
1155 	u8			src_mac_addr[ETH_ALEN];
1156 	struct flow_keys	fkeys;
1157 	__le64			filter_id;
1158 	u16			sw_id;
1159 	u8			l2_fltr_idx;
1160 	u16			rxq;
1161 	u32			flow_id;
1162 	unsigned long		state;
1163 #define BNXT_FLTR_VALID		0
1164 #define BNXT_FLTR_UPDATE	1
1165 };
1166 
1167 struct bnxt_link_info {
1168 	u8			phy_type;
1169 	u8			media_type;
1170 	u8			transceiver;
1171 	u8			phy_addr;
1172 	u8			phy_link_status;
1173 #define BNXT_LINK_NO_LINK	PORT_PHY_QCFG_RESP_LINK_NO_LINK
1174 #define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL
1175 #define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK
1176 	u8			wire_speed;
1177 	u8			phy_state;
1178 #define BNXT_PHY_STATE_ENABLED		0
1179 #define BNXT_PHY_STATE_DISABLED		1
1180 
1181 	u8			link_state;
1182 #define BNXT_LINK_STATE_UNKNOWN	0
1183 #define BNXT_LINK_STATE_DOWN	1
1184 #define BNXT_LINK_STATE_UP	2
1185 #define BNXT_LINK_IS_UP(bp)	((bp)->link_info.link_state == BNXT_LINK_STATE_UP)
1186 	u8			duplex;
1187 #define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1188 #define BNXT_LINK_DUPLEX_FULL	PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1189 	u8			pause;
1190 #define BNXT_LINK_PAUSE_TX	PORT_PHY_QCFG_RESP_PAUSE_TX
1191 #define BNXT_LINK_PAUSE_RX	PORT_PHY_QCFG_RESP_PAUSE_RX
1192 #define BNXT_LINK_PAUSE_BOTH	(PORT_PHY_QCFG_RESP_PAUSE_RX | \
1193 				 PORT_PHY_QCFG_RESP_PAUSE_TX)
1194 	u8			lp_pause;
1195 	u8			auto_pause_setting;
1196 	u8			force_pause_setting;
1197 	u8			duplex_setting;
1198 	u8			auto_mode;
1199 #define BNXT_AUTO_MODE(mode)	((mode) > BNXT_LINK_AUTO_NONE && \
1200 				 (mode) <= BNXT_LINK_AUTO_MSK)
1201 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1202 #define BNXT_LINK_AUTO_ALLSPDS	PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1203 #define BNXT_LINK_AUTO_ONESPD	PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1204 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1205 #define BNXT_LINK_AUTO_MSK	PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1206 #define PHY_VER_LEN		3
1207 	u8			phy_ver[PHY_VER_LEN];
1208 	u16			link_speed;
1209 #define BNXT_LINK_SPEED_100MB	PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1210 #define BNXT_LINK_SPEED_1GB	PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1211 #define BNXT_LINK_SPEED_2GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1212 #define BNXT_LINK_SPEED_2_5GB	PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1213 #define BNXT_LINK_SPEED_10GB	PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1214 #define BNXT_LINK_SPEED_20GB	PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1215 #define BNXT_LINK_SPEED_25GB	PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1216 #define BNXT_LINK_SPEED_40GB	PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1217 #define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1218 #define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1219 	u16			support_speeds;
1220 	u16			support_pam4_speeds;
1221 	u16			auto_link_speeds;	/* fw adv setting */
1222 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1223 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1224 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1225 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1226 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1227 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1228 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1229 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1230 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1231 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1232 	u16			auto_pam4_link_speeds;
1233 #define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
1234 #define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
1235 #define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
1236 	u16			support_auto_speeds;
1237 	u16			support_pam4_auto_speeds;
1238 	u16			lp_auto_link_speeds;
1239 	u16			lp_auto_pam4_link_speeds;
1240 	u16			force_link_speed;
1241 	u16			force_pam4_link_speed;
1242 	u32			preemphasis;
1243 	u8			module_status;
1244 	u8			active_fec_sig_mode;
1245 	u16			fec_cfg;
1246 #define BNXT_FEC_NONE		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
1247 #define BNXT_FEC_AUTONEG_CAP	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
1248 #define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1249 #define BNXT_FEC_ENC_BASE_R_CAP	\
1250 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
1251 #define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1252 #define BNXT_FEC_ENC_RS_CAP	\
1253 	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
1254 #define BNXT_FEC_ENC_LLRS_CAP	\
1255 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |	\
1256 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
1257 #define BNXT_FEC_ENC_RS		\
1258 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |	\
1259 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |	\
1260 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
1261 #define BNXT_FEC_ENC_LLRS	\
1262 	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |	\
1263 	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
1264 
1265 	/* copy of requested setting from ethtool cmd */
1266 	u8			autoneg;
1267 #define BNXT_AUTONEG_SPEED		1
1268 #define BNXT_AUTONEG_FLOW_CTRL		2
1269 	u8			req_signal_mode;
1270 #define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
1271 #define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
1272 	u8			req_duplex;
1273 	u8			req_flow_ctrl;
1274 	u16			req_link_speed;
1275 	u16			advertising;	/* user adv setting */
1276 	u16			advertising_pam4;
1277 	bool			force_link_chng;
1278 
1279 	bool			phy_retry;
1280 	unsigned long		phy_retry_expires;
1281 
1282 	/* a copy of phy_qcfg output used to report link
1283 	 * info to VF
1284 	 */
1285 	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1286 };
1287 
1288 #define BNXT_FEC_RS544_ON					\
1289 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |		\
1290 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
1291 
1292 #define BNXT_FEC_RS544_OFF					\
1293 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |	\
1294 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
1295 
1296 #define BNXT_FEC_RS272_ON					\
1297 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |		\
1298 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
1299 
1300 #define BNXT_FEC_RS272_OFF					\
1301 	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |	\
1302 	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
1303 
1304 #define BNXT_PAM4_SUPPORTED(link_info)				\
1305 	((link_info)->support_pam4_speeds)
1306 
1307 #define BNXT_FEC_RS_ON(link_info)				\
1308 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1309 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1310 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1311 	  (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
1312 
1313 #define BNXT_FEC_LLRS_ON					\
1314 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\
1315 	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1316 	 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
1317 
1318 #define BNXT_FEC_RS_OFF(link_info)				\
1319 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |		\
1320 	 (BNXT_PAM4_SUPPORTED(link_info) ?			\
1321 	  (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
1322 
1323 #define BNXT_FEC_BASE_R_ON(link_info)				\
1324 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |		\
1325 	 BNXT_FEC_RS_OFF(link_info))
1326 
1327 #define BNXT_FEC_ALL_OFF(link_info)				\
1328 	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\
1329 	 BNXT_FEC_RS_OFF(link_info))
1330 
1331 #define BNXT_MAX_QUEUE	8
1332 
1333 struct bnxt_queue_info {
1334 	u8	queue_id;
1335 	u8	queue_profile;
1336 };
1337 
1338 #define BNXT_MAX_LED			4
1339 
1340 struct bnxt_led_info {
1341 	u8	led_id;
1342 	u8	led_type;
1343 	u8	led_group_id;
1344 	u8	unused;
1345 	__le16	led_state_caps;
1346 #define BNXT_LED_ALT_BLINK_CAP(x)	((x) &	\
1347 	cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1348 
1349 	__le16	led_color_caps;
1350 };
1351 
1352 #define BNXT_MAX_TEST	8
1353 
1354 struct bnxt_test_info {
1355 	u8 offline_mask;
1356 	u16 timeout;
1357 	char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1358 };
1359 
1360 #define CHIMP_REG_VIEW_ADDR				\
1361 	((bp->flags & BNXT_FLAG_CHIP_P5) ? 0x80000000 : 0xb1000000)
1362 
1363 #define BNXT_GRCPF_REG_CHIMP_COMM		0x0
1364 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER	0x100
1365 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT		0x400
1366 #define BNXT_CAG_REG_LEGACY_INT_STATUS		0x4014
1367 #define BNXT_CAG_REG_BASE			0x300000
1368 
1369 #define BNXT_GRC_REG_STATUS_P5			0x520
1370 
1371 #define BNXT_GRCPF_REG_KONG_COMM		0xA00
1372 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER	0xB00
1373 
1374 #define BNXT_GRC_REG_CHIP_NUM			0x48
1375 #define BNXT_GRC_REG_BASE			0x260000
1376 
1377 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER		0x640180c
1378 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER		0x6401810
1379 
1380 #define BNXT_GRC_BASE_MASK			0xfffff000
1381 #define BNXT_GRC_OFFSET_MASK			0x00000ffc
1382 
1383 struct bnxt_tc_flow_stats {
1384 	u64		packets;
1385 	u64		bytes;
1386 };
1387 
1388 #ifdef CONFIG_BNXT_FLOWER_OFFLOAD
1389 struct bnxt_flower_indr_block_cb_priv {
1390 	struct net_device *tunnel_netdev;
1391 	struct bnxt *bp;
1392 	struct list_head list;
1393 };
1394 #endif
1395 
1396 struct bnxt_tc_info {
1397 	bool				enabled;
1398 
1399 	/* hash table to store TC offloaded flows */
1400 	struct rhashtable		flow_table;
1401 	struct rhashtable_params	flow_ht_params;
1402 
1403 	/* hash table to store L2 keys of TC flows */
1404 	struct rhashtable		l2_table;
1405 	struct rhashtable_params	l2_ht_params;
1406 	/* hash table to store L2 keys for TC tunnel decap */
1407 	struct rhashtable		decap_l2_table;
1408 	struct rhashtable_params	decap_l2_ht_params;
1409 	/* hash table to store tunnel decap entries */
1410 	struct rhashtable		decap_table;
1411 	struct rhashtable_params	decap_ht_params;
1412 	/* hash table to store tunnel encap entries */
1413 	struct rhashtable		encap_table;
1414 	struct rhashtable_params	encap_ht_params;
1415 
1416 	/* lock to atomically add/del an l2 node when a flow is
1417 	 * added or deleted.
1418 	 */
1419 	struct mutex			lock;
1420 
1421 	/* Fields used for batching stats query */
1422 	struct rhashtable_iter		iter;
1423 #define BNXT_FLOW_STATS_BATCH_MAX	10
1424 	struct bnxt_tc_stats_batch {
1425 		void			  *flow_node;
1426 		struct bnxt_tc_flow_stats hw_stats;
1427 	} stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1428 
1429 	/* Stat counter mask (width) */
1430 	u64				bytes_mask;
1431 	u64				packets_mask;
1432 };
1433 
1434 struct bnxt_vf_rep_stats {
1435 	u64			packets;
1436 	u64			bytes;
1437 	u64			dropped;
1438 };
1439 
1440 struct bnxt_vf_rep {
1441 	struct bnxt			*bp;
1442 	struct net_device		*dev;
1443 	struct metadata_dst		*dst;
1444 	u16				vf_idx;
1445 	u16				tx_cfa_action;
1446 	u16				rx_cfa_code;
1447 
1448 	struct bnxt_vf_rep_stats	rx_stats;
1449 	struct bnxt_vf_rep_stats	tx_stats;
1450 };
1451 
1452 #define PTU_PTE_VALID             0x1UL
1453 #define PTU_PTE_LAST              0x2UL
1454 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1455 
1456 #define MAX_CTX_PAGES	(BNXT_PAGE_SIZE / 8)
1457 #define MAX_CTX_TOTAL_PAGES	(MAX_CTX_PAGES * MAX_CTX_PAGES)
1458 
1459 struct bnxt_ctx_pg_info {
1460 	u32		entries;
1461 	u32		nr_pages;
1462 	void		*ctx_pg_arr[MAX_CTX_PAGES];
1463 	dma_addr_t	ctx_dma_arr[MAX_CTX_PAGES];
1464 	struct bnxt_ring_mem_info ring_mem;
1465 	struct bnxt_ctx_pg_info **ctx_pg_tbl;
1466 };
1467 
1468 #define BNXT_MAX_TQM_SP_RINGS		1
1469 #define BNXT_MAX_TQM_FP_RINGS		8
1470 #define BNXT_MAX_TQM_RINGS		\
1471 	(BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS)
1472 
1473 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN	256
1474 
1475 #define BNXT_SET_CTX_PAGE_ATTR(attr)					\
1476 do {									\
1477 	if (BNXT_PAGE_SIZE == 0x2000)					\
1478 		attr = FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K;	\
1479 	else if (BNXT_PAGE_SIZE == 0x10000)				\
1480 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K;	\
1481 	else								\
1482 		attr = FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K;	\
1483 } while (0)
1484 
1485 struct bnxt_ctx_mem_info {
1486 	u32	qp_max_entries;
1487 	u16	qp_min_qp1_entries;
1488 	u16	qp_max_l2_entries;
1489 	u16	qp_entry_size;
1490 	u16	srq_max_l2_entries;
1491 	u32	srq_max_entries;
1492 	u16	srq_entry_size;
1493 	u16	cq_max_l2_entries;
1494 	u32	cq_max_entries;
1495 	u16	cq_entry_size;
1496 	u16	vnic_max_vnic_entries;
1497 	u16	vnic_max_ring_table_entries;
1498 	u16	vnic_entry_size;
1499 	u32	stat_max_entries;
1500 	u16	stat_entry_size;
1501 	u16	tqm_entry_size;
1502 	u32	tqm_min_entries_per_ring;
1503 	u32	tqm_max_entries_per_ring;
1504 	u32	mrav_max_entries;
1505 	u16	mrav_entry_size;
1506 	u16	tim_entry_size;
1507 	u32	tim_max_entries;
1508 	u16	mrav_num_entries_units;
1509 	u8	tqm_entries_multiple;
1510 	u8	tqm_fp_rings_count;
1511 
1512 	u32	flags;
1513 	#define BNXT_CTX_FLAG_INITED	0x01
1514 
1515 	struct bnxt_ctx_pg_info qp_mem;
1516 	struct bnxt_ctx_pg_info srq_mem;
1517 	struct bnxt_ctx_pg_info cq_mem;
1518 	struct bnxt_ctx_pg_info vnic_mem;
1519 	struct bnxt_ctx_pg_info stat_mem;
1520 	struct bnxt_ctx_pg_info mrav_mem;
1521 	struct bnxt_ctx_pg_info tim_mem;
1522 	struct bnxt_ctx_pg_info *tqm_mem[BNXT_MAX_TQM_RINGS];
1523 
1524 #define BNXT_CTX_MEM_INIT_QP	0
1525 #define BNXT_CTX_MEM_INIT_SRQ	1
1526 #define BNXT_CTX_MEM_INIT_CQ	2
1527 #define BNXT_CTX_MEM_INIT_VNIC	3
1528 #define BNXT_CTX_MEM_INIT_STAT	4
1529 #define BNXT_CTX_MEM_INIT_MRAV	5
1530 #define BNXT_CTX_MEM_INIT_MAX	6
1531 	struct bnxt_mem_init	mem_init[BNXT_CTX_MEM_INIT_MAX];
1532 };
1533 
1534 enum bnxt_health_severity {
1535 	SEVERITY_NORMAL = 0,
1536 	SEVERITY_WARNING,
1537 	SEVERITY_RECOVERABLE,
1538 	SEVERITY_FATAL,
1539 };
1540 
1541 enum bnxt_health_remedy {
1542 	REMEDY_DEVLINK_RECOVER,
1543 	REMEDY_POWER_CYCLE_DEVICE,
1544 	REMEDY_POWER_CYCLE_HOST,
1545 	REMEDY_FW_UPDATE,
1546 	REMEDY_HW_REPLACE,
1547 };
1548 
1549 struct bnxt_fw_health {
1550 	u32 flags;
1551 	u32 polling_dsecs;
1552 	u32 master_func_wait_dsecs;
1553 	u32 normal_func_wait_dsecs;
1554 	u32 post_reset_wait_dsecs;
1555 	u32 post_reset_max_wait_dsecs;
1556 	u32 regs[4];
1557 	u32 mapped_regs[4];
1558 #define BNXT_FW_HEALTH_REG		0
1559 #define BNXT_FW_HEARTBEAT_REG		1
1560 #define BNXT_FW_RESET_CNT_REG		2
1561 #define BNXT_FW_RESET_INPROG_REG	3
1562 	u32 fw_reset_inprog_reg_mask;
1563 	u32 last_fw_heartbeat;
1564 	u32 last_fw_reset_cnt;
1565 	u8 enabled:1;
1566 	u8 primary:1;
1567 	u8 status_reliable:1;
1568 	u8 resets_reliable:1;
1569 	u8 tmr_multiplier;
1570 	u8 tmr_counter;
1571 	u8 fw_reset_seq_cnt;
1572 	u32 fw_reset_seq_regs[16];
1573 	u32 fw_reset_seq_vals[16];
1574 	u32 fw_reset_seq_delay_msec[16];
1575 	u32 echo_req_data1;
1576 	u32 echo_req_data2;
1577 	struct devlink_health_reporter	*fw_reporter;
1578 	/* Protects severity and remedy */
1579 	struct mutex lock;
1580 	enum bnxt_health_severity severity;
1581 	enum bnxt_health_remedy remedy;
1582 	u32 arrests;
1583 	u32 discoveries;
1584 	u32 survivals;
1585 	u32 fatalities;
1586 	u32 diagnoses;
1587 };
1588 
1589 #define BNXT_FW_HEALTH_REG_TYPE_MASK	3
1590 #define BNXT_FW_HEALTH_REG_TYPE_CFG	0
1591 #define BNXT_FW_HEALTH_REG_TYPE_GRC	1
1592 #define BNXT_FW_HEALTH_REG_TYPE_BAR0	2
1593 #define BNXT_FW_HEALTH_REG_TYPE_BAR1	3
1594 
1595 #define BNXT_FW_HEALTH_REG_TYPE(reg)	((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK)
1596 #define BNXT_FW_HEALTH_REG_OFF(reg)	((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK)
1597 
1598 #define BNXT_FW_HEALTH_WIN_BASE		0x3000
1599 #define BNXT_FW_HEALTH_WIN_MAP_OFF	8
1600 
1601 #define BNXT_FW_HEALTH_WIN_OFF(reg)	(BNXT_FW_HEALTH_WIN_BASE +	\
1602 					 ((reg) & BNXT_GRC_OFFSET_MASK))
1603 
1604 #define BNXT_FW_STATUS_HEALTH_MSK	0xffff
1605 #define BNXT_FW_STATUS_HEALTHY		0x8000
1606 #define BNXT_FW_STATUS_SHUTDOWN		0x100000
1607 #define BNXT_FW_STATUS_RECOVERING	0x400000
1608 
1609 #define BNXT_FW_IS_HEALTHY(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\
1610 					 BNXT_FW_STATUS_HEALTHY)
1611 
1612 #define BNXT_FW_IS_BOOTING(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \
1613 					 BNXT_FW_STATUS_HEALTHY)
1614 
1615 #define BNXT_FW_IS_ERR(sts)		(((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \
1616 					 BNXT_FW_STATUS_HEALTHY)
1617 
1618 #define BNXT_FW_IS_RECOVERING(sts)	(BNXT_FW_IS_ERR(sts) &&		       \
1619 					 ((sts) & BNXT_FW_STATUS_RECOVERING))
1620 
1621 #define BNXT_FW_RETRY			5
1622 #define BNXT_FW_IF_RETRY		10
1623 
1624 enum board_idx {
1625 	BCM57301,
1626 	BCM57302,
1627 	BCM57304,
1628 	BCM57417_NPAR,
1629 	BCM58700,
1630 	BCM57311,
1631 	BCM57312,
1632 	BCM57402,
1633 	BCM57404,
1634 	BCM57406,
1635 	BCM57402_NPAR,
1636 	BCM57407,
1637 	BCM57412,
1638 	BCM57414,
1639 	BCM57416,
1640 	BCM57417,
1641 	BCM57412_NPAR,
1642 	BCM57314,
1643 	BCM57417_SFP,
1644 	BCM57416_SFP,
1645 	BCM57404_NPAR,
1646 	BCM57406_NPAR,
1647 	BCM57407_SFP,
1648 	BCM57407_NPAR,
1649 	BCM57414_NPAR,
1650 	BCM57416_NPAR,
1651 	BCM57452,
1652 	BCM57454,
1653 	BCM5745x_NPAR,
1654 	BCM57508,
1655 	BCM57504,
1656 	BCM57502,
1657 	BCM57508_NPAR,
1658 	BCM57504_NPAR,
1659 	BCM57502_NPAR,
1660 	BCM58802,
1661 	BCM58804,
1662 	BCM58808,
1663 	NETXTREME_E_VF,
1664 	NETXTREME_C_VF,
1665 	NETXTREME_S_VF,
1666 	NETXTREME_C_VF_HV,
1667 	NETXTREME_E_VF_HV,
1668 	NETXTREME_E_P5_VF,
1669 	NETXTREME_E_P5_VF_HV,
1670 };
1671 
1672 struct bnxt {
1673 	void __iomem		*bar0;
1674 	void __iomem		*bar1;
1675 	void __iomem		*bar2;
1676 
1677 	u32			reg_base;
1678 	u16			chip_num;
1679 #define CHIP_NUM_57301		0x16c8
1680 #define CHIP_NUM_57302		0x16c9
1681 #define CHIP_NUM_57304		0x16ca
1682 #define CHIP_NUM_58700		0x16cd
1683 #define CHIP_NUM_57402		0x16d0
1684 #define CHIP_NUM_57404		0x16d1
1685 #define CHIP_NUM_57406		0x16d2
1686 #define CHIP_NUM_57407		0x16d5
1687 
1688 #define CHIP_NUM_57311		0x16ce
1689 #define CHIP_NUM_57312		0x16cf
1690 #define CHIP_NUM_57314		0x16df
1691 #define CHIP_NUM_57317		0x16e0
1692 #define CHIP_NUM_57412		0x16d6
1693 #define CHIP_NUM_57414		0x16d7
1694 #define CHIP_NUM_57416		0x16d8
1695 #define CHIP_NUM_57417		0x16d9
1696 #define CHIP_NUM_57412L		0x16da
1697 #define CHIP_NUM_57414L		0x16db
1698 
1699 #define CHIP_NUM_5745X		0xd730
1700 #define CHIP_NUM_57452		0xc452
1701 #define CHIP_NUM_57454		0xc454
1702 
1703 #define CHIP_NUM_57508		0x1750
1704 #define CHIP_NUM_57504		0x1751
1705 #define CHIP_NUM_57502		0x1752
1706 
1707 #define CHIP_NUM_58802		0xd802
1708 #define CHIP_NUM_58804		0xd804
1709 #define CHIP_NUM_58808		0xd808
1710 
1711 	u8			chip_rev;
1712 
1713 #define CHIP_NUM_58818		0xd818
1714 
1715 #define BNXT_CHIP_NUM_5730X(chip_num)		\
1716 	((chip_num) >= CHIP_NUM_57301 &&	\
1717 	 (chip_num) <= CHIP_NUM_57304)
1718 
1719 #define BNXT_CHIP_NUM_5740X(chip_num)		\
1720 	(((chip_num) >= CHIP_NUM_57402 &&	\
1721 	  (chip_num) <= CHIP_NUM_57406) ||	\
1722 	 (chip_num) == CHIP_NUM_57407)
1723 
1724 #define BNXT_CHIP_NUM_5731X(chip_num)		\
1725 	((chip_num) == CHIP_NUM_57311 ||	\
1726 	 (chip_num) == CHIP_NUM_57312 ||	\
1727 	 (chip_num) == CHIP_NUM_57314 ||	\
1728 	 (chip_num) == CHIP_NUM_57317)
1729 
1730 #define BNXT_CHIP_NUM_5741X(chip_num)		\
1731 	((chip_num) >= CHIP_NUM_57412 &&	\
1732 	 (chip_num) <= CHIP_NUM_57414L)
1733 
1734 #define BNXT_CHIP_NUM_58700(chip_num)		\
1735 	 ((chip_num) == CHIP_NUM_58700)
1736 
1737 #define BNXT_CHIP_NUM_5745X(chip_num)		\
1738 	((chip_num) == CHIP_NUM_5745X ||	\
1739 	 (chip_num) == CHIP_NUM_57452 ||	\
1740 	 (chip_num) == CHIP_NUM_57454)
1741 
1742 
1743 #define BNXT_CHIP_NUM_57X0X(chip_num)		\
1744 	(BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1745 
1746 #define BNXT_CHIP_NUM_57X1X(chip_num)		\
1747 	(BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1748 
1749 #define BNXT_CHIP_NUM_588XX(chip_num)		\
1750 	((chip_num) == CHIP_NUM_58802 ||	\
1751 	 (chip_num) == CHIP_NUM_58804 ||        \
1752 	 (chip_num) == CHIP_NUM_58808)
1753 
1754 #define BNXT_VPD_FLD_LEN	32
1755 	char			board_partno[BNXT_VPD_FLD_LEN];
1756 	char			board_serialno[BNXT_VPD_FLD_LEN];
1757 
1758 	struct net_device	*dev;
1759 	struct pci_dev		*pdev;
1760 
1761 	atomic_t		intr_sem;
1762 
1763 	u32			flags;
1764 	#define BNXT_FLAG_CHIP_P5	0x1
1765 	#define BNXT_FLAG_VF		0x2
1766 	#define BNXT_FLAG_LRO		0x4
1767 #ifdef CONFIG_INET
1768 	#define BNXT_FLAG_GRO		0x8
1769 #else
1770 	/* Cannot support hardware GRO if CONFIG_INET is not set */
1771 	#define BNXT_FLAG_GRO		0x0
1772 #endif
1773 	#define BNXT_FLAG_TPA		(BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1774 	#define BNXT_FLAG_JUMBO		0x10
1775 	#define BNXT_FLAG_STRIP_VLAN	0x20
1776 	#define BNXT_FLAG_AGG_RINGS	(BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1777 					 BNXT_FLAG_LRO)
1778 	#define BNXT_FLAG_USING_MSIX	0x40
1779 	#define BNXT_FLAG_MSIX_CAP	0x80
1780 	#define BNXT_FLAG_RFS		0x100
1781 	#define BNXT_FLAG_SHARED_RINGS	0x200
1782 	#define BNXT_FLAG_PORT_STATS	0x400
1783 	#define BNXT_FLAG_UDP_RSS_CAP	0x800
1784 	#define BNXT_FLAG_NEW_RSS_CAP	0x2000
1785 	#define BNXT_FLAG_WOL_CAP	0x4000
1786 	#define BNXT_FLAG_ROCEV1_CAP	0x8000
1787 	#define BNXT_FLAG_ROCEV2_CAP	0x10000
1788 	#define BNXT_FLAG_ROCE_CAP	(BNXT_FLAG_ROCEV1_CAP |	\
1789 					 BNXT_FLAG_ROCEV2_CAP)
1790 	#define BNXT_FLAG_NO_AGG_RINGS	0x20000
1791 	#define BNXT_FLAG_RX_PAGE_MODE	0x40000
1792 	#define BNXT_FLAG_CHIP_SR2	0x80000
1793 	#define BNXT_FLAG_MULTI_HOST	0x100000
1794 	#define BNXT_FLAG_DSN_VALID	0x200000
1795 	#define BNXT_FLAG_DOUBLE_DB	0x400000
1796 	#define BNXT_FLAG_CHIP_NITRO_A0	0x1000000
1797 	#define BNXT_FLAG_DIM		0x2000000
1798 	#define BNXT_FLAG_ROCE_MIRROR_CAP	0x4000000
1799 	#define BNXT_FLAG_PORT_STATS_EXT	0x10000000
1800 
1801 	#define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |		\
1802 					    BNXT_FLAG_RFS |		\
1803 					    BNXT_FLAG_STRIP_VLAN)
1804 
1805 #define BNXT_PF(bp)		(!((bp)->flags & BNXT_FLAG_VF))
1806 #define BNXT_VF(bp)		((bp)->flags & BNXT_FLAG_VF)
1807 #define BNXT_NPAR(bp)		((bp)->port_partition_type)
1808 #define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)
1809 #define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1810 #define BNXT_SH_PORT_CFG_OK(bp)	(BNXT_PF(bp) &&				\
1811 				 ((bp)->phy_flags & BNXT_PHY_FL_SHARED_PORT_CFG))
1812 #define BNXT_PHY_CFG_ABLE(bp)	((BNXT_SINGLE_PF(bp) ||			\
1813 				  BNXT_SH_PORT_CFG_OK(bp)) &&		\
1814 				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
1815 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1816 #define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1817 #define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\
1818 				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\
1819 				  (bp)->max_tpa_v2) && !is_kdump_kernel())
1820 
1821 #define BNXT_CHIP_SR2(bp)			\
1822 	((bp)->chip_num == CHIP_NUM_58818)
1823 
1824 #define BNXT_CHIP_P5_THOR(bp)			\
1825 	((bp)->chip_num == CHIP_NUM_57508 ||	\
1826 	 (bp)->chip_num == CHIP_NUM_57504 ||	\
1827 	 (bp)->chip_num == CHIP_NUM_57502)
1828 
1829 /* Chip class phase 5 */
1830 #define BNXT_CHIP_P5(bp)			\
1831 	(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
1832 
1833 /* Chip class phase 4.x */
1834 #define BNXT_CHIP_P4(bp)			\
1835 	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
1836 	 BNXT_CHIP_NUM_5745X((bp)->chip_num) ||	\
1837 	 BNXT_CHIP_NUM_588XX((bp)->chip_num) ||	\
1838 	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
1839 	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1840 
1841 #define BNXT_CHIP_P4_PLUS(bp)			\
1842 	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1843 
1844 	struct bnxt_en_dev	*edev;
1845 
1846 	struct bnxt_napi	**bnapi;
1847 
1848 	struct bnxt_rx_ring_info	*rx_ring;
1849 	struct bnxt_tx_ring_info	*tx_ring;
1850 	u16			*tx_ring_map;
1851 
1852 	struct sk_buff *	(*gro_func)(struct bnxt_tpa_info *, int, int,
1853 					    struct sk_buff *);
1854 
1855 	struct sk_buff *	(*rx_skb_func)(struct bnxt *,
1856 					       struct bnxt_rx_ring_info *,
1857 					       u16, void *, u8 *, dma_addr_t,
1858 					       unsigned int);
1859 
1860 	u16			max_tpa_v2;
1861 	u16			max_tpa;
1862 	u32			rx_buf_size;
1863 	u32			rx_buf_use_size;	/* useable size */
1864 	u16			rx_offset;
1865 	u16			rx_dma_offset;
1866 	enum dma_data_direction	rx_dir;
1867 	u32			rx_ring_size;
1868 	u32			rx_agg_ring_size;
1869 	u32			rx_copy_thresh;
1870 	u32			rx_ring_mask;
1871 	u32			rx_agg_ring_mask;
1872 	int			rx_nr_pages;
1873 	int			rx_agg_nr_pages;
1874 	int			rx_nr_rings;
1875 	int			rsscos_nr_ctxs;
1876 
1877 	u32			tx_ring_size;
1878 	u32			tx_ring_mask;
1879 	int			tx_nr_pages;
1880 	int			tx_nr_rings;
1881 	int			tx_nr_rings_per_tc;
1882 	int			tx_nr_rings_xdp;
1883 
1884 	int			tx_wake_thresh;
1885 	int			tx_push_thresh;
1886 	int			tx_push_size;
1887 
1888 	u32			cp_ring_size;
1889 	u32			cp_ring_mask;
1890 	u32			cp_bit;
1891 	int			cp_nr_pages;
1892 	int			cp_nr_rings;
1893 
1894 	/* grp_info indexed by completion ring index */
1895 	struct bnxt_ring_grp_info	*grp_info;
1896 	struct bnxt_vnic_info	*vnic_info;
1897 	int			nr_vnics;
1898 	u16			*rss_indir_tbl;
1899 	u16			rss_indir_tbl_entries;
1900 	u32			rss_hash_cfg;
1901 
1902 	u16			max_mtu;
1903 	u8			max_tc;
1904 	u8			max_lltc;	/* lossless TCs */
1905 	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];
1906 	u8			tc_to_qidx[BNXT_MAX_QUEUE];
1907 	u8			q_ids[BNXT_MAX_QUEUE];
1908 	u8			max_q;
1909 
1910 	unsigned int		current_interval;
1911 #define BNXT_TIMER_INTERVAL	HZ
1912 
1913 	struct timer_list	timer;
1914 
1915 	unsigned long		state;
1916 #define BNXT_STATE_OPEN		0
1917 #define BNXT_STATE_IN_SP_TASK	1
1918 #define BNXT_STATE_READ_STATS	2
1919 #define BNXT_STATE_FW_RESET_DET 3
1920 #define BNXT_STATE_IN_FW_RESET	4
1921 #define BNXT_STATE_ABORT_ERR	5
1922 #define BNXT_STATE_FW_FATAL_COND	6
1923 #define BNXT_STATE_DRV_REGISTERED	7
1924 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN	8
1925 #define BNXT_STATE_NAPI_DISABLED	9
1926 #define BNXT_STATE_L2_FILTER_RETRY	10
1927 #define BNXT_STATE_FW_ACTIVATE		11
1928 #define BNXT_STATE_RECOVER		12
1929 #define BNXT_STATE_FW_NON_FATAL_COND	13
1930 #define BNXT_STATE_FW_ACTIVATE_RESET	14
1931 #define BNXT_STATE_HALF_OPEN		15	/* For offline ethtool tests */
1932 
1933 #define BNXT_NO_FW_ACCESS(bp)					\
1934 	(test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) ||	\
1935 	 pci_channel_offline((bp)->pdev))
1936 
1937 	struct bnxt_irq	*irq_tbl;
1938 	int			total_irqs;
1939 	u8			mac_addr[ETH_ALEN];
1940 
1941 #ifdef CONFIG_BNXT_DCB
1942 	struct ieee_pfc		*ieee_pfc;
1943 	struct ieee_ets		*ieee_ets;
1944 	u8			dcbx_cap;
1945 	u8			default_pri;
1946 	u8			max_dscp_value;
1947 #endif /* CONFIG_BNXT_DCB */
1948 
1949 	u32			msg_enable;
1950 
1951 	u32			fw_cap;
1952 	#define BNXT_FW_CAP_SHORT_CMD			0x00000001
1953 	#define BNXT_FW_CAP_LLDP_AGENT			0x00000002
1954 	#define BNXT_FW_CAP_DCBX_AGENT			0x00000004
1955 	#define BNXT_FW_CAP_NEW_RM			0x00000008
1956 	#define BNXT_FW_CAP_IF_CHANGE			0x00000010
1957 	#define BNXT_FW_CAP_KONG_MB_CHNL		0x00000080
1958 	#define BNXT_FW_CAP_OVS_64BIT_HANDLE		0x00000400
1959 	#define BNXT_FW_CAP_TRUSTED_VF			0x00000800
1960 	#define BNXT_FW_CAP_ERROR_RECOVERY		0x00002000
1961 	#define BNXT_FW_CAP_PKG_VER			0x00004000
1962 	#define BNXT_FW_CAP_CFA_ADV_FLOW		0x00008000
1963 	#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2	0x00010000
1964 	#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED	0x00020000
1965 	#define BNXT_FW_CAP_EXT_STATS_SUPPORTED		0x00040000
1966 	#define BNXT_FW_CAP_ERR_RECOVER_RELOAD		0x00100000
1967 	#define BNXT_FW_CAP_HOT_RESET			0x00200000
1968 	#define BNXT_FW_CAP_PTP_RTC			0x00400000
1969 	#define BNXT_FW_CAP_VLAN_RX_STRIP		0x01000000
1970 	#define BNXT_FW_CAP_VLAN_TX_INSERT		0x02000000
1971 	#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED	0x04000000
1972 	#define BNXT_FW_CAP_LIVEPATCH			0x08000000
1973 	#define BNXT_FW_CAP_PTP_PPS			0x10000000
1974 	#define BNXT_FW_CAP_HOT_RESET_IF		0x20000000
1975 	#define BNXT_FW_CAP_RING_MONITOR		0x40000000
1976 	#define BNXT_FW_CAP_DBG_QCAPS			0x80000000
1977 
1978 	u32			fw_dbg_cap;
1979 
1980 #define BNXT_NEW_RM(bp)		((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1981 	u32			hwrm_spec_code;
1982 	u16			hwrm_cmd_seq;
1983 	u16                     hwrm_cmd_kong_seq;
1984 	struct dma_pool		*hwrm_dma_pool;
1985 	struct hlist_head	hwrm_pending_list;
1986 
1987 	struct rtnl_link_stats64	net_stats_prev;
1988 	struct bnxt_stats_mem	port_stats;
1989 	struct bnxt_stats_mem	rx_port_stats_ext;
1990 	struct bnxt_stats_mem	tx_port_stats_ext;
1991 	u16			fw_rx_stats_ext_size;
1992 	u16			fw_tx_stats_ext_size;
1993 	u16			hw_ring_stats_size;
1994 	u8			pri2cos_idx[8];
1995 	u8			pri2cos_valid;
1996 
1997 	u16			hwrm_max_req_len;
1998 	u16			hwrm_max_ext_req_len;
1999 	unsigned int		hwrm_cmd_timeout;
2000 	unsigned int		hwrm_cmd_max_timeout;
2001 	struct mutex		hwrm_cmd_lock;	/* serialize hwrm messages */
2002 	struct hwrm_ver_get_output	ver_resp;
2003 #define FW_VER_STR_LEN		32
2004 #define BC_HWRM_STR_LEN		21
2005 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
2006 	char			fw_ver_str[FW_VER_STR_LEN];
2007 	char			hwrm_ver_supp[FW_VER_STR_LEN];
2008 	char			nvm_cfg_ver[FW_VER_STR_LEN];
2009 	u64			fw_ver_code;
2010 #define BNXT_FW_VER_CODE(maj, min, bld, rsv)			\
2011 	((u64)(maj) << 48 | (u64)(min) << 32 | (u64)(bld) << 16 | (rsv))
2012 #define BNXT_FW_MAJ(bp)		((bp)->fw_ver_code >> 48)
2013 
2014 	u16			vxlan_fw_dst_port_id;
2015 	u16			nge_fw_dst_port_id;
2016 	__be16			vxlan_port;
2017 	__be16			nge_port;
2018 	u8			port_partition_type;
2019 	u8			port_count;
2020 	u16			br_mode;
2021 
2022 	struct bnxt_coal_cap	coal_cap;
2023 	struct bnxt_coal	rx_coal;
2024 	struct bnxt_coal	tx_coal;
2025 
2026 	u32			stats_coal_ticks;
2027 #define BNXT_DEF_STATS_COAL_TICKS	 1000000
2028 #define BNXT_MIN_STATS_COAL_TICKS	  250000
2029 #define BNXT_MAX_STATS_COAL_TICKS	 1000000
2030 
2031 	struct work_struct	sp_task;
2032 	unsigned long		sp_event;
2033 #define BNXT_RX_MASK_SP_EVENT		0
2034 #define BNXT_RX_NTP_FLTR_SP_EVENT	1
2035 #define BNXT_LINK_CHNG_SP_EVENT		2
2036 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT	3
2037 #define BNXT_RESET_TASK_SP_EVENT	6
2038 #define BNXT_RST_RING_SP_EVENT		7
2039 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT	8
2040 #define BNXT_PERIODIC_STATS_SP_EVENT	9
2041 #define BNXT_HWRM_PORT_MODULE_SP_EVENT	10
2042 #define BNXT_RESET_TASK_SILENT_SP_EVENT	11
2043 #define BNXT_LINK_SPEED_CHNG_SP_EVENT	14
2044 #define BNXT_FLOW_STATS_SP_EVENT	15
2045 #define BNXT_UPDATE_PHY_SP_EVENT	16
2046 #define BNXT_RING_COAL_NOW_SP_EVENT	17
2047 #define BNXT_FW_RESET_NOTIFY_SP_EVENT	18
2048 #define BNXT_FW_EXCEPTION_SP_EVENT	19
2049 #define BNXT_LINK_CFG_CHANGE_SP_EVENT	21
2050 #define BNXT_FW_ECHO_REQUEST_SP_EVENT	23
2051 
2052 	struct delayed_work	fw_reset_task;
2053 	int			fw_reset_state;
2054 #define BNXT_FW_RESET_STATE_POLL_VF	1
2055 #define BNXT_FW_RESET_STATE_RESET_FW	2
2056 #define BNXT_FW_RESET_STATE_ENABLE_DEV	3
2057 #define BNXT_FW_RESET_STATE_POLL_FW	4
2058 #define BNXT_FW_RESET_STATE_OPENING	5
2059 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN	6
2060 
2061 	u16			fw_reset_min_dsecs;
2062 #define BNXT_DFLT_FW_RST_MIN_DSECS	20
2063 	u16			fw_reset_max_dsecs;
2064 #define BNXT_DFLT_FW_RST_MAX_DSECS	60
2065 	unsigned long		fw_reset_timestamp;
2066 
2067 	struct bnxt_fw_health	*fw_health;
2068 
2069 	struct bnxt_hw_resc	hw_resc;
2070 	struct bnxt_pf_info	pf;
2071 	struct bnxt_ctx_mem_info	*ctx;
2072 #ifdef CONFIG_BNXT_SRIOV
2073 	int			nr_vfs;
2074 	struct bnxt_vf_info	vf;
2075 	wait_queue_head_t	sriov_cfg_wait;
2076 	bool			sriov_cfg;
2077 #define BNXT_SRIOV_CFG_WAIT_TMO	msecs_to_jiffies(10000)
2078 #endif
2079 
2080 #if BITS_PER_LONG == 32
2081 	/* ensure atomic 64-bit doorbell writes on 32-bit systems. */
2082 	spinlock_t		db_lock;
2083 #endif
2084 	int			db_size;
2085 
2086 #define BNXT_NTP_FLTR_MAX_FLTR	4096
2087 #define BNXT_NTP_FLTR_HASH_SIZE	512
2088 #define BNXT_NTP_FLTR_HASH_MASK	(BNXT_NTP_FLTR_HASH_SIZE - 1)
2089 	struct hlist_head	ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
2090 	spinlock_t		ntp_fltr_lock;	/* for hash table add, del */
2091 
2092 	unsigned long		*ntp_fltr_bmap;
2093 	int			ntp_fltr_count;
2094 
2095 	/* To protect link related settings during link changes and
2096 	 * ethtool settings changes.
2097 	 */
2098 	struct mutex		link_lock;
2099 	struct bnxt_link_info	link_info;
2100 	struct ethtool_eee	eee;
2101 	u32			lpi_tmr_lo;
2102 	u32			lpi_tmr_hi;
2103 
2104 	/* copied from flags and flags2 in hwrm_port_phy_qcaps_output */
2105 	u32			phy_flags;
2106 #define BNXT_PHY_FL_EEE_CAP		PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED
2107 #define BNXT_PHY_FL_EXT_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED
2108 #define BNXT_PHY_FL_AN_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED
2109 #define BNXT_PHY_FL_SHARED_PORT_CFG	PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED
2110 #define BNXT_PHY_FL_PORT_STATS_NO_RESET	PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET
2111 #define BNXT_PHY_FL_NO_PHY_LPBK		PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED
2112 #define BNXT_PHY_FL_FW_MANAGED_LKDN	PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN
2113 #define BNXT_PHY_FL_NO_FCS		PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
2114 #define BNXT_PHY_FL_NO_PAUSE		(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)
2115 #define BNXT_PHY_FL_NO_PFC		(PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED << 8)
2116 
2117 	u8			num_tests;
2118 	struct bnxt_test_info	*test_info;
2119 
2120 	u8			wol_filter_id;
2121 	u8			wol;
2122 
2123 	u8			num_leds;
2124 	struct bnxt_led_info	leds[BNXT_MAX_LED];
2125 	u16			dump_flag;
2126 #define BNXT_DUMP_LIVE		0
2127 #define BNXT_DUMP_CRASH		1
2128 
2129 	struct bpf_prog		*xdp_prog;
2130 
2131 	struct bnxt_ptp_cfg	*ptp_cfg;
2132 
2133 	/* devlink interface and vf-rep structs */
2134 	struct devlink		*dl;
2135 	struct devlink_port	dl_port;
2136 	enum devlink_eswitch_mode eswitch_mode;
2137 	struct bnxt_vf_rep	**vf_reps; /* array of vf-rep ptrs */
2138 	u16			*cfa_code_map; /* cfa_code -> vf_idx map */
2139 	u8			dsn[8];
2140 	struct bnxt_tc_info	*tc_info;
2141 	struct list_head	tc_indr_block_list;
2142 	struct dentry		*debugfs_pdev;
2143 	struct device		*hwmon_dev;
2144 	enum board_idx		board_idx;
2145 };
2146 
2147 #define BNXT_NUM_RX_RING_STATS			8
2148 #define BNXT_NUM_TX_RING_STATS			8
2149 #define BNXT_NUM_TPA_RING_STATS			4
2150 #define BNXT_NUM_TPA_RING_STATS_P5		5
2151 #define BNXT_NUM_TPA_RING_STATS_P5_SR2		6
2152 
2153 #define BNXT_RING_STATS_SIZE_P5					\
2154 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2155 	  BNXT_NUM_TPA_RING_STATS_P5) * 8)
2156 
2157 #define BNXT_RING_STATS_SIZE_P5_SR2				\
2158 	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\
2159 	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
2160 
2161 #define BNXT_GET_RING_STATS64(sw, counter)		\
2162 	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
2163 
2164 #define BNXT_GET_RX_PORT_STATS64(sw, counter)		\
2165 	(*((sw) + offsetof(struct rx_port_stats, counter) / 8))
2166 
2167 #define BNXT_GET_TX_PORT_STATS64(sw, counter)		\
2168 	(*((sw) + offsetof(struct tx_port_stats, counter) / 8))
2169 
2170 #define BNXT_PORT_STATS_SIZE				\
2171 	(sizeof(struct rx_port_stats) + sizeof(struct tx_port_stats) + 1024)
2172 
2173 #define BNXT_TX_PORT_STATS_BYTE_OFFSET			\
2174 	(sizeof(struct rx_port_stats) + 512)
2175 
2176 #define BNXT_RX_STATS_OFFSET(counter)			\
2177 	(offsetof(struct rx_port_stats, counter) / 8)
2178 
2179 #define BNXT_TX_STATS_OFFSET(counter)			\
2180 	((offsetof(struct tx_port_stats, counter) +	\
2181 	  BNXT_TX_PORT_STATS_BYTE_OFFSET) / 8)
2182 
2183 #define BNXT_RX_STATS_EXT_OFFSET(counter)		\
2184 	(offsetof(struct rx_port_stats_ext, counter) / 8)
2185 
2186 #define BNXT_RX_STATS_EXT_NUM_LEGACY                   \
2187 	BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks)
2188 
2189 #define BNXT_TX_STATS_EXT_OFFSET(counter)		\
2190 	(offsetof(struct tx_port_stats_ext, counter) / 8)
2191 
2192 #define BNXT_HW_FEATURE_VLAN_ALL_RX				\
2193 	(NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)
2194 #define BNXT_HW_FEATURE_VLAN_ALL_TX				\
2195 	(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_STAG_TX)
2196 
2197 #define I2C_DEV_ADDR_A0				0xa0
2198 #define I2C_DEV_ADDR_A2				0xa2
2199 #define SFF_DIAG_SUPPORT_OFFSET			0x5c
2200 #define SFF_MODULE_ID_SFP			0x3
2201 #define SFF_MODULE_ID_QSFP			0xc
2202 #define SFF_MODULE_ID_QSFP_PLUS			0xd
2203 #define SFF_MODULE_ID_QSFP28			0x11
2204 #define BNXT_MAX_PHY_I2C_RESP_SIZE		64
2205 
2206 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
2207 {
2208 	/* Tell compiler to fetch tx indices from memory. */
2209 	barrier();
2210 
2211 	return bp->tx_ring_size -
2212 		((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
2213 }
2214 
2215 static inline void bnxt_writeq(struct bnxt *bp, u64 val,
2216 			       volatile void __iomem *addr)
2217 {
2218 #if BITS_PER_LONG == 32
2219 	spin_lock(&bp->db_lock);
2220 	lo_hi_writeq(val, addr);
2221 	spin_unlock(&bp->db_lock);
2222 #else
2223 	writeq(val, addr);
2224 #endif
2225 }
2226 
2227 static inline void bnxt_writeq_relaxed(struct bnxt *bp, u64 val,
2228 				       volatile void __iomem *addr)
2229 {
2230 #if BITS_PER_LONG == 32
2231 	spin_lock(&bp->db_lock);
2232 	lo_hi_writeq_relaxed(val, addr);
2233 	spin_unlock(&bp->db_lock);
2234 #else
2235 	writeq_relaxed(val, addr);
2236 #endif
2237 }
2238 
2239 /* For TX and RX ring doorbells with no ordering guarantee*/
2240 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
2241 					 struct bnxt_db_info *db, u32 idx)
2242 {
2243 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2244 		bnxt_writeq_relaxed(bp, db->db_key64 | idx, db->doorbell);
2245 	} else {
2246 		u32 db_val = db->db_key32 | idx;
2247 
2248 		writel_relaxed(db_val, db->doorbell);
2249 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2250 			writel_relaxed(db_val, db->doorbell);
2251 	}
2252 }
2253 
2254 /* For TX and RX ring doorbells */
2255 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
2256 				 u32 idx)
2257 {
2258 	if (bp->flags & BNXT_FLAG_CHIP_P5) {
2259 		bnxt_writeq(bp, db->db_key64 | idx, db->doorbell);
2260 	} else {
2261 		u32 db_val = db->db_key32 | idx;
2262 
2263 		writel(db_val, db->doorbell);
2264 		if (bp->flags & BNXT_FLAG_DOUBLE_DB)
2265 			writel(db_val, db->doorbell);
2266 	}
2267 }
2268 
2269 /* Must hold rtnl_lock */
2270 static inline bool bnxt_sriov_cfg(struct bnxt *bp)
2271 {
2272 #if defined(CONFIG_BNXT_SRIOV)
2273 	return BNXT_PF(bp) && (bp->pf.active_vfs || bp->sriov_cfg);
2274 #else
2275 	return false;
2276 #endif
2277 }
2278 
2279 extern const u16 bnxt_lhint_arr[];
2280 
2281 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
2282 		       u16 prod, gfp_t gfp);
2283 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
2284 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx);
2285 void bnxt_set_tpa_flags(struct bnxt *bp);
2286 void bnxt_set_ring_params(struct bnxt *);
2287 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
2288 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap,
2289 			    int bmap_size, bool async_only);
2290 int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp);
2291 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings);
2292 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
2293 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
2294 int bnxt_nq_rings_in_use(struct bnxt *bp);
2295 int bnxt_hwrm_set_coal(struct bnxt *);
2296 void bnxt_free_ctx_mem(struct bnxt *bp);
2297 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
2298 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
2299 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
2300 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
2301 int bnxt_get_avail_msix(struct bnxt *bp, int num);
2302 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
2303 void bnxt_tx_disable(struct bnxt *bp);
2304 void bnxt_tx_enable(struct bnxt *bp);
2305 void bnxt_report_link(struct bnxt *bp);
2306 int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
2307 int bnxt_hwrm_set_pause(struct bnxt *);
2308 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
2309 int bnxt_cancel_reservations(struct bnxt *bp, bool fw_reset);
2310 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
2311 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
2312 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
2313 int bnxt_hwrm_fw_set_time(struct bnxt *);
2314 int bnxt_open_nic(struct bnxt *, bool, bool);
2315 int bnxt_half_open_nic(struct bnxt *bp);
2316 void bnxt_half_close_nic(struct bnxt *bp);
2317 void bnxt_reenable_sriov(struct bnxt *bp);
2318 int bnxt_close_nic(struct bnxt *, bool, bool);
2319 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
2320 			 u32 *reg_buf);
2321 void bnxt_fw_exception(struct bnxt *bp);
2322 void bnxt_fw_reset(struct bnxt *bp);
2323 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
2324 		     int tx_xdp);
2325 int bnxt_fw_init_one(struct bnxt *bp);
2326 bool bnxt_hwrm_reset_permitted(struct bnxt *bp);
2327 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
2328 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
2329 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
2330 int bnxt_get_port_parent_id(struct net_device *dev,
2331 			    struct netdev_phys_item_id *ppid);
2332 void bnxt_dim_work(struct work_struct *work);
2333 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
2334 void bnxt_print_device_info(struct bnxt *bp);
2335 #endif
2336