1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_H 12 #define BNXT_H 13 14 #define DRV_MODULE_NAME "bnxt_en" 15 #define DRV_MODULE_VERSION "1.10.0" 16 17 #define DRV_VER_MAJ 1 18 #define DRV_VER_MIN 10 19 #define DRV_VER_UPD 0 20 21 #include <linux/interrupt.h> 22 #include <linux/rhashtable.h> 23 #include <net/devlink.h> 24 #include <net/dst_metadata.h> 25 #include <net/switchdev.h> 26 #include <net/xdp.h> 27 #include <linux/net_dim.h> 28 29 struct tx_bd { 30 __le32 tx_bd_len_flags_type; 31 #define TX_BD_TYPE (0x3f << 0) 32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 34 #define TX_BD_FLAGS_PACKET_END (1 << 6) 35 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 38 #define TX_BD_FLAGS_LHINT (3 << 13) 39 #define TX_BD_FLAGS_LHINT_SHIFT 13 40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 44 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 45 #define TX_BD_LEN (0xffff << 16) 46 #define TX_BD_LEN_SHIFT 16 47 48 u32 tx_bd_opaque; 49 __le64 tx_bd_haddr; 50 } __packed; 51 52 struct tx_bd_ext { 53 __le32 tx_bd_hsize_lflags; 54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) 55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1) 56 #define TX_BD_FLAGS_NO_CRC (1 << 2) 57 #define TX_BD_FLAGS_STAMP (1 << 3) 58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) 59 #define TX_BD_FLAGS_LSO (1 << 5) 60 #define TX_BD_FLAGS_IPID_FMT (1 << 6) 61 #define TX_BD_FLAGS_T_IPID (1 << 7) 62 #define TX_BD_HSIZE (0xff << 16) 63 #define TX_BD_HSIZE_SHIFT 16 64 65 __le32 tx_bd_mss; 66 __le32 tx_bd_cfa_action; 67 #define TX_BD_CFA_ACTION (0xffff << 16) 68 #define TX_BD_CFA_ACTION_SHIFT 16 69 70 __le32 tx_bd_cfa_meta; 71 #define TX_BD_CFA_META_MASK 0xfffffff 72 #define TX_BD_CFA_META_VID_MASK 0xfff 73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12) 74 #define TX_BD_CFA_META_PRI_SHIFT 12 75 #define TX_BD_CFA_META_TPID_MASK (3 << 16) 76 #define TX_BD_CFA_META_TPID_SHIFT 16 77 #define TX_BD_CFA_META_KEY (0xf << 28) 78 #define TX_BD_CFA_META_KEY_SHIFT 28 79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28) 80 }; 81 82 struct rx_bd { 83 __le32 rx_bd_len_flags_type; 84 #define RX_BD_TYPE (0x3f << 0) 85 #define RX_BD_TYPE_RX_PACKET_BD 0x4 86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 87 #define RX_BD_TYPE_RX_AGG_BD 0x6 88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 92 #define RX_BD_FLAGS_SOP (1 << 6) 93 #define RX_BD_FLAGS_EOP (1 << 7) 94 #define RX_BD_FLAGS_BUFFERS (3 << 8) 95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 99 #define RX_BD_LEN (0xffff << 16) 100 #define RX_BD_LEN_SHIFT 16 101 102 u32 rx_bd_opaque; 103 __le64 rx_bd_haddr; 104 }; 105 106 struct tx_cmp { 107 __le32 tx_cmp_flags_type; 108 #define CMP_TYPE (0x3f << 0) 109 #define CMP_TYPE_TX_L2_CMP 0 110 #define CMP_TYPE_RX_L2_CMP 17 111 #define CMP_TYPE_RX_AGG_CMP 18 112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 114 #define CMP_TYPE_STATUS_CMP 32 115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 117 #define CMP_TYPE_ERROR_STATUS 48 118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 123 124 #define TX_CMP_FLAGS_ERROR (1 << 6) 125 #define TX_CMP_FLAGS_PUSH (1 << 7) 126 127 u32 tx_cmp_opaque; 128 __le32 tx_cmp_errors_v; 129 #define TX_CMP_V (1 << 0) 130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 139 140 __le32 tx_cmp_unsed_3; 141 }; 142 143 struct rx_cmp { 144 __le32 rx_cmp_len_flags_type; 145 #define RX_CMP_CMP_TYPE (0x3f << 0) 146 #define RX_CMP_FLAGS_ERROR (1 << 6) 147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7) 148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10) 149 #define RX_CMP_FLAGS_UNUSED (1 << 11) 150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12 151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) 152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) 153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) 154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) 155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) 156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) 157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) 158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) 159 #define RX_CMP_LEN (0xffff << 16) 160 #define RX_CMP_LEN_SHIFT 16 161 162 u32 rx_cmp_opaque; 163 __le32 rx_cmp_misc_v1; 164 #define RX_CMP_V1 (1 << 0) 165 #define RX_CMP_AGG_BUFS (0x1f << 1) 166 #define RX_CMP_AGG_BUFS_SHIFT 1 167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) 168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) 170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 171 172 __le32 rx_cmp_rss_hash; 173 }; 174 175 #define RX_CMP_HASH_VALID(rxcmp) \ 176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) 177 178 #define RSS_PROFILE_ID_MASK 0x1f 179 180 #define RX_CMP_HASH_TYPE(rxcmp) \ 181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ 182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 183 184 struct rx_cmp_ext { 185 __le32 rx_cmp_flags2; 186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) 191 __le32 rx_cmp_meta_data; 192 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff 193 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff 194 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 195 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 196 __le32 rx_cmp_cfa_code_errors_v2; 197 #define RX_CMP_V (1 << 0) 198 #define RX_CMPL_ERRORS_MASK (0x7fff << 1) 199 #define RX_CMPL_ERRORS_SFT 1 200 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 201 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 202 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) 203 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 204 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 205 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) 206 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) 207 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) 208 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) 209 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) 210 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) 211 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) 212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) 213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) 214 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) 215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) 216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) 217 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) 218 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) 219 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) 220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) 221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) 222 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) 223 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) 224 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) 225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) 226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) 227 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) 228 229 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) 230 #define RX_CMPL_CFA_CODE_SFT 16 231 232 __le32 rx_cmp_unused3; 233 }; 234 235 #define RX_CMP_L2_ERRORS \ 236 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) 237 238 #define RX_CMP_L4_CS_BITS \ 239 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) 240 241 #define RX_CMP_L4_CS_ERR_BITS \ 242 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) 243 244 #define RX_CMP_L4_CS_OK(rxcmp1) \ 245 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ 246 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) 247 248 #define RX_CMP_ENCAP(rxcmp1) \ 249 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ 250 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) 251 252 #define RX_CMP_CFA_CODE(rxcmpl1) \ 253 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ 254 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) 255 256 struct rx_agg_cmp { 257 __le32 rx_agg_cmp_len_flags_type; 258 #define RX_AGG_CMP_TYPE (0x3f << 0) 259 #define RX_AGG_CMP_LEN (0xffff << 16) 260 #define RX_AGG_CMP_LEN_SHIFT 16 261 u32 rx_agg_cmp_opaque; 262 __le32 rx_agg_cmp_v; 263 #define RX_AGG_CMP_V (1 << 0) 264 __le32 rx_agg_cmp_unused; 265 }; 266 267 struct rx_tpa_start_cmp { 268 __le32 rx_tpa_start_cmp_len_flags_type; 269 #define RX_TPA_START_CMP_TYPE (0x3f << 0) 270 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) 271 #define RX_TPA_START_CMP_FLAGS_SHIFT 6 272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) 273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 277 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 278 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) 279 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) 280 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 281 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 282 #define RX_TPA_START_CMP_LEN (0xffff << 16) 283 #define RX_TPA_START_CMP_LEN_SHIFT 16 284 285 u32 rx_tpa_start_cmp_opaque; 286 __le32 rx_tpa_start_cmp_misc_v1; 287 #define RX_TPA_START_CMP_V1 (0x1 << 0) 288 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) 289 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 290 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) 291 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 292 293 __le32 rx_tpa_start_cmp_rss_hash; 294 }; 295 296 #define TPA_START_HASH_VALID(rx_tpa_start) \ 297 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 298 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) 299 300 #define TPA_START_HASH_TYPE(rx_tpa_start) \ 301 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 302 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ 303 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 304 305 #define TPA_START_AGG_ID(rx_tpa_start) \ 306 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 307 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) 308 309 struct rx_tpa_start_cmp_ext { 310 __le32 rx_tpa_start_cmp_flags2; 311 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) 312 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 313 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 314 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 315 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) 316 317 __le32 rx_tpa_start_cmp_metadata; 318 __le32 rx_tpa_start_cmp_cfa_code_v2; 319 #define RX_TPA_START_CMP_V2 (0x1 << 0) 320 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) 321 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 322 __le32 rx_tpa_start_cmp_hdr_info; 323 }; 324 325 #define TPA_START_CFA_CODE(rx_tpa_start) \ 326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) 328 329 #define TPA_START_IS_IPV6(rx_tpa_start) \ 330 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \ 331 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE))) 332 333 struct rx_tpa_end_cmp { 334 __le32 rx_tpa_end_cmp_len_flags_type; 335 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 336 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) 337 #define RX_TPA_END_CMP_FLAGS_SHIFT 6 338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) 339 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 340 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 341 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 342 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 343 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 344 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) 345 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) 346 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 347 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 348 #define RX_TPA_END_CMP_LEN (0xffff << 16) 349 #define RX_TPA_END_CMP_LEN_SHIFT 16 350 351 u32 rx_tpa_end_cmp_opaque; 352 __le32 rx_tpa_end_cmp_misc_v1; 353 #define RX_TPA_END_CMP_V1 (0x1 << 0) 354 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) 355 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 356 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) 357 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 358 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) 359 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 360 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) 361 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 362 363 __le32 rx_tpa_end_cmp_tsdelta; 364 #define RX_TPA_END_GRO_TS (0x1 << 31) 365 }; 366 367 #define TPA_END_AGG_ID(rx_tpa_end) \ 368 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 369 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) 370 371 #define TPA_END_TPA_SEGS(rx_tpa_end) \ 372 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 373 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) 374 375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ 376 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ 377 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) 378 379 #define TPA_END_GRO(rx_tpa_end) \ 380 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ 381 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) 382 383 #define TPA_END_GRO_TS(rx_tpa_end) \ 384 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ 385 cpu_to_le32(RX_TPA_END_GRO_TS))) 386 387 struct rx_tpa_end_cmp_ext { 388 __le32 rx_tpa_end_cmp_dup_acks; 389 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) 390 391 __le32 rx_tpa_end_cmp_seg_len; 392 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) 393 394 __le32 rx_tpa_end_cmp_errors_v2; 395 #define RX_TPA_END_CMP_V2 (0x1 << 0) 396 #define RX_TPA_END_CMP_ERRORS (0x3 << 1) 397 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 398 399 u32 rx_tpa_end_cmp_start_opaque; 400 }; 401 402 #define TPA_END_ERRORS(rx_tpa_end_ext) \ 403 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ 404 cpu_to_le32(RX_TPA_END_CMP_ERRORS)) 405 406 #define DB_IDX_MASK 0xffffff 407 #define DB_IDX_VALID (0x1 << 26) 408 #define DB_IRQ_DIS (0x1 << 27) 409 #define DB_KEY_TX (0x0 << 28) 410 #define DB_KEY_RX (0x1 << 28) 411 #define DB_KEY_CP (0x2 << 28) 412 #define DB_KEY_ST (0x3 << 28) 413 #define DB_KEY_TX_PUSH (0x4 << 28) 414 #define DB_LONG_TX_PUSH (0x2 << 24) 415 416 #define BNXT_MIN_ROCE_CP_RINGS 2 417 #define BNXT_MIN_ROCE_STAT_CTXS 1 418 419 #define INVALID_HW_RING_ID ((u16)-1) 420 421 /* The hardware supports certain page sizes. Use the supported page sizes 422 * to allocate the rings. 423 */ 424 #if (PAGE_SHIFT < 12) 425 #define BNXT_PAGE_SHIFT 12 426 #elif (PAGE_SHIFT <= 13) 427 #define BNXT_PAGE_SHIFT PAGE_SHIFT 428 #elif (PAGE_SHIFT < 16) 429 #define BNXT_PAGE_SHIFT 13 430 #else 431 #define BNXT_PAGE_SHIFT 16 432 #endif 433 434 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 435 436 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 437 #if (PAGE_SHIFT > 15) 438 #define BNXT_RX_PAGE_SHIFT 15 439 #else 440 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT 441 #endif 442 443 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) 444 445 #define BNXT_MAX_MTU 9500 446 #define BNXT_MAX_PAGE_MODE_MTU \ 447 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ 448 XDP_PACKET_HEADROOM) 449 450 #define BNXT_MIN_PKT_SIZE 52 451 452 #define BNXT_DEFAULT_RX_RING_SIZE 511 453 #define BNXT_DEFAULT_TX_RING_SIZE 511 454 455 #define MAX_TPA 64 456 457 #if (BNXT_PAGE_SHIFT == 16) 458 #define MAX_RX_PAGES 1 459 #define MAX_RX_AGG_PAGES 4 460 #define MAX_TX_PAGES 1 461 #define MAX_CP_PAGES 8 462 #else 463 #define MAX_RX_PAGES 8 464 #define MAX_RX_AGG_PAGES 32 465 #define MAX_TX_PAGES 8 466 #define MAX_CP_PAGES 64 467 #endif 468 469 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) 470 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) 471 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) 472 473 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) 474 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 475 476 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) 477 478 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) 479 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 480 481 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 482 483 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 484 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 485 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 486 487 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 488 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 489 490 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 491 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 492 493 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 494 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 495 496 #define TX_CMP_VALID(txcmp, raw_cons) \ 497 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ 498 !((raw_cons) & bp->cp_bit)) 499 500 #define RX_CMP_VALID(rxcmp1, raw_cons) \ 501 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ 502 !((raw_cons) & bp->cp_bit)) 503 504 #define RX_AGG_CMP_VALID(agg, raw_cons) \ 505 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ 506 !((raw_cons) & bp->cp_bit)) 507 508 #define TX_CMP_TYPE(txcmp) \ 509 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) 510 511 #define RX_CMP_TYPE(rxcmp) \ 512 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) 513 514 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) 515 516 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) 517 518 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) 519 520 #define ADV_RAW_CMP(idx, n) ((idx) + (n)) 521 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) 522 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) 523 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) 524 525 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) 526 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 527 #define DFLT_HWRM_CMD_TIMEOUT 500 528 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) 529 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) 530 #define HWRM_RESP_ERR_CODE_MASK 0xffff 531 #define HWRM_RESP_LEN_OFFSET 4 532 #define HWRM_RESP_LEN_MASK 0xffff0000 533 #define HWRM_RESP_LEN_SFT 16 534 #define HWRM_RESP_VALID_MASK 0xff000000 535 #define HWRM_SEQ_ID_INVALID -1 536 #define BNXT_HWRM_REQ_MAX_SIZE 128 537 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ 538 BNXT_HWRM_REQ_MAX_SIZE) 539 #define HWRM_SHORT_MIN_TIMEOUT 3 540 #define HWRM_SHORT_MAX_TIMEOUT 10 541 #define HWRM_SHORT_TIMEOUT_COUNTER 5 542 543 #define HWRM_MIN_TIMEOUT 25 544 #define HWRM_MAX_TIMEOUT 40 545 546 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \ 547 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \ 548 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \ 549 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT)) 550 551 #define HWRM_VALID_BIT_DELAY_USEC 20 552 553 #define BNXT_RX_EVENT 1 554 #define BNXT_AGG_EVENT 2 555 #define BNXT_TX_EVENT 4 556 557 struct bnxt_sw_tx_bd { 558 struct sk_buff *skb; 559 DEFINE_DMA_UNMAP_ADDR(mapping); 560 u8 is_gso; 561 u8 is_push; 562 union { 563 unsigned short nr_frags; 564 u16 rx_prod; 565 }; 566 }; 567 568 struct bnxt_sw_rx_bd { 569 void *data; 570 u8 *data_ptr; 571 dma_addr_t mapping; 572 }; 573 574 struct bnxt_sw_rx_agg_bd { 575 struct page *page; 576 unsigned int offset; 577 dma_addr_t mapping; 578 }; 579 580 struct bnxt_ring_mem_info { 581 int nr_pages; 582 int page_size; 583 u32 flags; 584 #define BNXT_RMEM_VALID_PTE_FLAG 1 585 #define BNXT_RMEM_RING_PTE_FLAG 2 586 587 void **pg_arr; 588 dma_addr_t *dma_arr; 589 590 __le64 *pg_tbl; 591 dma_addr_t pg_tbl_map; 592 593 int vmem_size; 594 void **vmem; 595 }; 596 597 struct bnxt_ring_struct { 598 struct bnxt_ring_mem_info ring_mem; 599 600 u16 fw_ring_id; /* Ring id filled by Chimp FW */ 601 union { 602 u16 grp_idx; 603 u16 map_idx; /* Used by cmpl rings */ 604 }; 605 u8 queue_id; 606 }; 607 608 struct tx_push_bd { 609 __le32 doorbell; 610 __le32 tx_bd_len_flags_type; 611 u32 tx_bd_opaque; 612 struct tx_bd_ext txbd2; 613 }; 614 615 struct tx_push_buffer { 616 struct tx_push_bd push_bd; 617 u32 data[25]; 618 }; 619 620 struct bnxt_tx_ring_info { 621 struct bnxt_napi *bnapi; 622 u16 tx_prod; 623 u16 tx_cons; 624 u16 txq_index; 625 void __iomem *tx_doorbell; 626 627 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 628 struct bnxt_sw_tx_bd *tx_buf_ring; 629 630 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 631 632 struct tx_push_buffer *tx_push; 633 dma_addr_t tx_push_mapping; 634 __le64 data_mapping; 635 636 #define BNXT_DEV_STATE_CLOSING 0x1 637 u32 dev_state; 638 639 struct bnxt_ring_struct tx_ring_struct; 640 }; 641 642 #define BNXT_LEGACY_COAL_CMPL_PARAMS \ 643 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \ 644 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \ 645 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \ 646 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \ 647 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \ 648 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \ 649 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \ 650 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \ 651 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT) 652 653 #define BNXT_COAL_CMPL_ENABLES \ 654 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \ 655 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \ 656 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \ 657 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT) 658 659 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \ 660 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 661 662 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \ 663 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 664 665 struct bnxt_coal_cap { 666 u32 cmpl_params; 667 u32 nq_params; 668 u16 num_cmpl_dma_aggr_max; 669 u16 num_cmpl_dma_aggr_during_int_max; 670 u16 cmpl_aggr_dma_tmr_max; 671 u16 cmpl_aggr_dma_tmr_during_int_max; 672 u16 int_lat_tmr_min_max; 673 u16 int_lat_tmr_max_max; 674 u16 num_cmpl_aggr_int_max; 675 u16 timer_units; 676 }; 677 678 struct bnxt_coal { 679 u16 coal_ticks; 680 u16 coal_ticks_irq; 681 u16 coal_bufs; 682 u16 coal_bufs_irq; 683 /* RING_IDLE enabled when coal ticks < idle_thresh */ 684 u16 idle_thresh; 685 u8 bufs_per_record; 686 u8 budget; 687 }; 688 689 struct bnxt_tpa_info { 690 void *data; 691 u8 *data_ptr; 692 dma_addr_t mapping; 693 u16 len; 694 unsigned short gso_type; 695 u32 flags2; 696 u32 metadata; 697 enum pkt_hash_types hash_type; 698 u32 rss_hash; 699 u32 hdr_info; 700 701 #define BNXT_TPA_L4_SIZE(hdr_info) \ 702 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) 703 704 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ 705 (((hdr_info) >> 18) & 0x1ff) 706 707 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ 708 (((hdr_info) >> 9) & 0x1ff) 709 710 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ 711 ((hdr_info) & 0x1ff) 712 713 u16 cfa_code; /* cfa_code in TPA start compl */ 714 }; 715 716 struct bnxt_rx_ring_info { 717 struct bnxt_napi *bnapi; 718 u16 rx_prod; 719 u16 rx_agg_prod; 720 u16 rx_sw_agg_prod; 721 u16 rx_next_cons; 722 void __iomem *rx_doorbell; 723 void __iomem *rx_agg_doorbell; 724 725 struct bpf_prog *xdp_prog; 726 727 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 728 struct bnxt_sw_rx_bd *rx_buf_ring; 729 730 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 731 struct bnxt_sw_rx_agg_bd *rx_agg_ring; 732 733 unsigned long *rx_agg_bmap; 734 u16 rx_agg_bmap_size; 735 736 struct page *rx_page; 737 unsigned int rx_page_offset; 738 739 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 740 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 741 742 struct bnxt_tpa_info *rx_tpa; 743 744 struct bnxt_ring_struct rx_ring_struct; 745 struct bnxt_ring_struct rx_agg_ring_struct; 746 struct xdp_rxq_info xdp_rxq; 747 }; 748 749 struct bnxt_cp_ring_info { 750 u32 cp_raw_cons; 751 void __iomem *cp_doorbell; 752 753 struct bnxt_coal rx_ring_coal; 754 u64 rx_packets; 755 u64 rx_bytes; 756 u64 event_ctr; 757 758 struct net_dim dim; 759 760 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; 761 762 dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; 763 764 struct ctx_hw_stats *hw_stats; 765 dma_addr_t hw_stats_map; 766 u32 hw_stats_ctx_id; 767 u64 rx_l4_csum_errors; 768 769 struct bnxt_ring_struct cp_ring_struct; 770 }; 771 772 struct bnxt_napi { 773 struct napi_struct napi; 774 struct bnxt *bp; 775 776 int index; 777 struct bnxt_cp_ring_info cp_ring; 778 struct bnxt_rx_ring_info *rx_ring; 779 struct bnxt_tx_ring_info *tx_ring; 780 781 void (*tx_int)(struct bnxt *, struct bnxt_napi *, 782 int); 783 u32 flags; 784 #define BNXT_NAPI_FLAG_XDP 0x1 785 786 bool in_reset; 787 }; 788 789 struct bnxt_irq { 790 irq_handler_t handler; 791 unsigned int vector; 792 u8 requested:1; 793 u8 have_cpumask:1; 794 char name[IFNAMSIZ + 2]; 795 cpumask_var_t cpu_mask; 796 }; 797 798 #define HWRM_RING_ALLOC_TX 0x1 799 #define HWRM_RING_ALLOC_RX 0x2 800 #define HWRM_RING_ALLOC_AGG 0x4 801 #define HWRM_RING_ALLOC_CMPL 0x8 802 803 #define INVALID_STATS_CTX_ID -1 804 805 struct bnxt_ring_grp_info { 806 u16 fw_stats_ctx; 807 u16 fw_grp_id; 808 u16 rx_fw_ring_id; 809 u16 agg_fw_ring_id; 810 u16 cp_fw_ring_id; 811 }; 812 813 struct bnxt_vnic_info { 814 u16 fw_vnic_id; /* returned by Chimp during alloc */ 815 #define BNXT_MAX_CTX_PER_VNIC 2 816 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 817 u16 fw_l2_ctx_id; 818 #define BNXT_MAX_UC_ADDRS 4 819 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; 820 /* index 0 always dev_addr */ 821 u16 uc_filter_count; 822 u8 *uc_list; 823 824 u16 *fw_grp_ids; 825 dma_addr_t rss_table_dma_addr; 826 __le16 *rss_table; 827 dma_addr_t rss_hash_key_dma_addr; 828 u64 *rss_hash_key; 829 u32 rx_mask; 830 831 u8 *mc_list; 832 int mc_list_size; 833 int mc_list_count; 834 dma_addr_t mc_list_mapping; 835 #define BNXT_MAX_MC_ADDRS 16 836 837 u32 flags; 838 #define BNXT_VNIC_RSS_FLAG 1 839 #define BNXT_VNIC_RFS_FLAG 2 840 #define BNXT_VNIC_MCAST_FLAG 4 841 #define BNXT_VNIC_UCAST_FLAG 8 842 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 843 }; 844 845 struct bnxt_hw_resc { 846 u16 min_rsscos_ctxs; 847 u16 max_rsscos_ctxs; 848 u16 min_cp_rings; 849 u16 max_cp_rings; 850 u16 resv_cp_rings; 851 u16 min_tx_rings; 852 u16 max_tx_rings; 853 u16 resv_tx_rings; 854 u16 max_tx_sch_inputs; 855 u16 min_rx_rings; 856 u16 max_rx_rings; 857 u16 resv_rx_rings; 858 u16 min_hw_ring_grps; 859 u16 max_hw_ring_grps; 860 u16 resv_hw_ring_grps; 861 u16 min_l2_ctxs; 862 u16 max_l2_ctxs; 863 u16 min_vnics; 864 u16 max_vnics; 865 u16 resv_vnics; 866 u16 min_stat_ctxs; 867 u16 max_stat_ctxs; 868 u16 max_irqs; 869 }; 870 871 #if defined(CONFIG_BNXT_SRIOV) 872 struct bnxt_vf_info { 873 u16 fw_fid; 874 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ 875 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only 876 * stored by PF. 877 */ 878 u16 vlan; 879 u32 flags; 880 #define BNXT_VF_QOS 0x1 881 #define BNXT_VF_SPOOFCHK 0x2 882 #define BNXT_VF_LINK_FORCED 0x4 883 #define BNXT_VF_LINK_UP 0x8 884 #define BNXT_VF_TRUST 0x10 885 u32 func_flags; /* func cfg flags */ 886 u32 min_tx_rate; 887 u32 max_tx_rate; 888 void *hwrm_cmd_req_addr; 889 dma_addr_t hwrm_cmd_req_dma_addr; 890 }; 891 #endif 892 893 struct bnxt_pf_info { 894 #define BNXT_FIRST_PF_FID 1 895 #define BNXT_FIRST_VF_FID 128 896 u16 fw_fid; 897 u16 port_id; 898 u8 mac_addr[ETH_ALEN]; 899 u32 first_vf_id; 900 u16 active_vfs; 901 u16 max_vfs; 902 u32 max_encap_records; 903 u32 max_decap_records; 904 u32 max_tx_em_flows; 905 u32 max_tx_wm_flows; 906 u32 max_rx_em_flows; 907 u32 max_rx_wm_flows; 908 unsigned long *vf_event_bmap; 909 u16 hwrm_cmd_req_pages; 910 u8 vf_resv_strategy; 911 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 912 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 913 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2 914 void *hwrm_cmd_req_addr[4]; 915 dma_addr_t hwrm_cmd_req_dma_addr[4]; 916 struct bnxt_vf_info *vf; 917 }; 918 919 struct bnxt_ntuple_filter { 920 struct hlist_node hash; 921 u8 dst_mac_addr[ETH_ALEN]; 922 u8 src_mac_addr[ETH_ALEN]; 923 struct flow_keys fkeys; 924 __le64 filter_id; 925 u16 sw_id; 926 u8 l2_fltr_idx; 927 u16 rxq; 928 u32 flow_id; 929 unsigned long state; 930 #define BNXT_FLTR_VALID 0 931 #define BNXT_FLTR_UPDATE 1 932 }; 933 934 struct bnxt_link_info { 935 u8 phy_type; 936 u8 media_type; 937 u8 transceiver; 938 u8 phy_addr; 939 u8 phy_link_status; 940 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK 941 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL 942 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 943 u8 wire_speed; 944 u8 loop_back; 945 u8 link_up; 946 u8 duplex; 947 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 948 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 949 u8 pause; 950 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 951 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 952 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 953 PORT_PHY_QCFG_RESP_PAUSE_TX) 954 u8 lp_pause; 955 u8 auto_pause_setting; 956 u8 force_pause_setting; 957 u8 duplex_setting; 958 u8 auto_mode; 959 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ 960 (mode) <= BNXT_LINK_AUTO_MSK) 961 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 962 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 963 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 964 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 965 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 966 #define PHY_VER_LEN 3 967 u8 phy_ver[PHY_VER_LEN]; 968 u16 link_speed; 969 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 970 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 971 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 972 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 973 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 974 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 975 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 976 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 977 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 978 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 979 u16 support_speeds; 980 u16 auto_link_speeds; /* fw adv setting */ 981 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 982 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 983 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 984 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 985 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 986 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 987 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 988 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 989 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 990 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 991 u16 support_auto_speeds; 992 u16 lp_auto_link_speeds; 993 u16 force_link_speed; 994 u32 preemphasis; 995 u8 module_status; 996 u16 fec_cfg; 997 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 998 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 999 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 1000 1001 /* copy of requested setting from ethtool cmd */ 1002 u8 autoneg; 1003 #define BNXT_AUTONEG_SPEED 1 1004 #define BNXT_AUTONEG_FLOW_CTRL 2 1005 u8 req_duplex; 1006 u8 req_flow_ctrl; 1007 u16 req_link_speed; 1008 u16 advertising; /* user adv setting */ 1009 bool force_link_chng; 1010 1011 bool phy_retry; 1012 unsigned long phy_retry_expires; 1013 1014 /* a copy of phy_qcfg output used to report link 1015 * info to VF 1016 */ 1017 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 1018 }; 1019 1020 #define BNXT_MAX_QUEUE 8 1021 1022 struct bnxt_queue_info { 1023 u8 queue_id; 1024 u8 queue_profile; 1025 }; 1026 1027 #define BNXT_MAX_LED 4 1028 1029 struct bnxt_led_info { 1030 u8 led_id; 1031 u8 led_type; 1032 u8 led_group_id; 1033 u8 unused; 1034 __le16 led_state_caps; 1035 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 1036 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) 1037 1038 __le16 led_color_caps; 1039 }; 1040 1041 #define BNXT_MAX_TEST 8 1042 1043 struct bnxt_test_info { 1044 u8 offline_mask; 1045 u8 flags; 1046 #define BNXT_TEST_FL_EXT_LPBK 0x1 1047 u16 timeout; 1048 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; 1049 }; 1050 1051 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 1052 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1053 #define BNXT_CAG_REG_BASE 0x300000 1054 1055 struct bnxt_tc_flow_stats { 1056 u64 packets; 1057 u64 bytes; 1058 }; 1059 1060 struct bnxt_tc_info { 1061 bool enabled; 1062 1063 /* hash table to store TC offloaded flows */ 1064 struct rhashtable flow_table; 1065 struct rhashtable_params flow_ht_params; 1066 1067 /* hash table to store L2 keys of TC flows */ 1068 struct rhashtable l2_table; 1069 struct rhashtable_params l2_ht_params; 1070 /* hash table to store L2 keys for TC tunnel decap */ 1071 struct rhashtable decap_l2_table; 1072 struct rhashtable_params decap_l2_ht_params; 1073 /* hash table to store tunnel decap entries */ 1074 struct rhashtable decap_table; 1075 struct rhashtable_params decap_ht_params; 1076 /* hash table to store tunnel encap entries */ 1077 struct rhashtable encap_table; 1078 struct rhashtable_params encap_ht_params; 1079 1080 /* lock to atomically add/del an l2 node when a flow is 1081 * added or deleted. 1082 */ 1083 struct mutex lock; 1084 1085 /* Fields used for batching stats query */ 1086 struct rhashtable_iter iter; 1087 #define BNXT_FLOW_STATS_BATCH_MAX 10 1088 struct bnxt_tc_stats_batch { 1089 void *flow_node; 1090 struct bnxt_tc_flow_stats hw_stats; 1091 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; 1092 1093 /* Stat counter mask (width) */ 1094 u64 bytes_mask; 1095 u64 packets_mask; 1096 }; 1097 1098 struct bnxt_vf_rep_stats { 1099 u64 packets; 1100 u64 bytes; 1101 u64 dropped; 1102 }; 1103 1104 struct bnxt_vf_rep { 1105 struct bnxt *bp; 1106 struct net_device *dev; 1107 struct metadata_dst *dst; 1108 u16 vf_idx; 1109 u16 tx_cfa_action; 1110 u16 rx_cfa_code; 1111 1112 struct bnxt_vf_rep_stats rx_stats; 1113 struct bnxt_vf_rep_stats tx_stats; 1114 }; 1115 1116 #define PTU_PTE_VALID 0x1UL 1117 #define PTU_PTE_LAST 0x2UL 1118 #define PTU_PTE_NEXT_TO_LAST 0x4UL 1119 1120 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 1121 1122 struct bnxt_ctx_pg_info { 1123 u32 entries; 1124 void *ctx_pg_arr[MAX_CTX_PAGES]; 1125 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; 1126 struct bnxt_ring_mem_info ring_mem; 1127 }; 1128 1129 struct bnxt_ctx_mem_info { 1130 u32 qp_max_entries; 1131 u16 qp_min_qp1_entries; 1132 u16 qp_max_l2_entries; 1133 u16 qp_entry_size; 1134 u16 srq_max_l2_entries; 1135 u32 srq_max_entries; 1136 u16 srq_entry_size; 1137 u16 cq_max_l2_entries; 1138 u32 cq_max_entries; 1139 u16 cq_entry_size; 1140 u16 vnic_max_vnic_entries; 1141 u16 vnic_max_ring_table_entries; 1142 u16 vnic_entry_size; 1143 u32 stat_max_entries; 1144 u16 stat_entry_size; 1145 u16 tqm_entry_size; 1146 u32 tqm_min_entries_per_ring; 1147 u32 tqm_max_entries_per_ring; 1148 u32 mrav_max_entries; 1149 u16 mrav_entry_size; 1150 u16 tim_entry_size; 1151 u32 tim_max_entries; 1152 u8 tqm_entries_multiple; 1153 1154 u32 flags; 1155 #define BNXT_CTX_FLAG_INITED 0x01 1156 1157 struct bnxt_ctx_pg_info qp_mem; 1158 struct bnxt_ctx_pg_info srq_mem; 1159 struct bnxt_ctx_pg_info cq_mem; 1160 struct bnxt_ctx_pg_info vnic_mem; 1161 struct bnxt_ctx_pg_info stat_mem; 1162 struct bnxt_ctx_pg_info *tqm_mem[9]; 1163 }; 1164 1165 struct bnxt { 1166 void __iomem *bar0; 1167 void __iomem *bar1; 1168 void __iomem *bar2; 1169 1170 u32 reg_base; 1171 u16 chip_num; 1172 #define CHIP_NUM_57301 0x16c8 1173 #define CHIP_NUM_57302 0x16c9 1174 #define CHIP_NUM_57304 0x16ca 1175 #define CHIP_NUM_58700 0x16cd 1176 #define CHIP_NUM_57402 0x16d0 1177 #define CHIP_NUM_57404 0x16d1 1178 #define CHIP_NUM_57406 0x16d2 1179 #define CHIP_NUM_57407 0x16d5 1180 1181 #define CHIP_NUM_57311 0x16ce 1182 #define CHIP_NUM_57312 0x16cf 1183 #define CHIP_NUM_57314 0x16df 1184 #define CHIP_NUM_57317 0x16e0 1185 #define CHIP_NUM_57412 0x16d6 1186 #define CHIP_NUM_57414 0x16d7 1187 #define CHIP_NUM_57416 0x16d8 1188 #define CHIP_NUM_57417 0x16d9 1189 #define CHIP_NUM_57412L 0x16da 1190 #define CHIP_NUM_57414L 0x16db 1191 1192 #define CHIP_NUM_5745X 0xd730 1193 1194 #define CHIP_NUM_58802 0xd802 1195 #define CHIP_NUM_58804 0xd804 1196 #define CHIP_NUM_58808 0xd808 1197 1198 #define BNXT_CHIP_NUM_5730X(chip_num) \ 1199 ((chip_num) >= CHIP_NUM_57301 && \ 1200 (chip_num) <= CHIP_NUM_57304) 1201 1202 #define BNXT_CHIP_NUM_5740X(chip_num) \ 1203 (((chip_num) >= CHIP_NUM_57402 && \ 1204 (chip_num) <= CHIP_NUM_57406) || \ 1205 (chip_num) == CHIP_NUM_57407) 1206 1207 #define BNXT_CHIP_NUM_5731X(chip_num) \ 1208 ((chip_num) == CHIP_NUM_57311 || \ 1209 (chip_num) == CHIP_NUM_57312 || \ 1210 (chip_num) == CHIP_NUM_57314 || \ 1211 (chip_num) == CHIP_NUM_57317) 1212 1213 #define BNXT_CHIP_NUM_5741X(chip_num) \ 1214 ((chip_num) >= CHIP_NUM_57412 && \ 1215 (chip_num) <= CHIP_NUM_57414L) 1216 1217 #define BNXT_CHIP_NUM_58700(chip_num) \ 1218 ((chip_num) == CHIP_NUM_58700) 1219 1220 #define BNXT_CHIP_NUM_5745X(chip_num) \ 1221 ((chip_num) == CHIP_NUM_5745X) 1222 1223 #define BNXT_CHIP_NUM_57X0X(chip_num) \ 1224 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) 1225 1226 #define BNXT_CHIP_NUM_57X1X(chip_num) \ 1227 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) 1228 1229 #define BNXT_CHIP_NUM_588XX(chip_num) \ 1230 ((chip_num) == CHIP_NUM_58802 || \ 1231 (chip_num) == CHIP_NUM_58804 || \ 1232 (chip_num) == CHIP_NUM_58808) 1233 1234 struct net_device *dev; 1235 struct pci_dev *pdev; 1236 1237 atomic_t intr_sem; 1238 1239 u32 flags; 1240 #define BNXT_FLAG_VF 0x2 1241 #define BNXT_FLAG_LRO 0x4 1242 #ifdef CONFIG_INET 1243 #define BNXT_FLAG_GRO 0x8 1244 #else 1245 /* Cannot support hardware GRO if CONFIG_INET is not set */ 1246 #define BNXT_FLAG_GRO 0x0 1247 #endif 1248 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) 1249 #define BNXT_FLAG_JUMBO 0x10 1250 #define BNXT_FLAG_STRIP_VLAN 0x20 1251 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ 1252 BNXT_FLAG_LRO) 1253 #define BNXT_FLAG_USING_MSIX 0x40 1254 #define BNXT_FLAG_MSIX_CAP 0x80 1255 #define BNXT_FLAG_RFS 0x100 1256 #define BNXT_FLAG_SHARED_RINGS 0x200 1257 #define BNXT_FLAG_PORT_STATS 0x400 1258 #define BNXT_FLAG_UDP_RSS_CAP 0x800 1259 #define BNXT_FLAG_EEE_CAP 0x1000 1260 #define BNXT_FLAG_NEW_RSS_CAP 0x2000 1261 #define BNXT_FLAG_WOL_CAP 0x4000 1262 #define BNXT_FLAG_ROCEV1_CAP 0x8000 1263 #define BNXT_FLAG_ROCEV2_CAP 0x10000 1264 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ 1265 BNXT_FLAG_ROCEV2_CAP) 1266 #define BNXT_FLAG_NO_AGG_RINGS 0x20000 1267 #define BNXT_FLAG_RX_PAGE_MODE 0x40000 1268 #define BNXT_FLAG_MULTI_HOST 0x100000 1269 #define BNXT_FLAG_DOUBLE_DB 0x400000 1270 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 1271 #define BNXT_FLAG_DIM 0x2000000 1272 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 1273 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 1274 1275 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 1276 BNXT_FLAG_RFS | \ 1277 BNXT_FLAG_STRIP_VLAN) 1278 1279 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 1280 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 1281 #define BNXT_NPAR(bp) ((bp)->port_partition_type) 1282 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 1283 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 1284 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) 1285 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) 1286 1287 /* Chip class phase 4 and later */ 1288 #define BNXT_CHIP_P4_PLUS(bp) \ 1289 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ 1290 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ 1291 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ 1292 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ 1293 !BNXT_CHIP_TYPE_NITRO_A0(bp))) 1294 1295 struct bnxt_en_dev *edev; 1296 struct bnxt_en_dev * (*ulp_probe)(struct net_device *); 1297 1298 struct bnxt_napi **bnapi; 1299 1300 struct bnxt_rx_ring_info *rx_ring; 1301 struct bnxt_tx_ring_info *tx_ring; 1302 u16 *tx_ring_map; 1303 1304 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, 1305 struct sk_buff *); 1306 1307 struct sk_buff * (*rx_skb_func)(struct bnxt *, 1308 struct bnxt_rx_ring_info *, 1309 u16, void *, u8 *, dma_addr_t, 1310 unsigned int); 1311 1312 u32 rx_buf_size; 1313 u32 rx_buf_use_size; /* useable size */ 1314 u16 rx_offset; 1315 u16 rx_dma_offset; 1316 enum dma_data_direction rx_dir; 1317 u32 rx_ring_size; 1318 u32 rx_agg_ring_size; 1319 u32 rx_copy_thresh; 1320 u32 rx_ring_mask; 1321 u32 rx_agg_ring_mask; 1322 int rx_nr_pages; 1323 int rx_agg_nr_pages; 1324 int rx_nr_rings; 1325 int rsscos_nr_ctxs; 1326 1327 u32 tx_ring_size; 1328 u32 tx_ring_mask; 1329 int tx_nr_pages; 1330 int tx_nr_rings; 1331 int tx_nr_rings_per_tc; 1332 int tx_nr_rings_xdp; 1333 1334 int tx_wake_thresh; 1335 int tx_push_thresh; 1336 int tx_push_size; 1337 1338 u32 cp_ring_size; 1339 u32 cp_ring_mask; 1340 u32 cp_bit; 1341 int cp_nr_pages; 1342 int cp_nr_rings; 1343 1344 int num_stat_ctxs; 1345 1346 /* grp_info indexed by completion ring index */ 1347 struct bnxt_ring_grp_info *grp_info; 1348 struct bnxt_vnic_info *vnic_info; 1349 int nr_vnics; 1350 u32 rss_hash_cfg; 1351 1352 u16 max_mtu; 1353 u8 max_tc; 1354 u8 max_lltc; /* lossless TCs */ 1355 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; 1356 u8 tc_to_qidx[BNXT_MAX_QUEUE]; 1357 u8 q_ids[BNXT_MAX_QUEUE]; 1358 u8 max_q; 1359 1360 unsigned int current_interval; 1361 #define BNXT_TIMER_INTERVAL HZ 1362 1363 struct timer_list timer; 1364 1365 unsigned long state; 1366 #define BNXT_STATE_OPEN 0 1367 #define BNXT_STATE_IN_SP_TASK 1 1368 #define BNXT_STATE_READ_STATS 2 1369 1370 struct bnxt_irq *irq_tbl; 1371 int total_irqs; 1372 u8 mac_addr[ETH_ALEN]; 1373 1374 #ifdef CONFIG_BNXT_DCB 1375 struct ieee_pfc *ieee_pfc; 1376 struct ieee_ets *ieee_ets; 1377 u8 dcbx_cap; 1378 u8 default_pri; 1379 u8 max_dscp_value; 1380 #endif /* CONFIG_BNXT_DCB */ 1381 1382 u32 msg_enable; 1383 1384 u32 fw_cap; 1385 #define BNXT_FW_CAP_SHORT_CMD 0x00000001 1386 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002 1387 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004 1388 #define BNXT_FW_CAP_NEW_RM 0x00000008 1389 #define BNXT_FW_CAP_IF_CHANGE 0x00000010 1390 1391 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM) 1392 u32 hwrm_spec_code; 1393 u16 hwrm_cmd_seq; 1394 u32 hwrm_intr_seq_id; 1395 void *hwrm_short_cmd_req_addr; 1396 dma_addr_t hwrm_short_cmd_req_dma_addr; 1397 void *hwrm_cmd_resp_addr; 1398 dma_addr_t hwrm_cmd_resp_dma_addr; 1399 1400 struct rx_port_stats *hw_rx_port_stats; 1401 struct tx_port_stats *hw_tx_port_stats; 1402 struct rx_port_stats_ext *hw_rx_port_stats_ext; 1403 struct rx_port_stats_ext *hw_tx_port_stats_ext; 1404 dma_addr_t hw_rx_port_stats_map; 1405 dma_addr_t hw_tx_port_stats_map; 1406 dma_addr_t hw_rx_port_stats_ext_map; 1407 dma_addr_t hw_tx_port_stats_ext_map; 1408 int hw_port_stats_size; 1409 u16 fw_rx_stats_ext_size; 1410 u16 fw_tx_stats_ext_size; 1411 1412 u16 hwrm_max_req_len; 1413 u16 hwrm_max_ext_req_len; 1414 int hwrm_cmd_timeout; 1415 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 1416 struct hwrm_ver_get_output ver_resp; 1417 #define FW_VER_STR_LEN 32 1418 #define BC_HWRM_STR_LEN 21 1419 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) 1420 char fw_ver_str[FW_VER_STR_LEN]; 1421 __be16 vxlan_port; 1422 u8 vxlan_port_cnt; 1423 __le16 vxlan_fw_dst_port_id; 1424 __be16 nge_port; 1425 u8 nge_port_cnt; 1426 __le16 nge_fw_dst_port_id; 1427 u8 port_partition_type; 1428 u8 port_count; 1429 u16 br_mode; 1430 1431 struct bnxt_coal_cap coal_cap; 1432 struct bnxt_coal rx_coal; 1433 struct bnxt_coal tx_coal; 1434 1435 u32 stats_coal_ticks; 1436 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1437 #define BNXT_MIN_STATS_COAL_TICKS 250000 1438 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1439 1440 struct work_struct sp_task; 1441 unsigned long sp_event; 1442 #define BNXT_RX_MASK_SP_EVENT 0 1443 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1444 #define BNXT_LINK_CHNG_SP_EVENT 2 1445 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1446 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1447 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1448 #define BNXT_RESET_TASK_SP_EVENT 6 1449 #define BNXT_RST_RING_SP_EVENT 7 1450 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1451 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1452 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1453 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1454 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1455 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1456 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1457 #define BNXT_FLOW_STATS_SP_EVENT 15 1458 #define BNXT_UPDATE_PHY_SP_EVENT 16 1459 1460 struct bnxt_hw_resc hw_resc; 1461 struct bnxt_pf_info pf; 1462 struct bnxt_ctx_mem_info *ctx; 1463 #ifdef CONFIG_BNXT_SRIOV 1464 int nr_vfs; 1465 struct bnxt_vf_info vf; 1466 wait_queue_head_t sriov_cfg_wait; 1467 bool sriov_cfg; 1468 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) 1469 1470 /* lock to protect VF-rep creation/cleanup via 1471 * multiple paths such as ->sriov_configure() and 1472 * devlink ->eswitch_mode_set() 1473 */ 1474 struct mutex sriov_lock; 1475 #endif 1476 1477 #define BNXT_NTP_FLTR_MAX_FLTR 4096 1478 #define BNXT_NTP_FLTR_HASH_SIZE 512 1479 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) 1480 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; 1481 spinlock_t ntp_fltr_lock; /* for hash table add, del */ 1482 1483 unsigned long *ntp_fltr_bmap; 1484 int ntp_fltr_count; 1485 1486 /* To protect link related settings during link changes and 1487 * ethtool settings changes. 1488 */ 1489 struct mutex link_lock; 1490 struct bnxt_link_info link_info; 1491 struct ethtool_eee eee; 1492 u32 lpi_tmr_lo; 1493 u32 lpi_tmr_hi; 1494 1495 u8 num_tests; 1496 struct bnxt_test_info *test_info; 1497 1498 u8 wol_filter_id; 1499 u8 wol; 1500 1501 u8 num_leds; 1502 struct bnxt_led_info leds[BNXT_MAX_LED]; 1503 1504 struct bpf_prog *xdp_prog; 1505 1506 /* devlink interface and vf-rep structs */ 1507 struct devlink *dl; 1508 enum devlink_eswitch_mode eswitch_mode; 1509 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ 1510 u16 *cfa_code_map; /* cfa_code -> vf_idx map */ 1511 u8 switch_id[8]; 1512 struct bnxt_tc_info *tc_info; 1513 struct dentry *debugfs_pdev; 1514 struct dentry *debugfs_dim; 1515 struct device *hwmon_dev; 1516 }; 1517 1518 #define BNXT_RX_STATS_OFFSET(counter) \ 1519 (offsetof(struct rx_port_stats, counter) / 8) 1520 1521 #define BNXT_TX_STATS_OFFSET(counter) \ 1522 ((offsetof(struct tx_port_stats, counter) + \ 1523 sizeof(struct rx_port_stats) + 512) / 8) 1524 1525 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 1526 (offsetof(struct rx_port_stats_ext, counter) / 8) 1527 1528 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 1529 (offsetof(struct tx_port_stats_ext, counter) / 8) 1530 1531 #define I2C_DEV_ADDR_A0 0xa0 1532 #define I2C_DEV_ADDR_A2 0xa2 1533 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 1534 #define SFF_MODULE_ID_SFP 0x3 1535 #define SFF_MODULE_ID_QSFP 0xc 1536 #define SFF_MODULE_ID_QSFP_PLUS 0xd 1537 #define SFF_MODULE_ID_QSFP28 0x11 1538 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1539 1540 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 1541 { 1542 /* Tell compiler to fetch tx indices from memory. */ 1543 barrier(); 1544 1545 return bp->tx_ring_size - 1546 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 1547 } 1548 1549 /* For TX and RX ring doorbells with no ordering guarantee*/ 1550 static inline void bnxt_db_write_relaxed(struct bnxt *bp, void __iomem *db, 1551 u32 val) 1552 { 1553 writel_relaxed(val, db); 1554 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1555 writel_relaxed(val, db); 1556 } 1557 1558 /* For TX and RX ring doorbells */ 1559 static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val) 1560 { 1561 writel(val, db); 1562 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1563 writel(val, db); 1564 } 1565 1566 extern const u16 bnxt_lhint_arr[]; 1567 1568 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1569 u16 prod, gfp_t gfp); 1570 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); 1571 void bnxt_set_tpa_flags(struct bnxt *bp); 1572 void bnxt_set_ring_params(struct bnxt *); 1573 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); 1574 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); 1575 int _hwrm_send_message(struct bnxt *, void *, u32, int); 1576 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout); 1577 int hwrm_send_message(struct bnxt *, void *, u32, int); 1578 int hwrm_send_message_silent(struct bnxt *, void *, u32, int); 1579 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 1580 int bmap_size); 1581 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); 1582 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); 1583 int bnxt_hwrm_set_coal(struct bnxt *); 1584 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); 1585 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max); 1586 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); 1587 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp); 1588 int bnxt_get_avail_msix(struct bnxt *bp, int num); 1589 int bnxt_reserve_rings(struct bnxt *bp); 1590 void bnxt_tx_disable(struct bnxt *bp); 1591 void bnxt_tx_enable(struct bnxt *bp); 1592 int bnxt_hwrm_set_pause(struct bnxt *); 1593 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); 1594 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); 1595 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); 1596 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); 1597 int bnxt_hwrm_fw_set_time(struct bnxt *); 1598 int bnxt_open_nic(struct bnxt *, bool, bool); 1599 int bnxt_half_open_nic(struct bnxt *bp); 1600 void bnxt_half_close_nic(struct bnxt *bp); 1601 int bnxt_close_nic(struct bnxt *, bool, bool); 1602 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 1603 int tx_xdp); 1604 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); 1605 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); 1606 int bnxt_restore_pf_fw_resources(struct bnxt *bp); 1607 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr); 1608 void bnxt_dim_work(struct work_struct *work); 1609 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); 1610 1611 #endif 1612