1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_H 12 #define BNXT_H 13 14 #define DRV_MODULE_NAME "bnxt_en" 15 #define DRV_MODULE_VERSION "1.10.0" 16 17 #define DRV_VER_MAJ 1 18 #define DRV_VER_MIN 10 19 #define DRV_VER_UPD 0 20 21 #include <linux/interrupt.h> 22 #include <linux/rhashtable.h> 23 #include <net/devlink.h> 24 #include <net/dst_metadata.h> 25 #include <net/switchdev.h> 26 #include <net/xdp.h> 27 #include <linux/net_dim.h> 28 29 struct tx_bd { 30 __le32 tx_bd_len_flags_type; 31 #define TX_BD_TYPE (0x3f << 0) 32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 34 #define TX_BD_FLAGS_PACKET_END (1 << 6) 35 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 38 #define TX_BD_FLAGS_LHINT (3 << 13) 39 #define TX_BD_FLAGS_LHINT_SHIFT 13 40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 44 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 45 #define TX_BD_LEN (0xffff << 16) 46 #define TX_BD_LEN_SHIFT 16 47 48 u32 tx_bd_opaque; 49 __le64 tx_bd_haddr; 50 } __packed; 51 52 struct tx_bd_ext { 53 __le32 tx_bd_hsize_lflags; 54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) 55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1) 56 #define TX_BD_FLAGS_NO_CRC (1 << 2) 57 #define TX_BD_FLAGS_STAMP (1 << 3) 58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) 59 #define TX_BD_FLAGS_LSO (1 << 5) 60 #define TX_BD_FLAGS_IPID_FMT (1 << 6) 61 #define TX_BD_FLAGS_T_IPID (1 << 7) 62 #define TX_BD_HSIZE (0xff << 16) 63 #define TX_BD_HSIZE_SHIFT 16 64 65 __le32 tx_bd_mss; 66 __le32 tx_bd_cfa_action; 67 #define TX_BD_CFA_ACTION (0xffff << 16) 68 #define TX_BD_CFA_ACTION_SHIFT 16 69 70 __le32 tx_bd_cfa_meta; 71 #define TX_BD_CFA_META_MASK 0xfffffff 72 #define TX_BD_CFA_META_VID_MASK 0xfff 73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12) 74 #define TX_BD_CFA_META_PRI_SHIFT 12 75 #define TX_BD_CFA_META_TPID_MASK (3 << 16) 76 #define TX_BD_CFA_META_TPID_SHIFT 16 77 #define TX_BD_CFA_META_KEY (0xf << 28) 78 #define TX_BD_CFA_META_KEY_SHIFT 28 79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28) 80 }; 81 82 struct rx_bd { 83 __le32 rx_bd_len_flags_type; 84 #define RX_BD_TYPE (0x3f << 0) 85 #define RX_BD_TYPE_RX_PACKET_BD 0x4 86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 87 #define RX_BD_TYPE_RX_AGG_BD 0x6 88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 92 #define RX_BD_FLAGS_SOP (1 << 6) 93 #define RX_BD_FLAGS_EOP (1 << 7) 94 #define RX_BD_FLAGS_BUFFERS (3 << 8) 95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 99 #define RX_BD_LEN (0xffff << 16) 100 #define RX_BD_LEN_SHIFT 16 101 102 u32 rx_bd_opaque; 103 __le64 rx_bd_haddr; 104 }; 105 106 struct tx_cmp { 107 __le32 tx_cmp_flags_type; 108 #define CMP_TYPE (0x3f << 0) 109 #define CMP_TYPE_TX_L2_CMP 0 110 #define CMP_TYPE_RX_L2_CMP 17 111 #define CMP_TYPE_RX_AGG_CMP 18 112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 114 #define CMP_TYPE_STATUS_CMP 32 115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 117 #define CMP_TYPE_ERROR_STATUS 48 118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 123 124 #define TX_CMP_FLAGS_ERROR (1 << 6) 125 #define TX_CMP_FLAGS_PUSH (1 << 7) 126 127 u32 tx_cmp_opaque; 128 __le32 tx_cmp_errors_v; 129 #define TX_CMP_V (1 << 0) 130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 139 140 __le32 tx_cmp_unsed_3; 141 }; 142 143 struct rx_cmp { 144 __le32 rx_cmp_len_flags_type; 145 #define RX_CMP_CMP_TYPE (0x3f << 0) 146 #define RX_CMP_FLAGS_ERROR (1 << 6) 147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7) 148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10) 149 #define RX_CMP_FLAGS_UNUSED (1 << 11) 150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12 151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) 152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) 153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) 154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) 155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) 156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) 157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) 158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) 159 #define RX_CMP_LEN (0xffff << 16) 160 #define RX_CMP_LEN_SHIFT 16 161 162 u32 rx_cmp_opaque; 163 __le32 rx_cmp_misc_v1; 164 #define RX_CMP_V1 (1 << 0) 165 #define RX_CMP_AGG_BUFS (0x1f << 1) 166 #define RX_CMP_AGG_BUFS_SHIFT 1 167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) 168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) 170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 171 172 __le32 rx_cmp_rss_hash; 173 }; 174 175 #define RX_CMP_HASH_VALID(rxcmp) \ 176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) 177 178 #define RSS_PROFILE_ID_MASK 0x1f 179 180 #define RX_CMP_HASH_TYPE(rxcmp) \ 181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ 182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 183 184 struct rx_cmp_ext { 185 __le32 rx_cmp_flags2; 186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) 191 __le32 rx_cmp_meta_data; 192 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff 193 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff 194 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 195 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 196 __le32 rx_cmp_cfa_code_errors_v2; 197 #define RX_CMP_V (1 << 0) 198 #define RX_CMPL_ERRORS_MASK (0x7fff << 1) 199 #define RX_CMPL_ERRORS_SFT 1 200 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 201 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 202 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) 203 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 204 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 205 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) 206 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) 207 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) 208 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) 209 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) 210 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) 211 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) 212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) 213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) 214 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) 215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) 216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) 217 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) 218 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) 219 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) 220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) 221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) 222 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) 223 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) 224 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) 225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) 226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) 227 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) 228 229 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) 230 #define RX_CMPL_CFA_CODE_SFT 16 231 232 __le32 rx_cmp_unused3; 233 }; 234 235 #define RX_CMP_L2_ERRORS \ 236 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) 237 238 #define RX_CMP_L4_CS_BITS \ 239 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) 240 241 #define RX_CMP_L4_CS_ERR_BITS \ 242 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) 243 244 #define RX_CMP_L4_CS_OK(rxcmp1) \ 245 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ 246 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) 247 248 #define RX_CMP_ENCAP(rxcmp1) \ 249 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ 250 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) 251 252 #define RX_CMP_CFA_CODE(rxcmpl1) \ 253 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ 254 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) 255 256 struct rx_agg_cmp { 257 __le32 rx_agg_cmp_len_flags_type; 258 #define RX_AGG_CMP_TYPE (0x3f << 0) 259 #define RX_AGG_CMP_LEN (0xffff << 16) 260 #define RX_AGG_CMP_LEN_SHIFT 16 261 u32 rx_agg_cmp_opaque; 262 __le32 rx_agg_cmp_v; 263 #define RX_AGG_CMP_V (1 << 0) 264 __le32 rx_agg_cmp_unused; 265 }; 266 267 struct rx_tpa_start_cmp { 268 __le32 rx_tpa_start_cmp_len_flags_type; 269 #define RX_TPA_START_CMP_TYPE (0x3f << 0) 270 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) 271 #define RX_TPA_START_CMP_FLAGS_SHIFT 6 272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) 273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 277 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 278 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) 279 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) 280 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 281 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 282 #define RX_TPA_START_CMP_LEN (0xffff << 16) 283 #define RX_TPA_START_CMP_LEN_SHIFT 16 284 285 u32 rx_tpa_start_cmp_opaque; 286 __le32 rx_tpa_start_cmp_misc_v1; 287 #define RX_TPA_START_CMP_V1 (0x1 << 0) 288 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) 289 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 290 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) 291 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 292 293 __le32 rx_tpa_start_cmp_rss_hash; 294 }; 295 296 #define TPA_START_HASH_VALID(rx_tpa_start) \ 297 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 298 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) 299 300 #define TPA_START_HASH_TYPE(rx_tpa_start) \ 301 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 302 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ 303 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 304 305 #define TPA_START_AGG_ID(rx_tpa_start) \ 306 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 307 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) 308 309 struct rx_tpa_start_cmp_ext { 310 __le32 rx_tpa_start_cmp_flags2; 311 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) 312 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 313 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 314 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 315 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) 316 317 __le32 rx_tpa_start_cmp_metadata; 318 __le32 rx_tpa_start_cmp_cfa_code_v2; 319 #define RX_TPA_START_CMP_V2 (0x1 << 0) 320 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) 321 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 322 __le32 rx_tpa_start_cmp_hdr_info; 323 }; 324 325 #define TPA_START_CFA_CODE(rx_tpa_start) \ 326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) 328 329 #define TPA_START_IS_IPV6(rx_tpa_start) \ 330 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \ 331 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE))) 332 333 struct rx_tpa_end_cmp { 334 __le32 rx_tpa_end_cmp_len_flags_type; 335 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 336 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) 337 #define RX_TPA_END_CMP_FLAGS_SHIFT 6 338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) 339 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 340 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 341 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 342 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 343 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 344 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) 345 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) 346 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 347 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 348 #define RX_TPA_END_CMP_LEN (0xffff << 16) 349 #define RX_TPA_END_CMP_LEN_SHIFT 16 350 351 u32 rx_tpa_end_cmp_opaque; 352 __le32 rx_tpa_end_cmp_misc_v1; 353 #define RX_TPA_END_CMP_V1 (0x1 << 0) 354 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) 355 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 356 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) 357 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 358 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) 359 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 360 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) 361 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 362 363 __le32 rx_tpa_end_cmp_tsdelta; 364 #define RX_TPA_END_GRO_TS (0x1 << 31) 365 }; 366 367 #define TPA_END_AGG_ID(rx_tpa_end) \ 368 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 369 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) 370 371 #define TPA_END_TPA_SEGS(rx_tpa_end) \ 372 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 373 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) 374 375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ 376 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ 377 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) 378 379 #define TPA_END_GRO(rx_tpa_end) \ 380 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ 381 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) 382 383 #define TPA_END_GRO_TS(rx_tpa_end) \ 384 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ 385 cpu_to_le32(RX_TPA_END_GRO_TS))) 386 387 struct rx_tpa_end_cmp_ext { 388 __le32 rx_tpa_end_cmp_dup_acks; 389 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) 390 391 __le32 rx_tpa_end_cmp_seg_len; 392 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) 393 394 __le32 rx_tpa_end_cmp_errors_v2; 395 #define RX_TPA_END_CMP_V2 (0x1 << 0) 396 #define RX_TPA_END_CMP_ERRORS (0x3 << 1) 397 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 398 399 u32 rx_tpa_end_cmp_start_opaque; 400 }; 401 402 #define TPA_END_ERRORS(rx_tpa_end_ext) \ 403 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ 404 cpu_to_le32(RX_TPA_END_CMP_ERRORS)) 405 406 struct nqe_cn { 407 __le16 type; 408 #define NQ_CN_TYPE_MASK 0x3fUL 409 #define NQ_CN_TYPE_SFT 0 410 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL 411 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION 412 __le16 reserved16; 413 __le32 cq_handle_low; 414 __le32 v; 415 #define NQ_CN_V 0x1UL 416 __le32 cq_handle_high; 417 }; 418 419 #define DB_IDX_MASK 0xffffff 420 #define DB_IDX_VALID (0x1 << 26) 421 #define DB_IRQ_DIS (0x1 << 27) 422 #define DB_KEY_TX (0x0 << 28) 423 #define DB_KEY_RX (0x1 << 28) 424 #define DB_KEY_CP (0x2 << 28) 425 #define DB_KEY_ST (0x3 << 28) 426 #define DB_KEY_TX_PUSH (0x4 << 28) 427 #define DB_LONG_TX_PUSH (0x2 << 24) 428 429 #define BNXT_MIN_ROCE_CP_RINGS 2 430 #define BNXT_MIN_ROCE_STAT_CTXS 1 431 432 /* 64-bit doorbell */ 433 #define DBR_INDEX_MASK 0x0000000000ffffffULL 434 #define DBR_XID_MASK 0x000fffff00000000ULL 435 #define DBR_XID_SFT 32 436 #define DBR_PATH_L2 (0x1ULL << 56) 437 #define DBR_TYPE_SQ (0x0ULL << 60) 438 #define DBR_TYPE_RQ (0x1ULL << 60) 439 #define DBR_TYPE_SRQ (0x2ULL << 60) 440 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 441 #define DBR_TYPE_CQ (0x4ULL << 60) 442 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 443 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 444 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 445 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 446 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 447 #define DBR_TYPE_NQ (0xaULL << 60) 448 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 449 #define DBR_TYPE_NULL (0xfULL << 60) 450 451 #define INVALID_HW_RING_ID ((u16)-1) 452 453 /* The hardware supports certain page sizes. Use the supported page sizes 454 * to allocate the rings. 455 */ 456 #if (PAGE_SHIFT < 12) 457 #define BNXT_PAGE_SHIFT 12 458 #elif (PAGE_SHIFT <= 13) 459 #define BNXT_PAGE_SHIFT PAGE_SHIFT 460 #elif (PAGE_SHIFT < 16) 461 #define BNXT_PAGE_SHIFT 13 462 #else 463 #define BNXT_PAGE_SHIFT 16 464 #endif 465 466 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 467 468 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 469 #if (PAGE_SHIFT > 15) 470 #define BNXT_RX_PAGE_SHIFT 15 471 #else 472 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT 473 #endif 474 475 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) 476 477 #define BNXT_MAX_MTU 9500 478 #define BNXT_MAX_PAGE_MODE_MTU \ 479 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ 480 XDP_PACKET_HEADROOM) 481 482 #define BNXT_MIN_PKT_SIZE 52 483 484 #define BNXT_DEFAULT_RX_RING_SIZE 511 485 #define BNXT_DEFAULT_TX_RING_SIZE 511 486 487 #define MAX_TPA 64 488 489 #if (BNXT_PAGE_SHIFT == 16) 490 #define MAX_RX_PAGES 1 491 #define MAX_RX_AGG_PAGES 4 492 #define MAX_TX_PAGES 1 493 #define MAX_CP_PAGES 8 494 #else 495 #define MAX_RX_PAGES 8 496 #define MAX_RX_AGG_PAGES 32 497 #define MAX_TX_PAGES 8 498 #define MAX_CP_PAGES 64 499 #endif 500 501 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) 502 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) 503 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) 504 505 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) 506 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 507 508 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) 509 510 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) 511 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 512 513 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 514 515 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 516 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 517 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 518 519 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 520 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 521 522 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 523 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 524 525 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 526 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 527 528 #define TX_CMP_VALID(txcmp, raw_cons) \ 529 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ 530 !((raw_cons) & bp->cp_bit)) 531 532 #define RX_CMP_VALID(rxcmp1, raw_cons) \ 533 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ 534 !((raw_cons) & bp->cp_bit)) 535 536 #define RX_AGG_CMP_VALID(agg, raw_cons) \ 537 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ 538 !((raw_cons) & bp->cp_bit)) 539 540 #define TX_CMP_TYPE(txcmp) \ 541 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) 542 543 #define RX_CMP_TYPE(rxcmp) \ 544 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) 545 546 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) 547 548 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) 549 550 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) 551 552 #define ADV_RAW_CMP(idx, n) ((idx) + (n)) 553 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) 554 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) 555 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) 556 557 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) 558 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 559 #define DFLT_HWRM_CMD_TIMEOUT 500 560 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) 561 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) 562 #define HWRM_RESP_ERR_CODE_MASK 0xffff 563 #define HWRM_RESP_LEN_OFFSET 4 564 #define HWRM_RESP_LEN_MASK 0xffff0000 565 #define HWRM_RESP_LEN_SFT 16 566 #define HWRM_RESP_VALID_MASK 0xff000000 567 #define HWRM_SEQ_ID_INVALID -1 568 #define BNXT_HWRM_REQ_MAX_SIZE 128 569 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ 570 BNXT_HWRM_REQ_MAX_SIZE) 571 #define HWRM_SHORT_MIN_TIMEOUT 3 572 #define HWRM_SHORT_MAX_TIMEOUT 10 573 #define HWRM_SHORT_TIMEOUT_COUNTER 5 574 575 #define HWRM_MIN_TIMEOUT 25 576 #define HWRM_MAX_TIMEOUT 40 577 578 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \ 579 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \ 580 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \ 581 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT)) 582 583 #define HWRM_VALID_BIT_DELAY_USEC 20 584 585 #define BNXT_RX_EVENT 1 586 #define BNXT_AGG_EVENT 2 587 #define BNXT_TX_EVENT 4 588 589 struct bnxt_sw_tx_bd { 590 struct sk_buff *skb; 591 DEFINE_DMA_UNMAP_ADDR(mapping); 592 u8 is_gso; 593 u8 is_push; 594 union { 595 unsigned short nr_frags; 596 u16 rx_prod; 597 }; 598 }; 599 600 struct bnxt_sw_rx_bd { 601 void *data; 602 u8 *data_ptr; 603 dma_addr_t mapping; 604 }; 605 606 struct bnxt_sw_rx_agg_bd { 607 struct page *page; 608 unsigned int offset; 609 dma_addr_t mapping; 610 }; 611 612 struct bnxt_ring_mem_info { 613 int nr_pages; 614 int page_size; 615 u32 flags; 616 #define BNXT_RMEM_VALID_PTE_FLAG 1 617 #define BNXT_RMEM_RING_PTE_FLAG 2 618 619 void **pg_arr; 620 dma_addr_t *dma_arr; 621 622 __le64 *pg_tbl; 623 dma_addr_t pg_tbl_map; 624 625 int vmem_size; 626 void **vmem; 627 }; 628 629 struct bnxt_ring_struct { 630 struct bnxt_ring_mem_info ring_mem; 631 632 u16 fw_ring_id; /* Ring id filled by Chimp FW */ 633 union { 634 u16 grp_idx; 635 u16 map_idx; /* Used by cmpl rings */ 636 }; 637 u8 queue_id; 638 }; 639 640 struct tx_push_bd { 641 __le32 doorbell; 642 __le32 tx_bd_len_flags_type; 643 u32 tx_bd_opaque; 644 struct tx_bd_ext txbd2; 645 }; 646 647 struct tx_push_buffer { 648 struct tx_push_bd push_bd; 649 u32 data[25]; 650 }; 651 652 struct bnxt_db_info { 653 void __iomem *doorbell; 654 union { 655 u64 db_key64; 656 u32 db_key32; 657 }; 658 }; 659 660 struct bnxt_tx_ring_info { 661 struct bnxt_napi *bnapi; 662 u16 tx_prod; 663 u16 tx_cons; 664 u16 txq_index; 665 struct bnxt_db_info tx_db; 666 667 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 668 struct bnxt_sw_tx_bd *tx_buf_ring; 669 670 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 671 672 struct tx_push_buffer *tx_push; 673 dma_addr_t tx_push_mapping; 674 __le64 data_mapping; 675 676 #define BNXT_DEV_STATE_CLOSING 0x1 677 u32 dev_state; 678 679 struct bnxt_ring_struct tx_ring_struct; 680 }; 681 682 #define BNXT_LEGACY_COAL_CMPL_PARAMS \ 683 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \ 684 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \ 685 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \ 686 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \ 687 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \ 688 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \ 689 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \ 690 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \ 691 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT) 692 693 #define BNXT_COAL_CMPL_ENABLES \ 694 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \ 695 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \ 696 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \ 697 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT) 698 699 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE \ 700 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 701 702 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \ 703 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 704 705 struct bnxt_coal_cap { 706 u32 cmpl_params; 707 u32 nq_params; 708 u16 num_cmpl_dma_aggr_max; 709 u16 num_cmpl_dma_aggr_during_int_max; 710 u16 cmpl_aggr_dma_tmr_max; 711 u16 cmpl_aggr_dma_tmr_during_int_max; 712 u16 int_lat_tmr_min_max; 713 u16 int_lat_tmr_max_max; 714 u16 num_cmpl_aggr_int_max; 715 u16 timer_units; 716 }; 717 718 struct bnxt_coal { 719 u16 coal_ticks; 720 u16 coal_ticks_irq; 721 u16 coal_bufs; 722 u16 coal_bufs_irq; 723 /* RING_IDLE enabled when coal ticks < idle_thresh */ 724 u16 idle_thresh; 725 u8 bufs_per_record; 726 u8 budget; 727 }; 728 729 struct bnxt_tpa_info { 730 void *data; 731 u8 *data_ptr; 732 dma_addr_t mapping; 733 u16 len; 734 unsigned short gso_type; 735 u32 flags2; 736 u32 metadata; 737 enum pkt_hash_types hash_type; 738 u32 rss_hash; 739 u32 hdr_info; 740 741 #define BNXT_TPA_L4_SIZE(hdr_info) \ 742 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) 743 744 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ 745 (((hdr_info) >> 18) & 0x1ff) 746 747 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ 748 (((hdr_info) >> 9) & 0x1ff) 749 750 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ 751 ((hdr_info) & 0x1ff) 752 753 u16 cfa_code; /* cfa_code in TPA start compl */ 754 }; 755 756 struct bnxt_rx_ring_info { 757 struct bnxt_napi *bnapi; 758 u16 rx_prod; 759 u16 rx_agg_prod; 760 u16 rx_sw_agg_prod; 761 u16 rx_next_cons; 762 struct bnxt_db_info rx_db; 763 struct bnxt_db_info rx_agg_db; 764 765 struct bpf_prog *xdp_prog; 766 767 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 768 struct bnxt_sw_rx_bd *rx_buf_ring; 769 770 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 771 struct bnxt_sw_rx_agg_bd *rx_agg_ring; 772 773 unsigned long *rx_agg_bmap; 774 u16 rx_agg_bmap_size; 775 776 struct page *rx_page; 777 unsigned int rx_page_offset; 778 779 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 780 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 781 782 struct bnxt_tpa_info *rx_tpa; 783 784 struct bnxt_ring_struct rx_ring_struct; 785 struct bnxt_ring_struct rx_agg_ring_struct; 786 struct xdp_rxq_info xdp_rxq; 787 }; 788 789 struct bnxt_cp_ring_info { 790 struct bnxt_napi *bnapi; 791 u32 cp_raw_cons; 792 struct bnxt_db_info cp_db; 793 794 struct bnxt_coal rx_ring_coal; 795 u64 rx_packets; 796 u64 rx_bytes; 797 u64 event_ctr; 798 799 struct net_dim dim; 800 801 union { 802 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; 803 struct nqe_cn *nq_desc_ring[MAX_CP_PAGES]; 804 }; 805 806 dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; 807 808 struct ctx_hw_stats *hw_stats; 809 dma_addr_t hw_stats_map; 810 u32 hw_stats_ctx_id; 811 u64 rx_l4_csum_errors; 812 813 struct bnxt_ring_struct cp_ring_struct; 814 815 struct bnxt_cp_ring_info *cp_ring_arr[2]; 816 #define BNXT_RX_HDL 0 817 #define BNXT_TX_HDL 1 818 }; 819 820 struct bnxt_napi { 821 struct napi_struct napi; 822 struct bnxt *bp; 823 824 int index; 825 struct bnxt_cp_ring_info cp_ring; 826 struct bnxt_rx_ring_info *rx_ring; 827 struct bnxt_tx_ring_info *tx_ring; 828 829 void (*tx_int)(struct bnxt *, struct bnxt_napi *, 830 int); 831 u32 flags; 832 #define BNXT_NAPI_FLAG_XDP 0x1 833 834 bool in_reset; 835 }; 836 837 struct bnxt_irq { 838 irq_handler_t handler; 839 unsigned int vector; 840 u8 requested:1; 841 u8 have_cpumask:1; 842 char name[IFNAMSIZ + 2]; 843 cpumask_var_t cpu_mask; 844 }; 845 846 #define HWRM_RING_ALLOC_TX 0x1 847 #define HWRM_RING_ALLOC_RX 0x2 848 #define HWRM_RING_ALLOC_AGG 0x4 849 #define HWRM_RING_ALLOC_CMPL 0x8 850 #define HWRM_RING_ALLOC_NQ 0x10 851 852 #define INVALID_STATS_CTX_ID -1 853 854 struct bnxt_ring_grp_info { 855 u16 fw_stats_ctx; 856 u16 fw_grp_id; 857 u16 rx_fw_ring_id; 858 u16 agg_fw_ring_id; 859 u16 cp_fw_ring_id; 860 }; 861 862 struct bnxt_vnic_info { 863 u16 fw_vnic_id; /* returned by Chimp during alloc */ 864 #define BNXT_MAX_CTX_PER_VNIC 2 865 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 866 u16 fw_l2_ctx_id; 867 #define BNXT_MAX_UC_ADDRS 4 868 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; 869 /* index 0 always dev_addr */ 870 u16 uc_filter_count; 871 u8 *uc_list; 872 873 u16 *fw_grp_ids; 874 dma_addr_t rss_table_dma_addr; 875 __le16 *rss_table; 876 dma_addr_t rss_hash_key_dma_addr; 877 u64 *rss_hash_key; 878 u32 rx_mask; 879 880 u8 *mc_list; 881 int mc_list_size; 882 int mc_list_count; 883 dma_addr_t mc_list_mapping; 884 #define BNXT_MAX_MC_ADDRS 16 885 886 u32 flags; 887 #define BNXT_VNIC_RSS_FLAG 1 888 #define BNXT_VNIC_RFS_FLAG 2 889 #define BNXT_VNIC_MCAST_FLAG 4 890 #define BNXT_VNIC_UCAST_FLAG 8 891 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 892 }; 893 894 struct bnxt_hw_resc { 895 u16 min_rsscos_ctxs; 896 u16 max_rsscos_ctxs; 897 u16 min_cp_rings; 898 u16 max_cp_rings; 899 u16 resv_cp_rings; 900 u16 min_tx_rings; 901 u16 max_tx_rings; 902 u16 resv_tx_rings; 903 u16 max_tx_sch_inputs; 904 u16 min_rx_rings; 905 u16 max_rx_rings; 906 u16 resv_rx_rings; 907 u16 min_hw_ring_grps; 908 u16 max_hw_ring_grps; 909 u16 resv_hw_ring_grps; 910 u16 min_l2_ctxs; 911 u16 max_l2_ctxs; 912 u16 min_vnics; 913 u16 max_vnics; 914 u16 resv_vnics; 915 u16 min_stat_ctxs; 916 u16 max_stat_ctxs; 917 u16 max_irqs; 918 }; 919 920 #if defined(CONFIG_BNXT_SRIOV) 921 struct bnxt_vf_info { 922 u16 fw_fid; 923 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ 924 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only 925 * stored by PF. 926 */ 927 u16 vlan; 928 u32 flags; 929 #define BNXT_VF_QOS 0x1 930 #define BNXT_VF_SPOOFCHK 0x2 931 #define BNXT_VF_LINK_FORCED 0x4 932 #define BNXT_VF_LINK_UP 0x8 933 #define BNXT_VF_TRUST 0x10 934 u32 func_flags; /* func cfg flags */ 935 u32 min_tx_rate; 936 u32 max_tx_rate; 937 void *hwrm_cmd_req_addr; 938 dma_addr_t hwrm_cmd_req_dma_addr; 939 }; 940 #endif 941 942 struct bnxt_pf_info { 943 #define BNXT_FIRST_PF_FID 1 944 #define BNXT_FIRST_VF_FID 128 945 u16 fw_fid; 946 u16 port_id; 947 u8 mac_addr[ETH_ALEN]; 948 u32 first_vf_id; 949 u16 active_vfs; 950 u16 max_vfs; 951 u32 max_encap_records; 952 u32 max_decap_records; 953 u32 max_tx_em_flows; 954 u32 max_tx_wm_flows; 955 u32 max_rx_em_flows; 956 u32 max_rx_wm_flows; 957 unsigned long *vf_event_bmap; 958 u16 hwrm_cmd_req_pages; 959 u8 vf_resv_strategy; 960 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 961 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 962 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2 963 void *hwrm_cmd_req_addr[4]; 964 dma_addr_t hwrm_cmd_req_dma_addr[4]; 965 struct bnxt_vf_info *vf; 966 }; 967 968 struct bnxt_ntuple_filter { 969 struct hlist_node hash; 970 u8 dst_mac_addr[ETH_ALEN]; 971 u8 src_mac_addr[ETH_ALEN]; 972 struct flow_keys fkeys; 973 __le64 filter_id; 974 u16 sw_id; 975 u8 l2_fltr_idx; 976 u16 rxq; 977 u32 flow_id; 978 unsigned long state; 979 #define BNXT_FLTR_VALID 0 980 #define BNXT_FLTR_UPDATE 1 981 }; 982 983 struct bnxt_link_info { 984 u8 phy_type; 985 u8 media_type; 986 u8 transceiver; 987 u8 phy_addr; 988 u8 phy_link_status; 989 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK 990 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL 991 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 992 u8 wire_speed; 993 u8 loop_back; 994 u8 link_up; 995 u8 duplex; 996 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 997 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 998 u8 pause; 999 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 1000 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 1001 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 1002 PORT_PHY_QCFG_RESP_PAUSE_TX) 1003 u8 lp_pause; 1004 u8 auto_pause_setting; 1005 u8 force_pause_setting; 1006 u8 duplex_setting; 1007 u8 auto_mode; 1008 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ 1009 (mode) <= BNXT_LINK_AUTO_MSK) 1010 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 1011 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 1012 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 1013 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 1014 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 1015 #define PHY_VER_LEN 3 1016 u8 phy_ver[PHY_VER_LEN]; 1017 u16 link_speed; 1018 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 1019 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 1020 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 1021 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 1022 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 1023 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 1024 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 1025 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 1026 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 1027 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 1028 u16 support_speeds; 1029 u16 auto_link_speeds; /* fw adv setting */ 1030 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 1031 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 1032 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 1033 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 1034 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 1035 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 1036 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 1037 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 1038 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 1039 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 1040 u16 support_auto_speeds; 1041 u16 lp_auto_link_speeds; 1042 u16 force_link_speed; 1043 u32 preemphasis; 1044 u8 module_status; 1045 u16 fec_cfg; 1046 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 1047 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 1048 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 1049 1050 /* copy of requested setting from ethtool cmd */ 1051 u8 autoneg; 1052 #define BNXT_AUTONEG_SPEED 1 1053 #define BNXT_AUTONEG_FLOW_CTRL 2 1054 u8 req_duplex; 1055 u8 req_flow_ctrl; 1056 u16 req_link_speed; 1057 u16 advertising; /* user adv setting */ 1058 bool force_link_chng; 1059 1060 bool phy_retry; 1061 unsigned long phy_retry_expires; 1062 1063 /* a copy of phy_qcfg output used to report link 1064 * info to VF 1065 */ 1066 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 1067 }; 1068 1069 #define BNXT_MAX_QUEUE 8 1070 1071 struct bnxt_queue_info { 1072 u8 queue_id; 1073 u8 queue_profile; 1074 }; 1075 1076 #define BNXT_MAX_LED 4 1077 1078 struct bnxt_led_info { 1079 u8 led_id; 1080 u8 led_type; 1081 u8 led_group_id; 1082 u8 unused; 1083 __le16 led_state_caps; 1084 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 1085 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) 1086 1087 __le16 led_color_caps; 1088 }; 1089 1090 #define BNXT_MAX_TEST 8 1091 1092 struct bnxt_test_info { 1093 u8 offline_mask; 1094 u8 flags; 1095 #define BNXT_TEST_FL_EXT_LPBK 0x1 1096 u16 timeout; 1097 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; 1098 }; 1099 1100 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 1101 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1102 #define BNXT_CAG_REG_BASE 0x300000 1103 1104 struct bnxt_tc_flow_stats { 1105 u64 packets; 1106 u64 bytes; 1107 }; 1108 1109 struct bnxt_tc_info { 1110 bool enabled; 1111 1112 /* hash table to store TC offloaded flows */ 1113 struct rhashtable flow_table; 1114 struct rhashtable_params flow_ht_params; 1115 1116 /* hash table to store L2 keys of TC flows */ 1117 struct rhashtable l2_table; 1118 struct rhashtable_params l2_ht_params; 1119 /* hash table to store L2 keys for TC tunnel decap */ 1120 struct rhashtable decap_l2_table; 1121 struct rhashtable_params decap_l2_ht_params; 1122 /* hash table to store tunnel decap entries */ 1123 struct rhashtable decap_table; 1124 struct rhashtable_params decap_ht_params; 1125 /* hash table to store tunnel encap entries */ 1126 struct rhashtable encap_table; 1127 struct rhashtable_params encap_ht_params; 1128 1129 /* lock to atomically add/del an l2 node when a flow is 1130 * added or deleted. 1131 */ 1132 struct mutex lock; 1133 1134 /* Fields used for batching stats query */ 1135 struct rhashtable_iter iter; 1136 #define BNXT_FLOW_STATS_BATCH_MAX 10 1137 struct bnxt_tc_stats_batch { 1138 void *flow_node; 1139 struct bnxt_tc_flow_stats hw_stats; 1140 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; 1141 1142 /* Stat counter mask (width) */ 1143 u64 bytes_mask; 1144 u64 packets_mask; 1145 }; 1146 1147 struct bnxt_vf_rep_stats { 1148 u64 packets; 1149 u64 bytes; 1150 u64 dropped; 1151 }; 1152 1153 struct bnxt_vf_rep { 1154 struct bnxt *bp; 1155 struct net_device *dev; 1156 struct metadata_dst *dst; 1157 u16 vf_idx; 1158 u16 tx_cfa_action; 1159 u16 rx_cfa_code; 1160 1161 struct bnxt_vf_rep_stats rx_stats; 1162 struct bnxt_vf_rep_stats tx_stats; 1163 }; 1164 1165 #define PTU_PTE_VALID 0x1UL 1166 #define PTU_PTE_LAST 0x2UL 1167 #define PTU_PTE_NEXT_TO_LAST 0x4UL 1168 1169 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 1170 1171 struct bnxt_ctx_pg_info { 1172 u32 entries; 1173 void *ctx_pg_arr[MAX_CTX_PAGES]; 1174 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES]; 1175 struct bnxt_ring_mem_info ring_mem; 1176 }; 1177 1178 struct bnxt_ctx_mem_info { 1179 u32 qp_max_entries; 1180 u16 qp_min_qp1_entries; 1181 u16 qp_max_l2_entries; 1182 u16 qp_entry_size; 1183 u16 srq_max_l2_entries; 1184 u32 srq_max_entries; 1185 u16 srq_entry_size; 1186 u16 cq_max_l2_entries; 1187 u32 cq_max_entries; 1188 u16 cq_entry_size; 1189 u16 vnic_max_vnic_entries; 1190 u16 vnic_max_ring_table_entries; 1191 u16 vnic_entry_size; 1192 u32 stat_max_entries; 1193 u16 stat_entry_size; 1194 u16 tqm_entry_size; 1195 u32 tqm_min_entries_per_ring; 1196 u32 tqm_max_entries_per_ring; 1197 u32 mrav_max_entries; 1198 u16 mrav_entry_size; 1199 u16 tim_entry_size; 1200 u32 tim_max_entries; 1201 u8 tqm_entries_multiple; 1202 1203 u32 flags; 1204 #define BNXT_CTX_FLAG_INITED 0x01 1205 1206 struct bnxt_ctx_pg_info qp_mem; 1207 struct bnxt_ctx_pg_info srq_mem; 1208 struct bnxt_ctx_pg_info cq_mem; 1209 struct bnxt_ctx_pg_info vnic_mem; 1210 struct bnxt_ctx_pg_info stat_mem; 1211 struct bnxt_ctx_pg_info *tqm_mem[9]; 1212 }; 1213 1214 struct bnxt { 1215 void __iomem *bar0; 1216 void __iomem *bar1; 1217 void __iomem *bar2; 1218 1219 u32 reg_base; 1220 u16 chip_num; 1221 #define CHIP_NUM_57301 0x16c8 1222 #define CHIP_NUM_57302 0x16c9 1223 #define CHIP_NUM_57304 0x16ca 1224 #define CHIP_NUM_58700 0x16cd 1225 #define CHIP_NUM_57402 0x16d0 1226 #define CHIP_NUM_57404 0x16d1 1227 #define CHIP_NUM_57406 0x16d2 1228 #define CHIP_NUM_57407 0x16d5 1229 1230 #define CHIP_NUM_57311 0x16ce 1231 #define CHIP_NUM_57312 0x16cf 1232 #define CHIP_NUM_57314 0x16df 1233 #define CHIP_NUM_57317 0x16e0 1234 #define CHIP_NUM_57412 0x16d6 1235 #define CHIP_NUM_57414 0x16d7 1236 #define CHIP_NUM_57416 0x16d8 1237 #define CHIP_NUM_57417 0x16d9 1238 #define CHIP_NUM_57412L 0x16da 1239 #define CHIP_NUM_57414L 0x16db 1240 1241 #define CHIP_NUM_5745X 0xd730 1242 1243 #define CHIP_NUM_57500 0x1750 1244 1245 #define CHIP_NUM_58802 0xd802 1246 #define CHIP_NUM_58804 0xd804 1247 #define CHIP_NUM_58808 0xd808 1248 1249 #define BNXT_CHIP_NUM_5730X(chip_num) \ 1250 ((chip_num) >= CHIP_NUM_57301 && \ 1251 (chip_num) <= CHIP_NUM_57304) 1252 1253 #define BNXT_CHIP_NUM_5740X(chip_num) \ 1254 (((chip_num) >= CHIP_NUM_57402 && \ 1255 (chip_num) <= CHIP_NUM_57406) || \ 1256 (chip_num) == CHIP_NUM_57407) 1257 1258 #define BNXT_CHIP_NUM_5731X(chip_num) \ 1259 ((chip_num) == CHIP_NUM_57311 || \ 1260 (chip_num) == CHIP_NUM_57312 || \ 1261 (chip_num) == CHIP_NUM_57314 || \ 1262 (chip_num) == CHIP_NUM_57317) 1263 1264 #define BNXT_CHIP_NUM_5741X(chip_num) \ 1265 ((chip_num) >= CHIP_NUM_57412 && \ 1266 (chip_num) <= CHIP_NUM_57414L) 1267 1268 #define BNXT_CHIP_NUM_58700(chip_num) \ 1269 ((chip_num) == CHIP_NUM_58700) 1270 1271 #define BNXT_CHIP_NUM_5745X(chip_num) \ 1272 ((chip_num) == CHIP_NUM_5745X) 1273 1274 #define BNXT_CHIP_NUM_57X0X(chip_num) \ 1275 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) 1276 1277 #define BNXT_CHIP_NUM_57X1X(chip_num) \ 1278 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) 1279 1280 #define BNXT_CHIP_NUM_588XX(chip_num) \ 1281 ((chip_num) == CHIP_NUM_58802 || \ 1282 (chip_num) == CHIP_NUM_58804 || \ 1283 (chip_num) == CHIP_NUM_58808) 1284 1285 struct net_device *dev; 1286 struct pci_dev *pdev; 1287 1288 atomic_t intr_sem; 1289 1290 u32 flags; 1291 #define BNXT_FLAG_CHIP_P5 0x1 1292 #define BNXT_FLAG_VF 0x2 1293 #define BNXT_FLAG_LRO 0x4 1294 #ifdef CONFIG_INET 1295 #define BNXT_FLAG_GRO 0x8 1296 #else 1297 /* Cannot support hardware GRO if CONFIG_INET is not set */ 1298 #define BNXT_FLAG_GRO 0x0 1299 #endif 1300 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) 1301 #define BNXT_FLAG_JUMBO 0x10 1302 #define BNXT_FLAG_STRIP_VLAN 0x20 1303 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ 1304 BNXT_FLAG_LRO) 1305 #define BNXT_FLAG_USING_MSIX 0x40 1306 #define BNXT_FLAG_MSIX_CAP 0x80 1307 #define BNXT_FLAG_RFS 0x100 1308 #define BNXT_FLAG_SHARED_RINGS 0x200 1309 #define BNXT_FLAG_PORT_STATS 0x400 1310 #define BNXT_FLAG_UDP_RSS_CAP 0x800 1311 #define BNXT_FLAG_EEE_CAP 0x1000 1312 #define BNXT_FLAG_NEW_RSS_CAP 0x2000 1313 #define BNXT_FLAG_WOL_CAP 0x4000 1314 #define BNXT_FLAG_ROCEV1_CAP 0x8000 1315 #define BNXT_FLAG_ROCEV2_CAP 0x10000 1316 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ 1317 BNXT_FLAG_ROCEV2_CAP) 1318 #define BNXT_FLAG_NO_AGG_RINGS 0x20000 1319 #define BNXT_FLAG_RX_PAGE_MODE 0x40000 1320 #define BNXT_FLAG_MULTI_HOST 0x100000 1321 #define BNXT_FLAG_DOUBLE_DB 0x400000 1322 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 1323 #define BNXT_FLAG_DIM 0x2000000 1324 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 1325 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 1326 1327 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 1328 BNXT_FLAG_RFS | \ 1329 BNXT_FLAG_STRIP_VLAN) 1330 1331 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 1332 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 1333 #define BNXT_NPAR(bp) ((bp)->port_partition_type) 1334 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 1335 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 1336 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) 1337 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) 1338 #define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \ 1339 !(bp->flags & BNXT_FLAG_CHIP_P5)) 1340 1341 /* Chip class phase 5 */ 1342 #define BNXT_CHIP_P5(bp) \ 1343 ((bp)->chip_num == CHIP_NUM_57500) 1344 1345 /* Chip class phase 4.x */ 1346 #define BNXT_CHIP_P4(bp) \ 1347 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ 1348 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ 1349 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ 1350 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ 1351 !BNXT_CHIP_TYPE_NITRO_A0(bp))) 1352 1353 #define BNXT_CHIP_P4_PLUS(bp) \ 1354 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp)) 1355 1356 struct bnxt_en_dev *edev; 1357 struct bnxt_en_dev * (*ulp_probe)(struct net_device *); 1358 1359 struct bnxt_napi **bnapi; 1360 1361 struct bnxt_rx_ring_info *rx_ring; 1362 struct bnxt_tx_ring_info *tx_ring; 1363 u16 *tx_ring_map; 1364 1365 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, 1366 struct sk_buff *); 1367 1368 struct sk_buff * (*rx_skb_func)(struct bnxt *, 1369 struct bnxt_rx_ring_info *, 1370 u16, void *, u8 *, dma_addr_t, 1371 unsigned int); 1372 1373 u32 rx_buf_size; 1374 u32 rx_buf_use_size; /* useable size */ 1375 u16 rx_offset; 1376 u16 rx_dma_offset; 1377 enum dma_data_direction rx_dir; 1378 u32 rx_ring_size; 1379 u32 rx_agg_ring_size; 1380 u32 rx_copy_thresh; 1381 u32 rx_ring_mask; 1382 u32 rx_agg_ring_mask; 1383 int rx_nr_pages; 1384 int rx_agg_nr_pages; 1385 int rx_nr_rings; 1386 int rsscos_nr_ctxs; 1387 1388 u32 tx_ring_size; 1389 u32 tx_ring_mask; 1390 int tx_nr_pages; 1391 int tx_nr_rings; 1392 int tx_nr_rings_per_tc; 1393 int tx_nr_rings_xdp; 1394 1395 int tx_wake_thresh; 1396 int tx_push_thresh; 1397 int tx_push_size; 1398 1399 u32 cp_ring_size; 1400 u32 cp_ring_mask; 1401 u32 cp_bit; 1402 int cp_nr_pages; 1403 int cp_nr_rings; 1404 1405 int num_stat_ctxs; 1406 1407 /* grp_info indexed by completion ring index */ 1408 struct bnxt_ring_grp_info *grp_info; 1409 struct bnxt_vnic_info *vnic_info; 1410 int nr_vnics; 1411 u32 rss_hash_cfg; 1412 1413 u16 max_mtu; 1414 u8 max_tc; 1415 u8 max_lltc; /* lossless TCs */ 1416 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; 1417 u8 tc_to_qidx[BNXT_MAX_QUEUE]; 1418 u8 q_ids[BNXT_MAX_QUEUE]; 1419 u8 max_q; 1420 1421 unsigned int current_interval; 1422 #define BNXT_TIMER_INTERVAL HZ 1423 1424 struct timer_list timer; 1425 1426 unsigned long state; 1427 #define BNXT_STATE_OPEN 0 1428 #define BNXT_STATE_IN_SP_TASK 1 1429 #define BNXT_STATE_READ_STATS 2 1430 1431 struct bnxt_irq *irq_tbl; 1432 int total_irqs; 1433 u8 mac_addr[ETH_ALEN]; 1434 1435 #ifdef CONFIG_BNXT_DCB 1436 struct ieee_pfc *ieee_pfc; 1437 struct ieee_ets *ieee_ets; 1438 u8 dcbx_cap; 1439 u8 default_pri; 1440 u8 max_dscp_value; 1441 #endif /* CONFIG_BNXT_DCB */ 1442 1443 u32 msg_enable; 1444 1445 u32 fw_cap; 1446 #define BNXT_FW_CAP_SHORT_CMD 0x00000001 1447 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002 1448 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004 1449 #define BNXT_FW_CAP_NEW_RM 0x00000008 1450 #define BNXT_FW_CAP_IF_CHANGE 0x00000010 1451 1452 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM) 1453 u32 hwrm_spec_code; 1454 u16 hwrm_cmd_seq; 1455 u32 hwrm_intr_seq_id; 1456 void *hwrm_short_cmd_req_addr; 1457 dma_addr_t hwrm_short_cmd_req_dma_addr; 1458 void *hwrm_cmd_resp_addr; 1459 dma_addr_t hwrm_cmd_resp_dma_addr; 1460 1461 struct rx_port_stats *hw_rx_port_stats; 1462 struct tx_port_stats *hw_tx_port_stats; 1463 struct rx_port_stats_ext *hw_rx_port_stats_ext; 1464 struct rx_port_stats_ext *hw_tx_port_stats_ext; 1465 dma_addr_t hw_rx_port_stats_map; 1466 dma_addr_t hw_tx_port_stats_map; 1467 dma_addr_t hw_rx_port_stats_ext_map; 1468 dma_addr_t hw_tx_port_stats_ext_map; 1469 int hw_port_stats_size; 1470 u16 fw_rx_stats_ext_size; 1471 u16 fw_tx_stats_ext_size; 1472 1473 u16 hwrm_max_req_len; 1474 u16 hwrm_max_ext_req_len; 1475 int hwrm_cmd_timeout; 1476 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 1477 struct hwrm_ver_get_output ver_resp; 1478 #define FW_VER_STR_LEN 32 1479 #define BC_HWRM_STR_LEN 21 1480 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) 1481 char fw_ver_str[FW_VER_STR_LEN]; 1482 __be16 vxlan_port; 1483 u8 vxlan_port_cnt; 1484 __le16 vxlan_fw_dst_port_id; 1485 __be16 nge_port; 1486 u8 nge_port_cnt; 1487 __le16 nge_fw_dst_port_id; 1488 u8 port_partition_type; 1489 u8 port_count; 1490 u16 br_mode; 1491 1492 struct bnxt_coal_cap coal_cap; 1493 struct bnxt_coal rx_coal; 1494 struct bnxt_coal tx_coal; 1495 1496 u32 stats_coal_ticks; 1497 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1498 #define BNXT_MIN_STATS_COAL_TICKS 250000 1499 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1500 1501 struct work_struct sp_task; 1502 unsigned long sp_event; 1503 #define BNXT_RX_MASK_SP_EVENT 0 1504 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1505 #define BNXT_LINK_CHNG_SP_EVENT 2 1506 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1507 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1508 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1509 #define BNXT_RESET_TASK_SP_EVENT 6 1510 #define BNXT_RST_RING_SP_EVENT 7 1511 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1512 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1513 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1514 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1515 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1516 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1517 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1518 #define BNXT_FLOW_STATS_SP_EVENT 15 1519 #define BNXT_UPDATE_PHY_SP_EVENT 16 1520 1521 struct bnxt_hw_resc hw_resc; 1522 struct bnxt_pf_info pf; 1523 struct bnxt_ctx_mem_info *ctx; 1524 #ifdef CONFIG_BNXT_SRIOV 1525 int nr_vfs; 1526 struct bnxt_vf_info vf; 1527 wait_queue_head_t sriov_cfg_wait; 1528 bool sriov_cfg; 1529 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) 1530 1531 /* lock to protect VF-rep creation/cleanup via 1532 * multiple paths such as ->sriov_configure() and 1533 * devlink ->eswitch_mode_set() 1534 */ 1535 struct mutex sriov_lock; 1536 #endif 1537 1538 #if BITS_PER_LONG == 32 1539 /* ensure atomic 64-bit doorbell writes on 32-bit systems. */ 1540 spinlock_t db_lock; 1541 #endif 1542 1543 #define BNXT_NTP_FLTR_MAX_FLTR 4096 1544 #define BNXT_NTP_FLTR_HASH_SIZE 512 1545 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) 1546 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; 1547 spinlock_t ntp_fltr_lock; /* for hash table add, del */ 1548 1549 unsigned long *ntp_fltr_bmap; 1550 int ntp_fltr_count; 1551 1552 /* To protect link related settings during link changes and 1553 * ethtool settings changes. 1554 */ 1555 struct mutex link_lock; 1556 struct bnxt_link_info link_info; 1557 struct ethtool_eee eee; 1558 u32 lpi_tmr_lo; 1559 u32 lpi_tmr_hi; 1560 1561 u8 num_tests; 1562 struct bnxt_test_info *test_info; 1563 1564 u8 wol_filter_id; 1565 u8 wol; 1566 1567 u8 num_leds; 1568 struct bnxt_led_info leds[BNXT_MAX_LED]; 1569 1570 struct bpf_prog *xdp_prog; 1571 1572 /* devlink interface and vf-rep structs */ 1573 struct devlink *dl; 1574 enum devlink_eswitch_mode eswitch_mode; 1575 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ 1576 u16 *cfa_code_map; /* cfa_code -> vf_idx map */ 1577 u8 switch_id[8]; 1578 struct bnxt_tc_info *tc_info; 1579 struct dentry *debugfs_pdev; 1580 struct dentry *debugfs_dim; 1581 struct device *hwmon_dev; 1582 }; 1583 1584 #define BNXT_RX_STATS_OFFSET(counter) \ 1585 (offsetof(struct rx_port_stats, counter) / 8) 1586 1587 #define BNXT_TX_STATS_OFFSET(counter) \ 1588 ((offsetof(struct tx_port_stats, counter) + \ 1589 sizeof(struct rx_port_stats) + 512) / 8) 1590 1591 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 1592 (offsetof(struct rx_port_stats_ext, counter) / 8) 1593 1594 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 1595 (offsetof(struct tx_port_stats_ext, counter) / 8) 1596 1597 #define I2C_DEV_ADDR_A0 0xa0 1598 #define I2C_DEV_ADDR_A2 0xa2 1599 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 1600 #define SFF_MODULE_ID_SFP 0x3 1601 #define SFF_MODULE_ID_QSFP 0xc 1602 #define SFF_MODULE_ID_QSFP_PLUS 0xd 1603 #define SFF_MODULE_ID_QSFP28 0x11 1604 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1605 1606 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 1607 { 1608 /* Tell compiler to fetch tx indices from memory. */ 1609 barrier(); 1610 1611 return bp->tx_ring_size - 1612 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 1613 } 1614 1615 #if BITS_PER_LONG == 32 1616 #define writeq(val64, db) \ 1617 do { \ 1618 spin_lock(&bp->db_lock); \ 1619 writel((val64) & 0xffffffff, db); \ 1620 writel((val64) >> 32, (db) + 4); \ 1621 spin_unlock(&bp->db_lock); \ 1622 } while (0) 1623 1624 #define writeq_relaxed writeq 1625 #endif 1626 1627 /* For TX and RX ring doorbells with no ordering guarantee*/ 1628 static inline void bnxt_db_write_relaxed(struct bnxt *bp, 1629 struct bnxt_db_info *db, u32 idx) 1630 { 1631 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1632 writeq_relaxed(db->db_key64 | idx, db->doorbell); 1633 } else { 1634 u32 db_val = db->db_key32 | idx; 1635 1636 writel_relaxed(db_val, db->doorbell); 1637 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1638 writel_relaxed(db_val, db->doorbell); 1639 } 1640 } 1641 1642 /* For TX and RX ring doorbells */ 1643 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db, 1644 u32 idx) 1645 { 1646 if (bp->flags & BNXT_FLAG_CHIP_P5) { 1647 writeq(db->db_key64 | idx, db->doorbell); 1648 } else { 1649 u32 db_val = db->db_key32 | idx; 1650 1651 writel(db_val, db->doorbell); 1652 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1653 writel(db_val, db->doorbell); 1654 } 1655 } 1656 1657 extern const u16 bnxt_lhint_arr[]; 1658 1659 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1660 u16 prod, gfp_t gfp); 1661 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); 1662 void bnxt_set_tpa_flags(struct bnxt *bp); 1663 void bnxt_set_ring_params(struct bnxt *); 1664 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); 1665 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); 1666 int _hwrm_send_message(struct bnxt *, void *, u32, int); 1667 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout); 1668 int hwrm_send_message(struct bnxt *, void *, u32, int); 1669 int hwrm_send_message_silent(struct bnxt *, void *, u32, int); 1670 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 1671 int bmap_size); 1672 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); 1673 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); 1674 int bnxt_hwrm_set_coal(struct bnxt *); 1675 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); 1676 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max); 1677 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); 1678 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp); 1679 int bnxt_get_avail_msix(struct bnxt *bp, int num); 1680 int bnxt_reserve_rings(struct bnxt *bp); 1681 void bnxt_tx_disable(struct bnxt *bp); 1682 void bnxt_tx_enable(struct bnxt *bp); 1683 int bnxt_hwrm_set_pause(struct bnxt *); 1684 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); 1685 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); 1686 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); 1687 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); 1688 int bnxt_hwrm_fw_set_time(struct bnxt *); 1689 int bnxt_open_nic(struct bnxt *, bool, bool); 1690 int bnxt_half_open_nic(struct bnxt *bp); 1691 void bnxt_half_close_nic(struct bnxt *bp); 1692 int bnxt_close_nic(struct bnxt *, bool, bool); 1693 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 1694 int tx_xdp); 1695 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); 1696 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); 1697 int bnxt_restore_pf_fw_resources(struct bnxt *bp); 1698 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr); 1699 void bnxt_dim_work(struct work_struct *work); 1700 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); 1701 1702 #endif 1703