1 /* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 */ 10 11 #ifndef BNXT_H 12 #define BNXT_H 13 14 #define DRV_MODULE_NAME "bnxt_en" 15 #define DRV_MODULE_VERSION "1.10.0" 16 17 #define DRV_VER_MAJ 1 18 #define DRV_VER_MIN 10 19 #define DRV_VER_UPD 0 20 21 #include <linux/interrupt.h> 22 #include <linux/rhashtable.h> 23 #include <net/devlink.h> 24 #include <net/dst_metadata.h> 25 #include <net/switchdev.h> 26 #include <net/xdp.h> 27 #include <linux/net_dim.h> 28 29 struct tx_bd { 30 __le32 tx_bd_len_flags_type; 31 #define TX_BD_TYPE (0x3f << 0) 32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0) 33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0) 34 #define TX_BD_FLAGS_PACKET_END (1 << 6) 35 #define TX_BD_FLAGS_NO_CMPL (1 << 7) 36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8) 37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8 38 #define TX_BD_FLAGS_LHINT (3 << 13) 39 #define TX_BD_FLAGS_LHINT_SHIFT 13 40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13) 41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13) 42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13) 43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13) 44 #define TX_BD_FLAGS_COAL_NOW (1 << 15) 45 #define TX_BD_LEN (0xffff << 16) 46 #define TX_BD_LEN_SHIFT 16 47 48 u32 tx_bd_opaque; 49 __le64 tx_bd_haddr; 50 } __packed; 51 52 struct tx_bd_ext { 53 __le32 tx_bd_hsize_lflags; 54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0) 55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1) 56 #define TX_BD_FLAGS_NO_CRC (1 << 2) 57 #define TX_BD_FLAGS_STAMP (1 << 3) 58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4) 59 #define TX_BD_FLAGS_LSO (1 << 5) 60 #define TX_BD_FLAGS_IPID_FMT (1 << 6) 61 #define TX_BD_FLAGS_T_IPID (1 << 7) 62 #define TX_BD_HSIZE (0xff << 16) 63 #define TX_BD_HSIZE_SHIFT 16 64 65 __le32 tx_bd_mss; 66 __le32 tx_bd_cfa_action; 67 #define TX_BD_CFA_ACTION (0xffff << 16) 68 #define TX_BD_CFA_ACTION_SHIFT 16 69 70 __le32 tx_bd_cfa_meta; 71 #define TX_BD_CFA_META_MASK 0xfffffff 72 #define TX_BD_CFA_META_VID_MASK 0xfff 73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12) 74 #define TX_BD_CFA_META_PRI_SHIFT 12 75 #define TX_BD_CFA_META_TPID_MASK (3 << 16) 76 #define TX_BD_CFA_META_TPID_SHIFT 16 77 #define TX_BD_CFA_META_KEY (0xf << 28) 78 #define TX_BD_CFA_META_KEY_SHIFT 28 79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28) 80 }; 81 82 struct rx_bd { 83 __le32 rx_bd_len_flags_type; 84 #define RX_BD_TYPE (0x3f << 0) 85 #define RX_BD_TYPE_RX_PACKET_BD 0x4 86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5 87 #define RX_BD_TYPE_RX_AGG_BD 0x6 88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4) 89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4) 90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4) 91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4) 92 #define RX_BD_FLAGS_SOP (1 << 6) 93 #define RX_BD_FLAGS_EOP (1 << 7) 94 #define RX_BD_FLAGS_BUFFERS (3 << 8) 95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8) 96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8) 97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8) 98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8) 99 #define RX_BD_LEN (0xffff << 16) 100 #define RX_BD_LEN_SHIFT 16 101 102 u32 rx_bd_opaque; 103 __le64 rx_bd_haddr; 104 }; 105 106 struct tx_cmp { 107 __le32 tx_cmp_flags_type; 108 #define CMP_TYPE (0x3f << 0) 109 #define CMP_TYPE_TX_L2_CMP 0 110 #define CMP_TYPE_RX_L2_CMP 17 111 #define CMP_TYPE_RX_AGG_CMP 18 112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19 113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21 114 #define CMP_TYPE_STATUS_CMP 32 115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34 116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36 117 #define CMP_TYPE_ERROR_STATUS 48 118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL 119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL 120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL 121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL 122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 123 124 #define TX_CMP_FLAGS_ERROR (1 << 6) 125 #define TX_CMP_FLAGS_PUSH (1 << 7) 126 127 u32 tx_cmp_opaque; 128 __le32 tx_cmp_errors_v; 129 #define TX_CMP_V (1 << 0) 130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1) 131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0 132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2 133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4 134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5 135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4) 136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5) 137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6) 138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7) 139 140 __le32 tx_cmp_unsed_3; 141 }; 142 143 struct rx_cmp { 144 __le32 rx_cmp_len_flags_type; 145 #define RX_CMP_CMP_TYPE (0x3f << 0) 146 #define RX_CMP_FLAGS_ERROR (1 << 6) 147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7) 148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10) 149 #define RX_CMP_FLAGS_UNUSED (1 << 11) 150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12 151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12) 152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12) 153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12) 154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12) 155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12) 156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12) 157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12) 158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12) 159 #define RX_CMP_LEN (0xffff << 16) 160 #define RX_CMP_LEN_SHIFT 16 161 162 u32 rx_cmp_opaque; 163 __le32 rx_cmp_misc_v1; 164 #define RX_CMP_V1 (1 << 0) 165 #define RX_CMP_AGG_BUFS (0x1f << 1) 166 #define RX_CMP_AGG_BUFS_SHIFT 1 167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9) 168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9 169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16) 170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16 171 172 __le32 rx_cmp_rss_hash; 173 }; 174 175 #define RX_CMP_HASH_VALID(rxcmp) \ 176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID)) 177 178 #define RSS_PROFILE_ID_MASK 0x1f 179 180 #define RX_CMP_HASH_TYPE(rxcmp) \ 181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\ 182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 183 184 struct rx_cmp_ext { 185 __le32 rx_cmp_flags2; 186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1 187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4) 191 __le32 rx_cmp_meta_data; 192 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff 193 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff 194 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000 195 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16 196 __le32 rx_cmp_cfa_code_errors_v2; 197 #define RX_CMP_V (1 << 0) 198 #define RX_CMPL_ERRORS_MASK (0x7fff << 1) 199 #define RX_CMPL_ERRORS_SFT 1 200 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1) 201 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1) 202 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1) 203 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1) 204 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1) 205 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4) 206 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5) 207 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6) 208 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7) 209 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8) 210 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9) 211 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9) 212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9) 213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9) 214 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9) 215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9) 216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9) 217 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9) 218 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12) 219 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12) 220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12) 221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12) 222 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12) 223 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12) 224 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12) 225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12) 226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12) 227 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12) 228 229 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16) 230 #define RX_CMPL_CFA_CODE_SFT 16 231 232 __le32 rx_cmp_unused3; 233 }; 234 235 #define RX_CMP_L2_ERRORS \ 236 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR) 237 238 #define RX_CMP_L4_CS_BITS \ 239 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC)) 240 241 #define RX_CMP_L4_CS_ERR_BITS \ 242 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR)) 243 244 #define RX_CMP_L4_CS_OK(rxcmp1) \ 245 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \ 246 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS)) 247 248 #define RX_CMP_ENCAP(rxcmp1) \ 249 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \ 250 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3) 251 252 #define RX_CMP_CFA_CODE(rxcmpl1) \ 253 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \ 254 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT) 255 256 struct rx_agg_cmp { 257 __le32 rx_agg_cmp_len_flags_type; 258 #define RX_AGG_CMP_TYPE (0x3f << 0) 259 #define RX_AGG_CMP_LEN (0xffff << 16) 260 #define RX_AGG_CMP_LEN_SHIFT 16 261 u32 rx_agg_cmp_opaque; 262 __le32 rx_agg_cmp_v; 263 #define RX_AGG_CMP_V (1 << 0) 264 __le32 rx_agg_cmp_unused; 265 }; 266 267 struct rx_tpa_start_cmp { 268 __le32 rx_tpa_start_cmp_len_flags_type; 269 #define RX_TPA_START_CMP_TYPE (0x3f << 0) 270 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6) 271 #define RX_TPA_START_CMP_FLAGS_SHIFT 6 272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7) 273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7 274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 277 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 278 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10) 279 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12) 280 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12 281 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 282 #define RX_TPA_START_CMP_LEN (0xffff << 16) 283 #define RX_TPA_START_CMP_LEN_SHIFT 16 284 285 u32 rx_tpa_start_cmp_opaque; 286 __le32 rx_tpa_start_cmp_misc_v1; 287 #define RX_TPA_START_CMP_V1 (0x1 << 0) 288 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9) 289 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9 290 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25) 291 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25 292 293 __le32 rx_tpa_start_cmp_rss_hash; 294 }; 295 296 #define TPA_START_HASH_VALID(rx_tpa_start) \ 297 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \ 298 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID)) 299 300 #define TPA_START_HASH_TYPE(rx_tpa_start) \ 301 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 302 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \ 303 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK) 304 305 #define TPA_START_AGG_ID(rx_tpa_start) \ 306 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \ 307 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT) 308 309 struct rx_tpa_start_cmp_ext { 310 __le32 rx_tpa_start_cmp_flags2; 311 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0) 312 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1) 313 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2) 314 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3) 315 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8) 316 317 __le32 rx_tpa_start_cmp_metadata; 318 __le32 rx_tpa_start_cmp_cfa_code_v2; 319 #define RX_TPA_START_CMP_V2 (0x1 << 0) 320 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16) 321 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16 322 __le32 rx_tpa_start_cmp_hdr_info; 323 }; 324 325 #define TPA_START_CFA_CODE(rx_tpa_start) \ 326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \ 327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT) 328 329 #define TPA_START_IS_IPV6(rx_tpa_start) \ 330 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \ 331 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE))) 332 333 struct rx_tpa_end_cmp { 334 __le32 rx_tpa_end_cmp_len_flags_type; 335 #define RX_TPA_END_CMP_TYPE (0x3f << 0) 336 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6) 337 #define RX_TPA_END_CMP_FLAGS_SHIFT 6 338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7) 339 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7 340 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7) 341 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7) 342 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7) 343 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7) 344 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10) 345 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12) 346 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12 347 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12) 348 #define RX_TPA_END_CMP_LEN (0xffff << 16) 349 #define RX_TPA_END_CMP_LEN_SHIFT 16 350 351 u32 rx_tpa_end_cmp_opaque; 352 __le32 rx_tpa_end_cmp_misc_v1; 353 #define RX_TPA_END_CMP_V1 (0x1 << 0) 354 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1) 355 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1 356 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8) 357 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8 358 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16) 359 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16 360 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25) 361 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25 362 363 __le32 rx_tpa_end_cmp_tsdelta; 364 #define RX_TPA_END_GRO_TS (0x1 << 31) 365 }; 366 367 #define TPA_END_AGG_ID(rx_tpa_end) \ 368 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 369 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT) 370 371 #define TPA_END_TPA_SEGS(rx_tpa_end) \ 372 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \ 373 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT) 374 375 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \ 376 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \ 377 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS) 378 379 #define TPA_END_GRO(rx_tpa_end) \ 380 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \ 381 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO) 382 383 #define TPA_END_GRO_TS(rx_tpa_end) \ 384 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \ 385 cpu_to_le32(RX_TPA_END_GRO_TS))) 386 387 struct rx_tpa_end_cmp_ext { 388 __le32 rx_tpa_end_cmp_dup_acks; 389 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0) 390 391 __le32 rx_tpa_end_cmp_seg_len; 392 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0) 393 394 __le32 rx_tpa_end_cmp_errors_v2; 395 #define RX_TPA_END_CMP_V2 (0x1 << 0) 396 #define RX_TPA_END_CMP_ERRORS (0x3 << 1) 397 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1 398 399 u32 rx_tpa_end_cmp_start_opaque; 400 }; 401 402 #define TPA_END_ERRORS(rx_tpa_end_ext) \ 403 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \ 404 cpu_to_le32(RX_TPA_END_CMP_ERRORS)) 405 406 #define DB_IDX_MASK 0xffffff 407 #define DB_IDX_VALID (0x1 << 26) 408 #define DB_IRQ_DIS (0x1 << 27) 409 #define DB_KEY_TX (0x0 << 28) 410 #define DB_KEY_RX (0x1 << 28) 411 #define DB_KEY_CP (0x2 << 28) 412 #define DB_KEY_ST (0x3 << 28) 413 #define DB_KEY_TX_PUSH (0x4 << 28) 414 #define DB_LONG_TX_PUSH (0x2 << 24) 415 416 #define BNXT_MIN_ROCE_CP_RINGS 2 417 #define BNXT_MIN_ROCE_STAT_CTXS 1 418 419 #define INVALID_HW_RING_ID ((u16)-1) 420 421 /* The hardware supports certain page sizes. Use the supported page sizes 422 * to allocate the rings. 423 */ 424 #if (PAGE_SHIFT < 12) 425 #define BNXT_PAGE_SHIFT 12 426 #elif (PAGE_SHIFT <= 13) 427 #define BNXT_PAGE_SHIFT PAGE_SHIFT 428 #elif (PAGE_SHIFT < 16) 429 #define BNXT_PAGE_SHIFT 13 430 #else 431 #define BNXT_PAGE_SHIFT 16 432 #endif 433 434 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 435 436 /* The RXBD length is 16-bit so we can only support page sizes < 64K */ 437 #if (PAGE_SHIFT > 15) 438 #define BNXT_RX_PAGE_SHIFT 15 439 #else 440 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT 441 #endif 442 443 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT) 444 445 #define BNXT_MAX_MTU 9500 446 #define BNXT_MAX_PAGE_MODE_MTU \ 447 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \ 448 XDP_PACKET_HEADROOM) 449 450 #define BNXT_MIN_PKT_SIZE 52 451 452 #define BNXT_DEFAULT_RX_RING_SIZE 511 453 #define BNXT_DEFAULT_TX_RING_SIZE 511 454 455 #define MAX_TPA 64 456 457 #if (BNXT_PAGE_SHIFT == 16) 458 #define MAX_RX_PAGES 1 459 #define MAX_RX_AGG_PAGES 4 460 #define MAX_TX_PAGES 1 461 #define MAX_CP_PAGES 8 462 #else 463 #define MAX_RX_PAGES 8 464 #define MAX_RX_AGG_PAGES 32 465 #define MAX_TX_PAGES 8 466 #define MAX_CP_PAGES 64 467 #endif 468 469 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd)) 470 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd)) 471 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp)) 472 473 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT) 474 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT) 475 476 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT) 477 478 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT) 479 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT) 480 481 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT) 482 483 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1) 484 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1) 485 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1) 486 487 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 488 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1)) 489 490 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 491 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1)) 492 493 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4)) 494 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1)) 495 496 #define TX_CMP_VALID(txcmp, raw_cons) \ 497 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \ 498 !((raw_cons) & bp->cp_bit)) 499 500 #define RX_CMP_VALID(rxcmp1, raw_cons) \ 501 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\ 502 !((raw_cons) & bp->cp_bit)) 503 504 #define RX_AGG_CMP_VALID(agg, raw_cons) \ 505 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \ 506 !((raw_cons) & bp->cp_bit)) 507 508 #define TX_CMP_TYPE(txcmp) \ 509 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE) 510 511 #define RX_CMP_TYPE(rxcmp) \ 512 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE) 513 514 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask) 515 516 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask) 517 518 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask) 519 520 #define ADV_RAW_CMP(idx, n) ((idx) + (n)) 521 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1) 522 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask) 523 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1)) 524 525 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) 526 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 527 #define DFLT_HWRM_CMD_TIMEOUT 500 528 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) 529 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) 530 #define HWRM_RESP_ERR_CODE_MASK 0xffff 531 #define HWRM_RESP_LEN_OFFSET 4 532 #define HWRM_RESP_LEN_MASK 0xffff0000 533 #define HWRM_RESP_LEN_SFT 16 534 #define HWRM_RESP_VALID_MASK 0xff000000 535 #define HWRM_SEQ_ID_INVALID -1 536 #define BNXT_HWRM_REQ_MAX_SIZE 128 537 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \ 538 BNXT_HWRM_REQ_MAX_SIZE) 539 #define HWRM_SHORT_MIN_TIMEOUT 3 540 #define HWRM_SHORT_MAX_TIMEOUT 10 541 #define HWRM_SHORT_TIMEOUT_COUNTER 5 542 543 #define HWRM_MIN_TIMEOUT 25 544 #define HWRM_MAX_TIMEOUT 40 545 546 #define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \ 547 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \ 548 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \ 549 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT)) 550 551 #define HWRM_VALID_BIT_DELAY_USEC 20 552 553 #define BNXT_RX_EVENT 1 554 #define BNXT_AGG_EVENT 2 555 #define BNXT_TX_EVENT 4 556 557 struct bnxt_sw_tx_bd { 558 struct sk_buff *skb; 559 DEFINE_DMA_UNMAP_ADDR(mapping); 560 u8 is_gso; 561 u8 is_push; 562 union { 563 unsigned short nr_frags; 564 u16 rx_prod; 565 }; 566 }; 567 568 struct bnxt_sw_rx_bd { 569 void *data; 570 u8 *data_ptr; 571 dma_addr_t mapping; 572 }; 573 574 struct bnxt_sw_rx_agg_bd { 575 struct page *page; 576 unsigned int offset; 577 dma_addr_t mapping; 578 }; 579 580 struct bnxt_ring_struct { 581 int nr_pages; 582 int page_size; 583 void **pg_arr; 584 dma_addr_t *dma_arr; 585 586 __le64 *pg_tbl; 587 dma_addr_t pg_tbl_map; 588 589 int vmem_size; 590 void **vmem; 591 592 u16 fw_ring_id; /* Ring id filled by Chimp FW */ 593 union { 594 u16 grp_idx; 595 u16 map_idx; /* Used by cmpl rings */ 596 }; 597 u8 queue_id; 598 }; 599 600 struct tx_push_bd { 601 __le32 doorbell; 602 __le32 tx_bd_len_flags_type; 603 u32 tx_bd_opaque; 604 struct tx_bd_ext txbd2; 605 }; 606 607 struct tx_push_buffer { 608 struct tx_push_bd push_bd; 609 u32 data[25]; 610 }; 611 612 struct bnxt_tx_ring_info { 613 struct bnxt_napi *bnapi; 614 u16 tx_prod; 615 u16 tx_cons; 616 u16 txq_index; 617 void __iomem *tx_doorbell; 618 619 struct tx_bd *tx_desc_ring[MAX_TX_PAGES]; 620 struct bnxt_sw_tx_bd *tx_buf_ring; 621 622 dma_addr_t tx_desc_mapping[MAX_TX_PAGES]; 623 624 struct tx_push_buffer *tx_push; 625 dma_addr_t tx_push_mapping; 626 __le64 data_mapping; 627 628 #define BNXT_DEV_STATE_CLOSING 0x1 629 u32 dev_state; 630 631 struct bnxt_ring_struct tx_ring_struct; 632 }; 633 634 struct bnxt_coal { 635 u16 coal_ticks; 636 u16 coal_ticks_irq; 637 u16 coal_bufs; 638 u16 coal_bufs_irq; 639 /* RING_IDLE enabled when coal ticks < idle_thresh */ 640 u16 idle_thresh; 641 u8 bufs_per_record; 642 u8 budget; 643 }; 644 645 struct bnxt_tpa_info { 646 void *data; 647 u8 *data_ptr; 648 dma_addr_t mapping; 649 u16 len; 650 unsigned short gso_type; 651 u32 flags2; 652 u32 metadata; 653 enum pkt_hash_types hash_type; 654 u32 rss_hash; 655 u32 hdr_info; 656 657 #define BNXT_TPA_L4_SIZE(hdr_info) \ 658 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32) 659 660 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \ 661 (((hdr_info) >> 18) & 0x1ff) 662 663 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \ 664 (((hdr_info) >> 9) & 0x1ff) 665 666 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \ 667 ((hdr_info) & 0x1ff) 668 669 u16 cfa_code; /* cfa_code in TPA start compl */ 670 }; 671 672 struct bnxt_rx_ring_info { 673 struct bnxt_napi *bnapi; 674 u16 rx_prod; 675 u16 rx_agg_prod; 676 u16 rx_sw_agg_prod; 677 u16 rx_next_cons; 678 void __iomem *rx_doorbell; 679 void __iomem *rx_agg_doorbell; 680 681 struct bpf_prog *xdp_prog; 682 683 struct rx_bd *rx_desc_ring[MAX_RX_PAGES]; 684 struct bnxt_sw_rx_bd *rx_buf_ring; 685 686 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES]; 687 struct bnxt_sw_rx_agg_bd *rx_agg_ring; 688 689 unsigned long *rx_agg_bmap; 690 u16 rx_agg_bmap_size; 691 692 struct page *rx_page; 693 unsigned int rx_page_offset; 694 695 dma_addr_t rx_desc_mapping[MAX_RX_PAGES]; 696 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES]; 697 698 struct bnxt_tpa_info *rx_tpa; 699 700 struct bnxt_ring_struct rx_ring_struct; 701 struct bnxt_ring_struct rx_agg_ring_struct; 702 struct xdp_rxq_info xdp_rxq; 703 }; 704 705 struct bnxt_cp_ring_info { 706 u32 cp_raw_cons; 707 void __iomem *cp_doorbell; 708 709 struct bnxt_coal rx_ring_coal; 710 u64 rx_packets; 711 u64 rx_bytes; 712 u64 event_ctr; 713 714 struct net_dim dim; 715 716 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES]; 717 718 dma_addr_t cp_desc_mapping[MAX_CP_PAGES]; 719 720 struct ctx_hw_stats *hw_stats; 721 dma_addr_t hw_stats_map; 722 u32 hw_stats_ctx_id; 723 u64 rx_l4_csum_errors; 724 725 struct bnxt_ring_struct cp_ring_struct; 726 }; 727 728 struct bnxt_napi { 729 struct napi_struct napi; 730 struct bnxt *bp; 731 732 int index; 733 struct bnxt_cp_ring_info cp_ring; 734 struct bnxt_rx_ring_info *rx_ring; 735 struct bnxt_tx_ring_info *tx_ring; 736 737 void (*tx_int)(struct bnxt *, struct bnxt_napi *, 738 int); 739 u32 flags; 740 #define BNXT_NAPI_FLAG_XDP 0x1 741 742 bool in_reset; 743 }; 744 745 struct bnxt_irq { 746 irq_handler_t handler; 747 unsigned int vector; 748 u8 requested:1; 749 u8 have_cpumask:1; 750 char name[IFNAMSIZ + 2]; 751 cpumask_var_t cpu_mask; 752 }; 753 754 #define HWRM_RING_ALLOC_TX 0x1 755 #define HWRM_RING_ALLOC_RX 0x2 756 #define HWRM_RING_ALLOC_AGG 0x4 757 #define HWRM_RING_ALLOC_CMPL 0x8 758 759 #define INVALID_STATS_CTX_ID -1 760 761 struct bnxt_ring_grp_info { 762 u16 fw_stats_ctx; 763 u16 fw_grp_id; 764 u16 rx_fw_ring_id; 765 u16 agg_fw_ring_id; 766 u16 cp_fw_ring_id; 767 }; 768 769 struct bnxt_vnic_info { 770 u16 fw_vnic_id; /* returned by Chimp during alloc */ 771 #define BNXT_MAX_CTX_PER_VNIC 2 772 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC]; 773 u16 fw_l2_ctx_id; 774 #define BNXT_MAX_UC_ADDRS 4 775 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS]; 776 /* index 0 always dev_addr */ 777 u16 uc_filter_count; 778 u8 *uc_list; 779 780 u16 *fw_grp_ids; 781 dma_addr_t rss_table_dma_addr; 782 __le16 *rss_table; 783 dma_addr_t rss_hash_key_dma_addr; 784 u64 *rss_hash_key; 785 u32 rx_mask; 786 787 u8 *mc_list; 788 int mc_list_size; 789 int mc_list_count; 790 dma_addr_t mc_list_mapping; 791 #define BNXT_MAX_MC_ADDRS 16 792 793 u32 flags; 794 #define BNXT_VNIC_RSS_FLAG 1 795 #define BNXT_VNIC_RFS_FLAG 2 796 #define BNXT_VNIC_MCAST_FLAG 4 797 #define BNXT_VNIC_UCAST_FLAG 8 798 #define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10 799 }; 800 801 struct bnxt_hw_resc { 802 u16 min_rsscos_ctxs; 803 u16 max_rsscos_ctxs; 804 u16 min_cp_rings; 805 u16 max_cp_rings; 806 u16 resv_cp_rings; 807 u16 min_tx_rings; 808 u16 max_tx_rings; 809 u16 resv_tx_rings; 810 u16 max_tx_sch_inputs; 811 u16 min_rx_rings; 812 u16 max_rx_rings; 813 u16 resv_rx_rings; 814 u16 min_hw_ring_grps; 815 u16 max_hw_ring_grps; 816 u16 resv_hw_ring_grps; 817 u16 min_l2_ctxs; 818 u16 max_l2_ctxs; 819 u16 min_vnics; 820 u16 max_vnics; 821 u16 resv_vnics; 822 u16 min_stat_ctxs; 823 u16 max_stat_ctxs; 824 u16 max_irqs; 825 }; 826 827 #if defined(CONFIG_BNXT_SRIOV) 828 struct bnxt_vf_info { 829 u16 fw_fid; 830 u8 mac_addr[ETH_ALEN]; /* PF assigned MAC Address */ 831 u8 vf_mac_addr[ETH_ALEN]; /* VF assigned MAC address, only 832 * stored by PF. 833 */ 834 u16 vlan; 835 u32 flags; 836 #define BNXT_VF_QOS 0x1 837 #define BNXT_VF_SPOOFCHK 0x2 838 #define BNXT_VF_LINK_FORCED 0x4 839 #define BNXT_VF_LINK_UP 0x8 840 #define BNXT_VF_TRUST 0x10 841 u32 func_flags; /* func cfg flags */ 842 u32 min_tx_rate; 843 u32 max_tx_rate; 844 void *hwrm_cmd_req_addr; 845 dma_addr_t hwrm_cmd_req_dma_addr; 846 }; 847 #endif 848 849 struct bnxt_pf_info { 850 #define BNXT_FIRST_PF_FID 1 851 #define BNXT_FIRST_VF_FID 128 852 u16 fw_fid; 853 u16 port_id; 854 u8 mac_addr[ETH_ALEN]; 855 u32 first_vf_id; 856 u16 active_vfs; 857 u16 max_vfs; 858 u32 max_encap_records; 859 u32 max_decap_records; 860 u32 max_tx_em_flows; 861 u32 max_tx_wm_flows; 862 u32 max_rx_em_flows; 863 u32 max_rx_wm_flows; 864 unsigned long *vf_event_bmap; 865 u16 hwrm_cmd_req_pages; 866 u8 vf_resv_strategy; 867 #define BNXT_VF_RESV_STRATEGY_MAXIMAL 0 868 #define BNXT_VF_RESV_STRATEGY_MINIMAL 1 869 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2 870 void *hwrm_cmd_req_addr[4]; 871 dma_addr_t hwrm_cmd_req_dma_addr[4]; 872 struct bnxt_vf_info *vf; 873 }; 874 875 struct bnxt_ntuple_filter { 876 struct hlist_node hash; 877 u8 dst_mac_addr[ETH_ALEN]; 878 u8 src_mac_addr[ETH_ALEN]; 879 struct flow_keys fkeys; 880 __le64 filter_id; 881 u16 sw_id; 882 u8 l2_fltr_idx; 883 u16 rxq; 884 u32 flow_id; 885 unsigned long state; 886 #define BNXT_FLTR_VALID 0 887 #define BNXT_FLTR_UPDATE 1 888 }; 889 890 struct bnxt_link_info { 891 u8 phy_type; 892 u8 media_type; 893 u8 transceiver; 894 u8 phy_addr; 895 u8 phy_link_status; 896 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK 897 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL 898 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 899 u8 wire_speed; 900 u8 loop_back; 901 u8 link_up; 902 u8 duplex; 903 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 904 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 905 u8 pause; 906 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 907 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 908 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 909 PORT_PHY_QCFG_RESP_PAUSE_TX) 910 u8 lp_pause; 911 u8 auto_pause_setting; 912 u8 force_pause_setting; 913 u8 duplex_setting; 914 u8 auto_mode; 915 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \ 916 (mode) <= BNXT_LINK_AUTO_MSK) 917 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 918 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 919 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 920 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 921 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 922 #define PHY_VER_LEN 3 923 u8 phy_ver[PHY_VER_LEN]; 924 u16 link_speed; 925 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 926 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 927 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 928 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 929 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 930 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 931 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 932 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 933 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 934 #define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 935 u16 support_speeds; 936 u16 auto_link_speeds; /* fw adv setting */ 937 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 938 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 939 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 940 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 941 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 942 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 943 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 944 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 945 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 946 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 947 u16 support_auto_speeds; 948 u16 lp_auto_link_speeds; 949 u16 force_link_speed; 950 u32 preemphasis; 951 u8 module_status; 952 u16 fec_cfg; 953 #define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 954 #define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 955 #define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 956 957 /* copy of requested setting from ethtool cmd */ 958 u8 autoneg; 959 #define BNXT_AUTONEG_SPEED 1 960 #define BNXT_AUTONEG_FLOW_CTRL 2 961 u8 req_duplex; 962 u8 req_flow_ctrl; 963 u16 req_link_speed; 964 u16 advertising; /* user adv setting */ 965 bool force_link_chng; 966 967 bool phy_retry; 968 unsigned long phy_retry_expires; 969 970 /* a copy of phy_qcfg output used to report link 971 * info to VF 972 */ 973 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 974 }; 975 976 #define BNXT_MAX_QUEUE 8 977 978 struct bnxt_queue_info { 979 u8 queue_id; 980 u8 queue_profile; 981 }; 982 983 #define BNXT_MAX_LED 4 984 985 struct bnxt_led_info { 986 u8 led_id; 987 u8 led_type; 988 u8 led_group_id; 989 u8 unused; 990 __le16 led_state_caps; 991 #define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \ 992 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED)) 993 994 __le16 led_color_caps; 995 }; 996 997 #define BNXT_MAX_TEST 8 998 999 struct bnxt_test_info { 1000 u8 offline_mask; 1001 u8 flags; 1002 #define BNXT_TEST_FL_EXT_LPBK 0x1 1003 u16 timeout; 1004 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN]; 1005 }; 1006 1007 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 1008 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1009 #define BNXT_CAG_REG_BASE 0x300000 1010 1011 struct bnxt_tc_flow_stats { 1012 u64 packets; 1013 u64 bytes; 1014 }; 1015 1016 struct bnxt_tc_info { 1017 bool enabled; 1018 1019 /* hash table to store TC offloaded flows */ 1020 struct rhashtable flow_table; 1021 struct rhashtable_params flow_ht_params; 1022 1023 /* hash table to store L2 keys of TC flows */ 1024 struct rhashtable l2_table; 1025 struct rhashtable_params l2_ht_params; 1026 /* hash table to store L2 keys for TC tunnel decap */ 1027 struct rhashtable decap_l2_table; 1028 struct rhashtable_params decap_l2_ht_params; 1029 /* hash table to store tunnel decap entries */ 1030 struct rhashtable decap_table; 1031 struct rhashtable_params decap_ht_params; 1032 /* hash table to store tunnel encap entries */ 1033 struct rhashtable encap_table; 1034 struct rhashtable_params encap_ht_params; 1035 1036 /* lock to atomically add/del an l2 node when a flow is 1037 * added or deleted. 1038 */ 1039 struct mutex lock; 1040 1041 /* Fields used for batching stats query */ 1042 struct rhashtable_iter iter; 1043 #define BNXT_FLOW_STATS_BATCH_MAX 10 1044 struct bnxt_tc_stats_batch { 1045 void *flow_node; 1046 struct bnxt_tc_flow_stats hw_stats; 1047 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX]; 1048 1049 /* Stat counter mask (width) */ 1050 u64 bytes_mask; 1051 u64 packets_mask; 1052 }; 1053 1054 struct bnxt_vf_rep_stats { 1055 u64 packets; 1056 u64 bytes; 1057 u64 dropped; 1058 }; 1059 1060 struct bnxt_vf_rep { 1061 struct bnxt *bp; 1062 struct net_device *dev; 1063 struct metadata_dst *dst; 1064 u16 vf_idx; 1065 u16 tx_cfa_action; 1066 u16 rx_cfa_code; 1067 1068 struct bnxt_vf_rep_stats rx_stats; 1069 struct bnxt_vf_rep_stats tx_stats; 1070 }; 1071 1072 struct bnxt { 1073 void __iomem *bar0; 1074 void __iomem *bar1; 1075 void __iomem *bar2; 1076 1077 u32 reg_base; 1078 u16 chip_num; 1079 #define CHIP_NUM_57301 0x16c8 1080 #define CHIP_NUM_57302 0x16c9 1081 #define CHIP_NUM_57304 0x16ca 1082 #define CHIP_NUM_58700 0x16cd 1083 #define CHIP_NUM_57402 0x16d0 1084 #define CHIP_NUM_57404 0x16d1 1085 #define CHIP_NUM_57406 0x16d2 1086 #define CHIP_NUM_57407 0x16d5 1087 1088 #define CHIP_NUM_57311 0x16ce 1089 #define CHIP_NUM_57312 0x16cf 1090 #define CHIP_NUM_57314 0x16df 1091 #define CHIP_NUM_57317 0x16e0 1092 #define CHIP_NUM_57412 0x16d6 1093 #define CHIP_NUM_57414 0x16d7 1094 #define CHIP_NUM_57416 0x16d8 1095 #define CHIP_NUM_57417 0x16d9 1096 #define CHIP_NUM_57412L 0x16da 1097 #define CHIP_NUM_57414L 0x16db 1098 1099 #define CHIP_NUM_5745X 0xd730 1100 1101 #define CHIP_NUM_58802 0xd802 1102 #define CHIP_NUM_58804 0xd804 1103 #define CHIP_NUM_58808 0xd808 1104 1105 #define BNXT_CHIP_NUM_5730X(chip_num) \ 1106 ((chip_num) >= CHIP_NUM_57301 && \ 1107 (chip_num) <= CHIP_NUM_57304) 1108 1109 #define BNXT_CHIP_NUM_5740X(chip_num) \ 1110 (((chip_num) >= CHIP_NUM_57402 && \ 1111 (chip_num) <= CHIP_NUM_57406) || \ 1112 (chip_num) == CHIP_NUM_57407) 1113 1114 #define BNXT_CHIP_NUM_5731X(chip_num) \ 1115 ((chip_num) == CHIP_NUM_57311 || \ 1116 (chip_num) == CHIP_NUM_57312 || \ 1117 (chip_num) == CHIP_NUM_57314 || \ 1118 (chip_num) == CHIP_NUM_57317) 1119 1120 #define BNXT_CHIP_NUM_5741X(chip_num) \ 1121 ((chip_num) >= CHIP_NUM_57412 && \ 1122 (chip_num) <= CHIP_NUM_57414L) 1123 1124 #define BNXT_CHIP_NUM_58700(chip_num) \ 1125 ((chip_num) == CHIP_NUM_58700) 1126 1127 #define BNXT_CHIP_NUM_5745X(chip_num) \ 1128 ((chip_num) == CHIP_NUM_5745X) 1129 1130 #define BNXT_CHIP_NUM_57X0X(chip_num) \ 1131 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num)) 1132 1133 #define BNXT_CHIP_NUM_57X1X(chip_num) \ 1134 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num)) 1135 1136 #define BNXT_CHIP_NUM_588XX(chip_num) \ 1137 ((chip_num) == CHIP_NUM_58802 || \ 1138 (chip_num) == CHIP_NUM_58804 || \ 1139 (chip_num) == CHIP_NUM_58808) 1140 1141 struct net_device *dev; 1142 struct pci_dev *pdev; 1143 1144 atomic_t intr_sem; 1145 1146 u32 flags; 1147 #define BNXT_FLAG_VF 0x2 1148 #define BNXT_FLAG_LRO 0x4 1149 #ifdef CONFIG_INET 1150 #define BNXT_FLAG_GRO 0x8 1151 #else 1152 /* Cannot support hardware GRO if CONFIG_INET is not set */ 1153 #define BNXT_FLAG_GRO 0x0 1154 #endif 1155 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO) 1156 #define BNXT_FLAG_JUMBO 0x10 1157 #define BNXT_FLAG_STRIP_VLAN 0x20 1158 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \ 1159 BNXT_FLAG_LRO) 1160 #define BNXT_FLAG_USING_MSIX 0x40 1161 #define BNXT_FLAG_MSIX_CAP 0x80 1162 #define BNXT_FLAG_RFS 0x100 1163 #define BNXT_FLAG_SHARED_RINGS 0x200 1164 #define BNXT_FLAG_PORT_STATS 0x400 1165 #define BNXT_FLAG_UDP_RSS_CAP 0x800 1166 #define BNXT_FLAG_EEE_CAP 0x1000 1167 #define BNXT_FLAG_NEW_RSS_CAP 0x2000 1168 #define BNXT_FLAG_WOL_CAP 0x4000 1169 #define BNXT_FLAG_ROCEV1_CAP 0x8000 1170 #define BNXT_FLAG_ROCEV2_CAP 0x10000 1171 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \ 1172 BNXT_FLAG_ROCEV2_CAP) 1173 #define BNXT_FLAG_NO_AGG_RINGS 0x20000 1174 #define BNXT_FLAG_RX_PAGE_MODE 0x40000 1175 #define BNXT_FLAG_MULTI_HOST 0x100000 1176 #define BNXT_FLAG_DOUBLE_DB 0x400000 1177 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000 1178 #define BNXT_FLAG_DIM 0x2000000 1179 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000 1180 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000 1181 1182 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \ 1183 BNXT_FLAG_RFS | \ 1184 BNXT_FLAG_STRIP_VLAN) 1185 1186 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF)) 1187 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF) 1188 #define BNXT_NPAR(bp) ((bp)->port_partition_type) 1189 #define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST) 1190 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp)) 1191 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0) 1192 #define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE) 1193 1194 /* Chip class phase 4 and later */ 1195 #define BNXT_CHIP_P4_PLUS(bp) \ 1196 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \ 1197 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \ 1198 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \ 1199 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \ 1200 !BNXT_CHIP_TYPE_NITRO_A0(bp))) 1201 1202 struct bnxt_en_dev *edev; 1203 struct bnxt_en_dev * (*ulp_probe)(struct net_device *); 1204 1205 struct bnxt_napi **bnapi; 1206 1207 struct bnxt_rx_ring_info *rx_ring; 1208 struct bnxt_tx_ring_info *tx_ring; 1209 u16 *tx_ring_map; 1210 1211 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int, 1212 struct sk_buff *); 1213 1214 struct sk_buff * (*rx_skb_func)(struct bnxt *, 1215 struct bnxt_rx_ring_info *, 1216 u16, void *, u8 *, dma_addr_t, 1217 unsigned int); 1218 1219 u32 rx_buf_size; 1220 u32 rx_buf_use_size; /* useable size */ 1221 u16 rx_offset; 1222 u16 rx_dma_offset; 1223 enum dma_data_direction rx_dir; 1224 u32 rx_ring_size; 1225 u32 rx_agg_ring_size; 1226 u32 rx_copy_thresh; 1227 u32 rx_ring_mask; 1228 u32 rx_agg_ring_mask; 1229 int rx_nr_pages; 1230 int rx_agg_nr_pages; 1231 int rx_nr_rings; 1232 int rsscos_nr_ctxs; 1233 1234 u32 tx_ring_size; 1235 u32 tx_ring_mask; 1236 int tx_nr_pages; 1237 int tx_nr_rings; 1238 int tx_nr_rings_per_tc; 1239 int tx_nr_rings_xdp; 1240 1241 int tx_wake_thresh; 1242 int tx_push_thresh; 1243 int tx_push_size; 1244 1245 u32 cp_ring_size; 1246 u32 cp_ring_mask; 1247 u32 cp_bit; 1248 int cp_nr_pages; 1249 int cp_nr_rings; 1250 1251 int num_stat_ctxs; 1252 1253 /* grp_info indexed by completion ring index */ 1254 struct bnxt_ring_grp_info *grp_info; 1255 struct bnxt_vnic_info *vnic_info; 1256 int nr_vnics; 1257 u32 rss_hash_cfg; 1258 1259 u16 max_mtu; 1260 u8 max_tc; 1261 u8 max_lltc; /* lossless TCs */ 1262 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE]; 1263 u8 tc_to_qidx[BNXT_MAX_QUEUE]; 1264 1265 unsigned int current_interval; 1266 #define BNXT_TIMER_INTERVAL HZ 1267 1268 struct timer_list timer; 1269 1270 unsigned long state; 1271 #define BNXT_STATE_OPEN 0 1272 #define BNXT_STATE_IN_SP_TASK 1 1273 #define BNXT_STATE_READ_STATS 2 1274 1275 struct bnxt_irq *irq_tbl; 1276 int total_irqs; 1277 u8 mac_addr[ETH_ALEN]; 1278 1279 #ifdef CONFIG_BNXT_DCB 1280 struct ieee_pfc *ieee_pfc; 1281 struct ieee_ets *ieee_ets; 1282 u8 dcbx_cap; 1283 u8 default_pri; 1284 u8 max_dscp_value; 1285 #endif /* CONFIG_BNXT_DCB */ 1286 1287 u32 msg_enable; 1288 1289 u32 fw_cap; 1290 #define BNXT_FW_CAP_SHORT_CMD 0x00000001 1291 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002 1292 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004 1293 #define BNXT_FW_CAP_NEW_RM 0x00000008 1294 #define BNXT_FW_CAP_IF_CHANGE 0x00000010 1295 1296 #define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM) 1297 u32 hwrm_spec_code; 1298 u16 hwrm_cmd_seq; 1299 u32 hwrm_intr_seq_id; 1300 void *hwrm_short_cmd_req_addr; 1301 dma_addr_t hwrm_short_cmd_req_dma_addr; 1302 void *hwrm_cmd_resp_addr; 1303 dma_addr_t hwrm_cmd_resp_dma_addr; 1304 1305 struct rx_port_stats *hw_rx_port_stats; 1306 struct tx_port_stats *hw_tx_port_stats; 1307 struct rx_port_stats_ext *hw_rx_port_stats_ext; 1308 struct rx_port_stats_ext *hw_tx_port_stats_ext; 1309 dma_addr_t hw_rx_port_stats_map; 1310 dma_addr_t hw_tx_port_stats_map; 1311 dma_addr_t hw_rx_port_stats_ext_map; 1312 dma_addr_t hw_tx_port_stats_ext_map; 1313 int hw_port_stats_size; 1314 u16 fw_rx_stats_ext_size; 1315 u16 fw_tx_stats_ext_size; 1316 1317 u16 hwrm_max_req_len; 1318 int hwrm_cmd_timeout; 1319 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */ 1320 struct hwrm_ver_get_output ver_resp; 1321 #define FW_VER_STR_LEN 32 1322 #define BC_HWRM_STR_LEN 21 1323 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN) 1324 char fw_ver_str[FW_VER_STR_LEN]; 1325 __be16 vxlan_port; 1326 u8 vxlan_port_cnt; 1327 __le16 vxlan_fw_dst_port_id; 1328 __be16 nge_port; 1329 u8 nge_port_cnt; 1330 __le16 nge_fw_dst_port_id; 1331 u8 port_partition_type; 1332 u8 port_count; 1333 u16 br_mode; 1334 1335 struct bnxt_coal rx_coal; 1336 struct bnxt_coal tx_coal; 1337 1338 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 1339 1340 u32 stats_coal_ticks; 1341 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1342 #define BNXT_MIN_STATS_COAL_TICKS 250000 1343 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1344 1345 struct work_struct sp_task; 1346 unsigned long sp_event; 1347 #define BNXT_RX_MASK_SP_EVENT 0 1348 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1349 #define BNXT_LINK_CHNG_SP_EVENT 2 1350 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1351 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1352 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1353 #define BNXT_RESET_TASK_SP_EVENT 6 1354 #define BNXT_RST_RING_SP_EVENT 7 1355 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1356 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1357 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1358 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1359 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1360 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1361 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1362 #define BNXT_FLOW_STATS_SP_EVENT 15 1363 #define BNXT_UPDATE_PHY_SP_EVENT 16 1364 1365 struct bnxt_hw_resc hw_resc; 1366 struct bnxt_pf_info pf; 1367 #ifdef CONFIG_BNXT_SRIOV 1368 int nr_vfs; 1369 struct bnxt_vf_info vf; 1370 wait_queue_head_t sriov_cfg_wait; 1371 bool sriov_cfg; 1372 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000) 1373 1374 /* lock to protect VF-rep creation/cleanup via 1375 * multiple paths such as ->sriov_configure() and 1376 * devlink ->eswitch_mode_set() 1377 */ 1378 struct mutex sriov_lock; 1379 #endif 1380 1381 #define BNXT_NTP_FLTR_MAX_FLTR 4096 1382 #define BNXT_NTP_FLTR_HASH_SIZE 512 1383 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1) 1384 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE]; 1385 spinlock_t ntp_fltr_lock; /* for hash table add, del */ 1386 1387 unsigned long *ntp_fltr_bmap; 1388 int ntp_fltr_count; 1389 1390 /* To protect link related settings during link changes and 1391 * ethtool settings changes. 1392 */ 1393 struct mutex link_lock; 1394 struct bnxt_link_info link_info; 1395 struct ethtool_eee eee; 1396 u32 lpi_tmr_lo; 1397 u32 lpi_tmr_hi; 1398 1399 u8 num_tests; 1400 struct bnxt_test_info *test_info; 1401 1402 u8 wol_filter_id; 1403 u8 wol; 1404 1405 u8 num_leds; 1406 struct bnxt_led_info leds[BNXT_MAX_LED]; 1407 1408 struct bpf_prog *xdp_prog; 1409 1410 /* devlink interface and vf-rep structs */ 1411 struct devlink *dl; 1412 enum devlink_eswitch_mode eswitch_mode; 1413 struct bnxt_vf_rep **vf_reps; /* array of vf-rep ptrs */ 1414 u16 *cfa_code_map; /* cfa_code -> vf_idx map */ 1415 u8 switch_id[8]; 1416 struct bnxt_tc_info *tc_info; 1417 struct dentry *debugfs_pdev; 1418 struct dentry *debugfs_dim; 1419 struct device *hwmon_dev; 1420 }; 1421 1422 #define BNXT_RX_STATS_OFFSET(counter) \ 1423 (offsetof(struct rx_port_stats, counter) / 8) 1424 1425 #define BNXT_TX_STATS_OFFSET(counter) \ 1426 ((offsetof(struct tx_port_stats, counter) + \ 1427 sizeof(struct rx_port_stats) + 512) / 8) 1428 1429 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 1430 (offsetof(struct rx_port_stats_ext, counter) / 8) 1431 1432 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 1433 (offsetof(struct tx_port_stats_ext, counter) / 8) 1434 1435 #define I2C_DEV_ADDR_A0 0xa0 1436 #define I2C_DEV_ADDR_A2 0xa2 1437 #define SFF_DIAG_SUPPORT_OFFSET 0x5c 1438 #define SFF_MODULE_ID_SFP 0x3 1439 #define SFF_MODULE_ID_QSFP 0xc 1440 #define SFF_MODULE_ID_QSFP_PLUS 0xd 1441 #define SFF_MODULE_ID_QSFP28 0x11 1442 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1443 1444 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) 1445 { 1446 /* Tell compiler to fetch tx indices from memory. */ 1447 barrier(); 1448 1449 return bp->tx_ring_size - 1450 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); 1451 } 1452 1453 /* For TX and RX ring doorbells with no ordering guarantee*/ 1454 static inline void bnxt_db_write_relaxed(struct bnxt *bp, void __iomem *db, 1455 u32 val) 1456 { 1457 writel_relaxed(val, db); 1458 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1459 writel_relaxed(val, db); 1460 } 1461 1462 /* For TX and RX ring doorbells */ 1463 static inline void bnxt_db_write(struct bnxt *bp, void __iomem *db, u32 val) 1464 { 1465 writel(val, db); 1466 if (bp->flags & BNXT_FLAG_DOUBLE_DB) 1467 writel(val, db); 1468 } 1469 1470 extern const u16 bnxt_lhint_arr[]; 1471 1472 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, 1473 u16 prod, gfp_t gfp); 1474 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data); 1475 void bnxt_set_tpa_flags(struct bnxt *bp); 1476 void bnxt_set_ring_params(struct bnxt *); 1477 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode); 1478 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16); 1479 int _hwrm_send_message(struct bnxt *, void *, u32, int); 1480 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout); 1481 int hwrm_send_message(struct bnxt *, void *, u32, int); 1482 int hwrm_send_message_silent(struct bnxt *, void *, u32, int); 1483 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap, 1484 int bmap_size); 1485 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id); 1486 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings); 1487 int bnxt_hwrm_set_coal(struct bnxt *); 1488 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp); 1489 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max); 1490 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp); 1491 unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp); 1492 int bnxt_get_avail_msix(struct bnxt *bp, int num); 1493 int bnxt_reserve_rings(struct bnxt *bp); 1494 void bnxt_tx_disable(struct bnxt *bp); 1495 void bnxt_tx_enable(struct bnxt *bp); 1496 int bnxt_hwrm_set_pause(struct bnxt *); 1497 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool); 1498 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp); 1499 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp); 1500 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all); 1501 int bnxt_hwrm_fw_set_time(struct bnxt *); 1502 int bnxt_open_nic(struct bnxt *, bool, bool); 1503 int bnxt_half_open_nic(struct bnxt *bp); 1504 void bnxt_half_close_nic(struct bnxt *bp); 1505 int bnxt_close_nic(struct bnxt *, bool, bool); 1506 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs, 1507 int tx_xdp); 1508 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc); 1509 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool); 1510 int bnxt_restore_pf_fw_resources(struct bnxt *bp); 1511 int bnxt_port_attr_get(struct bnxt *bp, struct switchdev_attr *attr); 1512 void bnxt_dim_work(struct work_struct *work); 1513 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi); 1514 1515 #endif 1516